A process for producing a non-particulate laundry detergent comprises the steps of providing a powdered porous carrier material, adsorbing a perfume onto the powdered porous carrier material, and depositing the powdered porous carrier material having adsorbed perfume on the non-particulate detergent product. In another aspect of the invention, a process for producing a non-particulate detergent product having a perfume loaded carrier material coating includes the step of providing a non-particulate detergent composition having an electrically conductive surface. The process further includes grounding the electrically conductive surface of the non-particulate detergent composition. Still further, the process includes providing an electrostatically chargeable carrier material having a perfume adsorbed therein. Finally, the process includes coating the electrostatically chargeable carrier material onto the electrically conductive surface of the non-particulate detergent composition by means of an electrostatic charging and delivery system, whereby the electrostatically charged carrier material is adhered to the electrically conductive surface of the detergent composition.

The present invention relates to detergent compositions in non-particulate form. More particularly, the invention relates to a process for improving the aesthetics of detergent compositions in non-particulate form, e.g., tablet, block or bar, by improving the neat product odor of a non-particulate detergent and also enabling the delivery of different fragrances to a non-particulate detergent product as compared to the odor delivered to the laundry by a perfume incorporated within the detergent, by using electrostatic techniques.
Non-particulate solids detergents are an alternative to granular or particulate forms of detergents for simplifying the dosing of such detergents for automatic laundry or dishwashing washing machines. Such non-particulate detergents are usually supplied in the form of bars or tablets or briquettes. Such non-particulate detergents not only prevent spillage of the detergent composition but also eliminate the need for the consumer to estimate the correct dosage of the detergent composition per wash. Further, such non-particulate detergents also minimize the contact by the consumer with the detergent.
An important factor for successful performance of a non-particulate detergent is its ability to dissolve in the washing machine in a controlled manner according to a desired dissolution profile during the program cycle of the machine. Another important performance factor is that the non-particulate detergent should be hard enough to facilitate easy handling of the detergent prior to use, so that it does not inadvertently lose its structure, crumble, or deteriorate, both during the packaging, transport and storage and during handling by the end consumer prior to actual use. Such performance aspects are an important feature of the non-particulate detergent, and although they are not necessarily the focus of the present invention, they are inherently a part of the background of the present invention.
A very desirable feature of a non-particulate detergent, such as for example, a tablet, is its appearance and odor. From an aesthetics standpoint, consumers prefer to use detergent tablets that have a fragrant odor. It is thus desirable to improve the neat product odor of detergent tablets. Hence, most detergent compositions include a perfume incorporated within the detergent. However, in order to improve the hardness of the detergent tablet, the tablets are occasionally encapsulated by a protective coating. This coating can substantially mask the odor of the perfume incorporated within the detergent. By dusting the tablet with a perfume carrier, one can improve the neat product odor and make the tablet detergent product more aesthetically pleasing. Additionally, the deposition of a perfume carrier coating on a detergent tablet enables the delivery of different fragrances to the detergent tablet product as compared to the odor delivered to the laundry by a perfume incorporated within the detergent composition.
It is highly desirable to have a laundry detergent tablet with a core which is formed by compressing a particulate material, the particulate material having a surfactant and detergent builder, which is coated with a perfume in order to improve its odor. It is also desirable to provide a laundry tablet with a hard, thin, coating which has a perfume coating deposited on it, so that the laundry tablet has a pleasant odor, it can be stored, shipped and handled, but the coating is broken when the tablet is in the washing machine exposing the soft core which breaks up easily and rapidly, releasing the active ingredients into the wash solution.
Thus, it is highly desirable to improve the neat product odor of a nonparticulate detergent. It is also highly desirable to have a process for providing a non-particulate detergent tablet with a perfume carrier in a manner so that the perfume carrier would adhere to the tablet and remain so during packaging, transport, storage and handling prior to eventual use.
The prior art is replete with methods of coating tablets, and many methods have been suggested for coating detergent tablets.
GB-A-0 989 683, published on Apr. 22, 1965, discloses a process for preparing a particulate detergent from surfactants and inorganic salts; spraying on water-soluble silicate; and pressing the detergent particles into a solid form-retaining tablet. Finally a readily water-soluble organic film-forming polymer (for example, polyvinyl alcohol) provides a coating to make the detergent tablet resistant to abrasion and accidental breakage.
EP-A-0 002 293, published on Jun. 13, 1979, discloses a tablet coating comprising hydrated salt such as acetate, metaborate, orthophosphate, tartrate, and sulphate.
EP-A-0 716 144, published on Jun. 12, 1996, also discloses laundry detergent tablets with water-soluble coatings which may be organic polymers including acrylic/maleic co-polymer, polyethylene glycol, PVPVA, and sugar.
PCT Publication WO 95/18215, published on Jul. 6, 1995, provides water-insoluble coatings for solid cast tablets. The tablets are provided with hydrophobic coatings including wax, fatty acid, fatty acid amides, and polyethylene glycol.
Other prior art discloses the use of carriers, such as zeolite, for example, for delivering perfume. For example, U.S. Pat. No. 5,648,328 discloses a process for producing a particulate laundry additive composition for perfume delivery primarily in laundry detergent and fabric softening products. The process utilizes a porous carrier material loaded with a perfume and as a result of this process, the perfume is sealed into the carrier material sufficiently to not permit exposure until subjected to the laundering or softening process. In the ""328 patent, the preferred perfume carrier materials are zeolite X, zeolite Y, and mixtures thereof However the focus of the ""328 patent is on particulate laundry composition additives and not on non-particulate detergents having perfume deposited on the surface.
U.S. Pat. No. 5,000,978 discloses a process for making coated detergent granules by producing detergent granules and then uniformly distributing finely divided powder onto the surfaces of the detergent granules by means of an electrostatic charging and delivery system.
The invention meets the needs above by providing a process for producing a non-particulate detergent having an improved neat product odor, and a process for producing a non-particulate detergent product having a perfume loaded carrier material coating.
In one aspect of the present invention, the process comprises the steps of (a) providing a powdered porous carrier material; (b) adsorbing a perfume onto the powdered porous carrier material; and (c) depositing the powdered porous carrier material having adsorbed perfume on the non-particulate detergent product. With the aforementioned optimally selected steps of the present invention, a uniform coating of a perfume laden porous carrier material is adhered to a detergent tablet surface, thus improving its neat product odor and also enabling the delivery of different fragrances to the detergent tablet product as compared to the odor delivered to the laundry by a perfume incorporated within the detergent composition.
In another aspect of the present invention, the process includes the step of providing a non-particulate detergent composition having an electrically conductive surface. The process further includes the step of grounding the electrically conductive surface of the non-particulate detergent composition. Still further, the process includes the step of providing an electrostatically chargeable carrier material having a perfume adsorbed therein. Finally, the process includes the step of coating the electrostatically chargeable carrier material onto the electrically conductive surface of the non-particulate detergent composition by means of applying an electrostatic charge with an electrostatic charging and delivery system, such that the electrostatically charged carrier material is adhered to the electrically conductive surface of the detergent composition, even after the electrostatic charge has dissipated.
As used herein, the phrase xe2x80x9celectrically conductivexe2x80x9d means that the surface is capable of allowing electric current to pass through it without offering a substantial resistance to the flow of current.
As used herein, the phrase xe2x80x9celectrostatically chargeablexe2x80x9d means a powder that is ionically chargeable by electrostatic induction means.
The process of the invention unexpectedly provides a means by which a non-particulate detergent composition, say, a tablet, can be coated with a finely sized uniformly dispersed, thin layer coating of a perfume loaded powder, thus improving its neat product odor and also enabling the delivery of different fragrances to the detergent tablet product as compared to the odor delivered to the laundry by a perfume incorporated within the detergent composition.
Different modes of deposition can be chosen, such as spraying, dusting, using a fluidized bed chamber and the like. Most unexpectedly, it has been discovered that the amount of the perfume loaded powder deposited electrostatically in a fixed amount of time according to the claimed process invention, is more than ten times greater than the amount of perfume loaded powder depositable without following the steps of the claimed process invention. Further, this process unexpectedly produces an extremely uniform coating of a de-agglomerated perfume loaded powder, which enhances the aesthetics of the detergent tablet, such as appearance and smell.
In one embodiment, the porous carrier particles loaded with perfume can be electrostatically deposited on the surface of the detergent tablet without treating the detergent tablet surface. In another embodiment, the detergent tablet surface can be electrostatically charged or connected to a grounding source. Preferably, a detergent tablet having an electrically conductive surface formed of a coating, as described hereinafter, is provided. The detergent tablet having the electrically conductive coating, is electrically connected to a grounding source. A porous carrier material having perfume adsorbed therein, as described hereinafter, is also provided. The porous carrier material selected must be electrostatically chargeable. The porous carrier material is electrostatically charged and delivered to the grounded detergent tablet by one of various electrostatic charging and delivery systems, such as by using an electrostatic powder spray gun or an electrostatic fluidized bed coater, as described in more detail in the ensuing paragraphs. The charged perfume loaded carrier powder is distributed onto the surface of the grounded detergent tablet. The carrier powder and the detergent tablet surface are attracted to each other due to Coulomb forces and a uniform coating of the perfume loaded carrier material on the detergent tablet surface is resultantly formed. Because the carrier powder de-agglomerates upon electrostatic charging, a superior, more uniform coverage of the tablets is obtained and the coating remains adhered to the detergent tablet even after the electrostatic charge has dissipated.
The detergent tablets to be coated with a perfume can be prepared simply by mixing the solid ingredients together and compressing the mixture in a conventional tablet press as used, for example, in the pharmaceutical industry. Any liquid ingredients, for example the surfactant or suds suppresser, can be incorporated in a conventional manner into the solid particulate ingredients. Preferably, the principal ingredients are used in a particulate form.
In particular for laundry tablets, the ingredients such as builder and surfactant can be spray-dried in a conventional manner and then compacted at a suitable pressure.
The detergent tablets provided can be made in any size or shape and can, if desired, be surface treated before providing a perfume coating, according to the present invention. In the core of the tablet is included a surfactant and a builder which normally provides a substantial part of the cleaning power of the tablet. The term xe2x80x9cbuilderxe2x80x9d is intended to mean all materials which tend to remove calcium ion from solution, either by ion exchange, complexation, sequestration or precipitation.
The particulate material used for making the detergent tablet provided in this invention can be made by any particulation or granulation process. An example of such a process is spray drying (in a co-current or counter current spray drying tower) which typically gives low bulk densities 600 g/l or lower. Particulate materials of higher density can be prepared by granulation and densification in a high shear batch mixer/granulator or by a continuous granulation and densification process (e.g. using Lodige(copyright) CB and/or Lodige(copyright) KM mixers). Other suitable processes include fluid bed processes, compaction processes (e.g. roll compaction), extrusion, as well as any particulate material made by any chemical process like flocculation, crystallization sentering, etc. The individual particles can also be in any other form, such as for example, particle, granule, sphere or grain.
The particulate materials may be mixed together by any conventional means, for example, a concrete mixer, Nauta mixer, ribbon mixer or any other. Alternatively the mixing process may be carried out continuously by metering each component by weight on to a moving belt, and blending them in one or more drum(s) or mixer(s). A liquid spray-on to the mix of particulate materials (e.g. non-ionic surfactants) may be carried out. Other liquid ingredients may also be sprayed on to the mix of particulate materials either separately or premixed. For example perfume and slurries of optical brighteners may be sprayed. A finely divided flow aid (dusting agent such as zeolites, carbonates, silicas) can be added to the particulate materials after spraying the non-ionic, preferably towards the end of the process, to make the mix less sticky.
The detergent tablets provided may be manufactured by using any compacting process, such as tabletting, briquetting, or extrusion, preferably tabletting. Suitable equipment includes a standard single stroke or a rotary press (such as Courtoy(copyright), Korch(copyright), Manesty(copyright), or Bonals(copyright)). In one embodiment, the tablets are coated with an electrically conductive coating in order to provide an electrically conductive surface for the detergent tablet. The tablets are coated with a coating that is both electrically conductive and substantially insoluble in water so that the tablet does not absorb moisture, or absorbs moisture at only a very slow rate. The coating is also strong so that moderate mechanical shocks to which the tablets are subjected during handling, packing and shipping result in no more than very low levels of breakage or attrition. Further, the coating is preferably brittle so that the tablet breaks up when subjected to stronger mechanical shock. Furthermore it is advantageous if the coating material is dissolved under alkaline conditions, or is readily emulsified by surfactants. This avoids the deposition of undissolved particles or lumps of coating material on the laundry load. This may be important when the coating material is completely insoluble (for example less than 1 g/l) in water.
As defined herein xe2x80x9csubstantially insolublexe2x80x9d means having a very low solubility in water. This should be understood to mean having a solubility in water at 25xc2x0 C. of less than 20 g/L, preferably less than 5 g/l, and more preferably less than 1 g/l. Water solubility is measured following the test protocol of ASTM E1148-87 entitled, xe2x80x9cStandard Test Method for Measurements of Aqueous Solubilityxe2x80x9d.
Suitable coating materials are fatty acids, adipic acid and C8-C13 dicarboxylic acids, fatty alcohols, diols, esters and ethers. Preferred fatty acids are those having a carbon chain length of from C12 to C22 and most preferably from C18 to C22. Preferred dicarboxylic acids are adipic acid (C6), suberic acid (C8), azelaic acid (C9), sebacic acid (C10), undecanedioic acid (C11), dodecanedioic acid (C12) and tridecanedioic acid (C13). Preferred fatty alcohols are those having a carbon chain length of from C12 to C22 and most preferably from C14 to C18. Preferred diols are 1,2-octadecanediol and 1,2-hexadecanediol. Preferred esters are tristearin, tripalmitin, methylbehenate, ethylstearate. Preferred ethers are diethyleneglycol mono hexadecylether, diethyleneglycol mono octadecylether, diethyleneglycol mono tetradecylether, phenylether, ethyl naphtyl ether, 2 methoxynaphtalene, beta naphtyl methyl ether and glycerol monooctadecylether. Other preferred coating materials include dimethyl 2,2 propanol, 2 hexadecanol, 2 octadecanone, 2 hexadecanone, 2, 15 hexadecanedione and 2 hydroxybenzyl alcohol. The electrically conductive coating is a hydrophobic material having a melting point preferably of from 40xc2x0 C. to 180xc2x0 C.
In the preferred embodiment, the electrically conductive coating can be applied in a number of ways. Two preferred coating methods are a) coating with a molten material and b) coating with a solution of the material. In a), the coating material is applied at a temperature above its melting point, and solidifies on the tablet. In b), the coating is applied as a solution, the solvent being dried to leave a coherent coating. The substantially insoluble material can be applied to the tablet by, for example, spraying or dipping. Normally when the molten material is sprayed on to the tablet, it will rapidly solidify to form a coherent coating. When tablets are dipped into the molten material and then removed, the rapid cooling again causes rapid solidification of the coating material. Clearly substantially insoluble materials having a melting point below 40xc2x0 C. are not sufficiently solid at ambient temperatures and it has been found that materials having a melting point above about 180xc2x0 C. are not practicable to use. Preferably, the materials melt in the range from 60xc2x0 C. to 160xc2x0 C., more preferably from 70xc2x0 C. to 120xc2x0 C.
By xe2x80x9cmelting pointxe2x80x9d is meant the temperature at which the material when heated slowly in, for example, a capillary tube becomes a clear liquid.
An electrically conductive coating of any desired thickness can be applied according to the present invention. For most purposes, the electrically conductive coating forms from 1% to 10%, preferably from 1.5% to 5%, of the tablet weight.
Alternatively, the detergent tablet may be imparted with an electrically conductive surface without providing a coating. One method of providing an electrically conductive surface is by providing an electrostatic charge on the surface of the detergent tablet.
As used herein, xe2x80x9cporous carrier particlesxe2x80x9d means any material capable of supporting (e.g., by absorption onto the surface or adsorption into pores) a perfume agent for incorporation into the particulate compositions. Such materials include porous solids selected from the group consisting of amorphous silicates, crystalline nonlayer silicates, layer silicates, calcium carbonates, calcium/sodium carbonate double salts, sodium carbonates, clays, zeolites, sodalites, alkali metal phosphates, macroporous zeolites, chitin microbeads, carboxyalkylcelluloses, carboxyalkylstarches, cyclodextrins, porous starches and mixtures thereof Preferred perfume carrier materials are zeolite A, zeolite X, zeolite Y, zeolite P, zeolite MAP and mixtures thereof. The term xe2x80x9czeolitexe2x80x9d used herein refers to a crystalline aluminosilicate material. The structural formula of a zeolite is based on the crystal unit cell, the smallest unit of structure represented by
Mm/n[(AlO2)m(SiO2)y].xH2O
where n is the valence of the cation M, x is the number of water molecules per unit cell, m and y are the total number of tetrahedra per unit cell, and y/m is 1 to 100. Most preferably, y/m is 1 to 5. The cation M can be Group IA and Group IIA elements, such as sodium, potassium, magnesium, and calcium.
The zeolites to be used herein preferably contain less than about 20% desorbable water, more preferably less than about 8% desorbable water, and most preferably less than about 5% desorbable water. Such materials may be obtained by first activating/dehydrating by heating to about 150xc2x0 C. to 350xc2x0 C., optionally with reduced pressure (from about 0.001 to about 20 Torr). After activation, the perfume is slowly and thoroughly mixed with the activated zeolite and, optionally, heated to about 60xc2x0 C. for up to about 2 hours to accelerate absorption equilibrium within the zeolite particles. The perfume/zeolite mixture is then cooled to room temperature and is in the form of a free-flowing powder.
In the preferred embodiment, the perfume is adsorbed on the surface of the zeolite by spraying liquid perfume on the zeolite particles. It is preferred to adsorb the perfume on the surface of the zeolite rather than incorporating the perfume within the zeolite because the odor of the perfume that is adsorbed on the zeolite rather than incorporated therein is greater, when the perfume laden zeolite powder is electrostatically coated on the detergent tablet surface.
In the preferred embodiment, the zeolite powder can be electrostatically charged by any electrostatic charging system, such as an electrostatic spray gun, for example.
As used herein the term xe2x80x9cperfumexe2x80x9d is used to indicate any odoriferous material which is subsequently released into the aqueous bath and/or onto fabrics contacted therewith. The perfume will most often be liquid at ambient temperatures. A wide variety of chemicals are known for perfume uses, including materials such as aldehydes, ketones and esters. More commonly, naturally occurring plant and animal oils and exudates comprising complex mixtures of various chemical components are known for use as perfumes. The perfumes herein can be relatively simple in their compositions or can comprise highly sophisticated complex mixtures of natural and synthetic chemical components, all chosen to provide any desired odor. Typical perfumes can comprise, for example, woody/earthy bases containing exotic materials such as sandalwood, civet and patchouli oil. The perfumes can be of a light floral fragrance, e.g., rose extract, violet extract, and lilac. The perfumes can also be formulated to provide desirable fruity odors, e.g., lime, lemon, and orange. Any chemically compatible material which exudes a pleasant or otherwise desirable odor can be used in the perfumed compositions herein.
Perfumes also include pro-fragrances such as acetal pro-fragrances, ketal pro-fragrances, ester pro-fragrances (e.g., digeranyl succinate), hydrolyzable inorganic-organic pro-fragrances, and mixtures thereof. These pro-fragrances may release the perfume material as a result of simple hydrolysis, or may be pH-change-triggered pro-fragrances (e.g., pH drop) or may be enzymatically releasable pro-fragrances.
In the preferred embodiment, the amount of perfume adsorbed on the carrier material, such as zeolite for example, is preferably in the range of 0.1% to 50% by weight, more preferably in the range of 0.5% to 25% by weight, and most preferably in the range of 1% to 15% by weight of zeolite powder.
The perfume loaded carrier material is uniformly distributed on the surface of the detergent tablets preferably by means of an electrostatic charging and delivery system. U.S. Pat. No. 4,780,331, Cobbs, Jr. et al., issued Oct. 25, 1988, incorporated herein, describes a particular method and apparatus for charging powder particles by electrostatic induction. Generally, the electrostatic charging system contains electrodes which ionize the air surrounding them. The perfume loaded carrier material is preferably in a finely divided powder form. The finely divided powder is passed by these electrodes and acquires the ionic charges. The powder is then distributed in the area of the detergent tablets. Because of the electrostatic charges, the powder is attracted to and uniformly distributed on the surfaces of the detergent tablets. It is not necessary to charge the detergent tablets. The detergent tablets must be grounded. As a practical matter, the detergent tablets are not individually grounded but the object which contains them, preferably a conveyor belt, should be grounded. After the charged powder application, there is no need for a curing or fusion step to ensure long-term adhesion of the powder on the tablet.
The preferred electrostatic system for use herein is an electrostatic powder spray gun. An electrostatic powder spray gun is described in U.S. Pat. No. 4,380,320, Hollstein et al., issued Apr. 19, 1983, incorporated herein. This step preferably comprises charging the finely divided powder in an electrostatic powder spray gun and then spraying the charged finely divided powder from the gun onto the detergent tablets.
The most preferred electrostatic powder spray gun for use herein has three parts: a gravity feed hopper, a control console, and the gun itself. The finely divided powder is fed into the gravity feed hopper. The control console has controls for regulating flow rate, fluidizing rate, atomizing rate and voltage level. The type of powder used generally controls which rate settings give the best results. The finely divided powder is channeled from the gravity feed hopper into the central passageway of the gun. Pressurized gas forces the powder through the passageway, where the powder acquires an electrostatic charge and, when a trigger on the gun is pressed by an operator, the charged powder is emitted from the gun in a conical spray pattern.
It is preferred that multiple electrostatic powder spray guns be mounted above and below a conveyor belt having perforations or openings therein. The nozzle of the gun is preferably pointed directly at the tablets from both sides of the conveyor belt. The detergent tablets are placed on the conveyor belt randomly, when the cloud of charged powder particles is emitted from the gun. The charged powder particles are attracted to the detergent tablet surface and are uniformly distributed on the surfaces of the tablets.
Any other method for maintaining the tablets in the area of the charged powder particles can be used; for example, by placing the detergent tablets within a fluidized bed chamber. In a fluidized bed chamber, the finely divided particles are charged by ionized air which passes through a perforated plate at the base of the chamber and the charged particles are uniformly deposited on the detergent tablets.

Process for producing electrostatically coated non-particulate detergent product


One or more substrates may be coiled into one or more coils in such a way that adjacent turns of the coils do not touch one another. The one or more coiled substrates are placed in a treatment chamber where substantially an entire surface of the one or more coiled substrates may be treated with a surface treatment process. One or more spacers may be placed between adjacent layers of the coiled substrate before a full turn of the substrate has been coiled around a carousel.

Several forms of surface chemistry and surface treatment depend upon the interaction of a substrate with its environment, including annealing, drying, and exposure to reactive gas. For example, Atomic Layer Deposition (ALD) is a high-quality thin-film deposition technique based on sequential, self-limiting surface reactions. Atomic layer deposition works by exposing a substrate sequentially to two or more reactant vapors or solutions and maintaining the substrate temperature within, for example, a temperature range that depends on the chemistry of the particular ALD reaction. A typical ALD process involves a sequence of two different and alternating surface reactions involving two different gaseous reactants referred to herein as A and B. The ALD system is typically purged of reactant gas in between reactions with a non-reactive purge gas C, and/or is pumped clean of the reactant gases. Sequencing the reactions provides precision in the rate of deposition and allows the use of highly reactive reactants. With each reactant exposure, a self-limiting reaction occurs on the surface of the substrate if the substrate temperature is, for example, within the right temperature range, or alternative energy sources are provided, such as energetic ions or molecules or atoms, ozone, plasma, UV light, etc.
ALD can control the thickness of deposited films at the level of an atomic or sub-atomic layer. Thus films deposited by ALD tend to be uniform over large areas. In addition ALD allows deposition of conformal films on structures having very high aspect ratios (e.g., >>10). A wide variety of materials may be deposited by ALD, including semiconductors, metals, oxides, nitrides, and other materials. ALD techniques can thus deposit thin films one atomic layer at a time, in a "digital" fashion. Such "digital" build-up of material greatly simplifies thickness control, thus reducing both the complexity and cost of thin film deposition.
Many industries, such as the optoelectronics industry, can benefit from the high uniformity, high aspect ratio conformal coating abilities and low cost of ALD. Unfortunately, prior art ALD systems have mostly been made for semiconductor wafer processing, which is oriented to batch processed wafer handling systems. Although existing ALD systems are suitable for the semiconductor industry, they are unsuitable for high volume manufacturing of large area devices such as photovoltaic cells. Current systems are typically designed to coat small area wafers. Scaling up systems that coat a small area at a time might not be practical for coating large area sheets, panels or rolls of material. ALD may be too slow and expensive overall, if only small area batch processing can be performed. Further, surface treatments such as annealing, drying, and exposure to reactive gases cannot be carried out at high-volume for large-area substrates when the surface treatments and/or reactions take place in a relatively smaller treatment chamber.
Thus, there is a need in the art, for a high throughput surface treatment method and system.

High throughput surface treatment on coiled flexible substrates


The invention relates to an integrated circuit, containing an A/D converter and a test circuit, the latter in a test mode enabling explicit testing of analog and digital control signals of the circuit by supplying these control signals to circuit sections of the A/D converter and thus generating digital data signals at the output of the A/D converter. Analog signals, like bias signals and reference signals, can be selected and supplied to the input facility of the converter. Subsequently, a digital representation of the selected signal is obtained at the output facility of the converter. Digital signals, like clock signals, can be selected and supplied directly to the output facility. The output facility is operated by a clock signal and constructs a clocked version of the selected digital signal, which is subsequently available at the output. Thus, selected signals, either digital or analog, are available at the output of the converter and can be compared to specified data.

The invention relates to an integrated circuit containing an A/D converter and a test circuit, the operation of said A/D converter being under control of a plurality of analog and digital control signals, one of the latter being a clock signal, said A/D converter including an input facility for receiving an analog input signal, analog signal comparison means connected to the input facility for comparing the analog input signal with a number of reference values and thus generating respective elements of a digital sequence, digital conversion means connected to the analog signal comparison means for converting the digital sequence to a first digital data signal, and a digital output facility that is controlled by the clock signal and connected to the digital conversion means for outputting the first digital data signal.
In view of the importance of the A/D converter for the overall performance of the system of which the converter forms a part, thorough testing of this component is required. The operation of an A/D converter is controlled by a set of time-variant and time-invariant control signals. These control signals, also designated the control path, consist of reference signals, bias signals, clock signals, etc. For proper operation of the converter, these control signals are required to match certain specifications. This is tested only implicitly with functional (data path) testing. Explicit testing of the control path could detect defects and faults that would otherwise escape detection. To make explicit testing feasible, a Design for Testability (DfT) solution is necessary, since the control path is generally not accessible for measurement. In U.S. Pat. No. 5,389,926 a set-up has been disclosed, featuring a test circuit, coupled to an A/D converter. This test circuit is activated in a test mode to connect a terminal to an output node of an internal circuit section of the converter, which has a function of generating a changeable reference voltage at that output node. The magnitude of the thus generated reference voltage can be monitored on the terminal. This set-up, however, does not provide a way for digital on-chip testing of the control signals of the A/D converter.

Testing control signals in A/D converters


An arrangement for locking and unlocking a door of a container for increasing operating reliability when locking and unlocking in a simple manner and for ensuring an opening and closing of the transport container in automated operation. Particle generation is reduced at the same time. Locking elements within a door, which can move in and out, penetrate into recesses of the container to be closed when moved out along a curved path. The arrangement is particularly applicable in transport containers for wafer-shaped objects of larger diameter, in which removal and charging are effected individually in a plane parallel to the surface of the wafer-shaped object and whose container cover is removed and inserted laterally.

a) Field of the Invention
The invention is directed to an arrangement for locking and unlocking a door of a container, in particular containers for transporting wafer-shaped objects, with locking elements within the door which can move in and out and which, when moved out, penetrate into recesses of the container to be closed. The invention is especially applicable in the semiconductor industry, but can also be used in the manufacture of flat display screens. A technical solution of this kind is known from U.S. Pat. No. 4,995,430, for example.
b) Description of the Related Art
For the purpose of charging semiconductor processing installations, so-called SMIF boxes are frequently used as magazine containers in which semiconductor wafer magazines can be stored and transported. The box can be placed on an opening mechanism in an enclosure which encloses one or more work stations so as to keep them free of dust. The box and opening mechanism have closing elements which are adapted to one another and which can be opened simultaneously one above the other so that dust particles resting on the outside of the closing elements can be enclosed therebetween when the semiconductor wafer magazines are lowered into the enclosure together with the two closing elements. The box itself encloses the opening formed in the enclosure.
The locking mechanism disclosed in U.S. Pat. No. 4,995,430 for opening and closing a SMIF box of this kind operates in consecutive steps in which a locking mechanism occupies three different positions. The first position corresponds to a moved-in state and the second position corresponds to a fully moved-out state. In the fully moved-out position, the closing of the SMIF box is effected by a tilting of the locking element, which is constructed as a lever, so as to prevent particles generated by friction from occurring in the locking region. However, the formation of particles is not prevented in the regions of actuation, since wedges are pushed under the other end of the lever in order to tilt the locking mechanism.
The technique of SMIF boxes is especially suited for semiconductor wafers with conventional smaller diameters. In view of the material characteristics of the semiconductor wafers, these SMIF boxes and the semiconductor wafer magazines used with them are becoming increasingly less suitable as transporting containers as the diameter of semiconductor wafers increases. Transporting containers which simultaneously perform the function of magazines are already known for semiconductor wafers of this type. Removal and charging of the semiconductor wafers is effected individually in a plane parallel to the surface of the semiconductor wafers, wherein the transporting container can be closed by a container cover which is directed substantially at right angles to the removal and charging plane. Accordingly, in contrast to the SMIF box, the container cover is removed and inserted laterally rather than in a downward direction.
Current known transport containers which are also subject to the requirement that particle formation be avoided when opening and closing have the disadvantage that the container cover can often only be opened with difficulty, if at all. For a dependable operation, known locking and unlocking elements which act separately and which have favorable results with respect to clean rooms due to their vacuum actuation and the possibility of encapsulation must be provided with sensors which signal a failure. Moreover, overcoming failures in automated operation results in additional costs.

Arrangement for locking and unlocking a door of a container


An integrated circuit includes a number of terminals to transfer signals. Each of the terminals has an adjustable termination impedance. The integrated circuit also includes a control circuit coupled to the terminals to adjust the value of the termination impedance of each of the terminals to improve signal detection at the terminals.

A typical electrical device has terminals or pins. Cables or conducting traces on a circuit board are usually used as transmission lines connecting between the terminals of two or more devices to transfer signals between the devices.
To maintain the property of the signals during the transmission between the terminals and the transmission lines, each terminal of a typical electrical device usually has a termination resistor. The termination resistor often has a value chosen to match the resistance (impedance) value of the transmission line connected to the terminal to reduce signal reflection on the transmission line.
Changes in the environment factors such as manufacturing processes, voltage, and temperature may change the value of the termination resistor. Thus, various methods were developed to hold the value of the termination resistor at the chosen value when the environment factors changes.
In one known method, an external resistor is used as a reference to hold the termination resistor at the chosen value. However, the external resistor requires additional pins for the device. The additional pins waste available space and may increase the cost of the device. Further, even if the value of the termination resistor is kept at the chosen value using known methods, the resistance value of the transmission line may change due to changes in factors such as signal frequency and design topology of the transmission lines. Therefore, even if the value of the termination resistor remains at the chosen value, a mismatch may still exist between the value of the termination resistor and the resistance value of the transmission line.
The mismatch between the value of the termination resistor and the resistance value of the transmission line may cause degradation of the signal received at the terminal or may cause detection of the signal at the terminal more difficult or inaccurate.

Adaptive termination for optimum signal detection


A communication system includes a wireless IC tag and a reader/writer that performs reading and writing on the wireless IC tag via wireless communication. The reader/writer includes an error control encoder and an error control decoder. On writing data into the wireless IC tag, the reader/writer encodes the data by the error control encoder and writes real data separately from error-control-decodable data. On reading out data from the wireless IC tag, the reader/writer selects whether to read out only the real data or to read out data including error-control-decodable information to decode the data by the error control decoder based on error control information indicating whether to perform error control or not.

Wireless IC tag communication system has become widely used for physical distribution, parts management, and inventory management in recent years. In the wireless IC tag communication system, management is realized with a wireless IC tag (RFID tag), which is attached to an article or the like to be managed and in which information such as an identification code of the article or the like to be managed is written, and a reader/writer (interrogator) which reads out the information from the wireless IC tag. A manner to deal with errors caused by distortion generated in a communication channel is not specifically set down in standard of the wireless IC tag itself. Hence, conventionally, data in the wireless IC tags are processed through independent techniques for error control (See Patent Document 1, for example).
FIG. 9 is a diagram illustrating an allocation of memory regions in the wireless IC tag of the above-described system. In the above-described system, an error correcting code is applied to data before the data is written into the wireless IC tag as shown in FIG. 9. In communication between the reader/writer and the wireless IC tag, all of 128 bits shown in FIG. 9 are always employed, and the communication is made only with a reader/writer that has an error correcting function.    Patent Document 1: Japanese Patent Application Laid-Open No. 2004-29984


An activated carbon producing system includes a heating furnace for thermally decomposing multi-layer film including a polyvinyl alcohol layer and cellulose triacetate (TAC) layers formed on surfaces of the polyvinyl alcohol layer, to produce carbonized material by carbonization. An activation device activates the carbonized material with heat, to produce activated carbon by forming fine pores therein. A burner assembly combusts acetic acid contained in pyrolysis gas created by thermal decomposition in the heating furnace, to produce gaseous carbon dioxide. A first heat exchanger exchanges heat between the pyrolysis gas from the burner assembly and heat exchange medium, to provide the heating furnace with the heat of the heat exchange medium. A washer absorbs gaseous carbon dioxide contained in the pyrolysis gas from the first heat exchanger by use of alkaline absorption solution. If the multi-layer film contains additive, the washer washes away the combusted additive.

1. Field of the Invention
The present invention relates to a method and system for producing activated carbon. More particularly, the present invention relates to a method and system for producing activated carbon, in which cellulose acylate can be utilized as raw material, and the activated carbon can be produced with economized heat energy.
2. Description Related to the Prior Art
Polymer films have excellent optical transmittance and flexibility and are capable of forming thin and lightweight films. Owing to this, the polymer films are widely used as optical functional films. In particular, a cellulose acylate film formed of cellulose acylate and the like has toughness and low birefringence in addition to those properties. The film is used as a support of photo film or photosensitive material, and a protection film for a polarizing filter incorporated in a panel, namely, a liquid crystal display (LCD) whose market is recently expanding.
In a polarizing filter production process to produce polarizing filters, approximately 30% of the total amount of supplied films is discarded. The discarded films or waste films are rapidly increasing in accordance with rapid market expansion of the polarizing filters. However, reuse and recycle systems have not been developed for the waste films in comparison with a reuse system of wastepaper and a recycle resin forming system of waste plastics. Waste films are burned or disposed of in landfills at additional waste-processing expense.
However, reuse of the waste films has not been known with the viewpoint of recent environmental problems and saving of resources.
To reuse waste materials, their recycling as raw materials for newly producing film is conceived. Separation or isolation of cellulose acylates and polyvinyl alcohol from waste films is required. Furthermore, various additives are contained in waste materials of polarizing filters, as those must be contained polymer films as initial form of polarizing filters. It is extremely difficult to isolate the cellulose acylates and polyvinyl alcohol, namely to recover the cellulose acylates and polyvinyl alcohol selectively by removing additives from the waste films in the mixture. The cellulose acylates and polyvinyl alcohol will be unrecoverable as material for new films.
Paper, wood, and thermoset resins such as phenol resin become porous without liquefaction upon application of heat. JP-A 11-171524 discloses a method which reuses wastepaper such as old newspaper and the like as a raw material of activated carbon. JP-A 7-172808 discloses a method which reuses phenol resin-based wastes as raw materials of activated carbon. There is a known process of decomposing cellulose acylate by application of heat.
However, in many cases, carbonized materials generated by carbonization of waste materials do not have high absorptivity due to the above reasons. Accordingly, carbonized materials are used not as adsorbents, but mainly as soil improvement agents, fuels or the like.
According to the conventional knowledge, the thermoplastic resin does not become porous characteristically in carbonization, because of thermal decomposition with heat. Although it is well-known that cellulose acylate as thermoplastic resin decomposes when heated, a reaction mechanism of its carbonization has not been essentially found. There is no known method of producing activated carbon from waste material of polarizing filters which have increased industrially. Saving of heat energy is an important focus because heat energy of a very great amount is required for producing activated carbon.

Method and system for producing activated carbon


A tool for adjusting a grip. The tool includes a tubular section for containing the grip while receiving a cable. A first stop is positioned in or near a first end of the tubular section to provide an opening for introducing the cable into the tubular section while the grip is contained in the tool. One of first and second stops is arranged for displacement along the longitudinal axis with respect to the other stop. With the grip positioned between the first and second stops, when one of the stops is displaced toward the other stop a force is applied against the grip, causing the size of the bore to increase and the length of the grip to be contracted.

Cable grips are used extensively in many industries to pull cable segments through conduit, along and between overhead towers, or in structural applications. Such grips are important tools for installation of both electrical and mechanical cables in, for example, bridge structures, hoisting and conveyor cables. Contemporary designs of cable grips were advanced during the first half of the twentieth century by Edgar Kellems, as described in part in U.S. Pat. Nos. 1,670,543, 1,886,026, and 2,664,609, each of which is incorporated herein by reference.
Commonly, a grip has a bore at one end and an eye portion at a distal end. With a cable which is to be pulled or secured placed in the bore, the grip is tightened about the cable and the eye portion is attached to a hook, or another cable or another type of mechanical linkage, in order to place the grip under tension. Such grips are generally fashioned as woven wire tubes with meshes of wire much smaller in gauge than the size of the cable inserted within the bore. Commonly, such grips are available in a large variety of sizes for application to mechanical cable and electrical wire varying in radial dimension from relatively small sizes such as used in residential electrical applications to large dimensions on the order of about two inches (5.08 cm) or greater. Cable grips are useful for pulling, positioning, routing and providing for strain relief of cables.
When attaching a grip to a cable, the grip is contracted along a longitudinal axis in order to enlarge the radial dimension of the bore about the longitudinal axis and thereby permit entry of the cable into the grip bore. Once the cable is positioned in the bore, the diameter of the bore opening is reduced to tighten the grip about the cable. Grips of this type are designed for limited ranges of cable size to assure that the grip can be used to reliably pull or secure the cable.

Method and tool for adjusting cable grips


One embodiment of the present invention provides a switch. The switch comprises a plurality of ports, a link management module, a forwarding module, and a link adaptation module. The link management module operates at least two ports of the plurality of ports of the switch to form a link aggregation. This link aggregation operates as a single logical channel. The forwarding module determines an egress port for a packet among the ports participating in the link aggregation based on a distribution policy. The link adaptation module detects an imbalance of the respective link utilizations among links of the link aggregation based on one or more imbalance criteria, and applies one or more corrective actions to the distribution policy.

Field
The present disclosure relates to network management. More specifically, the present disclosure relates to a method and system for providing adaptive link aggregations (LAGs) and virtual link aggregations (VLAGs).
Related Art
The exponential growth of the Internet has made it a popular delivery medium for multimedia applications, such as video on demand and television. Such applications have brought with them an increasing demand for bandwidth. As a result, equipment vendors race to build larger and faster switches with versatile capabilities, such as multicasting, to move more traffic efficiently. However, the size of a switch cannot grow infinitely. It is limited by physical space, power consumption, and design complexity, to name a few factors. Furthermore, switches with higher capability are usually more complex and expensive. More importantly, because an overly large and complex system often does not provide economy of scale, simply increasing the size and capability of a switch may prove economically unviable due to the increased per-port cost.
As more time-critical applications are being implemented in data communication networks, high-availability operation is becoming progressively more important as a value proposition for network architects. It is often desirable to aggregate multiple links to a switch (referred to as a link aggregation), or links to multiple switches (referred to as a virtual link aggregation or a multi-chassis trunk) to operate as a single logical link to facilitate load balancing among the multiple links/switches while providing redundancy. This ensures that a link failure, or a device failure for the case of a virtual link aggregation, would not affect the data flow. A switch participating in a virtual link aggregation can be referred to as a partner switch of the virtual link aggregation.
Currently, such link aggregations or virtual link aggregations in a network have not been able to provide efficient adaptive forwarding for different traffic flows. A traffic flow is often identified based on a source address, a destination address, and/or corresponding ports. If the packets of different traffic flows are forwarded via only a few specific links of the (virtual) link aggregation, while the other links remain underutilized, the (virtual) link aggregation may not be able to redistribute the packets to use the underutilized links. As a result, the packets become bottlenecked at those specific links and fail to utilize the bandwidth offered by the other links of the (virtual) link aggregation.
While link aggregation and virtual link aggregation bring many desirable features to networks, some issues remain unsolved in efficient adaptive forwarding.

Adaptive link aggregation and virtual link aggregation


A plurality of modules, each connected to communication lines, are interconnected by a logically separated interprocessor communication bus for transferring header information and control information and a frame transfer bus for transferring data. When each module receives data from a line, the module generates a header containing header information from the received data, stores the header and user data in respective queue-type data storage sections, and transmits the header on the interprocessor communication bus; when one of the other modules detects its own identification from the header on the bus, the module sends a data send request to the transmitting module which in response reads the data from the data storage and outputs it on the frame transfer bus for transmission to the requesting module.

1. Field of the Invention
The present invention relates to a data switching processing method and apparatus for performing the switching of data units such as packets, frames, cells, etc., with addressing information included therein.
2. Description of the Related Art
In data switching networks, such as packet switching networks, frame relay switching networks, or cell switching networks, processing for switching is performed with a data unit, such as a packet, frame, or cell, as a unit, each data unit consisting of variable-length or fixed-length data and a header containing data addressing information appended to the data.
According to a prior art switching method, in switching processing equipment also, data is unconditionally transferred from the entrance to the exit side of the switching equipment with the variable-length or fixed-length data unit as a unit and in accordance with the addressing information included therein. This increases the complexity of processing at both the entrance and the exit side. Furthermore, for a data unit containing an error, it will be sufficient to only transfer the header from the entrance to the exit side, but in the above method, the whole data unit has to be transferred, which has been a major obstacle to the improvement of throughput.
Moreover, since congestion processing (discarding of data units, etc., in the event of congestion) is usually not performed at the entrance side, a buffer with a sufficient capacity has to be provided at both the entrance and the exit side.

Data switching processing method and apparatus


The present invention provides a technique for, in the case in which a failure has occurred in a shared memory, controlling a period of a pseudo through operation to reduce a period in which performance of a disk array device falls. Control information is divided into management information, which is required to be duplexed, and directory information, which is only required to simplexed, and the management information and the directory information are stored in separate shared memories. In the case in which a failure has occurred in the shared memory of an expanded memory unit (Option) storing the directory information, the directory information is reestablished in the shared memory of a basic memory unit (Basic). The pseudo through operation is cancelled at the point when the directory information is reestablished. After a package of the expanded memory unit is replaced with a normal product, the directory information is reestablished again. Management information managed in the other cluster is copied to the shared memory of the basis memory unit to complete maintenance and recovery work.

1. Field of the Invention
The present invention relates to a disk array device and a maintenance method for the disk array device.
2. Description of the Related Art
A disk array device is established, for example, by arranging a large number of disk drives in array and on the basis of RAID (Redundant array of Independent Inexpensive Disks). A logical volume, which is a logical storage area, is formed on a physical storage area provided in each disk device. A host computer can read and write desired data by issuing a writing command or a reading command of a predetermined format to the disk array device.
Various preventive measures are applied to the disk array device in order to prevent loss or the like of data stored in the disk drives. One of the preventive measures is adoption of a RAID configuration. For example, the disk array device adopts a redundant storage configuration, which is known as RAID 1 to 6 or the like, whereby likelihood of data loss is reduced.
Moreover, duplexing of a physical configuration is also performed in the disk array device. For example, in the disk array device, duplexing is realized by providing plural principal parts such as host interface circuits, which perform data communication with a host computer, and subordinate interface circuits, which perform data communication with the respective disk drives. In addition, there are also provided plural paths for connecting the principal parts, respectively, plural power supplies for supplying power to the respective principal parts, and the like.
In addition, the conventional disk array device includes shared memories and cache memories such that control information is stored in the shared memories and data is stored in the cache memories (JP-A-2000-339101). In the conventional technique, both the shared memories and the cache memories are mounted in one memory package. Further, in order to supplement a cache capacity, cache memories are also mounted in a selector package.
User data, which has been requested by a host apparatus to be written in the disk drives but has not been written in the disk drives yet, is required to be stored in plural cache memories to be duplexed. This is for performing data guarantee. In addition, control information for controlling an operation or the like of the disk array device is also required to be duplexed from the viewpoint of securing redundancy. By duplexing the control information, even in the case in which one piece of control information becomes unavailable due to occurrence of a failure or the like, requests for reading and writing from the host apparatus can be processed on the basis of the other piece of control information.
However, with a configuration in which control memories storing control information and cache memories storing user data are provided in identical packages, in the case in which a failure occurs in a control memory or a cache memory, responsiveness declines during a period until maintenance and replacement work of an entire package, in which the failure has occurred, is completed.
In the case in which a writing request is received form the host apparatus in a normal state in which a failure has not occurred in both the packages, it is possible to inform the host apparatus of completion of writing at the point when data is stored in the cache memories. The data requested to be written is duplexed in the cache memories and guaranteed. Thus, no inconvenience is caused even if the host apparatus is informed of completion of writing before writing the data in the disk drives.
On the other hand, in the case in which entire one package is subjected to blocking processing, only the control memories and the cache memories mounted to the other package, which is operating normally, can be used. Therefore, in this case, since data cannot be guaranteed by duplexing, it is impossible to inform the host apparatus of completion of writing at the point when data requested to be written is stored in the single cache memory. Thus, in the case in which one of the packages is unavailable, the host apparatus is informed of completion of writing after the data requested to be written is written in the disk drives. This response operation is called, for example, a "pseudo through operation".
Even at the time of the pseudo through operation, the disk array device can continue operation normally. However, since response to the host apparatus is delayed, performance of the disk array device falls. The pseudo through operation continues throughout a period from the time when the package, in which a failure has occurred, is replaced until the time when necessary work is completed. Therefore, the pseudo through operation is performed over an entire period required for maintenance and recovery, and responsiveness of the disk array device falls.

Disk array device and maintenance method for disk array device


A visual display device is provided for delivering a generated image, preferably combinable with environment light, to the eye of a user. The device is lightweight and compact but yields a high quality image. In one embodiment, a color shutter provides a high-density color image. In one embodiment, a shroud protects from stray light and holds optical elements in desired alignment. In one embodiment an image generator is masked by at least two masks to provide for a high quality image without waste. In one embodiment, a removably mounted shield or activatable device can convert the apparatus from a see-through device to an immersion device and back again. In one embodiment, the device can be comfortably mounted to the user's head while still allowing for use of conventional eyeglasses. In one embodiment various controls, such as a mute button, volume control and the like can be provided, such as by mounting on the head-mounted display device.

It is often desirable to provide visual information to a living being. Frequently, one wishes to superimpose such visual information upon the being's view of the real world. In other applications, it is desired to shield the user from a view of the environment, providing an exclusive view of the visual information.
Such displays include a number of components including, in a form known as a folded catadioptric display, an image generator, a beam splitter which receives the image light from the image generator, often via a series of lenses and other optic elements and sends a fraction, designated the reflected fraction, of such image light to a reflective combiner that is either non-transmissive or both allows light from the real world to pass through such combiner and reflects the image light such that both the real-world light and the image light are transmitted to the eye of the user through the beam splitter, often via another series of lenses or other optical elements. The beam splitter will transmit a fraction, designated the transmitted fraction, of the image light reflected from the collimator-combiner. In embodiments in which the combiner is at least partially transmissive, a fraction of the real-world light is also transmitted by the beam splitter.
Previous devices included a number of additional components. Some devices have included corrective optical elements. Other devices have included a depixelator, e.g., as described in PCT/US94/01390 filed Feb. 7, 1994 for "Depixelated Visual Display" (incorporated herein by reference). Still other devices have included apparatus for intensifying the visual display such as those described in PCT/US94/01391, filed Feb. 7, 1994 for "Intensified Visual Display" (incorporated herein by reference).
In designing a system for providing a generated image to the eye or eyes of a user, various factors are often in opposition. Although it is desirable to provide an image which has high quality so as to not only provide a pleasing and attractive display for the user but also to reduce eyestrain, very often the techniques used to produce such a pleasing image have been contrary to goals of an apparatus which is lightweight, low-cost, and relatively easy to design, fabricate and/or repair. Many previous devices have required expensive and heavy series of optical elements such as lenses to achieve a desired picture quality. Other devices have simply accepted a lower-quality image in order to achieve goals of low-cost or light weight. For example, some previous devices have failed to provide a flat focal field to the user. Others have resulted in a poor image contrast, particularly at high viewing angles of the image. Many devices have deprived the user of the full image in order to mask-off unwanted light near the edge of an image generator.
Accordingly, it would be useful to provide a personal, visual display apparatus which provides a high quality of image, which is low cost, lightweight, comfortable and has increased ease of design, fabrication, repair and the like.


A method and a system of alerting patient with sleep disorder are provided. The method includes: detecting a change in a parameter(s), and if the change is detected, sounding an alarm, wherein the parameter(s) includes sound, motion, heartbeat, blood pressure, breathing frequency, magnitude and/or frequency of movement. The system includes a detector for detecting a change in a parameter(s) and an output device for sounding an alarm, wherein the parameter(s) comprise(s) sound, motion, heartbeat, blood pressure, breathing frequency, and/or magnitude and/or frequency of movement.

Patients with sleep disorder, such as rapid eye movement sleep behavior disorder (RBD) or sleep terror, have the potential to be injured or have disrupted sleep behavior, indicated by talking, laughing, shouting, gesturing, grabbing, flailing arms, punching, kicking, sitting up, and/or leaping from bed. Sometimes vigorous, violent episodes may occur.
For example, RBD is typically characterized by abnormal or disruptive behaviors emerging during the rapid eye movement (REM) sleep stage. Most people are paralyzed during this sleep period; however, RBD patients are not and therefore can act out their dreams. These actions can include shouting, kicking, running, etc., which may cause serious injury and/or harm to themselves, and/or disruptions to others nearby (e.g., sleep partners).
In contrast to sleep walking, patients with RBD can be easily woken up with even small noises. However, many RBD patients live alone, and may not be able to be alerted until injured by their movements.
The medical treatments for RBD (e.g., medications) are not always effective, and may also have undesirable side effects.
Also, for example, in patients with obstructive sleep apnea (OSA), the soft tissue in the back of the throat collapses and blocks the airway, which leads to partial reductions in breathing, commonly referred to as "hypopneas". This can lead to complete pauses in breathing, which are often referred to as "apneas." In children, these obstructions tend to occur during the rapid eye movement (REM) sleep stage. OSA may cause the patient to have low levels of oxygen in the blood. While adults with OSA may wake up easily after their breathing stops, children with OSA often do not wake up in response to pauses in breathing. OSA may lead to deformation of the chest, such as depression in the chest wall, abnormal sleep positions, and other health issues and/or behavior issues. For example, patients with OSA may suffer from high blood pressure, heart disease, stroke, pre-diabetes and diabetes, and depression.
As such, there is a need for helping patients with sleep disorder, such as RBD or OSA, to avoid harm or injury.

Method and system of alerting patient with sleep disorder


Apparatus and methods for consolidating granular silicon and determining trace elements content of the consolidated silicon are disclosed. Silicon granules are placed in a vessel, and a silicon slug of known purity is embedded at least partially in the granules. The slug is preheated to a temperature sufficient to couple with an induction heater. As the silicon slug melts, silicon granules adjacent the molten silicon also melt. The vessel passes through an induction coil to successively inductively heat and melt regions of the silicon granules from the leading end to the trailing end with each region solidifying as the molten silicon exits the induction coil to provide a multicrystalline silicon ingot. The multicrystalline silicon ingot is sliced into wafers, which are analyzed by low-temperature Fourier transform infrared spectroscopy to determine levels of trace elements in the ingot.

Granular silicon is used, for example, for making silicon ingots, which subsequently are sliced into silicon wafers. The granular silicon is required to have a very high purity. However, granular silicon presents technical challenges in the characterization of its material properties. These challenges increase the characterization cost, which in turn increases the production cost. For example, determining product variability is particularly challenging when dealing with very high purity materials, such as electronic-grade silicon. Present methods of characterizing granular material may not produce meaningful results and/or may be prohibitively expensive. Thus, there is a need for a reliable, relatively rapid, cost-effective method for characterizing granular silicon.

Method and apparatus for consolidation of granular silicon and measuring non-metals content


A photoelectric hybrid device includes an optical connector on a flat optical surface at one end of vertical optical waveguides for inputting and outputting an optical signal. Integration of the photoelectric hybrid device into an interposer or the like is standardized. The photoelectric hybrid device includes: conductive pins connected to an electric signal pathway for a photoelectric hybrid substrate; a translucent member having a flat optical surface and a translucent part; and self-organizing optical waveguides that form an optical path between the translucent part and an optical waveguide. The flat optical surface is not lower than the tops of the electrical connection parts on the conductive pins. Collision of the optical connector and the tops of the electrical connection parts can be avoided when an optical connector on which an optical waveguide that transmits an optical signal among the optical waveguides.

In recent years, in the connection between boards, between computers, between peripheral devices and so on, problems such as delay of signals, generation of heat, generation of EMI (electromagnetic noise) and so on due to electrical wiring are coming to surface. For solving these problems that occur in the electrical wiring, optical interconnection that uses silicon photonics techniques is being developed (refer to Non-patent-related Documents 1, 2, and 3). In this regard, it is interpreted that the silicon photonics means an optical device technique that uses silicon as a material, and that the optical interconnection means a technique for communicating signals by converting an electric signal from an external device to an optical signal and/or converting an optical signal to an electric signal, and transmitting the optical signal or the electric signal to another external device or the like. The optical interconnection is an innovative technique for eliminating problems relating to the electrical wiring, such as delay of a signal due to parasitic capacitance, deterioration of signal due to instable grounding, EMI radiation from an electrical line and so on. However, specifications of the constructions for inputting/outputting optical signals and electric signals and so on are often unique to the constructions respectively, that is, the specifications are not standardized.
For realizing the optical interconnection, some suggestions regarding a photoelectric hybrid device that mixedly loads optical circuits and electronic parts on a circuit board have been proposed (for example, refer to the "Background Art" section of Patent-related Document 1, FIG. 13 of Patent-related Document 2, etc.).
For example, regarding a device relating to a chip-type optical transceiver using a silicon photonics, a silicon photo-chip provided from Luxtera, that is installed on a printed circuit board (PCB) available from Molex, is available. The silicon photo-chip is an optical transceiver (refer to page 11 of Non-patent-related Document 3), and it is constructed in such a manner that an electric signal and an optical signal are to be inputted into and outputted from the upper surface of the chip. The silicon photo-chip of Luxtera and the PCB of Molex are electrically connected by wire-bonding; and optical fibers for communicating optical signals are directly adhered to the top part of a silicon CMOS chip by use of an epoxy resin (refer to Non-patent-related Document 2).
In prior art, as an elemental technology for fabricating a photoelectric hybrid device, a technique of a self-forming optical waveguide has been known. In the self-forming optical waveguide technique, by allowing light having a photosensitive wavelength for a photocurable resin to propagate through the resin, a part in the resin through which the light propagated is cured and made to be an optical waveguide core (for example, refer to Patent-related Document 2). An example implementation of a photoelectric hybrid device 29400, which may be fabricated by use of such a prior-art self-forming optical waveguide technique, is shown in FIG. 32. A photodetector 29450 is placed on a substrate 29410 in such a manner that the light receiving surface of the photodetector 29450 faces upward. An optical waveguide core 29420, which may be made of photocurable resin, is formed on the top part of the photodetector 29450 in such a manner that the optical waveguide core 29420 is vertical to the substrate 29410 and extends upwardly from the light receiving surface of the photodetector 29450. The part around the optical waveguide core 29420 is covered by a resin that acts as a clad layer 29430. A 45-degree mirror 29460 is placed above the upper end surface of the optical waveguide core 29420, and an optical fiber 29470 is placed at a position that is above the clad layer 29430 and beside the 45-degree mirror 29460. In such an implementation, an optical path of an optical signal that has been transmitted via the optical fiber 29470 is vertically bended by the 45-degree mirror 29460 toward the substrate 29410. As a result, the optical signal enters the optical waveguide core 29420 and propagates therethrough, and the photodetector 29450 receives the propagated optical signal.
FIGS. 33A and 33B illustrate an example of a method for fabricating the optical waveguide core 29420 formed of a photocurable resin (refer to FIG. 2 of Patent-related Document 2). First, a photocurable resin 29422 is supplied onto the substrate 29410 (the photodetector is not shown), and a mask 29510 for forming an optical waveguide core is placed on the photocurable resin 29422. The mask 29510 comprises a glass plate 29514 and a chrome film 29516 formed on one of the surfaces of the glass plate 29514 except for an area for an opening 29512. Next, the photocurable resin 29422 is irradiated by a light 29520 having a photosensitive wavelength for the photocurable resin 29422 (for example, UV light) via the mask 29510 (FIG. 33A). By the light passing through the opening 29512 and propagating through the photocurable resin, a part of the photocurable resin through which the light propagates is cured and the optical waveguide core 29420 is consequently formed (FIG. 33B). Next, an uncured portion of the photocurable resin 29422 is washed and removed by a developing solution. Further, a resin 29430 for a clad layer is filled in the space around the optical waveguide core 29420.

Photoelectric hybrid device and method for manufacturing same

PHOTONICS ELECTRONICS TECHNOLOGY  RESEARCH ASSOCIATION


A recording apparatus includes: edge guides which move in a width direction of the recording target medium and align side edges of the recording target medium which is stacked; a motor which moves the edge guides; a determining section which determines whether an electric current value when the motor is driven reaches a predetermined threshold value; and a position detecting section which detects a position of the edge guides in the width direction. Here, when the side edges of the recording target medium are aligned, the edge guides move close to the recording target medium and it is determined whether a difference between a position of the edge guides at the time when the electric current value reaches the predetermined threshold value and a position of the edge guides corresponding to the size of the recording target medium is equal to or smaller than a predetermined allowable value.

1. Technical Field
The present invention relates to a recording apparatus which includes a stacking section on which a recording target medium is stacked and edge guides which move in a width direction of the recording target medium and align side edges of the recording target medium stacked on the stacking section.
In this description, the recording apparatus includes an ink jet printer, a wire dot printer, a laser printer, a line printer, a copier, a facsimile or the like.
2. Related Art
As disclosed in JP-A-2002-128286, a recording apparatus in the related art includes feeding rollers which feed a recording paper which is an example of a recording target medium, and a hopper which can move close to or away from the feeding rollers and is a stacking section on which the recording paper is stacked. A pair of edge guides for guiding the recording paper in a width direction is installed in the hopper to be able to slide in the width direction. Accordingly, when a user sets the recording paper, the user firstly widens the edge guides in the width direction, and then stacks the recording paper on the hopper. Then, the user slides the edge guides in a narrowing direction to align opposite side edges of the recording paper. As a result, the recording paper can be fed in a stable posture.
However, the user should slide the edge guides to a predetermined position in a manual manner. Thus, in a case where the user does not perform the manual manipulation, it is likely that the posture of the recording paper which is being fed becomes inclined. Further, it is likely that the opposite side edges of the plurality of recording papers which is stacked on the hopper are not aligned. In these cases, variation may be generated in the position of the recording paper in the width direction, and thus, variation may be generated in a recording position with respect to the recording paper. As a result, desired recording may not be obtained.


There is provided a semiconductor test apparatus which assuredly detects an inhibited edge only which affects a test pattern and truly requires an error warning. This semiconductor test apparatus includes: a real time selector which receives a plurality of sets of waveform data, receives a plurality of sets of timing data, selects and outputs predetermined waveform data and timing data, inhibits a next edge immediately following the current edge and outputs an inhibiting signal when an edge with the same polarity which is continuous in an interval shorter than a proximity limit time exists in the waveform data; and a detector which receives the waveform data, the timing data and the open signal, and outputs fail signal when an edge with a polarity reverse to that of an inhibited edge exists in the proximity limit time before the inhibited edge.

In a semiconductor test apparatus which tests a semiconductor component such as an IC or an LSI as a device under test (DUT), a predetermined test pattern is applied to the DUT, an output signal which is output from the DUT as a result of test pattern application is fetched with a timing of a predetermined strobe signal, and the fetched output signal is compared with a predetermined expected signal (an expected pattern) to determine the quality of an operation of the DUT (see, e.g., Japanese Patent Application Laid-open No. 110357-1995: pp. 4–6, FIG. 1, Japanese Patent Application Laid-open No. 174827-1995: pp. 4–5, FIG. 1, and Japanese Patent Application Laid-open No. 062292-1996: pp. 3–4, FIG. 1).
Test pattern data applied to the DUT comprises waveform data (format control data) indicative of a waveform corresponding to a logical pattern and timing data (timing set data) indicative of a timing of an edge in this waveform, arbitrary waveform data and timing data are selected from a plurality of sets of waveform data and timing data, thereby generating a desired test pattern.
Here, in order to highly accurately evaluate characteristics of the DUT, generation of a test pattern with a highly accurate timing is demanded in recent semiconductor test apparatuses, and it is often the case that a timing set in the test pattern (a delay time of an edge with respect to a predetermined reference of a test cycle) is a sum of an integral multiple of a reference clock (Reference Clock: REFCLK) and a fraction or only an integral multiple of the reference clock. Therefore, timing data (delay data) indicative of an edge timing of waveform data is also constituted by a combination of integral multiple data (Gate Enable: GTE) of a reference clock cycle and high resolution data (High Resolution: HR) as fractional data of the reference clock.
Further, in recent semiconductor test apparatuses, combinations of a plurality of sets of waveform data are usually utilized so that further complicated test patterns can be generated.
For example, a plurality of groups (a group of set signals: T1S, T2S . . . TnS, a group of reset signals: T1R, T2R . . . T2R) are prepared as waveform data, and a timing pulse is generated by arbitrarily combining the set signals and the reset signals.
Further, such set signals and reset signals are supplied to a flip-flop, and a rising edge or a falling edge of a test pattern is formed.
FIG. 6 is a block diagram showing a schematic structure of a conventional semiconductor test apparatus.
As shown in this drawing, the conventional semiconductor test apparatus comprises a pattern generator (PG) 110, timing generators 120, a waveform memory 130, a real time selector 140 and others, a plurality of sets of waveform data output from the waveform memory 130 and a plurality of sets of timing data output from the timing generator are selected by the real time selector 140, and a test pattern input to a DUT (not shown) as a device under test is generated.
Of these components, the waveform memory 130 and elements on the next stage constitute a waveform formatter circuit.
It is to be noted that the semiconductor test apparatus shown in FIG. 6 is a pin multiplex mode tester using two sets of data in one test cycle, waveform data of groups T1 and T2 are generated from the waveform memory 130, and two timing generators 120 of T1 and T2 are provided in accordance with the groups of the waveform data from the waveform memory 130.
The pin multiplex mode is a mode in which a high-speed test signal or strobe signal is generated by combining (multiplexing) test patterns or strobe signals generated from a plurality of test channels (tester pins) of the semiconductor test apparatus on a time base.
The PG 110 outputs pattern data (PAT A/B/C) which becomes an address of a logical pattern (waveform data) which is applied to a DUT, a timing set (TS) which becomes an address of timing data indicative of a switching timing for the pattern data, and a rate signal which serves as a test rate.
The plurality of timing generators 120 are provided in accordance with the groups of the waveform data from the waveform memory 130, the two timing generators of T1 and T2 are provided in the example shown in FIG. 6, and each timing generator 120 comprises a timing memory 121 and a counter delay 122.
The timing memory 121 stores a delay timing of a clock with respect to a timing set, and generates a set time and a reset time of waveform data read from the waveform memory 130.
Specifically, the timing memory 121 stores a GATE signal used to select any clock of reference clocks REFCLK and an HR signal which is high-resolution delay data which is not more than a cycle of this REFCLK, and the reference clock REFCLK corresponds to 4 ns in the example shown in FIG. 6.
Further, the GATE signal and the HR signal are read with a timing set (TS) output from the PG 110 being used as an address, the HR signal is input to a real time selector 140 on the next stage as it is, and the GATE signal is output with a timing of a rate signal (RATE) input to the counter delay 122 and then input to the real time selector 140.
The waveform memory 130 stores waveform data (a SET/RES beat) corresponding to a logical pattern. Furthermore, respective waveform data of a set time and a reset time are read from the waveform memory 130 with pattern data (PAT A/B/C) output from the PG 110 being used as addresses.
In the waveform memory 130 shown in FIG. 6, respective waveform data of a set time and a reset time of pattern data in two groups (T1, T2) are output and then input to the real time selector 140 on the next stage.
The waveform memory 130 has, e.g., eight words, and a word is specified by three bits (A/B/C) of the pattern data (PAT). Data such as driver high-level drive first data T1S, driver low-level drive first data T1R, driver high-level drive second data T2S and driver low-level drive second data T2R is read every time each word is read.
It is to be noted that, as to a storage content of this waveform memory 130, it differs depending on a type of waveform to be generated, i.e., whether a non-return waveform NRZ, its inverse waveform/NRZ, a return waveform RZ, its inverse waveform/RZ, an exclusive OR waveform XOR, its inverse waveform/XOR and others, and a waveform is formed in accordance with the storage content.
The real time selector 140 receives respective signals from the timing generator 120 and the waveform memory 130 on a set side (SET) and a reset side (RES), selects arbitrary data in real time, and outputs the selected data as a set signal (SET) and a reset signal (RES).
The set signal (SET) and the reset signal (RES) output from the real time selector 140 are distributed to a set side and a reset side of a timing circuit (Pin Timing Generator: PTGA) 160 on the next stage. In the example shown in FIG. 6, an upper timing circuit (PTGA) 160a is a set signal passage (path) and a lower timing circuit (PTGA) 160b is a reset signal passage (path).
Moreover, the set signal and the reset signal are supplied to a flip flop 170, and a rising edge or a falling edge of a test signal are formed based on timings of these signals.
In the semiconductor test apparatus having the above-described structure, when a pattern is started, signals from the PG 110 access the waveform memory 130 and the timing memory 121, and outputs from these members are input to the real time selector 140.
Specifically, when a pattern is started, timing data TS and a rate signal RATE are supplied to the timing memory 121 and the counter delay 122 from the PG 110, and a delay quantity HR and a reference timing GTE read from the timing memory 121 are output.
Additionally, waveform data is read from the waveform memory 130 by using pattern data PAT from the PG 110, input to the real time selector 140 with a timing of the reference timing GTE, and selected and output with a delay timing of the delay quantity HR.
Further, this data is applied to a non-illustrated DUT through the timing circuit (PTGA) 160 and the flip flop 170.
Meanwhile, generally, in the semiconductor test apparatus, an interval between signals which are supplied to the same signal passage must be larger than that of a reference clock. For example, each of an interval between two set signals in the signal passage on the set side 160a of the timing circuit (PTGA) 160 and an interval between two reset signals in the signal passage on the reset side 160b of the same shown in FIG. 6 must be larger than a reference clock cycle. That is because each functional element, each circuit or the like is configured to operate in synchronization with a reference clock in the semiconductor test apparatus, a signal having a smaller cycle than the cycle of the reference clock cannot be recognized, and such a signal cannot be correctly transmitted.
As described above, in the semiconductor test apparatus, when a high-speed pulse exceeding a limit of the reference clock REFCLK is applied, a normal operation cannot be carried out. Here, within the context of the background art and the present invention, such a limit is referred to as a "proximity limit". Typically, a proximity limit time is a time length of one cycle of the reference clock.
Therefore, when HR signals each indicating a delay timing of a high resolution are continuously applied in a cycle not longer than that of the reference clock REFCLK, the PTGA cannot differentiate and recognize the second pulse, and it responds to a smaller HR signal as though one continuous pulse were applied.
Thus, in the prior art, a signal which conflicts with a proximity limit of a clock of the PTGA 160 on the later stage is eliminated in advance so that such a signal cannot be output in the real time selector 140 (see, e.g., Japanese Patent Application Laid-open No. 094722-1996: pp. 2–3, FIG. 1, and Japanese Patent Application Laid-open No. 228721–2002: pp. 4–5, FIG. 1)
Specifically, if the same reference clock cycle has one waveform data edge, the real time selector 140 selects and outputs this edge and the corresponding timing data. If the same reference clock cycle has a plurality of waveform data edges, the real time selector 140 compares the sets of timing data associated with the respective edges, and selects and outputs an edge having small timing data and this timing data. Furthermore, as to edge data having large timing data, the real time selector 40 opens (inhibits) this edge data so that this data cannot be output. It should be noted that within the context of the background art and the present invention, a term "open" is used for describing a situation where a signal or data is inhibited or prohibited to be transmitted to later stages.
Based on this, in any case, a signal which is proximate to or exceeds the proximity limit time derived from a reference clock cycle (e.g., 4 ns) is not input to the PTGA.
A concrete example of a test pattern generated in the conventional semiconductor test apparatus will now be described with reference to FIG. 7.
FIG. 7 shows a timing chart of a test pattern generated in the above-described conventional semiconductor test apparatus. In the example shown in this drawing, a reference clock REFCLK is 4 ns, and a test rate RATE is set to 4 ns which is the same as the reference clock.
It is to be noted that the reference clock REFCLK remains unchanged (fixed) by its semiconductor test apparatus, but the test rate RATE can be set to a desired cycle which is an integral multiple of the reference clock REFCLK, and this setting can be arbitrarily performed by a user or the like.
As shown in this drawing, respective sets of waveform data T1S, T1R, T2S and T2R are input to the set side (SET) and the reset side (RES) of the real time selector 140 with a timing of the reference timing GTE. Moreover, delay timing data T1HR and T2HR corresponding to the respective sets of waveform data T1 and T2 are input to the set side (SET) and the reset (RES) side of the real time selector 140.
In the real time selector 140, if the same reference clock cycle has one waveform data edge, this edge and corresponding timing data are selected and output. If the same reference clock cycle has a plurality of waveform data edges, respective sets of timing data corresponding to the respective edges are compared with each other, and an edge having small timing data and this timing data are selected and output.
Additionally, as to an edge having large timing data, this edge data is opened so that it cannot be output.
In the example shown in FIG. 7, in the first cycle of the reference clock cycle, since the SET signal is T1S only, T1S is selected, and the SET signal is output with a delay timing of 0.5 ns indicated by T1HR.
In the second cycle of the reference clock cycle, since the RES signal is T1R only, T1R is selected, and the RES signal is output with a delay timing of 1.0 ns indicated by T1HR.
In the third cycle of the reference clock cycle, since both T1S nd T2S exist as the set signal, values of the delay timing data T1HR (0.5 ns) and T2HR (3.0 ns) corresponding to the respective sets of waveform data are compared with each other, T1S having a smaller value is selected, and the SET signal is output with a delay timing of 0.5 ns indicated by T1HR. In this third cycle, T2S having large delay timing data is opened and erased (see SET 3.0 indicated by an upward broken arrow in FIG. 7), and it is not output from the real time selector 140. In other words, the set signal (edge) T2S is inhibited to be transferred to the later stages.
Thereafter, the waveform data and the timing data are likewise selected in accordance with each cycle, and the set signal (SET) and the reset signal (RESET) such as shown in FIG. 7 are output from the real time selector 140. Further, these set signal and reset signal are supplied to the timing circuit (PTGA) 160 and the flip flop 170, and a test pattern (PAT) having such a rising edge or falling edge as shown in the lowermost column in FIG. 7 is generated.
In this manner, by opening (inhibiting) a clock which conflicts with a proximity limit in the real time selector 140, namely, a clock which is proximate to or exceeds a reference clock cycle (e.g., 4 ns) is not input to the PTGA on the later stage, and hence the semiconductor test can be accurately conducted based on the reference clock.
In the above-described conventional semiconductor test apparatus, however, data of an edge timing which conflicts with the limit is opened and erased by the proximity limit of the clock, which results in a problem that an output waveform varies due to opening the edge when the timing setting is changed by a user.
For example, as shown in FIG. 8(a), it is assumed that the set signal and the reset signal are output with a timing which does not conflict with the proximity limit. In this case, it is assumed that the timing setting is changed by a user or the like so that a delay timing of SET=1.0 ns of the first cycle shown in FIG. 8(a) is changed to SET=2.0 ns.
Then, as shown in FIG. 8(b), since SET=2.0 ns of the second cycle conflicts with the proximity limit of 4 ns with respect to SET=2.0 ns of the first cycle, SET=2.0 ns of the second cycle is opened. As a result, an output waveform is changed to a waveform which is different from the correct waveform shown in FIG. 8(a).
Even in such a case, however, if an edge of RES=3.0 ns does not exist before the opened edge shown in FIG. 8(b), the subsequent output waveform is not changed even if SET=2.0 ns of the second cycle is opened.
As described above, when a given edge conflicts with the proximity limit of the clock and is thereby opened, there are a case where the subsequent output waveform is changed due to this opening and another case where the output waveform is not changed and hence there is actually no impact.
In the conventional semiconductor test apparatus, however, when the clock is opened, the fact that the clock is opened can be detected. However, the conventional apparatus cannot detect a difference between opening which affects the above-described output waveform and opening which does not affect the same.
Therefore, there is a problem that opening of the edge which is truly required for correct waveform generation cannot be accurately detected.

Format control circuit and semiconductor test device