A method of manufacturing a semiconductor device to prevent uneven polysilicon gate dopant accumulation at the gate/gate oxide interface. A layer of gate oxide is formed on the surface of the silicon substrate, a layer of amorphous silicon is deposited on the gate oxide and a doped layer of amorphous silicon is deposited on the first layer. The first and second layers are deposited by chemical vapor deposition and an oxygen containing gas is selectively injected into the stream of silicon source gas depositing the first and second layers of amorphous silicon.

1. Field of the Invention
This invention relates generally to the manufacture of high performance semiconductor devices and, more particularly, to the manufacture of high performance submicron semiconductor devices and, even more particularly, to a method for the manufacture of high performance submicron semiconductor devices to minimize dopant accumulation at the polysilicon-tunnel oxide interface.
2. Discussion of the Related Art
The semiconductor industry is characterized by the dual requirements of an increase in the speed of integrated circuits and an increase in the speed of integrated circuits and an increase in the density of elements in integrated circuits. Thus, these two requirements have become the two major goals of MOSFET scaling. Increasing the density of elements means, primarily, that smaller channel lengths and widths have to be used. Increasing the speed of integrated circuits means, primarily, that the MOSFET saturation drain current I.sub.DSAT must be increased to allow faster charging and discharging of parasitic capacitances. Existing performance models for MOSFETs predicted that a decrease in either the channel length, L, or the gate oxide thickness, t.sub.ox, would increase I.sub.DSAT. However, as device were scaled below approximately 2 microns, "short-channel" effects were observed that were not predicted by the existing performance models which were then referred to as "long channel" models. For example, one of the short channel effects that was not predicted by the long channel model was that I.sub.DSAT becomes independent of channel length in extremely small MOSFETs and approaches a constant value regardless of any decrease in the channel length. It was also found that decreasing the gate oxide thickness, t.sub.ox, provided a much greater increase in I.sub.DSAT than a concomitant decrease in channel length, L. However, a thinner gate oxide thickness, t.sub.ox, will cause I.sub.DSAT to increase faster to the constant value as the channel length, L, is decreased. Therefore, decreasing the gate thickness, t.sub.ox, results in an increase in I.sub.DSAT in two ways and, therefore, it was determined that it is more advantageous to concentrate on methods to decrease gate oxide thickness rather than on methods to decrease channel length.
As device dimensions continued to decrease, it was discovered that other short-channel effects needed to be addressed. All of the short-channel effects were placed into the following two general categories: (1) the problem of increased leakage current when the MOSFET is off and (2) reliability problems associated with short-channel and thin gate oxide device structures.
The reliability problems that arise in short-channel and thin gate oxide MOSFETs include: (1) thin gate oxide breakdown; (2) device degradation due to hot-carrier effects; and (3) reliability problems associated with interconnects between MOSFETs. The problems that are of interest are the phenomena of thin gate oxide breakdown and the phenomena of device degradation due to contamination of the gate/gate oxide region, and more specifically, the gate/gate oxide interface.
The characteristics of the Si--SiO.sub.2 interface in a MOSFET determine, to a significant extent, the functioning of the gate dielectric. Similarly, the interface between the polysilicon gate and the gate oxide determine, to a significant extent, the functioning of the gate dielectric. A study of the structure of the gate/gate oxide interface has resulted in the identification of device degradation effects caused by the accumulation of dopant atoms at the gate/gate oxide interface. In addition, because of defects or faults that exist in prior art devices that are exacerbated by the conventional method of growing a polysilicon. The trend in the semiconductor industry has been to deposit a layer of amorphous silicon in an attempt to obtain conformality of the gate layer over the faults that exist at the gate/gate oxide interface. FIG. 8 illustrates a conventional method of forming a layer of amorphous silicon 802 on the layer of gate oxide 702. A stream of silane, indicated by arrows 800 is directed towards the gate oxide layer 702. A dopant is injected into the silane stream to dope, in situ, the amorphous silicon. As is known in the art, the device is later annealed at a temperature to form polysilicon from the amorphous silicon layer. One such dopant is phosphene which provides phosphorous atoms as the dopant material in the gate. Because the gates have become ultrathin for reasons discussed above, the control of the doping concentrations at various depths in the gate have become very difficult. The ultrathin gates, gate oxide layers, and other elements in the semiconductor device have made problems associated with contaminants more apparent and have made semiconductor devices more susceptible to degradation and failure because of contamination levels that were acceptable in prior devices. The conventional method shown in FIG. 8 introduced phosphene in a concentration to "lightly" dope the amorphous silicon gate material because more than a "lightly" doped material would cause uneven accumulation in an anneal step or a post anneal process. The difficultly of controlling the concentration is primarily due to the fact that the gate is scaled to submicron levels. However, the "lightly" doped gate region has resulted in a P depletion effect in the gate which will affect operating parameters of the device. In memory devices, a high concentration of P degrades the gate oxide and cause devices, such as memory devices, particularly flash memory devices to degrade and fail.
What is needed is a method of manufacturing a semiconductor device that has a properly doped gate without having unwanted dopant concentrations at the gate/gate oxide interface.

Oxygen-doped in-situ doped amorphous silicon multilayer gate structures


A glass fiber capable of withstanding temperatures in excess of 1900.degree. F. is produced by treating a glass, preferably E-glass, fiber. The glass fiber is first leached with selected acids, and then the leached fiber is treated with organo-metallic materials of low viscosity, such as a dispersion of low molecular weight water-in-oil emulsion of dimethyl polysiloxane. The fiber is used in such applications as embedding it in a fire-resistant active coating material or embedding it into one surface of a polyolefin or composite plastic, such as a polypropylene sheet. The treated fiberglass can be used as a sole component or in concert with a fire-resistant or fire retardant material to further enhance its fire-resistant properties.

This invention relates to a glass form, preferably a fiber, which resists high temperatures, at least 1900.degree. F. and higher, while retaining at least some of its tensile strength and other physical properties.
In numerous applications, fabrics are utilized in systems which resist high temperatures. An example of the use of such fabrics is in reinforced coating systems. In these systems, the fabric is embedded in a char-forming, fire-resistive coating such as those described in Deogon, U.S. Pat. No. 5,591,791. Briefly, such coatings include ablative coatings, which swell to less than twice their original thickness when exposed to fire or other thermal extremes, intumescent coatings such as those disclosed in Nielsen et al., U.S. Pat. No. 2,680,077, Kaplan, U.S. Pat. No. 3,284,216, or Ward et al., U.S. Pat. No. 4,529,467, which swell to produce a char more than five times the original thickness of the coating, and subliming char-forming coatings of the type disclosed in Feldman, U.S. Pat. No. 3,849,178, which undergo an endothermic phase change and expand two to five times their original thickness to form a continuous porosity matrix. The intumescent and subliming coatings are denoted "active" thermal protective coatings.
The time required for a given temperature rise across a predetermined thickness of the composition, under specified heat flux, environmental, and temperature conditions, is a measure of the composition's effectiveness in providing thermal protection to an underlying substrate.
Eventually, the char is consumed by physical erosion and by chemical processes, such as oxidation by oxygen in the air and by free radicals produced by the coating or otherwise in a fire environment, and protection is substantially reduced. Before the char is totally consumed, degradation of the char layer leaves it crumbled and without the necessary strength to sustain itself, causing it to fail by being blown off or simply falling off (spalling).
Some of these chars degrade rapidly during exposure to high temperature, high heat flux environments. In the case of coatings which swell when exposed to thermal extremes, the degradations are usually in the form of fissures which are formed in the char as a result of differential thermal stresses produced by the high thermal gradients with them, and differential thermal expansion between the virgin material and the char.
To increase the strength of char layers during exposure to thermal extremes, and to limit spalling and fissures, fabrics have long been incorporated in the coating materials. As set out in Feldman et al., U.S. Pat. No. 5,622,774, fiberglass fabric provides an inexpensive, easy to install, reinforcement in many high temperature applications. In certain applications, however, such as coatings which may be exposed to high velocity petroleum fires or to high-temperature, high heat flux fires which will raise the fabric to temperatures above the softening point of the glass (around 1600.degree. F.), the fiberglass fabric has disintegrated. Other fabrics have therefore been required. Graphite cloth, as taught in the foregoing Feldman et al. U.S. Pat. No. 5,622,774 and in Kobayashi et al., U.S. Pat. No. 5,401,793, is very expensive. Refractory materials, such as quartz (Refrasil) fabric is also expensive. Metal mesh is inexpensive but it is heavy and difficult to install, particularly because it generally requires welding metal studs to the substrate to be protected.
Other examples of fabric-reinforced systems are laminates in which the fabric is embedded directly in a structural resin material itself, for example in the structure of a furnace or a rocket nozzle. Generally, these materials also produce a char when exposed to sufficiently high temperatures, although in many applications they are routinely exposed to high temperatures below their char-forming temperature for extended periods. In other applications they are exposed for short periods to temperature, heat flux, and environmental conditions which do not cause a char to form, but which are sufficiently high to cause serious loss of structural properties. Examples of these latter systems are automobile gasoline tanks and trunks, which can be made of plastic material if they can pass a test involving preventing structural failure (such as drop through or explosion in the case of a gasoline tank) when the tank or trunk is placed over a fire of a specified temperature and intensity for a predetermined period such as two minutes. In all of these conditions, a fabric which resists complete degradation under the foregoing conditions can provide sufficient structural integrity to impede failure of the system.
Attempts have been made for many years to produce a glass fiber which retains a substantial portion of its mechanical properties even when subjected to very high temperatures, greater than 1600.degree. F. (871.degree. C.), and preferably on the order of 1900.degree. to 2000.degree. F. (1038.degree. to 1093.degree. C.). Examples are Nordberg, U.S. Pat. No. 2,461,841, Parker et al., U.S. Pat. No. 2,491,761, and Leeg et al., U.S. Pat. No. 2,992,960. These patents all involve leaching of the glass fiber with mineral acid, followed by treatment with a sizing material. Heretofore, such attempts have failed to provide a reliable, reproducible, and efficient process of converting commercial grade fiberglass (such as Type E and Type F glass fibers) into a material capable of withstanding elevated temperatures and aerodynamic shear which may be coupled with elevated temperatures.

Method of making high-temperature glass fiber and thermal protective structures


Embodiments of the present invention provide methods, computer program products, and systems for adapting digital content. Embodiments of the present invention can be used to identify one or more entities in media content. Embodiments of the present invention can determine that an identified entity of the one more identified entities is associated with sensitive material. Embodiments of the present invention can, in response to determining that the identified entity of the one or more identified entities is sensitive, determine a contextual impact of the identified entity. Embodiments of the present invention can also be used to modify the media content based on the determined contextual impact of the identified entity.

The present invention relates generally to the wearable technology, and more particularly to content modification of media displayed on a wearable device.
In general, social media refers to interactive computer-mediated technologies that facilitate the creation and sharing of information, ideas, career interests and other forms of expression via virtual communities and networks. Typically, users can access social media via interactive Web 2.0 Internet-based applications. Examples of content that can be found on social include user-generated content, such as text posts or comments, digital photos or videos, and data generated through all online interactions.
Wearable technology, wearables, typically refer to one or more smart electronic devices (e.g., electronic device with micro-controllers) that can be incorporated into clothing or worn on the body as implants or accessories. For example, wearable devices such as activity trackers that enable objects to exchange data through the internet with a manufacturer, operator, and/or other connected devices, without requiring human intervention. Wearable technology has a variety of applications and is prominent in consumer electronics with the popularization of smartwatches and activity trackers.


Programming non-volatile memory includes applying a series of programming pulses to the memory cells as part of a coarse/fine programming process. Between programming pulses, memory cells in the coarse phase are verified for a coarse phase verify level for a target data state and memory cells in the fine phase are verified for a fine phase verify level for the target data state, both in response to a single reference voltage applied on a common word line. For a memory cell in the coarse phase that has been verified to have reached the coarse phase verify level, the memory cell will be temporarily inhibited from programming for a next programming pulse and switched to the fine phase. For a memory cell in the fine phase that has been verified to have reached the fine phase verify level, the memory cell will be inhibited from further programming.

Semiconductor memory is widely used in various electronic devices such as cellular telephones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, and non-mobile computing devices. Semiconductor memory may comprise non-volatile memory or volatile memory. A non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a source of power (e.g., a battery). Examples of non-volatile memory include flash memory (e.g., NAND-type and NOR-type flash memory) and Electrically Erasable Programmable Read-Only Memory (EEPROM).
A charge-trapping material can be used in non-volatile memory devices to store a charge which can correlate to a data state. The charge-trapping material can be arranged vertically in a three-dimensional (3D) stacked memory structure. One example of a 3D memory structure is the Bit Cost Scalable (BiCS) architecture which comprises a stack of alternating conductive and dielectric layers. A memory hole is formed in the stack and a NAND string is then formed by filling the memory hole with materials including a charge-trapping layer to create a vertical column of memory cells. Control gates of the memory cells are provided by the conductive layers. The threshold voltage (Vt) of the memory is controlled by the amount of charge that is retained in the charge-trapping material. That is, the minimum amount of voltage that must be applied to the control gate before the memory cell is turned on to permit conduction between its source and drain is controlled by the level of charge retained in the charge-trapping material. As such, the threshold voltage is used to an indicator of the data being stored by a memory cell.
Some non-volatile memory devices are used to store two ranges of charges and, therefore, the memory cell can be programmed/erased between two ranges of threshold voltages that correspond to two data states: an erased state (e.g., data "1") and a programmed state (e.g., data "0"). Such a device is referred to as a binary or two-state device.
A multi-state (or multi-level) non-volatile memory is implemented by identifying multiple, distinct allowed ranges of threshold voltages. Each distinct range of threshold voltages corresponds to a data state assigned a predetermined value for the set of data bits. The specific relationship between the data programmed into the memory cell and the ranges of threshold voltages depends upon the data encoding scheme adopted for the memory cells. For example, U.S. Pat. No. 6,222,762 and U.S. Patent Application Publication No. 2004/0255090 both describe various data encoding schemes for multi-state flash memory cells. While multi-state non-volatile memory can store more data than binary non-volatile memory, the process for programming and verifying the programming can take longer for multi-state non-volatile memory.

Non-volatile memory with two phased programming


An apparatus and method for managing a satellite service resource is provided. The method may include measuring, using a communication system monitoring unit, at least one satellite service signal being received for at least one satellite service, calculating, using a service resource management unit, an optimum frequency and an optimum output power for the at least one satellite service through analysis of a satellite service resource, allocating the calculated frequency and the calculated output power to the at least one satellite service, and transmitting the allocated information to the communication system monitoring unit, and comparing, using the communication system monitoring unit, the measured information to the allocated information, and transmitting a result of the comparison to the service resource management unit.

1. Field of the Invention
Exemplary embodiments relate to an apparatus and method for managing a satellite communication and broadcasting service resource.
2. Description of the Related Art
A satellite service resource management system assigns and manages a satellite communication and broadcasting service resource. With the launch of a satellite, various types of satellite communication and broadcasting services are in demand. However, the limited frequency and output power of a satellite transponder makes acceptance of all services difficult, and performing adjustment between services is required.
The satellite service resource management system allows the satellite transponder to operate in an optimum condition through efficient management of the satellite service resource.
For optimum operation of the satellite transponder, the satellite service resource management system allocates optimum frequency and output power for a satellite service in demand, monitors the satellite service for a frequency, an output power, and a service life while being run, and when a violation of permitted conditions is detected, suitable action is taken.

Apparatus and method for managing satellite service resource

ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE


A contact housing for an electrical plug connector, having multiple contact chambers for receiving a respective contact body insertable through a placement opening into the contact chamber having, a respective elastically deflectable latching arm, protruding laterally into the contact chamber, for primary latching of the contact body inserted to its end position into the contact chamber, and having a respective locking element, displaceably guided transversely to the insertion direction of the contact body, that in its locked position protrudes, with a first locking projection, laterally into the contact chamber for secondary locking of the contact body latched in primary fashion therein. Provision is made that the locking element has a second locking projection that, in the locked position of the locking element, blocks the latching arm against deflection out of its position protruding into the contact chamber.

Contact systems in which the individual contacts in a first working step come to a stop against the electrical leads, and in a second working step are latched into the contact chambers of the plug, are used at present in the automotive sector in electrical plug connectors. So-called clean-body contacts, among others, are used in this context. In these contact systems, elements of the contact chambers deflect into recesses or undercuts of the contacts and thereby provide primary latching of the contacts. In multi-part contact chamber systems, two primary latching types for clean-body contacts are known. In both cases the latching arms, with their latching hooklets, usually emerge as injection-molded parts from the lower part of the contact carrier as parts of the contact chamber walls. The first latching type is characterized in that the latching arm is attached to the contact chamber wall at the level of the contact shoulder, and the latching hooklet engages into a contact undercut in the vicinity of the contact opening. The latching arm grows out, so to speak, in the insertion direction, and when retained is loaded substantially axially in compression. The second latching type is characterized in that the latching arm is attached to the contact chamber wall at the level of the contact opening, and the latching hooklet engages over the contact shoulder or into a corresponding opening in the vicinity of the contact shoulder. The latching arm grows out, so to speak, opposite to the insertion direction, and when retained is loaded substantially axially in tension. In order to enhance functional reliability, customers are now requiring correct primary latching of the latching hooklets to be ensured by the fact that after assembly of the contact, the position of the latching arms is tested. For the first latching type, so-called spacer elements made of plastic, which are inserted from the plug face between the backs of the latching arms and the wall located therebehind, are already known. If a latching arm is not in the correct location, for example because it is not completely snapped into the contact, the spacer element is blocked and the placement state of the contact must be checked. When the spacer element is completely inserted, it prevents (usually unmonitored) reopening of the primary latch, thereby securing the position of the latching arm.
A general disadvantage of such spacer elements is that an additional part is required in the plug connectors in order to check the primary latching hooks, which means additional cost for the connection as a whole. For the second latching type, no comparable spacer systems that allow the position of the latching arms to be tested and secured are known at present.
In the contact chambers of plug connectors having a large number of pins, the contacts that have been latched in primary fashion are usually additionally checked, by way of a so-called secondary locking system, in terms of their correct position in the contact chamber, and are additionally secured at their correct insertion depth upon failure of the primary latching system. Plug connectors having many pins utilize, in many cases, so-called preassembled and transversely displaceable secondary locking plates that, in a clear position, initially permit unimpeded placement of the contacts into the contact chamber and then, at the end of the placement operation, are shifted at least one-half contact-chamber width transversely to the contact-chamber axes. With their locking contours protruding laterally into the contact chambers, the secondary locking plates on the one hand test for the correct insertion depth of the contacts, and on the other hand ensure additional locking.

Contact housing for an electrical plug connector


A data storage architecture is composed of an array of a flash memory solid state disk and a hard disk drive or any nonvolatile random access storage that are intelligently coupled by an intelligent processing unit such as a multi-core graphic processing unit. The solid state disk stores seldom-changed and mostly read reference data blocks while the hard disk drive stores compressed deltas between currently accessed I/O blocks and their corresponding reference blocks in the solid state disk so that random writes are not performed on the solid state disk during online I/O operations. The solid state disk and hard disk drive are controlled by the intelligent processing unit, which carries out high speed computations including similarity detection and delta compression/decompression. The architecture exploits the fast read performance of solid state disks and the high speed computation of graphic processing units to replace mechanical operations on hard disk drives while avoiding slow and wearing solid state drive writes.

While data storage capacity and central processing unit (CPU) processing power have experienced rapid growth in the past, improvement in data bandwidth and access times of disk input/output (I/O) systems have not kept pace. As a result, there is an ever-widening speed gap between CPU and disk I/O systems. Disk arrays can improve overall I/O throughput but random access latency is still very high because of mechanical operations involved. Large buffers and deep cache hierarchy can improve latency but the access time reduction has been very limited so far because of poor data locality at the disk I/O level.
Recent developments of flash memory-based solid state drives (SSD) have been very promising with rapid increase in capacity and decrease in cost. Because an SSD is on a semi-conductor chip it provides great advantages in terms of high-speed random reads, low power consumption, compact size, and shock resistance. Researchers in both academia and industry have been very enthusiastic in adopting this technology.
However, most existing research on SSDs focuses either on using an SSD in largely the same way as a hard disk drive (HDD), with various management algorithms at files system level and device level, or using an SSD as an additional cache in the storage hierarchy. The physical properties of SSDs impose constraints on both approaches that limit significant advances in the speed and reliability of disk I/O systems.
The limitations of SSDs result from their physical properties. A typical NAND-gate array flash memory chip that is widely used in SSDs consists of a number of blocks, each block containing a number of pages (e.g., a block with 64 pages of 2 KB each). Blocks are the smallest erasable units. Pages are the smallest programmable units. When a system performs a write operation it needs to first find a free page to write. If there is no free page available, an erase operation is necessary to make free pages. A read operation usually takes a few or tens of microseconds, whereas a write operation takes hundreds of microseconds and an erase operation takes from 1.5 to 3 milliseconds.
A more important limitation is imposed by the maximum number of erase operations that may be performed on a block of flash memory during the lifetime of a flash memory chip. Typically, a block can be erased for only 10K times in a multi level cell (MLC) memory element or 100K times in a single level cell (SLC) memory element. After that, the block becomes bad. For example, a block of MLC memory that is erased and reprogrammed every minute will be dead in 7 days because 60×24×7=10,080 erase operations, which exceeds the life cycle of the memory element. The lifetime of a flash memory is typically extended by wear leveling that distributes erase operations evenly across all blocks. As a result, write operations in flash memory SSDs are not done in-place as is done in HDDs and are much slower than read operations.
It is clear from the above discussions that allowing random writes to SSDs in the same way as to HDDs is not an optimal approach. Using an SSD as another level of storage cache cannot avoid random writes either. In addition, lower level storage cache provides limited performance benefits because data locality at disk I/O level is very weak. The best cache hit ratios of second level disk caches (in theoretically optimal caches with off-line caches managed manually in an optimal way) ranges from 16.5% to 86.4% for cache sizes between 16 MB and 2 GB, depending on applications.
High performance, low cost multi-core graphics processing units (GPU)/CPUs represent another dramatic technology advance. GPUs have traditionally been thought of as commodity chips to drive consumer video games. However, the push for realism in such games along with the rapid development of semiconductor technologies has made GPUs capable of supercomputing performance for many applications at very low cost. There are many low-end to medium GPU controller cards available on the market for under $100 that deliver extraordinary computation power. There has already been extensive research in using GPUs for general purpose computing (GPGPU). Besides high performance and low cost, there has also been a technology drive for reliable and low power GPUs. For example, an embedded system using the ATI Radeon HD 3650 GPU draws very little power but delivers performance levels of hundreds of GFLOPS. The next-generation mobile GPUs are expected to nearly double this performance with a similar power envelope.
With such rapid development of GPU/CPUs, experiments have been carried out on GPU cards such as NVIDIA 9500GT and ATI Radeon HD 2400 PRO. Specifically, the execution time of computing Alder32 and Rabin fingerprint values of large data blocks in parallel were measured on multi-core GPUs and it was observed that a straightforward program implementation takes 60 to 90 microseconds to compute hash values of all chunks of 128 B in an entire data block of size 4 KB to 32 KB. This promising computing speed makes it possible to do on-the-fly computation for disk I/O operations.
Researchers in computer systems have long observed the strong regularity and content locality that exist in memory pages. Memory pages contain data structures, numbers, pointers, and programs that process data in a predefined way. Such strong regularity and content-locality have been successfully exploited for in-memory data compression. Large files and collections of files also show strong content locality with large amounts of data redundancy that can be eliminated by efficient compression algorithms. Delta encoding has been successfully used to eliminate redundancy of one object relative to another, suggesting that many data blocks can be represented as small patches/deltas with respect to reference blocks. Furthermore, recent research has shown strong content locality in many data-intensive applications, with only 5% to 20% of bits inside a data block being actually changed on a typical block write operation.
Besides the strong regularity and content locality inherent in block data, the most popular computing platform, virtual machines, provides us with additional opportunities for content locality. The emergence of cloud computing requires hundreds, even thousands of virtual machines running on servers and clients. Such widespread use of virtual machines creates a problem of virtual machine image sprawl where each virtual machine needs to store the entire stack of software and data as a disk image. These disk images contain a large amount of redundant data. Gupta et al. have recently presented a powerful Difference Engine that has successfully exploited such content locality to perform memory page compression with substantial performance gains. This strong content locality suggests again the possibility of organizing data differently in data storage to obtain optimal performance.

Storage of data reference blocks and deltas in different storage devices


In a database management system for concurrently executing a plurality of transactions for access to a database, there is provided a user interface for defining a parent/child relationship between a plurality of pieces of data. The parent information of data is added to the data itself and to a storage location information of the data in the database. Upon access to data, lock control is performed by use of the parent information of the data, thereby performing representation of locked a object.

1. Field of the Invention
This invention relates to a database system having a lock control function, and particularly to a lock control method for representing locking of lockable objects.
2. Description of the Related Art
In a database (hereinafter, abbreviated to as DB) system, a lock control facility is provided by a DB management system (hereinafter, abbreviated to as DBMS) for managing a DB in the order to assure consistency in DB when a plurality of transactions are concurrently executed.
The fundamental lock control of the DB is described in "INFORMATION STRUCTURE AND Database, IWANAMI Lectures of Information Science-8, 1983" (Document 1). Here, two different lock modes, or exclusive lock and share lock, are described.
A transaction exclusively locks data being updated. The exclusive lock does not allow other transactions to refer to nor update the locked data. On the other hand, a transaction performs a share lock on data for reference only. The share lock allows the other transactions to refer to the locked data but does not allow them to update it.
The problems associated with the lock control includes a trade off between the transaction concurrence based on the granularity of the locked data unit and the overhead in the lock control processing.
A method, concerning this problem, of efficiently controlling locks by use of lock control rules based on a hierarchy relationship between locked data is described in "Granularity of Locks in a Large Shared DataBase", J. N. Gray, R. A. Lorie and G. R. Putzolu, Proc. 1st International Conference on Very Large Database, 1975 (Document 2).
For example, in a relational database system, since the database consists of a group of tables each of which consists of a group of records, a hierarchy can be constructed in this order (database>table>record). Here, five different lock modes are used which include lock modes having a notion of intention in addition to the above-mentioned two lock modes.
When a transaction performs an exclusive lock on a certain record, it also performs an exclusive intention lock on the table ranking superior to the record. Then, when the other transactions refer to the other records belonging to that table, they should request a for share lock on the table, but the lock does not conflict with the exclusive intention lock. Thus, all transactions can be executed concurrently.
However, when records are updated, the exclusive intention share lock is requested on the table, but the lock conflicts with the exclusive intention lock. Thus, since there is no lock conflict on each record, the overhead for lock control can be reduced.
The relationship among such lock modes is shown in Table 1 (page 434) of Document 2.
In addition, a method of reducing the overhead in a lock control process is described in JP-A-7-191898 (Document 3).
In this method, a table for exclusive control is provided in which predetermined items for exclusive control are registered, and when values of the corresponding items are being locked, the lock control table is checked for the registration, so that the amount of input data for lock control can be reduced and that the overhead for lock control can be reduced.
A model capable of a benchmark test in a DB system presented in "The 007 Benchmark", Carey Michael J., DeWitt David J., Naughton Jeffery F., Proc. ACM SIGMOD Conference, June 93 (Document 4) has a mode in which data of one hundred million pieces or more can be treated.
In this case, when the data length of one record of the lock management table is assumed to be about 100 bytes, simultaneous lock control on data of one hundred million pieces or more will need a memory region of 10 gigabytes or more. In this mode, lock control is also made in a data page unit having a plurality of pieces of data, so that the number of records in the lock management table can be reduced.


Disclosed is a process for manufacturing a plasma display panel comprising a novel forming step in which a very thick dielectric layer can be formed in an efficient manner. The process for manufacturing a plasma display panel comprising a step of transferring a coating material layer formed on a support film to the surface of a glass substrate to which an electrode is secured; and a step of baking the transferred coating material layer to form a dielectric layer on the surface of the glass substrate.

1. Field of the Invention
This invention relates to a process for manufacturing a plasma display panel, and, particularly, to a process for manufacturing a plasma display panel including a novel step of forming a dielectric layer on a glass substrate.
2. Description of the Background Art
A plasma display in the form of a plate-type fluorescent display has attracted considerable attention in recent years. FIG. 1 is a typical view showing a configuration in section of an A.C. type plasma display panel (hereinafter called "PDP"). In this figure, the symbols 1 and 2 represent glass substrates opposedly positioned and the symbol 3 represents a partition wall. A combination of the glass 1, the glass 2, and the partition wall 3 forms divisional cells. The symbols 4, 5, and 6 represent a bus electrode secured to the glass substrate 1, an address electrode secured to the glass substrate 2, and a fluorescent material supported in the cell respectively. The symbol 7 represents a dielectric layer formed on the surface of the glass substrate 1 so as to cover the bus electrode 4. The symbol 8 represents a protective layer made, for example, of magnesium oxide. The dielectric layer 7 is formed of a sintered glass material with a film thickness, for example, of 20 to 50 .mu.m.
In order to form the dielectric layer 7, there is a known process in which a paste composition containing glass powder is prepared and applied to the surface of the glass substrate 1 by screen printing, followed by drying to form a coating material layer which is then burned to remove organic substances thereby baking the glass powder.
In this case, the thickness of the coating material layer is required to be 1.3 to 1.5 times that of the dielectric layer 7 to be formed in consideration of loss in film thickness associated with the removal of organic materials in the baking step. For example, in order for the thickness of the dielectric layer 7 to be 20 to 50 .mu.m, the thickness of the coating material layer must be designed to be about 30 to 70 .mu.m.
On the other hand, if the paste composition containing the above glass powder is applied by screen printing, a film thickness formed by one application is about 15 to 25 .mu.m. This requires plural repetitions (for example, two to five times) of application of the paste composition to prepare a coating material layer with the desired thickness.
The problems to be solved by the invention, especially relating to the screen printing method, are as follows:
(1) Operation of plurally repeated applications of a paste composition (multiple printing) is complicated and is inferior in workability. It is also necessary to confirm the dispersion condition of the components for each application of the paste composition. Redispersion treatment is required when an inferior dispersion, e.g. deposition of glass powder, occurs. Therefore, the conventional method in which a dielectric layer is formed through such a complicated application step has a problem in view of efficiency of producing a PDP. This problem is more significant as the display panel increases in size.
(2) In the case of forming the coating material layer by multiple printing utilizing a screen printing method, the film thickness of a dielectric layer formed by baking the coating material layer is not uniform. The tolerance, for example, within .+-.5% cannot be achieved using this method. This is because it is difficult to uniformly apply the paste composition to the surface of the glass substrate by multiple printing utilizing a screen printing method. The dispersion in the film thickness of the dielectric layer is greater with increased area of application (panel size) and with the number of applications. The dispersion in the film thickness causes dispersion in dielectric properties in the surface of a panel material (the glass substrate provided with the dielectric layer) prepared in the application step using multiple printing. This dispersion in dielectric properties causes display defects (uneven luminance) in the PDP.
(3) In the screen printing method, a small amount of air is trapped in the paste composition passing through a screen and there are cases where this air remains as air bubbles in the coating material layer. When the coating material layer containing an air bubble is baked, pinholes or cracks are produced in the formed dielectric layer. In addition, the (n)th coating tends to be damaged by being squeezed in the step of forming the (n+1)th coating. This causes cracks to occur in the dielectric layer. The insulating properties of the dielectric layer are damaged by the pinholes or cracks whereby the dielectric layer exhibits dielectric properties lower than expected.
(4) In the screen printing method, there are cases where the shape of a screen print mesh is transferred to the surface of the coating material layer. A dielectric layer formed by baking such a coating material layer has a deteriorated surface smoothness.
The present invention has been developed in view of this situation and has an object of providing a process for manufacturing a PDP comprising a novel forming step in which a very thick dielectric layer can be formed in an efficient manner.
Another object of the present invention is to provide a process for manufacturing a PDP comprising a novel forming step in which a dielectric layer required for a large panel can be efficiently formed.
Yet another object of the present invention is to provide a process for manufacturing a PDP comprising a dielectric layer with a highly uniform film thickness.
A further object of the present invention is to provide a process for manufacturing a PDP comprising a reliable dielectric layer having no defects, including pinholes or cracks.
A still further object of the present invention is to provide a process for manufacturing a PDP comprising a dielectric layer possessing excellent surface smoothness.

Process for manufacturing plasma display panel


This disclosure relates to modeling an Agile team structure such that it aligns with Agile principles, achieve synergy and deliver intended business benefits. Current approach to modelling depends on unproven manually arrived patterns that do not predict benefits, are based on limited number of experts utilizing heuristics from personal experience. Once a working model is derived, it is refined over time which is a slow process with no verification of its effectiveness. In accordance with the present disclosure, scalable and customizable location independent Agile delivery models can be generated using a palette based user interface such that constraints are optimized. A pre-configured meta-model is chosen and the location independent model is generated given the constraints. A compliance indicator provides a degree of compliance with the Agile principles. The model is then evaluated using machine learning models that have been trained by leveraging a knowledge base of successfully implemented Agile models.

Agile is a methodology by which a team delivers value faster and better than the competition when a customer wants the value, thereby meeting the needs of the customer in a sustainable, safe and high quality mode. Adhering to the values and principles of Agile captured in 'The Agile Manifesto' results in small Agile development team, often less than 10 members. The team works very closely with the business in short time frame, often in weeks, to deliver an increment of functionality. The team augments or refines the functionality over several iterations. Agile promotes a human friendly way of working involving simplicity, small team, experimentation, and mutual empathy. A key catalyst of Agile is the co-location of all the members in the small team. Co-location is explicitly demanded in one of the Agile principles, 'The most efficient and effective method of conveying information to and within a development team is face-to-face conversation'.
Its more than 17 years since publication of the Agile Manifesto. There are marked changes in the way organizations work today. Companies have grown in size, even spread to different continents/time zones. Many large enterprises have skilled professionals of all kinds all over the world who need to collaborate to develop organization capabilities. Hence, co-location of all Agile teams is not practical for many enterprise efforts.

Generating scalable and customizable location independent agile delivery models


The present disclosure provides a thickness measuring device including a base, a first moving component, a second moving component, a frame and a linking component. The base includes a base main body and a sensor. The first moving component moves along a first direction and includes a contacting end. The second moving component moves along a second direction and includes a sensing element corresponding to the sensor. The frame is connected to the base and includes a frame main body, a first guiding groove and a second guiding groove. The first and second guiding grooves are formed on the frame main body for accommodating the first and second moving components. The linking component includes a rotating element, a first connection portion and a second connection portion. The first and second connection portions are disposed on a surface of the rotating element and connected to the first and second moving components.

When the laminator performs the hot-pressing process, the thickness of the laminating film should be known so as to determine the parameters of the hot-pressing process. Generally, within a conventional thickness measuring device used for measuring the thickness of the laminating film, a fixed grating is directly connected to a detection rod. When the detection rod contacts the detected object, i.e., the laminating film, the thickness of the detected object can be obtained by sensing the displacement of the fixed grating with respect to the capacitance-grating sensor. In such structure of the conventional thickness measuring device, the measurement accuracy is directly determined by the precision of the components and the resolution of the sensor. When the measurement accuracy is needed to be improved, the requirements of the precision of the components and the resolution of the sensor are significantly increased. As a result, the cost of the thickness measuring device is raised.
Therefore, there is a need of providing a thickness measuring device so as to obviate the drawbacks encountered in the prior arts.


A pilot warning system is disclosed for a helicopter having a main rotor rotatable about a yaw axis, a fuselage connected to the main rotor and having a tail boom with a controllable force mechanism to counter-act the torque exerted on the fuselage by rotation of the main rotor. The pilot warning system acts on foot pedals operatively connected to the controllable force mechanism, with the pedal movement controlling the amount of force exerted by the controllable force mechanism on the tail boom to the control the orientation of the helicopter fuselage about the yaw axis. A position sensing device senses the location of at least one of the foot pedals between its first and second positions, and a warning indicator operatively connected to the position sensing device provides a warning to the pilot when the sensed foot pedal reaches a predetermined distance from one of the first and second positions. The warning indicator provides a tactile warning into the pilot, such as vibration or shaking of the respective foot pedal to provide an unmistakable warning to the pilot that the foot pedal has reached a predetermined position near its maximum travel position. By such a warning system, the pilot is provided with a tactile input indicating that the helicopter yaw control system is approaching its maximum counter-rotating torque and that he/she should take appropriate action.

Devices for shaking the control column or "stick" which controls fixed-wing aircraft are well known and provide an unmistakable warning of an impending stall. Such devices are typically mounted on the aircraft's control column or "stick" and provide a high amplitude, low frequency vibration to signal the pilot of an impending stall. Such signals provide an unmistakable warning to the pilot, which cannot be confused with other warnings and signals typically present in an aircraft cockpit. Control column shakers of various designs are manufactured and sold by Safe Flight Instrument Corporation of White Plains, N.Y., the assignee of the present invention.
The use of a control column shaker in rotary wing aircraft is also known, as evidenced by U.S. Pat. No. 4,115,755 to Cotton. As disclosed therein, an alarm, such as a shaking of the collective pitch control lever of a helicopter, is used as an indication that the actual acceleration exceeds the permissible acceleration. As disclosed by this reference, the structural envelope of the helicopter, as defined by weight, air speed, rotor rpm, air density and collective stick position, is used as an indication of permissible loading of the helicopter rotor. Cotton also teaches the use of a gross measure of the aircraft weight, density of the air, air speed, collective pitch and rotor speed of the aircraft as indices of a table look-up to determine the maximum permissible aircraft acceleration under such flight conditions, which is then compared against the actual aircraft acceleration to determine when the aircraft is maneuvered close to a loading which exceeds the structural envelope.
Controls for a single rotor helicopter typically include a cyclic control stick which movement controls the movement of the helicopter about the roll axis and the pitch axis, a collective control stick which controls the vertical movement of the helicopter by collectively adjusting the pitches of the rotor blades, and foot pedals which control the orientation of the helicopter about the yaw axis. Typically, such yaw control involves a tail rotor located near the end of the tail boom of the helicopter and rotating in a plane generally perpendicular to the plane of rotation of the main rotor. Movement of the fuselage of the helicopter about the yaw axis is achieved by pushing on one of the left and right foot pedals, which movement typically adjusts the pitch of the tail rotor thereby increasing, or decreasing the force on the tail boom which counteracts the rotational force exerted on the fuselage of the helicopter by the power plant during rotation of the main rotor blade.
While it is known to incorporate a force mechanism through the tail boom of the helicopter to direct a jet of air or other gas laterally through the end of the tail boom or over the exterior of the tail boom, thereby eliminating the need for a tail rotor, the magnitude of such a lateral force is controlled by the foot pedals so as to control the yaw orientation of the helicopter fuselage.
Given the ever increasing torque capabilities of modern helicopter power plants, circumstances may arise, especially under rapid helicopter ascent, in which the force exerted by the tail rotor, or other yaw control force mechanism, is incapable of counteracting the counter-rotational force exerted on the fuselage by the aircraft power plant. Such circumstances, quite obviously, are undesirable and may result in the loss of control of the helicopter by the pilot.
It is believed that there is a significant need for a warning system which will alert the pilot as to the impending maximum force exerted by the tail rotor, or other force mechanism, in a direction to counteract the rotational forces imposed on the helicopter fuselage by the power plant. Given the warning of an approach of such maximum force, it may then be possible for the pilot to adjust the other helicopter controls to avoid any undesired movement of the helicopter fuselage about the yaw axis due to insufficient rotor force. Such a warning system should provide an unmistakable warning to the pilot and should not be confused with other aircraft warning signals.

Helicopter anti-torque limit warning device


Gasket stock is disclosed having a rectangular metal core that is readily bendable in one direction and a deformable rubberized jacket coextruded with and encasing the metal core. A method of fabricating the gasket stock through a coextrusion process is disclosed. A method also is disclosed for forming a press-in-place gasket with the method including obtaining bendable gasket stock, incrementally advancing the gasket stock to predetermined positions in a bender, and bending the gasket stock at the predetermined positions along its length to form a desired shape of the press-in-place gasket. The bender is controlled by a computer to form the shape of the gasket according to a CAD or other electronic file. Finally, a method of supplying press-in-place gaskets and accommodating design changes of such gaskets is disclosed.

Press-in-place gaskets are well known for sealing between a pair of flanges that are secured together in face-to-face relationship with bolts or the like. Such gaskets, sometimes referred to as spaghetti gaskets, generally are relatively thin bands of rubber or similar material that are injection molded to have a shape corresponding to that of a groove formed in the surface of one (or both) of the flanges to be sealed. The press-in-place gasket, as its name implies, is pressed into the groove before the flanges are joined and bolted together. A cross-sectional profile of the gasket may be configured to hold the gasket in place within the groove and to control the compression of the gasket as the flange and its mating flange are bolted together, whereupon the gasket forms a seal between the mating surfaces. Some press-in-place gaskets are made with a metal core to, among other things; help the gaskets hold their shape before and during installation. These metal core gaskets generally are fabricated in an injection mold wherein a metal core in the shape of the gasket is placed in the injection mold. The rubberized gasket material is then injection molded around the metal to form the gasket.
Prior press-in-place gaskets, and methods of making them, have exhibited inherent problems and shortcomings. For example, the cost of an injection mold for molding press-in-place gaskets can be exceedingly expensive and generally requires weeks of time for its production. This also means that there can be no substantive changes in the shape or configuration of the gasket once the mold maker begins the task of making the mold. Further, a modification in the gasket before or after the mold is finished usually requires that a new mold be created, taking time and consuming substantial financial resources. It often is useful for a designer of power train components to have access to prototypes of gaskets to be used in power train components in order to test and refine the components and surfaces to be sealed. Unfortunately, it is problematic to provide prototypes of press-in-place gaskets since the injection molding process by which they are made is expensive, slow, and does not lend itself readily to rapid prototyping techniques.
A need exists for a press-in-place gasket and a method of making press-in-place gaskets that addresses these and other problems of the prior art. It is to the provision of such a gasket and method that this disclosure is primarily directed.

Press-in place gaskets and fabrication methods


A one-shot circuit comprises a pulse generation circuit having an external clock terminal adapted to receive an external clock signal, a reset terminal coupled to receive a reset signal, and an internal clock terminal on which the pulse generation circuit develops an internal clock signal. The pulse generation circuit operates in a first mode to drive the internal clock signal from a first level to a second level in response to a transition of the external clock signal from a first level to a second level. The pulse generation circuit operates in a second mode to drive the internal clock signal from the second level to the first level in response to the reset signal going active. A delay circuit has input and output terminals coupled to the internal clock terminal and reset terminal, respectively, of the pulse generation circuit. The delay circuit operates to drive the reset signal active a delay time after the pulse generation circuit drives the internal clock signal from the first level to the second level. The delay circuit further operates, while maintaining the reset signal active, to precharge in response to the reset signal going active.

In synchronous system memories, an external clock signal drives individual synchronous memory devices in the system, and the synchronous memory devices perform specific data transfer operations, typically in response to the rising edges of the external clock signal. For example, in a typical synchronous dynamic random access memory ("SDRAM") a processor or some other external circuit applies address, data and transfer command information to one of the SDRAMs. The SDRAM latches the address and command information on a particular rising edge of the external clock signal, and the processor knows that a predetermined number of clock cycles later data may be read from the addressed SDRAM. During such data transfers, a clock buffer circuit in the SDRAM develops an internal clock signal in response to the external clock signal, and the various components within the SDRAM are controlled in response to the internal clock signal. The clock buffer circuit typically includes a one-shot circuit which operates to develop the internal clock signal in response to the external clock signal. In modern system memories, the frequency of the external clock signal is ever increasing to enable data transfer to and from the SDRAMs at correspondingly faster rates. As the external clock frequency increases, operation of the one-shot circuit becomes more critical due to the corresponding frequency increase of the internal clock signal that must be developed by the one-shot circuit.
FIG. 1 illustrates a conventional clock buffer circuit 10 including an input buffer circuit 12 receiving an external clock signal XCLK supplied by an external circuit (not shown in FIG. 1). The buffer circuit 12 inverts the external clock signal XCLK and develops an inverted clock signal XCLK on an output. The clock buffer circuit 10 further includes a one-shot circuit 38 receiving the inverted external clock signal XCLK, and developing a pair of complementary internal clock signals CLKIN and CLKIN in response to the clock signal XCLK. The one-shot circuit 38 includes a pair of cross-coupled NAND gates 40 and 42 connected as shown to form an RS flip-flop 44, as known in the art. A NAND gate 46 provides on its output a reset pulse in response to a high signal at the output of the NAND gate 40, and a high output from a delay circuit 48. The delay circuit 48 develops a high output a predetermined time after the clock signal CLKIN goes high. The reset pulse signal on the output of the NAND gate 46 is coupled to one input of the NAND gate 42, and operates to reset the RS flip-flop 44, as will be described in more detail below. Although the one-shot circuit 38 is shown as directly developing the internal clock signals CLKIN and CLKIN, one skilled in the art will appreciate a conventional driver circuit (not shown in FIG. 1) may be coupled to the outputs of the RS flip-flop 44. Such a conventional driver circuit develops the internal clock signals CLKIN and CLKIN in response to the outputs from the flip-flop 44, and may be utilized to ensure such internal clock signals have very sharp rising and falling edges.
The delay circuit 48 includes two positive-edge delay circuits 50 and 52 connected in series as shown, each operable to delay for a delay time t.sub.d a rising edge on their inputs, and to pass without such a delay a falling edge on their inputs. FIG. 2 is a more detailed schematic of the positive-edge delay circuits 50 and 52 comprising the delay circuit 48. The positive-edge delay circuit 50 includes a NAND gate 54 having inputs receiving the signal CLKIN and the supply voltage V.sub.CC, respectively, and an output coupled to a node D1'. The NAND gate 54 is typically formed of NMOS and PMOS transistors (not shown) which are sized such that the transistors driving the output high are relatively large while the transistors driving the output low are relatively small, thereby causing the NAND gate 54 to drive the node D1' high relatively quickly and low more slowly. A capacitor 56 is coupled between the node D1' and ground, and has a value selected to define the delay time t.sub.d of the positive-edge delay circuit 50. An inverter 58 drives the output D1 high when the voltage on node D1' drops below a low threshold voltage, and drives the output D1 low when the voltage on node D1' exceeds a high threshold voltage. The positive-edge delay circuit 52 includes a NAND gate 60, a capacitor 62, an inverter 64, an internal node D2' and an output D2 coupled as shown, and each of which operates in the same manner as previously described for the positive-edge delay circuit 50.
This series connection of the positive-edge delay circuits 50 and 52 results in the delay times t.sub.d of the two circuits being summed together with the output D2 going high two predetermined time delays t.sub.d after the signal CLKIN goes high. Although the delay times t.sub.d of the positive-edge circuits 50 and 52 are described as being equal, one skilled in the art will realize that in other embodiments the delay times t.sub.d may be different.
The operation of the clock buffer circuit 10 will now be described in more detail with reference to the timing diagram of FIG. 3. It should be noted that the signal CLKIN is not shown in the timing diagram of FIG. 3, but one skilled in the art will understand that this signal is merely the complement of the signal CLKIN. The clock buffer circuit 10 may be viewed as operating in one of three modes. In a first mode, designated a positive-edge mode, the clock buffer circuit 10 drives the internal clock signals CLKIN and CLKIN high and low, respectively, in response to a rising edge of the external clock signal XCLK. In a delay mode, the clock buffer circuit 10 times a delay time. After expiration of the delay time, the clock buffer circuit 10 commences the third mode of operation, designated the reset and precharge mode. During the reset and precharge mode, the clock buffer circuit 10 drives the clock signals CLKIN and CLKIN low and high, respectively, and precharges the circuits 50 and 52 in anticipation of the next rising edge of the external clock signal XCLK. Each of these modes will be described in more detail with reference to the timing diagram of FIG. 3.
Before a time t.sub.0, the signals XCLK, D1, D2, and CLKIN are low, while the signals on nodes D1', D2', and the output of the NAND gate 46 are high. At the time t.sub.0, the external clock signal XCLK goes high and the clock buffer circuit 10 operates in the positive-edge mode. In response to the external clock signal XCLK going high, the buffer 12 drives the inverted clock signal XCLK low. When the signal XCLK goes low, the NAND gate 40 drives the internal clock signal CLKIN high at a time t.sub.1.
When the internal clock signal CLKIN goes high, the delay mode of operation commences. In the delay mode, the positive-edge delay circuit 50 begins timing the delay time t.sub.d in response to the signal CLKIN going high. In other words, when the signal CLKIN goes high, the NAND gate 54 drives its output low which starts discharging the capacitor 56 as indicated by the decay of the voltage on the node D1' at the time t.sub.1. At about a time t.sub.2, the inverter 58 drives the output D1 high in response to the voltage on node D1' dropping below the low threshold voltage of the inverter. As indicated in the timing diagram, the output D1 goes high the delay time t.sub.d after the signal CLKIN goes high. When the output D1 goes high at time t.sub.2, both inputs of the NAND gate 60 of the positive-edge delay circuit 52 are high, causing the NAND gate 60 to drive its output low which begins discharging the capacitor 62 as indicated by the decay of the voltage on node D2'. The output D2 of the positive-edge delay circuit 52 remains low until the voltage on the node D2' is discharged below the low threshold voltage of the inverter 64. At a time t.sub.3, the inverter 64 drives the output D2 high in response to the voltage on node D2' dropping below the low threshold voltage of the inverter. Note that just before the time t.sub.3, the external clock signal XCLK goes low causing the buffer circuit 12 to drive the signal XCLK high. At this point, even though the signal XCLK goes high, the output of the NAND gate 40 continues driving the signal CLKIN high because the output of the NAND gate 42 remains low.
When the output D2 goes high at time t.sub.3, the reset and precharge mode of operation commences. In response to the output D2 going high, the NAND gate 46 drives its output low since both its inputs, D2 and CLKIN, are high. The output of the NAND gate 46 functions as a reset signal for the RS-flip-flop 44, and when its output goes low the internal clock signals CLKIN and CLKIN are reset low and high, respectively, in anticipation of the next rising edge of the external clock signal XCLK. More specifically, at the time t.sub.4, the low output from the NAND gate 46 causes the NAND gate 42 to drive its output high. In response to the output of the NAND gate 42 going high, the NAND gate 40, which now has two high inputs, drives the signal CLKIN low at time t.sub.4. In this way, the output of the NAND gate 46 operates as a reset pulse to drive the signals CLKIN and CLKIN low and high, respectively.
When the signal CLKIN goes low at time t.sub.4, the precharging portion of the reset and precharge mode begins. During the precharge portion, the output of the NAND gate 46 goes high just after the time t.sub.4 in response to the signal CLKIN going low. In addition, the low signal CLKIN causes the positive-edge delay circuits 50 and 52 to begin precharging their respective internal nodes D1' and D2' as indicated by the increasing voltages on these nodes just after the time t.sub.4. A short time after the time t.sub.4, the inverter 64 drives the output D2 low in response to the voltage on node D2' exceeding the high threshold voltage of the inverter 64. At approximately the same time, the inverter 58 drives the output D1 low in response to the voltage on node D1' exceeding the high threshold voltage of the inverter 58.
After the time t.sub.4, the voltages on nodes D1' and D2' continue to increase as these nodes precharge. A precharge time is defined for the positive-edge delay circuits 50 and 52 as the time between when the respective internal nodes D1' and D2' begin precharging to when the nodes begin discharging. Accordingly, a precharge time t.sub.p50 of the positive-edge delay circuit 50 is from the time t.sub.4 to a time t.sub.5, and a precharge time t.sub.p52 of the positive-edge delay circuit 52 is from the time t.sub.4 to a time t.sub.6. The precharge time t.sub.p52 is longer than the precharge time t.sub.p50 so the positive-edge delay circuit 52 has longer to precharge the internal node D2' than the positive-edge delay circuit 50 has to precharge the internal node D1'. The positive-edge delay circuit 52 is able to fully precharge the node D2' due in part to the longer precharge time t.sub.p52, and in part because the node D2' was not discharged as close to ground when precharging began at time t.sub.4.
At the time t.sub.5, a second cycle of the external clock signal XCLK is marked by the signal XCLK going high, and the clock buffer circuit 10 once again begins operation in the positive-edge mode. As previously described, when the signal XCLK goes high the signal CLKIN goes high a short time later, causing the delay circuit 50 to begin discharging the node D1' during operation in the delay mode. From the timing diagram, it is seen that at the time t.sub.5 the voltage on node D1' has not yet been fully precharged to the supply voltage V.sub.CC. As a result, when the capacitor 56 starts discharging at just after time t.sub.5, the voltage on the node D1' reaches the low threshold voltage of the inverter 58 faster than it did in the previous cycle. This is true because the voltage on node D1' must be discharged from a lesser voltage than in the previous cycle at just after the time t.sub.0. At a time t.sub.6, the output D1 goes high upon the voltage on node D1' reaching the low threshold voltage of the inverter 58. The delay time of the positive-edge delay circuit 50 during this cycle is given by the time interval from just after time t.sub.5 to time t.sub.6, and is designated t'.sub.d. The delay time t'.sub.d is seen to be shorter than the delay time t.sub.d during the last cycle. Thus, the output D1 goes high sooner than is desired due to the delay circuit 50 not having been fully precharged before the positive-edge of the signal XCLK at time t.sub.5. In response to the output D1 going high at time t.sub.6, the clock buffer circuit 10 operates as previously described with the output D2 going high at a time t.sub.7 and the signal CLKIN going low a short time later at a time t.sub.8.
The shorter delay time t'.sub.d of the positive-edge delay circuit 50 manifests itself as a variation in the pulse width of the internal clock signals CLKIN and CLKIN. The internal clock signal CLKIN has a shorter pulse width t'.sub.w for its second pulse between times t.sub.5 and t.sub.8 than its initial pulse width t.sub.w between times t.sub.1 and t.sub.4. The shorter pulse width t'.sub.w of the second pulse is due to the shorter delay time t'.sub.d of the positive-edge delay circuit 50 caused by the node D1' not having time to fully precharge to its desired level. As shown in the signal timing diagram, a third pulse of the internal clock signal CLKIN may have yet a different pulse width t".sub.w due to the varying precharge voltage on node D1'. Thus, the pulse width of the internal clock signal CLKIN varies undesirably during operation of the clock buffer circuit 10 due to the variations in the delay time of the positive-edge delay circuit 50 caused by the inability to precharge the internal node D1' during the precharge time t.sub.p50 available at the operating frequency of the external clock signal XCLK. As the frequency of the external clock signal XCLK increases, the precharge time t.sub.p50 available to fully precharge the internal node D1' decreases, and variations in the pulse width of the signal CLKIN from cycle to cycle become more significant. Although the positive-edge delay circuit 52 is described as fully precharging the internal node D2', similar problems may result for the circuit 52 as the frequency of the external clock signal XCLK increases and the precharge time t.sub.p52 accordingly decreases.
There is a need for a one-shot circuit having a delay circuit capable of a fast precharge to thereby enable the one-shot circuit to develop an internal clock signal having a constant pulse width in response to a high frequency external clock signal.

Method and apparatus for fast reset of a one-shot circuit


The present invention relates to a steering control apparatus for maintaining operating characteristics which do not change from when conditions are normal and when an impairment occurs. The apparatus includes a plurality of motors for driving a steered wheel and a plurality of ECUs, each associated with one of the motors. When the steering control apparatus is operating normally, a torque command representing torque required to turn the steered wheel is generated. The torque command is divided in accordance with the number of motors. Each of the ECUs control the associated motors in accordance with a corresponding one of the distributed torques.

The present invention relates to a vehicle steering control apparatus, and more particularly, to a steer-by-wire type steering control apparatus.
A first control apparatus used for steer-by-wire power steering is known in the prior art. In a vehicle that employs steer-by-wire power steering, the steering wheel is not mechanically connected to a steering wheel box, which is connected to the front wheels (steered wheels). The steer-by-wire type steering control apparatus drives the electric motor of the steering gear box in accordance with the steering angle of the steering wheel.
This conventional steering control apparatus has a back-up system so as to continue steering operation even when a breakdown occurs. Japanese Laid-Open Patent Publication No. 2002-37112 discloses a first prior art steering control apparatus provided with two control systems. One of the two control systems is a primary control system, and the other control system is a secondary control system. That is, the backup system of the first prior art steering control apparatus is formed by a redundant control system.
The primary control system includes a primary electric motor for driving a steering rod coupled to the steered wheels, a primary drive circuit for driving the primary motor, a primary control circuit for supplying control signals for driving the primary electric motor to the primary drive circuit, and various types of sensors. The structure of the secondary control system is identical to that of the primary control system. When both control systems are operating normally, the primary control system and the secondary control system operate the primary motor and the secondary motor to drive the steering rods in accordance with the steering angle of the steering wheel to avoid mutual interference between the primary motor and the secondary motor.
When the primary control system is impaired, the primary control circuit stops the primary electric motor, and the secondary control circuit drives the steering rod by means of the secondary steering motor.
Japanese Laid-Open Patent Publication No. 10-218000 (corresponding to U.S. Pat. No. 6,523,637) discloses a second conventional steering control apparatus for driving two steering motors. The control unit of this steering control apparatus distributes the drive forces of the two steering motors at a predetermined ratio.
The first and second conventional art steering control apparatuses control electric motors based on a detection value from a steering angle sensor for detecting the steering angle of a steering wheel. Thus, the torques of the two steering motors produce mutual interference.
Although the rotation angles of the output shafts of the electric motors detected by a rotation angle sensor provided to each electric motor is used for feedback control, the output shafts of the two electric motors are controlled at mutually different positions by the feedback control due to electric motor assembly errors and rotation angle sensor assembly errors. Therefore, the drive torque directions of the two steering motors are mismatched, and the synthesized torque is insufficient. Furthermore, noise and vibration are generated, and the electric motors are heated.
In the first conventional prior art apparatus, a detection mechanism is provided for detecting mutual torque interference of the steering motors of both control systems. When the mutual interference detection mechanism detects mutual interference, the operation of one of the control systems (including the operation of the electric motor) is stopped.
However, when mutual torque interference occurs, one control system is stopped and the steering rod coupled to the steered wheels are driven by the electric motor of the other control system, even though both control systems were operating normally. Therefore, this method is undesirable when both control systems are operating normally.
In the second conventional prior art apparatus, a primary steering motor and a secondary steering motor having mutually different configurations and performance are disposed at different locations. Since the performance (characteristics) of the two steering motors are mutually different, there is limited freedom for torque distribution to the two steering motors. Furthermore, a difference occurs in the steering operation sensitivity before and after impairment occurs regardless of which motor is impaired.


A cleaning apparatus for a quantity-metering device includes a housing and spray nozzles for dispensing fluid onto the feed rollers of the quantity-metering device and collecting the fluid together with media which is removed from said feed rollers. The cleaning apparatus includes manifolds which carry the nozzles. The cleaning apparatus is inserted in a location vacated by a component of said quantity-metering device.

The invention relates generally to volumetric discharge devices such as extruders and the like, which will be referred to as a class hereinafter as "quantity-metering devices", used for example in manufacturing and processing operations to continuously dispense a volume or metered volumetric quantities of a flowable or plastic media such as baking doughs, confections, and the like. More particularly, the invention relates to cleaning apparatus for such quantity-metering devices, particularly for integral inclusion or association therewith. The cleaning apparatus of the present invention can be used with many particular types of quantity-metering devices, but in a particularly desirable application the invention is used for cleaning quantity-metering devices for flowable baking dough or other food products, especially those devices known commercially as "wire-cut" machines.
Conventionally, a wire-cut quantity-metering device uses counter-rotating feed rollers supported within a hopper which force a continuous supply of baking dough downward through die extrusion cups in a die tray. A cutting wire, or knife, passes beneath each extrusion cup at repeated time intervals and slices off a short cylindrical (or otherwise shaped) segment of the baking dough on each cycle. Each segment sliced off represents an individual article such as a cookie or the like.
Another somewhat analogous machine Uses continuously-repetitive quantity-metering devices to dispense measured volumes of food product which are more accurate than the volumes dispensed by standard wire-cut devices. A significantly improved quantity-metering device is disclosed in U.S. Pat. No. 4,494,920 entitled POSITIVE-DISPLACEMENT VOLUMETRIC DEPOSITOR APPARATUS FOR BAKING DOUGH AND THE LIKE, issued to the inventor hereof on Jan. 22, 1985, and assigned to the same assignee. This machine includes a hopper and counter-rotating rollers which feed media to a volume-confining metering device, and the device outputs a continuous sequence of identical media volumes at a supply outlet by utilizing a head having a measuring cavity which is connected to the supply outlet.
Regardless of the particular type of metering device used, it is necessary that the device be cleaned following prescribed periods of use in food production. To clean the extrusion die cups used in wire-cut quantity-metering devices, the die tray including the cups is removed through an access opening in the food-processing apparatus in which the quantity-metering device is housed. Once the die tray is removed, the die cups are easily accessed for purposes of removing baking media and otherwise cleaning them.
Despite the ease with which die cups and shaping orifices are cleaned, it remains difficult and time consuming to clean the feed rollers and associated structure of wire-cut machines and other such quantity-metering devices. Typically, such rollers are initially scraped manually to remove larger quantities of media therefrom, and then scrubbed with brushes, etc. as well as hosed down with a series of cleaning agents, rinses, steam, etc. However, this process is very time-consuming and also exposes sanitation personnel to the risk of injury. Additionally, sanitation personnel may accidentally drop cleaning and scraping tools, etc. into the device during cleaning, requiring extensive disassembly and delay, or even inadvertently leave such tools in the device after cleaning is completed. Tools left in the extruder will obviously cause great problems with subsequent start-up efforts, and may well cause serious damage to the apparatus. In addition, high-pressure cleaning liquids, steam, etc. are hazardous as well as time-consuming, and also difficult to confine to a particular apparatus, splashing and spattering of adjacent machinery being a likely consequence and represent potential contamination which is highly objectionable in a food-processing environment.
An additional and related difficulty in conventional cleaning processes is preventing the flow of cleaning solutions into other parts of the apparatus being cleaned. If the solution is not confined to the rollers, for example, cleaning solution, together with media residue, will spread into other parts of the apparatus. This increases the time and difficulty of the cleaning operation, and May involve damage to parts or machinery of a sensitive nature.

Method and apparatus for cleaning feed rolls in food-processing machinery


The invention relates generally to a system and method for the treatment of gaseous emissions comprising methane, and in one specific embodiment, to a system and method for the treatment of emissions through the use of methanotrophic microorganisms. Certain embodiments of the invention are particularly advantageous because they reduce environmentally-destructive methane emissions and produce harvestable end-products.

1. Field of Invention
This invention relates generally to a system and method for the treatment of methane emissions, and in one specific embodiment, to a system and method for the treatment of methane emissions through the use of methanotrophic microorganisms.
2. Description of the Related Art
Methane emissions, or methane off-gases, are generated by a variety of natural and human-influenced processes, including anaerobic decomposition in solid waste landfills, enteric fermentation in ruminant animals, organic solids decomposition in digesters and wastewater treatment operations, and methane leakage in fossil fuel recovery, transport, and processing systems. As a particularly potent greenhouse gas, methane emissions are responsible for about twenty percent of planetary warming, and thus represent a significant environmental concern. Accordingly, there have been numerous efforts in the past to remediate, control, and/or otherwise treat methane emissions.
In addition to processing methane that is emitted from landfills, coal mines, wastewater treatment plants, manure digesters, agricultural digesters, compost heaps, enclosed agricultural feedlots, leaking or otherwise emitting petroleum systems, several embodiments of the present invention are directed to capturing and processing methane emitted by ruminant animals. Methane emissions from ruminant animals account for about twenty percent of total global methane emissions, and atmospheric methane accounts for about twenty percent of planetary warming. In addition to the environmentally destructive effects of ruminant animal methane emissions, such emissions represent wasted energy, as a significant percentage of the food ruminant animals eat is lost as methane. Accordingly, there have been significant efforts in the past to reduce ruminant animal methane emissions.
Ruminant animal methane emissions or, more specifically, enteric fermentation methane emissions, originate in the four-stomach digestive tract common to all ruminant animals, which includes the rumen, a large forestomach connected to the four-stomach digestive tract. The rumen contains a host of digestive enzymes, fungi, bacterium, and protozoa, and the bulk of digestion, as well as methane production via enteric fermentation, takes place here. Not surprisingly, all prior efforts to reduce enteric fermentation methane emissions from ruminant animals, which include dairy cows, beef cattle, sheep, goats, water buffalo, and camels, have focused on modifications associated with the rumen or digestive tract.
Several methods are known for the treatment of natural and human-influenced methane emissions Used in conjunction with well-known methane emissions collection methods, such as landfill gas extraction wells/blowers and coal mine methane ventilation systems, the treatment of air containing captured methane emissions includes the use of turbines, microturbines, engines, reverse-flow reactors, fuel cells, and boilers to convert methane emissions into heat and/or electricity. Other well-known methods for the treatment of methane emissions include the conversion of methane emissions into pipeline-quality, liquefied, or compressed natural gas.
The treatment and utilization of methane off-gases for the production of fuel, heat, and/or electricity is described by a number of patents, including U.S. Pat. Nos. 5,642,630, 5,727,903, 5,842,357, 6,205,704, 6,446,385, and 6,666,027, herein incorporated by reference. U.S. Pat. No. 5,642,630 describes the use of landfill gas to produce high quality liquefied natural gas, liquefied carbon dioxide, and compressed natural gas products. U.S. Pat. No. 5,727,903 describes the use of landfill gas to create vehicle grade fuel. U.S. Pat. No. 5,842,357 describes the use of landfill gas to create high grade fuel and food-grade carbon dioxide. U.S. Pat. Nos. 6,205,704 and 6,446,385 describe the use of landfill gas to provide heat, electricity, and/or carbon dioxide to enhance greenhouse operations. U.S. Pat. No. 6,666,027 describes the use of off-gas from landfills and digesters to power turbines for electricity generation.
Although each of these methods is effective at treating methane emissions under a specific range of conditions, none are known to be economically and/or technologically feasible under a range of sub-optimal methane-in-air conditions, including conditions where the flow rate, concentration, or purity of methane gas emissions is variable, unpredictable, low, and/or otherwise unfavorable.
Methane-utilizing, or methanotrophic, microorganisms are well-known in the microbiology art for their capacity to grow and reproduce using methane as a source of carbon and/or energy, particularly in a wide range of diverse methane availability conditions. Accordingly, methanotrophic microorganisms have been proposed in the past as a potential tool for the remediation of methane emissions, particularly in conditions where other treatment methods are technologically and/or economically unfeasible.
Two methods have been proposed for the utilization of methanotrophic microorganisms to treat methane emissions. In one proposed process, methanotrophic microorganisms are naturally present or purposefully situated in high-methane emissions environments, such as landfill covers or coal mines, are provided with growth-stimulating nutrients, such as oxygen, water, or mineral salts, to encourage increased microbial methane emission uptake rates. This method may be carried out using nutrient injection methods such as air or water sparging to induce increased methanotrophic growth and oxidation rates in high emissions environments. U.S. Pat. No. 6,749,368, for example, describes methanotrophic microorganisms that are placed in an aerated soil cover above a municipal landfill in order to oxidize and reduce methane emissions.
In a second proposed process, air containing methane emissions is diverted into an environment containing methanotrophic microorganisms in order to cause the microbial breakdown of methane emissions. This method may be carried out by diverting air containing methane emissions into a biofiltration column containing methanotrophic microorganisms, water, and a microorganism growth medium, whereby electricity, water, nitrogen, trace minerals, and other materials are continuously added to and consumed by the system in order to effect the microbial breakdown of methane emissions.
Both of these prior methanotrophic treatment techniques cannot effectively or efficiently reduce methane emissions. Indeed, the application of these processes has been precluded in practice because while both generate continuous and costly requirements for supply-limited materials, such as electricity and minerals, neither generates direct economic benefits to recover the capital costs of treatment, and the use of methanotrophic microorganisms for the treatment of methane emissions is simply too costly to operate and sustain over time. Prior to the applicants' discovery, no methods were known to enable the practical sustainability of the biological treatment of methane emissions, and, accordingly, the utilization of methanotrophic microorganisms for the treatment of methane emissions has been precluded in practice.
Accordingly, there exists a significant need to develop a system that enables methanotrophic methane emissions treatment to be technologically, financially, and logistically sustainable and, thus, viable in practice

This patent is subject to a terminal disclaimer.

Process for the treatment of methane emissions


A wireless network (20) participates in radio frequency communication with plural wireless terminals (30). The network (20) comprises plural transmitters (40); a precoder value processor (42) configured to develop a set of precoder values; and a precoder (44) which uses the precoder values for coding the signals transmitted from the plural transmitters. The precoder value processor (42) is configured to develop a set of frequency-independent, linear precoder values for use in precoding signals transmitted from the plural transmitters (30). Each vector of the set is associated with one wireless terminal (30). The set of precoder values is determined such that a set of target average signal to interference noise (SINR) ratios is achieved by the plural wireless terminals with a predetermined total transmit power. Preferably, the predetermined total transmit power is minimum total transmit power.

I. Technical Field
This invention pertains to wireless telecommunications, and particularly the use of wireless communication over channels having multiple transmit and multiple receive antennas.
II. Related Art and Other Considerations
Wireless communication over channels having multiple transmit and multiple receive antennas has generated a great deal of interest over the last decade. Multiple-input and multiple-output (MIMO) is the use of multiple antennas at both transmitter and receiver to improve communication performance. Until recently, most MIMO research was focused on serving a single user. In the single-user MIMO (SU-MIMO) case, if perfect channel state information (CSI) is available at the transmitter and receiver, one can diagonalize the channel, thereby creating as many parallel, non-interfering, sub-channels as the minimum number of transmit and receive antennas. Rather surprisingly, in the SU-MIMO case, it was later shown that the same number of parallel channels can be created between the transmitter and receiver even if only statistics of the channels are known at the transmitter (assuming some rather mild conditions on the average rank of the downlink channels). A. Tulino, A. Lozano, and S. Verdu, "Capacity-Achieving Input Covariance for Single-User Multi-Antenna Channels", IEEE Trans, on Wireless Communications, VOL. 5, NO. 3, March 2006; and I. E. Teletar, "Capacity of multi-antenna Gaussian channels," Eur. Trans. Telecom, vol. 10, pp. 585-595, November 1999.
In a non-coordinated cellular system, the transmissions in different cells are formed independently. Hence, the transmission from one cell typically acts as unwanted interference to mobiles in other cells. Since each cell acts independently, each cell has no way of knowing how its transmission will impact the mobiles in other cells. With small to medium-sized cells, other-cell interference is a main factor limiting the performance of the cellular system. Particularly for mobiles near the cell edge, the other-cell interference is a main factor prohibiting the delivery of high data rate to these users.
On the other hand, a coordinated system with distributed antennas uses its knowledge of the propagation environment to control the mutual interference by jointly shaping the signals that are transmitted to all the users.
More recently, considerable work has been done in investigating the role of multiple antenna systems in multiuser wireless networks, and especially in the broadcast (downlink) and multiple-access (uplink) scenarios. It has been shown recently that dirty-paper coding in conjunction with linear precoding is capacity achieving for the downlink Gaussian broadcast channel. See, e.g., H. Weingarten, Y. Steinberg, S. Shamai, "The capacity region of the Gaussian Multiple-Input Multiple-Output Broadcast Channel," in IEEE Trans. Infor. Theory, vol. 52, September 2006; G. Caire and S. Shamai, "On the achievable throughput in multiantenna Gaussian broadcast channel," IEEE Trans. Infor. Theory, vol. 49, July 2003; and W. Yu and 3. Cioffi, "Sum capacity of Gaussian vector broadcast channels," in IEEE Trans. Inform. Theory. All these results rely on the assumption that the channel between every transmitting antenna and every mobile is known perfectly at the transmitter at every frequency.
Coherent coordination schemes that have been proposed recently include the following:
Linear beamforming See, e.g., P. Viswanath and D. Tse, "Sum capacity of the vector Gaussian broadcast channel and uplink-downlink duality," IEEE Trans. Inform. Theory, vol. 49, no. 8, August 2003.
Linear beamforming with dirty-paper coding. See, e.g., G. Caire and S. Shamai, "On the achievable throughput in multiantenna Gaussian broadcast channel," IEEE Trans. Infor. Theory, vol. 49, July 2003.
Zero-forcing beamforming See, e.g., M. Karakayali, G. Foschini, and R. Valenzuela, "Network coordination for spectrally efficient communication in cellular systems," in IEEE Wireless Communication, August 2006.
Zero-forcing beamforming and dirty-paper coding. See, e.g., Kambiz Zangi and Dennis Hui, "Costa-Precoding and Zero-Forcing Linear Beamforming for Gaussian Broadcast Channels," Ericsson Internal Report, BAE-07:002519, June 2007.
There is a formidable problem with existing coherent schemes (such as those listed above, for example) for coordinating the transmissions in a system equipped with distributed antenna infrastructures. The problem is that these coherent schemes require that the channel between every transmitting antenna and every mobile be known perfectly at the transmitter. Assuming a system with t number of distributed antennas, with m number of users to be served on a given transmission timing interval (TTI), f number of subcarriers, and r number of receive antennas per user, the network must acquire the exact value of t×m×f×r channel coefficients for each TTI (e.g., very one msec). Enabling the network to acquire this information might require considerable overhead and feedback from the mobiles to the network (especially in a frequency division duplex [FDD] system).


An elevator escape device comprises a pressure increasing apparatus and a pressure decreasing apparatus, which are located in the emergency window of an elevator cab and can be operated manually to activate an oil pressure cylinder of the oil pressure mechanism to drive an oil pressure cylinder of the oil pressure mechanism to drive the elevator cab to a desired floor at such time when the elevator cab is diabled by an incident, such as a fire, a power outage, and so forth.

As shown in FIG. 1, an elevator lifting mechanism of the prior art comprises an oil pressure mechanism 1 capable of actuating an oil pressure cylinder 2 to move up and down. The oil pressure cylinder 2 is fastened at one end thereof with an elevator cab 3. The oil pressure mechanism 1 is provided with a pressure lowering valve 4, which is intended for use by a maintenance worker to cause the elevator cab 3 to descent slsowly at such time when the elevator is being serviced or stopped by the power outage.
It is very likely that the elevator cab 3 is stopped right between two floors by an incident or a power interruption. Under such a circumstance, a passenger who is trapped in the elevator cab 3 is often unable to activate the pressure lowering valve 4 to drive the elevator cab 3 to the safety.

Oil pressure auxiliary escape device of elevator