A method of processing a query about an Extensible Markup Language (XML) data. The XML query processing method includes the first step of representing the XML data in the form of an XML graph, the second step of creating and updating an Adaptive Path indEX (APEX) based on frequently used paths extracted from previously processed XML queries and the XML graph, and the third step of processing an XML query using the APEX. The XML query processing is capable of improving the performance of processing the query by extracting frequently used paths from path expressions having been used as queries for XML data and updating the APEX through the use of the frequently used paths.

1. Field of the Invention
The present invention relates to an index structure capable of allowing users to effectively retrieve data represented by extensible markup language (see T. Bray, J. Paoli, C. M. Sperberg-McQueen, and E. Maler. Extensible Markup Language (XML) 1.0 (second edition). W3C) that is the de facto standard for the representation and exchange of data on the Internet, and a method of managing the same, and more particularly to a method of processing XML queries using an adaptive path index, which utilizes frequently used paths. Thus, the query performance for XML data can be significantly improved and storage space can be reduced compared with conventional path indexes.
2. Description of the Prior Art
The emergence of the Internet has dramatically increased the amount of data of all kinds available electronically. To overcome the limitations of Hyper Text Markup Language (HTML) and solve the complexity of Standard Generalized Markup Language (SGML), extensible Markup Language (XML) was proposed by the World Wide Web Consortium (W3C) in 1998.
XML can describe a wide range of data, from regular to irregular, from flat to deeply nest, and tree shaped to graph shaped structure. Due to the flexibility of XML, XML is rapidly emerging as the de facto standard for the representation and exchange of data on the next generation Web application.
Various query languages for retrieving data represented in XML have been proposed. XML query languages, such as XPath (see J. Clark and S. DeRose. XML path language (Xpath) version 1.0. W3C Recommendation) and XQuery (see S. Boag, C. Chamberlin, M. Fernandez, D. Florescu, J. Robie, J. Simeon, and M. Stefanescu. Xquery 1.0: An XML query language. Working draft), use path expressions to traverse an irregular structure consisting of XML elements. Thus, the navigation of irregularly structured XML data is one of essential components for processing XML queries. Since the elements may be scattered at different location in the disk, the performance of processing an XML query results in significant degradation. Furthermore, when an XML query consisting of a partial matching path expression is processed, all elements constituting XML data must be traversed, which is very inefficient.
Meanwhile, a structural summary and a path index speed up the XML query evaluation by allowing only the relevant portions of XML data to be traversed with respect to a given path expression. As a result, structural summary extraction and path index generation techniques have received a lot of attention as schemes of improving the XML query performance. Goldman and Widom developed a path index that is called "strong DataGuide" (see R. Goldman and J. Widom. DataGuides: Enable query formulation and optimization in semistructured database. VLDB 1997.). This index was proposed to extract the structural information of Semi-structural data such as XML data, and records simple paths starting from a root element without overlapping. The building algorithm of the strong DataGuide emulates an algorithm for converting Non-deterministic Finite Automata (NFA) into Deterministic Finite Automata (DFA)(see J. E. Hopcraft and J. D. Ullman. Introduction to Automata Theory, Language, and Computation. 1979). Accordingly, this scheme is problematic in that, in the case where given XML data has a complicated graph structure, the size of the strong DataGuide may become larger than that of original XML data.
Milo and Suciu proposed another index called "1-Index" (see T. Milo and D. Suciu. Index structures for path expression. ICDT. 1999). 1-Index is identical with strong DataGuide in that information of all paths is maintained. 1-Index generates indexes using backward stimulation and backward simulation which are originated from the graph verification area. This method is that two nodes are integrated into a single node when the two nodes exist and two path sets starting from the two nodes are identical with each other. This method allows a graph, such as a non-deterministic finite automata, to be obtained, unlike strong DataGuide. However, when a given input graph takes a tree form, 1-Index and strong DataGuide are identical with each other. Accordingly, 1-Index can be considered a non-deterministic variation of strong DataGuide.
In the field of object-oriented database, to support frequently used reference chains between two object instances, Access Support Relation (ASR) has been used (see A. Kemper and G. Moerkotte. Access support relations: An indexing method for object bases. Information Systems, 17(2): 117-145, 1992). However, ASR materializes the reference chains of arbitrary lengths, and is problematic in that it can support only predefined subset of paths.
Cooper et al. proposed Index Fabric that is conceptually similar to strong DataGuide in that all paths starting from a root element are maintained (see B. Cooper, N. Sample, M. J. Franklin, G. R. Hjaltason, and M. Shadmon. A fast index for semistructured data. VLDB. 2001). Index Fabric encodes the paths of elements having data values to be converted into strings, and maintains them using a string index, such as Patricia Trie. However, Index Fabric is disadvantageous in that a parent-child relationship among elements cannot be maintained. Accordingly, Index Fabric is ineffective in partial matching path expressions that must employ a parent-child relationship.
Many queries on XML Data have the partial matching path expressions because user of XML data does not take the structure of the data into account, and intentionally uses a partial matching path expression so as to obtain desired results. The above-described XML path indexes, such as strong DataGuide, 1-Index, Index Fabric, etc., record all paths starting from a root element, so the index must be exhaustively traversed, thus deteriorating performance. Furthermore, these path indexes are generated only through the use of data. Thus, they do not take advantage of query workload to effectively process frequently used path expressions.

Method of processing query about XML data using APEX

Korea Advanced Institute of Science and Technology


A thermoelectrically cooled surface-enhanced Raman Spectroscopy (TEC-SERS) fiber optic probe for real-time and in-situ monitoring of volatile organic compounds in gas, liquid, and soil environments. The TEC-SERS probe comprises a sample chamber for receiving a gas sample and a fiber optic Raman probe. The sample chamber comprises an inlet having a semipermeable membrane for separating moisture from the gas sample, a SERS substrate mounted on a thermoelectric cooler, a mass flow device for providing airflow, and an output port. The fiber optic Raman probe is operably coupled to a transparent window in the sample chamber for directing an optical excitation signal to irradiate the SERS substrate and for receiving a SERS optical signal from analytes from the gas sample that are in contact with the SERS substrate.

The invention relates generally to the field of Raman spectroscopy. More specifically, the invention relates to a handheld fiber optic probe that uses a thermoelectric cooler (TEC) to condense volatile organic compounds (VOCs) onto a SERS substrate for real-time monitoring and in-situ monitoring of VOCs in gas, liquid, and soil environments.
Raman spectroscopy is an emission technique that involves inelastic scattering of incident laser energy and results in spectral peaks that are frequently shifted from the incident energy. The Raman bands arise from changes in polarizability in a molecule during vibration. As a result, virtually all organic molecules display a characteristic Raman emission. Therefore, a Raman-based sensor would not be limited to a specific class of molecules as is the case for the laser induced fluorescence (LIF) sensor. FIG. 1 shows Raman spectra obtained for carbon tetrachloride (CCl4), chloroform (CHCl3), and methylene chloride (CH2Cl2). These chlorinated solvents vary in the number of hydrogen and chlorine atoms. Yet they can easily be distinguished by their Raman spectra. Unlike fluorescence, the Raman peaks are very narrow. The inherently high resolution of Raman spectra often permits the analysis and identification of several components in a mixture simultaneously.
Despite the advantages of Raman spectroscopy over other spectroscopic techniques, Raman spectroscopy is, inherently, an insensitive technique. In the 1970s, it was discovered that Raman scattering from molecules adsorbed on such noble metals as silver, copper, and gold can be enhanced by as much as 106 to 107. The phenomenon, surface-enhanced Raman spectroscopy (SERS), has been the subject of intensive theoretical and experimental research. More than one mechanism is involved in the SERS phenomenon. Initially, the SERS technique was used as a means to probe adsorption at metal interfaces both in electrochemical and gas-phase environments. This technique has proven useful in deducing the effects of interfacial structure and reactivity on the adsorption process. However, the sensitivity of the technique as well as its exceptional spectral selectivity has made SERS attractive for a broad range of analytical applications. SERS can be used for trace organic analysis and as a detection method in gas chromatography, liquid chromatography, and thin layer chromatography. Electrochemical SERS and SERS of chemically modified surfaces have been used to detect aromatic compounds and chlorinated hydrocarbons, organic contaminants of environmental concern, in the ppm concentration range.
Although SERS is very sensitive, the technique requires intimate contact between the SERS active surface and analyte. In turn, this requires that the analyte adsorbs to the SERS active surface. If SERS spectra need to be obtained in real time and in-situ, then the reaction between the SERS substrate and the analyte needs to be reversible.
A sensor design which would (1) be compact and robust and (2) extract VOC vapors from the air and concentrate them onto the SERS substrate would result in a sensor that could be used to monitor VOCs in real time and in-situ. Besides environmental monitoring, such a sensor could be used for homeland security and force protection. There is a real concern that terrorists could poison water supplies using readily available toxic industrial chemicals such as the BTEX compounds and chlorinated solvents.

Handheld thermo-electrically cooled surface-enhanced Raman spectroscopy (TEC-SERS) fiber optic probe

The United States of America as represented by the Secretary of the Navy


A thermal transfer plate for removing heat to a heat sink or cooling fins positioned between an electrical component and a mounting surface. The plate comprises a heat conductive material which is in thermal communication with the electrical component and extends beyond the electrical component to establish thermal communication with a heat sink or cooling fins. In one specific embodiment, the thermal transfer plate has a base portion with upright side walls which form a socket to receive the electrical component. Horizontal cooling fins are located at the top of the sidewalls. The cooling fins can be of any shape which will perform the cooling or heat sink function and can be made with openings which permit air to circulate through the cooling fins. Moreover, due to its efficient heat transfer capabilities, the thermal transfer plate could be thermally connected to a separate heat sink device.

Integrated circuit ("IC") chips contain a variety of miniaturized electronic circuitry and are widely used on printed circuit boards manufactured by the electronics industry to form composite electrical circuits. A typical IC chip or die is located within a ceramic substrate and is the actual electronic circuitry that is coupled to leads that extend to contacts or terminals positioned about the perimeter of the substrate or in various patterns across the bottom surface such as land grid arrays. This assembly is referred to as an IC package or a chip carrier. During operation of the electronic circuitry, the die generates heat and this heat can destroy the active elements in the die. In addition, heat can severely limit the speed and power capabilities of the circuitry of an IC chip. Therefore, it is necessary to dissipate the heat generated by the die in the IC chip.
One means of dissipating the heat generated by the IC chip is the use of a heat sink. For example, the heat sink or radiating member can be integrated into the top of the IC package to radiate heat from the top of the IC package, as shown in Spaight U.S. Pat. No. 4,092,697, Sugimoto et al. U.S. Pat. No. 4,803,546, and Werther U.S. Pat. No. 4,750,092. In another example of heat dissipation, thermal conducting elements are used to transmit heat to a heat sink which is mounted on a printed circuit ("PC") board on the side which is opposite to the IC package, as shown in Pitasi U.S. Pat. No. 4,682,269 and IBM Technical Disclosure Bulletin Vol. 13 No. 1, June 1970 at page 58. In yet another example of heat dissipation, a removable heat sink is attached to the upper surface of an IC package, as shown in Bright et al. U.S. Pat. No. 4,716,494.
These methods could be used with IC packages which direct the thermal flow upward, i.e., away from the PC board. In these IC packages, the thermal transfer and the electrical contacts are located on opposing surfaces of the IC package. These IC packages use a "cavity down" configuration and incorporate a copper/tungsten slug into the cavity. The die is mounted directly onto the copper/tungsten slug and a silver glass paste is used to attach the die to the slug in order to minimize voiding. The die and slug are attached to the upper portion of the IC package. The heat generated by the die is conducted to the slug which then dissipates the heat to the air above and surrounding the IC package. Thus, these IC packages direct the thermal flow upward, i.e., away from the PC board or socket.
However, these prior art heat sinking methods are not suitable for IC packages which direct the thermal flow downward, i.e., toward the PC board or into the socket. In these IC packages, the thermal transfer area and electrical contacts are located on the same surface. These IC packages use a "cavity up" configuration and also incorporate a metal slug into the cavity to dissipate the heat from the die. However, in the cavity up configuration, the metal slug is attached to the lower portion of the IC package, i.e., the mounting side of the IC package. In addition, the metal slug can incorporate posts or a plate. The ceramic substrate, which forms the exterior of the IC package, is molded around the posts or plate so that the ends of the posts or the bottom surface of the plate protrude through the ceramic material to form thermal lands or pads. Consequently, in the cavity up configuration, the thermal flow is directed downward, i.e., toward the PC board or into the socket.
This cavity up configuration permits a higher density of inputs and outputs ("I/O") to the die and also reduces the length of the traces which connect the I/O's on the die to the pads or lands on the bottom of the IC package. The shorter traces result in faster signal speeds since the signal travels a shorter distance along the trace.
Furthermore, other methods for dissipating heat from IC packages which use a cavity up configuration have disadvantages. For example, if the thermal path between the IC package and the PC board is completed by soldering, the heat transfer is compromised because solder is a poor thermal coupler. In addition, solder joints are less reliable in a large array area captured under the IC package and soldering would increase the manufacturing costs. Another alternative would be to use a heat sink which penetrates the PC board. However, such a heat sink would require relatively large thru-holes in the PC board and these thru-holes would waste vast areas of precious electrical real estate on the PC board.
Another alternative would be heat dissipation via a copper layer or layers on or embedded in the PC board. However, these copper layers are very thin which greatly reduces the thermal conduction. Another alternative would be heat dissipation via the low expansion planes. The low expansion planes are incorporated into multilayer PC boards to control the thermal expansion of the PC board. Conventional multilayer boards use copper-clad Invar as a low expansion plane. However, low expansion planes are expensive and would increase the manufacturing cost. In addition, the low expansion planes eliminate areas where traces can be used on the PC board and results in wasted areas of potential electrical real estate. Therefore, a new means to dissipate heat from an electrical component was necessary.
Furthermore, IC packages are either soldered to the PC board or mounted into sockets or socket cavities which are attached to the PC board. The sockets are electrically attached to the PC board at the position designated for the IC package. The IC package is then inserted into the IC socket or socket cavity. The sockets are advantageous because a faulty IC package can be replaced with an operable IC package without the need to unsolder the faulty IC package and solder an operable IC package. Therefore, the socket saves time and expense in replacing a faulty IC package.
Accordingly, it is the object of this invention to provide a means to dissipate heat from an IC package or other electrical component which meets the aforementioned requirements and solves the aforementioned problems.
Another object of this invention is to provide a means to dissipate heat from an IC package or other electrical component which is mounted in a socket.
An additional object of this invention is to provide a means to dissipate heat from an electrical component located in a socket whereby the invention can include cooling fins or the invention can transfer the heat to a heat sink.
A further object of this invention is to provide a means to dissipate heat from an electrical component which directs the thermal flow downward into the socket or socket cavity.
Another object of the invention is to provide an additional means to dissipate heat from an electrical component which primarily directs the thermal flow upward away from the socket or socket cavity.
Another object of this invention is to provide a means to dissipate heat from an IC package or electrical component which is inexpensive to manufacture, reliable in operation, and efficient in dissipating heat.
Other objects and advantages of the invention will become apparent upon reading the following detailed description and appended claims, and upon reference to the accompanying drawings.

Thermal transfer plate and integrated circuit chip or other electrical component assemblies including such plate


There is disclosed a chocolate containing disaturated monolinoleate and non-tempering type hard butter as its oil ingredients. A process for producing a rolled chocolate by rolling-up a chocolate containing disaturated monolinoleate and non-tempering type hard butter as its oil ingredients is also disclosed.

A rolled chocolate used for decorating cakes and the like has been produced by manually scraping a plate-like chocolate with a spoon or the like. However, since this requires skill, and it is difficult to obtain uniform products, the mass production thereof by a machine has been recently employed (JP-A 59-66842, JP-A 63-263048, etc.). In such a mechanical treatment, there is a rolling-up step such as peeling off a chocolate spread on a belt with a scraper or shaving it off therefrom with a cutting blade. Since extremely severe temperature control is required in such a rolling-up step and the shape and size become uneven in many cases even in such a highly mechanized step, the yield in the rolling-up step is usually from 50 to 70%. Further, a cylindrical inner surface of the rolled chocolate thus produced tends to become whitish and this is undesirable from the viewpoint of appearance.

Chocolate for use in producing rolled chocolate


The present invention relates to a method for preparing a TNFR-Fc fusion protein mixture comprising a target content of hydrophobic chromatogram peak 3, and to a method for adjusting a content of hydrophobic chromatogram peak 3. Specifically, the present invention relates to (a) a method for preparing a TNFR-Fc fusion protein mixture using a hydrophobic interaction chromatograph medium containing an aromatic functional group, which is pre-equilibrated with an equilibration buffer comprising sodium chloride or ammonium sulfate, and a sample comprising a TNFR-Fc fusion protein mixture liquid produced from mammalian cells, and to a method for adjusting the content of hydrophobic chromatogram peak 3 by hydrophobic chromatography using an equilibration buffer containing a predetermined concentration of sodium chloride or ammonium sulfate.

Etanercept is a biological inflammation modulator that functions as a competitive inhibitor of TNF-α, binding to cell surface TNF-α receptor, to inhibit TNF-α mediated immune responses. Etanercept is a macromolecule with a molecular weight of 150 kDa, and is a homodimer of two fusion proteins linked by disulfide bond, and each fusion protein consisting of a human soluble p75 TNF (tumor necrosis factor) receptor coupled to the Fc portion of human immunoglobulin G subclass 1 (Goldenberg, Clinical Therapeutics, 21(1): 75-87, 1999; Moreland et al., Ann. Intern. Med., 130(6): 478-486, 1999).
The typical form of such fusion protein was first synthesized in the early 1990s by Bruce A. Beutler et al., at the University of Texas Southwestern Medical Center, and marketed by Amgen under the trade name of Enbrel® in 2002. Etanercept is a TNF-α inhibitor used to treat rheumatoid arthritis, psoriasis, and ankylosing spondylitis, and is under clinical trials for the treatment of vasculitis, Alzheimer's disease, and Crohn's disease.
The TNFR-Fc fusion protein can be prepared by fusing 235 amino acids of TNFR and 232 amino acids of Fc region, and when producing gene recombination technology, it exists in the form of a dimer and exhibits biological activity. TNFR is divided into 4 domains and a transmembrane region, and among the 235 amino acids consisting the same, the number of cysteine is 22, and such cysteine all forms disulfide bonds to form a three-dimensional structure. However, when TNFR-Fc is produced from animal cells, cysteines bind with each other at random, and thus they do not form disulfide bonds identical to those of a native protein. TNFR may be also partially truncated, and fail to form a correct TNFR-Fc dimer. TNFR-Fc with incorrect disulfide bonds cannot show the proper biological activity due to a drastic reduction in the binding ability to TNF-α. Further, when the entirety or a part of TNFR is truncated, it may also not exhibit such biological activity.
Therefore, when the TNFR-Fc dimers are produced using a recombinant DNA technology and an animal cell culture technique, active proteins, inactive proteins with incorrect disulfide bonds, aggregates, and truncated forms are produced at the same time, and thus a technique for isolating and purifying the proteins is needed.
Further, according to U.S. Pat. No. 7,294,481, whose applicant is Immunex Corporation, the developer of etanercept, and which relates to a method for producing recombinant proteins, it was confirmed that three peaks are present by hydrophobic interaction chromatography (HIC), and it was confirmed that the peaks are sequentially constituted of etanercept of various forms having a very low biological activity comprising etanercept in the truncated form at positions S186 and D235, TNFR-Fc fusion protein in an active form and aggregate, disulfide scrambled TNFR-Fc, etc. The same peak pattern is also disclosed in Korean patent No. 10-1454316, which relates to a method for preparing an active form of TNFR-Fc fusion protein by using a method for producing a recombinant protein. Meanwhile, hydrophobic interaction chromatography conventionally used for isolating TNFR-Fc fusion protein is merely designed to obtain high purity of an active form of TNFR-Fc fusion protein by removing and minimizing impurities except active forms of TNFR-Fc fusion protein, such as aggregates, disulfide-scrambled TNFR-Fc fusion protein, and truncated forms of TNFR-Fc fusion protein.
Meanwhile, a biosimilar is a material which is equivalent to existing approved products in terms of quality, safety, and efficacy, and specifically, only when it has a constitution similar to an originator product thereof in terms of ingredients and content of impurities, it can be used as a biomedical product. For example, etanercept (Pfizer) contains approximately 9% to 18% of the ingredient having low bioactivity which is disclosed as a component of hydrophobic interaction chromatography peak 3 (hereinafter, "peak 3") in the conventional art, and which may have influence on pharmacology as well as potency. Accordingly, developing a biosimilar product requires adjusting the content of peak 3 to a level similar to that of the originator product. Although there is a method for purifying a sample including TNFR-Fc prepared using HIC by a conventional method for producing recombinant proteins (Korean patent No. 10-1454316), the method is merely designed to obtain high purity of a peak 2 ingredient, which is an active form of TNFR-Fc after removing impurities. There has been no trial for adjusting the content of peak 3, which is a type of impurity having low bioactivity, to a level similar to that of an originator product.

Method for preparing TNFR-Fc fusion protein containing target content of impurities


The invention relates to processes for converting hydrocarbons to olefins products such as ethylene and propylene. The invention also relates to polymerizing the olefins, and to equipment useful for these processes.

Olefins, such as ethylene and propylene can be produced by conventional pyrolysis processes, such as steam cracking. Steam cracking involves exposing water and a hydrocarbon having at least two carbon atoms to a temperature in the range of about 600° C. to about 1100° C., a pressure in the range of about 1.5 to 2.75 bar, and a residence time in the range of 0.1 to 0.6 second. See, e.g., Kirk Othmer Encyclopedia of Chemical Technology, Vol. 10, 599-609. The reference discloses that steam cracking feeds comprising butane and light naphtha lead to an increase in the relative amount of propylene in the product. Although the reference discloses optimizing the process for increased propylene production, the relative amount of ethylene in the product is generally much larger than the amount of propylene.
European Patent Application Publication No. EP 1741691A1 discloses a two-step process for producing ethylene. According to that reference, high-temperature hydrocarbon pyrolysis is utilized to produce acetylene. Hydrogen is then thermally transferred from alkane to the acetylene, the hydrogen transfer being conducted at a temperature in the range of 800° C. to 910° C. When the alkane is propane, the hydrogen transfer produces ethylene and propylene.
Hydrocarbon pyrolysis and thermal hydrogen-transfer require a significant amount of energy. Hydrocarbon conversion processes utilizing less energy are desired. In certain cases, it is also desired to increase the relative amount of propylene in the product.


According to various embodiments of the present invention, a data management process is provided that manages ECG data collection, review, and reporting in an efficient and secure manner by utilizing biometric checks, quality control measures, and workflow control systems that route data based on a variety of factors to efficiently complete the measurement and analysis process.

Various types of patient medical data are valuable pieces of information with respect to a variety of medical practices. These medical practices may include treating, diagnosing, monitoring, and performing clinical trials. Clinical trials are often performed to determine the effect a particular drug may have on a particular type of patient or patients in general. During clinical trials, medical data regarding participating patients needs to be submitted over a period of time. For example, medical data may be required to be submitted before receiving a drug, on a periodic basis while taking a drug, and after the patient has stopped taking the drug.
One type of medical data commonly required during a clinical trial is data from an electrocardiogram (ECG or EKG). To obtain an ECG, medical personnel attach up to 12 leads to various areas on a patient's body. The leads are connected to a device that is able to monitor and record, electronically, the electrical signals measured by the leads with respect to time. The device may be able to display the obtained measurements graphically.
All or part of a patient's medical data may be reviewed by individuals obtaining the data, the person or entity supervising the clinical trial, and a data management company. For instance, during clinical trials involving a drug being administered to a patient, generally an ECG is performed on the patient, and data obtained from the ECG is reviewed, to monitor the patient's health and the effect the drug may have on the patient's heart. ECG data is often sent to other locations besides a testing clinic for review. The ECG data, for example, may be sent to a cardiologist for review and generation of a report based on the data. Clinical trial ECG data generally must be handled confidentially and with great care to ensure the integrity of the clinical trial. Furthermore, the review of the data often must occur relatively quickly, such as within 24 hours, in order to adequately and safely monitor the patient's health.
Conventional processes for reviewing ECG data have involved faxing the ECG data to a data management company. The data management company employs trained technicians that review the data and perform measurements on the ECG data graph to determine information such as a QT, PR, ST, and RR interval. The following, in a non-limiting way, discloses examples of values and how they are determined. The QT interval is measured from the beginning of the QRS complex to the end of the T wave. The QT interval is important for diagnosing prolongation or shortening of the QT interval. A long QT interval signifies an abnormally long delay between the electrical excitation (or depolarization) and relaxation (repolarization) of the ventricles of the heart. A short QT interval involves short QT values that do not significantly change with the heart rate. The QRS value corresponds to the current that causes contraction of the left and right ventricles of the heart. The T wave represents the repolarization of the ventricles.
The PR value is determined as the distance between a P wave and R wave. A P wave is the electrical signature of the current that causes atrial contraction. Its relationship to QRS values determines the presence of a heart block. The R wave indicates contraction of the myocardium, or the muscular tissue of the heart, itself. The ST interval is measured from the QRS complex to the T wave. Like the R wave, the S wave indicates contraction of the myocardium, or the muscular tissue of the heart, itself. The RR value is the interval from the onset of one QRS complex to the onset of the next QRS complex.
A cardiologist is employed to review the ECG and the technician's measurements for accuracy and to create a report. The resulting report is faxed back to the clinical testing center for the patient's records. The report is also faxed to the data management company to collect the information for clinical drug trial reporting purposes.
Recently, computerized systems have been implemented to create, modify, maintain, archive, retrieve, and transmit clinical data. Computerized systems assist data management companies in collecting, handling, and securing clinical trial data. Utilizing a computerized system, ECG data may be transmitted electronically to the data management companies' trained technicians. The technicians are then able to measure the ECG on a computer system screen by using cross hairs associated with a mouse cursor to obtain measurements based on a location of the mouse cursor. Additionally, the technician is able to transmit, electronically, the ECG and measurements from the ECG to a cardiologist for review and generation of a report. The computerized systems allow the technician, cardiologist and the storage facility to be in separate places, including on separate continents, and then allows all concerned to benefit from ideal locations of capacity, data storage, medical expertise, and technical and other desired capacity. Finally, computerized systems provide the ability to electronically transmit ECG data and reports to the clinical trial organizers and to the Federal Drug Administration (FDA) in a format acceptable to the FDA.
Conventional computerized data management systems, however, do not provide sufficient data management processes for securely, efficiently, and safely transmitting and analyzing ECG data. For instance, conventional data management techniques do not provide workflow management functions that promote quick and efficient review of ECG data and reporting. Conventional data management techniques do not provide a high level of security and audit trails to safeguard patient confidentiality and the integrity of the clinical trial. In addition, conventional systems do not provide for automatic quality control procedures to ensure consistency and accuracy with respect to the patient's data. Various embodiments of the present invention, therefore, provide a data management process that includes a high level of patient data security, clinical trial integrity, quality control, workflow management, and ECG review and reporting.

System and method for managing medical data


Various embodiments are disclosed relating to database configuration refinement. In an example embodiment, a method is provided that may include determining a size limitation for a database configuration, determining a workload of the database configuration, and making a determination that a size of the database configuration is greater than a size limit. The method may also include applying either a merge process or a reduction process to decrease the size of the database configuration. The merge process may merge a first index/view with a second index/view to produce a merged index/view, for example. The reduction process may delete a first portion of a first view to produce a reduced view.

Databases are very useful tools, and may allow users to organize and selectively retrieve data based on queries, etc. However, as new queries are entered and new sets of indexes and views are generated, a database configuration may typically increase in size over time. A database administrator (DBA) may typically adjust or tune the database configuration to decrease its size. This can be a significant challenge, and often involves using a combination of automated tools and manual adjustment. Current techniques directed to this problem are typically inadequate.

Database physical design refinement using a merge-reduce approach


A lighting apparatus has a light source emitting primary light; a reflector device with first and second focal points; a rotatable light wheel with two functional regions; a primary light device irradiated by the light source and having functionally assigned to it one of the functional regions as a primary light functional region, the first focal point being located at the primary light device; a utility light device to which is functionally assigned another of the functional regions as a utility light functional region, the second focal point being located at the utility light device; a primary light functional region having in a first rotational position of the light wheel at least one phosphor sensitive to the primary light; and a utility light functional region being transmissive to the light whose wavelength is converted by the primary light functional region.

In the case of projection applications based on the fundamentally known LARP ("Laser activated remote phosphor") technique, a phosphor is irradiated by a laser and the irradiated light is partially converted by means of the phosphor into a wavelength-converted or frequency-converted utility light, and partially scattered back without a wavelength conversion. A primary pump light generated by the laser need not be used, or need not be continuously used, directly as utility light. In order to generate a wavelength-converted utility light that is pure during the irradiation of the phosphor, it is necessary for the pump light component of unconverted wavelength to be filtered out at this time. A rotating filter wheel with optical filters such as is known from projector applications can provide a assistance here.
If use is made of a rotating phosphor wheel in order to carry the phosphor, something which is particularly advantageous for an efficient wavelength conversion given high pump light intensities (from approximately 5 W/mm2), there is a need for a total of two rotating wheels, specifically the filter wheel and the phosphor wheel, to be synchronized with one another. This signifies a high technical outlay.


A non-contact communication medium according to an embodiment of the present technology is a non-contact communication medium for a recording medium cartridge, including: a circuit component; a support substrate; and an antenna coil. The circuit component has a memory unit capable of storing management information relating to the recording medium cartridge therein. The support substrate supports the circuit component. The antenna coil includes a coil unit that is electrically connected to the circuit component and formed on the support substrate, an inductance value of the coil unit being 0.3 μH or more and 2.0 μH or less.

In recent years, a magnetic recording medium has been widely used for backing up electronic data, and the like. As one magnetic recording medium, for example, a magnetic tape cartridge has a large capacity and can be preserved for a long time, and thus, the magnetic tape cartridge has attracted increasing attention as a storage medium for big data and the like.
For example, a magnetic tape cartridge of the LTO (Linear Tape Open) standard includes an RFID (Radio Frequency Identification) tag called a cartridge memory (see, for example, Patent Literature 1). The cartridge memory includes an antenna and an IC chip for communication and recording, and is configured to be capable of reading and writing production management information of the magnetic tape, the outline of the recorded content, and the like. The cartridge memory receives a signal magnetic field transmitted from a tape drive (reader/writer) to generate electric power, and thus operates without power supply.

Non-contact communication medium and recording medium cartridge


To provide a wireless communication method in the case where communication of a wireless signal from a communication device to a semiconductor device can be ensured, communication of a wireless signal can be ensured without using a repeater even when communication of a wireless signal from a semiconductor device to a communication device is difficult due to an external factor such as an obstacle. A plurality of semiconductor devices operate in selectively switching between a first state in which the first wireless signal transmitted from the communication device is received and a second state in which the second wireless signal transmitted from the semiconductor device is received. The semiconductor device in the second state receives the second wireless signal from the semiconductor device in the first state and transmits to the communication device the second wireless signal including detection data for indicating that the second wireless signal is received.

1. Field of the Invention
The present invention relates to a wireless communication method. The present invention particularly relates to a method for wireless communication between a semiconductor device which transmits and receives a signal, that is, RFID (radio frequency identification) tag and an external communication device.
Note that a semiconductor device here refers to a general device which can function using semiconductor characteristics.
2. Description of the Related Art
Owing to development of computer technologies and improvement of image recognition technologies, data identification methods utilizing media such as barcodes have spread widely and have been used for identification of product data and the like. It is expected that the amount of data to be identified will further increase in the future. On the other hand, data identification utilizing barcodes is disadvantageous in that a barcode reader is required to be in contact with the barcodes, and that the amount of data capable of being stored in the barcodes is not so large. Therefore, contactless data identification and increase in the storage capacity of a medium have been required.
In view of the foregoing requirements, an RFID tag (hereinafter referred to as a semiconductor device, and also referred to as an ID chip, an IC tag, an ID tag, an RF tag, a wireless tag, an electronic tag, or a transponder) utilizing semiconductor characteristics and a wireless communication device (hereinafter referred to as a communication device, and also referred to as a reader/writer, a controller, or an interrogator) having a function of communicating with a semiconductor device have been developed. A semiconductor device stores necessary data in a storage element of the semiconductor device and reads the data by the communication device with the use of a contactless means, generally a wireless signal. It is expected that practical application of such a wireless communication system for reading data stored in a semiconductor device will allow commercial distribution and the like to be simplified and reduced in cost while ensuring high security.
In recent years, a system with which data can be transmitted and received without contact in a variety of fields where automatic identification is necessary, such as payment for goods, has spread widely. A product on which such a semiconductor device is mounted is designed so as to read and write data from/to an external device without contact through an antenna having a shape suited to a frequency band used at the time of transmission or reception of data.
A semiconductor device which performs wireless communication can read a signal from a plurality of semiconductor devices by providing an anti-collision function (also referred to as anti-collision simply) in a communication device, unlike reading of two-dimensional data such as barcodes. Further, a semiconductor device which performs wireless communication can transmit and receive a wireless signal even if there is an obstacle between a communication device and the semiconductor device, unlike reading of two-dimensional data such as barcodes. In the case where there is an obstacle between a communication device and the semiconductor device and accordingly a wireless signal cannot be transmitted and received, a repeater for transmitting and receiving the wireless signal is provided to secure identification information of a desired semiconductor device (see Patent Document 1: Japanese Published Patent Application No. 2001-24547).

Semiconductor Energy Laboratory Co., Ltd.


The present disclosure relates to dipeptidase inhibitors, and more particularly, to N-Acetylated .alpha.-Linked Acidic Dipeptidase (NAALADase) enzyme inhibitors which are proposed as novel agents for the treatment of prostate cancer. NAALADase is enzyme which is a membrane-bound metalloprotease which hydrolyzes the dipeptide, N-acetyl-L-aspartate-L-glutamate (NAAG) to yield glutamate and N-acetylaspartate. The compounds of the present invention include phosphinic acid derivatives that inhibit NAALADase enzyme activity and which have been found useful for inhibiting the growth of prostate cancer cells.

1. Field of the Invention
The present invention relates to novel compounds and compositions which inhibit N-Acetylated .alpha.-Linked Acidic Dipeptidase (NAALADase) enzyme activity, and in particular to phosphinic acid compounds or phosphinic acid compositions which inhibit NAALADase enzyme activity in humans and warm-blooded animals. The present invention is also directed to novel compounds and compositions which inhibit N-Acetylated .alpha.-Linked Acidic Dipeptidase (NAALADase) enzyme activity as novel agents for treatment of cancer. Further, the present invention is directed to novel compounds and compositions which inhibit N-Acetylated .alpha.-Linked Acidic Dipeptidase (NAALADase) enzyme activity as novel agents for treatment of diseases of the prostate.
2. Description of the Prior Art


An air cleaner for a motor vehicle includes a housing having an air inlet opening, an air outlet opening, a secondary air inlet opening and at least one peripheral wall defining a chamber therein. An air filter element is provided and received into the chamber and positioned to separate the air inlet opening from the air outlet opening. A vacuum actuated valve is provided in the secondary air inlet opening of the housing and is in communication with a secondary air portion of a dirty face of the filter element. The valve configured and adapted to automatically change from a closed to an open state when a vacuum in the housing increases to a predetermined vacuum value and then to close when the vacuum decreases below the predetermined value, thereby permitting the vehicle engine to continue to operate even though airflow in the primary air intake may be obstructed.

Internal combustion engines require a source of combustion air. A typical source for combustion air is air drawn from outside of the vehicle, which commonly includes particulate contaminants. An air cleaner including an air filter element is normally provided in the air induction system to capture these particulate contaminants before combustion air is delivered to the vehicle engine. When operated in colder climates where heavy or blowing snow is common, snow may be drawn into the air cleaner and lead to eventual blockage of the air filter element, thereby cutting off the supply of combustion air and leading to poor engine performance.
In the prior art, air cleaners are known that include a secondary air inlet having a movable damper or power operated valve operable to open a secondary air supply to the air cleaner when the primary air supply becomes obstructed by snow. One example is U.S. Pat. No. 4,969,939, which discloses an air cleaner, equipped with a slideable valve including mechanical linkage extending into the operator cabin and operable by a vehicle operator to admit secondary air into the air cleaner in the event the normal air inlet becomes blocked by snow.
U.S. Pat. No. 6,395,048 discloses an air cleaner having an annular door with an open window that is rotatable between a first and a second position. In the first position outside air is admitted to the air cleaner. In the second position warmer under the hood air is provided to the air cleaner and the normal outside air inlet is blocked. A mechanical actuator rotates the door.
As can be understood from the above, many varieties of air cleaners equipped for secondary air induction are known. As can be seen from the prior art, air cleaners equipped for secondary air induction have a number of moving parts, are more complex and are therefore more costly that similar air cleaners lacking secondary air adaptations.

This patent is subject to a terminal disclaimer.


A curable film-forming composition is provided comprising (i) 10 to 90 percent by weight based on the total weight of resin solids in the film-forming composition of a crosslinking agent; (ii) 10 to 90 percent by weight of a polymer containing a plurality of functional groups reactive with the crosslinking agent; and (iii) 5 to 85 percent by volume of particles having a mean particle size less than 100 nm. The particles comprise 1 to 99 percent by weight of at least one metal oxide wherein the metal is selected from zinc, titanium, cerium, manganese, bismuth, copper, zirconium and iron.

Color-plus-clear coating systems involving the application of a colored or pigmented base coat to a substrate followed by the application of a transparent or clear topcoat to the base coat have become very popular as original finishes for automobiles. The color-plus-clear systems have outstanding gloss and distinctness of image. The clear coat is particularly important for these properties.
Because of almost constant exposure to ultraviolet radiation (sunlight) in automotive applications, it is imperative that coating compositions used in such applications be resistant to degradation caused by ultraviolet radiation exposure. Degradation of coating systems due to ultraviolet light exposure can cause appearance problems, and in severe cases, coating adhesion failure and delamination of one or more coating layers.
Prior art attempts to improve the ultraviolet resistance of coating compositions have included the addition of expensive organic UV(A) absorbers and hindered amine light stabilizers to compositions including primers, base coats, and clear coats. These organic additives are themselves susceptible to photodegradation, limiting their effectiveness with time. These small organic molecules are mobile within cured and uncured coating systems and as a result can migrate, for example, from a clear coating into underlying coated layers, reducing the protection provided to the upper layers. Furthermore, these materials are often volatile and may be partially lost from coatings that are cured at elevated temperatures. Other efforts involve addition of opaque pigments such as carbon black, but such pigments are not suitable for use in transparent (clear coat) compositions.
U.S. Pat. No. 5,846,310 to Noguchi et al. discloses silica particles coated with particles of TiO2, Fe2O3, ZnO or ZrO2, for use as pigments in coatings, or as sunscreening agents. The biphasic nature of these particles, however, can lead to problems of haze and poor durability. The refractive indices of TiO2, Fe2O3, ZnO and ZrO2 are significantly higher than that of a plastic or coating composition, which rapidly leads to haze with increasing phase size and concentration. In addition, TiO2 and, to a lesser extent Fe2O3, are photoactive which can result in accelerated photodegradation of the coating or plastic which is typically undesirable. Also, ZnO is chemically unstable to acids and bases. Furthermore, Fe2O3 can lead to coloration and ZrO2 does not absorb UV(A).

Curable film-forming composition exhibiting improved resistance to degradation by ultraviolet light

Abstract: A multi-component composite coating composition is also provided, comprising a pigmented basecoat and a clear coat. The basecoat and/or clearcoat may be derived from the curable film-forming composition described above.

Abstract: Also provided are coated substrates in which the curable coating compositions or the multi-component composite coating compositions described above are applied to a substrate and cured to form a cured coating.

Abstract: Further provided is a pigment comprising particles having a mean particle size less than 100 nm and comprising 1 to 99 percent by weight metal oxide wherein the metal is selected from zinc, titanium, cerium, manganese, bismuth, copper, zirconium and iron and 1 to 99 percent by weight silica. These particles may be used in the curable film-forming compositions described above.


In accordance with an embodiment, a method for manufacturing a semiconductor component includes providing a semiconductor material having a surface and forming a passivation layer on the semiconductor material Portions of the passivation layer are removed and portions of the semiconductor material exposed by removing the portions of the passivation layer are also removed. A layer of dielectric material is formed on the passivation layer and the exposed portions of the semiconductor material and first and second cavities are formed in the layer of dielectric material. The first cavity exposes a first portion of the semiconductor material and has at least one step shaped sidewall and the second cavity exposes a second portion of the semiconductor material. A first electrode is formed in the first cavity and a second electrode is formed in the second cavity.

In the past, the semiconductor industry used various different device structures and methods to form semiconductor devices such as, for example, diodes, Schottky diodes, Field Effect Transistors (FETs), High Electron Mobility Transistors (HEMTs), etc. Devices such as diodes, Schottky diodes, and FETs have been manufactured from compound semiconductor substrates such as, for example III-N materials. Drawbacks with semiconductor devices made from III-N materials such as gallium nitride (GaN)/aluminum gallium nitride (AlGaN) materials include high reverse leakage currents and low reverse breakdown voltages. To overcome these drawbacks, semiconductor manufacturers have used a dielectric layer at the anode of the device to reduce the reverse leakage current. U.S. Patent Application Publication Number 2011/0133251 A1 by Zhi He published on Jun. 9, 2011, describes using a dielectric layer at the anode to reduce the reverse leakage current. Although He teaches a technique to mitigate a high reverse leakage current, the issue of a low reverse breakdown voltage remains.
Accordingly, it would be advantageous to have a structure and method for manufacturing a semiconductor component using a III-N semiconductor substrate that addresses the performance specifications and manufacturability. It would be of further advantage for the structure and method to be cost efficient to implement.
For simplicity and clarity of illustration, elements in the figures are not necessarily to scale, and the same reference characters in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor or a cathode or anode of a diode, and a control electrode means an element of the device that controls current flow through the device such as a gate of an MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain n-channel or p-channel devices, or certain n-type or p-type doped regions, a person of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with embodiments of the present invention. It will be appreciated by those skilled in the art that the words during, while, and when as used herein are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay, such as a propagation delay, between the reaction that is initiated by the initial action. The use of the words approximately, about, or substantially means that a value of an element has a parameter that is expected to be very close to a stated value or position. However, as is well known in the art there are always minor variances that prevent the values or positions from being exactly as stated. It is well established in the art that variances of up to about ten percent (10%) (and up to twenty percent (20%) for semiconductor doping concentrations) are regarded as reasonable variances from the ideal goal of exactly as described.

SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC


An electric drum brake comprising: an electric motor including an armature for providing actuation force for the electric drum brake and a backing plate comprising a substantially flat disk portion, a support section located radially outward from a center of the flat disk portion and a substantially cylindrical wall projecting out of the support section as a continuous structure thereof, wherein an armature for the electric motor is located substantially within the substantially cylindrical wall.

One known alternative to a hydraulic drum brake is an electric drum brake, examples of which are set forth in U.S. Pat. Nos. 5,310,026, 5,219,049, 5,024,299 and 5,000,297. The electric drum brake typically includes an electric motor that drives an actuator for converting the rotational motion of the motor to linear motion output. The linear motion output of the actuator acts, through one or more levers, on the brake shoes, causing the desired release and apply of the brake shoes against the brake drum.


A dual input mode liquid crystal display having high resolution and employing dynamic capacitance compensation (“DCC”) is provided. The liquid crystal display includes a timing controller including a DCC processing unit for applying dynamic capacitance compensation (“DCC”) to a part of the pixels, a timing redistribution block for converting a format of the DCC-applied data to a predetermined format for a source driver, and a control signal generating block for generating a control signal for displaying an image. Since the DCC processing unit uses only two frame memories, the DCC may be employed by a dual input mode LCD. In addition, since a clock frequency for data processing in the frame memory of the timing controller is preferably the same as the clock frequency in the timing controller of the dual input mode LCD, thereby preventing the increase of EMI.

1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly to a dual input mode liquid crystal display having high resolution and performing dynamic capacitance compensation ("DCC").
2. Description of the Related Art
Lighter and thinner personal computers or television sets require lighter and thinner display devices. Since flat panel displays such as liquid crystal displays ("LCDs") satisfy such requirements, the LCDs have been developed and put to practical use in a variety of fields instead of cathode ray tubes ("CRTs").
LCDs display desired images by applying an electric field to a liquid crystal layer with dielectric anisotropy between two panels and adjusting the strength of the electric field to control the transmittance of incident light onto the panels.
LCDs are used in notebook computers as well as desktop computers. Computer users desire to see moving pictures by using the computers provided with developed multimedia environments. Thus, it is necessary to improve the response speed of the LCDs.
One exemplary technique for improving the response speed of the LCDs is dynamic capacitance compensation ("DCC"). Now, DCC will be described in detail.
The DCC processes RGB data by comparing gray value for a pixel in a previous frame with gray value for a pixel in a current frame and adding a predetermined value larger than the difference between the gray values to the gray value of the previous frame. A typical duration of one frame is 16.7 msec. Since it takes a time for a liquid crystal material in a pixel to respond to an applied voltage, time delay is inevitable until a desired gray is displayed. The DCC minimizes the time delay by applying a voltage larger than the predetermined voltage for a given gray to the pixel.
FIG. 1 shows an exemplary DCC processing unit of a conventional single input mode LCD. The DCC processing unit is in a timing controller of an LCD and is a part of a data processing block.
A single input mode LCD transmits one data for one clock, while a dual input mode LCD transmits two data for one clock. The dual input mode LCD has an advantage of reducing the clock period by half relative to the single input mode LCD. Accordingly, the dual input mode LCD simultaneously transmits both even and odd image data for one clock.
Referring to FIG. 1, the DCC processing unit includes a DCC block 11, a memory controller 12 and frame memories A and B 13 and 14.
The DCC block 11 receives current frame data from an external graphic source and previous frame data from the frame memory B 14 via the memory controller 12. The DCC block 11 compares the current frame data and the previous frame data and outputs DCC converted data selected from a built-in look-up table ("LUT") based on the result of the comparison. The optimal DCC data for the current frame data and the previous fame data is given in the LUT. The current frame data is stored in the frame memory A 13 under the control of the memory controller 12. As described above, a conventional single input mode LCD performing the DCC requires two frame memories for respectively storing the current frame data and the previous frame data. Typically, LCDs having low resolutions such as VGA or WXGA grade resolution are single input mode LCDs, while LCDs having high resolutions equal to or more than SXGA grade resolution, which has the greater number of data lines and thus requires high clock frequency for data processing, are dual input mode LCDs.
FIG. 2 shows an exemplary DCC processing unit of a conventional dual input mode LCD. The DCC processing unit is in a timing controller of the LCD.
A DCC processing unit shown in FIG. 2 includes two sub-DCC processing units each processing even data or odd data and having substantially the same configuration as the DCC processing unit shown in FIG. 1. A first sub-DCC processing unit includes a DCC block 21, a memory controller 22, a frame memory C 23 and a frame memory D 24, and processes even data of a current frame. A second sub-DCC processing unit includes a DCC block 31, a memory controller 32, a frame memory A 33 and a frame B 34 and processes odd data of the current frame.
As shown in FIG. 2, the dual input mode LCD employing the DCC requires four frame memories 23, 24, 33, and 34 and thus has a problem of the increased number of frame memories. To solve the problem of the increased number of frame memories, it is suggested that the high resolution LCD employs the single input mode while its timing controller increases the data processing clock frequency. However, the high data processing clock frequency causes electromagnetic interference ("EMI"), which enforces to introduce a filter between the timing controller and the frame memory. This increases the area of a printed circuit board for mounting the timing controller thereon as well as a product cost.

Liquid crystal display and driving method thereof


A process of preparing foods using granular pregelatinized starch produced by high-pressure at a pressure form 350 MPa to 800 MPa and a temperature of -5 C. to 45 C. The starch can be treated with high pressure within the food product itself, and the food product may be hermetically sealed in a retail package during the pressure treatment.

Starch pastes or gelatinized starches are generally produced by heating aqueous starch suspensions, i.e., those containing sufficient water excess, at temperatures above the so-called gelatinization temperature. This gelatinization temperature is dependent on the type of starch, and is generally markedly above 50.degree. C. The starch granules which occur as discrete partially crystalline particles swell intensely in this process. While some of the starch polymers (in particular the amylose) go into the solution, the insoluble, swollen, amylopectin-rich particles produce a matrix, which can no longer be separated into individual particles by conventional techniques. Accordingly, the physical properties of the starch pastes or gels thus obtained are determined by this matrix of dissolved amylose and swollen particles.
During the drying, and in particular during the roller drying which is preferably used for the production of gelatinized starches, the structure present in the pastes is further destroyed. In the gelatinized starches thus obtained, the granular structure is completely destroyed at the latest by the grinding of the film taken off from the roller. However, gelatinized starches produced in this manner are cold-swelling, in contrast to native starches.
In the light of this background, two processes have been developed, by means of which destruction of the granule shape and size caused by the swelling can be prevented, but nevertheless pregelatinization, i.e., cold swelling properties, of the starch granules can be achieved. The starches thus obtained are called "granular cold-water-swelling starches" (GCWS starches) and have special properties because of their granular character.
These granular cold-water-swelling starches are either produced by pregelatinization during spray-drying or by heating in alcohol-water mixtures. In the first process, the drying process follows the pregelatinization process so rapidly that swelling and aggregation of the granules is prevented. In the alcohol-water mixtures, the water content is sufficient for a complete gelatinization, but, at the same time, the alcohol content is high enough to prevent swelling.
A particular property of such GCWS starches is, for example, that very smooth pastes are retained therefrom, a property which is of interest particularly in the production of low-fat systems, i.e., in systems in which fat is fully or partially replaced by starch. It is thought that the granular character of these starches, which simulates fat droplets, is essential for this application.
Granular starch pastes and gels containing granular pregelatinized starch granules today cannot be produced directly, but can be produced only by the processes described above, in which they are obtained as pulverulent dry products. In this context, the above mentioned swelling which begins immediately in the presence of excess of water is, of course, one reason, but not the principal reason, why it is possible to produce GCWS-starches only by these specific processes. An even more critical fact is that the individual starch granules present in a starch suspension gelatinize, i.e., swell, at different temperatures. Usually, the last granules of a suspension only gelatinize at a temperature about 10.degree. C. above that of the beginning of gelatinization. This means that a uniform gelatinization can never be achieved, not even with an extremely precise temperature control.
Pastes of native starches produced in the conventional manner by heating in excess of liquid are, depending on the type of starch, clear (e.g., potato starch or waxy maize starch) or are opaque to a greater or lesser extent (e.g., maize starch), but, in comparison with a finely dispersed emulsion containing fat droplets, they are always transparent. In order to obtain a higher "whiteness power" in the case of starch-based fat substitutes, a number of processes have been proposed. Products obtained by these processes can be classified as so-called "microparticulates," i.e., discrete particles of approximately the size of the fat droplets present in emulsions.
A number of similar products are described in the literature and patent literature. These products share the property that the crystalline parts of the starch granule were enriched. Retention of a certain crystallinity is therefore essential for (starch-based) microparticulates. (In addition, protein- and cellulose-based products of this type have also been developed.)
However, because of the particular properties of pastes containing pregelatinized, restricted swollen starch granules (and furthermore still partially crystalline), there is great interest in producing pastes of this type directly, and not via spray-drying or via an alcohol-water treatment.
Surprisingly, it has now been found that this can be achieved. Moreover, pastes of this type can be produced directly in a very simple manner, by using high pressures.
The high-pressure treatment of starch is known in principle.
In Carbohydrate Research 93: 304-307 (1981), the effect of high pressure on the gelatinization temperature of starch has been investigated. Up to about 1500 atm, the gelatinization temperature is displaced upwards by increase in pressure by 3-5.degree. C./100 atm. Pressures higher than 2500 atm could not be investigated in this study.
In Carbohydrate Polymers 2: 61-74 (1982), microscopic and DSC (differential scanning calorimetry) studies report the effect of pressure in the range from 200-1500 MPa on the gelatinization of wheat starch and potato starch. In contrast to the publication above, the hydrostatic pressure is said to decrease the gelatinization temperature. Except for the specimens containing little water, there is said to be no great effect of pressure on the product properties (staining, behavior under the polarization microscope, later gelatinization at atmospheric pressure).
This latter finding is confirmed in Carbohydrate Polymers 2: 91-102 (1982), according to which a slight increase in the gelatinization temperature was observed only at the beginning, which then remained constant in the pressure range 150-250 MPa, and which decreased slightly at higher pressures up to 400 MPa.
Further studies, such as those described in Starke 45: 19-24 (1993), carried out in a DSC apparatus with barley starch and potato starch at low water contents (10-34%) and high temperatures (50-250.degree. C.), show that, under these conditions, higher enthalpy values are required for gelatinizing the starch.
From these partly contradictory literature data, which furthermore are only based on studies carried out with microquantities, few conclusions can be drawn for the use of high-pressure-treated starches in industrial practice.


A circuit for compensating for an offset voltage in a PhotoDetector Integrated Circuit (PDIC). The circuit includes a temperature detection unit, a current transfer unit and a current adjustment unit. The temperature detection unit generates a current that varies with variation in surrounding temperature. The current transfer unit transfers the generated current. The current adjustment unit adjusts the current transferred from the current transfer unit at a predetermined ratio and outputs the adjusted current.

1. Field of the Invention
The present invention relates generally to a circuit and method for compensating for variation in an offset voltage depending on variation in temperature in a photodiode integrated circuit and, more particularly, to a circuit and method capable of compensating for variation in an offset voltage depending on variation in surrounding temperature by adding a circuit for varying currents flowing through bipolar junction transistors, the characteristics of which varies with variation in surrounding temperature, according to variation in temperature.
2. Description of the Related Art
Recently, optical storage technology is developing toward high density, high speed and compactness in technical competition with memory, hard disk and magnetic disk technology, and the importance of the optical storage technology is increasing due to advantages over other storage technologies.
Such optical storage technology uses a method in which a disk drive and a storage medium (that is, an optical disk) are detachably attached to each other. The storage medium has advantages in that it can be implemented at low cost compared to other storage media, and data can be permanently stored thereon. In particular, the durability of the optical storage medium against temperature and impact is known to be excellent compared to that of other storage media.
However, the optical storage technology is disadvantageous in that its transmission rate is low and its storage capacity is low. To overcome the disadvantages, high-capacity and high-speed optical storage technologies rivaling a magnetic disk have recently been developed with rapid technological advances. Currently, research into a PhotoDetector Integrated Circuit (PDIC), that is, one of optical storage technologies, is being conducted.
FIG. 1 is a schematic diagram of a typical PDIC.
As shown in FIG. 1, the PDIC generates a current Iph when light is incident on a light-receiving element, for example, a photodiode 10. The current Iph is converted into a voltage and is amplified by a current-voltage conversion amplifier 20 and a feedback resistor RF, so that an output voltage VOUT is output.
When an input optical signal is 0, that is, when an optical signal input to the photodiode 10 does not exist, the output voltage VOUT must be 0 V ideally. However, a current flows from the inverting and non-inverting input terminals of the current-voltage conversion amplifier 20, and a voltage that is applied to the feedback resistor RF appears at an output terminal, so that the output voltage VOUT is not 0. In this case, the applied voltage is referred to as an offset voltage.
In the prior art, to compensate for such an offset voltage, a method of compensating for the offset voltage by reducing the magnitude of an offset current flowing from the inverting and non-inverting input terminals is used.
As an example, FIG. 2 shows the construction of a conventional current-voltage conversion amplifier 20 including a compensation circuit 21.
The current-voltage conversion amplifier 20 has a non-inverting input terminal (+) and an inverting input terminal (−). A reference character RF of FIG. 1 corresponds to a feedback resistor. Metal-Oxide-Silicon Field Effect Transistors (MOSFETs) P7 and P8 constitute an active resistor 24. A capacitor C1 is a circuit element for compensating for frequency characteristics.
When no optical signal is incident on the photodiode that is connected to the non-inverting input terminal (+), an offset current IB1 flowing from the base terminal of a transistor Q1, which is a Bipolar Junction Transistor (BJT), generates the offset voltage.
For convenience of description, it is assumed that the magnitude of the offset current flowing from the non-inverting terminal (+) is 1 μA. Constant current values of 100 μA, 50 μA and 50 μA are set on MOSFETs P1, P2 and P3, respectively, by a bias stage.
Accordingly, when constant currents IC1 and IC2 flowing through transistors Q1 and Q2, which are identical BJTs, each are 50 μA, and the amplification factor of the transistor Q1 is 50, the offset current IB1 is 1 μA. That is, when the compensation circuit does not exist, the offset current IB1 is 1 μA.
Meanwhile, the current I1 of 50 μA flowing through the MOSFET P3 also flows through a transistor Q3. Assuming that the amplification factor of the transistor Q3 is 50, the base current IB4 of the transistor Q3 is 1 μA. A current division unit 23 is composed of current mirror circuits, and the MOSFETs P4 and P5 and MOSFETs P4 and P6 constitute two pairs of current mirrors. In the current division unit 23, a current IB3 flowing through the MOSFET P4 is divided into halves of the current IB3, that is, 0.5 μA, and is then mirrored. The mirrored currents 0.5 μA are applied to the non-inverting input terminal (+) and the inverting input terminal (−), and the current compensates for the offset current IB1, so that the current of the base terminal of the transistor Q1 is 0.5 μA.
Since the compensation current is 0.5 μA and the current flowing from the non-inverting input terminal (+) is 1 μA, the offset current is 0.5 μA.
The offset voltage VOUT is affected by the magnitude of the offset current IB1, and the magnitude of the offset current BI1 is reduced by the compensation circuit 21. As a result, variation in the output voltage VOUT, which is affected by the magnitude of the offset current, decreases even though variation occurs due to arbitrary factors.
Meanwhile, of the elements constructing the current-voltage conversion circuit 22, BJTs O1, Q2 and Q4 have base-emitter voltages that are affected by variation in surrounding temperature, so that the base-emitter voltage VBE decreases by about 2 mV whenever the surrounding temperature increases by 1° C., and the base-emitter voltage VBE increases by 2 mV whenever the surrounding temperature decreases by 1° C.
The case of the transistor Q4 is described below. When the surrounding temperature increases, the current IC4 flowing through the transistor Q4 is constant at 50 μA because the base-emitter voltage VBE of the transistor Q4 decreases and the current IC4 is fixed at 50 μA by a bias applied to the MOSFET P2 regardless of the variation of the base-emitter voltage VBE, so that the output voltage VOUT increases.
In contrast, when the temperature decreases, the base-emitter voltage VBE of the transistor Q4 increases, and the current IC4 flowing through the transistor Q4 is constant at 50 μA, so that the output voltage VOUT decreases.
As described above, when the output voltage varies, the operation of the circuit, which is designed to be optimized for a constant offset voltage, is affected by variation in surrounding temperature.
As shown in FIG. 2, the circuit having the conventional compensation circuit 21 does not directly compensate for variation in the offset voltage depending on variation in surrounding temperature, and only reduces the magnitude of the offset current in proportion to the offset voltage, thus causing only an effect of reducing the variation in the offset voltage depending on variation in temperature.
In the circuit including the BJTs, a compensation circuit, which allows a constant operation regardless of the variation in temperature by compensating for the variation in the magnitude of the output voltage generated depending on variation in surrounding temperature, is required.
In relation to such a compensation circuit, Japanese Unexamined Pat. Pub. No. 11-68476 discloses a scheme of correcting an offset voltage by applying an offset setting voltage to the substrate of a MOSFET that constitutes a differential amplifier as an example of a scheme for compensating an offset voltage.
Although the disclosed scheme may be a next best measure for compensating for operational variation depending on variation in temperature, it does not provide a direct solution to the problem caused by variation in the operational value of elements depending on variation in temperature.

Circuit and method for compensating for offset voltage


When a current flows through a battery, a resistance loss proportional to the square of the current is produced by an internal resistance component of the current. In a case where the temperature of a heat capacity element is raised, a charging current is controlled such that prescribed thermal energy is provided to the heat capacity element by this resistance loss. Air is induced into a power supply unit through a vehicle compartment air exhaust duct. Then, the thermal energy stored in the heat capacity element is transferred to the air induced into the power supply unit. The air to which the thermal energy has been provided from the heat capacity element is blown out toward a vehicle compartment space by a fan.

So-called electric vehicles such as electrical vehicles, hybrid vehicles or fuel cell vehicles are equipped with a power storage device made up of a secondary battery, a capacitor or the like, and generate driving force from electric power stored in the power storage device through a motor.
A configuration has been proposed in which the power storage device mounted on these electric vehicles is charged by an external power supply such as a system power supply or a solar cell. As for a hybrid vehicle, in particular, if the cost of charging by an external power supply is lower than that of electric power generation by a mounted engine, the overall driving cost can be suppressed by charging the power storage device by the external power supply.
The power storage device is often formed of a secondary battery utilizing the electrochemical action, and the charge/discharge characteristics thereof are significantly affected by temperature. Therefore, a configuration has been proposed in which a reduction in temperature of the power storage device is suppressed in the electric vehicle where the power storage device is configured to be rechargeable by the external power supply.
For example, Japanese Patent Laying-Open No. 08-214412 discloses a charge control apparatus for a power storage device for use on an electric vehicle including: a charging period calculating means for calculating a necessary charging period based on an amount of electric energy discharged from the power storage device for use on the electric vehicle when charging is commanded, a detected power supply voltage value and a predetermined charging current value; and a charging start time calculating means for calculating a charging start time to finish the charging at the indicated scheduled boarding time based on the indicated scheduled boarding time and the calculated necessary charging period. According to the invention disclosed in this Japanese Patent Laying-Open No. 08-214412, since the charging is finished at the scheduled boarding time, the period of time for which the power storage device is left to stand after it has been charged will be short, and any reduction in the capacity due to a temperature drop can be small.
In the electric vehicle put to practical use, however, it is also necessary to ensure not only the power storage device but also the passenger comfort. In other words, in winter, summer and the like, air-conditioning (heating or cooling) of a vehicle compartment space is required. This air-conditioning in the vehicle compartment requires a relatively large power source. Therefore, electric power to be used for generation of vehicle driving force is used for air-conditioning in the vehicle compartment, and the traveling performance may be restricted due to the power storage device. In other words, out of an amount of electric energy stored in the power storage device, an amount of electric energy that can be ensured for vehicle traveling may be decreased, and the distance that can be traveled may be shortened. Furthermore, out of electric power that can be discharged from the power storage device, electric power that can be ensured for vehicle traveling may be decreased, and the driving force that can be generated may be reduced.

Electric vehicle and vehicle charging system


A method to determine a desired thickness for a surface layer through which ion implantation will take place in order to control the shape of the implantation profile to minimize the formation of flaws includes choosing a maximum angle .theta. between solid phase epitaxial regrowth fronts, determining a projected range of ion implantation distance Rp into the substrate and a projected standard deviation .DELTA.Rp along a first axis direction and a projected standard deviation .DELTA.Y along a second axis direction. These values are then substituted into the following equation to solve for thickness t of the surface layer: t=Rp+cos.theta.[[(.DELTA.Y sin .theta.).sup.2 +(.DELTA.Rp cos .theta.).sup.2 ].sup.0.5 ] After the layer is placed onto the substrate, the implantation step is carried out. Annealing is then performed to recrystallize the amorphous zone. The morphology of the surface being implanted through can also be modified in order to control the directions of recrystallization upon annealing.

1. Field of the Invention.
The present invention relates to a method for reducing the likelihood that defects form during semiconductor device fabrication. More particularly, the present invention relates to a method for limiting defect formation by controlling the morphology of an implantation profile in a semiconductor substrate.
2. Description of the Related Art
There is a continuing trend toward increasing the storage density of integrated circuit memories to provide increased levels of data storage on a single chip. Higher density memories provide storage that is generally more compact and is often cheaper on a per bit basis than an equivalent amount of storage provided on plural chips. It has generally been possible to provide these higher levels of storage at equivalent or improved levels of performance as compared to earlier, less dense chips. Historically, the density of integrated circuit devices has been increased in part by decreasing the size of structures such as wiring lines and transistor gates and by decreasing the separation between the structures which make up the integrated circuit device. Reducing the size of circuit structures is generally referred to as decreasing the "design rules" used for the manufacture of the integrated circuit device.
In dynamic random access memories (DRAMs), information is typically stored by selectively charging or discharging each capacitor of an array of capacitors formed on the surface of a semiconductor substrate. Most often, a single bit of binary information is stored at each capacitor by associating a discharged capacitor state with a logical zero and a charged capacitor state with a logical one. The surface area of the electrodes of the memory capacitors determines the amount of charge that can be stored on each of the capacitors for a given operating voltage, for the electrode separation that can reliably be manufactured, and for the dielectric constant of the capacitor dielectric typically used between the electrodes of the charge storage capacitor. Read and write operations are performed in the memory by selectively coupling the charge storage capacitor to a bit line to either transfer charge to or from the charge storage capacitor. The selective coupling of the charge storage capacitor to the bit line is typically accomplished using a transfer field effect transistor (FET). The bit line contact is typically made to one of the source/drain electrodes of the transfer FET and the charge storage capacitor is typically formed in contact with the other of the source/drain electrodes of the transfer FET. Word line signals are supplied to the gate of the FET to connect one electrode of the charge storage capacitor through the transfer FET to the bit line contact facilitating the transfer of charge between the charge storage capacitor and the bit line.
FIG. 1 shows in schematic cross-section two memory cells of a DRAM at an intermediate stage of manufacture. The illustrated DRAM cells are formed on a P-type substrate 10 and include thick field oxide regions 12 to provide isolation from other, adjacent memory cells. A gate oxide layer 14 is formed by thermal oxidation on part of the active device region between the field oxidation regions and polysilicon gate electrodes 16 are formed on the gate oxide layer 14. The two gate electrodes 16 illustrated in FIG. 1 are part of two independent transfer FETs for the two illustrated memory cells. Polysilicon gate electrodes 16 are formed by depositing a layer of undoped polysilicon over the substrate, typically using low pressure chemical vapor deposition (LPCVD), and then implanting impurities into the polysilicon and activating the impurities to render the polysilicon layer conductive. The gate electrodes are then patterned using conventional photolithography techniques. A layer of silicon oxide 18 is provided over the polysilicon gate electrodes 16 to protect the gate electrodes in subsequent processing steps and, often, to serve as an etch stop for subsequent etching steps. Sidewall oxide spacer structures 20 are also provided adjacent the gate electrodes during the source/drain implantation process (discussed below). At the same time that the gate electrodes 16 are formed, wiring lines 22 which connect different gate electrodes are formed on field oxide regions 12. Because the wiring lines are generally formed in the same process used to form the gate electrodes 16, the wiring lines have a similar structure consisting of polysilicon lines 22 covered by oxide layers 24 with sidewall oxide spacer structures 26 formed alongside the wiring lines 22.
Doped source/drain regions 28, 30 and 32 are formed on either side of the polysilicon gate electrodes 16 to define the channel regions of the transfer FETs. The source/drain region 30 that is common to the transfer FETs will serve as the bit line contact for the two illustrated memory cells. Lightly doped drain (LDD) structures are often used in small design rule memory transistors of the type that are primarily used in modem memory and logic devices. LDD source/drain regions 28, 30 and 32 are typically formed in a two step process, beginning with a relatively low level dopant implantation made self-aligned to the polysilicon gate electrodes 16. Spacer oxide regions 20 are then formed on either side of the gate electrodes 16 by first depositing a layer of CVD oxide over the device and then anisotropically etching back the oxide layer to expose the substrate over the source/drain regions 28, 30 and 32. Etching back the CVD oxide layer produces the spacer oxide regions 20 on either side of the polysilicon gate electrodes 16 and on either side of the polysilicon wiring lines 22. After the spacer oxide regions 20 are provided on either side of the polysilicon gate electrodes 16, a second, heavier ion implantation is made into the source/drain regions 28, 30 and 32 self-aligned to the spacer oxide regions 20 to complete the source/drain regions.
After the formation of the transfer FETs of the DRAM cells, processing continues to form the charge storage capacitors and the bit line contacts by first depositing an insulating silicon oxide layer 34 over the FIG. 1 structure using chemical vapor deposition (CVD). The resulting structure is shown in FIG. 2. Openings 36 are then formed by conventional photolithography through the silicon oxide layer 34 to expose the source/drain regions 28, 32 of the substrate. Referring now to FIG. 3, a layer of undoped polysilicon 38 is next deposited by low pressure chemical vapor deposition (LPCVD) over the surface of the device and within the openings 36 in contact with source/drain regions 28, 32. Polysilicon layer 38 will form part of the lower electrode of the charge storage capacitor for the DRAM memory cells. The layer is doped by ion implantation and annealing and then the lower electrodes 38 are defined by photolithography. A capacitor dielectric layer 40, such as a two layer structure of silicon nitride and silicon oxide, is provided over the surfaces of the lower electrodes 38. Upper capacitor electrodes 42 are formed by depositing, doping and patterning a layer of polysilicon, producing the structure illustrated in FIG. 4.
Processing continues by blanket depositing a layer of interlayer dielectric material, such as a doped glass deposited by atmospheric pressure CVD from a TEOS source gas, over the FIG. 4 structure. A bit line contact 46 is opened through the dielectric layer 44 by conventional photolithography to expose the common source/drain contact 30. The bit line contact 50 is then formed, typically by providing an additional bit line contact ion implantation and then providing one or more layers of metal sputter or CVD deposited over the surface of the layer 44 and within the opening 46 as illustrated in FIG. 5. The bit line is then patterned and further processing is performed to complete the device.
Reducing the design rules used for forming the device illustrated in FIG. 5 places heightened demands on many of the structures illustrated in FIG. 5, along with the processing techniques used for forming the structures. The formation of source/drain regions becomes more critical because of the comparatively shallower and narrower source/drain regions that are incorporated in reduced dimension memory cells. There is a greater need to control implantation energies and the extent of diffusion of source/drain regions to achieve small device sizes. There is also a need to maintain highly conductive source/drain regions to maintain the high performance of these structures. An aspect of maintaining high conduction levels is preventing the formation of defect structures in the source/drain regions.
Several types of crystal lattice defect structures may be formed in the processes of implanting dopant ions into semiconductor substrates and annealing the substrates to activate the implanted dopants. The ion implant doses used in forming many semiconductor circuit components may render amorphous the crystalline silicon semiconductor substrate into which the dopant ions are implanted. The substrate must subsequently be annealed to activate the implantation and often to recrystallize the amorphous zone. Recrystallization of implanted silicon substrates occurs by solid-phase epitaxial (SPE) regrowth. SPE regrowth is a process in which the substrate is heated to a temperature below the melting point of the substrate material. Crystal growth occurs by solid state transport and proceeds over the boundary between the crystalline (implanted or unimplanted) portion of the substrate and the amorphous, implanted region of the substrate. The recrystallization occurs incrementally, with the direction of recrystallization of each incremental amorphous region determined by the orientation of the crystalline region on which the recrystallization takes place. Thus, the orientation of the crystalline substrate at the interface of the crystalline region and the amorphous region will determine the directions of SPE regrowth.
Due to the shape of the boundary of the amorphous region, it is possible for SPE regrowth to proceed along different crystalline planes. Various studies have indicated that SPE regrowth occurring along different crystalline planes can result in the formation of defects in the crystal. For example, the merging of growth fronts corresponding to two different crystal planes can result in the formation of extended defect structures in recrystallized silicon substrates. Other forms of residual defects may be introduced into the crystal lattice, both from implantation and from other processes. For example, the presence of gate layers and sidewall spacer layers on the substrate can introduce compressive stresses on the underlying material, particularly during subsequent thermal processing steps. The presence of such stresses may generate defects such as dislocations and can lead to dislocation multiplication.
Certain types of defects known as projected range defects (PRDs) and end of range defects (ERDs) may be formed in implanted and annealed regions of the substrate. PRDs and ERDs are secondary defects (dislocations or line defects), with PRDs located near the region of maximum implanted ion concentration and ERDs located near the amorphous-crystalline interface after implantation. These defects are believed to result from vertical SPE regrowth of amorphous silicon, that is, regrowth perpendicular to the silicon surface, and the defects may include dislocation loops buried within the implanted region. The location and density of PRDs and ERDs are related to the energy and dose of the implanting ions. Another type of defect related to recrystallization of a silicon made amorphous through ion implantation is the mask edge defect (MED). It is believed that MEDs are dislocations resulting from the merging of recrystallization fronts of vertical and lateral SPE regrowth. During the annealing and recrystallization process, the dislocations formed from the merging SPE regrowth fronts tend to agglomerate as additional epitaxial layers are formed, with the defects growing into a structure that has been described as being similar to a grain boundary. This extended defect structure can affect electron transport if it is positioned along a primary direction of current flow. Such defect structures may be formed near the lateral edges of the implantation zone at or near the substrate surface, often at the location where a recrystallizing substrate surface adjoins another structure on the surface of the substrate, and can lead to junction leakage problems.

Method to inhibit the formation of ion implantation induced edge defects