A method and system for monitoring the capacity of a battery pack (6) is provided. The battery pack (6) is capable of delivering current to a load (R.sub.L). The battery pack (6) includes a monitor cell (C4) and battery cells (C1, C2, and C3). The monitor cell (C4) has a predetermined initial energy level that is lower than the predetermined initial energy level of the battery cells. A monitoring system (22) including an analog-to-digital converter (10) and a microprocessor (12) is connected to the battery pack and monitors the voltage of the battery pack. When the monitoring system detects a voltage change indicating depletion of the monitor cell (C4), the monitoring system provides a signal indicative that the battery pack is nearing depletion.

Batteries are often used to power portable electronic devices. After a period of use, the batteries in a portable device will become depleted and affect the performance of the portable device. When the energy level of the batteries falls below a certain threshold, the portable device will cease to operate. At this point, the batteries must be recharged or replaced. Accordingly, in many applications it would be beneficial to monitor the remaining charge in the batteries and alert the user of a portable device before the batteries are depleted.
One environment where monitoring the remaining charge in batteries is important is in portable external cardiac defibrillators. Portable cardiac defibrillators generate and apply a high energy defibrillation pulse to the chest of a patient to cause the patient's heart to stop fibrillating and return to a normal rhythm. Sometimes the application of a single defibrillation pulse fails to restore the patient's heart to a normal rhythm. In such an event, it may be necessary to apply additional defibrillation pulses. Portable external defibrillators generally use a battery pack containing a number of cells to power the defibrillator. The battery pack allows an energy storage capacitor to be charged in order to generate a defibrillation pulse. If the battery pack becomes depleted, the patient cannot be treated.
In order to assure that an external cardiac defibrillator is always ready for use, it is therefore advantageous to monitor the remaining charge in the battery pack. Battery monitoring provides an indication of when the battery pack is nearly depleted and needs to be replaced or recharged.
Various efforts in the prior art have been devoted to monitoring the remaining energy in a battery pack. One common approach entails measuring an output voltage from the battery pack while the battery pack is connected to an electrical load. As the battery pack is discharged, the voltage will typically drop. Variations of this approach involve measuring other battery parameters, such as the impedance of the batteries in the battery pack, to detect changes that indicate that the battery pack is nearing the end of its useful life.
One disadvantage of monitoring the output voltage from the battery pack to detect a drop in voltage is that the method is unable to accurately monitor the energy level of typical nonrechargeable batteries. FIG. 1 depicts the output voltage v from a single nonrechargeable lithium battery plotted with respect to time. The output voltage from the lithium battery remains relatively constant until near the end of its life t when the output voltage drops precipitously. Because of the steep drop in voltage, it is nearly impossible to give sufficient advance warning when the battery pack is nearly depleted. By the time the battery voltage begins to drop, insufficient energy often remains in the battery pack to power the electronic device for any appreciable period. This is especially true for devices which have a high energy utilization rate such as defibrillators.
Another approach for determining the remaining charge in a battery pack is disclosed in U.S. Pat. No. 5,483,165 to Cameron et al. Cameron et al. disclose a defibrillator having a main battery consisting of a number of identical battery cells connected in series. A sense cell is connected in series to the main battery. The sense cell is identical in type and manufacture to each of the main battery cells. A current flows through the main battery and the sense cell to a load. Because all the cells are identical, the sense cell and battery cells in the main battery should in normal circumstances be depleted at the same rate. However, Cameron et al. disclose a dedicated circuit for drawing additional, incremental current from the sense cell. The value of the incremental current equals the value of the current delivered to the load scaled by an arbitrary constant. The dedicated circuit drawing the incremental current includes a variable resistance connected between the sense cell and ground potential. The variable resistance is used to vary the value of the incremental current drawn from the sense cell.
The sense cell in Cameron et al. is used to estimate the remaining charge in the main battery. Since the sense cell is discharged at a quicker rate than the main battery, the voltage drop characteristic of battery cells at the end of their useful life will first occur on the sense cell. When the voltage drop on the sense cell is detected by a controller, a signal or other warning is generated to indicate that the main battery is also nearly depleted.
While the Cameron et al. approach offers some advantages over other prior art techniques for monitoring batteries, it also presents disadvantages. The need to draw an additional current from a sense cell adds undue complexity and, it will be appreciated, problems attendant with that complexity. For example, the Cameron et al. approach requires adding a dedicated voltage monitor and a variable resistance circuit to draw the incremental current from the sense cell. The additional components and battery contacts required to draw the incremental current increase the likelihood that a component in the battery monitoring system could fail and render the battery monitoring technique ineffective.
Apart from the increased likelihood of failure, the need to provide a voltage monitor and variable resistance poses other problems. The addition of the voltage monitor and the variable resistance increases the cost of a device incorporating the battery monitoring system. The voltage monitor and the variable resistance also add weight and size to the system.
The use of additional circuitry to draw an incremental current from the sense cell also limits the interchangeability of the type of battery cell incorporated in a battery pack. For example, if lithium battery cells are used in the battery packs, a certain incremental current must be used that corresponds to the anticipated voltage curve of the lithium battery cell. If there is an improvement in battery technology or if a user desires to use a different type of battery cell, such as a rechargeable nickel cadmium battery cell, a different amount of incremental current should be drawn from the new cell to correspond to the anticipated voltage curve of the new cell. An operator of the portable electronic device must therefore somehow adjust the amount of incremental current drawn depending upon the type of battery pack that is to be used in the device. The need to perform an additional adjustment limits the ease with which the user may select a type of battery suitable for a particular application.
In addition to monitoring the remaining charge in the battery pack, it would also be advantageous to monitor the health of the individual battery cells within the battery pack in order to detect a possible cell failure. Individual cell failures decrease the energy storage capacity of the battery pack and can also detrimentally affect the performance of the battery pack during discharge of the battery pack.
As can be seen from the discussion above, there exists a need for improved methods of monitoring the condition of battery packs. The present invention is directed toward addressing this need.

Method and system for monitoring the condition of a battery pack in a defibrillator


A processing method for a color film substrate, the color film substrate comprising a substrate, a photoresist layer, a conductive layer and a spacer layer. The photoresist layer is disposed on the substrate; the conductive layer is disposed on the photoresist layer and completely covers the photoresist layer; and the spacer layer is disposed on the conductive layer. The method comprises: detecting the spacer layer; determining whether the spacer layer meets a preset condition; if the spacer layer meets the preset condition, removing the spacer layer using a rework liquid medicine so as to expose the conductive layer; and re-preparing a spacer layer on the exposed conductive layer, wherein the etching selection ratio of the spacer layer to the conductive layer is greater than 1.

The statements in this section merely provide background information related to the present disclosure and may or may not constitute prior art.
With the continuous development of the society, liquid crystal display (LCD) technology has replaced the cathode ray tube (CRT) imaging technology to become the mainstream.
Generally, a liquid crystal display panel includes a color film substrate and an array substrate aligned with the color film substrate. A liquid crystal is provided between the color film substrate and the array substrate.
When preparing a spacer layer of the color film substrate, if the spacer layer continues to be used in the presence of technical defects, the quality of the entire color film substrate and even the liquid crystal display panel will be seriously affected.

Processing method and system for color film substrate


An imaging device detects an occurrence of a trigger event, stores images before and after the trigger event occurrence for a specified time and transmits them to an image management server. The image management server stores the image file and key information associated with the image file, the key information including information related to timing of the trigger event occurrence related to the image in an image DB. When the image management server receives a search condition, the image management server obtains an image file stored in association with the key information satisfying the designated search condition from the image DB.

1. Field of the Invention
The present invention relates to an image information management system and method which store images before and after a trigger with key information associated with the images and search the stored image based on the key information.
2. Description of the Related Art
A digital image can be recorded for a long time at present owing to expansion of storage capacity and price reduction of an apparatus. However, if all the events are recorded, when a desired image lasts only for a short time in the long-time image, the required information should be searched in the vast volume of information. In this case, there is a problem that time for searching necessary information becomes long. Then, an art to record only a required image and search a desired image in recorded images in a short time is in demand.
As a method of storing a required image, such an art is proposed that when a trigger occurs, an image before and after the occurrence of the trigger is recorded. For example, in Unexamined Japanese Patent Application KOKAI Publication No. 2005-165805, an art is disclosed that by storing images before and after a collision using a sudden speed change at the collision as a trigger, a situation at occurrence of the accident is recorded. However, Unexamined Japanese Patent Application KOKAI Publication No. 2005-165805 discloses an art to store a required image but does not describe an art to search and take out a desired image from the stored images.

Image information management system and method


Power supply circuitry is disclosed which suppresses changes in a converted voltage regardless of changes in a load state without substantially increasing the volume and weight of the power supply circuitry and raising the manufacturing cost. The circuitry has a direct current power source. A first DC-to-DC converter converts a voltage of the direct current power source. A smoothing filter smoothes the converted voltage of the first DC-to-DC converter and outputs it. The power supply circuitry further includes a power supply section. The power supply section has a voltage detecting portion for detecting a decrease in the converted voltage and outputs a voltage-decrease detection signal. A power holding portion charges capacitor devices with the converted voltage or a voltage of the direct current power source, and discharges the capacitor devices when a voltage-decrease detection signal is output. A second DC-to-DC converter converts an output of the power holding portion and synthesizes the converted output with the converted voltage of the first DC-to-DC converter. A predetermined voltage at which the voltage-decrease detection signal starts to be generated is set lower than the internal control voltage of the first DC-to-DC converter.

1. Field of the Invention
The present invention relates generally to power supply circuitry suitable for supplying driving power to a portable optical mark reader, such as a bar code scanner. More particularly, the invention relates to power supply circuitry which can minimize changes in voltages converted from voltages of a direct current power supply and supplied to a load even though the state of the load is considerably changed.
2. Description of the Related Art
Hitherto, for facilitating the operability of a portable optical mark reader, such as a bar code scanner, to enhance its portability, built-in batteries, such as miniature secondary cells and dry cells, are used as a power supply source. Further, in order to avoid enlargement of such a portable device, the number of built-in secondary cells and dry cells are reduced to a minimal level, and a direct-current-to-direct-current converter (DC-to-DC converter) compensates for shortage of cells and is provided for power supply circuitry to generate a voltage required for driving a load.
FIG. 4 is a circuit diagram illustrating an example of the configuration of conventional power supply circuitry for supplying power to a portable optical mark reader, such as a bar code scanner. The power supply circuitry is, as illustrated in FIG. 4, adapted to convert an output voltage of a built-in power supply source 41, such as a miniature secondary cell or dry cell, and to supply driving power to a load 45. The power supply circuitry has a DC-to-DC up-converter 42 for raising an output voltage of the built-in power source 41, a large-capacity shunt capacitor 43, and a ripple filter 44 for eliminating ripple components. The DC-to-DC up-converter 42 is formed of a series inductor 46, a field effect transistor (FET) 47, a Schottky barrier diode (SBD) 48, a self-excited oscillator circuit 49, an operational amplifier (OP) 50, a reference voltage source 51, and resistor dividers 52 and 53. The ripple filter 44 includes a series inductor 54 and a shunt capacitor 55. Moreover, the output terminal of the DC-to-DC up-converter 42, the input terminal of the ripple filter 42, and one end of the shunt capacitor 43 are connected to an output line 56.
A portable optical mark reader, such as a bar code scanner, driven by the aforedescribed power supply circuitry, enters a heavy-load mode and more specifically, the resistance of the optical mark reader is small as viewed from the power supply, when marks are read or the read marks are transmitted in remote control signals, such as light signals. In contrast, the optical mark reader enters a light-load mode, and more specifically, the resistance of the mark reader is large as viewed from the power supply, when in a standby position in which mark reading or remote-control signal transmitting is not performed.
FIG. 5 illustrates the operational states of the known power supply circuitry shown in FIG. 4 when the individual factors of the load 45 are significantly changed: FIG. 5a illustrates a change in the resistance (impedance) of the load 45; FIG. 5b illustrates a change in a load current flowing in the load 45; FIG. 5c illustrates a change in a load voltage applied to the load 45; and FIG. 5d is a change in an output current of the DC-to-DC up-converter 42.
The conventional power supply circuitry operates in the following manner when the resistance of the load 45 is large, i.e., under light-load conditions.
In the DC-to-DC up-converter 42, the self-excited oscillator circuit 49 generates a square-wave signal having a predetermined duty cycle and applies it to the gate of the FET 47. When this square-wave signal is at a positive level, the FET 47 is actuated to allow an inductor current I.sub.L to flow from the built-in power supply source 41 via the series inductor 46 and the FET 47, thereby charging the series inductor 46 with energy proportional to the inductor current I.sub.L. When the square-wave signal is changed to a negative level, the FET 47 is turned off to discontinue the flow of the inductor current I.sub.L. Instead, the charging energy supplied to the series inductor 46 is emitted to the output line 56 via the SBD 48 so as to generate a raised voltage corresponding to the charging energy in the output line 56. The increased voltage is then divided at the resistor dividers 52 and 53 and supplied to the non-inverting input terminal of the operational amplifier 50. In the amplifier 50, the voltage is compared with a reference voltage generated by the reference voltage source 51.
When the raised voltage is within tolerance of a prescribed voltage, the divided voltage fed to the operational amplifier 50 is substantially equal to the reference voltage, and the output of the operational amplifier 50 is a first voltage indicating that there is no difference between the voltages supplied to the two input terminals of the amplifier 50. The self-excited oscillator circuit 49 maintains the above-described predetermined duty cycle of the square-wave signal while the first voltage is being fed to the circuit 49.
If the increased voltage is lower than the tolerance of the prescribed voltage, the divided voltage supplied to the operational amplifier 50 is lower than the reference voltage to create a difference therebetween. The operational amplifier 50 then generates a second voltage obtained by adding a positive voltage equivalent to a difference between the divided voltage and the reference voltage to the first voltage. In response to this second voltage, the oscillator circuit 49 increases the predetermined duty cycle of the square-wave signal. This lengthens the actuation duration and shortens the inactuation duration of the FET 47, which further increases the energy charged to the series inductor 46 and elevates the energy output from the series inductor 46 accordingly. Control is exerted in this manner so that the increased voltage can be contained within the tolerance of the predetermined voltage.
In contrast, if the raised voltage is higher than the tolerance of the predetermined voltage, a divided voltage fed to the operational amplifier 50 is equally higher than the reference voltage to create a difference in a manner similar to the case where the increased voltage is lower than the reference voltage. Thus, the operational amplifier 50 generates a third voltage obtained by adding a negative voltage equivalent to a difference between the divided voltage and the reference voltage to the first voltage. In response to this third voltage, the oscillator circuit 49 decreases the predetermined duty cycle of the square-wave signal. This shortens the actuation duration and lengthens the inactuation duration of the FET 47, which further reduces the energy charged to the series inductor 46 and lowers the energy output from the inductor 46 accordingly. Control is exerted in this manner so that the increased voltage can be contained within the tolerance of the prescribed voltage, in a manner similar to the case where the increased voltage is lower than the prescribed voltage.
During the above-described operation, the increased voltage of the output line 56 is charged by the large-capacitance shunt capacitor 43 and is substantially averaged. Subsequently, the ripple components contained in the increased voltage are removed by the ripple filter 44, and the resulting voltage is then supplied to the load 45.
An explanation will now be given with reference to FIG. 5 of the operation of the known power supply circuitry when the resistance of the load 45 decreases, i.e., under heavy-load conditions.
During a first period from time t.sub.0 to t.sub.1, a portable optical mark reader, such as a bar code scanner, is in a standby mode, in which the resistance of the load 45 is large, as shown in FIG. 5a, i.e., under light-load conditions. In this state, a load current is small (minimum), as illustrated in FIG. 5b, while a load voltage is large (maximum), as shown in FIG. 5c. The output current of the DC-to-DC up-converter 42 is small (minimum), as illustrated in FIG. 5d.
At time t.sub.1, the portable optical mark reader is caused to transition from the standby mode to a mark reading mode or a remote-control signal transmitting mode. At this time, the resistance of the load 45 is sharply reduced, as shown in FIG. 5a, and the mode is abruptly changed from a light-load mode to a heavy-load mode. The load current is sharply changed from the minimum to a high level (maximum), as illustrated in FIG. 5b, while the load voltage starts to gently decrease from the maximum, as shown in FIG. 5c. The output current of the DC-to-DC up-converter 42 starts to gently increase from the minimum, as illustrated in FIG. 5d. The major portion of the load current at time t.sub.1 is discharging current from the shunt capacitor 43.
During a second period from time t.sub.1 to t.sub.2, the portable optical mark reader is set in the mark reading mode or in the remote-control signal transmitting mode. The resistance of the load 45 is small, as illustrated in FIG. 5a, under heavy-load conditions, while the load current progressively decreases from the high level (maximum), as shown in FIG. 5b. The load voltage progressively decreases, as illustrated in FIG. 5c, and the output current of the DC-to-DC up-converter 42 slightly increases, as shown in FIG. 5d. The load current during the second period initially maintains a comparatively large value because the major portion of the load current is discharging current from the shunt capacitor 43. However, when this discharging current is progressively decreased, the load current is also progressively lowered because a progressive decrease in the discharge current from the shunt capacitor 43 cannot be completely compensated with an increase in the current output from the DC-to-DC up-converter 42.
At time t.sub.2, the portable optical mark reader is returned to the standby mode from the mark reading mode or the remote-control signal transmitting mode. At this time, the resistance of the load 45 abruptly increases, as illustrated in FIG. 5a, under light-load conditions. In this state, the load current reduces to a low level (minimum), as shown in FIG. 5b, while the load voltage is caused to transition, as illustrated in FIG. 5c, from a low level to a high level. The output current of the DC-to-DC up-converter 42 starts to gently decrease, as shown in FIG. 5d. The load current at time t.sub.2 is part of the output current of the DC-to-DC up-converter 42 because the shunt capacitor 43 has completed discharging.
During a third period from time t.sub.2 to t.sub.3, the portable optical mark reader is maintained in the standby mode. At this time, the resistance of the load 45 is large, as shown in FIG. 5a, under the light-load conditions. In this state, the load current is maintained at a low level (minimum), as illustrated in FIG. 5b, while the load voltage sequentially increases, as shown in FIG. 5c, to finally return to the high level (maximum). The output current of the DC-to-DC up-converter 42 slightly decreases, as illustrated in FIG. 5d, to finally return to the low level (minimum).
In the aforedescribed known power supply circuitry used in a portable optical mark reader, the DC-to-DC up-converter 42 has a small current-supplying capability, as low as approximately 150 mA, because only a miniature secondary cell or a dry cell is used as the built-in power source. In contrast, the load current intermittently flows with extreme changes (for example, a duty cycle of 1/20 or smaller) by switching between the heavy-load condition and the light-load condition. Accordingly, the average current is 150 mA or smaller, which can be contained within the current-supplying capability of the DC-to-DC up-converter 42. However, the peak load current flowing in a short period of time (for example, 1 millisecond to 100 milliseconds) is approximately 1 A, which far exceeds the current-supplying capability of the DC-to-DC up-converter 42. The abovedescribed operation can be typically observed in power supply circuitry used in a portable optical mark reader as a load. In the aforedescribed known power supply circuitry, when the resistance of the load 45 is considerably changed, the load voltage sharply drops, thereby causing erroneous operation.
Hitherto, for preventing such erroneous operation, means for substantially maintaining the load voltage is provided in response to a significant change in the resistance of the load 45. Among the above known means, the most simple is to increase the capacitance of the shunt capacitor 43, for example, to raise it to approximately 80000 .mu.F. This is much larger than the averaged load current, which disadvantageously enlarges the volume of the power supply circuitry, thereby increasing the size and weight of the overall portable optical mark reader having the built-in power supply circuitry. Additionally, the manufacturing cost is increased.
Another means for substantially preserving the load voltage is to charge a capacitor under light-load conditions and to discharge the capacitor under heavy-load conditions so as to compensate for a decrease in the load voltage caused by heavy-load conditions with a discharging current generated by the capacitor. An example of such means is disclosed in Japanese Unexamined Patent Publication No. 4-251532.
Although this means can compensate for a decrease in the load voltage under heavy-load conditions, a charging current generated by a capacitor is primarily used to offset the load voltage. Accordingly, a considerably large-capacitance capacitor is required, thus enlarging the volume of the power supply circuitry. This further increases the size and weight of the overall portable optical mark reader having the built-in power supply circuitry. The manufacturing cost is also increased.

Double DC-DC converter having power holding portion


A high power AM-band transmitter amplifier comprises four switches in an H-Bridge configuration and operates by adjusting the duty cycle of the voltage waveform on a transformer. The duty cycle is adjusted by changing the phase relationship between the diagonal switch pairs. An embodiment of the amplifier operates efficiently by the addition of a current source that may comprise inductor and capacitor circuits to assure zero voltage switching of all the switches. The inventive H-Bridge configuration can also be utilized in a phase modulated power supply.

The present invention relates generally to an H-Bridge switching circuit that can be used in a power amplifier for a radio transmitter or a switching power supply.
It has been well known in the switching power supply industry that high efficiency systems can be designed by chopping a voltage to produce another voltage. Pulse width regulated power supplies operate at efficiencies in excess of 97%. However, the higher switching frequencies needed to operate in the AM band tend to increase switching losses. Also, it becomes difficult to turn FETs, which are commonly used in switching power supplies, on and off quickly enough when the duty cycle is small.
It has always been a goal to produce AM transmitters that will be more efficient. AM transmitters using two stages to do the modulation and the amplification of the audio signal are known and are suitable for handling transmitters up to a power of 10 kW. However, it is difficult to reach necessary efficiencies (e.g., 86%) using a separate modulator and amplifier for higher power level (e.g., 25 kW, 50 kW and 100 kW) transmitters. An amplification-modulation scheme that is much more efficient is required for the higher power levels.
One way to improve efficiency is to remove sections of the transmitter or to group different parts of the transmitter. In general, an AM transmitter comprises a power supply, modulator, power amplifier, combiner, and output network. Each of these parts has an associated energy loss that adds up to form the total system loss.
It is known to combine the modulation and the amplification into one stage to improve efficiency. To perform the modulation of the transmitters, known systems turn the amplifiers off and on. These amplifiers are added through RF combiner transformers on the output of each RF stage. This means that many amplifiers are needed to reduce the change in amplitude when one module is turned off or on. These systems prove impractical below the 10 kW power level because of the large number of amplifiers needed to apply this scheme.
A design known from U.S. Pat. No. 4,580,111 can operate fairly efficiently, however, one difficulty with this type of design is that it is only practical for high power (e.g., 10 kW and above—at, e.g., 9 kW watts and below, particularly at 5 kW and below, this circuit becomes increasingly impractical). To build this type of design, enough modules are needed so the step size in turning a module off and on will be small.

Phase to amplitude H-Bridge switching circuit


Embodiments of the present invention provide an ad-hoc query engine. The ad-hoc query engine comprises a query management module, a metadata module, a data cache module and a viewer module. The query management module receives a query request from a client device. The query request is specified in terms of a plurality of business objects. The query management module utilizes the metadata module to translate the business objects into a structured query language statement as a function of the content of the data cache module. The SQL statement comprises a plurality of aggregation. The query management module dynamically causes each aggregation to be re-directed to execute against the content of the data cache module, when the aggregation is locally or linearly computable from said content of said data cache module. The query management utilizes the viewer module to generate a report as a function of the results of the executed SQL statement.

Relational databases, according to the conventional art, can be utilized to store vast amounts of data. Efficiently capturing and manipulating the data into information is becoming more critical as storage capacity and computing power increases. The capturing of data and the manipulation of data to obtain information typically involves competing design considerations.
Accordingly, database systems delivering very large storage capacity and performant data querying typically comprise a data capture server, a database and an application server. The data capture server is dedicated to capturing data and saving it in the database. The application server is dedicated to running queries against the data saved in the database.
Referring to FIG. 1 a block diagram of an online analytic processing (OLAP) 110 type application server and a relational online analytic processing (ROLAP) 120 type application server according to the conventional art is shown. As depicted in FIG. 1, the ROLAP system 120 runs queries directly against either an online transaction processing (OLTP) type source database 130 or a data warehouse type source database 140. The ROLAP 120 type application server provides access to the most recently available data in the source database 130, 140. However, the performance of the system is reduced as a result of such queries running against the source database 130, 140. Furthermore, the end-user typically needs to be proficient with structured query language (SQL), or the like, to generate the particular report they desire.
The OLAP system 110 retrieves a pre-computed query from a data cube 150 in response to a query request from an end user. The data cube 150 is populated with a plurality of queries. The plurality of queries are pre-computed from either the OLTP database 130 or the data warehouse database 140. The OLAP 110 type application server provides increased performance by allowing queries to be pre-computed during times of low system utilization. Pre-computing the queries also typically relieves the end user from being versed in SQL. However, the data provided to the user is only as current as the last update of the pre-computed query results. Furthermore, if an end user desires a query that has not been pre-computed, they typically need an administrator to generate an appropriate query in SQL.


A method for fabricating a CMOS image sensor for preventing corrosion of a metal pad. The method for fabricating the CMOS image sensor can include sequentially forming a dielectric film, a metal pad having an opening, and a first passivation film on a semiconductor substrate having a scribe lane and a pixel region defined therein, forming a color filter layer on the first passivation film at the pixel region, forming an overcoat layer on the entire surface of the semiconductor substrate, including the metal pad, to reduce the step difference between the scribe lane and the pixel region, forming a micro lens on the overcoat layer at the pixel region, forming a photo resist to expose the overcoat layer at the scribe lane, performing an etching process on the entire surface of the semiconductor substrate to etch the overcoat layer at the scribe lane, and removing the photo resist by a cleaning process.

An image sensor is a semiconductor device for converting an optical image into an electric signal. The image sensor may be generally classified as a charge coupled device (CCD) and a CMOS image sensor.
The CCD may include a plurality of photodiodes (PDs) which are arranged in a matrix, each photodiode converting an optical signal into an electric signal. In the matrix of the photodiodes, a plurality of vertical charge coupled devices (VCCDs) are provided between the respective vertically arranged neighboring photodiodes to transmit electric charges, generated by the respective photodiodes, in a vertical direction, and a plurality of horizontal charge coupled devices (HCCDs) are provided to transmit the electric charges, transmitted by the respective vertical charge coupled devices, in a horizontal direction. Also, a sense amplifier is provided to sense the horizontally transmitted electric charges to output electric signals.
Disadvantages of the CCD include a complicated driving method, high electric power consumption, and a complicated manufacturing process requiring a multi-step photo process. Furthermore, the CCD has another disadvantage in that it is difficult to integrate a control circuit, a signal processing circuit, an analogue/digital conversion circuit (A/D converter), etc. in a CCD chip. This makes it impossible to achieve compact-sized products.
Recently, the CMOS image sensor has received much recognition as a next-generation image sensor to solve the problems of the CCD. The CMOS image sensor is a device employing a CMOS technology. The CMOS image sensor uses a control circuit, a signal processing circuit, etc. as peripheral circuits, such that MOS transistors, having the same number as unit pixels, are formed on a semiconductor substrate. The outputs of the respective unit pixels are sequentially detected by the MOS transistors by a switching method. Meaning, the CMOS image sensor is characterized in that a photodiode and a MOS transistor are formed in a unit pixel to sequentially detect electric signals of the respective unit pixels by a switching method, thereby achieving an image.
As a result of employing a CMOS fabrication technology, the CMOS image sensor has several advantages, for example, low electric power consumption, and a simplified fabricating process based on a reduced number of photo process steps.
Example FIGS. 1A to 1C illustrate a method for fabricating a CMOS image sensor and which may include dielectric film 11, such as a gate dielectric film or an interlayer dielectric film, formed on and/or over semiconductor substrate 10. Metal pad 12 for each signal line is formed on and/or over dielectric film 11. Passivation film 13, made of an oxide film or a nitride film, is formed on and/or over the entire surface of dielectric film 11, including metal pad 12.
As illustrated in example FIG. 1B, photosensitive film 14 is applied to the top of passivation film 13 and patterned by an exposure and development process to expose the top of metal pad 12. Passivation film 13 is selectively etched using the patterned photosensitive film 14 as a mask to form opening 15 at the exposed metal pad 12.
As illustrated in example FIG. 1C, a silicon nitride film or a silicon oxide nitride film is deposited on and/or over the entire surface of semiconductor substrate 10 to form planarization layer 16. Planarization layer 16 is selectively etched by a photo and etching process such that planarization layer 16 is left only at the remaining area excluding the metal pad. Color filter layers 17 are formed on and/or over planarization layer 16 corresponding to respective photodiode regions. The respective color filter layers are formed by applying respective color resists and performing a photolithography using an additional mask. Subsequently, overcoat layer 18 is formed on and/or over the entire surface of semiconductor substrate 10, including color filter layers 17. The remaining area, excluding metal pad 12, is selectively etched by a photo and etching process. A polymer material is then applied to the top of overcoat layer 18 to form a micro lens material layer. Photosensitive film 14 is patterned by an exposure and development process to define a micro lens region. Subsequently, the micro lens material layer is selectively patterned using photosensitive film 14 to form a micro lens pattern corresponding to color filter layers 17. The micro lens pattern is heat-treated by a reflow process to form hemispherical micro lenses 19 having a predetermined radius of curvature.
In the afore-described method for fabricating the CMOS image sensor, however, color filter layers 17 and planarization layer 16 form a sharp step between a scribe lane and a pixel region, before the formation of the micro lenses. Accordingly, the film thickness of the applied photo resist is non-uniform. The non-uniform thickness of the photo resist, in turn, causes non-uniformity in the thickness of micro lenses 19. For a spin coat type resist application, such non-uniformity of thickness causes striation in which radial stripes are formed outward from the center of a wafer. The striation causes defectiveness in which vivid stripes are diagonally formed on the CMOS image sensor.
Moreover, in the afore-described method for fabricating the CMOS image sensor, the metal pad is opened for connection with an external circuit, and then the process for forming the color filter layers and the micro lenses are carried out. All the processes are photolithography processes using a strong base developing solution, which may result in corrosion of the grounded metal pad.

Methods for fabricating CMOS image sensor


A data transfer circuit for coordinating transfer of data between a host and a disc of a disc drive having a state machine for coordinating with a buffer controller to transfer data between the host and a buffer segment and a second state machine for coordinating with the buffer controller to transfer data between the buffer segment and a disc of the disc drive. Counting circuits count the number of bytes transferred between the host and the buffer segment and between the buffer segment and the disc and provide sector count signals each time a sector of data is transferred into or out of the buffer segment. The sector count signals are received by a buffer manager which includes counters for counting sectors of data transferred into and out of the buffer segment and a comparator circuit that compares the contents of the buffer manager counters to provide a code indicative of the state of the buffer segment to a decoder. The decoder provides pause signals to the state machines to suspend data transfers from the source, host or disc, of data when the buffer segment is filled to capacity and to suspend transfers to the receiver, host or disc, of the data when the buffer contains no data which has not been previously transferred to the receiver.

1. Field of the Invention
The present invention relates generally to improvements in data transfer systems and, more particularly but not by way of limitation, to improvements in apparatus for controlling the transfer of data between a host computer and discs of a hard disc drive.
2. Brief Description of the Prior Art
In a hard disc drive, files used by a host computer are stored on rotating discs on which are defined a series of concentric data tracks to which data contained in the files is written and from which the data is subsequently read. To this end, the discs are provided with magnetizable surface coatings, and a read/write head capable of magnetizing the surface in either of the two opposite directions along a track is provided for each disc surface to write the data to a selected track in the form of a series of magnetized cells along the track. Data is then recovered, or read, by the generation of emf pulses in the read/write head as boundaries between cells pass the head.
The data in a file is made up of a series of data characters, each corresponding to a particular pattern of bits, so that, at a microscopic level, the cells along a data track correspond generally to the series of bits that make up the individual characters of which a file is composed. (As is known in the art, the data is encoded prior to writing so that the correspondence is only a general one and the stream of emf pulses issuing from the read/write head is similarly decoded to recover the original bits of the data characters.) Thus, at a microscopic level, data in a file is corresponded to magnetized cells along a data track when a file is stored.
At a macroscopic level, the tracks are organized into sectors, each containing a header that identifies the sector, in which a selected number, usually 512, of data bytes are stored. Thus, when a file is be stored, it is divided into data sectors, corresponding to the sectors on the discs, and each data sector is stored at a selected sector on a disc. Thus, at the macroscopic level, reading and writing of files is effected on a sector basis and a file allocation table on the disc maintains a record of the disc sectors at which the file is located.
The transfer of a file between the host and a disc of the disc drive is similarly controlled at two levels, the microscopic level in which cells along a track on a disc are magnetized in relation to the bit structure of the file for subsequent reading and the macroscopic level in which sectors are selected to contain the data sectors into which the file is divided, and sectors of data are channeled to the selected sectors along a track of the disc. To implement this bi-level transfer scheme, a disc drive includes a buffer into which sectors of data are first transferred, either from the host or the disc, and from which the sectors of data are subsequently transferred to the disc or the host. Specifically, a system microprocessor, which is programmed to control the operation of the disc drive as a whole, includes programming for locating sectors at which a file is to be stored or from which a file is to be retrieved and for controlling the transfers at the sector level. At the microscopic, or character, level, transfers are carried out by hardware controllers that include state machines that control transfers of data to and from the buffer on a character by character basis.
Typically, then, transfers of files between the host and discs of the disc drive are carried out in a series of steps under the overall control of the system microprocessor but under microscopic control of the controllers. Thus, for example, at such times that a file is to be written to a disc, the host will provide general information to the system microprocessor, via a host interface controller, that will enable the system microprocessor to determine the sectors to which a file is to be written, and the system microprocessor initiates the transfer by carrying out a series of operations effecting transfer at the sector level. These operations include the issuance of commands to a servo system which controls the radial location of the read/write heads to cause movement of the heads to the track on the disc that is to receive the file and the selection of a segment of the buffer which is to be utilized in the transfer of the file to the disc sectors. Generally, the buffer segment is organized as a circular register which can contain a selected number of sectors, and sector length blocks within the buffer segment are reused once data stored in a block has been transferred from the buffer. Once these operations are complete, the system microprocessor transmits transfer control parameters to the host interface controller and issues a command to the host interface controller to transfer one or more sectors of data to the buffer segment. The state machine of the host interface controller then coacts with the host and a buffer controller, which provides microscopic control over the buffer, to cause the characters which comprise the file to be transferred into the sector blocks within the buffer segment.
Once the read/write head reaches the track that contains the sectors that are to receive the file, the microprocessor similarly issues commands and control parameters to a disc interface controller to cause sectors of data that have been stored in the buffer segment to be transferred, a bit at a time, to the appropriate sectors on the disc. More particularly, the disc interface controller, like the host interface controller, receives commands calling for the transfer of a selected number of sectors from the buffer segment to a read/write circuit which carries out the magnetization of cells along the data tracks.
Reading of a file is carried out in a similar manner. As in the case of writing, the system microprocessor will select a buffer segment to temporarily store data as it is read from a disc and will issue commands to the disc drive servo system to bring the read/write head into radial alignment with the track that contains the sectors at which the file is stored. Once these preliminary steps have been completed, the system microprocessor issues commands and control parameters to the disc interface controller to transfer one or more sectors from the disc to the buffer segment and subsequently issues commands to the host interface controller to transfer these sectors of data from the buffer segment to the host.
As will be clear from the above description of reading and writing, the system microprocessor must maintain a record of the number of sectors that have been transferred into and out of the buffer segment. For example, should the buffer segment become filled to capacity, further transfer of data into the buffer segment would result in overwriting of blocks of data that have not yet been transferred from the buffer segment. Similarly, issuance of a command to transfer data from the buffer segment after all blocks that have been transferred to the buffer segment have already been transferred from the buffer segment would result in the transfer of previously transferred data. In the first case, portions of a file would be deleted, and in the latter case unwanted insertions would be included in the file.
The maintenance of a record of sector transfers is accomplished by the issuance of commands to the controllers to transfer a selected number of sectors of data and by the use of interrupts of the system microprocessor when such number of sectors have been transferred. Thus, the host and disc interfaces generally comprise counting circuits which count the number of data transfers that have been made to or from the buffer segment and an interrupt generator that generates an interrupt to the system microprocessor when the selected number of sectors have been transferred. More particularly, the state machines in the interface controllers receive signals from the counting circuits each time a sector is transferred and are "programmed" by the selection of the truth table of decoders they contain to provide status signals to an interrupt generator indicative of the number of sectors that have been transferred. The interrupt generators then issue the interrupts to the system microprocessor.
While this general scheme of effecting data transfers between the host and discs of a disc drive provides an effective means of implementing the storage and retrieval of data files, problems have arisen with the use of the system microprocessor to orchestrate the transfers of sectors of data into and out of the buffer segment. Initially, as is known in the art, microprocessors operate very slowly in comparison with the rate at which data transfers are made at the character, or microscopic, level. In the time required for the system microprocessor to execute one program instruction, many characters of data are transferred into and out of the buffer segment. Such high speed transfer at the character level is necessary in order to effect the storage or retrieval of a file in a time that is acceptable to the users of computers and is the reason for the use of hardware controllers to control the transfer of data at the character level. Unlike a microprocessor, programming of a state machine is implemented in a decoder, rather than in a memory device, so that the state machine can be caused to have a limited number of functions which are performed in only a few clock cycles. Thus, the state machine operates at a rate that is comparable to the time required to magnetize a cell along a data track and can be used to control microscopic level data transfers.
Because of the relatively slow operation of the microprocessor, a decision must be made by the microprocessor at a time that is considerably in advance of the time that a sector on a disc that is to receive data from the buffer segment or that is to provide a source of data to be transferred to the buffer segment reaches the read/write head by means of which data is magnetically read from or written to the track. Typically, unless the microprocessor has received signals indicative of the presence of a sector of data in the buffer to be written to a disc or the presence of a free block to receive a sector in the buffer segment by the time the previous sector along the track has reached the read/write head, it will not have time to issue the necessary commands to the disc interface controller to transfer data to or from the disc. Commonly, the disc interface controller contains circuitry for reading sector headers and comparing them with header identification codes supplied by the system microprocessor and reporting to the disc interface controller state machine when the previous sector header has been read. The state machine is programmed to respond to such report by providing a status code to the interrupt generator that results in an interrupt of the system microprocessor which then reads the status code and determines, while such previous sector is passing the read/write head, whether a sector of data is available to be written to the disc or whether a sector length block is available in the buffer to receive data from disc. If not, no command to transfer a sector of data will be issued to the disc interface controller. Thus, even though a sector to be written to a disc may be in the buffer segment or space to receive data from the disc may be available in the buffer at the time that the sector actually reaches the read/write head, writing or reading, as the case may be, will, perforce, be suspended for the time required for the disc to make a complete revolution to return the sector next to receive or provide data to the read/write head. Such a suspension will unduly lengthen the time required to store a file to a disc or retrieve a file from a disc.
An additional problem with microprocessor intervention each time one or only few sectors are transferred into or out of the buffer segment is the amount of microprocessor operating time that must be allocated to the transfer of data between the disc and the host. As can be seen from the above, each time either interface controller reports the completion of the transfer of a sector, or a few sectors, of data to or from the buffer segment, the system microprocessor must execute an interrupt routine that will determine whether additional sectors can be transferred into or out of the buffer sector and cause the microprocessor to issue commands to transfer additional sectors. Since the system microprocessor provides overall control of the disc drive, the time required for executing these interrupt routines can limit the capabilities of the disc drive solely on the basis that the microprocessor processing time is not available to carry out functions required to provide additional capabilities. Thus, while the general scheme for effecting data transfers between a host and a disc is, in principle, an effective approach to data storage and retrieval, the implementation of the scheme has given rise to practical problems that have not heretofore been solved.

Disc drive with improved data transfer management apparatus


A memory system allows page boundaries to be crossed in successive reads of a Dynamic Random Access Memory (DRAM) without the necessity of waiting for another page of memory to be read out of a memory array of the DRAM. The memory is divided into multiple banks, each of which has a Bit-Line Sense Amplifier (BLSA) capable of holding one page of memory. Successive pages of memory are stored in separate banks, and may be activated or deactivated while data from another page is being read. The memory system is operable whether the successive reads are sequential or out-of-order.

Dynamic Random Access Memories (DRAMs) are commonly used in digital computers to store data. DRAMs have significantly greater storage density than Static Random Access Memories (SRAMs) but operate at slower speeds than SRAMs.
A number of techniques have been developed to improve the access time of memory systems employing DRAM chips. A common technique is the use of page mode addressing which exploits the internal organization of the DRAM. Specifically, typical DRAM chips employ a storage array organized in rows (also known as "pages") and columns. Presentation of a row address causes access of an entire row, which includes a plurality of columns, to a Bit-Line Sense Amplifier (BLSA). Presentation of a column address then causes selection and output from the chip of a column comprising one or more bits. The row access typically is the significant limiting factor in a data access from a DRAM. Once the row access is performed, multiple column accesses may be performed to implement the aforesaid page mode operation.
Page mode operation provides significant increases in the speed of reading from and writing to a DRAM. However, such an increase only occurs so long as all accesses are within a particular row, or page. Whenever an access occurs across a row/page boundary, a performance penalty is incurred. What is needed is a system whereby a performance penalty is not necessarily incurred when an access occurs which crosses a row/page boundary.

Real time DRAM eliminating a performance penalty for crossing a page boundary


A first head unit configured to discharge a liquid, a unit holder detachably holding the first unit, and a member configured to move relative to the unit holder are provided. When a trajectory through which the first head unit passes when the first head unit is attached and detached with the unit holder is used as the first trajectory, the member is configured to move between a first position at which the member is positioned relative to the unit holder so as to overlap the first trajectory, and a second position at which the member is positioned relative to the unit holder separated from the first trajectory.

1. Technical Field
The present invention relates to an image recording device constituted with a head unit for discharging a liquid made to be detachable with a unit holder.
2. Related Art
In Unexamined Patent Publication No. 2011-93174, described is a device for recording an image on a recording medium by discharging ink from a head unit on a recording medium supported on a rotating drum. At this time, alignment of the head unit to the rotating drum is realized by the head unit being held by a carriage. In particular, with Unexamined Patent Publication No. 2011-93174, the carriage holds the head unit so as to be detachable, and it is possible for the operator to insert the head unit in the carriage and to pull out the head unit from the carriage.
To smoothly perform attaching and detaching of the head unit with a unit holder such as a carriage, it is important to not have the head unit that is being attached or detached interfere with the peripheral members. However, with the device noted above, it is necessary to arrange members in the periphery of the head unit. Because of this, when attaching or detaching the head unit with the unit holder, it was difficult to avoid interference between the members provided in the periphery of the unit holder and the head unit.


The present invention discloses a method of simultaneously conducting more than one step of a radiofrequency phase cycle in a nuclear magnetic resonance (NMR) experiment. The method first involves providing a sample. Next, one or more radiofrequency pulses are applied to a plurality of spatially discrete slices of the sample under conditions effective to simultaneously conduct more than one step of a radiofrequency phase cycle in a single transient. Then, NMR signals generated from the step of applying the radiofrequency pulses are acquired. Finally, the NMR signals are processed to obtain an NMR spectrum.

Nuclear Magnetic Resonance Phenomenon
Atomic nuclei possessing a spin quantum number larger than zero have a non-classical angular momentum called "nuclear spin." Since the nuclei are charged, the nuclear spin creates a nuclear magnetic moment. In the presence of an external magnetic field, a slight majority of these magnetic moments are aligned parallel with the field. This "excess population" of aligned spins or "polarization" is the target for nuclear magnetic resonance (NMR) experiments.
A radio frequency (RF) pulse at exactly the right frequency causes a coherent precession of spin magnetic moments (a "coherence") about the external magnetic field axis (also called the "longitudinal axis"). The angle that the RF pulse tips the net magnetic moment of the spins away from the longitudinal axis is called the "flip angle" and is usually 90° in an "excitation pulse" or 180° in an "inversion pulse." If the net magnetic moment has been rotated 90° from the longitudinal axis, it is said to be "transverse." RF pulses also have a phase associated with them (usually 0°, 90°, 180°, or 270°), which determines which direction the net magnetic moment will be pointing once it reaches the transverse plane.
The precessing magnetic moments produce a free induction decay (FID) signal that can be detected with an RF coil and an RF receiver. The experimental power of NMR lies in the extraordinarily high "Q" (the ratio of stored to dissipated energy per cycle in a dynamic system) in a precessing population of spin ½ magnetic moments due to their weak interaction with the environment. The resulting narrow linewidth allows accurate spatial separation in magnetic resonance imaging and precise measurement of chemical shifts in high resolution NMR spectroscopy.
Magnetic Resonance Imaging and Spatial Selectivity
The NMR phenomenon is exploited in a medical imaging modality called magnetic resonance imaging (MRI). In this technique, a part of the (human) body is placed in a large (usually superconducting) magnet. RF transmission and reception is used to excite and receive NMR signals from 1H nuclei in the body (primarily those present in water). The relaxation rates of the detected signals vary with the type of tissue the nuclei are embedded in. Special techniques are used to localize the RF signals in space and the result is a detailed anatomical picture of the imaged region. Current MRI images depict planes of tissue only a few millimeters thick and have in-plane resolution of less than a millimeter.
A key tool for signal localization in MRI is a set of 3-axis "pulsed magnetic field gradients." These gradients can be rapidly switched on and off and produce a variation in the magnetic field strength that is linear in a certain direction (usually labeled as x, y, and z). During the application of a gradient, the resonance frequency of the NMR signal is, thus, a linear function of the position along the axis of that gradient. In MRI, these gradients are applied in different ways to achieve spatial localization in each of the three spatial dimensions (Mansfield et al., NMR Imaging in Biomedicine Academic Press, San Diego (1982)).
In the first dimension (which can be an arbitrary plane in three dimension), spatial localization is achieved during RF excitation. A linear pulsed field gradient known as the "slice select gradient" is applied simultaneously with the application of the RF excitation pulse as shown in FIG. 1. The "temporal" shape of the pulse defines the "excitation profile" in the frequency domain. The effect of the linear field gradient is to map the frequency domain "excitation profile" into position in space along the gradient, creating a "spatial profile." The result is that the "spatial excitation profile" is to first order the Fourier transform of the temporal RF pulse shape. Usually a (sin(t)/t) or "sinc" shaped RF pulse is used, which results in excitation of a narrow planar slice of the body, since the Fourier transform of (sin(t)/t) is a rectangle. The excitation gradient is applied during the duration of the shaped RF pulse. Since the gradient shifts the resonance frequency of the spins proportionally to their position in the gradient, the RF pulse is "off-resonance" or not quite at the correct frequency for all spins except those in the exact center of the gradient. An off-resonance RF pulse leads to a phase shift proportional to the frequency offset. This shift can be approximated by assuming an on-resonance pulse followed by an evolution period of duration,tau=2*(pulse width)/piduring which time phase evolves due to the frequency offset (Cavanagh et al., Protein NMR Spectroscopy, Academic Press, San Diego (1996)). The frequency offset of each spin is proportional to its position in the selection gradient direction. Therefore, the phase shift resulting from the selective excitation is also proportional to position. The result is a linear phase shift in the direction of the gradient. This shift can be removed by reversing the gradient for the period tau, during which transverse magnetization is present (FIG. 1).
Once a thin plane of material has been excited, the radio receiver is turned on and RF signals from the precessing spins are detected with a receiver. During this period, a linear magnetic field gradient known as the "readout" or "frequency encoding" gradient is applied in a direction orthogonal to the slice select gradient. The signal frequency of each spin is proportional to its localized magnetic field strength and, thus, is proportional to its position in the gradient direction (i.e., X). A Fourier transform of the received time domain signals then separates the signals by position in the readout gradient direction (FIG. 2). The implementation of the readout gradient is shown in FIG. 3. After excitation, the phase of the signal from each part of the sample is the same. A "readout dephase" gradient pulse imparts a phase shift as a function of position. The readout gradient then causes frequency encoding which acts to rephase the phase shift. In the middle of the acquisition window, the signal peaks because signals from the entire sample are instantaneously in-phase.
The same method is used to localize in the final, third dimension. In this case, rather than apply a continuous gradient pulse as in the readout direction, a short gradient pulse known as the "phase encoding" gradient is applied in the third direction in the time between RF excitation and reception. The entire experiment is repeated many times with the phase encoding gradient strength (amplitude times duration) incremented linearly as a function of experiment number. The net result is again that a Fourier transform of the received time domain signals, this time in the direction associated with repeated experiments, results in localization in the third direction. Simultaneous application of all three of these techniques provides a detailed two-dimensional (2D) picture of a thin slice of tissue. FIG. 4 shows a schematic of the basic spatial encoding scheme used in MRI.
A slight modification of the technique described above, which allows acquisition of an entire 2D slice in a single experiment, is called "echo planar imaging." In this technique, the readout gradient is stronger, thereby compressing the spatial encoding of the second direction in time. During each gradient pulse, the transverse magnetization across the sample is gradually rephased, producing a signal peak or "gradient echo." Fourier transform of the gradient echo produces a spatial profile of the signal in the gradient direction. The gradient is then reversed and rephased again from the opposite direction. Thus, a "square wave oscillating" gradient will generate a train of gradient recalled echoes in the center of each gradient pulse. The phase encoding gradient can then be applied in short pulses between these echoes, allowing acquisition of an entire 2D image in a single transient. FIG. 5 shows a schematic of the spatial encoding scheme for echo planar MRI.
High Resolution Nuclear Magnetic Resonance Spectroscopy
Like MRI, high resolution NMR relies on the phenomenon of magnetic resonance in order to obtain spectral information from NMR active (usually spin ½) atomic nuclei. However, in the case of conventional high resolution NMR, signals are not spatially resolved. Instead, experiments are employed that gather detailed information about the localized chemical environment of the nuclei in a molecule, as well as the spatial interaction of their magnetic moments. High resolution NMR is conducted on samples in solution and each atomic nucleus in the molecule resonates at a slightly different frequency or "chemical shift." The chemical shift provides information about the molecular environment of the atom and allows, in conjunction with their mutual coupling, one to assign signals to specific nuclei.
NMR active nuclei that are covalently bonded in a molecule interact by a mechanism known as "scalar coupling" in which one nucleus causes a frequency shift (+ or −½ of the scalar coupling constant depending on the spin state of the atom) to the NMR frequency of the other nucleus. Scalar coupling can be exploited to transfer polarization from one nucleus to the next. Polarization can be transferred to the same type of atom (i.e., 1H to 1H) in a "homonuclear" NMR experiment or to another type of atom (i.e., 1H to 15N) in a "heteronuclear" NMR experiment.
A pulse sequence module known as "insensitive nuclei enhanced by polarization transfer" or INEPT is used to transfer polarization from an NMR sensitive spin such as 1H to a less sensitive spin such as 15N. "Multidimensional heteronuclear NMR" studies use this module repeatedly to sequentially transfer polarization. The experiment is repeated with different time delays or "chemical shift evolution periods" in order to gather chemical shift information on each of the involved spins. RF pulse sequences have been designed that exploit the known covalent structure of proteins and provide chemical shifts for hydrogens, carbons, and nitrogens in proteins that have been labeled with the spin ½ isotopes 13C and 15N. The chemical shifts can be combined with signals from another type of study that produces signals from pairs of protons that are close in space to solve the three dimensional structure of biological macromolecules.
NMR RF pulse sequences often rely on "RF pulse phase cycling" to suppress artifacts, to detect signals in indirect dimensions in a phase-sensitive manner ("quadrature detection"), to select desired coherence transfer pathways as in double quantum filtered (DQF) correlation spectroscopy (COSY), and/or to edit signals into sub-spectra of a G-matrix Fourier transform (GFT) NMR experiment. Phase cycling consists of repeating the same sequence of RF pulses two or more times while changing the phase(s) of one or more RF pulses and/or the receiver phase (Ernst et al., Principles of Nuclear Magnetic Resonance in One and Two Dimensions, Clarendon, Oxford (1987)).
Historically, NMR experiments are repeated many times so that "signal averaging" can be used to increase the signal to noise ratio. If such signal averaging is required to achieve a sufficiently high signal-to-noise ratio, an NMR experiment is considered "sensitivity limited" (Szyperski et al., "Reduced-Dimensionality NMR Spectroscopy for High-Throughput Protein resonance Assignment," Proc. Natl. Acad. Sci. USA 99:8009-8014 (2002)). The desire to obtain complete chemical shift assignments for protein amino acid residues has led to the development of two-, three-, and even four-dimensional NMR experiments requiring the acquisition of hundreds or even thousands of free induction decays (FIDs) in order to sample the indirect chemical shift evolution periods. When using a highly sensitive NMR spectroscopic set-up, this may lead to the situation where NMR time is solely invested to sample indirect dimensions and not for achieving a sufficient signal-to-noise ratio. This data acquisition regime is named the "sampling limited regime" (Szyperski et al., "Reduced-Dimensionality NMR Spectroscopy for High-Throughput Protein Resonance Assignment," Proc. Natl. Acad. Sci. USA 99:8009-8014 (2002)).
Several approaches have been developed to decrease data collection time while still obtaining high-dimensional NMR spectral information. GFT NMR spectroscopy (Kim et al., "GFT NMR, A New Approach to Rapidly Obtain Precise High-Dimensional NMR Spectral Information," J Am. Chem. Soc. 125:1385-1393 (2003); Atreya et al., "G-matrix Fourier Transform NMR Spectroscopy for Complete Protein Resonance Assignment," Proc. Natl. Acad. Sci. U.S.A. 101:9642-9647 (2004)) allows projection of multi-dimensional NMR spectra into fewer dimensional space with associated time savings. In another vein, Frydman et al. have adapted spatially selective excitation from MRI to simultaneously conduct multiple time increments of indirect dimensions of a multidimensional NMR experiment on a sample by dividing the sample into discrete spatial slices (Frydman et al. "Principles and Features of Single-Scan Two-Dimensional NMR Spectroscopy," J Am. Chem. Soc. 125:9204-9217 (2003); U.S. Pat. No. 6,873,153 to Frydman).
As mentioned above, the combination of higher dimensional studies which require a number of transients to get usable resolution in each dimension, along with improvements in equipment sensitivity, higher field strength magnets and cryogenic probes, has lead to a point where the duration of the data acquisition is determined by sampling needs rather than intrinsic signal to noise limitations. Development of methods for shortening this duration while retaining the required NMR spectral information is an active area of research. Reduced dimensionality and GFT NMR spectroscopy (Szyperski et al., "GFT NMR, A New Approach to Rapidly Obtain Precise High-Dimensional NMR Spectral Information," J Am. Chem. Soc. 125:1385-1393 (2003)), sparse sampling of NMR data, and Frydman's spatial-temporal approach (Frydman et al., "The Acquisition of Multidimensional NMR Spectra Within a Single Scan," Proc. Natl. Acad. Sci. U.S.A. 99:15858 (2002)) each address this problem in different ways. Nonetheless, a large need for tools allowing one to reduce the minimal measurement times of multidimensional NMR experiments remains.
The present invention is directed to achieving this objective.

Simultaneous phase cycling for nuclear magnetic resonance spectroscopy

The Research Foundation of the State University of New York


Disclosed is a method for forming a capacitor of a semiconductor device. An etch stop layer, first oxide layer and second oxide layer are sequentially deposited on an insulating interlayer of a substrate. Contact holes through which portions of the etch stop layer are exposed above plugs of the insulating interlayer are formed. The contact holes are cleaned by a cleaning solution having an etching selectivity which is higher for the first oxide layer than for the second oxide layer, thereby enlarging lower portions of the contact holes. A spacer nitride layer is formed on surfaces of the contact holes and the second oxide layer. Portions of the spacer nitride layers located on the second oxide layer and above the plugs together with portions of the etch stop layer located on the plugs are removed. A double polysilicon layer is formed on the spacer nitride layer segments.

1. Field of the Invention
The present invention relates to a method for forming a capacitor of a semiconductor device, and more particularly to a method for forming a capacitor of a semiconductor device, which can suppress formation of bridges between lower electrodes of the capacitor, and can improve various characteristics of the capacitor, in relation to leakage current, capacitance, and breakdown voltage of the capacitor.
2. Description of the Prior Art
As generally known in the art, Dynamic RAMS (DRAMs) store data without being directly and constantly connected to power source, and so they should be refreshed at regular intervals. In other words, DRAMs store data in the form of charge on capacitors, and so require that the capacitors be recharged regularly: every few milliseconds. Further, the larger the capacitance of the capacitors is, the longer the data stored in the DRAMs can be maintained.
However, a recent trend toward a higher integration of semiconductor devices induces reduction in the cell size, accompanied by reduction in the area of capacitors, which results in reduction in capacitance of the capacitors. Therefore, the conventional capacitor construction has difficulties in enabling the capacitors to retain necessary capacitance for maintenance of constant device operation characteristics.
Therefore, various types of highly integrated devices are currently mass-produced, such as devices having lower electrodes (i.e., charge storage electrodes) of various three-dimensional structures in order to increase the surface area, devices having a dielectric layer made from material having a high dielectric constant, or devices having as thin a dielectric layer as possible, in order to secure more than a certain amount of capacitance necessary for cell operation. Such mechanical features of the devices as described are based on a principle that a capacitance of a capacitor is proportional to either a surface area of an electrode or a dielectric constant of a dielectric layer, and is inversely proportional to a spacing between the lower and upper electrodes, i.e., a thickness of the dielectric layer.
Specifically, first, in order to secure a necessary capacitance, the thickness of the dielectric layer or the spacing between the upper and lower electrodes may be reduced. For example, an ONO film lamination (oxide film/nitride film/oxide film) intends to increase a capacitance through reduction in the thickness of the dielectric layer. Second, the dielectric layer may be made from material having a high dielectric constant in order to increase the capacitance. For example, dielectric films of Ta2O2, TaON, and Al2O3 intend to increase a capacitance by employing a dielectric layer made from material having a high dielectric constant. Third, various three dimensional structures of the lower electrodes, such as cylindrical structures, concave structures, and pin-shaped structures, intend to increase a capacitance by increasing the surface area of the electrodes. For example, U.S. Pat. No. 5,655,536 discloses a crown-shaped stacked capacitor, and U.S. Pat. No. 5,716,884 discloses a stacked capacitor having a fin-shaped electrode. In contrast, U.S. Pat. No. 5,877,052 discloses a method of increasing a capacitance of a capacitor by forming hemispherical silicon grains on surfaces of lower electrodes.
Here, in the method of forming the lower electrodes with the hemispherical silicon grains grown on the surfaces of the lower electrodes, silicon grains are deposited and heat-treated on the surfaces of the lower electrodes, so as to cause the surfaces of the lower electrodes to be flexural, thereby increasing the surface area of the lower electrodes and securing the necessary capacitance. The step of forming the hemispherical silicon grains is also called a "meta-stable polysilicon (MPS) process." When the MPS process has been performed to cause the surfaces of the lower electrodes to be flexural, thereby increasing the surface area of the lower electrodes, the capacitance can be increased up to a value about twice larger than that of a capacitor having flat electrodes. However, the capacitor having flexural electrodes shows an inferior characteristic in relation to current leakage and has a limitation in that a film having excellent step coverage have to be inevitably used as a dielectric layer in the following step.
FIGS. 1a through 1f are cross-sectional views showing a process of forming a conventional capacitor, which will be described hereinafter.
In the step as shown in FIG. 1a, a semiconductor substrate 11 on which an insulating interlayer 12 having plugs 13 is formed is firstly arranged. Then, an etch stop layer 14, an oxide layer 15, and a hard mask layer 16 are deposited in sequence on the insulating interlayer 12.
In the step as shown in FIG. 1b, a photoresist film is applied on the hard mask layer 16 and is then exposed to light and developed, so as to form a photoresist pattern defining a region in which lower electrodes shall be formed. Thereafter, the hard mask layer and the oxide layer 15 are etched while using the photoresist pattern as an etching barrier, so as to form contact holes 17 through which the etch stop layer 14 is exposed. Thereafter, the photoresist pattern and the hard mask layer are eliminated in sequence.
In the step as shown in FIG. 1c, polymers generated when the contact holes 17 are formed are eliminated, and the insides of the contact holes 17 are cleaned so as to increase an effective surface area of the region in which the lower electrodes shall be formed. Here, diluted hydrogen fluoride (DHF) solution or buffered oxide etchant (BOE) solution is used in the cleaning. Thereafter, portions of the etch stop layer 14 under the contact holes 17 are eliminated, so as to expose the plugs 13.
In the step as shown in FIG. 1d, a double polysilicon layer 18 used to form the lower electrodes is deposited on the exposed surfaces of the oxide layer 15 and the inside surfaces of the contact holes 17. Herein, the double polysilicon layer 18 has a dual structure including a doped polysilicon layer 18a and an undoped polysilicon layer 18b.
In the step as shown in FIG. 1e, another photoresist film is applied to fill the contact holes in which the double polysilicon layer 18 for the lower electrodes is formed. Then, the photoresist film is etched back or subjected to a chemical mechanical polishing (CMP), so as to divide the double polysilicon layer 18 into a plurality of adjacent polysilicon layer segments for the lower electrodes. Thereafter, the photoresist film is eliminated through a stripping process, and the resultant lamination on the substrate is then cleaned.
In the step as shown in FIG. 1f, the hemispherical silicon grains 19 are developed on surfaces of the segments of the undoped polysilicon layer 18b, so as to form the lower electrodes.
Thereafter, although not shown, a dielectric film and an upper electrode are formed in sequence on the lower electrodes having the hemispherical silicon grains 19 formed on the surfaces thereof, thereby completing a capacitor.
However, such a conventional method for forming a capacitor of a semiconductor device as described above has several problems as follows.
FIG. 2a is a photograph showing the contact holes which are in a state after being cleaned after being formed by etching an oxide layer. The cleaning is performed in order to increase the effective surface area of the region in which the lower electrodes shall be formed and eliminate the polymers remaining after the etching. However, FIG. 2a shows a capacitor in which the oxide layer is insufficiently etched and remains at lower portions of the contact holes, thereby failing to achieve actual increase in the effective surface area of the region in which the lower electrodes shall be formed. Herein, when a quantity of the etched oxide layer is increased, the space between cells may become insufficient and bridges may be formed between cells. In contrast, it is nearly impossible to increase the capacitance of the capacitor when the etching is carried out in such a degree as to prevent bridges from being formed between cells.
FIGS. 2b and 2c are photographs of a lamination formed on a substrate, including hemispherical silicon grains developed thereon, taken from above and side of the lamination.
In partially eliminating the polysilicon layer for the lower electrodes deposited on the oxide layer in order to form the electrically separated lower electrodes, a photoresist film is applied to fill the contact holes, and then, the photoresist film is etched back to eliminate the polysilicon layer for the lower electrodes deposited on the oxide layer.
Here, the difference between the etching rates of the oxide layer and the polysilicon layer for the lower electrodes may cause loss of an upper portion of the oxide layer, which causes the polysilicon layer segments for the lower electrodes to protrude outward beyond the oxide layer. As a result, the excessively protruding polysilicon layer segments for the lower electrodes may induce excessive development of hemispherical silicon grains, and may induce formation of hemispherical silicon grains even on outer wall surfaces of the lower electrodes.
FIG. 2d illustrates graphs showing diffusion of phosphorus P from the doped polysilicon layer to the undoped polysilicon layer when the lamination has been subjected to an annealing at 650° C. in order to grow the hemispherical silicon grains on the undoped polysilicon layer. Here, a doped polysilicon layer having a thickness of 300 Å and an undoped polysilicon layer having a thickness of 100 Å and doped with phosphorus at a density of 24E20 atoms/cc were employed in the experiment as shown in the graphs of FIG. 2d.
As a result of the annealing, the entire doping profile shows no change, but it is noted that the diffusion of the phosphorus has lowered the doping density at the surface of the doped polysilicon layer down to 1E19˜1E18 atoms/cc.
As described above, in order to increase growth of hemispherical silicon grains, the undoped silicon for the lower electrodes is deposited with an increased thickness, and the hemispherical silicon grains are grown on the undoped silicon layer. Then, the hemispherical silicon grains are excessively grown and phosphorus is diffused in the doped polysilicon layer, thereby causing a thinning phenomenon, in which the thickness of the doped polysilicon layer is reduced. As a result, pinholes are formed in the doped polysilicon layer, and cleaning solution may come into the pinholes and etch the oxide layer, thereby forming holes in the oxide layer, in the following cleaning step. Consequently, in the following step of depositing the dielectric film, the dielectric film may be deposited in the entire holes so as to form bridges between cells.
FIG. 2e is a photograph showing pinholes formed in the doped polysilicon layer according to the thinning phenomenon, that is, reduction of the thickness of the doped polysilicon layer.
Here, the pinholes formed while the hemispherical silicon grains are grown degrade various characteristics of the capacitor, in relation to leakage current, capacitance, and breakdown voltage of the capacitor.

Method for forming capacitor of semiconductor device


A Partially-Overlapped Block (POB) code used in an encoding and decoding method in which a plurality of different block codes are combined so that the block codes partially overlap one another. A method for recovering a plurality of packets by using a loss correction capability of this encoding method in which a larger number of packets than the number of added redundant packets per frame are recovered, by reusing redundant information of neighboring frames effectively, without increasing the asymptotic complexity of its decoding algorithm.

An encoding technique for packet recovery and a decoding technique corresponding to the encoding technique have been increasingly important for wired or wireless network applications. The reason for this is that an increase in a data transfer speed brings about packet losses more often, while the conventional packet recovery method based on retransmission of packets increases performance overhead and buffer management overhead. Here, packet losses occur due to congestion attributed to errors in the detection of a header/synchronization pattern attributed to a temporary concentration of data packets at a network switch.
One prior art technique for solving the foregoing problems, encodes packets on a frame-by-frame basis using a block code such as an interleaved Reed Solomon (RS) erasure correcting code (Nonnenmacher, E. W. Biersack, and D. Towsley, "Parity-based loss recovery for reliable multicast," IEEE/ACM Trans. Networking, vol. 6, pp. 349.361, August 1998.). In this conventional technique, however, a redundant packet is not used, and is just wasted when there are no lost packets in a given frame. This inefficiency can be reduced when a code length is set to be longer. At the same time, however longer code lengths result in an increase in the computational complexity for decoding.
As another prior art technique involves performing decoding by using a nonsystematic code specific to packet recovery, on the basis of a graph structure consisting of source nodes and check nodes which are commonly used by a sender and a receiver (Luby, M. Mitzenmacher, A. Shokrollahi, and D. Spielman, "Efficient erasure correcting codes," IEEE Trans. Inform. Theory, vol. 47, pp. 569. 584, February 2001.). A non-systematic code is effective in terms of an encoding rate, and is efficient since it exhibits a substantially linear latency for decoding. Non-systematic codes, however, are not particularly efficient in terms of required bandwidth. Moreover, the efficiency of a hardware implementation of this method is similarly lacking due to random graph structures. For this reason, the application range of this method is limited to streaming media and data delivery for which encoding and decoding are implemented with software.
As still another conventional technique, there is a method for packet recovery using convolutional codes of (n, n−1, m) (M. Arai, A. Yamaguchi, K. Iwasaki, "Method to Recover Internet Packet Losses Using (n, n−1, m) Convolutional Codes," IEEE Dependable System and Network, pp. 382-389, 2000.). In this method, a lost packet can be recovered more flexibly than a frame-based technique using block codes. Nevertheless, this method is based on a binary convolutional code, and thereby requires a loss correction on a bit-by-bit basis. For this reason, this method does not allow decoding on a symbol-by-symbol basis to be performed. Accordingly, it is necessary to arrange a large number of decoders in parallel rendering a costly hardware implementation in terms of area.
The foregoing conventional techniques for packet recovery suffer from inefficiencies related to longer code length, more complexity in implementation of a decoder circuit, etc. In addition, an excessive addition of redundant information may cause new congestion.

Encoding and decoding method for packet recovery

International Business Machines Corporation


A method and apparatus is provided for implementing a memory cell array having a performance-improved critical read path using a Domino boost amplifier configuration. The memory bit line is broken into small segments with a Domino boost amplifier and the bit line is connected to the input of the amplifier. The output of the amplifier drives the global bit line. The amplifier is turned "on" during a "read" and turned "off" during a "write". During a read, one memory cell within one array segment is turned on. The memory cell drives the differential signal on to the local bit line pair. Also during a read, the boost amplifier which attaches to that local bit line is enabled. The boost amplifier amplifies the input signal (local bit line pair) and drives that signal on to the global bit line. Since the bit line is broken into small segments with boost amplifiers, there are many boost amplifiers attached on the global bit line. When enough signal is developed on the global bit line pair, the other boost amplifiers which are attached to the global bit line will be turned on. The bit line is thus quickly pulled to ground thereby significantly improving performance for the critical read path.

In general, the term "domino logic" is used to refer to an arrangement of logic circuit stages which may, for example, be cascaded together in an integrated circuit array configuration. A signal may be inputted to a first stage where it is evaluated in order to provide an output signal to a second stage where that output signal is again evaluated to provide an output signal for propagation to and evaluation by yet another stage in the circuit. Thus a "domino" effect is achieved whereby signals are sequentially propagated through an array of "stages" or "domino blocks", and each successive stage performs an evaluation of an input condition until a final output is provided at a final output stage. Domino logic circuits may be arranged so that signals can propagate through the various stages without being separately clocked at each stage.
In traditional differential signal memory arrays utilizing the standard six device cell, four transistors are configured to form a cross-coupled latch/memory cell for storing data and two transistors are used to obtain access to the memory cell. During a "read" access, differential data stored within the memory cell is transferred to an attached bit line pair. Differential voltage is allowed to develop on the bit lines until sufficient offset between bit lines (100-200 mv) has developed to reliably sense the binary state of the memory cell. with the completion of the read, the differential bit line pairs are clamped together and restored high (to a "high" logic level voltage or "VDD") to cancel the offset generated during the read operation.
During a "write" access, data is written into the cell through the differential bit line pair. In general, one side of the bit line pair is driven low (i.e. to a low logic level potential or ground) and the other side of the differential pair is driven high to VDD minus the threshold voltage of the transistor Vt. Following the write, the differential bit line pair must be restored to VDD prior to the next read/write access to the memory cell. For a traditional memory array, the time required for a sufficient bit line offset development to reliably read the memory cell in addition to the time required to restore one-half of the differential bit line pair ground potential to VDD after a write operation defines the minimum cycle time for the array.
Improvements to either the bit line offset development rate, or the bit line restore time following a write, will increase performance of the memory structure as a whole. For a large array, it is more efficient if the array is organized in long column bit lines, i.e. many rows. However, the length of an array bit line is limited by the signal development time for a read. For an array with a long bit line, the signal development time is therefore the most critical path.
Thus there is a need to provide an improved method and apparatus for the implementation of a boost amplifier circuit which is effective to boost the performance of a critical read path in memory cell arrays having extensive bit line layouts.

Method and apparatus for memory cell array boost amplifier

International Business Machines Corporation