Apparatus for reading an identification code from a blood sample container includes an elastic member (42) which engages the upper side (34) of the sample container. A rotary device rotates the elastic member bidirectionally. An up-and-down moving device moves the elastic member up and down. A rotating/up-and-down moving control device (56) controls the movement of the container. An identification code reader (19) reads the sample code from the container, and a reading controller (57) permits the identification code reader to read from the container as it rotates in either forward or reverse direction. The elastic member abuts the upper part of the sample container and rotates it. If the identification code reader cannot read the identification code when the container rotates in the forward direction, the elastic member rotates the sample container in the reverse direction for the identification code to be read again.

The present invention relates to an identification code reader for a sample container for reading a sample identification code, such as a bar code attached to a sample container, when automatically supplying blood or other samples to a sample analyzer.
To prevent mistake in sampling, a bar code label or similar label for distinguishing it from others is glued to the outer wall of a sample container. The code marked on this label is read by a code reader installed in a blood analyzer or a smeared sample preparation unit.
If the sample container having the bar code label is merely set in the sample rack, the reading face of the bar code label may be directed to any side. But the code cannot be read unless the label is correctly facing the bar code reader.
There is prior art for eliminating reading error, for example, a device for reading a bar code while rotating the container as it is being lifted from the container supporting surface is disclosed in the Japanese Laid-open Patent Sho. 57-199958.
As far as the bar code label is glued neatly, by rotating the sample container, the bar code can be read regardless of the label position.
However, for example, when the edge of the label is slightly peeled, the peeled portion may be stuck in the sample rack when rotating, and the sample container cannot be rotated, and hence the bar code cannot be read.

Apparatus for reading an identification code from a sample container as it is rotated


A wireless base station having K antennas communicates with M mobile devices using multiuser diversity scheme with opportunistic interference management. The base station transmits K distinct pilot signals from K corresponding antennas and receives feedback from mobile devices. The feedback from each device indicates a strong pilot signal and a weak pilot signal received from the K distinct pilot signals. Using these indications, the base station assigns each of the K antennas to a mobile device. The base station then transmits distinct data streams to the mobile devices using the corresponding antennas assigned to the corresponding mobile devices. The transmission may include multiplying the transmitted distinct data streams by a vector V orthogonal to a vector U, thereby allowing mobile devices not assigned to an antenna to cancel the transmitted distinct data streams.

It is well known that the communication capacity of wireless networks is limited by interference. Depending on the strength of the interference, there are three conventional approaches to this problem. If the interference is very strong, then the receiver can decode the interfering signal and subtract from the desired signal using successive interference cancelation. If the interference signal is very weak compared to the desired signal, it can be treated as noise. The third and most common possibility is when the interference is comparable with the desired signal. In this case the interference can be avoided by orthogonalizing it with the desired signal using techniques such as time division multiple access (TDMA) or frequency division multiple access (FDMA).
In addition to interference, wireless networks also experience channel fading. Conventional approaches to wireless networking attempt to combat fading. Depending on the coherence time of the fading, various approaches have been used. For example, fast fading may be mitigated by the use of diversity techniques, interleaving, and error-correcting codes. The use of multiple antennas provides channel diversity to combat fading and may also be used to increase multiplexing gain and system capacity.
Multiuser diversity scheme is a technique to increase the capacity of wireless networks using multiple antennas at the base station. In this approach the base station selects a mobile device that has the best channel condition, maximizing the signal-to-noise ratio (SNR). According to some implementations of this approach, K random beams are constructed and information is transmitted to the users with the highest signal-to-noise plus interference ratio (SINR). Searching for the best SINR in the network, however, requires feedback from the mobile devices that scales linearly with the number of users. These implementations also use beamforming, which is complex to implement. In addition, the cooperation requirement is substantial.

Interference management for concurrent transmission in downlink wireless communications

The Regents of the University of California


The present invention is drawn to an immunogen derived from a protein allergen, which is a) a non-anaphylactic immunogenic recombinant fragment of the protein allergen which contains an IgG epitope partly but not wholly overlapping an IgE epitope of the protein allergen; b) a polymeric form of the fragment, in which the fragment constitutes the monomeric units; or c) a non-anaphylactic recombinant polymeric form of the protein allergen having 2–10 monomeric units, in which the protein allergen constitutes the monomeric units. The present invention is further drawn to the use of the immunogen for in vitro diagnoses of type I allergy and hyposensitization.

The invention concerns non-anaphylactic forms of protein allergens and the use of the forms for hyposensitization and for determining antibodies (IgA, IgD, IgE, IgG, IgM) directed against the allergen, for instance in the context of diagnosing in vitro type I allergy (IgE mediated allergy). The invention also concerns a method for hyposensitization of a mammalian individual, typically a human individual, suffering from type I allergy against a protein allergen.
The invention primarily concerns treating and diagnosing humans.
By a protein allergen is meant any protein/polypeptide causing a type I mediated allergic reaction. Thus the term encompasses any naturally occuring protein allergen including the smallest fragments thereof that will cause a type I allergic reaction in a mammal, most importantly humans.
In April 1997, the present inventors have published an article dealing with non-anaphylactic fragments of the Bet v 1 allergen. See Vrtala et al., "Conversion of the major birch pollen allergen, Bet v 1, into two non-anaphylactic T cell epitope containing fragments", J. Clin. Invest. 99(7) April 1997) 1673–1681.
Type I allergy represents a major health problem in industrialised countries where more than 20% of the population suffer from Type I allergic reactions (allergic rhinitis, conjunctivitis, allergic asthma and anaphylactic shock) (Kaplan (ed) Allergy. Churchill Livingstone, New York (1985)). Environmental proteins from pollen, mites and animal dander belong to the major components which induce release of biological mediators (e.g. histamine) by crosslinking effector cell (mast cell, basophil) bound specific IgE antibodies. The production of specific IgE from B-cells is stimulated by allergen specific T-helper cells which in their majority belong to the TH2 type (Romagnani, Immunol Today 13 (1992) 379–381). Therapy of Type I allergic diseases is currently performed by pharmacological treatment and by specific immunotherapy. Specific immunotherapy has been established already early in this century (Noon, Lancet 1 (1911) 1572–1573) and involves the systemic application of increasing doses of allergens for extended periods. Although specific immunotherapy is recognized as effective treatment, the occurrence of anaphylactic side effects represents one of the major disadvantages of this therapy. To reduce anaphylactic reactions the use of T-cell epitopes has recently been proposed for allergen specific immunotherapy (Briner et al., Proc. Natl. Acad. Sci. USA 90 (1993) 7608–7612, and Norman, Curr. Opin. Immunol 5 (1993) 986–973). Allergens harbour a great variety of different T-cell epitopes (Ebner et al., J. Immunol 150 (1993) 1047–1054; Joost-van-Neerven et al., J. Immunol. 151 (1993) 2326–2335; and Schenket al., J. Allergy Clin. Immunol. 96 (1995) 986–996) which may overlap with continuous IgE-epitopes. To prevent crosslinking of effector cell (mast cell, basophil) bound IgE and mediator release, T-cell epitopes and IgE epitopes need to be dissected. Following the concept of converting a major allergen into a T-cell vaccine we have selected Bet v 1 (Breiteneder et al., EMBO J. 8 (1989) 1935–1938), the major birch pollen allergen as a model. Bet v1 was selected because epitope analysis indicated that it forms conformational IgE epitopes (Visco et al., J. Immunol. 157 (1996) 956–962; and Laffer et al., J. Immunol. 157 (1996) 4953–4962). In addition Bet v1 represents one of the most common allergens which is recognized by 95% of tree pollen and food allergic individuals and almost 60% of them are sensitisized exclusively against Bet v1 (Jarolim et al., Allergy 44 (1989) 385–394). The cDNA coding for Bet v1 has recently been isolated (Breitenederet al., EMBO J. 8 (1989) 1935–1938) and recombinant Bet v1 was expressed in Escherichia coli (Valenta et al., J. Allergy Clin. Immunol. 88 (1991) 889–894; and Ferreira et al., J. Biol. Chem. 268 (1993) 19574–19580). Recombinant Bet v1 has been shown to possess similar IgE-binding capacity as natural Bet v1 and shares IgE as well as T-cell epitopes with Bet v1 homologous proteins present in pollen from various trees and plant derived foods (Ebner et al., J. Allergy Clin Immunol. 95 (1995) 962–969; Ebner et al., J. Immunol 150 (1993) 1047–1054; and Schenk et al., Eur. J. Biochem. 224 (1994) 717–724). The biological activity of the recombinant Bet v1 has been demonstrated by histamine release experiments and by skin prick testing of allergic patients (Valenta et al., J. Allergy Clin. Immunol. 91 (1993) 88–97; Pauli et al., J. Allergy Clin. Immunol. 98 (1996) 1100–1109; and Menz et al., Clin. Exp. Allergy 26 (1995) 50–60).

Non-anaphylactic forms of allergens and their use


The clip of the present invention can be used to mount a number of different objects onto an associated panel system. Due to its design, the clip can be used either to support or carry a number of different objects. Thus, the same clip and panel system can be used to offer customized products for customers. Further, since the clip is provided with a tension control element that acts against the associated panel system when the clip is mounted on the panel, the clip ensures that an object is mounted securely on the panel.

The present invention is directed generally to a mounting device and specifically to a clip for mounting objects on a panel system.
Mounting devices having various designs and functions are well-known. A shortcoming common to these known devices is their lack of versatility. Such devices are often limited to a single use or application. For example, such devices can be used to mount only one type of object. Thus, there is a need in the art for a mounting device that is versatile and therefore can be used for a number of different applications.
The known mounting devices suffer from yet another shortcoming. They are not provided with a tension control element to ensure the secure mounting of an object. Thus, there is a need in the art for a device that securely mounts objects on an associated panel system.
The present invention meets the shortcomings of the prior art by providing a clip that can be used to mount a number of different objects onto an associated panel system. Due to its design, the clip can be used either to support or carry a number of different objects. Thus, the same clip and panel system can be used to offer customized products to customers.
Further, the present invention meets the shortcomings of the prior art by providing a clip device having a tension control. Specifically, the clip includes a standard spring plunger that acts against the associated panel system when the clip is mounted on the panel. Thus, the clip with this spring plunger ensures that the object is mounted securely on the panel.


Disclosed are methods for rectifying or ameliorating abnormal responses of mammalian immune systems, such as rheumatoid arthritis. Also disclosed are methods for modifying normal responses of the mammalian immune system. Further disclosed are methods for accomplishing the foregoing by administering to a mammal a prolactin reducer and/or enhancer at a pre-determined time or times during a 24-hour period that results in modification of the mammal's abnormal prolactin profile so that it approaches or conforms to the prolactin profile of a young, healthy mammal of the same species (or to a standard profile generated from such individuals). Additionally, methods of upregulating or augmenting an immune response in a mammal are disclosed.

1. Field of the Invention
This invention relates to methods for rectifying or ameliorating abnormal responses of the mammalian immune system, and modifying normal responses of the mammalian immune system. More particularly, this invention relates to methods employing the alteration of prolactin rhythms as a method of adjusting mammalian immune response.
2. Prolactin and Immunity
The importance of neuroendocrine regulation of immunity has become increasingly evident during the past decade (Besedovsky, H. O. et al., J. Immunol. 135:750s-754s, 1985; Blalock, J. E., Physiol. Rev. 69: 1-54, 1989; Berozi, I., Dev. Comp. Immunol. 13:329-341, 1989). Much of this interest has focused on the anterior pituitary hormone prolactin, which has been reported to have potent, albeit inconsistent and often conflicting, effects on immune activity (Gala, R. R., Proc. Soc. Exp. Biol. Med. 198:5-13, 1991; Nicoletti, J. et al., Reprod. Immunol. 15:113-121, 1989; Vidaller, A., et al., Clin. Immunol. Immunopathol. 38:337-343, 1986; Gerli, R. et al., Clin. Immunol. 7:463-470, 1987).
The role of prolactin in immunity is exemplified by studies demonstrating exogenous prolactin-induced restoration of immune competence in hypophysectomized mammals (Gala, R. R., Proc. Soc. Exp. Biol. Med. 198:5-13, 1991; Bercal, I. et al., Acta Endocrinol. 98:506-513, 1981). In intact animals, prolactin administration has been associated with numerous immunological effects including stimulation of cellular or antibody responses, as well as stimulation of various immune system upregulating substances such as IL-2 (both IL-2 production and IL-2 receptor expression); enhancement of lymphocyte number, activity and mitogenic responses; and augmentation of macrophage cytotoxicity (Gala, R. R., Proc. Soc. Exp. Biol. Med. 198:5-13, 1991; Bernton, E. W. et al., Science 239:401-404, 1988; Rovensky, J. et al., Int. J. Immuno. Pharmac. 13:267, 1991).
Other lines of evidence reveal an association between hyperprolactinemia (i.e. elevated levels of circulating endogenous prolactin) which is due to natural, pathological, pharmaceutical, or stress conditions, and states of immune dysfunction, such as immunosuppression or autoimmune diseases. The autoimmune diseases for which exacerbative associations with prolactin have been observed in the past include rheumatoid arthritis, systemic lupus erythematosus (SLE) and multiple sclerosis. Nicoletti, J. et al., Reprod. Immunol. 15:113-121, 1989; Vidaller, A., et al., Clin. Immunol. Immunopathol. 38:337-343, 1986; Gerli, R. et al., Clin. Immunol. 7:463-470, 1987; McMurray, R. et al., J. Immunol. 147:3780, 1991.
In light of these apparently conflicting results, (increased prolactin level-associated augmentation of allo-immune response, exacerbated auto-immune response, and immunosuppression) the effects of elevated blood prolactin levels on the immune system have been far from clear.
In recent years, research has focused on improving the ability of the immune system to combat various diseases including malignancies. Experimental evidence that major histocompatibility antigens have an important role in host defenses against the development and spread of tumors has been rapidly accumulating.
Another line of research has specifically focused on suppression of autoimmune diseases, which are characterized by the inability of the immune system to recognize self tissue as "self" and by the mounting of an immune response against self tissue as though it were a foreign antigenic substance.
Yet another area of intensive immunological research is focused on various immunodeficiencies including AIDS. Despite intense research however, progress is slow and the immune mechanisms involved are proving elusive.
Numerous potential immunomodulatory agents are under current investigation by third parties for clinical usefulness. These agents include biologically derived compounds such as interferons and interleukins (and synthetic compounds such as isoprinosine and pyrimidinones). Although interferons and other cytokines and lymphqkines are naturally occurring substances, their clinical use (which has involved administration by injection) has not been consistently beneficial (and/or the favorable results have been short-lived). Furthermore, cytokine and lymphokine therapies are most often accompanied by severe side effects such as toxicity and fever.
Accordingly, there is a need in the field of immunology for agents which modify pathological immune system responsiveness and regulate the endogenous production of substances which are in turn native immune system regulators. Use of such agents to "re-program" the immune system: (i) would improve host resistance to infection and ability to combat existing infections; (ii) overcome immunosuppression, abate immunodeficiency, and improve immunity against tumors and restore normal immune function; and (iii) prevent or suppress autoimmunity and restore normal immune function.


The present invention is directed to a packaging, storage and display system for articles, such as small tools, like drill bits and the like. An index for holding the articles is pivotably mounted in a case. A rack, which may be selected from a variety of rack structures, is mounted within the index, for holding articles having particular sizes and shapes. A frame structure is resistively pivotably mounted on the index, so that the frame structure may be pivoted to a particular position relative to the index, and will tend to remain in that position, until a force in excess of a particular amount is exerted on the frame structure. The index and/or the frame structures may be interchangeably mounted.

1. The Technical Field
The present invention is directed to packaging, storage and display devices, such as are used for containing articles such as drill bits (for example, high speed, masonry, wood, general use bits, etc.), driver bits, other power tool and hand tool accessories and the like.
2. The Prior Art
Containers for packaging, storage and display of tools, particularly small tool items, such as drill bits, saw blades, bolt- and screwdriver bits, sockets and the like are known.
Some such containers are formed as a hinged plastic or metal two-piece hinged case, that is held closed by a resilient plastic or metal latch that is simply bent back to release a detent, and permit the two parts of the two-piece hinged case to be pivoted away from one another, to open like a book. The parts of the two-piece hinged case may have approximately the same dimensions, but be formed as essentially mirror images of each other, except for the latch structure.
In each part of the two-piece hinged case, positions for holding parts, e.g., drill bits, may be formed directly into the inner surfaces, in the form of pairs of prongs that are spaced apart and sized, so that each part position is formed to hold a specific drill bit (or other part) having a specific diameter or nominal size. That is, a bit of a particular size is pressed between the respective prongs (usually concave toward one another) of the respective pairs and snap-fitted in. Alternatively, elongated slots of different lengths and widths may be formed directly into the inside surfaces of the two-piece hinged case parts.
Alternatively, instead of forming prongs or slots directly into the inside surfaces of the two-piece hinged case parts, molded or stamped non-moving inserts that have specifically sized slots formed in them, may be positioned into the interior spaces of the two-piece hinged case parts. One such drill bit holder is sold by DeWalt® under the name New Guaranteed Tough™ Case.
In more complex versions, a bar or block (usually called an "index") may be fitted into the bottom portion of one or both parts of the two-piece hinged case. The index may have a number of blind bores or combinations of bores and aligned slots formed into it, again having different diameters, and possibly different depths as well, to receive tool parts (e.g., drill bits) of different size.
The index is often formed as a single piece that may be blow or injection molded (if plastic) or stamped (if made of thin metal). Often, the sizes (or other information) of the tools that are to be held in the index are printed or stamped into the front or back of the index, lined up with the locations of the respective tools.
The index may be fixed in place, such as by gluing or welding, simple friction or snap-fit. In some prior art tool bit holders, the index is provided at the opposite ends with male or female dovetail components that interfit with counterpart female or male dovetail components formed into the inside surfaces of the side walls of the two-piece hinged case part. One such drill bit holder is made and sold by Blu-Mol under the mark "Armor-Case".
In these three types of cases, the cases are fixed both in the sense that only specifically sized bits can be held in the cases, and in the sense that because the indexes (if provided) do not move, there is some limitation to the accessibility of the tool bits.
Alternatively the index may be provided with bumps that project from the ends of the index, that are received, e.g., in a snap-fit manner, in corresponding recesses, bores or slots formed in the inside walls of the two-piece hinged case part. In some prior art embodiments, the index must be bent or deformed in order to fit into the receiving recesses, bores or slots. These recesses, bores or slots may be provided in one or a number of pairs, so that the index may be placed at various locations along the "height" of the two-piece hinged case part. This permits the bar or index to be pivoted, relative to the two-piece hinged case part, so that the access to the parts is improved. Additional, smaller resilient projections may be provided to act as detents to hold the bars in place in their recessed positions. Pivoting of the bars out of their recessed positions thus requires some small effort to overcome the frictional or interference resistance of the smaller resilient projections. One such case is made and sold under the Skil® trademark.
In other prior art embodiments, the index, in addition to being configured to pivot, may be formed as a two-piece construction. One portion of the index engages, in a snap-fit manner, to the inside surface of the two-piece hinged case part, and is pivotably connected to the other portion of the index which pivots upwardly and out of the plane of the two-piece hinged case part. One example of such a case is made for and sold by Sears® under the Craftsman® mark, with the particular index construction being marketed under the mark Speed-Dex™. In this construction, the front area of the index that faces the user is open, so that there is no room for indicia in front of each bore, to indicate the bit sizes. In this product, the holder of the pivoting portion of the index must be glued in place, against the inside surfaces of the case part.
In the previously-mentioned case made and sold under the Skil® trademark, the index is formed from two pieces of a molded rubber or rubber-like material. One piece has a U-shaped cross-section, that forms the front, bottom and rear of the index. The second piece is a mostly solid wedge-shaped block, that is insertingly received and molded, glued or welded into the first piece, and has apertures formed in it to receive the shanks of the tool pieces.
In other kinds of tool part holders, the case may be formed again as a two-piece hinged case, but with the hinge located at the bottom of the case. One portion of the case is often larger or has more depth than the other portion. One of the portions may include a hole at the top, to permit the case to be hung from a hook, such as on a store shelf or in a workshop. These cases may also be fabricated from metal, plastic or a combination of metal and plastic.
Such bottom-hinged cases usually include an index that is pivotably connected to both parts, often using the axis of pivoting of the two parts also as the axis of pivoting for the index, and held in place by wire and metal rivets. In some of these prior art constructions, there may be provided detents or ridges on one or both of one of the case parts and the index. Upon opening of the case, once the two parts have been pivoted away from one another by a certain angle or amount, the index is forced or at least prompted to pivot away from one or both case parts. This results in the index being moved to an angular position somewhere between the two case parts. Alternatively, a hook or wire may connect one of the case parts to the index, to both prompt movement of the index and hold the index in place once the case has been opened. Such cases are used to package and sell drill bits sold by MIBRO®.
These cases can exhibit certain characteristics that may make them less than optimal, such as that in some prior art cases having indexes that are not positively affixed, the indexes can fall out when the cases are opened. In some of the two-piece hinged case (book-opening style) cases, the indexes may be configured to pivot, but once out of their recessed positions, there is nothing to hold the index in its elevated position, so that the index tends to fall back into the case part from which it has been pivoted. Alternately, in the bottom hinged cases, the interlocking of the index to the movements of the case parts constrains the movement and positioning of the index to a single specific position, when the case has been opened to its in-use position.
It would be desirable to provide a packaging, storage and display case for holding small tool parts, that is capable of adaptation to accommodate different combinations of tools of different sizes.
It would also be desirable to provide a packaging, storage and display case for holding small parts, that is provided with an index that is capable of being moved to a variety of different positions, and held in any such different position.
It would also be desirable to provide a packaging, storage and display case for holding small parts, that is provided with an index that can be moved between stowed and deployed positions repeatedly, while reliably maintaining the selected stowed positions.
It would be desirable to provide a system of packaging, storage and display components that provides for enhanced flexibility in packaging and storage of individual tool parts.
These and other desirable characteristics of the present invention will become apparent in view of the present specification, including claims, and drawings.

Packaging, storage and display apparatus and system


A wireless base station that performs data communication using a plurality of sub carriers, and repeatedly generates frame patterns comprising one combination or more of at least two types of frames in which the number of common pilots in each is different, and transmits data for mobile terminals having poor receiving quality in a frame having a large number of common pilots, and transmits data for mobile terminals having good receiving quality in a frame having a small number of common pilots.

This invention relates to a wireless communication method and wireless base station, and more particularly to a wireless base station and wireless communication method that performs data communication using sub-carriers.
In a Digital Terrestrial Television system or an OFDM communication system that uses OFDM (Orthogonal Frequency-Division Multiplexing), measurement of the receiving power of the signal, controlling the receiving power, and channel estimation are performed using a time-division multiplexed common pilot signal as the transmission signal.
FIG. 29 is a drawing showing the construction of a transmission apparatus in an OFDM communication system, where a data-modulation unit 1 modulates the transmission data (user data or control data) using QPSK modulation, and converts the transmission data to a plurality of baseband signals (symbols) having an in-phase component and quadrature component. A time-division-multiplexing unit 2 performs time-division multiplexing of the pilots of a plurality of symbols in front of the data symbols. A serial-to-parallel converter 3 converts input data to parallel data of M symbols, and outputs M sub-carrier samples S0 to SM-1. An IFFT (Inverse Fast Fourier Transform) unit 4 performs IFFT (inverse fast Fourier transformation) processing of the sub-carrier samples S0 to SM-1 that were input in parallel and combines them to output a discrete-time signal (OFDM signal). A guard-interval insertion unit 5 inserts a guard interval into the M symbol long OFDM signal that was input from the IFFT unit 4, and a transmission unit (TX) 6 performs DA conversion of the OFDM signal inserted with a guard interval, and converts the frequency of the OFDM signal from baseband to the wireless band, then performs high-frequency amplification and transmits the signal from an antenna 7.
FIG. 30 is a drawing explaining the serial-to-parallel conversion, where a common pilot P is time multiplexed in front of one frame of transmission data. In the case where the common pilot per frame is 4×M symbols, and the transmission data is 28×M symbols, the M symbols of the pilots are output from the serial-to-parallel converter 3 the first four times as parallel data, and after that the M symbols of the transmission data are output 28 times as parallel data. As a result, the pilots in one frame period can be time multiplexed on all of the sub carriers and transmitted 4 times, and on the receiving side the channel is estimated for each sub carrier using those pilots, and channel compensation (fading compensation) becomes possible. An OFDM symbol is configured with M symbols.
FIG. 31 is a drawing explaining the insertion of guard intervals. Guard-interval insertion is copying the end section to the start section of an IFFT output signal that corresponds to M sub-carrier samples (=1 OFDM symbol). By inserting guard intervals GI, it is possible to do away with the effect of symbol interference due to a multipath.
FIG. 32 is a drawing showing the construction of an OFDM receiving apparatus. The signal that is output from the transmission antenna 7 is received by the receiving antenna 8 of the receiving apparatus via a fading propagation path, and a receiving circuit (Rx) 9 converts the RF signal that was received from the antenna to a baseband signal, and performs AD conversion to convert that baseband signal to a digital signal, then an FFT timing synchronization circuit 10, which extracts the signal of a desired band from the signal after AD conversion, detects the FFT timing from a time domain signal that includes the signal of the desired band that is output from the receiving circuit 9, and a symbol-extraction unit 11 extracts the OFDM symbols at FFT timing and inputs them to an FFT unit 12. The FFT unit 12 performs FFT (fast Fourier transformation) processing for each extracted OFDM symbol, and converts the signal to frequency domain sub-carrier samples S0′ to SM-1′. By calculating the correlation between the pilot symbols that were received during a set interval and a pre-known pilot pattern, a channel-estimation circuit 13 estimates the channel for each sub carrier, and a channel-compensation circuit 14 uses the estimated channel value to compensate for channel fluctuations of the data symbols. By the above processing, transmission data that is distributed by each sub carrier is demodulated. After that, the demodulated sub-carrier signals (not shown in the figure) are converted to serial data, and decoded. The example above is a process in which pilots are used in channel estimation, however, they can also be used in measuring the received signal power, SN ratio or the like.
As shown in FIG. 33, when pilot symbols exist at only the start and/or end of a frame, the receiving power of the data between pilots is estimated by the receiving power of the pilots. As shown by the solid line A in FIG. 34, when the speed of movement of a mobile station is slow, for example, walking speed (approximately 4 km/h), the time-variation interval of the received electric field intensity E becomes long, the variation width becomes small, and sudden drops decrease, so it is easy to estimate the receiving power of the pilot symbols. However, as shown by the dashed line B in FIG. 34, when the speed of movement of a terminal is fast, the time-variation interval becomes short and the variation width becomes large. Furthermore, it becomes easy for sudden drops to occur. As a result, the precision of estimating the receiving power between pilot symbols decreases. Also, the channel estimation precision decreases, and since decoding and demodulation are performed using these poor estimation results, the quality of communication decreases. In other words, when moving at high speed, the channel estimation precision decreases and thus the communication quality and throughput decrease. A detailed case will be explained below.
A case is presumed in which communication is performed with a base station having 100 terminals inside a cell, where 50 of the terminals are moving at high speed, and the remaining 50 terminals are moving at low speed or are still. The channel estimation precision of the terminals moving at high speed decreases, as well as the quality of communication decreases and the transmission speed decreases. Here, supposing that it is not possible to maintain the required communication quality for 25 of the high speed terminals, and the transmission speed becomes 0, the overall transmission speed throughput of the base station becomes 0.75. Hereupon it is assumed that the throughput is 1 when all of the terminals are moving at low speed or are still. In this way, when the interval between pilot symbols is long, the communication quality of terminals moving at high speed decreases, and the overall transmission speed (throughput) of the base station decreases.
First Prior Art
In regards to the problem described above, a method is feasible, as shown in FIG. 35, in which the interval between common pilot symbols is narrowed, and the number of pilot symbols is increased. However, in this method the following problems exist, so this method is not desirable.
(1) The pilot symbols are common pilot symbols, so the number of symbols increases regardless of whether or not the terminal is moving at high speed.
(2) Data is decreased by the amount that pilot symbols are added, so the actual transmission speed decreases.
A detailed example will be explained below.
Supposing that the overall transmission speed of a wireless frame is 10 Mbps. Then here, the ratio between the normal number of pilot symbols and the number of data symbols is taken to be 0.1:0.7. The remaining 0.2 is the control signal. Therefore, the actual transmission speed is 7 Mbps.
Next, as countermeasures for high-speed movement, the interval between pilot symbols is narrowed, and 2× the number of pilot symbols are inserted. By doing this, the aforementioned ratio becomes 0.2:0.6, and the actual transmission speed drops to 6 Mbps. Therefore, even though some terminals may be moving at low speed, when pilots are added and inserted as a countermeasure for high-speed movement, the actual transmission speed becomes 1 Mbps (15%) less than 7 Mbps. As described above, by simply just adding pilot symbols, a drop in actual transmission speed, as well as a decrease in throughput occurs. Therefore, the overall transmission speed (throughput) of the base station decreases.
To handle this problem, a method has been proposed that performs variable control of the number pilot symbols according to the propagation environment (see JP 2000-151548A and JP 2005-027294A). This method measures the propagation environment, and performs control so that when the propagation environment is poor, it increases the number of pilots, and when it is good, decreases the number of pilots. However, the number of symbols is increased or decreased for each individual mobile station, so control is complicated. Particularly, there is a problem in that since the number of symbols is increased or decreased for each individual mobile station, scheduling control becomes difficult.
Second Prior Art
Also, in regards to terminals moving at high speed, as shown in (a) of FIG. 36, a method has been proposed in which, in addition to common pilots P, dedicated pilots PD are added between the common pilots (see JP 2001-197037A). However, in this method of inserting dedicated pilots, control must be performed of measuring the propagation environment and inserting dedicated pilots when the environment is poor, and not inserting pilots when the environment is good. Therefore, as in the first prior art, control of each individual mobile terminal is necessary, and there is a problem in that together with the control being complicated, scheduling control becomes difficult. Also, the insertion position where the dedicated pilots are inserted is treated as a special position, and when dedicated pilots are not inserted, then as shown in (b) of FIG. 36, a special control signal is inserted, thus data decreases and transmission speed drops. In other words, for terminals moving at low speed, data cannot be inserted in the positions where the dedicated pilots are inserted, so as a result, the same problem occurs as in the case when the interval between pilot symbols is narrowed and the number of pilot symbols is increased.

Wireless base station and wireless communication method


A method for introducing desired electromagnetic radiation into a photonic crystal having a photonic bandgap and at least one defect, wherein the desired electromagnetic radiation has a frequency within the photonic bandgap. The method includes the steps of: delivering source electromagnetic radiation having an electromagnetic frequency outside the photonic bandgap to the defect; and generating the desired electromagnetic radiation at the defect in response to the source electromagnetic radiation.

This invention relates to optoelectric devices, their methods of use, and, in particular, methods of using photonic crystals.
Photonic crystals are structures having a periodic variation in dielectric constant. A one-dimensional example of a photonic crystal is an alternating stack of dielectric layers, which includes the well-known "quarter-wave stack" dielectric mirror. Light of the proper wavelength at normal incidence to such a mirror is completely reflected by the mirror. One description of the basis for this complete reflection is destructive interference between multiply-scattered waves of light inside the stack. An alternative description is that the solutions for propagating electromagnetic (EM) modes within the periodic stack give rise to a photonic "band" structure, in which propagating EM modes having frequencies within a "photonic bandgap" cannot exist within the periodic stack. EM waves having these frequencies are therefore completely reflected by the stack when incident on the stack. This band theory for EM waves is analogous to the band theory developed for electrons in crystals.
In general, the position and width of a photonic bandgap will depend on the propagation direction of the propagating EM wave and its polarization. In multi-dimensional photonic crystals (i.e., materials having a periodic dielectric constant along more than one dimension), a photonic bandgap can exist over a larger range of propagation directions. For example, a three-dimensional (3D) photonic crystal, such as a solid structure formed from dielectric spheres at the sites of a diamond lattice, can have a "complete photonic bandgap". Within such a photonic crystal, no propagating EM modes having frequencies within the complete photonic bandgap can propagate, regardless of propagation direction and polarization.
By fabricating photonic crystals having specific periodicities, the properties of the photonic bandgap can be tailored to specific applications. For example, the central wavelength of a photonic bandgap is approximately equal to the periodicity of the photonic crystal and the width of the photonic bandgap is proportional to the differences in dielectric constant within the photonic crystals. For a general reference, see: J. D. Joannopoulos et al., Photonic Crystals, (Princeton University Press, Princeton, 1995), the contents of which are incorporated herein by reference.
Photonic crystals can also include defects with respect to their periodicity that support a localized electromagnetic mode having a frequency within a photonic bandgap. For example, in a three-dimensional photonic crystal formed from dielectric spheres at the sites of a diamond lattice, the absence of a sphere produces a defect. In the immediate vicinity of the absent sphere, the photonic crystal is no longer periodic, and a localized electromagnetic mode having a frequency within the photonic bandgap can exist. This defect mode cannot propagate away from the absent void, it is localized in the vicinity of the defect. Thus, the introduction of a defect into the photonic crystal creates a resonant cavity, i.e., a region of the crystal that confines EM radiation having a specific frequency within the region. Resonant cavities are used in optical devices such as lasers and light-emitting diode displays, as well as components for microwave and millimeter wave applications, such as filters and power generators. Brommer et al. describes fabricating such devices by introducing defects into photonic crystals in U.S. Pat. Nos. 5,187,461, 5,389,943 and 5,471,180, the contents of which are incorporated herein by references. In these applications, separate dielectric waveguides channel the confined EM radiation into, and away from, the defect region.
In other applications, a photonic crystal includes a series of defects that combine to form a waveguide within the photonic crystal. The series of defects support EM modes having frequencies within the photonic bandgap that can propagate along the series of defects but are otherwise confined to regions of the photonic crystal in the vicinity of these defects. Defect-based waveguides in photonic crystals can include sharp turns since the photonic bandgap can prevent propagation of the EM radiation away from the waveguide for at least some, if not all, propagation directions. Waveguides based on photonic crystals and incorporated into optoelectronic integrated circuits are described by Meade et al. in U.S. Pat. No. 5,526,449, the contents of which are incorporated herein by reference.

Methods and systems for introducing electromagnetic radiation into photonic crystals


In a SRAM of a selected word line structure, each local decoder is connected to a corresponding main word line and a corresponding Z decoder signal line. Each local decoder includes a circuit including two MOS transistors connected in series to each other which circuit has one end grounded. The corresponding local word line is connected to a node between these two transistors. Out of the corresponding main word line and the corresponding Z decoder signal line, one is connected to the gates of these transistors and the other is connected to the other end of said circuit, which the other end is not grounded. The potential on the corresponding local word line attains a high level only when the potential on the signal line connected to the gate of these two transistors, is at a logical level at which the transistor can be turned on and the potential on said one signal line is at a high level. Theoretically, therefore, each local word line is controlled to be activated or inactivated by the operations of two elements in the corresponding local decoder.

1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to semiconductor memory devices of a divided word line structure.
2. Description of the Background Art
A SRAM (Static Random Access Memory) is a semiconductor memory device whose storage data is not lost unless power is turned off. With a recent increase in capacity of a semiconductor memory device, the number of memory cells connected to each word line in such SRAM has been increased.
FIG. 26 is a schematic block diagram of a function of the entire structure of a SRAM and includes only a minimum function block necessary for describing a basic operation of the SRAM, that is, a reading and writing operation. In FIG. 26, a memory cell array 102 includes a circuit structure of a memory cell illustrated as a representative. In practice, memory cell array 102 comprises memory cells each having a shown circuit structure arranged in a matrix of a plurality of rows and columns. A word line WL is provided for each of the plurality of rows and a bit line pair of BitL and BitR is provided for each of the plurality of the columns. Each memory cell is connected to a word line WL and a bit line pair of BitL and BitR respectively corresponding to the row and the column in which the memory cell is disposed.
A basic operation of the SRAM will be described with reference to FIG. 26.
In writing data to a memory cell 200, an external address signal is applied to an address signal input circuit 104, the signal indicative of a location (address) of the memory cell 200 to which data is to be written in memory cell array 102. Address signal input circuit 104 charges a voltage amplitude of the external signal to a voltage amplitude suitable for an internal circuit of this SRAM. For example, if the external signal has a TTL level with its H level (logical high) being 2.2 V and its L level (logical low) being 0.8 V, the voltage amplitude thereof is 1.4 V. If a signal of the internal circuit of the SRAM has an MOS level with its H level being 5 V and its L level being 0 V, its voltage amplitude is 5 V. In such a case, therefore, address signal input circuit 104 changes the voltage amplitude 1.4 V of the external signal to 5 V.
The address signal (hereinafter referred to as an internal address signal) which level has been changed by address signal input circuit 104 is converted into a word line select signal and a bit line pair select signal by an address signal decoding circuit 106.
Memory cell 200 is selected by a word line WL connected thereto attaining a high level potential and a bit line pair of BitL and BitR connected thereto being electrically connected to an internal data bus (not shown) referred to as an I/0 line. The above-described word line select signal and bit line pair select signal are a signal bringing only the potential on the word line WL connected to memory cell 200 to high and a signal electrically connecting the bit line pair of BitL and BitR connected to memory cell 200 with the I/0 line, respectively.
After the selection of memory cell 200 by the word line select signal and the bit line pair select signal, data to be written to memory cell 200 is transferred from the I/O line to the bit lines. The data to be written is supplied to a data signal input circuit 108 as an external signal. Data signal input circuit 108 changes the voltage amplitude of the external data signal to that of the MOS level and applies the level converted signal to a data write circuit 100.
Data write circuit 100 transfers the converted data signal to the I/O line by using a transistor (not shown) with a current drivability enabling a drive of the bit line pair of BitL and BitR. As a result, the bit line pair of BitL and BitR receives the data signal as complementary potentials.
Meanwhile, N channel MOS transistors 210 and 220 are turned on in memory cell 200 in response to a high level potential on the word line WL. Therefore, when the potentials on the bit lines BitL and BitR are at a high level and a low level, respectively, an N channel MOS transistor 240 is rendered conductive in response to a potential increase of a node N1 caused by the high level potential on the bit line BitL and conversely, an N channel MOS transistor 230 is rendered non-conductive in response to a potential drop of a node N2 caused by the low level potential on the bit line BitR. As a result, the potentials transmitted from the I/O line onto the bit lines BitL and BitR are held at nodes N1 and N2. In other words, even after the potential on the word line WL attaining a low level to render transistors 210 and 220 non-conductive, the non-conductive transistor 230 causes the potential at node N1 to remain a high potential (logic high level) transmitted from a power supply Vcc through a resistance element 250, while the conductive transistor 240 causes the potential at node N2 to remain a low potential (.apprxeq.0 V: logic low level) determined by a ratio of a resistance value of a resistance element 260 to an ON resistance value of transistor 240.
The foregoing operation completes data writing in memory cell 200.
In reading data from memory cell 200, an external address signal corresponding to memory cell 200 from which data is to be read is supplied to address signal input circuit 104 as is done in data writing. As a result, the potential on the word line WL connected to memory cell 200 attains a high level to electrically connect the bit line pair BitL and BitR connected to memory cell 200 with the I/O line. The potential increase of the word line WL renders transistors 210 and 220 conductive. As a result, when the potentials at nodes N1 and N2 are respectively at a high level and a low level, for example, the potential on the bit line BitR drops because of current flow from the bit line BitR to ground GND through transistors 210 and 240. Conversely, the potential on the bit line BitL om ,aomtaomed at the high potential at node N1 because no current is generated flowing from bit line BitL to ground GND. That is, complementary potential changes corresponding to the storage data (the potentials maintained at nodes N1 and N2) of the memory cell 200 appear on the bit lines BitL and BitR, respectively.
Differently from data writing, the I/O line is electrically connected to a data amplification circuit 112 in data reading. Therefore, the storage data of memory cell 200 is transferred to data amplification circuit 112 after appearing on the bit lines BitL and BitR.
Data amplification circuit 112 amplifies the potential changes of the bit lines BitL and BitR by amplifying a difference voltage between the potentials on the bit lines BitL and BitR to convert the level of the data signal read from memory cell 200 into a signal level (ordinarily an MOS level) for use in the internal circuit of this SRAM. The level converted data signal is externally output through a transistor (not shown) having a current drivability enabling drive of an external data bus (not shown) and provided in a data signal output circuit 114.
The foregoing operation completes data reading from memory cell 200.
A write control signal input circuit 111 controls data write circuit 100 and data amplification circuit 112 to operate in such a manner as described above. The circuit arrangement of the memory cell shown in FIG. 26 is generally-called high resistive load type, which uses resistance elements 250 and 260 having a large resistance value as loads.
Since in data reading, the potentials on the bit lines BitL and BitR should be fully changed in response to the potentials at nodes N1 and N2, respectively, it is preferable that resistances and capacitances of the bit line pair of BitL and BitR are small.
For example, when high level and low level potentials are maintained at nodes N1 and N2, respectively, the potential on the bit line BitR drops more rapidly in data reading with more current flowing from the bit line BitR to ground GND through transistors 210 and 240. Conversely, when low level and high level potentials are maintained at nodes N1 and N2, respectively, the potential on the bit line BitL drops more rapidly with more current flowing from the bit line BitL to ground GND through transistors 220 and 230. That is, transistors 230 and 240 in the memory cell drive the bit lines BitL and BitR, respectively, in data reading.
Therefore, in order to read out the storage data of memory cell 200 onto the bit line pair of BitL and BitR rapidly and reliably, it is desirable that currents are large, the current which can be drawn by transistor 230 from one bit line BitL to ground GND through transistor 220 and the current which can be drawn by transistor 240 from one bit line BitR to ground GND through transistor 210. However, each transistor size in a memory cell is very small. On the other hand, each bit line length is very large relative to such transistor size. Therefore, resistances and capacitances of the bit lines BitL and BitR are preferably small to allow transistors 230 and 240 in memory cell 200 to rapidly draw some amount of current from the bit lines BitL and BitR, respectively.
Then, the bit line pair of BitL and BitR is formed of metal to have sufficiently small resistances and capacitances.
On the other hand, the word line WL is connected to the gates of transistors 210 and 220 of memory cell 200. In general, a gate of an MOS transistor is formed of a material such as polysilicon having a resistance value larger than that of metal. Therefore, a word line WL formed of metal requires a contact hole for connecting a polysilicon layer constituting the gates of transistors 210 and 220 with a metal layer serving as a word line WL. Such contact hole, however, in general, prevents a semiconductor integrated circuit from being highly integrated and makes a manufacturing process complicated. Then, the word line WL is formed of such a material as polysilicon having a large resistance value than that of metal to be contiguous to the gates of transistors 210 and 220.
However, with a recent increase in capacity of a SRAM, the number of memory cells arranged in each row is increased, which is followed by an increase in length of each word line WL. As a result, a resistance and a capacitance of each word line WL are significantly increased, whereby address signal decoding circuit 106 requires more time to change the potential on the word line WL to a high level.
Transistors 210 and 220 do not rapidly become conductive in memory cell 200 when the word line WL does not rapidly attain a high level potential. As a result, more time is required for the potentials on the bit lines BitL and BitR to be changed in response to the storage data of memory cell 200 in data reading and for the potentials at nodes N1 and N2 to be forced to a level corresponding to external data in data writing. Therefore, such increase in a length of the word line WL increases a time period, i.e. an access time, from a supply of an external address signal to address signal input circuit 104 to data reading from or data writing in a memory cell 200 corresponding to the address signal.
While such problem can be avoided to a certain degree by increasing a size of transistors in address signal decoding circuit to increase a drivability of address signal decoding circuit 106 with respect to the word line WL, it is not possible to increase a size of elements in a semiconductor integrated circuit device without limit. Therefore, the word line WL should be driven by the elements of a limited size provided in address signal decoding circuit 106 irrespective of an increase of the word line length. The problem cannot be resolved in this manner.
As a conventional technique for avoiding such problem as described above, each word line WL is divided into a plurality of sections each section being provided with a decoding circuit for driving the section, which technique is referred to as a divided-word line structure. Such divided-word line technique is disclosed in U.S. Pat. Nos. RE32993 and 4,554,646, for example.
FIG. 27 is a schematic diagram showing the principle of such word line division in a SRAM. The principle of the word line division will be briefly described with reference to FIG. 27.
As shown in FIG. 27(a), a memory cell array 102 is divided into a plurality of blocks in the direction of a row. As shown in FIG. 27(b), each row includes a word line which is divided into individual blocks. Hereinafter, these individually provided word lines are referred to as local word lines. That is, a plurality of local word lines provided corresponding to each row constitutes one word line group in memory cell array 102. Local word line selection is carried out by generating a signal for selecting one local word line in one word line group (hereinafter, referred to as a local word line signal) as shown in FIG. 27(c) by obtaining a logical product of a signal for selecting one block among the plurality of blocks constituting memory cell array 102 (hereinafter referred to also as a Z decoder signal) and a signal for selecting one group among the plurality of word line groups included in memory cell array 102 (hereinafter referred to also as a main word line signal).
As shown in FIG. 27(d), in memory cell array 102, bit line pairs of the corresponding columns of blocks constitute one bit line pair group. One bit line pair is selected from each block by a signal selecting one group among the plurality of bit line pair groups in memory cell array 102.
As shown in FIG. 27(e), out of the memory cells connected to the plurality of the bit line pairs included in the selected one bit line pair group, one memory cell connected to the selected one local word line is selected through such local wide line selection and bit line pair selection. As described above, an address of a memory cell from and in which data is to be read and written is determined by a block address indicative of n-th block to be selected among the plurality of blocks, a row address indicative of an n-th row word line group to be selected among the plurality of word line groups, and a column address indicative of an n-th column bit line pair group of each block to be selected among the plurality of bit line pair groups.
Then, a SRAM of a divided-word line structure includes circuits for generating a local word line signal (hereinafter referred to as a local decoder) by obtaining a logical product of the Z decoder signal and the main word line signal, which circuit is provided for each block.
FIG. 28 is a schematic diagram showing an arrangement of the vicinity of the memory cell array, including a local decoder of the SRAM having a divided-word line structure.
In a memory cell array as shown in FIG. 28, divided n blocks BL0-BL (n-1) are provided with local decoder, groups DEC0-DEC (n-1), respectively. These blocks BL0-BL (n-1) include the same number of local word lines LWL0-LWL (n-1), respectively. Local decoder groups DEC0 -DEC (n-1) include, as local decoders LD0-LD (n-1), logical gates provided corresponding to the local word lines LWL0-LWL (n-1) included in the corresponding blocks BL0-BL (n-1), respectively.
A row decoder 6 is provided for supplying main word line signals to the local decoder groups DEC0-DEC (n-1). A Z decoder 18 is provided for supplying Z decoder signals to the local decoder groups DEC0-DEC (n-1). Row decoder 6 has output signal lines MWL each provided for each row. The signal lines MWL are referred to as main word lines. Z decoder 18 has output signal lines ZL each provided corresponding to each of the local decoder groups DEC0-DEC (n-1). The signal lines ZL are referred to as Z decoder signal lines.
Each of the local decoders LD0-LD (n-1) receives a signal on the corresponding Z decoder signal line ZL and a signal on the main word line MWL of the corresponding row as inputs to selectively generate, onto the corresponding one of the local word lines LWL0-LWL (n-1), a local word line signal for selecting the corresponding local word line.
Row decoder 6 includes logical gate circuits 40 each provided corresponding to each main word line MWL, for example. Upon reception of an external address signal indicative of a row address, one of the logical gate circuits 40 in row decoder 6 outputs, onto the corresponding main word line MWL, a main word line signal for activating the main word line MWL.
Z decoder 18 outputs, onto one of the signal lines ZL, a Z decoder signal for activating the signal line ZL in response to an external address signal indicative of a block address. At this time, both of the potentials on the activated Z decoder signal line and the activated main word line MWL are at a high level. Therefore, with 2-input AND gates being used as the local decoders LD0-LD (n-1), only one local word line connected to one local decoder receiving the potential on the activated main word line MWL and the potential on the activated Z decoder signal line ZL as inputs is brought to a high level. That is, only one local word line receives a local word line signal for activating the local word line.
For the purpose of simplicity, neither bit line pair nor memory cell is shown in FIG. 28.
FIG. 29 shows an actual layout of local decoder groups and divided memory cell array blocks on a semiconductor substrate in such SRAM of a divided-word line structure.
In practice as shown in FIG. 29, n (n is an even number) divided divisional blocks BL0-BL (n-1) of a memory cell array fall into n/2 groups each group including two blocks in view of layout. Then, in each of these n/2 groups, an even-numbered local decoder group provided corresponding to the even-numbered block and an odd-numbered local decoder group provided corresponding to an odd-numbered block located adjacent to the even numbered block are disposed between these two blocks.
Recently proposed in "S. Aizaki et al, IE.sup.3 ISSCC Digest of Technical Papers, pp. 126-127, 1990" and the like is a further division of the row direction divided blocks BL0-BL (n-1) into a plurality of blocks divided in a column direction. FIG. 30 is a circuit diagram showing a schematic arrangement of a main part of a SRAM wherein a memory cell array is divided into 32 blocks of BL0-BL31 in a row direction, each block further divided into 128 sub-blocks of SBL0-SBL127 in a column direction. Each of the blocks BL0-BL31 includes the same number of memory cell columns. Similarly, each of the sub-blocks SBL0-SBL127 includes the same number of memory cell rows.
When each block is further divided into a plurality of sub-blocks in a column direction, row decoder 6 has 128 output signal lines, i.e. 128 main word lines MWL provided corresponding to the sub-block groups SBL0-SBL127. Row decoder 6 includes logical gate circuits 40 provided corresponding to the main word lines MWL, for example. Upon reception of an external address signal indicative of a row address, one of these logical gates 40 applies, to the corresponding main word line MWL, a potential (high level) activating the main word line.
Z decoder 18 has output signal lines, i.e. Z decoder signal lines ZL provided in the same number (m) of the local word lines included in one sub-block for each of the 32 blocks BL0-BL31. Therefore, the plurality of Z decoder signal lines provided corresponding to each of the blocks BL0-BL31 constitute one signal line group ZLG. In response to an external address signal indicative of a block address and an external address signal indicative of a row address, Z decoder 18 supplies, to only one of all the signal lines ZL included in these signal line groups ZLG, a high level potential for activating the one signal line ZL.
Local decoder groups DEC0-DEC31 are provided corresponding to the blocks BL0-BL31, respectively. More specifically, located between each of the odd-numbered blocks BL1, BL3, . . . BL31 and each of the even-numbered blocks BL0, BL2, . . . BL30 adjacent thereto are two local decoder groups corresponding to these two blocks as described above.
The local decoder groups DEC0-DEC31 include logical gate circuits LD0-LD31 as local decoders, respectively, which logical gate circuits are provided for the respective local word lines LWL0-LWL31 included in the corresponding blocks BL0-BL31.
A signal on each main word line MWL is applied in common to all the local decoders LD0-LD31 provided corresponding to the 32 sub-blocks (any of SBL0-SBL127) corresponding to this main word line MWL. A plurality of signal lines included in each Z decoder signal line group ZLG are provided corresponding to a plurality of local word lines in the corresponding block (any of BL0-BL31). Then, the plurality of lines included in each signal line group ZLG are connected in common to 128 local decoders provided corresponding to 128 local word lines corresponding to 128 sub-blocks SBL0-SBL127 included in the corresponding one block.
Therefore, each of the local decoders LD0-LD31 comprises a two-input AND gate, only one local decoder connected to an activated main word line MWL and an activated Z decoder signal line ZL activates the corresponding one local word line. That is, only one local decoder outputs a local word line select signal.
As described above, when a plurality of row direction divided blocks are further divided in a column direction, local word line selection is carried out by row decoder 6 outputting a signal indicating that an n-staged one, out of the sub-blocks, from the top of the drawing including one local word line to be selected and Z decoder 18 outputting a signal indicating an n-numbered block from the left of the drawing including the one local word line to be selected and an n-numbered sub-block from the top including the local word line.
FIG. 31 is a table showing how external address signals are divisionally supplied to row decoder 6 and Z decoder 18 of FIG. 30 in a case of a memory cell array including memory cells arranged in a matrix of 512 rows and 2048 columns. With reference to FIGS. 31 and 30, out of the external address signals indicative of a column direction address of a memory cell to be selected, 5-bit signals Z0-Z4 indicative of block addresses are input to Z decoder 18 and 6-bit signals Y0-Y5 indicative of column addresses in a block are input to a column decoder (not shown in FIG. 30). Out of the external address signals indicative of a row direction address of a memory cell to be selected, more significant 7-bit signals X2-X8 are input to row decoder 6 and less significant 2-bit signals X0 and X1 are input to Z decoder 18.
In such a case, row decoder 6 decodes the 7-bit signals X2-X8 to output 2.sup.7 -bit (=128) signals X0-X127 one of which signals being at a high level. As a result, only one of the 128 main word lines MWL is activated. Z decoder 18 decodes a total of 7-bit signals including 5-bit block address signals Z0-Z4 and two-bit row address signals X0 and X1 to output 2-bit (=32.times.4) X decoder signals ZX0-ZX127 only one of which signals being at a high level.
In case of a memory cell array including 512 memory cell rows, each of the sub-blocks SBL0-SBL127 includes four local word lines. Therefore, output of the above-described 128-bit signals ZX0-ZX127 by Z decoder 18 activates one of four signal lines ZL included in one of the 32 signal line groups ZLG provided corresponding to 32 blocks BL0-BL31.
The column decoder decodes the 6-bit signals Y0-Y6 to output 2.sup.6 -bit (=64) signals one of which signals is at a high level. In case of a memory cell array including 2048 memory cell columns, each of the blocks BL0-BL31 includes 64 bit line pairs and therefore, each of the 64-bit signals selects one bit line pair in each of the blocks BL0-BL31.
FIG. 32 is a logical circuit diagram showing an example of an actual arrangement of a local decoder. An arrangement of a conventional local decoder will be described with reference to FIG. 32.
In the following description, in n blocks BL0-BL (n-1) obtained by dividing the memory cell array in a row direction, local word lines included in even-numbered blocks and local word lines included in odd-numbered blocks are represented as LWL (2j) and LWL (2j+1), respectively (j=0, 1, . . . , (n-2)/2). Similarly, local decoders provided corresponding to the odd-numbered blocks and local decoders provided corresponding to the even-numbered blocks are represented as LD (2j) and LD (2j+1), respectively.
FIG. 32 shows, as a representative, two local decoders LD (2j) and LD (2j+1) arranged adjacent to each other in actual layout.
Each of the conventional local decoders LD (2j) and LD (2j+1) includes, for example, a two-input NAND gate 800 receiving a signal on the corresponding main word line MWL and a signal on the corresponding Z decoder signal line ZL and an inverter 810 for inverting the output of NAND gate 800. The output signal from inverter 810 is supplied to the corresponding local word line LWL (2j) or LWL (2j+1).
Operation of the local decoders shown in FIG. 32 will be described with reference to FIG. 33. FIG. 33 is a table of truth values of the logical circuit shown in FIG. 32.
As can be seen from FIG. 33, in each of the local decoders LD (2j) and LD (2j+1), the output potential (that is, the potentials on the corresponding local word lines LWL (2j) and LWL (2j+1)) of inverter 810 attains a high level in response to NAND gate 800 attaining a low level output potential only when both of the potentials on the corresponding main word line MWL and the corresponding Z decoder signal line ZL are at a high level. However, when at least one of the potentials on the corresponding main word line MWL and the corresponding Z decoder signal line ZL is at a low level, the output potential of NAND gate 800 is fixed to a high level, whereby the output potential of inverter 810 is at a low level. Therefore, the corresponding local word lines LWL (2j) and LWL (2j+1) are not activated unless both of the potentials on the corresponding main word line MWL and Z decoder signal line ZL attain a high level.
FIG. 34 is a circuit diagram showing a specific circuit arrangement of NAND gate 800 and inverter 810 of FIG. 32 relative to a single local decoder. Now, an arrangement of a conventional local decoder will be described in more detail with reference to FIG. 34.
In each local decoder, NAND gate 800 includes a P channel MOS transistor 800a and N channel MOS transistors 800b and 800c connected in series to each other between power supply Vcc and ground GND and a P channel MOS transistor 800d provided between power supply Vcc and a node between transistors 800a and 800b. The gates of transistors 800a and 800b are connected to the Z decoder signal line ZL and the gates of transistors 800c and 800d are connected to the main word line MWL. Inverter 810 includes a P channel MOS transistor 810a and an N channel MOS transistor 810b connected in series to each other between power supply Vcc and ground GND. The node between transistors 810a and 810b is connected to the local word line LWL (2j) or LWL (2j+1).
The gates of transistors 810a and 810b are connected to the node between transistors 800a and 800b.
When the potential on the main word line MWL is at a low level, while transistor 800d is turned on, transistor 800c is turned off, so that the gate potential of transistors 810a and 810b attains a high level irrespective of ON/OFF states of transistors 800a and 800b. Therefore, when the potential on the main word line MWL is at a low level, the local word line LWL (2j) or LWL (2j+1) connected to inverter 810 attains a low level, that is, it is activated irrespective of the potential level of the signal line ZL.
Conversely, when the potential on the main word line MWL is at a high level, transistor 800c is turned on, while transistor 800d is turned off, whereby the gate potential of transistors 810a and 810b is changed according to ON/OFF states of transistors 800a and 800b. That is, when transistor 800a is rendered conductive in response to a low level potential on the signal line ZL, the gate potential of transistors 810a and 810b attains a high level. Conversely, when transistor 800b is rendered conductive in response to a high level potential on the signal line ZL, the gate potential of transistors 810a and 810b attains a low level. Therefore, in case of the main word line MWL attaining a high level potential, the potential on the local word line LWL (2j) or LWL (2j+1) connected to inverter 810 attains a high level, that is, it is activated only when the potential on the Z decoder signal line ZL is at a high level.
In FIG. 34, a numeral in parenthesis put beside each element represents a gate width of the element in .mu.m.
As described above, each local decoder for use in a semiconductor memory device of a divided-word line structure is arranged as shown in FIG. 34 in order to obtain the logical product of a signal on the corresponding main word line and a signal on the corresponding Z decoder signal line. More specifically, each local decoder requires a total of 6 elements including two transistors constituting an inverter and four transistors constituting an NAND gate.
As can be seen from FIG. 28 and FIG. 30, the semiconductor memory device of a divided-word line structure requires the same number of local decoders as that of local word lines. For example, in a case where each of the sub-blocks SBL0-SBL127 includes four local word lines in FIG. 30, 2.sup.14 (=4 lines.times.128 sub-blocks.times.32 blocks) local decoders are required to make the total area of the local decoders equivalent to the total area of as many as 6.times.2.sup.14 MOS transistors.
As described in the foregoing, local decoders occupying a large area of a semiconductor memory device of a divided-word line structure make it difficult to reduce a chip area of a semiconductor memory device and to increase a memory capacity of the same.
In other words, in order to increase a storage capacity of a semiconductor memory device without increasing a chip area, more area of a semiconductor substrate available for use for a memory cell array is required by reducing an area occupied by other circuits than the memory cell array, thereby increasing the number of memory cells arranged on one chip. However, it is difficult to reduce an area of such peripheral circuits because even a single local decoder includes six elements. This fact makes a local decoder of a conventional arrangement another factor preventing an increase of a capacity of a semiconductor memory device.
In addition, as shown in FIGS. 28 and 30, the Z decoder signal line is formed extending in a column direction of a memory cell array also on a semiconductor substrate. Therefore, in a memory cell array divided both in a row direction and a column direction as shown in FIG. 30, a large number of Z decoder signal lines are arranged in a column direction between the respective odd-numbered blocks BL1, BL3, . . . BL31 and the even-numbered blocks BL0, BL2, . . . BL30 disposed adjacent thereto. For example, in FIG. 32, wherein each of the sub-blocks SBL0-SBL127 includes four local word lines, a total of 8 Z decoder signal lines are arranged in a column direction between an even-numbered block and an odd-numbered block adjacent to each other. As a result, the total of a row direction width of wiring layers forming the Z decoder signal lines reaches a high sum, resulting in an increase in the total width of the local decoders and the Z decoder signal lines provided corresponding thereto on the semiconductor substrate. Thus, a conventional semiconductor memory device of a divided-word line structure has an increased row direction width of other circuits than a memory cell array.
As described above, conventional semiconductor memory device of a divided-word line structure involves difficulty in increasing a capacity of a semiconductor memory device and reducing a chip area because of not only the number of elements of each local decoder but also the number of Z decoder signal lines.

Semiconductor memory device of divided word line


A protective glove for protecting the hand of a wearer from injury from blows impacting the hand. The protective glove includes a glove having front and back faces, a plurality of digit stalls, a palm region and a wrist opening. Each of the digit stalls has a fingertip shield adjacent the tip of the respective digit stall. The glove has a knuckle shield on the back face of the glove in a knuckle area of the palm region of the glove.

1. Field of the Invention
The present invention relates to protective gloves and more particularly pertains to a new protective glove for protecting the hand of a wearer from injury from blows impacting the hand.
2. Description of the Prior Art
The use of protective gloves is known in the prior art. More specifically, protective gloves heretofore devised and utilized are known to consist basically of familiar, expected and obvious structural configurations, notwithstanding the myriad of designs encompassed by the crowded prior art which have been developed for the fulfillment of countless objectives and requirements.
Known prior art includes U.S. Pat. No. 3,916,448; U.S. Pat. No. 4,094,014; U.S. Pat. No. 5,070,540; U.S. Pat. No. 3,636,568; U.S. Pat. No. 2,217,377; and U.S. Pat. No. Des. 275,909.
While these devices fulfill their respective, particular objectives and requirements, the aforementioned patents do not disclose a new protective glove. The inventive device includes a glove having front and back faces, a plurality of digit stalls, a palm region and a wrist opening. Each of the digit stalls has a fingertip shield adjacent the tip of the respective digit stall. The glove has a knuckle shield on the back face of the glove in a knuckle area of the palm region of the glove.
In these respects, the protective glove according to the present invention substantially departs from the conventional concepts and designs of the prior art, and in so doing provides an apparatus primarily developed for the purpose of protecting the hand of a wearer from injury from blows impacting the hand.


A processor module has a cache of SRAM chips mounted on both a back and a front surface but de-coupling capacitors mounted on only the back surface. Each de-coupling capacitor is for suppressing current spikes from a pair of SRAM chips. The pair of SRAM chips includes a first SRAM chip on the same surface as the capacitor and a second SRAM chip opposite the first SRAM chip on the front surface of the module. The first SRAM chip belongs to a first bank while the second SRAM chip belongs to a second bank. Two chip-enable signals control access to the two banks. Since only one bank is accessed at any time, and access causes current spikes, only one bank and only one SRAM chip in the pair of SRAM chips creates a current spike at any time. Thus, a capacitor can be shared between the two SRAM chips in the pair. The shared capacitor can be mounted next to or under one of the SRAM chips, or formed within the multi-layer substrate itself. Having capacitors on only one of the surfaces reduces the number of placement sequences required, reducing manufacturing cost. The capacitors are mounted on the opposite surface from the large processor for efficiency.

1. Field of the Invention
This invention relates to processor and memory modules, and more particularly for modules and production methods to reduce the cost of CPU/SRAM modules.
2. Description of the Related Art
Memory modules containing dynamic random-access memories (DRAM's) are shipped with most personal computers (PC's) today, allowing for later expansion with additional modules. Occasionally the central processing unit (CPU) or microprocessor is mounted on a small daughter or processor card or module that is inserted into a socket in the PC's motherboard. Using processor modules allow the CPU to be upgraded by replacing the processor card.
These processor modules often include a small cache memory, such as a first or second-level cache. A cache memory reduces memory latency by providing a small storage area for the most-recently-used data and instructions. Locality of instructions and data predicts that the most-recently-used data and instructions are likely to be used again. Since the cache memory is faster than the main DRAM memory, data in the cache is fetched more rapidly than data in the main DRAM memory.
Static RAM chips are used for cache memories. The access delay for SRAM chips is significantly smaller than for DRAM chips, as SRAM chip access delays are currently under 10 nanoseconds, while DRAM access delays are 50 or 60 nanoseconds. SRAM chips are simpler to interface, as they do not require refreshing, as do DRAM chips.
Like memory modules, processor modules are made in many different sizes and capacities, with different numbers of interface pins. The "pins" were originally pins extending from the module's edge, but now most modules are leadless, having metal contact pads or leads. The modules are small in size, being about 3 to 5 inches long and one or two inches high. The modules contain a small printed-circuit board substrate, typically a multi-layer board with alternating laminated layers of fiberglass insulation and foil or metal interconnect layers. Surface mounted components are soldered onto one or both surfaces of the substrate. Static-RAM integrated circuits (IC's) or chips are commonly packaged in inexpensive surface-mount packages such as small-outline J-leaded (SOJ) packages, PLCC's, or small-outline (SO) packages.
The SRAM chips draw significant amounts of current when address signals change and when OE (output enable) is asserted during accessing of the memory. Asserting OE or other control signals, and changing address inputs cause current spikes, which could upset the power and ground potentials on the processor module. Thus, capacitors are often mounted on the substrate near each SRAM chip. The capacitors are connected between power and ground as close as possible to the power and ground pins of each SRAM package. For wide SRAM chips with multiple power and ground pins, several capacitors may be used for each chip.

Processor module with dual-bank SRAM cache having shared capacitors and R-C elements integrated into the module substrate


Methods and apparatus are disclosed for identifying a variable number of items first in sequence from a variable starting position which may be particularly useful by packet or other scheduling mechanisms, such as, but not limited to the SLIP/I SLIP scheduling algorithms or variants thereof. Each of the groups of items is typically identified with a number of items the group desires to be selected. Based on an identified starting position, a progressive sum value is initialized, with progressive sum values corresponding to successive groups of items in the sequence being adjusted typically based on the corresponding number of items each successive group desires to be selected. The number of items a particular group is authorized to select can then be determined, such as, but not limited to, by being based on its corresponding progressive sum value, the progressive sum value of the immediately prior group in the sequence, and its desired number of items to be selected.

The communications industry is rapidly changing to adjust to emerging technologies and ever increasing customer demand. This customer demand for new applications and increased performance of existing applications is driving communications network and system providers to employ networks and systems having greater speed and capacity (e.g., greater bandwidth). In trying to achieve these goals, a common approach taken by many communications providers is to use packet switching technology. Increasingly, public and private communications networks are being built and expanded using various packet technologies, such as Internet Protocol (IP).
SLIP is an iterative algorithm for scheduling the sending of packets across an N×N switch. In one implementation, the following three steps are performed:                1. Each unmatched input sends a request to every output for which it has a queued cell.        2. If an unmatched output receives any requests, it chooses the one that appears next in a fixed, round-robin schedule starting from the highest selection priority element. The output notifies each input whether or not its request was granted. The pointer to the highest selection priority element of the round-robin schedule is incremented (modulo N) to one location beyond the granted input if and only if the grant is accepted in step 3 of the first iteration. The pointer is not incremented in subsequent iterations.        3. If an input receives a grant, it accepts the one that appears next in a fixed, round-robin schedule starting from the highest selection priority element. The pointer to the highest selection priority element of the round-robin schedule is incremented (modulo N) to one location beyond the accepted output.
I-SLIP is a scheduling algorithm including multiple iterations of the SLIP algorithm to determine the scheduling of packets for each round of sending packets (rather than just one SLIP iteration.)
Each output scheduler decides among the set of ordered, competing requests using a rotating selection priority. When a requesting input is granted and the input accepts that grant, the input will have the lowest selection priority at that output in the next cell time. Also, whatever input has the highest selection priority at an output will continue to be granted during each successive time slot until it is serviced. This ensures that a connection will not be starved: the highest selection priority connection at an output will always be accepted by an input in no more than N cell times.
Moving the pointers not only prevents starvation, it tends to desynchronize the schedulers. Each of the outputs that matched in the previous time slot will have a different highest selection priority input. Thus, they will each grant to different inputs. Consider an example in which two inputs are both requesting the same two outputs. Initially, both outputs may grant to the same input; in that case only one connection will be made in the first iteration.
The successful output will increment its pointer and in the next cell time, the outputs will no longer contend: one will have moved on to grant to another input and the other will grant to the same input as before. This leads to a better match in the first iteration of the next cell time. This is because the output schedulers have become desynchronized (or "slipped") with respect to each other. This leads to high performance, even for a single iteration of SLIP.
Because of the round-robin movement of the pointers, the algorithm tends to provide a fair allocation of bandwidth among competing connections and to be burst-reducing. The burst-reduction is simplest to understand under high load when all input queues are occupied: the algorithm will visit each competing connection in turn, so that even if a burst of cells for the same output arrives at the input, the burst will be spread out in time if there is competing traffic.
An example implementation is described in Nicholas W. McKeown, "Method and Apparatus for Scheduling Cells in an Input-Queued Switch, U.S. Pat. No. 5,500,858, issued Mar. 19, 1996, which is hereby incorporated by reference. Another example implementation is described in Nicholas W. McKeown, "Combined Unicast and Multicast Scheduling," U.S. Pat. No. 6,212,182, issued Apr. 3, 2001, which is hereby incorporated by reference.
The operation to find the first n elements from a starting position is a key component of many scheduling and other mechanisms. For example, the highest priority element (i.e., the starting position), beginning from which to select a next known number of elements, changes during the operation of a scheduling mechanism based on I-SLIP, and the number of elements to select remains the same or decreases for a subsequent I-SLIP iteration. These varying positions and values typically complicate the find first n operation. Moreover, the rate at which these next n elements are identified affects the performance of the scheduler, and therefore it is important to quickly and efficiently identify these next n elements. Needed are new methods and apparatus for finding a first n elements for a possibly varying value of n and possibly from a variable starting position.

Methods and apparatus for identifying a variable number of items first in sequence from a variable starting position which may be particularly useful by packet or other scheduling mechanisms


In a superconducting cable line in which a superconducting cable is connected to a terminal connecting part or an intermediate connecting part, an offset part in which a superconducting cable is laid in a curved-shape is provided near the terminal connecting part or the intermediate connecting part. Further, when it is assumed that the superconducting cable is movable in the offset part, an external tube of the superconducting cable is fixed such that a maximum amplitude part which maximizes the amount of movement of the superconducting cable following thermal expansion and contraction of a cable core becomes immovable.

Conventionally, there has been a known superconducting cable using a superconducting wire that can be in a superconducting state at cryogenic temperatures as a conductor. A superconducting cable is expected as a power cable capable of transmitting a large current with low loss, and has been developed for the practical use.
An example of a superconducting cable is illustrated in FIG. 2. A superconducting cable 10 illustrated in FIG. 2 is a single-core superconducting cable, in which a cable core 11 as the single core is housed in a thermal insulation tube 12.
The cable core 11 is composed of a former 111, superconductive conductor layers 112, an electric insulating layer 113, superconducting shield layers 114, a normal conducting shield layer 115, a protecting layer 116, and the like. The superconductive conductor layers 112 are formed by winding a plurality of superconducting wire materials spirally on the former 111. Similarly, the superconducting shield layers 114 are formed by winding a plurality of superconducting wire materials spirally on the electric insulating layer 113.
Each of superconducting wire materials for forming the superconductive conductor layers 112 and the superconducting shield layers 114 has a laminated structure obtained by forming an intermediate layer, a superconducting layer, a protecting layer in this order on a tape-shaped metal substrate, for example. As a superconductor for forming the superconducting layer may be a RE-based superconductor (RE: rare earth element) showing superconductivity at a liquid nitrogen temperature (−196° C. in the atmospheric pressure) or more, for example. An yttrium-based superconductor (Y-based superconductor, hereinafter) expressed as the chemical formula YBa2Cu3O7-y is especially typical.
The thermal insulation tube 12 has a double tube structure constituted of an internal tube 121 and an external tube 122. Between the internal tube 121 and the external tube 122, a multilayer thermal insulator (Super Insulation) 123 is interposed and vacuumed. In addition, the outer periphery of the external tube 122 is covered by a corrosion-resistant layer 124 of polyvinyl chloride (PVC), polyethylene, or the like.
During a steady operation of the superconducting cable 10, a cooling medium such as liquid nitrogen is circulated inside the internal tube 121, and thus transmitted electric current flows into the superconductive conductor layers 112 at a very low temperature.
At such a portion at which the superconducting cable 10 and a practical system such as a power device are connected, terminal processing is applied using a terminal connecting part. In the terminal connecting part, an end of the superconducting cable 10 is housed in a low temperature container which serves as a low temperature part, and is connected to the practical system which serves as a normal temperature part through a current lead.
Further, at such a portion at which the superconducting cables 10 are connected, terminal processing is applied using an intermediate connecting part. In the intermediate connecting part, two superconducting cables 10 are introduced in the low temperature container, and cable cores 11 are connected inside the low temperature container.
In the superconducting cable line having the terminal connecting part or intermediate connecting part above explained, the superconducting cable 10 is cooled from the normal temperature to a liquid nitrogen temperature or is heated from the liquid nitrogen temperature to the normal temperature upon assembly or maintenance. It is known that, under such a heat cycle, the cable core 11 thermally expands and contracts at about 0.3% of the length of the superconducting cable.
Particularly, in the terminal connecting part or the intermediate connecting part, when the cable core 11 has difficulty in moving in a longitudinal direction, and when the cable core 11 thermally expands and contracts, a local stress applies to the superconducting cable 10. Further, buckling occurs in superconducting wire materials forming the superconducting conductor layers 112 and the superconducting shield layers 114, and performance of the superconducting cable 10 significantly decreases.
Hence, a technique has been proposed which absorbs thermal expansion and contraction of a cable core by connecting superconducting conductor layers and current leads using connection terminals such as braided wires having flexibility (flexible connection terminals) in the terminal connecting part (see, for example, Patent Literature 1). Further, a technique has been proposed which absorbs thermal expansion and contraction of a cable core by providing an offset to a superconducting cable in a terminal connecting part or allowing the terminal connecting part to slide in the longitudinal direction of the superconducting cable.
Furthermore, a method has been proposed which provides offset parts on both sides of an intermediate connecting part and, when distortion is produced in a superconducting cable due to thermal expansion and contraction of a cable core, cancels distortion by moving the intermediate connecting part up or down (see, for example, Patent Literature 2). The offset part means a method of laying a cable in a meandering manner so as to absorb thermal expansion and contraction of the cable.


A trim assembly for interior walls of buildings has a cornerpiece configured for retention in a corner between intersecting walls, a trim strip extending from each opposite side of the cornerpiece, a tang extending from each opposite side of the cornerpiece and extending into slots in respective trim strips, a block member at each opposite side of the cornerpiece, at least one post extending from at least one of the block members and into a slot in a decorative member, and a clip device disposed about the post to retain it in the slot to retain the decorative member relative to the block member.

The present invention provides components and features which enable a non-expert person to install trim assemblies for interior walls in a building such as a house without requiring specialized skills and special equipment.
The present invention enables an unskilled person, such as a homeowner, to install trim assemblies between interior walls and ceilings.
The prior art ordinarily requires a person with certain expertise and utilizing specialized equipment to install such trim assemblies.
Preferred embodiments of the trim assemblies for interior walls and ceilings, include trim strips at opposite sides of a cornerpiece, and a tang extending from respective opposite sides of the cornerpiece into slots in respective trim strips. A block member is disposed at each of the opposite sides of a cornerpiece, and at least one post extends from one or more block members into respective slots in decorative members, and clips to retain the posts in slots to retain decorative members.
Tangs extend oppositely from respective sides of the cornerpiece and into slots in respective decorative strips. The clips are preferably of a T-shaped configuration and have outwardly extending portions to engage in slots to retain the posts.
One or more tangs extend from each block member and into the slots in the cornerpiece. Other tangs extend from each block member oppositely from said first tang members and into slots in respective trim strips at opposite sides of the cornerpiece.
Clip members are disposed at respective posts to retain the posts in respective slots to retain the decorative member.
The block members are preferably secured at an inter-section between a ceiling and walls by clip members on posts extending into slots in the wall.
In embodiments of generally rectilinear arrangements, as about a door or window, a plurality of corner members are disposed at intersections of elongate members.
Each corner member has at least one tang extending from two adjacent sides and into elongate members to attach them together, the elongate members having end portions thereon at least one post extending into a slot in a trim member with clip means to retain the trim member in the slots.