The present invention is a method and apparatus for compensating for position error inherent in a raster output scanning printing system by adjusting the intensity of image exposure to effect a correction in the output image. The invention is particularly well suited to compensate for position errors arising from a plurality of sources by first summing the errors and then applying a single compensating adjustment to the intensity of individual scan rasters based upon the position error thereof.

The present invention is directed to a method and apparatus capable of monitoring raster positioning errors (e.g., those produced by photoreceptor motion error, polygon wobble or optics vibration in a raster output scanning printing system) and altering the output signal in order to compensate for such error. Raster position errors as small as 0.5% give rise to visually objectionable banding in halftone output prints. Such errors typically arise in raster scan image output terminals (IOTs) due to polygon wobble and photoreceptor velocity non-uniformity. Although techniques have been proposed to eliminate such error, it is typically expensive to control or limit the error to an acceptable level; a level below which the error will not be detected by the unaided eye.
Heretofore, a number of patents and publications have disclosed techniques for compensating for position errors in image output terminals, the relevant portions of which may be briefly summarized as follows:
U.S. Pat. No. 4,073,566 to Noguchi et al., issued Feb. 14, 1978, discloses the use of a stationary hologram in the optical path of a beam scanning device in order to compensate for displacement of the beam resulting from errors in parallelism of the facets of a polygon mirror.
U.S. Pat. No. 4,707,122 to Lama et al., issued Nov. 17, 1987, discloses the use of an optical filter in the optical path of a reprographic machine to eliminate the effects of mechanical vibration that result in strobing (exposure modulation). The filter is tuned so as to have an incidence profile that is a function of the vibration frequencies.
U.S. Pat. No. 4,801,978 to Lama et al., issued Jan. 31, 1989, teaches an electronic printer employing an image write bar for exposing a photoconductive member. An encoder is used to monitor the vibration of the rotating photoconductive member, the signals generated by the encoder being employed to modify the on/off timing and/or the intensity of the image bar output.
U.S. Pat. No. 4,884,083 to Loce et al., issued Nov. 28, 1989, discloses a printing system employing a raster output scanning device that is compensated for the effects of motion of the medium that it is used to expose. The system disclosed is directed toward compensating for periodic exposure modulation in images transmitted by the raster output scanning device to the surface of a photoreceptor.
U.S. Pat. No. 4,332,461 to Cail et al., issued Jun. 1, 1982, teaches a servomotor system capable of monitoring and compensating for motion error in a continuously variable reduction copier. The copier employs a light-lens scanning carriage driven in relationship to the rotation of an image carrier.
As described by R. Loce, W. Lama, and M. Maltz in "Modeling Vibration-Induced Halftone Banding in a Xerographic Laser Printer," Journal of Electronic Imaging, Vol. 4 No. 1, p. 48-61, the relevant portions being hereby incorporated by reference, in a raster scanning printer, a laser beam is scanned across a photoreceptor in a direction perpendicular to the photoreceptor motion. When there is vibratory motion of the photoreceptor or wobble in the polygon mirror, the raster lines on the photoreceptor will not be evenly spaced. The authors analyze the positioning error and show that fractional raster spacing error is equal to photoreceptor fractional velocity error. The raster position errors result in various print defects, of which halftone banding is the dominant defect.
Polygon wobble in laser scanners is described in "Laser Beam Scanning-Opto-Mechanical Devices, Systems and Data Storage Optics," Marcel Dekker, Inc. (1985), p. 78. A possible correction technique for such wobble is described by L. Mailloux in "Exposure Compensation for Polygon Wobble Errors," Xerox Disclosure Journal, Vol. 14, No. 3, May/June 1989, where it is suggested that exposure control may be employed to reduce the resulting error.
Also, several authors have considered the effects of nonuniform photoreceptor motion and other sources of noise in digital printers, including Bestenreiner, Geis, Helmberger, and Stadler, "Visibility and Correction of Periodic Interference Structures in Line-by-Line Recorded Images," J. Appl. Phot. Engr. Vol. 2, p. 86-92 (1976); Takiguchi, Miyagi, Okamura, Ishoshi, and Shibata, "Effect of Photoreceptor Drum Rotational Speed Variation on Laser Beam Printer Halftone Reproduction," Proceedings of the SPSE Third International Congress: Recent Advances in Non-Impact Printing Technologies, p. 168-172, San Francisco (Aug. 1986). Haas "Contrast Modulation in Halftone Images Produced by Variation in Scan Line Spacing," J. Imaging Tech. Vol. 15, p. 46 (1989), examined the effects of periodic scan line position errors when printing periodic binary patterns (e.g., halftones). Bloomberg and Engeldrum, "Color Error due to Pixel Placement Errors in a Dot Matrix Printer," Proceedings of the SPSE Third International Congress: Recent Advances in Non-impact Printing Technologies, p. 257-260 (Aug. 1986), analyze color error on a print that is caused by random pixel placement errors. Loce and Lama in "Halftone Banding due to Vibrations in a Xerographic Image Bar Printer," Journal of Imaging Technology, Vol. 16, No. 1, p. 6-11 (1990) and in "Halftone Banding Due to Vibrations in a Xerographic Image Bar Printer," SPSE 41st Annual Conference, Washington (1988), employ exposure and xerographic models to examine vibration induced halftone banding in image bar printers.
In "Color Errors Due to Pixel Placement Errors in a Dot Matrix Printer," Third International Congress on Advances in Non-impact Printing Technologies--Society of Photographic Scientists and Engineers, (Aug. 24, 1986), pp. 257-260, S. Bloomberg teaches the modeling of a dot matrix printer using a structured dot theory. The model was used to study the impact of pixel placement errors on color.
In accordance with the present invention, there is provided a raster output scanning printer, including: an exposure device suitable for emitting a light beam therefrom; a movable imaging member; a rotating, multifaceted polygon suitable for reflecting the light beam toward a photoresponsive surface of said imaging member; a controller for controlling the velocity of the photoresponsive surface about a nominal velocity; means for monitoring the velocity of the photoresponsive surface and determining the deviation thereof from the nominal velocity; means for determining the deviation of the position of the light beam from a nominal position on the photoresponsive surface; first compensation means, responsive to the velocity deviation of the photoresponsive surface, for producing a first motion compensation signal; second compensation means, responsive to the light beam position deviation, for producing a second motion compensation signal; a summing circuit for summing the first motion compensation signal and the second motion compensation signal to produce a cumulative error signal; and means for altering the exposure level produced by the light beam in response to the cumulative error signal to expose the imaging member in a manner so as to compensate for the motion error arising from the velocity and light beam deviations.
In accordance with another aspect of the present invention, there is provided a raster printer, including: a movable imaging member; an exposure device suitable for raster-wise exposing a surface of the imaging member and thereby creating a latent image thereon; a plurality of position deviation detection means, each generating a compensation signal representative of the deviation of an exposed raster from a nominal position on the surface of the imaging member; summation means, responsive to the compensation signals generated by said plurality of position deviation detection means, for producing a cumulative error signal; and means for altering the exposure level of said exposure device in response to the cumulative error signal to expose the surface of the imaging member in a manner so as to compensate for the cumulative error.
In accordance with yet another aspect of the present invention, there is provided a method for automatically compensating for raster position deviations in a raster printing system, including the steps of: predicting an intensity variation for a raster exposed on an imaging member where the intensity variation is caused by each of a plurality of sources of motion error within the raster printing system summing the intensity variations from each of the plurality of sources of motion error; and altering, in response to the summed intensity variation, the level at which each pixel of a subsequent raster is exposed on the imaging member to compensate for the motion error.
One aspect of the invention deals with a basic problem in the variance or deviation of raster placement on a photoconductive surface in order to print an output image. This aspect is further based on the discovery of an inexpensive technique that alleviates cumulative positional error arising from multiple sources (e.g., photoreceptor motion nonuniformity and polygon wobble). The technique alters the local exposure level of pixels within a raster based upon the error in positioning of the raster with respect to a nominal raster position. The local exposure level may be altered by either varying the intensity of a exposure device or by altering the exposure period with a constant intensity device (effectively varying intensity).
The technique described herein is advantageous because it is inexpensive compared to other approaches. In addition, it can be used to correct for positional errors no matter what the source, so long as the error can be characterized or monitored and the plural sources can be summed.

Method and apparatus for compensating for raster position errors in output scanners


The invention is directed to a grounding clip which can provide an electrical connection between a ground wire, a first panel and a second panel. The grounding clip has a wire terminating section for terminating a grounding wire thereto, a first panel receiving portion for terminating a first panel therein, and a second panel receiving portion for terminating a second panel therein.

Grounding clips are known generally and used widely, for example to fasten electrical conductors or wires to conductive appliance panels while providing an electrical contact therebetween. Known grounding clips comprise generally a U-shaped panel contact section, and a wire contact section disposed adjacent to a curved portion or bight of the panel contact section opposite an open end thereof. In other grounding clips, the wire contact section extends axially from the bight of the clip. It is known also to provide one or more barbs protruding from inner sides of the panel contact section to provide improved electrical contact with the panel.
Examples of known grounding clips include the grounding clip shown and described in U.S. Pat. No. 4,993,959 entitled "Grounding Clip". This grounding clip has a stamped and formed member having a U shaped section with opposed walls extending from a bight for engagement with a panel. Tines or serrations are struck inwardly from each wall to grip the panel. A wire contact section is offset from the U-shaped panel. A centrally disposed strain relief arm extends from the U-shaped section, and any force transmitted from the wire to the clip is in the form of a straight pull extending through the centrally disposed strain relief arm.
U.S. Pat. No. 6,106,310 discloses a panel-grounding contact which includes a wire-connecting section and a panel-connecting section which has a deep U-shaped channel between walls. The walls include opposed pairs of teeth which extend toward the channel bottom and which are staggered inwardly from the channel entrance. The points of the teeth are adapted to scrape away corrosion layers of a conductive panel during mounting of the grounding clip onto an edge thereof as well as to secure the contact on the panel. The wire-connecting section extends orthogonally with respect to the panel edge after mounting of the clip onto the panel.
U.S. Pat. No. 6,276,947 discloses a grounding clip having a generally U-shape spring clamp which has first and second opposing walls which extend from a curved base portion thereof. The first and second walls each having a leading edge portion opposite the curved base portion. The spring clamp is fastened to a panel with the curved base portion disposed over the panel edge, the first wall of the spring clamp adjacent one side of the panel and the second wall thereof adjacent the other side of the panel. A wire fastening member, preferably the crimping type, extends from first wall of the spring clamp between the curved base portion of the spring clamp and the leading edge portion thereof. When the spring clamp is fastened to the panel, the wire fastening member and wire fastened thereto are adjacent the corresponding side of the panel and spaced apart from the panel edge, whereby only the curved base portion of the grounding clip protrudes beyond the panel edge.
Other grounding clips are shown in Tyco Electronics Application Specification 114-13095 (2006 Mar. 7 Rev B) entitled "Grounding Clip Terminals with 'F.' Crimp Features". Although all the prior art grounding clips recited above fasten electrical conductors or wires to conductive panels while providing an electrical contact therebetween, their use is limited to instances in which one or more wires are ground to one panel. In instances in which a wire is to be electrically ground to more than one panel (i.e. ballast can and ballast lid), another grounding clip must be used. It is, therefore, desired to provide a one piece ground clip which is capable of grounding the conductor(s) to more than one conductive panel.


An image signal processing apparatus is disclosed. A peaking signal generation section extracts and amplifies high frequency components contained in an input image signal to generate a peaking signal. An operation section allows a target area for which contour correction is to be performed using the peaking signal to be accepted. A control section generates an area gate signal describing position information corresponding to the designated target area. A mask processing section performs a mask process of outputting an image signal to which the peaking signal has been added to the target area designated through the operation section based on the area gate signal supplied from the control section. A scaling processing section converts pixels of the image signal for which the mask process has been performed is converted at a predetermined scaling ratio.

1. Field of the Invention
The present invention relates to an image signal processing apparatus, an image capturing apparatus, and an image signal processing method, and more particularly to an image signal processing technique that performs peaking that emphasizes an edge portion or the like of an image displayed for easy focus adjustment.
2. Description of the Related Art
In a video camera used for a broadcasting station and a camera-built-in type video tape recorder of related art, to easily perform focus adjustment, a captured image whose high frequency components are emphasized and whose contour is clarified is displayed on a viewfinder. At this point, the captured image displayed on the viewfinder is composed by adding an image signal obtained by an image capturing apparatus such as a video camera and a peaking signal.
The peaking signal is a signal generated by extracting high frequency components from a luminance signal that composes an image signal and amplifying the extracted high frequency components. By adding the peaking signal generated in such a manner to the image signal and outputting the resultant signal to the viewfinder, the captured image is displayed on the viewfinder such that the contour portion or the like of the image is emphasized. When the photographer (also called the user) watches such an image on the screen, he or she can easily perform focus adjustment.
FIG. 1 is a block diagram showing an example of a structure of an image capturing apparatus 200 of related art, the image capturing apparatus 200 displaying a captured image whose high frequency components are emphasized. The image capturing apparatus 200 shown in FIG. 1 includes a camera section 150 and a viewfinder section 160. First, the structure of the camera section 150 will be described. The camera section 150 includes as an optical system an image-capturing lens 101, a lens barrel 102, and a prism 103. Image sensors 104B, 104G, and 104R capture an image. The image capturing apparatus 200 is structured such that image signals captured by the image sensors 104B, 104G, and 104R are processed by a video amplifier 105, an analog-to-digital conversion section 106 (hereinafter referred to as the A/D conversion section 106), a digital signal processing section 107, and a digital-to-analog conversion section (hereinafter referred to as the D/A conversion section 108).
The image-capturing lens 101 focuses an optical image of an object on respective photosensitive planes (not shown) of the image sensors 104B, 104G, and 104R and has a focus adjustment function. The lens barrel 102 is a barrel that holds the image-capturing lens 101. The prism 103 separates light entered through the image-capturing lens 101 into rays of light of three primary colors R (red), G (green), and B (blue).
The image sensors 104B, 104G, and 104R photoelectrically convert light of rays of individual colors separated by the prism 103 into image signals AB, AG, and AR and output the obtained image signals AB, AG, and AR to the video amplifier 105. The video amplifier 105 amplifies the image signals AB, AG, and AR that are output from the image sensors 104B, 104G, and 104R and outputs amplified image signals AB′, AG′, and AR′ to the A/D conversion section 106. The A/D conversion section 106 converts the image signals AB′, AG′, and AR′ that are output from the video amplifier 105 into digital image signals DB, DG, and DR, respectively.
The digital signal processing section 107 performs a digital signal process including a matrix process for the image signals DR, DG, and DB, generates a luminance signal DY and color difference signals DU and DV, and outputs the generated individual signals to the D/A conversion section 108. The D/A conversion section 108 converts the digital luminance signal DY that is output from the digital signal processing section 107 into an analog luminance signal AY and the digital color difference signals DU and DV that are output from the digital signal processing section 107 into analog color difference signals AU and AY and then outputs the generated luminance signal AY and color difference signals DU and DV to the viewfinder section 160.
The viewfinder section 160 includes a video amplifier 109, a band limit filter 110, an A/D conversion section 111, a peaking signal generation section 112, a multiplying device 113, an adding device 114, a scaling processing section 115, a matrix processing section 116, a display device drive section 117, and a display device 118.
The video amplifier 109 amplifies the luminance signal AY and the color difference signals AU and AV that are output from the D/A conversion section 108 of the camera section 150 and supplies amplified luminance signals AY′ and color difference signals AU′ and AV′ to the band limit filter 110. The band limit filter 110 is composed of a low-pass filter or a band-pass filter, limits frequency bands of the luminance signal AY′ and color difference signals AU′ and AV′ and outputs band-limited luminance signal AY″ and color difference signals AU″ and AV″ to the A/D conversion section 111.
The A/D conversion section 111 converts the luminance signal AY″ and the color difference signals AU″ and AV″ that are output from the band limit filter 110 into a digital luminance signal DY and digital color difference signals DU and DV, and outputs the luminance signal DY to the peaking signal generation section 112 and the adding device 114 and the color difference signals DU and DV to the scaling processing section 115.
The peaking signal generation section 112 extracts high frequency components from the luminance signal that is output from the A/D conversion section 111 and generates a peaking signal based on the high frequency components. Thereafter, the peaking signal generation section 112 outputs the generated peaking signal to the multiplying device 113. The multiplying device 113 multiplies a peaking level setting signal supplied from a control section (not shown) by a peaking signal that is output from the peaking signal generation section 112 and outputs a resultant peaking signal PEAK to the adding device 114.
The peaking level setting signal is a signal that sets the peaking level (intensity). The peaking level can be set by the user (photographer) through an operation section or the like (not shown). Thus, the peaking signal PEAK that is generated by multiplying the peaking setting signal and the peaking signal and that is output from the multiplying device 113 becomes a peaking signal whose level has been adjusted to a predetermined value.
The adding device 114 adds the luminance signal DY that is output from the A/D conversion section 111 and the peaking signal PEAK that is output from the multiplying device 113 and outputs a resultant luminance signal DYpk to the scaling processing section 115. The scaling processing section 115 performs pixel conversion that converts the number of pixels based on the number of pixels of the display device 118 and interlace-to-progressive (i/p) conversion to the luminance signal DYpk that is output from the adding device 114 and the color difference signals DU and DV that are output from the A/D conversion section 111. The scaling processing section 115 outputs resultant luminance signal DYpk′ and color difference signals DU′ and DV′ to the matrix processing section 116.
The matrix processing section 116 converts the luminance signal DYpk′ and the color difference signals DU′ and DV′ into RGB image signals, generates resultant image signals DRpk, DGpk, and DBpk, and outputs the individually generated image signals to the display device drive section 117. The display device drive section 117 generates a drive signal that drives the display device 118 and supplies the drive signal to the display device 118. The display device 118 is composed of a liquid crystal display (LCD) or the like and displays an image based on the drive signal supplied from the display device drive section 117.
The image signals DRpk, DGpk, and DBpk that compose an image displayed on the display device 118 are image signals to which the peaking signal generated in the peaking signal generation section 112 has been added. Thus, an image whose contour portion or the like is emphasized is displayed on the display device 118.
For example, Japanese Unexamined Patent Application Publication No. HEI 09-139952, referred to as Patent Document 1, describes a technique that emphasizes a contour portion of a captured image displayed on a viewfinder that uses a color liquid crystal display device.

Image signal processing apparatus, image capturing apparatus, and image signal processing method


A method and apparatus that provide for determining a multilayer switching path are disclosed. In one embodiment of the invention, a Layer 3 path and a Layer 2 path between a source device and destination device are first determined in order to identify the relevant switch engines that perform the multilayer switching. Determining whether the switch engines satisfy a set of criteria identifies the relevant switch engines.

A computer network generally includes a number of devices, including switches, routers and hubs, connected so as to allow communication among the devices. The devices within a network are often categorized into two classes: end stations such as workstations, desktop PCs, printers, servers, hosts, fax machines, and devices that primarily supply or consume information; and network devices such as gateways, switches and routers that primarily forward information between the other devices.
Network devices ordinarily operate on a continuous basis. Each device has one or more circuit boards, a microprocessor and a memory, and runs a control program. In general, networks often include several different types of data switching and routing devices. These network devices may have different physical characteristics. New devices, with characteristics that are presently unknown, are constantly being developed. In addition, the characteristics of many network devices may change over time. For example, characteristics of the network devices change when subsystems like boards, network interface modules, and other parts are added or removed from a device.
Many networks are managed, supervised and maintained by a network administrator. Typically, the network administrator employs a variety of software and hardware tools to monitor and maintain a network. The Open Systems Interconnection ("OSI") reference model is useful in classifying communications between network devices. The OSI reference model divides the tasks of moving information between the network devices into groups of manageable tasks. Each group of tasks is assigned to one of seven layers of the OSI reference model. The upper layers of the OSI reference model relate more to the end user. For example, the highest layer (Layer 7), also referred to as the OSI Application Layer, is the closest to the end-user in that both the OSI Application Layer and the end-user interact directly with software applications that implement a communication component. The lower layers of the OSI reference model relate to data transport. For example, the OSI Physical Layer, also referred to as Layer 1, defines the electrical, mechanical, procedural, and functional specifications for the physical link between communicating network systems.
The OSI Data Link Layer, also referred to as Layer 2, defines network and protocol characteristics, including physical addressing, network topology, sequencing of frames, and flow control. Layer 2 further comprises a Logical Link Control ("LLC") sublayer and a Media Access Control ("MAC") sublayer. The LLC sublayer manages communications between devices over a single link of a network. The MAC sublayer manages protocol access to the physical network medium. Data communications devices that operate principally at the Layer 2 level are referred to as data link layer devices. Bridges and switches are examples of data link layer devices. Bridges connect and enable packet forwarding between networks. Today, switches and switching technology dominate in applications in which bridging technologies were implemented in prior network designs. Switches have superior throughput performance, higher port density, lower per-port cost and greater flexibility. Thus, switches have emerged as the replacement technology for bridges. Also, switches, because of their superiority, are viewed as complements to routing technology as further explained herein.
The OSI Network Layer, also referred to as a Layer 3, provides routing and related functions that enable data to move across an internetwork from a source device to a destination device. For example, Layer 3 may manage the routing of a packet of data from one Virtual Local Area Network (VLAN) to another. Routing involves two basic activities: 1) determining optimal routing paths, 2) transporting packets through an internetwork, hereinafter referred to as "switching." To determine optimal routing paths, routing algorithms are used to initialize and maintain routing tables, which contain route information. Examples of route information include destination and "next hop" information that tell a route processor that a particular destination can be reached optimally by sending a packet to a particular router representing the "next hop" on the way to the final destination. When a route processor receives an incoming packet, the router checks the destination address and attempts to associate the destination address with a next hop. The path traversed by a packet at Layer 3 is referred to herein as "Layer 3 path." The path determination at Layer 3 is referred to herein as "Layer 3 path tracing."
Although path determination at Layer 3 identifies a path from route processor to route processor, it does not identify the actual network devices, such as LAN switches and bridges, which a packet may traverse to go from a source device to a destination device. The path between any two Layer 3 devices may traverse entire networks of devices that operate at Layer 2. The path traversed by a packet at Layer 2 is referred to herein as "Layer 2 path." The path determination at Layer 2 is referred to herein as "Layer 2 path tracing."
Thus, an effective network management system would include both Layer 3 path tracing and Layer 2 path tracing. However, knowledge of the Layer 3 and Layer 2 paths may not provide certain path information, such as shortcuts in the Layer 3 and Layer 2 paths, whereby a packet may bypass certain devices at Layer 3 and Layer 2 as the packet moves to the destination device. For example, in the interest of efficiency, switches may be configured to perform some of the functions that a route processor would have performed, and therefore the router is bypassed.
The process of transporting packets by bypassing certain Layer 3 and Layer 2 devices through which the packets would have otherwise traversed is referred to herein as "multilayer switching." Multilayer switching may be desirable to reduce the work to be performed by route processors and to reduce latency. Switches are significantly faster because they switch in hardware, while route processors route in software, and therefore use of switches may result in reduced packet latency. Details of multilayer switching are further explained herein. A path tracing that takes into account multilayer switching is herein referred to as "multilayer switching path tracing."
In addition, when switches and associated route processors are configured to perform multilayer switching, a mechanism is needed to determine whether particular switches and route processors have been configured correctly. Multilayer switching path tracing would provide a means of investigating network switch and route processor configurations for use in improved network management. It would also provide a more reliable way to create, manipulate and display a multilayer topology of network devices.
Based on the foregoing, there is a clear need for a mechanism that can identify the path from a source device to a destination device in a switched network at multiple network layers.
There is a specific need for a way to carry out path tracing for multilayer switching paths, for use in network management.

This patent is subject to a terminal disclaimer.

Method and apparatus for determining a multilayer switching path


A method for making transmural lesions in one or more walls of the atria of the heart in open-heart surgery. The lesion blocks electrical impulses in a direction crosswise to the lesion. The method uses a probe having a handle (1), a closed electrode (2) at an end of the probe, a relatively rigid member (5) of physiologically acceptable plastic connecting the probe and the electrode, and means (6, 7) for coupling the probe to an RF power source.

All kinds of heart arrhythmias, and in particular chronic and paroxysmal atrial fibrillation, can currently be treated by surgery.
A known surgical procedure (MAZE) was designed to eliminate atrial fibrillation permanently. In this procedure incisions are made with a scalpel in the walls of the atria, in order to block electrical impulse conduction in a direction crosswise to the incisions, by the interruption of the tissue continuity. As a result of the subsequent scarring, these electrical blocks acquire a permanent character.
This known technique is as yet performed only to a limited extent worldwide, owing to the complexity of the operation. The increased risk is particularly associated with the duration of the operation and the way in which the operation has to be carried out.
The duration of the operation, and in particular the cross-clamp time (x-clamp) is so long that there is a great risk of damage to the heart muscle.
The cross-clamp time required for the MAZE procedure alone is currently still an average of 68 min. (range 50–102 min.), and the necessary time on the heart-lung machine is on average 182 min. (range 130–256 min.). For further data you are referred to Atrial Fibrillations: Mechanisms and Therapeutic Strategies, Futura Publishing Co. Inc. Armonk, N.Y. 1994. J. L. Cox: Surgical Interruption of Atrial Reentry as a Cure for Atrial Fibrillation. The way in which the operation is performed with the scalpel produces an increased risk of vascular suture leaks and subsequent bleeding, due to the large number and location of the vascular sutures involved.

Method for interrupting conduction paths within the heart


Creating virtual extender plugins using MGTs (Multi-Gigabit Transceivers). A virtual extender plugin allows a user seamlessly to bridge between various FPGAs (Filed Programmable Logic Arrays) when designing and implementing electronic devices. These bridges, provided by these virtual extender plugins, allow for efficient use of various untapped resources within a device. For example, a given FPGA may employ virtual extender plugin(s) to access and use various untapped (or relatively lightly tapped) functionality of other FPGAs. These virtual extender plugins may be implemented according to a relatively wide variety of applications allowing the tapping of unused resources such as memory, microprocessor peripherals, LUTs (Look Up Tables), IOs (Input/Output devices and/or ports), memory, and embedded microprocessor blocks. Practically speaking, these virtual extender plugins actually “plug in” to a standard or user-defined bus stream having a standardized/known type of serialized format such that every type of virtual extender plugin uses that same serialized format.

1. Technical Field of the Invention
The invention relates generally to electronic devices; and, more particularly, it relates to interfacing of FPGAs (Filed Programmable Logic Arrays) within various electronic devices.
2. Description of Related Art
As is known in the art of designing and building various electronic devices, one of the difficult tasks presented is the efficient allocation of resources for use by any one or more functional blocks within a device. When even considering the various basic functionality of a microprocessor within a device, there seems always to be the various design challenges to ensure sufficient (yet efficient) amount of memory (including both on-chip and off-chip in some instances), sufficient peripheral support, sufficient amount of IOs (Input/Output devices and/or ports), and so on. Once a designer decides on a particular implementation and the amounts of such processing and support allocation (e.g., amounts of memory, peripheral support, IOs, and so on), there is typically great inflexibility in changing those allocations for a particular device. Certainly, knowledge (either good or bad) may be acquired for a particular device, and that knowledge may be used to allow for a more efficient allocation of resources in a next-generation device. However, this does not help the present device to perform any more efficiently in terms of the allocation and usage of resources.
Within more complex devices that include a wider variety of functional blocks, some of these functional blocks may actually include an appropriate amount of support resources. However, as is oftentimes the case, a functional block includes too little support resources (e.g., memory, processing functionality, IOs, etc.) or there are many support resources that go unused. For example, one functional block in a device may be using all (e.g., to capacity) of the support resources provided there to. Another functional block in the same device may have a large amount of support resources available that are simply sitting idly and performing no functions whatsoever; or else, these support resources may be used on a relatively infrequent basis.
The static and one-time design of such prior art devices shows their inflexibility to accommodate changing needs or operating conditions in terms of their support resources. That is to say, once a design is made, the user simply needs to deal with the existent and dedicated support resources for the various functional blocks included within a device. While some support resources can be upgraded (e.g., memory), the vast majority of such support resources cannot be modified once the device is made (e.g., number of IOs of an integrated circuit). A common approach is simply to over-allocate support resources for various functional blocks to ensure that the capabilities of these support resources will not (ideally, never) be saturated. However, this often results in a high degree of waste, in that, such support resources are simply sitting idly and being unused. As such, it is clear there is a need in the art for some means by which greater flexibility may be provided to the various functional blocks within devices to accommodate changing needs and/or operating conditions of the device
FIG. 1 is a diagram illustrating a prior art embodiment of FPGAs (Field Programmable Gate Arrays) operating such that each FPGA has its own dedicated resources. A number of FPGAs (shown as FPGA 110, FPGA 120, and FPGA 130) are all interconnected via an FPGA interconnection 101. It is noted that the FPGA interconnection 101 is typically implemented using a number of parallel buses that interconnect each of the individual functional components of each of the FPGAs. This can be a very inefficient and cumbersome way in which to interface the various FPGAs.
Each of the FPGAs includes various types of functionality. For example, the FPGA 110 includes embedded processing functionality 112, block memory 114, and CLBs (Configurable Logic Blocks) 116. The embedded processing functionality 112 may be an actual integrated circuit that is operable to perform various digital signal processing functions, such as multiplication. The block memory 114, such as a block random access memory (BRAM), may be used by the embedded processing functionality 112. The CLBs 116 may be viewed as being reconfigurable circuitry that is able to support various logic functions such as OR gates, AND gates, NAND gates, XOR gates, among other types of logic functions. Generally speaking, the CLBs 116 may be viewed as being reconfigurable circuitry that is operable to be implemented to support and perform any of a wide variety of logic functional processing including various logic functions having various numbers of inputs and outputs. Each of the other FPGA 120 and FPGA 130 includes its corresponding dedicated support resources as well. For example, the FPGA 120 includes embedded processing functionality 122, block memory 124, and CLBs 126, and the FPGA 130 includes embedded processing functionality 132, block memory 134, and CLBs 136. A description of a conventional FPGA is found in the Virtex-II Pro Platform FPGA Handbook, October 2002, from Xilinx Inc. of San Jose, Calif.
Again, an mentioned above, each of the individual functional components of each of the FPGAs is interconnected via the FPGA interconnection 101 using various parallel buses included therein. For example, when the embedded processing functionality 112 is to be communicatively coupled to either the embedded processing functionality 122 or the embedded processing functionality 132, or vice versa, then a relatively large parallel bus is employed to perform this actual interfacing. Similarly, when the block memory 114 is to be communicatively coupled to either the block memory 124 or the block memory 134, or vice versa, then a relatively large parallel bus is employed to perform this actual interfacing. Lastly, as shown within this example embodiment, when the CLBs 116 are to be communicatively coupled to either the CLBs 126 or the CLBs 136, then a relatively large parallel bus is also employed to perform this actual interfacing. The number of parallel lines within each of the various types of parallel buses that are employed to communicatively couple each of the various types of individual functional components within each of the FPGAs may vary in size and number. Clearly, this is a prior art approach to interfacing the various individual functional components within each of the FPGAs can be very intensive and cumbersome.
The manner in which communication is performed along these various parallel buses can be unique for various types of FPGA applications. That is to say, different users may implement the interfacing in different manners. This variability in the manner by which the individual functional components within each of the FPGAs are interfaced only contributes to the lack of uniformity and commonality of the manner by which the various FPGAs operate within a larger application.
This multiple FPGA arrangement can suffer from many of the deficiencies described above, in that, each of the individual FPGAs sometimes does not have a sufficient amount of support resources available to perform the functionality it is intended to do. Block memory is one particular type of support resource that is typically consumed and capitalized upon very quickly. When the block memory of any FPGA is consumed, then a quick solution approach is simply to use the available CLBs on that particular FPGA. However, this is a very inefficient usage of the CLB functionality provided by an FPGA. The inflexibility of this prior art approach, in that, each FPGA is limited to the support resources that have been implemented therein can present difficulty in various designs. Moreover, even when designers seek to try to interface one FPGA to another, there does not exist in the art a common means or approach by which this can be done. There is an extremely large number of means by which this interfacing may be performed, and it can vary greatly from one implementation to another. Clearly, there is a need in the art to allow for a better means of interfacing FPGAs to one another and also a means that can address the design challenges and inflexibility of statically dedicated support resources within an FPGA.


A method and apparatus for real-time encoding and decoding of data on a computer system. The present invention is used preferably with a utility which causes data objects to be encoded and decoded. Such utilities include data compression utilities, data encryption utilities and security utilities. The general method involves the steps of opening an encoded data object; starting operation of an encoding/decoding means; encoding a decoded data object from a list of decoded data objects; removing the decoded data object from the list of decoded data objects; decoding the encoded data object; posting the encoded data object to the list of decoded data objects; terminating execution of the encoding/decoding utility; and invoking an application associated with said data object that was just decoded. Data objects may be comprised of sub-objects of a plurality of sub-objects. In such instances, the encoding and decoding occurs at the sub-object level.

1. Field Of the Invention
This invention relates to the field of computer operating environments, in particular the operation of operating system utilities for encoding and decoding data objects.
2. Prior Art
A computer requires an operating system in order to be functional. An operating system provides the logic, timing and protocols by which the various components of a computer system communicate. However, an operating system may not include all of the tools that a user may want to have in order to maintain their operating environment. Commonly, a user may utilize operating system utilities in order to provide desired functionality.
Operating system utilities generally operate in one of two modes; a mode requiring user intervention and a mode that is transparent to the user. Examples of utilities requiring user intervention are a storage media back-up program or data recovery utilities. Transparent utilities are performed without user intervention. They are automatically invoked in response to some event occurring, e.g. the starting of an application. Examples of transparent utilities include processor accelerators or memory managers.
Of course some utilities may operate in both modes. For example data compression utilities may be invoked by a user to compress a file; or may operate transparently where files are decompressed and compressed automatically when they are opened and closed.
Transparent utilities must have a means by which they recognize that they should be invoked. Using data compression as an example, whenever a user closes a file, i.e. indicates to the computer system that the file is no longer needed, that file is compressed in order to save storage on a storage medium such as a hard disk. The data compression utility will be invoked to initially compress and store the file. Next, when the file is to be re-used, the data compression utility will be invoked to decompress the file. Finally, when use of the file is complete, the data compression utility is invoked to re-compress the file (i.e., to compress the file again). Note that when the file is closed, the file may initially be stored as uncompressed and then recompressed. Several solutions will be discussed with respect to the data compression example.
It is first instructive to discuss the notion of foreground and background processing. Computer systems that support foreground and background processing are typically referred to as having multi-tasking capabilities. A task operating in the foreground is one in which the user is typically aware of. For example, a spreadsheet program being run by the user is in the foreground. Conversely, a task running in the background is one that is executing, while the user is performing some other task on the computer system (i.e. it is transparent to the user). An example of a background task is a print job.
A first solution to the problems of invoking the compression utility is to keep the compression utility always running in the background. Whenever a file is decompressed the compression utility is notified and the name of the file is added to the compression utility's list of open files. The compression utility periodically scans the list of decompressed files. When it detects that a decompressed file has been closed, it compresses the file.
There are several disadvantages to this approach. First the compression utility must always be running in the background. This degrades the overall performance of the computer system, and requires allocation of dedicated memory. Second, because the compression program is running in the background, background recompression of the file may interfere with the any foreground operation on the file. Finally, if the user is frequently switching back and forth between a compressed file and other files, the user may experience annoying time delays because of the repeated decompressions and recompressions of the file. These problems can cause unexpected delays and even corruption of the compressed file.
A second solution is to associate a file with the compression utility. In this manner, whenever the file is referenced, e.g. opened, the compression utility will be invoked. However, when the file is closed, there must be a means to notify the utility that a re-compression is required. Some known computer operating systems provide a means to do this, e.g. the MS/DOS.RTM. Operating System, available from the Microsoft Corporation of Redmond, Wash. Other known computer operating systems do not provide ready means, e.g. the PENPOINT.TM. Operating System, available from the Go Corporation of Foster City, Calif. MS/DOS and Microsoft are registered trademarks of Microsoft Corporation. PENPOINT is a trademark of Go Corporation.
A third way of integrating a compression utility into the operating system environment is to grant ownership of a resource to the compression utility. For example, a hard disk resource may be "owned" by the compression utility. Whenever that hard disk resource is accessed, the utility is automatically invoked. Unfortunately, this will typically require a high degree of integration of the utility into the operating system. Such integration may be difficult, if not impossible, for many operating system environments.
While various solutions exist, each has its drawbacks. Thus, it is a primary object of the present invention to provide a means by which a transparent utility may be integrated into an operating system environment that overcomes the foregoing drawbacks of the prior art.
It is also known that the utilities require their own temporary operating storage areas in order to perform their function. For example with respect to a data compression utility, temporary storage is required for the uncompressed data as well as the compressed data. If the temporary storage area is not available, the function of the utility cannot be performed. Moreover, if sometime during the execution of the utility, the required temporary storage is not available, the compression must be restarted. As various applications may be contending for the same pool of temporary storage, it is difficult to accurately estimate the storage that would be needed.
Thus, it is desirable to minimize the amount of temporary storage required to execute a utility.

Method and apparatus for encoding data objects on a computer system


A two dimensional laser diode array consists of rows and columns of individual multimode laser diodes, each diode having a separate collection lens. The array is imaged at a large reduction ratio to achieve high resolution recording. In order to decrease the apparent spacing of the diodes in the scanning direction, the rows are staggered relative to the scan direction. In order to avoid variations caused by the near-field non-uniformity of multimode diodes the final spot generated on the media is an image of the aperture of the collecting lens and not of the diode facet. The larger dimension of this aperture, formed by the diffraction limited direction of the laser diode, is reduced by using anamorphic optics.

Laser diodes are available as single mode or multimode diodes. Single mode laser diodes are effectively point sources, diffraction limited in their divergence in both axis. Multimode diodes typically have laser junctions in the form of short stripes, typically from 10 to 200 microns long. Multimode diodes are diffraction limited in the direction perpendicular to the junction but have non-diffraction limited divergence in the direction parallel to the laser junction. The emitting aperture of a multimode diode can be a single continuous stripe, a collection of short stripes or even a collection of single mode emitters electrically connected in parallel. All these difference constructions will be referred to as "multimode laser diodes". The diodes can be used in the visible part of the spectrum or in the IR. The term "light" is used here to cover all wavelengths.
Two dimensional laser diode arrays have been used for high resolution recording both in the optical data storage and laser plotting fields. These arrays make better use of the field-of-view of the lens than linear arrays. Two dimensional arrays are described in U.S. Pat. Nos. 4,743,091; 5,291,329 and 5,477,259.
All prior art requires a very large de-magnification ratios, typically over 100, to reduce the mechanical pitch of the array to an acceptable high resolution image. This high de-magnification ratio requires the distance between the final imaging lens and the collecting lenses to be typically over 100 times the focal length of the imaging lens. Such a large distance is acceptable for single mode laser diodes, as light from the point sources of single mode laser diodes can be collimated, but is too large for multimode lasers, as light from the spatially extended emitters of multimode laser diodes cannot be collimated and diverges, therefore missing the aperture of the final lens.
A second difficulty using multimode laser diodes is their non-uniform near field pattern. Even if the diodes are equally spaced mechanically, the equivalent emission point can move around by many microns as the near-field pattern changes with aging. This variation in the near-field pattern causes unacceptable banding in the image if the near field of the diodes is imaged onto the recording material. For these two reasons all prior art designs of two dimensional laser diode arrays used for recording had to use single mode diodes. Single mode diodes are more expensive than multimode diodes (for the same output power) and are limited in input power. Most prior art methods of using multimode diodes use multimode optical fibers to direct light from the laser diodes. Coupling to optical fibers causes a large brightness loss.

Two dimensional laser diode array using multimode lasers


A method of recovering crystal defects in an impurity doped diffusion silicon layer in contact with a C54 crystal phase titanium silicide layer includes the step of causing a cohesion reaction of the C54 crystal phase titanium silicide layer by heat treating the C54 crystal phase titanium silicide layer so as to cause a vacancy-diffusion of lattice-vacancy of silicon atoms from the C54 crystal phase titanium silicide layer into the impurity doped diffusion silicon layer including the crystal defects while maintaining the continuity of the C54 crystal phase titanium silicide layer.

The present invention relates to a method of forming a semiconductor device, and more particularly to a method of forming a semiconductor device having a titanium salicide shallow junction diffusion layer.
High integration of a semiconductor device has been made by scaling down semiconductor elements.
For scaling down of the semiconductor elements, it is important to shallow the junction depth of diffusion regions such as source/drain regions or emitter regions. Further, it is also important to reduce an effective sheet resistance as the depth of the diffusion layers is reduced. For those purposes, the titanium salicide diffusion layers have been on the use, wherein a titanium silicide layer having a C54 crystal structure is provided by use of self-alignment technique. Under 0.25 micrometers design rule, the junction depth of the diffusion layer is 0.15 micrometers. Such shallow junction diffusion layer may be formed by an ion-implantation of a conductive impurity. Notwithstanding, it is difficult to form a shallow junction diffusion layer having a junction depth of less than 0.15 micrometers by use of normal ion-implantation of a conductive impurity. Particularly, it was difficult to form a p.sup.+ -type diffusion layer. For example, it was difficult to form a shallow diffusion layer of a junction depth of approximately 0.08 micrometers required under 0.13 micrometers design rule. Also it is required by a normal ion-implantation to form an n.sup.+ -type shallow junction diffusion layer having a depth of approximately 0.05 micrometers required under 0.1 micrometer design rule.
The cause of difficulty in forming such extremely shallow diffusion layers by ion-implantation of the conductive impurity is in a channeling phenomenon in ion-implantation process. Theoretically, at a high dose of ions, silicon substrate surface is made amorphous so that the channeling phenomenon is prevented. Actually, however, the channeling phenomenon appears within an initial time period of the ion-implantation without the silicon substrate surface being made of amorphous.
A conventional method of forming a diffusion layer with avoiding such channeling phenomenon is disclosed in IEEE, Transaction-of-electron-devices, ED-38, pp. 476-486. In accordance with the conventional method, before the ion-implantation of conductive impurity is carried out, an ion-implantation of Ge has been carried out into a predetermined region of the diffusion layer of an n-type silicon substrate surface for forming an amorphous silicon. Subsequently, an ion-implantation of B or BF.sub.2 is carried out. Further, a rapid thermal anneal is carried out at a temperature of 1050.degree. C. to form a p.sup.+ -type shallow having approximately 0.1 micrometer. In the above conventional method, in place of Ge, Si may be ion-implanted.
It is possible to form the shallow junction diffusion layer by use of the above method. However, the channeling phenomenon is likely to be caused by the ion-implantation of Ge or Si for forming the amorphous silicon. Those diffusion layers increase in junction leakage probability as compared to the normal ion-implantation of conductive impurity. Such junction leakage is caused by residual crystal defects due to insufficient recovery of crystal structure from amorphous structure.
It is disclosed in 1987 Applied Physics Letter Vol. 51, No. 12, pp. 1182-1184, that an amorphous silicon layer is formed on a silicon substrate surface to form a diffusion layer over the amorphous silicon layer before a C49 structured crystal phase titanium silicide layer is formed by self-alignment over the diffusion layer. A heat treatment to the C49 structured crystal phase titanium silicide layer is then carried out to cause a phase transition from C49 to C54 thereby forming a C54 structured crystal phase titanium silicide layer. As a result, the crystal defects generated by the formation of amorphous layer are reduced. The junction leakage is reduced by the reduction of the crystal defects. It was measured that p.sup.+ -n junction is in the order of 1.times.10.sup.-8 A/mm.sup.2 or 10 nA/mm.sup.2. The actually required device more scaled down than 0.25 micrometers design rule is approximately 1.times.10.sup.-10 A/mm.sup.2 or 100 pA/mm.sup.2. It is therefore difficult to make a direct combination of the above described two techniques in order to form a titanium salicide shallow diffusion layer.
In the above circumstances, it had been required to develop a novel method of forming a titanium salicide shallow junction diffusion layer while keeping a reduced sheet resistance and avoiding any increase in p-n junction leakage.

Method of forming a semiconductor device having a titanium salicide shallow junction diffusion layer


A heating device for use in an induction heating type fixing system is composed of a sleeve 12 made of an electrical conductive material and an electromagnet 13 with a coil 20 and a core 18. It is constructed so as to fulfill the following formulas (1), (2), and (3). EQU S1+S2.gtoreq.0.3.times.S3 (1) EQU 0.2.ltoreq.S2/(S1+S2).ltoreq.0.8 (2) EQU 1 mm.ltoreq.Dmax.ltoreq.5 mm (3). wherein S1 stands for the cross sectional area of the core 18, S2 for the cross sectional area of the coil 20, S3 for the cross sectional area of the sleeve 12, and Dmax for the maximum distance formed between the outer periphery of the holder 14 and the inner periphery of the sleeve 12.

1. Field of the Invention
This invention relates to a heating device for a fixing system for use in such image forming apparatuses as electrophotographic copying machines, printers, and facsimile systems and more particularly to a heating device for use in an induction heating type fixing system for thermally fusing a toner image on a sheet and fixed the toner image on the sheet.
2. Description of the Related Art
Electrophotographic copying machines and other similar apparatuses are provided with a fixing system. The fixing system thermally fuses a toner image transferred on a sheet such as a recording paper or a transfer material, a recording medium and fixed the toner image on the sheet. A halogen lamp heating method such as is used in a heat roller fixing system and a induction heating method such as is used in a film fixing system may be cited as concrete examples of the heating technique used by the heating device in the fixing system. In recent years, the induction heating technique has been attracting attention on account of the advantage that the rate of temperature rise is high.
The film fixing system with the excellent temperature rise characteristics as disclosed in JP-A-07-114,276 and JP-A-08-16, 007 is proposed concerning the conventional fixing systems adopting the induction heating method. The film fixing system is provided with a film as a rotator, an exciting coil disposed on the inner side of the film, and a pressure roller. The film fixing system generates the magnetic flux in the exciting coil to generate an eddy current in the film for induction heating. Then, it causes the sheet to move in concert with the heated film while heating and fusing the toner on the sheet for fixation. In the fixing system disclosed in the patent publications, the rate of temperature rise of the fixing system is heightened by heating only the nip part of the periphery of the film in contact with the pressure roller.
The conventional fixing system is so constructed as to heat the nip part only. Consequently, it must perform both the heating of the film as a rotator and the heat transfer from the film to the sheet within a very small span of time in which the sheet passes through the nip part. A low-speed copying machine or printer may take a relatively long time to pass one sheet through the nip part. It can heat the film in the nip part thoroughly and thus fulfills the desired function of fixing. However, the medium- to high-speed copying machine or printer has to take a relatively short time for the passage of one sheet through the nip part. Namely, it requires to move the sheet and the film at a high speed and is incapable of thoroughly heating the film in the nip part. And it has the possibility of suffering defective fixation particularly on the rear end of the sheet along the direction of conveyance.


A canoe attachment includes a frame made of cylindrical members arranged in a substantially rectangular configuration. A seat is suspend between the forward frame member and the rearward frame member. A "forward-facing" rowing assembly is rotatably mounted on each of the opposite side frame members.

Both U.S. Pat. No. 2,815,517 to Andersen, Jr. and U.S. Pat. No. 4,649,852 to Piantedosi disclose a canoe attachment having a seat and oar supporting brackets. U.S. Pat. No. 4,068,611 to Leather discloses a sailing vessel attachment having a seat and oar supporting brackets. However, by converting any of these watercraft in the manners disclosed, one sacrifices the ability to see where one is going.
"Forward-facing" rowing assemblies are disclosed in several patents, including U.S. Pat. No. 2,536,451 to Lanning et al., U.S. Pat. No. 2,613,373 to Magdits, and U.S. Pat. No. 5,100,352 to Dunstan. Though enabling rowers to see where they are going, these devices are designed primarily for mounting on rowboats and do not appear to be readily adaptable for convenient installation and use on a canoe. In other words, there exists a need for a "forward-facing" rowing assembly which is designed specifically for attachment and operation relative to a conventional canoe.


An active matrix substrate includes a substrate, a TFT formed on the substrate, a storage capacitor element formed on the substrate, an interlayer insulating film covering the storage capacitor element, and a pixel electrode formed on the interlayer insulating film. The storage capacitor element includes a storage capacitor line, an insulating film formed on the storage capacitor line, and two or more storage capacitor electrodes opposed to the storage capacitor line with the insulating film interposed therebetween. The two or more storage capacitor electrodes are electrically connected via associated contact holes formed in the interlayer insulating film to the pixel electrode and electrically continuous with a drain electrode of the TFT.

AM substrates have been widely used for AM type display devices, such as liquid crystal display devices and EL (electroluminescence) display devices. A known AM type liquid crystal display device using such an AM substrate includes a plurality of scanning signal lines formed on the substrate, a plurality of data signal lines crossing the scanning signal lines, thin-film transistors (hereinafter, referred to also as "TFTs") located at the intersections of the above-mentioned signal lines, and other elements. An image signal is transmitted to each of pixel portions of the AM type liquid crystal display device by the switching function of the associated TFTs. Furthermore, the pixel portion may be provided with a storage capacitor element (see, for example, Patent Document 1).
Such a storage capacitor element prevents self-discharge of a liquid crystal layer during a period during which a TFT is in the off state or degradation of the image signal quality due to the off-state current of the TFT and is used not only for storage of the image signal during the period during which the TFT is in the off state but also as a path through which various modification signals are applied to the storage capacitor element to drive liquid crystal. A liquid crystal display device including a storage capacitor element can achieve low power consumption and high image quality.
An example of the known AM substrate configuration will be described hereinafter with reference to the drawings. FIG. 24 is a schematic plan view illustrating the configuration of a portion of an AM substrate corresponding to a pixel including a storage capacitor element. The AM substrate is used for a known AM type liquid crystal display device. FIG. 25 is a schematic cross-sectional view illustrating the cross section of the AM substrate taken along the line A-A′ in FIG. 24.
As illustrated in FIGS. 24 and 25, the AM substrate is provided with a plurality of pixel electrodes 51 arranged in a matrix form, scanning signal lines 52 for supplying scanning signals, and data signal lines 53 for supplying data signals. The data signal lines 53 extend along the lateral edges of the pixel electrodes 51, and the scanning signal lines 52 cross the data signal lines 53. TFTs 54 are located, as switching elements connected to the pixel electrodes 51, at the intersections of the scanning signal lines 52 and the data signal lines 53. Each scanning signal line 52 is connected to gate electrodes 62 of the associated TFTs 54, and the drive of each TFT 54 is controlled by a scanning signal fed to the associated gate electrode 62. Each data signal line 53 is connected to source electrodes 66a of the associated TFTs 54, and a data signal is fed to the source electrode 66a of the associated TFT 54. Furthermore, a drain electrode 66b is connected through a connection electrode 55 to one of electrodes (an upper storage capacitor electrode 55a) of a storage capacitor element, and the electrode of the storage capacitor element is further connected via an associated contact hole 56 formed in an interlayer insulating film 68 to the associated pixel electrode 51. A storage capacitor (common) line 57 is formed on a transparent insulating substrate (insulating substrate) 61, and the storage capacitor (common) line 57 functions as the other electrode (lower storage capacitor electrode) of the storage capacitor element.
As illustrated in FIG. 25, the gate electrode 62 is formed on the transparent insulating substrate (insulating substrate) 61 made of glass, plastic, or any other material so as to be connected to the associated scanning signal line 52. The scanning signal line 52 and the gate electrode 62 are formed of a metal film made of titanium, chromium, aluminum, molybdenum, or any other metal, an alloy of these metals, or a layered film of these metals. The storage capacitor (common) line 57 functioning as the other electrode (lower storage capacitor electrode) of the storage capacitor element is formed of the same material as the scanning signal line 52 and the gate electrode 62. A gate insulating film 63 covering the storage capacitor (common) line 57, the scanning signal line 52 and the gate electrode 62 is formed of an insulating film made of silicon nitride, silicon oxide, or any other material. A high-resistance semiconductor layer 64 made of amorphous silicon, polysilicon or any other material and a low-resistance semiconductor layer made of n+ amorphous silicon further doped with impurities, such as phosphorus, are formed on the gate insulating film 63 to overlap the gate electrode 62. The low-resistance semiconductor layer is changed into a source electrode 66a and a drain electrode 66b.
Each data signal line 53 is formed so as to be connected to the associated source electrodes 66a. Furthermore, the connection electrode 55 is formed so as to be connected to the associated drain electrode 66b and extends continuously with one of the electrodes of the storage capacitor element, i.e., the upper storage capacitor electrode 55a. The upper storage capacitor electrode 55a is connected via the contact hole 56 to the pixel electrode 51. The data signal line 53, the connection electrode 55 and the upper storage capacitor electrode 55a are formed of the same material, such as a metal film made of titanium, chromium, aluminum, molybdenum, or any other metal, an alloy of these metals, or a layered film of these metals.
The pixel electrode 51 is formed of a transparent conductive film made of, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, or tin oxide. The contact hole 56 passes through the interlayer insulating film 68 covering the TFT 54, the scanning signal line 52, the date signal line 53, and the connection electrode 55. As a material of the interlayer insulating film 68, use is made of, for example, an acrylic resin, silicon nitride, silicon oxide, or any other material. An AM substrate configured as illustrated in FIGS. 24 and 25 is disclosed, for example, in Patent Document 2.
For an AM substrate of such a configuration, in order to simplify a fabrication process and reduce the production cost, the storage capacitor (common) line (lower storage capacitor electrode) 57 is formed in the same process step as the scanning signal line 52, and the upper storage capacitor electrode 55a is formed in the same process step as the data signal line 53 and the connection electrode 55. Furthermore, in a case where, as illustrated in FIG. 25, the pixel electrode 51 covers the interlayer insulating film 68, this allows the pixel electrode 51 to overlap the signal lines 52 and 53. This overlapping increases the aperture ratio of a pixel and further has the effect of shielding electric fields from the signal lines 52 and 53 to the pixel electrode 51. In the above-mentioned case, the contact hole 56 is formed in a part of the interlayer insulating film 68 on a pattern forming the storage capacitor (common) line 57 or a pattern forming the scanning signal line 52. This provides connection between the pixel electrode 51 and the upper storage capacitor electrode 55a, and the upper storage capacitor electrode 55a is connected through the connection electrode 55 to the drain electrode 66b, thereby providing connection between the pixel electrode 51 and the drain electrode 66b. The location at which the contact hole 56 is formed is not limited within a region of the interlayer insulating film 68 located on the upper storage capacitor electrode 55a and may be within a region thereof located on the connection electrode 55. As illustrated in FIG. 24, the contact hole 56 is preferably formed within the region of the interlayer insulating film 68 located on the upper storage capacitor electrode 55a formed on a pattern forming the storage capacitor (common) line 57. The reason for this is that if the contact hole 56 is formed within the above-mentioned region, this prevents a reduction in the aperture ratio from being further caused.
For the storage capacitor element of the AM substrate illustrated in FIGS. 24 and 25, when conductive foreign particles (dust or particles) or a pin hole 99 exist in a part of the gate insulating film 63 between the storage capacitor line (lower storage capacitor electrode) 57 and the upper storage capacitor electrode 55a, this causes a short circuit between the storage capacitor line (lower storage capacitor electrode) 57 and the upper storage capacitor electrode 55a. Thus, the pixel in which a short circuit has occurred is found as a point defect on a display image. This should be improved. Furthermore, also when poor etching or poor photolithography cause a short circuit between the data signal line 53 and the upper storage capacitor electrode 55a which are formed in the same process step due to defects, such as an unnecessarily left part 98 of a film, a point defect likewise occurs and cannot be repaired. This should be devised.
For example, a liquid crystal display panel using vertically alignment (VA) liquid crystal, such as a multi-domain vertical alignment (MVA) liquid crystal, is set such that, under the condition that no voltage is applied to a liquid crystal, an associated pixel is displayed in black. In a case where a short circuit is caused between the data signal line 53 and the upper storage capacitor electrode 55a, a data signal is fed to the pixel electrode 51 without passing through the TFT 54. This prevents the data signal fed to the pixel electrode 51 from being able to be controlled by a scanning signal. In view of the above, the pixel is not displayed in black even on the condition that no voltage is applied to the liquid crystal but recognized as a bright dot. The bright dot generated when the whole area of the panel is displayed in black is more conspicuous than a black dot or a dark dot generated when the whole area thereof is displayed in white. As a result, the display quality is significantly affected by the bright dot. Techniques for repairing such point defects are disclosed in, for example, Patent Documents 3 through 5.
In recent years, pixels have increased in size with an increase in the screen areas of thin television sets. Accordingly, a defective pixel has come to be large enough to be unignorable from the viewpoint of the display quality. A technique has been developed in which, in order to reduce the size of a defective pixel, the size of a point defect is decreased by dividing one pixel into a plurality of subpixels. In this technique, a pattern becomes complicated by dividing one pixel into a plurality of subpixels, resulting in the reduced aperture ratio of the pixel. For example, for a 26-inch wide extended graphics array (WXGA) display, the aperture ratio of a pixel is reduced approximately 4% through 5%.
The structure of a liquid crystal display device in which adjacent pixels share a storage capacitor line to increase the aperture ratio of each pixel is disclosed in, for example, Patent Documents 6 and 7. More specifically, even when a pixel is divided into, for example, two subpixels, the existence of conductive foreign particles or a pin hole in a part of an insulating layer between a storage capacitor line (lower storage capacitor electrode) and an upper storage capacitor electrode causes a short circuit therebetween. The subpixel in which a short circuit occurs is recognized as a point defect on a display image. However, as compared with a case where a pixel is not divided, the area of the point defect is reduced to half. As a result, the display quality is insignificantly affected by the point defect.
FIG. 26 is a plan view schematically illustrating the configuration of a portion of an AM substrate corresponding to a pixel divided into a plurality of subpixels. FIG. 27 is a schematic cross-sectional view of the AM substrate taken along the line B-B′ in FIG. 26. In FIGS. 26 and 27, the same components as those illustrated in FIGS. 24 and 25 are denoted by the same reference numerals.
As illustrated in FIGS. 26 and 27, a pixel electrode 51 is divided into two subpixel electrodes 51L and 51R. A scanning signal line 52 for supplying scanning signals is located in the vicinity of the border between these subpixel electrodes 51L and 51R, and a data signal line 53 for supplying data signals extends along the lateral edges of the pixel electrode 51. TFTs 54L and 54R serving as switching elements are located at the intersection of the scanning signal line 52 and the data signal line 53 so as to be connected to the subpixel electrodes 51L and 51R. The scanning signal line 52 is interposed between the TFTs 54L and 54R when viewed in plan. The scanning signal line 52 is connected to gate electrodes 62L and 62R of the TFTs 54L and 54R. The drive of the TFTs 54L and 54R is controlled by scanning signals fed to the gate electrodes 62L and 62R. Furthermore, the data signal line 53 is connected to source electrodes 66a of the TFTs 54L and 54R, and thus data signals are fed to the source electrodes of the TFTs 54L and 54R. Moreover, drain electrodes 66b are connected through connection electrodes 55L and 55R to respective ones (upper storage capacitor electrodes) 55La and 55Ra of electrodes of storage capacitor elements and further connected via contact holes 56L and 56R formed in an interlayer insulating film 68 to the subpixel electrodes 51L and 51R. A storage capacitor (common) line 57 is formed on a transparent insulating substrate (insulating substrate) 61 and functions as the other electrodes (lower storage capacitor electrodes) of the storage capacitor elements. In other words, the respective upper storage capacitor electrodes 55La and 55Ra of adjacent pixels share the storage capacitor (common) line 57 as the other electrodes (lower storage capacitor electrodes) of the storage capacitor elements. The AM substrate illustrated in FIGS. 26 and 27 can be fabricated through the similar process steps to those through which the AM substrate illustrated in FIGS. 24 and 25 are fabricated.
For the AM substrate illustrated in FIGS. 26 and 27, the storage capacitor (common) line 57 is formed in the vicinity of the border between adjacent pixels to suppress a reduction in the aperture ratio of each pixel. In order to ensure sufficient storage capacity, the areas of the upper storage capacitor electrodes 55La and 55Ra opposed to the storage capacitor (common) line 57 need to be as large as possible. In view of the above, since the respective upper storage capacitor electrodes 55La and 55Ra of adjacent pixels are close to each other, it is likely to cause current leakage failures between the upper storage capacitor electrodes 55La and 55Ra adjacent to each other.
In a case where a current leakage failure is caused, two subpixel electrodes 51L and 51R sharing a storage capacitor (common) line 57 become electrically continuous, resulting in combined defects. In order to avoid this, a repair needs to be made to defects to prevent a data signal for an adjacent pixel from being fed to the pixel. For example, in order to prevent a data signal from entering from an upper storage capacitor electrode 55La of one (first pixel) of adjacent pixels into a subpixel electrode 51R of a second pixel adjacent to the first pixel, a part of the subpixel electrode 51R of the second pixel located in a contact hole 56R is removed. In this manner, the subpixel electrode 51R is electrically isolated from the upper storage capacitor electrode 55Ra. Furthermore, in order to prevent a data signal from entering through a drain electrode 66b of the second pixel and the upper storage capacitor electrodes 55La and 55Ra into a subpixel electrode 51L of the first pixel, a connection electrode 55R of the second pixel is electrically isolated from the upper storage capacitor electrode 55Ra. In view of the above, a subpixel of one (second pixel) of the adjacent pixels is nonenergized, leading to a point defect.
In other words, for an AM substrate in which a pixel is divided into a plurality of subpixels, a point defect less significantly affects the display quality than for an AM substrate in which a pixel is not divided. The AM substrate in which a pixel is divided into a plurality of subpixels may cause a current leakage failure between adjacent upper storage capacitor electrodes 55La and 55Ra, resulting in an increase in the possibility of bringing about a point defect. This should be improved.
Patent Document 1: Japanese Unexamined Patent Application Publication No. 6-95157 (page 1)
Patent Document 2: Japanese Unexamined Patent Application Publication No. 9-152625 (pages 8 through 11 and 19, FIGS. 3 and 4)
Patent Document 3: Japanese Unexamined Patent Application Publication No. 1-303415
Patent Document 4: Japanese Unexamined Patent Application Publication No. 9-222615
Patent Document 5: Japanese Unexamined Patent Application Publication No. 7-270824
Patent Document 6: Japanese Unexamined Patent Application Publication No. 2004-62146
Patent Document 7: Japanese Unexamined Patent Application Publication No. 2004-78157

Active matrix substrate, method for fabricating active matrix substrate, display device, liquid crystal display device, and television device


A camera is fixed to a camera fixture extending forward and upward from a rear end of an arm mechanism. The camera picks up the direction of extension of the arm mechanism when the substrate is carried in and out. If a normal still image in a hot plate unit previously recorded and a still image picked up by the camera coincide with each other, a substrate transport robot TR carries in and out the substrate.

1. Field of the Invention
The present invention relates to a substrate processing apparatus and a substrate processing method for subjecting a substrate to predetermined processing.
2. Description of the Background Art
Conventionally, substrate processing apparatuses have been provided with a plurality of processing units such as liquid processing units and thermal processing units. In order to subject a substrate to a series of processings, a substrate transport robot for carrying the substrate among the plurality of processing units is provided (see JP-A-11-329912).
Each of the processing units is provided with a shutter. When the substrate is carried in and out, the shutter is opened, so that the substrate can be carried in and out by the substrate transport robot. Further, the shutter is closed while the substrate is being processed.
When the shutter is not opened due to inferior operation or the like at the time of carrying in the substrate, collisions between the substrate transport robot and the shutter cannot be avoided so that the substrate is damaged. Even when there exists a substrate receiving member in a carrying passage of the substrate transport robot due to inferior operation of the substrate receiving member, for example, within each of the processing units, collisions between the substrate transport robot and the substrate receiving member cannot be also avoided so that the substrate is damaged.

Substrate processing apparatus and method including obstacle detection


A process and apparatus are disclosed for the demineralization of ground bone particles or pieces of cancellous or cortical bone. The apparatus includes multiple solution reservoirs which supply solutions to be pumped into one or more columns filled with bone samples to be demineralized. Solvent outflowing from the column(s) can be monitored for pH, calcium ion concentration or conductivity as a basis for determining when demineralization is complete. During the delipidization phase of processing, lipid solute can be monitored by photometry, or a small assay of the eluent can be dropped into deionized water to see whether a precipitate develops. Flow through the apparatus, including the types and amounts of solutions to be flowed through the apparatus, can be manually or computer controlled.

1. Field of the Invention
The invention concerns an apparatus which is suitable for permeating solid materials with various solutions and is particularly directed to processes for the demineralization of bone tissue. The invention is also directed to an apparatus for performing the processes.
2. Description of Background Information
It is known that implementation of acid demineralized bone (DB) in the form of a powder in extraskeletal sites stimulates new bone formation. Various research groups (Syftestad, 1982; Urist et al., 1967; Urist and Strates, 1970; Urist & Strates, 1971; Urist et al., 1983) have suggested that a noncollagenous protein present in demineralized bone has the ability to induce new bone formation when present within the implanted bone matrix.
Procedures presently utilized to demineralize ground bone fragments involve the use of ethanol to remove lipids and hydrochloric acid to remove the mineral component of bone.
It is also known to treat bones and bone particles to render them biocompatible so that they can be implanted in living animal and human bodies without being rejected. Included among the known methods for treating bone is the delipidization of bone using ethanol or chloroform. It is further known to demineralize bone matrix with an inorganic acid such as hydrochloric acid.
Demineralized, defatted bone can be further treated with antibacterial and antifungal agents to help prevent infection upon implantation into a living organism.
SEYEDIN et al., U.S. Pat. No. 4,434,094, describes the fragmentation of bone into small pieces and subsequent treatment by extraction with ethanol ethylacetate to remove lipids from the bone fragments. Calcium phosphate is next dissolved from the bone matrix by contacting the bone particles with dilute hydrochloric acid for one hour up to several days.
JEFFERIES, U.S. Pat. No. 4,394,370, discloses a similar method of demineralization wherein bones are first cleaned and extracted with absolute ethanol followed by anhydrous ethyl ether. The bones are then pulverized and sieved to a standard particle size. Demineralization is achieved through extraction with 0.5N hydrochloric acid for at least three hours followed by multiple washes in sterile distilled water to remove calcium and acid residues, followed by multiple sequential 60-minute washes in ethanol and anhydrous ether.
Although it is well known to defat and demineralize bone for implantation purposes, known methods of demineralizing and removing lipids have been extremely tedious, labor intensive and slow. Furthermore, an excessive amount of handling and/or exposure of the bone to non-sterile conditions has been necessary during the various phases of processing.
Delipidization and demineralization of bone matrix has been conducted largely through soaking the bone matrix in extraction solutions. Demineralization of bone involves the solubilization of hydroxyapatitic materials using fairly strong acids. As demineralization proceeds, the solubilized hydroxyapatitic materials act to buffer the acidic solution thereby raising the pH. This renders the acid less effective, and demineralization thus takes longer, or greater volumes of acid are required, because the acid solution must be completely changed to restore the pH to an effective level.

Process for demineralization of bone using column extraction


The invention presents a method, apparatus and container for sterilizing solid matter or liquid matter containing solid matter efficiently in a short time, while preventing deterioration of quality or decline of flavor.. In this method, solid matter (a) and liquid matter (b) are separately heated and sterilized, and both are mixed after being sterilized, and put and sealed in a bag (c) or container. When heating and sterilizing the solid matter independently, the solid matter is weight and dispensed in each retainer (c) by the portion of one pack each, and sterilized, and is transferred, after being sterilized, from the retainer (d) into a bag (c) or container, and sealed. Sterilization is executed by rotating the retainer (d) and inducing an agitating action on the inside solid matter. The apparatus comprises a sterilizing tank 22 or 42 for receiving and supporting a plurality of retainers (d) by a plurality of guide rails 22e so as to allow to roll in an aligned state, and an oscillating device 40 or 72 for oscillating it like a seesaw. The retainer (d), that is, a container 81 is formed in a cylindrical cup form on the outer circumference so as to be easy to roll and rotate, and the inner circumference and inner bottom are provided with means for promoting agitation of the solid matter.

Generally, retort food is prepared by mixing unsterilized food materials, such as solid matter and liquid matter, putting in a bag or the like of plastics or aluminum, sealing, applying in a retort apparatus, and heating and processing to sterilize.
In the conventional sterilizing method, since solid matter and liquid matter are heated and processed simultaneously by passing through a sealed bag or the like, processing suited to solid matter and processing suited to liquid matter cannot be done separately, and the processing time tends to be long, ranging from scores of minutes to several hours, and it took a longer time when the thickness of the bag was larger. Accordingly, the food was exposed to high temperature for a long time, which led to problems of deterioration of quality and decline of flavor.
Moreover, when sterilizing solid matter only, hitherto, a large volume was put in a large pressure vessel to sterilize for a long time, and uneven processing and overcooking were likely to occur, or it required weighing or dispensing to distribute into bags after processing, which was often accompanied by deformation, and yet drip or juice exuding from the solid matter at the time of sterilization process remained in the bottom of the pressure vessel, and it was extremely difficult to put it into the bag together with the solid matter, and the drip containing taste components was discarded as waste liquid.

Sterilizing method, apparatus and container of solid matter or liquid matter containing solid matter


Peak power of a coherent light beam generated by a laser and injected into an optical fiber is chosen so that the spectrum of the light beam emanating from the fiber, for illuminating particles, includes Raman lines.

A method of this type is already known, for example from document EP-1 183 518, in which a coherent light beam, preferably a pulsed light beam, is injected into an optical fiber, via one end of the fiber, and said particles are illuminated by the pulses of the light beam emanating from the other end of said fiber.
To implement such a method, a monomode optical fiber is chosen for the purpose of preventing the occurrence of parasitic noise in said images.
However, to obtain contrasted sharp images of said particles, the energy injected at each pulse of the coherent light beam must be high enough to allow said particles to be illuminated sufficiently to form their images. In such a case when the injected light energy is high, despite the use of a monomode optical fiber, the images of said particles exhibit parasitic background noise and a moiré effect that degrade their sharpness.

Method for illuminating particles for the purpose of forming their images


Embodiments of the present invention relate to methods and systems for detecting and removing a clogging condition of a filter in a dishwasher. According to one embodiment, the method includes determining a normal water level or a normal rate of water level change for a wash cycle of the dishwasher and monitoring a water level or a rate of water level change during execution of the wash cycle. The method further includes detecting the clogging condition of the filter by detecting a deviation thereof. A current position of the wash cycle being executed may then be determined. The method further includes executing a remedial operation to facilitate removal of the clogging condition and determining if the clogging condition has been removed. Finally, the method includes resuming operation of the dishwasher at a wash cycle position based on the current position if the clogging condition has been removed.

Dishwashers have become an integral part of everyday household use. Typical dishwashers use water pumped into a tub to clean dishes and utensils during wash cycles. Dishwasher tubs comprise a sump with a filter that separates food soils from wash water. The soils exit the tub through the drain and the wash water falls through the filter to a circulation pump that re-circulates the water through the tub via spray arms. Sometimes, however, the filter can become clogged with soils, overwhelming the filter and preventing or slowing the passing of wash water through the filter. In this case, a lack of water below the filter causes the circulation pump to suck in air, which may cause the circulation pump to become starved (run dry), lose its prime, or stop pumping altogether. These conditions may ultimately damage the circulation pump if not treated quickly.

Method and system for detecting and removing a clogging condition of a filter in a dishwasher


There is provided an electrolyte solution including a solvent formed from a sulfone, and a magnesium salt dissolved in the solvent.

The present disclosure relates to an electrolyte solution, a method for producing an electrolyte solution, and an electrochemical device. More specifically, the present disclosure relates to a suitable electrolyte solution, and method for producing that electrolyte solution, that is used as the electrolyte layer in a magnesium (Mg) ion battery for example, and various electrochemical devices having a magnesium ion battery and the like that uses this electrolyte solution.
Magnesium ion batteries are drawing attention as a next-generation secondary battery to replace lithium ion batteries due to the fact that compared with lithium, magnesium is a much more abundant natural resource and is far cheaper, the amount of electricity per unit volume that can be extracted by a redox reaction is large, and there is also a high level of safety when used in a battery.
In the past, magnesium electrolyte solutions for a magnesium ion battery have all used an ether solvent. Especially, it has been reported that the electrolyte solutions that use tetrahydrofuran (THF) have the best properties (refer to JP-T-2003-512704, JP-A-2009-21085, and Nature Communications Volume: 2, Article number: 427 DOI: doi:10.1038/ncomms1435).
However, ether solvents such as THF are difficult to handle due to their high volatility and because they are often toxic. Further, the potential window (the maximum voltage that can be applied without the electrolyte solution degrading) of a magnesium electrolyte solution that uses an ether solvent is at most about 3.0 V, which is small. Consequently, it has not been possible to produce a battery having a high voltage using a magnesium metal negative electrode.
Due to the above reasons, development has proceeded on magnesium electrolyte solutions that use a solvent other than THF. As a result, a magnesium electrolyte solution was discovered that can be used on magnesium alloy (refer to Electrochemistry Communications 16 (2012) 103-106).
JP-A-2003-100347 discloses a non-aqueous electrolyte battery that uses alkyl sulfone, which is a non-ether solvent, for the electrolyte solution. Specifically, this non-aqueous electrolyte battery includes a positive electrode, a negative electrode including at least one element selected from aluminum, calcium, and magnesium, and a non-aqueous electrolyte solution. This non-aqueous electrolyte solution contains an alkyl sulfone represented by R1R2SO2 (wherein R1 and R2 represent an alkyl group) and at least one selected from an aluminum salt, a calcium salt, and a magnesium salt in a mixed solvent of the alkyl sulfone and an organic solvent that dissolves the at least one selected from an aluminum salt, a calcium salt, and a magnesium salt. As the organic solvent, at least one selected from γ-butyrolactone, acetonitrile, and propylene carbonate is used.

Electrolyte solution, method for producing electrolyte solution, and electrochemical device