A fiber-reinforced resin member of the present invention comprises a solid or hollow rod member (2) made of a fiber-reinforced resin material (5, 6), a soft metal layer (3) formed on the outer periphery of the rod member by squeezing a soft metal on the outer periphery of the rod member so as to cause the soft metal to adhere under pressure to the outer periphery of said rod member, and a hard metallic deposit (4) formed on the surface of the sot metal layer. The present invention also provides a method of producing the fiber-reinforced resin member.

Solid or hollow fiber-reinforced resin members, which are formed by winding a strand of continuous filaments impregnated with a resin, increasingly attract attention because of their light weight and high strength For example, refer to JP, A, 63-166519, 63-166522 and 63-249628. In these publications, JP, A, 63-166519 discloses the use of a fiber-reinforced resin member for the piston rod of a hydraulic or pneumatic cylinder. However, there is a problem in that, when a fiber-reinforced resin member is used as a member such as the piston rod of a hydraulic or pneumatic cylinder, the spool of a hydraulic or pneumatic valve or the like, which is required to have an external surface having surface accuracy, it is difficult to secure the surface accuracy.
Namely, although JP, A, 63-166519 discloses the use of a fiber-reinforced resin member for the piston rod of a hydraulic or pneumatic cylinder, since the piston rod of the hydraulic or pneumatic cylinder hermetically slides in the cylinder, high surface accuracy is required for providing a seal between the rod and the sliding surface of the cylinder. In practice, it is therefore necessary to perform treatment for securing the surface accuracy of the external surface after a fiber-reinforced resin member rod has been produced in accordance with the proposal of JP, A, 63-166519 and then subjected to surface finish of the external surface by mechanical polishing. An example of such treatment is plating treatment for coating the external surface with a rigid material such as chromium or the like. This plating treatment is effected by a general method for plating the surfaces of conventional synthetic resins in accordance with the following procedure:
After the external surface of the fiber-reinforced resin member produced has been finished by mechanical polishing, a layer of a soft metal such as copper or the like is first formed on the external surface by plating, and a layer of a hard metal such as chromium or the like is then formed on the soft metal layer by plating.
However, since the fiber-reinforced resin member is made of a soft resin and a fiber material composed of continuous hard filaments, fine cracks occur in the soft resin portion when the external surface of the fiber-reinforced resin member is polished. When the external surface is plated to form the soft metal layer thereon, therefore, the plating solution used penetrates into the cracks. This causes insufficient coating of the soft metal layer and consequently the difficulty in coating of the hard metal layer with high strength. Further, since the soft resin portion is polished earlier than the hard fiber material, the hard fiber material remains raised on the surface, and it is thus difficult to finish the surface flatly. It is thus impossible to obtain high surface accuracy because, even if the external surface is subjected to plating suitable for the soft metal layer and the hard metal layer, unevenness remains on the surface of the hard metal layer in correspondence with the unevenness on the polished surface of the fiber-reinforced resin member.
It is an object of the present invention to provide a fiber-reinforced resin member which can attain high surface accuracy and a method of producing the resin member.

Fiber-reinforced resin member and method of producing the same

Hitachi Construction Machinery Co., Ltd.


A device for forming panels of cast concrete having simulated mortar lines. The device rests above a casting bed on the beds rails. As the bed moves relative to the device, the movement is translated to a shuttle and press mechanism that descends into the uncured concrete, makes the impression, lifts and returns to the start. At this time the rear mortar line is now in position with the device to make a new forward line due to the indexing of the bed movement relative to the device.

1. Field of the Invention
This invention relates to an apparatus for forming hollow-core concrete slabs with a brick, block, stone or other embossed imprint on a surface.
2. Description of the Related Art
U.S. Pat. No. 4,369,153 which issued Jan. 18, 1983 to Nash et al discloses a machine which casts hollow core concrete panels in a single casting operation utilizing a slip form technique to fill cores with core material which can be dumped from the core after curing of the concrete has been accomplished. U.S. Pat. No. 4,369,153 is incorporated herein by reference.
In single casting operations, hollow core concrete panels are formed on a moving bed in which concrete is first poured around the front end of a slip form which forms the bottom layer of the concrete panel. The bed moving past the slip form shapes the bottom layer of the concrete panel. As the concrete travels on the bed past the slip form, core material which may be an aggregate, is fed into openings in the slip form to fill the desired cores with core material.
Such casting uses relatively wet concrete and often involves beds of 600 feet or more in length. A variety of patterns may be placed into the still wet concrete before it has cured. Many hand laid patterns may be made with the involvement of skilled laborers. However, such hand-operated techniques are difficult to control, since one mistake may ruin a long length of finished plank.
A number of surface finishes have been formed in which longitudinal ribbing is placed into the screed surface. This is relatively easy to accomplish as typified by U.S. Pat. No. 4,457,682. Alternatively, the top concrete may be carefully washed to expose the underlying aggregate rock. See U.S. Pat. No. 4,360,333.
Other means for making a simulated brick wall involve the placement of thin bricks into the still wet concrete. British patent 1,539,179 is an example.
The art described in this section is not intended to constitute an admission that any patent, publication or other information referred to herein is "prior art" with respect to this invention, unless specifically designated as such. In addition, this section should not be construed to mean that a search has been made or that no other pertinent information as defined in 37 C.F.R. .sctn. 1.56(a) exists.


The present invention includes a condition setting portion configured to set a condition used to select titles to be registered in a play list among a plurality of titles recorded on a recording medium, a retrieval portion configured to retrieve titles corresponding to a set condition by making reference to management information recorded on the recording medium, and a registration portion configured to register retrieved titles in the play list.

1. Field of the Invention
The present invention relates to a data reproduction apparatus and a data reproduction method which read recorded data from a recording medium, e.g., a DVD (Digital Versatile Disk) and reproduce the data, and more particularly to an apparatus and a method which facilitate play list editing operation.
2. Description of the Related Art
As is well known, the above-described data reproduction apparatus is provided with a so-called play list reproduction function which automatically reproduces preset titles in a predetermined order among a plurality of titles recorded on an optical disk.
When performing this play list reproduction, there is required a play list editing operation which selects titles to be registered in a play list from a plurality of titles recorded on an optical disk.
As this play list editing operation, there is a technique to select required titles while grasping the content of each title by reproducing an optical disk, and a technique to select required titles while making reference to management information of individual titles.
In short, when performing the play list editing, there is required an operation to reproduce titles recorded on an optical disk or an operation to make reference to management information of titles.
In such a play list editing operation, however, when the number of titles recorded on the optical disk is increased, there occurs a problem that the operation to select required titles becomes troublesome and handling is inconvenient for users.
Further, when the title selection operation becomes troublesome in this way, there also occurs an inconvenience that a title which should be selected is passed over and a requested title is not registered in a play list.
It is to be noted that Jpn. Pat. Appln. KOKAI Publication No. 2001-167559 discloses a structure which is a method for adding information of a video object determining a difference value between recording time information and display start time information as identification information, and which can specify a video object without being affected by deletion of time information.
Furthermore, Jpn. Pat. Appln. KOKAI Publication No. 2002-150750 discloses a structure which controls a reserved recording operation based on information concerning recording reservation and information indicating whether this information is valid or invalid.
Moreover, Jpn. Pat. Appln. KOKAI Publication No. 2002-84495 discloses a structure which changes original management information of a video stream recorded on a recording medium into new management information based on editing information input by a user.
However, these publications do not mention facilitation of an operation to select titles to be registered in a play list from a plurality of titles recorded on an optical disk.

Data reproduction apparatus and data reproduction method


The invention relates to a charging apparatus for contactless charging of an electrical energy store (2) of a motor vehicle (1), comprising a primary unit (13) which is arranged outside the motor vehicle (1) and comprising a vehicle-mounted secondary unit (14). In order to simplify contactless charging of a motor vehicle comprising an electrical energy store, the vehicle-mounted secondary unit (14) can be moved relative to the primary unit (13), which is arranged outside the motor vehicle (1), in order to reduce the size of an air gap or distance (16) between the primary unit (13) and the secondary unit (14).

1. Field of the Invention
The invention relates to an apparatus for contactless charging of an electrical energy store of a motor vehicle. The apparatus has a primary unit outside the motor vehicle and a secondary unit mounted in the vehicle. The invention also relates to a motor vehicle comprising an electrical energy store and a vehicle-mounted secondary unit that cooperates with a primary unit outside the motor vehicle. The invention further relates to a method for contactless charging of an electrical energy store of a motor vehicle.
2. Description of the Related Art
An electric vehicle or a hybrid vehicle has an electric motor that is supplied with electrical energy by an electrical energy store. The electrical energy store can be charged with the aid of a charging apparatus, as is disclosed, for example, in Japanese publication JP 2000-152512. German laid-open specification DE 10 20011 003 436 A1 discloses a charging column that can be connected to an electric vehicle by a charging cable for charging the electric vehicle. The charging column can be retracted and extended in relation to a hollow space.
The object of the invention is to simplify contactless charging of a motor vehicle that has an electrical energy store.

Contactless charging of an electrical energy store of a motor vehicle

Dr. Ing. h.c. F. Porsche Aktiengesellschaft


An axial gap alternator comprises a first carrier associated with or secured to an output shaft of an internal combustion engine. A first carrier carries a first set of magnets arranged radially about a rotational axis. A second carrier carries a second set of magnets arranged radially and spaced apart axially from the first set of magnets. A stator intervenes axially between the first set of magnets and the second set of magnets.

A hybrid vehicle may include an internal combustion engine that provides rotational energy to an alternator or generator. Although the mechanical coupling between the alternator and the internal combustion engine may comprise a belt, a chain, gears, or pulleys or other intermediary mechanical devices, such intermediary devices may occupy too much space within an engine compartment or be less reliable than desired. Accordingly, there is a need for an axial gap alternator associated with a flywheel of an output shaft (e.g., crankshaft) of the internal combustion engine.

Axial gap alternator associated with a flywheel


A handle, housing and cover assembly includes an relatively thick oval handle sandwiched between a relatively thin oval housing base and a relatively thin oval cover. The oval exteriors of these three relatively movable components are of substantially the same size and shape, and align when the cover is closed and when the handle is in its normal, non-operated position to provide a low profile stack of components that can nest comfortably within the palm of one's hand so the palmed cover can be moved by gentle hand pressure between closed and open positions, and so the handle can be pivoted by fingertip pressure between non-operated and operated positions. The cover, when open, provides access to a keyway into which a key can be inserted and turned to selectively prevent and permit turning of the handle relative to the housing base.

Handle and housing assemblies having a handle that can be grasped and turned about an axis to operate an auxiliary mechanism such as an associated latch (or a set of associated latches) are known and used widely to latch and lock such closures as the tailgates and tonneau covers of pickup trucks, sport utility vehicles and the like.
To minimize the possibility of clothing or belongings of passers being inadvertently hooked or caught on handle and housing assemblies used in motor vehicle applications, and taking into account other concerns of appearance and safety, handle and housing assemblies having rounded exterior surfaces and low profiles have been proposed. Some proposals have included pivotal covers to shield and conceal lock cylinder keyways.
A problem common to many of these proposals is that their relatively movable handle, housing and cover components have proved difficult to grasp and operate, especially for persons wearing gloves or for persons afflicted with infirmities such as arthritis. Designing a handle, housing and cover assembly that incorporates attractive, easy to grasp and operate handle and cover components which cooperate with a housing to provide suitably rounded exterior surfaces and a desirably low profile has presented more of a challenge than one might expect.

Low profile, lockable handle, housing and cover assembly


A fuel extraction and pressurization system for delivering a gaseous fuel from a adsorbent fuel tank to a fuel injection system of an internal combustion engine, wherein the fuel extraction and pressurization system comprises one or more components for applying a vacuum to the interior of the tank to facilitate the extraction of the adsorbed gaseous fuel from the tank and compressing the extracted gaseous fuel to a pressure appropriate for the fuel injection system.

Sorbent-based gaseous fuel storage systems such as activated carbon sorbent storage of natural gas advantageously operate at lower pressures than non-sorbent systems. For example, sorbent storage systems operate at relatively low pressures in a range of about 10 psi (0.07 MPa) to about 1000 psi (7 MPa) compared to 3,600 psi (24.821 MPa) for conventional, non-sorbent systems for internal combustion engines. While the lower pressures associated with sorbent-based systems have the potential of being more readily utilized in applications such as motor vehicles due to the fact that the systems can be less robust, bulky, complicated, and costly than high pressure systems, there have been performance drawbacks that have hindered their acceptance. In particular, getting the adsorbed gaseous fuel out of a tank and delivered to the engine for combustion in a controlled and consistent manner has been a technical challenge.
One reason for the difficulty is due to the relatively low pressures involved, which is as the amount of fuel in a tank is drawn down during operation of the engine. Specifically, the release of adsorbed gaseous fuel is typically a linear relationship with tank pressure. Thus, as the fuel is drawn from the tank, the pressure decreases, which in turn decreases the tendency of fuel to be released. This decrease in pressure has been particularly challenging to operating internal combustion engines which can often require fuel pressures that exceed that of the gaseous fuel in the tank.
Additionally, the type of sorbent and/or type of gaseous fuel can affect the fuel release. In general, the more fuel a particular fuel-sorbent combination can accommodate, the stronger the adsorbtion of the fuel. The stronger the adsorbtion, the less likely the fuel may be consistently delivered to an engine, especially as the pressure decreases. This has tended to limit the selection of sorbents, in particular, the most effective sorbents.
Still further, because the typical modern conventional engines require gaseous fuel to be pressurized for injection into the engine (e.g., up to about 200 psi), a significant amount of fuel has remained essentially unusable/inaccessible in the tank.
In view of the foregoing, a need still exists for equipment and methods for extracting a gaseous fuel from a sorbent-based storage tank in a consistent and controlled manner over a wide range of tank pressures and/or fuel levels. Further, a need still exists for the consistent and controlled delivery of gaseous fuel extracted from a sorbent-based storage tank to the fuel injection system of an internal combustion engine over a wide range of tank pressures and/or fuel levels.

Sorbent-based low pressure gaseous fuel delivery system


Optical print head includes: light-emitting elements connected one-to-one to current supply lines branching from first power line at different positions in longitudinal direction; holding elements; signal writing unit writing luminance signal into each holding element, the luminance signal being represented by voltage indicating light emission amount of corresponding light-emitting element; second power line supplying reference voltage to each holding element, the reference voltage being reference when signal writing unit writes luminance signal into holding element; and driving drivers corresponding one-to-one with current supply lines and controlling current supplied to corresponding current supply line from first power line, in accordance with voltage held in corresponding holding element when signal writing unit has written luminance signal into corresponding holding element, wherein power source supplying the reference voltage to second power line is common with power source supplying voltage to signal output subunit outputting luminance signal.

(1) Field of the Invention
The present invention relates to an optical print head (PH) that performs writing onto a photoreceptor by an optical beam and an image forming apparatus including the optical PH.
(2) Related Art
Some of image forming apparatuses such as printers include an optical PH that writes an image onto a photoreceptor by an optical beam emitted from each of minute light-emitting elements that are arranged in line.
Japanese Patent Application Publication No. 2005-144686 discloses, as an optical PH, a line head including a large number of organic EL elements as light-emitting elements that are arranged on a substrate in a main scanning direction.
Such a line head has a configuration in which a parallel circuit is arranged on the substrate, which is composed of the organic EL elements each having an anode connected with a power line A on a power source side and a cathode connected with a power line B on a ground side. Also, a moisture-proof plate is provided spaced from the substrate, and has wired thereon an auxiliary power line C on the power source side and an auxiliary power line D on the ground side.
The line head has a circuit configuration in which an increased number of power feeding points for the organic EL elements are provided by electrically connecting the power line A on the substrate with the auxiliary power line C on the moisture-proof plate at a plurality of points and electrically connecting the power line B on the substrate with the auxiliary power line D on the moisture-proof plate at a plurality of points.
With this circuit configuration in which an increased number of power feeding points are provided, it is possible to shorten a wiring distance on the power line from one power feeding point to each of the organic EL elements compared with the configuration in which a less number of power feeding points are provided. Since there is a less potential drop due to a wiring resistance, it is possible to decrease a difference in supply current between the organic EL elements caused by the potential drop, thereby suppressing unevenness in light emission amount between the organic EL elements.
However, even if the configuration is adopted in which a certain increased number of power feeding points are provided as in the configuration disclosed in the above patent application publication, there is no change that a potential drop occurs on a part of a power line between each two adjacent power feeding points in the current flowing direction. Accordingly, a problem still remains that unevenness in light emission amount due to the potential drop is not eliminated.

Optical print head having first and second power lines and image forming apparatus


A laser arrangement includes a VCSEL array comprising multiple VCSELs arranged on a common semiconductor substrate, an optical structure, and a diffusor structure. The optical structure is arranged to reduce a divergence angle of laser light emitted by each respective VCSEL to a section of the diffusor structure assigned to the respective VCSEL. The diffusor structure is arranged to transform the laser light received from the optical structure to transformed laser light such that a continuous illumination pattern is configured to be provided in a reference plane in a defined field-of-view. The diffusor structure is arranged to increase a size of the illumination pattern in comparison to an untransformed illumination pattern which can be provided without the diffusor structure. The VCSEL array, optical structure, and diffusor structure are arranged such that sections of the diffusor structure do not overlap. Diffusor properties of the diffusor structure vary across the diffusor structure.

Laser arrangements comprising a VCSEL array can be used for infrared illumination devices. Using short pulses VCSEL arrays are, for example, applied in time-of-flight applications. Such applications comprise e.g. short-range gesture recognition for portable devices and 3D space recognition. VCSEL arrays of about 1 mm2 area with output power in the 1-10 W range are discussed for such applications. A specific field of illumination or view is defined by the application (e.g. a time-of-flight camera observing e.g. 70°×50°).
US 2016/0164261 A1 discloses methods, devices and systems for selectively illuminating different zones of a field of view by a multi-zone illumination device. The multi-zone illuminator may include a plurality of vertical cavity surface emitting lasers (VCSELs), and a plurality of micro-optical devices aligned with apertures of individual or groups of VCSELs, which are configured to be individually activated to provide adjustable illumination to different zones of a field of view of an image sensor.

Laser arrangement comprising a VCSEL array


A weather strip has a trim part adapted to be mounted on a flange, a seal part having a hollow portion and a cover lip. The trim part has a bottom wall portion, and an interior and an exterior side wall portions which constitute a pair of side wall portions and is formed into a shape, as a whole, having a substantially U-shaped cross section, and an insert of a center bonded type is embedded in the interior of the trim part so constructed. In a skeletal piece of the insert, an angle θa formed by a bottom wall part embedded in the bottom wall portion and an internal part embedded in the interior side wall portion and an angle θb formed by the bottom wall part and an external part embedded in the exterior side wall portion are made to form acute angles.

1. Field of the Invention
The present invention relates to a weather strip having a trim part of a substantially U-shaped cross section.
2. Related Art
In general, for example, a weather strip made of a rubber material such as EPDM is provided on a peripheral portion of a door opening in a body of a vehicle such as an automobile. The weather strip is formed into an elongated shape having a constant cross-sectional shape by extrusion molding. In addition, as shown in FIG. 6A, a weather strip 51 has a trim part 52 that is held by being fitted on a flange along a peripheral portion of the door opening and a hollow seal part 53 that is provided so as to protrude from the trim part 52. The trim part 52 includes a bottom portion 54, and an interior side wall portion 55 and an exterior side wall portion 56 which are extend substantially in parallel from the bottom portion 54 and is formed into a shape having a substantially U-shaped cross section as a whole. A metallic insert 57 is embedded in the interior of the trim part 52 in order to hold the substantially U-shaped cross section.
In assembling the weather strip 51 like this to a corner portion of the peripheral portion of the door opening in the vehicle body, the weather strip 51 needs to be bent relative to a longitudinal direction thereof so as to conform to a curved shape of the corner portion. Here, when the curvature of the curved shape is large, there may exist a risk that a so-called open deformation of the trim part occurs in which an opening in the substantially U-shaped cross section of a trim part 58 opens as shown in FIG. 6B. In a weather strip 59 in which the open deformation of the trim part occurs, a gap is generated between the flange and the weather strip itself, leading to drawbacks that the external appearance is deteriorated and that the holding force is reduced to facilitate the dislocation of the weather strip.
Then, in order to make the opening width of the trim part corresponding to the corner portion narrower than that of the trim part corresponding to the straight portion, there have been considered countermeasures in which the opening width is made to vary depending upon longitudinal positions of the weather strip (for example, refer to Japanese Patent No. 2750641) and in which clamping or compressing work is applied to the portion where the open deformation of the trim part occurs afterwards.
When varying the opening width partially, however, the manufacturing process becomes complicated and the manufacturing facility also becomes complicated. By this structure, there may be caused a risk that the production costs of weather strips are increased. Moreover, there have existed cases where only narrowing the opening width is not sufficient as the countermeasures against the open deformation of the trim part. In addition, also in a case where the compressing or clamping work is performed afterwards, since a step for the work is added, there exists a risk that the production costs are increased.


A semiconductor device carries out a test utilizing contact with a probe needle without being affected by narrowing of the pitch at which output pads are arranged. The device is equipped with test circuits provided between a plurality of output buffers via which signals are output and output pads corresponding thereto. The test circuit includes output switches caused to sequentially make connections by a controller in test and interpad switches involved in making connections of the output pads with a test pad by the controller in test. In test, probe needles are brought into contact with the test pad. The output pads are not used in test, and can be arranged at a narrowed pitch. Thus, the chip area can be reduced and are therefore so that the pitch for the output pads can be narrowed and the chip area can be decreased.

1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a semiconductor device suitably applicable to an integrated circuit for driving a liquid crystal panel.
2. Description of the Related Art
Integrated circuit chips of manufactured semiconductor devices are tested in various ways. One of the tests is a function test that confirms whether an expected signal is available at an output terminal in response to a given signal applied to an input terminal. Generally, in the function test, connections with all pads used on the chip are made in a certain way.
FIG. 7 shows a conventional manner of testing semiconductor devices. Referring to FIG. 7, a plurality of pads 102 are formed around a circuit formation surface of a semiconductor chip 101. The pads 102 are connected to all terminals used as inputs, output and power supply of circuits formed on the semiconductor chip 101.
The function test of the semiconductor chip 101 is carried out in such a manner that probe needles 103 connected to a test device are contacted to all the pads 102 used. That is, input signals that are output from the test device are input to the pads 102 of the given input terminals of the semiconductor chip 101 via the probe needles 103, and the resultant signals that are output to the given output terminals are sent to the test device via the probe needles 103.
The number of pads 102 on the semiconductor chip 101 increases as the integration progresses. For example, a recent integrated circuit for driving a liquid crystal panel has output terminals as many as 384 outputs. Thus, the pitch of the pads 102 is narrowed and the pitch is now as narrow as 50 μm.
Recently, an increased number of terminals are required as the number of pixels increases due to progress to higher precision of the liquid crystal panel. It is estimated that the integrated circuit for driving the liquid crystal panel further progresses from the 384 outputs and has 480 or 512 outputs. The conventional pad pitch needs an increased chip area and raises the production cost. Therefore, there has been considerable activity in narrowing the pad pitch to thus reduce the chip area so that an increased number of outputs are realized at a low cost. The recent assembly technique goes toward a pad pitch as narrows as 45 μm and further 35 μm.
However, a new problem will arise from the narrowing of the pad pitch. More particularly, a difficulty in contacting pads with the probe needles will be encountered. It will become difficult to correctly make contact the pads with the probe needles due to the narrowing of the pad pitch. The adjacent pads may frequently be short-circuited. Further, it may be difficult to make an adjustment for cancellation of the difference in contact pressure among the pads due to the difference in height so as to have a uniform constant contact pressure on each pad because each of the all pads is contacted with the respective probe needle. The factors mentioned above will reduce the yield in mass production.

Semiconductor device and liquid crystal panel driver device


A voltage reference circuit is provided in the periphery of a memory array. Each subarray of the memory array is associated with a respective voltage driver circuit responsible for generating the cell plate and equilibrate reference voltage for the memory cells in the subarray. The voltage reference circuit is connected to and controls each voltage driver so that each driver generates the proper reference voltage. The distributed circuitry substantially reduces the amount of space used within the memory array while mitigating the problems of prior art voltage generator circuits.

1. Field of the Invention
The present invention relates to the field of semiconductor memory devices and, more particularly to semiconductor memory devices having a distributed cell plate and/or digit line equilibrate voltage generator.
2. Description of the Related Art
FIG. 1 illustrates a portion of a dynamic random access memory (DRAM) device 300. The DRAM 300 includes a plurality of dynamic memory cells 312, a plurality of word lines 314 and a plurality of bit lines 316. For convenience purposes, only two memory cells 312, word lines 314 and bit lines 316 are illustrated in FIG. 1.
The memory cells 312 are organized as an array of columns and rows. Each column typically includes numerous memory cell pairs, such as the single pair illustrated in FIG. 1. Although not illustrated, a typical column may contain 1024 or 2048 pairs of memory cells 312. Each memory cell 312 comprises a storage cell 320 (e.g., a capacitor) and an access device 322, which is typically a metal oxide semiconductor field effect transistor (MOSFET).
Two supply voltages are usually required to operate and access a DRAM cell 312. The first supply voltage is typically a ground and the second supply voltage is typically referred to as Vcc. A first side or cell plate of the storage cell 320 is connected to an intermediate cell plate reference voltage DVC2 having a potential between Vcc and ground. This cell plate reference voltage DVC2 is typically equal to Vcc/2, or the average of the first and second memory cell supply voltages. The cell plate reference voltage DVC2 is produced by a cell plate generator circuit (not shown). The first cell plates of all of the storage cells 320 are typically connected to the cell plate reference voltage DVC2.
A second side of each storage cell 320 is connected to one active terminal of an access device 322. One of the bit lines 316 is connected to the other active terminal of the access device 322. The gate or control terminal of the access device 322 is connected to one of the word lines 314. Thus, each memory cell 312 is connected to a word line 314 and a bit line 316. The word lines 314 and bit lines 316 form a two-dimensional array having a plurality of intersections. A single memory cell 312 corresponds to each intersection. At an intersection, a word line 314 is used to selectively activate the corresponding memory cell 312. Activating the memory cell 312 connects its storage cell 320 to the corresponding bit line 316, which allows conventional memory access operations (e.g., data read, data write and refresh) to occur.
The illustrated DRAM 300 also contains an equilibrate circuit 330. The equilibrate circuit 330 includes two MOSFET transistors 332, 334. One active terminal of each of each transistor 332, 334 is connected to receive the cell plate reference voltage DVC2. The other active terminal of each transistor 332, 334 is connected to one of the adjacent bit lines 316. The equilibrate circuit 330 is responsive to an equilibrate signal EQ to simultaneously connect the reference voltage DVC2 to the bit lines 316. During normal memory access operations, the equilibrate signal EQ is activated to xe2x80x9cprechargexe2x80x9d the bit lines 316 to the reference voltage DVC2 prior to activating the corresponding access transistor 322 and accessing the memory cells 312.
Typically, the first cell plate of each storage cell 320 is maintained at the non-varying cell plate reference voltage DVC2. The second cell plate is charged to either the first memory cell supply voltage or the second memory cell supply voltage, depending on whether a xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d is being written to the cell 320. Data is read from the cells 312 of the DRAM 300 by activating a word line 314 (via a row decoder), which couples all of the memory cells 312 corresponding to that word line 314 to respective bit lines 316, which define the columns of the array. One or more bit lines 316 are also activated. When a particular word line 314 is activated, sense amplifier circuitry connected to a bit line 316 detects and amplifies the data bit transferred from the storage cell 320 to its bit line 316 by measuring the potential difference between the activated bit line 316 and a reference line which may be an inactive bit line. The operation of typical DRAM sense amplifier circuitry is described, for example, in U.S. Pat. Nos.5,627,785; 5,280,205; and 5,042,011, all assigned to Micron Technology Inc., and incorporated by reference herein.
While the DRAM 300 has proven to be a reliable architecture, it is not without its shortcomings. For example, the reference voltage DVC2 is generated by a centralized voltage generator circuit within the array of the DRAM 300. If the array is divided into subarrays, then the DRAM may contain multiple voltage generator circuits. Reference voltage DVC2 lines are then fanned out to the components of the array/subarrays. The voltage generator circuit is relatively large and consumes precious space within the array. There is a desire and need to reduce the amount of space used by the voltage generator circuitry in the array of the DRAM 300.
In addition, the reference voltage DVC2 generated by the voltage generator circuit may swell or experience dips in different portions of the DRAM 300. That is, different sections of the memory array will have different voltage levels. This adversely effects the operation of the standard DRAM functions such as reads, writes and precharging. Accordingly, there is a desire and need to reduce the amount of reference voltage swells and dips experienced in today""s DRAM arrays.
Another problem experienced by the conventional DRAM 300 is bit line coupling. With the current DRAM configuration, the cell plates of the storage cells 320 move, which couples noise onto the bit lines 316. If there is too much movement, there will be too much noise on the bit lines 316. Bit line coupling creates memory cell margin problems, and are a direct result of the current centralized voltage generator techniques. Accordingly, there is a desire and need for a DRAM having a voltage generator circuit that reduces bit line coupling within its arrays.
The present invention provides voltage generator circuitry that substantially reduces the amount of reference voltage swells and dips in a DRAM memory array.
The present invention further provides voltage generator circuitry that substantially reduces bit line coupling within a DRAM memory array.
The above and other features and advantages of the invention are achieved by providing a voltage reference circuit in the periphery of a memory array. Each subarray of the memory array is associated with a respective voltage driver circuit responsible for generating the cell plate and equilibrate reference voltage for the memory cells in the subarray. The voltage reference circuit is connected to and controls each voltage driver so that each driver generates the proper reference voltage. The distributed circuitry substantially reduces the amount of space used within the memory array while mitigating the problems of prior art voltage generator circuits.

Distributed cell plate and/or digit equilibrate voltage generator


Disclosed herein is a novel chimeric antigen receptor and use thereof. The novel chimeric antigen receptor consists of a signal peptide, an antigen binding domain, a transmembrane region, and an intracellular signal domain, and comprises a 4-1BB signal peptide and/or a 4-1BB molecular transmembrane region. Nucleic acid sequences of various chimeric antigen receptors are separated and purified and provided is a chimeric antigen receptor and a CAR-T cell which are specific for a CD19 malignant tumor antigen. In the malignant tumor killing test of hematological cell lines, the ability of immune cells to target and recognize tumor cells is significantly enhanced, and the killing activity against tumor cells is also enhanced.

According to the 2015 Global Cancer Statistics, data showed that in 2012, there were 14.1 million new tumor patients and 8.2 million patients died worldwide. According to the Chinese Cancer Registry, data showed that in 2015, there were 4.3 million new cancer cases in China, and more than 2.81 million cancer patients died, accounting for 28.82% of the total number of deaths in the year, that is, an average of more than 7,500 people died of cancer every day, which was ranked number one in the world.
Traditional tumor treatment means mainly comprise surgery, radiotherapy, chemotherapy, and stem cell transplant arising in recent years. These treatment means often cure the symptoms, not the underlying problems. With the development of science, immunotherapy of tumor has achieved a great breakthrough in recent years, which mainly comprises immunological checkpoint inhibitors (such as anti-PD1 monoclonal antibody), and chimeric antigen receptor modified T cell therapy (CAR-T) with the best clinical effect. In recent years, CAR-T technology has made encouraging progresses in clinical trials of hematologic disease treatment, and was ranked as number one of top ten scientific breakthroughs in 2013 by Science magazine. Since the CAR1 June group in University of Pennsylvania firstly reported in 2013 that the child (Emily Whitehead) suffering from the acute B lymphoblastic leukemia who was treated with the targeted CD19 CAR-T was completely relieved, the CAR-T cell immunotherapy had rapidly developed in just a few years. Currently, CAR-T cell treatment is the most effective cell immunotherapy with the highest targeting ability. After the evolution of technology, CAR-T has become more sensitive and more immune persistent, and has a miraculous effect on hematologic tumors such as lymphoma. At present, a number of cell treatment methods have been awarded the "breakthrough therapy" qualification by the FDA. Among them, the results of a number of clinical trials have shown that the clinical complete remission rate of CD19 CAR-T treatment of B-cell lymphoma has exceeded 90%.
CAR-T cells are a class of T cells that can be genetically engineered to express CAR recognizing particular antigens on the T cell surface and transmit signals. Generally, CAR-T cells recognize specific molecules on the tumor cell surface via a chimeric antigen receptor (CAR) in an antigen-antibody or ligand-receptor recognition mode, and then are activated and proliferated and exert cell killing function through the intracellular signal transduction. The chimeric antigen receptor modified T cells can specifically recognize tumor-associated antigens, making the targeting ability, killing activity and persistence of effector T cells higher than those of conventionally used immune cells, and can overcome local immunosuppression microenvironment of tumors and break the host's immune tolerance state.
The modified T cells express such a class of chimeric antigen receptor molecules composed of: an extracellular segment generally comprising a CD8α or GM-CSFRα signal peptide, an antigen recognition region, or an antigen binding domain comprising a single chain variable region consisting of heavy chain and light chain variable regions of an antibody; an intracellular segment which is an intracellular chimera of various signalling molecules including CD28, 4-1BB, OX-40, CD3zeta, etc.; and a transmembrane region which is derived from other molecules, such as PD1, CD8, CD4, CD28, CD3zeta (CD3ζ), etc. The non-antigen recognition region of the extracellular segment of CAR comprises a signal peptide and a hinge region (a linking region between the scFv and the transmembrane region, also referred to as a spacer domain), and has an important influence on the function of the CAR. Kober L et al. in Germany reported that the expression level of a bi-specific single chain antibody (bi-specific scFv antibody) can be significantly increased by optimizing the signal peptide sequence pair from different sources, which is closely related to the ability of the signal peptide to guide the protein into the secretory pathway (Biotechnol Bioeng. 2013 April; 110(4): 1164-73). Michael Hudecek et al. in the Fred Hutchinson Cancer Research Center in the United States reported that although the CAR using an inappropriate spacer domain has a good tumor cell killing effect in in vitro experiments, the CAR-T cells undergo activation-induced T cell death in vivo due to the binding of the spacer domain to the Fc receptor, resulting in the inability of such CAR constructs to persist in vivo and loss of anti-tumor activity (Cancer Immunol Res; 3(2); 125-35). In the international application WO 2016/014789 A2, without changing the extracellular antigen recognition region and the intracellular signal region, the performance of the CAR vector can be greatly realized by only changing the sequence of the transmembrane region, and the non-specific killing effect of the CAR-T on the non-target cells is reduced. Currently, in the field of CAR-T, compared with the CD28 intracellular signal domain, the CAR structure containing a 4-1BB intracellular signal domain is considered to have better tumor cell killing activity and persistence in vivo.
In the field of B cell leukemia, CD19 is expressed on the surfaces of almostly all the B cell tumor cells, but is hardly expressed in other parenchymal cells and hematopoietic stem cells. CD19 is a relatively specific B-line tumor antigen target. The CD19 CAR structure that has achieved a significant clinical progress at present is CD8α signal peptide-anti-CD19 single chain antibody-CD8α hinge region & transmembrane region-4-1BB intracellular region-CD3ζ intracellular region (CD8α signal peptide-antiCD19scFv-CD8α Hinge&TM-4-1BBcyto-CD3ζ).
Human 4-1BB molecule (NCBI database protein number NP_001552.2), also known as CD137, or tumor necrosis factor receptor superfamily member 9 (TNFRSF9), has amino acids 1-23 as a signal peptide, amino acids 24-186 as an extracellular region, amino acids 187-213 as a transmembrane region, and amino acids 214-255 as an intracellular region in its primary structure. At present, there is no report that designs a CAR using the basic structure of 4-1BB.
The present invention provides a novel CAR structure comprising a 4-1BB signal peptide and/or a 4-1BB transmembrane region structure, for example, a 4-1BB signal peptide-tumor antigen recognition binding region-4-1BB transmembrane region-4-1BB intracellular region-CD3zeta intracellular region (4-1BB signal peptide-VH-Linker-VL/VHH-4-1BB TM-4-1BBcyto-CD3ζ), which maximizes the use of the amino acid sequence of 4-1BB. The use of the 4-1BB signal peptide, and the transmembrane region and intracellular region of 4-1BB facilitates the optimization of the extension of the extracellular tumor antigen recognition binding region on CAR-T cells, which not only achieves good tumor killing effects in vitro and in vivo, but also achieves complete remission in the clinical treatment of patients with acute lymphoma, with a milder cytokine release response.

Chimeric antigen receptor and use thereof


A silicon carbide sintered body according to the present invention is a silicon carbide sintered body having a density of 2.9 g/cm.sup.3 or higher, obtained by means of hot pressing a mixture of silicon carbide powder and a non-metal-based sintering additive such as an organic compound which produces carbon upon heating at a temperature of 2,000.degree. C. to 2,400.degree. C. and under a pressure of 300 to 700 kgf/cm.sup.2 in a non-oxidizing atmosphere. It is preferable that the silicon carbide powder have an average particle diameter of from 0.01 to 10 .mu.m and that the non-metal sintering additive be a resol type phenol resin. The present invention is to provide a silicon carbide sintered body of high quality which has a high density, a high purity, and a high electrical conductivity and which is useful for semiconductor manufacturing industry.

1. Field of the Invention
The present invention relates to a silicon carbide sintered body and a process for making the same and, more particularly, to a silicon carbide sintered body having a high density useful for structural parts and components of semiconductor manufacturing equipment, electronic information equipment, vacuum devices, and the like.
2. Description of the Related Art
Silicon carbide is a highly covalent material and has found various applications taking advantage of its properties of, for example, strength at a high-temperature, heat resistance, wear resistance and chemical resistance. Recently, there have been demands in the fields of materials for electrical information equipment and semiconductor manufacturing toward a high heat-resistance, and a highly dense and highly pure silicon carbide sintered body without heat distortion and due to heat deterioration when washed with chemicals such as hydrofluoric acid, as in conventional parts and components made of quartz with increase in wafer processing temperature, wafer diameter, and processing unit.
As mentioned above, the silicon carbide is highly covalent and is thus difficult to sinter. Dense silicon carbide sintered bodies are known to be produced by means of hot pressing, reaction sintering, and atmospheric sintering.
The hot pressing is a method in which silicon carbide is sintered under a high pressure and has been studied with a variety of metal sintering additives after this technique was reported (J. Am. Ceram. Soc., 39(11), 386-389 (1956)) with aluminum added as a metal sintering additive. A highly conductive and electrically insulating sintered body was developed in 1980 that was sintered by the hot pressing by adding BeO("Silicon Carbide Ceramics", pages 327-343 published by Uchida Rokakuho (1988)).
The reaction sintering involves in the following steps of: (1) mixing raw materials (i.e., mixing silicon carbide powder and carbon powder), (2) molding fabricating, (3) reaction sintering, and (4) post-processing, if necessary. This technique involves silicification of the carbon particles which have already been molded in the reaction sintering step (3) above, which provides an advantage of allowing sintered bodies of less variation in dimension without any sintering additives. Accordingly, this technique provides an easier operation to produce a sintered body of a higher purity and has been used for production of parts and components for semiconductors. However, the sintered bodies obtained by means of this technique contains non-reacted metal silicon so that their applications are restricted when parts and jigs are used in the fields where the heat resistance, the chemical resistance and a high strength are required.
The atmospheric sintering process is a technique characterized by using sintering additives for sintering the silicon carbide and was proposed by S. Prochazka in "Ceramics for High Performance Applications" in 1974, on page 239. This technique allows production of a high dense structural member having a high strength at a high temperature. As a result, studies of the silicon carbide have been developed. The sintering additive used is a combination of a metal-based sintering additive comprising a metal such as boron, aluminum and beryllium or a compound thereof and a carbon-based sintering additive such as carbon black and graphite. The metal-based sintering additive has essential effects of, for example, reduction of surface energy at a grain boundary due to local deposit of boron onto the boundary, enhancement of diffusion of carbon-boron substances on the grain boundary, and suppression of surface diffusion thereof, for the boron which is used as the optimum sintering additive. The carbon-based sintering additive is considered to have an effect of removing an oxide layer on the surface of silicon carbide particles. Details, however, have still remained unknown.
Metal contaminants are eluded when the metal-based sintering additive used is exposed to a high temperature or is subjected to washing with chemicals. The resultant sintered bodies are thus not suitable for the application to the areas of the semiconductor manufacturing equipment.
In order to overcome the above mentioned problems, Japanese Patent Application Laid-Open (JP-A) No. 60-108370 proposes a process for making a dense sintered body by hot press process without adding a sintering additive, using a special ultra-fine powder of silicon carbide obtained through heat decomposition of a silane compound. However, there is no clear description on properties of the resultant sintered bodies. In this connection, "Silicon Carbide Ceramics", published by Uchida Rokakuho, in 1988, on page 89, describes that it is essential to add boron as a metal-based sintering additive even by using the powder obtained according to this technique.
As an improved hot pressing, Japanese Patent Application Laid-Open (JP-A) No. 2-199064 proposes a process for making a dense sintered body without any additives by the hot press method, using ultra-fine silicon carbide powder synthesized by means of CVD plasma technique. However, impurities such as iron are contained in an amount of several ppm or more even in the process described in this application. This is not a satisfactory level of impurities. The ultra-fine silicon carbide powder used for this system as the sintering additive has an average particle diameter of 30 nm. Such ultra-fine powder is relatively expensive and should be treated with significant care for preventing oxidation on the surface thereof. In light of the above, the process disclosed in the above application is far from a solution to the problems to date.
It is difficult for the conventional processes to obtain a high dense silicon carbide sintered body, containing less or no impurities, which is suitable for being used for parts and components of semiconductor manufacturing equipment and electronic information equipment. Furthermore, there is no such a sintered body available on the market.

Process for making a silicon carbide sintered body


A filter has a longitudinal axis with an inner diameter defined by a hollow longitudinally extending center. The filter has fingers extend radially outwardly arcuately from the longitudinal axis. The fingers have base ends near the longitudinal axis and outer edges at extremities spaced from the longitudinal axis. The outer diameter of the filter is defined by the outer edges of the fingers. The filter is formed from a sintered porous molded thermoplastic or another material resulting in a filter more rigid than standard filters. The fingers are spaced apart from one another a predetermined, substantially fixed distance to form slots therebetween sized to capture contaminants therein.

Filters for fluids (liquids and gases) have been known in the art. For instance, filters are commonly used in such systems as air filtration systems, water filtration systems, water purification systems, etc. One particular application of filters is in recreational waters, such as pools and spas.
At least two types of filters are known. The first type of filter is a cartridge-type filter with a replaceable filter typically mounted on a core and placed in the filtration system. The replaceable filter is typically formed from a porous, relatively soft material having pores sized to prevent contaminants and/or other particles (hereinafter "contaminants" for the sake of convenience, without intent to limit) from flowing through the filtration system, while letting the fluid pass therethrough. However, contaminants and particles typically become embedded in such filters such that the filters must be replaced on a regular basis.
The second type of filter is a Diatomaceous Earth ("DE") filter having a support grid resembling a nylon mesh on which a powder is deposited. The powder forms a uniform cake-like structure that performs the filtration operation. However, the support grid is relatively fragile and has a limited life. Moreover, such a support grid system assembly is complex and thus relatively difficult to assemble.
Typically, cartridge-type filters are cylindrical elements having a substantially open longitudinal center portion with radially-outwardly extending, longitudinal folded portions or pleats. A plurality of pleats are commonly arranged around a tubular core defining a cylinder. When viewed in a transverse cross-section, the pleats typically extend radially outward from the core toward the outer periphery of the filter. Conventional pleats extend in a straight manner from the inner diameter of the filter (the core) toward the outer diameter (the periphery) of the filter. A drawback of the straight pleat is that, because the filter industry has become standardized, the overall dimensions of the filter body are restricted and a straight pleat cannot be increased in size beyond the dimension of the filter body. Thus the filter capacity and effectiveness are limited.
Because the effectiveness of the standard cartridge-type filter is generally a function of the surface area of the filter, pleats have been modified to extend from the center core toward the periphery in an arched manner. Thus, the effective length of each pleat between an inner diameter and outer diameter can be increased. The increase in the length of each pleat results in an increased surface area of the filter.
In standard cartridge-type filters, to increase the effectiveness of a typical filter, the volume of empty space within the filter body has traditionally been targeted as wasted space. Attempts have been made to approach filling 100% of the volume of the filter body, between the open center core and the periphery, with filter material. Furthermore, the curvature of each pleat between an ascending and descending arm of the pleat has been modified to decrease empty volume at the distal and proximal ends of each respective pleat. The pleats were also designed to contact one another such that minimal empty volume exists between two adjacent pleats. Adjacent pleats often lie directly on neighboring pleats such that adjacent pleats are in intimate contact with each other. The curvature of pleats is typically modified such that the empty volume of the overall filter is reduced to nearly zero.
However, several drawbacks of the traditional system exist. Because the pleats are in intimate contact, any large particles that enter the filter have no particular position in which to become positioned or trapped. The large particles therefore become lodged in unpredicted and unwanted positions and can create dead spaces, disrupting proper functioning of the filter. Furthermore, because the pleats are in intimate contact, any contaminants that enter the filter become lodged within the inter-pleat space and are not fully removable. Therefore, the filter is not entirely cleanable and has a very limited reusable life. The filter also cannot be washed, brushed aggressively, or backwashed at high pressure because of its relative fragility. Therefore, the filter must be disposed of when it becomes contaminated.
Porex Porous Products Group, Fairburn, Ga. has improved upon the above filters by forming a molded filter element, preferably formed from a sintered porous plastic. The sintered porous plastic material used to form these filters provides a more durable composition and therefore permits the filter to be more effectively cleaned and reused over a longer period of time. For instance, the sintered porous plastic permits the filter to be repeatedly backwashed and cleaned. Backwashing is where a clean fluid is flown in a reverse direction from the normal direction of flow across a filter. The reverse flow dislodges particles that were previously trapped by the filter, thereby cleaning the filter for later use. Additionally, the sintered porous plastic is predominately uniform in composition and therefore the filter flow is not direction specific. A substance to be filtered can flow from the outside in as well as from the inside out.
Furthermore, because the sintered porous plastic filter is more rigid than the first type of filter described above, the Porex filters do not require a central core or an outer cage to provide a specific form and structure. The sintered porous plastic is capable of being formed into a shape and structure independent of employing a central core and outer cage. Moreover, molding permits the filter to be formed as a single piece, thus minimizing parts and simplifying manufacture as well as assembly.
Yet another benefit of the sintered porous plastic is that the pore size can be modified as desired. The pore size of the sintered material is dependent on the size and shape of the initial starting particles prior to sintering. Adjusting and determining the pore size based on the starting particle size and shape is described in U.S. Pat. No. 6,551,608 issued to Yao; U.S. Published Application No. U.S. 2003-0062311-A1; and U.S. Pending Application Ser. No. 09/375,383, each of which is incorporated herein by reference in its entirety.
It would therefore be desirable to form a filter that has a uniform surface for removing contaminants of multiple sizes, an increased filtering capacity, and an effective service life. It would further be desirable to form a filter having an increased capacity to capture contaminants and to form the filter so that it may be backwashed to clean off the contaminants so that the filter may be reused. Also, the surface preferably would be configured to retain the contaminants thereon, without creating dead spaces and blocking proper filter functioning.


A counter device having a jumping function includes a counter circuit for counting clock pulses, a circuit for setting a jump starting count, a circuit for setting the number of bits to be jumped, a detecting circuit for detecting equality/unequality between a count of the counter circuit and the jump starting count as set, and a circuit for modifying the count of the counter circuit by the number of bits to be jumped in response to equality detection by the detecting circuit. The modifying circuit varies the count in the same direction as a direction of variation of the count provided by the counter circuit. This construction realizes a counting function which jumps a desired count or counts from a selected count.

1. Field of the Invention
This invention relates to a counter device for counting clock pulses and to a method of driving the counter device. More particularly, the invention relates to an asynchronous binary counter and a method of operating the same, and a memory device with the counter embedded therein and operating method thereof
2. Description of the Background Art
Counter devices are used in various fields. Certain types of counter devices are used as timers, with a count thereof corresponding to a period of time, to generate a control signal for actuating or stopping a particular component at every predetermined counts.
In a certain system, a plurality of components are affixed with numbers, and a counter device is used for successively actuating the components according to the numbering. In this construction, a component of a number corresponding to a count of the counter device is actuated.
In a serially accessible memory device, word lines (rows) or bit lines (columns) are successively selected. A counter device called a program counter (or an address counter) is used to generate an address for designating a word line or a bit line to be selected. In this construction, the counter device successively increments or decrements its count in response to a control signal, and the count is used as an address for designating a word line or a bit line.
FIG. 1 is a view showing one example of conventional asynchronous binary counters, which is exemplified in "Principle of CMOS VLSI Design - A Systems Perspective" by Neil Weste et al, FIG. 8.25 on pages 335-336, published 1985, by Addison-Wesley Publishing Company.
Referring to FIG. 1, a conventional asynchronous binary counter 7 is a one-bit counter including a first-stage latch block 71 and a second-stage latch block 72. The first-stage latch block 71 includes transmission gates 6a and 6b which turn on and off in response to two phase non-overlapping, or complementary clock signals .phi., .phi. applied through inputs C, C, and inverters 8a and 8b for inverting signals applied thereto. In response to the clock signals .phi., .phi., the transmission gate 6a passes an output Q generated from the second-stage latch block 72. The transmission gate 6b, in response to the clock signals .phi., .phi., connects an input of the inverter 8a and an output of the inverter 8b. The inverter 8a inverts a signal received from the transmission gate 6a. The inverter 8b inverts a signal received from the inverter 8a.
Generally, a transmission gate has a construction in which the sources and the drains of an n-channel MOS (insulated gate field effect) transistor and a p-type MOS transistor are interconnected. The clock signals applied to control terminals of the transmission gates 6a and 6b have different phases, so that the transmission gates 6a and 6b turn on and off in a complementary manner.
Similarly, the second-stage latch block 72 includes transmission gates 6c and 6d, and two inverters 8a and 8b connected in series. The inverter 8c outputs the signal Q, and the inverter 8d outputs a signal Q. The transmission gate 6c operates synchronously with the transmission gate 6b, while the transmission gate 6d with the transmission gate 6a.
The latch block 71 is in a through state when the clock signal .phi. is "H", a latching state when the clock signal .phi. is "L". The latch block 72 is in a through state when the clock signal .phi. is "L", and in a latching state when the clock signal .phi. is "H". The latching state is a state for continuously outputting an immediately preceding input signal regardless of a current input signal, whereas the through state is a state for just passing an input signal therethrough as an output.
The binary counter shown in FIG. 1 is a one-bit counter, and in practical use, normally, a plurality of such one-bit binary counters 7 are connected in series as shown in FIG. 2. FIG. 2 shows a construction for implementing an n+1-bit binary counter with n+1 one-bit binary counters 7a-7n connected in series.
In the asynchronous counter shown in FIG. 2, input signals (count inputs, i.e. clock signals .phi., .phi.) are applied only to the counter of the least significant bit. Each of the remaining counters receives outputs Q, Q of a counter of the lower bit at count inputs C, C. More particularly, referring to FIG. 1, a higher bit counter receives outputs Q, Q of a lower bit counter instead of the clock signals .phi., .phi.. In such a counter, each counter excluding a first stage receives an output of a preceding counter stage as a clock signal. Clock signals to be count are applied only to the first counter stage. Such a counter is called an asynchronous counter or a ripple counter. An operation will be described next with reference to FIG. 3. FIG. 3 is a diagram showing operational waveforms of 3-bit binary counters 7a-7c (FIG. 2), i.e. three of the counter in FIG. 1 connected in a 3stage series.
It is assumed that, in an initial state prior to application of the clock signals .phi., .phi., counter outputs Q0, Q1 and Q2 are all maintained in "L" level (logical "038 ).
The counter 7a at the first stage operates as follows. When the clock signal .phi. rises to "H" (logical "1"), the transmission gate 6a turns on to transmit an "L" signal (output Q) to the first-stage latch block 71. The transmission gates 6b and 6c remain in an off state
When the clock signal .phi. falls from "H" to "L", the transmission gate 6a turns off and the transmission gate 6b on, thereby establishing data "L" in the first-stage latch block 71 owing to its latching function. Simultaneously, the established data "L" is transmitted from the first-stage latch block 71 to the second-stage latch block 72 through the transmission gate 6c. As a result, output Q0 of the first-stage counter 7 becomes "H", and output Q0 is "L".
When the clock signal .phi. rises to "H" again, the transmission gate 6c in the second-stage latch block 72 turns off, and the transmission gate 6d turns on, thereby establishing data in the second-stage latch block 72, i.e. output data Q0 and Q0. The established output data Q0 in "H" level is transmitted to the first-stage latch block 71, and through the transmission gate 6a in the ON state to the inverter 8a.
When the clock signal .phi. falls from "H" to "L" again, the transmission gate 6b in the ON state forms a latch circuit in the first-stage latch block 71, thereby establishing data "H" in the first-stage latch block 71. Simultaneously, this data "H" is transmitted through the transmission gate 6c in the ON state to the inverter 8c in the second-stage latch block 72. As a result, output Q0 becomes "L" and output Q0 "H".
By repeating this operation, the state of output Q0 of the first counter 7a changes each time the clock signal .phi. falls from "H" to "L". Output Q0 falls from "H" to "L" at every second fall of the clock signal .phi.. Thus, a onebit counter having counts "0" and "1" is realized.
The counter 7b at the second stage receives outputs Q0, Q0 of the first counter 7a at the count inputs C, C.
Consequently, the second counter 7b is operable by using output Q0 as its clock signal instead of the clock signal .phi. used in the first counter 7a. Thus, the state of output Q1 of the second counter 7b changes each time the output Q0 of the first counter 7a falls from "H" to "L". That is, output Q1 falls from "H" to "L" at every second fall of output Q0 of the first counter 7a and, therefore, returns to an initial state at every four counts of the clock signal .phi..
The counter 7c at the third stage receives outputs Q1, Q1 of the second counter 7b as count inputs. Thus, the state of output Q2 of the third counter 7c changes each time the output Q1 of the second counter 7b falls from "H" to "L". The third counter 7c operates in a period twice that of the second counter 7b and, therefore, returns to an initial state at every eight counts of the clock signal .phi..
Where, as described above, three counters 7a-7c are connected in series, a binary counter for counting up clock signals .phi. and providing counts in binary notation is realized by using output Q2 as the most significant bit and output Q0 as the least significant bit.
Similarly, a count-down binary counter is obtained by using outputs Q of respective counter stages.
The conventional binary counter is constructed as described above, which receives clock pulses as count inputs and provides counts in binary notation. Since this binary counter continuously outputs counts, such counter may be used in the field of sequence control, for example, in which a plurality of components are successively actuated according to the above counts.
However, the conventional counter has a limited application since its output is successively incremented or decremented one by one, the counter being unable to jump certain predetermined counts.
Assume, for example, that counts 0-5 (decimal numbers) of the counter are used as signals to determine timing for actuating components of system A, counts 6-10 (decimal numbers) for actuating components of system B and counts 11-15 (decimal numbers) for actuating components of system C. Each component is in one-to-one relationship with a count of the counter.
Where the components of systems A, B and C are actuated successively, sequence control may be effected by using the counter. However, the conventional counter cannot be used as a timing generator or a component selecting signal generator for a control system which successively actuates the components of systems A, B and C under certain conditions but successively actuates only those of systems A and C under others.
To cope with such a situation, possible consideration is to provide counters for the respective systems A, B and C and switch from one counter to another. However, this would require a control device for the switching, resulting in a large and complicated counter device. Even if such devices were used, components to be maintained inactive would be determined in a fixed manner by a timer, which makes it impossible to obtain a flexible control system configuration allowing variable the components to be maintained inactive.
A serially accessible memory such as a field or frame memory is used in the field of image processing. In such a memory, a counter device such as a program counter is used as an address generator to generate a row or column designating signal for selecting a word line or a bit line. The following problem arises in such a memory. Assume a screen split up into three image areas A, B and C. The screen may be split up vertically or horizontally, and here it is assumed that the screen is split up vertically into three parts as shown in FIG. 4. In the case of a field memory or a plane memory in FIG. 4, the word lines WL correspond to horizontal scan lines on the screen, and are successively selected in accordance with counter outputs.
In a field memory of FIG. 4, pixels on the screen are generally corresponding in one-to-one mapping relation to the bits (memory cells) in a memory cell array 950. A counter/decoder 951 selects a word line WL from a memory cell array 950 in response to a clock signal .phi.c. In other words, the counts of the counter are used as row addresses. If, in the course of image editing, it is desired to process data by reading the data for the image areas A and C only, omitting the image area B, it is necessary to apply word line designating signals from outside since the conventional counter cannot be used as an address generator in such a case, which makes a high-speed word line selection impossible. More specifically, the counter/driver 951 can not jump-from a word line WLa of the last word line in the area A to a word line WLb of the first word line in the area C in one clock cycle.
If the counter/decoder 951 is employed to jump the area A (word line WLa) to the area C (word line WLb), it is required to disable the data read/write operation of the memory device while the clock signal .phi.c is applied to the counter/decoder successively by a certain number of times to set an output of the counter/decoder corresponding to the word line WLb. This scheme degrades data processing performance.
When, during a data writing operation, it is desired to update the data for the image areas A and C, leaving the data for the image area B unchanged, the same problem arises since the conventional counter cannot be used as a row address generator. Also where the screen is split up horizontally, the same problem arises if a counter is used for generating bit line selecting addresses.
In the absence of the count jumping function, i.e. a function to jump from one count to another, as described above, the conventional counter has the disadvantage of having a limited application in that it cannot be used for applications requiring such count jumping actions.
As described above, where an address counter only operates in response to a clock signal and it is not provided with a jumping function, a memory device with such an address counter may only employable as a buffer memory.
In image data processor, such a buffer memory is frequently employed. A typical use of such a buffer memory on an image data processor is shown in FIG. 5.
FIG. 5 is a block diagram of an interframe comparison type comb filter. Referring to FIG. 5, a frame buffer 910 receives a composite video signal, and delays received composite video signal by one frame period. The frame buffer 910 is a first-in, first-out memory, and serves as a one frame delay element.
An adder 911 receives current composite video signal at its positive input and an output of the frame buffer 910 at its negative input. The adder 911 serves as a subtractor for subtracting, from current video signal, video signal preceding by one frame period to the current video signal.
An amplifier 912 has an amplification rate of 1/2 and serves as a divider by a factor of 2.
A bandpass filter 913 passes only a desired frequency components from received signal from the amplifier 912. The bandpass filter 913 has a pass band of 3.58 MHz and produce a chrominance signal C.
An adder 914 receives an output of the bandpass filter 913 at its negative input and the current video data at its positive input. The adder 914 serves as a subtractor for subtracting the output of the bandpass filter 913 or a chrominance signal from current composite video signal to produce a luminance signal.
FIG. 6 shows schematically an overall structure of a FIFO type memory device. The memory device can perform asynchronously data read operation and data write operation.
Referring to FIG. 6, the FIFO type memory device includes a memory cell array 801 having a plurality of memory cells arranged in rows and columns, and a row decoder 802 for decoding a row address received from a selection control unit 804 to select a corresponding row in the memory cell array 801. The selection control circuit 804 passes either of outputs of a read row address counter 806 and a write row address counter 808.
The read row address counter 806 increments its count by 1 in response to a first read clock signal .phi.R1 from a read-out clock generator 810. The read-out clock generator 810 generates the first clock .phi.R1 and a second read clock signal .phi.R2 in response to externally applied read enable signal RE and read control signal .phi.R.
The read-out clock generator 810 gates the read clock signal .phi.R to generate the second read clock signal .phi.R2, and also generates the first read clock signal .phi.R1 when the read clock .phi.R is applied thereto by the times of the number of columns of the array 801.
The write row address counter 808 increments its count by 1 in response to the reception of a first write clock signal .phi.W1 from a write-in clock generator 812 which in turn generates the first write clock signal .phi.W1 and a second write clock signal .phi.W2 in response to externally applied write enable signal WE and write control signal .phi.W.
The second write clock signal .phi.W2 is generated by gating the write clock signal .phi.W by the write enable signal WE. The first write clock signal .phi.W1 is generated when the second write control signal .phi.W2 is generated by the times of the number of the columns in the array 801.
The memory device of FIG. 6 also includes a serial read counter 814 for generating a column select signal in response to the second read clock signal .phi.R2, a read-out buffer 816 for storing data of one row of the array 801, and an output buffer 818 for receiving data from the read-out buffer 816 to produce an external read-out data Dout. The serial read counter 814 includes a read column address counter 834 for counting the second read clock signal .phi.R2 to generate a read column address, and a read decoder 832 for decoding a read column address from the read column address counter 834 to generate a column select signal.
The read-out buffer 816 includes a plurality of storage elements corresponding in number and position to the columns of the array 801 and connects sequentially the storage elements to the output buffer 818 in response to the column select signal from the read decoder 832.
The memory device further includes a serial write counter 820 for generating a write column select signal in response to the second write clock signal .phi.W2, and a write-in buffer 822 for storing write-in data of one row to the array 801 received from an input buffer 824. The input buffer 824 produces write-in data from externally applied write-in data. The write-in buffer 822 includes a plurality of storage elements corresponding in number and position to the columns of the array 801. The write-in buffer 822 connects sequentially the storage elements therein to the input buffer 824 in response to the column select signal received from the serial write-in counter 820.
The serial write-in counter 820 includes a write column address counter 838 for counting the second write-in clock signal .phi.W2 to generate a write column address, and a write decoder 836 for decoding a write column address from the write column address counter 838 to generate a write column select signal.
The selection control circuit 804 arbitrates between a read row selection and a write row selection, controls sensing operation in the array 801, and also controls the data transfer between the array 801 and the read-out buffer 816 and between the array 801 and the write-in buffer 822. Now operation of the memory device will be briefly described.
In data writing operation, the write enable signal WE is brought into an active state. The write-in clock generator 812 is made active in response to the activated write enable signal WE to generate the first and second write clock signals .phi.W1 and .phi.W2. The write column address counter 838 counts the second write clock signal .phi.W2, and supplies its count to the write decoder 836 as a write column address. A storage element in the write-in buffer 822 selected by the write decoder 836, or designated by a write column address from the decoder 836, is connected to the input buffer 824 to receive and store write-in data.
The write-in clock generator 812 generates the first write clock signal .phi.W1 at an appropriate timing in response to the write clock .phi.W. The write-row address counter 808 generates a write row address in response to the first write control signal .phi.W1. The selection control unit 804 detects the transition of the output of the write-row address counter 808 to pass the write row address from the counter 808 to the-row decoder 802. The row decoder 802 selects in the array 801 a row corresponding to the received row address. When the write-in buffer 122 receives and stores one row amount of data, the selection control unit 804 connects the write-in buffer 822 and the array 801, so that data in the write-in buffer 822 are transferred in parallel to memory cells on the selected row in the array 801.
In data reading operation, the read enable signal RE is brought into an active state to activate the read-out clock generator 810. The first read clock signal .phi.R1 is generated from the read-out clock generator 810 to be applied to the read-row address counter 806. The read-row address counter 806 increments its count by 1 every receipt of the first read clock signal .phi.R1. When the selection control unit 804 detects the transition of the count of the counter 806, it passes through the output or the count of the read-row address counter 806 to provide the same to the row decoder 802 as a read row address. The row decoder 802 selects a row corresponding to thus received row address from the counter 806 in the array 801.
After selection of the row and assertion of data potential on each column, the array 801 is connected to the read-out buffer 816 under the control of the selection control unit 804, so that data of a selected row in the array 801 are transferred from the array 801 to the read-out buffer 816.
Then, the read-out clock generator 810 generates the second read clock signal .phi.R2 to provide the same to the read column address counter 834. The read column address counter 834 increments its count by 1 every receipt of the second read clock signal .phi.R2, and provides its count to the read decoder 832 as a read column address. The read decoder 832 connects sequentially the storage elements of the read-out buffer 816 to the output buffer 818 in response to received read column addresses.
When the read enable signal RE and the write enable signal WE are both active, the selection control unit 804 arbitrates between read row selecting operation and write row selecting operation. In general, read row selecting operation is first performed and then write row selecting operation is performed in one clock cycle if the clock signals .phi.R1 and .phi.W1 are synchronized with each other. If the clock signals .phi.R1 and .phi.W1 are asynchronous with each other, the selection control unit 804 selects first a row address generated earlier. The selection control unit 804 also monitors a read row address and a write row address to prevent the read row address from being in advance of the write row address.
With such a FIFO type memory device, video data of raster scan system can be processed at a fast rate. When the read clock .phi.R and the write clock .phi.W are synchronous with each other, the memory device serves as a delay element such as a field delay element or a frame delay element.
In such a memory device used in video application, data sequence in data reading operation should be made the same as that in data writing operation. Thus, a conventional redundancy scheme cannot be employed for repairing a defective memory cell (a defective bit).
FIG. 7 shows a structure of a memory device with a conventional redundancy scheme. In FIG. 7, only circuitry related to defective row repairing is shown. Referring to FIG. 7, a row decoder RD and a spare row decoder correspond to the row decoder 802 shown in FIG. 6, and a row address counter RAD corresponds to the read-row address counter 806 or the write-row address counter 808 shown in FIG. 6. The memory cell array 801 of FIG. 6 includes a memory cell array MA and a redundant array MR of FIG. 7. The redundant array MR includes one or more redundant word lines for repairing a defective word line having a defective memory cell in the memory cell array MA.
The spare row decoder SRD stores a defective row address indicating a defective row in the memory cell array MA. The programming of the defective row address is performed by blowing off one or more fuse elements provided in the spare row decoder SRD with a laser beam, for example.
The output of the row address counter RAD is supplied both to the row decoder RD and to the spare row decoder SRD. When a row address from the counter RAD designates a normal row in the array MA, the row decoder RD decodes the received row address to select a corresponding row in the array MA. The spare row decoder SRD does not generate an active signal (redundant row selecting signal), and no redundant word line is selected in the redundant array MR.
If a row address from the row address counter RAD designates the defective row in the memory cell array MA, the spare row decoder SRD generates a redundant row selecting signal to select a corresponding redundant row in the redundant array MR because the row address from the row address counter RAD coincides with the stored defective row address in the spare row decoder SRD. The spare row decoder SRD also generates a normal element disable signal NED to deactivate the row decoder RD for inhibiting row selection in the memory cell array MA. In other words, the row decoder RD performs decoding operation according to the received row address until the normal element disable signal NED is generated.
According to the redundancy scheme, a defective row (word line) WLD is replaced with a redundant row WLR as shown in FIG. 8 (a), so that the defective word line WLD is equivalently repaired.
However, in the shown redundancy scheme, the row decoder RD is once activated, and then it is deactivated in response to the normal element disable signal NED. Thus, there is a time period in which the defective row is activated in the memory cell array MA to connect the memory cells thereon to respective columns. In order to avoid data contention on the columns between data of the defective row and data of the redundant row, it is necessary to wait for the activation of the redundant row until the defective row is deactivated, resulting in increased access time.
In addition, the mapping of video data in the memory cell array MA is in general the same as that on a display screen CRT as shown in FIG. 8. With the above described redundancy scheme, such a correspondence in mapping can not be maintained.
For a certain application, such destruction in mapping correspondence may not be a problem as far as a row word line selection is concerned because it can not be seen from an outer world how row addresses are made correspondent to physical dispositions of rows in a memory cell array.
However, in a video application video data are serially input and output to and from a memory, and the sequence of video data is required to be the same in input data and output data. Therefore, the above described redundancy scheme can not be applied to the very column repairing scheme.
Possible scheme for accommodating such a difficulty in column repairing may be that as shown in FIG. 9. In FIG. 7 a defective column line CLD having connected thereto defective memory cell is indicated by the mark "x" is replaced with a redundant column CLR. A storage element a2 is connected through a transfer gate transistor TG2 to the redundant column CLR. With the repairing scheme, the sequence of video data al to an is maintained in data inputting and in data outputting.
However, in the scheme, the redundant column CLR is connected through a long interconnection line IL to the transfer gate transistor TG2, and it takes longer time for data transfer between the storage element a2 and the redundant column CLR as compared to any other normal column-to- storage element data transfer, deteriorating fast operability.
In order to connect the redundant column CLR to the transistor TG2, fuse elements may be employed, and fuse elements between the transfer gate transistors for normal columns and the interconnection line IL may be blown off with a laser beam, as has been done in programming a ROM. However, it is difficult in practice to execute correctly such a repairing interconnection technique because there are many fuse elements to be blown off, leading to reduction in product yield.

Counter device and method of operating the same


This invention relates to a system and apparatus for retaining a prosthetic valve in a valve pocket suspended in a sealed container to protect from damage and contamination during shipment, handling and storage. The apparatus is an easy to open container having remote fill ports for adding a sterile liquid after enclosing the valve inside. A tamper evident seal is provided having a novel configuration to detect prior opening of the container. The apparatus includes an assembly having a shelf that is provided in a variety of configurations. The shelf has a mitral valve configuration and an aortic valve configuration. The shelf is selected based on the valve configurations and size. The system is easily assembled having a single variable component to adapt to a particular prosthetic valve to be stored. The present invention provides an apparatus for eliminating the need for direct attachment of the valve serial tag to the valve.

Heart valves and more specifically prosthetic aortic and mitral valves are manufactured and prepared for insertion into patients during a surgical procedure. The valves must be sterilized after manufacture and stored in a container for shipment to a hospital or surgery center. The valve is then removed from the package, rinsed and prepared for placement in a patient during surgery.
The container preserves the sterile condition of the valve, protects the valve from damage and minimizes the effort needed by the surgical team to prepare and insert the valve. Sterilization is critical and challenging in working with prosthetic devices. The devices are made in a non-sterile environment and sterilized before packaging and shipping. The valve is usually stored in a sterile solution such as a 0.2% Glutaraldehyde solution after sterilization. Glass jars are commonly used because glass resists reacting with the solution, is inexpensive and can withstand sterilization. A retainer holds the valve in a fixed position inside the container to keep it submerged in the solution.
Prior art designs to store and ship prosthetic heart valves include U.S. Pat. No. 4,750,619 to Cohen assigned to Osteonics Corp entitled "PACKAGE WITH TRAY FOR SECURING AND PRESENTING A STERILE PROSTHETIC IMPLANT ELEMENT". In the '619 patent, a package for holding the prosthetic heart valve has a tray which is stored in a hinged receptacle which is sealed to protect against contamination. In all, three containers are used including the sealing cover. In the Dohm U.S. Pat. No. 5,720,391, entitled "PACKAGING HOLDER FOR HEART VALVE PROSTHESIS", the prosthetic is mounted on a holder having a post. The holder is suspended in a plurality of trays each having a lid. The trays are heat sealed to protect the valve. In U.S. Pat. No. 5,823,342 to Caudillo for "PACKAGING FOR MITRAL OR AORTIC HEART VLAVE DEVICE" an outer shell is screwed together to form a housing over a container having an interchangeable holder for an aortic or mitral valve. U.S. Pat. No. 5,960,956, entitled, "STORAGE CONTAINER", describes a container for holding a prosthetic device in a high humidity environment of sterile liquid but not submersing the device.
Manufacturers are making a variety of valve designs and sizes. This variety of size and configuration demands a flexible packaging system to reduce inventory of valve containers and retainers. Accordingly, there is a need for a system or apparatus for packaging prosthetic heart valves that can be configured to different valve designs, valve sizes, and styles with minimal changes. There is also a need for a storage system that is easy to open.

Heart valve storage and shipping retainer


A radio frequency (RF) remote controller device comprises radio frequency (RF) circuitry operably coupled to an antenna arrangement and arranged to transmit and receive RF signals to and from controllable devices. The RF remote controller device further comprises signal process logic operably coupled to the RF circuitry and to a user interface. The antenna arrangement is arranged to comprise a directivity characteristic. The signal processing logic upon receipt of a command input from the user interface, is arranged to: determine at least one link quality value that is at least partly dependent upon the directivity characteristic for the at least one controllable device; and select the controllable device for remote controlling based on the determined at least one link quality value.

In the field of Radio Frequency (RF) remote controllers, it is known for such RF remote controllers to be paired with a plurality of devices to be controlled of the same type. For example, an RF remote controller may be paired with two or more television sets, the television sets being located in different rooms within, say, a residential building. Examples of other devices to which the RF remote controller may additionally/alternatively be paired with include, by way of example, DVD (Digital Versatile Disk) players, lighting systems, air conditioning systems, etc. Such RF remote controllers may be arranged to operate using IEEE 802.15.4 global standard RF protocols (see http://www.ieee802.org/15/) such as the new RF4CE (RF for Consumer Electronics) protocol currently being developed by the RF4CE consortium (www.rf4ce.org), the applicant's SynkroRF™ entertainment control network protocol (www.freescale.com/synkro), etc.
Typically, at any given moment only one device of any given type may be selected and controlled by an input means of a user interface of the RF remote controller, such as appropriate buttons or keys. In order to select a different device of a certain type to that currently selected, a user of the RF remote controller manually selects the device that they wish to control via the user interface.
This need for a user to manually select the required device to be controlled can significantly degrade the user experience. For example, in a case where a user moves from one room to another, it may be necessary for that user to change the selection of multiple types of devices (e.g. DVD player, television set, lighting system, etc.), resulting in a cumbersome experience for the user. The need to manually select the required device to be controlled may be even more detrimental to the user experience when a plurality of devices of the same type are present within close proximity, for example within the same room, and which a user may wish to control substantially concurrently. For example, the RF remote controller device may be paired with, say, two or more lighting systems within a room. In order for the user to configure the overall lighting arrangement within the room, for example to turn two of the lighting systems 'on', whilst turning a third lighting system 'off', the user is required to manually select each lighting system in turn in order to remotely control them.

Radio frequency remote controller device, integrated circuit and method for selecting at least one device to be controlled