A method for fabricating sidewall spacers in the manufacture of an integrated circuit device is disclosed. A dielectric spacer layer is formed over the semiconductor substrate. The dielectric spacer layer is etched prior to forming a layer subsequent to the dielectric layer, to form an L-shaped spacer. In another embodiment, a structure is formed on a substrate, the structure having a sidewall portion that is substantially orthogonal to a surface of the substrate. A dielectric layer is formed over the substrate. A spacer is formed over a portion of the dielectric layer and adjacent to the sidewall portion of the structure, wherein at least a portion of the dielectric layer over the substrate without an overlying oxide spacer is an unprotected portion of the dielectric. At least a part of the unprotected portion of the dielectric layer is removed. An intermediate source-drain region can be formed beneath a portion of the L-shaped spacer by controlling the thickness and/or the source drain doping levels.

An integrated circuit (IC) is an assembly of discrete devices such as resistors, transistors, capacitors, etc. As an example, the transistor is a device comprising on-off properties that act as a power switch to the IC. A commonly known transistor to those skilled in the art is a metal-oxide-semiconductor field effect transistor (MOSFET).
Generally speaking, a typical MOSFET comprises a silicon substrate with a thin layer of thermally grown oxide used to isolate the substrate from conductive electrode. The metal electrode, generally referred to as a gate electrode, controls the on-off properties of the working device. The substrate including the gate electrode further comprises an oxidized gate dielectric layer on the sidewalls of the gate electrode and low-doped drain regions formed by implanting ions into the substrate of both sides of the gate dielectric layer. A spacer of an insulating layer is generally formed adjacent to opposite sidewalls of the gate electrode and the oxidized gate dielectric layer. An ion implantation process is performed to form a source and a drain at predetermined positions of the substrate besides the at least two spacers.
A conventional spacer commonly known to those skilled in the art is a D-shaped spacer. As the semiconductor industry continues to increase the density of devices manufacturable on a semiconductor substrate, the device features continue to shrink below the quarter-micron size. The critical dimensions between the gate electrodes are decreased, making it more difficult to achieve void-free fill between the spacers adjacent to the gate electrodes. In addition, channel stress-related and silicide stress-related problems increase with decreasing dimension. It is desired to fabricate semiconductor devices using reliable processing methods including a reduction in the number of steps required to fabricate a semiconductor device, reduced defects, lower thermal budget, reduced channel stress, and reduced resistivity at the source/drain region.
The disclosed invention provides space methods of forming this spacer, and more specifically a method of forming a spacer.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the Figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the Figures to indicate corresponding or analogous elements.
FIGS. 1 through 18 depict, in accordance with various embodiments of the disclosures made herein, the formation of a semiconductor device with a self aligned spacer, and a method of forming such a self aligned spacer during manufacture of a semiconductor device. The method provides for improved thermal budget, reduced channel stress, and reduced resistivity at the source/drain region.
FIG. 1 is a cross-sectional view illustrating an exemplary embodiment of a portion of a semiconductor device 11. The device of FIG. 1 includes a substrate 10. In the assorted embodiments, substrate 10 is a semiconductor device substrate such as silicon, gallium arsenide, or other appropriate substrate, on which the illustrated features have been formed. For reference purposes, substrate 10 is illustrated as having a horizontal surface. A structure 16 is formed on the substrate 10, wherein the structure 16 comprises a sidewall portion 17 that is substantially orthogonal to the surface of the substrate 10, and a top portion 19 that is substantially parallel to the surface of the substrate 10. In a more specific embodiment, the structure 16 is a gate structure comprising a gate electrode 40 overlying a gate dielectric layer 42, which forms the sidewall portion 17. In an embodiment, the gate electrode 40 is a polysilicon conductor and the gate dielectric layer 42 is an oxide layer, such as silicon dioxide, hafnium oxide, or a hafniumsilicate compound. In another embodiment, the gate electrode 40 comprises a layer containing at least one of a heavy metal or oxygen atoms, or other suitable gate material known to those of skill in the art. By way of example, the heavy metal atoms include Ruthenium or Indium. More specifically, the gate electrode 40 can comprise Ruthenium oxide or Iridium oxide.
FIG. 2 is a cross-sectional view illustrating a liner oxide layer 21 formed over the substrate 10 and gate electrode 40 of semiconductor device 11 according to an embodiment of the present disclosure. Liner oxide layer 21 may be formed using low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor desposition (PECVD) techniques, and ranges in thickness from about 50 to 300 angstroms. In one embodiment, the thickness of liner oxide layer 21 ranges from about 60 to 200 angstroms.
FIG. 3 is a cross-sectional view illustrating a dielectric layer 22 formed over the liner oxide layer 21 of semiconductor device 11. In an embodiment, the dielectric layer 22 is a nitride layer ranging in thickness from about 150 to 500 angstroms. In an exemplary embodiment, the thickness of dielectric layer 22 ranges from about 150 to 350 angstroms, and may be formed using LPCVD or PECVD techniques. Further, precursors for the nitride deposition include silane, dichlorosilane, hexachlorosilane, or BTBAS.
FIG. 4 is a cross-sectional view illustrating formation of an additional layer 24 over the semiconductor device 11 according to at least one embodiment of the present disclosure. In one embodiment, additional layer 24 may be comprised of an oxide layer ranging in thickness from about 500 to 1000 angstroms. For example, the oxide layer can include silicon dioxide. In another embodiment, additional layer 24 may be a silicon-containing layer ranging in thickness from about 300 to 900 angstroms. For example, the silicon-containing additional layer 24 can include polysilicon or amorphous silicon. Additional layer 24 serves the purpose of being sacrificial to the degree required to shape a forming spacer, as seen in FIG. 5. FIGS. 5 through 10 reference forming spacers made from an oxide additional layer 24, while FIGS. 11, 12, and 15 through 18 reference forming spacers made from a silicon-containing additional layer 24.
FIG. 5 illustrates a cross-sectional view showing the forming spacers 25 adjacent to the sidewall portion of structure 16 including the gate electrode 40 that remain after etching away portions of additional layer 24. In one embodiment, the forming spacers 25 are oxide portions that substantially fill an interior angle space 23 defined by the horizontal and vertical portions of the dielectric layer 22. Portions 15 of the dielectric layer 22 which do not have an overlying forming spacer 25, are referred to as unprotected portions 15 of the dielectric layer 22. For this particular embodiment, a process to etch away portion of additional layer 24 to form spacers 25 is a process selective to nitride that includes using C4F8 as a main etch gas and is commonly known to those skilled in the art. In another embodiment, the forming spacers 25 are silicon-containing portions that substantially fills an interior angle space 23 defined by the horizontal and vertical position of the dielectric layer 22. For this case, the silicon-containing forming spacers 25 can be sacrificial portions that are removed after its purpose has been served. In particular, the silicon-containing portions are removed using a process that includes HBr, Cl2, and HeO2 and is also commonly known to those skilled in the art.
FIG. 6 is a cross-sectional view illustrating the semiconductor device 11, wherein at least part of the unprotected portions 15 (FIG. 5) of the dielectric layer 22 are removed to form at least one spacer 27. In one embodiment, the spacer 27 is an L-shaped spacer 27 having a sidewall portion 28 and a substrate portion 29. More specifically, the sidewall portion 28 of the spacer 27 is a vertical portion parallel to the sidewall portion 17 of structure 16 (FIG. 1) including the gate electrode 40. Further, the substrate portion 29 of the spacer 27 is a horizontal portion approximately orthogonal to the sidewall portion 17 of structure 16 including the gate electrode 40 and is substantially parallel to the original surface of the substrate 10. Portions 30 of liner oxide layer 21 that do not have an overlying L-shaped spacer 27 are referred to as unprotected portions 30 of the liner oxide layer 21. In one embodiment, the sidewall portion 28 of the L-shaped spacer 27 may be recessed as shown in FIG. 6.
By way of example, the distance between the uppermost section of the sidewall portion 28 and the upper surface of the gate electrode 40 range from about 200 to 300 angstroms. The recessed L-shaped spacer 27 enhances silicide growth in the following fabrication sequence. It should be noted that although forming spacer 25 is illustrated in FIG. 6 as extending above the uppermost section of sidewall portion 28 of L-shaped spacer 27, in other embodiments, forming spacer 25 may be on the same level as, or recessed slightly below, the uppermost section of sidewall portion 28 of L-shaped spacer 27. Final size of forming spacer 25 is dependant upon the extent of etch conducted upon it.
In the described embodiments, the etch process for removing at least part of the unprotected portions 15 of the dielectric layer 22 can utilize a dry etch process. In the assorted embodiments, the etch process involves the substrate 10 to be placed in an exemplary process chamber capable of performing a dry, anisotropic etch. The chamber can be a capacitively coupled chamber or an inductively coupled chamber. In one embodiment, the process steps of forming the forming spacer 25 by removing portions of additional layer 24 and the process steps of forming the L-shaped spacer 27 by removing at least part of the unprotected portions 15 of the dielectric layer 22 are executed in one process chamber. In another embodiment, the process steps of forming the forming spacer 25 and the L-shaped spacer 27 are performed in at least two different process chambers.
The chamber is pressurized to a value that enhances a uniform etch and the substrate 10 is adjusted to a temperature such as about 10C to 30C. In the case in which the dielectric layer 22 is a nitride layer, the resulting L-shaped spacer 27 comprises a nitride layer. A fluorine gas source and an oxygen gas source then flows a fluorine-containing gas mixture, which may optionally include an oxygen-containing gas mixture, into the pressurized chamber. The gas flow rate ratio may vary depending on the particular embodiment and the desired selectivity for a particular application.
In one embodiment, a process selective to both oxide and silicon layers includes using CH3F and O2. The gas mixture comprising CH3F and O2 flows into the chamber with a gas flow rate ratio having a value within the range of approximately 1:2 and 1:6, with a preferred range of 1:2 and 1:3. For this particular case, the chamber is pressurized to a value within the range of approximately 20 and 250 milli Torr (mTorr) and, more specifically, 60 to 100 mTorr.
In another embodiment, the use of an oxygen gas source is optional. By way of example, a process that is sufficiently selective to an oxide and silicon layer comprises CF4, and CHF3. The gas flow rate ratio of CF4 and CHF3 is a value within the range of approximately 1:0 and 0:1 and the chamber is pressurized to a value within the range of approximately 50 and 250 mTorr. Alternatively, a process selective to an oxide layer but not a silicon layer includes using CF4 and HBr. For this case, the substrate 10 is adjusted to a temperature such as about 50C to 80C. The gas flow rate ratio of CF4 and HBr is a value within the range of approximately 5:1 and 2:1 and the chamber is pressurized to a value within the range of approximately 50 and 150 mTorr.
After a sufficient time for the pressure and gas flow to stabilize, an excitation power is applied to sustain plasma for a sufficient period of time needed to etch away the unprotected area of a layer, such as the unprotected portion 15 of the dielectric layer 22 shown in FIG. 5. In one embodiment, an RF source power generator (not shown) coupled to an inductive antenna coils provides power to generate reactive species and controls the plasma density, which, in turn, enhances chemical reactions. An RF bias power generator controls the ion bombardment of the surface of device 11, and enhances a more physical etch. In another embodiment, only a single RF power generator is used and the etching mechanism may be either reactive or physical.
The period of time in which the excitation power sustains plasma needed to etch away the unprotected area of the dielectric layer 22 varies depending on the thickness of the dielectric layer 22. By way of example, the dielectric layer 22 is a nitride layer. More specifically, the dielectric layer 22 is a nitride layer having a thickness within the range of 150 and 500 angstroms. For this particular case, the etch rate is a value within the range of 300 and 900 angstroms per minute and, therefore, the excitation power is sustained at a value within the range of approximately 10 and 100 seconds.
In one embodiment, unprotected portions 30 of liner oxide layer 21 may be etched such that only the protected portion 20 remains, as seen in FIG. 7. FIG. 7 is a cross-sectional view of the portion of a transistor of semiconductor device 11 after etching away the unprotected portions 30 of the liner oxide 21. The protected portion 20 of liner oxide layer 21 that remains is also L-shaped.
In the various embodiments, a metal layer such as one of titanium, cobalt, nickel, or similar group metals may be formed over the device 11 of FIG. 8, including over the forming spacer 25, L-shaped spacer 27, remaining portion of liner oxide 20, and the top of gate electrode 40. Annealing the device 11 of FIG. 8 at an elevated temperature causes the metal layer to react with the underlying surfaces of substrate 10 and the polysilicon gate electrode 40 during a silicidation process. More specifically, the heat reaction with the metal layer and the silicon present in substrate 10 and gate electrode 40, form silicide layers 92, illustrated by cross-section in FIG. 8. It should be noted that the remaining metal layer, which does not react at elevated temperature, is removed and is thus not illustrated in FIG. 8.
FIG. 9 illustrates a cross-sectional view of device 11 further including the addition of a pre-metal dielectric layer 108. In one embodiment, the pre-metal dielectric layer 108 includes at least one of an oxide layer, a boron silicon glass (BSG) layer, a boron phosphorous silicon glass (BPSG) layer or a phosphorous silicon glass (PSG) layer. Pre-metal dielectric layer 108 is formed over the device 11 of FIG. 8 to accommodate a subsequent metal layer (not illustrated). It should be noted that device 11 of FIG. 9 is a transistor, however, the formation of source/drain regions is not illustrated in FIG. 9.
In an alternate embodiment of the present disclosure, the pre-metal dielectric layer 108 comprises a composite layer 111 including a first layer containing nitrogen 109 and a second layer 110, as illustrated in the cross-sectional view of FIG. 10. In particular, the first layer 109 of the composite layer 111 is between the forming spacer 25 overlying the spacer 27 and the second layer 110. By way of example, the first layer 109 is a silicon nitride layer or a siliconoxynitride layer. The second layer 110 comprises at least one of an oxide layer, a boron silicon glass (BSG) layer, a boron phosphorous silicon glass (BPSG) layer or a phosphorous silicon glass (PSG) layer.
FIG. 11 is a cross-section view illustrating a partially formed transistor of semiconductor device 11 according to an embodiment of the disclosure. In the illustrated embodiment of FIG. 11, the various processing steps up to the formation of the L-shaped spacer 27 and remaining portion of liner oxide 20 have been completed, as was presented in FIGS. 4 through 7. Additionally, in FIG. 11, removal of the forming spacer (item 25 in FIGS. 5 through 7) which substantially filled an interior angle space defined by the horizontal and vertical position of the spacer 27 has been accomplished. For this particular embodiment, the forming spacer was a silicon-containing forming spacer. An exemplary technique for removing the (silicon or oxide) forming spacer includes reactive ion etching (RIE) dry etching.
FIG. 12 illustrates a cross-sectional view of the semiconductor device of FIG. 11 having a silicide and pre-metal dielectric layer formed in a similar manner as discussed with reference to FIGS. 8 and 9. Alternately, the pre-metal dielectric layer may comprise a composite layer such as was discussed with reference to FIG. 10, including a first layer containing nitrogen, and a second layer.
Referring now to FIG. 13, a cross-sectional view of a semiconductor device according to at least one embodiment of the present invention is presented. In this particular embodiment, semiconductor device 111 comprises two partially formed transistors 103 and 104. The distance of separation between the gate sidewalls of partially formed transistors 103 and 104 is denoted by the letter d, and in one embodiment is less than 150 nanometers, with a preferred distance being at or less that 120 nanometers. Device 111 comprises a substrate 110, a first gate structure 215 and a second gate structure 216 formed on the substrate 110, at least one gate dielectric layer 220, a liner oxide layer 121 and a spacer dielectric layer 122 which has been formed overlying liner oxide layer 121. Substrate 110 may be active silicon or field isolation material. There is no oxide or silicon-containing forming spacer utilized in this particular embodiment.
The spacer dielectric layer 122 is selectively etched to form an L-shaped spacer 127 as shown in the cross-sectional illustration of FIG. 14. In one embodiment, spacer dielectric layer 122 is a nitride layer. More specifically, the spacer dielectric layer 122 can be a nitride layer having a thickness within the range of approximately 150 and 500 angstroms. Similar to the dielectric layer 22 of FIG. 5, the spacer dielectric layer 122 can be formed using an PECVD or LPCVD technique. The underlying liner oxide 121, when used, would generally have a thickness in the range of approximately 20 angstroms to 200 angstroms.
For this particular embodiment, the process for forming the L-shaped spacer 127 from the dielectric layer 122 can utilize a dry etch process. The etch process involves the substrate 110 to be placed in an exemplary chamber capable of performing a dry, anisotropic etch. For example, the chamber can be a capacitively coupled chamber or an inductively coupled chamber. The chamber is pressurized to a value that enhances a uniform etch and the substrate 110 is adjusted to a temperature such as about 10C to 30C.
A fluorine gas source and an oxygen gas source then flows a fluorine-containing gas mixture and an oxygen-containing gas mixture into the pressurized chamber. The gas flow rate ratio may vary depending on the particular embodiment and the desired selectivity for a particular application. By way of example, the gas mixture comprises CH3F and O2. The CH3F and O2 gas mixture flows into the chamber with a gas flow rate ratio (CH3F: O2) having a value within the range of approximately 2:1 and 5:1, with a preferred range of 3:1 and 4:1. For this particular case, the chamber is pressurized to a value within the range of approximately 20 and 500 mTorr and, more specifically, 60 to 100 mtorr.
In the described embodiment, the CH3F-rich gas mixture allows the L-shaped spacer 127 to be formed without employing the use of a sacrificial forming spacer. Variations and different embodiments of the L-shaped spacer 27 of FIG. 9 are applicable in the L-shaped spacer 127. In addition, the resulting benefits from the L-shaped spacer 27 of FIG. 9 are applicable to the L-shaped spacer 127. Examples of resulting benefits include a reduction in the number of steps required to fabricate a semiconductor device, reduced defects, lower thermal budget, reduced channel stress, and reduced resistivity at the source/drain region. The process used to form spacer 127 can reduce the number of steps used in the formation of the L-shaped spacers. The resulting spacer 127 has a bulging, which, with respect to the horizontal portion 128 of the spacer 127, results in a profile which varies gradually in thickness from a maximum thickness immediately adjacent the vertical portion of the L-shaped spacer to a portion of the L-shaped spacer furthest from the vertical-portion of the L-shaped spacer. The resulting profile of the horizontal portion of the spacer 127 varies gradually to provide for an average thickness of that is 50 to 85 percent of the maximum thickness, and, more specifically, 60 to 75 percent of the maximum thickness. In addition, one embodiment results in the formation of the horizontal portion 128 having a length that is between 80 and 150 percent of the deposition thickness of the layer 122 from which the spacers are formed.
FIG. 15 illustrates a cross-sectional view of a partial transistor 1100 having a lightly doped source/drain region 230 (also referred to as a source/drain extension) in a substrate 101. Partial transistor 1100 is formed in the same manner as the partial transistor 11 illustrated in FIG. 11. Although not illustrated in FIG. 15, it is possible to have various halo implants underlying doped regions 230 in order to control short channel effects.
FIG. 16 is a cross-sectional view illustrating the formation deeply formed by doping source/drain regions 660 within portions of the substrate 101 adjacent to the spacers 270. Doped regions 660 are created by ion implantation 305 and is commonly known to those skilled in the art.
In FIG. 17, substrate 101 is doped by ion implantation 305 to form intermediate doped regions 760 and deeply formed source/drain regions 660. In an embodiment, the intermediate doped regions 760 are intermediate source/drain regions formed by doping the substrate 101, wherein the dopants are implanted through the substrate portion of the spacer 270. The formation of intermediate doped regions 760 is a function of both the thickness of the lower portion of the L-shaped spacer and the energy of the implanted ions (implant power). By way of example, the substrate portion of the L-shaped spacer 270 comprise a thickness within the range of approximately 150 to 500 angstroms and the underlying liner oxide layer 200 includes a thickness within the range of approximately 50 and 300 angstroms. For this assorted embodiment, possible implant species for a PMOS are Boron (B), Indium (In) and Boron diflouride (BF2). In particular, to implant Boron with an ion dose within the range of 1e13/cm2 and 1e15/cm2, the ion energy applied is a value within the range of about 5 keV and 15 keV. Possible implant species for an NMOS are Arsenic (As), Phosphorous (Ph) and Antimony (Sb). Similarly, to implant Arsenic with an ion dose within the range of 1e13/cm2 and 1e15/cm2, the ion energy applied is a value within the range of about 10 keV and 100 keV.
The intermediate doped regions 760 is not formed as deeply into the substrate 101 as the deeply formed source/drain regions 660, since the L-shaped spacer resides over the intermediate doped regions 760.
In the described embodiments, the depth of the intermediate doped regions 760 can be a value within the range of approximately 50 angstroms to 500 angstroms, while the source/drain region 660 will have a greater depth, generally in the range of 300 to 1000 Angstroms or greater. In another embodiment in which the ion energies are at the lower end of its range and/or the thickness of the oxide and nitride layers are at the upper end of its range, the ion does not penetrate through the substrate portion of the spacer 270 to the silicon. In particular, the deeply formed source/drain regions 660 have an average depth that is greater than the average depth of the intermediate source/drain region 760. Likewise, the intermediate source/drain region 760 has an average depth that is greater than the source/drain extension region 230.
FIG. 18 is a cross-sectional view of a substantially completed transistor 1100 according to an embodiment of the present disclosure. A pre-metal dielectric layer 1108 is applied over the partially formed transistor device 1100 of FIG. 17. In one embodiment, the pre-metal dielectric layer 1108 may be comprised of a composite layer (not illustrated). A metal structure 990 has been formed over a portion of the pre-metal dielectric layer 1108. Formation of metal structures, such as metal structure 990, can be performed using any appropriate process as would be readily known in the art. While metal structure 990 is illustrated as an inlaid structure, it will be appreciated that non-inlaid structures may be used as well.
In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims.

System for forming a semiconductor device and method thereof


A system and method for estimating power of a wireless system simultaneously estimates and displays a code domain power and a time domain power in the system which may be a wireless communication system that mixes TDMA and CDMA methods such as WCDMA TDD and TD-SCDMA. The method includes designating a section where an output power is to be estimated, estimating a time domain power in the designated section; estimating a code domain power in the designated section, and displaying the estimated time domain power and the code domain power on a display unit.

1. Field of the Invention
The present invention generally relates to wireless communications, and more particularly to estimating power in a wireless mobile communication system.
2. Description of the Related Art
A multiple access method performs wireless communications by allowing a plurality of users to share time and frequency simultaneously. Multiple access methods include frequency division multiple access (FDMA) methods, time division multiple access (IDMA) methods, and code division multiple access (CDMA) methods. The FDMA method allocates one frequency per user.
The TDMA method is performed by adding a time division notion to a frequency division notion of the FDMA method. Also, in TDMA, a voice signal is converted into a digital frame or packet to be transmitted, and each channel is divided into a short time period.
The CDMA method is a spread-spectrum technique, in which a plurality of users simultaneously share time and frequency. Each user is allocated a specific code, and a transmitter and receiver have to be synchronized in order to modulate and demodulate code spread data.
Generally, functions performed in TDMA/CDMA methods are certified by estimating a quality of output power of a base station or mobile station. Time domain power is estimated in the TDMA method and a code domain power is estimated in the CDMA method, and equipment for estimating time domain power is different from equipment for estimating code domain power. Therefore, conventionally, equipment for estimating the time domain power can only be used in a TDMA system, and equipment for estimating code domain power can only be used in a CDMA system.
In order to measure the quality of output power, in a CDMA method a certain allocated frequency band is divided into different codes to distinguish respective channels. At this time, transmission frequency and receiving frequency are different from one another. A duplexer may therefore be used at a high frequency end. In contrast, in a TDMA method, the same frequency band is allocated for transmitting and receiving data, and transmission and reception channels are distinguished by time division switching. A time division switch is used at the high frequency end during this technique.
Certifying a function of a mobile communication system by estimating the quality of output power of a base or mobile stations is important. This process is widely used over the entire mobile communication industry, for example, to perform quality testing during the manufacture of a mobile station, to measure communication quality between base and mobile stations, and to operate one or more radio resources.
FIG. 1 is a graph showing a time domain power measurement in a global system for mobile communication (GSM) method employing TDMA. In the graph, a frequency band allocated to an up-link and a down-link in the GSM method is divided into each channel, and the divided channel is again divided into time slots using a TDMA method. That is, the channel is divided into time slots (or burst periods), the most basic unit in TDMA.
The up-link denotes a transmission path from a mobile station to a base station, and the down-link denotes a transmission path from a base station to a mobile station. One TDMA frame is divided into 8 time slots (TS0-TS7), and power is estimated for each time slot based on this arrangement. Power is represented by dBm units. Time slot TS0 is allocated to the down-link and is used to transmit a data signal or operational information from a base station for controlling a mobile station. The remaining time slots TS1-TS7 are allocated to the up-link and down-link, and are used to detect and display levels operated on each channel.
FIG. 2 is a graph showing a code domain power measurement performed in an IS-95 method. In this method, 64 (0-63) channels are used and each channel has an output power which is estimated and displayed in the graph. The code domain power is represented in dB units. In estimating and displaying the code domain power based on a CDMA method, the signal power of each channel and noise power is simultaneously estimated. In FIG. 2, channels 3, 6 and 59 are shown as having power which is greatly decreased compared to the power of the remaining channels, which, for example, have not received data to be transmitted. The measurement results are displayed together on one screen, so that a signal-to-noise ratio (SNR or S/N) can be easily recognized.
In order to distinguish channels in the CDMA method, a Walsh code is generally used. Because multiple users use the same frequency in a CDMA method, power management is necessary. Accordingly, base station power is estimated by being distinguished based on Walsh codes, and a code domain power is estimated by comparing a non-operational code power with a total power, thereby properly distributing power. This also reduces interference between channels and maximizes capacity of a section.
FIG. 3 is a chart showing a state of a channel allocated by a Walsh code length in a general CDMA method. When the Walsh code length is 4 (L=4), 4 channels 0-3 are allocated. When the Walsh code length is 8 (L=8), 8 channels 0-7 are allocated. And, when the Walsh code length is 16 (L=16), 16 channels 0-15 are allocated. From these chart entries, it can be seen that channel allocation is proportional to the Walsh code length, L.
As previously mentioned, in order to estimate transmitting power in a CDMA system, code domain power estimation for estimating an output power per channel is performed. However, because transmitting frequencies of the base station and mobile station are different, and because the TDMA method was not introduced for each CDMA channel, no method for estimating the code domain power in a TDMA method has heretofore been proposed. Moreover, a method for estimating the time domain power in a CDMA method has not been proposed.
Therefore, there is a problem in that a method for performing power estimation in a code region in next-generation mobile communication systems where TDMA and CDMA methods are mixed, such as but not limited to wideband CDMA time division duplex (WCDMA TDD) systems and time division synchronous CDMA (TD-SCDMA) systems.

Power estimating method in wireless system


A coral holder resides in an aquarium and includes shelves with holes which accept coral plugs. The coral plugs are small round tables with cylindrical stems extending down from the table. Hobbyist take adult size living corals and “frag” them (i.e., cut the mother colony and break off a small section) and glue the coral fragments to the coral plugs. The coral plugs are inserted into the holes on the shelves providing a coral display. The holder includes a center section, a fixed top shelf and adjustable shelves. The adjustable shelves extend out sides and front of the center section and are adjustable allowing the aquarium owner to adjust the adjustable shelves accordingly to their needs (i.e., for the number of coral plugs). The positions of the shelves are fixed by inserting the coral plugs through the fixed top shelf and through the adjustable shelves.

The present invention relates to coral displays in aquariums and in particular to a display with adjustable shelves which may be fixed in a desired position.
Coral is often displayed in aquariums providing a colorful display of various natural shapes. Some aquarium owners collect a variety of different coral types and attach each to a common holder. Unfortunately when the aquarium owner desires to add to his display, he may reach a point where there is no additional room for added coral types.

Coral propagation holder with adjustable shelves


The African history card game includes a deck of educational cards. Each card has a front face with a fact, picture, question, and series of multiple choice answers each relating to a common theme, and a rear face having an alphabetic matrix of columns and rows concealing the correct answer. Point values based on the difficulty of the question on the particular card are provided on each card. Each card has a particular theme related to African history, e.g., geography, prominent individuals, history, inventions, science, engineering, sports, religion, culture, civil rights, agriculture, language, and music. The game may be adapted to other themes and subject areas, as desired. The object of the game is to determine the correct response of the choices on the front of the card, then find and point out this response in the rows, columns, and/or diagonals of the matrix on the back of the card.

1. Field of the Invention
The present invention relates generally to educational games. More particularly, the present invention comprises a game having a series of cards each containing a question and a series of answer choices, with the correct answer concealed in an alphabetic matrix on the reverse side of the card.
2. Description of the Related Art
Many African-Americans, both young and old, do not have a basic knowledge of African history. This lack of knowledge can cause problems in a person's ability to effectively function in today's society. There are many instances when basic knowledge of African history is needed.
Recent studies have shown a large percentage of people in this country are ignorant of world geography and cannot identify countries on a map. Other studies have shown that people do not know elected officials, both here and abroad; cultural events; or even basic historical facts. Evidently, the teaching methods and apparatus available now are not serving the function of teaching this basic knowledge. There are card games with printed information on the cards, but the games do not appear to be very effective in helping people retain knowledge about geography coupled with basic African history.
Accordingly, there is a need for an enjoyable educational card game that helps people retain basic knowledge about African history by providing facts and pictorial stimulation reiterated with a question having multiple choice answers, and including the answer hidden on the back of the card in a letter grid or matrix. Such educational card games can begin at an entry level and continue to much higher and more difficult levels, enticing people to play. Thus, an African history card game solving the aforementioned problems is desired.


A firearm cartridge with a bullet including a body and a nose element. The body has a forward end, and an opposed rear end, with an intermediate cylindrical portion between the ends. The front end of the body defines a cavity that may have a cylindrical shape. The nose element is formed of a resilient material such as an elastomer, and has a first portion received in the cavity, and a pointed second portion extending from the forward end of the body. The bullet may be received in a centerfire rifle casing, for safe use in a tubular magazine rifle, so that the resilient tip protects against discharge of an adjacent cartridge primer by absorbing energy of recoil or other impulse. The second portion of the tip has a small meplat, and is smoothly contoured with the exterior surface of the front of the bullet, to provide an increased ballistic coefficient.

Many popular types of rifles such as lever action rifles employ tubular magazines, in which a single line of cartridges is stored in a cylindrical tube parallel to and just below the rifle barrel. The cartridges are arranged nose first, with a compressed spring and piston forward of the nose of the forward most cartridge. The spring pressure transmits through the row of cartridges, and forces the rear most cartridge into the action when the action is cycled.
Because the nose of each cartridge in the tube presses against the rear of the next cartridge, this raises a critical safety concern. Centerfire cartridges have primers centered on the base of the cartridge, and it is essential to ensure that the nose of one bullet does not act like a firing pin that strikes the primer of the next bullet. Such forces can occur if a rifle is dropped, such as from an elevated tree stand, or from recoil upon discharge. Thus, sharply pointed bullets common to other types of rifles employing box magazines (in which the cartridges are positioned side-by-side) are not suitable for tube-magazine rifles.
Rifles with tubular magazines are limited to rimfire cartridges (which do not have a central primer and require a sharp pinching of the rim to discharge) and to centerfire cartridges having broad flat noses. Blunt, rounded nose bullets have been employed, but these are regarded as more risky than flat nosed bullets. Typically, the flat nose of a suitable bullet has a diameter of approximately 60% or greater than that of the primer. This ensures any force transmitted to the primer is distributed over a large enough area to ensure that primer discharge will not occur. Cartridges with heavier bullets generally have larger diameter flat noses, to account for the increased force that the added mass of a stack of cartridges can generate upon dropping a loaded rifle, and the increased recoil associated with such cartridges. The noses of such bullets are generally formed of exposed lead and are not fully jacketed to provide further safety.
While effective to ensure safety, flat nosed or other blunt bullets are aerodynamically inefficient compared to the sharply pointed bullets used in other rifles. This means that they lose more velocity as a function of distance traveled than a sharp pointed bullet, due to increased air resistance. This effect is greatest over longer distances. Because of this higher rate of velocity loss blunt bullets carry less energy downrange than do pointed bullets. In addition, the reduced velocity at distance leads to greater bullet drop and crosswind drift, requiring more compensation by and opportunity for error from the shooter.
A suitable safe, blunt bullet for a tubular rifle magazine will generally have a ballistic coefficient (BC) of approximately 0.200 depending on the caliber and weight of the bullet. Sharply pointed bullets, of comparable caliber and weight, have BC values typically of 0.250 to 0.350. Thus, a lever action rifle chambered in 30-30 Winchester is considered effective for deer hunting only out to about 100-150 yards, while cartridges with spire-point bullets of comparable weight and muzzle velocities are effective for deer beyond 250 yards.
The present invention overcomes the limitations of the prior art by providing a firearm cartridge with a bullet including a body and a nose element. The body has a forward tapered end, and an opposed flat or tapered rear end, with an intermediate cylindrical portion between the ends. The front end of the body defines a cavity that may have a cylindrical shape. The nose element is formed of a resilient elastomer material, and has a first portion received in the cavity, and a pointed second portion extending from the forward end of the body, smoothly contoured with the exterior surface of the front of the bullet, which provides an increased ballistic coefficient. The bullet can be placed in a centerfire rifle casing, and the resulting cartridge loaded in a tubular rifle magazine. The resilient tip protects against discharge of an adjacent cartridge primer by absorbing energy of recoil or other impulse.

Rifle cartridge with bullet having resilient pointed tip


The frequency of a clocking signal is adjusted in response to fluctuations in the power supply voltage. In one embodiment, a control circuit has a plurality of clock input terminals each coupled between selected adjacent ones of the stages of a multiple-stage ring oscillator circuit and has an output clock terminal coupled to an input terminal of the ring oscillator circuit. In this manner, the control circuit may implement a plurality of loops each including a different variety of the stages of the ring oscillator circuit, wherein the clocking signal associated with each of the loops has a unique frequency. A plurality of trip voltages each being equal to a unique predetermined fraction of the power supply voltage are compared to a reference voltage. The control circuit selects, in response to the comparison of the trip voltages and the reference voltage, one of the loops mentioned above to provide its clocking signal to an output terminal of the oscillator. Thus, fluctuations in the power supply voltage are reflected in the trip voltages and result in a selection of a loop which has associated therewith a clocking signal having a frequency appropriate for the power supply voltage.

1. Field of the Invention
This application relates generally to oscillators and specifically to adjusting the frequency of an oscillator circuit in response to changes in the power supply voltage.
2. Description of Related Art
Ring oscillator circuits are well known and may be used in a variety of circuit implementations. For example, charge pumps may employ a ring oscillator circuit to provide a clocking signal according to which the various stages of the charge pump are successively charged and discharged. The frequency of the clocking signal generated by the ring oscillator circuit typically varies over the operating voltage range of the power supply. As the power supply voltage decreases below approximately 3.0 volts, the frequency of the clocking signal generated by the ring oscillator circuit may, during such fluctuations described above, decrease to a level which degrades the performance of an associated circuit. For instance, when used as mentioned above with a charge pump circuit, the frequency of the clocking signal provided to the charge pump circuit may decrease to a level which undesirably limits the maximum current delivered to the charge pump, thereby retarding the charging of the charge pump.
The above-described problem of frequency variations has led to the development of ring oscillator circuits which generate a clocking signal having a frequency substantially independent of fluctuations in the magnitude of the power supply voltage. However, as the voltage of the associated power supply decreases, more current is required to sustain a constant charging of the charge pump circuit. Thus, there is a need to provide to charge pump circuit a clocking signal whose frequency increases with decreases in the voltage of the power supply.

Adaptive frequency compensation technique


The imaging apparatus has: a first exposure mode in which an exposure condition is determined based on pixel data generated by photoelectrically converting, by a plurality of pixels, light rays entering through a pupil division unit, a state of vignetting of the photographing optical system is determined based on information about a construction of a photographing optical system, and an exposure condition is determined based on the pixel data selected from the pixel data generated in accordance with the vignetting state; and a second exposure mode in which an exposure condition is determined based on data obtained by adding the generated pixel data with respect to the exit pupil area of the photographing lens.

Field of the Invention
The present invention relates to an imaging apparatus and, more particularly, to an exposure control technique of an imaging apparatus which can obtain a plurality of parallactic images.
Description of the Related Art
In the related arts, an automation of exposure (what is called AE) has been considered in a case where an imaging apparatus is automated. In recent years, many systems for obtaining two or more parallactic images have been proposed and techniques about exposure control of them have also been proposed. For example, Japanese Patent Application Laid-Open No. 2012-124622 discloses such a photographing system having a plurality of imaging apparatuses that an object is photographed under different exposure conditions of those imaging apparatuses and, thereafter, photographed images are combined by an image processing.
Japanese Patent Application Laid-Open No. 2011-197278 discloses such an imaging system that a program diagram is designed so as to give a priority to a parallax and a parallax-priority exposure condition is determined.
A camera system which can obtain light field information has been disclosed in Ren Ng, et al., "Light Field Photography with a Hand-held Plenoptic Camera", 2005, Computer Science Technical Report CTSR. A method of performing a focus adjustment (what is called refocus) after an image is obtained is disclosed in such a system.
However, according to the related art disclosed in the foregoing Patent Literature, a desired exposure is not necessarily obtained in the system which can simultaneously obtain many parallactic images from one imaging element. In other words, although the invention disclosed in Japanese Patent Application Laid-Open No. 2012-124622 can be applied to an imaging system (that is, multocular camera) in which a plurality of imaging apparatuses are combined, it is not easily implemented in a monocular camera.
According to the invention disclosed in Japanese Patent Application Laid-Open No. 2011-197278, although such an idea that there is a parallax-priority function can be realized, it cannot cope with a case where a complex vignetting of a photographing optical system exists, or the like.
According to the invention disclosed in Ren Ng, et al., "Light Field Photography with a Hand-held Plenoptic Camera", 2005, Computer Science Technical Report CTSR, although an idea such as refocus, change in iris value, or the like is widely disclosed, nothing is disclosed about how to determine the exposure condition when obtaining the light field information.
It is, therefore, an aspect of the invention to provide an imaging apparatus in which even in a state where there is a vignetting in a photographing optical system, an exposure condition corresponding to a function which has preferentially been set by the user can be determined.

Imaging apparatus and its control method and program


A system and method allow for extracting target signals from the overall measurement data without knowing how and where these data are collected, the locations and characteristics of target sources as well as those of random background noise sources. In essence, it uses an innovative and advanced signal processing technique to reveal certain critical information from a mixture of data that is hard to obtain otherwise. In particular, it allows for denoising the measured data that have been contaminated by various interfering and background noise, making it possible to extract certain target information that may be otherwise difficult to observe. The only assumption made in this method is that the target signal is incoherent with respect to all interfering signals and background noise. The more information about a target signal is available, the more complete the extracted signal becomes.

In practice, almost all signals are contaminated to certain degree by interfering signals and background noise. Since the test environment is usually non-ideal, contamination in data collection is unavoidable. Meanwhile, the test environment is typically arbitrary, and interfering signals and background noise are unknown a priori. As such, it is extremely challenging to extract target information from a mixture of data that include some unknown number of interfering signals and random background noise.
Common signal processing technologies such as the Fourier transform and short-time Fourier transform do not work, because they cannot handle the signals that are varying in time and frequency in an arbitrary manner. The wavelet transform allows for converting an arbitrary time signal into a form that either makes certain features of the original signal more amenable to study or enables the original data set to be described more succinctly. However, the standard discrete wavelet transform cannot be used directly to extract desired information from the measured data. This is because the discrete wavelet transform decomposes an arbitrary time signal into various scales, and displays their corresponding behaviors in the time domain at these scales. Such a treatment makes it difficult to analyze the behaviors of various components and features of the measured data, which is critical for extracting the desired information in practice.


A method and system for controlling carrier use to help manage uplink noise. A base station detects threshold high uplink noise on a carrier, and the base station responsively configures itself to prevent the carrier from being added as a secondary carrier for carrier-aggregation service, though the base station still allows establishment of new radio-link-layer connectivity encompassing the carrier as a primary serving carrier.

A cellular wireless network typically includes a number of base stations that are configured to provide wireless coverage areas in which to serve user equipment devices (UEs) such as cell phones, tablet computers, tracking devices, embedded wireless modules, and other wirelessly equipped communication devices (whether or not user operated. In turn, each base station could be coupled with a core network that provides connectivity with one or more transport networks, such as the public switched telephone network (PSTN) and/or the Internet for instance. With this arrangement, a UE within coverage of the network could engage in air interface communication with a base station and could thereby communicate via the base station with various remote network entities or with other UEs served by the base station.
Such a network could operate in accordance with a particular radio access technology, with air-interface communications from the base stations to UEs defining a downlink or forward link and air-interface communications from the UEs to the base stations defining an uplink or reverse link.
Over the years, the industry has embraced various "generations" of radio access technologies, in a continuous effort to increase available data rate and quality of service for end users. These generations have ranged from "1G," which used simple analog frequency modulation to facilitate basic voice-call service, to "4G"—such as Long Term Evolution (LTE), which facilitates mobile broadband service using technologies such as orthogonal frequency division multiplexing (OFDM) and multiple input multiple output (MIMO). And most recently, the industry is now exploring developments in "5G" and particularly "5G NR" (5G New Radio), which may use a scalable OFDM air interface, advanced channel coding, massive-MIMO, beamforming, and/or other features, to support higher data rates and countless applications, such as mission-critical services, enhanced mobile broadband, and massive Internet of Things (IoT).
In accordance with an example radio access technology, a base station could operate on one or more carriers, each of which could have a respective downlink frequency channel for carrying communications from the base station to UEs and a respective uplink frequency channel for carrying communications from the UEs to the base station. Each such carrier could be frequency division duplex (FDD), in which its downlink and uplink channels occupy separate respective ranges of frequency, each having an associated center frequency and bandwidth, or time division duplex (TDD), in which its downlink and uplink channels are time division multiplexed on a common range of frequency, having an associated center frequency and bandwidth.
Further, the downlink and uplink of each carrier could be structured to define various air interface resources and channels for carrying information between the base stations and UEs.
For example, the air interface could be divided over time into frames, with each frame being divided in turn into subframes or transmission time intervals (TTIs), and the carrier bandwidth could be divided over frequency into subcarriers, which could be grouped within each TTI to define physical resource blocks (PRBs) in which the subcarriers can be modulated to carry data. In each downlink TTI, a first time-portion of the air interface could define a downlink control region for carrying control signaling from the base station to served UEs, and a remaining time-portion of the air interface could define a physical downlink shared traffic channel on which the base station could allocate PRBs to carry data to served UEs. And in each uplink TTI, certain PRBs at the low-frequency and high-frequency ends of the uplink bandwidth could define an uplink control region for carrying control signaling from UEs to the base station, and a remainder of the PRBs across the uplink bandwidth could define a physical uplink shared traffic channel of which the base station could allocate PRBs to carry data from UEs to the base station. Further, certain air interface resource elements on the downlink and uplink could be reserved for other purposes as well.
When a UE is positioned within coverage of such a system, the UE could detect threshold strong coverage of a base station on a particular carrier. In turn, the UE and base station could then engage in control signaling to establish a radio-link-layer connection, defining an air interface connection through which the base station will then serve the UE. And the base station could establish for the UE a context record indicating an identity of the established radio-link-layer connection and noting that the connection encompasses the carrier on which the UE connected. Further, if the UE is not already registered for service with the core network, the UE could engage in attach signaling with the core network via the base station, and the core network could establish for the UE one or more bearer channels for carrying packet-data communications between the UE and a transport network such as the Internet.
The base station could then serve the UE on the carrier on which the UE connected, allocating PRBs as necessary to carry data over the air to and from the UE.
For instance, when the base station has data to transmit to a UE, the base station could assign certain PRBs in the downlink traffic channel of a given TTI for use to carry the data to the UE, and the base station could then transmit to the UE in that TTI a downlink control information (DCI) message that specifies the assigned PRBs and then encode and transmit the data to the UE in the assigned PRBs. Per the DCI message, the UE could then receive the transmitted data on the assigned PRBs.
Likewise, when the UE has data to transmit to the base station, the UE could transmit a scheduling request to the base station, the base station could then assign certain PRBs in an uplink traffic channel of a given TTI for use to carry the data from the UE and could transmit to the UE, in advance of that TTI, a DCI message that specifies the assigned PRBs. And the UE could accordingly encode and transmit the data to the base station in the assigned PRBs in that TTI.
Further, when served by the base station on such a carrier, the UE may regularly monitor air-interface channel quality and provide the base station with channel-quality reports. And the base station may use these channel-quality reports as a basis to set a modulation and coding scheme for downlink and uplink communications between the base station and the UE, which the base station may indicate in its DCI messages to the UE.

Controlling use of carrier as secondary carrier for carrier-aggregation service


A memory tester including an algorithmic pattern generator (ALPG) for generating a test pattern as a digital signal based on vector data is provided with a digital-to-analog converter built in the memory tester or provided outside the memory tester. Thus, the function of a device under test (DUT) having the analog-to-digital converting function can be verified. In other words, an address signal included in the test pattern generated in the ALPG is used for generating an analog signal to be input to the DUT having the analog-to-digital converting function, not for address designation. A control unit compares an output digital signal generated in the DUT with the address signal generated in the ALPG as a test digital signal to detect the degree of agreement between these signals, thereby verifying the analog-to-digital converting function of the DUT. Consequently, a test system and a testing method capable of testing the analog-to-digital or digital-to-analog converting function of the DUT using the memory tester are obtained.

1. Field of the Invention
The present invention relates to a memory tester for verifying operations of a semiconductor memory by detecting whether or not a predetermined expected value is sent back when a predetermined signal is supplied to the semiconductor memory.
2. Description of the Background Art
A memory tester and a logic tester exemplify a semiconductor integrated circuit testing apparatus for testing a semiconductor integrated circuit such as a memory or a logic LSI (large scale integration). As indicated by their names, a memory tester is an apparatus for testing whether or not a memory operates normally, and a logic tester is an apparatus for testing whether or not a logic LSI operates normally.
On the other hand, semiconductor integrated circuits for image processing and for mobile communications are desired to have the capability of processing both of an analog signal and a digital signal. Thus, an analog/digital mixed LSI (mixed signal LSI) containing an analog signal processing part and a digital signal processing part is employed for such circuits. The mixed signal LSI is generally provided with a digital-to-analog converter for converting a digital signal into an analog signal and an analog-to-digital converter for converting an analog signal into a digital signal.
To test a device having the analog-to-digital (A/D) converting function and digital-to-analog (D/A) converting function such as the mixed signal LSI, an analog signal as well as a digital signal needs to be used. Thus, a mixed signal tester capable of outputting both of digital and analog signals is employed for this purpose.
FIG. 10 illustrates an exemplary structure of such mixed signal tester. A mixed signal tester T2 comprises: a control unit 10; a digital-to-analog (D/A) converter 11 for converting a digital signal S10 output from the control unit 10 into an analog signal S11 and outputting the signal to the outside; and an analog-to-digital (A/D) converter 12 for converting an analog signal S14 input from the outside into a digital signal S15 and outputting the signal to the control unit 10.
The control unit 10, which represents a central processing unit (CPU) or a digital signal processor (DSP) to which storing means (e.g., a read-only memory (ROM) and a random access memory (RAM)) is connected, is a functional component operated by predetermined software programs stored in the ROM and RAM. The control unit 10 controls the D/A converter 11 and the A/D converter 12, while exchanging a digital signal S12 with the outside via another path different from one leading to the D/A converter 11.
A device under test (DUT) 200 serving as the mixed signal LSI is connected to the mixed signal tester T2 through pin electronics PE. The pin electronics PE serve as an interface circuit for transmitting a signal from the mixed signal tester T2 to each pin of the DUT 200 and an output signal from each pin of the DUT 200 to the mixed signal tester T2. The pin electronics PE generally comprise, per pin, a driver DR for controlling a signal from the mixed signal tester T2 and a comparator CP for detecting whether an output signal from each pin of the DUT 200 has a value greater (or smaller) than a predetermined value.
To operate the driver DR and the comparator CP, a voltage source VS is provided, whose potentials at its both terminals are indicated by first and second reference potentials V1 and V2, respectively.
FIG. 11 illustrates an exemplary structure of the comparator CP. The comparator CP includes a High-side comparator C1 and a Low-side comparator C2. One side input terminals of the High-side comparator C1 and the Low-side comparator C2 are both supplied with an output signal S13 from the DUT 200. The other input terminal of the High-side comparator C1 is supplied with the first reference potential V1 through a High-side pad P1, and that of the Low-side comparator C2 is supplied with the second reference potential V2 through a Low-side pad P2.
Output signals S12a and S12b of the High-side comparator C1 and the Low-side comparator C2 are transmitted to the control unit 10, respectively, as the digital signal S12. The control unit 10 judges whether a malfunction occurs in the DUT 200 in accordance with the transmitted result. In the case that the signal S13 from the DUT 200 is an analog signal and thus no comparison need to be made at the comparator CP, the analog signal is output as the signal S14 from the pin electronics PE to the A/D converter 12 included in the mixed signal tester T2.
The mixed signal tester is capable of processing both digital and analog signals 15 and thus have improved convenience, whereas it is expensive due to the complexity of its device structure and that of information processing performed therein.
On the other hand, a memory tester, which processes a digital signal alone, is inexpensive because of its simple device structure and simple information processing compared to those of the mixed signal tester. However, the memory tester is incapable of processing an analog signal, and thus, incapable of testing a device having the A/D converting function and D/A converting function such as the mixed signal LSI.
FIG. 12 illustrates an exemplary structure of the memory tester. The memory tester T1c comprises: a control unit 1; an algorithmic pattern generator (ALPG) 2 for generating, on the basis of vector data VD, a test pattern as a digital signal to be supplied to a memory cell in each address in a DUT 300 serving as a memory; and a fail bit analyzer (FBA) 3 for analyzing a failure position in the DUT 300 when a failure is found in an output of the DUT 300, thereby replacing the failure position with a redundant circuit included in the DUT 300.
The control unit 1, which represents a CPU or a DSP to which storing means (e.g., ROM and RAM) is connected, is a functional component operated by predetermined software programs stored in the ROM and RAM. The control unit 1 controls the ALPG 2 and the FBA 3.
The DUT 300 is connected to the memory tester T1c through the pin electronics PE similar to those illustrated in FIG. 10. Each of signals from the ALPG 2 (an address signal S1a and a data signal S1b, both of which are 8-bit digital signals, for example) is transmitted to the DUT 300 through the pin electronics PE as a signal S2.
FIG. 13 is a flow chart showing an operation of the memory tester T1c. First, a test pattern to be supplied to the DUT 300 is designated as vector data VD and is input to the control unit 1 (step ST1). The vector data here represents data for designating what type of data (e.g., xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d) is to be stored in each of a plurality of memory cells arranged in row and column directions in the DUT 300.
Concrete examples of the vector data VD are shown in FIGS. 14 and 15. FIG. 14 shows an example of vector data that designates the contents of data for each memory cell by xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d in binary. FIG. 15 shows another example of vector data that designates the contents of data for each memory cell by applying a predetermined rule.
The respective vector data shown in FIGS. 14 and 15, whose X (row) addresses and Y (column) addresses are designated by, e.g., 8 bits, respectively, have data patterns like a checker flag (in which data is aligned with the contents inverted alternatingly as xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d . . . both in the X and Y directions). The vector data shown in FIG. 14 has the data contents inverted alternatingly as xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d . . . in the same Y address as the X addresses increase one by one. Invoked in the vector data shown in FIG. 15 is a program having a pattern name of CHK in which an algorithm for previously generating a pattern like a checker flag (e.g., algorithm for inputting data xe2x80x9c1xe2x80x9d to memory cells having X and Y addresses both in odd coordinates and those having X and Y coordinates both in even coordinates, while inputting data xe2x80x9c0xe2x80x9d to other memory cells) is stored.
The ALPG 2 exchanges a signal S0 with the control unit 1, thereby receiving controlling information and information on vector data VD from the control unit 1 and providing the control unit 1 with information on the operating condition thereof. The ALPG 2 then generates a test pattern on the basis of the vector data VD (step ST2), and supplies the pattern to the DUT 300 (step ST3c). More specifically, the ALPG 2 supplies the address signal S1a and the data signal S1b to the DUT 300 as the signal S2 through the pin electronics PE. Although illustration is omitted, the ALPG 2 also outputs a control signal to the DUT 300.
On the other hand, the signal S2 includes a signal output from the DUT 300 to the pin electronics PE. The output signal is input to the FBA 3 through the pin electronics PE as a signal S5.
The FBA 3 analyzes a failure position. The result of analysis is supplied to the control unit 1 as a signal S6 together with the output signal of the DUT 300. The control unit 1 verifies whether the output signal from the DUT 300 is in accordance with 20 the test pattern generated in the ALPG 2 (step ST4c).
It is desirable that a digital tester such as the above-described memory tester be capable of testing a device having the A/D converting function and D/A converting function such as the mixed signal LSI.
An object of the present invention is to provide a test system and a testing method capable of testing the A/D converting function or D/A converting function of a device under test using a memory tester which is less expensive than a mixed signal tester.
A first aspect of the present invention is directed to a test system. The test system includes a memory tester and a digital-to-analog converter. The memory tester includes a test pattern generating section for generating a predetermined test pattern to be supplied to a memory cell in each address in a memory device and a control unit for controlling the test pattern generating section. The digital-to-analog converter is one of digital-to-analog converters, one built in the memory tester and the other provided outside the memory tester. In the test system, the control unit is supplied with vector data for generating the predetermined test pattern. The test pattern generating section generates the predetermined test pattern on the basis of the vector data. A test digital signal included in the predetermined test pattern is converted into a test analog signal by the digital-to-analog converter to be supplied to a device under test having the analog-to-digital converting function. And the control unit compares the test digital signal with an output digital signal generated in the device under test by converting the test analog signal, thereby verifying the analog-to-digital converting function of the device under test.
In the test system, the test digital signal included in the predetermined test pattern is converted into the test analog signal by the digital-to-analog converter and to be supplied to the device under test. The control unit compares the test digital signal with the output digital signal generated in the device under test by converting the test analog signal, thereby verifying the analog-to-digital converting function of the device under test. This allows the memory tester to perform testing of the analog-to-digital converting function of the device under test.
Preferably, the test system further includes a storage device for storing the output digital signal and outputting the signal to the control unit.
In the test system, the storage device for storing the output digital signal and outputting the signal to the control unit is further provided. Thus, the control unit does not need to make a real-time comparison between the output digital signal and the test digital signal.
Preferably, in the test system, the storage device is a memory provided in a fail bit analyzer for analyzing a failure position in the memory device when a failure is found in an output of the memory device.
In the test system, the storage device is the memory provided in the FBA. Thus, there is no need to provide an additional storage device for the memory tester, but the memory provided inside the FBA which is generally built in the memory tester can be diverted for the storage device.
Preferably, in the test system, the control unit, in the comparison between the output digital signal and the test digital signal, judges that analog-to-digital conversion functions normally in the device under test when the signals are different only within a predetermined range of numerical values.
In the test system, the control unit, in the comparison between the output digital signal and the test digital signal, judges that analog-to-digital conversion functions normally in the device under test when the signals are different only within a predetermined range of numerical values. Thus, the percentage of devices under test passing a test can be increased by setting the predetermined range appropriately.
A second aspect of the invention is directed to another test system includes a memory tester and pin electronics. The memory tester includes a test pattern generating section for generating a predetermined test pattern to be supplied to a memory cell in each address in a memory device and a control unit for controlling the test pattern generating section. The pin electronics include a first digital-to-analog converter and a first comparator. In the test system, the control unit is supplied with vector data for generating the predetermined test pattern. The test pattern generating section generates the predetermined test pattern on the basis of the vector data. A test digital signal included in the predetermined test pattern is supplied to a device under test having the digital-to-analog converting function. A predetermined digital value designated by the control unit is converted into a first reference analog signal by the first digital-to-analog converter to be input to one input terminal of the first comparator. An output analog signal generated in the device under test by converting the test digital signal is input to the other input terminal of the first comparator. The first comparator compares the output analog signal generated in the device under test with the first reference analog signal, thereby supplying the result of comparison to the control unit as a first result digital signal. And the control unit verifies the digital-to-analog converting function of the device under test on the basis of the first result digital signal.
In the test system, the test digital signal included in the predetermined test pattern is supplied to the device under test having the digital-to-analog converting function. The first comparator compares the output analog signal generated in the device under test with the first reference analog signal, thereby supplying the result of comparison to the control unit as a first result digital signal. The control unit verifies the digital-to-analog converting function of the device under test on the basis of the first result digital signal. This allows the memory tester to perform testing of the digital-to-analog converting function of the device under test.
Preferably, in the test system, the pin electronics further include a second digital-to-analog converter and a second comparator. Another predetermined digital value designated by the control unit is converted into a second reference analog signal by the second digital-to-analog converter to be input to one input terminal of the second comparator. The output analog signal generated in the device under test is input to the other input terminal of the second comparator. The second comparator compares the output analog signal generated in the device under test with the second reference analog signal, thereby supplying the result of comparison to the control unit as a second result digital signal. And the control unit verifies the digital-to-analog converting function of the device under test also on the basis of the second result digital signal.
In the test system, the second comparator compares the output analog signal generated in the device under test with the second reference analog signal, thereby supplying the result of comparison to the control unit as a second result digital signal. The control unit verifies the digital-to-analog converting function of the device under test also on the basis of the second result digital signal. Thus, setting the predetermined digital values different from each other such that the first and second reference analog signals have values different from each other allows the control unit to verify whether the output analog signal generated in the device under test has a value that falls within a range limited by the values of the respective reference analog signals.
A third aspect of the invention is directed to a testing method. The testing method uses a memory tester and a digital-to-analog converter. The memory tester includes a test pattern generating section for generating a predetermined test pattern to be supplied to a memory cell in each address in a memory device and a control unit for controlling the test pattern generating section. The digital-to-analog converter is one of digital-to-analog converters, one built in the memory tester and the other provided outside the memory tester. The testing method includes the steps of: (a) supplying the control unit with vector data; (b) generating the predetermined test pattern; (c) converting a test digital signal included in the predetermined test pattern into a test analog signal by the digital-to-analog converter; and (d) comparing, in the control unit, the test digital signal with an output digital signal generated in the device under test by converting the test analog signal, thereby verifying the analog-to-digital function of the device under test. The vector data is for generating the predetermined test pattern. The predetermined test pattern is generated in the test pattern generating section on the basis of the vector data. The test digital signal is converted to be supplied to a device under test having the analog-to-digital converting function.
With the method, a test digital signal included in the predetermined test pattern is converted into a test analog signal by the digital-to-analog converter to be supplied to the device under test. The control unit compares the test digital signal with the output digital signal generated in the device under test by converting the test analog signal, thereby verifying the analog-to-digital converting function of the device under test. This allows the memory tester to perform testing of the analog-to-digital converting function of the device under test.
Preferably, the testing method further uses a storage device for storing the output digital signal and outputting the signal to the control unit. The testing method further includes the step of (e) storing the output digital signal in the storage device.
With the method, the storage device for storing the output digital signal and outputting the signal to the control unit is further provided. Thus, the control unit does not need to make a real-time comparison between the output digital signal and the test digital signal.
Preferably, in the testing method, the storage device is provided in a fail bit analyzer for analyzing a failure position in the memory device when a failure is found in an output of the memory device.
With the method, the storage device is a memory provided in the FBA. Thus, there is no need to provide an additional storage device for the memory tester, but the memory provided inside the FBA which is generally built in the memory tester can be diverted for the storage device.
Preferably, in the testing method, the control unit, in the comparison between the output digital signal and the test digital signal, judges that analog-to-digital conversion functions normally in the device under test when the signals are different only within a predetermined range of numerical values.
With the method, the control unit, in the comparison between the output digital signal and the test digital signal, judges that analog-to-digital conversion functions normally in the device under test when the signals are different only within a predetermined range of numerical values. Thus, the percentage of devices under test passing a test can be increased by setting the predetermined range appropriately.
A fourth aspect of the invention is directed to another testing method. The testing method uses a memory tester and pin electronics. The memory tester includes a test pattern generating section for generating a predetermined test pattern to be supplied to a memory cell in each address in a memory device and a control unit for controlling the test pattern generating section. The pin electronics include a first digital-to-analog converter and a first comparator. The testing method includes the steps of: (a) supplying the control unit with vector data; (b) generating the predetermined test pattern; and (c) supplying a test digital signal included in the predetermined test pattern to a device under test having the digital-to-analog converting function. The vector data is for generating the predetermined test pattern. The predetermined test pattern is generated in the test pattern generating section on the basis of the vector data. In the testing method, a predetermined digital value designated by the control unit is converted into a first reference analog signal by the first digital-to-analog converter to be input to. one input terminal of the first comparator. An output analog signal generated in the device under test by converting the test digital signal is input to the other input terminal of the first comparator. The first comparator compares the output analog signal generated in the device under test with the first reference analog signal, thereby supplying the result of comparison to the control unit as a first result digital signal. The testing method further includes the step of (d) verifying the digital-to-analog converting function of the device under test in the control unit on the basis of the first result digital signal.
In the method, the test digital signal included in the predetermined test pattern is supplied to the device under test having the digital-to-analog converting function. The first comparator compares the output analog signal generated in the device under test with the first reference analog signal, thereby supplying the result of comparison to the control unit as a first result digital signal. The control unit verifies the digital-to-analog converting function of the device under test on the basis of the first result digital signal. This allows the memory tester to perform testing of the digital-to-analog converting function of the device under test.
Preferably, in the testing method, the pin electronics further include a second digital-to-analog converter and a second comparator. Another predetermined digital value designated by the control unit is converted into a second reference analog signal by the second digital-to-analog converter to be input to one input terminal of the second comparator. The output analog signal of the device under test is input to the other input terminal of the second comparator. The second comparator compares the output analog signal generated in the device under test with the second reference analog signal, thereby supplying the result of comparison to the control unit as a second result digital signal. And the control unit verifies the digital-to-analog converting function of the device under test also on the basis of the second result digital signal, in the step (d).
In the method, the second comparator compares the output analog signal generated in the device under test with the second reference analog signal, thereby supplying the result of comparison to the control unit as a second result digital signal. The control unit verifies the digital-to-analog converting function of the device under test also on the basis of the second result digital signal. Thus, setting the predetermined digital values different from each other such that the first and second reference analog signals have values different from each other allows the control unit to verify whether the output analog signal generated in the device under test has a value that falls within a range limited by the values of the respective reference analog signals.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

Test system and testing method using memory tester

Ryoden Semiconductor System Engineering Corporation


An example electron beam drawing apparatus includes an electron beam emitting unit which emits an electron beam, a rotary stage which rotatably supports a turntable for retaining a drawing object, and a sample stage which is supported by the turntable in a range including a rotating center of the turntable to retain an adjustment sample. A rotationally symmetrical pattern such as a concentric pattern and a radial pattern can be drawn in the drawing object by irradiating the drawing object with the electron beam during rotation of the turntable. Before the pattern is actually drawn in the drawing object, beam adjustment and rotating center adjustment are performed using an adjustment sample. The adjustment sample is retained by the sample stage, and the sample stage is supported by the turntable in the range including the rotating center of the turntable. Therefore, the beam adjustment and the rotating center adjustment can be performed using the adjustment sample supported by the turntable, and the different stage for placing the adjustment sample is not required, which allows the apparatus to be miniaturized.

Recently, there have been developed various recording mediums in which large-capacity image/sound data and digital data can be recorded. An optical disc such as a DVD (Digital Versatile Disc) can be cited as an example of this kind of recording medium. There has also been developed a large-capacity disc such as a magnetic recording hard disc.
However, in producing a conventional master disc with a visible-range or ultraviolet-range laser beam, recording resolution is restricted by a spot diameter of a recording laser beam. In order to increase the recording density of the above-mentioned disc, it has been studied to perform the production, so-called cutting, of the master disc by a master disc producing apparatus using an electron beam, which has the spot diameter smaller than that of the visible-range or ultraviolet-range laser beam and by which the recording resolution can be improved.
In the production of the master disc, after the electron beam resist is applied onto a substrate, the electron beam is irradiated in a vacuum atmosphere. A latent image of a fine pattern is formed on the electron beam resist by the irradiation of the electron beam (electron beam exposure). A development process, a patterning process, and a resist removing process are performed to the substrate, and a fine convexoconcave pattern is formed on the substrate. Patent Documents 1 and 2 disclose a master disc producing apparatus in which the electron beam is utilized.
In the above-mentioned master disc producing apparatus, the disc substrate onto which the electron beam resist is applied is irradiated with the electron beam while rotated on a rotary stage, so that the fine pattern such as a concentric pattern and a radial pattern is drawn on the disc substrate. Therefore, before the pattern is drawn with the electron beam, it is necessary that objective lens strength and an astigmatism corrector in an electron beam optical system be previously adjusted to narrow the beam diameter. For this reason, it is necessary that a beam adjustment sample be attached in the apparatus or on the substrate. Furthermore, in order to correctly form the concentric or radial fine pattern on the disc substrate, it is necessary that a rotating center of the rotary stage be specified to match a drawing origin of the electron beam with the rotating center of the rotary stage, i.e., with a polar coordinate origin of a rotary linear motion stage system.
Non-Patent Document 1 discloses a beam diameter adjustment technique, wherein the fine-structured adjustment sample attached to a micro-adjustment stage adjacent to the turntable is matched with a substrate height, and the focus adjustment is performed by an electron microscope function possessed by the drawing apparatus of itself such that the resolution of the adjustment sample becomes the best in the electron microscope image.
Non-Patent Document 2 discloses a rotating center adjustment technique, wherein a grating is attached to a center portion of the turntable, and the turntable is rotated to adjust a position of the electron beam.
However, in the beam diameter adjustment technique disclosed in Non-Patent Document 1, because it is necessary that the adjustment sample be moved in an electron beam irradiation range during the adjustment, it is necessary to lengthen a movement distance of a radial-direction moving linear motion stage, which results in a problem that the whole drawing apparatus becomes large. In the case where the drawing apparatus has a function of applying a decelerating voltage for decelerating the electron beam to the substrate as a drawing target, usually the stage on which the adjustment sample is placed is not equipped with a function of applying the decelerating voltage. Therefore, the focal height of the electron beam is different between the substrate surface having a potential of the applied decelerating voltage and the adjustment sample having a ground potential because the decelerating voltage is not applied. Accordingly, in order to correctly perform the beam adjustment in the actual decelerating voltage applied state, decelerating voltage applying means is separately required for the adjustment sample, which results in problems such as complication of an apparatus configuration and cost increase.
On the other hand, in the rotating center adjustment technique disclosed in Non-Patent Document 2, time and effort are required because the grating is attached only in the adjustment while detachment of the grating is required in the actual drawing.
Patent Document 1; Japanese Patent Application Laid-Open No. 2002-367241
Patent Document 2: Japanese Patent Application Laid-Open No. 2003-36572
Non-Patent Document 1. JPN. J. Appl. Phys. Vol. 40, pp 1653-1660, Oct. 30, 2000, "High-Density Recording Using an Electron Beam Recorder", by Yasumitu Wada, Masahiro Katsumura, Yoshiaki Kojima, Hiroaki Kitahara, and Tetsuya Iida
Non-Patent Document 2: Applied Optics, Vol. 33, No. 10, pp. 2032, April, 1994, "Electron-beam writing system and its application to large and high-density diffractive optic elements", Shiro Ogata, Masami Tada and Masahiro Yoneda


A terrain imaging apparatus and method for indicating to a user the location and distance of moving objects from a user. A transmitting means transmitts a coherent radiation beam to distant objects and receives back the coherent radiation beam reflected from the objects. A communicating means indicates the direction and distance of objects moving in that field relative to the user by determining the distances to the objects from the transmitting and receiving means and the direction in which the beam is directed to synthesize a vector field image of the terrain based on a set of direction measurements and corresponding range measurements and indicating the direction the user is facing relative to the terrain image.

This invention relates to terrain imaging using coherent beam radiation. It is usable to detect short range objects and determine the movement of the objects. It can be used by a blind person to avoid running into obstacles. Law enforcement and security personnel can use it to detect the location and movement of persons which are not visible to the eye such as at night.
In the last several decades, several electronic techniques have been tried to develop methods to image the near field terrain of an area for circumnavigating through and around obstacles and for protection against intrusion of an area. These methods have suffered from a common problem of poor resolution and false information or images as a result of background objects moving, such as leaves blowing, birds flying or small animals.
One of the technologies employed for intrusion detection or for terrain imaging has been ultrasonics. An ultrasonic acoustical signal is transmitted into space is reflected from objects in the near field to the transmitter. By ascertaining the return signal level or by measuring the time delay, you can infer a range of the object from the transmitter to the receiver.
A primary problem with the ultrasonics is the very low resolution of distinguishing objects. This is a result of the difficulties in focusing the ultrasonic sound waves into a small beam that doesn't disperse. The relatively low resolution of an image by such a method makes it of less value to the user in trying to circumnavigate himself through an area of obstacles. When this method is used for intrusion detection, the low resolution is not the only problem. Ultrasonics is very susceptible to motion from blowing bushes, plants or small animals moving about. These objects, when in the field of view, tend to give a high number of false alarms. Other technologies have attempted to use light or microwave emissions to detect the presence of objects, but have relied largely on the return signal strength or on triangulation to determination what the range is to the reflecting objects. These methods of range determination suffer from low resolution since triangulation can only be used for a very near field. Signal strength is subject to other sources of errors, in particular, the type of target light hits and hence the amount that is reflected back.
The inability to resolve accurate ranges well as the azmith of those ranges have made these methods of limited value. Failure to use computational devices to interpret what image is generated has further reduced the effectiveness of these methods.
One type of light intrusion detection that has been used successfully and extensively is the photo-electric beam devices. These devices require some sort of an inflector that is the receiver at the end of a light beam to operate. This method has not been used for scanning but does not produce any accurate image of the surrounding terrain. Furthermore, this method does not provide range information about intrusions.
Methods of passive infrared emissions have also been used for intrusion detection and for a means to avoid obstacles. These methods do not provide good range information and provide no azmith information and do not generate good images.
Video based systems by their very nature provide a very high definition image. However, translating this image information into a format usable by the blind or by a computer is a problem of great complexity. While it is possible to use video systems for motion detection in an intrusion scenario, they are plagued by high false alarm rates since any change in light causes an alarm signal. This method generally requires a stable closed environment in which to work. Thus, a method that can provide moderate resolution image of only 2 dimensions provides a means that can easily be interpreted by computational methods or by the blind, who can only process a limited amount of stimuli, and interpret as an image.
An object of the invention to provide a method and apparatus which can be used by a blind person to ascertain obstacles and to indicate the location and movement of the obtacles.
Another object of the invention to provide a method and apparatus which can be used by any person at night to ascertain obstacles and to indicate the location and movement of the obtacles.
Another object of the invention to provide a method and apparatus which can be used to ascertain short range obstacles and to indicate the location and movement of the obtacles.
Another object of the invention to provide a method and apparatus which can be used to ascertain obstacles and to indicate the location and movement of the obtacles in security monitoring situations.
Other objects of the invention will be apparent from the specification and claims.