A trigger-type drinker for poultry and small animals including a water retaining disc at the free end of the trigger pin is disclosed. The disc is generally flat with an upturned lip around the perimeter thereof. A residual water drop or water leaking from the drinker runs down the trigger pin and collects on the disc, contained by the lip. The disc allows several drops of water to collect at the bottom of the pin. The increased amount of water on the pin assists in attracting birds to the drinker. When the bird actuates the drinker, the disc tilts toward the bird, thereby causing the water to run across the surface of the disc and into the bird's mouth. Thus, the disc assists in directing more water to the bird. Additionally, because the side of the disc farthest from the bird tilts upward as the bird actuates the drinker, it not only acts as a ramp for the water to flow downward toward the bird, but also acts as a retaining wall, preventing the water from flying off the opposite side of the pin Accordingly, the floor of the poultry house remains drier.

This application relates to nipple or trigger-type poultry watering devices, and, more specifically, to an improved method for retaining water on the trigger pin of such a drinker.
Trigger-type watering devices are commonly used for delivering water to poultry in poultry houses. Such drinkers generally include a cylindrical chamber through which the water flows. One end of the chamber is adapted to be fit to a water supply line and includes an inlet for allowing water to pass from the supply line into the chamber. The other end of the chamber generally includes an opening to allow fluid to flow out of the chamber. A valve seat and valve member are normally disposed within the chamber to prevent water from flowing out when the drinker is not being actuated by a bird. A valve actuating member is normally housed partially within the chamber and extends through the chamber outlet. The valve actuating member normally includes a cylindrical pin portion, which the bird pecks or lifts, thereby unseating the valve member from the valve seat and allowing water to flow through the chamber and out to the bird. When actuation ceases, the valve member returns to the valve seat, thereby shutting off the water flow.
In many instances, a drop of water will remain hanging from the end of the pin after the bird has finished drinking. Similarly, a drop of water may also collect on the pin if the drinker leaks. The residual drop of water on the pin serves a useful function in that it attracts birds to the drinkers. When a thirsty bird sees the residual drop of water on the pin, it knows that it should go to the drinker to get water. However, it my also happen that the residual drop of water is so large that it eventually falls from the pin onto the floor of the poultry house. Additionally, if the watering system is vibrated, such as when a bird bumps into it, the droplet may fall from the pin. Furthermore, if a large or strong bird pecks at the pin forcefully, the water drop may fly off the pin on the side opposite the bird. Accordingly, the bird does not receive any water and the floor of the poultry house does. Aside from the fact that the poultry do not receive as much water under these circumstances, the health of the poultry is also threatened by the increased wetting of the manure on the floor of the poultry house. The wetter the manure is, the easier it is for bacteria and disease to breed in the poultry house.
Accordingly, it is an object of the present invention to provide an improved trigger-type drinker for poultry and small animals.
Another object of the present invention is to provide a trigger-type drinker that reduces the amount of water on the floor of the poultry house.
Yet another object of the present invention is to provide a trigger-type drinker that better attracts poultry to the water source.
Still another object of the present invention is to provide a trigger-type drinker that better directs the water flow toward the bird activating the drinker.
These and other objects of the present invention are attained by the provision of a water retaining disc at the free end of the trigger pin. The disc is generally flat with an upturned lip around the perimeter thereof. The residual water drop or water leaking from the drinker runs down the trigger pin and collects on the disc, contained by the lip. The disc allows several drops of water to collect at the bottom of the pin. The increased amount of water on the pin assists in attracting birds to the drinker. When the bird actuates the drinker, the disc tilts toward the bird, thereby causing the water to run across the surface of the disc and into the bird's mouth. Thus, the disc assists in directing more water to the bird. Additionally, because the side of the disc farthest from the bird tilts upward as the bird actuates the drinker, it not only acts as a ramp for the water to flow downward toward the bird, but also acts as a retaining wall, preventing the water from flying off the opposite side of the pin Accordingly, the floor of the poultry house remains drier.
Other objects, advantages and novel features of the present invention will now be readily apparent to those skilled in the art upon consideration of the following detailed drawings and description.


Embodiments of printer optical sensing error determination are disclosed.

Printers and other image producing devices sometimes include optical sensors that are used to monitor printhead or pen position, e.g., in relation to a print area or print zone. These optical sensors often take erroneous measurements and may not provide an orthogonally accurate measuring system or device for the printer.

Printer optical sensing error determination

HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.


Muffler with catalytic converter (1) essentially arranged in direct connection with a combustion engine's exhaust port and mainly intended for portable working tools such as chain saws. A spark arrester screen (3), i.e. a structure (3) which at least partly contains a wire mesh (4) and a net (4), usually made of metallic material, is located in the exhaust gas flow downstream a converter element (5). In connection with the spark arrester screen (3), upstream or downstream the screen, flow dividers (8, 13, 9) are arranged.

For portable power equipment such as chain saws, mufflers have since long in some cases been equipped with so called spark arresters. This arrester was then often positioned at the outlet of the muffler with the function to trap any sparks so that these did not exit the muffler. For a two-stroke engine chain saw for instance, the exhaust gases have a temperature of approximately 600 degrees C. when entering such a spark arrester screen. The mesh is commonly made of stainless acid proof material in order to stand such high thermal loads.
Small combustion engines have since long had comparatively high exhaust emission levels. This particularly applies to two-stroke type engines, because the combustion is more incomplete than in the case of four-stroke engines. Increased demands concerning exhaust emissions from small engines have however resulted in the introduction of catalytic converters for different types of small engines. This also applies to small engines for portable equipment such as chain saws etc.. Several different solutions for so called catalyst mufflers, particularly for chain saws, have emerged. These mufflers are usually connected directly to the exhaust port of the cylinder. A catalytic element is placed inside the muffler, and in the element an exotherm chemical reaction takes place. For chain saws for instance, this implies a temperature increase inside the muffler from around 600 degrees C. before the catalytic element to around 1000 degrees C. after the catalytic element. The applicant does not know of any case where a muffler with a catalytic converter has been equipped with a spark arrester positioned in the exhaust flow downstream the catalyst element. Due to the high exhaust gas temperature after the element, the working conditions for such a spark arrester become very difficult. At the same time, it is in many cases preferable to position a spark arrester downstream the catalytic element in order to reduce risks for fire and accidents when using the power equipment.
The muffler with catalytic converter in accordance with the invention thus is essentially characterized in that a spark arrester, i.e. a structure that at least partly contains a wire mesh or a screen, usually made of metallic material, is positioned in the exhaust flow downstream a catalytic element. Furthermore the spark arrester screen is usually positioned in close proximity to the exhaust outlet. In order to withstand the high thermal loads on the spark arrester screen, so that a reasonable life time can be obtained, a number of different measures are used, on their own or in combination with each other. Partly design measures on the spark arrester screen itself to achieve a well distributed heating of the screen and good cooling, e.g. measures for separation of the exhaust flow. Partly restriction are use in the muffler upstream to achieve increased turbulence in the exhaust stream and thereby cause better distribution across the spark arrester screen and at the same time achieve better cooling of the exhaust stream before it reaches the spark arrester screen. These and other characteristics and advantages will be apparent from the ensuing description of the preferred embodiments and with the support of the drawing figures.

Spark arresting structure for a muffler having a catalytic converter


Systems and methods for operating a powertrain or driveline that includes an engine and a belt integrated starter/generator are described. In one example, the belt integrated starter/generator is used to start an engine unless vehicle operating conditions indicate that the belt integrated starter/generator may be having difficulty starting the engine.

A vehicle may include a starter that selectively engages an engine during engine starting. The vehicle may also include a belt integrated starter/generator (BISG) to charge a battery of a vehicle, provide propulsion power to the vehicle, and to start an engine of the vehicle. The BISG may rotate the engine during starting and it may rotate the engine while generating less noise, vibration, and harshness as compared to the starter. However, the starter may provide improved engine cranking while starting the engine at lower ambient temperatures as compared to the BISG because of belt slip. While it may be desirable to start the engine via the BISG each time the engine is started, it may be difficult to predict if the BISG may have sufficient torque capacity to start the engine each time the engine is requested to be started. Therefore, the starter may be used to start the engine more frequently than may be desired to ensure that the engine starts.
The inventors herein have recognized the above-mentioned issues and have developed an engine operating method, comprising: rotating an engine via a belt integrated starter/generator (BISG) in response to an engine start request; and engaging a starter to rotate the engine while the engine is rotated via the BISG, wherein the starter is engaged in response to a rate of change in battery voltage that is greater than a threshold rate of change.
By selectively engaging the starter while the BISG is rotating the engine, it may be possible to reliably start the engine when the BISG's capacity to start the engine may be lower than is desired. In addition, if the BISG's capacity to start the engine is determined to be higher, the starter may not be engaged so that engine starting noise and vibration may be reduced. Thus, the BISG may be used to start the engine, but if the torque capacity of the BISG is less than may be desired, then the starter may be engaged to start the engine. For example, if a battery has a reduced charge storing capacity or if vehicle operating conditions are conducive to BISG belt slip, the engine may be started via the starter. Since the torque capacity of the BISG is partially dependent on battery output, BISG torque capacity may be indicated by the rate of reduction in battery voltage when the engine is being cranked via the BISG. If the absolute value of the rate of battery voltage change is greater than a threshold rate of change, it may be an indication that the engine may not be started solely via the BISG or by simultaneously engaging the starter and rotating the engine via the BISG.
The present description may provide several advantages. In particular, the approach may improve the probability of engine starting when BISG torque capacity is low due to battery charge capacity being lower than may be desired. Further, the approach may reduce the possibility of further battery degradation that may be related to sourcing larger amounts of electric current. Further still, the approach may improve selection of devices to crank an engine during starting.
The above advantages and other advantages, and features of the present description will be readily apparent from the following Detailed Description when taken alone or in connection with the accompanying drawings.
It should be understood that the summary above is provided to introduce in simplified form a selection of concepts that are further described in the detailed description. It is not meant to identify key or essential features of the claimed subject matter, the scope of which is defined uniquely by the claims that follow the detailed description. Furthermore, the claimed subject matter is not limited to implementations that solve any disadvantages noted above or in any part of this disclosure.


A control system for controlling a gas powered water heater includes a power system to provide electrical power, a valve control system to selectively hold a main gas valve in an open position, a valve pick system to selectively pick the main gas valve from a closed position to the open position, a safety system to prevent the valve control system from holding the main gas valve in the open position, and a controller. The controller is electrically powered by the power system and communicatively coupled to the valve control system, the valve pick system, and the safety system. The controller is configured to control operation of the main burner and the main gas valve using the valve control system, the valve pick system, and the safety system to provide water heated to substantially a set point temperature.

Storage water heaters may be utilized domestically and industrially in various applications. Domestically, a storage water heater is used for generation of hot water that may be used for bathing, cleaning, cooking, space heating, and the like.
A conventional gas fired water heater includes a water storage tank and gas fired burner assembly for heating water within the tank. In operation, combustion gases generated by the firing of the burner assembly may be directed upwardly through a flue pipe via a hood. The combustion gases serve to transfer heat to the water contained within the storage tank. The top of the water heater may include suitable fittings for connection to a supply of water and a water distribution system with a water inlet provided with a dip tube, which serves to direct the inflow of cold water to the bottom of the tank.
This Background section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.

Systems and methods for controlling gas powered appliances


A coil component includes a base body containing metal magnetic particles and a binder binding together the metal magnetic particles and having a first surface extending along a coil axis and a second surface opposing the first surface, a first external electrode provided on the base body, a second external electrode provided on the base body, and a coil conductor electrically connected to the first and second external electrodes and extending around the coil axis. In one embodiment, the coil conductor has a winding portion, the winding portion has first conductor portions and one or more second conductor portions smaller in number than the first conductor portions, and the first and second conductor portions alternate with and are connected to each other, and a distance between the first conductor portions and the first surface is less than a distance between the second conductor portions and the second surface.

There are conventional coil components including a magnetic base body formed of a magnetic material, an external electrode provided on the surface of the magnetic base body, and a coil conductor provided in the magnetic base body and extending around a coil axis.
Coil components are, for example, inductors. Inductors are passive elements used in electronic circuits. For example, inductors eliminate noise in power source or signal lines. A conventional inductor is disclosed in Japanese Patent Application Publication No. 2018-0101732 ("the '732 Publication"). As disclosed in '732 Publication, there is a demand for more compact inductors. Here, coil components are required to have high inductance.
Metal-composite magnetic base bodies are known as the magnetic base bodies for electronic parts such as inductors. In the metal-composite magnetic base bodies, a large number of metal magnetic particles are bound together by a binder made of a resin material. The metal-composite magnetic base bodies can be made by, for example, pouring a sealing material containing a metal magnetic material and a resin into a mold having a conductor placed therein and applying pressure to the sealing material and conductor in the mold. Such metal-composite magnetic base bodies are disclosed in Japanese Patent Application Publications Nos. 2016-208002 and 2018-041955.
Containing a binder made of a resin material, the metal-composite magnetic base bodies are capable of absorbing water. Therefore, the magnetic base body contains water. When a coil component including such a metal-composite magnetic base body is mounted on a substrate using a reflow process, the magnetic base body experiences a sudden temperature rise. This causes the water contained within the magnetic base body to move to the surface of the magnetic base body and eventually evaporate into the air through the surface of the magnetic base body. When moving from within the magnetic base body to the surface, the water may follow only some of the routes within the magnetic base body. If such is the case, these routes experience a rise in pressure, which is likely to create micro cracks near these routes.
If magnetic base bodies suffer from micro cracks, the coil components may exhibit lower inductance. When water evaporates from the magnetic base bodies, the water preferably follows a plurality of diverse routes from within the magnetic base body to the surface.

Coil component, circuit board, and electronic device


A device for controlling a power distribution to subsystems which has a power input to be connected to a power source, a primary power output to be connected to a primary device, at least one secondary power output to be connected to at least one secondary device; sensing unit for sensing when a current level falls below a threshold in response to the primary device being turned off and when the level current raises above a threshold in response to the primary device being turned on; and executing unit operatively connected with the sensing unit and operative for interrupting a power supply to the at least one secondary device when the sensing unit sense the current level below the threshold and supplying power to the at least one secondary device when the sensing unit sense the current level above the threshold correspondingly; and means for limiting voltage across said sensing means so as to limit heat produced by said sensing means but at the same time to allow tripping of said sensing means.

The present invention relates to devices for controlling a distribution of power to subsystems, for example to a main device and at least one secondary device or a plurality of secondary devices.
More particularly, the present invention relates to the above mentioned devices formed as electrical power strips and power control sensors which can be used with new devices having two modes of operation, standby or off and full on, with the use of main device or secondary devices.
One type of an electrical distribution device is the power strip or power control center, which generally comprises of a row of power outlets, switched or unswitched, to distribute power to a primary device and secondary device(s) from a standard outlet (e.g., wall outlet). Some power strips and control centers contain options like circuit breakers, fuses and/or surge protectors, for example.
In newer personal computers the system can turn itself off and is controlled by the operating system. During the system shutdown, there is a delay in which the operator must wait for the system to finish before turning off the secondary device(s). Depending on the operating software and programs, this can be a long time. Using this invention, the user may leave after the shutdown is started. When the system finishes and switches off or to the standby mode, the secondary device(s) will be turned off.
When used with computer devices, each device is plugged into a separate outlet with the computer plugged into the main outlet. When the computer is turned on, the current level increases to a high enough level to turn on the secondary device(s). Other constant power outlets may also be included for wake up devices, such as modems capable of bringing the system out of standby mode.
U.S. Pat. No. 4,659,941 discloses a power strip where the main outlet current controls the secondary device(s) as shown in FIG. 2. Here, the secondary switch and trigger device are the same. In this configuration, the main device must draw current at the start of each cycle of line power for the triac to trigger correctly. With high efficiency supplies, this is never the case because they only draw power during the peak voltage of the line power. So, when used with a PC or newer video/audio equipment, the voltage to the secondary outlets will not be a sine wave like the voltage from the wall outlet. This waveform can damage the secondary device(s). The second problem is personal computers and newer video/audio equipment do not turn off completely, but remain in a standby mode so they can turn themselves on at a given time or occurrence. Because of this, the secondary device(s) will never be turned off, defeating the purpose of the power strip""s use.
U.S. Pat. Nos. 4,731,549 and 4,970,623 are methods for controlling secondary device(s). Both require internal power supplies and many components, making them too expensive for mass production and difficult to fit in a standard power strip.
Accordingly, it is an object of present invention to provide a device for controlling distribution of power to subsystems, which avoids the disadvantages of the prior art.
In keeping with these objects and with others which will become apparent hereinafter, one feature of present invention resides, briefly stated, in a device for controlling a power distribution to subsystems which has a power input to connected to a power source, a primary power output to be connected to a primary device, at least one secondary power output to be connected to at least one secondary device; sensing means for sensing when a current level falls below a threshold in response to the primary device being turned off and when the level current raises above a threshold in response to the primary device being turned on; executing means operatively connected with said sensing means and operative for interrupting a power supply to said at least one secondary device when the sensing means sense the current level below the threshold and supplying power to said at least one secondary device when said sensing means sense the current level above the threshold; and means for limiting voltage across said sensing means so as to limit heat produced by said sensing means but at the same time to allow tripping of said sensing means.
In accordance with a further feature of present invention, the inventive device further has time delay means which is located between said sensing means and said executing means and is operative for delaying interruption of power supply or supply of power to the at least one secondary device in response to the sensing of the current level below the threshold or above the threshold by the sensing means correspondingly. The time delay means can be formed as a capacitor and resistors arranged between the sensing means and the executing means.
In accordance with a further embodiment of the present invention, the sensing means can be formed as a current sensing resistor arranged in series with a power input of the device and a triac connected to the resistor, for example through another resistor.
The executing means can be formed for example as a solid state DC relay, as an AC mechanical relay, as a solid state AC relay, etc.
The novel features which are considered as characteristic for the present invention are set forth in particular in the appended claims. The invention itself, however, both as to its construction and its method of operation, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.

Device for controlling power distribution to subsystems


The memory card is comprised of memory that stores a user name and password for each respective network address or universal resource locator (URL). The information is encrypted to preclude unauthorized access to the memory. A controller controls operation and access to the card. A bus interface couples the card to various buses, such as a universal serial bus. When the card is attached to an electronic device that is accessing a particular URL, the consumer enters the password or other unlock request information. Once the unlock request is validated, the user name and password associated with that particular URL is transmitted to the browser on the electronic device that is requesting the information.

1. Field of the Invention
The present invention relates generally to electronic password protection. Particularly, the present invention relates to the storing of electronic passwords in a portable memory device.
2. Description of the Related Art
With the increasing use of the Internet for commercial purposes, the average consumer is being overwhelmed with "usernames" and their associated passwords. For example, to log on to an Internet news site, the consumer may have to generate their own six to twelve character user name as well as a password. These phrases must then be used whenever the consumer wishes to log on to that particular web site.
Most web sites require or at least strongly suggest the use of usernames and passwords. Financial transactions, in the interest of security, require such protection. This causes the consumer to face many problems associated with user name and password use.
For example, the web site may generate a user name and/or password for the consumer. These phrases are typically very cryptic, making them difficult to remember.
If the consumer desires to access dozens of web sites that require usernames and passwords, he or she must track each of these sites and its associated user name/password. The consumer may decide to write the information down. However, losing this information would then leave the protected information vulnerable to misuse. For example, if the consumer lost his or her user name and password for Internet banking, those accounts may be accessed by whoever finds the codes.
For convenience, the consumer may decide to make all of his or her user name/passwords the same for each web site. However, various web sites have different rules for the generation of such protection. One site may require that the password be only four characters and include at least one number. If the consumer has already generated a generic password for other sites that is six alphabetic characters in length, this will cause the consumer to generate and track the new password. There is a resulting need for a portable memory device that stores and protects all of a consumer's usernames and password protection information.

Method and apparatus for storage of usernames, passwords and associated network addresses in portable memory


An analog soft-start circuit for a switching regulator (e.g., a buck converter) including an analog ramp circuit and an open-loop analog voltage clamp circuit. The voltage ramp circuit utilizes a two-stage current divider circuit to generate a very low, stable current signal, and an integrator circuit including a relatively small, integral capacitor to generate the ramp voltage signal in response to the very low current signal. The analog voltage clamp circuit clamps the regulated output signal to the ramp voltage until the ramp voltage signal increases to a predetermined voltage level, thereby causing the regulated output voltage to exhibit the desired soft-start characteristics. The analog clamp circuit includes a current mirror circuit that generates a clamp current that pulls down the error amplifier output stage via a clamping element (e.g., a diode) until the ramp voltage signal reaches a predetermined level.

Switching-type regulators typically include a high current switch (e.g., a MOSFET) along with an oscillator and pulse width modulator (PWM) that can operate the switch and vary its duty cycle as a function of a feedback or control voltage input. When combined with appropriate external components, such regulators can provide a regulated direct current (DC) voltage output signal. Buck converters are switching-type voltage regulators in which the output voltage is substantially lower ("stepped down") than an applied input voltage. In contrast, up-converters are switching-type voltage regulators in which the regulated output exceeds the input supply voltage, and positive-to-negative or negative-to-positive polarity converters are switching-type voltage regulators in which the regulated output is inverted. In terms of power supply efficiency switching-type regulators can operate at about 90% or better.
FIG. 3 is a diagram showing a simplified circuit including a conventional buck converter 10. Buck converter 10 includes an error amplifier 50 that receives a reference voltage VREF on its non-inverting input and a feedback signal VFB on its inverting signal. The output signal VEA-OUT from error amplifier 50 is applied to one input terminal of a pulse width modulator (PWM) circuit 70, and a second input terminal of PWM circuit 70 is connected to receive an oscillating ramp signal VOSC-RAMP from an oscillator 80. The PWM circuit 70 compares error amplifier output signal VEA-OUT with oscillating ramp signal VOSC-RAMP to produce a square wave signal VPULSE having a duty cycle whose instantaneous value is related to the voltage level of error amplifier output signal VEA-OUT. Square wave signal VPULSE is applied to the gate of a power transistor 75, which generates a regulated output voltage VOUT that is applied to a load represented by inductor LL, a capacitor CL, and a resistor RL. By feeding back a portion of regulated output voltage VOUT via a suitable feedback circuit (e.g., the divider formed by resistors R1 and R2), the duty cycle of PWM circuit 70 can be maintained at a level that generates the duty cycle needed to produce the desired regulated voltage VOUT.
A problem associated with conventional buck converters is voltage overshoot at start up. Before start up, load capacitance CL is fully discharged, and output voltage VOUT is zero. At start up (e.g., when power VDD is applied), feedback voltage VFB is initially zero, so reference voltage VREF will dominate the operation of error amplifier 50, thus causing it to generate output signal VEA-OUT that maximizes the duty cycle of PWM circuit 70 in an effort to charge load capacitor CL as rapidly as possible. The resulting surge can damage output transistor 75 and typically overshoots the desired output voltage, possibly overloading the input supply and/or damaging the load circuit. The surge would also generate a huge input current, touching the alarm limit on the input supply. Accordingly, some form of "soft-start" is desirable where the starting surge is avoided.
One prior art solution to the start up overshoot problem is to employ some form of "soft-start", where the starting surge is avoided by causing output voltage VOUT to gradually rise from zero to the desired nominal level at start up. A common method for achieving this soft-start function is to employ an external capacitor to control the error amplifier output signal VEA-OUT such that it increases gradually at start up, thereby causing the duty cycle of PWM 70 to gradually increase, thus preventing significant overshoot when the desired output voltage is VOUT achieved. External capacitors are used to produce the soft-start function because operational amplifier currents are typically too large to support the use of practical semiconductor (i.e., integrated) capacitors. The size (capacitance) of the external capacitor is selected to achieve desired output characteristics (i.e., based on the load circuit impedance and desired overshoot characteristics), and the external capacitor is typically connected to the operational amplifier during assembly by way of a dedicated device pin.
A problem with the practice of using external capacitors to produce desired soft-start characteristics is that the use of external capacitors is relatively expensive due to both the component cost and the assembly costs associated with mounting the external capacitor. Further, the external capacitor takes up a valuable device pin, which prevents the use of that pin for other input/output signals.
One prior art solution to the start up overshoot problem is to employ a digital soft-start circuit, which digitally controls the duty cycle of the regulator during start up, thereby providing the soft-start function without the need for a large external capacitor. A problem with digital soft-start circuits is that they require a significantly larger amount of chip area than analog solutions, so by comparison analog soft-start solutions present a strong price and simplicity advantage.
What is needed is an analog soft-start circuit for switching regulator that generates a ramp voltage without using an external capacitor and dedicated device pin. What is also needed is an analog soft-start circuit for switching regulator that uses an analog voltage clamp circuit to ramp the regulated output voltage to the desired voltage level without significant overshoot.

Analog internal soft-start and clamp circuit for switching regulator


A heat sink retention assembly for retaining a heat sink in thermal contact with a CPU while transmitting load away from the CPU. The heat sink retention assembly includes a frame sized to receive the heat sink, the frame including opposing pin capture channels and a wire module. The wire module includes an upper handle section and a lower pivoting section. The wire module is pivotably coupled to the frame at the lower pivoting section. The wire module further includes opposing end pins, wherein each pin is moveably retained within and extends through a corresponding pin capture channel such that when the wire module is rotated with respect to the frame, the pins travel within their respective channels in order to engage the heat sink.

1. Statement of the Technical Field
The present invention relates to heat sinks and more particularly to a method and apparatus of securing a heat sink above a central processing unit (CPU) of a computer in order to divert the weight and force of the heat sink to the computer's chassis or mounting plate rather than toward the CPU while maintaining the requisite thermal interface with the CPU.
2. Description of the Related Art
Heat sinks are a vital part of any computer system. The heat generated by continued and extended use of a computer can severely damage the electrical components in the computer. Heat sinks provide a way for the heat to be transferred away from the source and away from critical components. To increase the amount of thermal transfer, heat sinks typically include a large surface area or a large number of thermally conductive fins. However, the problem that arises when large heat sinks or heat sinks with a large number of fins are used is that critical space within the confines of the computer chassis is used up. Also, heavy heat sinks must be secured directly to the computer chassis in order to avoid transmitting the direct weight of the heat sink on the CPU.
The contact area between the heat sink and the electrical components and the pressure at the point of contact between the heat sink and the heat source are also important considerations in heat sink design. A heat sink with a flat contact area is preferred since a thinner layer of thermal compound may be used. This reduces the thermal resistance between the heat sink and the heat source. The pressure between the heat sink and the heat source must be high in order to maintain the requisite thermal contact and to facilitate thermal flow. Mechanical clips may help maintain the requisite pressure between the surface of the heat sink and the CPU, but such clips are usually difficult to install and are not reliable when the computer is being shipped. Even a slight jarring during shipping may cause the weight of the heat sink to fall directly on the CPU or motherboard causing severe damage. Further, because of the increased thickness in motherboards, the use of an under-the-board spring to dampen the force exhibited by the heat sink on the CPU and other electrical components is no longer feasible.
The recent proliferation of Land Grid Array (LGA) sockets have created another problem that must be considered during heat sink design and particularly in the manner in which heat sinks or other cooling devices are attached to the socket/CPU assembly. Current LGA socket designs frequently contain heat sinks as part of the assembly. The heat sink base is usually used as one of the loading plates in the assembly and is typically attached to a back-side stiffener using multiple screws or spring-loaded threaded fasteners. Even these simple attachment means can consume a significant portion of the effective heat sink volume, since the screws or spring-loaded fasteners protrude through the heat sink and require removal or partial removal of some of the fin structure, thereby reducing its thermal efficiency. Additionally, deflection that might occur under actuation load can create gaps between the heat sink and the assembly that can compromise the thermal effectiveness of the heat sink and/or cause the weight of the heat sink to fall directly on the CPU.
It is therefore desirable to have an apparatus and method that allows a heat sink to be mounted above a CPU and to deliver a load commensurate with the required thermal flow characteristics of the heat sink and to provide a mechanism to hold the heat sink firmly in place with the weight of the heat sink being transmitted to the chassis or mounting plate of the computer rather than the CPU, motherboard or other critical components of the computer.

Torsion spring force and vertical shear pin retention of heat sink to CPU

International Business Machines Corporation


An exhaust valve assembly for use in an exhaust system includes a body region and an auxiliary region. The body region has first and second ends and defines a longitudinal axis defined between the ends. The body region has an interior surface terminating at the ends and defines a flow path along the axis and an opening. The auxiliary region is coupled to the body region about the opening. The auxiliary region has at least one wall that defines a space in communication with the opening outside the flow path. The exhaust valve assembly further includes a shaft coupled to the wall of the auxiliary region and a vane coupled to the shaft. The vane is movable between an open position with the vane disposed entirely within the auxiliary region and a closed position with at least a portion of the vane disposed in the body region intersecting the axis.

1. Field of the Present Disclosure
The present disclosure relates generally to an exhaust valve assembly, and more specifically, to an exhaust valve assembly for a vehicle exhaust system.
2. Description of the Related Art
Mostly every vehicle includes a combustion engine having an exhaust system. The exhaust system typically includes exhaust pipes for directing a flow of exhaust gas from an engine to various exhaust system components, such as a muffler and a resonator.
Some exhaust systems do not perform optimally. For instance, the flow of exhaust gas passing through the exhaust system may generate undesirable acoustic noise, such as low-frequency noise. In these situations, the exhaust system may require specific tuning to attenuate the undesirable acoustic noise.
An exhaust valve can be incorporated into the exhaust system to attenuate the undesirable acoustic noise. In an example, the exhaust valve is designed to control the flow of exhaust gas passing through the exhaust system by a spring, which is configured to bias a valve plate or vane against the flow of the exhaust gas. In doing so, the exhaust valve provides variable backpressure against the flow of exhaust gas, thereby attenuating the acoustic noise.
It has been found, however, that some exhaust valves have several disadvantages. For instance, the exhaust valve may be difficult to manufacture and maintain. In particular, the spring, the vane, and perhaps one or more other exhaust valve components may be permanently installed within the architecture of the exhaust valve. For at least this reason, in some instances, it may thus be difficult to access the exhaust system components for purposes of maintenance, to replace a component, and/or the like. In addition, the exhaust valve may be limited in application, and may be non-adjustable in various clearance situations. This is due, at least in part, to the exhaust valve being permanently integrated as part of the exhaust system.


A method of achieving year-round utilization of pollinating insects such as bumble bees and a constant temperature box to be employed for this purpose. In order for this to be achieved, the temperature inside the nest box for housing pollinating insects such as bumble bees is maintained within an optimal habitat environment temperature range throughout the year. In the constant temperature box for maintaining the temperature within the optimal habitat environment temperature range, the temperature in the space where the nest box for housing pollinating insects such as bumble bees is placed is maintained within the optimal habitat environment temperature range for pollinating insects such as bumble bees through a device for temperature control. In addition, the constant temperature box is provided with a communication passage for access to allow the pollinating insects in the nest box to come and go between the nest box and the outside.

1. Field of the Invention
The present invention relates to a method for year-round utilization of pollinating insects such as bumble bees. To give a more detailed description, the present invention makes it possible for pollinating insects such as bumble bees to be engaged in pollinating activity from January through February, from mid-April through June in the daytime and from July through early September, which are normally inactive periods for such insects in the Northern Hemisphere. In addition, the present invention relates to a constant temperature box which performs temperature control for the nest box to achieve year-round utilization of pollinating insects such as bumble bees.
2. Description of the Related Art
With the development of the apiculture industry, honey bees have been used for pollination of agricultural products. However, there are limits to the utilization of honey bees for the purpose of pollination, such as the fact that they do not visit flowers such as those of tomatoes and eggplants, which do not produce floral nectar, and the fact that they cannot be kept within a small enclosed space. Bumble bees or the like solve these problems concerning pollination.
The utilization of bumble bees for the purpose of pollination was first implemented in Belgium, where they were used for pollination of greenhouse tomatoes. Bumble bees native in Europe (Bombus terrestris) are imported from Europe and used for pollination of tomatoes and the like. According to the present invention, native Japanese species may be used for pollination of tomatoes and the like. The type of nest boxes that are widely employed for housing imported bumble bees in the known art is manufactured using a paper material such as hard board or a plastic material. Such a box is positioned at a strategic location within a greenhouse for growing tomatoes or the like. Typically, a nest box is installed 0.5.about.1 meters above the ground and the temperature inside the nest box is, generally speaking, subject to change in correspondence to changes in the temperature of the outside air. In view of this fact, such measures as installing an awning made of a styrofoam plate on top of the nest box or burying the nest box in the ground have been taken when the temperature becomes high.
Furthermore, there are basically no measures that may be taken against low temperatures in the winter and, normally, bumble bees have not been used for pollination when the temperature is low. In other words, the technology in the prior art does not implement management of the habitat temperature environment in a positive manner but rather it is employed simply to supplement natural mechanisms for adjusting the nest box internal temperature of the nest where bumble bees or the like are housed.
Thus, bumble bees or the like are often exposed to low temperatures or high temperatures that are beyond their capacity for adjusting to the nest internal temperature. By nature, bumble bees or the like form a covering (internal insulating layer) over the contents of the nest to achieve heat preservation when the temperature inside the nest falls below 23.degree. C. and they become active in heat producing activity whereby they produce heat by vibrating their muscles while walking a short distance when the temperature is under 20.degree. C. In addition, when the temperature exceeds 31.degree. C., they attempt to lower the temperature inside the nest by performing ventilating activity.
As a result, when the temperature is under 20.degree. C. or when the temperature exceeds 31.degree. C., individuals who would normally be engaged in pollinating activity outside the nest remain inside the nest to produce heat or to ventilate the nest. Because of this, bumble bees which are capable of performing pollination with the outside air temperature ranging from 5.degree. C. to 37.degree. C. in a natural state can be used for pollination inside a greenhouse only when the temperature is within the range of 10.degree. C. to 28.degree. C. Consequently, they cannot be expected to accomplish much pollination from January through February, from mid-April through June during the daytime, and from July through early September.
Furthermore, with natural nest internal temperature adjustment performed by bumble bees or the like, the life of the colony is reduced due to energy exhaustion in individuals, weakening of physical resources and the death of eggs and larvae when the temperature is too low or too high. In addition, the method that is employed as a countermeasure against high temperatures whereby the nest box is buried underground is not a practical method since, normally, one nest is moved around to serve several greenhouses.

Method for year-round utilization of pollinating insects such as bumble bees and constant temperature box for achieving this


The present invention relates to a sink access device which is utilized to facilitate a child or a diminutive person to wash their hands at a lavatory located at a public restroom. The sink access device includes a step support mount having a base and an upwardly extending arm. The step support mount is fixedly attached to a portion of a public restroom. A step is pivotally mounted to the upwardly extending arm of the step support mount. The step has a first position wherein the step is in a vertical position and a second position wherein the step is in a horizontal position providing a platform for a diminutive person to step onto. The step is positioned either at or behind a vertical plane defined by the front profile of a sink when the step is in the first position and the step breaks the plane when in the second position.

1. Field of the Invention
The present invention relates to a pivoting step which is utilized to facilitate a child or a diminutive person to wash their hands at a lavatory located at a public restroom.
2. Description of Related Art
Restroom utilization is typically a daily routine for just about everyone, whether at home, work, shopping, or eating out. However, restroom designs are not standardized and are typically inadequate. The flux of the inconsistencies of restrooms has prompted, among other things, the formation of the American Restroom Association, which discusses various aspects of restrooms at www.Americanrestroom.org. The mission statement for the American Restroom Association includes the advocation for the availability of clean, safe, well-designed public restrooms which includes restroom design and technology, restroom availability, pertinent legislation and regulations, and increasing research related to the problems faced by people who hesitate to travel or who avoid activities that put them out of range of proper toilet facilities. Since there is no standardization of restrooms, almost all states adopt comprehensive consensus code that contains language, requiring toilet facilities for customers, patrons and visitors. This code is then enacted statewide, or where not mandated, is often adopted voluntarily at the municipal level. Of related interest, the formulas that describe the required minimum number of toilets are being updated to reflect ongoing issues. With a few exceptions, states adopt either the International Plumbing Code (IPC), the Uniform Plumbing Code (UPC) or the National Standard Plumbing Code (NSPC). While these codes typically are concerned with identifying issues regarding the number of restrooms and lavatories which must be present depending upon accessibility and the size of the public establishment, these codes are deficient in identifying specific requirements to standardization of rest rooms. For instance, while there is a trend for hands-free operation of toilets, lavatories and the like, these are merely incorporated into restrooms at the discretion of the proprietor of the public facility and are not mandated by any legislation. Accordingly, while restrooms are required to meet certain standards so that they can be utilized by everyone, they are not necessarily designed for everyone. In fact, until recently, handicapped individuals experienced great hardship in utilizing public restrooms until legislation to eliminate these hardships was put into place by the passage of the Americans with Disabilities Act ("ADA"). Accordingly, since the utilization of public restrooms is a common occurrence, their designs should include access for everyone. For the purposes of this patent application, "restroom" is defined as a room equipped with toilets and lavatories for public use.
The impact of the construction of toilets has led to the establishment of international meetings regarding issues surrounding public restrooms. In 2005, conventions were held in Belfast, Ireland and Shanghai, China, and in 2006 conventions are scheduled for Moscow, The Russian Federation, and Bangkok, Thailand, with the conference in Moscow including issues relating to children's utilization of public restrooms.
In addition to the adequate presence of restrooms, the overall construction and condition of restrooms is also important to the public. A recent survey conducted by the International Facility Management Association, www.ifma.org, indicated that besides a public building's front entrance, its restrooms have the greatest potential to negatively impact a visitor's impression of a facility. Also, durability, cleanliness and ADA compliance were highly regarded characteristics of restrooms. Of the respondents to the survey, nearly three-quarters believed that their restrooms were the most frequently visited common area of the building. Key findings from the survey indicated that issues regarding the restrooms were as frequent as other prime issues such as parking and temperature. In particular, customers were most concerned with restroom cleanliness and indicated hands-free sensor technology is the most popular design trend. Accordingly, the experience which the public has with a particular establishment's restroom will greatly affect that individual's perception of that establishment.
The interrelationship between the public and restrooms is so intertwined that not only is the location of restrooms important but also their accessibility, interactivity and safety. For instance, at a meeting at the School of Architecture and Planning at the University of Buffalo regarding utilization of public amenities, certain key attributes for restrooms was discussed. Such guidelines regarding the design of restrooms included the physical design, such as the floor surfaces draining and drying quickly; the provision of the automatic flush plumbing and changing tables for babies; hooks for coats at or below 48 inches, and other ergonomically friendly features.
However, with all of the attention placed on restrooms and their "friendliness" to the public, a major problem with restrooms currently exists. Namely, lavatories are too high for children, toddlers and diminutive persons to utilize. This is especially a problem because many lavatories have installed infrared devices to trigger the faucet to turn on. Hence, while parents go to public places with their children such as museums, aquariums, zoos, and restaurants, the lavatories and sinks at these public restrooms are too high for the child to use without assistance from a parent. Accordingly, a parent has to pick up a toddler and hold them prone over a sink countertop to enable the toddler to wash its hands. Inevitably, the toddler gets its clothing wet due to the water left on the countertop from previous usage by an adult. To perform this maneuver, the parent typically has to place a diaper bag or other item which he is typically carrying onto the lavatory floor, pick up the toddler, and then place the toddler back down. As toddlers mature, their weight can approach forty pounds and more, but they are still too short to utilize the lavatory. Such toddler weight is too heavy for some parents, and in some cases, the parent may injure himself picking up and orienting the toddler over the sink.
While portable step stools are known to increase a person's height for various reasons, these portable step stools are generally only utilized at home so they may be conveniently stored and utilized. These stools are too cumbersome for travel, especially with a small child or toddler. However, when away from home, children also need to utilize the lavatories in public places such as stores, restaurants, aquariums, zoos, parks, airports and the like, and accordingly, there is a need for a way to enable toddlers and diminutive persons to have access to a sink at a public restroom.
Accordingly, it is an object of the present invention to provide a booster step for children/toddlers and diminutive persons to enable the individual to utilize a sink in a public facility.
It is also an object of the present invention to provide a booster step that is accessible for children/toddlers and diminutive persons while also being out of the way of taller individuals, so that their utilization of a sink in a public facility is not impeded.

Sink access device for a public restroom


In an IBM PC AT-compatible computer architecture, CPU-generated addresses and data for accesses to a peripheral device in the I/O address space are coupled directly to the peripheral device from the local bus, without traversing the I/O bus. Any data returned from the peripheral device is coupled directly to the local bus, also without traversing the I/O bus. No buffers are needed for communicating such address and data information between the peripheral device and the I/O bus.

1. Field of the Invention
The invention relates to IBM PC AT-compatible computer architectures, and more particularly, to enhancements thereof for communicating with I/O peripheral devices.
2. Description of Related Art
The IBM PC AT computer architecture has become an industry standard architecture for personal computers and is typically built around a CPU such as an 80286, 80386SX, 80386DX, or 80486 microprocessor manufactured by Intel Corporation. The CPU is coupled to a local bus, capable of performing memory accesses and data transfers at high rates of speed (i.e., on the order of 10-50MHz with today's technology). The local bus includes 16 or 32 data lines, a plurality of address lines, and various control lines.
The typical IBM PC AT-compatible platform also includes DRAM main memory, and in many cases a timer, a real-time clock, and a cache memory, all coupled to the local bus.
The typical IBM PC AT-compatible computer also includes an I/O bus which is separate and distinct from the local bus. The I/O bus, sometimes referred to in these systems as an AT bus, an ISA bus or an EISA bus, is coupled to the local bus via certain interface circuitry. The I/O bus includes 8, 16 or 32 data lines, a plurality of I/O address lines, as well as control lines. The I/O address space is logically distinct from the memory address space and if the CPU desires to access an I/O address, it does so by executing a special I/O instruction. Such an I/O instruction generates memory access signals on the local bus, but also activates an MIO# signal to indicate that this is an access to the I/O address space. The MIO# line is often considered as merely another address line. The interface circuitry recognizes the I/O signals thereby generated by the CPU, performs the desired operation over the I/O bus, and if appropriate, returns results to the CPU over the local bus.
In practice, some I/O addresses may reside physically on the local bus and some memory addresses may reside physically on the I/O bus. The interface circuitry is responsible for recognizing that a memory or I/O address access must be emulated by an access to the other bus, and is responsible for doing such emulation. For example, a ROM (or EPROM) BIOS may be physically on the I/O bus, but actually form part of the local memory address space. During system boot, when the CPU sends out a non-I/O address which is physically within the ROM BIOS, the interface circuitry recognizes such, enables a buffer which couples the address onto the I/O bus, and activates the chip select for the ROM. The interface circuitry then assembles a data word of the size expected by the CPU, from the data returned by the ROM, and couples the word onto the local bus for receipt by the CPU. In many systems, at some point during the ROM-based boot-up procedure, the ROM BIOS is copied into equivalent locations in the DRAM main memory and thereafter accessed directly. The portion of DRAM main memory which receives such portions of the BIOS is sometimes referred to as "shadow RAM."
More specifically, in the standard architecture, the logical main memory address space is divided into a low memory range (0h-9FFFFh), a reserved memory range (A0000h-FFFFFh) and an extended memory range (100000h-FFFFFFh). In a typical system the system ROM BIOS is located logically at addresses F0000h-FFFFFh, and is located physically on the I/O bus. Addresses C0000h-EFFFFh contain ROM BIOS portions for specific add-on cards and are located physically on their respective cards on the I/O bus. Addresses A0000h-BFFFFh contain the video buffer, located physically on a video controller on the I/O bus. Duplicate memory space is typically provided in DRAM on the local bus for addresses C0000h-FFFFFh, and the user of the system can select during a setup procedure, which portions of the ROM BIOS are to be "shadowed" by being copied into the duplicate DRAM space during boot-up. Subsequent accesses to "shadowed" portions of the BIOS are to the DRAM copy, which is typically much faster than accesses to the ROM copy.
In addition to the above elements, a keyboard controller typically is also coupled to the I/O bus, as is a video display controller. A typical IBM PC AT-compatible system may also include a DMA controller which permits peripheral devices on the I/O bus to read or write directly to or from main memory, as well as an interrupt controller for transmitting interrupts from various add-on cards to the CPU. The add-on cards are cards which may be plugged into slot connectors coupled to the I/O bus to increase the capabilities of the system.
General information on the various forms of IBM PC AT-compatible computers can be found in IBM, "PC/AT Technical Reference Manual", in Sanchez, "IBM Microcomputers: A Programmer's Handbook" (McGraw-Hill: 1990) and Solari, "AT Bus Design" (San Diego: Annabooks, 1990). See also the various data books and data sheets published by Intel Corporation concerning the structure and use of the iAPX-86 family of microprocessors, including the "i486 Microprocessor Hardware Reference Manual", published by Intel Corporation, copyright date 1990, "386 SX Microprocessor", data sheet, published by Intel Corporation (1990), and "386 DX Microprocessor", data sheet, published by Intel Corporation (1990). All the above references are incorporated herein by reference.
The local bus includes a plurality of address lines and a plurality of data lines, as well as a number of control lines and power and ground. The exact set of lines which make up the local bus is well known in the industry, and may be determined from various sources, including the references cited above. For present purposes, it is sufficient to identify the following signal lines on the local bus ("#" indicates active low):
______________________________________ CA(23:1) or Address lines. For the 80286 and CA(31:2) 80386SX, 24 bits of address are provided. The high order 23 bits are provided on CA(23:1). For the 80386DX and 80486, 32 bits of address are available. The high order 30 bits are provided on CA(31:2). BHE# & BLE# Byte High Enable and Byte Low or BE#(3:0) Enable, or Byte Enables (3:0). For the 80286 and 80386SX, BLE# can be thought of as equivalent to CA(0) and BHE# = !BLE#. For the 80386DX and 80486, BE#(3:0) carries a 1-of-4 decode of the 2 low order address bits CD(15:0) or Data lines. The 80286 and 80386SX CD(31:0) operate with a 16-bit external data bus, and the 80386DX and 80486 operate with a 32-bit data bus. M/IO# Memory/IO control line. When asserted low by the CPU, indicates that the address on CA is an I/O address as opposed to a main memory address. READY# Acknowledgment to CPU that a current request has been serviced and CPU can start a new cycle. CLK2 or CLK CPU clock signal. W/R# Distinguishes write cycles from read cycles. D/C# Distinguishes data cycles, either memory or I/O, from control cycles which are: interrupt acknowledge, halt, and instruction fetching. LOCK# Indicates that other system bus masters are denied access to the system bus while it is active. ADS# Indicates that a valid bus cycle definition and address (W/R#, D/C#, M/IO#, BE0#, BE1#, BE2#, BE3# (or BHE# and BLE#) and CA) are being driven on the local bus. NA# Requests address pipelining. BS16#(386) Allows direct connection of 16- BS8#(486) bit and 8-bit data buses. HOLD Allows another bus master to request control of the local bus. HLDA Indicates that the CPU has surrendered control of its local bus to another bus master. BUSY# Signals a busy condition from a processor extension. ERROR# Signals an error condition from a processor extension. PEREQ Indicates that the processor extension has data to be transferred by the CPU. INTR A maskable input to CPU that signals the CPU to suspend execution of the current program and execute an interrupt acknowledge function. NMI A non-maskable input that signals the CPU to suspend execution of the current program and execute an interrupt acknowledge function. RESET Suspends any operation in progress and places the CPU in a known reset state. ______________________________________
The various signals on the I/O bus are also well specified and well known in the industry. The Solari book identified above described the lines in detail. For present purposes, only the following signals are important:
______________________________________ SA(19:0) 20 address lines. Sufficient to address 1MB of memory. Only SA(15:0) are used to address the 64k I/O address space, and only SA(9:0) are used to address the basio 1k AT I/O address space. Additional address lines for LA(23:17) addressing a 16MB memory address space on the I/O bus. The LA lines are valid earlier in an I/O bus cycle, but must be latched if needed later in the cycle. The SA lines are not valid as early as the LA lines, but remain valid longer. BALE Bus address latch enable In line. In a CPU initiated I/0 bus cycle, this line indicates when the SA address, AEN and SBHE# lines are valid. In other I/O bus cycles, the platform circuitry drives BALE high for the entire cycle. SBHE# System byte high enable. When SBHE# is active and SA(0) is low, then a 16-bit access will be performed. AEN When active, informs I/0 resources on I/O bus to ignore the address and I/O command signals. Used primarily in DMA cycles where only the I/O resource which has requested and received a DMA acknowledgment signal (DACK#) knows to ignore AEN and respond to the I/O signal lines. Some systems include slot-specific AEN signal lines. SD(15:0) 16 data lines. MEMR#, Read request lines to a memory SMEMR# resource on the I/O bus. SMEMR# is the same as MEMR# except that SMEMR#becomes active only when the read address is below 1MB (i.e., LA(23:20) = 0). MEMW# Write request lines to a memory SMEMW# resource on the I/O bus. SMEMW# becomes active only when the write address is below 1 MB. IOR# Read request line to an I/O resource on the I/O bus. IOW# Write reguest line to an I/O resource on the I/O bus. MEMCS16# Memory chip select 16. Asserted by an addressed memory resource on the I/O bus if the resource can support a 16-bit memory access cycle. IOCS16# I/O chip select 16. Asserted by an addressed I/O resource on the I/O bus if the resource can support a 16-bit I/O access cycle. SRDY# Synchronous Ready line. Also sometimes called OWS# or ENDXFR#. Activated by an addressed I/O resource to indicate that it can support a shorter-than-normal access cycle. IOCHRDY I/O channel ready line. lf this line is deactivated by an addressed I/O resource, the cycle will not end until it is reactivated. A deactivated IOCHRDY supersedes an activated SRDY#. Also sometimes called CHRDY. MASTER# After requesting and receiving a DMA-acknowledged (DACK#) signal, an I/O bus add-on card can assert MASTER# to become the bus master. REFRESH# Activated by refresh controller to indicate a refresh cycle. IRQ(15, 14, Interrupt request lines to 12:9, 7:3) interrupt controller for CPU. DRQ(7:5, DMA Request lines from I/O 3:0) resource on I/O bus to platform DMA controller. DACK(7:5, DMA Acknowledge lines. 3:0) TC DMA terminal count signal. Indicates that all data has been transferred. BCLK I/O bus clock signal. 6-8.33 MHz square wave. OSC 14.318 MHz square wave. ______________________________________
Recently, efforts have been made to reduce the size and improve the manufacturability of PC AT-compatible computers. Specifically, efforts have been made to minimize the number of integrated circuit chips required to build such a computer. Several manufacturers have developed "PC AT chipsets", which integrate a large amount of the I/O interface circuitry and other circuitry onto only a few chips. An example of such a chipset is the 386WB PC/AT chipset manufactured by OPTi, Inc., Santa Clara, Calif.
In the original IBM PC AT computer manufactured by IBM Corp., the I/O bus operated with a data rate of 8 MHz (BCLK=8 MHz). This was an appropriate data rate at that time since it was approximately equivalent to the highest data rates which the CPUs of that era could operate with on the local bus. Numerous third party vendors have since developed peripheral devices and controller cards which are intended to be plugged into an AT slot on the I/O bus, and which rely upon the 8 MHz maximum data rate. The AT standard also requires a wait state (i.e. 125 nS) for 16-bit data transfers, and four wait states (500 nS) for 8-bit data transfers. A zero wait state data transfer is also available, but only if the peripheral device signals, by activating the SRDY# control line on the I/O bus, that it can handle such fast data transfers.
In the years since the IBM PC AT was originally introduced, technology has improved dramatically to the point where local buses on typical high-end PC AT-compatible computers can operate on the order of 50 MHz. Despite these advances, however, such computers are still manufactured with an I/O bus operating at around 8 MHz because of the need to maintain compatibility with previously designed peripheral devices. These devices were designed in reliance upon the 8 MHz data rate and AT wait state protocol, and many such devices are not capable of operating faster. Even modern designs for AT bus peripherals often rely on the 8 MHz maximum data rate, even though very little additional effort or cost would be involved to design them to operate faster.
In addition to the large disparity between data transfer rates on the I/O bus as compared to the local bus in modern PC AT-compatible computers, the I/O interface circuitry needs to delay its handling of requests and responses from one bus to the other merely because the clocks are not synchronized. The circuitry therefore must hold a request or response until the appropriate clock edge on the destination bus appears. This can add on the order of 30-200 nS to each I/O bus cycle. Accordingly, it can be seen that any access to a peripheral device on the I/O bus imposes a substantial penalty on the performance of PC AT-compatible computers. This penalty will only become worse as the disparity between the local bus and I/O bus data rates continues to increase.
FIG. 1 depicts the important elements of a prior art PC AT-compatible computer architecture 10 which addressed the problem of the I/O bus access penalty with respect to one particularly speed-sensitive peripheral device, namely, a VGA video graphics controller 12. This particular computer system used an ET4000 VGA controller chip, manufactured by Tseng Labs, Newtown, Pa. The ET4000 is described in a data book entitled "ET4000 Graphics Controller High Performance Video Technology", published by Tseng Labs (1990), incorporated herein by reference. The VGA controller 12 shown in FIG. 1 includes this chip, the video memory, a DAC, and all associated circuitry. Although originally intended to be used in a standard configuration as a peripheral device on the I/O bus, the VGA controller 12 is nevertheless capable of operating at the high speeds of the local bus.
A VGA controller in the PC AT-compatible architecture is addressable in two address ranges: I/O ports are accessible at addresses 3B0-3DE in the I/O address space, and the video memory itself is accessible at addresses A0000-BFFFF in the main memory address space. In the original PC AT configuration, the VGA controller was located on the I/O bus and accesses to the I/O ports of the VGA controller occurred in the normal way for peripheral devices. That is, as mentioned above, the CPU issued an I/O read or write command and the I/O interface circuitry recognized it and generated the appropriate signals on the I/O bus in order to read or write from the addressed I/O port on the VGA controller. In order to access the video memory directly, the CPU issued an ordinary read or write cycle on the local bus as if the video memory was physically attached to the local bus. The I/O interface circuitry decoded the address to determine that it was within the address range of video memory, and then generated the appropriate signals on the I/O bus to execute the read or write cycle. When the cycle completed, any data returned by the VGA controller on the I/O bus was transmitted to the local bus. The READY# signal, which would have been asserted to the CPU almost immediately if the video memory was physically on the local bus, is withheld until the I/O cycle is complete.
In the architecture 10 shown in FIG. 1, accesses to the I/O ports of the VGA controller 12 continue to occur via the I/O bus. That is, the VGA controller 12 responds to the control signals on the I/O bus, receives its addressing from the I/O bus, and transfers data via the I/O bus. Similarly, master accesses to or from either port of the VGA controller, as well as DMA data transfers to or from video memory, also continue to occur via the I/O bus. Direct accesses by the CPU to or from video memory, however, occur directly from the local bus.
Referring to FIG. 1, the architecture 10 includes a CPU 20, which may be an Intel 80386SX microprocessor. Importantly, the CPU 10 has only a 16-bit external data bus and a 24-bit address bus. The CPU 20 is coupled to a local bus 22, together with a main memory array 24. The local bus 22 includes, among other things, 16 data lines CD(15:0), address lines CA(23:1) and BHE# and BLE#. For convenience, when referring to multiple CPU address lines herein, the BLE# line is sometimes referred to by its shorthand equivalent, CA(0).
The architecture 10 also includes an I/O bus 30 which includes, among other things, 16 data lines SD(15:0), address lines SA(19:0), and various control lines. Various peripheral devices illustrated as 32 and 34 in FIG. 1 are attached to the I/O bus 30. Such devices may include, for example, a local area network (LAN) card, an IDE disk drive controller, a modem, and so on.
The architecture 10 also includes an I/O interface chipset 40 which implements the I/O interface circuitry referred to above. On the local bus side, it is bi-directionally connected to the address lines CA(23:1), BHE# and BLE#, as well as the data lines CD(15:0). On the I/O bus side, the I/O interface chipset 40 is bi-directionally connected to the address lines SA(19:0) and data lines SD(15:0). The I/O interface chipset 40 includes an Appian System 90/SX chipset, manufactured by Appian Technology, Sunnyvale, Calif. The chipset 40 also includes an MCS1# input which can be activated by external circuitry to inhibit the performance of an I/O bus cycle in response to a local bus command which would otherwise be interpreted by the chipset 40 as requiring such an I/O bus cycle. It is believed that the MCS1# input was originally intended to be activated by a coprocessor which was present on the local bus instead of the I/O bus.
The VGA controller 12 includes, among other things, a partially multiplexed address/data port. On this port, pins DB(15:0) carry 16 data bits multiplexed with the low order 16 bits of an address, and pins A(19:16) carry four higher order address bits. These pins are connected to a dedicated VGA bus 44, different from both the local bus 22 and the I/O bus 30. As described in the above-mentioned Tseng Labs databook, the VGA controller 12 further includes the following signal lines for connecting to the remainder of the system:
______________________________________ CDMW# Input Memory Write signal for writing data to display memory. Typically connected to I/O bus MEMW# line. ADMR# Input Memory Read signal for reading data from display memory or BIOS ROM. Typically connected to I/O bus MEMR# line. MIOW# Input I/O Write signal for writing to VGA control registers. Typically connected to I/O bus IOW# line. CIOR# Input I/O Read signal for reading from VGA control registers. Typically connected to I/O bus IOR# line. WAIT# Output Memory or I/O read/write access should be stretched until this signal deactivates. Typically used to generate I/O bus READY line (i.e., IOCHRDY) ADRE# Output Enables low order 16 address signals onto DB(15:0). Typically, controls buffers which enable the I/O bus address onto DB(15:0), but used differently in the FIG. 1 architecture as hereinafter described. RDMH# Output Enables upper 8-bits of external bi-directional buffer coupling data lines with DB(15:8). Typically controls a buffer which enables coupling of DB(15:8) with the I/O bus data lines SD(15:8), but used differently in the FIG. 1 architecture as hereinafter described. RDML# Output Enables low order 8-bits of external bi-directional buffer coupling data lines with DB(7:0). Typically controls a buffer ooupling DB(7:0) with the I/O bus data lines SD(7:0) but used differently in the FIG. architecture as hereinafter described. DIR Output Signal for controlling the direction of bi-directional buffers coupling DB(15:0) with a data bus. 1 indicates a memory or I/O read from the VGA controller 12; 0 indicates a memory or I/O write to the VGA controller 12. CS16# Output ldentifies the VGA controller 12 as supporting 16-bit memory accesses. Typically connected to I/O bus MEMCS16# line. IO16# Output Identifies the VGA controller 12 as supporting 16-bit I/O accesses. Typically connected to I/O bus IOCS16# line. AEN# Input I/O address valid input Typically connected to I/O bus AEN# line. SBHE# Input Together with SA(0), indicates whether 8- or 16-bit access is intended. Typically connected to receive I/O bus SBHE# line, but connected differently in the architecture of FIG. 1. SFDB# Output 16-bit memory access enable. Same as CS16# but generated earlier. Not used in typical PC-AT compatible computer; used in FIG. 1 architecture to generate an early CS16# type signal which is used for video memory accesses during DMA and master cycles. ROME# Output Enable signal for external video BIOS ROM. ______________________________________
Octal 3-state buffers 50, 52 and 54 couple address lines from the local bus 22 onto the VGA bus 44. In particular, when enabled, buffer 50 couples local bus address lines CA(19:16) onto VGA bus lines A(19:16), buffer 52 couples local bus address lines CA(15:8) onto VGA bus lines DB(15:8), and buffer 54 couples local bus address lines CA(7:0) onto VGA bus lines DB(7:0).
Bi-directional buffers 56 and 58 can further couple data bi-directionally between the data lines of the local bus 22 and the corresponding lines of VGA bus 44. In particular, the local bus side of bi-directional buffer 56 is connected to local bus data lines CD(15:8), and the local bus side of buffer 58 is connected to local bus data lines CD(7:0). The VGA bus side of bi-directional buffer 56 is connected to VGA bus lines DB(15:8), and the VGA bus side of bi-directional buffer 58 is connected to VGA bus lines DB(7:0).
Additional octal buffers 60, 62 and 64 are provided to couple address lines from the I/O bus 30 onto the VGA bus 44. In particular, buffer 60, when activated, couples I/O bus address lines SA(19:16) onto VGA bus lines A(19:16), buffer 62 couples I/O bus address lines SA(15:8) onto VGA bus lines DB(15:8), and buffer 64 couples I/O bus address lines SA(7:0) onto VGA bus lines DB(7:0). Two additional bi-directional octal buffers 66 and 68 are provided to couple data signals bi-directionally between the VGA bus 44 and the I/O bus 30. In particular, the I/O bus side of bi-directional buffer 66 is coupled to I/O bus data lines SD(15:8), and the I/O bus side of bi-directional buffer 68 is connected to I/O bus data lines SD(7:0). The VGA bus side of bi-directional buffer 66 is connected to VGA bus lines DB(15:8), and the VGA bus side of bi-directional buffer 68 is connected to VGA bus lines DB(7:0).
In a standard system, in which all addresses and data for VGA controller 12 are communicated via the I/O bus 30, buffers 50, 52, 54, 56, 58 and 60 are unnecessary and the Output Enables (OE#) for buffers 62, 64, 66 and 68 are driven by the VGA-generated ADRE#, ADRE#, RDMH# and RDML# signals respectively. In the architecture of FIG. 1, these output enables are driven instead by newly defined signals BADRE#, BADRE#, BRDMH# and BRDML# respectively. The output enables (OE#) for buffers 50, 52, 54, 56, 58 and 60 are connected to receive respective newly defined signals LOCAL#, LADRE#, LADRE#, LRDMH#, LRDML# and BUS#. The directional inputs to bi-directional buffers 56, 58, 66 and 68 are all connected to receive the DIR signal generated by the VGA controller 12, as would the equivalent of bi-directional buffers 66 and 68 in a standard architecture.
The OE# signals identified above for the above buffers are all generated by a group of three programmable logic devices and some additional random logic devices in response to the control signals generated by the VGA controller 12, and in response to various signals on the local and I/O buses 22 and 30. The MCS1 signal provided to I/O interface chipset 40 is also generated by such devices. A fourth PLD generates CS16#, substituting for that normally generated by VGA controller 12. All of these signals derive at least in part from a decode of the address lines on the local bus 22 which indicates whenever a local bus access is being performed to or from any address in the video memory address range A0000-BFFFF, and from a decode of I/O bus addresses to the VGA I/O port addresses.
In operation, buffers 60, 62, 64, 50, 52 and 54 are generally enabled to thereby place any address supplied by CPU 20 onto the VGA bus 44. Memory addresses to the video memory range A0000-BFFFF are supplied through buffers 50, 52 and 54 directly from the local bus 22, and all other memory and I/O addresses are supplied through buffers 60, 62 and 64 from the I/O bus 30. Addresses which do not appear on I/O bus 30, and which are not within the video memory address range, are not provided to the VGA bus 44. If an I/O bus cycle occurs which seeks to access any of the I/O ports on VGA controller 12, VGA controller 12 recognizes the I/O address on SA and, through the PLDs and other logic, controls the BADRE#, BRDMH#, BRDML# and DIR signals to respond as required to the I/O bus cycle. The VGA controller 12 is, during this time, essentially disconnected from the local bus 22. Master bus cycles and any DMA cycles which access the VGA I/O ports also occur in this manner. Similarly, if a local bus access occurs to an address outside the video memory address range, the VGA controller 12 remains essentially disconnected from the local bus 22.
If a local bus access occurs to or from an address which is within the video memory address range A0000-BFFFF, the PLDs and associated logic activate the MCS1# input to the I/O interface chipset 40. The chipset 40, which would otherwise have decoded the address, withheld the CPU's READY# signal, and initiated an access to the video memory on the I/O bus 30, is thereby inhibited from doing so. Instead, the OE# signals for the buffers shown in FIG. 1 are controlled to essentially couple the VGA bus 40 to the local bus 22 and to disconnect it from the I/O bus 30. This logic circuitry, in addition to the VGA controller 12, controls the operation of the buffers 50, 52, 54, 56 and 58 such that the VGA controller 12 responds to the video memory access as if it were physically present on the local bus 22. When the access is complete, one of the PLDs generates an MRDY1# signal to the chipset 40. The chipset 40 activates the READY# line to the CPU 20, and the VGA controller 12 returns to listening on the I/O bus 30.
If an access occurs to or from an address which is within the video BIOS address range, typically C0000h-C8000h, the chipset 40 recognizes this and may initiate a standard AT cycle on the I/O bus 30 for accessing the video BIOS ROM. In a standard architecture, where the VGA controller is physically on the I/O bus, the VGA controller decodes the address on the I/O bus itself in order to generate a ROME# ROM enable signal for the video BIOS ROM. This procedure continues to be used in the architecture of FIG. 1 since, as explained above, the video ROM BIOS addresses which appear on I/O bus 30 will be passed to the VGA controller 12 via buffers 60, 62 and 64.
The FIG. 1 architecture operates, as mentioned above, only with an 80386SX (or lesser) CPU, which has only a 24-bit address bus and 16-bit data bus. The technique incurs a problem when an attempt is made to extend the concept for use with a CPU and local bus which has 32 data lines instead of 16. This is the trend in the personal computer market today, with the advent of such 32-bit external data bus microprocessors as the Intel 80386DX and 80486. These microprocessors also have a 32-bit address bus. The natural extension of the FIG. 1 technique would therefore require adding two more bi-directional buffers similar to 56 and 58 to accommodate the additional data lines and one additional uni-directional buffer similar to 50, 52 or 54 to accommodate the additional address lines. Counting these buffers, the natural extension of the FIG. architecture for a 32-bit external data bus microprocessor therefore requires a total of 13 buffer chips. In addition, further programmable logic and other random logic control circuitry may also be required. Such a large number of chips in an industry moving toward reducing the number of chips required to implement a computer, may in effect prohibit the use of the FIG. 1 technique on newer computers.


A metal connection member having joining parts on the upper and lower stories vertical frame members' side surfaces.

In the past, when connecting an upper floor wall panel and a lower floor wall panel, there is known a structure using joint hardware comprised of three pieces of hardware consisting of two pieces of hold down hardware and a set of a connection bolt and nut, fastening the hold down hardware to the vertical frame stud in the upper floor wall panel, fastening the vertical frame stud to the hold down hardware in the lower floor wall panel, and connecting these hold down hardware by the bolt and nut connection hardware.
In a joint structure using joint hardware using such three pieces of hardware, when an earthquake or wind causes a horizontal force to act on the structure, since only tensile force can be transmitted, the compressive force is transmitted by the floor assembly parts. This requires complicated measures such as insertion of compression reinforcing hardware inside the floor assembly sandwiched between the vertical frame studs of the upper and lower floor wall panels, increases the number of pieces, and complicates the design and installation.
Further, as shown in FIG. 18 and FIG. 19, there is also known a joint structure of a type providing, instead of compression reinforcing hardware separately arranged inside the floor assembly, flanges 28 at the top and bottom of a cylindrical body 27 comprised of a steel pipe to form a flanged cylindrical body 29, arranging a connection bolt 30 inside the flanged cylindrical body 29, and connecting upper and lower hold down hardware 31, 32 by nuts 33 (for example, Japanese Patent Publication (A) No. 10-311110)

Joint fitting between members, joint structure of upper and lower floor vertical frame members, and method of joining