A symmetric multiprocessor system includes a first processor and a second processor for executing a multi-threaded process on packets, a first inbound interface and a first outbound interface associated with the first processor, a first task queue accessible for reading by the first processor, a second inbound interface and a second outbound interface associated with the second processor, and a second task queue accessible for reading by at least the first processor. The first inbound interface receives incoming packets and has a first input buffer maintaining a first input queue of the packets for processing by the first processor. The first outbound interface receives packets from the first processor and transmits outgoing packets. The first task queue receives packets output from at least the second processor and maintains another input queue of the packets for processing by the first processor and which are outgoing from the first outbound interface. The second inbound interface receives incoming packets and has a second input buffer maintaining a second input queue of the packets. The second outbound interface receives packets from the second processor and transmits outgoing packets. The second task queue receives packets output from at least the first processor and maintains another input queue of the packets for processing by the second processor and which are outgoing from the second outbound interface. The first processor executes a process thread on packets by requesting the packets from the first input queue and the first task queue in a predetermined manner. The second processor executes a process thread on packets by requesting the packets from the second input queue and the second task queue in a predetermined manner.

1. Field of the Invention
The present invention relates to the field of computer systems for data communications networks. More particularly, the present invention relates to a symmetric multiprocessor system having a plurality of interface devices, and a method for operating the system.
2. The Background
Routers are an essential element of internetworks, an example of which is the Internet. Routers allow (or deny, if necessary) communications between LANs (local area networks) and WANs (wide area networks). Routers transfer packets of data from one network to another and one major task of routers is the switching and forwarding of data packets. A router receives many packets through its multiple interfaces, and a network input/output (NetIO) process (program) and/or port ASIC (application specific integrated circuit) handles incoming packets received on inbound interfaces and outgoing packets sent to outbound interfaces. A router also performs other processes such as configuration, management, maintenance and updating of the system.
Recent rapid expansion of data communications networks has brought pressure for higher performance in network devices such as routers and switches in order to handle the increasing network traffic load. One solution for realizing improved performance of a computer system or a network device, such as a router, is to provide the system with a plurality of microprocessors (CPUs) that execute individual processes simultaneously. Such a microprocessor system, in which a number of microprocessors share memory, I/O (input/output) devices, and other resources, is called a symmetric multiprocessing (SMP) system. A SMP system typically uses a single operating system (OS) to control the microprocessors and a high-speed bus to provide communication among the components of the SMP system. Any idle processor in a SMP system can be assigned any task or process and additional microprocessors can be added to improve the performance of and deal with increased loads on the SMP system. The task of parceling out processes to each component microprocessor of the SMP system may be handled by the OS of the system or by an application program running outside the OS. Although symmetric multiprocessing can produce significant performance gains under ideal conditions, the resources of the system must be allocated to the concurrently running processes in a reasonable manner. In addition, overhead increases as more microprocessors are added to the system.
Multithreading of a process (or task) also generally provides improved performance of a computer system. Multithreading allows different parts (threads) of a single program or process to be executed simultaneously. A thread is a portion of a program or process that can operate independently of other portions of the program or process. In a multithreaded application, all the threads can run at the same time without interfering with one another, if so programmed. In a multiprocessor system, the OS, which is capable of executing such a multithreaded program, allots the threads of the program to the microprocessors. However, it is often difficult to divide a program in such a way that separate microprocessors can execute different portions of it without interfering with one another.
If a router utilizes a SMP system (without multithreading), the processes performed by the router can be executed concurrently by several microprocessors. For example, a NetIO process may run on one microprocessor, while other processes may run on other microprocessors. However, if the NetIO process restricts itself to single-threaded operation, its input/output performance is limited by the microprocessor executing NetIO process. The process drops packets when it is overloaded despite the fact that there may be a number of idle microprocessors in the SMP system which could, but are not adapted to handle the load. Alternatively, the NetIO process can be multithreaded so that each thread is processed by an available microprocessor. For instance, a first packet received on an interface is handled by a first microprocessor, the following packet is handled by a second microprocessor while the first microprocessor is busy processing the first packet, and so forth.
In this scenario of a multithreaded NetIO process, each interface of the router can be used by any of the available microprocessors at any time. A NetIO forwarding process typically receives a packet on an inbound interface, switches the packet based on its destination address, and sends the packet to an outbound interface. Thus, one switching and forwarding process for a packet usually involves an inbound and an outbound interface, the result being that each of the microprocessors executing the NetIO process may have to access any interface of the router. Therefore, it is necessary to adopt some measure such as a mutex or scheduler to prevent more than one microprocessor from accessing the same interface at the same time. That is, the xe2x80x9cright to usexe2x80x9d each interface device must be dynamically allocated among the microprocessors and must not overlap. For example, using a scheduler, a process thread on each microprocessor is xe2x80x9cawakenedxe2x80x9d when the interface becomes available to that microprocessor. However, this approach has the undesirable effect of dramatically slowing the router""s switching performance.
Moreover, the multithreaded NetIO process may cause another problem known as xe2x80x9cpacket reorderingxe2x80x9d when successive packets arriving at an interface constitute a unit of information such as a single data file or an audio or video stream. When the first arriving packet is handled by a first microprocessor and the following packet by a second microprocessor, the second microprocessor may reorder the packets either because it thinks that the second packet should have arrived before the first packet or simply because it completes its task before the first microprocessor. When the reordered packet arrives on the interface, a third microprocessor, rather than the second microprocessor, may handle that third packet, resulting in another potential packet reordering. If the NetIO process is to avoid having more than one microprocessor handle the different interfaces, it is required to perform context switching (forcing one microprocessor to handle a particular packet stream so as to maintain packet ordering within the stream). Such context switching also significantly increases overhead and thus lowers the observed performance of the router or switch.
A symmetric multiprocessor system includes a first processor and a second processor for executing a multi-threaded process on packets, a first inbound interface and a first outbound interface associated with the first processor, a first task queue accessible for reading by the first processor, a second inbound interface and a second outbound interface associated with the second processor, and a second task queue accessible for reading by at least the first processor. The first inbound interface receives incoming packets and has a first input buffer maintaining a first input queue of the packets for processing by the first processor. The first outbound interface receives packets from the first processor and transmits outgoing packets. The first task queue receives packets output from at least the second processor and maintains another input queue of the packets for processing by the first processor and which are outgoing from the first outbound interface. The second inbound interface receives incoming packets and has a second input buffer maintaining a second input queue of the packets. The second outbound interface receives packets from the second processor and transmits outgoing packets. The second task queue receives packets output from at least the first processor and maintains another input queue of the packets for processing by the second processor and which are outgoing from the second outbound interface. The first processor executes a process thread on packets by requesting the packets from the first input queue and the first task queue in a predetermined manner. The second processor executes a process thread on packets by requesting the packets from the second input queue and the second task queue in a predetermined manner.


A stent for receiving and supporting a tissue heart valve for ultimate implantation into a human, the heart valve including tissue leaflets joined at circumferentially spaced commissures, wherein the stent includes at least one commissure support post and at least one sinus support structure each sinus support structure being disposed between but not functionally connected to an adjacent commissure support post.

Prosthetic heart valves are typically used to replace diseased natural heart valves in either the aortic or mitral position. Several categories of prosthetic heart valves are in existence. One category includes what may be referred to as mechanical heart valves. Such valves typically have a rigid orifice ring and rigid hinged leaflets coated with a blood compatible substance such as pyrolytic carbon. Other configurations, such as ball-and-cage assemblies, have also been used for such mechanical valves.
A second category of prosthetic heart valves comprises assemblies having various amounts of biological or natural material. As described in more detail below, some of these valves include leaflets derived from natural material (typically porcine) and still include the natural supporting structure or ring of the aortic wall. In other valves, leaflets derived from natural material (typically bovine pericardium) are trimmed and attached to a synthetic, roughly annular structure or ring that mimics the function of the natural aortic wall. In still other valves, both the leaflets and the annular support ring are formed of synthetic polymers or biopolymers (e.g., collagen and/or elastin). For ease of description, these valves will be referred to herein as bioprosthetic valves.
Many bioprosthetic valves include an additional support structure or stent for supporting the leaflets, although so-called stentless valves are also used. The stent provides structural support to the cross-linked valve, and provides a suitable structure for attachment of a sewing cuff to anchor or suture the valve in place in the patient.
Bioprosthetic valves which include a stent are typically of two types. In one type, an actual heart valve is retrieved from either a deceased human ("homograft") or from a slaughtered pig or other mammal ("xenograft"). In either case, the retrieved valve may be trimmed to remove the aortic root, or the aortic root or similar supporting structure may be retained. The valve is then preserved and/or sterilized. For example, homografts are typically cryopreserved and xenografts are typically cross-linked, typically in a glutaraldehyde solution. The tissue valve may then be attached to the stent.
The other type of stented bioprosthetic valve includes individual valve leaflets which are cut from biological material, e.g., bovine pericardium. The individual leaflets are then positioned on the stent in an assembly that approximates the shape and function of an actual valve.
In the case of either type of stented bioprosthetic valve, the function of the stent is similar. Primarily, the function of the stent is to provide a support structure for the prosthetic valve. Such a support structure may be required because the surrounding aortic or mitral tissue has been removed in harvesting the valve. The support offered by a stent in a valve is important for several reasons. First of all, a valve is subject to significant hemodynamic pressure during normal operation of the heart. Upon closing the valve the leaflets close to prevent backflow of blood through the valve, In the absence of any support structure, the valve cannot function properly and will be incompetent. One function of the stent is to assist in absorbing the stresses imposed upon the leaflets by this hemodynamic pressure. This is typically achieved in existing stents through the use of commissure support posts to which the valve commissures are attached.
Some known stents have been designed such that the commissure support posts absorb substantially all the stresses placed on the valve by hemodynamic pressure. One such stent is a formed piece of spring wire which is bent to form three vertically-extending commissure support posts, each having a U-shape and being connected to the other commissure support posts via arcuate segments of wire. Such a stent is described in U.S. Pat. No. 4,106,129 to Carpentier, et al. In that stent, the leaflet stresses are borne by the commissure posts rotating around and exerting a torque upon the arcuate wire sections between the posts. The composition and structure of this stent also provides for deformability of the orifice-defining elements. A separate insert element in the form of a plastic web is positioned around the wire stent prior to attachment of the valve.
In other types of stents, the commissure posts are fixed to a rigid base and are designed to be substantially flexible along their entire length so that the posts bend in the manner of a fishing pole in response to the stresses imposed upon the leaflets by hemodynamic pressure. An example of such a stent is shown in U.S. Pat. No. 4,343,048 to Ross, et al.
Other stents, for example the stent shown in U.S. Pat. No. 4,626,255 to Reichart, et al., include further support structure connected to and disposed between the commissure support posts. Such support structure prevents a given commissure post from being resilient along its entire length. Still other stents, such as in U.S. Pat. No. 5,037,434 to Lane, include an inner support frame with commissure posts resilient over their entire length, and a relatively more rigid outer stent support which begins to absorb greater stress as the associated commissure support bends further inward.
Although all of these stents provide support to the bioprosthetic valves to which they are attached, the stress distributions are often unnatural, leading to premature wear or degradation of over-stressed portions of the valve. Accordingly, the need exists for stents which more closely approximate the stress response of a natural aortic or mitral valve. Furthermore, the stents which include several parts are mechanically complex and require multiple assembly steps. A stent which includes a stress response that approximates a natural valve would thus also desirably have an integral construction.
Another function of a stent is to serve as a framework both for attachment of the valve, and for suturing of the valve into place in the recipient, e.g., a human patient. Toward that end, the stent, or a portion of the stent, is typically covered with a sewable fabric or membrane, and may have an annular sewing ring attached to it. This annular sewing ring serves as an anchor for the sutures used to attach the valve to the patient.
A variety of different stent designs have been employed in an effort to render valve attachment, and implantation of the valve simpler and more efficient. Design trade-offs have often occurred in designing these stents to have the desirable stress and strain characteristics while at the same time having a structure which facilitates assembly and implantation.
In the stentless valves previously referred to, the unsupported valve is sewn into the recipient's aorta in such a way that the aorta itself helps to absorb the stresses typically absorbed by a stent. Current porcine aortic stentless valves, such as porcine aortic stentless valves, are typically intended for use in the aortic position and not in the mitral position. A mitral valve would require a support structure not presently available with porcine aortic valves, and recently, stentless porcine mitral valves for placement in the mitral position have been developed.
Indeed, the stented valves used in the mitral position utilize the stent to provide support for normal valve function. In these stented mitral valves, a "low profile" stent having generally shorter commissure posts has been used, so as to prevent the ventricle wall from impinging on the valve. However, use of a lower profile stent often requires that the bioprosthetic valve be somewhat distorted upon attachment to the low-profile stent. This, in turn, can lead to reduced functionality of such valves. While the "higher profile" stents can avoid this distortion, care must be given to valve placement so as to avoid the referenced impingement by the ventricle wall. A need exists for a stent for use in the mitral position that includes the advantageous stress/strain and attachment characteristics previously described.
Known stents for bioprosthetic valves have been formed from a variety of materials including both metals and polymers. Regardless of the material employed, the long-term fatigue characteristics of the material are of critical importance. Unusually short or uneven wear of a stent material may necessitate early and undesirable replacement of the valve. Other material characteristics are also considered in selecting a stent material, including: rate of water absorption, creep, and resilience to the radiation which may be used for sterilization. Further, it may be highly desirable to form the stent of a radio-opaque material to allow the stented valve to be viewed by x-ray imaging. Of course, the selected material must also be biocompatible and have the required physical characteristics to provide the desired stress/strain characteristics. Furthermore, most existing stents are formed of a material having a constant cross-sectional dimension. Formed wire stents and stents formed from stamped metal are examples. Use of a material of variable cross section would allow stress and strain characteristics to be carefully controlled by adding or subtracting cross sectional area in certain regions of the stent, as may be required.

Integral supporting structure for bioprosthetic heart valve


An energy generating system for generating thermal energy and electrical energy for a premises. The system includes an engine that drives an AC power generator to supply supplemental or standby power to the premises. The thermal energy given off by the engine is also coupled to the premises to provide heat thereto. A processor controls the various parameters of both the energy generating system and the premises to coordinate the proper heating and cooling thereof.

Many auxiliary electrical generators function as standby units to provide AC power when the power from the utility AC grid is interrupted. The standby generators are often equipped with sensors that sense the absence of AC power from the grid and are started to thereby provide supplemental AC power to the home, office, building or other facility. Many facilities that provide necessary services have standby generators so that such services can continue to be provided. Hospitals and telecommunication providers are examples where the use of standby generators is utilized. Many standby generators are powered by engines that use gasoline or diesel as a fuel. It is not economical to use diesel or gasoline-powered engines to drive generators as the cost of operation due to maintenance and fuel far exceeds the cost of electricity obtained from utility providers.
The acceptance of standby generators relates to the emergency need for electricity, rather than the cost effectiveness of such equipment. In other words, in many situations, the need for electrical power overrides any concern for the cost of providing power in emergency situations. Even at the homeowner level, the cost of electricity delivered by standby means is less important than the comfort provided by the supplemental electricity when the power grid is unable to provide the same. But, the continued supply of AC power to a home when the grid fails, or during a brownout, is a function of the ability of the homeowner to pay for the standby equipment, and is not related to efficiency or cost payback. Accordingly, the luxury of having heat and cooling in a home during a power grid outage is available to those few who can easily afford the standby equipment.
The utilization of engine-driven generators by homeowners is not widespread as the initial cost of such equipment is significant, it requires periodic maintenance even if not used, and the fuel is not stable over long periods of time. When alcohol is added to gasoline by refineries, the alcohol tends to absorb moisture which can cause mechanical as well as operational problems with the engine. It is well known that gasoline deteriorates after six months or so and must be replaced so as to maintain the critical components thereof. The lubricating oil of the standby engine must be replaced periodically, not because the use thereof breaks down the lubricating properties, but because the time of non-use deteriorates the lubricating properties as well as allows the oil to be exposed to environmental moisture.
The efficiency of a gasoline or diesel-powered generator is compromised because such type of engine is at best 30% efficient. The efficiency is low because an internal combustion engine generates substantial heat that is dissipated to the air. The dissipation of heat from an engine is essential to the service life of the engine. A supplemental dissipation of engine heat is through the oil which circulates through the engine, and back to the oil reservoir where it is cooled somewhat. Some engines are specially equipped with oil coolers, which are like water radiators, that allow air to circulate through a separate radiator to cool the oil.
An additional shortcoming of the widespread use of standby generators is the engineering of the same for different individuals or businesses. While standby generators are widely available, they are not easily tailored to specific or specialized applications. In addition, while one can easily purchase a standby AC power unit, there is often a lack of experienced personnel who know how to modify the power delivery equipment of a home or business to make an orderly transition from the power grid to the standby unit easy and as transparent as possible. The normal person who is interested in a standby power unit does not know how many kilowatts of AC power is necessary either during normal use, or during periods of surge currents such as when large AC power-using equipment starts to operate. The proper engineering of the correct size of a standby unit must take into consideration surge capabilities as well as average power used under normal circumstances.
The acceptance of standby AC power generators by more consumers can be facilitated by making the standby units more efficient so that the initial investment is not only recovered, but recovered in a short period of time. When a standby power unit is powered by natural gas or propane gas, the cost effectiveness is enhanced, and such type of fuel does not deteriorate over time, thus eliminating the need to change out the fuel supply every year or so. Moreover, the cost of natural gas is much lower than the corresponding cost of either gasoline or diesel. When the cost of the standby unit is amortized over a period of time, together with the lower cost of fuel, and with the production of thermal energy to heat a house or business, standby units can be much more attractive and cost effective to ordinary persons. In addition to the foregoing, when AC power is available from the power grid, but thermal energy is needed to heat the premises during cold weather, the standby unit can be employed to generate heat and any excess AC power can be coupled back to the AC power grid. In many instances, the delivery of AC power back to the AC power grid can reduce the user's electricity bill from the utility, thereby providing an additional incentive to use the standby unit as often as possible.
In remote areas where electricity is not yet available, such as mountain cabins, lake houses, and the like, the availability of an AC power generator is more attractive especially when AC power can be individually provided to each house, and the thermal energy generated by the AC power unit can be used to heat the premises. In this instance, any excess AC power can be converted to DC and used to charge a bank of batteries for supplementary electrical energy for use by the user. The batteries, solar panels or wind generators can be used to generate hydrogen for use as a fuel for the engine that drives the generator. The hydrogen can be stored for use when needed by the engine.
From the foregoing, it can be seen a need exists for a standby AC power generator that is used more often to accommodate the various needs of the user and thereby make the unit more cost effective.

Energy generating system for supplying energy to a premises


The present invention relates to a functionalized siloxy compound which is useful in silica-filled rubber compositions and the processing of a sulfur curable rubber composition containing silica. Accordingly, the invention further relates to a rubber composition containing at least one diene-based elastomer, particulate synthetic amorphous silica (e.g. precipitated silica) and said functionalized siloxy compound as a coupling agent and to an article of manufacture (e.g. tire) containing a component comprised of such rubber composition.

Sulfur containing organosilicon compounds are useful as reactive coupling agents between rubber which contains carbon-to-carbon unsaturation and synthetic silica fillers (e.g. precipitated silica) providing for improved physical properties.
U.S. Pat. Nos. 6,096,832 and 6,184,306 disclose functionalized siloxy compounds for use in silica-filled rubber compositions as being represented by the general formula (I):
where R1, R2 and R3 are independently selected from the group consisting of alkoxy radicals having from 1 to 8 carbon atoms; R4 is selected from the group consisting of alkylene groups having from 1 to 15 carbon atoms and arylene and alkyl substituted arylene groups having from 6 to 10 carbon atoms; and n is an integer of from 1 to 8.
Functionalized siloxy compounds for use in silica filled rubber are also mentioned in U.S. Pat. No. 4,820,751.
Representative of various functionalized siloxy compounds may be, for example, siloxy compounds containing benzothiazole or thiocarbamyl moieties.
As used herein, the term or phrase "rubber or elastomer containing olefinic unsaturation" is intended to include both natural rubber and its various raw and reclaim forms as well as various synthetic rubbers. As used herein, the terms "rubber" and "elastomer" may be used interchangeably, unless otherwise prescribed. The terms "rubber composition", "compounded rubber" and "rubber compound" may be used herein interchangeably to refer to rubber which has been blended or mixed with various ingredients and materials and such terms are well known to those having skill in the rubber mixing or rubber compounding art.
The term "phr" as used herein, and according to conventional practice, refers to "parts by weight of a respective material per 100 parts by weight of rubber, or elastomer."

Functionalized siloxy compound, silica reinforced rubber compositions thereof and tire with component comprised thereof


A method in a computer system for coordinating scheduling of threads among a plurality of processors. The method includes collecting, using a cooperative scheduling component (CSC), system data pertaining to the plurality of processors. The method further includes calculating, using the CSC, unified scheduling-related parameters (USRPs) from the system data. The method additionally includes furnishing the USRPs from the CSC to at least two of a thread launcher, a thread balancer, and a thread stealer, whereby at least two of the thread launcher, the thread balancer, and the thread stealer employ the USRPs to perform their respective scheduling-related tasks.

In a multi-processor computer system, a scheduler subsystem is often employed to schedule threads for execution on the various processors. One major function of the scheduler subsystem is to ensure an even distribution of work among the processors so that one processor is not overloaded while others are idle.
In a modern operating system, such as the HP-UX® operating system by the Hewlett-Packard Company of Palo Alto, Calif., as well as in many modern Unix and Linux operating systems, the scheduler subsystem may include three components: the thread launcher, the thread balancer, and the thread stealer.
With reference to FIG. 1, kernel 102 may include, in addition to other subsystems such as virtual memory subsystem 104, I/O subsystem 106, file subsystem 108, networking subsystem 110, process management subsystem 112, a scheduler subsystem 114. As shown, scheduler subsystem 114 includes three components: a thread launcher 120, a thread balancer 122, and a thread stealer 124. These three components are coupled to a thread dispatcher 138, which is responsible for placing threads onto the processor's per-processor run queues as will be discussed herein.
Thread launcher 120 represents the mechanism for launching a thread on a designated processor, e.g., when the thread is started or when the thread is restarted after having been blocked and put on a per-processor run queue (PPRQ). As is known, a per-processor run queue (PPRQ) is a priority-based queue associated with a processor. FIG. 1 shows four example PPRQs 126a, 126b, 126c, and 126d corresponding to CPUs 128a, 128b, 128c, and 128d as shown.
In the PPRQ, threads are queued up for execution by the associated processor according to the priority value of each thread. In an implementation, for example, threads are put into a priority band in the PPRQ, with threads in the same priority band being queued up on a first-come-first-serve basis. For each PPRQ, the kernel then schedules the threads therein for execution based on the priority band value.
To maximize performance, thread launcher 120 typically launches a thread on the least-loaded CPU. That is, thread launcher 120 instructs thread dispatcher 138 to place the thread into the PPRQ of the least-loaded CPU that it identifies. Thus, at least one piece of data calculated by thread launcher 120 relates the least-loaded CPU ID, as shown by reference number 130.
Thread balancer 122 represents the mechanism for shifting threads among PPRQs of various processors. Typically, thread balancer 122 calculates the most loaded processor and the least loaded processor among the processors, and shifts one or more threads from the most loaded processor to the least loaded processor each time thread balancer 122 executes. Accordingly, at least two pieces of data calculated by thread balancer 122 relate to the most loaded CPU ID 132 and the least loaded CPU ID 134.
Thread stealer 124 represents the mechanism that allows an idle CPU (i.e., one without a thread to be executed in its own PPRQ) to "steal" a thread from another CPU. Thread stealer accomplishes this by calculating the most loaded CPU and shifts a thread from the PPRQ of the most loaded CPU that it identifies to its own PPRQ. Thus, at least one piece of data calculated by thread stealer 124 relates the most-loaded CPU ID. The thread stealer performs this calculation among the CPUs of the system, whose CPU IDs are kept in a CPU ID list 136.
In a typical operating system, thread launcher 120, thread balancer 122, and thread stealer 124 represent independently operating components. Since each may execute its own algorithm for calculating the needed data, e.g., least-loaded CPU ID 130, most-loaded CPU ID 132, least-loaded CPU ID 134, the most-loaded CPU among the CPUs in CPU ID list 136, and the algorithm may be executed based on data gathered at different times, each component may have a different idea about the CPUs at the time it performs its respective task. For example, thread launcher 120 may gather data at a time t1 and executes its algorithm, which results in the conclusion that the least loaded CPU is CPU 128c. Thread balancer 122 may gather data at a time t2 and executes its algorithm, which results in the conclusion that the least loaded CPU is a different CPU 128a. In this case, each of thread launcher 120 and thread balancer 122 may operate correctly according to its own algorithm. Yet, by failing to coordinate (i.e., by executing their own algorithms and/or gathering system data at different times), they arrive at different calculated values.
The risk is increased for an installed OS that has been through a few update cycles. If the algorithm in one of the components (e.g., in thread launcher 120) is updated but there is no corresponding update in another component (e.g., in thread balancer 122), there is a substantial risk that these two components will fail to arrive at the same calculated value for the same scheduling parameter (e.g., the most loaded CPU ID).
The net effect is rather chaotic and unpredictable scheduling by scheduler subsystem 114. For example, it is possible for thread launcher 120 to believe that CPU 128a is the least loaded and would therefore place a thread A on PPRQ 126a associated with CPU 128a for execution. If thread stealer 124 is not coordinating its effort with thread launcher 120, it is possible for thread stealer 124 to believe, based on the data it obtained at some given time and based on its own algorithm, that CPU 128a is the most loaded. Accordingly, as soon as thread A is placed on the PPRQ 126a for execution on CPU 128a, thread stealer 124 immediately steals thread A and places it on PPRQ 126d associated with CPU 128d.
Further, if thread balancer 122 is not coordinating its effort with thread launcher 120 and thread stealer 124, it is possible for thread balancer 122 to believe, based on the data it obtained at some given time and based on its own algorithm, that CPU 128d is the most loaded and CPU 128a is the least loaded. Accordingly, as soon as thread A is placed on the PPRQ 126d for execution on CPU 128d, thread balancer 122 immediately moves thread A from PPRQ 126d back to PPRQ 126a, where it all started.
During this needless shifting of thread A among the PPRQs, the execution of thread A is needlessly delayed. Further, overhead associated with context switching is borne by the system. Furthermore, such needless shifting of threads among PPRQs may cause cache misses, which results in a waste of memory bandwidth. The effect on the overall performance of the computer system may be quite noticeable.

Hewlett-Packard Development Company, L.P.


The present invention provides a radiation hardened flip-flop formed from a modified temporal latch and a modified dual interlocked storage cell (DICE) latch. The temporal latch is configured as the master latch and provides four output storage nodes, which represent outputs of the temporal latch. The DICE latch is configured as the slave latch and is made of two cross-coupled inverter latches, which together provide four DICE storage nodes. The four outputs of the temporal latch are used to write the four DICE storage nodes of the DICE latch. The temporal latch includes at least one feedback path that includes a delay element, which provides a delay.

Electronic circuits, and in particular circuits that involve storing electronic states, are vulnerable to high-energy sub-atomic particles and electromagnetic radiation. Many high-altitude flight, outer space, military, and nuclear applications require that such vulnerability be reduced to an acceptable level. The techniques that are used to reduce the vulnerability of these circuits to the effects of radiation are generally referred to as radiation hardening. For the most part, radiation hardening involves employing special circuit designs, circuit layouts, the use of select materials, or any combination thereof to increase the robustness of the circuit. Long-term radiation effects that may impact the long-term functionality of the circuit are referred to as total ionizing dose (TID) effects and are often mitigated using special circuit layer techniques.
Another type of radiation effect that is becoming more of an issue is referred to a single event effect (SEE). When a high-energy particle passes through a semiconductor providing the electronic circuit, excess charge may be left in the semiconductor along the path through which the particle passes. If excess charge is left on or near a node that is charged to a level representing a desired logic state, the excess charge may change the level of charge at the node. The change in charge level may result in the node changing from the desired logic state to another logic state. For example, if an ionized particle of radiation passes through a bi-state storage node that is charged for a logic 1, excess electrons from the ionized particle may collect at the storage node and discharge the storage node to a charge level corresponding to a logic 0. The effect of the change in charge level of the storage node may result in a temporary transient, where the storage node returns to the charge level for a logic 1 and does not upset the overall output of the of the electronic circuit. This type of SEE is referred to as a single event transient (SET). If the effect of the change in charge level of the storage node completely changes the output of the circuit, where the output does not return to the proper state, a single event upset (SEU) is said to occur. Generally, SETs and SEUs are temporary, unlike TID effects, which are more permanent, long-term radiation effects.
Latches are frequently used circuits that include storage nodes and benefit from being hardened to radiation. Exemplary radiation hardened latches include the dual interlocked storage cell (DICE) latch and a classic temporal latch. A traditional DICE latch is illustrated in FIG. 1. The DICE latch includes two cross-coupled inverter latches formed from PMOS transistors T1-T4 and complementary NMOS transistors T5-T8. The first cross-coupled inverter latch is formed from transistors T1, T2, T5, and T6 while the second cross-coupled inverter latch is formed from transistors T3, T4, T7, and T8.
Notably, node X0 is formed where transistors T1 and T5 are coupled, node X1 is formed where transistors T2 and T6 are coupled, node X2 is formed when transistors T3 and T7 are coupled, and node X3 is formed where transistors T4 and T8 are coupled. Node X0 is coupled to the gate of transistor T2 as well as the gate of transistor T8. Node X1 is coupled to the gates of transistors T5 and T3. Node X2 is coupled to the gates of transistors T6 and T4. Node X3 is coupled to the gates of transistors T7 and T1, and provides the output Q of the DICE latch.
The traditional DICE latch has only two inputs, which are connected to nodes X0 and X2. These two inputs are represented as nodes M0 and M1, which are respectively coupled to nodes X0 and X2 through pass transistors T9 and T10. A clock signal, CLKb, controls when the values on nodes M0 and M1 are written to nodes X0 and X2. As illustrated, when the clock signal CLKb is asserted low, the values on nodes M0 and M1 are written to nodes X0 and X2.
Generally, node X0 is at the same state as node X2. Similarly, node X1 is at the same state as node X3, which is the opposite state of nodes X0 and X2. Accordingly, the output Q, which corresponds to node X3, is generally the opposite logic state that is stored on nodes X0 and X1.
To radiation harden the DICE latch, the nodes X0-X3 must be physically separated from each other to an extent that will prevent any two of the nodes X0-X3 from being hit by a single radiation particle. As such, if one of the nodes X0-X3 is struck by a radiation particle and as a result has its state changed, the remaining nodes X0-X3 will effectively override the state change at the affected node such that the output Q is at most subjected to a transient glitch. The overall state of the DICE latch is not upset. When the affected node X0-X3 changes state in response to being struck by the radiation particle, the remaining nodes X0-X3 will operate to restore the affected node X0-X3 to its proper state.
One of the drawbacks of the traditional DICE latch is that it is prone to capturing the wrong logic states if nodes M0 and M1 have the wrong logic state when the clock signal CLKb is asserted low and the DICE latch is in a transparent mode. Although the DICE latch is relatively compact and has been proven effective in mitigating SEUs, it is vulnerable to SETs while in a transparent mode. Accordingly, there is a need for a technique to provide radiation hardened DICE latches that are not vulnerable to SETs while in transparent modes.
A classic temporal latch is illustrated in FIG. 2. The temporal latch employs three redundant feedback paths that are separated in time by intentionally differing delays. As illustrated, the first feedback path corresponds to node N2, the second feedback path corresponds to the delay circuit D1 and node MDb, and the third feedback path corresponds to delay circuits D2 and D3 as well as node MDDb. The delay circuits D1, D2, and D3 each provide a fixed delay δ. Those skilled in the art will recognize that the delays provided by each of the delay circuits D1, D2, and D3 may be different from one another, but for the purposes of illustration they are assumed to each provide the same delay δ.
The inputs to the temporal latch are a data input D and a clock signal CLK. The data input D is passed through a pass gate formed by transistors T11 and T12 to a node N1. The logic state of node N1 is inverted by an inverter I1 and presented to the beginning of each of the three redundant feedback paths. Each of the three redundant feedback paths terminates a corresponding input of an inverting majority gate MG1. The basic functionality of a majority gate is to provide an output corresponding to that of the majority of the inputs.
An exemplary majority gate is depicted in FIG. 3. As illustrated, the majority gate has three inputs, input A, input B, and input C. The majority gate is formed from six PMOS transistors T15-T20 and six NMOS transistors T21-T26, which are arranged in three complementary inverter stacks. When any two or more of the inputs A, B, and C are a logic 1, at least one pair of series NMOS transistors T21-T26 are turned on and pull the output OUT to a logic 0. Similarly, when any two or more of the inputs A, B, and C are a logic 0, at least one pair of the PMOS transistors T15-T20 are turned on and pull the output OUT to a logic 1. For example, if inputs A and B are a logic 1 and input C is a logic 0, transistors T21 and T22 are turned on and the output OUT is pulled to a logic 0. The other two stacks that include transistors T23-T26 are not pulled to a logic 0, because transistors T24 and T26, which are driven by input C, are turned off. Although input C is a logic 0, this will not affect the output OUT.
Returning to FIG. 2, the majority gate MG1 will receive three inputs from the three feedback paths and provide an output that corresponds to the majority of the three inputs. For example, if two or three of the three inputs are a logic 0, the output will be a logic 1, because the majority gate illustrated is an inverting majority gate. Similarly, if two or three of the inputs were a logic 0, the output of the majority gate MG1 would be a logic 1. In essence, the majority gate MG1 will filter out those inputs that are not in line with the majority of inputs. The output of the majority gate MG1 is fed through a pass gate formed by transistors T13 and T14 back to node N1. Notably, the logic state of node M, which corresponds to the output of the majority gate MG1 or the logic state of the input D, is alternately passed to node N1 through the respective pass gates in response to the clock signal CLK or CLKb as inverted by inverter I2.
The temporal latch provides immunity to SETs in the following manner. If the input D temporarily transitions to the wrong logic state for a duration less than the delay δ, the resulting transient is passed to the majority gate MG1 through the three different feedback paths at different times. In particular, a delay of δ is provided between the transients that appear on the three feedback paths. Assuming the transient is less than the delay δ, the majority gate MG1 will only see the transient on one input at a time. Since there are three inputs, a transient on a minority input will not affect the output of the majority gate MG1. In other words, assuming the transient has a duration of less than the delay δ, two of the three feedback paths will always have the correct logic state and the output of the majority gate MG1 will be based on the correct logic states. The temporal latch basically filters out any transients on the input D where the transients have a duration less than the delay δ. In a similar fashion, the temporal latch will filter out transients appearing on the clock signal CLK or CLKb through the same overall feedback loop. In addition to addressing transients on the input D and the clock signal CLK, transients appearing in the feedback paths, such as along nodes N2, MDb, and MDDb, are filtered out as long as no two nodes are affected at the same time.
One drawback of the temporal latch is that it typically cannot handle simultaneous hits on multiple nodes in the feedback paths. Further drawbacks include not being able to provide immunity to SETs that last longer than the delay δ. Unlike the DICE latch of FIG. 1, the temporal latch tends to be quite large due to the number of transistors and other components required for the delay circuits D1, D2, and D3. Accordingly, there is a need for a latch that overcomes the deficiencies of the temporal latch while maintaining its benefits.

Radiation hardened master-slave flip-flop

Arizona Board of Regents for and on behalf of Arizonia State University


A device for dosing and forming pods (1) containing a product for infusion and comprising a piece of filter material containing a dose of the product for infusion. The device comprises: a station (2) for feeding the product into at least one forming impression (3) defining a single dose of the product and made in means (4) for forming a respective compressed disk (5) of the infusion product and releasing the compressed disk (5) from the impression (3) in the filter material to form the pod (1).

In the current market of products for infusion, such as coffee, barley coffee, tea and camomile, the use of single-dose "pods" has increased considerably and a very popular way of making American-style coffee is now to use such pods in specially designed machines, even for household or office use (that is, for small to medium quantities).
This specification does not concern other forms of filter bags normally used to make American-style coffee and consisting of a "maxi dose" bag designed to be placed in a funnel-like container at the top of a machine that supplies boiling hot water. The hot water comes into contact with the coffee filter bag producing a brew of coffee which is simply allowed to drip into a cup below.
Unlike this type of solution—which is widely used and extremely popular—pods used to brew a single serving of beverage usually consist of two portions of filter paper placed one over the other and sealed to enclose a single product dose of circular shape.
In the specific case of pods for American-style coffee, the product is not (and must not be) excessively compressed, which means that it remains relatively loose inside the pod.
For technical reasons linked to the type of machines used to make them, the pods have an asymmetrical profile, that is to say, with one flat surface (defined by one of the portions of filter paper) and one cupped surface (defined by the other portion of filter paper) containing the dose of infusion product.
One prior art method and related apparatus for making this type of pod is described in patent EP-432.126. The method disclosed therein comprises the following sequence of steps:                feeding a first web of filter paper to a station where suitable means cause the filter paper to be wrinkled or crinkled;        moving the web of filter paper along the surface of a forming drum, provided with circular pockets and with suction means, and simultaneously training a belt in contact with the filter paper, with the filter paper being between the belt and the surface of the forming drum, so that spaced areas of the belt are pulled by suction into the pockets in the drum, drawing the filter paper along with it in such a way as to form a succession of pouches in the filter paper;        filling a dose of product into each pouch by means of a dosing station located downstream of the suction drawing belt in the direction of rotation of the pouch forming drum and consisting of a second revolving drum synchronised with the pouch forming drum;        joining the first web of filter paper, provided with the product filled pouches, to a second web fed at a respective sealing station located downstream of the filling station, again relative to the direction of rotation of the forming drum;        cutting out the pods thus made and feeding them out towards further packaging stations.
The structure of the dosing and forming unit of the apparatus has several disadvantages due to:                the need to pre-process the web of filter paper to make it suitable for forming the pouches, which means that the apparatus requires an additional station; this operation being necessary especially when two or more parallel rows of pouches are formed in the filter paper web; and        the possible difficulty of accurately controlling the volume of product filled into each pouch on account of the two revolving cylindrical surfaces of the drums (dosing and forming); this can cause a certain amount of product being lost as it is gravity fed into the pouch.
The aim of the present invention is to overcome the above mentioned drawbacks by providing a device with a simple structure for dosing and forming disks for pods containing products for infusion and that allows the disk of infusion product to be formed in a manner that is at once practical, fast and reliable in dosing the product, and enables the product disk to be placed on a web of filter paper at high operating speeds.

Device for dosing and forming disks for pods containing a product for infusion

I.M.A. Industria Macchine Automatiche S.p.A.


A system and method for processing financial payments including a user terminal, an account processor, and a processing server. The processing server receives financial transaction data from the user terminal and communicates with the account processor, the financial transaction data comprising an amount and an account number. The processing server determines which of the account processors corresponds to the financial transaction data and transmits at least part of the financial transaction data to the determined account processor.

The present invention relates to a system and method for automated financial transaction processing and, more specifically, to a system and method for processing financial transaction data, including payment, refund, and loan funding data, using a standard web browser in which the system automatically updates, from a group of account processors, the account processor associated with a particular account.
Extensive manual effort is often involved to properly locate and apply a payment (or data corresponding to a financial transaction) to an account in the case where a financial or payment processing institution maintains multiple payment or other financial transaction accounting systems, especially loan payment systems. This situation results from debtors who wish to make a payment to their account, but do not have their payment stub, have an incomplete account number, or have only an account number with no other means of identifying which of the payment systems their account is based. These types of payments are referred to herein as miscellaneous payments.
Tellers or other individuals who interact with customer account holders are often too busy and do not have access to the tools necessary to investigate which processing system is associated with the customer's account. In this case, the teller typically sets the payment aside for manual processing by an operator whose responsibility it is to determine which payment system maintains the account associated with the customer's payment. The operator is typically located at a site remote from the teller's branch, and services many groups of miscellaneous payments from a large region.
A typical procedure employed by financial transaction or payment system owners to process miscellaneous payments and financial transactions including loan funding, loan refunds, and other payables will be described with reference to FIG. 1. In order to determine the financial transaction system associated with a particular account, one or more operators 2 must use one or more terminals 4 to log into each account processor 6 and search for a valid account. Account processors 6 are typically mainframe based programs used to track debit and credit transactions such as loan balances, payments thereto and refunds. Once a valid account is located, operator 2 must then process the payment or refund.
To process the payment, operator 2 first applies a credit to the account in the amount of the payment. Operator 2 prepares a magnetic ink character recognition (MICR) encoded proof ticket, and forwards the remittance provided by the customer such as the check or cash substitute payment slip and the proof ticket to the department responsible for ensuring that the loan owner, i.e., bank, receives payment from the customer's checking account (hereinafter "demand deposit account" or "DDA") or credit card account owner.
Once the payment data has been entered into the appropriate account processor 6 and the remittance and proof ticket forwarded to the appropriate department, operator 2 must then access the payment system owner's general ledger 8 and make one or more updating entries. General ledger 8 is typically a computer based program and database used to track corporation-wide accounting activity. General ledger 8 typically resides on a mainframe computer.
This process requires that each operator 2 have knowledge of the back end systems, i.e., account processor 6, and how to access and operate these systems. The above-described process is inefficient, requiring operators 2 to individually access multiple account processors 6, search for a valid account number in that system, individually apply payments to those systems, and subsequently access and update general ledger system 8. This level of activity decreases the quantity of miscellaneous payments which can be processed by operator 2 and leads to payment processing errors.
In addition, terminal 4 is typically a mainframe terminal or a personal computer ("PC") running mainframe emulation software. Depending on the particular networking environment of the processing system owner, terminal 4 can have dedicated access to only one or a subset of the systems. In this case, user 2 must move from terminal 4 to a different terminal 4 in order to determine which system is associated with an account number. In the case where terminal 4 has access to multiple account processors 6, each operator 2 must still separately log into each processor 6 to determine account association. These multiple logins further decrease operator payment processing efficiency.
It is therefore desirable to have a financial transaction processing system which can automatically determine which account processor 6 a particular payment is associated with, automatically update that system and automatically make the proper accounting treatment entries to general ledger 8. It is also desirable to have a financial transaction processing system which does not require that operator 2 have any special knowledge of the underlying account processors 6.
Special data entry application software is often required in the case where terminal 4 is a PC running mainframe emulation software. As a result, technicians are required to visit each terminal 4 to upgrade data entry applications, terminal emulators and keystroke macros. Also, the use of special emulation software requires particularized operator training such that operator 2 must be trained as to the operation of the software in addition to the processing institution's payment processing procedures. This creates significant expense for the system owner and adds to the inefficiency of payment processing.
In an effort to avoid visits by technicians to terminals 4, systems have been developed which push, i.e., roll out, the application software from a central computer to a permanent storage device within terminal 4 when the terminal is turned on or when an operator logs onto the system. Application roll out is typically used to push software updates to terminal 4. This type of roll out, however, is problematic because pushing applications to a terminal is highly error prone and sensitive to the hardware and software configuration of the terminal. As a result, roll outs often fail and a technician is forced to visit the terminal to complete the software installation and resolve any other problems caused by the failed roll out.
It is therefore also desirable to have an interface on terminal 4 for operator 2 which does not require special customized data entry application software or multiple visits by technicians to upgrade this software, and which does not require specialized training to use (other than the actual payment processing procedures).

Network based financial transaction processing system


A method of transmitting data is disclosed. The method transmits data from a source device over a contention channel in a centralized network to more than one device on the channel, including a central coordinator. The method then waits for a data acknowledgment signal from the central coordinator as an indicator of successful reception of the data by any device to which the data was transmitted.

Some networks have a centralized controller that provides scheduled point-to-point communications, and may also coordinate a contention channel. These networks may also allow point-to-multipoint communication links between devices, but only of limited capacity. These types of networks will be referred to as centralized networks. In contrast, networks that have a shared medium, such as those having a broadcast channel, or those that have no centralized controller, such as Internet Protocol (IP) networks or other distributed networks operating by an agreed-upon standard.
In centralized networks, communications between devices are generally scheduled and controlled by the central controller. If device A needs to send something to device B, device A must either send the communication to the central controller, which then sends it to device B, or device A must send a message to the central controller indicating the desire to send something to device B. In the latter example, the central controller then notifies all of the devices on the network to stay off the network at a certain point in time, as device A will be allowed to send the communication to device B at that time. Some systems may support a contention access channel, a first-come-first-served channel access for which the devices contend.
Because of the point-to-point nature of these systems, as well as the need for a centralized controller, there are no current methods to allow for broadcast or multicast messages in these systems. A broadcast message is one sent to all devices on the network, while a multicast system is one sent to a specified subset of the network. Centralized networks may have the ability to send point-to-multipoint messages, which are in essence a multicast message, but the capabilities are limited.

Transmitting data across a contention channel in a centralized network


Coke is burned in the regenerator vessel of an FCC complex with a combustion medium consisting of a diluent gas, such as air, enriched with oxygen, The regenerator is operated in partial combustion mode and excess oxygen is introduced into the combustion zone of the regenerator. Emission of nitrogen oxides to the atmosphere is reduced.

In catalytic cracking processes hydrocarbon feedstock is injected into the riser section of a hydrocarbon cracking reactor, where it cracks into lighter, valuable products on contacting hot catalyst circulated to the riser-reactor from a catalyst regenerator vessel. As the endothermic cracking reactions take place, the catalyst gets covered with coke deposits. The catalyst and hydrocarbon vapors are carried up the riser to the disengagement section of the reactor, where they are separated. Subsequently, the catalyst flows into the stripping section, where the hydrocarbon vapors entrained with the catalyst are stripped by steam injection, and the stripped catalyst flows through a spent catalyst standpipe and into the catalyst regenerator vessel.
Typically, the catalyst is regenerated by introducing air into the regenerator vessel to burn coke off the catalyst, thereby rejuvenating it. The coke combustion reactions are highly exothermic and heat the catalyst. The hot, reactivated catalyst flows through the regenerated catalyst standpipe back to the riser to complete the catalyst cycle. The coke combustion exhaust gas stream rises to the top of the regenerator and leaves the regenerator through the regenerator flue. The exhaust gas contains nitrogen and carbon dioxide (CO.sub.2), and generally also contains carbon monoxide (CO), oxygen, sulfur oxides (SO.sub.x), nitrogen oxides (NO.sub.x) and reduced nitrogen species, such as ammonia.
The catalyst regenerator may be operated in complete combustion mode, which has now become the standard combustion mode, or in partial CO combustion mode. In complete combustion operation, the coke on the catalyst is completely burned to CO.sub.2. This is typically accomplished by conducting the regeneration in the presence of excess oxygen, provided in the form of excess air. The exhaust gas from complete combustion operations comprises primarily CO.sub.2, nitrogen and excess oxygen, but also contains NO.sub.x and SO.sub.x.
In partial carbon monoxide combustion mode operation, the catalyst regenerator is operated with insufficient air to burn all of the coke in the catalyst to CO.sub.2, consequently the coke is combusted to a mixture of CO and CO.sub.2. The CO is oxidized to CO.sub.2 in a downstream CO boiler. The effluent from the CO boiler comprises primarily CO.sub.2 and nitrogen, but also contains NO.sub.x and SO.sub.x.
Recently, there has been considerable concern about the amount of NO.sub.x and SO.sub.x being released to the environment in refinery flue gases. It is now the accepted view that most of the NO.sub.x present in catalyst regenerator exhaust comes from coke nitrogen, i.e. nitrogen contained in the coke in the form of heterocompounds such as condensed cyclic compounds, and that little or none of the NO.sub.x contained in the exhaust gas is derived from the nitrogen contained in the air feed to the regenerator. The mechanism by which the coke nitrogen ends up as NO.sub.x differs, depending on whether the regenerator is operated in complete combustion mode or in partial combustion mode. In complete combustion mode regenerator operation, coke nitrogen is converted to a mixture of NO.sub.x and elemental nitrogen. In this operational mode, the amount of NO.sub.x in catalyst regenerator flue gas tends to increase as the excess oxygen concentration from the regenerator increases.
When the regenerator is operated in partial CO combustion mode, very little NO.sub.x is produced in the regenerator, and coke nitrogen leaves the regenerator as reduced nitrogen species, such as ammonia. The reduced nitrogen species are unstable in the CO boiler, and they are easily converted to NO.sub.x and elemental nitrogen.
Several approaches have been used in industry to reduce NO.sub.x in cracking catalyst regenerator exhaust gases. These include capital-intensive and expensive options, such as pretreatment of reactor feed with hydrogen and flue gas post-treatment options; intermediate cost options, such as split-feed injection to the hydrocarbon reactor, and less expensive options, such as the use of catalysts and catalyst additives.
Efforts to reduce NO.sub.x from boiler stacks downstream of FCC units operated in partial combustion mode are centered on the reduction of ammonia and other NO.sub.x precursors in regenerator flue gas. U.S. Pat. No. 4,755,282 discloses the use of a noble metal on an inorganic support to reduce the ammonia content of flue gas from regenerators. U.S. Pat. No. 4,744,962 teaches the addition of NO.sub.x either to the regenerator or to the downstream flue gas line. U.S. Pat. No. 5,021,144 teaches the reduction of ammonia from a regenerator operated in partial CO combustion, by the addition of excess amounts of CO promoter.
U.S. Pat. No. 5,268,089 teaches that NO.sub.x can be reduced by regenerator operation "on the brink", i.e. in a region between conventional partial CO combustion operation and complete combustion operation with less than 0.05 mol % excess CO. The patent indicates that by operating in this mode, the reduced nitrogen species, such as ammonia, which are formed in partial CO combustion operation, are oxidized to nitrogen oxides and elemental nitrogen, and because of the prevailing reducing environment in the regenerator, the nitrogen oxides are reduced to elemental nitrogen prior to leaving the regenerator. Drawbacks associated with operating in the above-described mode are the existence of very high regenerator temperatures and afterburn, in addition to the difficulties associated with regenerator controllability.
Several patents disclose the reduction of NO.sub.x in FCC regenerators by means of promoters, segregated feed cracking, post treatment of exhaust gas, etc. These patents are discussed in detail in U.S. Pat. No. 5,268,089, the disclosure of which is incorporated herein by reference.
Because of considerable pressure from environmentalists and others to avoid polluting the atmosphere with noxious gases, efforts are continuously underway to find new and improved methods of reducing the concentration of NO.sub.x and SO.sub.x in industrial flue gases, such as FCC regenerator exhaust gases. This invention provides a method of taking advantage of the peculiar nitrogen chemistry in partial CO combustion to reduce the amount of effluent NO.sub.x by enriching selected zones in the regenerator with oxygen.

Reduction of emissions from FCC regenerators


A device, including a semiconductor chip having a plurality of first electrodes is disclosed. A plurality of second electrodes is arranged on a first surface of the semiconductor chip. A first electrically conductive layer is applied over a first section of the first surface and electrically coupled to the first electrodes arranged within the first section. A second electrically conductive layer is applied over the first electrically conductive layer and electrically coupled to the second electrodes arranged within the first section.

This invention relates to a device that includes a semiconductor chip having a plurality of electrodes on one of its surfaces and a method of assembling thereof.
Power semiconductor chips may have a plurality of electrodes on one surface. Power semiconductor chips are suitable, for the switching or control of currents and/or voltages. Power semiconductor chips may, for example, be configured as power transistors, power diodes or IGBTs (Insulated Gate Bipolar Transistors).

Device including a semiconductor chip having a plurality of electrodes


A client-server database system enables persistent client-server database sessions, without modification to a client-side application, a database system, or native client-side database drivers. The client is implemented with a driver manager to facilitate communication between the native database drivers and the database application. The driver manager wraps the native drivers, intercepting queries passed from the database application to the database drivers. The driver manager modifies the queries to form modified queries that direct the database server to render result sets produced from processing the queries persistent at the database server. Upon recovery following a server crash, the driver manager directs the drivers to reestablish a connection with the database server. The driver manager then finds the persistent result set table and, using logged data, returns to the same operation on the result set table just prior to the crash. The driver manager then reassociates the application context to the new database session without the database application being aware that a failure occurred. The recovery is thus transparent to the client-side application.

Computer systems occasionally crash. A "system crash" is an event in which the computer quits operating the way it is supposed to operate. Common causes of system crashes include power outage, application operating error, and computer goblins (i.e., unknown and often unexplained malfunctions that tend to plague even the best-devised systems and applications). System crashes are unpredictable, and hence, essentially impossible to anticipate and prevent.
A system crash is at the very least annoying, and may result in serious or irreparable damage. For standalone computers or client workstations, a local system crash typically results in loss of work product since the last save interval. The user is inconvenienced by having to reboot the computer and redo the lost work. For servers and larger computer systems, a system crash can have a devastating impact on many users, including both company employees as well as its customers.
Being unable to prevent system crashes, computer system designers attempt to limit the effect of system crashes. The field of study concerning how computers recover from system crashes is known as "recovery." Recovery from system crashes has been the subject of much research and development.
Current database systems support fault-tolerance and high availability by recovering quickly from system failures. In general, the goal of redo recovery is to return the computer system after a crash to a previous and presumed correct state in which the computer system was operating immediately prior to the crash. Then, transactions whose continuations are impossible can be aborted.
Much of the recovery research focuses on database recovery for database computer systems, such as network database servers or mainframe database systems. Imagine the problems caused when a large database system having many clients crashes in the midst of many simultaneous operations involving the retrieval, update, and storage of data records. Database system designers attempt to design database recovery techniques that minimize the amount of data lost in a system crash, minimize the amount of work needed following the crash to recover to the pre-crash operating state, and minimize the performance impact of recovery on the database system during normal operation.
While database recovery techniques are helpful for recovering data, the techniques offer no help in recovering applications that are interacting with the database at the time of failure. Currently, such applications either fail, resulting in an application outage, or are forced to cope with database failures assuming they survive the database crash. The former compromises application availability and can increase operational complexity. The later either severely restricts application flexibility or increases its complexity.
When an application fails because of a database system crash, organizations responsible for the application need to quickly bring the application back on line. In the enterprise-computing world, time is quite literally money. Database recovery ensures that the database state is consistent. However, an application retaining state across database transactions can have consistency requirements that are not captured at the database transaction boundary. Furthermore, parts of the application state may be lost during a crash. Restoring and continuing application execution is all too frequently a very complex and time-consuming operational problem.
In some system configurations, an application can survive a database system crash. For example, when the application executes on a client machine while the database is on a separate server. This permits the application to include logic to deal with database crashes and hence avoid an application outage. However, handling errors or exceptions is a very difficult part of getting applications right. Dealing with database system failures at the application level is tedious and error-prone, even when the application itself stays alive.
There has been some work in this area. One technique exploits logging and recovery techniques to enable applications to be recoverable. See, e.g., Lomet, D. Application recovery using generalized redo recovery. Int'l. Conference on Data Engineering, Orlando, Fla. (February, 1998); and Lomet, D. and Tuttle, M. Redo recovery from system crashes. VLDB Conference, Zurich, Switzerland (September 1995) 457-468. The focus of this work has been to minimize the impact of providing recovery on the normal operation of the system. In practice, this means minimizing the amount of logging and application checkpointing required. Sometimes, it means making the application an object that can be managed by the database recovery manager.
Other prior work on application fault-tolerance in distributed systems is based on some form of application "installation points" and/or "message logging". The prior work can be categorized into the following three approaches, all of which incur high normal operation and/or recovery costs: (1) fault-tolerant process pairs, (2) distributed state tracking, and (3) persistent queues.
Another client-server system directed to application recovery is described in U.S. patent application Ser. No. 09/033,511, entitled "Client-Server Computer System With Application Recovery of Server Applications and Client Applications", which was filed Mar. 2, 1998 in the names of David B. Lomet (an inventor in this invention) and Gerhard Weikum. This application is assigned to Microsoft Corporation.
Despite these efforts, there remains a need to improve application recovery techniques in client-server database systems. Particularly, there is a need to provide application recovery at modest system implementation cost that avoids modification to the application itself.

Persistent client-server database sessions


A DC superconducting cable which is formed by housing stranded three cable cores in a thermal insulation pipe and in which structure for absorbing thermal contraction occurring during cooling can easily be achieved by adjusting the stranded state of the cores. Also, the structure in which three cores are housed together in the thermal insulation pipe enables the simultaneous cooling of the three cores, allowing the cooling system to be simplified.

Three-core high temperature superconducting cables (three-core HTS cables) are known as conventional alternating current (AC) superconducting cables (see, for example, Japanese Patent Application Publication Nos. 9-134620 and 2001-202837). In these cables, a three-core stranded unit is housed in a thermal insulation pipe. Each cable core is formed of, sequentially from the center, a former, a superconducting cable conductor, an electrical insulating layer, and a shielding layer. Generally, a space formed in the former and a space formed between the thermal insulation pipe and each cable core serve as coolant channels. The superconducting cable conductor is formed by stranding superconducting wires in multilayers, and the spiral pitch and the winding direction are adjusted so that the impedances of the layers become uniform to allow a current to flow uniformly. The shielding layer is formed by using superconducting wires in a similar structure as the superconducting cable conductor.
As described above, in AC superconducting cables, a conductor is formed by winding the superconducting wires spirally so that the current may become radially uniform. However, AC loss is caused by the inductance, and the transmission current is restricted to that extent. Also, in the AC line system, the short-circuit current becomes large in the event of failure, and as a result, the temperature increases, which is also disadvantageous.
Accordingly, transmission using DC superconducting cables is also considered. DC superconducting cables are used for long-distance or bulk-power transmission. The conductor size must be increased in order to perform bulk-power transmission, and thus, the use of single-core cables has been considered.
However, known single-core DC superconducting cables have the following drawbacks.
(1) It is difficult to simplify the cooling system.
For conducting bipolar power transmission, a plurality of cables is required. However, since the superconducting cables are independently cooled in practice, the system becomes complicated, and the system cost also increases.
(2) It is difficult to take measures against the contraction of cable cores occurring during cooling.
In known AC cables, in order to provide an allowance for thermal contraction of cores, a three-core stranded unit is loosened in advance, or a spacer is interposed at the center of the stranded cores. However, in DC superconducting cables using single-core cables, measures against contraction cannot be taken by the adjustment of stranding. If the cores are not loosened, a tensile stress is generated in superconducting cable wires during cooling. This requires the use of wires resistant to this tensile stress. Thus, it is difficult to implement measures against the contraction.


A fuel cell can be heated, upon starting thereof, by supplying hydrogen gas from a hydrogen tank to a hydrogen adsorbing alloy tank so as to be adsorbed therein. The hydrogen adsorbing alloy tank adsorbs the hydrogen gas with generation of heat. The heat thus generated is transmitted to the fuel cell by cooling water circulating between the hydrogen adsorbing alloy tank and the fuel cell, whereby the temperature increases.

1. Field of the Invention
The invention generally relates to a fuel cell system including a hydrogen tank for supplying hydrogen gas and a fuel cell for receiving the hydrogen gas and generating electric power, a method of controlling the system, and a vehicle mounted with the system. More particularly, the invention relates to a fuel cell system capable of controlling the temperature of a fuel cell, a method of controlling the system, and a vehicle mounted with the system.
2. Description of the Related Art
When a vehicle with a fuel cell system including both a high-pressure hydrogen tank and a fuel cell is used in, e.g., a cold region in winter, the ambient temperature is so low (e.g., below 0° C.) that the fuel cell (e.g., electrolyte membranes therein) may possibly be in a frozen state before the fuel cell system is started. The fuel cell cannot be operated in such a state. Accordingly, when the fuel cell system is to be started, the fuel cell can be operated only after thawing the fuel cell, i.e., after heating the fuel cell to normal temperature (e.g., 0° C. or higher).
In such a case, the related art employs a method of heating the fuel cell or the cooling water circulating therein by using an electric heater or a combustion heater.
The related art also employs the same method in the case where the temperature of the fuel cell does not rise to a proper temperature even after the fuel cell has begun operation.
For example, the method using the electric heater requires a large-capacity battery to be mounted on the vehicle in order to supply electric power to the electric heater.
In the method using the combustion heater, hydrogen gas (i.e., fuel to be supplied to the fuel cell) is supplied to the combustion heater and burnt therein. Accordingly, the fuel (hydrogen gas) thus supplied to the combustion heater is used only for combustion, not at all for generation of electric power in the fuel cell. This is a loss of energy from the standpoint of power generation. Note that even the method using the electric heater is subjected to the same problem if electric power generated by the fuel cell is accumulated in the battery for use in heating the electric heater.
It is also possible to entirely wrap the fuel cell in a heat insulating material to keep the fuel cell warm. In this method, however, the fuel cell can be kept at a proper temperature for a certain time after operation of the fuel cell is terminated, but the temperature of the fuel cell falls to the ambient temperature over time. Therefore, the fuel cell must still be heated to a proper temperature upon starting of the fuel cell system after a long interval of non-use.

Fuel cell system, method of controlling the same, and vehicle mounted with the same


A semiconductor memory device including (A) a global line; (B) a memory array having (i) a local line, (ii) a decoder connected to the global line and the local line, and (iii) a memory block and a redundant block each constructed by a plurality of memory cells each having a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a diffusion region disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and a memory functional unit formed on both sides of the gate electrode and having the function of retaining charges, the memory array having the function that when the decoder is usable, the global line is selectively connected to one of the local lines in accordance with address information and, when a defective block is included in the memory blocks and the decoder is unusable, the local line is separated from the global line and the defective block is replaced with the redundant block; and (C) a circuit for making the decoder of the defective block unusable and, only when the defective block is addressed, for making the decoder of the redundant block usable.

1. Field of the Invention
The present invention relates to a semiconductor memory device and a portable electronic apparatus. More particularly, the present invention relates to an electrically erasable and writable semiconductor memory device including a decoder for a memory block and a decoder for a redundant block capable of replacing a defective block found in a memory array with a redundant block without exerting an influence on the other blocks, and to a portable electronic apparatus having the semiconductor memory device.
2. Description of the Related Art
Conventionally, a flash memory is typically used as a nonvolatile memory.
In a flash memory, as shown in FIG. 27, a floating gate 902, an insulating film 907 and a word line (control gate) 903 are formed in this order on a semiconductor substrate 901 via a gate insulating film. On both sides of the floating gate 902, a source line 904 and a bit line 905 are formed by a diffusion region, thereby constructing a memory cell. A device isolation region 906 is formed around the memory cell (see, for example, Japanese Unexamined Patent Publication No. HEI 5(1993)-304277).
The memory cell retains data according to the more or less a charge amount in the floating gate 902. In a memory cell array constructed by arranging the memory cells, an operation of rewriting/reading a desired memory cell can be performed, by selecting a specific word line and a specific bit line and applying a predetermined voltage.
In such a flash memory, when a charge amount in the floating gate changes, a drain current (Id)-gate voltage (Vg) characteristic as shown in FIG. 28 is displayed. When the amount of negative charges in the floating gate increases, the threshold increases, and an Id-Vg curve shifts almost in parallel in the direction of increasing Vg.
In such a flash memory, however, it is necessary to dispose the insulating film 907 for separating the floating gate 902 from the word line 903 from the functional viewpoint. In addition, it is difficult to reduce the thickness of the gate insulating film in order to prevent leakage of charges from the floating gate 902. It is therefore difficult to effectively reduce the thickness of the insulating film 907 and the gate insulating film, and it disturbs reduction in size of the memory cell.

Semiconductor memory device and portable electronic apparatus


The PWM control circuit is provided. The PWM control circuit includes: a PWM control signal generator that generates a PWM period signal defining a period of a PWM signal and a PWM resolution signal specifying a resolution in one period of the PWM period signal; and a PWM unit that generates the PWM signal based on the PWM period signal and the PWM resolution signal, wherein the PWM control signal generator changes a frequency of the PWM resolution signal while keeping a frequency of the PWM period signal unchanged.

1. Field of the Invention
The present invention relates to PWM control.
2. Description of the Related Art
One proposed PWM control technique is disclosed in Japanese Patent Laid-Open No. 2004-364366.
This related art technique forms a PWM fundamental wave from a basic frequency signal of a preset frequency and divides the frequency of the PWM fundamental wave to generate a PWM period signal. The PWM fundamental wave specifies a resolution to set a duty cycle in one period of the PWM period signal.
In a system of this related art technique, a change in frequency of the PWM fundamental wave for varying the accuracy of PWM control leads to a change in frequency of the PWM period signal. The changed frequency of the PWM period signal may coincide with a resonance frequency of a load structure (for example, a motor main body) under PWM control to cause undesirable vibration and noise.

PWM control circuit and motor equipped with the same


A method and apparatus for providing ESD protection. An ESD clamp is connected across the terminals to be protected circuit. The clamp is coupled to a current detector that activates the clamp when current from an ESD event exceeds a predefined limit.

Typically, an Integrated Circuit (IC) consists of a number of supply pins (power and ground), a number of input signal pins and some output pins. All of those pins (also referred to herein as pads) need safe electrostatic discharge (ESD) protection paths to all the other pins of the integrated circuit. In the IC industry, many different protection concepts exist, which include heterogeneous types of ESD protection for different pin types on a single IC. Various approaches have been utilized to provide ESD protection for the output pins of an IC, each with particular advantages and disadvantages. An output driver is typically created by an inverter-type of circuit. ESD protection of output drivers is extremely difficult. Many techniques exist all with drawbacks and disadvantages, such as time delay, and silicon consuming trigger voltage tuning, area, complexity, speed reduction, among other notable deficiencies.
FIG. 1 is a schematic diagram of a conventional CMOS output driver 100 consisting of an inverter stage 102 comprising a first transistor 104 and a second transistor 106. Depending on the logic state of the input node 108 (driven by the core circuit 110), the output potential is pulled either high to Vdd (PMOS conduction) or low to Vss (NMOS conduction). In particular, the inverter circuit 102 comprises at least one PMOS transistor 104 and at least one NMOS transistor 106 coupled together (i.e., formed in a stack), illustratively between a first voltage line, Vdd, and a second voltage line, Vss. The internal core circuit 110 of the integrated circuit manipulates an input node 108 (gate connection of the NMOS and PMOS transistors 104, 106) of the inverter 102 to communicate with other chips or logic at the outside of the integrated circuit. For a logic low signal voltage at the input node, the NMOS transistor 106 will be switched off, while the PMOS transistor 104 will conduct and bring the output node close to the Vdd potential. In an instance where a logical high is present at the input node 108, the NMOS transistor 106 will conduct, thereby pulling the output node low, while the PMOS transistor 104 is switched off.
When positive ESD stress is applied at an unprotected output pad 112 versus the Vss line or ground, the NMOS transistor 106 will first conduct a small amount of current in MOS mode, due to an uncontrolled or floating NMOS gate. If no special 'keep-off' circuitry is behind the NMOS gate, such as described in commonly assigned U.S. Pat. No. 6,529,359, the contents of which is incorporated herein by reference, the gate is typically pulled high due to the parasitic gate-drain capacitance. This parasitic or dynamic gate-biasing reduces the snapback trigger voltage Vt1 to a Vt1′, as shown in FIG. 2. This will create a MOS channel in the NMOS transistor 106 which reduces the Vt1 trigger voltage. Consequently, the NMOS transistor 106 will more easily trigger into a (parasitic) bipolar mode. A low gate bias is enough to reduce the Vt1 trigger voltage to the holding voltage of the parasitic NPN device.
One approach to providing ESD protection is to prevent snapback in the NMOS transistor 106 in the output driver 100. One conventional protection concept shown as circuit 300 in FIG. 3 consists of 'dual diode' protection of the output node, connecting a diode 304 between the Vss or ground node and the output node (diode down) and connecting a diode 302 between the output node and the Vdd node (diode up). These diodes 302/304 redirect ESD current to the supply lines/busses. A power clamp 306 between the Vdd and Vss lines clamps the voltage between the supply lines and dissipates the ESD current.
FIG. 3 depicts a schematic diagram of a dual diode and power clamp protection circuit 300 for ESD protection of the output driver 102. Two competitive trigger paths exist for the positive stress between the output pad and Vss. The intended current path flows through the diode 302 from output to Vdd and the power clamp 306 to the grounded Vss node. Due to a floating gate of the NMOS transistor 106, the transistor triggers into snapback at a reduced trigger voltage Vt1˜Vh. In many high voltage technologies, this causes damage to the NMOS transistor. However, in many other technologies, such as, but not limited to, advanced silicided technologies, triggering into snapback can be dangerous as well. If the NMOS transistor is not ballasted to ensure uniform conduction through the entire NMOS, damage may result. In all cases, it will lead to a failure if the NMOS is not robust enough to shunt large ESD currents.
Furthermore, the total voltage drop in the intended current path can become very high due to a large bus resistance (large distance to a power clamp), a resistive diode (typical for high voltage technologies) or a high resistive power clamp. When this total voltage drop in the intended current path is too high, the current path through the NMOS transistor 106 can trigger, stressing the NMOS transistor 106 into a bipolar mode. When the NMOS transistor 106 is not designed for bipolar conduction, this leads to destruction of the NMOS transistor. Due to the reduced trigger voltage of the NMOS (Vt1′<Vt1, see above and FIG. 2), the maximum or critical voltage for the intended current path can be relatively small in advanced CMOS technologies.
Special techniques exist to increase the Vt1 trigger voltage of the NMOS transistor by pulling the NMOS gate to Vss during ESD stress. Such 'keep-off circuits' have been described before (U.S. Pat. No. 6,529,359) and can be used to protect the NMOS transistor. However, those circuits increase the complexity of the pre-driver logic and only increase the critical voltage a small amount (typically 1–2V in advanced CMOS technologies: Vdelta=Vavalanche−Vhold). NMOS destruction can still occur for larger ESD stress currents.
The isolation resistor 308 'Riso' (see FIG. 3) that is sometimes placed between the output pad 112 and the output driver 102 can reduce the current through the NMOS transistor 106. If a small part of the ESD current flows through the NMOS transistor 106 and the resistor 308, a large voltage drop is induced that favors the intended current path through the diode 302 and the power clamp 306. This isolation resistor 308 has been used in mature technologies as a "quick" ESD fix, but it has many drawbacks. A large resistance value (˜50 Ohm to 1 kOhm) is needed to effectively reduce the current through the NMOS transistor 106 to safe values. The output driver speed and output current/voltage is reduced as a function of the resistance value. Thus, the output driver size needs to be increased to maintain the normal operation output current level constant. Such an increase in size may not be practical.
Because the bus resistance typically increases the total voltage drop to excessive values, another method exists which locally protects the NMOS transistor 106. A local clamp 318/320 is placed near and parallel to the drain-source of the NMOS. The intention is to clamp the voltage to a safe value below the (reduced) Vt1 (Vt1′) trigger voltage of the NMOS transistor 106. This requires a cumbersome trigger voltage selection for the local clamp 318/320 due to a very narrow ESD design window. The clamp needs to start conduction at a voltage well below the Vt1/Vt1′ trigger voltage (which defines the maximum trigger voltage) of the NMOS transistor, but well above the normal operation maximum signal voltage to prevent unwanted triggering (which defines the minimum trigger voltage). In many applications, the difference between the maximum and minimum voltage is very small and sometimes negative. As such, in many instances, use of a local clamp 318/320 is not useful in protecting the transistors of any output driver inverter 102.
Presently, available techniques for protecting an output driver from ESD events are complex and interfere with the normal operation of the output driver. Therefore, there is a need in the art for a method and apparatus to improve the protection of the transistors used in output drivers.

Method and apparatus for providing current controlled electrostatic discharge protection