In an erase method for a nonvolatile semiconductor memory device in which a memory cell array is divided into blocks, an erase pulse application for erasing information, a first verify operation for verifying a threshold voltage shift due to the erase pulse application and a second verify operation for verifying whether excessive erasure has occurred due to the erase pulse application are performed for memory cells connected to one word line in a certain block. When a memory cell excessively erased is found by the second verify operation, a soft program operation for the memory cell is performed after the second verify operation. The erase pulse application, the first verify operation, and the second verify operation are executed word line by word line in the block.

The present invention relates to an erase method for nonvolatile semiconductor memory devices, and in particular, to an erase method for a nonvolatile semiconductor memory device in which threshold voltages of memory cells in an erased state are lower than threshold voltages of memory cells in a written state.
One of most widely used flash memories is a flash memory of ETOX (a registered trademark of Intel Corp.) type, a memory cell of which has a basic structure as shown in FIG. 11. The memory cell of this basic structure has a source 12 and a drain 13 formed on a surface of a substrate (well) 11. Above a channel region 14 located between the source and the drain, a floating gate FG is formed with the interposition of a tunnel oxide film 15, and a control gate CG is further formed with the interposition of an interlayer insulation film 16.
The principle of operation of the flash memory of ETOX type will be described. As shown in Table 1, during a write (program) operation, there are applied a voltage Vpp (10 V, for example) to the control gate CG, a reference voltage Vss (0 V, for example) to the source 12, and a voltage of 6 V to the drain 13. It is to be noted that the drain application voltage of xe2x80x9c6 V/0 Vxe2x80x9d in Table 1 means the application of a voltage of 6 V to the drain of a selected memory cell and the application of a voltage of 0 V to the drain of a non-selected memory cell.
With this arrangement, a large current flows through the channel region 14 of a memory cell as shown in FIG. 12, and channel hot electrons (CHE) are generated in a drain-side portion where the electric field is high. The generated electrons are injected into the floating gate FG, and the threshold voltage of the memory cell rises. The threshold voltage distribution of memory cells in the written state has a mean value of 5.0 V and a lower limit of 4.5 V. This is shown in FIG. 10.
As shown in Table 1, during an erase operation, there are applied a voltage Vnn (xe2x88x929 V, for example) to the control gate CG and a voltage Vpe (4 V, for example) to the source 12. Then, as shown in FIG. 13, the drain 13 is opened to extract electrons at the source side, thereby lowering the threshold value of the memory cell (source side erase). The threshold voltage distribution of the memory cells in the erased state has an upper limit of 2.5 V and a lower limit of 0.5 V, as shown in FIG. 10. During this erase operation, a BTBT (Band To Band Tunneling) current flows, and hot holes and hot electrons are generated at the same time. Among these, the hot electrons flow to the drain 13, whereas the hot holes are pulled to the tunnel oxide film side and trapped in the tunnel oxide film. It is generally said that this phenomenon degrades the reliability.
As shown in Table 1, during a read (readout) operation of a memory cell, there are applied a voltage of 1 V to the drain 13 and a voltage of 5 V to the control gate CG. When the memory cell is in the erased state with a low threshold voltage, a current flows through the memory cell, and this state is determined to be xe2x80x9c1xe2x80x9d. When the memory cell is in the written state with a high threshold voltage, no current flows through the memory cell, and this state is determined to be xe2x80x9c0xe2x80x9d.
The aforementioned operating method has a problem that the reliability of the memory cell is deteriorated by the band to band tunneling current generated through the source side erase operation. As a measure for solving this problem, there is a method of executing xe2x80x9cchannel erasexe2x80x9d by which no band to band tunneling current is generated. In order to execute this channel erase operation, there is employed a memory cell having a triple well structure in which an N-well is arranged outside a P-well, as shown in FIG. 16. In the memory cell of this triple well structure, an N-well 22 is formed on the surface of a P-type substrate 21, and a P-well 23 is formed in this N-well 22. Further, a source 24 and a drain 25 are formed at a surface of the P-well 23. A floating gate FG is formed on a channel region 26 located between the source and the drain via a tunnel oxide film (not shown), and a control gate CG is further formed via an interlayer insulation film (not shown).
Table 2 shows applied voltages in each mode for the memory cell of the triple well structure. As shown in Table 2, the write operation and the read operation for the memory cell of this triple well structure are executed on the same voltage application conditions as those for the memory cell of the aforementioned basic structure (FIG. 11). FIG. 17 shows the write operation by channel hot electrons. In this case, in addition to the voltage application conditions of FIG. 12 there are further applied a voltage of 3 V to the N-well 22 and a voltage of 0 V to the substrate 21 and the P-well 23.
When executing channel erase in the memory cell of the triple well structure, as shown in FIG. 18, there are applied a voltage Vnn (xe2x88x929 V, for example) to the control gate CG (word line) and a voltage Vesc (+7 V, for example) to the source 24 and the N-well 22. By this operation, an intense electric field is applied to the tunnel oxide film located between the channel region 26 and the floating gate FG, and electrons are extracted from the floating gate FG to the channel region 26 by the Fowler-Nordheim tunneling phenomenon, with the result that the threshold voltage lowers. At this time, the potential of the source 24 and the potential of the P-well 23 are equal to each other. Therefore, no electric field is concentrated on the boundary between the source 24 and the P-well 23, and the band to band tunneling current is not generated. Consequently, hot holes are neither generated nor trapped, and the reliability of the memory cell is improved.
FIG. 14 shows an array structure of the flash memory that employs the aforementioned memory cells. As is apparent from the figure, the array structure is a NOR type array structure. When a threshold voltage distribution as shown in FIG. 10 is provided in the above array structure, there is a problem as follows.
Basically, the threshold voltage distribution after the channel erase becomes a distribution similar to that labeled erased state in FIG. 10. A case where characteristic change occurs after repeated erase and write operations will be discussed. For example, assume that the threshold voltage of a memory cell M127 bearing the mark o in FIG. 14 was subjected to excessive erasure and made to have a negative threshold voltage (xe2x88x920.3 V, for example), and that a memory cell M01 bearing the mark xcex94 was put into a written state (for example, the threshold voltage was set to 4.5 V). In this case, when reading the data of the memory cell M01 bearing the mark xcex94, no current flows since the memory cell M01 bearing the mark xcex94 has a very high threshold voltage of not lower than 4.5 V. However, since the threshold voltage of the memory cell M127 bearing the mark o has a negative value, a current flows even in a non-selected state, i.e., even when a word line WL127 has a voltage of 0 V. Therefore, if a current flowing through a bit line BL0 is detected by applying a voltage of 1 V to the bit line BL0, then the data of the memory cell M01 bearing the mark xcex94 is determined to be xe2x80x9c1xe2x80x9d (a state in which the threshold voltage is low), which is a misread. As understood from this fact, the NOR (non-disjunction) type flash memory is not permitted to have a negative threshold voltage in the array.
An erase algorithm as shown in FIG. 15 is used as a method for solving the aforementioned problem in the flash memory (see, for example, Japanese Patent Laid-Open Publication No. HEI 5-182481). According to this erase algorithm, a batch erase operation is executed in blocks. Specifically, when the erase operation of a certain block starts, the write operation is first executed in all the memory cells in the block (pre-erase program S501). By this operation, the threshold voltages of the memory cells in the block all come to have a high threshold voltage (not lower than 4.5 V, for example). Subsequently, an erase pulse is applied to all the memory cells in the block (S502). The erase pulse application is executed either by the source side erase method or by the channel erase method. This erase pulse application continues while verifying the threshold voltage through a verify operation until all the memory cells come to have a specified value (2.5 V, for example) (S503 through S506). Next, it is confirmed whether there is a memory cell that has a negative threshold voltage in the block. Practically, it is confirmed whether there is a threshold voltage of not higher than 0.5 V (S507). If there is a memory cell that has a negative threshold voltage in the array, a soft program operation (write to a slight degree) is executed for all the memory cells connected to a bit line to which the memory cell having a negative threshold voltage is connected (S508). For example, in the case of a memory cell of the basic structure as shown in FIG. 19, the voltage application conditions of the soft program operation are: a voltage of 6 V applied to the control gate CG (word line), a voltage of 6 V applied to the drain 13 (bit line) and a voltage of 0 V applied to the source 12 (source line). In the case of a memory cell of the triple well structure as shown in FIG. 20, the voltage application conditions of the soft program operation are: a voltage of 6 V to the control gate CG (word line), a voltage of 6 V to the drain 25 (bit line), a voltage of 0 V to the source 24 (source line), a voltage of 0 V to the P-well 23 and a voltage of 3 V to the N-well 22. The soft program operation causes channel hot electrons, and electrons are thus injected into the floating gate FG to thereby slightly raise the threshold voltage. The soft program operation and the verify operation are repeated until memory cells that have a negative threshold voltage disappear from the block and the threshold voltages of all the memory cells become a positive threshold voltage (practically higher than 0.5 V) (S509 through S511 in FIG. 15). Thus, the block has no memory cells that have a negative threshold voltage.
With reduction in dimensions of the memory cells due to finer patterns and the use of the channel erase technique, it can be predicted that the variations in the threshold voltage distribution in the erased state will be increased. When the variations are increased, the above-described erase algorithm will present a problem.
For example, in the NOR type memory cell array as shown in FIG. 14, it is assumed that the threshold voltage of the memory cell M01 bearing the mark xcex94 has a negative value (xe2x88x922 V, for example), although a majority of the threshold voltages of the memory cells are distributed in the positive region as shown in, for example, FIG. 8. For example, in order to execute the verify operation of the memory cell M00 bearing the mark xe2x96xa1 shown in FIG. 14, the word line WL0 is selected to sense and amplify the flowing current by a sense amplifier circuit (not shown) connected to the bit line BL0. At this time, a voltage of 0 V is applied to a word line WL1 since the word line WL1 is not selected. However, since the threshold voltage of the memory cell M01 bearing the mark xcex94 has a negative threshold voltage, a current disadvantageously flows through the memory cell M01. Therefore, it is disadvantageously determined that the memory cell M00 has a negative threshold voltage, regardless of the value of the threshold voltage of the memory cell M00 bearing the mark xe2x96xa1. Subsequently, if the verify operation is executed by sequentially selecting the memory cells, then a similar determination is to be made with regard to all the memory cells whose drains are connected to the bit line BL0. Therefore, the soft program operation is executed for the memory cells whose drains are connected to the bit line BL0. In this case, even when the memory cell M00 bearing the mark xe2x96xa1 actually has a threshold voltage of 2.5 V, so long as the threshold voltage of the memory cell M01 has a negative value, the soft program operation is repetitively executed due to the erroneous detection during the verify operation. This operation is continued until the threshold voltage of the memory cell M01 becomes a positive threshold voltage (practically until the threshold voltage becomes higher than 0.5 V).
In this case, the memory cell M01 bearing the mark A has a very low threshold voltage of xe2x88x922 V. Therefore, assuming that five soft program pulses of 1xcexcs are applied, then the five pulses are similarly applied to the memory cell M00 bearing the mark xe2x96xa1. As a result of the soft program pulse application, the memory cell M00 bearing the mark xe2x96xa1, which had a threshold voltage of 2.5 V before the pulse application, comes to have a threshold voltage increased to higher than 2.5 V. In the worst case, the data which is originally xe2x80x9c1xe2x80x9d corresponding to the low threshold may be erroneously read as data xe2x80x9c0xe2x80x9d (which corresponds to the high threshold voltage).
Next, it is assumed that the ratio of the memory cells in an excessively erased (overerase) state is great in a certain block as shown in FIG. 9 and a majority of the memory cells whose drains are connected to a certain bit line have a negative threshold voltage. If it is attempted to execute the soft program operation to the memory cells whose drains are connected to the certain bit line, then the program operation results unsuccessful as a consequence of the occurrence of the following phenomenon. That is, assuming that the memory cells connected to one bit line represent 128 bits (128 memory cells) and 60 bits (60 memory cells) among them have a negative threshold voltage, then the current caused by the voltage (6 V, for example) applied to the bit line is delivered to 60 memory cells in parallel in order to execute the soft program. This large current disadvantageously makes the bit line voltage drop due to the bit line resistance and the like, as a consequence of which the soft program cannot be executed.
To sum up, the following two problems occur when the threshold voltage distribution of the memory cells in the block to be erased varies.
(1) If a memory cell having a negative threshold voltage exists in the block, then erroneous detection occurs during the verify operation for other memory cells. Therefore, the threshold voltage of the memory cell in which the data xe2x80x9c1xe2x80x9d is originally written disadvantageously rises due to the erroneous execution or continuation of the soft program operation, and this disadvantageously leads to the occurrence of the misread that the data is xe2x80x9c0xe2x80x9d.
(2) When many memory cells having a negative threshold voltage exist among the memory cells connected to an identical bit line, the soft program cannot be executed due to the voltage drop of the bit line.
As described above, in the nonvolatile semiconductor memory in which the intra-block batch erase is executed, the spread of the threshold voltage distribution of the memory cells in the block causes a serious problem. When the aforementioned source side erase operation is employed, the spread of the threshold voltage distribution attributed to the deterioration in reliability due to the trap of hot holes in the tunnel oxide film is, of course, a problem. Furthermore, a reduction of the memory cell area by making patterns finer becomes indispensable as the packing density and capacity of the nonvolatile semiconductor memory progress in the future, and therefore, the spread of the threshold voltage distribution of the memory cells causes a problem even when the channel erase technique is used.
Techniques avoiding these problems by reducing the unit of erase are disclosed in Japanese Patent Laid-Open Publication Nos. HEI 6-29499 and HEI 6-119789.
According to the technique taught by Japanese Patent Laid-Open Publication No. HEI 6-29499, as shown in FIG. 21, memory cells connected to one word line (for example, WL0) are connected to one source line (SL0 for WL0). The source line SL0 is separated from source lines SL1, . . . , SL127 connected to the other word lines WL1, WL127. Then, the memory cells M00, M10, . . . connected to this one word line WL0 constitute a block as one unit of erase. According to this system, there is only one memory cell connected to one bit line in one block of memory cells M00, M10, . . . even if the intra-block batch erase is executed. Therefore, the aforementioned two problems do not occur.
However, in this case, the unit of erase is small, and if a word line load capacitance, a load resistance and so on are taken into consideration, the unit of erase is disadvantageously reduced to a unit of about 1 KB, i.e., 8 kbit. When many memory cells are desired to be erased, it is required to issue the command many times, and this disadvantageously increases the load of the system. In a digital still camera or the like, the amount of data necessary for one photograph or the like tends to increase, and the unit of erase should preferably be large in such a case.
On the other hand, according to the technique taught by Japanese Patent Laid-Open Publication No. HEI 6-119789, as shown in FIG. 22, memory cells connected to a word line WL0 and memory cells connected to a word line WL1 have a common source line SL0. These memory cells constitute one block as a unit of erase. In this case, when the erase operation starts, an erase pulse is applied to the memory cells connected to the word line WL0. Specifically, there are applied a voltage of, for example, xe2x88x929 V to the word line WL0 and a voltage of, for example, 5 V to the source line SL0, and the bit line is put into an open state. At this time, the word line WL1 has a voltage of, for example, 0 V, and basically no erase pulse is applied to the word line WL1. Next, the word line WL0 is made to have a voltage of 0 V, and no erase pulse is applied thereto. On the other hand, there are applied a voltage of, for example, xe2x88x929 V to the word line WL1 and a voltage of, for example, 5 V to the source line SL0, and the bit line is put into the open state, with the erase pulse applied to the word line WL1. That is, according to this method, the spread of the threshold voltage distribution is narrowed by independently applying the erase pulse to the memory cells connected to the word line WL0. However, this method has the following problems.
(1xe2x80x2) Since no soft program operation is used after the erase pulse application, misread occurs if the threshold voltage has a negative value, as in the case of the foregoing prior art. Even if a soft program operation is used, since the unit of erase includes two memory cells connected to one bit line, misread occurs. That is, assuming that one memory cell has a threshold voltage of xe2x88x922 V and the other memory cell has a threshold voltage of 2.5 V, when the soft program operation is executed after the erase pulse application, the threshold voltage of the memory cell that had the threshold voltage of 2.5 V surely becomes higher than 2.5 V, and finally a misread occurs.
(2xe2x80x2) The unit of erase includes only two word lines and corresponds to, for example, about 2 KB (merely doubled as compared with that of FIG. 21). Therefore, it is required to input the erase command many times when erasing the large capacity, and the system load is increased.
The object of the present invention is to provide an erase method for a nonvolatile semiconductor memory device which, in performing an erase operation block by block, is capable of:
(1xe2x80x3) correctly completing the erase operation even if the threshold voltage distribution of memory cells in a block varies while preventing the occurrence of misread; and
(2xe2x80x3) correctly executing a soft program operation even if there are many memory cells that have a negative threshold voltage among the memory cells connected to an identical bit line, without changing the general memory cell array structure.
In order to accomplish the above object, according to an aspect of the present invention, there is provided an erase method for a nonvolatile semiconductor memory device, the memory device comprising electrically erasable and programmable floating gate field-effect transistors arranged in a matrix form so as to form a memory cell array, each memory cell having a control gate, a drain and a source, a plurality of word lines connected to the control gates of memory cells in each row, and a plurality of bit lines connected to the drains of memory cells in each column, the memory cell array being divided into a plurality of blocks including the memory cells of a plurality of rows and a plurality of columns, the sources of the memory cells in each block being commonly connected, and the memory cells in each block being connected together in a NOR type form. The erase method which executes an erase operation in blocks comprises:
executing, for the memory cells connected to one word line in a certain block, an erase pulse application for erasing information, a first verify operation for verifying a threshold voltage shift due to the erase pulse application and a second verify operation for verifying whether excessive erasure has occurred due to the erase pulse application, and
when a memory cell that has undergone excessive erasure is found by the second verify operation, executing a soft program operation for the memory cell after the second verify operation,
the erase pulse application, the first verify operation, and the second verify operation being executed word line by word line in the block.
Note that the term xe2x80x9csoft program operationxe2x80x9d used herein means a slight write operation that causes a smaller threshold voltage shift than when a full write (program) operation is performed.
The erase method of the present invention carries out, for the memory cells connected to one word line passing through a certain block, the erase pulse application for erasing information, the first verify operation for confirming a threshold voltage shift due to the erase pulse application, and the second verify operation for confirming the fact that no excessive erasure (overerase) due to the erase pulse application has occurred. Furthermore, when a memory cell that has undergone excessive erasure is found through the second verify operation as a consequence of the variation in the threshold voltage distribution of the memory cells in the block due to the erase pulse application, the soft program operation is executed in the memory cell. In this case, the second verify operation is executed every word line, and therefore, only one memory cell that has undergone excessive erasure is specified per bit line. Therefore, the soft program operation is executed only for the single memory cell that has undergone excessive erasure, and the soft program operation is not executed for memory cells that have not undergone excessive erasure. Therefore, the soft program is correctly executed even if there are memory cells that have a negative threshold voltage among the memory cells connected to an identical bit line. As a result, the threshold voltage of the memory cell that has undergone excessive erasure can be shifted to fall within a target range (tolerance prescribed with regard to the threshold voltage of the memory cell in the erased state), and the threshold voltage of the memory cell that has not undergone excessive erasure can be kept intact at the value. By executing a series of operations of the erase pulse application, the first verify operation, the second verify operation and the soft program operation sequentially word line by word line on a plurality of word lines that extend through a block, the threshold voltages of the memory cells in the block can be made to fall in the target range. Therefore, even if the threshold voltage distribution of the memory cells in the block varies, the erase operation can be completed correctly. Therefore, misread after the erase operation is prevented.
In one embodiment, a target range of threshold voltages of each memory cell in an erased state is set lower than a lower limit value of threshold voltages in a written state. And, the first verify operation verifies that the threshold voltages of the memory cells connected to the word line are equal to or lower than an upper limit value of the target range. Also, the second verify operation verifies that the threshold voltages of the memory cells connected to the word line are equal to or higher than a lower limit value of the target range.
The soft program operation may be executed by means of channel hot electrons. In that case, the soft program operation can successfully be done bit by bit even when the memory cells in the block are connected to form a NOR type memory cell array.
In one embodiment, the soft program is performed using the following voltage application conditions. That is, a voltage applied to the control gate of a memory cell in the soft program operation is same in polarity as and smaller in value than a voltage applied to the control gate of the memory cell during a write operation. Also, a voltage applied to the drain of the memory cell in the soft program operation is substantially identical to a voltage applied to the drain of the memory cell in the write operation.
In one embodiment, the erase pulse application includes applying a first voltage to the sources of a certain block, applying a second voltage to one word line selected from the plurality of word lines of the block, and applying a third voltage to non-selected word lines of the block, to thereby extract electrons from the floating gate to the source of each memory cell connected to the selected word line. The first voltage may be a positive voltage, the second voltage may be a negative voltage and the third voltage may be a reference voltage.
In one embodiment, each memory cell constituted of the floating gate field-effect transistor has a triple well structure in which a P-well that provides a channel region is formed via an N-well on a P-type semiconductor substrate. In this case, the erase pulse application includes applying a first voltage to the source and the P-well of a certain block, applying a second voltage to one word line selected from the plurality of word lines of the block, and applying a third voltage to non-selected word lines of the block, to thereby extract electrons from the floating gate to the channel region of each memory cell connected to the selected word line. The first voltage may be a positive voltage, the second voltage may be a negative voltage and the third voltage may be a reference voltage or a positive voltage lower than the first voltage.
An erase method according to a second aspect of the present invention is used for a nonvolatile semiconductor memory device that comprises electrically erasable and programmable floating gate field-effect transistors arranged in a matrix form so as to form a memory cell array, each memory cell having a control gate, a drain and a source, a plurality of word lines connected to the control gates of memory cells in each row, and a plurality of bit lines connected to the drains of memory cells in each column. Also, the memory cell array is divided into a plurality of blocks including the memory cells of a plurality of rows and a plurality of columns, each block is divided into a plurality of segments with respect to a row direction, each bit line consists of a main bit line and a plurality of sub-bit lines connected to the main bit line via a respective select transistor, the sub-bit lines are connected to the drains of the memory cells included in the corresponding segments, the sources of the memory cells in each block are commonly connected, and the memory cells in each block are connected together in a NOR type form.
In the erase method according to the second aspect of the present invention which executes an erase operation in blocks, an erase pulse application for erasing information, a first verify operation for verifying a threshold voltage shift due to the erase pulse application and a second verify operation for verifying whether excessive erasure has occurred due to the erase pulse application are executed for the memory cells connected to one word line in each segment of a certain block. If a memory cell that has undergone excessive erasure is found by the second verify operation, a soft program operation is performed for the memory cell after the second verify operation.
The erase pulse application, the first verify operation, the second verify operation, and the soft program operation are executed in the plurality of segments of the block in parallel, and also word line by word line in each segment of the block.
The erase method of the second aspect of the present invention enables an erase operation at a higher speed than the erase method of the first aspect.
In one embodiment, a target range of threshold voltages of each memory cell in an erased state is set lower than a lower limit value of threshold voltages in a written state. And, the first verify operation verifies that the threshold voltages of the memory cells connected to the word line are equal to or lower than an upper limit value of the target range. Also, the second verify operation verifies that the threshold voltages of the memory cells connected to the word line are equal to or higher than a lower limit value of the target range.
The first verify operation and the second verify operation for the memory cells connected to the selected word line may be executed by turning on the select transistors for the sub-bit lines included in the segment through which the selected word line extends while turning off the select transistors for the sub-bit lines included in remaining segments.
Other objects, features and advantages of the present invention will be obvious from the following description.

Erase method for nonvolatile semiconductor memory device


A capacitive multiplier circuit for an integrated circuit includes a capacitor coupled between a first node and a second node. A current source is coupled to provide a controlling current to the second node. A first current path shunts the first node and a second current path shunts the second node. The first current path is a first transistor having its conductance path connected between the first node and the substrate and its control electrode connected to the first node. The second current path is a second transistor having its conductance path connected between the second node and the substrate and its control electrode connected to the first node. The current ratio between the two current paths will be determined by the relative areas of the respective conductance paths.

The ability to generate medium to long delays in semiconductor integrated circuits has been limited due either to the very small charging currents required, or to the large value of capacitors required which result in large, expensive areas of silicon. Additionally, if a method for producing small charging currents is implemented, the loading effects of measurement circuitry can give rise to errors. Therefore, it would be desirable to have a circuit which can provide significant time delays while avoiding these problems.

Capacitive multiplier for timing generation


An over-the-wire heat exchange catheter includes a heat transfer extension having at least one supply lumen and at least one return lumen for circulating heat exchange fluid within the catheter. The catheter has a distal tip and valve attached to the distal tip. The valve automatically seals the distal tip around a guidewire or a mandrel to seal the heat transfer extension and inhibit escape of the heat transfer fluid from the heat transfer extension.

The present invention relates to over the wire heat exchange catheters, particularly to catheters having a distal end with a coiled heat exchanger.
In warm blooded creatures, temperature regulation is one of the most important functions of the body. Despite the known importance of properly maintaining body temperature, scientists have discovered certain beneficial effects of artificially inducing a hypothermic state. For instance, cooling the body can help regulate vital functions during surgery by lowering the metabolism. With stroke, trauma, and other conditions, hypothermia is believed to reduce the permeability of the blood/brain barrier. Also, induced hypothermia is believed to inhibit the release of damaging neurotransmitters, inhibit calcium mediated effects, inhibit brain edema, and lower intra cranial pressure. Regardless of the particular mechanism, the present invention understands that fevers degrade the outcomes for patients suffering from brain trauma or stroke, and moreover that hypothermia improves the outcomes for such patients.
Hypothermia may be induced locally or systemically. With local hypothermia, physicians focus their cooling efforts on a particular organ, limb, anatomical system, or other region of the body. With systemic hypothermia, body temperature is lowered without particular attention to any body part.
One technique for inducing systemic hypothermia includes packing the patient""s entire body in ice. Although this technique has been used with some success, some physicians may find it cumbersome, and particularly time consuming. Also, it is difficult to precisely control body temperature with ice packing. As a result, the patient""s body temperature overshoots and undershoots the optimal temperature, requiring physicians to add or remove ice. Furthermore, there is some danger of injuring the skin, which is necessarily cooled more than any other body part.
In another approach to systemic hypothermia, the patient is covered with a cooling blanket, such as an inflatable air-filled or water-filled cushion. Physicians control the patient""s temperature by regulating the temperature of the inflation medium. Nonetheless, some delay is still inherent, first for a cooling element to change the temperature of the cooling medium, and then for the temperature adjusted cooling medium to cool the desired body part. This delay is even longer if the targeted body part is an internal organ, since the most effective cooling is only applied to the skin, and takes some time to successively cool deeper and deeper layers within the body.
A proven approach to inducing hypothermia is by circulating a cooling fluid through a cooling catheter placed inside a patient""s body. The catheter may be inserted into veins, arteries, cavities, or other internal regions of the body. It is often desired to precisely position such a catheter within the body of a patient to provide for local, or, systematic heat exchange.
An over-the-wire heat exchange catheter includes a heat transfer extension having at least one supply lumen and at least one return lumen for circulating heat exchange fluid within the catheter. The catheter has a distal tip and valve attached to the distal tip. The valve automatically seals the distal tip around a guidewire or a mandrel to seal the heat transfer extension and inhibit escape of the heat transfer fluid from the heat transfer extension.
The valve is normally closed, but opens upon receipt of a guide wire and seals the distal tip around the guidewire. The valve automatically closes upon removal of the guide wire to re-seal the distal tip to inhibit escape of the heat exchange fluid from the heat transfer extension.
The valve has a disk shape and an aperture for admitting a guidewire. The aperture is a centrally defined aperture for admitting a guidewire, and opposing concave sides. According to aspects of the invention, the valve is made from silicon or plastic. According to another aspect of the invention, the valve includes sealed flaps. According to a further aspect of the invention, the valve includes a spongy membrane.
The heat transfer extension includes a flow through lumen to deliver fluids via the distal tip of the catheter.

Over the wire heat exchange catheter with distal valve


A foreign substance removing apparatus that can provide the desired vibration amplitude to a light transmitting member, without using a large driving voltage. The foreign substance removing apparatus removes foreign substances adhered to a surface of an optical member disposed in a light ray incident path and includes a piezoelectric element fixed to a first plane of the optical member, a circular disk fixed to a second plane, opposite from the first plane, of the optical member so as to face the piezoelectric element, and a driving unit for applying an AC voltage to the piezoelectric element to cause the optical member to elastically vibrate in a direction perpendicular to the planes thereof, thereby removing the foreign substances adhered to the surface of the optical member.

1. Field of the Invention
The present invention relates to a foreign substance removing apparatus, and more particular, to a foreign substance removing apparatus for removing foreign substances adhered to a surface of a plate-like light transmitting member disposed in a light ray incident path.
The foreign substance removing apparatus is mounted to an original reading apparatus of a copying machine, a facsimile machine, a document scanner or the like or mounted to an image pickup apparatus such as a video camera and a still camera.
2. Description of the Related Art
In a recent image pickup apparatus, a shot image is much affected by dusts adhered to an optical system of the image pickup apparatus, with improvement of resolution of an optical sensor of the apparatus. In particular, with remarkable improvement of resolution of an image pickup device of a video camera, a still camera or the like, dusts are sometimes captured in a shot image. More specifically, when dusts from the outside or abrasive dusts produced by friction in the image pickup apparatus are adhered to an infrared ray cut filter, an optical low pass filter or the like disposed near the image pickup device, such dusts are captured in a shot image.
When reading a planar original disposed close to a line sensor of an image pickup unit of a facsimile machine, a document scanner or the like, the image pickup unit repetitively scans the original in a lengthwise direction of the line sensor (main scanning direction) while relatively moving the line sensor and the original in a sub-scanning direction. At this time, if dusts are adhered to a light ray incident part of the line sensor, the dusts are captured in the read image. In particular when dusts are adhered to the line sensor, the dusts are each captured in the image as a continuous line image extending in the sub-scanning direction, thus greatly impairing the quality of the image.
Although the desired image quality can be restored by a human intervention wiping foreign substances with a cloth or the like, a human operator is not aware of dust adherence until completion of shooting or image reading. When an image obtained by the shooting or image reading is in an electronic data form, the obtained image in which dust images have been captured can be corrected using an image processing software. However, laborious correcting operations are required. When the obtained image is output onto a paper medium, the paper medium is wastefully consumed.
Therefore, a camera with a dustproof mechanism that removes dusts using vibration has been proposed as disclosed in Japanese Laid-open Patent Publication Nos. 2002-204379 and 2003-333391, and an image reading apparatus using vibration to cause dusts to move away from an image reading unit has also been proposed as disclosed in Japanese Laid-open Publication Nos. 2003-280110 and 2004-012474.
FIG. 8 is a perspective view of an image reading apparatus disclosed in Japanese Laid-open Publication No. 2003-280110.
Referring to FIG. 8, a reader section 200 is provided that optically reads image information recorded on an original and optoelectrically converts the image information into image data. The reader section 200 includes a platen glass 201 for auto document feeder (ADF), hereinafter referred to as the "ADF platen 201", a platen glass 202 for book-original, and a scanner unit 209 including a lamp 203 and a mirror 204. The reader section 200 further includes mirrors 205, 206, a lens 207, a CCD sensor (not shown), and the like.
When reading an image of an original conveyed from an ADF, not shown, the reader section 200 causes the scanner unit 209 to move to and stop at a location beneath the ADF platen 201, and reads image information while the original is conveyed along the ADF platen 201.
Reference numeral 210 denotes a piezoelectric element attached to a lower surface of the ADF platen 201. A high-frequency signal is applied from a circuit, not shown, to the piezoelectric element. As a result, bending vibration is produced in the ADF platen 201. The bending vibration removes foreign substances from the ADF platen 201, if they have been adhered to the ADF platen 201, whereby the foreign substances are prevented from being captured in a shot image. The piezoelectric element 210 is positioned so as not to hinder an optical image of an original from passing through the ADF platen 201 and reaching the scanner unit 209.
The ADF platen 201 is supported by a housing of the reader section 200 via supporting members made of an elastic material and disposed near the ADF platen 201. A foreign substance removing apparatus of the reader section 200 is comprised of the ADF platen 201, the piezoelectric element 210, and the supporting members.
FIGS. 9A through 9D are views showing bending vibrations produced in the ADF platen 201 by the piezoelectric element 210. The bending vibrations include multiple-order standing waves. FIG. 9B shows a first vibration mode, and FIG. 9C shows a second vibration mode. The first vibration mode is a seventh-order mode where eight nodes are present in the platen, and the second vibration mode is a sixth-order mode where seven nodes are present therein. As shown in FIG. 9D, each of the first and second vibration modes has a Y-directional vibration displacement distribution which is uniform without any nodes.
Vibrations in at least first and second vibration modes are sequentially applied from the piezoelectric element 210 to the ADF platen 201. As a result, vibrations are produced at various parts of the ADF platen 201. Since positions of the nodes in the first vibration mode are different from those in the second vibration mode, vibrations are produced at every position on the ADF platen 201. As a result, foreign substances are peeled off and moved away from the ADF platen 201.
However, the conventional foreign substance removing apparatus provided in the image reading apparatus in FIG. 8 poses the following problems.
FIG. 10A is a section view of the ADF platen 201 of the conventional foreign substance removing apparatus in FIG. 8 taken along an X-Z plane at a location near the piezoelectric element 210, and FIG. 11A is a section view of the ADF platen 201 taken along an X-Z plane at a location away from the piezoelectric element 210.
The ADF platen 201, which is a rectangular plate-like light transmitting member, is affixed with the circular plate-like piezoelectric element 210 using adhesive. FIG. 10A shows a sectional shape of the piezoelectric element 210 observed when a bending vibration in the piezoelectric element 210 causes a maximum Z-directional (thickness-directional) displacement of the piezoelectric element 210 at a location near the center 216 of the circular plate that forms the piezoelectric element 210. In FIGS. 10A and 11A, reference numeral 215 denotes a bending neutral surface, which represents a surface position where no X-directional elongation/contraction is produced by the bending vibration. In FIGS. 10B and 11B, the magnitudes of X-directional strains in the ADF platen 201 and the piezoelectric element 210 are represented by the lengths of arrows shown therein, in which the right pointing arrows represent elongation and the left pointing arrows represent contraction.
As shown in FIG. 11A, the bending neutral surface 215 is located at the thickness-directional (Z-directional) center of the ADF platen 201 in a part of the ADF platen 201 to which the piezoelectric element 210 is not affixed. On the other hand, in another part of the ADF platen 201 to which the piezoelectric element 210 is affixed and the rigidity of the piezoelectric element 210 is added, the bending neutral surface 215 is shifted toward the piezoelectric element 210 so as to be sometimes positioned in the piezoelectric element 210, as shown in FIG. 10A.
For the above reasons, the following two problems are caused.
First, an allowable vibration amplitude corresponding to a rupture limit of the ADF platen 201 decreases.
The ADF platen 201 made of an optical material such as glass or quartz is relatively low in rupture limit. When the bending neutral surface 215 is inside the ADF platen 201 as shown in FIG. 11A, the ratio of tensile stress in the upper and lower surfaces of the ADF platen 210 to amplitude of the bending vibration decreases to a minimum. On the other hand, at that part of the ADF platen 201 to which the piezoelectric element 210 is affixed, the bending neutral surface 215 is away from the ADF platen 201 as shown in FIG. 10A, and the tensile stress in the ADF platen 201 shown in FIG. 10A increases since the amount of strain varies in proportion to the distance from the neutral surface 215. As a result, the allowable vibration amplitude at which the rupture limit of the ADF platen 201 shown in FIG. 10A is reached decreases to be smaller than the allowable vibration amplitude corresponding to the rupture limit of the ADF platen 201 shown in FIG. 11A. Therefore, there is a risk that vibration having a sufficient amplitude cannot be applied to the ADF platen 201.
Second, an applicable force which the piezoelectric element 210 can apply to the ADF platen 201 decreases.
The piezoelectric element 210 is polarized in advance in the thickness direction (Z direction). A rear surface electrode is provided in a rear surface of the piezoelectric element 210 at which the piezoelectric element is affixed to the ADF platen 201, and a front surface electrode is provided in a front surface of the piezoelectric element, which is opposite from the rear surface. When a potential difference is applied across these electrodes, X-directional elongation/contraction stress is produced in the piezoelectric element 210 due to lateral electostrictive effect. In the piezoelectric element 210 which is in a state shown in FIG. 10A, a uniform contraction stress is produced in the piezoelectric element 210 in the thickness direction.
By virtue of the stress being produced, an X-directional elongation strain is produced in an upper region above the bending neutral surface 215 inside the piezoelectric element 210, and an X-directional contraction strain is produced in a lower region below the bending neutral surface 215.
As a result, despite that contraction stress is produced in a region 217 extending from the surface at which the piezoelectric element 210 and the ADF platen 201 are affixed together to the bending neutral surface 215, an elongation strain is produced in the region 217, and therefore, the stress does not effectively act. Specifically, in the region 217, even when a sufficient voltage is applied to the piezoelectric element 210, the desired vibration amplitude cannot be produced in the ADF platen 201.
An object of the present invention is to provide a foreign substance removing apparatus that can provide the desired vibration amplitude to a light transmitting member, without using a large driving voltage.


Device for generating multiple quality level bit-rates in a video encoder having a motion estimator providing a predicted block for each predefined block based upon estimating the motion between the predefined block of the current image and the corresponding block in the previous image, a transformer for transforming a prediction error resulting from the difference between the predicted block and the predefined block into the frequency domain, and a quantizer for quantizing the coefficients of the prediction error and providing the quantized coefficients to a video multiplex coding unit. Such a device includes a number n of stages, each corresponding to a quality level i=1 to n, and each stage having a computer for reducing the prediction error in accordance with the quality level i and providing a corresponding quantized prediction error residual QDi, and an adder for obtaining a cumulative prediction error:       QD    TOTAL    =            ∑              j        =        0                    j        =        i                        QD      j

The present invention relates to the video encoding standard H.263 developed by the International Telecommunication Union (ITU) for very low bit-rate multimedia telecommunication and particularly to a device for generating multiple quality level bit-rates in a H.263 video encoder.
The H.263 standard developed by the ITU (International Telecommunication Union) is a part of its H.324/H.323 recommendations for very low bit-rate multimedia telecommunication. The H.263 coding scheme which is described in xe2x80x9cVideo Coding for Very Low bit-rate Communicationxe2x80x9d, Draft ITU-Recommendation H.263, May 1996, is based on earlier schemes used in H.261 and MPEG-1/2 standards, and using a Hybrid-DPCM concept comprising a motion estimation/compensation mechanism, transform coding and quantization. Each image is divided into blocks of size 16xc3x9716 pixels (called macroblocks) and the macroblock in the current picture is predicted from the previous picture using motion estimation techniques. After the prediction, the macroblock is divided into four blocks of size 8xc3x978 pixels. The prediction error is then transformed using the Discrete Cosine Transform (DCT) and the resulted coefficients are quantized and stored in the bitstream along with the motion parameters and other side information. The H.263 standard contains several improvements compared to earlier standards which allow a substantial reduction in the bit-rate while maintaining the same image quality. These improvements make it most suitable for very low bit-rate communication (but do not exclude it from being used in high bit-rate compression as well).
The H.263 bit-stream syntax defines the structure of the coded data from the basic block data to the entire image. The quality of the reconstructed video sequence can be controlled by changing the quantization step in the encoding process according to a pre-defined rate control mechanism. This allows a flexibility in generating a video sequence according to a desired bit-rate or image quality.
When a system is designed to transmit video content to a wide range of communication channels (video servers or video-on-demand), it is highly desired to be able to use one compressed video sequence which can accommodate all needs as opposed to keeping several versions of the compressed video sequence each compressed to a different bit-rate according to the target communication channel.
Therefore, the main object of the invention is to provide a device incorporated in a video encoder for accommodating a wide range of communication channels without storing several video bitstreams.
Another object of the invention is to provide a device used in a video encoder for supplying different quality level video bitstreams by using the same stored video sequence with different quantization step sizes.
Accordingly, the device according to the invention is used in a video encoder comprising motion estimation means providing a predicted block for each predefined block based upon estimating the motion between the predefined block of the current image and the corresponding block in the previous image, transform means for transforming a prediction error resulting from the difference between the predicted block and the predefined block into the frequency domain, and quantizing means for quantizing the coefficients of the prediction error in the frequency domain and providing the quantized coefficients to a video multiplex coding unit, wherein the quantized coefficients are de-quantized and inverse transformed to give back the prediction error and add it to the predicted block whereby the result is provided to the motion estimation means in order to get a new current predicted block. Such a device which generates, from one video sequence, multiple video bitstreams of different bit-rates and corresponding to different quality levels comprises a number n of stages corresponding each to a quality level i=1 to n, each stage comprising computing means for reducing the prediction error in accordance with the quality level i and a corresponding quantized prediction error residual QDi, and summing means for obtaining a cumulative prediction error:       QD    TOTAL    =            ∑              j        =        0                    j        =        i                        QD      j
corresponding to quality level i.
wherein QDj is the dequantized value of the quantized prediction error residual QDj.
The invention further provides a way to efficiently store up to four compressed video sequences corresponding to up to four different quality level compression of the same video sequence.
The major advantage of the invention is to save storage space or transmission bits when this data is respectively stored as a data file or sent on a transmission line because the motion vector information are only stored once for the four different compressed video sequences. In addition, only one file (for storage) or stream (for transmission) is used as opposed to the normal case where each compressed video sequence is handled independently. One other advantage of the solution is that video decoders able to process H.263 standard bitstreams but not modified according to the new storing of data of the invention, will be however able, with no change, to reconstruct the base layer of the compressed data while discarding the rest of the sub-bitstreams it cannot decode.

Abstract: corresponding to quality level i

Abstract: wherein QDj is the de-quantized value of the quantized prediction error residual QDj. Such a device is well suited to the current H.263 bitstream structure of the ITU recommendation H.324/H.323 by using the sub-bitstream feature without the need to change the bitstream structure.

International Business Machines Corporation


Infusion systems for holding an infusion pump on the body of a user are provided. According to one embodiment, the infusion system includes: a carrier frame; a guiding member disposed on the carrier frame; and a linear guide on the infusion pump wherein, when the infusion pump is attached to the carrier frame, the guiding member and the linear guide mate with each other to hold the infusion pump in place.

Medical devices that pump medication into an individual are known and commonly used in the medical industry. Typically, the medication that is delivered from such medical devices, or infusion systems, depends on the medical condition that is sought to be treated. For example, it is common to deliver insulin using an insulin pump to treat a diabetic patient.
Typically, the infusion systems include a reservoir or a cartridge that contains the medication. Due to trend towards the miniaturization of products, there is an expectation that the infusion systems be small and wearable for discrete operation. Since different users typically wear the infusion system in different places, it is desirable to provide an interface that will allow a user this flexibility. As the size of the infusion system becomes smaller, the infusion system may be attached directly to the skin of the user. In many cases, the medication is infused by adhering the infusion system to the stomach area. Human skin is flexible and pliable. In many cases the stomach area often comprises skin folds. The application of carriers between such skin folds may cause discomfort. Additionally, the skin tends to stretch-out more in the vertical axis than in the horizontal axis. Large pressure sensitive adhesives in the vertical axis may inhibit skin movement and induce stress. Also, the pressure sensitive adhesive may be difficult for the user to access. Furthermore, when carriers are worn on the skin, perspiration (skin breathing) is reduced and may lead to skin irritation.
Therefore, a needs exists for carriers where the infusion system can be comfortably worn on the skin without hindering the operation of the infusion system.


The present invention relates to a composition, which is useful for producing coatings for metal sheet substrates of metal cans for storing and/or transporting food or beverages or a lid thereof, and which comprises the following components:    (a) 30 to 90 wt. % of a polyvinylchloride-(PVC)-polymer,    (b) 7 to 25 wt. % of an acrylic resin,    (c) 3 to 40 wt. % of a crosslinking agent, which is produced from phenol, para-tert.-butylphenol, xylenol or a mixture thereof, and formaldehyde,    (d) 0 to 8 wt. % additive,    (e) 0 to 50 wt. % pigment and    (f) a solvent-component,where all weight percentages are on the basis of the total dry weight of the coating composition (without solvents) and the composition is substantially free of bisphenol-A-diglycidyl-ether (“BADGE”) and also substantially free of bisphenol-A-resins. The composition provides metal can coatings that have suitable flexibility, scratch resistance, adherence and sterilization resistance when processed in contact with food. The coatings are suitable for three-piece cans as well as deep-drawn metal cans. In particular they are, however, useful for lids that are to be torn open due to their extraordinary flexibility and sterilization resistance.

Metal containers for receiving foods and beverages generally have one or more coatings to prevent contact between the filled product and metal. This is to prevent or minimize corrosion to the metal by the product and any disadvantageous influences on the quality of the product. For producing containers of this type, such as cans of tin-plated or chromium-plated steels or aluminum, metal sheets are used which, prior to their shaping (such as for three-piece can production) or deformation (such as for deep drawing process), are coated with suitable coating compositions. In producing cans for foods and beverages, coatings are required which are extremely flexible and have a low order of toxicity. Furthermore, filled food cans are often sterilized under application of temperatures up to 135° C. The coating must therefore be sufficiently stable at those temperatures an must be capable of adhering to the surface of the metal.
Epoxy phenolic type coatings have been applied as lacquers onto metal can stock (e.g. for three-piece cans) and baked to provide coatings having good resistance to aggressive filled products, mechanical performance and metal adhesion. However, many of these incorporate 2,2′-bis(4-hydroxyphenyl)propane-bis(2,3-epoxypropyl)-ether (or homologues thereof), otherwise known as bisphenol-A-diglycidyl-ether or "BADGE" (Bisphenol-A-Di-Glycidyl-Ether).
The use of BADGE-containing formulations is restricted under food law aspects.
Currently available polyester type coatings, such as those cross-linked with amino-type or isocyanate-type resins, are used on the exterior of three-piece cans, but do not resist processing when in contact with food, or do not comply with food laws, and therefore do not yet provide an alternative coating formulation.
WO 00/55265 describes BADGE-free compositions, which are, however, produced on the basis of polyester resins in combination with bisphenol-A (BPA). Organosoles on the basis of PVC crosslinked with bisphenol-A serve as an alternative to polyester resins. Bisphenol-A was therefore preferably used for the production of sterilization resistant, epoxy-free can coatings. However, it has been found that bisphenol-A acts to the human body in a similar manner as estrogen, which may lead to reproduction disorders.
Crosslinked coating compositions of the polyvinylchloride type are commercially available. However, all known sterilization-resistant coating compositions contain BADGE and/or BPA. The term "cross-links", as used within the context of the present invention, designates covalent bonds linking one polymer chain to another and the term "crosslinking agents" designates monomers or polymers that are able to react or co-react with the polymer chains linking them together to form a duroplastic network.
Many known coating compositions for metal cans also contain metal stabilizers such as lead- or tin-based stabilizers. These metal stabilizers are undesirable in cans for foods and beverages and do not comply with food laws.
Furthermore, in many known coating compositions it is necessary to first apply a primer composition onto the metal surface, before applying the coating composition. This is disadvantageous because a further, costly processing step is required, and because many primer compositions do not comply with food laws.
In view of the foregoing disadvantages of the prior art, a novel can coating is need which is substantially BADGE- and BPA-free.


Examples described herein relate to apparatuses and methods for reducing an amount of time that a user of a drive-up banking system is exposed to outdoor environmental conditions. A method includes detecting, by a drive-up banking system, a presence of a vehicle proximate the drive-up banking system; projecting, by the drive-up banking system, a user interface onto a vehicle window such that the user interface is visible to the occupant of the vehicle; receiving, by the drive-up banking system, information indicative of an identity of the occupant of the vehicle; determining, by the drive-up banking system, an account corresponding to the occupant of the vehicle; requesting, by the user interface, transaction information; receiving, by the user interface, information indicative of the transaction information; and conducting, by the drive-up banking system, a transaction based on the transaction information.

Drive-up banking systems, such as automated-teller machines (ATM)s or other payment terminal devices are often in outdoor locations. Customers can access drive-up banking systems as drivers or occupants of vehicles. Conventional drive-up banking systems require customers to lower a vehicle window to interact with a user interface of the drive-up banking system to enter account information, transaction instructions, deposit physical media such as checks or physical currency, and/or retrieve withdrawn physical currency. While the vehicle window is open, occupant(s) of the vehicle can be exposed to uncomfortable outdoor conditions, such as cold temperatures, hot temperatures wind, rain, and/or snow.


In an information device, a fingerprint image capture section captures a fingerprint image of an operator. When a fingerprint image captured by the fingerprint image capture section is referred to as a first fingerprint image and a fingerprint image captured at a given time interval after the first fingerprint image is captured is referred to as a second fingerprint image, a comparison section compares minutiae points of the first and second fingerprint images extracted by a minutiae point extraction section. An image generation section generates image information which is changed while reflecting the comparison results of the comparison section. A display section displays an image based on the image information generated by the image generation section. The information device may be provided with a check section, and display control by the display section may be performed after a fingerprint image is checked by the check section.

The present invention relates to an information device and a display control method.
In information devices including a display section, various types of control (operations) are performed by designating a position on a menu screen or moving a pointer on a screen. The information device may be controlled by specifying coordinates on a panel having conductors disposed in the shape of a matrix by using an input indicator having a tuning circuit, for example (see Japanese Patent Application Laid-open No. 7-134630). In this case, current is caused to flow through two arbitrary conductors in the X direction or Y direction disposed in the shape of a matrix, and a position designated on the panel is specified by a voltage generated by magnetic coupling between the tuning circuit inside the input indicator and the conductors. The information device is controlled by using the position specified as instruction information.

Information device and display control method


A valve timing adjusting device for and engine includes a sprocket configured to rotate by receiving drive power from a driving shaft, a vane rotor fixed to a driven shaft so as to be rotatable relative to the sprocket, a housing that includes an oil chamber housing the vane rotor and is fixed to one end in a thickness direction of the sprocket, a bolt fixing the sprocket to the housing, and a knock pin inserted into a sprocket hole formed in the sprocket at one end thereof and into a housing hole formed in the housing at the other end thereof to restrict relative relation between the sprocket and the housing. The knock pin abuts against an inner wall of the sprocket hole at one end thereof, and abuts against an inner wall of the housing hole at the other end thereof.

1. Field of the Invention
The present invention relates to a valve timing adjusting device for adjusting open/close timing of an intake valve or an exhaust valve of an engine, a manufacturing apparatus for manufacturing the valve timing adjusting device and a method for manufacturing the valve timing adjusting device.
2. Description of Related Art
There are known valve timing adjusting devices configured to adjust open/close timing of an intake valve or an exhaust valve of a vehicle engine by varying the rotational phase between the crankshaft (driving shaft) and the camshaft (driven shaft) of a vehicle engine.
For example, Japanese Patent Application Laid-open No. H9-209722 describes a valve timing adjusting device which includes a sprocket receiving torque from a crankshaft, a vane rotor fixed to the camshaft, a housing with an oil chamber housing the vane rotor, and a sleeve disposed rotatably relative to the camshaft. A knock pin is inserted into a hole formed in the sleeve, a hole formed in the sprocket and a hole formed in the housing. The sprocket, the housing and the sleeve are fastened to one another by this knock pin and a bolt so that they can rotate together.
However, there is a slight clearance between the inner wall of the hole of the sprocket and the knock pin depending on tolerance of the inner diameter of the hole of the sprocket and the outer diameter of the knock pin. Further, there is a slight clearance between the inner wall of the hole of the housing and the knock pin depending on tolerance of the inner diameter of the housing of housing and the outer diameter of the knock pin. Incidentally, the vane rotor of the valve timing adjusting device may be at the intermediate phase position while the engine is stopped. In addition, generally, the oil in the oil chamber of the valve timing adjusting device is evacuated therefrom while the engine is stopped. Accordingly, since the oil flows into the oil chamber rapidly when the vane rotor is phase-controlled to its starting position at the time of engine start, there is a concern that the vane rotor may collide with the inner wall of the oil chamber, causing positional deviation between the housing and the sprocket If the positional deviation causes the bolt fixing the sprocket, housing and the sleeve to be loosened relative to each other, it may be difficult for the valve timing adjusting device to control the phase between the crankshaft and the camshaft.

Valve timing adjusting device, apparatus for manufacturing same and method for manufacturing same


A cylinder head for an internal combustion engine with at least one cylinder has a cooling duct system which has a coolant inlet side and a coolant outlet side, a combustion chamber section, two coolant-inlet-side gas ducts, two coolant-outlet-side gas ducts and two adjacent component openings, such as a spark plug opening and an injection nozzle opening. The cylinder head has an annular wall section provided between the component openings, on the one hand, and the gas ducts, on the other hand. The cooling duct system has a web cooling duct which runs into the annular wall section, extends between the coolant-inlet-side gas ducts and has an upper wall. The upper wall has a guiding surface which is directed obliquely downwards in the region of the annular wall section in order to deflect coolant in the direction of the combustion chamber section.

The invention relates to a cylinder head for an internal combustion engine, having a cooling duct system.
A cylinder head together with a cylinder block, on which the cylinder head is fastened, defines the combustion chamber of an internal combustion engine. Cooling ducts of a cooling duct system are formed both in the cylinder block and in the cylinder head and can transport away the waste heat arising during the combustion. Furthermore, the cylinder head has ducts and openings which lead into the combustion chamber. A fuel injection nozzle and a spark plug, for example, can project through the openings into the combustion chamber, and combustion gases can be supplied to the combustion chamber or removed from the combustion chamber through the ducts.
Accordingly, the cooling ducts in the cylinder head have to be guided around the gas ducts and around the other openings, thus resulting in complex geometries which are difficult to produce. A particular problem here is the cooling of the "web", i.e. of the region of the upper deck of the combustion chamber section that surrounds the spark plug opening and/or injection nozzle opening. In particular in the case of cylinder heads having four valves per cylinder, the region of the web is virtually completely surrounded by the gas ducts, and therefore this region can be difficult to cool with cooling ducts.
On account of this, only a low transport of heat away from the web occurs in the case of customary cylinder heads, and therefore high temperatures occur there during operation and may reduce the service life of the cylinder and therefore of the entire engine.
It is therefore an object of the invention to provide a cylinder head which permits improved cooling of the web.
The object is achieved by a cylinder head for an internal combustion engine having at least one cylinder, having a cooling duct system which has a coolant-inlet side and a coolant-outlet side, a combustion chamber section, two coolant-inlet-side gas ducts, two coolant-outlet-side gas ducts and two adjacent component openings, such as a spark plug opening and an injection nozzle opening, wherein the coolant-inlet-side gas ducts, the coolant-outlet-side gas ducts and the component openings all lead into the combustion chamber section. The cylinder head has an annular wall section which is provided between the component openings, on the one hand, and the gas ducts, on the other hand, wherein the cooling duct system has a web cooling duct which runs into the annular wall section, extends between the coolant-inlet-side gas ducts and has an upper wall. The upper wall has a guiding surface which is directed obliquely downward in the region of the annular wall section, in order to deflect coolant in the direction of the combustion chamber section. Here, "up" is understood as meaning that side of the cylinder head which faces away from the combustion chamber section. Accordingly, the direction "down" runs toward that side of the cylinder head at which the combustion chamber section is provided.
The coolant flows obliquely upward in the region of the coolant-inlet-side gas ducts and is then deflected downward in the direction of the web by the guiding surface which is directed obliquely downward. The coolant thereby flows directly toward the web, as a result of which efficient cooling of the web is achieved. The heat transmitted to the web by the combustion operation can therefore be efficiently removed, and therefore the service life of the engine is increased.
In this case, the coolant-inlet-side gas ducts can be the outlet ducts of the cylinder and the coolant-outlet-side gas ducts can be the inlet ducts of the cylinder. For example, the coolant-inlet-side component opening is the spark plug opening and the coolant-outlet-side component opening is the opening for the injection nozzle.
The cylinder head can be produced by casting. The cooling duct system is formed here by a core, wherein the core can be produced by 3D printing. The advantage of 3D printing is that any desired geometries, in particular those with undercut regions, can be produced.
For example, the web cooling duct rises between the coolant-inlet-side gas ducts, and therefore the contour of the upper side of the combustion chamber section can be followed in order to permit more efficient cooling.
Preferably, the upper wall rises between the coolant-inlet-side gas ducts, reaches its highest point on the coolant-inlet side before the center axis of the annular wall section and drops down toward the coolant-outlet side. This geometry ensures a particularly good flow toward the web. The highest point here means that point which is higher than the rest of the web cooling duct, at least from the center axis of the annular wall section on the coolant-inlet side.
In one refinement of the invention, the upper wall is partially wave-shaped with at least one wave crest, and therefore the coolant is deflected in a manner as free from turbulence as possible in the direction of the combustion chamber section. The downwardly directed guiding surface can be the dropping section of the wave crest here.
In a further embodiment of the invention, the web cooling duct has an extension which projects toward the combustion chamber section and is provided in the region of the annular wall section. It is possible by means of this extension to guide coolant in the region of the web closer to the combustion chamber section.
The extension is preferably provided in the region of the guiding surface and/or adjoining the region of the guiding surface on the coolant-outlet side, and therefore the coolant is deflected into the extension by the guiding surface.
For example, the upper wall of the web cooling duct has a wave trough in the region of the extension. This ensures that coolant sufficiently flows through the extension.
The extension can reach up to 9 mm or less to the combustion chamber section. The distance between the lower wall of the web cooling duct and the upper side of the combustion chamber section in the annular wall section is therefore at minimum only 9 mm or less, as a result of which particularly efficient cooling of the web is achieved.
In one variant embodiment, the cooling duct system has at least one outer cooling duct which runs to above one of the two coolant-inlet-side gas ducts and forms an upper coolant duct, as a result of which efficient cooling of the regions which are not cooled by the web cooling duct is made possible.
For example, in the half of the annular wall section which faces the outlet, in particular in the region of the coolant-outlet side of the two component openings, the web cooling duct leads into the upper cooling duct, and therefore the coolant is efficiently removed without relatively great pressure losses.
In particular, the upper wall, in particular the entire web cooling duct, rises again before the web cooling duct leads into the upper cooling duct, as a result of which a particularly advantageous flow is realized.
In one refinement of the invention, the web cooling duct is separated from the at least one outer cooling duct and the upper cooling duct on the coolant-inlet side of the center axis of the annular wall section. As a result, the coolant flow through the web cooling duct can be improved.
For example, on the coolant-inlet side of the two component openings, the web cooling duct branches into two branches which extend on different sides of the component openings, as a result of which a uniform cooling of the web around the component openings is made possible.
A guiding surface and/or an extension are preferably provided in each of the branches, and therefore optimum cooling of the web is achieved in each of the branches.
Two outer cooling ducts can be provided which flow together above the coolant-inlet-side gas ducts and form the upper cooling duct, as a result of which a coolant circuit through which the flow passes uniformly is realized.
The upper cooling duct preferably runs between the coolant-outlet-side gas ducts, and therefore the coolant-outlet-side gas ducts are also cooled.
Further features and advantages of the invention emerge from the description below and from the attached drawings, to which reference is made. In the drawings:
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of one or more preferred embodiments when considered in conjunction with the accompanying drawings.

Cylinder head for an internal combustion engine

Bayerische Motoren Werke Aktiengesellschaft


Provided is a mobile communication terminal and more particularly a mobile communication terminal for easily executing a memo function and a method thereof, whereby the memo function can simply be executed according to a state of the mobile communications terminal to thusly easily compose a memo or easily confirm memo contents, the composed memo can be displayed on a standby screen to thus allow a user to recognize the memo being composed and also allow the user to confirm the memo contents directly on the standby screen without undergoing complicated menu selection procedures, the memo can automatically be stored upon ending a call or occasionally, and the composed memo can immediately be sent in a text message format.

1. Field of the Invention
The present invention relates to a mobile communication terminal, and particularly, to a mobile communication terminal for facilitating an execution of a memo function, and a method thereof.
2. Background of the Invention
In general, a mobile communication terminal is equipped with various additional functions as well as a voice communication function. For example, the additional functions may include a short message transmission function, a memo function, a phone book function, an alarm function, and the like, and other functions are being provided to the terminal in recent times.
A method for executing additional functions of a related art mobile communication terminal will now be explained hereafter.
First, a menu calling (selecting) key equipped in the terminal is entered (pressed) to display a sub menu list. An additional function menu is selected from the sub menu to display the additional function list contained therein. From the displayed additional function list, a certain function which a user want to use is selected to be then executed.
In order to select the sub menu or the additional function displayed, a navigation key in a keypad is used to scroll up or down a selection bar to a desired additional function. Thereafter, a confirmation key is entered (pressed) or any numeral key in the keypad is used to directly enter the number assigned to each additional function.
Regarding a memo function among the additional functions of the mobile communication terminal, for example, the related art mobile communication terminal must disadvantageously perform many steps of a menu selection procedure as described above in order to compose a memo or confirm contents included in a previously composed memo.
In the related art mobile communication terminal, the complicated execution procedure for the memo function makes it difficult to fast execute the memo function during a call communication. Furthermore, even through having composed a memo, it may be possible for a user to habitually terminate the his terminal in a state of not storing the composed memo, and also the user may not recognize even the memo he has composed.

Mobile communications terminal having adaptive memo function and method for executing memo function


A method and circuits for checking for a pattern on a display is provided where the CRC of the pattern is calculated and compared to a CRC reference. A blanking signal is produced when the two patterns do not match. Video pixel data and a first seed value are processed in a CRC circuit generating a first CRC value. The first CRC reference is stored in a first memory that can be one 24 bit register, much smaller than the 2048 bit pattern storage memory conventionally required for the 32.times.l6.times.2 pattern. The comparison circuit compares the first CRC value and the first CRC reference, producing an unequal signal at the input of a control circuit if they do not match. The control circuit also receives a D/A blanking signal. Responsive to an unequal signal, the control circuit produces and latches the blanking signal at its output and the input of the D/A converter coupled to it. The D/A converter stops producing analog video output, and the screen goes blank. For interlaced images the CRC circuit generates a first even and odd CRC values. The CRC references also need to be based on even or odd interlaced frames of the protected pattern. The even and/or odd CRC value is compared to its respective CRC reference in the comparison circuit and the result passed to the control circuit. For additional security the CRC circuit can generate a second CRC value based on a second seed value and the video pixel data. The comparison circuit compares the second CRC value to a second CRC reference stored in a second memory. When the two do not match the unequal signal is produced at the output of the comparison circuit and is latched by the control circuit at the input of a D/A converter. Having two CRC values increases the security, because to keep the D/A converter from shutting down either the protected pattern or a different pattern that produces two identical CRC values has to be generated.

The present invention relates generally to the field of electronic devices, and is more specifically directed to a method and circuitry for comparing data.
The manufacture of software to comply to proprietary hardware standards without a license from the owner of the hardware standards, hereinafter unlicensed software, is a significant problem for the owner of the hardware standards and for software producers who have obtained a license, hereinafter licensed software producers. This problem can lead to low quality software because the owner of the proprietary standard is not given a chance to review the unlicensed software before it is released to the market. This is particularly of concern to game console manufacturers, who have proprietary standards for the manufacture of the console and either manufacture or license others to manufacture games, i.e. the software to operate on their hardware.
Many game console manufacturers have installed security devices to prevent unlicensed software from being able to play on their consoles. These security devices try to prevent games which are not manufactured by the console manufacturers or their licensees, but are manufactured by parties who are not licensed to manufacture games for the console, hereinafter unlicensed software producers.
If the security device determines that the game is not manufactured by a licensed software producer the console shuts down. Typically, from a technical viewpoint, most security devices can be designed around by the unlicensed software producers.
To avoid the problem of unlicensed games, some owners of the proprietary hardware standards for game consoles implement a security scheme that involves sending a pattern, hereinafter overlay pattern, to the display device and comparing this pattern with a reference pattern that is legally protected, such as a copyrighted pattern or is a pattern of a trademark. If the overlay pattern is different from the reference pattern the security device shuts down the console. If the overlay pattern corresponds to the reference pattern and the unlicensed software producer displays such a protected pattern he is violating the owner's copyright or trademark and the owner can typically stop the sale of products that violates his copyright or trademark.
FIG. 1 illustrates one such security device 10. The security device 10 is connected to a host interface 12 through a data bus 13 and an address bus 15. The security device 10 contains a pattern storage memory 14 for storing the overlay and reference patterns. When the overlay pattern is written to the pattern storage memory 14, the address of a reference pattern in a pattern reference ROM 16 is passed to the pattern storage memory 14 and the reference pattern is also retrieved by the pattern storage memory 14. The overlay and reference patterns are compared in a comparison circuit 18, typically using a bit by bit comparison. The result is passed to a control circuit 20.
The control circuit 20 is coupled to a digital to analog converter (D/A converter) 26. The D/A converter 26 receives the digital video pixel data 30 from the console's memory and CPU and outputs an analog video output 34 to a display device, hereinafter screen. If there is an exact match between the overlay pattern and the reference pattern the overlay control and color expansion circuit 22 de-references the overlay pattern in a look-up table and determines where on the screen the pattern should be displayed. The overlay pattern is then combined with video pixel data 30 in a pixel multiplexer 24 to make sure that the overlay pattern will be visible on the screen.
The control circuit 20 also receives a digital to analog blanking signal 32 (D/A blanking signal) from a conventional synchronizing ("sync") signal generator (not shown) in the CRT controller. If there is any difference between the overlay pattern and the reference pattern then the control circuit 20 permanently applies the D/A blanking signal 32 to the D/A converter. When the D/A blanking signal 32 is applied to the D/A converter 26, the analog video output 34 is the blanking signal 32 instead of the video pixel data with the overlay pattern.
One problem with such a security device 10 is that it requires a great deal of memory. For a 32.times.16.times.2 overlay pattern the security device 10 requires 1024 bits of RAM for the overlay pattern, in addition to the 1024 bits of ROM needed to store the reference pattern in the pattern reference ROM 16.
Additionally, the security device 10 requires a great deal of logic circuitry. The comparison circuit itself requires a large amount of logic circuitry to perform a bit by bit comparison of the entire overlay and reference patterns. Furthermore, the security device 10 also requires the overlay control and color expansion circuit 22 to de-reference the pattern through a look-up table. The security device 10 also needs the pixel multiplexer 24 to multiplex the pixels in the overlay pattern with the video pixel data 30.
Both the large memory requirement and the large logic requirement increase the complexity and area of the chip, making the chip both larger and more expensive. This goes against the long time goals of the semiconductor industry to reduce the size of an integrated circuit (IC) for a given functionality and to reduce the cost of ICs.
Another problem with the security device 10 is that the location of the read/write memory serving as the pattern storage memory 14 must be disclosed to the software to allow the software to place the overlay pattern into the pattern storage memory 14. This requires future hardware to maintain register compatibility, placing restrains on the future hardware. If register compatibility is not maintained the software will not be transportable between versions of the console. This would require the user to either not upgrade the console or to repurchase all of the games for the upgraded console, both unacceptable alternatives.
A further problem with the security device 10 is that the overlay pattern is checked and then displayed on the screen, leaving open the possibility that the correct overlay pattern may be replaced with another overlay pattern after the overlay pattern is compared to the reference pattern, but before the overlay pattern is displayed. It also allows for the possibility that the overlay control and color expansion circuit 22 and pixel multiplexer 24 will be completely by-passed and the overlay pattern may be simply not displayed at all. Both of these possibilities would make the security device 10 useless in stopping unlicensed games from being played on the console.

Security device for a video digital to analog converter


A polyisocyanate prepolymer composition which comprises the reaction product of a) diphenylmethane diisocyanate composition and b) an active hydrogen containing compound having a number average molecular weight of at least about 2000 wherein the reaction is carried out in the presence of a diluent capable of maintaining the average viscosity of the resulting prepolymer below about 500 cps at 25.degree. C. The prepolymer may be reacted with a resin composition to prepare soft elastomers.

Prepolymers useful for the production of elastomers have been known for many years. However, the known and currently employed prepolymers suffer from many perceived disadvantages. For example, prepolymers formed from active hydrogen containing compounds particularly those having molecular weights of 2000 or more, often have relatively high viscosities which in turn result in inconsistent prepolymers from batch to batch. Further, because of the inconsistency in the resultant prepolymers, high scrap rates are common.
To employ prepolymers having a relatively high viscosity, the prepolymer compositions generally require heating to allow for material flow. However, heating causes degradation of the prepolymer leading to less effective elastomers.
Thus, there is a need for low viscosity prepolymers which are stable at room temperature and which can be utilized to form elastomers over a broad processing range. Additionally, there is a need for elastomers which can be processed at ambient temperatures as opposed to known elastomers wherein the isocyanate component has to be kept at higher than ambient temperatures in order to effectuate a complete reaction.

Polyisocyanate prepolymer compositions and soft elastomers prepared therefrom


A delivery apparatus and method for the arrangement, generation and delivery of an integrated composite work having one of audio and visual content. The system includes a playback device (14) having a plurality of the audio or visual works stored therein, preferably on storage media (55), with distinctive identification means. Each of the stored works has a predetermined fixed content and the content of each work is one of simultaneous and sequentially related to at least one other of the works. A controller (42) is connected to the playback apparatus (41) and generates a playback of a selected first work. After the first work is selected, the controller (42) selects an additional work. If playback of the two works is to be simultaneous, the selection of the additional work will be made only from works which are simultaneously related. If the playback of the two works is to be sequential, the selection of the additional work will be made only from works which are sequentially related.

Conventional audio playback apparatus, such as a compact disk player, has the capability of sequentially playing a random sequence of pre-recorded audio tracks or cues. Thus, a plurality of recordings by the same artist or same composer or of audio-related material of various kinds can be randomly shuffled by the controller of the disk player and then played for the listener. This technology can also be used for the random sequential playing of video disk tracks, although such capability is not in such wide-spread use.
The sequential playback of pre-recorded audio or video works, however, has been limited to the sequential playing of a plurality of discrete compositions, rather than the generation of an integrated or continuous composite composition from the pre-recorded works. Thus, in prior art systems one complete musical composition is played and then another one is randomly selected and played. No attempt is made to form a unitary, although composite, musical work from two or more pre-recorded tracks.
One area in which pre-recorded audio compositions have been extensively used is in connection with public displays of the type found in museums, entertainment facilities and trade shows. Thus, a diorama illustrating the habitat of a particular group of animals also may include recordings of the voices of these animals in their natural habitat or environment. Most typically, the recordings played at such public exhibitions will be created by a sound engineer who overlays and mixes a plurality of individual recorded tracks to form a single recording that can be played for visitors of the diorama. A single track of, for example, fifteen minutes can be used to illustrate the various voices of the inhabitants of the diorama, and the visitors will have an experience which is substantially enhanced over merely the visual impact of the diorama. Museum personnel, however, will hear the diorama recording over and over during the course of the day to the point that the repeating sequencing of even a fifteen minute track becomes aggravating.
Several types of enhancements have been provided for the museum-type, repeating, audio delivery systems. First, infrared sensors have been used to sense the density or number of people listening to the audio program and to adjust the volume. When more listeners are present, the volume will be shifted toward a high volume setting, while the absence of sensed listeners reduces the volume. Second, sensors also have been used to trigger a pre-recorded audio sound so that when a listener walks in front of a sensor a sound track or sound cue is played. The first of these enhancements does not affect the monotony of repetition, and the second only has the minor impact of adding an event-driven sound to the overall audio playback.
Another enhancement which has been employed is to pan or move the sound being played over the plurality of spaced apart speakers in a speaker system. Thus, a rain storm can be heard first at one end of the diorama and then gradually move or pan through the speaker system to the opposite end. This type of enhancement similarly does not eliminate the redundancy of repetition, and the pans or moves of the sound merely become part of the repeating pattern.
It is also known in the music industry to create musical compositions by computer-controlled apparatus. Thus, a music synthesizer can be controlled by a computer in a manner used to generate a musical composition, but the generation of such audio or musical works is not based upon pre-recorded material, but instead on the synthesis of music as controlled by music composition software.

Apparatus and method for generation of integrated composite audio-visual works