An electronic mail system for transmitting a voice message from a telephone to a mail terminal equipment using an electronic mail, a destination identifier and a voice message are inputted from the telephone. A voice signal is generated in correspondence to the voice message and the destination identifier and the voice signal are transmitted from the telephone to a transceiver apparatus via a telephone line network. In the transceiver apparatus, a voice file is produced from the voice signal received from the telephone via the telephone line network and then the electronic mail is produced from the voice file and the destination identifier. The electronic mail is transmitted to the mail terminal equipment having a voice output function via a local area network (LAN). The mail terminal equipment reproduces the voice message from the voice file of the electronic mail using the voice output function.

1. Field of the Invention
The present invention relates to an electronic mail transceiver apparatus in an electronic mail system, and more particularly to the transmission of electronic mail in a voice message form in the electronic mail system.
2. Description of Related Art
Generally, a message handled in electronic mail is text data in many cases. However, there is the strong demand to handle voice data in an electronic mail system and an electronic mail system is recently developed in which voice data is inputted from a telephone, as disclosed in Japanese Laid Open Patent Disclosure (Heisei 3-99543).
The electronic mail system disclosed in the above reference is shown in FIG. 1 and includes a mail storage switching apparatus 101 which is composed of a message input/output processing section 102, a mail terminal access processing section 103, a message storing section 104, a correspondency table storing section 105, and a mail box 106. The electronic mail system further includes telephones 112 and 114 and a mail terminal equipment 116. The correspondency table storing section 105 stores a correspondency table in advance. The correspondency table is a set of mail terminal identifier and telephone number provided for each mail terminal equipment.
In such an electronic mail system, when a voice message is to be issued, a user first operates the mail terminal equipment 116 to transmit a message producing request to the mail storage switching apparatus 101. In response to the message producing request, the mail storage switching apparatus 101 searches the correspondency table for a set of mail terminal identifier and telephone number of the request issuing terminal equipment. Then, the mail storage switching apparatus 101 issues to the message input/output processing section 102 an input processing request of a voice message to be inputted from a telephone 112 having the searched telephone number. In response to the input processing request, the message input/output processing section 102 awaits a call from the telephone 112 having the searched telephone number by the user of the request issuing mail terminal equipment 116. When receiving the call, the message input/output processing section 102 acquires the voice message form the telephone 112 and stores the voice message with a message identifier assigned thereto in the message storing section 104. At the time when the acquisition and storage of the voice message is completed, the message input/output processing section 102 sends the message identifier of the stored voice message to the mall terminal access processing section 103 which transmits the message identifier to the request issuing mail terminal equipment 116 as the message producing result. In this manner, the voice message can be handled in the electronic mail system.
However, in the above conventional electric mail system, the mail storage switching apparatus 104 is connected to the telephones 112 and 114 and the mail terminal equipment 116. In order to input a voice message, the user needs to operate not only the telephone 112 but also the mail terminal equipment 116. That is, in the conventional electric mail system, a set of personal computer as the mail terminal equipment and telephone needs to be provided for each user so that numerous investment is necessary for the electronic mail system for a voice message. In addition, there is another problem in that the user cannot execute electronic mail transmission from another place where the personal computer as a mail terminal equipment is not located.

Control of transmission of electronic mail in voice message form


A method for fabricating capacitors of a DRAM by employing liquid-phase deposition. Since the working temperature required for performing liquid-phase deposition is low, the deposition process can be performed in the presence of the photoresist. This method comprises: filling the contact hole and covering the isolation layer with conductive layer; performing an etching process on the conductive layer by using photoresist and low-temperature spacer as mask; again performing an etching process on the conductive layer, to a desired depth by controlling the etching time and using the low-temperature spacer as mask; removing the low-temperature spacer for finally forming the lower electrode of a cylindrical capacitor.

1. Field of the Invention:
This invention relates to a method for fabricating capacitors of a dynamic random access memory (DRAM), and more particularly, to a method for fabricating a capacitor of a DRAM by using selective interlayer dielectric formation technology.
2. Description of Related Art:
FIG. 1 shows the circuit of a memory cell that includes a MOS transistor T and a capacitor C within a DRAM. The charging and discharging properties of the capacitor can be used to store data. Generally, a digit in a block of binary information is stored either in a charged capacitor if it is a logic 1 or in an uncharged capacitor if it is logic zero. The source of the MOS transistor T is connected to a corresponding bit line BL, the drain of the MOS transistor T is connected to the storage electrode (or lower electrode) 15 of the capacitor C, and the gate of the MOS transistor T is connected to a corresponding word line. The upper electrode 14 is connected to a fixed voltage source. There is a dielectric layer 12 filling the space between the upper electrode 14 and lower electrodes 15 of the capacitor C.
The capacitor is the major structure used by a memory cell for storing information. If the capacitance of the capacitor is high, the effect caused by noise will be reduced when a piece of information is read, and it will further reduce the refreshing frequency.
Conventionally, a poly spacer etch back technique which utilizes a wet etching process for removing a dummy oxide layer with silicon nitride as the etching stop layer is used for forming cylindrical capacitors. However, it is cracks often occur during the fabrication process due to silicon's high stress.
A conventional method for fabricating cylindrical capacitors of a DRAM is shown in FIGS. 2A through 2E. FIG. 2A shows formation of a field effect transistor on the surface of a semiconductor substrate 200 such as a p-type silicon substrate. The field effect transistor is isolated by field oxide 204; the field effect transistor contains a gate 212, and source/drain 222 and 232. Then, an isolation layer 206, for example, an oxide, and an etching stop layer 216, for example, silicon nitride, are formed in sequence on the substrate 200. A contact hole is formed through the isolation layer and the etching stop layer to expose the source/drain region 222. Source/drain region 222 is designed to couple with transistor. The contact hole is then filled with a conducting material, such as doped polysilicon, to form a conductive plug 242.
In FIG. 2B, a conductive layer 252 and a dummy oxide layer 226 are formed on the top of the etching stop layer 216 in sequence, to define the bottom region of a lower electrode of the desired cylindrical capacitor and to make contact with the conductive plug 242. The conductive layer 252 can be doped polysilicon and the dummy oxide layer 226 can be borophosphosilicate glass (BPSG) or phosphosilicate (PSG).
In FIG. 2C, a conductive layer 262 is formed to cover everything on the top of the substrate 200. The conductive layer can be doped polysilicon.
Next, in FIG. 2D, an anisotropic etching process is performed for forming the conductive spacer 262a, using the etching stop layer 216 as an etch stop. The spacer 262a is the portion of conductive layer 262 on the sides of the dummy oxide layer 226 and in contact with the conductive layer 252. The conductive spacer 262a and conductive layer 252 construe the lower electrode of the cylindrical capacitor 272.
Referring next to FIG. 2E, the dummy oxide layer 226 is removed by a wet etching method. A dielectric layer 236 having a thickness of approximately 10-60 .ANG. is then formed on the exposed surface of the lower electrode of the cylindrical capacitor 272. The dielectric can be silicon oxide, a silicon nitride/silicon oxide (NO) structure, a silicon oxide/silicon nitride/silicon oxide (ONO) structure, or other dielectric materials with high permissivities such as Ta.sub.2 O.sub.5, Pb(Zr,Ti)O.sub.3 (i.e. PZT), or (Ba,Sr)TiO.sub.3 (i.e. BST).
After that, a conductive layer 282 is formed on the top surface of the dielectric layer 236 as the upper electrode of the cylindrical capacitor to complete the capacitor of a DRAM.
However, the conventional method for fabricating cylindrical capacitors of a DRAM has to employ wet a etching process to remove the oxide in the presence of silicon nitride as the etching stop layer. Cracks often occur during the fabrication process due to silicon's high stress; furthermore, the conventional fabrication method is too complicated, and as a result the fabrication cost is not economical.

Method for fabricating capacitors of a dynamic random access memory


An ECC circuit has an error correction function of N (N is a natural number) bits for output data of a memory cell array. A BIST circuit reads background data out of test target addresses, and writes/reads inverted data of the background data in at least a part of the testing target addresses. An N+1 bit error detection circuit outputs a signal indicative of test NG (defective product) when a total of error bit numbers n1 and n2 detected by the ECC circuit during first and second readings exceeds N.

1. Field of the Invention
The present invention is directed to a semiconductor integrated circuit, and particularly, it is applied to a memory on which an error correcting code (ECC) circuit is utilized.
2. Description of the Related Art
Miniaturization of elements with progress of semiconductor device technology has caused, for example, a reduction in a storage node capacity of a cell that stores data. Consequently, a soft error of data has become a big problem.
Thus, in recent years, an ECC circuit has frequently been utilized as countermeasures of such a soft error.
The memory on which the ECC circuit is utilized has a section for storing data bits as normal data and a section for storing code bits used to detect errors. A data bit error is detected based on a code bit. If an error is detected, a bit in which the error occurs is further checked to execute error correction.
Error correction and detection capabilities of the ECC circuit are decided by the number of code bits. Generally, most of ECC circuits have 1-bit error correction functions and 2-bit error detection functions. In this case, single error correction-double error detection (SEC-DED) codes are used as code bits.
Meanwhile, in the system LSI chip, the built-in self test (BIST) circuit is often utilized in order to test defectiveness/nondefectiveness of the memory. The BIST circuit functions to write/read a test pattern in/from the memory, and to detect a defect of a cell by comparing read-out data as a memory output with written data as an expected value.
As the test pattern, a so-called marching pattern is widely used by taking a Stack-at-fault rate, testing time, a circuit size etc., into consideration.
A test algorithm (basic operation) by the marching pattern is as follows.
(1) First, background data are written in all the cells (all the addresses) that constitute the memory. As the background data, for example, repeated data [1010 . . . ], [0101 . . . ], identical data [1111 . . . ], [0000 . . . ] etc., are used.
(2) Next, a testing target address (first address) is specified, and data is read out of the testing target address. Then, the read-out data is compared with the background data (expected value) to test the testing target address.
(3) Subsequently, inverted data of the background data is written/read in/from the testing target address. For example, the inverted data becomes [0101 . . . ] if the background data is [1010 . . . ], and [0000 . . . ] if the background data is [1111 . . . ]. The read-out data is then compared with the inverted data (expected value) to test the testing target address.
Subsequently, the operations (2) and (3) are repeated while the testing target addresses are changed. When all the addresses are tested, the testing operation is finished.
FIG. 1 shows an example of a conventional semiconductor integrated circuit comprising a memory on which an ECC circuit is utilized and a BIST circuit.
A data bit as normal data and a code bit for error detection are stored in a memory cell array 11. During testing, a data bit is generated at, e.g., the BIST circuit 13, and a code bit is generated at, e.g., the ECC circuit 12 based on the data bit.
The read-out data as the memory output is subjected to error correction by the ECC circuit 12, and then transferred to the BIST circuit 13. Assuming that the ECC circuit 12 has a 1-bit error correction function, even if there is a 1-bit defect (cell failure or the like) in the testing target address, the defect can be corrected. Thus, such a defect can be permitted.
That is, in the BIST circuit 13, since the read-out data that has been subjected to the error correction by the ECC circuit 12 is compared with the background data (expected value), both data are equal to each other when there is a defect not exceeding one bit in the testing target address, and a result of the testing determines a product to be nondefective.
On the other hand, when there is a defect of two bits or more (cell failure or the like) in the testing target address, this defect cannot be corrected by the ECC circuit 12 that has the 1-bit error correction function. Thus, in the BIST circuit 13, complete coincidence is not determined between the read-out data and the background data (expected value), and a result of the testing determines a product to be defective.
However, in the conventional test carried out by generating the marching pattern at the BIST circuit 13, a defective bit may not be accurately detected in the testing target address. In this case, there is a problem that a defective product may be determined as nondefective.
This problem is specifically described below.
It is assumed that an ECC circuit that has a 1-bit error correction function and a 2-bit error detection function is utilized in a memory to be tested.
To begin with, consideration is given to a case in which [1010 . . . ] is written as background data in all the addresses of the memory.
As shown in FIG. 2, testing target addresses 0, 1, 2, . . . 7 are specified after the background data is written, and 8-bit data is read out of the testing target addresses 0, 1, 2, . . . 7. It is assumed here that among the testing target addresses 0, 1, 2, . . . 7, a bit of the address 5 is a Stack-at-one fault (always "1") and a bit of the address 7 is a Stack-at-zero fault (always "0").
In this case, as shown in 1) of the drawing, the Stack-at-zero fault of the address 7 cannot be detected while the Stack-at-one fault of the address 5 can be detected. That is, since the ECC circuit detects only the 1-bit error of the address 5 to correct the error, the BIST circuit determines a product to be nondefective even if the product is defective.
Subsequently, as shown in 2) of the drawing, writing/reading of inverted data [0101 . . . ] of the background data is executed in the testing target addresses 0, 1, 2, . . . 7.
In this case, the Stack-at-one fault of the address 5 cannot be detected while the Stack-at-zero fault of the address 7 can be detected. That is, since the ECC circuit detects only the 1-bit error of the address 7 to correct the error, the BIST circuit determines a product to be nondefective even if the product is defective.
Similarly, consideration is given to a case in which [1111 . . . ] is written as background data in all the addresses of the memory. Conditions are similar to those of the above example.
When 8-bit data is read out of the testing target addresses 0, 1, 2, . . . 7, as shown in 3) of the drawing, the Stack-at-one fault of the address 5 cannot be detected while the Stack-at-zero fault of the address 7 can be detected. That is, since the ECC circuit detects only the 1-bit error of the address 5 to correct the error, the BIST circuit determines a product to be nondefective even if the product is defective.
Subsequently, as shown in 4) of the drawing, writing/reading of inverted data [0000 . . . ] of the background data is executed in the testing target addresses 0, 1, 2, . . . 7.
In this case, the Stack-at-zero fault of the address 7 cannot be detected while the Stack-at-one fault of the address 5 can be detected. That is, since the ECC circuit detects only the 1-bit error of the address 5 to correct the error, the BIST circuit determines a product to be nondefective even if the product is defective.
Therefore, if the testing is executed by using the marching pattern even while there are Stack-at-2 bit faults in the testing target addresses 0, 1, 2, . . . 7, the ECC circuit cannot detect the Stack-at-2 bit faults simultaneously. Consequently, the BIST circuit mistakenly determines the product that has the Stack-at-2 bit faults in the testing target addresses 0, 1, 2, . . . 7 to be nondefective.
Incidentally, such a problem can be solved by increasing kinds of data patterns used for testing. That is, if there are Stack-at-faults a number of which exceeds the correction capability of the ECC circuit in the testing target addresses 0, 1, 2, . . . 7, testing can be carried out by using data patterns that enable sure detection of all the Stack-at-faults.
However, if the testing is carried out by increasing kinds of test patterns as described above, problems of increases in complexity and area of the BIST circuit, testing time etc., inevitably occur.


The subject matter disclosed herein relates to reduction of effective voltage drops within pixels in active matrix displays such as electrowetting display devices. The electrowetting display device comprises a plurality of pixel areas, wherein each pixel area comprises a hydrophobic surface, a first fluid and a second fluid on the hydrophobic surface, wherein the first fluid is immiscible with the second fluid, and a pixel electrode under the hydrophobic surface, wherein the pixel electrode has a substantially U-shape. A thin film transistor is coupled to the pixel electrode and a voltage source. Voltage via the thin film transistor and the voltage source applied to the hydrophobic surface via the pixel electrode causes the hydrophobic surface to become more hydrophobilic to thereby move the second fluid onto the hydrophobic surface to thereby substantially displace the first fluid on the hydrophobic surface.

Many portable electronic devices include displays for displaying various types of images. Examples of such displays include electrowetting displays (EWDs), liquid crystal displays (LCDs), electrophoretic displays (EPDs), light emitting diode displays (LED displays), etc. In electrowetting displays, the resistance of the electrolyte in a fluid in the pixel areas decreases the effective voltage of the pixel area. FIG. 1 illustrates a pixel area 100 represented as a simplified circuit. As can be seen, the pixel area 100 can be represented as including a voltage source 102, a thin film transistor (TFT) 104, storage capacitance Cs 106, capacitance of the area of the pixel's electrode Cew 108 and REGG, which represents the resistance of the electrolyte.
Equation 1 below illustrates the relationship of the parameters that influence the voltage drop in the pixel area 100, where t line is a line time, Vout equals Vsource minus Vkb, where Vkb is the kickback voltage drop present in all active matrix displays. As previously noted Cew is a pixel capacitance that is related to the area of the pixels' electrode, and Cs is a storage capacitance of the pixel area.
                              V          REGGdrop                =                              [                                          V                out                            -                                                V                  out                                *                                  (                                      1                    -                                          exp                                                                    (                                                                              -                                                          t                              line                                                                                R                              EGG                                                        *                                                          C                              EW                                                                                )                                                                              )                                                      ]                    *                      [                                          C                EW                                            (                                                      C                    S                                    +                                      C                    EW                                                  )                                      ]                                              (        1        )
In conventional electrowetting displays, the pixel electrode is a flat layer underneath the pixel area and thus, has a large area. Accordingly, REGG can be relatively large, for example, up to 300 mega ohms. Thus, the voltage drop attributable to REGG can be significant thereby greatly affecting the effective voltage of the pixel area.

Electrowetting display pixel architecture


A computer-implemented method for object localization includes providing a plurality of tags having fixed positions within an environment and known identifications, and providing a reader, for detecting the tags and reading the identifications, wherein the reader detects a plurality of tags within a scanning volume having a known shape. The method further includes determining positions for the plurality of tags within the scanning volume, and determining a position of the reader according to the positions for the plurality of tags within the scanning volume and the known shape of the scanning volume.

1. Technical Field
The present invention relates to object localization, and more particularly to a system and method for RFID based localization of an object.
2. Discussion of Related Art
Localization as a technology finds use in many applications ranging from autonomous navigation to augmented reality. There are many different technologies that can be used in localization, for example, the global positioning system (GPS) and cameras.
Few proposed solutions for limited application domains have been demonstrated. A generic technology is yet to be developed for multiple purposes.
Therefore, a need exists for an improved system and method for object localization.


An apparatus having a smart material actuator, a support structure and at least one temperature compensating material insert, either externally mounted to the support structure, integrally formed with the support structure, or any combination thereof. The apparatus includes a mechanically leveraged electrically stimulated smart material. The support structure and actuator are susceptible to the effects of differences in thermal coefficients of expansion of the materials used in the construction. The smart material typically displaces less than 0.001 inches and is leveraged up to fifty times to obtain useful movement. The temperature effect on the smart material is therefore leveraged and amplified producing undesirable motion in the apparatus with ambient and/or operating temperature changes. A method for dimensioning and placement of a compensating insert with respect to the support structure provides an accurate and cost effective compensating insert.

Various smart material actuator technologies have been developed for a wide range of applications in different industries. One component used in this type of actuator is an electrically stimulated smart material actuator. These smart material actuators when electrically stimulated change shape. This shape change can be designed such that one axis predominantly changes. Such a smart material actuator can be incorporated within a main support structure. As the axis of the smart material actuator changes dimension its motion is magnified by a lever integral to the main support structure. As a result of the magnification factor developed by the main support structure, extremely small differences of thermal coefficients of expansion between the smart material and main support structure can create relatively large movements of output in the main support structure over normal operating temperature ranges. This movement can be as much as fifty percent of the usable output of the actuator system.
Previous designs place the compensating element in line with the smart material. This method suffers from several problems. One such problem is the length of the compensating element inserted between the main body and the smart material increases the overall length of the actuator. Further smart materials are capable of delivering large amounts of force, so the compensating element must be sufficiently stiff to prevent a reduction of the force and movement performance of the actuator while acting as the inline compensating element. This is a difficult combination to achieve with inexpensive materials.
Another common design is to place sleeves with different coefficients of thermal expansion around the smart material causing the cavity that captures the smart material to expand and contract with temperature. This system uses several parts, all of which are complex, and costly to machine and increases the overall size making it less desirable.

Temperature compensating insert for a mechanically leveraged smart material actuator


A microstrip antenna (300) provides improved bandwidth control by gap coupling first and second triangular patches (310, 312) over a ground plane (322). The first and second triangular patches (310, 312) are resonant at different frequencies. The use of gap-coupled triangular patches (310, 312) allows for smaller structured microstrip antennas.

There is a continuing interest in personal communications systems, such as cellular telephones and pagers. Product requirements for these systems typically call for very small, lightweight, and low cost antennas. Microstrip antennas have been used in personal communication systems to accommodate these smaller design requirements, because they can be fabricated using inexpensive printed circuit board technology. Over the years, many forms of microstrip antennas have been developed, the "patch" antenna being one of the most popular. Patch antennas typically comprise radiator elements in the form of rectangular or square patches disposed onto a substrate over a ground plane. The substrate materials used for patch antennas typically have dielectric constants (.beta..sub.r) below 10 in order to achieve wider bandwidths. However, the major weakness of microstrip antennas still remains their very narrow impedance bandwidth characteristics.
FIG. 1 shows a prior art patch antenna 100 formed with a single rectangular patch having a resonant length (along length 110) characterized by equation: ##EQU1## c is the speed of light, f is the resonant frequency, and .epsilon..sub.r is the dielectric constant of substrate. To improve the bandwidth of this single resonant circuit, additional patches can be added to provide two resonant circuits. FIG. 2 shows a prior art patch antenna 200 with two gap-coupled rectangular patches 202, 204. The advantage of the two gap-coupled rectangular patches over the single patch is an increase in bandwidth, however the disadvantage is that the gap-coupled rectangular patches require an increase in the overall size of the antenna to achieve the improved bandwidth.
As an example, a single patch antenna, such as the antenna shown in FIG. 1 (not to scale), can be designed to resonate at a frequency of 1.85 gigahertz (GHz) when formed on a ceramic filled polytetrafluoroethylene (PTFE) substrate 102 having a dielectric constant .epsilon..sub.r =6. Substrate dimensions measuring 4.4 centimeters (cm) along width 104, by 3.7 cm along length 106, with a patch size measuring 3.8 cm along width 108, by 3.1 cm along length 110 produce a bandwidth of approximately 13.8 megahertz (MHz). The bandwidth can be increased by providing a longer substrate, such as the antenna shown in FIG. 2 (not to scale), measuring 6.9 cm along length 206 and with the second patch 204 having the same width but a slightly longer length 208 of 3.15 cm. With this second configuration the bandwidth increases to approximately 78 MHz, but the size of the antenna structure has effectively doubled. Increasing the size of the antenna structure by adding multiple patches thus makes an antenna less attractive for use in portable communications equipment which is troublesome since small size is particularly desirable in hand-held products, such as cellular handsets. Accordingly, there is a need for an improved microstrip antenna which provides a small, light weight, cost effective structure.

Microstrip antenna and method of forming same


Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections.

The present disclosure herein relates to a semiconductor device, and in particular, to a vertical-type memory device.
Higher integration of semiconductor devices is desired to satisfy demands for high-performance and low-cost electronic devices. In particular, the integration of memory devices can affect product prices. The integration density of typical two-dimensional (2D) or planar memory devices may be determined by the area occupied by a unit memory cell. Thus, integration of the 2D or planar memory devices may be influenced by fine pattern technology used in the device. However, process equipment for increasing pattern fineness may be very expensive and therefore can set a practical limit on increasing integration density for 2D or planar memory devices.


This invention relates to a method for simultaneously detecting live and dead cells using two fluorogenic reagents: calcein AM and ethidium homodimer. Live cells are distinguished by an intense uniform green fluorescence generated by the enzymatic hydrolysis of calcein AM: ##STR1## Dead or damaged cells are distinguished by a bright red fluorescence resulting from nucleic acids stained with ethidium homodimer: ##STR2## The assay is useful to determine cell viability and to monitor cytotoxicity agents or events.

Evaluation of the viability of biological cells through cytotoxicity measurements is important for assessing the effect of drugs, environmental pollutants, temperature and ionic extremes, radiation and irradiation, other cells and biological modifiers and other potentially adverse factors on cells and tissues. Cell membrane integrity is commonly used to indicate cell viability. Loss of the protective cell membrane results in loss of cell structure, loss of critical intracellular contents, loss of essential ionic gradients and loss of electrical potential. The inevitable result of a major loss of membrane integrity is cell death.
While there is not an exact equivalence between an intact cell membrane and the term "viability" (technically defined as the ability of a cell to maintain its existence), it is common to refer to cells that have intact membranes as "viable" cells and cells where the membrane has been irreversibly disrupted by a cytotoxic reagent as "dead" cells. There is, of course an intermediate condition where a cell that retains its membrane is in the process of "dying". A dying cell is not actually viable in that it cannot be cultured or reproduce. Dying cells are nevertheless often counted as living by common screening tests that rely on cell membrane integrity.
A common feature of loss of membrane integrity is the formation of pores which permit the passage of low molecular weight molecules (MW<2000 Daltons) in and out of the cytoplasm. This enhanced permeability has been the basis of many cell viability and cytotoxicity evaluations. The most common methods in use for cytotoxicity/viability measurements are .sup.51 Cr release, which uses a radioactive dye, and Trypan Blue exclusion, which uses a colored, non-fluorescent dye.
Fluorescent dyes can be detected with greater sensitivity than can colored dyes and do not have the disposal problems associated with the use of radioactive materials. The combination of different colored fluorescent probes to simultaneously detect live and dead cells is generally described by Haugland, HANDBOOK OF FLUORESCENT PROBES AND RESEARCH CHEMICALS, Set 24 (1989-91). Haugland suggests combining the use of a non-polar membrane permeant derivative that is converted to a polar fluorescent product inside live cells and a polar tracer of another color that is excluded from cells until the membrane is ruptured. Propidium iodide is mentioned as the most common fluorescent polar tracer complementary to those that are retained in live cells, although the reference also notes the potential usefulness of ethidium bromide and ethidium monoazide. Haugland and others have described the use of fluorescein, particularly carboxy fluorescein diacetate, with propidium iodide, for example for use with flow cytometry for sorting live and dead cells.
Two problems with the use of carboxy fluorescein diacetate are leakage from cells following hydrolysis and sensitivity to intracellular pH. Inside living cells, calcein AM is hydrolyzed to a fluorescent dye, calcein, that is well retained by cells, as described in the Haugland reference. The reference does not mention the simultaneous use of calcein AM in combination with any other dye used to detect dead cells. Calcein is less sensitive to intracellular pH than other fluorescein compounds, making it less likely to be quenched in intracellular environments.
Although ethidium homodimer is also described in the Haugland reference (Set 28), the use of ethidium homodimer as a viability stain for cells is not described. Ethidium homodimer has exceptionally high affinity for nucleic acids that is several orders of magnitude greater than ethidium bromide or propidium iodide. It is this high affinity that facilitates the simple, no wash, procedure of this invention. The use of propidium iodide results in unbound dye causing background fluorescence, which usually necessitates washing the cells after combination with the reagent. In contrast, the greater affinity of ethidium homodimer for nucleic acids results in virtually no background fluorescence, thus removing the requirement for washing cells and simplifying and accelerating the assay. The lack of background fluorescence and increased sensitivity related to the use of ethidium homodimer and calcein AM results in a two-color fluorescence assay that can detect fewer cells using a smaller sample. The combination of ethidium homodimer and calcein AM has not previously been suggested as or demonstrated to be suitable for a simultaneous or sequential two-color fluorescence assay of cell viability and cytotoxicity .

Dual-fluorescence cell viability assay using ethidium homodimer and calcein AM


A vehicle controller includes: a recognition unit that recognizes a surrounding state of a subject vehicle traveling in a road lane; an area specification unit that specifies a specific area in the lane in which the subject vehicle travels; and a driving control part that controls the subject vehicle with respect to a vehicle traveling ahead thereof, based on a result recognized b the recognition unit. The driving control part determines a condition of shifting from a first support status to a second support status such that there is a vehicle traveling ahead of the subject vehicle in the lane; and, if the subject vehicle enters the specific area at the first support status, the subject vehicle keeps the first support status, and if the subject vehicle enters the specific area at the second support status, shifts the support status from the second to the first support status.

WO 2018/047249 A1 (which may also be referred to as Patent Document 1) discloses a traveling plan revising device that includes: a traveling plan acquiring unit which acquires a first traveling plan from an automatic driving control device; a surrounding vehicle information acquiring unit which acquires surrounding vehicle information including at least a positional relationship between an own vehicle and surrounding vehicles; and a traveling plan revising unit which sets, as a traveling plan revision section, at least a partial section between a current location and an automatic driving level reduction switching location and constructs a second traveling plan with respect to the traveling plan revision section.
WO 2017/175377 A1 (which may also be referred to as Patent Document 2) discloses a vehicle control system that includes: an acquisition unit that acquires traffic conditions ahead in the direction a host vehicle is traveling; a prediction unit that refers to the traffic conditions acquired by the acquisition unit, and predicts a future state related to the host vehicle or the vicinity of the host vehicle; and a control unit that executes a vehicle control, and, after the vehicle control has been switched cancelled, prevents the switching or canceling of the vehicle control if the prediction unit predicts a return to the state before the switch or cancellation was executed within a prescribed period or within a prescribed travel distance.

Vehicle controller, vehicle, and vehicle control method


A transceiver employing a steerable phased-array antenna includes a modem architecture in which signals from each antenna element in the array are independently processed down to the individual baseband channel level, and digital beamforming is performed at baseband. The data rate reduction from IF to baseband permits parallel signal data from multiple antenna elements to be time multiplexed and serially processed at acceptable data rates at baseband with minimal modem hardware requirements. Both for transmit signal modulation and received signal demodulation, the computation of carrier tracking, automatic gain control (AGC)/power-control, and beamforming are shared by the same processing circuitry for all channels when performed at baseband. The resulting baseband circuitry is only incrementally larger than that required for carrier tracking and AGC alone, yet accomplishes independent beamforming for each antenna element on each user channel.

1. Field of the Invention
The present invention relates to wireless communication transceivers and modems and, more particularly, to the construction of a multi-frequency, multi-channel transceiver system such as might be used in a multi-user base station for terrestrial cellular or fixed-wireless applications.
2. Description of the Related Art
Directional antennas are widely used in a variety of communications systems to more efficiently transmit and receive radiated signals. Relative to an isotropic antenna, which transmits and receives signals equally in all directions, a directional antenna has an antenna gain pattern that is greater in certain directions than others, typically having a higher-gain main lobe several degrees wide (i.e., an antenna beam). Generally, a greater antenna gain reduces the amount of power required to transmit and receive signals between two communication devices. Thus, steering the main lobe of a transceiver's antenna gain pattern in the direction of another communication device facilitates communication between the two devices.
To be useful in certain applications, it may be necessary to rapidly point the antenna beam of a directional antenna in different directions. For example, base stations employed in cellular or wireless communication systems are required to communicate with several mobile communication devices at once. Often, the cell or region covered by the base station is divided into angular sectors (e.g., three 120° sectors), with certain antennas being responsible for communications with any mobile communication devices in a given sector. To permit virtually instantaneous redirecting of the antenna beam within the sector, an antenna formed of a phased array of independently controllable antenna elements may be used. The antenna beam is formed by applying appropriate phase and gain to the individual elements in the array.
More specifically, beamforming is a type of spatial filtering in which an array of sensor elements is controlled with appropriate signal processing to implement a phased array antenna for the purpose of shaping the antenna response over time in a space-varying manner (i.e., steering gain in some directions, while producing attenuation or nulls in other directions). In a radio communications system, a signal arriving at each element of an antenna array will arrive at slightly different times due to the direction of arrival with respect to the antenna array plane (unless the signal has normal incidence to the plane, in which case the signal will arrive at all elements simultaneously). A phased-array receive antenna achieves gain in a particular direction by phase shifting, or time shifting, the signal from each element, and then summing the phase-shifted element signals in a signal combiner. By choosing the relative phasing of each element appropriately, coherence can be achieved for a particular direction of arrival (DOA), across a particular signal bandwidth.
Digital beamforming is analogous to analog beamforming, except that the received signal on each antenna element is independently digitized, and the phasing/combining operation is performed mathematically on the digital samples. The present inventors describe digital beamforming techniques in U.S. patent application Ser. No. 09/778,854 entitled "Integrated Beam Forming/Rake/MUD CDMA Receiver Architecture", filed Feb. 8, 2001, the disclosure of which is incorporated herein by reference in its entirety. Conventionally, digital beamforming is done on a wideband signal, prior to despreading a CDMA waveform. This forces the computationally intense beamforming to take place at a much higher sampling rate, resulting in more mathematical operations per second, and corresponding increased hardware cost. To address this shortcoming, beamforming can be performed at baseband, as disclosed by Hanson et al. in U.S. Pat. No. 6,052,085, the disclosure of which is incorporated herein by reference in its entirety.
Furthermore, digital beamforming is conventionally performed as a separate process, independent of symbol modulation/demodulation, perhaps even as a separate product from the modem. In addition to the resulting inability to support advanced demodulation techniques with this architecture, the cost of the beamforming function is greater as a stand-alone function, compared to the incremental cost of adding the capability to a modem. The largest cost-component of beamforming is the complex multiplication of each sample for each element with the beamforming weights. Thus, whether stand-alone beamformers merely point in the direction of the signal of interest, or respond more adaptively to dynamic interference conditions by null-steering, such beamformers still lack the ability to be tightly coupled with potential advanced demodulation techniques.
When combined with the modem, there is potential to absorb the complex multiply required for beamforming into computation already taking place for extremely low incremental cost. In U.S. Pat. No. 5,764,187, the disclosure of which is incorporated herein by reference, Rudish et al. disclose an implementation of beamforming using digital direct synthesis (DDS) functions. However, Rudish does not suggest or recognize potential hardware and processing savings in both signal transmission and reception. Specifically, Rudish does not suggest combining demodulation with beamforming or using hardware in a time-shared manner for both transmit and receive. Rudish's architecture is highly parallel and does lend itself to time multiplexing techniques which could potentially reduce hardware requirements.
Accordingly, there remains a need for an efficient, integrated way of incorporating beamforming technology, for both transmit and receive, into base stations or transceiver terminals that process large number of users simultaneously using time division multiple access (TDMA) and/or frequency division multiple access (FDMA) technology. This problem can be extremely computationally burdensome, and architectures for cost-effectively performing this processing are not addressed sufficiently in the prior art.


An illuminated novelty device includes a plurality of light emitting diodes (LEDs). An elongated light bar can be mounted to each of the LEDs. The light bars have a light receiving end and a light emitting end and are mounted to respective LEDs at the light receiving end. The light bars are formed from a light transmissive material. Conductors extend between and connect the LEDs. The LEDs are spaced from one another along the length of the conductors. The LEDs, the elongated light bars and the conductors define an LED assembly. A power source is operably connected to the LED assembly and a switch is operably connected between the power source and the LED assembly. The power source and switch are maintained in a housing. A light transmissive sheath has the LED assembly fitted, at least in part, within it. The sheath has a first end mounted to the housing and a second free end. The LEDs are illuminated by actuation of the switch, and light from the LEDs is transmitted by the LEDs and by the light bars and is visible through the sheath.

The present invention is directed to a novelty device. More specifically, the present invention is directed to a LED illuminated necklace novelty device.
Novelty devices come in all manner, shape and size. Illuminated devices are typically more interesting and attraction-grabbing in that one's eyes are, by instinct, drawn to a lighted object. This is even more so when the lights (illumination) is colored and/or on and off in, for example, a blinking fashion.
Unfortunately, in order to create the greatest and most pleasing attraction, more and brighter lights, different colors, and blinking arrangements are needed. The power requirements of known incandescent lights is quite high. As such, light emitting diodes (LEDs) have come into favor for use in many light required areas, including use in novelty items. However, LEDs can be costly, particularly when the LEDs are manufactured in certain colors.
Another characteristic upon which the cost of an LED is based is the intensity of the LED. That is, high intensity LEDs are typically more expensive than lower intensity LEDs.
In that novelty items are often purchased in bulk or are impulse purchase items, it is important to keep the cost to consumers low. As such, the manufacturing costs must be kept commensurately low, without a loss of quality or aesthetic appeal.
Accordingly, there is a need for a high visual quality LED novelty device. Desirably, such a device is configured to permit long-term use, and provides a high output (highly visible) LED light.


Embodiments are disclosed for providing workout recommendations based on monitored user inputs with a digital design system. In particular, in one or more embodiments, the disclosed systems and methods comprise receiving a series of inputs performed by a user with an application, categorizing each input in the series of inputs into a user interaction type, where each of the plurality of user interaction types is associated with a counter maintaining a detected user input count, determining that a first counter associated with a first user interaction type has exceeded a threshold amount, identifying a first action associated with the first user interaction type, and providing a notification message including information associated with the first action.

Computing devices (e.g., computers, tablets, smart phones) provide numerous ways for users to capture, create, share, view, and otherwise edit numerous types of digital content, including images. However, many creative professionals are forced to terminate their careers prematurely due to various issues caused by their usage of computing devices, including incorrect posture and repetitive motions. In addition, tablets and mobile devices pose various ergonomic challenges when used for long durations.
Existing solutions can track the amount of time that a computing device is active. However, these existing solutions do not consider how the computing device is being used, and thus cannot provide recommendations to address potential negative impacts based on how the computing device is being used, resulting in imprecise recommendations.
These and other problems exist with regards to mitigating health issues related to computing device usage.

Providing recommendations based on monitored user inputs


A hidden type sliding rail assembly auto locking structure for drawer is disclosed comprised of a holder base, a slide, a coil spring member, a hook, a steel spring strip, a locking block, and an actuating block. When the outer sliding rail is moved outwards with the drawer, the actuating block pushes the steel spring strip to force the hook against the slide and to further force the locking block into a side notch and stopped at a stop edge at the holder base to prevent disconnection of the locking block, for enabling the coil spring member to return the drawer to the close position. Except the coil spring member, the holder base holds the other parts on the inside and keeps them from sight without the use of a cover, thereby saving much installation labor and time.

The present invention relates to a sliding rail assembly for drawer and more specifically, to a hidden type auto locking structure used in a sliding rail assembly for drawer, which has a small size that does not require much installation space and, which keeps the parts from sight without the use of a cover.
FIGS. 1 and 2 illustrate a sliding rail assembly auto locking structure used in a sliding rail assembly 9 for drawer. This sliding rail assembly auto locking structure comprises a holder base 91, a spring member 92, a slide 93, and a push block 941 at the inner sliding rail 94. Because the spring member 92 is mounted in a spring chamber 912 inside the holder base 91, the spring member 92 is forced to rub against the inside wall of the spring chamber 912 when it is alternatively compressed and stretched. Therefore, the spring member 92 wears quickly with use. Further, it is difficult to replace the spring member 92 when the spring member 92 is damaged. Further, the slide 93 has two guide rods 931 and 932 for guiding reciprocating motion of the slide 93 in a sliding groove 911 inside the holder base 91. The sliding groove 911 has a downwardly extending front retaining groove portion 9111 for receiving one guide rod 931. When the user arranges the drawer or touches the drawer accidentally, the guide rod 931 of the slide 93 may be forced out of the front retaining groove portion 9111 of the sliding groove 911, causing the slide 93 to be pulled backwards by the spring member 92. In this case, the auto locking structure fails to function normally, and the drawer cannot be pushed to the rear side. U.S. Pat. Nos. 5,207,781 and 5,302,016 and PCT WO 01/8279A2 have same drawbacks. Further, the spring member 93 has one end hooked on one guide rod 931 of the slide 93 and is kept in a oblique manner, i.e., the spring member 93 is not horizontally stretched and compressed, resulting in instability of the reciprocating motion of the slide 93 and short working life of the spring member 93. Further, because the slide 93 vibrates heavily when it is pulled directly by the spring member 92 during its return stroke. Therefore, it is desirable to provide a sliding rail assembly auto locking structure that eliminates the aforesaid drawbacks.
The present invention has been accomplished under the circumstances in view. According to one aspect of the present invention, the hidden type sliding rail assembly auto locking structure is comprised of a holder base, a slide, a coil spring member, a hook, a steel spring strip, a locking block, and an actuating block. When the outer sliding rail is moved outwards with the drawer, the actuating block is stopped against the steel spring strip to force the hook against the slide, and at the same time the locking block is inserted into a side notch of the holder base and stopped at a stop edge at one side of the side notch to prevent disconnection of the locking block from the stop edge upon a vibration of the drawer due to an accidental condition. When the outer sliding rail is moved backwards with the drawer, the actuating block is stopped against the hook to bias the hook and to further move the locking block away from the stop edge of the holder base for allowing the steel spring strip to be forced against the actuating block of the outer sliding rail to push the outer sliding rail and the drawer backwards to the close position, thereby achieving the auto locking effect.
According to another aspect of the present invention, the slide, the hook, the spring member and the locking block are mounted in the holder base. The whole assembly has a small size that does not require much installation space. Further, the holder base does not need a cover to keep the inside parts from sight, thereby saving much installation labor and time.
According to still another aspect of the present invention, the hook does not bias outwards when the drawer is forced accidentally by an external force, and the user can directly push the drawer backwards to force the actuating block over the oblique steel spring strip to the position between the steel spring strip and the hook, and therefore the drawer is accurately returned to the close position.
According to still another aspect of the present invention, the spring member is provided outside the holder base. When the spring member is stretched or compressed, the spring member does not rub against the outside wall of the holder base. Therefore, the spring member is durable in use and replacement of the spring member can easily be performed.
According to still another aspect of the present invention, the hook is pivoted to the slide, and the slide is connected to the spring member. This arrangement assures smooth reciprocation of the slide in the holder base. Further, a hydraulic cylinder is used to buffer the return stroke of the slide, eliminating noise.

Hidden type sliding rail assembly auto locking structure for drawer


A bypass valve-delay valve assembly for an electric-hydraulic braking system of an electrically driven vehicle which includes a bypass valve section in which the hydraulic braking circuit ducts are obstructed by a solenoid operated valve activated by an electric signal generated by brake pedal depression, and a delay valve section in which the hydraulic fluid is obstructed by a delay valve arranged in a regulator piston whose maximum stroke equals the pressure corresponding to the maximum energy recovery performance generated by the electric drive motors' braking action. Pressure exceeding the maximum energy recovery performance of the drive motors causes the delay valve to open adding hydraulic braking to the electric drive motor braking.

1. Field of the Invention
This invention refers to a bypass valve-delay valve set for braking systems. More specifically, this invention refers to a bypass valve-delay valve assembly for a mixed electric-hydraulic braking system to be fitted to electrically driven vehicles.
2. Description of the Prior Art
For electrically driven vehicles such as, for example, ecological vehicles for cities and the like, mixed braking systems are currently being studied and applied in which, together with the hydraulic braking circuits of the traditional type, electrical braking devices are fitted whose operation, with the exclusion of conditions at speeds below that of the presence of electrical torque, takes precedence over the former. This is to fully recover the energy output by the electric motors at the time when a request for braking is made, and to exploit it for recharging the batteries, which allows the range of the vehicles to be increased economically.
The hydraulic circuits are fitted with bypass valves and hydraulic valves so that they can work in this way. The function of the bypass valves is to exclude said hydraulic circuits when the electrical braking systems can be exploited to the full and that of the delay valves is to also start up the hydraulic braking, in a modulated way, in addition to he electrical braking action when same has reached its maximum capacity. See the applicant's co-pending application entitled "Braking System For Electrically Drive Vehicles ", U.S. Ser. No. 07/919, filed Jul. 23, 1992. These two types of valve are generally separate and bulky.

Bypass valve-delay valve assembly for braking systems


The invention provides a method for imparting durable press properties to a cotton-containing textile which avoids the use of formaldehyde and the problems associated therewith, which method comprises treating a textile with an aqueous finishing agent solution comprising at least one acetal of glutaraldehyde and at least one acidic catalyst and optionally contains a silicone softener and/or a pH-maintaining additive such as sodium perborate.

1. Field of the Invention
The present invention is directed to a method of imparting durable press properties to cotton textiles without using formaldehyde. More particularly, the invention is directed to a method of treating cotton textiles to impart durable press properties using acetals of glutaraldehyde.
2. Prior Art
Present-day textile finishing treatments that impart durable press properties use formaldehyde or form formaldehyde in situ as one of the ingredients to make durable press finishes. This formaldehyde can be released during the treatment of textiles or during storage and manufacture of garments made from the treated textile. Recently, there has been increasing concern over safety and health hazards associated with the use of formaldehyde. It has been determined that exposure to formaldehyde on textiles or in the air can cause allergic reactions in some persons. It has further been suggested that formaldehyde may be a carcinogen.
Efforts are being made to develop durable press treatments which eliminate formaldehyde or formaldehyde-based compounds in textile treatment. U.S. Pat. Nos. 4,269,603 and 4,472,167 disclose formaldehyde-free durable press finishes based on glyoxal chemistry with cellulose. Other dialdehydes, for example, glutaraldehyde, were found to be effective as cellulose crosslinking reagents (Japanese Publication No. 48061796 and European Patent Application No. 360,248,A2). However, the use of glutaraldehyde requires special handling precautions due to the presence of irritating vapors.
Dimethoxy-, diethoxy-, and diisopropoxy- pyrans have been reported by J. G. Frick, Jr., and R. J. Harper, Jr., "Acetals as Crosslinking Reagents for Cotton," Journal of Applied Polymer Science, Vol. 29, 1433-1447(1984). Since these symmetrical dialkoxypyrans are insoluble in water, they require an organic solvent for incorporating them into fabric treating compositions.
Surprisingly, it has been discovered that cotton textiles can be treated with an aqueous solution comprising an acetal of glutaraldehyde, without the disadvantage of using an organic solvent, to produce finished fabrics or textiles having durable press properties such as good dimensional stability, tensile retention, and crease resistance, as well as enhanced softness.

Method of imparting durable press properties to cotton textiles without using formaldehyde

Union Carbide Chemicals & Plastics Technology Corporation


Disclosed is a method for transmitting data comprised of bits with higher priority and bits with lower priority output from a coder, using a high-order modulator in which a bit stream comprised of at least 3 bits represents one symbol and includes a first bit part with higher reliability and a second bit part with lower reliability. The method comprises modulating the bits with higher priority and the bits with lower priority such that the bits with higher priority are mapped to the first bit part and the bits with lower priority are also mapped to the first bit part at initial transmission; and modulating the bits with higher priority and the bits with lower priority such that the bits with higher priority are mapped to the second bit part and the bits with lower priority are mapped to the first bit part at retransmission.

1. Field of the Invention
The present invention relates generally to an apparatus and method for transmitting and receiving data in a CDMA mobile communication system, and in particular, to a data transmission/reception apparatus and method for adjusting the reliability of data bits before transmission and weight-combining received data bits according to the reliability of received data bits to improve system performance.
2. Description of the Related Art
In a communication system, it is impossible to receive transmission signals without any distortion and noises mixed therein. In particular, a mobile communication system transmitting and receiving signals via a wireless network is more susceptible to the distortion and noises, compared with a wired communication system.
For this reason, there have been proposed various methods of reducing the influence of the distortion and noises on the mobile communication system. For example, in order to reduce a bit error rate from 10−2 to 10−3 in an AWGN (Additive White Gaussian Noise) environment using the typical modulation technique and coding technique, a low signal-to-noise ratio (SNR) of about 1 dB to 2 dB is required. On the other hand, in order to obtain the same results in a multipath fading environment, it is necessary to increase the signal-to-noise ratio to about 10 dB. However, a method of increasing transmission power in order to increase the signal-to-noise ratio for a reduction in the bit error rate may undesirably decrease the entire system performance. Therefore, a technique for effectively reducing or removing the influence of fading, i.e., the influence of distortion or noises, without additional power or a loss of bandwidth in both a UE (User Equipment) and a Node B is very important to the mobile communication system. One of the effective technique for this is a channel interleaving technology combined with an error control coding technique.
The channel interleaving technology interleaves transmission data bits before transmission to disperse the transmission data from a portion of a signal where data bits may be possibly damaged to different places instead of concentrating the portion on one place. That is, the interleaving technology prevents a burst error by allowing adjacent bits to be randomly affected by fading.
Meanwhile, codes used for the error control coding technique are divided into a memoryless code and a memory code. The memoryless code includes a linear block code, while the memory code includes a convolutional code and a turbo code. Further, a device for performing coding by the error control coding technique is called a "channel coder".
In particular, a future mobile communication system requires reliable transmission of high-speed multimedia data, so it needs a more powerful channel coding technique. A channel coding technique using the turbo code shows performance nearest to the Shannon limit with respect to the bit error rate (BER) even in the low signal-to-error ratio. An output of a channel coder using the turbo code can be divided into systematic bits and parity bits. Here, the "systematic bits" refer to actual information data bits to be transmitted, while the "parity bits" refer to bits added to help a receiver correct a possible transmission error. However, even the error control coded signals cannot overcome a possible burst error occurring in the systematic bits or the parity bits.
Of course, the systematic bits and the parity bits output from the channel coder have different priorities. In other words, in the case where errors occur in transmission data at a given rate, it is possible to perform more correct decoding when the errors occur in the parity bits, compared with when the errors occur in the systematic bits. The reason is because, as stated above, the systematic bits are the actual information data bits, while the parity bits are the bits added to assist the receiver to correct transmission errors in decoding process.
The SMP (Symbol Mapping method based on Priority) technique can increases system performance by decreasing the probability that errors will occur in the systematic bits having higher priority than the parity bits. The SMP technique uses two interleavers at an output stage of the channel coder to map the systematic bits and the parity bits to the bits having different reliabilities. That is, an existing transmitter not employing the SMP technique interleaves the systematic bits and the parity bits together without discrimination before transmission. However, a transmitter employing the SMP technique separately interleaves the systematic bits and the parity bits, and then maps during modulation the bits having higher priority to a bit position having higher reliability and the bits having lower priority to a bit position having lower reliability. As a result, when transmitted by the SMP technique, the bits having higher priority have a lower bit error rate than the bits having lower priority, contributing to an increase in an error correcting capability by the receiver during decoding process.
FIG. 1 illustrates a signal constellation diagram for 16QAM (16-ary Quadrature Amplitude Modulation) modulation, and FIG. 2 illustrates a signal constellation diagram for 64QAM (64-ary Quadrature Amplitude Modulation) modulation.
Referring to FIG. 1, 16QAM-modulated symbols are each comprised of 4 bits, and have a reliability pattern [H,H,L,L], where H represents a bit position having higher reliability and L represents a bit position having lower reliability. That is, the leading two bits have higher reliability and the following two bits have lower reliability.
Referring to FIG. 2, 64QAM-modulated symbols are each comprised of 6 bits, and have a reliability pattern [H,H,M,M,L,L], where H represents a bit position having higher reliability, M represents a bit position having medium reliability and L represents a bit position having lower reliability.
Therefore, it is possible to map the interleaved systematic bits and parity bits to the bit positions with higher reliability, the bit positions with medium reliability and the bit positions with lower reliability according to systematic bits and priority bits priorities. Based on this, the SMP technique maps the systematic bits to the bit positions with higher reliability, resulting in an improvement in frame error rate (FER) during transmission. Here, as to the reliability, in a process of modulating one symbol by the transmitter, the symbol expressing two bits in a macro region like the left/right quadrants or upper/lower quadrants on the X/Y-axis of FIGS. 1 and 2 is said to have "higher reliability", and the symbol expressing two bits in a micro region is said to have "lower reliability".
FIG. 3 illustrates a structure of a transmitter constituting an HSDPA (High-Speed Downlink Packet Access) wireless communication system employing the SMP technique.
Referring to FIG. 3, tail bits are added to transmission data in the tail bit generator 111. transmission data is separated into systematic bits and parity bits by a channel coder 112, and then subjected to rate matching through a rate matcher 114. The rate-matched systematic bits and parity bits are provided to a distributor 116. The distributor 116 distributes the systematic bits with higher priority to a first interleaver 118 and the parity bits with lower priority to a second interleaver 120. The systematic bits interleaved by the first interleaver 118 and the parity bits interleaved by the second interleaver 120 are output in series through a parallel-to-serial converter 122, and then provided to a modulator 124. The modulator 124 maps before transmission to the receiver the systematic bits to the bit positions having higher reliability and the parity bits to the symbol positions having lower reliability. The transmitter of FIG. 3 is under the control of controller 126.
As described above, the SMP technique maps the systematic bits having higher priority to the bit positions with higher reliability, thus contributing to an improvement in FER during high-speed downlink packet transmission.
Meanwhile, since the future mobile communication system needs reliable transmission of high-quality, high-efficiency, high-capacity and high-speed multimedia data, it is necessary to link the SMP technique to the high-speed downlink packet transmission. However, when the SMP technique is employed in a system using a H-ARQ (Hybrid Automatic Repeat Request) technique, it is assumed that the bits having higher priority are mapped to the bit positions having higher reliability even at retransmission. In this case, the effect of a coding gain may be reduced, because decoding performance of a turbo decoder is improved when its input bits have a homogeneous LLR (Log Likelihood Ratio). The present invention provides a technique capable of obtaining both the coding effect and a diversity gain, and also capable of using the characteristic of the turbo decoder, in a system using the H-ARQ technique.

Apparatus and method for transmitting and receiving data in a CDMA mobile communication system


A system including a carrier having a plurality of receptacles configured to receive rechargeable, removable battery packs, an AC power input connector for connecting to an AC power supply, a power output connector, a discharge/charge mode switch for switching between (1) a charging mode of operation that charges the battery packs using electrical power input through at least one of the power input connectors and (2) a discharging mode of operation that outputs electrical power from the battery packs through the power output connector, the charge/discharge control module controlling a plurality of charging switches to provide a charging current to the battery packs and an inverter electrically connected to the power output connector for providing an AC output signal at the power output connector.

Various types of electric power tools are commonly used in construction, home improvement, outdoor, and do-it-yourself projects. Conventional power tools generally fall into two categories—corded tools that are powered by an AC power source, e.g., an AC mains line, and cordless tools that are powered by one or more DC power sources, e.g., a rechargeable battery.
Corded power tools generally are used for heavy duty applications that require high power and/or long runtimes, such as heavy duty sawing, heavy duty drilling and hammering, and heavy duty metal working. However, as their name implies, corded tools require the use of a cord that can be plugged into an AC power outlet. In many applications, such as on construction sites, it is not convenient or practical to find an AC power outlet and/or AC power must be generated by a generator, e.g. gas powered generator.
Cordless power tools generally are used for lighter duty applications that require low or medium power and/or short runtimes, such as light duty sawing, light duty drilling, and fastening. As cordless tools tend to be more limited in their power and/or runtime, they have not generally been accepted by the industry for all applications. They are also limited by weight since the higher capacity batteries tend to have greater weight, creating an ergonomic disadvantage.
Generally, conventional power tool battery packs may not be able to run conventional corded power tools or other corded electrical devices, while untransformed AC power may not be able to be used to run cordless power tools. Further, the battery packs for cordless power tools may require frequent recharging, may be expensive to purchase, and may be cumbersome to manage on a large construction site.


A method of fabricating a liquid crystal display panel, includes providing a mother substrate having a plurality of display panel regions of different sizes, and forming a plurality of display panel substrates each formed at one of the display panel regions, parts of the display panel substrates to be rubbed being aligned to one side of the mother substrate where rubbing is to start.

1. Field of the Invention
The present invention relates to a method of fabricating a liquid crystal display device, and particularly, to a method of fabricating a liquid crystal display panel capable of preventing rubbing from being abnormally made due to a step difference by disposing liquid crystal display panels of various sizes with their pixel parts made to correspond to one side.
2. Description of the Related Art
In recent information society, a display is considered to be more and more important as a visual information transmission media. In order to occupy a major position in the future, the display has to satisfy a low power consumption characteristic, a thin and light characteristic, a high picture quality characteristic, etc. Because a liquid crystal display (LCD) device (a major product of a flat panel display (FPD)) is equipped with not only functions to satisfy said conditions but also with a mass production characteristic, various kinds of new products using the LCD device are rapidly being invented, and the LCD device has become a core component which can replace the existing cathode ray tube (CRT).
A general liquid crystal display device displays an image by controlling light transmittance by using an electric field. To this end, the liquid crystal display device includes a liquid crystal display panel including a driving circuit part, a backlight part installed at a lower portion of the liquid crystal display panel, a mold-frame for supporting the backlight part and the liquid crystal display panel, and a case.
Hereinafter, a general liquid crystal display panel will now be described in detail with reference to FIG. 1.
FIG. 1 is a plan view roughly showing a structure of a general liquid crystal display panel.
As shown therein, the liquid crystal display panel 10 largely includes an array substrate 20, a color filter substrate 30 and a liquid crystal layer formed between the array substrate 20 and the color filter substrate 30.
The array substrate 20 includes a plurality of gate lines 21 and a plurality of data lines 22 that define a plurality of pixel regions 25 by being arranged vertically and horizontally on the substrate 20, a plurality of thin film transistors (TFTs) each formed at an intersection of the corresponding gate line 21 and the corresponding data line 22 and a plurality of pixel electrodes formed in the pixel regions 25.
Here, the array substrate 20 has a region along a long side and a region along a short side that protrude beyond the color filter substrate 30 so that the driving circuit unit for driving the liquid crystal display panel is positioned thereto. Particularly, a gate pad part 24 is formed in the region along the short side region of the array substrate 20, and a data pad part 23 is formed in the region along the long side region of the array substrate 20.
In addition, the gate pad part 24 supplies a scanning signal, which is supplied from a gate driving circuit part (not shown), to the gate line 21 of each pixel region 25 of the pixel part, an image-displayed region. The data pad part 23 supplies image information, which is supplied from a data driving circuit part (not shown), to a data line 22 of the pixel region 25.
Even though it is not shown in FIG. 1, a color filter for implementing colors and a common electrode facing the pixel electrodes formed on the array substrate 20 are formed at an image-displayed region of the color filter substrate 30.
The array substrate 20 and the color filter substrate 30 constructed as above face each other and are attached by a sealant (not shown) formed along an outer edge of the image-displayed region. The attachment of the two substrates is made through an attachment key (not shown) formed at the array substrate 20 or the color filter substrate 30.
This process of fabricating the liquid crystal display device can be divided into an array substrate process for forming a switching device on an array substrate, a color filter substrate process for forming a color filter on a color filter substrate and a cell process. The process for fabricating the liquid crystal display device will now be described with reference to FIG. 2.
First, a plurality of gate lines and a plurality of data lines are arranged vertically and horizontally on a transparent insulation substrate such as glass to thereby define a plurality of pixel regions, and a thin film transistor (a switching element) connected to the corresponding gate line and the corresponding data line, is formed at each pixel region (S101). In addition, a pixel electrode connected to the corresponding thin film transistor and driving a liquid crystal layer as a signal is applied thereto through the thin film transistor, is formed at each pixel region through the array substrate process (S101).
In addition, a color filter including sub-color filters (R, G, B) for implementing colors, a black matrix for isolating the sub color filter from other sub color filters and cutting off light transmitted by a liquid crystal layer and a transparent common electrode corresponding to the pixel electrode are formed on the color filter substrate by the color filter substrate process (S104).
Then, alignment layers are applied over the array substrate and the color filter substrate, respectively, and then the alignment layers are rubbed in order to provide an alignment controlling force or a surface anchoring force (i.e., pretilt angle and alignment direction) to the liquid crystal molecules of the liquid crystal layer formed between the array and color filter substrates (S102, S105).
Next, spacers for maintaining a uniform cell gap are dispersed onto the array substrate, a sealing material is applied along an outer edge portion of the color filter substrate, and then the array substrate and the color filter substrate are attached by applying pressure thereto (S103, S106, S107).
At steps S101 and S104, the array substrate and the color filter substrate are formed respectively on large-sized mother glasses (i.e., mother substrates). Namely, a plurality of panel regions are formed on the large-sized mother substrate and a plurality of thin film transistors which are switching devices or a color filter layer are respectively formed at the panel regions. Therefore, in order to fabricate individual liquid crystal display panels, the mother substrates that are attached at step S107 are cut and processed to form individual liquid crystal display panels (S108).
Thereafter, a liquid crystal material is injected into each of the individual processed liquid crystal display panels through a liquid crystal injection opening, then the liquid crystal injection opening is encapsulated to form the liquid crystal layer, and finally, the injected liquid crystal display panel is tested, thereby completing the liquid crystal display panel (S109, S110).
In fabricating such a liquid crystal display panel, in order to improve productivity, a method of simultaneously disposing a plurality of unit liquid crystal display panels on a large-sized mother substrate is generally being used.
FIG. 3A is a view showing that a plurality of liquid crystal display panel regions in one same size are disposed on a mother substrate, and FIG. 3B is a view showing that liquid crystal display panel regions in one bigger same size are disposed on the mother substrate compared to the panel regions of FIG. 3A.
FIG. 3A shows a case that six liquid crystal display panel regions are disposed at regular intervals, considering the size of the mother substrate and the size of the liquid crystal display panels to be formed. That is, as shown therein, six first liquid crystal display panel regions 10a having the same size are disposed on the mother substrate 40. A TFT array substrate or a color filter substrate is formed at each region 10a.
Once the mother substrate having the array substrates and the mother substrate having the color filter substrates are attached to each other to form first liquid crystal display panels and then processed to separate the first liquid crystal display panels, leaving behind a region of the mother substrates where the liquid crystal display panels are not formed and which is discarded after the separation. Accordingly, preferably, the first liquid crystal display panels are disposed to minimize the region where the liquid crystal display panels are not formed and to maximize the number of liquid crystal display panel regions provided on the mother substrates.
Here, each first liquid crystal display panel region 10a having the array substrate or the color filter substrate has to pass through a rubbing process in order to provide an alignment controlling force to liquid crystal molecules. In the drawing, a case that the rubbing is made in an arrow direction regardless of a driving mode of a liquid crystal display panel (i.e., Twisted Nematic; TN) mode, an In-Plane Switching (IPS) mode or a S (super)-IPS mode, is depicted.
For an additional reference, a liquid crystal display panel is a display device for displaying an image by controlling the amount of light transmitted by a liquid crystal layer. The transmission level is controlled by an initial alignment state of the liquid crystal molecules having a double refraction property and by driving the liquid crystal molecules according to a signal. Driving modes of a liquid crystal display panel are determined by an initial alignment direction and the method of driving the liquid crystal molecules. Namely, because liquid crystal display panels with different modes have different initial alignment directions, the directions of the alignment layers have to be different.
Therefore, panel regions with different modes, which are formed on a substrate (array substrate and color filter substrate), have to be rubbed in different directions.
In addition, because a main viewing angle of the fabricated first liquid crystal display panel is determined according to a direction of rubbing made on the mother substrate 40, the panel regions 10a have to be disposed in the same direction in order to simultaneously fabricate the plurality of liquid crystal display panels having the same main viewing angle.
In case of fabricating bigger-sized liquid crystal display panels on the same mother substrate of FIG. 3A, only two second liquid crystal display panel regions 10b of the same size can be disposed on each mother substrate 40 as shown in FIG. 3B, and a region of the mother substrate 40 where the second liquid crystal display panel regions 10b are not disposed has to be discarded subsequently.
Accordingly, as the size of the liquid crystal display panels increases, the efficiency of using the mother substrate is deteriorated, which deteriorates productivity and increases product cost.
Here, when the second liquid crystal display panel regions 10b having the array substrate/color filter substrate are disposed as shown in the drawing, rubbing has to be made in a direction perpendicular to the direction of rubbing depicted in FIG. 3A. The arrangement direction of the array substrates and the color filter substrates on the mother substrates are made without regard to their pixel parts.
In general, a plurality of liquid crystal display panels (e.g., four, six, eight or sixteen liquid crystal display panels) are formed on a mother substrate and a technique for forming the plurality of liquid crystal display panels on the mother substrate are considered to be a main factor that determines fabrication efficiency of the liquid crystal display panel. Accordingly, researches on the techniques for efficiently using a mother substrate are actively ongoing, and these techniques affect competitiveness of liquid crystal display device manufacturers.
However, the size of the mother substrate 40 is standardized and depends on the size of the liquid crystal display panel being fabricated. Namely, the standard size of the mother substrate is set so that the mother substrate has an area to efficiently fabricate the liquid crystal display panels. As such, as shown in FIG. 3B, if a liquid crystal display panel with a different size is fabricated on the standard sized mother substrate, a large region of the mother substrate remains unused. This problem may be solved by forming the liquid crystal display panel on a mother substrate with a standard sized corresponding to the liquid crystal display panel to be made. But, there is no mother substrate that is standardized according to the liquid crystal display panel to be made, so the liquid crystal display panel must be formed on a mother substrate with a different standard as shown in FIG. 3B. Accordingly, a large portion of the mother substrate remains unused and the unused region of the mother substrate is discarded, thereby increasing the fabrication cost of the liquid crystal display panel.
In addition, if a plurality of liquid crystal display panels are disposed on the mother substrate, randomly (without any regular directionality) in order to improve the efficiency of using the mother substrate, the surface of the panel may be easily damaged during a rubbing process. That is, if a rubbing is made on the substrate on which a plurality of liquid crystal panels are disposed randomly, a blotted region may be generated due to a step difference because positions where rubbing is started and completed are varied according to the liquid crystal display panels.

Method of fabricating liquid crystal display panels having various sizes


A system for connecting a portable information equipment and an extension telephone, comprises: an extension telephone connecting device for connecting the portable information equipment to an extension telephone system after authentication through a virtual private network (VPN); and a Voice over Internet Protocol (VoIP) connecting device for connecting the portable information equipment connected to the extension telephone system to the extension telephone connected to the extension telephone system by VoIP. This system enables a temporary staff to make a call from outside to an extension telephone system in a dispatched company while maintaining security.

1. Field of the Invention
The present invention relates to a system and method for connecting a portable information equipment and an extension telephone, which connect a portable information equipment such as a personal digital assistance (PDA) to an extension telephone on the company premises or the like.
2. Description of the Related Art
Recent popularity of company business outsourcing has increased scenes in which temporary staffs work at dispatched companies. There is a case in which the temporary staff must make a call to an extension telephone of his/her company for business connection from inside/outside the dispatched company.
There are following conventional art documents relating to the present invention:                Japanese Patent Application No. 2001-265584,        Japanese Patent Application No. 2001-331389,
"Point-Illustrated VPN/VLAN Textbook" by Multimedia Communication Study Group under the editorship of HARUKI KORETOMO, issued by ASCII Publishing Company, Sep. 11, 1999,                "Mastering of IP Telephone" Network Magazine, pp. 137 to 159, issued by ASCII Publishing Company, November 2002.
However, the following disadvantages have been pointed out for telephone usability of the staff dispatched to the company.
(1) A portable telephone or a public telephone must be used to make a call to the dispatched company from the outside. However, a charge for such a call is high. In addition, the temporary staff does not always carry a portable telephone.
(2) The temporary staff cannot use a telephone system of the dispatched company even inside the company.
(3) The temporary staff cannot use telephone system customer information of the dispatched company from the outside.
(4) The dispatched company feels insecure when the temporary staff is permitted to use the company telephone.
Thus, objects of the present invention are to provide a system and method for connecting portable information equipment and an extension telephone, which enable use of an extension telephone of a dispatched company by a temporary staff while maintaining security.

System and method for connecting portable information equipment and extension telephone


A front transparent conductor assembly and, in one embodiment, a photovoltaic cell, includes at least three transparent conductor layers. In one embodiment, first and second transparent conductors comprised of SnO2 are positioned above and below a third transparent conductor comprised of ZnO2. In one embodiment, the second transparent conductor layer is significantly thicker than either the first or third transparent conductor layers. In one embodiment of a photovoltaic cell incorporating such an assembly, a sealing layer of SiO2 is interposed between a superstrate and the first transparent conductor. In another embodiment, first and second intermediate layers of ZnSnO3 are incorporated into the assembly, with the first intermediate layer interposed between the first and second transparent conductors and with the second intermediate layer interposed between the second and third transparent conductors.

Prior art thin-film amorphous silicon (a-Si) photovoltaic cells are built on a glass substrate as a series of layers. When the finished cell is operating, the glass substrate becomes a "superstrate"—the top layer through which the sunlight enters. Some of a solar cell's film layers are active (they participate in the actual conversion of light to electricity) and some are passive (they protect the active layers or the substrate). The first active layer deposited (closest to the glass) is usually a transparent conductive layer, such as tin oxide (SnO2). SnO2 is a transparent conductor that conducts current and voltage from the silicon PIN diode deposited thereabove (but located therebelow during operation) that converts sunlight into electricity. Because it is transparent, unlike ordinary conductors like aluminum, the SnO2 layer allows the sunlight to travel from the glass into the silicon.
In addition to its ability to transmit light and conduct electricity, SnO2 also has several other key advantages. It has good adhesion to glass. It also is very resistant to degradation by chemical attack in humid environments. In addition, SnO2 has the right value of work function to make a good contact to the p-layer of the silicon PIN diode that converts the sunlight to electricity. For soda-lime glass of the type typically used in the fabrication of glass superstrates for amorphous silicon photovoltaic cells, the adhesion, electrical properties and optical properties are often improved by coating the soda-lime glass with a very thin layer of SiO2 or SiOxCy that acts as a barrier to keep sodium from the glass away from the SnO2.
However, SnO2 has several disadvantages. First, its resistance is higher and its transparency is not as good as several other well known transparent conductors not used in amorphous silicon photovoltaic cells, such as ZnO. ZnO is inexpensive and abundant, but has several serious disadvantages as compared to SnO2. ZnO tends to be hygroscopic. It readily absorbs water and is easily attacked chemically in a humid environment. When applied to the surface of glass, for a variety of reasons, it adheres poorly and readily peels off the surface of the glass. In addition, ZnO is a soft material that is easily scratched and damaged mechanically.
ZnO has been demonstrated as a possible front conductor for a-Si photovoltaic cells in the laboratory. Tests have shown that the higher transparency and lower resistivity of ZnO produce, in a laboratory setting, photovoltaic cells with higher efficiency. However, the prior art fails to disclose the development of a production process for a-Si photovoltaic cells for use in the field with ZnO as the front conductor that can pass the usual reliability tests without the ZnO front conductor failing.
The present invention is directed to such a cell and a method therefor.

Front transparent conductor assembly for thin-film photovoltaic cells and method