A method of making a semiconductor device includes forming a recess in a compound semiconductor substrate using a patterned insulating film on a surface of the substrate, implanting dopant ions at the bottom of the recess to form a channel region, and depositing a refractory metal film. The refractory metal film is etched, using a resist pattern, to form a gate electrode and additional dopant ions are implanted to form relatively highly doped regions intersecting the channel region. Very highly doped regions are formed my implantation, after removing the insulating film, using the gate electrode and remainder of the resist mask as an implantation mask. After stripping the resist, annealing to activate the implanted ions, and depositing a passivating film on the substrate and gate electrode, source and drain electrodes are formed. The field effect transistor thus produced has a high breakdown voltage, improved reliability, a highly controlled pinch-off voltage, and improved transconductance and operating speed.

In field effect transistors (hereinafter referred to as FETs) employing compound semiconductors, n type layers are usually used as active layers, such as channel layers. Hereinafter the channel is called an n layer. In addition, a layer disposed beneath the channel layer and containing a dopant impurity producing a conductivity type opposite the conductivity type of the channel layer, i.e., n type, is a p type layer. This p type layer is called a buried p layer.
In conventional planar type compound semiconductor FETs, in order to reduce the source resistance and the drain resistance and increase the transconductance, high dopant concentration layers (hereinafter referred to as n.sup.+ layers) having an n type dopant concentration higher than that of the n layer are arranged adjacent to both sides of the n layer directly under a gate electrode. Those n.sup.+ layers are produced by ion implantation using the gate electrode as a mask, i.e., self-alignedly with the gate electrode. Generally, a refractory metal is employed for the gate electrode because the substrate after the ion implantation is annealed to activate the implanted ions. In this structure, however, the capacitance between the gate electrode and the n.sup.+ layers becomes an obstacle to high-speed operation of the FET. In addition, when the gate length is less than 1.0 .mu.m, the short channel effect occurs. Therefore, in recent years, LDD (Lightly Doped Drain) FETs have been employed, in which intermediate dopant concentration layers (hereinafter referred to as n' layers) having a dopant concentration higher than the dopant concentration of the n layer and lower than the dopant concentration of the n.sup.+ layers are interposed between the n layer and the n.sup.+ layers. FIG. 25(a) shows an example of the prior art planar LDD-FET. In the figure, reference numeral 1 designates a compound semiconductor substrate. An n type channel layer 2 is disposed on a center part of the substrate 1. N' layers 3 are disposed at opposite sides of and in contact with the n layer 2. N.sup.+ layers 4 are disposed contacting the n' layers 3. A refractory metal gate electrode 5a is disposed on the n layer 2, and ohmic electrodes 7a and 7b are disposed on the n.sup.+ layers 4. Reference numeral 6 designates an insulating film.
FIGS. 26(a)-26(g) illustrate process steps in a method of fabricating the LDD-FET shown in FIG. 25(a).
Initially, as illustrated in FIG. 26(a), a resist pattern 10 is formed on the compound semiconductor substrate 1. Using the resist pattern 10 as a mask, n type dopant ions are implanted into the substrate to a prescribed depth, forming an n layer 2. The pinch-off voltage V.sub.p of the FET is controlled by the implanted depth that depends on the accelerating energy and the dose. For example, when Si ions are implanted at an accelerating energy of 70 keV and a dose of 7.times.10.sup.12 cm.sup.-2, the pinch-off voltage V.sub.p is -2.0 V.
In the step of FIG. 26(b), after removal of the resist pattern 10, a thin refractory metal film 5 is deposited on the substrate, and a gate pattern 11 comprising a resist is formed on a portion of the refractory metal film 5. Preferably, WSi, WSiN, WN, or TiW is employed as the thin refractory metal film 5 as described in Japanese Published Patent Application No. Sho. 63-142681.
In the step of FIG. 26(c), using the resist pattern 11 as a mask, the thin refractory metal film 5 is etched by reactive ion etching (hereinafter referred to as RIE), forming a gate electrode 5a. When a gas mixture of CF.sub.4 +O.sub.2 or SF.sub.6 +CHF.sub.3 is employed for the RIE, the refractory metal film 5 is vertically etched without pattern-shifting from the resist pattern 11.
In the step of FIG. 26(d), after removal of the resist pattern 11, a resist pattern 12 is formed on the substrate. Using the resist pattern 12 and the refractory metal gate electrode 5a as masks, ion implantation is carried out to form the n' layers 3. The depth of the n' layers 3 from the surface of the substrate is approximately equal to the depth of the n layer 2.
After removal of the resist pattern 12, as illustrated in FIG. 26(e), an insulating film 13 is deposited on the substrate and etched back leaving portions on the both sides of the refractory metal gate electrode 5a. Hereinafter, the left portions 13 are called side walls. Preferably, an SiO.sub.2 film is used as the insulating film 13, and the etchback is carried out by RIE using a gas mixture of CHF.sub.3 +O.sub.2.
Thereafter, as illustrated in FIG. 26(f), a resist pattern 14 is formed on the substrate and, using the resist pattern 14, the refractory metal gate electrode 5a, and the side walls 13 as masks, ion implantation for producing the n.sup.+ layers 4 is carried out. The depth of the n.sup.+ layers 4 is approximately equal to the depth of the n layer 2.
After removal of the resist pattern 14 and the side walls 13, annealing is performed at about 800.degree. C. to activate the ions in the n layer 2, the n' layers 3, and the n.sup.+ layers 4. Finally, the insulating film 6 and the source and drain ohmic electrodes 7a and 7b are produced to complete the structure shown in FIG. 26(g). The annealing may be performed twice, i.e., first annealing for activating the n layer 2 and second annealing for activating the n' and n.sup.+ layers 3 and 4. In the step of implanting the n type dopant shown in FIG. 26(a), not only the n type dopant but also a p type dopant may be implanted to a depth exceeding the depth of the n layer 2 to form a buried p layer 31 under the active layers 2, 3, and 4 as shown in FIG. 25(b). This buried p layer 31 suppresses the short channel effect in an FET having a gate length less than 1.0 .mu.m. An FET having such structure is described by M. Noda et al. in IEEE Transactions on Electron Devices, Vol. 39 (1992), p.757. This FET is called a buried p layer LDD-FET (hereinafter referred to as BPLDD-FET). In this structure, the depletion layer is thinner at the interface between the n.sup.+ layer 4 and the buried p layer 31 than at interface between the n layer 2 and the buried p layer 31. Likewise, the capacitance is larger at the former interface than at the latter interface. Although the buried p layer 31 under the n.sup.+ layer 4 does not contribute to suppressing the short-channel effect, the capacitance at the interface between the p layer 31 and the n.sup.+ layer 4 reduces the operating speed of the FET. So, the buried p layer 31 may be produced by implanting the p type dopant after masking the n.sup.+ layers 4 with a resist pattern to prevent the p type dopant from being implanted into regions under the n.sup.+ layers. In this case, however, the resist pattern is not formed self-alignedly with the n.sup.+ layers 4.
In the FET fabricated as described above, since ion implantation is employed for the formation of the n layer 2, the controllability of the pinch-off voltage V.sub.p is good. In addition, since the gate electrode 5a comprises a refractory metal, the reliability of the contact between the gate electrode 5a and the n layer 2 is high. However, since current flows in the vicinity of the surface of the active layer, the drain breakdown voltage is low.
Meanwhile, FIG. 27 shows another example of a prior art compound semiconductor FET disclosed by B. Turner in Gallium Arsenide edited by M. J. Howes and D. V. Morgat, 1985, John Wiley & Sons Ltd, Chapter 10, p.377. This FET comprises a compound semiconductor substrate 1, an n layer 2 disposed on the substrate 1, an n.sup.+ layer 4 disposed on the n layer 2, a recess having a bottom within the n layer 2, and a low resistance metal gate electrode 8 disposed in the recess, and ohmic electrodes 7a and 7b disposed on the n.sup.+ layer 4 at opposite sides of the gate electrode 8.
A fabricating method of the FET with the recess structure shown in FIG. 27 is illustrated in FIGS. 28(a)-28(c). Initially, as illustrated in FIG. 28(a), on the compound semiconductor substrate 1 having the n layer 2 and the n.sup.+ layer 4, the ohmic electrodes 7a and 7b are produced contacting the n.sup.+ layer 4. Then, a resist film 17 having a prescribed opening pattern is formed on the substrate.
Thereafter, as shown in FIG. 28(b), using the resist film 17 as a mask, the n.sup.+ layer 4 and the n layer 2 are wet-etched with tartaric acid to form a recess, followed by deposition of a low resistance metal film 8. Preferably, Ti/Au or Ti/Al is employed for the low resistance metal film 8.
In the step of FIG. 28(c), the resist film 17 is dissolved with an organic solvent to lift-off unnecessary portions of the low resistance metal film 8 on the resist film 17, thereby producing the low resistance metal gate electrode 8. Since the same resist pattern 17 is used for the formation of the recess and the formation of the gate electrode, the gate electrode is formed self-alignedly with the recess.
In the FET with the recess structure fabricated as described above, current flows in a deeper region in the active layer than in the above-described BPLDD-FET, so that current concentration at the drain edge is reduced and the drain breakdown voltage is high. However, since it is difficult to accurately control the etching of the recess, the controllability of the pinch-off voltage V.sub.p is poor. In addition, since the gate electrode 8a comprises a low resistance metal, the reliability of the contact between the gate electrode and the n layer is low as compared to the FET employing the refractory metal gate electrode. In the structure shown in FIG. 27, the gate length is determined by the width of the opening of the resist film 17.
As described above, when a low resistance metal is used for the gate electrode, the reliability of the contact between the gate electrode and the n layer is not satisfactory. The reliability of the contact can be improved by a gate electrode having a double-layer structure in which a low resistance metal gate is disposed on a refractory metal gate. A compound semiconductor FET having such gate structure is disclosed by I. Hanyu et al. in Electronics Letters, Vol. 24 (1988), p.1327. FIG. 29 shows the FET structure. This FET comprises a compound semiconductor substrate 1, an n layer 2 disposed on the substrate 1, an n.sup.+ layer 4 disposed on the n layer 2, a recessed gate electrode comprising a refractory metal layer 5 and a low resistance metal layer 8, ohmic electrodes 7a and 7b disposed on the n.sup.+ layer 4 at opposite sides of the gate electrode, and an insulating film 6 covering the surface of the structure except upper surfaces of the ohmic electrodes 7a and 7b. Reference numeral 70 designates a porous portion of the refractory metal layer 5. Although in the above-described literature the n layer 2 has a double-layer structure of AlGaAs/GaAs, since the structure of the n layer matters little to the description about the structure and fabricating process of the gate electrode, a single n layer will be used in the following description.
FIGS. 30(a)-30(h) illustrate process steps in a method of fabricating the FET having the gate electrode with the double-layer structure comprising a refractory metal and a low resistance metal. Initially, a compound semiconductor substrate on which an n layer 2 and an n.sup.+ layer 4 are produced by epitaxial growth or ion implantation is prepared. As illustrated in FIG. 30(a), an insulating film 18 is deposited on the substrate and a resist film 19 having a desired opening pattern is formed on the insulating film 18. Thereafter, as illustrated in FIG. 30(b), using the resist film 19 as a mask, the insulating film 18 is etched and, subsequently, the n.sup.+ layer 4 and the n layer 2 are etched to form a recess. This etching is stopped within the n layer 2. When the insulating film 18 comprises SiO.sub.2, it is etched by RIE with a gas mixture of CHF.sub.3 +O.sub.2. The n.sup.+ layer 4 and the n layer 2 are etched by plasma etching with Cl.sub.2 or wet etching with tartaric acid.
In the step of FIG. 30(c), after removal of the resist film 19, an insulating film 20 is deposited over the substrate. The gate length is determined by the thickness of the insulating film 20 and the width of the opening pattern of the resist film 19. Thereafter, as illustrated in FIG. 30(d), the insulating film 20 is etched back, leaving portions on the inner side surfaces of the recess. Then, as illustrated in FIG. 30(e), a refractory metal film 5 comprising, for example, WSi, WSiN, or WN, is deposited by sputtering or the like, followed by annealing. After the annealing, a low resistance metal film 8 comprising, for example, Au, is deposited. Since the refractory metal film 5 is formed by sputtering of WSi, WSiN, or WN, the underlying n layer 2 is damaged. Therefore, annealing is required before the deposition of the low resistance metal film 8. This annealing is performed at 400.degree.-500.degree. C. Further, the refractory metal film 5 has porous portions 70 shown by dotted lines in FIG. 30(e) because of the difference in level, i.e., steps, on the substrate.
Thereafter, as shown in FIG. 30(f), a resist pattern 21 is formed on the low resistance metal film 8 and, using this resist pattern 21 as a mask, the low resistance metal film 8 is etched by ion milling with Ar gas and the refractory metal film 21 is etched by RIE with a gas mixture of CF.sub.4 +O.sub.2 or CHF.sub.3 +SF.sub.6. Further, as illustrated in FIG. 30(g), the resist pattern 21, the insulating film 18, and the insulating film 20 are removed, and source and drain ohmic electrodes 7a and 7b are formed on the n.sup.+ layer 4 at opposite sides of the gate electrode. Finally, as illustrated in FIG. 30(h), an insulating film 6 is deposited over the entire surface and portions of the insulating film 6 on the ohmic electrodes 7 are etched away. The gate electrode has a V-shaped hollow in the center of the top surface. Also in this fabricating process, the gate electrode is produced self-alignedly with the recess.
In the FET fabricated as described above, because the recess structure is employed, a high drain breakdown voltage is realized. In addition, the refractory metal layer 5 of the gate electrode is in contact with the n layer 2, so the reliability of the contact between the gate electrode and the n layer is high. However, since the recess is formed by etching, it is difficult to accurately control the pinch-off voltage V.sub.p. Further, since the refractory metal layer 5 of the gate electrode includes the porous portion 70 shown by the dotted line in FIG. 29, there is a possibility of abnormal diffusion of the low resistance metal layer 8 into the refractory metal layer 5.
FIG. 31 shows a prior art FET combining advantages of both the planar LDD-FET and the recessed gate FET, i.e., an FET providing high breakdown voltage, high reliability, and high V.sub.p controllability. In this FET, a gate electrode 5a is disposed in a recess while active layers 2, 3, and 4 are in an LDD structure.
FIGS. 32(a)-32(h) illustrate process steps in a method of fabricating the FET shown in FIG. 31. Initially, a recess is formed in a compound semiconductor substrate 1 using an etching technique with a resist mask 25. The process steps after the formation of the recess (FIGS. 32(c)-32(h)) are identical to the fabricating process of the LDD-FET already described with respect to FIGS. 26(a)-26(g). However, in the FET fabricated by this method, in contrast to the recessed gate FETs fabricated by the above-described methods shown in FIGS. 28(a)-28(c) and FIGS. 30(a)-30(h), since the gate electrode is not formed self-alignedly with the recess, the uniformity of the FET characteristics and their reproducibility are poor, so that good production yield is not obtained.
A description is given of a prior art method of fabricating a heterojunction bipolar transistor (hereinafter referred to as HBT). FIG. 33 is a sectional view of an HBT disclosed by N. Hayama and K. Honjo in IEEE Electron Device Letters, Vol. 11 (1990), p. 388. In this HBT structure, it is necessary to form an emitter electrode (E in the figure) self-alignedly with base electrodes (B in the figure), and the emitter electrode E is spaced apart from the base electrodes B using SiO.sub.2 side walls. A method of fabricating the HBT is illustrated in FIGS. 34(a)-34(i). Although a collector layer is not shown in the figures, it is included in the compound semiconductor substrate 1.
Initially, as illustrated in FIG. 34(a), a base layer 110 and an emitter layer 111 are epitaxially grown on the compound semiconductor substrate 1. Then, an SiN film is deposited over the emitter layer 111 and patterned by photolithography and etching to leave a portion 101 on a region where an emitter electrode is later produced.
In the step of FIG. 34(b), using the SiN film 101 as a mask, the structure is dry-etched using Cl.sub.2 gas until the etching front reaches into the emitter layer 111, forming a mesa structure for an emitter electrode. Thereafter, as illustrated in FIG. 34(c), an SiO.sub.2 film is deposited over the entire surface and etched back to form first SiO.sub.2 side walls 102 on both sides of the mesa structure. Further, portions of the emitter layer 111 outside the first side walls 102 are wet-etched until the surface of the base layer 110 is exposed.
In the step of FIG. 34(d), a base metal 103, such as AuMn, is deposited over the structure by vacuum evaporation. Then, as illustrated in FIG. 34(e), the base metal 103 is subjected to diagonal ion-milling to remove portions of the base metal 103 slightly deposited on the side surfaces of the SiO.sub.2 side walls 102. Thereafter, second SiO.sub.2 side walls 104 are formed in the same process as the first SiO.sub.2 side walls 102 as shown in FIG. 34(f).
In the step of FIG. 34(g), using the second side walls 104 as masks, the base metal 103 is etched by ion-milling, forming base electrodes 103a. Thereafter, as illustrated in FIG. 34(h), the SiN film 101 is selectively removed so as not to remove the first and second SiO.sub.2 side walls 102 and 104. This selective removal is easily carried out by plasma etching with SF.sub.6 gas. Finally, as illustrated in FIG. 34(i), an emitter electrode 105 is formed to complete the structure shown in FIG. 33.
In the above-described method, however, when the SiO.sub.2 film is etched back by RIE to form the SiO.sub.2 side walls, the substrate is damaged or undesirably etched, resulting in degradation in device characteristics and increased variations of the device characteristics. In addition, since diagonal ion-milling is used for removal of the base metal, the device characteristics are degraded as a result of imperfect etching with residual or excess etching.
According to the above-described prior art FETs, the planar LDD-FET employing a refractory metal gate (FIG. 25(a)) has a low drain breakdown voltage, and the recessed gate FET employing a refractory metal gate (FIG. 29) has a poorly controlled pinch-off voltage V.sub.p. Further, in the prior art FET employing both the recessed gate structure and the LDD structure in order to solve the above-described problems (FIG. 31), since the refractory metal gate is not self-aligned with the recess, good yield is not achieved. Furthermore, in the prior art BPLDD-FET employing a buried p layer for suppressing the short channel effect (FIG. 25(b)), although the buried p layer is desired to be absent under the n.sup.+ layer, in other words, present only under the n and n' layers, in order to remove the capacitance between the p layer and the n.sup.+ layers, since the buried p layer cannot be produced self-alignedly with the n.sup.+ layers, the capacitance between the buried p layer and the n.sup.+ layer remains, resulting in a reduction in the operating speed.
On the other hand, in the prior art HBT shown in FIG. 33, the RIE for forming the SiO.sub.2 side walls and the diagonal ion-milling for removing unnecessary portions of the base metal adversely affect the device characteristics and increase the variations in the device characteristics.

Method of fabricating semiconductor device

by Yoko Kohno, heir/legal representative


A wordline driver for a memory device includes a row decoder decoding externally inputted row address signals and outputting a main decoding signal and a main decoding bar signal, a wordline drive decoder decoding two lowest bits among the row address signals and outputting a global decoding signal, a local wordline driver receiving first and second signals and outputting a local wordline driving signal in accordance with the global decoding signal corresponding to the wordline drive decoder, and a sub-wordline driver coupled to the wordline drive decoder and the local wordline driver and outputting a sub-wordline driving signal to a sub-wordline in accordance with the local wordline decoding signal from the local wordline driver, and the main decoding signal and the main decoding bar signal outputted from the row decoder.

1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a wordline driver for a semiconductor memory device. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for reducing a driving voltage in the semiconductor memory device.
2. Discussion of the Related Art
When a row decoder decodes an externally applied row address in a semiconductor memory device, a wordline driver drives a wordline in accordance with a signal outputted from the row decoder. As a more integrated memory device is required, a design rule of the wordline becomes smaller. Also, the number of cells driven by a single wordline is increased with this trend.
To satisfy such demand, a dual wordline decoding scheme (DWDS) has been introduced. A wordline of the DWDS is divided by main wordlines and sub-wordlines and driven by hierarchically decoding a row address.
FIG. 1 is a block diagram of a dual wordline driver (DWD) in accordance with a background art. Specifically, the DWD includes a row decoder RD 10 decoding an externally inputted row address and outputting a main decoding signal. A plurality of wordline drive decoders WDD 20 each decoding two lowest bits among row address signals and outputting a sub-decoding signal. A plurality of sub-wordline drivers SWD 30 driving sub-wordlines using the main decoding signal from the row decoder RD 10 and the sub-decoding signals from the wordline drive decoders WDD 20.
The wordline drive decoders WDD 20 and the sub-wordline drivers SWD 30 are hierarchically connected each other. A plurality of cell arrays divided by a bitline sensing amplifier (BLSA) constitute a single bank.
FIG. 2 is a detailed diagram illustrating a part of the wordline driver for the semiconductor memory device.
FIG. 3 illustrates a circuit diagram of a single sub-wordline driver SWD 30. As shown therein, the sub-wordline driver SWD 30 includes a PMOS transistor P1 having a gate receiving an inverted main decoding signal MWLb and a source receiving a sub-decoding signal Wdi. An NMOS transistor N1 are connected between a drain of the PMOS transistor P1 and a ground Vss and having a gate receiving the inverted main decoding signal MWLb. A second NMOS transistor N2 are connected in parallel between the source and drain of the PMOS transistor P1 and having a gate receiving a main decoding signal MWL.
Each drain of the PMOS transistor P1 and the first NMOS transistor N1 and the source of the second NMOS transistor N2 are connected with a sub-wordline SWL through an output node A.
The operation of the wordline driver for the semiconductor memory device will be described as follows.
When a row address signal is externally inputted, as shown in FIG. 2, each pair of the wordline drive decoders WDD 20 respectively outputs four decoding signals WDi by decoding the two lowest bits among input row address signals. The row decoder RD 10 outputs the main decoding signals MWL and MWLb in accordance with a remaining row address signal.
Accordingly, the plurality of sub-wordline drivers SWD 30 enable each corresponding the sub-wordlines SWL in accordance with each level of the main decoding signals MWL, MWLb and the decoding signals WDi from the wordline drive decoder WDD 20.
Specifically, as shown in FIGS. 4A through 4D, only the first NMOS transistor N1 of the sub-wordline driver 30 is turned on for a period t1, thus a signal transmitted to the sub-wordline SWL through the output node A becomes a low level. For a period t2, the sub-wordline SWL is maintained in the low level. The second NMOS transistor N2 and the PMOS transistor P1 of each sub-wordline driver SWD 30 are turned on for a period t3. The decoding signals WDi of a low level from the wordline drive decoder WDD 20 are transmitted to the subwordline SWL. For a period t4, both the first and second NMOS transistors N1 and N2 and the PMOS transistor P1 of the sub-wordline driver SWD 30 are turned on. The decoding signals WDi of a high level outputted from the wordline driver decoder WDD 20 are thus transmitted to the subwordline SWL.
Accordingly, the sub-wordline drivers SWD 30 respectively enable the sub-wordline SWL only when both the main decoding signal from the row decoder RD 10 and the decoding signals WDi from the wordline drive decoders 20 are at the high level. Considering one cell block in the background art as described above, since the main decoding signal MWL, the main decoding bar signal MWLb and the decoding signals WDi are designated in the same bank, the above signals remain inactive while one wordline is active.
On the other hand, when the wordline driver according to the background art is applied to a multi-bank memory (i.e., a single wordline drive decoder driving sub-wordline drivers with several banks), the wordline driver cannot be operative under this condition. In the multi-bank memory, a wordline may be independently enabled by each bank. Since the decoding signals WDi of the wordline drive decoder commonly share several banks, both the decoding signals WDi and the decoding signal MWL should be enabled at the high level in order to enable a wordline of the bank.
However, when the main decoding bar signal MWLb and the decoding signals WDi are enabled to operate a wordline of a second bank before disabling the wordline of the first bank after predetermined time, the decoding signals WDi of the first wordline drive decoder is disabled. Consequently, the wordline designated to the decoding signals WDi of the first wordline drive decoder is disabled and the wordline designated to the decoding signals WDi of the second wordline drive decoder is enabled, thereby damaging cell data.
Accordingly, when the wordline driver according to the background art is applied to the multi-bank memory, an additional control line should be provided to eliminate a damage in the cell data. Increases in chip size and power consumption for driving the wordline are unavoidable.

Wordline driver for semiconductor memory device


An improved optical pick-up apparatus capable of simplifying the construction of a tracking coil and a focussing coil and more easily assembling the system by providing fine-patterned tracking coil and focussing coil, which generate a driving force so as to drive an objective lens, which includes an objective lens for condensing a light; an objective lens holder for supporting the objective lens; a yoke engaged to the objective lens holder and having a permanent magnet; and a fine-patterned coil provided with a tracking fine-patterned portion and a focusing fine-patterned portion, engaged to the objective lens holder, and constituting a magnetic circuit with the permanent magnet.

1. Field of the Invention
The present invention relates to an optical pick-up driving apparatus, and particularly to an improved optical pick-up apparatus for simplifying the construction of a tracking coil and a focusing coil and providing a more efficient assembling process of the system by using a fine-patterned tracking coil and a fine-patterned focusing coil, which generates a driving force to drive an objective lens.
2. Description of the Conventional Art
Referring to FIGS. 1 and 2, a conventional optical pick-up driving apparatus includes an objective holder 1 which surrounds an objective lens 6 for supporting the objective lens 6, and a printed circuit board (PCB) 5 mounted at one side of the objective holder 1.
Referring to FIG. 4A, a focusing coil 2 is wound around an outer surface of the objective holder 1 and has a certain height.
In addition, as shown in FIGS. 2 and 3A, a plurality of snail-shaped tracking coils 3 are mounted on a left-side surface and a right-side surface of the focusing coil 2, respectively.
The focusing coil 2 and the tracking coil 3 are electrically connected to a predetermined portion of the PCB 5 by an electrical interconnection therebetween.
Meanwhile, a plurality of rectangular insertion grooves 1a, which each extends from the top surface of the objective lens holder 1 through to the bottom surface thereof, are formed within the objective lens holder 1.
In addition, as shown in FIG. 2, a plurality of rectangular-shaped feet 9a are formed, which are inserted into insertion holes 1a of the objective lens holder 1, and yokes 9 each having a permanent magnet 4 (for generating a certain magnetic force in cooperation with the focusing coil 2 and the tracking coil 3) are provided between left-side feet 9a and 9b and between right-side feet 9a and 9b.
The objective lens holder 1, around which the focusing coil 2 having the tracking coils 3 is wound, includes the insertion grooves 1a into which the feet 9a are inserted.
In the drawings, reference numeral 7 denotes a wire spring connected to the objective holder 1.
Because the permanent magnets 4 and the tracking coil 3 of the conventional optical pick-up apparatus are directed to generating a certain magnetic field, when current is supplied to the tracking coil 3, as shown in FIG. 3B, the optical driving-apparatus is driven in the tracking direction in cooperation with the left-side and right-side direction magnetic force based on Fleming's left hand theory (F=B*I*L).
In FIG. 3B, reference character "B" denotes the direction of magnetic field, and reference character "F" denotes the direction of magnetic force.
In addition, when current is applied to the focusing coil 2, the optical pick-up driving apparatus is driven in the upward and downward directions due to the magnetic force based on Fleming's left hand theory (F=B*I*L).
In FIG. 4B, reference character "B" denotes the direction of magnetic field, and reference character "F" denotes the direction of magnetic force.
However, the conventional optical pick-up driving apparatus has disadvantages in that a printed circuit board is additionally necessary for electrically connecting the focusing coil and the tracking coil so as to supply voltage to the focusing coil and the tracking coil. In addition, winding apparatuses for winding the focusing coil around the outer surface of the objective lens holder and for forming the tracking coil, and an assembling apparatus are additionally necessary, thereby increasing manufacturing cost of the product.
Moreover, when manufacturing the focusing coil and tracking coil, manufacturing errors occur since the focusing coil and tracking are manually assembled by mechanical process, so that the performance of the optical pick-up driving apparatus is decreased.


Embodiments of a digital-to-analog conversion system that utilizes a specialized clock signal to reshape an analog impulse response of a digital-to-analog converter (DAC) are disclosed. Preferably, a shape of the specialized clock signal is such that Nyquist images resulting from digital-to-analog conversion are controlled in a desired manner. In one embodiment, the digital-to-analog conversion system includes a DAC that converts a digital input signal into an analog output signal. A specialized clock signal is applied to the analog output signal of the DAC such that an analog impulse response of the DAC is reshaped according to a shape of the specialized clock signal, thereby providing a modified analog output signal. The specialized clock signal reshapes the analog impulse response of the DAC such that Nyquist images resulting from digital-to-analog conversion are controlled in a desired manner.

Digital-to-analog converters (DACs) are primary components in many of today's electronic devices. For example, modern telecommunication devices include digital processors to perform complex processing while adhering to reasonable power and size constraints. In order to wirelessly transmit information, digital signals output by the digital processors are converted into analog signals. This conversion process is performed by a DAC.
The frequency domain representation of a digital signal consists of an infinite number of replicas of the desired analog signal located at integer multiples of a sampling rate (fS) of the digital signal, as illustrated in FIG. 1. These replicas are referred to herein as Nyquist images or simply images. Since the Nyquist images are undesirable after digital-to-analog conversion, several approaches have been developed to remove the Nyquist images in the analog domain, namely, analog low-pass filtering, interpolation, high-order sample-and-holds, and combining the output of multiple DACs that have offset clocks.
In this regard, FIG. 2 illustrates a DAC 10 followed by a low-pass filter 12. The low-pass filter 12 has a stop-band that starts at fS/2 (see FIG. 1) such that the low-pass filter 12 removes all undesired Nyquist images while passing the desired signal centered at DC. The passband of the low-pass filter 12 must be as large as the desired signal bandwidth. If the bandwidth of the desired signal is close to fS/2, like it is in FIG. 1, then there is a small region for the low-pass filter 12 to transition from passband to stopband. A short transition region requires that the low-pass filter 12 be highly selective, which means that the low-pass filter 12 must be physically large and is complex to design.
Interpolation in the digital domain can be used to increase the spacing between the Nyquist images in the frequency domain and thereby relax the selectivity requirements for the low-pass filter 12. Interpolation is equivalent to sampling a signal faster than the Nyquist rate, where the Nyquist rate is twice the baseband bandwidth of the signal. As illustrated in FIG. 3, as an example, interpolation may be used to increase the sampling rate of the digital signal of FIG. 1 by a factor of 4 to provide an increased sampling rate fS′. By increasing the sampling rate by a factor of 4, the spacing between the Nyquist images has also been increased by a factor of 4, which in turn relaxes the selectivity requirements on the low-pass filter 12 (FIG. 2). As illustrated in FIG. 4, interpolation consists of up-sampling the digital signal by a desired up-sampling factor, which in this example is 4, using an up-sampler 14 and then digitally filtering the up-sampled digital signal with a Finite Impulse Response (FIR) filter 16. The resulting digital signal is then digital-to-analog converted by the DAC 10. However, the low-pass filter 12 is still required to remove the undesired Nyquist images.
Nyquist images are also affected by the manner in which the DAC 10 generates the analog signal. In particular, the manner in which the DAC 10 generates the analog signal shapes the effective frequency response at the analog output of the DAC 10. The analog output is typically characterized as zero-order hold (ZOH), first-order hold (FOH), second-order hold (SOH), etc. An analog signal with ZOH holds the value of the corresponding digital signal constant for one clock period, as illustrated in FIG. 5A. An analog signal with FOH generates a straight line between two consecutive digital values, as illustrated in FIG. 5B. An analog signal with SOH generates a quadratic curve between three consecutive digital values, as illustrated in FIG. 5C. The corresponding frequency response of the ZOH, FOH, and SOH type DACs are sinc(πf/fS), sinc2(πf/fS), and sinc3(πf/fS), respectively, where the sinc function is defined as sinc(x)=sin(x)/x. These frequency responses exhibit nulls at the center of all undesired Nyquist images (i.e., have nulls at integer multiples of fS). Each hold order requires a differentiator in the digital domain and an integrator in the analog domain. As an example, a SOH requires two digital differentiators and two analog integrators. The frequency response of the high-order holds is not flat over the desired signal's passband. As such, some form of compensation is required. In addition, high-order holds do not significantly relax the low-pass filter requirements since the frequency responses do not provide sufficient stop-band attenuation near fS/2 (especially after compensation). However, high-order holds can be used with interpolation to relax the low-pass filter requirements. Interpolation confines more of the signal energy of the Nyquist images to the vicinity of the nulls of the high-order hold frequency responses.
Multiphase clocking involves summing the output of parallel DACs, whereby the clocks of each of the DACs are offset with respect to one another. Multiple DACs with different clock phases can be used to provide additional nulls in the frequency response. The same input signal is fed to all DACs. The additional nulls can be used to attenuate images beyond that achievable by the ZOH sinc response.
One problem with all of the aforementioned approaches to removing undesired Nyquist images is that all of the approaches require the low-pass filter 12. For future generations of mobile telecommunication device transmitters, it is desired to integrate the DAC and frequency up-conversion functions into a single integrated chip. The low-pass filters required in all of the above approaches do not integrate well onto an integrated chip due to their large area and precision issues related to passive devices. In order to integrate the DAC and frequency up-conversion functions, all undesired Nyquist images at the DAC output need to be significantly attenuated with a small integrated low-pass filter (small size corresponds to poor selectivity), or no filter at all. There are two issues if the undesired Nyquist images are not significantly attenuated. First, due to the specific frequency spacing of the Nyquist images, non-linear action in the up-conversion mixer will result in intermodulation distortion (IMD) falling directly into the passband. Second the Nyquist images and their IMD components outside the passband need to be filtered after up-conversion by a highly selective radio frequency (RF) band-pass filter, which is typically larger and more complex than the low-pass filter it is replacing.
As such, there is a need for systems and methods for attenuating undesired Nyquist images resulting from digital-to-analog conversion without the need for complex post-DAC analog filtering.


A water-absorbing cyclone dust cup for secondary dust-air separation comprises a dust cup cover body and a dust cup main body. The dust cup main body comprises a cup body portion, a primary cyclone arranged in an opening of the dust cup main body, and a secondary cyclone comprising a secondary cyclone main body provided with a ventilation hole defined in a center. At least one air guiding portion is arranged on a bottom end surface of the secondary cyclone main body. The air guiding portions comprise spiral air guiding plates, spiral air guiding passages formed by the spiral air guiding plates around the ventilation hole, and air guiding passage baffles enclosing first ends of the spiral air guiding plates, the spiral air guiding passages are formed by spiral longitudinal extension along the center line direction of the ventilation hole.

Vacuum cleaners have become essential household appliances for providing neatness and cleanliness and are gradually accepted by most users. The vacuum cleaners can be classified into two categories of dry vacuum cleaners and wet and dry vacuum cleaners according to their functions, and can be classified into two categories of dust cup type vacuum cleaners and dust bag type vacuum cleaners according to dust storage modes.
The existing dust cup type vacuum cleaner generally comprises a two-stage dust-air separation, structure. A primary dust-air separation structure is used for filtering large pollutants in the air, and a secondary dust-air separation structure is used for separating and collecting small dust particles and other sundries. The traditional secondary dust-air separation structure generally forms a secondary cyclone through the matching of a filter cover plate of a dust cup and a cyclone body provided with a plurality of cyclone ports. Such structure needs more parts and involves many complicated molds and tooling; more seals are required between the parts, which is difficult to control and easy to generate air leakage and dust leakage, thereby affecting the comprehensive performance of the whole machine.
The existing secondary dust-air separation type dust cup structure adopts an axial layout, and the purpose of dust-air separation is achieved by axially superimposing layers of conical bodies and a cyclone, so that a filter structure occupies a large space of the dust cup and occupies more dust storage space. Thus, the volume of the dust cup is small, causing that the secondary dust-air separation type dust cup structure is not suitable for small vacuum cleaners and portable vacuum cleaners, and is limited in the use range.
The secondary dust-air separation type dust cup of the above structure cannot be used for water absorption, and has no water retaining structure, causing that the secondary dust-air separation type dust cup is not suitable for the wet and dry vacuum cleaners.

Water-absorbing cyclone dust cup for secondary dust-air separation and vacuum cleaner thereof

CUORI ELECTRICAL APPLIANCES (GROUP) CO., LTD


A distributed channel allocation method and a wireless mesh network with the same are provided herein. By the distributed channel allocation, interference situations are avoided in a wireless network communication, and the allocated bandwidth can then be fully utilized. Besides, unnecessary depletion of an allocated bandwidth due to the interference can be avoided. By this method, a time division technique is applied for dividing a transmission time of each wireless NIC, and different non-overlapping channels can be assigned to different timeslots. Different from other researches that require a symmetrical number of the NICs between a receiving node and a transmitting node, in this method, a unique wireless NIC may communicate with the wireless NICs. The method provides the feature that the number of the NICs on a certain node can be adjusted to meet a communication requirement, by which the efficiency of a network flow is also significantly improved.

1. Field of the Invention
The present invention relates to a channel allocation method of a wireless network and a system thereof. More particularly, the present invention relates to a distributed channel allocation method of a wireless mesh network and a system thereof.
2. Description of Related Art
In recent years, there is a rapid development in the field of wireless broadband access techniques including Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series) and 3G, etc. The wireless mesh network (referred to hereinafter as WMN, IEEE 802.11s) is one of the key techniques integrated with the wireless broadband network. The structure of the WMN illustrated in FIG. 1 is a mesh network based on a wireless transmission interface, and the WMN has a similar operation mode to that of an Ad-hoc network. Since the operation of the WMN is based on the wireless transmission interface, it has the advantage of rapid deployment without restriction of the geographical landforms. The WMN is generally applied to a community network, a temporary network of exhibition halls or shopping stalls, networks established in disaster areas or areas having special geographical environments, and so on.
The operation of the WMN is based on the wireless transmission interface. Taking the IEEE 802.11a/g for an example, its transmission bandwidth of data is 54 Mbps (mega bytes per second), which is the maximum possible transmission bandwidth. However, influenced by a MAC (media access control) contention, 802.11 headers, 802.11 ACK signals and packet errors, an average applicable bandwidth is usually less than half of the maximum bandwidth.
Furthermore, the most serious issue lies in that a data transmission rate of a network link layer may be decreased greatly due to signal interference. Two possible interference problems are shown in FIG. 2: (1) interference in the same transmission path, (2) interference in the adjacent transmission paths. Referring to FIG. 2, the signal coverage of a node 3 includes nodes 2, 4 and 9. Similarly, the node 3 is simultaneously in the signal coverage of the nodes 2, 4 and 9. A first transmission path and a second transmission path are paths for data transmission. The first transmission path is taken for an example. When the node 2 and the node 3 are transmitting data, the node 4 may receive signals from the node 3, resulting in the fact that node 4 cannot transmit data to a node 5 provisionally. Therefore, the bandwidth of the first transmission path is reduced, which refers to the so-called interference in the same transmission path.
On the other hand, referring to the node 9 on the second transmission path, since the node 9 is in the signal coverage of the node 3, the node 9 may receive signals from the node 3 when the node 2 and the node 3 are transmitting data, resulting in the fact that the node 9 cannot transmit data to a node 8 or a node 10 provisionally. The phenomenon indicating an interference of data transmission through the first transmission path with that through another transmission path (a second transmission path) represents the so-called interference in the adjacent transmission paths. Therefore, many studies are performed on the WMN to learn how to improve an applicable bandwidth of the WMN by advancing a structural design thereof.
According to the IEEE 802.11s WiFi Mesh standard, a plurality of wireless transmission interfaces is allowed to use different non-overlapping channels for transmission, so as to increase the transmission bandwidth. Therefore, some studies have been developed to increase a network flow by applying multi-network interface cards (referred to hereinafter as Multi-NIC). A method of increasing the network flow includes allocating a plurality of NICs on each node, and each of the NICs may employ a different non-overlapping channel to communicate with other nodes. The advantage of this method lies in that it is unnecessary to modify any existing hardware structures. Only is an integral channel allocation method required for assisting the existing hardware structure, and the network flow can be substantially improved.
A method and a system for assigning channels in a wireless local area network (WLAN) is disclosed in U.S. Publication No. 2006/0072502 A1, in which the WLAN infrastructure mode (i.e. a client to hub communication mode) is provided. A mobile node (referred to hereinafter as MN) in the network is connected to an access point (referred to hereinafter as AP) by means of one hop, and the other end of the AP is connected to a wired network, wherein each AP has at least two applicable channels, and each AP is at least adjacent to another AP.
Each AP constantly collects the traffic load information and forecasts a possible throughput on each channel. Thereafter, the AP determines an optimal channel for connecting with the MN within the signal coverage of the AP. However, this channel allocation method only takes the optimal channel within one hop between the AP and the MN into account. Therefore, the application of the method is limited.
Most of the early studies focus on modifying an MAC layer protocol of the network to support a multiple channel transmission. The studies aim to find the optimal channel for transmitting every single packet, so as to avoid the interference. On the other hand, a concept of a Multi-NIC disclosed by V. Bahl et al. and P. H. Hsiao et al. in two articles has drawn attention and discussions recently. One of the articles was authored by V. Bahl, A. Adya, J. Padhye, A. Wolman, entitled "Reconsidering the Wireless LAN Platform with Multiple Radios" Workshop on Future Directions in Network Architecture (FDNA-03), while another one was authored by P. H. Hsiao, A. Hwang, H. T. Kung, and D. Vlah, entitled "Load-Balancing Routing for Wireless Access Networks" Proc. of IEEE Infocom 2001. The method disclosed therein is to install a plurality of the NICs on each node of the Ad-hoc network, and each NIC may dynamically determine a channel for communicating with other nodes. The advantage of this method lies in that it is unnecessary to modify any existing hardware structures. Only is the integral channel allocation method required for assisting the existing hardware structure, and the network flow can be substantially improved. Sequentially, a channel allocation method based on a centralize structure was disclosed by A. Raniwala, K. Gopalan, T. Chiueh, entitled "Centralized channel assignment and routing algorithms for multi-channel wireless mesh networks," ACM Mobile Computing and Communications Review 8 (2) (2003), which is one of the earliest articles having a formal definition of the channel allocation. In the method, a load-aware channel assignment is performed by an evaluation matrix defined by the authors themselves, the entire network is calculated in overall, and a preferable channel allocation is obtained. Thus, a maximum network flow is then achieved.
In recent studies, a channel allocation technique based on a dynamic & distributed structure has been disclosed, wherein channel allocation information is exchanged by using a common channel framework according to the IEEE 802.11s standard. This technique is based on IEEE 802.11 WLAN standard, wherein a plurality of wireless NICs is installed to support a multi-channel transmission. However, the interference still cannot be avoided in the aforementioned techniques.

Distributed channel allocation method and wireless mesh network therewith

Industrial Technology Research Institute


Techniques of using a Transmission Charged Particle Microscope for diffraction pattern detection are disclosed. An example method including irradiating at least a portion of a specimen with a charged particle beam, using an imaging system to collect charged particles that traverse the specimen during said irradiation, and to direct them onto a detector configured to operate in a particle counting mode, using said detector to record a diffraction pattern of said irradiated portion of the specimen, recording said diffraction pattern iteratively in a series of successive detection frames, and during recording of each frame, using a scanning assembly for causing relative motion of said diffraction pattern and said detector, so as to cause each local intensity maximum in said pattern to trace out a locus on said detector.

Charged-particle microscopy is a well-known and increasingly important technique for imaging microscopic objects, particularly in the form of electron microscopy. Historically, the basic genus of electron microscope has undergone evolution into a number of well-known apparatus species, such as the Transmission Electron Microscope (TEM), Scanning Electron Microscope (SEM), and Scanning Transmission Electron Microscope (STEM), and also into various sub-species, such as so-called "dual-beam" apparatus (e.g. a FIB-SEM), which additionally employ a "machining" Focused Ion Beam (FIB), allowing supportive activities such as ion-beam milling or Ion-Beam-Induced Deposition (MID), for example. More specifically:
In an SEM, irradiation of a specimen by a scanning electron beam precipitates emanation of "auxiliary" radiation from the specimen, in the form of secondary electrons, backscattered electrons, X-rays and cathodoluminescence (infrared, visible and/or ultraviolet photons), for example; one or more components of this emanating radiation is/are then detected and used for image accumulation purposes.
In a TEM, the electron beam used to irradiate the specimen is chosen to be of a high-enough energy to penetrate the specimen (which, to this end, will generally be thinner than in the case of a SEM specimen); the transmitted electrons emanating from the specimen can then be used to create an image. When such a TEM is operated in scanning mode (thus becoming a STEM), the image in question will be accumulated during a scanning motion of the irradiating electron beam.
As an alternative to the use of electrons as irradiating beam, charged particle microscopy can also be performed using other species of charged particle. In this respect, the phrase "charged particle" should be broadly interpreted as encompassing electrons, positive ions (e.g. Ga or He ions), negative ions, protons and positrons, for instance.
It should be noted that, in addition to imaging and performing (localized) surface modification (e.g. milling, etching, deposition, etc.), a charged particle microscope may also have other functionalities, such as performing spectroscopy, examining diffractograms, etc.
In all cases, a Charged Particle Microscope (CPM) will comprise at least the following components: A particle source, such as an electron source or ion source. An illuminator (e.g., a charged particle beam column), which serves to manipulate a "raw" radiation beam from the particle source and perform upon it certain operations such as focusing, aberration mitigation, cropping (e.g., with a diaphragm), filtering, etc. It will generally comprise one or more (charged-particle) lenses, and may comprise other types of (particle-)optical components also. If desired, the illuminator can be provided with a deflector system that can be invoked to cause the exit beam to perform a scanning motion across the specimen being investigated. A specimen holder on which a specimen under investigation can be held and positioned (e.g. tilted, rotated). If desired, this holder can be moved so as to effect scanning motion of the specimen with respect to the beam. In general, such a specimen holder will be connected to a positioning system. When designed to hold cryogenic specimens, the specimen holder can comprise means for maintaining said specimen at cryogenic temperatures, e.g. using an appropriately connected cryogen vat. A detector (for detecting radiation emanating from an irradiated specimen), which may be unitary or compound/distributed in nature, and which can take many different forms, depending on the radiation being detected. Examples include photodiodes, CMOS detectors, CCD detectors, photovoltaic cells, X-ray detectors (such as Silicon Drift Detectors and Si(Li) detectors), etc. In general, a CPM may comprise several different types of detector, selections of which can be invoked in different situations.
In the case of a transmission-type microscope (such as a (S)TEM, for example), a CPM will additionally comprise: An imaging system, which essentially takes charged particles that are transmitted through a specimen (plane) and directs (focuses) them onto analysis apparatus, such as a detection/imaging device, spectroscopic apparatus (such as an EELS device: EELS=Electron Energy-Loss Spectroscopy), etc. As with the illuminator referred to above, the imaging system may also perform other functions, such as aberration mitigation, cropping, filtering, etc., and it will generally comprise one or more charged-particle lenses and/or other types of particle-optical components.
In what follows, the techniques disclosed herein may—by way of example—sometimes be set forth in the specific context of electron microscopy; however, such simplification is intended solely for clarity/illustrative purposes, and should not be interpreted as limiting.
Charged-particle irradiation generally causes radiation damage to specimens, especially biological samples. Consequently, in (for example) life science TEM applications, it is desirable to work at relatively low-dose illumination conditions, in an attempt to minimize radiation damage to the specimen. Such low-dose operation, however, tends to cause a degradation in signal quality. These conflicting effects present the TCPM (Transmission Charged Particle Microscope) operator with a conundrum.

Diffraction pattern detection in a transmission charged particle microscope


The instant invention relates to compositions comprising a benzoxazine resin and an advancement resin based on bisphenol A diglycidyl ether and bisphenol S and, optionally, ferrocene and aluminium trihydrate. Such compositions are, when cured to form polymeric networks, difficultly inflammable and resistant to high temperatures. Such compositions may especially be used in the production of printed wiring boards.

FR-4 PCB Laminate is the most commonly used base material for printed circuit boards. The "FR" means Flame Retardant (to UL94V-0), and Type "4" indicates woven glass reinforced epoxy comprising resin. In addition, the FR-4 Laminate has to pass solder bath tests. In order to make resins flame retardant the addition of bromine, phosphorous, chlorine containing compounds, fillers or the use of special flame retardant backbones is necessary. However, such solutions to make a composition flame retardant based in particular on bromine or phosphorous compounds have as a rule one or several drawbacks:                They are not soluble in solvents and hence cause problems in terms of processing.        They show poor oxidative stabilities at elevated temperatures.        Additives are very often responsible for a decrease of the glass transition levels.        Very often poor physical properties (for example delaminations) of the cured resins are been observed, especially when phosphorous compounds are present.        Toxic gases of combustion may form in case of fire, especially when halogenated compounds are present.
An alternative, albeit not entirely satisfactory, approach is disclosed in JP 2001-220455, where prepregs and laminates free from halogen and phosphorus compounds are described as having good characteristics with regard to burning resistance, heat resistance and electrical properties. The composition comprises a phenol compound (for example, bisphenol F, phenol novolac or cresol phenol novolac), secondly, an epoxidized phenol compound of the phenol compound mentioned, thirdly, a dihydrobenzoxazine (for example, having a phenol novolac or a cresol novolac backbone) and, finally, an inorganic flame retardant (for example, aluminium hydroxide, magnesium hydroxide, molybdenum oxide, molybdic acid zinc, boric acid zinc or mixtures thereof).
Thus, there is still an unmet need for improved compositions suitable, in particular, for use in FR-4 Laminate.

Composition comprising benzoxazine and epoxy resin

Huntsman Advanced Materials Americas LLC


An optical encoder and method for measuring displacement information using an optical encoder uses an encoder member with multiple digital diffractive optic regions to optically diffract an incident beam of light to produce output beams of light having intensity distribution patterns, which are used to generate electrical signals that provide relative displacement information of the encoder member.

Optical encoders use optical signals to detect mechanical positions and motions in various types of systems. The mechanical positions and motions detected by optical encoders can be related to linear or rotational displacements of moveable components, such as shafts of motors. There are two common types of optical encoders, absolute position encoders and incremental encoders. Both types of optical encoders can determine mechanical positions and motions. The absolute position encoders can determine the exact mechanical position at any moment of operation, even at power-up. The incremental encoders, on the other hand, lose the existing position data at power-down, and cannot determine the exact mechanical position at power-up. However, the incremental encoders are less expensive and require less processing power than the absolute position encoders. Thus, the incremental encoders enjoy a greater market share than the absolute position encoders.
A conventional optical encoder typically includes an encoder member positioned between a light source and a number of photodetectors. The encoder member includes a number of openings, which allow light from the light source to reach the photodetectors as the encoder member is rotated or linearly displaced with respect to the light source and the photodetectors. The photodetectors generate signals in response to incident light that can be analyzed to determine the relative speed or position of the encoder member with respect to the light source and the photodetectors.
A concern with the described conventional optical encoder is that the encoder member with the opening is relatively expensive to manufacture, which is reflected in the overall cost of the encoder.
In view of this concern, there is a need for a cost-effective optical encoder.

Intensity-based optical encoder using digital diffractive optic regions


Various embodiments relate to tags, methods of using tags, systems, and methods of using systems. Various embodiments may be suitable for identifying a human or an animal. Various embodiments may provide mother-infant matching and cot-infant matching for both single and multiple births; monitoring of the location, movement, and status of the tags; detection of tampering and unauthorized removal of infant tags; and organizing of tags.

Many hospitals use identification (ID) bands to match a newborn to his or her mother and to match a newborn to his or her cot. This method, being rather manual, requires the staff to be diligent in ensuring that the ID bands are correctly labeled when they are first attached to the mother, her newborn, and the cot. This manual method is prone to human error. For example, a staff, in her busyness, may misread the names or ID numbers and end up giving the wrong newborn to the mother, who, having just given birth, may not be alert enough to notice the error. Such a mismatch or mix-up can lead to a baby being breastfed by a wrong mother, and, in a worst-case scenario, can also lead to the mother going home with a wrong baby. One way to help prevent such a mismatch or mix-up is to use, in addition to the manual method, an electronic matching method that is less prone to human error. Such an electronic method will give the caregiver an additional level of confidence that the correct baby will always be given to the mother or placed in the cot intended for the baby.

Primary tag and a secondary tag for communication with each other, and a system comprising a primary tag and one or more secondary tags


A method for packing bodies (3), e.g. fodder bales of a generally cyclindrical or parallelpipedic configuration, in continuous material, such as plastics, comprising a support of the body and a winding of continuous material around the body from at least one magazine with continuous material while rotating the body around a first axis (7) of the body by means of a roller arrangement including at least one roller device (5'), downwards to which the body envelope surface (9) then rotates, is adapted to approach the body envelope surface. The invention also relates to a device for packing bodies.

The present invention relates to a method for packing bodies, e.g. fodder bales with an essentially cylindrical or parallelepipedic configuration, in a continous material, such as continous plastics, comprising to support the body and winding the continous material around the body from one or several magazines for continous material while rotating the body around a first axis of the body by means of a roller arrangement, comprising at least one rotatably arranged roller device.
The invention relates also to a device for performing the method.
Methods of essentially the above mentioned type are already known. According to such a known method a body, such as a bale, is supported on a table with two axially parallel and at a distance from each other arranged rolls, between which continous belts or stripes are running. The bands are arranged to rotate the bale around said first axis being essentially parallel to the roller axes. An essential problem with bales with a square or a rectangular cross section across said first axis exists, in that the bale circumferential speed is varying during each turn. From a position with the bale resting on a corner, the bale thus tilts, parts of the bale perpihery then having a speed surpassing that for a normal driven rotation. This results in a varying overlapping of the continous material, the plastics, wrinkling at the bale end portions as well as highly undesired thrust stresses in the structure, when the bale hits the roll lying in the tilting direction. Bale rotation will also become more energy consuming than necessary, when the bale must be lifted to a greater extent, when the corner/edge hits the belt. The bales might have a weight over 500 kg/m.sup.3, the tendecy being to even larger bale weights.

Method and a device for wrapping with web-shaped material


A friction stir welding tool (1) of the present invention is used for friction stir welding, and includes: a base material (2); and a coating layer (3) formed on a surface of at least a portion of the base material (2) that is to be caused to contact workpieces during friction stir welding, the coating layer (3) containing cubic WC1-x.

In 1991, a friction stir welding technique of joining metal materials such as aluminum alloys together was established in the United Kingdom. This technique joins metal materials to each other in the following way. A cylindrical friction stir welding tool having a small-diameter protrusion formed at a tip thereof is pressed against joint surfaces of the metal materials to be joined. Meanwhile, the friction stir welding tool is rotated to thereby generate frictional heat. This frictional heat causes the metal materials of the joint portion to soften and plastically flow, and thereby joins the metal materials together.
"Joint portion" herein refers to a joint interface portion where joining of metal materials by butting the metal materials or placing one metal material on top of the other metal material is desired. Near this joint interface, the metal materials are caused to soften and plastically flow, and the metal materials are stirred. As a result, the joint interface disappears and the metal materials are joined. Simultaneously with the joining, dynamic recrystallization occurs to the metal materials. Due to this dynamic recrystallization, the metal materials near the joint interface become fine particles, and thus the metal materials can be joined with a high strength (Japanese Patent Laying-Open No. 2003-326372 (PTD 1)).
When aluminum alloys are used as the above-mentioned metal materials, plastic flow occurs at a relatively low temperature of approximately 500° C. Therefore, even when the friction stir welding tool made of an inexpensive tool steel is used, little wear and tear occurs and frequent replacement of the friction stir welding tool is unnecessary. Therefore, for the friction stir welding technique, the cost required to join the aluminum alloys is low. Thus, in place of a resistance welding method for melting and joining aluminum alloys, the friction stir welding technique has already been in practical use in various applications as a technique of joining parts of a railroad vehicle, a motor vehicle or an aircraft.
In order to improve the life of the friction stir welding tool, it is necessary to improve the wear resistance and the adhesion resistance of the friction stir welding tool. Friction stir welding uses frictional heat, which is generated by friction between the friction stir welding tool and the workpieces to be joined, to cause the workpieces to soften and plastically flow, and thereby join the workpieces together. Thus, in order to increase the joining strength to join the workpieces together, it is necessary to efficiently generate the frictional heat.
PTD 1, Japanese Patent Laying-Open No. 2005-199281 (PTD 2), and Japanese Patent Laying-Open No. 2005-152909 (PTD 3) each disclose an attempt to improve the tool life through improvements of the wear resistance and the adhesion resistance of the friction stir welding tool.
For example, a friction stir welding tool of PTD 1 has a diamond film coating on the surface of a base material formed of a cemented carbide or silicon nitride. Since the diamond film is excellent in hardness and wear resistance and has a low friction coefficient, workpieces are less likely to be adhered to the friction stir welding tool. Accordingly, the workpieces can successfully be joined together.
In contrast, according to PTD 2, a probe pin and a rotator, which constitute a part of the surface of a friction stir welding tool and are to be brought into contact with workpieces, are formed of a cemented carbide containing 5 to 18% by mass of Co Because of such a content of Co, the affinity of the friction stir welding tool for the workpieces is low and the workpieces are less likely to adhere to the tool. Moreover, since a cemented carbide having a thermal conductivity of 60 W/m·K or more is used for the base material, heat is likely to be released and diffused into the outside, and buckling of the rotator and the probe pin as well as thermal deformation of the joint of the workpieces hardly occur.
According to PTD 3, a friction stir welding tool has an anti-adhesion layer that is made of any of diamond-like carbon, TiN, CrN, TiC, SiC, TiAlN, and AlCrSiN and coats the surface of a portion of the tool that is to be brought into contact with workpieces. According to PTD 3, the tool also has an underlying layer made of any of TiN, CrN, TiC, SiC, TiAlN, and AlCrSiN and provided between a base material and the anti-adhesion layer to coat the base material. The underlying layer can thus be provided to enhance the adherence between the base material and the anti-adhesion layer, make the anti-adhesion layer less likely to crack, and improve the wear resistance. Moreover, diamond-like carbon to be used for the anti-adhesion layer has a low affinity for soft metals such as aluminum and is thus excellent in adhesion resistance.

Coated rotary tool and method for manufacturing the same


A hard disc drive is comprised of a casing, a head arm located in the casing and movable in unison with a head, and a diffraction grating mounted on the head arm so as to diffract a light introduced into the casing from the outside of the casing, in which a light diffracted by the diffraction grating is introduced to the outside of the casing. Also, this hard disc drive further comprises an optical system provided outside the casing for receiving the diffracted light, the optical system detecting the arm position, a controller for controlling the arm position, and a servo signal writer for writing a servo signal on the disc on the basis of a detected signal.

1. Field of the Invention
The present invention relates to a hard disc drive (HDD) and a servo signal writing apparatus which are both suitable for detecting the head position.
2. Description of the Related Art
External control type hard disc drives are known to write a servo signal as follows:
A head arm is secured to a moving body provided outside the casing of the hard disc drive and a motion of the moving body is detected by means of some suitable methods, such as a light interference method or the like. Then, on the basis of detected results, the position of the head arm is controlled, i.e., the writing of the servo signal is controlled.
Further, there are known other hard disc drives which include a mirror attached to a head arm to detect the position of the head on the basis of motion of the mirror or other hard disc drives in which a rotary encoder and an optical system for detecting the head position are disposed within the casing thereof.
Hard disc drives are miniaturized more and hence rigidity of the head is decreased, which causes the external control type of hard disc drive to deform the head arm thereof. Also, conditions of the hard disc drives are different when in use and when in the recording mode. There is the disadvantage that a servo signal cannot be written with high accuracy as expected.
According to the above-mentioned other hard drive drives in which the mirror is attached to the head, a load applied to the head tends to change the condition of the head when in the recording mode and in use. As a result, accuracy in the writing of servo signal cannot be increased as expected and resolution also is lowered.
Further, according to the above-mentioned other type of hard disc drives in which the rotary encoder and the like are disposed within the casing, the cost of optical parts is increased.

Hard disc drive and a servo signal writing apparatus


This puzzle game system utilizes a movable base frame 12 which defines within its body a cut-out template 26 which defines a crossed word pattern. The cut-out template 26 defines at least two intersecting word files 28, with each word file 28 being oriented at an angle to each other word file with which it intersects. A plurality of movable elements 14 which are size and shape to be received within the word files 28 are provided. Each element 14 has a display surface 18 for at least one symbol 16. To play the game, one edge of one word file 28 within base frame 12 is oriented cross-wise in front of the player and a plurality of symbol bearing movable elements 14 are provided which are at least sufficient to solve the puzzle. As a next step, base frame 12 is turned to orient one edge of a different word file 28 cross-wise in front of the player, and the puzzle is again solved. This process is continued until the base frame 12 has been solved in each of its edge orientations. Then, where the base frame 12 is three dimensional and two sided and is capable of being turned-over, the base frame 12 can be turned over, and the puzzle again solved for each edge orientation thereby providing twice as many different crossed word puzzles from a single frame 12.

a) Field of the Invention
This invention relates to games and puzzles and to accessories for puzzles which are in the form of boards defining geometric patterns which are used with relatively movable elements. More specifically it relates to a board used in a game and to game pieces which are used to form words or equations with the board, but in which no predetermined or defined word or equation is required.
b) Discussion of the Prior Art
Word games are popular with the public. Common crossword puzzles are known wherein words are formed in either a defined or random matrix diagram by the player by completing definitions to a given vertical (down) column or horizontal (across) array of crossed words, hereinafter collectively referred to as "word files." Such crossword puzzle games provide a puzzle solver with clues in the form of a definition or synonym of each word in a specific or approximate "across" or "down" position of the puzzle. The puzzle solver must then determine what word corresponds with the given definition or synonym and is compatible with the word or words that is crosses, and then enter that word in the appropriate "across" word file or "down" word file in the puzzle. In order for such crossword puzzles to be operative, the player must find the already defined words, and has no discretion in forming words of his or her choice, or in playing the game in more than one way.
Another form of prior art word games, are anagrams. In playing anagrams, the game player usually reorders or transposes letters from one word or phrase to form another word or phrase. In one form of the game, players compete by selecting letters to form words of their choice, while in another form of the game they add one or more letters in sequence in a number of different directions to form words, the popular "Scrabble.RTM." word game being one form thereof. In such games the player is not limited to defined words, and has substantial discretion in forming words of his or her choice, and may play the game in more than one way.
Other forms of relevant prior art word puzzle games are based on the word search or word hunt principle. Such games are currently offered so ubiquitously that they are approaching the omnipresence of crossword puzzles. In the known patent prior art, Massey, U.S. Pat. No. 1,642,424 utilizes the word search concept, in which a puzzle is comprised of a plurality of continuous rows of letters which are printed on a sheet and arranged in a manner which is at first glance meaningless. Intermingled among the letters are words. As an aid to finding those words, a stencil or template having an opening corresponding in size and form to the spaces occupied by the words is provided. In a related invention, DeLano, U.S. Pat. No. 4,595,203, provides a puzzle reading device made from a movable plate having a number of intersecting windows for use with a word search puzzle. The puzzle reading device helps to make words which are hidden in the horizontal, vertical or diagonal rows of the word search puzzle more readily identifiable. In both of these references, and in word search and word hunt games generally, the player must find the already existing words, and has no discretion in forming words of his or her choice, or in playing the game in more than one way.
In other prior art patents, Withington, U.S. Pat. No. 1,282,513, teaches a puzzle in which a sentence on a sheet is provided, which includes a movable partition having a slot formed within it for receipt of the number of letters necessary to spell a specific missing word to complete a specific quotation or phrase. Similarly, James, U.S. Pat. No. 4,185,830, discloses a game apparatus wherein a base is provided with a plurality of rows of letters and punctuation at fixed locations and is utilized with a template and a number of letter carrying elements to form a predetermined sentence or phrase. In both of these references, the player must find only specific words or phrases, and has no discretion in forming words of his or her choice, or in playing the game in more than one way.
Mitchell, U.S. Pat. No. 2,050,498, discloses a crossword board divided into squares, and in which alphabetical indicators and key numeral indicators can be utilized in developing the complete solution for a diagramless puzzle, or, in the alternative, for use in developing a new crossword puzzle. It is noted, that there is no specific template taught by this reference. Kelly, U.S. Pat. No. 2,517,115, discloses a crossword puzzle book in which a pad of crossword puzzle solution blank leaves are located on a page with the definitions for solving that puzzle, so that more than one player can solve the puzzle on a single leaf of the pad without receiving any clues from previous players, and without giving clues to subsequent players as to the solution. While this allows the game to be played by more than one player, or for a single player to play it more than once, as with any crossword puzzle, each time that it is played the player must find the correct defined words and has no discretion in forming words of his or her choice, or in playing the game in more than one way.
Larroca, U.S. Pat. No. 2,782,530, discloses a crossword puzzle structure which is comprised of a frame for receiving a sheet of paper and a movable masking sheet for location above the sheet which allows a variety of puzzle constructions to be produced and developed. Freedman, U.S. Pat. No. 2,586,017, provides a cover for use with a number of games, including crossword puzzles, in which a transparent material having a pressure sensitive face is placed over the game to receive indications of game pieces or words.
It is thus seen that it would be desirable to provide a novel word game or puzzle wherein no predetermined word is required or defined, and in which the player may construct a multitude of puzzle solutions in a predetermined yet variable matrix frame, without requiring any directions or clues. It would also be desirable to provide such a novel game or puzzle, wherein there are many variable modes of play, and in which the degree of difficulty of the puzzle may be varied by the player.


A mechanism is provided for managing the translation look-aside buffer (TLB) of an emulated computer, in which an extension to the TLB is provided so as to improve virtual address translation capacity for the emulated central processing unit (CPU).

The present invention relates to a mechanism for managing the translation look-aside buffer (TLB) of an emulated machine.
Computers comprise a processor or central processing unit (CPU) that carries out the instructions of a computer program and is the primary element performing the function of the computer CPUs are generally associated with memory, commonly in the form of random access memory (RAM), for storing data used in the processing of the instruction by the CPU. The RAM may be addressed using virtual addressing, with the translation between virtual and real addresses commonly being managed by a memory management unit (MMU) associated with the CPU. A page table is maintained by the MMU, which comprises the translations of the virtual address space to the corresponding physical address space.
A virtual address space may be very large and searching it for a given translation may be computationally expensive or time consuming. Thus, in order to speed up virtual address translation, the MMU is arranged to maintain a specialised cache in the form of a translation look-aside buffer (TLB). The TLB is used to hold a set of entries comprising the most recently used translations between the virtual address space and the physical address space. A TLB is commonly implemented as content addressable memory (CAM). Thus, the CAM search key is a virtual address and the search result is the corresponding physical address. If the TLB is searched and the given virtual address cannot be found, the MMU proceeds to locate the virtual address in the page table. Once located, and the translation returned to the MMU, the located virtual to physical address mapping is entered in the TLB.
A problem arises when a computer is emulated, for example, where the function of a given computer or machine is synthesised by a software system. In an emulated CPU, the computational cost of a virtual address translation is commonly proportionally higher than on a non-emulated CPU. Furthermore, if changes are made in the emulated hardware, some operating systems that are designed to run on the relevant CPU may no longer run as expected or processing errors may result.

Managing the translation look-aside buffer (TLB) of an emulated machine

International Business Machines Corporation


A device for sutureless attachment of soft tissue to bone has an elongate substantially cylindrical stud and a head disposed on a proximal end of the stud. The stud has a sidewall that defines a nominal diameter and the head has a diameter that is greater than the nominal diameter. At least one barb is provided to retain the stud within bone. The at least one barb may be constructed from a shape memory alloy and the stud and head may be constructed from a bioabsorbable material.

Repair of torn soft tissue has changed dramatically over recent years. Generally, techniques for repairing soft tissue tears involve reattaching the torn tissue back to the bone from which it is avulsed. Typically, suture material is used to tie the tissue directly back to bone to facilitate healing of the tissue. Open techniques for reattaching soft tissue to bone often require large incisions, resulting in long periods of immobilization and rehabilitation for the affected tissues as well as increased morbidity resulting from the lengthy surgery.
More recently, closed techniques, and fixation devices for use in closed techniques, have been developed to relieve some of the disadvantages resulting from the use of open techniques to attach soft tissues to bone. Suture anchors are one type of device known for use in attaching soft tissue to bone in closed surgical procedures. Examples of such anchors and their use may be found in U.S. Pat. Nos. 4,898,156; 4,899,743; 5,207,679; 5,217,486; 5,417,713; and 5,522,845. Generally, a suture anchor is inserted into a preformed bore in a bone where the suture anchor fixes to an internal portion of the bone. A length of suture thread, either pre-threaded in the anchor or threaded through an eyelet in the anchor after insertion, is used to tie the injured tissue into place so that healing may occur.
In some instances, it may be preferable to attach the soft tissue to bone without the need to tie the soft tissue with suture thread. One type of device that has been developed to meet this need is the tissue tack. Tissue tacks, such as those shown in U.S. Pat. Nos. 4,976,715; 5,261,914; 5,380,334; and 5,601,558, generally have an elongate portion and a head portion. The elongate portion is passed through a hole in the tissue and into a preformed bore in a bone. The head portion has a larger diameter than the hole in the tissue and thus serves to secure the tissue to the bone when the elongate portion is inserted into the bore. Often, tissue tack devices are constructed from bioabsorbable materials so that further surgery is not needed to remove the tack when tissue mending is complete.
Generally, bone fixation elements on tissue tacks such as those disclosed in the U.S. patents listed above are limited to circumferential ridges disposed on the elongate portion of the tack which form a friction fit within the bore in the bone. While this form of bone fixation may be sufficient for patients with very high quality bone, it is insufficient for many other patients, especially older patients, who may have poor quality bone, osteopenic bone or bone that has been weakened by disuse due to pain. Accordingly, there remains a need for tissue tacks having improved bone fixation elements so that such tacks may be used with a wider variety of patients who could benefit from the use of tissue tacks.

Device for sutureless attachment of soft tissue to bone


The mounting bracket has a flange which reaches in between portions of the open office structure and releasably engages in the slots in the post of the open office structure. The releasable engagement comprises tee-shaped hooks, configured so that they engage reversibly in the slots in either of the posts on the left or right side of the office entryway opening. A web on the flange carries an identification plate.

In modern office spaces, privacy is provided to each occupant in the open office structure by providing low walls to divide office spaces. These walls are formed of commercially available sections. Posts are mounted on the floor and they extend upward. Panels usually are provided with pressure clips which attach to the posts along the post edges to create an attached structure. Suitable posts and panels create the individual spaces of the open office. It is helpful and necessary to mark individual open office spaces. Such identification is common and is usually applied by adhesive or penetrating fasteners to the wall panels. Such attachment of identification devices unavoidably marks the panels and prevents clean removal and replacement of identification devices when changes are needed or desired. There is need for an identification mounting apparatus which can be attached to the open office structure on the left or right side of the office entryway opening in such a way that it is reversible, detachable, and does not deteriorate the panel.

Reversible mounting bracket for open office identification


Examples of techniques for speculation throttling for reliability management are described herein. An aspect includes determining that a power state of a processor is above a speculation throttling threshold. Another aspect includes, based on determining that the power state of the processor is above the speculation throttling threshold, throttling speculation in the processor. Another aspect includes determining that the power state of the processor is above a power proxy threshold, wherein the power proxy threshold is higher than the speculation throttling threshold. Another aspect includes, based on determining that the power state of the processor is above the power proxy threshold, enabling a performance throttle unit of the processor.

The present techniques relate to processors. More specifically, the techniques relate to speculation throttling for reliability management in processors.
Reliability events in a computer system may impact system reliability. In order to avoid damage to the computer system from a reliability event, operations of the processor may be throttled or stopped when a reliability event is detected. Reliability management is performed in response to a condition of impending reliability concern that may be flagged by on-chip or on-system sensors. Some examples of reliability management techniques include dynamic voltage and frequency scaling (DVFS), or performance throttling of all operations in the processor via issue rate management. In DVFS, the voltage and frequency of the processor are reduced. Voltage is the main determinant of power usage and heating in a processor. The voltage required for the stable operation of a processor is determined by the frequency at which the circuit is clocked; the voltage can be reduced if the frequency of the circuit is also reduced. DVFS reduces the number of instructions the processor can issue in a given amount of time, and may therefore result in a relatively large performance drop in the processor.
A performance throttling mechanism (PTM) is responsible for reducing system performance in order to mitigate impending reliability events, such as thermal reliability issues, likely_current draw>max_current_budget, voltage droop, etc. Whenever the PTM is triggered, the execution pipeline is throttled, reducing the power consumption and voltage drop. However, the performance drop from PTM or DVFS may be very large.

Speculation throttling for reliability management

INTERNATIONAL BUSINESS MACHINES CORPORATION


A safety hood for hypodermic needles has an elongated body having a U-shaped cross-section and two ends spaced from one another in a direction of elongation with one of the ends being closed, elements for preventing undesired withdrawal of a needle from the hood provided in the body, and a pivot member provided on another of the ends and formed so that the body can be turned in a direction transverse to its direction of elongation between a first position in which the body surrounds and closes the needle and a second position in which the body is turned away from the needle and exposes the needle.

This invention refers to a safety hood for hypodermic needles. More particularly it relates to a safety hood which is designed for preventing accidental pricking of a user by a needle.
Generally, as it is known the administration of injections and blood extraction involves using syringes that, both if they are reusable or non reusable, are provided with corresponding needles carrying a removeable hood. The hood protects the needles and constitutes a safety means against the possibility of accidental pricking of the operator.
The thusly achieved safety is not complete and the possibility of accidental pricking remains as the replacing or removing of the hood is made along the length of the needle.
Presently, because of the risk of infected through blood contact with diseases like AIDS and hepatitis, the use of the hood would unavoidable be--due to the above reasons--not completely safe. Considering that a health professional may operate 300 injections or blood extractions per month and that HIV carriers and AIDS patients can be estimated to represent 0.3% of the population, a few accidental prickings mean an unacceptable risk.


A door system for providing a door that is easily constructed and has interchangeable panel members. The door system includes a frame assembly comprising a pair of frame portions. Each of the frame portions defines a window aperture of the frame assembly. The frame assembly is designed for being hingably coupled to a door frame of a house whereby the frame assembly is selectively pivoted adjacent a door of the house when the frame assembly is in a closed position. Each of a plurality of panel members is selectively coupled to the frame assembly whereby the panel members are selectively positioned in the window aperture of each of the frame portions. Each of the panel members is designed for controlling environmental communication between an interior of the house and an exterior of the house when the door of the house adjacent the frame assembly is open.

1. Field of the Invention
The present invention relates to storm doors and more particularly pertains to a new door system for providing a door that is easily constructed and has interchangeable panel members.
2. Description of the Prior Art
The use of storm doors is known in the prior art. U.S. Pat. No. 4,311,183 describes a device for selectively storing either a storm window of screen when not in use. Another type of storm door is U.S. Pat. No. 5,5540,026 having a panel that is manufactured to appear as a framed panel. U.S. Pat. No. 5,711,125 has a storage building door having enhanced weather durability.
While these devices fulfill their respective, particular objectives and requirements, the need remains for a system that has certain improved features that allows for the panels to be readily removed.


An information recording medium is provided with a plurality of information recordable recording layers, and a spiral or concentric tracks are formed on each of the plurality of recording layers. At least a portion of each track has wobbles corresponding to a wobble signal that includes layer information for discriminating the recording layer formed with the track.

Recently, due to progresses made in digital techniques and improvements made in data compression techniques, there is much attention on optical disks for storing information (hereinafter also referred to as "contents") such as music, movies, photographs and computer software. The optical disks include compact disks (CDs), digital versatile disks (DVDs) capable of recording approximately 7 times the amount of data recordable on a CD having the same diameter as the DVD. Optical disk apparatuses which use the optical disks as the information recording medium have become popular as the optical disks have become less inexpensive.
The optical disk apparatus records information on or erases information from a spiral track or concentric tracks on the optical disk by irradiating laser light on a recording layer of the optical disk, and reproduces information from the spiral track or concentric tracks based on a reflected light (returned beam) from the recording layer. Hence, the optical disk apparatus is provided with an optical pickup unit that emits the laser light and receives the returned beam.
Generally, the optical pickup unit includes an objective lens, an optical system that guides the laser light emitted from a light source to the recording layer and guides the returned beam to a predetermined light receiving position, and a photodetector that is arranged at the light receiving position. The photodetector outputs signals including not only reproduced information of data recorded in the recording layer, but also information (servo information) necessary to control the position of the objective lens.
The amount of information of the contents is increasing every year, and there are demands to further increase the recording capacity of the optical disk. As one means of increasing the recording capacity of the optical disk, information recording media having a plurality of recording layers and apparatuses which use such information recording media as the access target have been developed. For example, such information recording media and apparatuses which use such information recording media as the access target are proposed in Japanese Laid-Open Patent Applications No. 2001-52342, No. 2002-74679, No. 2003-91874, No. 8-147762, No. 11-96568 and No. 2002-334448.
In order to control the position of the objective lens with respect to the information recording medium having a plurality of recording layers so that a light spot is accurately formed at a target position, it is necessary to accurately discriminate the recording layer on which the light spot is formed. In addition, in order to achieve a high-speed access, the position of the objective lens must be controlled at a high speed. However, according to the information recording media and the apparatuses proposed in the Japanese Laid-Open Patent Applications No. 2001-52342, No. 2002-74679, No. 2003-91874, No. 8-147762, No. 11-96568 and No. 2002-334448 referred above, it sometimes takes time to discriminate the recording layer on which the light spot is formed, and the access time may become long.

Information recording medium having a plurality of recording layers