A heat sink structure of a module substrate includes a plurality of stripe-like bottom regions extending in a longitudinal direction and repeated in a lateral direction with a predetermined pitch, a plurality of stripe-like top regions extending in said longitudinal direction and repeated in the lateral direction with said predetermined pitch, such that the stripe-like bottom regions and the stripe-like top regions are repeated alternately in the lateral direction, wherein the stripe-like top regions and the stripe-like bottom regions have respective lateral edges that are connected with each other by cooling fins.

The present invention generally relates to electronic apparatuses and more particularly to a heat sink structure adapted for mounting on a substrate of an electronic apparatus for cooling the same.
With recent developments in high speed computers and other electronic processing apparatuses, there is a demand for increasing the mounting density of module substrates that are used for carrying a circuit module. However, such an increased mounting density has led to a problem of increased heat generation. Therefore, there is an acute demand for a more efficient heat sink structure characterized by a reduced thermal resistance for heat dissipation, for module substrates.
Generally, heat sinks of module substrates have a size corresponding to the size of the module substrate itself and may have a size as large as 70 mm for each edge. Such a heat sink having a large size and designed for mounting directly upon the module substrate, is required to have a small rigidity such that the difference in the thermal expansion between the heat sink and the substrate is effectively absorbed. In recent electronic apparatuses, as a result of the increased mounting density of the substrates or mother boards within the electronic apparatuses, there is a tendency that the substrates are disposed relatively to each other with a decreased separation.
When air cooling an electronic apparatus having such a structure by air, it is preferable to apply the cooling air so as to flow generally parallel to the substrates rather than applying the cooling air perpendicularly to the substrate. Thereby, one can simplify the construction of the apparatus and reduce the space needed for cooling.
Therefore, it has been desired to provide a heat sink that is: (1) applicable to the cooling system wherein the cooling air flows parallel to the circuit substrate; (2) characterized by a small thermal resistance; and (3) characterized by a small rigidity.
FIGS. 1(A) and 1(B) show an example of a conventional heat sink 10 that is disclosed in the Japanese Laid-open Patent Publication 59-202657.
Referring to the drawings, the heat sink 10 includes a number of cooling fin elements 11 connected with each other in X- and Y-directions by a base 12 to form a matrix, wherein each fin element 11 has a top surface formed with a hole 13.
Each of the cooling fin elements 11 is formed with a cutout 14 that penetrates into the element 11 in the X-direction and another cutout 15 that penetrates into the element 11 in the Y-direction. Further, there is formed a gap between adjacent cooling fin elements 11 wherein, in correspondence to the gap, there are formed grooves 16 and 17 such that the groove 16 extends in the X-direction parallel to the cutout 14 and the groove 17 extends in the Y-direction parallel to the cutout 15. The heat sink 10 is mounted on a module substrate by soldering the base 12 thereon.
The heat sink 10 of FIGS. 1(A) and 1(B) is cooled by applying a flow, or jet, cooling air 20 vertically from the upward direction. Thus, the construction of FIG. 1 requires a duct structure immediately above the heat sink 10 for directing the cooling air, such a duct structure increases the size, particularly the height of the apparatus. Therefore, the construction of FIGS. 1(A) and 1(B) has an obvious drawback in that one cannot increase the mounting density of the substrate boards within an electronic apparatus.
FIG. 2 shows another heat sink 30 disclosed in the Japanese Laid-open Patent Publication 56-122149.
Referring to FIG. 2, the heat sink 30 includes a heat conduction base 31, and a plurality of fins 32 are provided vertically on the base 31 with a separation from each other. Each fin 32 is formed with a number of slits 33 with a separation from each other in the X-direction by a predetermined interval, wherein the slits are formed to extend in the Y-direction over the entire length of the heat conduction base 31. Further, a passage 34 of cooling air is formed between the adjacent fins 32. The heat sink 30 is mounted upon the module substrate by soldering the heat conduction base 31.
In the case of the heat sink 30 of FIG. 2, a cooling air flow 50 is applied in the X-direction parallel to the module substrate (of which illustration is omitted in the drawing). As a result of such a construction, one can eliminate the duct structure to direct the air. Thus, the construction of FIG. 2 is suitable for increasing the mounting density of the module substrates within the electronic apparatus.
On the other hand, the construction of FIG. 2 still has a drawback in that one cannot satisfactorily reduce the thermal resistance R between the heat sink and the air. Generally, the thermal resistance R of a heat sink for dissipating the heat of a module substrate to the air is represented as EQU R=t/(.multidot.A)+1/(h.multidot.A.sub.f) (1)
wherein represents the thermal conductivity of the heat sink, A represents the area of the heat conduction base of the heat sink, t represents the thickness of the heat conduction base, h represents the heat transfer coefficient on the fin surface for dissipating heat to the air, and A.sub.f represents the surface area of the fin that is contacted by the cooling air.
FIG. 3 shows the heat dissipation caused by a heat sink 40 schematically.
It will be noted that the heat sink 40, includes a fin part 41 for dissipating heat to the air and a heat conduction base 43 for conducting the heat from a module substrate 42 to the fin 41. As indicated by an arrow 45, the heat generated at the module substrate 42 is conducted to the fin 41 via the heat conduction base 43 and the heat is transferred to the air from the fin 41 as indicated by an arrow 46.
In the foregoing Eq.(1), the first term, t/(.multidot.A), represents the thermal resistance Ra that is encountered when conducting the heat of the module substrate 42 to the fin 41 via the heat conduction base 43. On the other hand, the second term 1/(h.multidot.A.sub.f) represents the thermal resistance Rb that is encountered when dissipating heat as in FIG. 3 from the fin 41 to the air.
Returning to FIG. 2 again, it will be noted that the passage 34 of the air has a U-shaped cross section characterized by an open top 35. Thus, the passage 34 communicates to the part above the heat sink 30 where the resistance to the air flow is minimum. On the other hand, the cooling air that has entered into the passage 34 experiences a resistance caused by the friction at the surface of the fin 32, and the speed of the air decreases gradually due to the pressure loss occurring in the passage 34. Thus, when the heat sink 30 is formed to have a size of more than 70 mm in the X-direction, the cooling air cannot pass the full length of the passage 34 and, instead, escapes in the upward direction as indicated by an arrow 51. Thus, the part of the heat sink 30 that is located downstream of the point where the escape of the cooling air occurs, is no longer effectively cooled by the air flow, and the efficiency of cooling is degraded significantly.
FIG. 4 explains the foregoing phenomenon.
Referring to FIG. 4, it will be noted that the area of a fin 32 that is cooled by the air is designated as S.sub.1 and S.sub.2, while S.sub.3 and S.sub.4 represent the total area of the fins 32. As will be noted, the area S.sub.1 or S.sub.2 that is actually cooled by the air is substantially smaller than the total area S.sub.3 or S.sub.4. In a typical example, the proportion of the area S.sub.1 or S.sub.2 with respect to the area S.sub.3 or S.sub.4 is about 60%. This indicates that the effective area A.sub.f of Eq.(1) is about 60% of the actual surface area of the fin. Thus, it has been difficult to reduce the thermal resistance R in the conventional heat sink structure.
The heat sink structure 30 of FIG. 2 has another drawback in that the structure cannot absorb the thermal deformation caused particularly in the Y-direction. It should be noted that the heat sink structure 30 has a reduced rigidity with respect to the deformation in the X-direction due to the formation of the number of slits 33. As a result, the thermal stress between the heat sink 30 and the module substrate is successfully suppressed with respect to the X-direction. In the Y-direction, on the other hand, the heat sink 30 has a high rigidity and the difference in the thermal expansion between the heat sink 30 and the module substrate directly leads to a thermal stress that acts upon the interface wherein the heat sink 30 is bonded upon the module substrate. In a typical example wherein aluminum is used for the heat sink, the heat sink has a thermal expansion coefficient of about 24.times.10.sup.-6 /.degree.C. On the other hand, a typical ceramic module substrate has a thermal expansion coefficient of 4-7.times.10.sup.-6 /.degree.C. Thus, it will be noted that the thermal expansion coefficient of the heat sink is four-six times larger than that of the ceramic substrate. Such a large difference in the thermal expansion inevitably causes a large thermal stress acting at the interface between the heat sink and the substrate as mentioned above, and there is a substantial risk that the bonding of the heat sink may come off or the module substrate is cracked. Such a tendency appears conspicuous with increasing performance of the electronic apparatuses and increasing heat generation of the module substrate. Further, such a tendency is enhanced with a increasing size of the module substrate.

Heat sink structure for cooling a substrate and an electronic apparatus having such a heat sink structure


A power supply control circuit for controlling a power supply circuit having a DC/DC converter is provided. A discharge circuit operates based on a discharge instruction signal for instructing discharge and uses a switching element to remove charges of a capacitor connected to an output terminal of the DC/DC converter. An overvoltage detecting circuit outputs a detection signal when a potential at the output terminal of the DC/DC converter exceeds a predetermined potential. A level conversion circuit outputs a signal obtained by converting a potential applied to the switching element of the discharge circuit. A logic circuit performs a logic operation between an inverted signal of a start-up signal, the detection signal, and the signal obtained by converting the potential, and outputs a failure detection signal representing a failed state of the power supply circuit.

1. Field of the Invention
The present invention relates to a power supply control circuit, electronic device, and printing apparatus and, more specifically, to detection of a failure in a power supply circuit having a DC/DC converter.
2. Description of the Related Art
In general, OA equipment having a mechanical part, such as a copying machine or printer, requires at least two types of power supplies having different voltages: a power supply (power supply for generating logic voltages of, e.g., +5 V and +3.3 V) for a logic circuit system for controlling the equipment and a power supply (power supply for generating driving voltages of, e.g., +24 V and +20 V) for a mechanism driving system.
Of the two types of power supplies, the power supply of the driving system must ensure safety for a serviceman and user in maintenance of a driving system component, and save power when the equipment stands by. To meet these requirements, the power supply voltage of the driving system needs a switch for switching the connection state, and must rise and fall in accordance with a specified sequence.
Driving of the equipment upon generation of a state such as an overvoltage in the power supply may deteriorate a driven portion or cause a failure. Thus, driving of the equipment must be avoided upon generation of an overvoltage in the power supply.
The above-mentioned overvoltage is a typical failure of the power supply output. To avoid such an anomaly, a conventional power supply control system suppresses, to a minimum time, a state in which the power supply sequence reverses upon generation of an anomalous output voltage (low voltage or overvoltage) from the power supply unit, or decreases the generation frequency of this state. This measure can avoid malfunction of a logic circuit for driving a load, or prevent deterioration and failure of the load.
For example, Japanese Patent Laid-Open No. 5-204496 discloses a method of turning off the power supply in correspondence with a power supply anomaly signal transmitted from a power supply unit in an arrangement having a plurality of power supply units. According to the method described in Japanese Patent Laid-Open No. 5-204496, at the same time as detection of a power supply anomaly signal, a power supply OFF signal is transmitted to a power supply unit which generated a power supply anomaly and a power supply unit equal to or higher than the anomalous power supply unit in output voltage. A power supply OFF signal is transmitted in accordance with a predetermined power-off sequence to a power supply unit lower in output voltage than the power supply unit which generated the power supply anomaly.
Japanese Patent Laid-Open No. 2000-188829 discloses a method of, when an anomaly occurs in the power supply sequence of a power supply unit, specifying a doubtful power supply unit and clearing up the cause of an operation error by the anomaly of the power supply sequence. According to the method described in Japanese Patent Laid-Open No. 2000-188829, the output power supply voltage of each power supply unit is compared with a specified value at the timing of rising of a power supply output. A doubtful power supply unit is specified on the basis of a logic signal representing the comparison result.
Both the methods described in Japanese Patent Laid-Open Nos. 5-204496 and 2000-188829 detect an anomaly in a power supply sequence when the voltage rises, but do not detect any anomaly in a power supply sequence when the voltage falls.
As for a device requiring periodic exchange of expendables and periodic maintenance, like OA equipment, it is also important to ensure safety in maintenance in addition to preventing deterioration and failure of the load. That is, it is necessary to ensure safety for a serviceman and user when performing maintenance or exchanging expendables. To meet this demand, the power supply voltage must reliably fall to GND level in a falling (power supply-off) sequence, and a generated failure must be detected.

Power supply control circuit, electronic device, and printing apparatus


A user equipment (UE) includes one or more non-transitory computer-readable media having computer-executable instructions embodied thereon, at least one processor coupled to the one or more non-transitory computer-readable media, and configured to execute the computer-executable instructions to receive a logical channel group (LCG) list having a plurality of logical channels in one or more LCGs, where grouping of the plurality of logical channels is based at least in part on a mapping policy between each of the plurality of logical channels and one or more numerology factors. The at least one processor is further configured to execute the computer-executable instructions to request for a numerology-specific uplink radio resource for one of the one or more LCGs through a buffer status report (BSR), wherein the BSR includes a LCG ID identifying the one of the one or more LCGs.

In fourth generation (4G) wireless communication systems (e.g., long term evolution (LTE), evolved LTE (eLTE), or LTE-Advanced (LTE-A)), a base station (e.g., evolved Node B (eNB)) can allocate orthogonal resources (e.g., time and frequency) to user equipment's (UEs) under its coverage, so that the UEs can share the radio resource (e.g., uplink/downlink) simultaneously. That is, the radio resource allocated by the base station to a specific UE cannot be used by other UEs. When a UE has uplink data that needs to be transmitted, the UE needs to request an allocation of uplink radio resource from the base station. The uplink radio resource requesting procedure is referred to as a buffer status report (BSR). For example, the BSR is transmitted from the UE to the base station, and contains information on the amount of data in each logical channel group that is ready for uplink transmission in the UE's buffers.
In the next generation (e.g., 5G) wireless communication networks, also referred to as New Radio (NR), a logical channel may be mapped to different numerologies (e.g., multiple TTIs and/or sub-carrier spacings and/or cyclic prefix). In order to support diverse use cases, (e.g., enhanced mobile broadband (eMBB), massive machine type communications (mMTC), and ultra-reliable low latency communications (URLLC)), which have a greater variety of quality of service (QoS) requirements than the 4G wireless networks, the physical layer of a UE in NR wireless networks needs to be more flexible to support multiple numerologies.
A numerology with a shorter TTI length would be more helpful in reducing latency as compared to a numerology with a longer TTI length. However, a numerology with a longer TTI length could be useful for resource efficiency aspects for other use cases.
For example, URLLC with ultra-low latency requirements may benefit from transmitting data with short TTIs, while eMBB communications may focus on achieving high throughputs and not so stringent on short TTI requirements. Since the UE may perform several applications simultaneously in an NR network, with each application generating data for transmission with different QoS requirements and different TTIs, it is desirable for a single MAC layer to support one or more numerologies, and a radio bearer/logical channel that can be mapped to multiple numerologies (e.g., TTI durations).
Since a logical channel can be mapped to multiple numerologies in NR, the BSR by a UE can provide more precise information in the radio resource allocation request. Moreover, the conventional BSR and related behaviors (e.g., BSR retransmission, periodic BSR reporting and scheduling request (SR) triggering) in the legacy LTE systems need to be modified to support multiple numerology factors.
Hence, it is desirable for the radio resource allocation procedure, for example, performed by the base station to take into account of the UE's specific needs or demands when allocating radio resource to the UE in order to improve the overall efficiency of the radio resource utilization.
In addition, in the current LTE system, the buffer status is reporting on a logical channel group (LCG) basis, which accumulates resource requests from all of the logical channels (LCHs) belonging to the LCG. However, since the numerology mapping for each LCH can be different, it is desirable to have a new BSR format for reporting buffer status on a LCH basis in order to have more precise reporting.

Evolved buffer status report supporting multiple numerology factors


A graphic processing unit having multiple computational elements flexibly interconnected to memory elements provides for data compressors/decompressors in the memory channels communicating between the computational elements and memory elements to provide an effective increase in bandwidth of those connections by the compression of data transferred thereon.

The present invention relates to graphics processing units (GPUs) and in particular to a method of accelerating processing by such units by compressing data subject to transfer between GPUs and their off-chip memory.
GPUs) provide a computer architecture specialized for graphics processing but they may also work with a conventional computer processing unit (CPU) to accelerate highly-parallel general-purpose applications. In this regard, GPUs provide for a large number of computational elements that may operate in parallel on data held in special GPU memory.
In normal operation, the CPU prepares data to be operated on by the GPU and loads that data into the GPU memory together with information about the desired GPU functions to be performed. The multiple computational elements then execute the desired functions and the data is returned to the CPU memory from the GPU memory.
The normal problems of long latency related to access by the computational elements to off-chip memory can be readily accommodated in a GPU by flexibly switching the computational elements to a different thread (context switching) when a given thread is facing a memory access delay. Since such switching is "lightweight" in a GPU because the GPU has a large register file so that multiple "in-flight" threads do not need to move their data from the register file to a secondary memory. For this reason such switches between threads can be accomplished rapidly with little delay, making this an effective strategy for dealing with memory latency.

Memory-link compression for graphic processor unit


A structure of via hole of electrical circuit board includes an adhesive layer and a conductor layer that are formed after wiring is formed on a carrier board. At least one through hole extends in a vertical direction through the carrier board, the wiring, the adhesive layer, and the conductor layer and forms a hole wall surface. The conductor layer shows a height difference with respect to an exposed zone of the circuit trace in the vertical direction. A conductive cover section covers the conductor layer and the hole wall surface of the through hole. The carrier board is a single-sided board, a double-sided board, a multi-layered board, or a combination thereof, and the single-sided board, the double-sided board, and multi-layered board can be flexible boards, rigid boards, or composite boards combining flexible and rigid boards.

1. Field of the Invention
The present invention relates to the field of via hole of electrical circuit board, and in particular to a structure of via hole of electrical circuit board and a manufacturing method thereof.
2. The Related Arts
A printed circuit board (PCB) is a vital electronic component and is also a support for electronic devices and parts, serving as a provider of connection of wiring of electronic parts. A conventional circuit board applies a process of printing etching resist to make wiring and patterns of circuit and is thus referred to as a printed circuit board or a printed wiring board. Since electronic products are getting smaller and more elaborate, most of the modern-day circuit boards are made by means of attaching resist (laminating or coating), and are then subjected to exposure and development, followed by etching to complete the manufacture of a circuit board.
A process conventionally adopted to make a via hole in a circuit board is to first provide a carrier board having upper and lower copper foil layers and adhesive layers. A drilling operation is then performed and a conductive cover portion is electroplated. Afterwards, the carrier board is subjected to coating of dry film, exposure, development, and etching to form a plurality of etched areas. Finally, laminating is applied to the etched carried board.
However, the conventional process of making via hole in circuit board is a process that first performs drilling and electroplating and etching is thereafter performed. The flow of operation is simple, but often suffers the following shortcomings (1) The thickness of the carrier board become inhomogeneous and this leads to poor yield rate of fine wiring process. (2) Impurity may be generated in the process of electroplating and this leads to reduced yield rate of image transfer and etching operation. (3) Size stability of the carrier board deteriorates and this leads to imprecise alignment for exposure. (4) The structure of the carrier is changed and this easily leads to poor flexibility. Consequently, further improvement can be made on the known process of making structure of via hole in circuit board.

Structure of via hole of electrical circuit board


A self-adjusting solar light transmission (daylighting) apparatus includes a sunlight concentrating member (e.g., a lens array) for concentrating direct sunlight in focal zone regions disposed inside a sheet containing an evenly-distributed stimuli-responsive material (SRM) that has a relatively high transparency state in the absence of concentrated sunlight, and changes to a relatively opaque (light scattering or absorbing) state in small portions located in the focal zone regions in response to concentrated direct sunlight. Thereby, 80% or more of direct sunlight is prevented from passing through the apparatus, but 80% or more of diffuse light is passed. The outer sheet surfaces are locally parallel (e.g., planar) such that sunlight scattered by the light-scattering SRM portions is transmitted by total internal reflection through the remaining transparent sheet material, and outcoupled to one or more optional solar energy absorbing structures (e.g., heatsinks or PV cells) disposed along the peripheral edge of the sheet.

Architectural daylighting is the practice of placing windows http://en.wikipedia.org/wiki/Window or other openings and reflective surfaces so that, during the day, natural light provides effective internal lighting within a building structure. Particular attention is given to daylighting while designing a building when the aim is to maximize visual comfort or to reduce energy use, for example, from the reduced use of artificial (electric) lighting. One form of architectural daylighting involves utilizing a transparent or semitransparent sheet (e.g., glass) strategically mounted on a roof or vertical side wall of a building such that daylight is able to enter interior spaces of the building. In this way, sunlight is used to reduce our dependence on conventional (e.g., oil, coal and gas) energy sources.
Architectural daylighting arrangements are typically designed to deal with two types of daylight: diffuse (indirect) light and direct sunlight. Diffuse light is made up of non-parallel light beams originating from the sky hemisphere and possibly as scattered or reflected light from various physical objects in our environment. Diffuse light arrives at a give point with a low intensity (luminance) but since the angular zone of origin is large, it has a significant contribution to the light flux (e.g. −15% on a clear day). Diffuse light has particularly beneficial properties for daylighting. In contrast, direct sunlight is made up of approximately parallel light beams received directly from the sun, and has a relatively high intensity (luminance) in comparison to diffuse light. The ideal architectural daylighting arrangement attempts to maximize the amount of diffuse light allowed into a room/building while minimizing the amount of admitted direct sunlight in order to avoid undesirable high radiance areas, undesirable fluctuations of the lighting level, and/or excessive solar heating.
A problem with existing daylighting devices (e.g., clear, tinted or textured glass) is that these devices typically either allow too much direct sunlight or not enough diffuse light. Clear glass maximizes the amount of diffuse light transmitted into a room, but also allows too much direct sunlight during certain portions of the daylight hours. Tinted or textured glass serves to reduce the amount of direct sunlight, but typically at the cost of reducing the amount of diffuse light as well. The underlying disadvantage is that conventional systems have approximately similar transmission for direct and diffuse light.
What is needed is a solar light transmission apparatus that maximizes the amount of transmitted diffuse light, but minimizes the amount of transmitted direct sunlight. To achieve this, what is furthermore needed is a solar light transmission apparatus that in operation exhibits pronouncedly different transmission for direct and diffuse light, respectively.

Self-adjusting solar light transmission apparatus


A balun network is provided having first and second conductor portions symmetric along a center line therebetween. A connecting conductor portion 130 couples ends of the first and second conductor portions with a spacing therebetween. The first and second conductor portions have a like-length of one-quarter wavelength. A balanced port 140 is provided between a first end of the first conductor portion 110 and a first end of the second conductor portion 120. An unbalanced port 150 is provided between a ground reference plane 160 and a first end of the first conductor portion.

1. Technical Field of the Invention
The present invention relates to balun networks and, more particularly, relates to a compact balun network having doubled-back sections.
2. Discretion of the Related Art
A balanced-unbalanced network, or balun network, typically has a transmission line of one form or another occupying physical space. As electronic devices become smaller in size, compact balun structures are desired.
Balun networks connect between an unbalanced port and a balanced port to couple balanced and unbalanced transmission lines. A 50 Ohm coaxial cable is an example of an unbalanced transmission line and a 300 Ohm twin-lead wire is an example of a balanced transmission line. Transmission lines are used internal to radios, on printed circuit boards, and in series with the inputs and outputs of components. A more compact balun structure is desired, particularly for use in a portable radio.

Compact balun network of doubled-back sections


A plug-in hybrid electric vehicle (PHEV), which has an engine and a motor and travels using a power of the engine and an electric power of the motor, includes: a battery configured to supply a drive energy of the motor; a battery sensor configured to measure a state of charge (SOC) of the battery; and a controller configured to estimate an average mileage per cycle established using traveling information of the vehicle, estimate an average SOC per cycle using the measured SOC, and control a reference power needed for driving the engine according to the estimated average mileage and the estimated average SOC.

A vehicle can be classified into an internal combustion vehicle (general engine vehicle), a hybrid electric vehicle, and a fuel cell electric vehicle (FCEV) according to power sources for generating driving force.
The hybrid electric vehicle includes a motor and an internal combustion engine, drives on the road using mechanical power of the engine and electric power of the motor, and operates the motor using a battery.
A driving mode of the hybrid vehicle may be classified into three modes, i.e., an electric vehicle (EV) mode, a hybrid electric vehicle (HEV) mode, and an auto mode. During the EV mode, the hybrid vehicle is driven only using electric power of the motor. During the HEV mode, the hybrid vehicle is driven using a combination of engine power and electric power of the motor. During the auto mode, the hybrid vehicle is driven by properly distributing engine power and electric power of the motor.
While state of charge (SOC) of the battery of the hybrid vehicle is variably controlled by engine operation based on a driving state, the engine operation is dynamically changed, such that it is impossible for the hybrid vehicle to immediately reflect the driving state into SOC control of the battery. In order to address this issue, an improved plug-in hybrid electric vehicle (PHEV) has recently been developed.
The PHEV has a relatively larger battery capacity than a conventional HEV, such that the PHEV has a higher degree of freedom than the conventional HEV in terms of fuel efficiency control, and the PHEV can be controlled in various ways using the larger battery capacity and higher degree of freedom. For example, when the PHEV travels a short distance within a commuting distance, the PHEV can charge a high-voltage battery with external power, such that the PHEV may travel in the EV mode or a charge depleting (CD) mode. During middle-distance or long-distance traveling of the PHEV, the PHEV may generally enter the auto mode so that the PHEV is driven in the auto mode in which engine power and motor power are properly distributed until reaching a destination, resulting in optimum efficiency of the PHEV. Typically, when a requested power is considered high on the basis of a requested power level or torque during the auto mode, the PHEV may use the engine. When a requested power is considered low on the basis of a requested power level or torque during the auto mode, the PHEV may be controlled to select a power source having a maximum instantaneous efficiency using electric power.
After a destination is first established, the PHEV may guarantee a control performance in the auto mode using information associated with the destination. After the destination is established, the PHEV may receive a distance from a navigation system to the destination as an input, may control a power source during the auto mode, may change a reference power needed for engine startup according to the distance to the destination, and may reduce the engine startup reference power in proportion to the increasing distance to the destination.
However, when a driver drives the PHEV on a favorite route or the like, the driver may frequently forget to set a destination so that the PHEV is unable to recognize a distance to the destination and it is impossible for the engine startup reference power to be changed according to the distance to the destination, resulting in reduction of fuel efficiency and difficulty in control performance during the auto mode.

Vehicle and method for controlling engine startup reference power


A charged particle multi-beam inspection system comprises a beam generator directing a plurality of primary charged particle beams onto an object to produce an array of beam spots; an array of a first number of detection elements generating detection signals upon incidence of electrons; imaging optics imaging the array of beam spots onto the array of detection elements; wherein the beam generator includes a multi-aperture plate having an array of a second number of apertures greater than the first number; wherein the beam generator includes a selector having plural different states, wherein, in each of the plural different states, the apertures of a different group of apertures are each traversed by one primary charged particle beam, wherein a number of the apertures of the different group of apertures is equal to the first number.

A conventional charged particle beam inspection system in which a plurality of particle beams is directed onto an object is known from WO 2005/024881. The system is an electron microscope in which a plurality of primary electron beams are focused in parallel to form an array of primary electron beam spots on the object. Electrons generated by the primary electrons and emanating from respective primary electron beam spots are received by a charged particle imaging optics to form a corresponding array of electron beams which are supplied to an electron detection system having an array of detection elements such that each electron beam is incident on a separate detection element. Detection signals generated from the detection elements are indicative of properties of the object at those locations where the primary electron beam spots are formed.
By scanning the array of primary electron beam spots across the object, it is possible to obtain an electron microscopic image of the object. It is desirable to obtain images at a high resolution, uniform resolution and a high throughput.

Charged particle multi-beam inspection system and method of operating the same


A system and method for providing a personalized recommendation from a series of partial preferences is presented. A preference distribution of a population including a plurality of weighted ranked lists is identified. A revealed preference of a user is compared to the plurality of ranked lists. An affinity weight between the user and each of the plurality of ranked lists is assigned, and a weighted average of each of the affinity weights is taken.

Existing recommendation systems, such as, but not limited to, Netflix five star ratings, Pandora like/dislike ratings, and other systems, utilize roughly the following methodology:                1) Illicit feedback for a given 'product.' Since this is feedback for a single product the feedback is necessarily delivered as some type of score (for example, like vs. don't like, one star vs. two stars vs. five stars, and other types of scores).        2) Build a customer profile based on how the customer rated various products.        3) Make recommendations to customers by first finding customers 'like' the customer in question and then recommending products that similar customers rated highly. The notion of 'likeness' here is typically defined on the basis of similarity in ratings across rated products.
This prior system has a number of flaws, the most obvious of which is the following: what 'three stars' for a particular product might mean varies both across customers (for example, five stars for a first reviewer is equivalent to three stars for a second reviewer) as well as over time for a given customer (for example, mood might determine how generous a reviewer is with stars). This makes it essentially impossible to get a high fidelity picture of the relative likes and dislikes of a customer both because it becomes difficult to find 'like' customers, and also because the language the customer uses in relating her preferences is itself changing.
Therefore, there is a need for a system and method for providing personalized recommendations.

System and method for providing personalized recommendations


Information streams are integrated with context information objects and processing instruction objects. The integrated information streams are received by a solution manifold and transformed in accordance with the context information objects, the instruction objects, and logic inherent in the solution manifold. The transformed information is then viewed by a client of the solution manifold. The client may also impose different transformation rules and context information on the transformed information and return those transformation rules and context information to the solution manifold to revised the manner in which integrated data is subsequently transformed. Additionally, the solution manifold logic may be overruled by the instruction objects and/or updated by the instruction objects.

In complex systems, many kinds of data are relied upon to obtain results. Integrating and making sense of these disparate kinds of data is a challenging task. For example, in the context of Battle Management Command Control and Communications (BMC3) systems, position and identification of friendly, neutral, and enemy actors needs to be determined quickly based on a wide variety of possible data types. Data types to be utilized include infrared (IR), microwave, radar, electronic intelligence, human intelligence, unmanned aerial vehicle (UAV), network monitoring, application management, and procurement systems to name a few.
Systems have been developed to tackle these complex tasks. However, the software developed typically falls in one of 2 categories: Hard coded for scalability and performance, or data driven. Hard coded solutions cannot be reconfigured without development of a new release by programmers. On the other hand, data driven approaches quickly go out of control as the number of rules grows and exceptions become the rule. In both cases, the problem is that these systems are not adaptive—they utilize an architecture that is either predetermined or cumulative. In neither case is the architecture adaptive to changes in environment.
The typical architectures also break down information into data, losing critical context information in the process. Data driven solutions attempt to resolve this problem by storing business rules and other context information, but in systems where exceptions are the rule this approach can quickly get out of control.
Another problem is that such systems as have been deployed do not provide for real time solutions—the decision makers are made to wait for the information while the system slowly prepares it for presentation. In certain fast moving situations (e.g., battle, air traffic control), timeliness of the information is important to minimize risk of human life.
While technology evolves new ways of generating data, it takes a very long time to integrate these new data generating means into current decision system architectures. That is because the system must be re-programmed to accept something new or new rules must be developed following pre-ordained rule semantics from a type of sensor (or source of data) that was not envisioned when the most recent release of the system was made.
Thus, what is needed is a way to integrate and make sense of disparate kinds of information in a way that is adaptive to operational needs, provides real time solutions, and is adaptive to incorporating information received from newly developed technology.

This patent is subject to a terminal disclaimer.


An improved running light fixture that includes a user aimable flood light attached to the convention running like support shaft and plug. The flood light is provided with strobe mechanism for providing a strobe effect that may be used by the boater to attract the attention of other boaters who could then come to provide assistance.

The present invention relates to removable boat running light fixtures that include a plug-in power supply and light support stem that has a bottom plug portion that is plugged into the electrical power running light socket provided at the front of a boat and a RED/GREEN running light fixture mechanically mounted in connection with a top end of the plug-in power supply and light support stem and in electrical connection with the bottom plug portion of the plug-in power supply and light support stem such that electrical power is delivered to the lights within the RED/GREEN light fixture from the electrical power running light socket provided at the front of a boat when the bottom plug portion is plugged into the electrical power running light socket of the boat; the improvement includes providing a high intensity driving flood/strobe light assembly in mechanical connection with the RED/GREEN running light fixture and providing a multi-directional pivot joint between the top end of the plug-in power supply and light support stem and the combination RED/GREEN running light and the high intensity driving flood/strobe light assembly such that a user can aim a light beam emitted from the high intensity driving flood/strobe light assembly in a desired direction prior to driving the boat during dim or dark ambient light conditions; the high intensity driving flood/strobe light assembly being supplied with power from the bottom plug portion of the plug-in power supply and light support stem and including a three position switch, a flood lamp assembly and a strobe control circuit including a strobe lamp power output, a power input and a variable output strobe intensity control mechanism; the switch power input of the three-position switch being wired in connection with the bottom plug portion of the plug-in power supply and light support stem such that when the three-position switch is in an xe2x80x9coffxe2x80x9d position, an open circuit exists between the switch power input and both the flood lamp assembly and the power input of the strobe control circuit; when the three-position switch is in a xe2x80x9cflood lamp onxe2x80x9d position, a closed circuit exists between the switch power input and the flood lamp assembly causing it to continuously illuminate and an open circuit exists between the switch power input and the power input of the strobe control circuit; and when the three-position switch is in a xe2x80x9cstrobe lamp onxe2x80x9d position, an open circuit exists between the switch power input and the flood lamp assembly and a closed circuit exists between the switch power input and the power input of the strobe control circuit causing the strobe control circuit to cause the strobe lamp power output to intermittently apply strobe power to the flood lamp assembly at a rate determined by the position of the variable output strobe intensity control mechanism.
It is often difficult for the driver/pilot of a boat to pilot/driver the boat in dim or dark conditions, especially when the boat must be driven/piloted in shallow, narrow canals and/or bayous such as those that exist all over the lower portion of South Louisiana. Although the boat driver/pilot could hold a spot light with one hand to find the banks and other hazards as the boat moves through the water in the darkness, this practice is dangerous as the boat driver/pilot needs one hand to steer the boat while using the other hand to simultaneously control the speed and forward/reverse direction of the boat motor. Attempting to steer and control the boat motor with one hand while handling a spot light with the other hand can result in serious injuries to the boat driver/pilot and also any occupants of the boat should the driver/pilot run into a submerged log, a sandbar, or under low overhanging tree limbs. It would be a benefit, therefore, to have a high intensity flood light that could be mechanically attached to the very front of the boat. Because the floodlight is attached to the very front of the boat and aimed in an initial desired direction by the boat driver/pilot, the driver/pilot is able easily aim the beam form the floodlight in the required direction by steering the front of the boat slightly in the direction to be illuminate while still having the ability to rapidly reverse the engine, slow down, and/or steer around a hazard. Because boats vary, the user must be able to aim the floodlight for viewing from his particular driving/piloting location, it would be desirable if the floodlight was attached to a support with a multi-direction pivot mechanism to allow the beam of the headlight to be properly aimed. In addition, because the floodlight would not be needed during daylight hours, it would be a further benefit if the flood light could be connected to the running light assembly of the boat that is adapted to seat into a power socket provided at the front of the boat. In addition, because a boater may require assistance from another boat at some time during dark conditions, it would be still further benefit if the flood light included a strobe mechanism for providing a strobe effect to attract the attention of other boaters who could then come to investigate.
It is thus an object of the invention to provide an improved boat running light fixture for removable boat running light fixtures that include a plug-in power supply and light support stem that has a bottom plug portion that is plugged into the electrical power running light socket provided at the front of a boat and a RED/GREEN running light fixture mechanically mounted in connection with a top end of the plug-in power supply and light support stem and in electrical connection with the bottom plug portion of the plug-in power supply and light support stem such that electrical power is delivered to the lights within the RED/GREEN light fixture from the electrical power running light socket provided at the front of a boat when the bottom plug portion is plugged into the electrical power running light socket of the boat; the improvement includes providing a high intensity driving flood/strobe light assembly in mechanical connection with the RED/GREEN running light fixture and providing a multi-directional pivot joint between the top end of the plug-in power supply and light support stem and the combination RED/GREEN running light and the high intensity driving flood/strobe light assembly such that a user can aim a light beam emitted from the high intensity driving flood/strobe light assembly in a desired direction prior to driving the boat during dim or dark ambient light conditions; the high intensity driving flood/strobe light assembly being supplied with power from the bottom plug portion of the plug-in power supply and light support stem and including a three position switch, a flood lamp assembly and a strobe control circuit including a strobe lamp power output, a power input and a variable output strobe intensity control mechanism; the switch power input of the three-position switch being wired in connection with the bottom plug portion of the plug-in power supply and light support stem such that when the three-position switch is in an xe2x80x9coffxe2x80x9d position, an open circuit exists between the switch power input and both the flood lamp assembly and the power input of the strobe control circuit; when the three-position switch is in a xe2x80x9cflood lamp onxe2x80x9d position, a closed circuit exists between the switch power input and the flood lamp assembly causing it to continuously illuminate and an open circuit exists between the switch power input and the power input of the strobe control circuit; and when the three-position switch is in a xe2x80x9cstrobe lamp onxe2x80x9d position, an open circuit exists between the switch power input and the flood lamp assembly and a closed circuit exists between the switch power input and the power input of the strobe control circuit causing the strobe control circuit to cause the strobe lamp power output to intermittently apply strobe power to the flood lamp assembly at a rate determined by the position of the variable output strobe intensity control mechanism.
Accordingly, an improved boat running light fixture is provided for running light fixtures that include a plug-in power supply and light support stem that has a bottom plug portion that is plugged into the electrical power running light socket provided at the front of a boat and a RED/GREEN running light fixture mechanically mounted in connection with a top end of the plug-in power supply and light support stem and in electrical connection with the bottom plug portion of the plug-in power supply and light support stem such that electrical power is delivered to the lights within the RED/GREEN light fixture from the electrical power running light socket provided at the front of a boat when the bottom plug portion is plugged into the electrical power running light socket of the boat; the improvement includes providing a high intensity driving flood/strobe light assembly in mechanical connection with the RED/GREEN running light fixture and providing a multi-directional pivot joint between the top end of the plug-in power supply and light support stem and the combination RED/GREEN running light and the high intensity driving flood/strobe light assembly such that a user can aim a light beam emitted from the high intensity driving flood/strobe light assembly in a desired direction prior to driving the boat during dim or dark ambient light conditions; the high intensity driving flood/strobe light assembly being supplied with power from the bottom plug portion of the plug-in power supply and light support stem and including a three position switch, a flood lamp assembly and a strobe control circuit including a strobe lamp power output, a power input and a variable output strobe intensity control mechanism; the switch power input of the three-position switch being wired in connection with the bottom plug portion of the plug-in power supply and light support stem such that when the three-position switch is in an xe2x80x9coffxe2x80x9d position, an open circuit exists between the switch power input and both the flood lamp assembly and the power input of the strobe control circuit; when the three-position switch is in a xe2x80x9cflood lamp onxe2x80x9d position, a closed circuit exists between the switch power input and the flood lamp assembly causing it to continuously illuminate and an open circuit exists between the switch power input and the power input of the strobe control circuit; and when the three-position switch is in a xe2x80x9cstrobe lamp onxe2x80x9d position, an open circuit exists between the switch power input and the flood lamp assembly and a closed circuit exists between the switch power input and the power input of the strobe control circuit causing the strobe control circuit to cause the strobe lamp power output to intermittently apply strobe power to the flood lamp assembly at a rate determined by the position of the variable output strobe intensity control mechanism is provided.


An improved decoder for recovering Non-Return-to-Zero Interface (NRZI) digital data from a multiple layer transition (MLT-3) encoded signal in a 100BASE-TX Ethernet (IEEE Standard 802.3u) uses multiple comparators to minimize jitter in the decoded signal. A CMOS-based biasing circuit receives the differential MLT-3 encoded input signals and control signals from a signal amplitude detection circuit. The biasing circuit adjusts for any DC offset, and also generates offset signals based on respective mid-peak voltage values of the respective differential input signals. Four comparators are then used to detect a prescribed edge transition (e.g., a positive edge) coinciding with the respective mid-peak voltage value in the respective signals. The detected edge transitions are then used by edge decoding logic to generate the NRZI bilevel signal.

1. Technical Field
The present invention relates to decoders for recovering digital data from a transmitted analog signal, more particularly to a multiple layer transition (MLT-3) decoder configured for receiving a 125 Mb/s MLT-3 encoded signal from a 100BASE-TX Ethernet (IEEE Standard 802.3u) transmission medium for decoding into a two-level Non-Return to Zero Interface (NRZI) digital signal in a physical layer transceiver.
2. Background Art
Local area networks use a network cable or other network media to link nodes (e.g., workstations, routers and switches) to the network. Each local area network architecture uses a media access control (MAC) enabling network interface device at each network node to share access to the media.
Physical (PHY) layer devices are configured for translating digital packet data received from a MAC across a standardized interface, e.g., a Media Independent Interface (MII), into an analog signal for transmission on the network medium, and reception of analog signals transmitted from a remote node via the network medium. An example is the 100BASE-TX Ethernet (IEEE Standard 802.3u) receiver, configured for receiving a three-level MLT-3 encoded analog signal at a 125 Mb/s data rate. For example, FIGS. 1A, 1B and 1C are diagrams illustrating an original NRZI-encoded digital signal for transmission on the media, an encoded MLT-3 signal generated at the transmitting PHY layer for transmission on the network medium, and an MLT-3-encoded analog signal having been transmitted by the network medium and received by a PHY transceiver at a destination node. As shown in FIG. 1A, the original bilevel digital signal, encoded as an NRZI signal, is encoded into the three-level MLT-3 signal of FIG. 1B before transmitting the digital information to the receiving station. On the receiving side, the MLT-3 encoded signal of FIG. 1B encounters transmission loss, for example high frequency attenuation, resulting in the received MLT-3 signal of FIG. 1C. Hence, the 100BASE-TX Ethernet (IEEE 802.3u) receiver must recover the digital information from the received MLT-3 signal of FIG. 1C.
FIGS. 2A, 2B and 2C illustrate one proposal for recovering the NRZI signal from the received MLT-3 signal. In particular, FIG. 2A is a diagram illustrating a prior art decoder that decodes the received MLT-3 signal of FIG. 2B to obtain the NRZI signal of FIG. 2C. As shown in FIG. 2A, the prior art decoder includes two comparators 10a and 10b, and an OR gate 12 to convert the received MLT-3 signal into an NRZI-format signal. Specifically, each comparator 10 receives the received MLT-3 signal (C) and an inverted copy of the received MLT-3 signal (CB), where the signal CB has an inverse polarity relative to signal C, as shown in FIG. 2B. In particular, comparator 10a receives the C signal and the CB signal at a non-inverting input and an inverting input, respectively, whereas comparator 10b receives the C signal and the CB signal at inverting and non-inverting inputs, respectively. The comparators 10a and 10b are positive edge triggered, hence the comparators output a logical zero (e.g., no signal) if the values of C and CB are equal (e.g., equal to zero volts). If the signal C exceeds signal CB by a prescribed threshold T.sub.a, as shown in FIG. 2B, the comparator 10a outputs a comparison signal 14 as a logical 1. In contrast, if signal CB exceeds signal C by a prescribed threshold Tb, the comparator 10b outputs a comparison signal 16 as a logical 1 to the OR gate 12.
Although the decoder circuit of FIG. 2A is relatively easy to implement, the circuit of FIG. 2A encounters numerous problems in actual implementation. Noise encountered during the transmission of the MLT-3 encoded signal requires that the threshold values of the comparators 10a and 10b be set to a non-zero value. The ideal comparator threshold is half of the peak value, namely between the middle point P.sub.1 and the positive/negative peaks P.sub.2 /P.sub.3. In practical design, however, such a comparator with controlled thresholds that can adapt to signal peak values is not easy to implement in the circuit of FIG. 2A.
In addition, the MLT-3 signal of FIG. 2B, having encountered high frequency attenuation during transmission, has slow rise-fall edges, e.g., a degraded slew rate. Hence, each comparator 10a, 10b will also generate an output signal 14, 16 having a reduced slew rate as a signal edge, as opposed to the ideal instantaneous (i.e., vertical edge). In addition, the precise point at which the input MLT-3 signals C and CB cross the thresholds T.sub.a and T.sub.b is varied due to the attenuated slew rate. Variations in the threshold voltage also affect the precise point at which the input signals C and CB cross the threshold. Hence, the precise location of the leading edge of the MLT-3 encoded signal as shown in FIG. 1B is difficult to identify.
Moreover, conventional comparators have threshold hysteresis, where the comparators do not have identical rising-edge thresholds and falling-edge thresholds. Hence, if the rising-edge threshold (T.sub.a ) is set at a peak voltage divided by 2 (e.g., 50 milli-volts), the falling-edge threshold (T.sub.c) may have a different value (e.g., 45 milli-volts) that affects when the comparator output signal is turned off. For example, if the rising-edge threshold is slower (e.g., 50 milli-volts) than the falling-edge threshold (e.g., 45 milli-volts), the resulting pulsewidth of the comparator signal will be narrower than ideal; conversely, if the rising-edge threshold is faster (e.g., 40 milli-volts) than the falling-edge threshold (e.g., 45 milli-volts), the resulting pulsewidth of the comparator signal will be wider than ideal. Hence, the threshold hysteresis present in comparators adversely affects the pulsewidth of the pulse 14 and 16 output by the comparators 10a and 10b, respectively.
These factors cause the comparators 10a and 10b to output a comparison signal at variable times, which introduces timing variations (i.e., jitter) into the decoded NRZI signal of FIG. 2C. Hence, the decoded NRZI signal may include jitter that may affect the accurate detection of the network clock, as well as accurate detection of the decoded data in a synchronous system.
FIGS. 3A and 3B illustrate an alternative MLT-3 decoder. The decoder of FIG. 3A includes buffers 14a and 14b, for example a unit-gain amplifier, and voltage offset supply sources 16a and 16b. Hence, the voltage sources 16a and 16b output the signals C.sub.o and CB.sub.o, respectively, as shown in FIG. 3B. Use of the unit-gain amplifiers 14 enables addition of a DC offset, which adds a degree of noise immunity to the comparators 18a and 18b, reducing the required threshold values. However, the additional stage of buffers 14a and 14b increases the propagation delay and reduces the input bandwidth of the decoder circuit, becoming a critical issue in relatively low speed CMOS circuit implementations, especially for 100BASE-TX Ethernet (IEEE 802.3u) applications.
FIGS. 4A and 4B illustrate still another conventional approach for performing MLT-3 decoding. Specifically, the MLT decoding circuit of FIG. 4A includes comparators 20a and 20b, where potential sources 22a and 22b are set according to the decoder threshold and the amplitudes of the differential input signals C and CB. However, the circuit of FIG. 4A provides poor performance of common mode noise rejection, unless the respective potentials P1 and P2 of voltage sources 22a and 22b can be derived to track the common mode noises in signals C and CB. In addition, bandwidth limitations are encountered if the decoder circuit of FIG. 4A is implemented in CMOS.

Apparatus and method for decoding differential multi-level data with adaptive threshold control


An amplifier circuit (1) is disclosed, wherein with a view to reducing the leakage power of the amplifier circuit (1) a current path (6) is provided between a first output terminal (A1) and a second output terminal (A2) of the amplifier circuit, said current path being open in the case of an uptake of energy at the output of the amplifier circuit (1), so that the electrical energy taken up by the one output terminal (A1) can be drained away immediately via the other output terminal (A2). If no uptake of energy is taking place via the output of the amplifier circuit (1) but instead electrical energy is being released by the amplifier circuit (1), the current path (6) between the two output terminals (A1, A2) is closed.

The present invention relates to an amplifier circuit, in particular an amplifier circuit with low leakage power.
Amplifiers that not only release energy but also, at least at times, take up energy at their output give rise to an unnecessarily high leakage power. It is not exclusively the supplied energy that is dissipated, but also additional energy which is withdrawn unnecessarily from the voltage supply. Therefore more elaborate, more expensive measures are required for the dissipation of heat. Furthermore, supply energy is wasted, which is disadvantageous particularly in the case of battery-driven devices.
An example of the uptake of energy by an amplifier via the output thereof is the connection of a reactive, for example capacitive, load to the output of the amplifier. A capacitive load of such a type is, for example, the European ringer load of a terminal device on an analogue subscriber line. Amplifiers that drive a capacitive load have a high leakage power. In the course of the charging process, at least the same amount of energy is dissipated in the amplifier as is transferred into the capacitive load. In the course of the discharging process, in addition to the amount of energy stored in the capacitive load at least twice as much energy is again dissipated in the amplifier. In the most favourable case, i.e. in the course of charging the capacitive load or the corresponding capacitance to the value of the full supply voltage, for each charge-discharge cycle the fourfold value of the energy stored maximally in the capacitive load is dissipated.
A further example of the uptake of energy by an amplifier via the output thereof is the connection of a reactive inductive load, for example an electromechanical or electroacoustic converter, to the amplifier. Also in the case of full-duplex transmission lines such as are employed, for example, in XDSL transmission systems ("Digital Subscriber Line") for bidirectional transmission of speech and data, at the amplifiers that are connected at both ends of the transmission line with impedance synthesis the uptake of energy occurs via the outputs of said amplifiers.
FIG. 5 shows schematically an amplifier 1 which is connected to a load 3, in particular a reactive load, via its output terminals A1, A2. In the example that is represented, the amplifier 1 comprises two sub-amplifiers 4, 5, the output of sub-amplifier 4 being coupled to output terminal A1 and the output of sub-amplifier 5 being coupled to output terminal A2. The two sub-amplifiers are connected to supply-voltage nodes or supply-voltage terminals V+, V− of the amplifier 1, to which in turn a supply voltage 2 is connected. In the case of an uptake of energy by the amplifier 1 via the output thereof by reason of the reactive load connected thereto, a flow of current occurs from the one output terminal to the other output terminal, this flow of current being routed, in particular, at least partially via the supply-voltage path. Thus, for example, in the case of the uptake of energy via the output of the amplifier 1 a flow of current starting from the output terminal A1 may be directed to the other output terminal A2 of the amplifier 1 via the sub-amplifier 4 and the supply-voltage terminal V−, the supply-voltage source 2, the supply-voltage terminal V+ and the sub-amplifier 5. This flow of current via the supply-voltage path results in the problems previously described, namely, in particular, the fact that in the case of an uptake of energy via the output of the amplifier 1 additional energy, which is withdrawn unnecessarily from the supply-voltage source 2, is dissipated in the amplifier.
In conventional solutions an overheating of the components by the additionally dissipated energy is avoided by appropriate dimensioning of the dissipation of heat from the amplifier 1, for example by providing an appropriately large cooling attachment on the amplifier 1. However, the effort required for these measures is relatively great, and the costs thereof are relatively high.
The object underlying the present invention is therefore to make available an amplifier circuit in which the leakage power of the amplifier circuit can be reduced with low costs and with little effort.

Arrangement and method for controlling an amplifier circuit corresponding to energy uptake in the amplifier circuit


This invention provides a method of preparing an electrical overstress material having a nonlinear resistance which declines sharply in response to an electric field exceeding a clamping voltage so as to be able to shunt out transient surges which method comprises using an adhesive binder, for example a silicone rubber or a ceramics dispersion, and thorough mixing therein of small conductive, and optionally semiconductive particles, for example nickel particles of various morphologies and silicon carbide particles respectively, followed by molding under pressure and curing. The invention is also directed to the electrical overstress material itself which has excellent strength and integrity as well as survivability from multiple surges and has multiple applications in, for example, electrical outlet strips and power cables. The invention is also directed to a power outlet strip comprising a plurality of surge arresting elements composed of the electrical overstress material of the invention.

The present invention relates in general to electrical circuit protection materials and methods, and, in particular to novel electrical overstress materials capable of conforming to predetermined shapes, as well as novel methods and processes for producing such materials. Apparatus for practicing the novel methods and processes, as well as both devices and systems which utilize such novel materials, are also disclosed.
The following specification and claims, read together with the accompanying drawings, are presented merely to teach examples and embodiments of the present invention, and should not be read or construed as limiting the proper scope of the claimed invention.
Conventional surge protection devices include fuses, varistors, Zener diodes, spark gap and thin-film devices, along with electronic filter circuits. Each of these devices and circuits is shown to have one shortcoming or another in countering the effects of fast-rise, broad frequency spectrum, transient voltage or current surges, or in recovering from such repeated surges.
More specifically, conventional surge protection devices are too slow in reaction times to provide protection for many modern delicate circuit elements, have inadequate voltage dissipation capacity to protect such delicate circuit elements from large electrical stresses, and are subject to destructive breakdown after a single high voltage surge, thereby leaving the circuit unprotected from any subsequent surge.
The concept of clamping voltage is also important in understanding electrical overstress materials. Clamping voltage, in relation to the nonlinear resistance characteristics of a device, is usually considered as being the overall or bulk resistance of a surge protection device or material in relation to a voltage applied to it. For applied voltages below the clamping voltage, a nonlinear resistance device, such as a varistor, offers the circuit a high resistance approaching the characteristics of an insulator, while, for applied voltages substantially above the clamping voltage, the device offers the circuit a substantially reduced resistance capable of shunting transient electrical surges to ground.
The prior art contains teachings of electrical resistance composites intended for purposes similar to that of the present invention, but they differ from the present invention and do not accomplish the same results.
U.S. Pat. No. 4,977,357 issued to Shrier discloses an electrical overstress material having conductive particles uniformly dispersed in an insulating matrix or binder to provide material having non-linear resistance characteristics that are determined by the interparticle spacing within the binder as well as by the electrical properties of the insulating binder. U.S. Pat. No. 4,726,991 issued to Hyatt et al. discloses specific materials intended for electrical overstress protection and provides both a general overview of the problem and a survey of the known prior art. Hyatt et al. proposes a material for electrical overstress protection that has a nonlinear resistance as the voltage across it varies. The material comprises a matrix containing a mixture of small conductive and semiconductive particles coated with inorganic insulating material that permits nonlinear conduction between the particles in response to electrical transients by what is believed to be the quantum mechanical tunneling of electrons in the matrix materials. In a preferred embodiment the material includes a binder or packaging material in which the particles are generally homogeneously mixed.
U.S. Pat. No. 4,359,414, issued to Mastrangelo, discloses an electric current regulating junction capable of being electrically switched between low resistance and relatively high resistance states by the application of a relatively low current pulse and that is useful as a computer memory storage element. The material comprises a normally insulative, electrically activatable composition disposed as a layer 0.1 to 2,540 microns in thickness that has an electrical resistance greater than 10.sup.8 ohms through its thickness. The composition consists essentially of 10 to 85 volume percent of a substantially linear, unitary polymeric binder having a glass transition temperature of at least 100 degrees Centigrade and is selected from aromatic polimides, aromatic poly(amides-imides), aromatic poly(ester-imides) and aromatic polyamides. The binder has 15 to 90 volume percent of particles of aluminum substantially homogeneously dispersed in it. The aluminum particles are stated to have electrically conductive metallic interiors and thin electrically insulative surface coatings of aluminum oxide sufficient to impart electric resistance between any two or more particles in contact with each other. However, this patent neither states nor suggests the use of semiconductive particles, whether they be coated or not, nor does it provide for its junction material automatically returning to its high resistive state once an initial triggering pulse is shunted to ground.

Electrical overstress materials and method of manufacture


A game apparatus and method played by throwing projectiles (such as darts) at a playing surface. The playing surface includes field markings that depict a sports field in perspective view. The playing surface also includes target markings that define offensive targets and defensive targets. The defensive targets resemble silhouettes of players involved in various action modes of a game. An active counter is provided for awarding score values according to factors such as time elapsed between when an offensive target is hit and a defensive target is hit.

A dart game is typically played with three darts that are thrown in succession at a circular sectored board. Numerous games have been developed over the years incorporating the basic elements of darts and a dart board. Included among these games are sports-related games such as adaptations of North American football. Examples of dart football games are described in U.S. Pat. Nos. 3,979,117 (Worsham), 4,893,822 (Tesa) and 5,005,842 (Bauer). Each of these patents are directed to games that feature one or more circular boards having sectors that are representative of offensive plays in a football game. The games are played by throwing darts at desired targets on the board to acquire specific yardage values and score a touchdown or a field goal.
One problem with such conventional sports-related dart games is their failure to adequately mimic the live action and complex interaction associated with the sports. Another problem with such conventional dart games is the lack of visual similarity to the specific aspects of the sport they are adapting.

Sports related dart game apparatus and method


The invention relates to novel piperazine derivatives and their use as active ingredients in the preparation of pharmaceutical compositions. The invention also concerns related aspects including pharmaceutical compositions containing one or more of those compounds and their use as medicaments for the treatment or prevention of protozoal infections, especially malaria.

Numerous serious diseases affecting humans as well as domestic and livestock animal are caused by protozoal organisms such as kinetoplastida, apicomplexa, anaerobic protozoa, microsporidia and plasmodium. The clinically most relevant of these diseases is malaria.
Malaria is one of the most serious and complex health problems affecting humanity in the 21st century. The disease affects about 300 million people worldwide, killing 1 to 1.5 million people every year. Malaria is an infectious disease caused by four species of the protozoan parasite plasmodium, P. falciparum being the most severe of the four. All attempts to develop vaccines against P. falciparum have failed so far. Therefore, therapies and preventive measures against malaria are confined to drugs. Various classes of antimalarial drugs exist. The most widely used are the quinoline antimalarials, e.g. chloroquine which has been an especially effective drug for both prophylaxis and therapy. However, resistance to many of the currently available antimalarial drugs is spreading rapidly, threatening people in areas where malaria is endemic. Reports of multi-drug resistant strains of malaria parasites render the search for new antimalarial agents especially urgent.
P. falciparum enters the human body by way of bites of the female anophelino mosquito (it may also be transmitted by blood transfusion from asymptotic donors; almost all infected blood components including red cells, platelet concentrates, white cells, cryoprecipitates and fresh plasma can transmit malaria). The plasmodium parasite initially populates the liver, and during later stages of the infectious cycle reproduces in red blood cells. During this stage, the parasite degrades hemoglobin and uses the degradation products as nutrients for growth. The limitations of the current antiprotozoal chemotherapeutic arsenal underscore the need for new drugs in this therapeutic area. The present invention relates to the identification of novel low molecular weight, non-peptidic, non-quinoline compounds of formula I which are useful in the treatment and/or prevention of protozoal infections, especially in the treatment and/or prevention of malaria, in particular plasmodium falciparum malaria.


A double-side optical disc formed by a pair of optical disc halves bonded together, and a process for producing the double-side optical disc. An adhesive is applied to the disc halves, which are then bonded together at an angle relative to each other in which the direction of the adhesive flow on one disc half will intersect the direction of the adhesive flow on the other disc half. In this manner, satisfactory flatness of the optical disc may be achieved without being affected by surface irregularities of the adhesive layer.

1. Field of the Invention
This invention relates to a double-side optical disc having a recording surface for information signals on each side thereof and, more particularly, to a double-side optical disc composed of a pair of optical discs each having a signal recording surface on one side thereof and bonded to each other by an adhesive.
2. Description of the Prior Art
There has been proposed an optical disc in which data signals in the form of pits are formed by resin molding using a stamper and subsequently read out by an optical pickup.
The optical disc is constituted by a disc-shaped base material formed of a synthetic resin, such as polycarbonate, acrylic resin or epoxy resin, or glass, and a signal recording layer of, for example, a magnetic material, formed on the major surface of the disc shaped base material.
As such optical disc, there has been proposed a double-side optical disc 102 comprised of a pair of optical disc halves 101a, 101b bonded to each other as shown in FIG. 1 to enable data signals to be read and/or written from or on both major surfaces of the disc. The optical disc halves 101a, 101b of the double-side optical disc 102 are bonded together at the back sides thereof so that the front sides on the signal recording sides face to outside. The optical disc halves 101a, 101b are bonded together by applying an adhesive 103 of, for example, a rubber material, on the overall back sides thereof and pressing the disc halves together in the superimposed state.
Meanwhile, when the adhesive 103 is applied on the optical disc halves 101a, 101b for producing the double-side optical disc 102, the surface of the adhesive 103 tends present irregularities. It is because the adhesive 103 is applied by roll coating in which the adhesive is applied to the outer periphery of a rotating applicator roll and by bringing the applicator roll into rolling contact with the optical discs 101a, 101b.
Should the surface of the adhesive 103 present irregularities, the optical disc halves 101a, 101b bonded together tend to deviate from optimum smoothness due to the surface irregularities of the adhesive 103. Unless the smoothness of the optical discs 101a, 101b is maintained, the signal recording layer is deteriorated in flatness to render it difficult to write and/or read data signals on or from the signal recording layer under optimum states.

Optical disc having signal recording layer on each side and method for producing same


A dual solid state switch architecture has a plurality of control/monitor ports, selected ones of which are used to control the operation of a pair of power MOSFETs current flow paths through which are coupled to prescribed ones of a plurality of input/output ports that are adapted to be coupled to a circuit path containing a load and either and AC or DC power source therefor. Selected others of the control/monitor ports are used to monitor current delivered to the load. A leakage current by-pass resistor is connected between selected input/output ports, to which a neon tube may be connected for indicating the switching on of an AC source. This resistor serves to provide a bypass path for leakage current through the MOSFETs, so as to prevent the neon tube from being erroneously illuminated, when the MOSFETs have been turned off.

In many test and evaluation applications it is necessary to control the application and/or interruption of one or more AC and DC sources to a load under test. Moreover, it is often the case that the amount of current consumed by a load should be monitored. Performing both of these tasks has typically required the use of separate and distinct interconnect and monitor components, such as a solid state AC switch or relay for controlling AC current, another type of switch controlling DC current, and additional circuitry used to monitor current flowing through the switch and the load.
In addition to these power supply and current monitoring functions, there is a need to prevent DC current from flowing backward through the switch when the switch is turned off. A further issue is the control current that turns on the solid-state switch, and the desire to provide a visual indication of the state of the switch, with the state of the switch being capable of being monitored from either its control or load side. Unfortunately, present day solid state switches have sufficient leakage current on the load side that can erroneously turn on a neon indicator, even through the switch has been turned off.


The semiconductor device includes a vertical channel layer formed on a substrate; conductive layer patterns and insulating layer patterns alternately formed around a length of each of the vertical channel layer; and a charge storing layer pattern formed between each of the vertical channel layers and the conductive layer patterns, where each of the charge storing layer patterns is isolated by the insulating layer patterns.

The present invention relates to a semiconductor device, a memory system including the semiconductor device, and a method of manufacturing the semiconductor device, and more particularly to a 3-Dimensional (3D) semiconductor device, a memory system including the 3D semiconductor device, and a method of manufacturing the 3D semiconductor device.
Generally, in order to improve the integration degree of the semiconductor device, methods of decreasing sizes of 2-dimensionally arranged memory cells have been developed.
There is a limitation in decreasing the sizes of the 2-dimensionally arranged memory cells. In order to overcome the limitation, a 3D semiconductor device in which memory cells are 3-dimensionally arranged on a substrate has been suggested. The 3D semiconductor device may efficiently utilize an area of the substrate and improve an integration degree compared to a case in which the memory cells are 2-dimensionally arranged. However, reliability of the 3D semiconductor device is lower than that of the 2D semiconductor device due to various reasons, so that the improvement of the reliability of the 3D semiconductor device has been demanded.

Semiconductor device, memory system including the same, and method of manufacturing the same


Power supply regulators, integrated circuits including a power supply regulator, and methods of regulating a power supply are provided. In one embodiment, a power supply regulator includes a first self-bias circuit configured to receive a supply voltage from a power supply, a second self-bias circuit coupled to a reference voltage, and a clamping circuit coupled between the first and second self-bias circuits. The clamping circuit includes a NMOS transistor coupled to the first self-bias circuit and a PMOS transistor coupled to the second self-bias circuit. The clamping circuit is further configured to generate an output voltage less than the supply voltage at substantially the same time as when the supply voltage is received from the power supply.

Input/output ("I/O") circuits are used to input electronic signals to and output electronic signals from integrated circuits. A typical integrated circuit ("IC") includes an integral I/O circuit for each of its externally accessible I/O pins. An I/O circuit usually includes a driver circuit which receives signals from the IC and outputs them to the I/O pin. It also generally includes an input buffer which receives signals from the I/O pin and inputs them to the IC. A typical I/O circuit also includes an enable circuit which can place the driver circuit in either a high impedance state in which signals can be input to the IC via the I/O pin, or in an output enabled state in which signals can be output from the IC via the I/O pin.
I/O circuits transfer signals to and from integrated circuit devices in a variety of types of electronic systems. For instance, I/O circuits may be used to interconnect integrated circuits to a shared system bus so that multiple ICs connected to the bus can communicate with each other. In many electronic systems all of the ICs connected to a system bus operate at the same supply voltage level. However, as the dimensions of the circuits in ICs have decreased, the supply voltages employed by ICs also have decreased. As a result, there has been a proliferation of mixed signal systems in which some ICs connected to a system bus operate at a higher supply voltage (e.g., 3.3-volts), and other ICs connected to the same system bus operate at a lower supply voltage (e.g., 1.65-volts).
A voltage regulator may be used to enable circuits/systems to operate using only one supply voltage from a power supply, with the voltage regulator providing various subcircuits and/or subsystems with different individual supply voltages. However, timing dead zone problems, which may cause hot carrier injection and gate oxide integrity issues, and power sequence problems have been encountered with multiple power domains. Thus, improved methods, systems, and apparatus for regulating power supplies are desirable.

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.


In a method of setting density for an image recording apparatus, an image for measurement having a plurality of regions having different densities is recorded by scanning a photosensitive material with a light beam having a constant intensity while changing light intensity using a light-amount adjusting device. The relationship between the amount of adjustment by the light-amount adjusting device and the density of the recorded image is obtained by measuring the densities of the respective regions of the recorded image for measurement. The light-amount adjusting device is set so that an image having a desired density is obtained according to the obtained relationship.

1. Field of the Invention
This invention relates to a method of setting a density used for an image recording apparatus, such as a laser imager for drawing an image on a photosensitive material by performing laser-beam scanning, or the like.
2. Description of the Prior Art
Recently, in the medical field, various techniques, such as CT (computed tomography), MR (magnetic resonance) and the like, have been used for observing the interior of a human body. Those techniques require high-definition images. In accordance with the development of such techniques, it has become necessary to record images obtained by these techniques without imparing the picture quality of the images. A laser imager is an apparatus which stores an image by digitizing the image for every picture element and performs recording by scanning a photosensitive member while modulating a laser beam with an intensity proportional to the digitized value of each picture element. The laser imager has an advantage in that, since the image is stored as digital values for every picture element, it is always possible to record a halftone stable image with a simple operation by performing image processing, such as gradation correction and the like. At present, a recorded image having the highest picture quality is obtained by performing recording on a transparent silver-halide film using the laser imager.
When changing the maximum density value of a photosensitive material in accordance with an object for an image, or the taste of an observer, if a method of suppressing the maximum intensity of a laser beam by directly modulating the laser beam is adopted, the dynamic range of the modulated light is reduced, particularly in the case of using a semiconductor laser light source. Hence, a desired gradation accuracy cannot be obtained. Accordingly, in general, as disclosed in Japanese Patent Application Public Disclosure (Kokai) No. 60-250327 (1985), the maximum intensity of a laser beam is optically changed by disposing a filter or the like in the optical path of the beam. For example, a polarizer is used as the filter, and the intensity of the laser beam passing through the polarizer is changed by rotating the polarizer using a dial for adjusting the density of a silver-halide film.
In the above-described conventional approach, however, the density of an image recorded on the photosensitive material is not exactly proportional to the intensity of the projected laser beam, and is greatly influenced by the environment, such as temperature and the like. Another influence is the kind of developer to be used. Hence, it is necessary to adjust the graduation of the dial for adjusting the density at a location where the laser imager is used. Conventionally, a complicated method has been adopted such that a test image is recorded and developed on a photosensitive material while the dial for adjustment is rotated to different angles, and the graduation of the dial is calibrated by measuring the densities of the recorded image. Accordingly, a method of setting the density of a photosensitive material in a simple manner is needed.

Method of setting density for image recording apparatus


A fuel cell system comprises a fuel cell supplied with fuel and air to generate electricity, an evaporator evaporating the fuel, an off-gas heating device heating an off-gas discharged from the fuel cell to produce a heating gas, a fuel cell heating device heating the fuel cell using the heating gas, an evaporator heating device heating the evaporator using the heating gas, a fuel cell temperature acquisition unit, an evaporator temperature acquisition unit, and a controller configured to, in a warm-up operation to perform a warm-up of the evaporator and a warm-up of the fuel cell, control at least one of the evaporator heating device and the fuel cell heating device based on the temperature of the evaporator and the temperature of the fuel cell to adjust at least one of a heating amount of the evaporator and a heating amount of the air by the heating gas.

JP2016-154067A discloses a fuel cell system including a start-up combustor for warming up a fuel cell stack and an evaporator, and a reformer. The system is configured to switch a supply destination of raw fuel between the start-up combustor and the reformer when starting the system.
In the fuel cell system of JP2016-154067A, until the reformer reaches a reforming possible temperature (until the warm-up of the reformer is finished), the components other than the reformer are heated by the start-up combustor to promote the warm-up of those components, and after the warm-up of the reformer is completed, the raw fuel is supplied to the reformer so that the reforming process is performed.

Fuel cell system and fuel cell system warm-up method