A current-perpendicular-to-plane (CPP) spin valve (SV) sensor and fabrication method with a contiguous junction type geometry that increases sensor resistance by up to two orders of magnitude over conventional CPP GMR geometry for a particular track read-width. The superior CPP GMR coefficient (δr/R) is implemented at an increased sensor resistance by using two small self-aligned SV stacks disposed with the sense current flowing perpendicular thereto when also flowing parallel to the free layer deposition plane. With the CPP geometry of this invention, thicker conductive spacer layers may be used without unacceptable sense current shunting, so the two self-aligned SV stacks may be completed following the free-layer track-mill step. The two SV stacks may be connected in parallel or back-to-back in series to provide different sense voltages.

1. Field of the Invention
This invention relates generally to giant magnetoresistive (GMR) spin valve (SV) sensors and more particularly to a high-sensitivity self-aligned lateral current-perpendicular-to-plane (CPP) dual-SV sensor geometry and fabrication method.
2. Description of the Related Art
Computers often include auxiliary memory storage devices having media on which data can be written and from which data can be read. A direct access storage device (DASD) or disk drive incorporating rotating magnetic disks is commonly used for storing data in magnetic form in concentric, radially-spaced tracks on the disk surfaces. Magnetic heads including read sensors are then used to read data from the tracks on the disk surfaces.
In high capacity disk drives, magnetoresistive (MR) read sensors (MR heads) are preferred in the art because of their capability to read data at greater track and linear densities than earlier thin film inductive heads. An MR sensor detects the magnetic data on a disk surface through changes in the MR sensing layer resistance, which are responsive to changes in the magnetic flux sensed by the MR layer.
The early MR sensors rely on the anisotropic MR (AMR) effect in which an MR element resistance varies as the square of the cosine of the angle between the magnetic moment of the MR element and the direction of sense current flowing through the MR element. Recorded data can be read from a magnetic medium because the external magnetic field from the recorded magnetic medium (the signal field) changes the moment direction in the MR element, thereby changing the MR element resistance and the sense current or voltage.
The later giant magnetoresistance (GMR) sensor relies on the spin-scattering effect. The chief source of the GMR effect is "spin-dependent" scattering of electrons. In GMR sensors, the resistance varies as a function of the spin-dependent scattering of the conduction electrons across two magnetic layers separated by a non-magnetic spacer layer. The spin-dependent scattering occurs at the interface of the magnetic and nonmagnetic layers and within the magnetic layers. Electrical resistance is affected by scattering of electrons moving through a material. Depending on the direction of its magnetic moment, a single-domain magnetic material scatters electrons with "up" or "down" spin differently. When the free and pinned magnetic layers in a GMR structure are aligned anti-parallel, the resistance is high because "up" electrons that are not scattered in one layer may be scattered in the other. When the layers are aligned in parallel, scattering is reduced for all of the "up" electrons, regardless of which layer they pass through, yielding a lower resistance. GMR sensors using only two layers of ferromagnetic (FM) material separated by a thin layer of non-magnetic conductive material (e.g., copper) are generally referred to in the art as spin valve (SV) sensors.
The sense current-in-plane (CIP) SV sensor is well-known in the art and includes a nonmagnetic electrically conductive spacer layer sandwiched between a FM pinned layer structure and a FM free layer structure. An antiferromagnetic (AF) pinning layer interfaces the pinned layer structure for pinning a magnetic moment of the pinned layer structure 90E to an air bearing surface (ABS), which is an exposed surface of the sensor that faces the magnetic disk. Two sense current lead conductors are connected on each side of the layered SV structure to conduct sense current in the plane of the several layers. The magnetic moment of the free layer structure is free to rotate upwardly and downwardly with respect to the ABS from a quiescent position or bias point in response to positive and negative magnetic field signals present on the surface of an adjacent rotating magnetic disk. The quiescent position, which is preferably parallel to the ABS, is the position of the magnetic moment of the free layer structure with the operating-bias sense current conducted through the sensor in the absence of external magnetic fields.
The spacer layer thickness is chosen to minimize the shunting of the CIP sense current and the magnetic coupling between the free and pinned layer structures. This thickness is typically less than the mean free path of electrons conducted through the sensor. With this arrangement, a portion of the conduction electrons are scattered at the conductive spacer layer interfaces with the pinned and free layer structures. Such scattering is minimal when the pinned and free layer magnetic moments are parallel with one another, and increases substantially when the magnetic moments are antiparallel. Because changes in scattering affects the SV sensor resistance, the sensor resistance varies as a weighted function of cos θ, where θ is the relative angle between the magnetic moments of the pinned and free layer structures. SV sensor sensitivity is quantified in terms of the MR coefficient, δr/R, where R is the sensor resistance when the magnetic moments are parallel and δr is the change in the sensor resistance arising from shifting the moments into an antiparallel position.
The sensitivity of a SV sensor depends upon the response of the free layer to external magnetic field signals from the surface of a rotating magnetic disk. The magnetic moment of the free layer depends upon the material or materials employed for the free layer. The responsiveness of the free layer decreases as the magnetic moment of the free layer increases. Reduced responsiveness means the free layer magnetic moment cannot rotate as far from its parallel position to the ABS for a given external magnetic field level, which reduces sensor signal output. Also, improved isolation of the free layer structure from the pinned layer structure usually requires a thicker intermediate conductive layer, which shunts sense current away from the FM layers, thereby reducing sensor resistance and sensitivity.
For example, FIG. 1 shows an ABS view (disposed for vertical relative medium motion) of a typical CIP SV sensor 20 from the prior art that is stabilized using the hard magnetic (HM) layers 22 formed by a lift-off process. SV sensor 20 is usually fabricated using thin-film deposition techniques known in the art. For example, a first shield (S1) layer 24 of a conductive material is formed on a substrate (not shown) and an insulating layer 26 of alumina, or the like, is deposited over S1 layer 24. The SV layers are then deposited in sequence over insulating layer 26. For example, the AFM pinning layer 28 is deposited followed by the FM pinned layer 30 to form a pinned layer structure. Next, the conductive spacer layer 32 of copper, or the like, is deposited followed by the FM free layer 34. Finally, a photoresist layer (not shown) is formed over the entire assembly and is processed in the usual manner to permit all material outside of the central (read-width) region 36 to be removed by etching down to insulating layer 26 (the "track-mill" step). After etching, a HM material is deposited over the exposed portions of insulating layer 26 and also over the remaining photoresist layer (not shown) in central region 36 and, before removing the photoresist layer covering central region 36, a conductive lead layer 38 is deposited over everything. The photoresist layer is then finally dissolved away, which "lifts off" the unwanted portions (not shown) of the HM layer 22 and lead layer 26 within central region 36, in a well-known manner. Because of this lift-off deposition procedure, the later layers are tapered to a very slight thickness at the junction with central region 36. The sense current (not shown) flows parallel to the plane of layers 28–34 from one side of lead layer 38 to the other, so the (fixed) conductivity of conductive spacer layer 32 reduces the GMR effect of scatter-dependent conductivity of MR layers 30 and 34.
As an alternative to the CIP structure, the sense current lead conductors may be arranged so that the sensing current passes through the sensor perpendicular to the plane of the layers, which is known in the art as current-perpendicular-to-plane (CPP) geometry. In an early paper, [AA New Design for an Ultra-High Density Magnetic Recording Head Using a GMR Sensor In the CPP Mode," Rottmayer, R. and Zhu, J.; IEEE Transactions on Magnetics, Vol. 31, No. 6, November 1995], Rottmayer et al. propose a GMR multilayer read element within a write head gap that operates in the CPP mode and is biased by an exchange coupled soft film acting like a permanent magnet while distinguishing conventional MR and SV head designs. Their read element has a repeated multilayer structure (to increase GMR sensitivity) that is quite different from the GMR SV stack later introduced in the art.
For example, FIG. 2 shows a partial ABS view (disposed for vertical relative medium motion) of a typical CPP SV sensor 40 from the prior art. Sensor 40 includes a substrate 42 with an overlying underlayer 44. In turn, an insulating gap layer 46 overlies underlayer 44. A first magnetic shield (S1) layer 48 overlies gap layer 46 substantially as shown. An optional gap layer 50, which may include aluminum-oxide (Al2O3) or silicon-dioxide(SiO2), may be formed upon first magnetic shield (S1) layer 48. The S1 & S2 shield layers may include nickel iron (NiFe), cobalt-zirconium-tantalum (CoZrTa), iron-nitride (FeN) or any other useful soft magnetic materials or their alloys, and may be about 2 microns or less in thickness. Gap layer 50 may be from about 10 to about 100 nanometers in thickness. A first lead (L1) layer 52 is formed on top of gap layer 50. First lead (L1) layer 52 may include between 10 and 100 nanometers in thickness of rhodium (Rh), aluminum (Al), gold (Au), tantalum (Ta) or silver (Ag) or their alloys. A FM free layer 54 overlies first lead (L1) layer 52. A non-magnetic conductive spacer layer 56, usually copper (Cu), overlies free layer 54 and a pinned layer 58 is formed on top of spacer layer 56. A pinning layer 60 overlies pinned layer 58 and a second lead (L2) layer 62, of material similar to that used to produce first lead layer 52, is formed thereon. First and second lead layers 52, 62 in conjunction with free layer 54, spacer layer 56, pinned layer 58 and pinning layer 60 together make up the SV stack 64, substantially as shown. An optional gap layer 66 may overly second lead (L2) layer 62 to isolate therefrom the second magnetic shield (S2) 68. A dielectric gap material 70 surrounds SV stack 64 and portions of first (L1) and second (L2) lead layers 52, 62 substantially as shown. The sense current (not shown) flows perpendicular to the plane of layers 94–100 from one to the other of lead layers 52, 62. The inverted SV structure wherein pinning layer 60 and pinned FM layer 58 underlie active FM layer 54, may be used instead of the more conventional arrangement of active and pinned layers shown.
By passing the sense current through SV stack 64 perpendicularly to the plane of layers 54–60, the spin-dependent scattering effect may be exploited while eliminating the effect of the in-plane current usually shunted through the non-magnetic layers such as conductive spacer layer 56. It has been demonstrated that the CPP GMR coefficient (δr/R) is accordingly larger than the CIP GMR coefficient. However, because the film layers 54–60 are quite thin, they have a low resistance perpendicular to their plane (even with modem read-width and throat-height dimensions of about 500 nm) and the series resistance of first (L1) and second (L2) lead layers 52, 62 significantly reduces the sensitivity of the CPP SV sensor over what could otherwise be available. This is true with read-width (RW) and throat-height (TH) dimensions of about 500 nm each and is likely to remain so until these dimensions are reduced by an order of magnitude.
Practitioners in the art have proposed various useful solutions to the CPP SV resistance problem; some proposing to reduce the lead resistance and others proposing to increase the effective CPP SV stack resistance. For example, in U.S. Pat. No. 6,134,089, Ronald Barr et al. disclose a technique for reducing sense lead conductor resistance to better exploit the little resistance available in the CPP GMR stack. In U.S. Pat. No, 6,198,609, Ronald Barr et al. disclose a fabrication technique for increasing stack resistance by preventing sense current shunting at the edges of the CPP GMR stack, thereby improving sensitivity. In U.S. Pat. 5,668,688, John Dykes et al. propose increasing stack resistance by using two SV stacks in series to provide an enhanced δr/R response said to be twice that seen for CIP SV geometries. Moreover, in U.S. Pat. No. 6,233,125, Kenneth Knapp et al. disclose a CPP MR read sensor that is formed in a groove between two conductors by a method results in the sense current passing twice through the MR thickness, thereby doubling the sensor CPP SV stack resistance. Although these proposals do improve exploitation of the inherently better CPP GMR sensitivity by enhancing CPP resistance in different ways, most of these proposed solutions require much more elaborate fabrication procedures than do the simpler CIP SV sensor.
Thus, the larger CPP GMR effect (δr/R) does not readily result in the expected improvement in GMR sensor signal amplitude over CIP SV geometries because the CPP SV resistances are so much lower than the corresponding CIP SV sensor resistances, leading to lower voltage drops for given sense current amplitudes. These unresolved problems and deficiencies are clearly felt in the art and are solved by this invention in the manner described below.

High resistance sense current perpendicular-to-plane (CPP) giant magnetoresistive (GMR) head

Hitachi Global Storage Technologies Netherlands B.V.


A beverage dispenser comprises: a housing (1), at least two refillable containers (2) for storing bulk beverage ingredients, at least a beverage preparation unit (3) operatively linked to the containers for preparing a beverage from at least one of the stored bulk beverage ingredients, a sub-housing (4) in which the containers are placed, the sub-housing being removable from the housing.

Many beverages like espresso and other coffee beverages, milk beverages, chocolate beverages, . . . are often prepared by dosing and mixing a food soluble powder with a diluent. According to one type of beverage preparation machine the food soluble powder is stored in a non disposable canister that is part of the machine and that is regularly refilled. For the refilling operation the canister is pulled out of the machine, its top is opened and powder is empty inside.
For machines preparing various beverages like e.g. coffee and milk and chocolate and tea, several canisters must be regularly refilled and it takes time to carry out the refilling of all the containers. Yet this refilling operation must be as short as possible because the dispenser is not operable for producing beverages during that time.
Once the operator has refilled one container with a powder it is also often important that the operator always replaces the same container at the same place in the dispenser. Actually in most of the machines, the containers contain dosing means (e.g. screw or spring auger at the bottom of the container) and dosing means are activated differently by the machine motors depending on the nature of the powder inside the container. Moreover each dosing means generally delivers a dose of powder to a mixer or whipper that is specifically configured for mixing or whipping that powder—e.g. a whipper for a coffee powder is differently configured from a whipper for a milk powder. If the operator does not correctly place the different containers in the machine, the beverages will not be correctly prepared and it will affect their taste.
One aim of the present invention is to solve these problems and to propose a beverage dispenser comprising several beverage powder containers that can be easily and rapidly refilled without mistake by the operator.

Beverage dispenser with improved refilling operation


Disclosed is a system for production of a cosmetic product including: at least one first single-use packaging unit including a preset quantity of a first phase of a cosmetic product, at least one second single-use packaging unit including a preset quantity of a second phase of a cosmetic product, a machine including a mixer inside of which the mixture of the preset quantity of the first phase and the preset quantity of the second phase is done automatically in order to end up with a cosmetic product directly consumable by the end consumer. The mixing is done in a manner such that neither the first phase nor the second phase are in direct contact with any part of the mixer which is not single use, thus avoiding dirtying the mixer.

According to a first prior art, presented for example in the European patent EP 2,038,189, a system is known for production of a personalized cosmetic product from pods containing different base products, where these pods are opened and their content mixed with water within a machine.
The first disadvantage of this prior art concerns the management of the circulation of water and the mixing of the water with the content of the pods, which makes the structure the machine relatively complex.
A second drawback of this prior art concerns the cleaning which will both necessarily be tedious, because it affects all the internal parts of the machine having been in contact with the mixture, and will also need to be done relatively often, at least each time that the new personalized product will be incompatible or could be polluted by the components of the former personalized product previously made in the machine.

System for making a cosmetic product by mixing components from several single-use packaging units


A decision is made as to which of a first segment and a second segment of an input picture signal more correlates to a third segment of the input picture signal. The third signal segment is of interest. The first signal segment precedes the third signal segment by a 2-field interval or a 4-field interval. The second signal segment follows the third signal segment by a 2-field interval or a 4-field interval. Calculation is made as to a difference between the third signal segment and the more-correlating signal segment for every pixel related to the input picture signal. Every 1-pixel-corresponding portion of the third signal segment and every 1-pixel-corresponding portion of the more-correlating signal segment are mixed into a 1-pixel-corresponding portion of a filtering-resultant picture signal at a mixing ratio depending on the calculated difference.

1. Field of the Invention
This invention relates to an adaptive filter device for removing noise from a picture signal. This invention also relates to a method of adaptively filtering a picture signal.
2. Description of the Related Art
In a prior-art adaptive filter device for removing noise from a picture signal, a decision is made as to whether every 1-pixel-corresponding portion of an image represented by the picture signal is still or moving. Then, each segment of the picture signal which relates to a still 1-pixel-corresponding image portion is subjected to a filtering process in a temporal direction (a time-base direction). On the other hand, each segment of the picture signal which relates to a moving 1-pixel-corresponding image portion is not subjected to the filtering process. Thus, it tends to be difficult to remove temporal-direction noise from segments of the picture signal which represent moving image portions.
The temporal-direction noise decreases the quality of the image represented by the picture signal. In the case where the prior-art adaptive filter device is followed by a data compressing stage, the temporal-direction noise consumes bits of the compression-resultant picture signal. When the bit rate of the compression-resultant picture is limited to a low level, the temporal-direction noise considerably decreases the quality of images represented by the compression-resultant picture signal.

Adaptive filter device and related method


A method for billing a telephone call to a called party for a telephone call between a calling party and the called party, comprising the steps of receiving a predetermined access number; prompting for a destination number, determining if the destination number will accept the cost of the telephone call; and completing the telephone call to the destination number. The method may find potential application in a situation where, for example, a child may need to call home from a public telephone, say at a movie theatre or a mall, without using a calling card, credit card, collect charging, an operator, or coins.

1. Technical Field
This invention generally relates to (1) a method of providing accessability between individuals wherein the caller relies on the called party to assume the costs of the call and (2) telephone billing systems and, more specifically, to a telephone billing system and method that allows for the cost of a telephone call to be automatically billed as a preauthorized charge to the called number.
2. Description of Related Art
Today, a customer who is "away from home" can use a pay phone to make telephone calls. Additionally, relatives, friends, and business associates may have a need for a relationship for which the called party accepts the cost of the call is important or appropriate. These calls are commonly billed to a calling card or credit card, placed as collect (i.e., the called party pays for the charges), or paid for by inserting coins directly into the telephone.
U.S. Pat. No. 5,381,467 to Rosinki et al. describes a billing system that allows the cost of a telephone call to be shared by two parties given (1) the originating ANI (automatic number identification), (2) the terminating ANI, (3) a predefined portion percentage, and (4) an optional PIN (Personal Identification Number).
Consequently, the prior art does not appear to address the problem of permitting, for example, a child to call home from a public telephone (for example, at a movie theatre or a mall) without using a calling card, credit card, collect charging, an operator, or coins.

Universal call access with reverse billing


An image processing method includes a page layout adjustment step of converting image data to create print data having a page layout such that, when printed sheets each of which has a specified number of pages are discharged from an image formation apparatus thereby forming a stack of the printed sheets in the discharged order and in a case where the stack of the printed sheets are cut into the specified number of separated stacks corresponding to the page layout, the stack order of the cut printed sheets in each of the separated stacks corresponds to a sequence page order.

1. Field of the Invention
This disclosure relates to an image formation apparatus and an image formation system configured to form an image on a sheet-shaped printing medium such as a print sheet.
2. Description of Related Art
Generally, when print sheets of a size set by an application program (hereinafter referred to as the "AP") in a higher-level device run out, an image formation apparatus suspends an image formation process and notifies a user of such a paper-out condition by using an information display unit such as an operation panel in the image formation apparatus or a status monitor in the higher-level device.
Also, there has been disclosed an image formation apparatus configured to perform printing by reducing or enlarging such suspended image data and switching to alternative sheets, and has been disclosed an image formation apparatus configured to perform printing by switching to alternative sheets without changing (i.e., without reducing or enlarging) the image size of the image data, as disclosed in Patent Document 1 (Japanese Patent Application Publication No. 2006-89186).

Image formation apparatus, image formation system and image formation method


Techniques include: identifying one or more first entities who have connections to more than a threshold number of other entities; identifying first content in the search index that is authored by the first entities; and associating author restricts with the first content, where the author restricts include data identifying entities who authored corresponding content. The techniques may also include: identifying one or more second entities who have social connections to one or more entities who authored second content, where the one or more second entities have connections to less than the threshold number other entities; associating searcher restricts with the second content; and providing the search index updated with searcher and author restricts.

This specification relates generally to a data processing, particularly information retrieval using access controls.
Search engines identify resources (e.g., images, audio, video, World Wide Web (Web) pages, text, documents) that are relevant to a user's needs and present information about the resources in a manner that is useful to the user. A search engine may be used to conduct a search of a source of data, e.g., the Internet, a social network, an intranet, non-networked storage, and the like.


An electrical connector assembly for electrically connecting a printed circuit board and an electronic package, comprises an electrical connector on which the electronic package is mounted, a heat sink module mounted upon the electronic package and a clip positioned upon the heat sink module. The printed circuit board defines a connector mounting area surrounded by a plurality of through holes thereof. The clip has a base portion downwardly pressing against the heat sink module, a pair of mounting portions mounted to the corresponding holes, and a pair of pressing portions extending from the mounting portions and disposed on opposite sides of the clip for pressing against the heat sink module.

1. Field of the Invention
The present invention relates to an electrical connector assembly, and more particularly to an electrical connector assembly with a clip for positioning a heat sink module on an electrical connector in which the clip applies at least three pressing points on the heat sink to ensure a balanced positioning of the heat sink over an IC module.
2. Description of the Prior Art
Electrical connector is typically used for electrically connecting an electronic package and a printed circuit board, generally comprises an insulative housing, a plurality of contacts received in the insulative housing and a fastening device. The fastening device comprises a stiffener, a clip pivotally mounted to one end of the stiffener and a lever pivotally mounted to the other end of the stiffener. The clip is adapted to press the electronic package toward the insulative housing, and the lever is used to lock the clip to the stiffener. However, the lever and the clip need an enough room to be operated, so this type electrical connector can be applied to a desktop computer and is impossible to be applied to a notebook computer.
Electrical connector used in notebook usually uses another type of clip to fasten the electronic package to an insulative housing of the connector. A chip 6′ shown in FIG. 1 is a substantially rectangular configuration and has two parallel plate-form springs 61′. When the clip 6′ is locked down to the printed circuit board, the spring 61′ will apply a downward force toward the package disposed within the insulative housing through a heat sink in contact with the package. Because the spring 61′ features an excellent elasticity and it can be easily pushed downward to do the job. Accordingly, if the chip 6′ bears an excessive force, a corresponding deformation may occur and once it exceeds its yielding point, a permanent deformation might happen, thereby rendering the clip 61′ useless. Hence, we must limit the force that exerts to the chip 6′.
Applicant has applied a Taiwan Pat No. M349083 issued on Jan. 11, 2009 as referring to FIG. 2 to FIG. 4. FIG. 2 and FIG. 3 show the electrical connector assembly connecting an electronic package 3′ to a printed circuit board 1′. The electrical connector assembly comprises an insulative housing 2′ with a plurality of contacts (not shown) received therein to in contact with the electronic package 3′, a supporting body 40′ assembled with the heat plate (not labeled), and a pair of clips 44′ and heat pipe 43′ mounted on the supporting body 40′. Referring to FIG. 3, the clip 40′ is attached to the printed circuit board 1′ by a plurality of screws 12′, and exerts a downward loading force to press the electronic package 3′ to securely connect with the contacts (not shown). Referring to FIG. 4, the screws 12′ are disposed near the edges of the free ends of the clip 44′, so the free ends of the clip 44′ will experience deformations as latching forces which are caused by the screws 12′ are too large. That may reduce the loading force of the clip 44′ and influence the connection between the electronic package 3′ and the contacts.
Therefore, it is need to find a new electrical connector assembly to overcome the problems mentioned above.

Electrical connector assembly having improved clip mechanism


The present disclosure describes embodiments of a compactor for compressing test results in an integrated circuit and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover, any of the disclosed compactors can be designed, simulated, and/or verified in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool. Embodiments of a method for diagnosing faults in the disclosed compactor embodiments are also described.

As integrated circuits are produced with greater and greater levels of circuit density, efficient testing schemes that guarantee high fault coverage while minimizing test costs and chip area overhead have become essential. The number of transistors that can be placed on a chip has been doubling roughly every eighteen months, as predicted by Moore's law. The amount of data required to test such massively complex chips has been increasing even more rapidly. In practical terms, for very large integrated circuits, the test cost is approaching (and may even exceed) the design cost. To address the rapid increase in volume of test data, a number of compression schemes have been developed.
Many integrated circuits are tested using structured design-for-testability ("DFT") techniques, which employ the general concept of making some or all state variables (e.g., memory elements such as flip-flops and latches) directly controllable and observable. Preferably, a circuit is treated, as far as testing of combinational faults is concerned, as a combinational or a nearly combinational network. The most-often used DFT methodology assumes that during testing all (or almost all) memory elements are connected into one or more shift registers termed "scan chains." See, e.g., U.S. Pat. No. 4,503,537.
A circuit that utilizes scan chains for testing typically has two basic modes of operation: a normal mode, and a test (or scan) mode. In the normal mode, the memory elements perform their regular functions. In the scan mode, the memory elements become scan cells that are connected to form a number of scan chains. These scan chains are used to shift a set of test patterns into the circuit and to shift out circuit (or test) responses to the test patterns. The test responses are then compared to fault-free responses to determine if the circuit-under-test ("CUT") works properly.
Scan design methodology has gained widespread adoption by virtue of its simple automatic test pattern generation ("ATPG") and silicon debugging capabilities. Today, ATPG software tools are so efficient that it is possible to generate test sets (a collection of test patterns) that guarantee almost complete fault coverage of several types of fault models including stuck-at and transition faults. It is also possible to target other fault models such as path delay and bridging faults. Typically, when a particular potential fault in a circuit is targeted by an ATPG tool, only a small number of scan cells (e.g., 2-5%) need to be specified to detect the particular fault. These scan cells are termed "deterministically specified cells." The remaining scan cells in the scan chains can then be filled with random binary values, which are termed "randomly specified cells." This results in a pattern that is fully specified, that is more likely to detect additional faults, and that can be stored on a tester.
FIG. 1 is a block diagram of a conventional system 100 for testing digital circuits with scan chains. Two-input XOR gates, in this and subsequent figures, are represented by a circle inscribed with a cross 112. During a typical scan mode, external automated test equipment ("ATE") or tester 102 applies a set of fully specified test patterns 104 to a CUT 106 via scan chains 108 within the circuit. Once the scan chains 108 have been loaded with the test patterns 104, the CUT 106 is run in normal mode using the test patterns for input values. The CUT 106 may be run for a designated period of time (e.g., one clock cycle) after which the test responses to the test patterns are stored in the scan chains 108. With the circuit again in scan mode, the test responses are routed back to the tester 102, which compares the captured test responses with fault-free reference responses 110. A significant limitation of this approach is that it requires an expensive, memory-intensive tester and a long test time to test a complex circuit. For example, it has been reported that the volume of test data can exceed one kilobit per single logic gate in a large design. It is undesirable to test large circuits using this method, as it is difficult to store the large number of test patterns required, and the test application itself is too time intensive.
These limitations of time and storage can be overcome to some extent by adopting a built-in self-test ("BIST") framework as shown in FIG. 2. In BIST, additional on-chip circuitry is included to generate test patterns, evaluate test responses, and control the test. For example, a pseudo-random pattern generator 200 ("PRPG") is used to generate the test patterns instead of storing deterministic test patterns. Additionally, a multiple input signature register ("MISR") 202 can be used to generate and store a resulting signature from the test responses. MISRs, such as the one shown in FIG. 5, compress the data and generate a signature based on the scan chain input 502, and feedback 504, 506.
Due to the high volume of test data that needs to be processed in a CUT, compactors are often used to compress the test responses from the scan chains. This greatly simplifies determining if the circuit has flaws and the location of any problems that are discovered. Currently-available test response compaction schemes can be grouped into two classes: (1) infinite input response compaction schemes (also known as "time compactors"); and (2) space compaction schemes (also known as "space compactors" or "linear compactors").
Time compactors typically have a feedback structure with memory elements for storing a signature, which represents the results of the test. After the signature is completed, it is read and compared to a fault-free signature to determine if an error exists in the circuit-under-test. Time compactors may use polynomial division, counting-based techniques, and check-sum-based methods, and are typically employed in BIST applications. The actual compaction is usually performed by linear finite state machines, such as a linear feedback shift register ("LFSR"), a MISR, or cellular automata. These schemes are capable of compacting gigabits of test response data into a small signature that is typically 32-, 64-, or 128-bits long, thereby achieving compaction ratios between 106 and 108. This is possible because an error, once injected into this type of compactor, remains there until another group of errors erases it in the rare case of aliasing. The infinite input response compaction schemes suffer from a number of disadvantages. In particular, this type of compaction scheme cannot handle any unknown states in the test response. Because these systems all include feedback, an unknown state will circulate in the compactor endlessly until the compactor is reset. Thus, all states can become unknown after a few cycles, thereby corrupting the test signature and rendering the test useless. Fault diagnosis is also more complicated as it requires multiple passes with direct access to pre-compacted responses.
LFSRs are among the most popular time compactors used in integrated circuits. An LFSR produces pseudo-random test sequences. In its basic form, the LFSR (shown in FIG. 3) is modified to accept an external input in order to act as a polynomial divider. An alternative implementation is shown in FIG. 4. The input sequence, represented by a polynomial, is divided by the characteristic polynomial of the LFSR. As the division proceeds, the quotient sequence appears at the output of the LFSR and the remainder is kept in the LFSR. Once testing is completed, the content of the LFSR can be treated as a signature.
FIG. 5 shows another time compactor (which is a natural extension of the LFSR-based compactor) called a multiple-input LFSR, also known as a multiple-input signature register or MISR. A MISR may be used to test circuits in a multiple scan chain environment as shown in FIG. 5. MISRs feature a number of XOR gates coupled to the CUT scan-chain outputs and to the flip-flops of the shift register.
In contrast to time compactors, which employ memory elements in their compaction schemes, space compactors comprise combinational circuits that are predominantly built from XOR networks. The XOR network is configured to generate n test outputs from m primary outputs of the CUT, where n<m. Space compactors typically offer smaller compaction ratios than time compactors, but can handle some unknown states in the test responses without circuit modification. Another difference between spatial compactors and time compactors is that the output value of a spatial compactor will change with a change in just one input to the compactor, making single errors observable that would be undetectable after compression in a time compactor. With time compactors, a change in an input value may be obscured by the compression, and therefore go undetected at the output of the compactor. Even spatial compactors, however, may mask errors. For example, one basic characteristic of an XOR (parity) tree as typically used in a spatial compactor is that any odd-numbered combination of errors on its inputs will propagate to the outputs, but any even-numbered combination of errors will remain undetected. For instance, when the spatial compactor reads two errors at the same time, the multiple errors may cancel each other out so that the compressed signature of the faulty circuit mimics that of a fault-free circuit. This phenomenon is known as "error masking" or "aliasing" since it involves a first error state value erasing a second error state value. Aliasing is often measured in terms of its likelihood of occurrence.
Spatial compactors can be customized for a given CUT to reduce the aliasing phenomenon, such as shown in the U.S. Pat. No. 5,790,562, based on multiplexed parity trees or nonlinear trees comprising elementary gates such as AND, OR, NAND, and NOR gates. FIG. 6 shows one example of a modified spatial compactor. In particular, FIG. 6 shows a pipelined spatial compactor that includes a bank of flip-flops separating stages of XOR gates. A clock (not shown) controls the flip-flops and allows a one-cycle delay before reading the compacted output. Another spatial compaction technique, known as the X-compact scheme, has recently been proposed. See S. Mitra and K. S. Kim, "X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction," Proc. ITC, pp. 311-320 (Oct. 2002). A so-called "X-compactor" is understood to have no memory and no feedback. Thus, the output of the X-compactor is indicative of the current X-compactor input, and any error present at the output is clocked out after a single clock cycle. As more fully explained below, however, the amount of compaction that can be realized in an X-compact scheme is severely limited by the number of compactor outputs.
For any of the spatial compactors described above, the presence of unknown states can also be problematic for accurate error detection. For example, an unknown state on one or more inputs of an XOR tree generates unknown values at its output, consequently masking the propagation of any faults at the other inputs. Thus, one limitation of spatial compactors, such as the X-compactor and the compactor of FIG. 6, is that unknown states can reduce fault coverage. Moreover, time compactors, such as shown in FIGS. 3, 4, and 5, are restricted in their ability to handle unknown states since an unknown state on any input can corrupt the compressed output generated by the compactor. Additionally, if an error is detected within the integrated circuit, both spatial and time compactors have a limited ability to localize the fault.

Compressing test responses using a compactor


Methods and apparatus are disclosed to self-initialize a processor. An example method disclosed herein detects a processor reset, receives initialization instructions from a core zone, establishes a core zone boundary, executes received initialization instructions, and publishes a data structure, the data structure comprising state information. Other embodiments are described and claimed.

Computing devices, personal computers, workstations, and servers (hereinafter "computer" or "computers") typically include a basic input and output system (BIOS) as an interface between computer hardware (e.g., a processor, chipsets, memory, etc.) and an operating system (OS). The BIOS includes firmware and/or software code to initialize and enable low-level hardware services of the computer, such as basic keyboard, video, disk drive, input/output (I/O) port(s), and chipset drivers (e.g., memory controllers) associated with a computer motherboard.
Real mode is a central processing unit (CPU) operating mode that BIOS developers and manufacturers rely upon when initializing a computer. The real mode of CPU operation uses a segment register and an offset register, which are combined to form a linear address. Despite most CPUs having registers larger than 16-bits, such CPUs must begin early execution procedures in real mode based on, in part, backwards compatibility requirements and reliance upon legacy 16-bit real mode assembly language having only a very small region of code space for execution. Accordingly, third parties, such as computer platform manufacturers and operating system manufacturers, for example, accommodate such limitations by developing real mode assembly code for disk, video, and keyboard interrupts (Interrupts 13h, 10h, and 16h, respectively). These boot limitations, which include limited memory storage, retard feature enhancement for modern-day computer platforms.
More recent non-legacy CPUs, such as 64-bit processors, include a greater amount of initialization complexity and features. However, processors in real mode allow no more than 1 MB of addressable memory. Such complexity and features are significantly hindered by the inability to take advantage of the CPU's full register width, thus severely limiting execution code space. Accordingly, a relatively large amount of handcrafted assembly language must be developed to employ real mode addressing schemes regardless of the CPU's true register width. Furthermore, real mode does not allow memory protection and may permit direct software access to BIOS routines and peripheral hardware.
Coping with real mode limitations is not limited to BIOS manufacturers. For example, effort must be applied by CPU manufacturers, chipset manufacturers, and computer platform original equipment manufacturers (OEMs) to understand CPU specific initialization details, and write corresponding drivers to support initialization processes during a typical BIOS hand-off from real mode to a protected mode, long mode, or other mode. Accordingly, the CPU manufacturers must invest significant amounts of time and resources developing public architecture documents, interface documents, whitepapers, and other instructional materials so that third party consumers and developers can write software to accommodate the hand-off between real mode and long mode. For example, OEMs typically write 16-bit real mode code that is to be executed at the reset vector. Today, all of the hardware initialization, both for the CPU and the chipset, needs to be described to the original design manufacturer (ODM) and OEM in significant detail so that such OEMs can create their own version(s) of startup BIOS/firmware code. In the event that the CPU manufacturer makes changes to its product design, or develops a new product line, additional low-level operational disclosures (e.g., user-manuals, system documents, whitepapers, etc.) must be provided from the CPU manufacturer to the various vendors that use the CPU so that such vendors may develop compatible device driver code.

Methods and apparatus to self-initialize a processor


Methods and systems are disclosed that generally involve handling logins for a user accessing a plurality of computer resources. In one embodiment, once a user enters login information for a first computer resource, the login information can be stored and/or re-used to access a plurality of other computer resources without the user having to re-enter the login information for each resource. The methods and systems can involve a software framework in communication with various plugins, each plugin including one or more login candidates representing a type of a computer resource. The plugins and/or login candidates can allow the framework to pluggably and dynamically recognize and log into various types of computer resources.

Information services and data processing industries in general have rapidly expanded as a result of the need for computer systems to manage and store large amounts of data. As an example, financial service companies such as banks, mutual fund companies and the like now, more than ever before, require access to many terabytes of data and files stored in high capacity data storage systems. Other types of service companies have similar needs for data storage.
Data storage system developers have responded to the increased need for storage by integrating high capacity data storage systems, data communications devices (e.g., switches), and computer systems (e.g., host computers or servers) into so-called "storage networks" or "Storage Area Networks" (SANs).
A variety of storage systems (also referred to herein as "storage arrays" or simply "arrays") are known in the art. One example of a storage system is a collection of storage devices (e.g. hard disk drives) and associated communication, power, cooling, and management components. Such storage systems can also include one or more storage processors for handling both requests for allocation and input/output (IO) requests from a user. A storage processor can be the controller for and primary interface to the storage system.
Storage systems are typically used to provide storage space for one or more computer file systems, databases, applications, and the like. For this and other reasons, it is common for storage systems to be logically partitioned into chunks of storage space. This allows a unified storage system to appear as a collection of separate file systems, network drives, etc. Storage systems can be logically partitioned in a variety of ways. For example, the storage devices (e.g., disk drives) of a storage system can be logically organized into one or more RAID groups. A RAID group is a group of physical storage devices across which data can be distributed and/or replicated to achieve redundancy. This can avoid the loss or unavailability of data arising from a hardware failure such as a disk drive failure. Alternatively, or in addition, the physical storage area of a storage system can be mapped to one or more "logical units" (LUs).
In a storage area network, a collection of storage systems can be networked together via a switching fabric to a number of host computer systems operating as servers. The host computers can access data stored in the storage systems (of a respective storage area network) on behalf of client computers that request data from the data storage systems. For example, according to conventional applications, upon receiving a storage access request, a respective host computer in the storage area network can access a large repository of storage through the switching fabric of the storage area network on behalf of the requesting client. Thus, via the host computer (e.g., server), the client has access to the shared storage system. In many applications, storage area networks support high-speed acquisitions of data so that the host servers are able to promptly retrieve data from and store data to the storage system.
One or more management systems or applications are generally required to administer storage area networks. Conventional storage area network management applications typically include a graphical user interface (GUI) that enables a network manager to graphically manage, control, and configure various types of hardware and software resources associated with a corresponding managed storage area network. For example, a conventional storage management application can generate a GUI that can be used by a storage administrator to graphically select, interact with, and manage local or remote devices and software processes associated with the storage area network. The GUI, in combination with an input device such as a hand operated mouse and corresponding pointer displayed on a viewing screen or other display, can allow a storage administrator to manage hardware and software entities such as file systems, databases, storage devices, volumes, peripherals, network data communications devices, RAID groups, LUs, etc., associated with the storage area network. Consequently, a storage management station and associated management software enables a storage administrator (a person responsible for managing the storage network) to manage the storage area network and its resources.
One problem with existing management methods and systems is that each computer resource associated with a storage area network can require its own login procedure for authenticating a user to the resource. Since storage area networks usually include multiple such resources, there is a need for methods and systems that can efficiently authenticate or log in a user to multiple computer resources.
Another problem with existing methods and systems is that they cannot recognize or log into computer resources that were not supported or contemplated when the method or system was designed. Thus, there is a need for pluggable login methods and systems that can support logins to initially unrecognized systems via registration of an appropriate plugin.
Yet another drawback to existing methods and systems is that they cannot dynamically recognize the various computer resources available for a user to log into. A user must typically know the specific addresses and types of each resource in order to log into that resource. Accordingly, there is a need for methods and systems that can dynamically discover available computer resources and recognize the type or types of such resources.

This patent is subject to a terminal disclaimer.

Pluggable login architecture and dynamic resource recognition


An excitation coil and/or a core member, which has a characteristic frequency other than frequencies used, is employed. Thereby, resonance is prevented between adjacent coils or between a coil and an adjacent component such as a core member.

1. Field of the Invention
The present invention relates to a heating device that produces heat by making use of induction heating, and a fixing unit in which the heating device is mounted.
2. Description of the Related Art
A heating device using induction heating is employed in a fixing device that is mounted in an electrophotographic copying machine.
As is disclosed in, for instance, Jpn. Pat. Appln. KOKAI Publication No. 9-258586, in this kind of heating method, eddy current is caused in a fixing (heating) roller, using a coil that is wound around a core extending along the rotational axis of the roller. Thus, the roller is heated.
Jpn. Pat. Appln. KOKAI Publication No. 8-76620 discloses a heating device wherein magnetic field generating means applies a magnetic field to a heating belt so that the heating belt produces heat by induction heating. The heating belt is clamped between a pressing belt and the field generating means, thus forming a nip.
In this type of heating device using induction heating, radio frequency (RF) power is supplied to the excitation coil, thereby to quickly raise the temperature up to a level that is needed for fixation. As a result, resonance noise is produced due to resonance of the excitation coil.
Consequently, there arises such a problem that a holder member that holds the excitation coil, or a coil unit that includes a magnetic core for enhancing magnetic flux may be damaged.

Induction-heating apparatus operating with power supplied in a select frequency range


An optical connector end face grinding apparatus comprises a grinding apparatus main body, a sliding plate and a grinding bolder. The grinding apparatus main body further comprises an eccentric member driven by a motor and a guide pin. The sliding plate further provides a grinding pad on which is disposed a grinding film and moves in a reciprocal action along a guide pin in synchronism with the circular movement of the rotation of the eccentric member. An optical connector with a ferrule can be attached to and detached from the grinding holder, which positions the end face of the ferrule in a predetermined position relative to the grinding film in the rotational center of the eccentric member.

1. Field of the Invention
The present invention relates to an optical connector end face grinding apparatus applied for example for re-grinding the end face of a ferrule of an optical connector with attached optical fiber.
2. Description of Related Art
Generally, optical connectors (connectors with optical fibers attached) are used for connections between devices used by subscribers and devices used by a station. This type of optical connector is a device used for connecting or disconnecting a line and is designed with a structure capable of withstanding 1,000 connection/disconnection operations.
Because an optical connector is repeatedly connected and disconnected, dust existing in the atmosphere adheres to the ferrule end face of the optical connector. The optical fiber suffers minute damage because of this dust, which causes increased connection losses. Once damage has been done to an optical fiber, such losses cannot be reduced even by cleaning the ferrule end face using a cleaning tool and the damage must be repaired by re-grinding the end face of the optical fiber with a grinder.
Furthermore, the location at which connection and disconnection of an optical connector is performed is frequently a narrow, cramped space. Because an optical connector must be removed from a device and re-ground in such narrow, cramped spaces, a small simple, handy type grinding apparatus that is able to perform the grinding operation in such spaces must be used.
A conventional grinding machine used for this purpose has been disclosed, for example, in Japanese Unexamined Patent Application Publication No. 2002-18691. This kind of conventional grinding machine, however, requires complex mechanisms for the grinding action as the grinding plate makes a planetary movement while inducing incremental phase lag. Problems thus arise because miniaturization is rendered difficult, additional costs are incurred and maintenance becomes more burdensome.

Optical connector end face grinding apparatus


Provided is a room temperature moisture-curable silicone gel composition containing: (A) diorganopolysiloxane, both terminals of which are blocked by silanol groups; (B) hydrolysable organosilicon compound represented by Formula (2) and/or a partial hydrolysate thereof

Silicone gel compositions are generally prepared as addition reaction-curable organopolysiloxane gel compositions comprising an organohydrogenpolysiloxane having a silicon-bonded hydrogen atom (i.e., SiH group), an organopolysiloxane having a silicon-bonded alkenyl group such as vinyl, and a platinum-based catalyst wherein on heating, hydrosilylation addition reaction of the silicon-bonded hydrogen atom to the alkenyl group yields gel-like cured products. The silicone gel compositions are heat cured into silicone gel cured products, which find use in the protection of electronic parts including automobile electronic parts and consumer electronic parts because of improved heat resistance, weather resistance, oil resistance, freeze resistance, and electrical insulation as well as low elastic modulus and low stress. The low elastic modulus and low stress which are characteristic of the silicone gel cured product are not available from other elastomer products. The recent demand for automobile and consumer electronic parts having higher reliability imposes an increasing need to impart heat resistance to silicone gel materials for encapsulation.
For the silicone gel cured products obtained from addition curing of addition reaction curable organopolysiloxane gel compositions, it is known that as the temperature elevates above 150° C., a creep hardening phenomenon occurs that the silicone gel cured products gradually become harder, detracting from the low elastic modulus or low stress. As the measure for suppressing the creep hardening, in the case of general silicone rubbers, it is known effective to fill the rubbers with such fillers as carbon and iron oxide. For the silicone gel materials requiring a low viscosity and transparency, the means of filling the silicone materials with fillers is not readily acceptable because of many demerits including transparency drop, filler settlement, viscosity buildup, and working inefficiency.
JP-A 2008-291148 (Patent Document 1) describes the use of a cerium metal salt as the means for imparting heat resistance. On use of cerium, however, an outstanding creep hardening phenomenon is observed at temperatures above 230° C. A new means for imparting heat resistance is thus desired.
Recently, JP 5962599 (Patent Document 2) describes the use of iron carboxylate as the means for imparting heat resistance. Either of JP-A 2008-291148 and JP 5962599 requires to premix the salt with organopolysiloxane and heat treat the premix to form a reaction product, prior to addition. Like JP-A 2008-291148, an outstanding creep hardening phenomenon is observed at temperatures above 230° C.
Also, JP-A 2017-025232 (Patent Document 3) describes the use of nickel and niobium carboxylates as the means for imparting heat resistance. Like JP-A 2008-291148 and JP 5962599, an outstanding creep hardening phenomenon is observed at temperatures above 230° C. The technique of further improving heat resistance remains unsolved.

Room temperature moisture-curable silicone gel composition, and cured product and article therefrom

Abstract: (where R2 is a monovalent hydrocarbon group, R3 is an alkyl group or a cycloalkyl group, and a is 2 or 3.); (C) a curing catalyst; and (D) a heat-resistant aid containing a homogeneous mixture of (D-a), (D-b), and (D-c) (where (D-a) is organopolysiloxane having a viscosity of 10-10,000 mPa·s at 25° C., (D-b) is carboxylate of cerium, and (D-c) is a titanium compound and/or a partial hydrolytic condensate thereof). This room temperature moisture-curable silicone gel composition can be a silicone gel cured product which has a small variation rate of low-stress properties evaluated by the index such as penetration even under heat-resistant conditions exceeding 230° C. and which has excellent heat-resistance.


An error correction decoding unit performs error correction decoding of an inputted data series. A first memory is written with the data series subjected to error correction decoding by the error correction decoding unit. When the data series undergoing error correction decoding is written to the first memory, an address generator supplies write addresses and when the data series written to the first memory is read out of the first memory at random, the address generator supplies random read addresses.

The present invention relates to a turbo encoder and a turbo decoder for receiving coded data and decoding it while performing error correction and a radio base station provided with the turbo encoder and decoder.
In the next generation radio communication, communication is carried out using turbo coding in order to have the ability to withstand random and bust noises. In the turbo coding, a packet string (data series) X1 . . . Xn is generated by convolutionally coding data Xs and another packet string (data series) Y1 . . . Ym is generated by convolutionally coding data Ys which is changed in order in accordance with a predetermined rule described in "cdma 2000 High Rate Packet Data Air Interface Specification", pages 9–43 to 9–44, 3GPP2, C.S0024 (Version 2.0) published on Oct. 27, 2000 (hereinafter referred to as reference 1). Communication is done by transmitting and receiving (coding/decoding) these packet strings. Conversion of the order or sequence of the data series is called interleave and inverse conversion is called de-interleave.
Reference 1 discloses a method for the interleave and its FIG. 22.214.171.124.4.2.3-1 depicts a method of generating addresses for write/read of a data series to/from a memory and a method of making correction or recalculation in order to perform interleave. For example, where the data length of a data series is N (bits) and the data length of the data series removed of tail bits is N′ (bits), a data series having a data length N′=250 can be interleaved by issuing sequential addresses of from 0 to 249 by means of a counter and sequentially writing the data series to the memory. In the reference 1, however, random read addresses for the memory are calculated pursuant to the rule in reference 1 through a special method in order to maintain the ability to withstand noises. According this calculation method, addresses such as 251, 254 and so on at which data do not exist on the memory are calculated and therefore, correction or recalculation is carried out in the reference 1.
Accordingly, when realizing the address generator, it is necessary to provide the address correction function so as to regenerate addresses for read from the memory. When the address regeneration process such as above is carried out, the process for address generation becomes complicated in structure and superfluous processing time is needed, thus increasing delay in processing in the turbo decoder.
Generally, when concretely constructing the address generator, with fulfillment of correction in mind, corrected read addresses are tabulated in advance and read addresses calculated in reference 1 and the table as above are consulted to provide correct read addresses. For example, a technique described in JP-A-2001-53624 (hereinafter referred to as reference 2) adopts a method of storing addresses for write/read of data of the interleaver/de-interleaver in a memory.

Turbo decoder, turbo encoder and radio base station with turbo decoder and turbo encoder


Disclosed herein is a method for fabricating a memory device. According to the present invention, during an etching process for forming a recess gate region, a device isolation film is etched using a mask partially exposing a channel region and its neighboring device isolation film, and then a semiconductor substrate is etched, thus preventing a silicon horn in the recess gate region from being formed. Accordingly, a margin for the etching process is increased.

1. Field of the Invention
The present invention relates to fabricating a memory device. In particular, the present invention provides a method for fabricating a semiconductor device, and more specifically to a method for fabricating a semiconductor device wherein during an etching process for forming a recess gate region, a device isolation film is etched using a mask partially exposing a channel region and its neighboring device isolation film, and then a semiconductor substrate is etched to prevent a silicon horn in the recess gate region from being formed, thus increasing a margin for the etching process.
2. Discussion of the Related Art
FIG. 1 is a simplified layout of one semiconductor device.
Referring to FIG. 1, a device isolation film 40, an active region 10a and a gate structure 120 as a word line passing across the active region 10a are formed on a semiconductor substrate. A distance between the neighboring gate structures 120 is F, which is the minimum line width according to the design rules. A line-type recess gate region 60 is disposed under the gate structure 120. The line width of the recess gate region 60 is 2D smaller than that of the gate structure 120. That is, a misalignment margin of the recess gate region 60 is D.
FIGS. 2A through 2F are simplified cross-sectional views illustrating a conventional method for fabricating a semiconductor device, wherein FIGS. 2A(i) through 2F(i) are cross-sectional views taken along the line I-I′ of FIG. 1 and FIGS. 2A(ii) through 2F(ii) are cross-sectional views taken along the line II-II′ of FIG. 1.
Referring to FIG. 2A, a pad oxide film 20 and a pad nitride film 30 are deposited on a semiconductor substrate 10. Next, a device isolation film 40 defining an active region 10a is formed by performing an STI process.
Referring to FIG. 2B, the device isolation film 40 is etched to lower the height of the device isolation film 40. The pad nitride film 30 is then removed. Next, a polysilicon layer 50 is formed on the entire surface.
Referring to FIG. 2C, a photoresist film (not shown) is formed on the polysilicon layer 50, and then exposed and developed using an exposure mask defining the recess gate region 60 of FIG. 1 to form a line-type mask pattern (not shown) exposing the recess gate region 60. Next, the exposed polysilicon layer 50 and the pad oxide film 20 are etched using the mask pattern as an etching mask to form a polysilicon layer pattern 50a and a pad oxide film pattern 20a defining the recess gate region 60. Thereafter, the mask pattern is removed.
Referring to FIG. 2D, the exposed semiconductor substrate 10 is etched using the polysilicon layer pattern 50a as an etching mask to form a recess gate region 70. Here, the etching process may be performed to simultaneously etch the semiconductor substrate 10 and the polysilicon layer pattern 50a. At this time, the etching rate of the semiconductor substrate 10 closest to the device isolation film 40 is slower than that of the semiconductor substrate 10 spaced apart from the device isolation film 40, thereby forming a silicon horn 'A' on the semiconductor substrate 10 within the recess gate region 70. Next, the pad oxide film pattern 20a is removed.
Referring to FIG. 2E, a gate oxide film 80 is formed on the surface of the exposed semiconductor substrate 10. Thereafter, a lower gate electrode layer 90 filling up the recess gate region 70 is formed on the entire surface. An upper gate electrode layer 100 and a hard mask layer 110 are then sequentially deposited on the lower gate electrode layer 90.
Referring to FIG. 2F, the hard mask layer 110, the upper gate electrode layer 100 and the lower gate electrode layer 90 are patterned to form a gate structure 120 consisting of a stacked structure 120 of a lower gate electrode 90a, an upper gate electrode 100a and a hard mask layer pattern 110a.
FIG. 3 is a cross-sectional view illustrating misalignment occurring during the process of forming the recess gate region according to the conventional method for fabricating a semiconductor device.
Referring to FIG. 3, in case of misalignment occurring between a recess gate mask and a device isolation film mask by M larger than D such a maximum misalignment, the semiconductor substrate 10 of M-D between the device isolation film 40 and the polysilicon layer pattern 50a is exposed.
Accordingly, the exposed semiconductor substrate 10 as unwanted portion is abnormally etched during the etching process of FIG. 2D. As the size of the semiconductor device is reduced, the process margin for manufacturing the semiconductor device is also reduced. If the misalignment is increased, a problem occurs in which the unwanted semiconductor substrate shown in FIG. 3 is exposed and then abnormally etched. In addition, the silicon horn within the recess gate region is formed to lower the threshold voltage for a cell transistor and increase its leakage current, thus degrading the refresh characteristic of the device.

Method for fabricating semiconductor device


Disclosed is an apparatus and method for processing signals such as sound signals. The sound processing apparatus includes a sound signal input unit for receiving sound signals, a harmonic noise separator for separating a harmonic region and a noise region from the received sound signals, a noise restraint index determination unit for determining an optimal noise restraint index k according to a system and circumstance, and a noise restrainer for restraining the separated noise region depending on the noise restraint index k so as to output noise attenuated signals.

1. Field of the Invention
The present invention relates to a sound processing apparatus and method, and more particularly, to a sound processing apparatus and method which can efficiently attenuate noise according to a real time environment.
2. Description of the Related Art
Typically, in the field of sound signal processing, noise reduction is one of the most important issues to consider. Unfortunately, it is also one of the most difficult issues to solve.
Although conventional noise processing algorithms are applied using predetermined methods which take into account an expected noise elimination effect, they do not take into account their flexibility and utility with respect to various types of noise and circumstances. Rather, most conventional noise processing methods employ algorithms which use filtering methods that are assumed without respect to their application. Further, although conventional noise processing methods can process noise under various assumptions, they often fail to adequately process noise in many typical cases in which such assumptions are not suitable. Thus, few commercially available noise removal algorithms are applicable to filtering noise that exists in a real environment.


A carbon-based composite particle for an electron emission source comprises a particle of a material selected from the group consisting of metals, oxides, and ceramic materials; and a carbon-based material such as a carbon nanotube which is partially embedded inside the particle and which partially protrudes from the surface of the particle.

(a) Field of the Invention
The present invention relates to a carbon-based composite particle for an electron emission display device and a method for preparing the same, and, more particularly, to a carbon-based composite particle having a high level of electron emission and a method for preparing the same.
(b) Description of the Related Art
Earlier field emission displays (hereinafter referred to as "FED") were made of a spindt-type electron emission source including Mo or Si, with sharp tips of sub-micron size. Since the spindt-type electron emission source is assembled with sharp tips of a sub-micron size, the method of fabricating the same requires a great deal of attention, and such an operation is considered high-level precision work. Therefore, it is difficult and expensive to produce a large-sized field emission display device according to this method.
Carbon material has recently emerged as a potentially useful electron emission source due to its low work function. One carbon material, a carbon nanotube (CNT), is particularly expected to be an ideal electron emission source since it features a high aspect ratio and a small tip radius of curvature of 100 Å, and thereby electrons are readily emitted by applying an external voltage of as low as 1˜3 V/μm.
Generally, the electron emission source is fabricated in such a manner that the carbon nanotubes are formed in a paste with a solvent, a resin, and so on, the paste is applied between substrates by a screen-printing method, and then it is sintered. Since the carbon nanotubes have a low work function, the resultant electron emission source can be driven by applying low voltages, and the method of fabricating the same is not complicated. It will thereby offer advantages for large size panel displays.
However, when the electron emission source is produced with carbon nanotubes by the screen-printing method, each carbon nanotube is roughly mixed with a solid powder present in the paste and irregularly distributed in the solid powder, so that the tips of most of the carbon nanotubes are covered by the solid powder. In addition, most of carbon nanotubes are oriented in a direction parallel with the substrate instead of the direction perpendicular to the substrate which is where the electro-field is applied. Accordingly, the ratio of carbon nanotubes incapable of emitting electrons to all carbon nanotubes is increased so that the electron emission capabilities are not fully utilized. Generally, an electron emission cathode fabricated by such method has a planar shape so that the surface area is minimized.
Therefore, there are considerable demands to find a way to expose the tips of the carbon nanotubes. As one scheme to satisfy such demands, Korean laid-open patent publication No. 2000-74609 discloses that carbon nanotubes are admixed to metal powders. However, this method requires an additional process to expose and align the carbon nanotubes, rendering the process overly complicated. Further, it is difficult to align many carbon nanotubes perpendicularly, and only a few metal particles have been observed to have carbon nanotubes on the surface thereof.
Further, Japanese laid-open patent publication No. 2000-223004 discloses a method for exposing the carbon nanotubes in which carbon and the metal particulate are mixed and compacted, then the compacted mixture is cut and selectively etched. However, this method is also quite complicated and is difficult to apply to a field emission device of an electron emission array.
Moreover, Japanese laid-open patent publication No. 2000-36243 discloses a method in which a laser beam is irradiated on the surface of a printed pattern in which carbon nanotubes are covered with silver particles combined with a binder, and the silver particles and the binder present on the surface are selectively removed, so that the carbon nanotubes are exposed. However, such laser irradiation can tend to thermally damage the carbon nanotubes.

Carbon-based composite particle for electron emission device, and method for preparing


Provided is a hybrid substrate with high density and low density substrate areas and a method of manufacturing the same. The hybrid substrate with high density and low density substrate areas includes a low density substrate layer having a cavity and a low density area, a high density substrate layer mounted in the cavity of the low density substrate layer and formed of a high density area having a higher pattern density than that of the low density area, an insulating support layer comprising a deposition area formed on upper portions, lower portions and the upper and lower portions of the high density substrate layer and the low density substrate layer, insulating layer vias passing through the deposition area of the insulating support layer and connected to patterns of the high density substrate layer and the low density substrate layer, and an outer pattern layer.

1. Field of the Invention
The present invention relates to a hybrid substrate with high density and low density substrate areas and a method of manufacturing the same, and more particularly, to a hybrid substrate with high density and low density substrate areas, in which a high density substrate layer is installed in a cavity of a low density substrate layer, and a method of manufacturing the same.
2. Description of the Related Art
In recent times, application of high integrated chips such as a flip chip or the like according to development of high speed devices is being gradually increased. An abrupt increase in number of input/output (I/O) units according to improvement in performance of the devices is caused by an abrupt reduction in line width of a substrate circuit. For this, a large amount of equipment investment of processes related to exposure, plating, etching, or the like, is needed. In order to minimize the investment and deal with high density devices, a technique of integrating both of a high density circuit substrate and a low density circuit substrate is needed.
Here, when high density and low density circuits are packaged together, for example, the high density circuit substrate is applied to a substrate, a portion of which is directly connected to a chip, in proportion to integration of the device, and the low density circuit substrate is applied to a substrate, a portion of which is connected to a mother board.
In a conventional package of the high density and low density substrates, a high density substrate layer is mounted on a low density substrate layer. However, when the high density substrate layer is mounted on the low density substrate layer, a thickness of the substrate may be increased, and the thickness of the substrate may be severely varied.

Hybrid substrate with high density and low density substrate areas, and method of manufacturing the same


A player can easily select a desired game, and the information about players can be appropriately managed and provided. A user terminal transmits self-introduction information to a room master. The room master adds the self-introduction information from the user terminal to the player table list. Additionally, the self-introduction information is added to update history data, and a count value of the update history counter is incremented. The user terminal adds the current count value of the update history counter and ask the room master for an update history. Upon receipt of the update history requests from multiple user terminals, the room master transmits data to all user terminal members (addressed to the IRC channel) in the room. The data is transmitted sequentially from the update history data associated with the oldest update counter value in the requests to the update history data associated with the latest history counter value of the room master.

1. Field of the Invention
The present invention relates to an online game system. More particularly, the present invention relates to player information management.
2. Description of the Related Art
Recently, there has been an increasing number of video games (online games) operating on a network in which multiple players can simultaneously take part in a game using the network. In an online game, multiple terminals operated by respective players are connected to a game server group through a network, and communications are established between the terminals and the game server group. The game server group includes a server to which multiple video game machines are connected so that players can select other players to play with. The server can be referred to as a lobby server because it provides a virtual lobby for communications among players.
When a video game machine is connected to a lobby server, a screen showing a virtual 'lobby' is displayed on the display device of the video game machine. On the lobby screen, the character of a player and the characters of other players connected to the lobby server are displayed. The player can chat with other players so that they can communicate with one another and look for other players to play with.
When a desired game is selected from the menu displayed on the lobby screen, a video game machine is connected to one of the game servers in the game server group, and the game screen is displayed on the display device of the video game machine, thereby starting the game.
However, when there are an enormous number of selectable games, a player cannot easily select a desired game on the lobby screen. Therefore, the lobby is divided into multiple sections so that the players can easily select desired games. However, when a lobby is divided into a number of sections, the information about players in each section cannot be strategically provided. As a result, the information about the players in each section cannot be appropriately offered. Furthermore, dividing a lobby into a number of sections complicates management of the information about players, thereby assigning a heavy load to the server system and the network.

Management of player information in a multiplayer network game environment


A method for idling vehicle detection comprises shining a light source on an exterior surface of a vehicle with an illumination module, collecting light reflected from the exterior surface of the vehicle with a capture module, and processing the collected light reflected from the exterior surface of the vehicle surface with a processing module wherein the processing model determines if the vehicle's engine is running or if the vehicle's engine is not running.

Vehicles that are left running while unoccupied or not in use can pose a variety of risks. For example, vehicles left idling at fueling stations can lead to explosions. Likewise, vehicles left idling in closed spaces such as parking structures, garages, or parking lots, pose both pollution and health risks due to accumulation of exhaust gas. With increasing concerns about pollution associated with combustion engines, it is increasingly important to curtail unnecessary idling of vehicles.
In consideration of these concerns, more than 25 states have passed legislation that prohibits idling trucks for longer than a specific period of time. In some counties it is illegal to allow a vehicle to run when stationary for various other reasons.
Traditional video surveillance systems are not well equipped to detect vehicle vibrations because the amplitude of vibration of an idling vehicle is too small to be detected. Typical surveillance cameras have sensor resolutions in the range of a few Megapixels and a field of view on the order to several square meters. Vehicle vibration amplitudes resulting from a running engine therefore translate to sub-pixel motion events. Therefore a need exists for an improved method and system for automatic detection of running engines in stationary motor vehicles.

Automated running-engine detection in stationary motor vehicles


A book is provided to teach and encourage writing skills which includes a picture printed on each leaf of a multi-leaved tear-off pad of identical leaves in each bundle of pages. The picture page is without words but has space in which the learner, typically a child, will generate writing to form a story which the learner imagines from viewing the picture. The multiple leaves, each having an identical picture, provide for the learner to tear off the top picture when a story has been written by the learner. Having a pad of identical pictures in each bundle of leaves provides the learner with a plurality of opportunities to re-formulate his or her written story, or to write a variety of different stories based upon the same picture. The sheets which have been written upon and then torn off from the picture pad will comprise a portfolio of the learner's educational progress. The teaching book is comprised of a number of such picture pads bound together to form a larger aggregate tear-off pad.

Various patents have utilized books as learning aids in promoting language skills.
For example, U.S. Pat. No. 3,704,338 of Shore describes a book with pictures. Underneath the pictures are provided slits with which playing piece blocks with letters affixed thereon are placed to create words. However, Shore does not provide for a plurality of pages wherein each completed page may be removed to create a permanent text.
U.S. Pat. No. 3,775,868 of Moore provides a base board with slots for geometrically shaped blocks. Moore does not entail the use of words with pictures.
U.S. Pat. No. 4,063,369 of Hart describes a book without pictures or words wherein a child selects various graphic pictorial pictures, such as a pumpkin, trees, owls or buildings to assemble a picture design on each page. Hart does not encourage the user to write words with the pictures. It is designed for pre-school children.
U.S. Pat. No. 4,176,473 of Rae provides a book with removable figurines to be inserted within slots provided in thick pages of a book. The words of a text to accompany the pictures are pre-printed upon the pages, so that the user does not use any creativity in developing a written text.
U.S. Pat. No. 4,597,743 of Becker describes a multi-leafed book which is provided on wheels, in the shape of a vehicle, such as a fire truck. It does not involve the encouragement of creative writing of a child.
U.S. Pat. No. 4,650,426 of Brigance discloses a loose leaf book wherein each page has a plurality of different geographic panels portions corresponding to differing subject matters, such that answers are revealed underneath each panel portion having questions thereon. Brigance does not teach the use of a plurality of pages with pictures to encourage creative writing.
U.S. Pat. No. 3,758,693 of Ebert a book with magnetic pages having pictorial maps depicted thereon, so that a child can move a playing piece such as an automobile, throughout selective roadway portions of the maps.
U.S. Pat. No. 4,896,888 of Owen describes an ocean yacht racing game in which a weather book is used in conjunction with a playing board to move yacht playing pieces in response to the weather depicted in each chosen page of the weather book.
U.S. Pat. No. 4,909,542 of Marks describes a three dimensional book in the shape of a soft animal.
U.S. Pat. No. 4,943,088 of Wada provides a book with pictures. A space is provided for a user to write words on the pages with an erasable, water soluble ink. Wada does not involve the permanent inscription on a page of a plurality of pages so that a set of pages with writing may be preserved. Wada does not provide for a sequential group of wordless pages upon which a child writes his or her own story. In fact, text is provided on each page in Wada, and the spaces are provided for the child to write or scribble other comments. Wada therefore does not teach a picture book without words, wherein the pictures are sequentially and strategically placed to encourage a child to write a story from the hints given in the pictures.
U.S. Pat. No. 5,080,590 of Frisque describes a book with tracing pages to trace images underneath transparent foil tracing pages.
U.S. Pat. No. 5,111,224 of Spector describes a photo album used in conjunction with a camera wherein a user writes text underneath the photographic pictures selected by the user. However, Spector does not teach the use of a preselected pictorial story line to encourage a child to write a story from the introduction through the climax to a conclusion, in an orderly manner which allows creative input from the child.


A phase change memory device comprises a cell array unit including a phase change resistance cell disposed in a region where a word line and a bit line are crossed, a sense amplifier configured to sense and amplify data of the phase change resistance cell, a write driving unit configured to supply a write voltage corresponding to data to be written in the cell array unit in response to an enabling signal, and a write verifying control unit controlled by an activation control signal and configured to compare data read through the sense amplifier with the data to be written so as to output the enabling signal.

Generally, nonvolatile memories such as magnetic memory and phase change memory (PCM) have a data processing speed of a random access memory (RAM), and a data preserving characteristic even when a power source is off.
FIGS. 1a and 1b are diagrams illustrating a conventional phase change resistor (PCR). A PCR 4 includes a phase change material (PCM) 2 inserted between an upper electrode 1 and a lower electrode 3. When a voltage and a current are applied, a high temperature is induced to the PCM 2 so that an electric conductive state is changed depending on resistance change.
The PCM 2 includes AgInSbTe. As a material of the PCM 2, Chalcogenide having S, Se and Te of chalcogen as a main ingredient, can be used. Specifically, germanium antimony tellurium alloy (Ge2Sb2Te5) consisting of Ge—Sb—Te is used.
FIGS. 2a and 2b are diagrams illustrating a principle of the conventional PCR. As shown in FIG. 2a, when a low current of less than a critical value flows in the PCR 4, the PCM 2 has a proper temperature to be crystallized. As a result, the PCM 2 enters a crystalline phase to become a low resistance material.
As shown in FIG. 2b, when a high current of more than a critical value flows in the PCR 4, the PCM 2 has a temperature over a melting point. As a result, the PCM 2 enters an amorphous phase to become a high resistance material.
The PCR 4 can store nonvolatile data corresponding to the two resistance states. That is, logic states of two data can be stored if when the PCR 4 is in a low resistance state is data "1" and when the PCR 4 is in a high resistance state is data "0".
FIG. 3 is a diagram illustrating a write operation of the conventional PCR. When a current flows between the upper electrode 1 and the lower electrode 3 of the PCR 4 for a given time, a high heat is generated. As a result, the PCM 2 becomes crystallized and amorphous by a state of temperature applied to the upper electrode 1 and the lower electrode 3.
When a low current flows for a given time, the PCM 2 becomes crystallized by a low heating state so that the PCR 4 which is a low resistor enters a set phase. When a high current flows for a given time, the PCM 2 becomes amorphous by a high heating state so that the PCR 4 which is a high resistor enters a reset phase. As a result, a difference of the two phases is represented as an electric resistance change.
In order to write the set state in a write mode, a low voltage is applied to the PCR 4 for a long time. On the other hand, in order to write the reset state in the write mode, a high voltage is applied to the PCR 4 for a short time.


An image forming apparatus includes an overheat prevention device to control a heater based on a fusing temperature detected by a temperature sensor within a predetermined range when a controller generates an abnormal heater control signal.

1. Field of the Invention
The present general inventive concept relates to an image forming apparatus to cope with an error of a controller to control a fusing temperature.
2. Description of the Related Art
An electrophotographic image forming apparatus, such as a printer, multifunction printer or the like, includes a fusing device for fusing a toner image transferred onto print paper.
The fusing device is adapted to actuate a heater through a controller to melt toner powder transferred onto the print paper.
The controller is adapted to control a fusing temperature based on a predetermined reference fusing temperature to cope with an excessive increase in the fusing temperature resulting from a malfunction in the fusing device or an electric circuit supplying power to the heater.
Together with this operation of controlling the fusing temperature, the controller acts to perform an operation of compulsorily cutting off power to the heater by a bimetal when the fusing temperature increases excessively.
On the other hand, the heater may be erroneously actuated due to an abnormal output of the controller. Where the heater is erroneously actuated in response to a control command from the controller, the fusing temperature rises. At the time that the fusing temperature rises excessively, the actuation of the heater is stopped by the bimetal and the fusing temperature thus falls. However, even though the fusing temperature falls just a little, the cut-off operation by the bimetal is released, so that the heater is again actuated by the control command from the controller. As a result, in spite of the fact that a fusing process is not actually required, a high fusing temperature may be maintained due to a wrong control command resulting from an error in the controller, so that the fusing device may be so overheated as to melt the structure thereof.


An assembly set includes a base member that has a pair of cylindrical parts and a connection part, a connector member, and a rod member. Each of the cylindrical parts has a first columnar protrusion protruding from one end and a first cylindrical boss portion positioned within the cylindrical part. The first protrusion of another base member is fitted between an inner peripheral surface of the cylindrical part and the first boss portion. The rod member has a pair of coupling parts fitted into the connector member and a rod part connecting the pair of coupling parts. The connector member has a second columnar protrusion fitted into the first boss portion and a pair of second cylindrical boss portions into which the coupling parts are fitted to swingably hold the rod member.

Patent Literature 1 describes an assembly structure in which two cylindrical parts are coupled together. In the assembly structure, each of the cylindrical parts has protrusions at one end and has an annular boss at the other end on the inner periphery. A plurality of assembly structures can be assembled by fitting protrusions of another assembly structure between an inner peripheral surface of the cylindrical part and the boss. In addition, the assembly structure is designed such that two assembly structures can be coupled together to cross each other by connecting smoothly the two cylindrical parts. This makes it possible to create organic-looking forms imitating animal skeletons. In addition, the assembled assembly structures can rotate with respect to each other.