There is provided a fuel cell system comprising: a stack for generating electric energy through a reaction between hydrogen and oxygen; a reformer for generating hydrogen from fuel through a catalytic reaction of the fuel using thermal energy and for supplying the generated hydrogen to the stack; a fuel supply unit for supplying the fuel to the reformer; and an oxygen supply unit for supplying oxygen to the reformer and the stack. The reformer comprises: a tubular reactor body; a heat source section which is formed in the inner space of the tubular reactor body and which generates thermal energy in a predetermined temperature range through an oxidation reaction of fuel; a reforming reaction section which is formed successive to the heat source section and which generates hydrogen from the fuel through a reforming reaction using the thermal energy; and a heat delivery unit which is provided in contact with the tubular reactor body and which delivers the thermal energy to the fuel supplied to the reforming reaction section.

As is well known, a fuel cell is a system for generating electric energy through an electrochemical reaction between oxygen and hydrogen contained in hydrocarbon materials such as methanol, ethanol, or natural gas.
Recently developed polymer electrolyte membrane fuel cells (hereinafter, referred to as PEMFCs) have excellent output characteristics, low operating temperatures, and fast starting and response characteristics. PEMFCs may be used for a wide range of applications including mobile power sources for vehicles, distributed power sources for homes or buildings, and small-sized power sources for electronic apparatuses.
A fuel cell system employing the PEMFC scheme basically includes a stack, a reformer, a fuel tank, and a fuel pump. The stack constitutes an electricity generation set having a plurality of unit cells and the fuel pump supplies fuel from the fuel tank to the reformer. There, the reformer reforms the fuel to generate hydrogen that is supplied to the stack.
The reformer generates hydrogen from the fuel through a catalytic chemical reaction using thermal energy, and includes a heat source section where thermal energy is generated, and a reforming reaction section where thermal energy is absorbed to generate hydrogen from the fuel.
However, in the reformer of a conventional fuel cell system, since the heat source section and the reforming reaction section are typically separated from one another and connected to each other through pipes, there is no direct heat exchange between the sections. Accordingly, such a system generally requires a preheating time for the reforming reaction section, and further, because the heat delivery path is elongated, the thermal efficiency is poor. In addition, since the respective sections are separated, it is difficult to make the system compact.
Furthermore, for a conventional fuel cell system, since the fuel supplied to the reformer generally must be preheated with an additional preheating device, much energy is spent in preheating the fuel, thereby deteriorating the performance and thermal efficiency of the entire system.

Reformer and fuel cell system having the same


A spray gun for coating golf balls having an axial bore formed therein. The bore has a first end connected to an air compressor for receiving a flow of air therefrom and a second open end defining a nozzle. Each spray gun further includes a first paint input channel for receiving a first fluid. The first paint input channel has an outlet in communication with the axial bore for injecting the first fluid into the flow of air. Each spray gun also has a second paint input channel for receiving a second fluid, wherein the second paint input channel has an outlet in communication with the axial bore for injecting the second fluid into the flow of air. The outlet of the second paint input channel is offset from the outlet of the first paint input channel.

1. Field of the Invention
The present invention relates to a golf ball paint delivery system and more particularly pertains to mixing paint adjacent to a nozzle of a spray gun from which the paint is delivered.
2. Description of the Prior Art
The use of paint delivery systems is known in the prior art. More specifically, paint delivery systems heretofore devised and utilized for the purpose of coating golf balls are known to consist basically of familiar, expected and obvious structural configurations, notwithstanding the myriad of designs encompassed by the crowded prior art which have been developed for the fulfillment of countless objectives and requirements.
In this respect, the golf ball paint delivery system according to the present invention substantially departs from the conventional concepts and designs of the prior art, and in so doing provides an apparatus primarily developed for the purpose of mixing paint adjacent to a nozzle of a spray gun from which the paint is delivered.
Therefore, it can be appreciated that there exists a continuing need for a new and improved golf ball paint delivery system which can be used for mixing paint adjacent to a nozzle of a spray gun from which the paint is delivered. In this regard, the present invention substantially fulfills this need.


A method of identifying an egress point to a network location includes receiving a client connection from an external network (e.g., the internet) and retrieving an egress point identifier from an egress data source (e.g., a database, look-up table, hash table, data object etc.) for the received client connection. The egress data source stores egress point identifiers associated with at least one of an internet protocol address and a subnetwork. The method further includes binding the client connection to an egress point corresponding to the retrieved egress point identifier, encapsulating packets of data received from the client connection, and sending the encapsulated data packets through an instantiated network tunnel to the bound egress point. The method includes decapsulating the encapsulated data packets at least near the bound egress point. A default routing policy may then guide the data packets to the egress point.

In general, autonomous systems (AS) having networks under a common administrator may share a common routing policy for communication therebetween, such as border gateway protocol (BGP). Within each autonomous system, the routing protocol typically entails an interior gateway protocol (IGP), such as a link state protocol.
Link state protocol generally relies on a routing algorithm executed at each network node. Each node on the network advertises, throughout the network, links to neighboring nodes and provides a cost associated with each link, which can be based on any appropriate metric such as link bandwidth or delay and is typically expressed as an integer value. A link may have an asymmetric cost, that is, the cost in a first direction along a link may be different from the cost in a second, reverse direction. Based on the advertised information in the form of a link state packet (LSP) each node constructs a link state database (LSDB), which is a map of the entire network topology, and from that constructs generally a single route to each available node based on an appropriate algorithm such as, a shortest path first (SPF) algorithm. As a result, a spanning tree is constructed, rooted at the node and showing a communication path including intermediate nodes to each available destination node.
The results of the spanning tree can be stored in a routing information base (RIB) and based on these results the forwarding information base (FIB) or forwarding table is updated to control forwarding of packets appropriately. When there is a network change a link state packet representing the change is flooded through the network by each node adjacent the change, each node receiving the link state packet sends it to each adjacent node. As a result, when a data packet for a destination node arrives at a node the node identifies a route to that destination and forwards the packet to the next node along that route. The next node repeats this step and so forth.

Identifying an egress point to a network location


The invention is based on the discovery that compositions containing certain maleimide compounds and aromatic diene compounds are useful as thermosetting resins for the electronic packaging industry. The invention compositions described herein can be cured in a variety of ways, with or without a catalyst. In some embodiments, the well-known “ene” reaction can be used to cure the compositions described herein, and therefore no catalyst is required.

As the electronics industry advances, and production of light weight components increases, the development of new materials gives producers increased options for further improving the performance and ease of manufacture of such components. Adhesive compositions, particularly conductive adhesives, are used for a variety of purposes in the fabrication and assembly of semiconductor packages and microelectronic devices. The more prominent uses include bonding of electronic elements such as integrated circuit chips to lead frames or other substrates, and bonding of circuit packages or assemblies to printed wire boards.
Adhesives used in the electronic packaging industry typically contain a thermosetting resin combined with a filler and some type of curing initiator. These resins are primarily used in the electronics industry for the preparation of non-hermetic electronic packages. Adhesives useful for electronic packaging applications typically exhibit properties such as good mechanical strength, curing properties that do not affect the component or the carrier, and rheological properties compatible with application to microelectronic and semiconductor components. Examples of such packages are ball grid array (BGA) assemblies, super ball grid arrays, IC memory cards, chip carriers, hybrid circuits, chip-on-board, multi-chip modules, pin grid arrays, and the like.
For all these applications, the microelectronics industry continues to require new resins that are able to meet its varying demands. Accordingly, there is a need for the development of materials to address the requirements of this rapidly evolving industry.
An even broader need is for high performance matrix resins and adhesives for use in high performance applications. These applications include temperature resistant adhesives and components for use in automobile engine compartments, brake pads, aerospace re-entry vehicles, engine nacelles, kilns and boilers, etc. Other applications include those where a combination of high modulus and toughness are required such as in sail boat masts, golf clubs, tennis rackets, and airplane parts.
Bismaleimides have been an attractive class of thermoset resins because of their unique performance advantages. Bismaleimides can be cured via a variety of mechanisms. Homo-cures of bismaleimides produce polysuccinimide thermosets. These cross-linked polysuccinimides generally yield high glass transition temperature thermosets with excellent heat resistance and stiffness. However, the homo-cured bismaleimide resins are also noted for their extreme brittleness. One useful approach that has been used to improve the fracture toughness of bismaleimide thermosets has been to co-cure them with diene or polyene compounds via "ene" and/or Diels/Alder reactions. These co-cures can result in thermosets that retain the high thermal performance advantages of the original polysuccinimides while also providing a substantial improvement in fracture toughness.
The commercially available "ene" and/or Diels-Alder curatives for bismalemides include a variety of allyl and propenyl functional compounds. Examples of these compounds are shown below as C-1 through C-9. The most attractive curatives are those that can participate in both "ene" and Diels-Alder reactions (i.e. compounds C-1 through C-5). The C-6 through C-9 bismaleimide curatives, even though they generally co-cure with bismaleimides via the ene reaction alone, can be used at low levels as reactive diluents.
All of the commercial allyl and propenyl curatives react with bismalemides in one or more steps to yield thermoset resins. These reactions must generally be conducted at temperatures well above 200° C., and often over several hours. Furthermore, all of the dual reactive curatives (i.e. C-1 through C-5) are extremely viscous liquids or solids. The relatively low viscosity reactive diluents may be added, but their use is restricted by their inability to participate in both the "ene" and Diels-Alder reactions. Thus, the addition of significant levels of compounds C-6 through C-9 would degrade the performance of the final thermosets. There remains, therefore, a need for improved curatives for bismaleimide monomers.

Maleimide compositions and methods for use thereof


A method of forming and resulting isolation region, which allows for densification of an oxide layer in the isolation region. One exemplary embodiment of the method includes the steps of forming a first trench, forming an oxide layer on the bottom and sidewalls of the trench, forming nitride spacers on the lined trench, and thereafter etching the silicon beneath the first trench to form a second trench area. An oxide layer is then deposited to fill the second trench. Densificiation of the isolation region is possible because the silicon is covered with nitride, and therefore will not be oxidized. Light etches are then performed to etch the oxide and nitride spacer area in the first trench region. A conventional oxide fill process can then be implemented to complete the isolation region.

Typically in semiconductor device applications, numerous devices are packed into a small area of a semiconductor substrate to create an integrated circuit. Generally, these devices need to be electrically isolated from one another to avoid problems among the devices. Accordingly, electrical isolation is an important part of semiconductor device design to prevent unwanted electrical coupling between adjacent components and devices.
Shallow trench isolation (STI) is one conventional isolation method. Shallow trench isolation provides very good device-to-device isolation. A shallow trench isolation process generally includes the following steps. First, a trench is formed in a semiconductor substrate using wet or dry etching with a mask. Then, an insulating layer is deposited on the entire surface of the semiconductor substrate to fill the trench. Finally, chemical mechanical polishing (CMP) is used to planarize the insulating layer. The insulating layer remaining in the trench acts as an STI region for providing isolation among devices in the substrate. Additionally, a nitride and/or oxidation layer may be formed on the sidewalls and bottom of the trench before depositing the insulating layer.
As semiconductor devices get smaller and more complex and packing density increases, the width of the STI regions also decreases. In addition, for certain types of electronic devices, a deeper isolation trench is desired. This leads to trench isolation regions with high aspect ratios; aspect ratio refers to the height of the trench compared to its width (h:w). An aspect ratio of greater than or equal to about 3:1 is generally considered a high aspect ratio. Even when filling an isolation trench with a high-density plasma having good filling capability, voids or seams may still exist in the isolation regions. These defects cause electrical isolation between the devices to be reduced. Poor isolation can lead to short circuits and can reduce the lifetime of one or more circuits formed on a substrate.
FIG. 1 illustrates a high aspect ratio isolation trench 11 formed in a semiconductor substrate 10 in accordance with the prior art. Before forming the isolation trench 11, other layers may be deposited over the semiconductor substrate 10, for example, layers used to form gate structure, including an oxide layer 12, a polysilicon layer 14, and a nitride layer 16. After a trench 11 is formed, an insulating layer 20 is deposited over the semiconductor substrate 10 to fill the trench 11. The insulating layer 20 can be deposited using high-density plasma chemical vapor deposition (HPDCVD). Due to the high aspect ratio of the trench 11, the HPDCVD process will leave void regions 22 in the insulating layer 20. This occurs because in the process of depositing the insulating layer 20, the insulating layer 20 on the sidewalls at the top of the trench 11 grows thicker than the portion closer to the bottom of the trench 11. Therefore, the opening at the top of the trench 11 becomes closed-off before the entire volume of the trench 11 can be filled, causing the void regions 22 which diminishes the isolation properties of the filled trench 11.
One other problem that has been experienced during known trench formation is that silicon and/or polysilicon becomes oxidized when exposed to high ambient temperatures, such as when put in a furnace for steam densification. This oxidation results in undesirable changes to the properties of the oxidized material.
Accordingly, there is a need and desire for a method of forming shallow trench isolation region that achieves good isolation, but minimizing the drawbacks experienced with conventional trench isolation formation.

Method of making an isolation trench and resulting isolation trench


A modified parser generator enables the parsing of programs such as C programs with preprocessor directives and implemented extensions to the normal abstract syntax tree representation of programs to create an integrated representation structure.

The present invention is more particularly useful where the programming language has a relatively loosely integrated macro processor. While the invention is not restricted to any specific language, it will be useful in the present explanation to use the C language as an illustratory example of a language having such a loosely integrated macro processor.
One well-known shortcoming of the C programming language is the poor integration of its macro preprocessor with the C grammar. This presents many problems to C language tools such as structure editors, view-oriented program browsers, or program transformation tools that try to integrate the syntax and semantics of the preprocessor directives within the underlying program structure.
Program databases, used in integrated programming support environments, must contain all of the original information found in the program text in order to present complete structural information to a programmer. In many of these environments, the syntax and semantics of programs are commonly represented with attributed abstract syntax trees (AST's). AST's are easy to generate and manipulate and conveniently reflect the structure of the programs they represent. However, for the case of C, AST's are not sufficient. The C preprocessor (cpp), which provides conditional compilation and macro substitution, supports features that cannot be described by a tree-structured representation and are not amenable to existing parsing techniques. For instance, a program containing a single #if is actually two programs: one where the controlling expression is true and the other where it is false. Much information is removed by cpp that the parser has no chance of recovering. However, even if the parser had access to this information, it would be difficult to concisely represent these two views of the program with a single AST. Thus a forest of AST's or, more compactly, a single abstract syntax graph (ASG) is needed for the representation. In most C language compilers and tools, programs are first processed by a macro preprocessor. The resulting text is then passed through a lexical and syntax analysis phase. In many respects, this preprocessor has contributed to C's power as a systems programming language. The following list of preprocessor directives points out the power of the preprocessor and also illustrates some of the resulting difficulties posed by them:
#define name token-string
Replace subsequent instances of name with token-string.
#define name(arg [,arg]. . . ) token-string
Define a parameterized macro. Macro definitions include a macro body and, optionally, a sequence of formal parameters. A macro body definition is an arbitrary sequence of tokens. Within a macro body, parameters are replaced by the actual arguments of the macro at the use site.
#include "file name"
Include the text of one file within another file. This directive is most often used to import interface information from other modules.
#if constant-expression
Conditionally include or exclude selected portions of text from a source file. The #if directive evaluates the constant expression and includes the text of its body up to the matching #else, #elif, or #endif, if the expression is true. These features are widely used to construct modules that are portable across different operating systems and machine architectures. This feature also allows the conditional inclusion of various features within a module.
#ifdef name
Similar to the #if statement, except that the intervening text between the next #else, #elif, or #endif is included if name has already been defined.
Various problems arise with the integration of the preprocessor with the syntax analysis phase. For example, the preprocessor's grammar is not integrated with the C grammar and since the preprocessor tokens can appear anyplace in a string of C program tokens, the two grammars cannot be combined. Furthermore, conditional compilation directives induce multiple parse trees, or versions, of the same module. Ideally, the syntactic and semantic information of these induced versions should be represented in one integrated program representation structure. In an integrated program representation structure, macro uses should be accessible simply as macros, similar in syntax to identifiers or function calls, as well as in their expanded forms. Another problem arises because the body of a macro definition is not required to be a complete syntactic unit in the underlying C grammar. Also, the text of an included file presents difficulties because the text is not required to be syntactically complete, thus a syntactic unit can span multiple files.

Method for parsing and representing multi-versioned computer programs, for simultaneous and synchronous processing of the plural parses


An improved method for curing coatings on optical fibers, without creating additional heat and compromising the manufacturing speed of optical fibers. The method of curing a coating on an optical fiber includes the steps of passing an optical fiber through a coating die, applying a coating to the optical fiber, curing the coating on the optical fiber and exposing the optical fiber to ultrasound to facilitate curing of the coating.

1. Field of the Invention
The present invention generally relates to the field of optical fibers, in particular the present invention is directed to using ultrasound to aid in the curing of UV-curable coatings of optical fibers.
2. Discussion of Related Art
Optical fibers are very small diameter glass strands which are capable of transmitting an optical signal over great distances, at high speeds, and with relatively low signal loss as compared to standard wire or cable networks. The use of optical fibers in today's technology has developed into many widespread areas, such as: medicine, aviation, communications, etc. Because of this development, there is a growing need to produce optical fibers of better quality at faster rates and lower costs.
Many of the areas of use for optical fibers, such as communications, require the optical fibers be protected from various destructive elements, such as adverse weather, moisture, impact damage, etc. This protection for the individual fibers comes from the fiber coatings. Today, most optical fibers have two coatings, which are often referred to as the primary and secondary coatings. The primary coating is applied onto the surface of the optical fiber, with the secondary coating being applied on top of the primary coating. The main function of the primary coating is to provide a soft "cushion" for the glass fiber, protecting it from shock damage. The main purpose of the secondary coating is to provide a semi-rigid protective shell to protect both the primary coating and the glass fiber from adverse environmental elements, as well as physical damage.
One of the most common methods of making optical fibers today is by a process often referred to as the "draw" process. In this process, a large glass preform is made. The preform is the actual material that the glass fiber (optical fiber) is made from. Once the preform is made, the next step is to "draw" the preform into a glass fiber (optical fiber) with the desired diameter. One of the most common means to accomplish this is through the use of a "draw tower". The "draw tower" is a production apparatus which has all of the major stages required to manufacture an optical fiber from a glass preform to the finished fiber. In this process the glass preform is typically suspended above the apparatus with the bottom most end of the preform entering into a furnace. The furnace uniformly melts the preform such that the preform exits the furnace as a very thin diameter optical glass fiber. The rate the preform is moved into the furnace can be regulated to allow the maintenance of a constant diameter in the optical fiber. Once the glass fiber leaves the furnace it is generally cooled.
After the glass fiber is cooled to a preset temperature then the fiber is typically coated with the primary coating. This is generally done in a coating die. The primary coating is applied in such a way as to completely cover the fiber. The primary coating is then cured or hardened. Once the primary coating has been cured or hardened, the secondary coating is then applied to completely cover the primary coating. The secondary coating is then cured so as to harden it and secure it to the primary coating. Once this process is complete then the fiber is generally considered an optical fiber, as commonly known and understood. Finally the optical fiber is wound past a capstan and onto a reel or spool.
The coatings of the optical fiber are mainly used to provide chemical, mechanical and environmental protection to the glass fiber core and cladding. To accomplish this purpose the two layers are usually made from different materials. Generally the primary coating is relatively soft (having a relatively low Modulus of Elasticity of 1–2 MPa) when compared to the secondary coating and is used as a cushion or shock protection for the glass fiber. The secondary coating is relatively hard (having a relatively high Modulus of Elasticity of 30–60 MPa) and provides a semi-rigid protective shell for the fiber and primary coating. The most common types of coatings used are ultraviolet (UV) curable coatings. These are coatings which have a photoinitiator component used in the coating composition which allow the curing of the coatings to be initiated by exposure to UV radiation.
Photoinitiators function by absorbing energy which is radiated by a UV, or sometimes a visible, light source. This energy absorption then initiates polymerization of the liquid coating placed on the fiber, and results in the hardening of the coating. The fast cure of coatings greatly reduces the production time of optical fibers, making production more profitable.
However, this method of curing optical fiber coatings is not without its problems. Among other things, the curing process can generate a large amount of heat in the coatings of the fiber. This heat generally comes from hot UV/Visible lamps by convection or by infrared irradiation accompanying the UV- or visible light of a lamp during cure, and from the exothermic polymerization (i.e. cure) itself. This heat also contributes in curing the coatings, but can cause serious problems. For instance, if the temperature of coating during cure is too high it may result in decomposition of microradicals in the coating material and result in a low degree of cure. Overall, it is generally known that excessive heat during the coating cure process is detrimental for efficient or effective cure by free radical polymerization.
As stated earlier, the primary coating should be relatively soft, to protect the glass fiber from microbending. Microbending is the formation of microscopic bends in the glass fiber, which will reduce the effectiveness of the fiber by reducing the magnitude of transmitted light power, i.e. attenuation. In the cure process the primary coating is applied and then cured, and then the secondary coating is applied and then cured. As the secondary coating is being cured, the primary coating is, and often additionally, cured up until 100% conversion of the coating monomer(s) into polymers.
Because of the problems associated with the generation of excessive heat during the cure process, many prior art methods have been developed to expedite the cure process without the generation of excessive heat. An example would be to reduce the level of UV radiation, however, with the reduction of UV radiation the line speed must be slowed to ensure that the coating receives the proper amount of UV exposure to effect a proper cure. This reduction in draw speed can severely affect the manufacturing efficiency of a fiber optic facility. It is desired to have a system of curing optical fiber coatings at as high a speed as possible.

UV-cure of coating for optical fiber assisted by ultrasound


A method of dividing a circuit pattern to be transferred by a photoprinting apparatus from a reticle to a photosensitive surface. The circuit pattern has a display section and a conductor section. The method includes dividing the circuit pattern into a plurality of divided patterns wherein each of the divided patterns includes at least a part of the display section and a part of the conductor section; and forming a plurality of reticles, each of the reticles having at least one of the divided patterns thereon.

The present invention relates to a method of dividing and exposing patterns. More particularly, the present invention relates to a method of dividing and exposing circuit patterns forming a liquid crystal display (LCD) with a plurality of divided patterns.
In recent years, liquid crystal displays have been used as display elements for personal computers, TV receivers, etc. in large quantities. Conventionally, the liquid crystal displays have been manufactured using glass substrates with photolithographically transferred circuit patterns.
A projection exposure apparatus is commonly used in an exposure process in which the images of circuit patterns are photolithographically transferred onto glass substrates. The exposure apparatus emits light from a light source for photolithographic transfer of the image through a reticle having liquid crystal display circuit patterns. Then it superimposingly projects the images of the circuit patterns by means of light going through the reticle onto a glass substrate via a projector lens system.
In this case, as illustrated in FIG. 12, a circuit pattern 1 of a liquid crystal display is formed in a rectangular shape consisting of a display section 2 and a peripheral portion 3 surrounding the display section 2. The display section 2 is a pattern in which a plurality of electrodes corresponding to a plurality of pixels of red, green, and blue are arranged regularly. The peripheral portion 3 comprises a plurality of, for example, trapezoidal interconnecting portions 4 (hereafter referred to as the "lead group") for connecting each of the electrode patterns with a plurality of drive circuits, not illustrated.
Recently, larger size liquid crystal displays have been in greater demand. The demand is met with the following step-and-repeat technique. When the size of a circuit pattern 1 of a liquid crystal display is larger than that of the effective diameter of the projection lens of the aforementioned exposure apparatus and larger than the area on which a reticle circuit pattern is formed (hereafter these sizes are referred to as "effective fields"), the circuit pattern 1 is divided into a plurality of types of patterns corresponding to the effective fields. In this case, a plurality of circuit patterns are formed by dividing a pattern (hereafter referred to as the "divided patterns") on a plurality of reticles. The images of the patterns of the reticles are then superimposingly photoprinted onto predetermined positions on each of the glass substrates in the exposure apparatus to transfer the circuit pattern 1 from the reticle onto the aforementioned glass substrate.
Now, as illustrated in FIGS. 13(A) and 13(B), when a liquid crystal display circuit pattern 1 is almost as large as the effective field, the aforementioned circuit pattern 1 is not divided FIG. 13(A)!, and the circuit pattern 1 is formed on a reticle 5 FIG. 13(B)!. The resist film on a glass substrate is superimposingly photoprinted relative to the circuit pattern 1 through the reticle 5 by "one exposure" processing in the exposure apparatus.
As illustrated in FIGS. 14(A) and 14(B), when the size of the circuit pattern 1 of the liquid crystal display is larger than the aforementioned effective field and up to about twice as large as the effective field, the aforementioned circuit pattern 1 is divided into divided patterns B and C Figure 14(A)! corresponding to the effective field to be transferred onto reticles 6A and 6B FIG. 14(B)!.
In this case, the exposure apparatus, for example, first photoprints the image of the left-half B of the divided circuit pattern 1 onto the resist film on the glass substrate through the reticle 6A; then, photoprints the image of the remaining right-half C of the divided circuit pattern 1 onto the resist film on the glass substrate through the reticle 6B. As such, in an exposure apparatus, the circuit pattern 1 is photolithographically transferred onto a resist film on a glass substrate using reticles 6A and 6B and two exposures.
As illustrated in FIGS. 15(A) and 15(B), when the circuit pattern 1 of a liquid crystal display is larger than the effective field by twice or more and less than about four times, the aforementioned circuit 1 is divided into four divided patterns D, E, F, and G Figure 15(A)! corresponding to the effective field. These divided patterns D through G are printed on reticles 7A, 7B, 7C, and 7D, respectively Figure 15(B)!.
The exposure apparatus first superimposingly photoprints the image of the upper left divided pattern D of the circuit pattern 1 onto a resist film on a glass substrate through a reticle 7A. Then the image of the upper right divided pattern E of the circuit pattern 1 is transferred onto the resist film on a glass substrate through a reticle 7B. After that it photoprints the image of the lower left divided pattern F of the circuit pattern 1 onto the resist film on the glass substrate through a reticle 7C. Finally, it photoprints the image of the lower right divided pattern G of a circuit pattern 1 onto a resist film on the glass substrate through a reticle 7D. As such, the exposure apparatus photolithographically transfers the circuit pattern 1 onto the resist film on the glass substrate using the reticles 7A, 7B, 7C, and 7D and four exposures.
Examples of this technique are described in U.S. Pat. Nos. 4,708,466 and 4,814,830.
Recently, however, a technique to increase manufacturing efficiency of a liquid crystal display has been introduced, namely the so-called "plural-area method." With this method, a plurality of liquid crystal display circuit patterns are photolithographically transferred onto an integral substrate to obtain a plurality of liquid crystal displays a so-called "plural-area production".
To apply the aforementioned step-and-repeat exposure in the plural-area production method, the lithographic pattern transfer can be performed by the number of exposures which is equal to the number of areas produced using each of the reticles having divided circuit patterns obtained by dividing a circuit pattern for the manufacture of a liquid crystal display.
When the size of such a liquid crystal display circuit pattern 1 is four times larger than that of the effective field, the aforementioned circuit pattern 1 is divided into a display section 2 and a periphery section 3 corresponding to the effective field, and the display section 2 and the periphery section 3 are divided further into smaller areas.
For example, as illustrated in FIG. 16(A), the display section 2 is divided into six even areas on the liquid crystal display circuit pattern 1.
In this case, because each of the electrode patterns in the display section 2 are relatively small and regularly arranged corresponding to each of the pixels, the display section 2 is divided into six almost identical divided patterns H.
Regarding the periphery section 3, each of the edges (hereafter referred to as "the first and the second edges") 3A and 3B arranged along the direction of the longer side of the circuit pattern 1 (hereafter simply referred to as "a longer side") are almost evenly divided into three sections. Also, each of the edges (hereafter referred to as "the third and the fourth edges") arranged in the direction perpendicular to the longer side are divided almost evenly into two sections.
In this case, in the periphery section 3, each of the lead patterns of the lead group 4 is relatively larger than each of the electrode patterns of the display section 2, and it is difficult to divide the periphery section 3 at the border of each of the adjacent lead groups 4, thus splitting the lead group 4 into two. Therefore, in the periphery section 3, the number of patterns increases because each of the divided patterns I, J, K, L, M, N, O, P, Q and R takes a different pattern.
For this reason, as illustrated in FIG. 16(B), when forming each of these divided patterns H through R onto a reticle 8, the conventional technique effectively uses the area of the surface on which divided circuit patterns H through R of the reticle 8 are formed. The divided pattern H is formed on a reticle 8A and each of the divided patterns, respectively, form a plurality of groups, I to K, L to N, and O to R to be, respectively, formed on each of the reticles 8B, 8C, and 8D. The technique decreases the number of reticles 8A through 8D required to accommodate the divided patterns H to R of a plurality of types.
Now, when superimposingly photoprinting using these reticles 8A, 8B, 8C, and 8D, the image of the display section 2 of the circuit pattern 1 is superimposingly photoprinted onto a glass substrate six times sequentially, first for example using the reticle 8A. Then using the reticles 8B, 8C, and 8D, the image of the periphery section 3 of the circuit pattern 1 is superimposingly photoprinted onto the glass substrate ten times sequentially while shutting off patterns other than the divided patterns required for exposure processing using a shutter plate.
Compared to a liquid crystal display having a circuit pattern size which is smaller than four times the size of the effective field, the liquid crystal display whose size of the circuit pattern 1 is larger by four times or more than the size of the effective field encounters a problem in that the number and the type of divided patterns I through R increase sharply. Also, the number and the types of exposure processing performed in an exposure apparatus increases sharply as well (sixteen times in the aforementioned case.) It also encounters a problem in that the throughput, the ability to process substrates per unit of time during exposure processing, decreases sharply.
Therefore, when a liquid crystal display circuit pattern 1 is four times or more larger than the effective field, the design of the reticle 8 has to take the number of divisions of the circuit into account, thus making difficult the designing of the aforementioned reticle 8.
In addition, the attempt to obtain plural divided areas of a liquid crystal display circuit pattern whose size is larger by four times or more than the effective fields of a projection lens system and reticles encounters problems of increasing the number of exposures and decreasing the throughput.
Plural divisions are produced basically to increase manufacturing efficiency of substrates. However, the attempt to print plural divided areas on an integrated substrate unfavorably increases the number of exposures, as mentioned, and decreases throughput. This is harmful in terms of efficiency.

Method of dividing and exposing patterns


The invention relates to a process for producing a tertiary amine, which includes reacting an alcohol with a primary or secondary amine gas in the presence of a catalyst with an agitating vessel under the stirring conditions where the ratio (Pg/P0) of agitating power at the time of the maximum flow rate of an introducing gas (Pg [W]) to agitating power at the time of no introduction of the gas (P0 [W]) becomes 10−1.8Na or more wherein Na is the gas flow number, and Na=Qg/nd3 whereupon Qg [m3/s] is the flow rate of an introducing gas, n [1/s] is the number of revolutions, and d [m] is the diameter of an agitating impeller.

In the field of production of tertiary amines, side products such as monomethyl dialkylamine are formed particularly in production of dimethyl monoalkylamine by reacting an alcohol with dimethylamine in the presence of a catalyst, thus causing a reduction in yield. To solve this problem, JP-A 2001-151733 for example discloses a process for producing a tertiary amine at a high yield by suppressing side products with a combination of a catalyst and specific reaction conditions.
In the conventional techniques such as those described above, those skilled in the art have produced tertiary amines under general stirring conditions in this field. That is, a correlation of the gas flow number (NA) and agitating power ratio (Pg/P0), which indicates a mixed state of liquid and gas, is disclosed in FIG. 20-14 on page 902 in "Kagaku Kogaku Binran" (Chemical Engineering Handbook), revised 5th edition, published on Apr. 15, 1992, pp. 901-902 and edited by The Society of Chemical Engineers, Japan (SCE). There is also a disclosure wherein the agitating power ratio is practically 0.6 or more.


Improved techniques for enhancing, associating, and linking various sources of metadata for music files, to allow integration of commercially generated metadata with user-entered metadata, and to ensure that metadata provided to the user is of the highest quality and accuracy available, even when the metadata comes from disparate sources having different levels of credibility. The invention further provides improved techniques for identifying approximate matches when querying metadata databases, and also provides improved techniques for accepting user submissions of metadata, for categorizing user submissions according to relative credibility, and for integrating user submissions with existing metadata.

1. Field of the Invention
The present invention relates generally to playing, copying, and managing music files, such as those found on compact discs (CDs), and more particularly to techniques for retrieving, associating, and linking various sources of metadata for the music files.
2. Description of the Background Art
Most audio CDs contain only digital music and a table of contents that tells the player how many tracks are present, the length of each track, and where on the disc each track starts. In general, audio CDs do not carry "metadata" such as the title of the album, the artist that recorded it, and the names of the songs or tracks contained on it.
Metadata is of value when playing, copying, and managing music files. Metadata includes descriptive information about music tracks and albums, so as to allow users to more easily identify files. For example, if a song title is available as metadata, an audio CD player can look up additional information from a web server, and can display artist name, album title, and song title while a track is being played. The user can view the contents of the CD by track name and select the tracks by name for random access playback. If a user makes a copy of a music file from a CD (a process known as "ripping"), or downloads a music file from an online source, metadata can be used as a default filename. Metadata is also useful in organizing and categorizing a collection of files, for example by artist name or musical genre; metadata can also be used as an identifier for gaining access to additional information about a song, artist, or CD.
Existing music players and CD management ("ripper") software applications that make use of available metadata include, for example:                Real Jukebox, available and CD from RealNetworks, Inc. of Seattle, Wash.;        Winamp, available from Nullsoft, Inc., a division of America Online, Inc., of Dulles, Va.;        Easy CD Creator 5, available from Roxio, Inc. of Santa Clara, Calif.;        KDE CD Player for Linux; and        Toast, available from Roxio, Inc. of Santa Clara, Calif.
Conventionally, since CDs themselves do not generally carry metadata, some music client software applications (including players and CD management software) obtain metadata from external sources. For example, in some software applications users enter metadata manually, and the entered metadata is then associated with some unique characteristics of a CD (such as track lengths), so that the entered metadata can later be accessed whenever the CD is re-inserted in the user's computer. Alternatively, the client software can obtain metadata from a central server that is run by an application service provider (ASP). Such functionality is provided, for example, by CDDB, available from Gracenote of Berkeley, Calif., or by FreeDB, available at "http://www.freedb.org". The Windows Media Player client, available from Microsoft Corporation of Redmond, Wash., also communicates with a CD Metadata ASP to obtain metadata.
FIG. 1 depicts a system for obtaining metadata from a remote server according to the prior art. An end user of client software 102 (such as a music player or ripper application) inserts CD 101 in a connected CD drive (not shown). Client software 102 requests that metadata client module 104 identify CD 101 and return the metadata for use by software 102. Client module 104 may derive a Disc ID from available information from CD 101, such as table of contents (TOC). Module 104 then sends the Disc ID over a network connection to a remote metadata ASP 103. The request is typically sent over the Internet using Hypertext. Transfer Protocol (HTTP) as a transmission protocol. Metadata server 105 receives the request and runs a query on metadata database 106 to find a metadata record that matches the Disc ID. Database 106 provides the metadata, which is then transmitted back to module 104. Module 104 makes the data available to software 102.
Existing systems such as CDDB and FreeDB create the metadata database from input provided by users of the system. If, when a CD is inserted, no matching metadata is found, software 102 prompts the user to enter the metadata manually. The user-entered metadata is then transmitted back to Metadata ASP 103 and is added to database 106 and associated with a new disc identifier for the inserted CD.
FIG. 2 depicts this method in more detail, as generally performed by metadata client 104 according to the prior art. Client 104 extracts 201 Disc IDs from the CD TOC data. Client 104 then transmits 202 the Disc IDs to metadata server 105. If server 105 indicates 203 that matching metadata was found in database 106, the metadata is made available 206 to client software 102. If server 105 indicates 203 that no match was found, client 104 prompts the user 202 to enter the missing metadata. Once the user has provided the metadata, client 104 transmits 205 the metadata to server 105, which saves the metadata in database 106. The metadata is made available 206 to client software 102.
FIG. 3 depicts a server method of obtaining metadata according to the prior art. Server 105 receives a request 301 for metadata from client 104 over HTTP or some other protocol. Server 105 looks up 302 the Disc ID in metadata database 106. If a match exists 303, server 105 returns 304 the metadata for the match to client 104, along with status indicating a match 304. Otherwise, server 105 returns a status code indicating that no matches were found.
Existing systems do not provide a mechanism for linking metadata from two or more sources. Thus, if metadata is available from some external source, such as a commercially developed third-party database of music information, existing systems are not generally able to integrate such external metadata with the above-described scheme. In general, then, prior art metadata systems do not take advantage of the availability of more accurate and/or more complete information that may be available from a variety of sources. Furthermore, existing systems do not provide a mechanism for establishing links between metadata records in disparate databases, nor do they allow for management of various data sources having different levels of credibility.

Associating and linking compact disc metadata


Sequential video data frames are encoded using cores including a first core and a second core. A first beginning frame is divided into slices. The first core is assigned to process a first slice. The second core is assigned to process a second slice. The first beginning frame is processed using the cores which results in a first ending frame in which the first slice was partitioned into a third slice and a fourth slice. The third slice was processed by the first core. The fourth slice and the second slice were processed by the second core. A second beginning frame, which immediately follows the first ending frame, is divided into a second plurality of slices. The first core is assigned to the third slice. The second core is assigned to a fifth slice which has a size equal to a sum of the second and fourth slices.

1. Field
This disclosure relates generally to video processing, and more specifically, to a system and method for load balancing a video signal in a multi-core processor.
2. Related Art
The Advanced Video Coding (AVC) standard, Part 10 of MPEG4 (Motion Picture Experts Group), otherwise known as H.264, was developed to enable transmission or storing of video signals with improved quality at a constant bit rate (CBR), or variable bit rate (VBR). A present day encoder compliant with the H-264 standard can be designed to run on a single-core processor. However, a commonly available single-core processor is not capable of running fast enough to reach high-definition resolutions (e.g. 720p, 1080i, and 1080p). In order to reach high-definition resolutions in near real-time, the H.264 encoder can be designed to run in parallel on a multi-core processor.
To effectively encode a video signal in a multi-core processor, video data should be relatively evenly divided between the cores for parallel processing. This load balancing is generally achieved using either data partitioning or function partitioning. In data partitioning, a frame of data is divided into multiple portions and provided to the cores in parallel. This approach is relatively easily implemented. However, it is difficult to insure proper load balancing between processor cores because some of the data will have more complex processing requirements. For example, one slice of a frame may include movement, or finer details than another slice of the frame. This can lead to processing bottlenecks causing some cores to be idle while others are busy.
In load balancing using function partitioning each core is assigned a different processing function, such as motion estimating or encoding. The data is then processed in a pipelined fashion. For example, one processor may apply a first function to video data and then pass the modified data to a second processor for a second function. However, it can be difficult to load balance by function because algorithms cannot easily be divided into an arbitrary number of blocks to match the number of processor cores.
Therefore, what is needed is a system and method that solves the above problems.

System and method for load balancing a video signal in a multi-core processor


A scribe mark reader (10) uses a source of circularly polarized light and a holographic beam-shaping optical element (40) to uniformly illuminate an area of a substrate (20) that includes a scribe mark (18). Light incident on the substrate at a scribe mark is predominantly scattered, whereas light incident on the substrate at a processed area (30) of the wafer surface between the pits (28) of the scribe mark is predominantly specularly reflected. The phase-reversed, specularly reflected light from the processed area is blocked by a circular analyzer that passes light scattered from the scribe mark. Light passing the polarizer can then be used to form an image of the scribe mark. The intensity of the images formed are sufficiently consistent that the automatic gain control of the CCD camera can be used and the images formed can be readily interpreted by optical character recognition software.

Semiconductor wafers used in the manufacture of integrated circuits are often marked with identifying information to facilitate in-process tracking during their production. The identifying marks, known as scribe marks, typically comprise a series of characters, bar codes, or other two-dimensional codes, each of which is formed from small circular depressions or "pits" in the substrate. The pits are typically formed by using a laser to melt a small area of the substrate, the melted material being removed in subsequent etching steps. Because integrated circuits should not be formed on the scribe marks, they are typically positioned near the unused outer edge of the wafer by the primary fiducial to maximize the wafer surface area available for forming integrated circuits.
Using a human operator to manually read the marks directly from the wafers is labor intensive and susceptible to error. Moreover, the marks are not always accessible to the operator during wafer processing. Using an imaging system that presents an enlarged image of the mark to the operator increases the accuracy of the observation, but the process is still labor intensive and susceptible to error because of poor image quality. Efficient wafer fabrication requires that the marks be reliably machine-readable by automated process equipment. Some marks, such as bar codes, are readable essentially only by a machine.
Automated reading of a mark is a three-step process. A camera typically forms an image of the scribe mark, and the image is converted into a computer-compatible digital format. The digitized image is then interpreted, for example, by optical character recognition software to determine letters, numbers, bar codes, or other symbols in the digitized image. For the mark to be interpreted by the software, the digitized image must be relatively clear, i.e., there must be adequate contrast between the background and the image of the mark.
It has been difficult to form a clear image of the scribe marks for several reasons. Because typical scribe marks comprise a group of relatively shallow depressions in the substrate, the marks are of the same color as the substrate background and are, therefore, hard to differentiate. The pits of shallow or "soft" marks, which are used to reduce contamination during wafer processing, can have a depth of only one micron. Moreover, the substrates are typically highly polished and, therefore, reflect into the camera a large amount of light that tends to obscure the mark. Light from the processed areas on the water surface around the pits of the scribe mark is process "noise" that tends to obscure the light "signal" from the scribe mark.
During wafer fabrication, layers are formed on the wafers using a variety of materials having a wide range of reflectivity and other optical properties. Illumination levels required to achieve an image having adequate contrast between the background and the mark can vary over three orders of magnitude, thereby requiring frequent gain adjustments to the charge-coupled device ("CCD") camera. The automatic gain control on CCD cameras reacts too slowly to such a wide range of brightnesses and, if used, unacceptably delays processing. Manual gain adjustments or sequenced changes in the illumination level can be used to compensate for the variation in image intensity, but such methods also slow production. Moreover, manual adjustments require an operator to continuously monitor the scribe mark reader.
The optical properties of the wafer surfaces vary not only from wafer to wafer but also across the surface of an individual wafer. Wafers can exhibit an "edge bead," i.e., an abrupt change in contrast and reflectivity of the surface as a result of a layer, such as a metal or oxide coating, not extending to the outer periphery of the wafer. The edge bead can appear across the scribe mark itself, producing artifacts in an image formed of the mark. Imperfect forming or etching of the layers can also cause thickness variations in the layers, especially at the edges of the wafers where the thickness variations are observable as annular rings. The coloration and nonuniform reflectivity of such rings, located at the edge of the wafer where the scribe marks are also located, interfere with reading the scribe marks by producing artifacts in the image. Furthermore, materials used to treat or coat wafers, particularly photoresist, can accumulate in the depressions of the scribe marks, further obscuring the mark by affecting the optical properties of the substrate surface and scribe marks.
Because the problems described above make it difficult to form a clear image of the scribe marks, the optical character recognition software often cannot interpret the poor quality image it receives. Scribe mark readers typically require, therefore, frequent intervention from human operators, either to adjust the optical elements to improve the image or to manually read the mark or significant investment by semiconductor manufacturers to improve or add additional process steps to improve the scribe readability.


Provided is a measuring apparatus and method of train wheel wear, the apparatus including a speed measuring unit measuring speed of a train, a position measuring unit measuring a position of the train, and a calculation unit calculating abrasiveness of a train wheel on a train based on the measured speed and position of the train, whereby status of the train wheel can be accurately learned to minimize the number of devices that may be additionally installed, and to quickly measure abrasiveness of the train wheel as well.

1. Field of the Disclosure
The present disclosure relates to a measuring apparatus and measuring method of train wheel wear, and more particularly to a measuring apparatus measuring a train wheel wear using a tachometer and a balise, and a measuring method using the measuring apparatus.
2. Discussion of the Related Art
The information disclosed in this Discussion of the Related Art section is only for enhancement of understanding of the general background of the present disclosure and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Train wheels need a periodic replacement due to continuous wear during operation of a train. Thus, a device or a method capable of measuring a periodic wear of a train is required.
In order to measure a train wheel wear in a CBTC (Communication Based Train Control)-based railway signal system, devices such as a camera and a photo sensor have been conventionally used to measure the train wheel wear.
FIG. 1 is a block diagram illustrating a configuration of a measuring apparatus of a train wheel wear. Referring to FIG. 1, a measuring apparatus (10) includes cameras (20-1, 20-2), Analogue to Digital Converters (ADCs, 30-1, 30-2), a CPU (Central Processing Unit, 40), a memory (50), a display interface (60), a display unit (70), an input/output interface (80) and a photo sensor (90).
The cameras (20-1, 20-2) function to photograph train wheels passing on a rail. A central position of a light receiving lens of the cameras (20-1, 20-2) photographing a distal end of a flange is aligned with a height of the distal end to allow facing between the distal end and a reference groove, where the camera photographs the train wheels at a contact region with the rail. A dimension of each part expected through the reference groove and a dimension of an image actually photographed are compared to calculate a size of the wheel. Meanwhile, the photo sensor (90) is disposed to reduce an error.
The image photographed by the cameras (20-1, 20-2) is converted to a digital signal by the ADCs (30-1, 30-2). The CPU (40) receives the digital signal to store the signal in the memory (50) or transmit the signal to the display interface (60). The display interface (60) displays the received signal to allow a user to intuitively learn abrasiveness of the wheel. Meanwhile, the apparatus may include input/output interface (80) enabling an input from an outside device (95).
Although the conventional apparatus has an advantage of performing a highly accurate measurement of wheel wears using the cameras, the conventional apparatus suffers from a disadvantage of requiring additional devices such as the cameras (20-1, 20-2) and the photo sensor (90) Furthermore, the cameras (20-1, 20-2) and the photo sensor (90) are too expensive for being disposed on all trains, and durability thereof is not that high.
Another disadvantage is that a mechanical characteristic may be changed due to formation of a reference groove on the train wheel for providing an accurate reference point for installation on the train wheel. Still another disadvantage is that it is difficult to measure the size of the train wheel during train operation, and that use is only possible during maintenance/repair processes for measuring the status of the train wheel.
Thus, there is a need to address the abovementioned disadvantages.

Measuring apparatus and measuring method of train wheel wear


Integrated circuit memory devices include a semiconductor substrate and a bit line on the semiconductor substrate. A plurality of memory cells is also provided. Each of these magnetic memory cells includes a magnetic storage element, a magnetic flux focusing layer on the magnetic storage element and an electrically insulating layer extending between the bit line and the magnetic flux focusing layer. This electrically insulating layer may contact an upper surface of the magnetic flux focusing layer and a lower surface of the bit line. The magnetic memory cell further includes a non-ferromagnetic electrically conductive layer extending between the magnetic flux focusing layer and the magnetic storage element. The electrically insulating layer is configured to cause current passing in a first direction (e.g., vertical direction) from the magnetic storage element to the non-ferromagnetic electrically conductive layer during a cell writing operation to spread laterally in the magnetic flux focusing layer (and non-ferromagnetic electrically conductive layer) in a second direction (e.g., lateral direction), which is orthogonal to the first direction. The magnetic flux focusing layer may be formed of a ferromagnetic material, such as NiFe.

Semiconductor memory devices, which may be used to store various types of data, can be divided into volatile memory devices and non-volatile memory devices. The volatile memory devices are typically represented by a dynamic random access memory (DRAM) and a static random access memory (SRAM). The DRAM stores data by using electric charges stored in a capacitor. To prevent the electric charges from leaking off the capacitor, a refresh operation is necessary. However, a power supply is stopped, the data stored in the DRAM may disappear. On the contrary, the non-volatile memory devices keep the stored data even when power is terminated. For this reason, non-volatile memory devices are used widely in circumstances where power cannot be supplied continuously, such as mobile phones and diverse application devices including a memory card for storing music or video data. The non-volatile memory devices include a flash memory representing '0' and '1' of data based on whether tunneling charges are stored or not, a Ferroelectric Random Access Memory (FRAM) using the polarization direction of a dielectric substance, a magnetic RAM (MRAM) using the magnetization direction of a magnetic substance. The flash memory has a disadvantage of slow data erase/write speed and the FRAM has a disadvantage of supporting relatively few rewrite operations (i.e., low reusable number).
The magnetic RAM, which typically does not have the above disadvantages has been attracting attention recently. The MRAM has advantages that it does not have a limit in the reusable number, and it can be highly integrated. Also, it can be operated at a high speed. In a magnetic memory device, data is stored in a simple thin ferromagnetic film or in a multi-layer magnetic thin film, (e.g., Tunneling Magneto-Resistance (TMR)), or in a Giant Magneto-Resistance (GMR). The basic structure and operation of a conventional magnetic memory device using the TMR will be described hereinafter with reference to the drawings.
FIG. 1 is a plane view showing a conventional magnetic memory device, and FIGS. 2A and 2B are cross-sectional views obtained by cutting the magnetic memory device of FIG. 1 along line 2A-2A′ and line 2B-2B′, respectively. Referring to FIG. 1, a plurality of conducting wires are formed perpendicularly to each other on a semiconductor substrate to thereby form bit lines 30 and digit lines 28. Magnetic storage elements 40 for storing data are formed in the area where the bit lines 30 and the digit lines 28 cross each other. Referring to FIGS. 2A and 2B, an field isolation layer 12 is positioned in a predetermined area of the semiconductor substrate 10 to define active regions. In each active region, a pair of gate electrodes 20 are formed. The gate electrodes 20 include a gate of a transistor used to read data stored in the magnetic storage elements 40. A common source region 16s is formed between the gate electrodes 20, and a drain region 16d is formed between a gate electrode 20 and an field isolation layer 12. The common source region 16s is connected to a common source electrode 18, and the drain region 16d is connected to a vertical wire 24. A bottom interlayer insulation layer 22 is formed on the entire surface of the semiconductor substrate 10 including the digit lines 28. The vertical wire 24 electrically connects the drain region 16d to a bottom electrode 26, which is formed in the upper part of the bottom interlayer insulation layer 22 with a space therefrom. The bottom electrode 26 is connected to the magnetic storage element 40, and a bit line 30 is formed on top of the magnetic storage element 40. Herein, the bottom electrode 26 and the magnetic storage element 40 is insulated by a top interlayer insulation layer 32 formed on top of the bottom interlayer insulation layer 22.
The magnetic storage element 40, which has a structure of Magnetic Tunnel Junction (MTJ) includes a pinning layer 41, a fixed layer 42, an insulating layer 43, and a free layer 44. The resistance of the magnetic storage element 40 is varied according to whether the magnetization directions of the free layer 44 and the fixed layer 42 are the same or not. The resistance characteristic of the magnetic storage element 40, which is dependent on the magnetization direction, is utilized as a data storing mechanism of the magnetic memory device. The magnetization direction of the fixed layer 42 is not changed during a typical reading/writing operation, and the pinning layer 41 fixes the magnetization direction of the fixed layer 42. On the contrary, the magnetization direction of the free layer 44 is variable. The free layer 44 can be magnetized in the same direction as the fixed layer 42 or can be magnetized in the opposite direction.
When data stored in a particular magnetic storage element 40 is read, the bit lines 30 and word lines 20 are used. The word lines 20 correspond to the gate electrodes 20 formed on the semiconductor substrate 10 and they are formed in perpendicular to the bit lines 30. When electric current flows into the magnetic storage element 40 by selecting a word line 20 and a bit line 30, the amplitude of the electric current is different according to the data storage state. In other words, the stored data can be read, because the resistance value is different according to whether the magnetization directions of the fixed layer 42 and the free layer 44 are the same and the amplitude of the electric current is different according to the resistance value. Meanwhile, data are recorded by providing electric current to a bit line 30 and a digit line 28 to select a particular magnetic storage element 40 and magnetizing the selected magnetic storage element 40 based on a vector addition of a magnetic field formed by the electric current.
Hereafter, problems of the conventional magnetic memory device will be described. When electric current flows through the bit lines 30 and the digit lines 28, a magnetic field is formed around the lines 28 and 30. Basically, the magnetic field should affect only the magnetic storage element 40 whose magnetization should be changed. However, as the magnetic memory device is highly integrated, memory cells become close to each other, and the magnitude of the magnetic field needed for writing data increases as well. Therefore, there can be a problem that the magnetic field generated by the bit lines 28 and the digit lines 30 affects not only the selected magnetic storage element 40 but also an adjacent magnetic storage element 40. To solve this problem, a magnetic memory device having a new structure not using the bit lines 28 is suggested. According to the suggested technology, the word lines 20 replace the digit lines 28 and the electric current flows through the word lines 20 and the bit lines 30 to thereby form a magnetic field. The formed magnetic field changes the magnetization direction of the magnetic storage element 40. Meanwhile, it is also possible to change the magnetization direction of the magnetic storage element 40 by increasing the amplitude of electric current, which is provided to the magnetic storage element 40 through the word lines 20 and the bit lines 30, more than when data are read while providing the electric current to the magnetic storage element 40 in the same method as data are read. This magnetic memory device is disclosed in U.S. Pat. No. 5,695,864.
The technology that does not use the digit lines 28, which is described above, can prevent other magnetic storage elements 40 from being affected by the magnetic field due to disturbance caused by the digit lines 28. However, it still has a problem of disturbance caused by the bit lines 30. In particular, in the method of providing electric current to the magnetic storage element 40 to record data, since a high amplitude of electric current flows during the data recording, a strong magnetic field is formed and this enhances the possibility that the magnetic field affects adjacent areas. Also, since the method of recording data only by using the bit lines 30 without the digit lines 28 requires a strong magnetic field necessarily, a method for reducing power consumption is needed.

This patent is subject to a terminal disclaimer.

Magnetic memory devices having rotationally offset magnetic storage elements therein


A dispenser pump is constituted by a closure body (2), a diaphragm body (3) which forms a pump chamber with the closure body and optionally a top actuator (4) for pressing the diaphragm body (4). The diaphragm body has a deformable wall (35) formed integrally in the same polymer as its annular mounting portion (31). An inlet valve (5) through the floor (21) of the closure body has a flap (52) which is formed and hinged integrally with that floor (21). An outlet valve may also be formed in the same polymer, either integrally with the diaphragm body or as a separate component. The deformable wall of the diaphragm body is shaped to generate a restoring force itself without a separate spring, so that the entire pump may be made from the same polymer e.g. polypropylene and without metal components.

The simplest mass-produced dispensers have a moulded plastics closure snapped or screwed onto the neck of a plastics bottle, defining an outlet opening through which product can be squeezed or poured. A cap or plug for the opening may be formed in one piece with the closure. Also widely used are pump dispensers, in which the user depresses a head or plunger to pump product out of a discharge nozzle or external discharge opening via a pump chamber of variable volume, usually with a piston/cylinder action, by means of inlet and outlet valves. Pump dispensers are more complex and expensive, and less susceptible to recycling because materials including metals and non-degradable plastics are often used for springs, valve elements and so forth. It is known to use a resilient pump chamber wall (bellows) to avoid using a discrete spring, but still much is left to be desired in terms of economy, simplicity and recyclability combined with effective operation.


A suture threader comprises a body having first and second ends, a first suture threader extending from the body first end, and a second suture threader extending from the body second end.

It is known to use a suture anchor of the sort having a transverse bore extending through a proximal portion thereof so as to facilitate attachment of the suture to the anchor. It is also known to use, in combination with the suture anchor, an inserter having a lengthwise bore extending therethrough and through which may extend the suture which is attached to the suture anchor. Such a combination is shown and described, for example, in U.S. Pat. No. 5,411,506, issued May 2, 1995 to Goble et al. for ANCHOR DRIVER, which patent is assigned to the assignee of the present patent application, and which patent is hereby incorporated herein by reference. See also U.S. patent application Ser. No. 08/514,613, filed Aug. 14, 1995 by Goble et al. for SUTURE ANCHOR ASSEMBLY, which patent application is also assigned to the assignee of the present patent application, and which patent application is also hereby incorporated herein by reference.
Before using the suture anchor and inserter to attach suture to a bone, the suture must be threaded through the transverse bore of the suture anchor and through the lengthwise bore of the inserter. Typically, the suture anchor's transverse bore is relatively short and the inserter's lengthwise bore is relatively long, thereby requiring different threader configurations. By way of example, an ordinary needle threader may be used to thread the suture through the suture anchor's transverse bore, whereas a crochet-hook type of threader may be used to thread the suture through the inserter's lengthwise bore.
In situations where the suture is to be threaded through the suture anchor and the inserter during initial manufacture, it may not be inconvenient for the manufacturer to use different threaders for threading the suture through the suture anchor and the inserter. However, where the suture is to be threaded through the suture anchor and inserter at the time of use, i.e., in the operating room, it can be undesirable for the operating room personnel to use different threaders for threading the suture through the suture anchor and through the inserter. Thus, it is deemed beneficial to have available a single threader which is adapted to thread suture through both (i) relatively short bores, such as those found in a suture anchor, and (ii) relatively long bores, such as those found in an inserter.

Suture threader assembly, suture anchor assembly, and method for threading suture


Implementation of a logic design in either an FPGA or a structured ASIC is facilitated by designing either type of implementation so that it takes into account the possible need to migrate the design to the other type of implementation. Portions of the design that are being considered for one type of implementation (e.g., FPGA implementation) are assessed for suitability and/or desirability based not only on their suitability/desirability in that one type of implementation, but also based on their suitability/desirability in the other type of implementation (e.g., structured ASIC implementation).

This invention relates to methods of doing "ASIC-aware" technology mapping for FPGAs or the like. For example, these are methods whereby the logic module or logic element outputs of the FPGA version of a user's logic design are also made "visible" in a structured ASIC version of the design.
A field programmable logic device ("FPGA") typically includes a network of logic elements ("LEs"). Each LE typically contains an N-input look-up table ("LUT") that can select the logical output of one of 2N configuration RAM bits ("CRAM bits"). By programming these bits appropriately, the LUT can be programmed to implement any logical function of N-inputs. The FPGA also contains programmable routing resources for connecting the inputs and outputs of LEs. Routing resources typically include routing muxes that are controlled by configuration bits. Thus, an FPGA has great flexibility, in that it can implement many different logic circuits simply by programming the configuration bits. However, a significant amount of the die area—and hence the device cost—comes from the circuitry needed to make the device configurable, e.g., the CRAM bits, the LUT circuitry, and the routing multiplexer circuitry.
A structured gate array is a mask-programmable logic device. Typically, it includes a uniform structure of "hard" logic elements ("HLEs"). These HLEs are typically multi-gate circuits that are much smaller than the programmable LEs of FPGAs, and implement simpler functions. These HLEs may be combined to form units called clusters of HLEs ("CHLEs"). An HLE is typically capable of implementing only some very simple two- or three-input functions, while a CHLE can implement functions of similar complexity to an N-input LUT. However, unlike a LUT, a CHLE with M inputs may be able to implement only a subset of all possible 2M functions of those M inputs.
The inputs and outputs of CHLEs are connected together via metal wires defined by one or more custom routing mask layers. Here, "mask" refers to the lithographic mask used in the integrated circuit manufacturing process. Some of the custom mask layers may also affect the functionality of the CHLE itself, by making connections within the HLE (and controlling, e.g., whether the HLE implements an AND or OR gate).
A structured gate array is not field-programmable. Once a custom mask has been made and once a device has been fabricated using this custom mask, the logic implemented in the device is fixed. Such a device is called an application-specific integrated circuit ("ASIC") or, in this case, a "structured ASIC" because at least the rudiments of an array of HLEs are always present (in addition to the customized features provided by the custom mask layers). An ASIC is much smaller than an equivalent FPGA, but the custom mask layers can result in high non-recoverable engineering costs ("NREs"). Once manufactured, it is not possible to fix mistakes in an ASIC without again incurring these NRE costs.
Technology mapping refers to the steps by which a design engineering automation ("EDA") software tool converts a user's specification of a design into a netlist of logic elements. Typically, the user's representation of a design is specified as a network of logic gates (e.g., AND gates, OR gates, and register primitives). In the prior art, technology mapping to LEs (for FPGAs) and technology mapping to CHLEs (for structured ASICs) have used different methods. In the case of FPGAs, the algorithms typically included partitioning the user's netlist into cones of logic with N or fewer inputs (since a LUT can implement any function with N or fewer inputs). This is typically implemented using well-known algorithms for finding min-cuts in a graph. In the case ASICs, the algorithm is implemented using a predefined library of logical functions, each of which has a predefined mapping into a small network of one or more HLEs. Both methods then typically use these algorithm implementations inside a bottom-up greedy or dynamic programming algorithm that chooses the best cut or best HLE for each node in the user's netlist. The output netlist includes the LUTs corresponding to the best cut of each visible node, or the best HLE for each visible node (where a visible node is a node that feeds an output pin, or is any input to a LUT or HLE of another visible node). Both methods attempt to minimize an overall metric for the user's design, which is typically a combination of cost and netlist delay. The cost of a LUT is typically fixed, while the cost of a CHLE depends upon the number of HLEs it contains. Secondary cost metrics may also take into account such things as the total number of inputs to the LUT (e.g., in an attempt to minimize routing costs), or the exact library primitive chosen for the CHLE (e.g., some multi-HLE CHLE primitives may have better packing or routing characteristics).
It would be desirable for a programmable logic manufacturer to be able to offer both an FPGA and an equivalent structured ASIC device to its customers. This would allow customers to initially design for the FPGA device without incurring any NRE costs, but also, after their design is fully debugged and production has ramped up, to switch to the ASIC device to reduce their unit-device costs.
In order to make the conversion of a design from an FPGA to an ASIC as seamless as possible, it would be desirable to make the network of LEs and the network of CHLEs be as similar as possible. In particular, it would be desirable to have the visible nodes of the LE netlist also be visible in the CHLE netlist, and vice-versa, so that nodes with the same name and implementing the same functionality exist in both devices. This would simplify functional and timing verification between the two netlists. These verification steps are important to catch errors (which could occur in the FPGA to ASIC conversion) before incurring the large NRE cost due to mask and device manufacturing. The timing verification is particularly important, because the FPGA and ASIC devices will have different timing characteristics (with the internal delays of the ASIC typically being much less than those in the FPGA).
What is desired is an ASIC-aware technology mapper for an FPGA device, which takes the costs and visible nodes of both types of networks into account simultaneously.

Methods for producing mappings of logic suitable for FPGA and structured ASIC implementations


A building board includes an undercoat coating, an overcoat coating having lower pigment content than the undercoat coating and having different hue from the undercoat coating and having variations in position and thickness, an inkjet coating having different hue from the overcoat coating and is applying partially, and a clear coating successively formed on surface of inorganic base material having a plurality of wood board patterns. There also is provided a method for manufacturing a building board including the steps of applying an undercoat paint to surface of inorganic base material having a plurality of wood board patterns, applying an overcoat paint having lower pigment weight concentration than the undercoat paint and having different hue from the undercoat paint, scraping off a part of the applied overcoat paint before the overcoat paint cures, partially applying inkjet painting having different hue from the overcoat paint, and applying a clear paint.

1. Field of the Invention
The present invention relates to building boards that constitute exterior and interior walls of buildings.
2. Description of the Related Art
Conventionally, construction of exterior and interior walls of buildings by installing a plurality of building boards to a structural building frame of a building has been performed. For this purpose, attempts have been made to improve the design by, for example, providing a pattern of deep irregularities on the surface of a building board. For example, JP 2004-353299A discloses a building board that is manufactured by forming a wood grain pattern on the surface of a building board and that presents a wood grain design and appearance, as well as a manufacturing method therefor.
However, recently, there has been a demand for a building board that more closely resembles wood and that presents a three-dimensional appearance. Thus, the inventor of the present invention has conducted intensive research on a building board that closely resembles wood and that presents a three-dimensional appearance and a manufacturing method therefor.

Building board and method for manufacturing the same