The present invention offers a universal guide device capable of using the sliders of conventional straight guide devices intact. The universal guide device does not need a different slider for each different radius of track rail. The universal guide device can be manufactured at lower cost than heretofore. This universal guide device in accordance with the invention comprises a track rail and sliders mounted to the rail via balls circulating through endless circular paths. The rail has at least one straight region and at least one curved region shaped in an arc with a given radius of curvature. Each of the sliders is of saddlelike cross section. The sliders span the rail. The sliders have ball-rolling surfaces shaped linearly. The curved region of the rail is set narrower than the straight region of the rail.

1. Field of the Invention
The present invention relates to a universal guide device that is used in sliding portions of various machine tools, part-conveying systems, and so on and is capable of guiding a movable object or material over a conveyance path containing both straight and curved regions.
2. Related Art
For example, on a product line or the like in a plant, if all processing stations are arranged linearly, then no problems will take place. However, depending on the space of the plant in which a machine is installed or on the contents of the processing performed in processing stations, it may be necessary to change the direction of conveyance of materials to be processed between two adjacent processing stations. In this case, it is customary to use a pallet changer or the like to achieve a change in the direction of conveyance. Unfortunately, additional space and cost for installing the pallet changer or the like are necessary.
Known means for modifying the direction of conveyance of materials or objects without using a pallet changer include universal guide devices (as described in Laid-open, unexamined Japanese patent application Nos. 293319/1988 and 50333/1994) capable of guiding materials continuously along a path including both straight and curved lines and curved guide devices (as described in Laid-open, unexamined Japanese patent application No. 186028/1988) capable of guiding materials continuously along an annular path.
These universal guide devices and curved guide devices each comprise a track rail, a slider, and a number of balls. The rail forms longitudinally extending surfaces on which the balls roll. The slider is mounted to span the rail. Load-rolling surfaces opposite to the rolling surfaces of the rail and an endless circular path for the balls are formed on and in the slider. The endless circular path includes the load-rolling surfaces. The balls roll in the endless circular path of the slider and between the rolling surfaces of the rail and the load-rolling surfaces of the slider carry a load. The slider moves along the rail in response to rolling movement of the balls.
In the former universal guide device, each load-rolling surface of the slider is partitioned into straight load regions formed linearly and curved load regions shaped into an arc in conformity with the curvature of the rail. In each straight load region of the rail, the load acting on the slider is carried by the balls rolling in the straight load region. In each curved region, the load is carried by the balls rolling in the curved region. As a result, even if straight and curved regions are intermingled on the track rail, the slider can move along the rail through the straight and curved regions continuously.
In the latter curved guide device, the track rail is shaped into an arc having a given curvature. The load-rolling surface of the slider is shaped into an arc in conformity with the curvature of the rail. All the balls interposed between the load-rolling surface of the slider and the rolling surface of the rail roll on while carrying the load acting on the slider. In consequence, the slider can make a curved motion along the rail.
In these conventional universal guide devices and curved guide devices, the load-rolling groove or race in the slider is shaped into an arc in conformity with the curvature of the track rail to permit movement of the slider through the curved region of the rail. Therefore, it has been necessary to machine the load-rolling surface in conformity with the curvature of the rail. Consequently, it has been impossible to directly use the sliders of conventional mass-produced linear guide devices that are available in the market. Hence, the production cost is increased. Furthermore, a different slider is necessary for each different curvature of track rail. Therefore, it is laborious to machine the sliders and to manage finished products.
Where the load-rolling surface of a slider is machined into an arc, the direction of bending of the curved region of a track rail is limited to one direction, left or right. Although it is possible to transport materials and objects annularly, it is impossible to convey materials along a track including two curved regions bent in different directions such as an S-shaped track.
On the other hand, in a path between two adjacent machining stations on a product line, if materials can be transported, no problems take place. It is considered that capability to carry very large loads is not necessary in curved regions of the rail. However, during a machining process, a machining force acting on a material needs to be sustained reliably by a guide device. Straight regions of the rail are required to have ability to carry a larger load than curved regions. In the aforementioned conventional universal guide device, the load-rolling surface formed on the slider is divided into straight and curved load regions. Therefore, the straight regions of the rail have decreased ability to sustain loads. Consequently, a machining force acting on materials cannot be sufficiently sustained.
Where materials are actually transported using such universal guide devices, it is necessary to construct a moving table device from two or more universal guide devices in order to transport such materials stably. In particular, two track rails are placed parallel to each other. Plural sliders are mounted to each track rail. A table is mounted so as to span all of these sliders. The materials to be transported are placed on this table.
Where the table is moved only through a linear region or only through a curved region, if all the sliders are mounted directly to the table, no problems take place. The table can be smoothly moved. However, where the table is moved from a curved region to a straight region or vice versa continuously, if all the sliders are directly mounted to the same table, the configuration of one slider relative to the track rail is restricted by other sliders. This makes it difficult to move the table smoothly. Accordingly, where plural universal guide devices of the construction described above are used to construct the moving table device, it has been impossible to mount the sliders directly to the table.
In view of the foregoing problem, the present invention has been made. It is an object of the present invention to provide a universal guide device which can directly use sliders heretofore employed in linear guide devices and which do not need different sliders for each different radius of track rail and thus can be fabricated at lower cost than conventionally.
It is another object of the invention to provide a universal guide device in which sliders can move through two curved regions of a track rail continuously along the rail even if the two curved regions are bent in different directions and in which the sliders can move from a straight region to a curved region or vice versa continuously without sacrificing the ability of the rail to sustain a load in the straight region even if the rail contains both straight and curved regions.
It is a further object of the invention to provide a moving table device comprising plural parallel track rails and plural sliders mounted to each track rail, the moving table device being characterized in that smooth movement of the sliders is assured even if a table is supported by the sliders that are four or more in number.
To achieve the objects described above, a universal guide device in accordance with the present invention comprises: a track rail including a straight region and a curved region shaped into an arc with a given radius of curvature and having ball-rolling surfaces on both its side surfaces, the ball-rolling surfaces extending longitudinally; a slider having a saddlelike cross section and mounted to span the track rail; load-rolling surfaces formed on the slider and located opposite to the rolling surfaces, respectively, of the rail; and an endless circular path for a number of balls. The circular path is formed on the slider and includes the load-rolling surfaces. The numerous balls sustain a load between each rolling surface of the track rail and each load-rolling surface of the slider. The load-rolling surfaces formed on the slider are formed linearly. The width of the curved region of the track rail is set narrower than the straight region of the rail.
In this universal guide device in accordance with the present invention, the load-rolling surfaces formed on the slider are not shaped into an arc corresponding to the curvature of the curved region of the track rail. Rather, the load-rolling surfaces are formed linearly in conformity with the rolling surfaces of the straight region of the track rail. In the present invention, however, the curved region of the rail is set narrower than the straight region of the rail. Therefore, if the rolling surfaces of the rail assume the form of an arc, and if the load-rolling surfaces of the slider are linear, the slider can engage the curved region of the rail and can move along the curved region without trouble.
When the slider is moving through the curved region of the track rail, the balls are squeezed in between the arc-shaped rolling surfaces formed longitudinally of the rail and the linear load-rolling surfaces formed on the slider and roll along the load-rolling surfaces while carrying the load. Therefore, with respect to the numerous balls rolling on the load-rolling surfaces, only some of the balls carry the load between the rolling surfaces of the rail and the load-rolling surfaces of the slider.
In this universal guide device in accordance with the present invention, the load-rolling surfaces formed on the slider are shaped linearly rather than into an arc. Therefore, the sliders of linear guide devices can be used intact. Furthermore, an operation for machining the load-rolling surface into an arc in conformity with the curvature of the track rail is dispensed with. Therefore, it is possible to fabricate a universal guide device at quite low cost. Furthermore, the linearly formed load-rolling surfaces have no directivity. Consequently, even if two curved regions bent in different directions are contained in the rail, the slider can move through these curved regions continuously.
In addition, in the universal guide device in accordance with the present invention as described above, all the balls rolling on the load-rolling surfaces of the slider bear against the rolling surfaces of the track rail within the straight region of the rail. Therefore, the ability of the slider to sustain a load is not impaired, unlike the case in which only some balls bear against the rolling surfaces in a curved region. If large loads act on the slider, the loads can be sufficiently sustained.
In the present invention, as long as the ball-rolling surfaces on the track rail side are formed on the surfaces of the rail, balls forming a row and rolling on the load-rolling surface of the slider do not simultaneously touch the arc-shaped rolling surface on the rail side. Therefore, this rolling surface may be shaped in the same way as the rolling surface of the prior art curved guide device without needing any special machining operation. Furthermore, this track rail can be easily fabricated, because one surface of the rail and the arc-shaped rolling surface formed on it can be simultaneously ground. However, where an upward facing rolling surface is formed on the top surface of a track rail, this rolling surface needs to be machined in a special manner. In particular, a downward facing load-rolling surface is linearly formed on the slider in an opposite orientation to the upward facing rolling surface of the track rail. Consequently, this upward facing rolling surface needs to have such a width that balls forming a row and rolling on the downward facing rolling surface of the slider simultaneously touch the upward facing surface.
In the universal guide device in accordance with the present invention, the slider can move through both straight and curved regions of the track rail freely. Therefore, if this rail is composed of only curved regions, the slider can move along the annular rail. That is, where attention is paid to only the curved region of the rail, the universal guide device in accordance with the invention can be regarded as a curved guide device.
As mentioned previously, in the universal guide device in accordance with the present invention, the straight and curved regions of the track rail differ in width. Therefore, it is desired to provide an intermediate rail portion connecting the straight and curved regions of the rail such that the width of the rail varies continuously in this intermediate rail portion.
Moreover, a moving table device can be built using universal guide devices of the construction in accordance with the invention as described above. Specifically, plural track rails are mounted parallel to each other on a fixed portion such as a pedestal or a base. A table is mounted to span sliders that move on these rails. However, if two or more sliders are mounted to each rail, and if all of the sliders are directly mounted to the same table, it will be difficult to move the table smoothly between the straight and curved regions of the rail, as mentioned previously.
In view of this, first and second track rails are mounted parallel to each other. Plural sliders are mounted to each of these rails. A fixed plate is made to span one slider mounted to the first rail and one slider mounted to the second rail such that these two sliders are coupled. Another fixed plate is bridged across another slider mounted to the first rail and another slider mounted to the second rail, and so on. Preferably, the table is mounted so as to be rotatable relative to the fixed plates. Where the moving table device is constructed in this way, even if the table is supported by the sliders that are four in number, the first fixed plate bridged over the first row of sliders that is the forerunner in the direction of movement and the second fixed plate bridged over the second row of sliders rotate in such a way that the sliders are oriented in the tangential direction of the rails. The distance between the sliders on the rails is made variable. Hence, the sliders can move smoothly.
Additionally, the table can be smoothly moved between the straight and curved regions of the rail by mounting the first and second rails parallel to each other, mounting plural sliders to each of the rails, and mounting the table so as to be rotatable relative to the sliders. That is, in this structure, when the sliders move through the curved region of the rail, they rotate to arbitrary directions so as to orient themselves to the tangential direction of the rails. This permits smooth movement of the sliders.
As described thus far, in the universal guide device in accordance with the present invention, the load-rolling surfaces formed on the sliders are only required to be shaped linearly rather than into an arc. Therefore, the sliders of numerous linear guide devices available on the market can be used intact. Moreover, it is not necessary to machine the load-rolling surfaces in conformity with the curvature of the rails. In consequence, the sliders can be manufactured easily and inexpensively.
Since the load-rolling surfaces formed on the sliders have no directivity, if each track rail has two curved regions bent in different directions, the sliders can move through the curved regions continuously along the rail. For example, materials can be guided freely along a track having a high degree of freedom (e.g., consisting of a combination of straight lines and curved lines such as an S-shaped track).
Because the load-rolling surfaces formed on the sliders are linear, all the balls rolling on the load-rolling surfaces of the sliders bear against the rail in the straight regions and sustain the load. Therefore, the sliders can exhibit sufficient ability to sustain the load within these straight regions. If straight and curved lines are intermingled on the rail, the sliders can move through the straight and curved regions continuously without sacrificing the ability of the rail in the straight regions to sustain the load.
Other objects and features of the invention will appear in the course of the description thereof, which follows.

Universal guide device and moving table device using same


Method and systems for nerve repair and for microfabrication. In specific embodiments, nerve repair is accomplished by repairing axons. In further embodiments, a modular, 3D system having very small dimentions is described. In further embodiments, a method ans system for performing surgery on axons is disclosed.

The discussion of any work, publications, sales, or activity anywhere in this submission, including in any documents submitted with this application, shall not be taken as an admission that any such work constitutes prior art The discussion of any activity, work, or publication herein is not an admission that such activity, work, or publication existed or was known in any particular jurisdiction.
Many fields of human endeavor, both biological and non-biological, would benefit from more precise manipulation of very small structures. Consider the nervous system. Injury may occur to the central nervous system (CNS), consisting of the eyes, brain, and spinal cord, or the peripheral nervous system (PNS), consisting of nerves to arms, legs and internal organs. In humans and other mammalian species, injuries to CNS axon pathways can have extremely severe consequences such as paraplegia or tetraplegia. Peripheral nerve injury can also lead to severe sensory motor disability for extended periods that often only result in partial recovery.
As one example of the need for very small scale manipulation, currently, there is no specific therapeutic treatment for nerve injuries in either the CNS or PNS. Conventional research strategies call for the regeneration of axons from the site of injury to reestablish contacts with post-synaptic targets and thereby obtain functional recovery. Despite much research effort, the complexities of the cellular and molecular mechanisms required for adult axon regeneration have proven to be significant impediments to this approach.
A number of patents and publications discuss various MEMS devices and manufacturing techniques thereby. Some of these are listed below. This list is not intended to suggest that any search has been performed and is not exhaustive. These patents and their incorporated documents are incorporated herein by reference to provide background information and for any other purposes.
PatentTitleU.S. Pat. No.Membrane seal secured to inner and outer oscillating6,125,007bearing members for small angle oscillations withinconfined axial spaceU.S. Pat. No.Method for Fabrication needles via conformal6,106,751deposition in two-piece moldsU.S. Pat. No.High Vertical Aspect Ratio Thin Film Structures for6,015,599immunological isolation of cell transplantsU.S. Pat. No.Microfabricated thin film particle filter and5,948,255methods of making itU.S. Pat. No.Microfabricated capsules for immunological isolation5,893,974of cell transplantsU.S. Pat. No.Microfabricated particle filter5,651,900U.S. Pat. No.Seal for bearings in small angle oscillation5,416,657applicationsU.S. Pat. No.Multilayer high vertical aspect ratio thin film5,645,684structures

Nerve repair by selective surgical repair of axons

The Regents of the University of California


A method for monitoring oxide film deposition is disclosed. The method utilizes monitor wafers having silicon nitride films thereon instead of bare wafers to monitor the growth of silicon oxide films in a furnace. The method for monitoring oxide film deposition includes the following steps. First of all, a monitor wafer having silicon nitride film and a process wafer are provided. Next an oxide layer is formed on the monitor wafer and the process wafer, and the thickness of the oxide layer is controlled substantially equally on the monitor wafer and the process wafer. Then the thickness of the oxide layer on the monitor wafer and the process wafer is measured.

1. Field of the Invention
The present invention relates to a method for monitoring oxide film deposition, and more particularly to a method for monitoring high temperature oxide (HTO) film deposition in a vertical HTO furnace.
2. Description of the Related Art
In the semiconductor industry, the oxide film deposition process which is performed in a vertical furnace has several issues to be solved. For example, as shown in FIG. 1A, the oxide film deposition process is used to form the silicon oxide films 51, 53 of an oxide-nitride-oxide (ONO) stack layers 55 of a semiconductor device 50. There is a nitride film 52 between the oxide film 51 and the oxide film 53. The semiconductor device 50 can be a non-volatile memory device or a flash memory device. However, the thickness of the oxide films 51, 53 formed on wafers which are loaded on different locations of the vertical furnace would vary due to the characteristics of the vertical furnace. To solve this problem, the wafer loading sequence between the depositions of the top oxide film 53 and the bottom oxide film 51 of the ONO stack layers 55 is reversed to balance the variation of thickness of the ONO stack layer.
Since the thickness of the oxide film is a crucial dimension for the semiconductor device 50 such as a non-volatile memory device or a flash memory device, monitoring the oxide film deposition is inevitable. In order to monitor the deposition of the oxide film, monitor wafers are utilized to measure the growth rate of the oxide film deposition. However, the conventional monitoring method has a troubling drawback. As shown in FIG. 1B, the monitor wafers 100a, 100b and 100c having native oxide films 102a, 102b and 102c thereon are located on the top, middle and bottom locations inside a furnace 300 respectively. A plurality of process wafers 400 are loaded together into the furnace 300 to form oxide films. The native oxide films 104a, 104b and 104c are formed during the wafer loading process. The variation of the thicknesses of native oxide films 104a, 104b and 104c generally results from the air flow brought into the furnace 300 during the wafer loading process and the different locations inside the furnace 300. After the wafer loading process, the furnace 300 is closed and starts to grow oxide films 106a, 106b and 106c on the native oxide films 104a, 104b and 104c. Because the native oxide films formed on the monitor wafers 100a, 100b and 100c are not well controlled, the growth rate of the oxide film deposition on the monitor wafers 100a, 100b and 100c would mislead the setting of the oxide film deposition process and result in wrong thickness of oxide films 51, 53 of the semiconductor device 50 such as a flash memory device deviate the predetermined value and unstable electrical characteristics of the semiconductor device 50.
In view of the drawbacks mentioned with the prior art, there is a continued need to develop a new and improved method for monitoring oxide film deposition that overcomes the disadvantages associated with prior art. The requirements of this invention are that it solves the problems mentioned above.

Method for monitoring oxide film deposition


A multistage amplifier circuit comprises a current constant mode variable amplifying circuit for amplifying an input signal and current variable mode variable amplifying circuits and for further amplifying the signal amplified by the first variable amplifying circuit. An AGC voltage VAGC is commonly applied between the bases and emitters of an amplification degree control transistor of the current constant mode variable amplifying circuit and amplification degree control transistors of the current variable mode amplifying circuits. Collector currents of the transistors change exponentially with respect to the linearly-varied AGC voltage VAGC. Further, currents each proportional to the collector current of the transistor flow in the transistors. Thus, the gain PG dB! of the current constant mode variable amplifying circuit changes linearly with the AGC voltage VAGC.

1. Field of the Invention
The present invention relates to a multistage variable gain amplifier circuit suitable for radio-frequency amplifying circuits of, for example, a CDMA (Code Division Multiple Access) mode portable telephone.
2. Description of the Related Art
In a CDMA mode portable telephone, variable gain amplifying circuits (hereinafter called "variable amplifying circuits") capable of varying a gain of 80 dB or above are normally provided at radio-frequency amplifying circuits of a transmitter unit and a receiver unit, respectively, in order to maintain communication when the portable telephone moves. FIG. 4 shows a radio frequency stage of a portable telephone having general CDMA and FM dual modes. A description will first be made of a configuration of a transmission (TX) system. An IF (intermediate frequency) transmit signal modulated by a modem 101 is QPSK-modulated by a QPSK modulating circuit 102. Next, the modulated signal is amplified by a transmitter variable amplifying circuit (TX-AMP) 103, which in turn is mixed into a local oscillating frequency produced from a local oscillator (OSC) 121 by a mixer (MIX) 104, where the mixed signal is converted into an RF (radio frequency) transmit signal. The RF transmit signal is transmitted through a band-pass filter 105, a power amplifier (PA) 106, a duplexer 107 and an antenna 108.
A description will next be made of a configuration of a reception (RX) system. An RF receive signal received by the antenna 108 is applied to a mixer (MIX) 111 through the duplexer 107, a low noise amplifier (LNA) 109 and a band-pass filter 110, where the signal is mixed into a local oscillating frequency generated from the local oscillator (OSC) 121 converting the signal into an IF receive signal. The IF receive signal is applied to a CDMA band-pass filter 112 and an FM band-pass filter 113, where one output signal is selected according to a set mode and amplified by a receiver variable amplifying circuit (RX-AMP) 114. Next, the amplified signal is demodulated by a QPSK demodulating circuit 115, and then provided to the modem 101.
The strength of the received signal, which has been detected by a receive-signal strength indicating circuit (RSSI) 116 provided within the modem 101 is compared with strength reference data by a comparator 117. The difference in strength therebetween is applied to a receiver AGC voltage correction circuit 118 and a transmitting output correction circuit 119. The AGC voltage correction circuit 118 outputs an AGC output so that the difference produced from the comparator 117 becomes "0," i.e., the output of the RSSI 116 coincides with the strength reference data, thereby controlling the gain of the variable amplifying circuit (RX-AMP) 114 on the receiving side. The difference produced from the comparator 117 and transmitting output correction data determined according to circuit conditions between a portable telephone and a base station are applied to the transmitting output correction circuit 119 on the transmitting side. An AGC voltage correction circuit 120 on the transmitting side outputs an AGC voltage so that a modulated signal is inversely proportional to the level of the received signal, and according to the transmitting output correction data, thereby controlling the gain of the variable amplifying circuit (TX-AMP) 103 on the transmitting side.
In this case, excellent linearity is required between the AGC voltage and the gain over a dynamic range of 80 dB or above in order to allow the variable amplifying circuits 103 and 114 on the transmitting and receiving sides to operate in interlock with each other. Since the portable telephone is driven by a battery, the battery power decreases as current consumption increases. As a result, a problem arises in that, for example, standby time and call duration are reduced and the battery must be replaced frequently. It is thus desired that the variable amplifying circuits 103 and 114 also provide current consumption as low as possible.
There are known current constant mode and current variable mode variable amplifying circuits whose differential amplifiers are respectively connected to constant-current sources. The range in which the gain can be linearly controlled, is normally about 20 dB to 30 dB in a variable amplifying circuit of one stage. A method of cascade-connecting variable amplifying circuits of the same type in three to four stages on a radio-frequency basis and parallel applying an AGC voltage to the respective variable amplifying circuits allows a dynamic range of gain of 80 dB or above.
FIGS. 5 and 6 respectively show commonly-used current constant mode and current variable mode variable amplifying circuits each composed of bipolar transistors. Symbols IN, OUT, VAGC and Vcc denote an input, an output, an AGC voltage and a power source voltage respectively. FIG. 7 shows the gain PG with respect to the AGC voltage VAGC, in which g represents a characteristic of the current constant mode variable amplifying circuit and h presents a characteristic of the current variable mode variable amplifying circuit.
In the current constant mode shown in FIG. 5, gain variable transistors Q1, Q2, Q3 and Q4 and amplifying transistors Q5 and Q6 constitute a differential amplifier. Further, resistors R1 and R2 are respectively load resistors for the transistors Q1 and Q4, E1 is a bias supply or source, and CS1 is a constant-current source.
The gain PG dB! of the current constant mode shown in FIG. 5 is represented by the following expression: EQU PG.varies.PGO+20 log (I1/I0) (1)
where PGO indicates gain at the time that I1 is I0. Further, the relationship between I1 and I0 (I1/I0) is represented by the following expression: EQU I1/I0.varies.1+exp{-VAGC*q/(kT)}! (2)
where
q: unit charge of electron PA1 k: Boltzmann constant, and PA1 T: absolute temperature. PA1 PG.varies.VAGC
The gain PG of the characteristic g does not change linearly when the AGC voltage VAGC is large. In the current constant mode, the amount of tertiary distortion caused by interference or disturbing waves is kept constant regardless of the magnitude of the gain PG. Further, the current consumption is also held constant regardless of the magnitude of the gain PG. In the variable amplifying circuit of a type wherein the current constant mode shown in FIG. 5 is connected in multistage form, the relationship between input intercept points and current consumption with respect to the gain PG is represented in the form of characteristics a and b in FIG. 3. The input intercept point characteristic a in a low range of gain PG is but the current consumption characteristic b is constant.
The current variable mode shown in FIG. 6 comprises gain variable transistors Q7 and Q8, a transistor Q15 for a constant current circuit, and load resistors R3 and R4 for the transistors Q7 and Q8. The gain PG dB! of the current variable mode is represented by the following expression: EQU PG.varies.20 log (I2) (3)
Further, I2 is represented as follows: EQU I2.varies.exp{VAGC*q/(kT)} (4)
Substituting the expression (4) in the expression (3) yields:
As indicated by the curve h in FIG. 7, the gain PG changes linearly with the AGC voltage VAGC. In the variable amplifying circuit of a type wherein the current variable mode is connected in multistage form, the relationship between input intercept points and current consumption with respect to the gain PG is represented in the form of characteristics c and d in FIG. 3. Since a collector current is small, distortion is apt to appear.
However, the variable amplifying circuit in which the current constant mode shown in FIG. 5 is connected in multistage form, has a problem in that the current consumption is large as compared with the current variable mode as indicated by b and d in FIG. 3.
Further, the variable amplifying circuit in which the current variable mode shown in FIG. 6 is connected in multistage form, has a problem in that although the current consumption is small as compared with the current constant mode, the input intercept points deteriorated in the low range of gain PG as compared with the current constant mode as indicated by a and c in FIG. 3. As a result, when a strong electric field is present, other stations will interfere with the corresponding circuit.
In a configuration in which the current constant mode and the current variable mode are cascade-connected, the current constant mode is different in AGC voltage VAGC from the current variable mode. Further, they are different from each other in the characteristic of the gain PG with respect to the AGC voltage VAGC. Therefore, the linearity of gain PG deteriorates.

Multistage variable gain amplifier circuit


In one aspect, the invention provides a method of forming an integrated circuitry memory device. In one preferred implementation, a conductive layer is formed over both memory array areas and peripheral circuitry areas. A refractory metal layer is formed over the conductive layer to provide conductive structure in both areas. According to a preferred aspect of this implementation, the conductive layer which is formed over the memory array provides an electrical contact for a capacitor container to be formed. According to another preferred aspect of this implementation, the conductive layer formed over the peripheral circuitry area constitutes a conductive line which includes at least some of the silicide. In another preferred implementation, the invention provides a method of forming a capacitor container over a substrate. According to a preferred aspect of this implementation, a conductive layer is elevationally interposed between an upper insulating layer and a lower conductive layer over the substrate. The upper insulating layer is etched relative to the interposed conductive layer to form a capacitor container first portion. Subsequently, the interposed conductive layer is etched to form a capacitor container second portion.

Integrated memory devices typically include a memory array area and a peripheral circuitry area. The memory array area constitutes the area in which information or data is stored. The peripheral circuitry area constitutes integrated circuitry which, in part, controls or provides access to the memory array area. One type of integrated memory device is a dynamic random access memory (DRAM) device. DRAMs include, as part of the memory array, plural capacitors which are used to store charges. It is desirable to fabricate integrated circuitry memory devices to have fairly close, comparable, and repeatable capacitance values.
Stacked DRAM capacitors are typically formed from a plurality of layers provided over a substrate by etching at least some of the layers to form a desired capacitor container construction. Capacitors are thereafter formed in the etched containers. To increase the capacitance values of the subsequently formed capacitors, a timed etch is typically conducted to further etch the provided layers after an initial capacitor container definition etch is conducted. Such timed etches can be problematic for a number of reasons. For example, such etches must be carefully monitored and timed to ensure that the etch does not undesirably extend into adjacent integrated device components, which can destroy the circuit. Thus, control of the etches is of major concern. Another problem is that reproducibility of the depth of such etches can be difficult to attain given variations in the processing regimes and materials used to fabricate the capacitor containers. Thus, a need exists for semiconductor processing methods which enable memory devices to be fabricated with predictable and readily reproducible capacitance values.
Another problem associated with the fabrication of integrated memory devices concerns forming electrical connections between conductive lines and substrate active areas in peripheral circuitry areas of the memory array. More specifically, it is sometimes desirable for conductive lines to be electrically connected with substrate active areas which are disposed elevationally lower over a substrate than the respective conductive lines. Typically, the elevational separation between the conductive lines and the substrate active area is due to one or more layers which are interposed between the conductive lines and the corresponding active area to which electrical connection is desired. Often such conductive lines do not typically directly overlie the entire active area with which electrical connection is desired. One prior art solution is to provide a conductive plug of material which extends generally vertically between and connects with the overlying conductive line and only a portion of the active area with which electrical connection is desired. This, however, gives rise to increased resistance and hence lower conductivity as between the conductive line and the elevationally lower substrate active area. Thus, a need exists to provide improved semiconductor processing methods and related integrated circuitry formed thereby with improved conductive connections between elevationally separated conductive lines and substrate active areas.
This invention arose out of concerns associated with forming integrated memory circuitry, particularly DRAM memory devices, with standardized and readily reproducible component values, as well as improving conductive connections between the memory device components.

Semiconductor processing methods of forming integrated circuitry memory devices, methods of forming capacitor containers, methods of making electrical connection to circuit nodes and related integrated circuitry


A device for implementing FFT/DFT is disclosed, comprising: a first multiplier, a second multiplier, a first adder, a second adder, a first multiplexer, a second multiplexer, a first accumulator register, a second accumulator register and a negation controller, wherein the first adder is configured to accumulate the output signals of the first multiplexer, the first multiplier and the second multiplier and input an accumulated signal to the first accumulator register; the second adder is configured to accumulate the output signals of the second multiplexer, the first multiplier and the second multiplier and input an accumulated signal to the second accumulator register; the first accumulator register is configured to output the output signal of the first adder or feed the same back to the first multiplexer; and the second accumulator register is configured to output the output signal of the second adder or feed the same back to the second multiplexer.

The FFT/DFT is widely applied to a communication system for processing a signal, including the communication system such as Long Term Evolution (LTE) involving in Orthogonal Frequency Division Multiplexing (OFDM), Worldwide Interoperability for Microwave Access (Wimax), China Mobile Multimedia Broadcasting (CMMB), Digital Video Broadcasting (DVB), Digital Audio Broadcast (DAB), Digital Subscriber Line (DSL) or the like.
For DFT, the DFT of finite length sequence x(n) with a length of N is computed by the following formula:
      X              (      k      )        =            DFT                    [                  x                                (            n            )                          ]              =                  ∑                  n          =          0                          N          -          1                                            x                                (            n            )                                                                      W              N              nk                                                  (                                                k                  =                  0                                ,                1                ,                                                      …                                                                                N                                    -                  1                                            )                                .                    In general, x(n) is a sequence of complex number. For a k value, it is needed N complex multiplications and (N−1) complex additions to compute a x(k) value according to the above formula, so the amount for computing directly the DFT is positive proportional to the square of the length N of a transform interval. When N is large, too large amount of computation will result in too long computation time and will result in waste of software and hardware resources. Therefore, the FFT emerges in order to avoid the problem of big difficulty when the signal is processed in real time by using the DFT directly.
The FFT is a fast algorithm of the DFT, which may simplify the amount of computation of the DFT, and improves the operation speed. Since the coefficient
      W    N    nk    =      ⅇ                  -        j                                                              2                    π                N                  nk      is a periodic function and is of periodicity and symmetry. According to the symmetry of WNnk, it is obtained that (WNnk)*=WN−nk, WNk+n/2=−WNk, WNn(N+k)=WNk(N+n)=WNnk and WNn(N−k)=WNk(N−n)=WN−nk. The operation of the DFT may be broken up into DFT operations of fewer points to the greatest extent by taking advantage of the periodicity and symmetry of WNnk.
At present, a traditional FFT/DFT may be computed by using a general-purpose operation unit or a special-purpose butterfly operation unit of some form. The traditional general-purpose operation unit may implement a real multiply operation, a real add operation, a real multiply-add operation, a real multiply-accumulate operation, a complex multiply operation, a complex add operation, a complex multiply-add operation, a complex multiply-accumulate operation and a radix 2 butterfly operation, but may not implement N-point high-order butterfly operation (N is a positive integer greater than 2). When the N-point high-order butterfly operation is performed, a relatively complicated special-purpose butterfly operation unit is usually adopted, for example the special-purpose butterfly operation unit which supports radix 3, radix 4 and radix 5 butterfly operations simultaneously may be adopted. However, the special-purpose butterfly operation unit of this type can only process the FFTs/DFTs of some fixed points after the special-purpose butterfly operation unit is designed. In a concrete application environment, the FFTs/DFTs of multiple fixed points may need to be computed. The special-purpose butterfly operation unit in the related art exits the problem of low flexibility, and at the same time, the special-purpose butterfly operation unit of this type often needs to consume more hardware resources and exits the problem of high complexity and power consumption. Thus, the operation speed is low when the signal is processed in real time, which is not conducive to the application of a mobile terminal.

Device and method for implementing fast fourier transform/discrete fourier transform


The construction of Shallow Trench Isolation, STI, regions is integrated in to a SIMOX fabrication process for a Silicon On Insulator, SOI, wafer. Prior to the beginning of the SOI process, a preferred nitrogen (N2) implant is applied to the silicon wafer in areas designated as active regions. The nitrogen modifies the oxidation rate of later implanted oxygen. Regions where the N2 is implanted result in thinner oxide layers. The SIMOX process can begin following the implantation of nitrogen. This results in buried regions of thick and thin oxide layers at fixed depths in the Si substrate. Excess Si on top of the buried thick and thin oxide regions can be polished down to the thick oxide regions to form the active device regions over the thin oxide regions. Thus, the SOI wafer exhibits an STI structure upon completion of the SOI process without a need for additional STI manufacturing steps.

1. Field of the Invention
The present invention relates to the construction of isolation region in integrated circuits, and particularly relates to the construction of isolation regions in silicon on insulator, SOI, structures.
2. Description of the Related Art
Silicon on insulator, SOI, is fast becoming the technology of choice for high performance MOS integrated circuits. Circuits constructed on SOI wafers are more resistant to high voltage damage (such as from drain-to-source punch through), are relatively immune from latchup problems, and have less parasitic capacitance as compared to bulk or epitaxial wafers. However, SOI wafers are more expensive, and thus any reduction in the production of SOI based circuits is of importance in reducing cost.
With reference to FIG. 1, a SOI wafer 11 is characterized by an insulator layer 13 buried under its top semiconductor layer 17. Buried insulator layer 13 separates the bulk substrate silicon region 15 from the top active silicon region 17, within which integrated circuits are constructed. As shown in FIG. 2, top layer 17 needs to be divided into active regions 19, within which circuits are constructed, separated by insulation regions 21. Thus, an initial step in the construction of any integrated circuit on a SOI wafer is to subdivide the wafer into active regions and insulation regions.
A preferred insulation method used in SOI technology is shallow trench isolation, STI, which provides a planar surface for further processing and avoids some of the problems inherent to less geometrically defined isolation structures, such as bird's beak issues found in LOCOS isolation.
There are various method of constructing a SOI wafer, including Silicon-On-Sapphire (SOS), Separation by Implanted Oxygen (SIMOX), and wafer bonding (WB). Of these three, SIMOX is the most commonly used method.
With reference to FIG. 3, a typical manufacturing process for constructing shallow trench isolation regions in a SOI wafer starting with a SIMOX process begins with a high dose implantation of oxygen ions O+ (˜2×1018/cm2) at a high energy of about 150-300 keV. This results in a layer 22 of buried oxygen ions O+ deep under the surface of the silicon wafer 11. This ion implantation step is typically executed at a temperature greater than 400° C. to ensure that the silicon maintains its crystallinity during the implantation.
Wafer 11 is then subjected to a heat anneal step (˜3-5 hours), preferably in an N2 atmosphere, at a high temperature of about 1100-1175° C. This permits the buried oxygen ions O+ to diffuse and recombine with the silicon to produce a buried oxide layer (SiO) as shown in FIG. 4, and additionally helps to remove any defects that may have been created during the ion implantation step. This process results in a typical top silicon layer of about 0.5 μm. If a top layer thicker than can be practically achieved by the ion implantation depth is desired, then an optional epitaxial silicon layer, not shown, may be deposited on the top silicon layer 17. At this point, construction of the SOI wafer structure is complete and construction of the isolation regions can begin.
With reference to FIG. 5, construction of the shallow trench isolation regions begins by growing a padding layer of oxide 21, followed by a deposition of a silicon nitride layer 20 by LPCVD, as shown in FIG. 6. Silicon nitride layer 20 is then configured into a mask layer 23 by means of a resist, as shown in FIG. 7. The pad oxide 21 in exposed regions is likewise removed in FIG. 7. Mask layer 23 covers the intended active regions, and exposes the areas where isolation trenches are to be constructed.
In FIG. 8, trenches 24 are form in an anistropic-etching step, typically to a depth of about 400-500 nm. This is followed by growth of a thin thermal oxide layer 25 within trenches 24.
In FIG. 9, a CVD dielectric layer 27 is deposited to fill the trenches. Dielectric layer 27 also covers silicon nitride layers 23. The wafer is then subjected to a chemical mechanical polishing step, CMP, to polish back dielectric layer 27, with silicon nitride layer 23 functioning as a CMP-stop layer, as shown in FIG. 10. The dielectric material is typically then densified at 900° C. Finally in FIG. 11, the silicon nitride is stripped, leaving the desired STI structure of active regions 19 separated by shallow trench isolation regions 21.

Method to fabricate completely isolated silicon regions


A descriptor for a multitier compute infrastructure is provided. A multitier topology map contains an inventory of network tier, application tier, and compute tier components and the relationships among the components. A business service can be defined as a logical grouping of components that transactionally implement a business process. A service descriptor includes the component dependencies that define the business service. The business service leverages the component dependencies to provide cross-tier visibility of the business process and performance analysis features.

With advances in computing, networking and software technology, an increasing number of applications are implemented in distributed environments, often composed of multitier compute infrastructures. For example, many Internet applications are implemented on a compute infrastructure that can be divided into three tiers: network, compute, and application. One advantage of a multitier compute infrastructure is that different tiers can function at different "levels" while still interoperating with each other. In the three-tier example, the network tier operates at the "lowest" level of the infrastructure, the compute tier operates on top of that, and the application tier operates at the "highest" level. As a result, enterprise and other applications can be distributed among the tiers in a fashion that results in greater optimization and utilization of the infrastructure. For example, if a certain functionality is desired, it is not required that the functionality be implemented in a monolithic piece of software installed on a particular computer in a specific location within the network. Rather, the overall functionality can be distributed among different components within the multitier compute infrastructure.
Software component architectures such as Java 2, Enterprise Edition (J2EE™) and .NET are one approach which takes advantage of this flexibility. (J2EE is a trademark of Sun Microsystems, Inc.) Software functionality is divided among different software components, each of which can run on a different host located at a different network address. Each of the software components, computers and the network topology may be optimized for efficiency, security, scalability, or other factors. For example, in the monolithic approach, a single code base and a single computer may be called upon to handle user requests for enhanced images, retrieve raw images from a large image warehouse, and perform complex calculations to enhance the images. With the component approach, one software component and server could handle user requests, another retrieve images, and a third could perform the calculation. The overall enterprise is also more salable since incremental capacity can be added by adding more instances of software components or servers.
One drawback of the multitier and software component approaches is that, typically, many components are used in order to implement the desired functionality. For example, the software portion can be implemented by a large number of software components, each possibly executing on a different server, with the multiple servers located on different networks. Software components may not even be executing on the same server each time. The real-time execution load can be load balanced among a server farm, for example. Currently, it is not uncommon for an enterprise application to have thousands of components, many of which must work simultaneously with each other in order for the overall enterprise application to function properly. In addition, multiple relationships between components exist within each tier, as well as across tiers of the compute infrastructure. For example, in the application tier, a web server and application server might work together to handle user requests. Cross-tier relationships can be more complex, such as those linking the web server, DNS server and access router with each other, but these often are the relationships that have a direct bearing on the availability, performance and security of the overall application.
Due to this increased complexity, managing a multitier compute infrastructure is more difficult. Typical management tools are mostly limited to a single tier. Many of these tools were developed for system administrators who are responsible only for a single tier. That is, one system administrator is responsible for networking, another for computers, and another for software loaded on the computers. Single-tier tools can give some visibility into the tier for which the system administrator is responsible, but do not give visibility into cross-tier relationships or interactions.
Single-tier tools also do not give direct visibility into the service which is a business' end goal. For example, in the image enhancement example, the business is really interested in the delivery of enhanced images, not in the congestion level of its internal routers or the state of its internal network. The router and network are of interest only to the extent that they impact the business service of delivering enhanced images but, with single-tier tools, it is difficult, if not impossible, to determine this relationship. As a result, the relationship typically must be manually pieced together, one tier at a time, and often using knowledge that resides only in some key employee's head. This is both time-consuming and risky—for example, if the key employee were to be unavailable.
Additionally, a lack of knowledge or incorrect knowledge about a cross-tier relationship can make the business impact of an outage unknown. For example, if an application server requires an upgrade to fix a potential security problem, the complexity of the cross-tier relationship may make it difficult to know which businesses processes could be directly or indirectly affected by the application server downtime. Similarly, the scope of the potential security problem could be unknown as well.
Other approaches attempt to address these shortcomings, yet lack visibility into enterprise-wide performance management analytics or business metrics. Much effort is being spent on approaches based on monitoring. OPENVIEW™ and TIVOLI® are examples of efforts in this general direction. (OPENVIEW is a trademark of Hewlett-Packard Company and TIVOLI is a registered trademark of International Business Machines Corp.) Management tools can monitor individual components in the infrastructure through instrumentation with increasing detail and sophistication. This can give improved visibility into the individual component but does not effectively address cross-tier visibility or the relationship between a component and a business service. For example, processor throughput, server availability and similar metrics at best can only give indirect visibility into business services, for example whether customers have access to an enterprise application and can perform promised tasks at published service levels.
What is therefore needed is a logical grouping of distributed components that: (1) provides visibility of cross-tier interactions; (2) provides metrics or performance analysis of a business process; and (3) provides a grouping of logical applications or sub-parts of logical applications to a business service.

Service descriptor for a multitier compute infrastructure

International Business Machines Corporation


A modular biosensor system for chemical or biological agent detection utilizes electrochemical measurement of an ion current across a gate membrane triggered by the reaction of the target agent with a recognition protein conjugated to a channel blocker. The sensor system includes a bioresponse simulator or "biochemical switch" module which contains the recognition protein-channel blocker conjugate, and in which the detection reactions occur, and a transducer module which contains a gate membrane and a measuring electrode, and in which the presence of agent is sensed electrically. In the poised state, ion channels in the gate membrane are blocked by the recognition protein-channel blocker conjugate. Detection reactions remove the recognition protein-channel blocker conjugate from the ion channels, thus eliciting an ion current surge in the gate membrane which subsequently triggers an output alarm. Sufficiently large currents are generated that simple direct current electronics are adequate for the measurements. The biosensor has applications for environmental, medical, and industrial use.

Prior art methods for high-sensitivity detection of chemical and biological materials have typically relied on colorimetric or electrometric analyses of enzymatic or immunological reactions of the test analytes. Enzyme immunoassay (EIA) techniques have been incorporated into a large number of biosensor devices employing colorimetric or fluorimetric analyses, as exemplified in the following U.S. and foreign patents: U.S. Pat. No. 4,343,782; EP 125,554; EP 128,318; EP 231,010; EP 288,256; EP 290,269; SU 1,189,224; JP 57,208,457. In a typical embodiment, an enzyme-conjugated antigen admixed with immobilized antibody reacts competitively with free test antigen to release the enzyme into solution containing its substrate, and subsequent enzyme reaction products are detected by changes in color or fluorescence. A drawback of this method is background color which limits sensitivity.
U.S. Pat. No. 4,343,782 to Shapiro, issued Aug. 10, 1982, describes a cytological assay procedure for non-excitable cells in which their membrane potential measured by an optical property of a permeant dye is used to determine characteristics of individual cells. Japanese Patent No. 57,208,457 to Olympus Optical Co., Ltd., published Dec. 21, 1982, describes an automated apparatus for staining of cells or tissues, including an indicator installed for the determination of dye concentration.
European Patent No. 125,554 to Charlton, published Nov. 21, 1984, describes an ion test means having a hydrophilic carrier matrix, which consists of a hydrophilic carrier matrix loaded with hydrophobic globules containing an ionophore, and a reporter substance and titanium dioxide, in a test strip attached to a support.
European Patent No. 128,318 to Charlton et al., published Dec. 19, 1984, describes the use of substituted indonaphthols as reporter substances in detecting ions in ionophore-containing test strips, for the detection of ions in aqueous solutions. U.S.S.R. Patent No. 1,189,224 to Lemeshko and Brovkovich, published Jul. 26, 1983, describes a method of determining phospholipids in biological membranes, by treating the preparations with chloroform-methanol and a molybdenum color reagent.
European Patent No. 231,010, to Halsey et al., published Aug. 5, 1987, describes a method of solid phase enzyme immunoassay and nucleic acid hybridization assay, in which a chromogenic material upon changing color in the presence of a solid phase enzyme, binds to the solid phase. Color change is analyzed on a dip stick, for use in allergy testing. European Patent No. 288,256, to Toner, published Oct. 26, 1988, describes europium chelates with polypyridine and phenanthroline derivatives for fluorescent labels for immunoassays.
Electrochemical coupling of EIA permits direct electronic readout, but may suffer from similar sensitivity limitations. Examples of prior art methods are disclosed in the following U.S. and foreign patents: U.S. Pat. No. 4,214,968; JP 58,103,659; JP 60, 44,865; JP 62,64,941; JP 63,171,355; JP 63,263,468; EP 302,661. U.S. Pat. No. 4,214,968 to Battaglia et al., issued July 29, 1980, describes a dry operative ion selective electrode comprising a dried salt solution in a hydrophilic polymeric binder in the internal reference, in contact with a hydrophobic ion-selective membrane containing an ion carrier dissolved therein.
Japanese Patent No. 60,44,865 to Fuji Photo Film Co., Ltd., published Mar. 11, 1985, describes a multilayered analytical element for ammonia determination in body fluids comprising a water-resistant support coated with an ammonia indicator layer, a barrier layer which is permeable to ammonia but not to liquid substances, a reagent layer which transforms ammonia-forming substances to ammonia, and a porous spreading layer. Japanese Patent No. 58,103,659 to Toshiba Corp., published Jun. 20, 1983, describes membranes for ion-selective electrodes, including a tetrahydrofuran solution of valinomycin dispersed in polyvinyl chloride in the presence of dioctyl phthalate and potassium tetraphenylboron, dried into a membrane useful for the determination of ions in blood. Japanese Patent No. 63,171,355 to Tsukada et al., published Jul. 15, 1988, describes a semiconductor chemical sensor for blood analysis, in which the surface of a field effect transistor gate on a base is coated with a hydrophilic polymer membrane and the membrane is treated with electrically accelerated particles to form hydrophilic groups.
Japanese Patent No. 62,64,941 to Takei et al., published Mar. 24, 1987, describes enzyme-immobilized membranes for a sensor, in which high molecular weight substances are dissolved, the mixture spread and air dried, and soaked in a solvent in which the high molecular weight component is insoluble, for enzyme immobilization. Japanese Patent No. 63,263,460 to Mitsumata et al., published Oct. 31, 1988, describes an immunoassay method using an enzyme immunosensor electrode, in which an electrode containing immobilized antibody is inserted into an electrolyte solution, enzyme-labelled antigen and a test antigen are added for competitive reaction with antibody, and instantaneous current or potential changes measured for detection of the antigen. European Patent No. 302,661 to Vadgama et al., published Feb. 8, 1989, describes a supported liquid membrane enzyme electrode sensor for analyte determination.
Biosensors incorporating electrochemical detection with adsorbed, deposited, or embedded receptor agents on an electrode are exemplified in the following U.S. and foreign patents: U.S. Pat. No. 4,634,599; U.S. Pat. No. 4,661,442; JP 63,153,462; JP 63,206,652; JP 01,59,058; EP 304,447; WO 87,03,095; WO 88,08,972; WO 88,09,499; and WO 88,09,808. In these systems, analyte detection is typically followed by a change in electrical potential or current at an electrode surface. Sensitivity and selectivity for specific analytes depend on the nature of the materials used on the electrode, and have limited the applicability of these devices.
Japanese Patent No. 63,153,462 to Takei et al., published Jun. 25, 1988, describes a sensitive field effect transistor biosensor containing an aluminum gate-immobilized biological substance. European Patent No. 304,947 to Kagayama, published Mar. 1, 1989, describes a biosensor containing immobilized physiologically active substance and transducer, comprising a pair of opposing flat plates between which an antibody, with antigen or enzymes immobilized onto one surface and a transducing chemical substance on the other surface.
PCT International Application No. WO 88,08,972 to Cheung et al., published Nov. 17, 1988, describes a biosensor comprising a reversibly selective binding protein immobilized upon the insulated gate region of a field effect transistor on the sensor. PCT International Application No. WO 88,09,808 to Taylor and Marenchic, published Dec. 15, 1988, describes receptor-based biosensors and a method of immobilizing and stabilizing an active biological receptor in a polymeric film onto an electrode. PCT International Application No. WO 88,09,499 to Newman, published Dec. 1, 1988, describes an optimized capacitive sensor for chemical analysis, which relies on biospecific binding between a biochemical binding system and the analyte of interest to change the dielectric properties of a capacitive affinity sensor.
Japanese Patent No. 01,59,058 to Kuriyama, published Mar. 6, 1989, describes an enzyme immunosensor and its use in enzyme immunoassay, consisting of a semiconductor ion sensor, a spacer, and plate containing immobilized antigen or antibody. French Patent 2,614,422 to Liston et al., published Oct. 28, 1988, describes an enzyme electrode and module for determination of analytes in physiological fluids, comprising a membrane chamber and composite layered membrane, an electrode element in contact with the membrane, a flow sampler connected with the membrane chamber, a wash cell and a sample container, and means for intermittent transfer of sample and sample and other solutions. German Patent No. 3,226,045 to Seshimoto et al., published Jan. 20, 1983, describes film-like ion selective electrodes comprised of a conductive layer adjacent to an ion-selective layer, and their use for body fluid analysis.
PCT International Application No. WO 87,03,095 to Newman, published May 21, 1987, describes a capacitive affinity sensor and method for chemical analysis and measurement, comprising an open capacitor which produces a higher electric field in one volumetric region and a lower field in a second region, a biospecific binding agent for the analyte localized on the surface between the conductors in the first region, and a means associated with the capacitor which responds to the average dielectric constant in the first chamber. U.S. Pat. No. 4,634,599, to Uzgiris, issued Jan. 6, 1987, describes a method for making ordered monolayers of macromolecules on supported lipid polylayers, for two-dimensional crystallization of macromolecules for imaging in electron microscopy. U.S. Pat. No. 4,661,442, to Lukens, issued Apr. 28, 1987, describes a process for preparing lipid-protein membranes for chemical detection, comprising an aqueous medium containing emulsified lipid and protein, applying the medium to an orifice, and evaporating the water to provide a stable membrane.
Membrane electrode biosensors incorporating oxidative probes, such as those used to detect glucose in blood, are exemplified in the following patents: FR 2,614,422; EP 248,680; JP 62,85,853; JP 01,59,055; JP 01,60,382. In these systems, a Clark-type oxygen sensing electrode is typically coupled to an oxidative enzyme such as glucose oxidase, in order to permit analysis of the desired biological parameter. Among other factors, synthetic membranes used in said systems vary in composition among the biosensor devices.
Japanese Patent No. 01,60,382 to Asakura, published Mar. 7, 1989, describes the manufacture of a fibroin-enzyme membrane and its use in an enzyme sensor. Japanese Patent No. 01,59,055 to Suetsugu et al., Mar. 6, 1989, describes water-absorbing layers in biosensors, for electrochemical detection of substances based on a reaction with a redox enzyme and an electron acceptor. Japanese Patent No. 62,85,853 to Miyai and Asano, published Apr. 20, 1987, describes a membrane for an enzyme electrode, comprised of an enzyme such as glucose oxidase immobilized on a fine powder carrier and supported with a membrane having a fractionating molecular weight capable of passing the protein molecule of the immobilized enzyme.
European Patent No. 248,680 to Reinhart et al., published Dec. 9, 1987, describes a noninvasive electrochemical apparatus and method for determining blood glucose, comprising a membrane means for containing glucose oxidase, means for providing oxygen to the membrane, and means for measuring the hydrogen peroxide product in the membrane.
Sensors using gated membrane electrodes, in which a reactive material for the analyte of interest is included in a membrane whose permeability changes upon reaction with the analyte, are exemplified in the following U.S. and foreign patents: U.S. Pat. No. 4,637,861; U.S. Pat. No. 4,776,944; and EP 261,887. Their sensitivity and selectivity are determined by the gated membrane composition, and can limit the types of agents which one can analyze by these methods. Activity of the gate material in prior art membranes can be strongly influenced by subtle physical changes in the membrane. For example, Krull, U. J., M. Thompson, E. T. Vandenberg, and H. E. Wong (1985) "Langmuir Blodgett Film Characteristics and Phospholipid Membrane Ion Conduction, " Analytica Chimica Acta 174: 83-94; 95-102, describe packing density effects and capacitance measurements on electrodes with phospholipid membranes. Other influences include regulatory substances. For example Montal, M. P. Labarca, D. R. Fredkin, B. A. Suarez-Isla, and J. Lindstrom (1984) "Acetylcholine Receptor from Torpedo californica Reconstituted in Planar Lipid Bilayer Membranes," Biophysical J. 45: 165-174, describe effects of bungarotoxin and other ion channel modulating toxins in phospholipid membranes. See also Krueger, B. K., J. F. Worley, and R. J. French (1986) "Block of Sodium Channels in Planar Lipid Membranes by Guanidinium Toxins and Calcium: Are the Mechanisms of Voltage Dependence the Same?" Annals of the New York Academy of Sciences 479: 257-268).
Caras and Janata, "Enzymatically Sensitive Field Effect Transistors," Methods in Enzymology, Volume 137: pages 247-255, 1988, describes the design, fabrication, principles of operation, applications and theoretical limitations of enzymatically coupled field effect transistors as solid state biosensors.

Thin membrane sensor with biochemical switch


A method for producing a small feature in a semiconductor device includes depositing a mask material on an unpatterned layer in which an ultra-narrow opening is to be formed, and then masking and etching the mask material to form a narrow opening. A spacer material is then deposited on the mask material, with spacer material settling into and covering the narrow opening. Thereafter, a portion of the spacer material is removed by etching, leaving some spacer material in the opening but exposing an ultra-narrow region of the first layer at the bottom of the opening in the mask material. The ultra-narrow region left uncovered by the spacer material is smaller than the narrow region in the mask material. Once the ultra-narrow region is uncovered, material in the first layer is removed through the ultra-narrow region, by anisotropic etching, for example, to form an ultra-narrow opening in the first layer.

In fabrication of semiconductor devices, increasing device density on a given die area provides significant advantages, including speed, power efficiency, and portability. To produce very fine resolution, very small device features and very small circuits are generated by a process of epitaxy, lithography, and etching. In typical processes, layers are deposited on the surface of a substrate and then masked and etched to a predetermined thickness. Lines of a material are then formed by depositing a layer of the material and then masking and etching away the material to form spaces where the layer is not desired. Depositing, masking and etching layers of substrate material allows the fabrication of very small semiconductor substrate features. However, because of uncertainties in the original thickness of a layer and uncertainties in etch rate, trace amounts of the material are occasionally left on the substrate. When the material is a conductor, for example, metal, the trace amounts of material often cause short circuits between the lines. Damascene techniques avoid this problem by depositing an insulating layer, forming trenches in the insulating layer, and then depositing the metal or other material within the trenches.
Damascene trenches are frequently formed by photolithographic patterning of the insulating layer, to achieve trench dimensions as small as possible. Photolithography produces very fine resolution on a substrate, but the resolution is limited by the particular wavelength used. But manufacturing constraints associated with the technologies capable of producing extremely high resolution, and in particular fine and closely spaced lines, hamper development of dies having greater device density. Damascene techniques therefore suffer from the same wavelength-dependent size limitations as other approaches to die manufacture. For deep-UV frequencies, each frequency carries a feature size limitation.
Presently, Deep-UV wavelengths are commonly used for fine-resolution lithography, and are considered state of the art. The E, G. H. and I lines of the deep-UV wavelengths are as short as 365 nm, which prevents the easy processing of a feature size finer than 248 nm (2480 .ANG.). Switching to a higher frequency would theoretically allow greater density, but would be prohibitively expensive due to a consequent need to develop new equipment, fabrication techniques, or resists appropriate to the shorter wavelengths, and the need to make presently available methods at the shorter wavelengths cost effective.
Some approaches to reducing feature size without switching to a higher frequency have been attempted. For example, phase-controlled interference patterns have been used with some success. These techniques place layers that are phase-shifting and transparent to the particular wavelength over (or under) some areas on a mask before exposing the mask, thus generating and positioning points of constructive and destructive interference on photoresistive materials. In addition to adding, large expense, these methods require broader areas of the device substrate to be exposed simultaneously, and the patterns desired must be highly repetitive for these methods to be appropriate. The added expense comes, in part, from the need to use materials and technologies matched to the resist and to the wavelength, and the material is difficult to align. Also, adjacent areas of constructive interference are often seen as a single large region, and are not resolved in some cases.

Method for producing semiconductor devices with small contacts, vias, or damascene trenches


A communications apparatus and method are provided. The communications method for an apparatus capable of Carrier Aggregation (CA), wherein the apparatus includes a plurality of processing engines and antennas, includes the steps of determining whether the apparatus is configured in a single component carrier for a first group of the antennas; and activating a second group of the antennas if the apparatus is configured in the single component carrier.

Field of the Invention
The invention generally relates to a communications method and apparatus, and more particularly, to a method to configure additional antennas in single component carrier situation.
Description of the Related Art
Wireless communications systems are widely deployed to provide various telecommunications services such as telephony, video, data, messaging, and broadcast. Typical wireless communications systems may employ multiple-access technologies capable of supporting communications with multiple users by sharing available system resources (e.g., bandwidth, transmitting power). Examples of such multiple-access technologies include code division multiple access (CDMA) systems, time division multiple access (TDMA) systems, frequency division multiple access (FDMA) systems, orthogonal frequency division multiple access (OFDMA) systems, single-carrier frequency divisional multiple access (SC-FDMA) systems, and time division synchronous code division multiple access (TD-SCDMA) systems.
Carrier Aggregation (CA) improves the data rate of user equipment (UE) by aggregating multiple component carriers for parallel transmission and reception. Carrier aggregation may be enhanced by allowing different Time Division Duplex (TDD) uplink (UL)-downlink (DL) configuration for inter-band carrier aggregation. With such an enhancement, the system can coexist well with the current 3G network and make deployment targeting for different needs easier.
Component carriers may be divided into a primary component carrier (PCC) and a secondary component carrier (SCC). The PCC refers to a carrier that is constantly activated, and the SCC refers to a carrier that may be activated or deactivated according to particular conditions. Activation means that transmission or reception of traffic data may be performed or traffic data is ready for its transmission or reception on the concerned component carrier. Deactivation means that transmission or reception of traffic data is not permitted on the concerned component carrier. The user equipment uses only a single PCC or one or more SCCs along with the PCC.
FIG. 1 is a block diagram of a receiver (or user equipment) in traditional Carrier Aggregation (CA). In FIG. 1 the receiver comprises two antennas R1-R2 and a plurality of processing engines such as Radio Frequency (RF)/Analog Front End (AFE) modules, Digital Front End (DFE) modules, Fast Fourier Transform (FFT) modules, Multiple Input Multiple Output (MIMO) Pre-processors, MIMO detectors and Bit Rate Processing (BRP) modules. When the service network provides two component carriers (CCs) for the transmission of Carrier Aggregation, the upper part of processing engines are configured for one component carrier, and the lower part of the processing engines are configured for the other component carrier. However, when the service network only provide single component carrier (e.g. PCC) for the receiver, the processing engines configured for the other component carrier (e.g. SCC) will be in an idle mode. Therefore, the processing engines in the idle mode are not operating efficiently.

Communications method and apparatus for carrier aggregation


A system for producing a user-selective HD synthesis video, including: a camera device for providing data of an HD video captured for chroma-key synthesis; an audio device for providing HD audio data; and a system main body which receives the HD video data and the HD audio data from the camera device and the audio device, synthesizes, in real-time, the HD video data and the HD audio data with background video data or background image data selected by a user as an HD video using a chroma-key synthesis scheme, and selectively stores the HD synthesis video data in an external memory device.

As an Internet user environment has advanced, an image production field, which had been the province of specialists, has become increasingly common. A variety of internet sites which share video files based on the Internet are provided where users may upload, post, and share their video files.
There are a great variety of methods for producing videos, e.g., a method using high-priced technical equipment and a simple method using a smart phone. The video which is directly produced by a personal user is called a user created content (UCC) video. Personal users' desires to produce videos and expression methods are increasing, and the personal users' desires to express UCC video through image synthesis are also increasing.
A chroma-key synthesis scheme for video synthesis is a method in which a video is captured in a green or blue screen area, and a screen image is removed, and then another background is synthesized. High-priced technical equipment and skilled techniques for dealing with the equipment are required to synthesize two videos using the chroma-key synthesis scheme. Therefore, it is difficult for nonprofessional personal users in a video synthesis field to produce the UCC video through the video synthesis.
Meanwhile, a video file for individual use may be leaked online despite a user's intention, and thus personal privacy may be infringed. As an internet environment is generalized, personal privacy infringement comes to the fore as a serious social problem. Therefore, in the case of the personal UCC video produced in public places, it is necessary to prevent the UCC video from being leaked in despite the user's intention, thereby protecting the personal privacy.

System for producing user-selective HD synthesis video


The present invention relates to document formatting using input trees. A method (30) and apparatus (200) for creating a split tree is provided. Marks are assigned to an input tree, removing the need to split the input tree and allowing the input tree structure to remain intact. The advantage of preserving the original structure of the input tree is that it allows interactive formatting. A method (40) of creating tree fragments from the split tree is also provided.

High-level languages for document formatting exist in many forms, some of which accept as input a description of a document in the form of an input tree. An example of such an input tree is presented in FIG. 1. The input tree comprises two main types of elements, namely data elements and instruction elements, those elements in FIG. 1 being indicated in FIG. 2. The data elements contain data to be formatted. Each data element can include text or images. Instruction elements contain information used by a document formatter to arrange the data elements on pages when producing an output. As seen in FIG. 3, the data elements form leaf nodes in the tree whereas the instruction elements form nodes. Further, nodes A and B are child nodes of node Cat(2). The left node, Node A in the example, is defined as the first child of node Cat(2), whereas the right node, Node B, is defined as the second child node Cat(2).
Instruction elements can be thought of as operators that define the output positions of data elements. There are a number of instruction elements or operators available. Certain of the instruction elements, for example those defining text size, text spacing and the like, typically only have one child.
The other relevant instruction in FIGS. 1 to 3 is "Cat( )", which performs vertical concatenation. Each concatenation instruction places its left parameter (the first child) above its right parameter (second child). For example, Cat(2) would place the content of data element B below the content of data element A.
As an input, data elements do not have an actual position. The actual position of the data elements is determined by the document formatter by evaluating the input tree. In the example of FIG. 1, the formatter, following the directions given by the instruction elements, determines that the result of the Cat(2) operator is placed above the result of the Cat(3) operator. The Cat(2) operator in turn places the content of data element A above data element 13, and the Cat(3) operator places the content of data element C above data element D. The result is that data element A, B, C and D are stacked in that order.
However, when the content of data elements are placed on a page in order to produce an output, it is sometimes found that the result is too big to fit onto one page. Therefore, placing the content data elements onto the page following the order specified, should the content of a next data element not fit into the space left on the present page, the remainder of the data elements are promoted to a next page. In the example presented in FIG. 1, if only the content of data elements A, B and C can fit onto page 1, then the content of data element D is promoted to page 2. The formatter also positions the data elements on the pages. The result of the evaluation of the input tree is shown in FIG. 4.
To better explain the above, a galley and a galley target need to be defined. A galley is a part of the input tree, whereas a galley target is a placeholder for a galley. The galley is therefore not evaluated at a position in the input tree but rather at the point where it is placed into the galley target. The galley target is a stretchable area on the output area with size 0 when no galley is targeted into it. When a galley is targeted into a galley target, the galley target stretches to accommodate for the incoming galley. The galley is unable to stretch infinitely though. There are restrictions on the maximum size of each galley target. Should it happen that the galley target reaches its maximum size before the galley is exhausted, a new galley target is found for the remainder of the content of the galley and the process of accommodating the remainder of the galley into the new target is continued.
Placing a galley into a series of galley targets involves splitting the input tree into fragments, each fragment filling its target. FIG. 5 shows another example of a galley in the form of an input tree 500. It is assumed that the galley in the example of FIG. 5 is targeted into a sequence of targets, with only data elements A and B fitting into the first galley target in the sequence by taking all the available space defined by the restrictions on the first galley target. The rest of the galley is promoted to the following galley target in the sequence.
FIGS. 6A and 6B show the result after a portion of the galley of FIG. 5 is placed into the sequence of galley targets. The original input tree 500 shown in FIG. 5 is split into the two tree fragments 510 and 520 respectively. The first fragment 510, shown in FIG. 6A, is placed into the first galley target. The remainder of the galley which now resides in the second tree fragment 520, shown in FIG. 6B, is waiting to be placed into the following galley targets. Thus, the original galley was split into two separate smaller trees.
The arrangement described above is used in batch text formatters which produce an output from an input tree. However, this arrangement suffers from the disadvantage that once the galley is split into smaller trees, it is hard to relate the fragmented trees back to their original galley tree. This is for example necessary whenever the order or contents of the data elements are changed, thus preventing interactive formatting.


A two-part sizing composition that imparts improved resistance to hydrolysis of reinforced composites including a size composition and a binder composition is provided. The size composition may include one or more coupling agents, one or more lubricants, and at least one wetting agent. The binder composition may include a copolymer formed from maleic anhydride and at least one other copolymerizable monomer, at least one crosslinking agent, and a surfactant or mixture of surfactants. In at least one exemplary embodiment, the maleic anhydride copolymer is a maleic anhydride-butadiene copolymer partial ammonium salt. The size composition may be applied to a reinforcing fiber material before the binder size material is applied. The two-part size composition may be applied to a reinforcing fiber material to form a reinforcing fiber product which may then be densified or compacted to form a densified reinforcing fiber product, such as a pellet.

Glass fibers are useful in a variety of technologies. For example, glass fibers are commonly used as reinforcements in polymer matrices to form glass fiber reinforced plastics or composites. Glass fibers have been used in the form of continuous or chopped filaments, strands, rovings, woven fabrics, nonwoven fabrics, meshes, and scrims to reinforce polymers. It is known in the art that glass fiber reinforced polymer composites possess higher mechanical properties compared to unreinforced polymer composites, provided that the reinforcement fiber surface is suitably modified by a sizing composition. Thus, better dimensional stability, tensile strength and modulus, flexural strength and modulus, impact resistance, and creep resistance may be achieved with glass fiber reinforced composites.
Chopped glass fibers are commonly used as reinforcement materials in reinforced composites. Conventionally, glass fibers are formed by attenuating streams of a molten glass material from a bushing or orifice. The glass fibers may be attenuated by a winder which collects gathered filaments into a package or by rollers which pull the fibers before they are collected and chopped. An aqueous sizing composition, or chemical treatment, is typically applied to the fibers after they are drawn from the bushing. After the fibers are treated with the aqueous sizing composition, they may be dried in a package or chopped strand form.
Chopped strand segments may be mixed with a polymeric resin and supplied to a compression- or injection-molding machine to be formed into glass fiber reinforced composites. Typically, the chopped strand segments are mixed with pellets of a thermoplastic polymer resin in an extruder. In one conventional method, polymer pellets are fed into a first port of a twin screw extruder and the chopped glass fibers are fed into a second port of the extruder with the melted polymer to form a fiber/resin mixture. Alternatively, the polymer pellets and chopped strand segments are dry mixed and fed together into a single screw extruder where the resin is melted, the integrity of the glass fiber strands is destroyed, and the fiber strands are dispersed throughout the molten resin to form a fiber/resin mixture. Next, the fiber/resin mixture is degassed and formed into pellets. The dry fiber strand/resin dispersion pellets are then fed to a molding machine and formed into molded composite articles that have a substantially homogeneous dispersion of glass fiber strands throughout the composite article.
Unfortunately, chopped glass fibers are often bulky and do not flow well in automated equipment. As a result, the chopped fiber strands may be compacted into rod-shaped bundles or pellets to improve their flowability and to enable the use of automated equipment, such as, for example, for transporting the pellets and mixing the pellets with the polymer resins. U.S. Pat. No. 5,578,535 to Hill et al. discloses glass fiber pellets that are from about 20 to 30% denser than the individual glass strands from which they are made, and approximately 5 to 15 times larger in diameter. These pellets are prepared by hydrating cut fiber strand segments to a hydration level sufficient to prevent separation of the fiber strand segments into individual filaments but insufficient to cause the fiber strand segments to agglomerate into a clump. The hydrated strand segments are then mixed for a period of time sufficient for the strand segments to form pellets. Suitable mixing methods include processes that keep the fibers moving over and around one another, such as by tumbling, agitating, blending, commingling, stirring and/or intermingling the fibers.
Sizing compositions, such as are used in reinforced composites, are well-known in the art and conventionally include a film forming polymeric or resinous component, a coupling agent, and a lubricant. A sizing composition is typically added to glass fibers to reduce interfilament abrasion and to make the glass fibers compatible with the polymeric matrices they are intended to reinforce. The sizing composition also ensures the integrity of the strands of glass fibers, e.g., the interconnection of the glass filaments that form the strand.
One fundamental problem associated with conventional sizing compositions used in reinforced composites is the aging of the polymer matrix composite under the action of hydrolysis, which results in a decrease in mechanical strength. For example, hydrolysis of polyamide composites reduces tensile strength, elongation at break, and Charpy un-notched impact strength. Hydrolysis is a particular problem in areas where there is a significant amount of water present, such as in water end caps of radiators for automobiles. Thus, there exists a need in the art for a sizing composition that confers improved hydrolysis resistance to glass reinforced composites under extreme hydrolysis conditions.

Hydrolization resistant sizing composition