A separate cacheable-in-virtual-cache attribute bit (CV) is maintained for each page of memory in the translation table maintained by the operating system. The CV bit indicates whether the memory addresses on the page to which the translation table entry refers are cacheable in virtually indexed caches. According to a first embodiment, when there are two or more aliases which are not offset by multiples of the virtual cache size, all of the aliases are made non-cacheable in virtually indexed caches by deasserting the CV bits for all aliases. With regards to the contents of the translation lookaside buffer (TLB), the translations for all aliases may simultaneously coexist in the TLB because no software intervention is required to insure data coherency between the aliases. According to second and third embodiments of the present invention, when there are two or more aliases which are not offset by multiples of the virtual cache size, only one of those aliases may remain cacheable in virtual caches. For the other aliases, the CV bits for the translation pages containing those aliases are deasserted. The operating system has the responsibility of flushing data from the virtually indexed internal cache before deasserting the CV attribute for a page. The second embodiment allows the newer mapping to a physical address to remain in the first-level cache, while the third embodiment allows the older alias to remain in the first-level cache when a newer alias is mapped.

1. Field of the Invention
The present invention relates to processors having multi-level memory systems, and specifically to aliasing in the presence of virtually-indexed caches.
2. Discussion of the Prior Art
Using multi-level memory systems is a general technique for exploiting locality of reference. The basic idea is to organize a small amount of fast access memory and a large amount of slower access memory so that most of the accesses go to the small, fast memory. The average access time of such a memory system may be only slightly greater than that of the small, fast memory, while its effective size is that of the large memory.
A common form of multi-level memory system is cache memory, or lookaside buffer memory. As illustrated in FIG. 1, a cache memory 10 is a relatively small, specialized memory device placed between the processor 11 and main memory 12. The cache memory 10 holds copies of words from main memory 12 that are likely to be accessed by the processor. The cache 10 is faster than main memory 12; thus if frequently accessed locations are found in the cache 10, the cache hit rate will be high and the average memory access time will be small. The strategy followed by the cache 10 is to hold words located near other words recently used by the processor. The locality of reference exploited by this strategy is the propensity of memory accesses, over short periods of time, to cluster in small regions of memory.
Cache memory locations are redundant, in the sense that each is used to provide a more accessible copy of information also stored in slower main memory 12. Thus the total addressable memory size, as seen by the programmer, is not increased by the presence of a cache 10. Rather, the cache 10 provides, in a program transparent way, an improvement in the average access time to locations in the same address space.
As the cache 10 is much smaller than main memory 12, only a minority of the main memory locations can be cached at any one time. Consequently, in the general case each location in the cache 10, or cache line, conceptually has two parts--a tag field and a contents field. When a read or write operation is requested, the desired address is compared with the tag field of certain lines of the cache. If a match is found, the contents field of the cache line containing the matching tag is read or written. This is known as a cache hit, and there is no need to access main memory.
Modern processors support virtual address space, which is conceptually distinct from physical address space. A virtual address is a label that the processor uses to specify a memory location. The processor is not concerned with where that memory location actually resides in the physical memory, so long as the processor is able to access the location with the virtual address. A processor architecture specification defines a certain virtual address space which must be supported. The operating system that manages the computer system has flexibility as to how that virtual address space is mapped to physical memory. Thus, there is a translation that must occur from virtual to physical address.
FIG. 2 illustrates a typical virtual to physical translation. Both virtual and physical memory is conceptually separated into pages. The virtual address 20 of a memory location, for instance, consists of a virtual page number 21 and a page offset index 22. The virtual page number 21 indicates on which page of memory the specified memory location resides. The page offset index 22 represents where the desired memory location is within the boundaries of its page. Thus, the page offset index 22 dictates the location relative to the beginning of the page. Physical addresses are also constructed in the same fashion. A physical page number 23 and a page offset index 24 define a physical memory address 25. By convention, most implementations of a virtual address space happen to index memory within each page in the same manner for the virtual and physical addresses. Thus, the page offset indexes 22 and 24 are the same for the virtual address 20 and corresponding physical address 25 of a memory location. Therefore, if the page size is 2.sup.p, the low order p bits of the virtual and corresponding physical address of a memory location are equal and represent the page offset index.
In the process of translating from a virtual address 20 to a physical address 23, since the virtual page offset 22 is the same as the physical page offset 24, the page offset portion of the virtual address does not need translation. However, the physical page number 23 is not the same as the virtual page number 21, and thus the virtual page number 21 must be translated. A memory management unit 26, which typically is implemented in a combination of hardware (translation lookaside buffers) and software (table walking), performs this virtual to physical page translation.
FIG. 3 illustrates the operation of a non-associative or direct mapped cache. The direct mapped cache uses the low-order bits 30 of the incoming memory address 31 to dictate the address within the cache to examine for a hit. Thus, a memory location A can only reside in the cache line whose address within the cache is represented by the low k bits 30 of the address of A. While constraining a memory address 31 to be cached in only one specific line within the cache is a serious limitation, it allows the use of cheaper and denser standard Random Access Memory (RAM) rather than associative memory. The constraint implies, however, that memory locations which share the same k low-order address bits 30 also share the same cache line. If each cache line only provides for the storage of the contents of one memory location, then two memory locations with the same low order k address bits 30 cannot be cached simultaneously, since they contend for the same cache line. Another important and attractive characteristic of a direct-mapped cache is that it tends to operate faster given that it is simpler and require less circuitry.
Most processor architecture specifications support aliases among the virtual addresses. Two virtual addresses which refer to the same physical address are aliases of each other. The low order p bits of the virtual address of any given memory location represent the page offset from the beginning of the virtual page. The page offset index for any given virtual address is equal to the page offset index of the physical address. Therefore, if two addresses are aliases of each other, their low order p bits must be equal, since they both refer to the same physical address. However, the bits which represent the virtual page numbers of the two aliases are different.
For the purposes of this discussion, the possible cache organizations are: virtually or physically indexed, virtually or physically tagged, and direct-mapped or set-associative. In a processor which supports virtual addresses, some of the caches in that processor may be virtually indexed direct mapped caches, while other caches are physically indexed direct mapped caches. A virtually indexed direct mapped cache uses the virtual address to provide the cache line mapping, while a physically indexed direct mapped cache uses the physical address to provide the cache line mapping. Thus, in a virtually indexed cache, if the number of cache lines is 2.sup.k, then the low order k bits of the virtual address are used to map to the cache line for that virtual address.
If the number of cache locations is equal to or smaller than the number of locations in a page, there is no distinction between a virtually indexed and a physically indexed cache, since the low order p bits of the physical address and its corresponding virtual address are the same. In that case, when k is less than or equal to p, all aliases will map to the same cache line, since the low order k bits used to map to the cache line are all equal. However, if the cache size is larger than 2.sup.p, the virtually indexed caches and physically indexed caches will produce different cache line mappings for the same memory location, since some of the virtual page bits or physical page bits are used to derive the cache line. Moreover, in a virtually indexed cache, aliases may map to different cache lines within the same cache. In a virtually indexed cache when the page size is less than the cache size, one or more of the virtual page bits are used to provide the cache line mapping. Since the virtual pages of the aliases are different, the virtual page bits of the virtual addresses are different. Thus, the cache lines may be different, since one or more of the low order virtual page number bits must be used to map into a cache line.
For example, if a virtually indexed cache has 2.sup.14 lines, and the physical page size is only 2.sup.12, then any given physical memory location could have as many as four aliases which all mapped to different cache lines. This is a consequence of the fact that two of the virtual page number bits must be used to provide the mapping into the cache. Since there are four possible values which could be represented by the two bits, the aliases could map to any of four different locations depending upon their low order two virtual page number bits.
When two or more virtual addresses map to the same physical address, data written to one of those virtual addresses should be visible upon subsequently reading from any of the aliases. If all the aliases map to the same cache lines, virtually indexed caches behave as expected. Data written to any one of the aliases will be written to the same cache line. However, significant data inconsistency problems occur if the aliases map to the different cache lines. If two virtual aliases map to different cache lines of a virtually addressed cache, each alias behaves as if it were its own independent variable. For example, if X and Y are virtual address aliases, and if a store to X is performed, that data would not be visible during a subsequent read of Y if Y were also resident in the cache. Furthermore, the value in Y remains unchanged by the write to X, whereas it should have been destroyed. When X and Y are removed from the cache, each will be written into the physical memory location to which they both refer. Assuming that the cache was a write back cache (rather than write through), the value which exists in the physical main memory after both X and Y are removed from the cache will depend upon which virtual address was removed from the cache last. Thus, if Y is removed last, the data written to X is destroyed while the stale data at Y incorrectly occupies the physical location in main memory.
In order to maintain data consistency, one prior art approach required that all of the virtual aliases be made non-cacheable; not even one of the aliases could remain in a cache. A serious performance degradation results from this prior art approach, since any references to any of the aliases cannot derive any benefit from the first-level or second-level caches, and must access main memory, which is the slowest level of memory.
FIG. 4 shows the structure of the cache and address translation mechanisms. The operating system maintains translation information in an arbitrary data structure, called the software translation table 40. Translation lookaside buffers provide quick hardware translations, and are essentially caches of the large and complex software translation table. For each cache, a translation lookaside buffer (TLB) 41 exists which acts as an independent cache of the software translation table 40. For more frequently accessed virtual pages, the TLB provides a one-cycle translation. The term "TLB hit" means that the desired translation is present in the on-chip TLB. The term "TLB miss" means that the desired translation is not present in the on-chip TLB.
On a TLB miss the memory management unit immediately traps to software for TLB miss processing. The TLB miss handler software routine has the option of filling the TLB by any means available. Some memory management units include an intermediate translation device, such as the translation storage buffer 42 shown in FIG. 4. The translation storage buffer acts like a second-level cache of address translations. While the TLBs are small and fast, the software translation table is likely to be large and complex. Thus, when the TLB miss handler operating system software routine is invoked after a TLB miss, a significant number of cycles may occur before the virtual to physical translation can be retrieved and processing can continue.
A second prior art approach involves allowing one virtual alias to stay in the caches, but requiring the others to be excluded from caches and from the TLB. Allowing one alias to remain cacheable offers some benefits over the previous approach of making all aliases non-cacheable. If one alias remains cacheable, then repeated accesses to that alias still derive benefit from the quickness of the cache and TLB entry for that address.
For example, if X and Y are aliases, X can remain in the cache and its translation can remain in the TLB. However, Y must be made non-cacheable. If X is referenced repeatedly without any references to Y, then some benefit of the cache is retained. However, when Y is referenced, a TLB miss will occur. To insure correct operation, before putting Y into the cache or including Y's translation in the TLB, the operating system must remove X from the cache and remove X's translation from the TLB. If X's translation were not removed from the TLB, no TLB miss would occur the next time a reference to X occurred. When X was again referenced, without software intervention, it would again be entered in the cache, unacceptably coexistent with Y.
The concept of cacheable address attributes is known in the prior art. A cacheable address attribute is a logical designation associated with a portion of memory which indicates whether data from that portion of memory can or cannot be placed into a cache. Cacheable address attributes are typically used to disallow the caching of memory mapped input or output locations. Most processor architectures support interfaces with input/output devices as being mapped to a certain part of the physical address space. For example, the mouse in a computer system may be mapped to a certain memory location. To keep up with what is happening with the mouse, the processor will periodically read from the address to which the mouse is mapped as if it were just another memory location. Similarly, when the processor wants to write data to a disk drive, for example, it writes to a special memory location dedicated to that output device. Caching those input/output locations is not permitted. A write to the output device is intended to reach the output terminals, not merely an internal cache which is only accessible to the processor. Similarly, a read from an input device is intended to read from the input device itself, not merely a cached version of what previously had been existent on the terminals of the input device.
An important problem with the approach of making aliases which violate the alias restriction non-cacheable is the possibility of having to deal with non-cacheable accesses to main memory. These accesses complicate many specialized instructions, such as "compare and swap" (CAS) and "partial store" (PST). It is very difficult to make these instructions work properly if they have to access non-cacheable main memory. Hence, there is a great benefit in developing a strategy where main memory can always be cacheable at least in physically indexed caches. The performance benefits which result from such a strategy, are additional added incentives.

Cachability attributes of virtual addresses for optimizing performance of virtually and physically indexed caches in maintaining multiply aliased physical addresses


The present disclosure provides various arrangements of a pixel defining layer. The pixel defining layer includes first and second sub-defining layers sequentially and laminatedly disposed on a base substrate. An orthographic projection of the second sub-defining layer less closer to the base substrate on the base substrate is located within an orthographic projection of the first sub-defining layer closer to the base substrate on the base substrate. A surface of each of the first and second sub-defining layers parallel to a surface of the base substrate is a lyophobic surface, a side surface of each of the first and second sub-defining layers is a lyophilic surface.

An organic light-emitting diode (OLED) display panel includes an anode, an organic light emitting layer, a cathode, and the like. The organic light emitting layer includes a hole injection layer, a hole transport layer, an organic light emitting material layer, an electron transport layer, an electron injection layer, and the like. The organic light emitting layer can be manufactured using an inkjet printing technique. When the organic light emitting layer is manufactured by using the inkjet printing technique, a pixel defining layer is formed on the glass substrate, and then a solution dissolving a material of the organic light emitting layer is sprayed onto a glass substrate on which a pixel defining layer is formed, to form an organic light emitting layer.
It should be noted that the information disclosed in the Background section above is only for enhancing the understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Pixel defining layer and manufacturing method thereof, display substrate, display panel


Quinazoline derivatives represented by general formula (1) and quinazoline complexes as protein kinase inhibitors, and their preparation methods are provided. Wherein, in general formula (1), at least one of R and R′ is a group containing an atom capable of coordinating with noble metals, m and n are either the same or different and are integers from 0 to 5. Said quinazoline complex as protein kinase inhibitor is formed by coordination compound containing noble metal and said quinazoline derivative ligand capable of coordinating with noble metal in the coordination compound. Used as tyrosine protein kinase inhibitors, Quinazoline derivatives and quinazoline complexes as protein kinase inhibitors provided by the present invention have exhibited good inhibitory effect on proliferation of various tumor cells including human breast cancer cells line (drug-resistant) MCF-7/A, human breast cancer cell line (sensitive) MCF-7/S, prostate cancer cell PC-3, keratinocytes Colo-16, human non-small cell lung cancer cell line A549, etc.

Anti-tumor chemical drugs used clinically include two major categories, cytotoxic drugs and molecular targeted drugs. Cytotoxic anti-tumor drugs (such as cisplatin, etc.) are all non-specific, while inhibiting and destructing abnormal proliferating tumor cells, they also cause inhibition and killing effect to other normal cells which proliferate rapidly. The side effects arising from this as well as congenital or acquired drug resistance of tumor cells to drugs have been a bottleneck restricting the clinical application of cytotoxic chemotherapy drugs. Over the past decade, highly selective molecular targeted therapeutic drugs against specific proliferation, differentiation and apoptosis mechanisms of tumor cell have developed rapidly. However, many small molecule compounds with good inhibitory activity on the protein kinases that are highly expressed in tumor cells may not be clinically used due to the poor water solubility or severe toxicity side effects, as well as easy to produce drug resistance.

Quinazoline derivatives and quinazoline complex protein kinase inhibitor for inhibiting multiplication of tumor cells and preparation method thereof

INSTITUTE OF CHEMISTRY, CHINESE ACADEMY OF SCIENCES


A process for forming a nanoparticle composition is provided. The process includes polymerizing conjugated diene monomer in a hydrocarbon solvent to form a first reaction mixture, and charging excess alkenylbenzense monomer and anionic catalyst to form mono-block and diblock polymers. Micelles of said mono-block and diblock polymers are formed, and at least one crosslinking agent is added to cross-link the micelles and form nanoparticles. The nanoparticles preferably have a poly(alkenylbenzene) core and an outer layer including monomer units selected from the group consisting of conjugated dienes, alkenylbenzenes, alkylenes, and mixtures thereof, and a size distribution of between about 1 and 1000 nm.

The present invention relates to polymer nanoparticles, methods for their preparation, and their use as, for example, additives for rubber, and particularly, tire compositions. The invention advantageously provides mechanisms for surface modifications, functionalization, and general characteristic tailoring to improve performance in various polymer compositions.
Polymer nanoparticles have attracted increased attention over the past several years in a variety of fields including catalysis, combinatorial chemistry, protein supports, magnets, and photonic crystals. Similarly, vinyl aromatic (e.g. polystyrene) microparticles have been prepared for use as a reference standard in the calibration of various instruments, in medical research and in medical diagnostic tests. Such polystyrene nanoparticles have been prepared by anionic dispersion polymerization and emulsion polymerization. However, controlling the size of nanoparticles during polymerization and/or the surface characteristics of such nanoparticles can be difficult.
Rubbers may be advantageously modified by the addition of various polymer compositions. The physical properties of rubber moldability and tenacity are often improved through such modifications. Of course, however, the simple indiscriminate addition of nanoparticles to rubber is likely to cause degradation of the matrix material, i.e., the rubber. Nonetheless, it is expected that the selection of nanoparticles having suitable size, material composition, and surface chemistry, etc., will improve the matrix characteristics.
In this regard, development of nanoparticles having a outer layer which would be compatible with a wide variety of matrix materials is desirable because discrete particles could likely disperse evenly throughout the host to provide a uniform matrix composition. However, the development of a process capable of reliably producing acceptable nanoparticles has been a challenging endeavor. For example, the solubility of various monomers in traditional alkane solvents has made solution polymerization a difficult process by which to achieve nanoparticles having a desirable outer layer. Moreover, the development of a solution polymerization process producing reliable nanoparticles, particularly nanoparticles advantageously employed in rubber compositions, has been elusive.
Commonly owned U.S. Pat. No. 6,437,050 is directed to polymer nanoparticles and a method of forming nanoparticles with desired surface characteristics and size. Commonly owned U.S. patent application Ser. No. 10/223,393 (filed Aug. 19, 2002) includes a method of controlling the surface characteristics of polymer nanoparticles via surface functionalization. Each of these is directed to the formation of nanoparticles having uniform sizes and each is herein incorporated by reference. In addition to the nanoparticles disclosed therein, it would be desirable to develop a process for forming polymer nanoparticles with a broad and controllable size distribution. It would also be desirable to develop a batch process for forming polymer nanoparticles with bimodal or trimodal size distributions.

This patent is subject to a terminal disclaimer.

Method of making nano-particles of selected size distribution


A system and method that determines building occupancy at a selected site by using geographically based structures to identify potential clients and to analyze aggregate carrier exposure levels at the selected site. This is achieved by using geographically based structures that are formed by geocoding business addresses and by linking all similarly geocoded businesses. Geographically based structures identify building characteristics and occupant related information. Specifically, all business addresses are address standardized, interjected with public protection code information and then geocoded. The geocoding information is used to identify and determine the building's occupancy configuration. For each tenant or occupant of the building, the system will initially display basic information that includes for example, business name, address and whether the business is currently insured by the carrier. The user can request additional information such as hazard concerns, safety issues and other occupant related information.

In the insurance industry, underwriters determine carrier exposure levels and insurance cost estimates based on where clients are located and their surrounding environment. It is particularly important to determine if a building occupied by a potential client has other tenants and if so, the underwriter must ascertain the business activities of these tenants to address potential liability ro exposure. Typically, an agent of the underwriter visually inspects each particular site to obtain the necessary information. A drawback of this method is that it is very inefficient and time consuming. Further disadvantages of this approach are that the information obtained may be inaccurate and incomplete.
Mapping applications provide the underwriters an alternative means for obtaining some of the information. However, mapping applications have a number of drawbacks. Mapping applications are typically used for geographically locating and identifying specified places or areas. However, the usefulness of these mapping applications is limited by their inability to easily identify all of the businesses located at a particular common site. A different business may be located depending upon the mapping application used for the query. A potentially insurable client, therefore, may have different identified tenants as a result of using different mapping applications. Inconsistent results affect risk exposure, insurance coverage and insurance premium costs for the client. Moreover, the fact that different occupants of the same building may utilize different addresses adds to this inconsistency.
In addition to being inefficient, inaccurate and inconsistent, a further drawback of the prior art methods is an inability to easily provide updated information reflecting changes in the occupancy of the building. For example, a chemical research company may initially have been a tenant in a potential client's building. Some time later, a convenience store may have replaced the chemical research company. The difference between the two businesses in terms of, for example, hazardous wastes and fire potential, greatly affects the insurance carrier's exposure level and in turn, the client's insurance premiums. Accurate and updated information would require the underwriter to inspect the site on a regular basis. The timeliness of the inspections would unduly affect the carrier's exposure and the client's costs. Accordingly, there is a need to provide a system and method that consistently provides accurate and updated building occupancy information for a selected site.

System and method for determining and analyzing building occupancy


A portable communication device and method of use is provided. In one embodiment, the method of using a handheld mobile telephone includes capturing a plurality of images via an image input device; storing the plurality of images in a memory, receiving a first speech input, identifying command information in said first speech input; retrieving information from memory based, at least in part, on the command information. The method may further include generating a request related to an article of commerce that includes, at least in part, the information retrieved from memory, determining a destination for transmitting the request, and wirelessly transmitting said request through a mobile telephone network to the destination.

The present invention relates to a system for providing transmissions relating to broadcast transmissions and methods of customizing and presenting the broadcast content in the form of audio, video, and text, to a viewer (i.e., a person). Until recently, radio and television were the two most common forms of presenting audio or audio and video to a viewer. However, in recent years, electronic transmissions over the Internet have become more and more widely used as a medium for presenting information to a viewer.
Television and traditional AM and FM band radio transmissions are unidirectional broadcasts of a one-to-many point transmission scheme. Most cable television stations and some digital television broadcasting companies include a unidirectional broadcast that can be viewed only by selected recipients. For example, viewers who subscribe to certain pay channels such as Showtime or Cinemax are able to view those channels, while viewers who do not subscribe to those channels cannot view those channels. In addition, viewers who desire to purchase a pay-per-view movie can telephone the broadcasting service (or through some other means indicate their desire) to purchase the movie and only those purchasers can view the movie. However, besides indicated the desire to purchase the movie or subscribe to a channel, viewers have few communications to the broadcaster and have very little control over the received information, the format and/or perspectives of viewing the information transmitted, the time of viewing, etc. In addition, traditional television and radio broadcasters transmit the same advertisements to all viewers irrespective as to the whether a viewer is likely to be a candidate interested in the advertised product.
The Internet provides a medium of communication that allows more bi-directional communication than previously available with traditional television and radio. For example, a viewer can select which web page to view from a selection of web pages and can view them in any order. When the broadcaster of the web page has implemented dynamic web pages, the viewer can also customize the web page to his or her preferences. For example, a web page can be retrieved that displays the viewer's stock portfolio. Since different viewers typically invest in different stocks, the web pages for different viewers vary accordingly. Thus, dynamic web pages have the capability of producing web pages that differ from viewer to viewer.
Chat rooms have also become increasingly popular as a forum for people of common interest to communicate by typing messages that are visible to other participants in the chat room in real-time. However, the information accessible to a potential participant of the chat room is usually limited to the participants' usernames (or screen names) and the title of the chat room. Similarly, email, list servers, and newsgroups have become other common methods of communication.
Direct marketing in the form of electronic transmissions (such as email or fax) is often used to invite participants to receive a broadcast of an auction, video presentation, a web site, or to get people to buy a product or service. Typically, the email addresses (or fax numbers) of a group of people who have a common interest (such as horse lovers, business opportunity seeks, investors, etc.) are rented or purchased from an email vender. The purchaser (or a bulk mail or fax service) will then email (or fax) an offer to all of the email addresses (or fax numbers) in hopes that at least a small percentage will respond favorably to the advertisement by purchasing the service or product or otherwise responding to the advertisement (e.g., by visiting the advertised web site). However, if the recipient of the transmission is not interested in the content of the transmission (e.g., the advertised product), the recipient will typically simply delete the email or discard the fax.
Print advertisements are also used to drive traffic to web sites. Often, however, the person reading the print ad is not also operating a computer to allow the individual to immediately access the web site if the individual desired to do so. Portable digital voice recorders have been developed that record a persons voice, which is stored for later retrieval. The most common use of voice recorders is to alleviate the need to write down information that the user wishes to remember. However, the user recording the voice message, or someone else, must still transcribe the voice message (e.g., web address or desire to purchase a product) and input that information manually into a web browser.
Many people enjoy gambling even though most people do no live near gambling establishments and people often travel great distances to participate in gambling. One alternative is online gaming, which is performed through software. Specifically, a computer program generates the order of cards in a virtual deck of cards that the user plays. The virtual cards are typically displayed in graphic form on the user's display. The computer generation of the virtual deck of cards and order of the cards (or other gaming device such as dice or roulette) is not, by many people, considered to be trustworthy and fair. In other words, many people do not trust virtual gaming in which a computer controls the device of chance (e.g., dice, cards, or roulette) and as a result, virtual gaming to date has only received limited acceptance in the general public.

Portable communication device and method of use


A bed sheet is made of: a material body with inner and outer surfaces configured to substantially cover a mattress. The sheet is provided with at least one pair of co-located pockets provided on the material body. The pockets are substantially rectangular and are placed one on top of the other. The outermost pocket has a height less than that of the inner pockets. The top edges of each pocket are open and slope in opposite direction to facilitate selective placement of objects in one pocket or the other.

a. Field of the Invention
The invention relates generally to a bed sheet with easily accessible side pockets. The bed sheet itself is a conventional fitted sheet having an elastic band circumferentially located on an outer perimeter of the bed sheet, and seams at the corners which form side panels. The pocket(s) are located on one or more side panels of the fitted sheet and designed for quick ingress and egress of objects from multiple closely located or co-located pockets.
b. Description of the Related Art
In the art there exists a variety of known bed sheets for mattresses. A sub-portion of these prior art bed sheets posses pockets and other similar mechanisms for the retention of objects. Prior art bed sheets with pockets use a variety of materials and means for securing the objects within the pocketed space.
Known prior art bed sheets are disclosed for example in U.S. Pat. No. 7,131,152 to Wootten et al., U.S. Pat. No. 6,684,422 to LeFevere et al., U.S. Design Pat. No. 471,049, U.S. Design Pat. No. 587,055, U.S. Design Pat. No. 537,286 and U.S. Design Pat. No. 481,899.
U.S. Pat. No. 7,131,152 to Wootten ("Wootten") is directed to a bed sheet with a side pocket. The pocketed bed sheet includes a fabric body to substantially cover a mattress and a pocket provided on the fabric body. The pocket includes a wall to hold objects in the pocket and a diagonal fabric edge that defines a diagonal opening at an angle relative to an edge of the fabric body. FIG. 3 of Wootten shows a typical fitted sheet with material sewn on the outer surface of the bed sheet (i.e., a patch pocket). The opening of the patch pocket is a diagonal fabric opening at an angle relative to an edge of the fabric body. The pocket described is roughly rectangular in shape. The Wootten patent explains that side edge 34 may extend approximately one-half the length of the entire height of pocket 12 as defined by side edge 36. The top edge 38 may extend approximately one-half the length of the entire width of pocket 12 as defined by bottom 40. Corners 42, 44 of edges 34, 38, respectively, form a diagonal opening 46 defined by edge 48. Alternatively, FIG. 4 depicts an embodiment of the pocket with an approximately semi-circle to form a partially enclosed compartment. The edge 52 "form[s] ends for diagonal opening 46." The Wootten patent, column 5, lines 3-8. As depicted in FIG. 4, the edge 52 begins along the top of the pocket at a point opposite a location about a third of the distance from a left bottom curve of the pocket. The edge 52 extends rightward from that point to then curve downward at a point about even with the right bottom corner of the pocket. The edge 52 continues downward and curves leftward to form a bottom of the pocket and returns upward to form the left end of the pocket. The Wootton patent describes that edge 48 of pockets 12, 12′ may include an elastic lining.
An obvious draw back of the pouches described by Wootton is that objects must be angled into a position matching the diagonal opening of the pocket. As such, ease of egress and ingress of objects is hampered by not only the pocket opening position, but placement of the pocket in general. More importantly, the designs of the pockets in Wootton prevent the use of multiple pockets that are co-located or serially located next to one another. It also makes it difficult to access the pockets if one is in a prone position on the bed.
Additionally, there is a need for others to access the pockets while not using it (i.e. while not in the prone position) on the bed. It is also necessary to have full access to the pocket interior for sanitary and observation reasons. The pockets as described in Wootton, fail to give total access to the interior of the pocket, The angled opening obscures the space directly adjacent to the opening. As such objects can not be located there if their dimensions exceed the pocket dimensions. Alternatively, if the objects are of small dimensions, a user may not be able to locate an object that has migrated to this space. Wootten thereby eliminates some of the usable pocket volume that it describes.
Another type of pocketed sheet is disclosed by U.S. Pat. No. 6,684,422 to LeFevere et al. ("LeFevere"). LeFevere is directed to an infant blanket that has mechanisms for attaching items to the blanket (e.g., small toys such as pacifiers, teethers, rattles) and describes two pockets 822, 823 sewn to the blanket for containing such items. LeFevere, column 6, lines 27-31; and FIG. 8. LeFevere, in FIG. 8 depicts each pocket being formed from an arcuate piece of material, where each pocket has one short side edge and an opposing, longer side edge. Each of the pockets 822, 823 is formed with an opening that extends at an angle from the upper end of the short side edge across the top of the pocket to the upper end of the opposing, longer side edge. Items can be placed into pockets 822, 823 at any angle from vertical to horizontal relative to the orientation of the pocket.
While the pocket sheet in LeFevere overcomes some of the drawbacks of the pouches disclosed by Wootton, the pockets of LeFevere still fail to point out multiple co-located pockets whose openings are angled so as to allow ease of ingress and egress as well as ease of locating specific pockets.
It would therefore be a benefit to provide a bed sheet having side pockets designed with substantially angled openings that are co-located with another opposite angled pocket opening, or parallel located next to one another. It would also be of benefit to provide these pockets on the side panels of a fitted bed sheet. It would further be of benefit to provide a wide variety of pocket types for various articles. It would additionally be of benefit to incorporate pocket types using gusseted sides and elastic rims so as to secure objects located within, all the while allowing the bed sheet profile to maintain as little external bulging as possible. It would also be of benefit to proved pockets where in the maximum usable space is available for item storage. Additionally, it would be of benefit to provide pockets designed so as to allow a user to access a specific pocket in a grouping of pockets from both a vertical or prone position.


A hull robot includes a turbine subsystem actuatable by fluid moving past the hull, a drive subsystem for maneuvering the robot about the hull, and an adjustment subsystem for either the turbine subsystem or the drive subsystem. A controller is configured to operate the adjustment subsystem to adjust the position of the turret subsystem relative to the drive subsystem until fluid flowing past the hull results in an optimal flow of fluid with respect to the turbine subsystem.

Co-pending U.S. patent application Ser. No. 12/313,643 filed Nov. 21, 2008 discloses a new autonomous hull robot including turbines drivable by water flowing past the hull while the vessel is underway. The turbines operate (e.g., power) the cleaning and the drive subsystems of the robot.
The flow of water past the hull of a vessel may vary in direction over the length of the hull. In addition, there may be times when the hull robot must maneuver around obstacles on the hull. It may also be desirable to traverse the hull at different angles for optimal cleaning and/or inspection operations.


The disclosure provides systems and methods for controlling an intersection of a route of a UAV. The systems and methods provide detection of vehicles and persons in (or predicted to enter) an area of the intersection and provide a signal to the UAV so that the UAV can avoid flying over vehicles and persons.

There is a need for unmanned aerial vehicles (UAVs) or drones to perform a host of functions, including delivering goods, assisting emergency crews, and helping to optimize traffic. However, strict laws regarding drone flight and use have limited the ability to provide many of these functions. For example, drones may not be allowed to operate over a non-participating person or a moving vehicle.
Such restrictions make the use of drones difficult for anyone trying to provide services using drones as it is difficult to determine a flight path that avoids civilization and traffic. Object recognition may be used to recognize objects to avoid persons and vehicles. However, this requires that the drone fly low to the ground and object recognition becomes more difficult at night.
It is with respect to these and other considerations that the disclosure made herein is presented.

Systems and methods for controlling an intersection of a route of an unmanned aerial vehicle


Methods for determining a volume of stored gas within a rock sample includes loading a rock sample into an overburden cell. A hydrocarbon gas at a gas pressure is applied to the rock sample and a confining fluid at a confining pressure is applied to the overburden cell. The confining pressure and the gas pressure are increased until a first pressure and temperature condition is met. With the rock sample maintained at the first temperature and pressure condition, a nuclear magnetic resonance spectrometer is used to scan the rock sample and measure a hydrocarbon gas volume within the rock sample. This measured hydrocarbon gas volume is then corrected using a Real Gas Index to determine the volume of stored gas within the rock sample.

The determination of the gas-in-place for shale gas reservoirs is important for assessing the quality of the reservoir and the suitability of that reservoir for development. Generally, gas-in-place for shale gas reservoirs is estimated by partitioning the total stored gas into free and adsorbed gas. Free gas is gas that is present in the reservoir either in gaseous phase at reservoir pressures or that will evolve out of the formation fluid as the formation pressure decreases. The free gas volume is calculated using the porosity of the rock and the amount of gas that can be stored in the rock at a given pressure and temperature assuming 'real gas' behavior.
Adsorbed gas is gas that accumulates on the pore surfaces of solid materials in the formation. The volume of adsorbed gas is computed from Langmuir adsorption isotherm tests, which assume a mono-layer adsorption of gas (of higher density) on the pore surfaces. The free gas and adsorbed gas volumes make up the total gas available in the reservoir but are assumed to behave differently under pressure drawdown scenarios.
It is understood that the physical properties and behavior of fluids in confined pore spaces are very different than bulk fluid behavior. In nano-porous rock systems, characteristic length scale of the medium approaches both the mean free path and the molecular size of the saturating fluid. Thus, in these systems fluid-pore interactions may tend to dominate over fluid-fluid interactions. For example, heightened capillary forces may impact interfacial tensions, fluid densities, viscosities, saturation pressures, phase compositions, and phase boundaries.
Understanding the behavior of gas stored in nano-porous rock systems is important for predicting and managing production from shale gas reservoirs. Thus, there remains a need for experimental methods for evaluating the behavior of gas stored in nano-porous rock systems.


A device for inflating an airbag has a gas generator. A gas generator housing can be anchored to a vehicle body. An end of an inflation tube is connected to a gas discharge socket fastened to the gas generator housing in an axially aligned and gas-tight manner. The tube end and the gas discharge socket are connected via a covering sleeve that bridges a gas-tight connection between the inflation tube and the gas generator.

The present invention relates to a device for inflating an airbag with a gas generator.
DE 197 38 741 A1 teaches a device for inflating a side curtain airbag in a vehicle. The folded airbag and the inflation tube are mounted along the roof edge in the vehicle. It is necessary that the inflation tube is adapted to the path of the roof edge or the upper roof crossbeam. As a result of these installation requirements, the path of the inflation tube deviates from alignment with the gas discharge socket. When the airbag is deployed the forces of inflation gas act on the connection between the inflation tube and the gas discharge socket. There is a risk that the gas-tight connection between the inflation tube and the gas discharge socket will be damaged and therefore inflation of the airbag within the required time is not achieved.
There is provided in accordance with the invention a device for inflating an airbag comprising a gas generator having a gas generator housing that can be anchored to a vehicle body and an inflation tube. An end of the inflation tube is connected in an axially aligned and gas-tight manner to a gas discharge socket fastened to the gas generator housing. The tube end is fixed by a covering sleeve that at least partially surrounds an outer face of the tube end or directly on the gas discharge socket so as to be secured in an axial direction and secured against rotation around an axis of the tube.


A stimulator device for controlling waste storage for a subject, having one electrode placed in proximity to a portion of each of the right and left pudendal nerves, which contains efferent fibers that, when stimulated, produce contraction of the urethral or anal sphincter. The stimulator device having a pulse generator connected to electrodes, bilaterally, to provide stimulation for each electrode to stimulate pudendal efferent axons. The pulse generator adapted to provide a first type of stimulation to cause waste to be stored within the subject. The pulse generator adapted to provide a second type of stimulation, different from the first type of stimulation, to allow waste to be voided from the subject by blocking nerve impulses that accompany sphincter dyssynergia. An input device to allow an end user to select the first type of stimulation, the second type of stimulation, or no stimulation. Variations of the concept are disclosed.

Storage and Elimination of Urine.
The lower urinary tract (LUT) is responsible for the storage and periodic elimination of urine. Urine is stored in the urinary bladder, which serves as a urine reservoir, and is eliminated through the urethra, which serves as the urine outlet.
During the urine storage phase, the bladder must remain relaxed to allow it to stretch to accommodate increasing volumes of urine, while the urethra must remain closed to prevent leakage of urine (also termed urinary incontinence). Bladder relaxation is maintained by inhibition of bladder parasympathetic reflex pathways in the sacral spinal cord and by activation of efferent sympathetic axons in the hypogastric nerve and beta3 adrenergic receptor stimulation to induce bladder smooth muscle relaxation.
Urethral closure is maintained by both urethral smooth muscle contractions of the internal urethral sphincter that are promoted by the efferent sympathetic axons in the hypogastric nerve, through alpha1 adrenergic receptor stimulation to induce contraction, and by striated muscle contractions of the external urethral sphincter that are promoted by efferent somatic motor axons in the pudendal nerve through nicotinic cholinergic receptor activation.
As the bladder fills with increasing volumes of stored urine, stretch receptors in the bladder send signals along pelvic nerve afferent fibers to the sacral spinal cord, where they are relayed to lumbar sympathetic centers that in turn stimulate efferent sympathetic hypogastric nerve activity to further relax the bladder and contract the internal urethral sphincter. These bladder stretch receptors also activate the efferent somatic motor pudendal nerve activity to tighten the external urethral sphincter. Thus, relaxation of the bladder and contraction of urethral sphincters together promote urine storage as the bladder fills.
When the bladder is stretched to the point where voiding should occur, the bladder stretch receptors relay this sensory information to the brain, which suppresses the bladder sensations and sacral parasympathetic voiding reflexes, while promoting the urine storage reflexes. When it is behaviorally appropriate, the brain inhibits the sympathetic and somatic urine storage reflexes to allow relaxation of the urethral sphincters and activates the sacral parasympathetic micturition reflex to produce a bladder contraction of sufficient strength and duration to completely empty the bladder. Thus, relaxation of the urethra and contraction of the bladder together produce efficient urine voiding. Urine voiding is sometimes called micturition or urination.
Storage and Elimination of Feces.
Similar to the storage and elimination of urine by LUT, the lower gastrointestinal (GI) tract is responsible for the storage and periodic elimination of feces (also termed stools). Feces are stored in the descending and sigmoid colon, which serves as a fecal reservoir, and are eliminated through the rectum and anus, which serves as the fecal outlet.
During the fecal storage phase, the descending and sigmoid colon must remain relaxed to allow stretch to accommodate increasing volumes of feces, while the rectum maintains tone to detect entry of feces, and the anus is closed to prevent leakage of feces (also termed fecal incontinence). Descending and sigmoid colon relaxation is maintained by activity of efferent sympathetic axons in the hypogastric nerve and alpha2 adrenergic receptor activation that inhibits GI smooth muscle. Anal closure is maintained by both smooth muscle contractions promoted by the efferent sympathetic axons in the hypogastric nerve through alpha1 adrenergic receptors and by striated muscle contractions of the external anal sphincter promoted by efferent somatic motor axons in the pudendal nerve through nicotinic cholinergic receptors. As the descending and sigmoid colon fill with increasing volumes of feces, stretch receptors send signals through intrinsic and extrinsic GI reflex pathways to tighten the smooth and striated muscle of the external anal sphincter, as well as inhibit sacral parasympathetic defecation reflex pathways.
As feces are propelled into the descending and sigmoid colon via peristalsis, the rectum begins to stretch, which inhibits peristalsis in the descending colon and contracts the rectum and anal sphincters. As the rectum is stretched to the point where voiding (also termed defecation) should occur, the rectal stretch receptors relay this sensory information to the brain, which can suppress the rectal sensations and the sacral parasympathetic defecation reflexes, while promoting the colon storage reflexes, until defecation is appropriate. When defecation is appropriate, the sacral parasympathetic defecation reflex is activated to relax the striated external anal sphincter, contract the sigmoid colon, and propel feces into the rectum, which simultaneously relaxes and stretches as it accepts the feces. The rectal stretching activates the rectoanal inhibitory reflex that relaxes the smooth muscle of the internal anal sphincter. Thus, contraction of the sigmoid colon coordinated with relaxation of the anal sphincters produces efficient defecation.
Continence and Voiding.
Healthy bladder and GI voiding behavior can thus be considered to exist in two modes: (1) continence or "storage mode" when the bladder and colon are relaxed and the external urethral and anal sphincters are contracted and (2) "voiding mode" when the bladder or colon contract and the external urethral and anal sphincters relax.
Incontinence.
Urinary and fecal incontinence are the involuntary loss of urine or feces, respectively, and can be caused by dysfunction of either the voiding or storage reflexes or both. Stress incontinence, which is an involuntary loss of urine or feces upon physical exertion (e.g. sporting activities or laughing, sneezing or coughing), is considered a weakness in storage reflexes and sphincter function, especially among women. Urge incontinence, which is an involuntary loss of urine or feces associated with episodic bladder or colon contractions and/or sensations of urgency, is considered an overactivity of the voiding reflexes. Some individuals are diagnosed with mixed incontinence, which is a combination of stress and urge urinary or fecal incontinence. Such urinary and fecal incontinence affects quality of life and participation in social and professional activities.
Dysfunctional Retention of Urine or Feces.
Urinary and fecal retention are the inability to efficiently void urine or feces, respectively, and can be caused by dysfunction of either the voiding or storage reflexes or both. Dysfunctional voiding reflexes cannot produce contractions of the bladder or colon that are of sufficient strength or duration to completely empty the bladder or colon of urine or feces, respectively. Dysfunctional storage reflexes can produce contractions of the urethral and anal sphincters that prevent the passage of urine or feces, respectively, when micturition or defecation are desired. This lack of coordination between bladder or colon contraction on one hand, and urethral or anal sphincter relaxation on the other hand, is termed sphincter dyssynergia. Thus, dysfunctions of either voiding or storage reflexes can result in residual urine in the bladder and feces remaining in the colon, respectively. Residual urine in the bladder can cause renal damage and promote urinary tract infections, either of which can be life-threatening. Feces remaining in the sigmoid colon can promote fecal impaction and functional constipation.
Impaired Nervous Systems.
Many individuals with damage or disease of the nervous system (e.g. spinal cord injury (SCI), spina bifida, multiple sclerosis) exhibit conditions of both incontinence and retention of both urine and feces (i.e. urinary incontinence and urinary retention and/or fecal incontinence and fecal retention). In this population, for example, the bladder contracts involuntarily, producing "uninhibited, neurogenic, non-voiding, bladder contractions" that overcome urethral resistance to cause urinary incontinence, but they also exhibit bladder-sphincter dyssynergia that produces urinary retention. Because the brain can no longer control and coordinate voiding or storage reflexes, the bladder and colon do not contract and empty properly to prevent retention, and the sphincters do not contract properly to prevent incontinence. Similar co-morbid voiding dysfunction is also prevalent in diabetics with diabetic cystopathy and gastroenteropathy and in community-dwelling and institutionalized elderly individuals.
Urinary Retention Treatment.
Urinary retention in SCI individuals is such a severe and unique condition that treatments, considered to be inappropriately risky for the general population, are used, but with limited success.
Current therapies for eliminating sphincter dyssynergia (Leippold et al., 2003 Eur Urol. August; 44(2):165-74) are intraurethral injection of botulinum toxin or surgical sphincterotomy, which produce semi-permanent or permanent paralysis of the sphincter, respectively. Naturally, paralysis of the sphincter prevents it from functioning and exacerbates involuntary leakage of urine (urinary incontinence) throughout the day. Another approach to drain urine from the bladder is catheterization. Some patients require an indwelling catheter to be inserted into the bladder through the urethra or a suprapubic incision, allowing one to continuously drain urine into a collecting bag attached to the patient's leg. Other patients use intermittent bladder catheterization, which requires passage of a catheter through the urethra into the bladder multiple times per day for the rest of the patient's life. Intermittent catheterization is obviously inconvenient and difficult or impossible (for quadriplegics) without caregiver assistance. Both forms of catheterization are also a major cause of catheter-associated urinary tract infections (CAUTIs) that result in hospitalization of 1 of 16 SCI individuals each year. The medical costs associated with urinary tract-related hospitalization are estimated at more than $12,000/year/patient and a total U.S. healthcare cost of $300-400 MM/year (Cardenas et al 2004 Archives Physical Medicine and Rehabilitation 85:1757-1763; DeVivo and Farris 2011 Top Spinal Cord Inj Rehabil, 16:53-61). The number of SCI individuals in the U.S. today exceeds 270,000 (National Spinal Cord Injury Statistical Center, Birmingham, Ala., 2013). Therefore, there is a great medical need for a safe and efficacious therapy that can block sphincter dyssynergia to eliminate or reduce the need for sphincterotomy, botulinum toxin injections, and/or catheterization.
Not only do SCI individuals have voiding difficulty due to sphincter dyssynergia and weak bladder contractions, they also have urine storage difficulty or urinary incontinence due to intermittent relaxations of the sphincter during uninhibited neurogenic bladder contractions. Acute SCI results in an 'areflexic' bladder in which urine builds up without any sensation of filling or physical ability to void. With time, involuntary, spinally-organized, bladder reflexes develop (de Groat and Yoshimura, 2012 Exp Neurol 235:123-132). Unfortunately, these spinal reflexes only produce weak (but frequent), short-duration, neurogenic, bladder contractions that do not empty the bladder but instead cause leakage of small amounts of urine throughout the day, i.e. urinary incontinence. Thus, most people with SCI have both urinary incontinence and retention.
Studies by Ko and Kim (1997 Spinal Cord. October 35(10):690-3) demonstrated that injecting phenol into the pudendal (PUD) nerve resulted in the relaxation of the sphincter with subsequent increases in voiding efficiency. However, phenolic poisoning of the pudendal nerve results in permanent loss of sphincter activity, which promotes incontinence, and thus does not solve the goal of temporary and reversible control of the pudendal nerve.
None of the above treatments for SCI individuals are appropriate for stress, urge or mixed incontinence in the general population. Currently, the only treatment available in the United States for which there is good evidence of effectiveness is pelvic floor muscle training, and it is considered first-line treatment for stress incontinence and mixed incontinence (Dumoulin and Hay-Smith 2010 Cochrane Database Syst Rev. January 20; (1):CD005654). Antimuscarinic agents and beta3 receptor antagonists can be used for urge incontinence.
In men who have undergone radical prostatectomy, which damages the urethral sphincter, an artificial urinary sphincter may be surgically implanted. However, these are reserved only for the most severe cases, because they produce ischemia and urethral erosion with time.
Sacral nerve stimulation is moderately effective for treatment of urge incontinence and fecal incontinence in patients with intact spinal cords, while tibial nerve stimulations, anal injections of bulking agents, and radio frequency energy have shown modest, but clinically significant, reductions in fecal incontinence (Wald A; Curr Gastroenterol Rep. 2018 Mar. 26; 20(3):9).
Cases of urinary retention are seen, rarely, in women with Fowler's syndrome and in children due to an inability to relax the pelvic floor and sphincters. In women, sacral nerve stimulation has been used with success (Kessler and Fowler 2008 Nat Clin Pract Urol. December 5(12):657-66). In both women and children, pelvic floor biofeedback training has also been attempted.
Fecal Retention Treatment.
Diet, enemas, and manual extraction are currently the primary methods of controlling fecal retention. Anal sphincter injections of botulinum toxin have also been reported as treatment of fecal retention in children (Zar-Kessler et al., 2018 J Pediatr Surg. April; 53(4): 693-697).
There have been attempts to control urethral sphincter dyssynergia using electrical stimuli. Preclinical studies in anesthetized cats (Bhadra et al. 2006 J Neural Eng. June 3(2):180-7; Gaunt et al., 2008 Neurorehabil Neural Repair. 2009 Jul.-Aug. 23(6):615-26; Wang et al., 2009 BJU Int. February 103(4):530-6; reviewed in Kilgore and Bhadra, 2014) showed that blockade of the pudendal nerve is highly effective in relaxing the urethral sphincter and improving voiding (Tai et al. 2004 J Urol. November 172(5 Pt 1):2069-72, Bhadra et al. 2006 J Neural Eng. June 3(2):180-7, Kilgore and Bhadra, 2014). Temporarily blocking amputee nerve pain and back nerve pain by using high frequency (e.g. 5-20 kHz) stimulation is known in the art (Kilgore and Bhadra, 2014 Neuromodulation. April 17(3):242-54). There have been no previous reports of using such high frequency stimulation in humans to block the pudendal nerve.
In U.S. Pat. No. 9,623,243 (Chancellor and Tai), one implanted electrode is used to excite the pudendal nerve to contract the bladder while second and optionally third electrodes are used to block the pudendal to external urethral sphincter conduction to prevent external urethral sphincter contraction.
In U.S. Patent Publication 2016/0129248 (Creasey and Toong), a dermal patch is applied over the dorsal nerve in order to send electrical signals that will control contraction and relaxation of the bladder.
In U.S. Pat. Nos. 8,396,555; 7,047,078; and 7,571,000; Boggs et al. describe the use of electrodes placed in a targeted region of the pudendal nerve to stimulate afferent fibers to evoke bladder contractions with one selected frequency while applying a second selected frequency range to inhibit bladder contractions.
In U.S. Pat. No. 9,072,866, Gaunt and Prochazka describe blocking of the pudendal nerve by stimulation with high frequency electrical pulses which cause the urethral sphincter to open, allowing bladder voiding. The pudendal nerve is blocked to allow bladder voiding until the bladder is empty.
In U.S. Pat. No. 9,393,411, Bhadra et al. describe a method for bladder control involving a first electrode coupled to an afferent nerve to which is applied a stimulation to reduce contractions of the urethral sphincter and a second electrode coupled to an afferent or efferent nerve to which is applied a second pulse burst stimulation to stimulate contractions of the bladder, which together result in complete voiding of the bladder.
Incontinence results from overactivity of the bladder and colon on one hand and/or underactivity of the urethral and anal sphincters on the other hand. Urinary and fecal retention result from underactivity of the bladder and colon on one hand and/or overactivity of the urethral and anal sphincters (sphincter dyssynergia) on the other hand. Therefore, therapy that increases the activity of the urethral and anal sphincters during storage of urine and feces, and blocks activity of the urethral and anal sphincters during voiding of urine and feces, is desired.
Vocabulary.
Cystometry is a clinical diagnostic procedure used to evaluate bladder function. Specifically, it measures contractile force of the bladder when voiding. See: //en.wikipedia.org/wiki/Cystometry. A cystometrogram (CMG) is a physiograph tracing resulting from cystometry procedures.
Bladder capacity (BC) refers to the volume of fluid that can be held in the bladder without voiding or leaking.
Bladder leak point pressure (LPP) is the pressure at which fluid leaks from the bladder and through the urethra in the absence of a bladder contraction.
Bladder voiding pressure (BVP) is the pressure at which fluid is expelled from the bladder through the urethra during a bladder contraction.
Electromyography (EMG) is a measurement of the electrical activity of a muscle, for example the striated anal or urethral sphincter muscle.
Pressure measurements are frequently made with respect to a column of a fluid. Two common fluids used for this purpose are mercury (Hg) and water (H20). As mercury is denser than water, a particular pressure will support a taller column of H2O than Hg. One millimeter of Hg is thus equal to 1.35951 centimeters of H20.
A stimulus response curve examines the effect of incrementally increasing the current, pulse duration, or frequency of the stimulus pulse while monitoring the relative changes in urethral, anal, or bladder pressure response.
A threshold response is the minimal current (I-T) or pulse width (PW-T) required to evoke a contraction of the external urethral or external anal sphincter, while a maximal response is the response that occurs at a given current (I-max) or pulse width (PW-max) above which no further increases in current or pulse width produce further increases in the contraction response of the external urethral or external anal sphincters.
Afferent neurons and efferent neurons are well-known in the art. Within the brain itself, the designation of afferent and efferent is context based but that is not relevant here. Within this disclosure, afferent neurons carry sensory information from peripheral organs as nerve impulses towards a central organ such as the brain or spinal cord. Afferent neurons are sometimes called sensory neurons. Efferent neurons transmit nerve impulses from the brain or spinal cord to the periphery of the body, such as to muscles and other structures. Efferent neurons are sometimes called motor neurons.
Unless explicit to the contrary, the word "or" should be interpreted as an inclusive or rather than an exclusive or. Thus, the default meaning of or should be the same as the more awkward and/or.
Unless explicit to the contrary, the word "set" should be interpreted as a group of one or more items.
Unless explicitly indicated as the smooth or internal urethral sphincter, the phrase "urethral sphincter" should be interpreted as the striated, external urethral sphincter.
Unless explicitly indicated as the smooth or internal anal sphincter, the phrase "anal sphincter" should be interpreted as the striated, external anal sphincter.
Frequently, when describing an industrial process it is useful to note that a given parameter is substantially met. Examples may be substantially parallel, substantially perpendicular, substantially uniform, and substantially flat. In this context, substantially X means that for purposes of this industrial process it is X. So something that may not be absolutely parallel but is for all practical purposes parallel is substantially parallel. Likewise, mixed air that has substantially uniform temperature would have temperature deviations that were inconsequential for that industrial process.
As recognized in C. E. Equipment Co. v. United States, 13 U.S.P.Q.2d 1363, 1368 (Cl. Ct. 1989), the word "substantially" in patent claims gives rise to some definitional leeway—thus the word "substantially" may prevent avoidance of infringement by minor changes that do not affect the results sought to be accomplished.
The term "about" means that quantities, parameters, shapes and other characteristics are not and need not be exact, but may be approximate and thus larger or smaller, reflecting tolerances, conversion factors, rounding off, measurement error and the like, and other factors known to those of skill in the art. In general, a quantity or characteristic is "about" or "approximate" whether or not expressly stated to be such.
Furthermore, the transitional terms "comprising", "consisting essentially of" and "consisting of", when used in the appended claims, in original and amended form, define the claim scope with respect to what un-recited additional claim elements or steps, if any, are excluded from the scope of the claim(s). The term "comprising" is intended to be inclusive or open-ended and does not exclude any additional, un-recited element, method, step or material. The term "consisting of" excludes any element, step or material other than those specified in the claim. The term "consisting essentially of" limits the scope of a claim to the specified elements, steps or material(s) and those that do not materially affect the basic and novel characteristic(s) of the claimed invention.
The term patient is most often a reference to a human that would benefit from a stimulating device in accordance to the teachings of this disclosure. The term patient should be read expansively to include animals that have received a stimulating device. The term patient also includes a teaching simulator that receives a stimulating device and is used by medical or veterinarian, or research personnel.
End user may be a set of people that includes the patient (having the one or more electrodes providing stimulus to the pudendal nerve). The term end user includes caregivers such as nurses or other professionals providing care to the patient and family members that may assist with providing care.


A vapor delivery system for delivering a vapor-phase reactant to a chemical process reactor at a substantially constant flow rate. The vapor delivery system includes a source of a reactant material, means for converting the reactant material to a vapor and for maintaining a predetermined volume of vapor in a vapor phase, a flow controller for providing a controlled flow of the vapor-phase reactant to the process reactor, means for detecting a parameter related to the availability of the vapor-phase reactant material to the process reactor from the flow controller, and means responsive to the detection signal for controlling the supply of reactant material to the vapor converter. In one embodiment the parameter is the pressure of the vapor within the predetermined volume. In another embodiment the parameter is the fluid conductance of a control valve within the flow controller. The vapor delivery system of the present invention can operate in either a substantially continuous or a noncontinuous delivery mode.

Various chemical processes use precise quantities of materials which must be introduced as vapors into a processing chamber at precisely controlled rates in order to yield a product of a defined composition. For example, in the microelectronics industry, controlled amounts of vaporized precursor materials must be carefully introduced into a chemical process chamber for reaction with other materials and for deposit onto a wafer (such as by condensation). In this and other chemical processes, such as chemical etching, stripping, and passivation, the ability to measure and control the flow of each vaporized precursor is vital for reliable manufacture of products having consistently high performance quality.
Vapors of precursor materials used to manufacture microelectronic and semiconductor devices are typically derived from liquid or solid precursor materials. A suitable delivery pressure for a reactant vapor depends on the vapor pressure of the liquid or solid precursor from which the vapor is derived, as well as the particular requirements of the mass flow controller.
Vapor-phase reactant delivery in about ninety percent of current microelectronics processing applications can be effectively controlled using so-called thermal mass flow controllers. With a thermal mass flow controller, one can determine the rate of laminar fluid flow in a heated channel by measuring the temperature losses from the fluid as it flows through the channel. Temperature measurement of the fluid can be accomplished with any known temperature measuring device, such as, for example, thermistors, thermocouples, and the like. For processes which require operation in a pressure range of 10.sup.-4 torr through atmospheric pressure (760 torr), a flow controller inlet pressure range of 50 torr to several atmospheres, fluid temperatures ranging from ambient through about 40.degree. C., and mass flow rates of 1.times.10.sup.-3 to 1000 torr-liters/sec, thermal mass flow controllers are highly effective in delivering a controlled flow of vapor to the process reactor.
For delivery of precursor materials to process reactors in systems in which the operating temperatures, pressures and flow rates are outside of these ranges, other devices for controlling mass flow may be more useful or effective. For example, a bubbler may be used to bubble a carrier gas, such as hydrogen or helium, through a source of a heated liquid reactant which is typically provided in a temperature-controlled ampule. The carrier gas bubbles through the liquid reactant in the ampule and becomes saturated with the vapor of the reactant material. It is then delivered to the reaction chamber through heated lines.
A disadvantage of bubblers is the periodic need to refill the ampule with reactant liquid. Replenishment of the ampule with liquid reactant introduces contaminants into the process, as well as batch-to-batch variations in various properties of the material, such as, for example, the viscosity and vapor pressure. The refilling process is messy, time-consuming and labor-intensive, and therefore costly. In addition, as the liquid level in the ampule changes, the ratio of carrier gas to reactant vapor changes also, making it difficult to control the amount of reactant delivered to the process chamber. Another disadvantage is that the bubbler requires a relatively large volume of reactant material which must be maintained at an elevated temperature. Some reactant materials undergo unfavorable chemical reactions or become otherwise unstable if held for prolonged periods of time at the desired maintenance temperatures.
An alternative to bubblers involves the use of a heated ampule of a liquid or solid reactant material. The vapor from the heated reactant material is provided directly to the inlet of a mass flow controller at an appropriate vapor pressure, without a carrier gas. This technique avoids the precise temperature and pressure control requirements of a bubbler and requires only that the reactant temperature be sufficient to deliver the vapor to the mass flow controller at a suitable pressure.
Disadvantages of this technique include those mentioned above relating to replenishment of the reactant material and the need for a relatively high volume of material to be held at an elevated temperature for potentially lengthy periods. In addition, this technique may not be effective for a reactant material whose vapor pressure at the ampule maintenance temperature is relatively close to the total pressure of the reaction chamber. The mass flow controller cannot effectively deliver fluid unless there exists a sufficient pressure differential across it.
Another alternative is to use a liquid flow control device, such as a volumetric displacement pump or a liquid mass flow controller in combination with a reservoir of liquid reactant material, with a downstream vaporizer. The liquid reactant material is provided at substantially ambient temperature, from either a reservoir or an integral distribution system, to a flash vaporizer, and the vaporized reactant is delivered to a process reactor. No temperature control is required for the liquid before it enters the vaporizer.
A disadvantage of this approach is the requirement of a flash vaporizer. In order to deliver a nonfluctuating, controlled flow of a reactant vapor to the process reactor, the vaporizer must operate as a continuous liquid-to-vapor conversion device which responds virtually instantaneously to flow rate changes. In addition, there may be deposition of particles from within the liquid reactant material and the formation of residual films on various vaporizer surfaces during the vaporization process. These events may lead to clogging of the vaporizer and delivery lines and may necessitate their frequent flushing and cleaning.
Alternative devices have been developed to measure and control the mass flow of vapors not suited for measurement by thermal mass flow transducers or the other devices discussed above. These are typically pressure-based mass flow controllers which measure temperature and pressure of a fluid flowing around and/or through a flow restrictor, such as a laminar flow element.

System for delivering a substantially constant vapor flow to a chemical process reactor


A method for fabricating a semiconductor device is provided. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a first insulating layer, a first conductive layer and a chemical mechanical polishing (CMP) stop layer over the semiconductor substrate in sequence; forming openings in the chemical mechanical polishing (CMP) stop layer and the underlying first conductive layer to expose the first insulating layer, thereby leaving a patterned chemical mechanical polishing (CMP) stop layer and a patterned first conductive layer; forming a second insulating layer on the patterned chemical mechanical polishing (CMP) stop layer, filling in the openings; performing a planarization process to remove a portion of the second insulating layer until the patterned chemical mechanical polishing (CMP) stop layer is exposed, thereby leaving a remaining second insulating layer in the openings; removing the patterned chemical mechanical polishing (CMP) stop layer.

1. Field of the Invention
The invention relates to a semiconductor device and method for fabricating the same, and more particularly to an interconnect structure of a semiconductor device and method for fabricating the same.
2. Description of the Related Art
The ever-increasing demand for high-performance semiconductor devices has motivated the semiconductor industry to design and manufacture ultra-large-scale integrated (ULSI) circuits with smaller feature size, higher resolution, denser packaging, and multi-layer interconnects. ULSI technology places stringent demands on global planarity of the interlayer dielectric (ILD) layers. Compared with other planarization techniques, the chemical mechanical polishing (CMP) process produces excellent local and global planarization at low cost. It is thus widely adopted for planarizing inter-level dielectric (silicon dioxide) layers.
FIG. 1 shows a cross section of a conventional semiconductor device 150, and specifically illustrates an interconnect structure. An intermetal dielectric (IMD) layer 112 and an interconnect layer 104 are formed on the interlayer dielectric (ILD) layer 102 and the semiconductor substrate 100. The intermetal dielectric (IMD) layer 112 has a top 122 lower than a metal layer 104. The lower intermetal dielectric (IMD) layer 112 is formed with material loss or recesses by the conventional planarization process. A barrier layer 114 and a poly-plug 116 subsequently formed on the metal layer 104 have residue or short problems if a misalignment problem occurs as shown in FIG. 1. Semiconductor device performance such as yield or reliability thus suffers because the recess problem of the intermetal dielectric (IMD) layer.
Thus, a novel and reliable method of fabricating a semiconductor device with more robust interconnect structure is desirable.

Semiconductor device and method for fabricating the same

Taiwan Semiconductor Manufacturing Co., Ltd.


Provided is a method of fabricating an electronic circuit. The method includes preparing a substrate, forming a polymer film on the substrate, patterning the polymer film to form a polymer pattern, and forming an electronic device on the polymer pattern.

The present invention disclosed herein relates to a method of fabricating an electronic circuit, and more particularly, to a method of fabricating a stretchable or foldable electronic circuit.
Unlike typical flexible devices having only a bendable function, stretchable electronic circuits may be applicable to various fields, such as a sensor skin for robots, wearable communication devices, internal or attachable bio-elements, and next-generation displays. Accordingly, studies for implementing stretchable electronic circuits have been conducted.
In order to implement a stretchable electronic circuit, technologies for forming a device region and a wiring region on a flexible substrate are required. In typical flexible devices, a device region is separately formed and then the device region is attached on a flexible substrate to form a flexible device. Besides, semiconductor processes are used in order to form the device region. However, since such flexible substrates do not allow for the formation of the device region and the wiring region in a continuous semiconductor process, such stretchable electronic devices have limitations in that high fabrication costs are required.

Method of fabricating electronic circuit

ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE


A cordless, hydrocarbon fuel powered hairdryer. The invention incorporates a novel electronic control system which evaluates the thermal and electrical conditions within the hairdryer during its operation. Two fuel flow valves are provided. The first fuel flow valve is mechanically actuated and opens and closes the valve in the hydrocarbon fuel cartridge. The second fuel flow valve is a solenoid valve that cannot open without a predetermined voltage being supplied. Application of the predetermined voltage will allow gas to flow through this second valve and into the area where the fuel is ignited. Only when both valves (the mechanical and the solenoid) are open, can fuel flow. A microcontroller monitors the temperature conditions in the combustion area, and controls system conditions such as power to the solenoid valve and to the fan motor to prevent uncombusted gas from building up and presenting a safety hazard.

The concept of a hydrocarbon cordless hairdryer has been known for many years. Yet, although the concept itself is not new in the art, practical design and effective implementation of the concept in a working embodiment has been problematic. Heretofore, the embodiments proposed in the art have generally presented important safety flaws. The safety considerations in a device of this nature arise from the necessity for regulation and control of a very high flow rate of fuel (approximately 30-50 g/hr) in a careful fashion to prevent any dangerous conditions arising for the consumer. The fuel must be combusted completely within the device without sparks activating fuel outside desired areas, and without flames escaping from the device. To prevent fire and explosion hazards, the exhaust gases must be maintained at a temperature which is cooler than the ignition temperature of combustible mixtures of air and common household solvents or natural gas. At the same time, for the product to be effective, to promote good hair drying without causing hair damage, the temperature of the exhaust when it leaves the dryer should be approximately 80.degree. C.
Safety problems are also introduced by misuse of the device. One anticipated misuse for example is that users could turn the gas on but not ignite it, or occasionally could cover the exhaust or intake openings causing flame outs. Whenever fuel flows but is not burnt, the flow of gas must be interrupted before hazardous explosive levels of gas accumulate outside of the hairdryer, presenting the possibility of inadvertent explosion. Similarly, the fuel flow must also be interrupted in cases of overheating. Overheating results from reduced air flow through the dryer. This can be caused by discharged fan motor batteries, by debris on the intake or exhaust grill interfering with the free flow of air, by debris on the axle of the motor causing binding, by a wornout motor, or by intake or exhaust areas which are significantly occluded by the user's hair or by other objects which lodge during normal use.
In addition, the fuel feed system must have the means available to evaporate desirable quantities of fuel (preferably butane) and to feed only vapor to the combustion area. Although the use of propane could overcome this problem, propane cartridges have to be of costly construction to conform with DOT regulations.
Accordingly, there is a need for a hydrocarbon fuel, cordless hair dryer which overcomes the safety problems that are prevalent within the prior art.

Cordless hydrocarbon fuel heated hairdryer


In an embodiment, a chemical mechanical polishing method for a substrate having a first layer and a stepped portion. A surface of the first layer is positioned above an upper face of the stepped portion. A polishing process for selectively removing the stepped portion is performed on the first layer by using a first slurry composition that has a self-stopping characteristic so that the first layer is changed into a second layer having a substantially flat surface. A second polishing process is performed using a second slurry composition that does not have the self-stopping characteristic, until the upper face of the stepped portion is exposed.

1. Field of the Invention
The present invention relates to a chemical mechanical polishing method. More particularly, the present invention relates to a chemical mechanical polishing method for polishing a silicon oxide layer.
2. Description of the Related Art
A multi-layer wiring structure may be employed in a semiconductor device if the semiconductor device is required to have a high capacity and a high degree of integration. The multi-layer wiring structure is generally formed by repeatedly performing processes for forming and patterning a conductive layer and an insulation layer. After the conductive layer and the insulation layer are etched to form a conductive layer pattern and an insulation layer pattern, planarization processes are carried out. Owing to the planarization processes, successive photolithography for forming the conductive layer pattern and the insulation layer pattern may be efficiently performed. The planarization processes may be typically divided into a local planarization process and a global planarization process. However, the ultimate goal of the planarization processes is to achieve the global planarization.
An etch-back process, a reflow process, and a chemical mechanical polishing process have been developed as planarization processes. The chemical mechanical polishing process is largely employed for forming a highly integrated circuit because the chemical mechanical polishing process efficiently achieves the global planarization of a layer to be polished. This is also because the chemical mechanical polishing process may efficiently achieve a relatively high planarity.
The chemical mechanical polishing process is developed by International Business Machines (IBM) Corp. in the late 1980s. In the chemical mechanical polishing process, a semiconductor substrate is disposed beneath a polishing head of a chemical mechanical polishing apparatus. A polishing pad is positioned under the semiconductor substrate. A slurry composition including deionized water, an abrasive and an additive is provided onto the semiconductor substrate. The semiconductor substrate and the polishing pad may be moved with respect to each other while the polishing pad makes contact with the semiconductor substrate. Thus, a surface portion of the semiconductor substrate may be planarized. The abrasive of the slurry composition and protrusions of the polishing pad may mechanically polish the surface portion of the semiconductor substrate. Simultaneously, the surface portion of the semiconductor substrate is chemically polished by reactions between chemical components included in the slurry composition and ingredients in the surface portion of the semiconductor substrate.
A polishing efficiency of the chemical mechanical polishing process may be determined by the chemical mechanical polishing apparatus, the slurry composition, and the type of the polishing pad. In particular, the efficiency of the chemical mechanical polishing process may be increased by selectively using at least two slurry compositions. For example, a conventional method selectively using at least two slurry compositions is disclosed in Korean Patent Laid-Open Publication No. 2001-0061124.
In addition, a high-planarity slurry chemical mechanical polishing (HPS-CMP) process using a high-planarity slurry composition capable of improving planarity has been developed.
The HPS-CMP process is characterized by a layer having a stepped portion that is passivated by polymers to reduce a chemical polishing rate of the layer. Thus, the layer may be mechanically polished from the stepped portion rather than chemically. When the stepped portion is removed, an area of the layer, the area contacting a polishing pad of a chemical mechanical polishing apparatus employed for performing the HPS-CMP process, may become wide. That is, the flat surface area increases. In addition, the area may also be passivated by the polymers. Because the layer is not chemically polished because of the polymers attached to the layer, the area of the layer may be substantially dense. Thus, the layer may hardly be polished either chemically or mechanically after the stepped portion is removed. That is, the HPS-CMP process may stop by itself after the stepped portion is removed. In other words, a self-stopping characteristic may appear. As a result, a substantially high planarity may be easily achieved by employing the HPS-CMP process.
However, although the HPS-CMP process is employed, if a substrate formed under the layer has a protrusion having an upper face, then the protrusion of the substrate may be partially removed in removing the stepped portion of the layer.
FIG. 1 is a cross-sectional view illustrating a substrate and a silicon oxide layer formed on the substrate before a conventional HPS-CMP process is performed on the silicon oxide layer. FIG. 2 is a cross-sectional view illustrating the substrate and the silicon oxide layer after the conventional HPS-CMP process is performed on the silicon oxide layer.
Referring to FIG. 1, a substrate 100 includes a first stepped portion 110 and a second stepped portion 120 connected to the first stepped portion 110. The first stepped portion 110 includes at least two patterns adjacent to each other. In addition, the first stepped portion 110 includes a first upper face 110a, a first lower face 110b positioned below the first upper face 110a and a first sidewall 110c between the first upper face 110a and the first lower face 110b.
The first upper face 110a and the first lower face 110b may be substantially horizontal. In addition, the first upper face 110a may be substantially parallel with the first lower face 110b. The first sidewall 110c may be substantially vertical. In addition, the first sidewall 110c may be substantially perpendicular to the first upper face 110a and the first lower face 110b.
The second stepped portion 120 may include a second upper face 120a, a second lower face 120b positioned below the second upper face 120a and a second sidewall 120c between the second upper face 120a and the second lower face 120b.
The first lower face 110b of the first stepped portion 110 and the second upper face 120a of the second stepped portion 120 may be substantially coplanar. That is, the first lower face 110b may correspond to the second upper face 120a. Thus, the first stepped portion 110 may be to the second stepped portion 120.
A layer 200 is formed on the substrate 100 to cover the first and second stepped portions 110 and 120. The layer 200 has a third stepped portion positioned over the first upper face 110a of the first stepped portion 110. The third stepped portion may conform to the first stepped portion 110.
A portion 201 of a surface of the layer 200, the portion 201 being positioned directly over the lower face 120b of the second stepped portion 120, is positioned below a polishing target face 300 corresponding to the upper face 110a of the first stepped portion 110.
Referring to FIG. 2, the conventional HPS-CMP process using the high-planarity slurry composition is performed on the layer 200. Thus, the layer 200 is polished to the polishing target face 300. As illustrated in FIG. 2, the first and second stepped portions 110 and 120 of the substrate 100 are partially removed.
In performing the HPS-CMP process, a polishing pad positioned directly over the lower face 120b of the second stepped portion 120 may be positioned lower than the polishing pad positioned directly over the upper face 110a of the first stepped portion 110. Thus, although the first stepped portion 110 is removed, the HPS-CMP process may not stop by itself. That is, the self-stopping characteristic may not appear. Furthermore, corners of the first and second stepped portions 110 and 120 may be excessively polished because of an orbital movement of the polishing pad. Thus, the first and second stepped portions 110 and 120 may be unfortunately damaged.
As a result, a chemical mechanical polishing method capable of achieving a substantially high planarity as well as fully protecting a structure covered with a layer that is to be polished is an important topic of research.