The present invention relates to rotating element sheet material with a generalized containment structure and methods of fabricating such rotating element sheet material, where the rotating element sheet material comprises a fibrous matrix, a plurality of rotatable elements, and an enabling fluid, and where the plurality of rotatable elements are disposed within the fibrous matrix and are in contact with the enabling fluid. In addition, rotating element sheet material with a generalized containment structure, and methods of fabricating such rotating element sheet material, includes rotating element sheet material which comprises a fibrous matrix and a plurality of micro-capsules, and where the micro-capsules define a hollow space therein, and the hollow space contains a subset of a plurality of rotatable elements and an enabling fluid, and where the plurality of micro-cavities are disposed within the fibrous matrix.

The present invention relates to the preparation and use of rotating element sheet material with a generalized containment structure. Specifically, the present invention relates to the preparation and use of rotating element sheet material with a matrix substrate, or a substrate derived from a matrix structure.
Rotating element sheet material has been disclosed in U.S. Pat. Nos. 4,126,854 and 4,143,103, both herein incorporated by reference, and generally comprises a substrate, an enabling fluid, and a class of rotatable elements. As discussed more below, rotating element sheet material has found a use as xe2x80x9creusable electric paper.xe2x80x9d FIG. 1 depicts an enlarged section of rotating element sheet material 18, including rotatable element 10, enabling fluid 12, cavity 14, and substrate 16. Observer 28 is also shown. Although FIG. 1 depicts a spherically shaped rotatable element and cavity, many other shapes will work and are consistent with the present invention. As disclosed in U.S. Pat. No. 5,389,945, herein incorporated by reference, the thickness of substrate 16 may be of the order of hundreds of microns, and the dimensions of rotatable element 10 and cavity 14 may be of the order of 10 to 100 microns.
In FIG. 1, substrate 16 is an elastomer material, such as silicone rubber, that accommodates both enabling fluid 12 and the class of rotatable elements within a cavity or cavities disposed throughout substrate 16. The cavity or cavities contain both enabling fluid 12 and the class of rotatable elements such that rotatable element 10 is in contact with enabling fluid 12 and at least one translational degree of freedom of rotatable element 10 is restricted. The contact between enabling fluid 12 and rotatable element 10 breaks a symmetry of rotatable element 10 and allows rotatable element 10 to be addressed. The state of broken symmetry of rotatable element 10, or addressing polarity, can be the establishment of an electric dipole about an axis of rotation. For example, it is well known that small particles in a dielectric liquid acquire an electrical charge that is related to the Zeta potential of the surface coating. Thus, an electric dipole can be established on a rotatable element in a dielectric liquid by the suitable choice of coatings applied to opposing surfaces of the rotatable element.
The use of rotating element sheet material as xe2x80x9creusable electric paperxe2x80x9d is due to that fact that the rotatable elements are typically given a second broken symmetry, a multivalued aspect, correlated with the addressing polarity discussed above. That is, the above mentioned coatings may be chosen so as to respond to incident electromagnetic energy in distinguishable ways. Thus, the aspect of rotatable element 10 to observer 28 favorably situated can be controlled by an applied vector field.
For example, as disclosed in U.S. Pat. No. 4,126,854, hereinabove incorporated by reference, rotatable element 10 may comprise a black polyethylene generally spherical body with titanium oxide sputtered on one hemisphere, where the titanium oxide provides a light-colored aspect in one orientation. Such a rotatable element in a transparent dielectric liquid will exhibit the desired addressing polarity as well as the desired aspect.
A multivalued aspect in its simplest form is a two-valued aspect. When the aspect is the chromatic response to visible light, a rotatable element with a two-valued aspect can be referred to as a bichromal rotatable element. Such a rotatable element is generally fabricated by the union of two layers of material as described in U.S. Pat. No. 5,262,098, herein incorporated by reference.
FIGS. 2-5 depict rotatable element 10 with a two-valued aspect and an exemplary system that use such rotatable elements from the prior art. In FIG. 2, rotatable element 10 is composed of first layer 20 and second layer 22 and is, by way of example again, a generally spherical body. The surface of first layer 20 has first coating 91 at a first Zeta potential, and the surface of second layer 22 has second coating 93 at a second Zeta potential. First coating 91 and second coating 93 are chosen such that, when in contact with a dielectric fluid (not shown), first coating 91 has a net positive electric charge with respect to second coating 93. This is depicted in FIG. 2 by the xe2x80x9c+xe2x80x9d and xe2x80x9cxe2x88x92xe2x80x9d symbols respectively. Furthermore, the combination of first coating 91 and the surface of first layer 20 is non-white-colored, indicated in FIG. 2 by hatching, and the combination of second coating 93 and the surface of second layer 22 is white-colored. One skilled in the art will appreciate that the material associated with first layer 20 and first coating 91 may be the same. Likewise, the material associated with second layer 22 and second coating 93 may be the same.
FIG. 3 depicts no-field set 30. No-field set 30 is a subset of randomly oriented rotatable elements in the vicinity of vector field 24 when vector field 24 has zero magnitude. Vector field 24 is an electric field. No-field set 30, thus, contains rotatable elements with arbitrary orientations with respect to each other. Therefore, observer 28 in the case of no-field set 30 registers views of the combination of second coating 93 and the surface of second layer 22, and first coating 91 and the surface of first layer 20 (as depicted in FIG. 2) in an unordered sequence. Infralayer 26 forms the backdrop of aspect 34. Infralayer 26 can consist of any type of material, including but not limited to other rotatable elements, or some material that presents a given aspect to observer 28.
FIGS. 4 and 5 depict first aspect set 32. First aspect set 32 is a subset of rotatable elements in the vicinity of vector field 24 when the magnitude of vector field 24 is nonzero and has the orientation indicated by arrow 25. In first aspect set 32, all of the rotatable elements orient themselves with respect to arrow 25 due to the electrostatic dipole present on each rotatable element 10. In contrast to no-field set 30, observer 28 in the case of first aspect set 32 registers a view of a set of rotatable elements ordered with the non-white-colored side up (the combination of first coating 91 and the surface of first layer 20 as depicted in FIG. 2). Again, infralayer 26 forms the backdrop of the aspect. In FIGS. 4 and 5, rotatable element 10, under the influence of applied vector field 24, orients itself with respect to vector field 24 due to the electric charges present as a result of first coating 91 and second coating 93. FIG. 4 is a side view indicating the relative positions of observer 28, first aspect set 32, and infralayer 26. FIG. 5 is an alternate view of first aspect set 32 from a top perspective. In FIG. 5, the symbol "THgr" indicates an arrow directed out of the plane of the figure.
One skilled in the art will appreciate that first aspect set 32 will maintain its aspect after applied vector field 24 is removed, in part due to the energy associated with the attraction between rotatable element 10 and the substrate structure, as, for example, cavity walls (not shown). This energy contributes, in part, to the switching characteristics and the memory capability of rotating element sheet material 18, as disclosed in U.S. Pat. No. 4,126,854, hereinabove incorporated by reference, and discussed in more detail below.
A rotatable element with multivalued aspect is generally fabricated as disclosed in U.S. Pat. No. 5,919,409, herein incorporated by reference. An exemplary rotatable element 10 with multivalued aspect of the prior art is depicted in FIG. 6. Rotatable element 10 in FIG. 6 is composed of first layer 36, second layer 37 and third layer 38. The surface of third layer 38 has third coating 95 at a first Zeta potential, and the surface of first layer 36 has first coating 94 at a second Zeta potential such that third coating 95 has a net positive charge, xe2x80x9c+,xe2x80x9d with respect to first coating 94 when rotatable element 10 is in contact with a dielectric fluid (not shown). First layer 36, first coating 94, third layer 38, and third coating 95 may be chosen to be transparent to visible light and second layer 37 may be chosen to be opaque or transparent-colored to visible light, such that the rotatable element acts as a xe2x80x9clight-valve,xe2x80x9d as disclosed, for example, in U.S. Pat. No. 5,767,826, herein incorporated by reference, and U.S. Pat. No. 5,737,115, herein incorporated by reference. As above, one skilled in the art will appreciate that the material associated with first layer 36 and first coating 94 may be the same. Likewise, the material associated with third layer 38 and third coating 95 may be the same.
Rotatable elements with multivalued aspect are generally utilized in rotating element sheet material that use canted vector fields for addressing. A canted vector field is a field whose orientation vector in the vicinity of a subset of rotatable elements can be set so as to point in any direction in three-dimensional space. U.S. Pat. No. 5,717,515, herein incorporated by reference, discloses the use of canted vector fields in order to address rotatable elements. The use of canted vector fields with rotating element sheet material allows complete freedom in addressing the orientation of a subset of rotatable elements, where the rotatable elements have the addressing polarity discussed above.
One skilled in the art will appreciate that no-field set and first aspect set discussed above in FIGS. 3-5 can form the elements of a pixel, where vector field 24 can be manipulated on a pixel by pixel basis using an addressing scheme as discussed, for example, in U.S. Pat. No. 5,717,515, hereinabove incorporated by reference.
As discussed above, a useful property of rotating element sheet material is the ability to maintain a given aspect after applied vector field 24 for addressing is removed. This ability contributes, in part, to the switching characteristics and the memory capability of rotating element sheet material 18, as disclosed in U.S. Pat. No. 4,126,854, hereinabove incorporated by reference. This will be referred to as aspect stability. The mechanism for aspect stability in the above embodiments is generally the energy associated with the attraction between the rotatable elements and the containment structure, or xe2x80x9cwork function.xe2x80x9d A host of factors influence the magnitude of the energy associated with the work function including, but not limited to: surface tension of enabling fluid in contact with rotatable elements; the relative specific gravity of the rotatable elements to the enabling fluid; magnitude of charge on rotatable elements in contact with containment structure; relative electronic permittivity of enabling fluid and containment structure; xe2x80x9cstickinessxe2x80x9d of containment structure; and other residual fields that may be present. The applied vector field for addressing must be strong enough to overcome the work function in order to cause an orientation change; furthermore, the work function must be strong enough to maintain this aspect in the absence of an applied vector field for addressing.
FIG. 7 depicts an exemplary diagram of number 54, N, of rotatable elements that change orientation as a function of applied vector field 24, V of the prior art. The work function 52, Vw, corresponds to the value of applied vector field 24 when the number 54 of rotatable elements that change orientation has reached the saturation level 56, Ns, corresponding to the orientation change of all rotatable elements 10.
As mentioned above in connection with FIG. 1, the substrate of rotating element sheet material is generally an elastomer material such as silicone rubber. Because of the expense of silicone rubber, the substrate is currently the most expensive component of rotating element sheet material. Thus, in large-area-display applications of rotating element sheet material, the cost of the substrate is the primary impediment. Other qualities of rotating element sheet material, however, are ideally suited to large-area-display applications. Such qualities include: lack of sensitivity to uniform thickness, low power requirements, and a wide viewing angle.
One option that is available for large-area-display applications using rotating element sheet material without a silicone rubber substrate is based on the disclosure of U.S. Pat. No. 5,825,529, herein incorporated by reference (the ""529 patent). The rotatable elements in the ""529 patent are supported by neighboring rotatable elements in a packed relationship. However, because of the proximity of other rotatable elements with an addressing polarity, and the limited contact with a containment structure, the work function associated with an aspect of the rotating element sheet material disclosed in the ""529 patent is less pronounced than in rotating element sheet material with a cavity-containing substrate. Thus, it remains desirable to fabricate rotating element sheet material with a generalized containment structure that exhibits a suitable work function.
Accordingly, in a first embodiment of the present invention, rotating element sheet material comprises a fibrous matrix and a plurality of rotatable elements, where the plurality of rotatable elements are disposed within the fibrous matrix and in contact with an enabling fluid.
In a second embodiment of the present invention, rotating element sheet material comprises a fibrous matrix, a plurality of micro-capsules, and a plurality of rotatable elements, where each of the plurality of micro-capsules contain a subset of the plurality of rotatable elements and an enabling fluid. Furthermore, an additional supporting material may be interstitially contained in the fibrous matrix.
In a first embodiment of a method for assembling rotating element sheet material, and the rotating element sheet material so produced, the method comprises dispersing a plurality of rotatable elements into pulp slurry, drying and pressing thin layers of the pulp slurry into a fibrous matrix where the plurality of rotatable elements are interstitially contained, and infusing the fibrous matrix with an enabling fluid.
In a second embodiment of a method for assembling rotating element sheet material, and the rotating element sheet material so produced, the method comprises encapsulating a plurality of rotatable elements and enabling fluid into a plurality of micro-capsules, dispersing the plurality of micro-capsules into pulp slurry, drying and pressing thin layers of the pulp slurry into a fibrous matrix where the plurality of micro-capsules are interstitially contained. Furthermore, an additional supporting material may be introduced to the interstitial regions of the fibrous matrix.
In a third embodiment of a method for assembling rotating element sheet material, and the rotating element sheet material so produced, the method comprises pressing thin layers of pulp slurry into a fibrous matrix sheet, embossing cavities of size suitable to contain, preferably, single rotatable elements onto the surface of the fibrous matrix sheet using a mechanical embossing tool incorporating heat and pressure as needed, and subsequently drying the fibrous matrix sheet. Next, the rotatable elements are introduced to the embossed cavities by any conventional means known in the art, the fibrous matrix sheet is infused with enabling fluid, and the embossed cavities are sealed by laminating a second fibrous matrix sheet over the embossed fibrous matrix sheet. Alternatively, the embossed cavities are sealed by applying windowing material, such as glass or plastic sheets, to the embossed fibrous matrix sheet containing the rotatable elements in the embossed cavities. Also, and again alternatively, the embossed cavities can be introduced into dried fibrous matrix sheets using heat and pressure as required, and subsequently introducing the rotatable elements by any conventional means known in the art.
In a fourth embodiment of a method for assembling rotating element sheet material, and the rotating element sheet material so produced, the method comprises pressing thin layers of pulp slurry into a fibrous matrix sheet, embossing cavities of size suitable to contain, preferably, single micro-capsules containing one or more rotatable elements and enabling fluid, onto the surface of the fibrous matrix sheet using a mechanical embossing tool incorporating heat and pressure as needed, and subsequently drying the fibrous matrix sheet. Next, the micro-capsules are introduced to the embossed cavities by any conventional means known in the art, and the embossed cavities are sealed by laminating a second fibrous matrix sheet over the embossed fibrous matrix sheet. Alternatively, the embossed cavities are sealed by applying windowing material, such as glass or plastic sheets, to the embossed fibrous matrix sheet containing the micro-capsules in the embossed cavities. Also, and again alternatively, the embossed cavities can be introduced into dried fibrous matrix sheets using heat and pressure as required, and subsequently introducing the micro-capsules by any conventional means known in the art. Furthermore, an additional supporting material may be introduced to the interstitial regions of the fibrous matrix.
In a fifth embodiment of a method for assembling rotating element sheet material, and the rotating element sheet material so produced, the method comprises weaving a fibrous matrix sheet using a loom or other method of rapidly creating a fabric that enables placement of fibers in preferred patterns, where the preferred pattern in this embodiment defines preferred interstitial regions. Rotatable elements are subsequently introduced to the preferred interstitial regions of the fibrous matrix sheet by any conventional means known in the art, the fibrous matrix sheet is infused with enabling fluid, and further laminated by another sheet or windowing material, as previously described. Alternatively, the plurality of rotatable elements may be placed in a preferred spatial configuration with respect to one another and a plurality of fibers or fibrous material introduced, by electrostatic or other means, to randomly encapsulate the rotatable elements. The plurality of fibers or fibrous material thus arranged constitutes the desired fibrous matrix. The fibrous matrix is then infused with enabling fluid, and further laminated by another sheet or windowing material, as previously described.
Further still, in a sixth embodiment of a method for assembling rotating element sheet material, and the rotating element sheet material so produced, the method comprises weaving a fibrous matrix sheet using a loom or other method of rapidly creating a fabric that enables placement of fibers in preferred patterns, where the preferred pattern in this embodiment defines preferred interstitial regions. Micro-capsules containing one or more rotatable elements and enabling fluid, are subsequently introduced to the preferred interstitial regions of the fibrous matrix sheet by any conventional means known in the art and the fibrous matrix sheet is laminated by another sheet or windowing material, as previously described. Alternatively, the plurality of micro-capsules may be placed in a preferred spatial configuration with respect to one another and a plurality of fibers or fibrous material introduced, by electrostatic or other means, to randomly encapsulate the micro-capsules. The plurality of fibers or fibrous material thus arranged constitutes the desired fibrous matrix. The fibrous matrix is then laminated by another sheet or windowing material, as previously described. Furthermore, an additional supporting material may be introduced to the interstitial regions of the fibrous matrix.

Rotating element sheet material with generalized containment structure


A method for sorting images by silver salt diffusion transfer comprising. imagewise exposing a light-sensitive element comprising a light-sensitive silver halide emulsion layer, PA1 developing the light-sensitive element in the presence of a silver halide solvent using an alkaline processing composition to turn at least a part of unexposed silver halide of the light-sensitive silver halide emulsion layer into a transfer silver halide complex salt, and PA1 transferring at least a part of the silver halide complex salt to an image receiving layer comprising a silver precipitating agent to form images on the image receiving layer, PA1 wherein at least one compound represented by formula (I) is added to at least one of the light-sensitive element, an image receiving element comprising the image receiving layer, and the processing composition in an amount of at least 1.times.10.sup.-6 and less than 1.times.10.sup.-2 mol based on one mol of silver applied per unit area (m.sup.2): ##STR1## wherein Q represents an atomic group for forming a quinone ring; R represents a monovalent group which may be substituted or unsubstituted; and n is an integer of 0 to 4, whereby the maximum density can be increased for a short time.

Silver salt diffusion transfer processes are well known in the art. For example, silver salt diffusion transfer processes are described in A. Rott and E. Weyde, Photographic Silver Halide Diffusion Processes, Focal Press, London (1972); J. Stutge, V. Walworth and A. Shepp, Imaging Processes and Materials: Neblette's Eighth Edition, Vol. 8, Chapter 6, Instant Photography and Related Reprographic Processes, Van Nostrand Reinhold (1989); and G. Haist, Modern Photographic Processing, Vol. 2, Chapter 8, Diffusion Transfer, John Wiley and Sons.
Many kinds of photographic materials can be prepared by the diffusion transfer processes. Namely, it is known that a light-sensitive element in which a silver halide emulsion is applied to a support and an image receiving element in which an image receiving layer containing silver precipitation nuclei is applied to another support are superimposed on each other, and an alkaline processing composition such as a high viscosity or low viscosity alkaline processing composition containing a developing agent and a silver halide solvent, i.e., a processing element, is developed between the two elements described above, whereby a transfer image can be obtained. In practicing the present invention, this photographic material described above is advantageously used.
Another photographic material is known in which a light-sensitive layer and an image receiving layer are applied to the same support, one over the other, and a positive image can be observed through a negative image, utilizing the high covering power of the positive image, as described in U.S. Pat. No. 2,861,885. Further, a photographic material is known in which materials similar to those described above are used where the light-sensitive layer is washed out after diffusion transfer processing to obtain a positive image alone.
Furthermore, another photographic material is known in which a light-sensitive layer of a silver halide, a layer containing a light reflection material such as titanium white, and an image receiving layer containing silver precipitation nuclei are applied to a support, one over the other in this order, and processed, whereby a positive image can be obtained. Moreover, a photographic material is also known in which a light-sensitive element and an image receiving element are integrally laminated on a support, and subjected to diffusion transfer processing, whereby it can be used without separation of the light-sensitive element and the image receiving element. These photographic materials are described in detail in the literature described above.
It is widely desired to reduce the time for formation of images utilizing the silver salt diffusion transfer processes. One method for reducing the time for formation of images encompasses increasing the amount of a developing agent. According to this method, however, metallic luster is developed on the images, the images become reddish in color tone, and the images deteriorate with respect to storage quality, in particular fading quality.
Another method encompasses increasing the amount of silver halide dissolving agent. This method is however undesirable because metallic luster is developed on the images and the images become bluish.
In addition, another method encompasses increasing the amount of silver applied. However, this method has the disadvantages of lowered sensitivity and difficulty in terminating the reaction at the late stage of transfer.
A further method encompasses reducing the thickness of a spacer of an image receiving sheet for determining the developing thickness of processing element to shorten the diffusion transfer distance. According to this method, however, the images are deteriorated in density unevenness, and manufacturing and processing suitability is also lost.
Thus, in the various methods seeking to reduce the time for forming images, many disadvantages result.

Method for forming images by silver salt diffusion transfer


A data acquisition and retrieval system (11) for fishing. Input means (37) are provided for inputting: (i) geographical positioning data indicating the geographical position of a point for fishing in substantially real-time relative to a region: (ii) weather data indicating the prevailing weather conditions applying to the geographical position of the point in the region; (iii) fish data characterising the fish located at or obtained at the point; (iv) time data specifying the date, time or season corresponding to the real-time at the point; and (v) water condition data of the prevailing environment at the point. A database (60) is provided for storing the data input by the input means (35) relative to the geographical position of the point and linking the data to any previous data stored for the particular geographical position of the point. A graphical user interface accesses the linked data of the database and outputs it in an appropriate medium, usually a display that presents an image pane (141), for interpreting by a user of the system. The system is particularly suited to lobster or prawn fishing in the ocean and can be used to predict where to fish. A method for fishing based on the system is also described.

Commercial fishing is an activity that is still dependent to a very large extent on the skill and intuition of the individual fisherman.
Very successful fishermen will always try to 'think' like a fish and try to imagine where the fish would prefer to be. It is generally acknowledged that good predictions can often be made as to where to commence fishing from observing the habitats of the different species of fish, and noting historically where fish have been caught in the past and in what numbers.
In practice, however, there is also much "throwing and hoping", as well as a lot of fisherman's intuition.
Consequently, many methods have been developed to bring a more scientific approach to fishing, but these have principally been related to methods of detecting the presence of fish in a given location or the preferred habitat for the particular fish being sought. These methods have predominantly used acoustic echo sounders and other reflective "wave" techniques as the means for detecting fish and/or their habitat.
Whilst these acoustic sounders, or echo sounders as they are more commonly referred to, can detect the preferred habitat for bottom-dwelling fish life, such as Western Australian rock lobster, they are unable to actually detect such fish life on the sea or lake bottom. The reason for this is that these fish appear to be part of the sea or lake bed itself, at least in so far as the acoustic sounder is concerned.
Acoustic sounders, however, are able to detect the physical presence of middle and top-dwelling fish life. However this only occurs when the vessel containing the acoustic sounder is virtually right on top of the fish.
Thus, in general terms, acoustic sounders may at best be described as fish detectors, but certainly not fish predictors.
Sometimes top-dwelling fish can often be detected by other natural means, such as bird activity, or alternatively, visual observation of surface water activity. Mostly, however, for these types of fish, surface fishing gear has to be set up on an ad hoc basis to see if fish are present in that area.
Whilst these techniques are effective in showing the quantity in species of mid-dwelling fish in a particular area and the likely habitat for bottom-dwelling fish, they do not detect the water conditions or the environment in that area. In this respect, it is believed that water conditions are more important than habitat to a fish, and in fact fish will follow water conditions that are favourable to them. Further, it is believed that certain types or species of fish do not like sudden changes in depth, water temperature, salinity and certain other environmental aspects, but they prefer to acclimatise slowly.
Contrary to popular belief, it has been established that the water in the seas, oceans, rivers and lakes of the world are not one homogenous mixture, but rather are a collection of very different patches of water. Whilst the temperature obviously varies according to the whereabouts in the world that the body of water in question is located, it has also been discovered that the acidity, dissolved oxygen, salinity, turbidity and ORP (oxygen reduction potential) also varies significantly.
Significant variations can occur within quite close distances to one another. For example, there are known places in oceans and seas where there are fresh water springs where there is obviously low salinity proximate to and downstream or down-current of the spring and high levels of salinity at places similarly proximate to but upstream or up-current of the spring. Indeed, the change in salinity is a factor experienced proximate to a river mouth, where differences in salinity can vary considerably dependent upon the season and rainfall.
It is believed that fish, like most other living species prefer to live in the most comfortable habitat and environment that they can find. However, if that habitat and/or environment should commence to degrade, the fish will move, if possible, to a better one.
Whilst habitat can change, generally it does so over long time periods. On the other hand, environmental changes may occur very quickly. An example of this is in the ocean where certain types of seaweeds can break free and then quickly decompose. The products of decomposition can include ammonia, methane, iodine, protein and hydrogen sulphide. amongst others. These products can rapidly affect the immediate environment proximate to the decomposing seaweed.
Whereas some species of fish, such as Western Australian bream or snapper can be very tolerant of a wide range of ammonia, they find even minute levels of sulphuric acid (as produced by the hydrogen sulphide dissolving in water to form sulphurous acid, combining then with the dissolved oxygen to form sulphuric acid) to be very toxic.
On the other hand, crustaceans such as crabs and lobsters are very intolerant of small amounts of ammonia, but can live in a wide range of ORP.
Yet again, tuna is very sensitive to temperature and iodine, but is insensitive to ammonia.
When the fish find this change in the environment uncomfortable, they generally commence to move to a better one.
Similarly, a temperature of a sector of ocean can not only change significantly from one locality to another, but also from one depth to another. For instance, under certain specific conditions, it is possible to have warmer water underneath colder water.
The temperature of the water in which the fish are living is therefore an important parameter, so that in the case of fish living at, or near, the seabed, the temperature of the water at that depth is much more important than the surface water temperature. Conversely, for top-dwelling fish, the water surface temperature or the thermocline up to 6 metres deep is believed to be the more important parameter.


A modulator having low insertion and a broad operating bandwidth is disclosed. The modulator has a movable membrane that is spaced from a substrate. The reflectivity of the movable membrane, and the reflectivity of the subtrate/gap interface are unequal. In particular, relative to the membrane, the substrate has a lower reflectivity. Device finesse is dictated by the lower reflectivity "mirror," i.e., the substrate. The substrate configuration thus provides a broad operating bandwidth while the higher reflectivity membrane provides low insertion loss.

A typical Fabry-Perot cavity optical modulator has two high and equal reflectivity dielectric mirrors separated by a gap. The mirrors have a nominal thickness equal to one-quarter of the operating wavelength ("quarter-wave") of the modulator. Usually, one of the mirrors is fixed and the other is movable towards the fixed mirror. As a voltage is applied across the two mirrors, the movable mirror moves toward the fixed mirror, decreasing the gap between the mirrors. Modulator reflectivity varies with the size of the gap. See, for example, Marxer et al., "MHz Opto-Mechanical Modulator," Transducers '95--Eurosensors IX, Royal Swedish Academy of Eng. Sciences, Stockholm (June 1995), pp. 289-292.
Fabry-Perot cavity modulators are high finesse devices. Finesse is given by the expression: F=4R/(1-R).sup.2, where R is the mirror reflectivity, which is the same for both mirrors. Mirror reflectivity is given by (n.sup.2 -n.sub.o)/(n.sup.2 +n.sub.o)!.sup.2, where n is the refractive index of the material comprising the mirror and n.sub.o is the refractive index of the underlying medium, typically air. Thus, for a Fabry-Perot cavity modulator having polysilicon mirrors (n=3.5, n.sub.o =1): R=72 percent and F.apprxeq.37. Such modulators can achieve high reflectivity, i.e., low insertion loss; with theoretical device reflectivity exceeding ninety percent. Unfortunately, as a result of its high finesse, a Fabry-Perot cavity modulator typically has a relatively narrow operating bandwidth, e.g., about 5 nanometers (nm) centered around a center operating wavelength.
A lower finesse modulator is disclosed in U.S. Pat. No. 5,500,761. That modulator has a quarter-wave movable membrane separated by a gap from a substrate layer. The movable membrane incorporates a layer having a refractive index that is about equal to the square root of the substrate's refractive index. The movable membrane and the substrate have equal reflectivities. Under applied voltage, the movable membrane moves toward the substrate layer, changing the size of the gap. Changing the gap size results in a change in device reflectivity.
As previously noted, the modulator described in U.S. Pat. No. 5,500,761 has a lower finesse than a typical Fabry-Perot cavity device. In particular, membrane and substrate reflectivity R is about 31 percent and finesse is about 2.6. Such a modulator is characterized by a maximum device reflectivity of about seventy-two percent. Due to its lower finesse, that modulator advantageously possesses a significantly broader operating bandwidth than a Fabry-Perot modulator, in particular about 50 to 60 nm around a center operating wavelength.
Thus, in the prior art, one can select a modulator providing low insertion loss but narrow operating bandwidth, or higher insertion loss and broader operating bandwidth. It would be desirable, however, to have an optical modulator providing the best characteristics of the prior art modulators. Such a modulator would have the low insertion loss of the standard Fabry-Perot cavity modulator, and also possess the relatively broad operating bandwidth of the modulator disclosed in U.S. Pat. No. 5,500,761.

Micromechanical modulator having enhanced performance


A method for inspecting a phase shift photomask employs a phase shift photomask having an active pattern region. An optical property of the phase shift photomask is measured within the active pattern region, rather than, for example, a non-active pattern border region. By making the measurement within the active pattern region, performance of the phase shift mask may be properly assured. The method is particularly useful for inspecting attenuated phase shift photomasks to assure absence of side-lobes when photoexposing blanket photoresist layers.

1. Field of the Invention
The invention relates generally to methods for assuring performance of photomasks employed for fabricating microelectronic products. More particularly, the invention relates to methods for assuring performance of phase shift photomasks employed for fabricating microelectronic products.
2. Description of the Related Art
Photolithographic processes and methods are integral to the fabrication of microelectronic products. They are employed for defining patterned photoresist mask layers that are employed within various microelectronic fabrication processes. The microelectronic fabrication processes may include, but are not limited to etch processes, deposition processes and ion implantation processes.
As microelectronic product feature dimensions have decreased, it has become increasingly difficult to form patterned photoresist layers with enhanced resolution while employing conventional photomasks and conventional actinic radiation sources. Phase shift photomask constructions have arisen as a result of the need for forming such patterned photoresist layers with enhanced resolution. Phase shift photomasks differ from conventional photomasks insofar as phase shift photomasks provide for a phase shifting of actinic radiation such as to provide a higher resolution (i.e., sharper) actinic radiation intensity peak transmitted through a phase shift photomask. In turn, this provides a correspondingly enhanced resolution of a patterned photoresist layer formed employing a phase shift photomask.
Various phase shift photomask constructions are known. A particularly common phase shift photomask construction is an attenuated phase shift photomask construction. It employs transparent areas of a transparent substrate that are separated by masked regions of the substrate formed from an incompletely opaque material layer. Typically, the incompletely opaque material layer has a transmittance on the order of several percent. The thickness of the incompletely opaque material layer is selected such as to provide for a phase shift of actinic radiation when employing the attenuated phase shift photomask.
While attenuated phase shift photomasks provide particular advantage when employed within photolithographic methods, they are nonetheless not entirely without problems. In that regard, it is particularly important when employing attenuated phase shift photomasks that a transmittance of an incompletely opaque material layer be within a generally narrow range. At a transmittance level below the narrow range, enhanced resolution of transmitted actinic radiation is not realized. At a transmittance level above the narrow range, a side lobe effect of the transmitted actinic radiation may occur. The side lobe effect yields an undesirable inhomogeneous photoexposure and development of a patterned photoresist layer.
Desirable are methods for assuring optimal performance of attenuated phase shift photomasks. The invention is directed towards the foregoing object.

Phase shift photomask performance assurance method

Taiwan Semiconductor Manufacturing Co., Ltd.


A data processing apparatus and method for floating point data used in a central processing unit for a digital computer effects the four fundamental arithmetic computations of floating point data and the rounding and normalizing computations. In the case of the floating point addition or subtraction, the mantissa portion of the two floating point data and a generated round addition value are summed using a single adder and, in the case of multiplication, a sum output and a carry output of a multiplying unit and a generated round addition value are added using a single adder, so as to correct the least significant bit of the output of the adder or the round addition value is again added. Since the need of effecting readdition for rounding is small, the average processing step numbers becomes small in comparison with the conventional techniques, and, since the mantissa operation and rounding are effected using the same adder at the same time, less hardware is required.

The present invention generally relates to a method and an apparatus for processing floating point data which are used in the central processing units of digital computers, and which are adapted to effect the four fundamental arithmetic computations of floating point data, and more particularly, the four fundamental arithmetic computations of floating point data and rounding and normalizing computations in accordance with ANSI/IEEE Standard for Binary Floating Point Arithmetic P754.
The conventional floating point data adding apparatus is shown in the block diagram of FIG. 24. An addition operation is effected with respect to the mantissa data upon the subtraction of different signs or upon the addition of the same signs of two floating point data numbers. A subtraction operation is effected with respect to the mantissa data upon the addition of different signs or upon the subtraction of the same signs of two floating point data numbers. The mantissa addition or subtraction operation is determined beforehand according to the signs of the input data and according to input instructions.
Referring still to FIG. 24, reference numeral 151 denotes a register for storing the mantissa of one of two floating point data numbers having an exponent which is not smaller than the exponent of the other of the two floating-point data numbers. Reference numeral 152 denotes a resister for storing the mantissa of the other of the two floating-point data aligned to the exponent of the one of the two floating point data. Reference numeral 153 denotes a complementer which takes the 1`s complement of the output of the register 152 at the time of a subtraction operation. Reference numeral 154 denotes an adder which receives outputs of the register 151 and the complementer 153 and which executes the addition operation with the carry input (Cin) into the least significant bit being 0, and executes the substraction operation with the carry input (Cin) being 1. Reference numeral 155 denotes a register for accommodating the output of the adder 154. Reference numeral 156 denotes a shift number generating circuit for generating shift numbers for normalization of the output of the adder 154. Reference numeral 157 denotes a barrel shifter which is adapted to effect a bit shift according to a bit number output by the shift number generating circuit 156 with respect to the output of the register 155 for realizing the normalization. Reference numeral 158 denotes a register for accommodating the output of the barrel shifter 157. Reference numeral 159 denotes a round value generating circuit which is adapted to control the round addition in accordance with the value retained in the register 158, the round mode and the round precision. That is, the round value generating circuit generates a round addition value in which the least significant bit (L) corresponding to the round precision is 1 and the remaining bits are 0 when rounding up, and generates a round addition value in which all the bits are 0 when rounding down. Reference numeral 160 denotes an adder for adding the output of the register 158 and the output of the round value generating circuit 159. Reference numeral 161 denotes an R1 shifter for shifting by 1 bit the output of the adder 160 in the least significant bit direction (hereinafter referred to as rightward). Reference numeral 162 denotes a register for accommodating the mantissa of the addition or subtraction result to be obtained by the output of the R1 shifter 161.
The operation of the above-described conventional floating point data addition and subtraction will be described herebelow.
First, a case where the augend (or minuend) and the addend (or subtrahend) are the basic single precision format according to ANSI/IEEE Standard for Binary Floating-Point Arithmetic P754 (hereinafter referred to as single precision), and where the sum or difference is also rounded in single precision, will be described.
(1) Pre-Processing Start Step
The mantissa of the one of the augend (or minuend) and the addend (or subtrahend) which has an exponent which is not smaller than the exponent of the other of the augend (or minuend) and the addend (or subtrahend) is accommodated in the register 151. The mantissa of the other of the augend (or minuend) and the addend (or subtrahend) is aligned to the exponent of the mantissa stored in the register 151 and is accommodated in the register 152. The bits which have been dropped off upon the alignment are accommodated, in the register 152, collectively as a round bit (R) having the weight of 2.sup.-24 which is one bit position lower than the least significant bit (L) and a sticky bit (S) which is the logical OR of the bits of the aligned mantissa having the weight of 2.sup.-25 or lower.
(2) Step 1
The complementer 153 and the adder 154 add (or subtract) the two mantissas retained in the register 151 and the register 152 so as to accommodate the result in the register 155. Upon adding, the complementer 153 outputs into the adder 154 the output of the register 152 as is and the Cin of the adder 154 is 0. Upon subtraction, the complementer 153 applies the 1's complement of the output of the register 152 to the adder 154 and the Cin of the adder 154 is 1.
(3) Step 2
The shift number generating circuit 1546 generates the shift number for normalization of the output of the adder 154. The barrel shifter 157 effects the shifting of the output of the register 155 in accordance with the output of the shift number generating circuit 156 so as to effect the normalization shifting operation with respect to the computation result of the step 1. At this time, the barrel shifter 157 generates the shift results down to the least significant bit (L), the round it (R) having the weight of the 2.sup.-24 lower by one unit of the least significant bit, a sticky bit (S) which is the logical OR of the bits having the weight of 2.sup.-25 or lower and accommodates them in the register 158.
(4) Step 3
The round value generating circuit 159 generates the round addition value in accordance with the least significant bit (L) retained in the register 158, the round bit (R), the sticky bit (S), the round mode, the round precision and the sign of the operation result. The generated round addition value has a value in which the bit having the weight of 2.sup.-23 is 1 and the remaining bits are 0 when the round addition signal is 1, and a value in which all the bits are 0 when the round addition signal is 0, in accordance with the input, output relation chart shown in FIG. 11. RM, RP, RN, RZ denote in order the directed rounding toward the nearest even mode stipulated in the ANSI/IEEE Standard for Binary Floating-Point Arithmetic P754. The adder 160 adds the output of the register 158 and the output of the round value generating circuit 159. The R1 shifter 161 shifts, by one bit rightward, the output of the adder 160 when overflow has been generated in the adder 160, and otherwise accommodates the output of the adder 160 as is in the register 162 so as to complete the processing.
A case where the augend (or minuend) and the addend (or subtrahend) are the basic double precision format according to ANSI/IEEE Standard for Binary Floating-Point Arithmetic P754 (hereinafter referred to simply as double precision), and where the sum or difference is also rounded in double precision, will be described.
(1) Pre-Processing Start Step
The mantissa of the one of the augend (or minuend) and the addend (or subtrahend) which has an exponent which is not smaller than the exponent of the other of the augend (or minuend) and the addend (or subtrahend) is accommodated in the register 151. The mantissa of the other of the augend (or minuend) and the addend (or subtrahend) is aligned to the exponent of the mantissa stored in the register 151 and is accommodated in the register 152. The bits which have been dropped off upon the alignment are accommodated in the register 152 collectively as a round bit (R) having the weight of 2.sup.-53 which is one bit position lower than the least significant bit (L) and a sticky bit (S) which is the logical OR of the bits of the aligned mantissa having the weight of 2.sup.-54 or lower.
(2) Step 1
The complementer 153 and the adder 154 add (or subtract) the two mantissas retained in the register 151 and the register 152 so as to accommodate the result in the register 155. For adding, the complementer 153 outputs into the adder 154 the output of the register 152 as is and the Cin of the adder 154 is 0. For subtracting, the complementer 153 applies the 1's complement of the output of the register 152 to the adder 154 and the Cin of the adder 154 is 1.
(3) Step 2
The shift number generating circuit 156 generates the shift number for normalization of the output of the adder 154. The barrel shift 157 effects the shifting of the output of the register 155 in accordance with the output of the shift number generating circuit 156 so as to effect the normalization shifting operation with respect to the operation result of the step 1. At this time, the barrel shifter 157 generates the shift results down to the least significant bit (L), the round bit (R) having the weight of the 2.sup.-53 lower by one unit of the least significant bit, a sticky bit (S) which is the logical OR of the bits having the weight of 2.sup.-54 or lower and accommodates them in the register 158.
(4) Step 3
The round value generating circuit 159 generates the round addition value in accordance with the least significant bit (L) retained in the register 158, the round bit (R), the sticky bit (S), the round mode, the round precision and the sign of the operation result. The generated round addition value a value in which a bit having the weight of 2.sup.-52 1 is and the remaining bits are 0 when the round addition signal is 1, and a value in which all the bits are 0 when the round addition signal is 0, in accordance with the input, output relation chart shown in FIG. 11. The adder 160 adds the output of the register 158 and the output of the round value generating circuit 159. The R1 shifter 161 shifts by one bit rightward the output of the adder 160 when overflow has been generated in the adder, and otherwise accommodates the output of the adder 160 as is in the register 162 so as to complete the processing.
The conventional floating point data multiplication apparatus is shown in the block diagram of FIG. 25.
In FIG. 25, reference numeral 251 denotes a multiplicand register for retaining the multiplicand which consists of a 1 bit signal portion 251s, an 11 bit exponent portion 251e, and a 53 bit mantissa portion 251f. Reference numeral 252 denotes a multiplier register for retaining the multiplier which consists of a 1 bit sign portion 251s, an 11 bit exponent portion 252e, and a 53 bit mantissa portion 252f. The most significant bit of the multiplicand register mantissa portion 251f and the multiplier register mantissa portion 252f is a so-called "hidden bit" having the weight of 2.sup.0 and is 1 in the normalized number. Except for this bit, the multiplicand register 251 and the multiplier register 252 both conform to the double precision format. Reference numeral 253 denotes a sign generating circuit for reading the signs of the multiplicand and multiplier from the multiplicand register sign portion 251s and the multiplier register sign portion 252s so as to generate the sign of the produce. Reference numeral 254 denotes an exponent adder of 11 bits for reading the exponents of the multiplicand and the multiplier from the multiplicand register exponent portion 251e and the multiplier register exponent portion 252e so as to compute the exponent of the product. Reference numerals 255 and 256 denote selectors of 11 bits for respectively selecting the two inputs of the exponent adder 254. Reference numeral 257 denotes a latch of 11 bits for retaining the output of the exponent adder 254 to be input into the exponent adder 254 again through the selector 255. Reference numeral 258 denotes a bias correction value generating circuit for generating the bias (deviation) of 11 bits in a step of computing the exponent of the product. Reference numeral 259 denotes a normalized correction value generating circuit for generating a constant for increasing by 1 the exponent through the normalization of a 1 bit shift of the mantissa of the product. Reference numeral 260 denotes a multiplicand upper, lower selecting circuit for reading the multiplicand register mantissa portion 251f, and selecting and outputting the upper 27 bits or the lower 27 bits (the most significant bit at this time is 0). Reference numeral 261 denotes a multiplier upper, lower selecting circuit for reading the multiplier resister mantissa portion 252f, and selecting and outputting the upper 27 bits or the lower 27 bits (the most significant bit at this time is 0). Reference numeral 262 denotes a multiplying unit for multiplying the output of the multiplicand upper, lower selecting circuit 260 of 27 bits by the output of the multiplier upper, lower selecting circuit 261 of 27 bits so as to respectively output the sum of 54 bits and the carry of 54 bits. Reference numerals 263 and 264 denote latches of 54 bits for retaining the sum output and the carry output of the multiplying unit 262. Reference numeral 265 denotes a product generating adder of 54 bits for adding the sum output and carry output of the multiplying unit 262 retained in the latch 263 and the latch 264. Reference numeral 266 denotes a latch of 54 bits for retaining the output of the product generating adder 265. Reference numeral 267 denotes a round adding value generating circuit for generating the constant in the adding operation for rounding the mantissa of the product into the single precision or the double precision. Reference numeral 268 denotes a selector of 54 bits for selecting the output of the round addition value generating circuit 267 or the value of the latch 266. Reference numeral 269 denotes a mantissa adder of 54 bits for adding the output of the selector 268 and the value to be retained in the latch 273 to be described later. Reference numeral 270 denotes a logical OR gate for computing the logical OR of the overflow from the most significant bit of the product generating adder 265 and the overflow from the most significant bit of the mantissa adder 269. Reference numeral 271 denotes a shifter of 54 bits for shifting by 0 bits, 1 bit or 26 bits the output of the mantissa adder 269 in the least significant bit direction. Reference numeral 272 denotes a sticky bit generating circuit for inputting the lower 30 bits of the output of the mantissa adder 269 and the shift overflow from the least significant bit of the 26 bits in the shifter 271 so as to generate the sticky bit in accordance with the single precision rounding or double precision rounding. Reference numeral 273 denotes a latch of 54 bits for retaining the output of the shifter 271. Reference numeral 274 is a product register for retaining the product which consists of a 1 bit sign portion 274s, an 11 bit exponent portion 274e, and a 53 bit mantissa portion 274f. The most significant bit of the product register mantissa portion 274f is also a so-called "hidden bit" having the weight of 2.sup.0 and is 1 in the normalized number. Except for this bit, the product register 274 conforms to the double precision format.
FIG. 26 is a performance illustrating chart showing the constant generated by the round addition value generating circuit 267 shown in FIG. 25. A round addition value D is generated in which only the 24th bit from the most significant bit is 1 and the remaining bits are 0, and a round addition value E is generated in which only the 2nd bit from the least significant bit is 1 and the remaining bits are 0.
The operation of the conventional floating point data multiplying apparatus will be described hereinafter.
First, a case where the multiplicand and the multiplier are the single precision, and where the product is also round in the single precision, will be described hereinafter with the use of the operation flow chart of the single precision multiplication shown in FIG. 27. FIG. 27 shows the contents of the operation of each of the processing steps of the exponent adder 254, the multiplying unit 262, the product generating adder 265, the mantissa adder 269, and the shifter 271.
(1) Pre-Processing Start Step
The multiplicand and the multiplier of the single precision are expanded into the double precision and are accommodated respectively into the multiplicand register 251 and the multiplier register 252. At this time, the multiplicand register exponent portion 251e and the multiplier register exponent portion 252e are both converted into the biased expression of the double precision (real exponent value=exponent value -1023.sub.(10)), with 0 being filled in the lower 29 bits of the multiplicand register mantissa portion 251f and the multiplier register mantissa portion 252f. The latch 273 is cleared to 0. Here, the subscript (10) denotes that the decimal number expression is used.
(2) Step 1
By operation of the selector 255 and the selector 256, the exponents of the multiplicand and the multiplier are inputted from the multiplicand register exponent portion 251e and the multiplier register exponent portion 252e into the exponent adder 254 where they are added to accommodate the addition result into the latch 257. The multiplicand upper, lower selecting circuit 260 reads and outputs the upper 27 bits of the multiplicand register mantissa portion 251f (all the effective bits of the mantissa portion of the multiplicand are included therein), and the multiplier upper, lower selecting circuit 261 reads and outputs the upper 27 bits of the multiplier register mantissa portion 252f (all the effective bits of the mantissa portion of the multiplier are included therein). The multiplier 262 executes the multiplication in accordance with the inputs from the multiplicand upper, lower selecting circuit 260 and the multiplier upper, lower selecting circuit 261 so as to accommodate the sum output and the carry output respectively into the latch 263 and the latch 264. At the same time, in the sign generating circuit 253, the signs of the multiplicand and the multiplier are read from the multiplicand register sign portion 251 s and the multiplier register sign portion 252s so as to take the exclusive OR of both, and to generate the sign of the product so as to be accommodated in the product register sign portion 724s.
(3) Step 2
As the value retained by the latch 257 is the sum of the biased exponents of the multiplicand and the multiplier, the biasing is double applied. Therefore, -1023 (actually the 2's complement expression is used) from the bias correction value generating circuit 258 is outputted. By operation of the selector 255 and the selector 256, the value of the latch 257 and the output of the bias correction value generating circuit 258 are added in the exponent adder 254 and accommodated again into the latch 257. The product generating adder 265 adds the sum output and the carry output-of the multiplying unit 262 respectively retained in the latch 263 and the latch 264 to accommodate the addition result into the latch 266.
(4) Step 3
The mantissa adder 269 adds the value retained in the latch 266 and output by selector 268 and the value 0 of the latch 273. When overflow from the product generating adder 265 exists at the step 2, namely, when the product of the mantissa is 2 or more, the shifter 271 shifts (at this time, 1 is buried at the most significant bit), in the 1 bit least significant bit direction, the output from the mantissa adder 269 for normalization so as to accommodate the result into the latch 273. By operation of the selector 255 and the selector 256, the exponent adder 254 adds the value of the latch 257 and the constant 1 output by the normalized correction value generating circuit 259 so as to be accommodated again into the latch 257. When overflow from the product generating adder 265 at the step 2 does not exist, namely, when the product of-the mantissa portion is or more and less than 2, the shifter 271 accommodate it as is into the latch 273 without shifting of the output from the mantissa adder 269, since normalization is not required. By operation of the selector 255 and the selector 256, the exponent adder 254 outputs the value of the latch 257 as is and accommodates it again into the latch 257. The sticky bit generating circuit 272 takes the logical OR of the lower 30 bits of the output of the mantissa adder 269 that the sticky bit is 1 if a bit having the value 1 exists in the 30 bits, and the sticky bit is 0 if all 30 bits are 0.
(5) Step 4
The round addition value generating circuit 267 decides whether the round addition is necessary in accordance with the rounding mode, the value of the 25th bit from the most significant bit which is a round bit of the value retained in the latch 273, the sign of the product output by the sign generating circuit 253 (necessary when the round mode is a round toward plus mode and a round toward minus mode) and the value of the sticky bit by the sticky bit circuit 272. The circuit 267 outputs the round addition value D shown in FIG. 26 when the round addition is necessary, and outputs 0 when the round addition is not necessary. By operation of the selector 268, the mantissa adder 269 adds the round addition value output by the round addition value generating circuit 267 and a value retained in the latch 273. At this time, when overflow is caused in the mantissa adder 269, namely, the mantissa is 2 or more by rounding up, the shifter 271 shifts by 1 bit in the least significant bit direction the output from the mantissa adder 269 again for normalization (at this time, 1 is buried at the most significant bit). By operation of the selector 255 and the selector 256, the exponent adder 254 adds the value of the latch 257 and the constant 1 output by the normalized correction value generating circuit 259. When the overflow is not caused in the mantissa adder 269, namely, the mantissa value is 1 or more and less than 2, the shifter 271 outputs the output, as is, from the mantissa adder 269 without shifting since it is not necessary to effect normalization. By operation of the selector 255 and the selector 256, the exponent adder 254 also outputs the value, as is, of the latch 257. In any case, the output of the exponent adder 254 is accommodated into the product register exponent portion 274e, the lower 29 bits of the 53 bits except for the least significant bit of the output of the shifter 271 are masked into 0, are accommodated in the product register mantissa portion 274f so as to complete the processing.
A case where the multiplicand and the multiplier are the double precision, and where the product is also rounded in the double precision, will be described with reference to the operation flow chart of the double precision multiplication shown in FIG. 28. FIG. 28 shows the contents of the operations of each processing step of the exponent adder 254, the multiplying unit 262, the product generating adder 265, the mantissa adder 269, and the shifter 271.
(1) Pre-Processing Start Step
The multiplicand and the multiplier in double precision are respectively accommodated in the multiplicand register 251 and the multiplier register 252. At this time, the multiplicand register exponent portion 251e and the multiplier register exponent portion 252e are both converted into the biased expression of the double precision (real exponent value =exponent value -1023.sub.(10)). The latch 273 is cleared to 0.
(2) Step 1
By operation of the selector 255 and the selector 256, the exponents of the multiplicand and the multiplier are inputted from the multiplicand register exponent portion 251e and the multiplier register exponent portion 252e into the exponent adder 254 where they are added so as to accommodate the addition result into the latch 257. The multiplicand upper, lower selecting circuit 260 reads and outputs the lower 27 bits (the most significant bit is 0) of the multiplicand register mantissa portion 251f, and the multiplier upper, lower selecting circuit 261 reads and outputs the lower 27 bits (the most significant bit is 0) of the multiplier register mantissa portion 252f. The multiplying unit 262 executes the multiplication in accordance with the inputs from the multiplicand upper, lower selecting circuit 260 and the multiplier upper, lower selecting circuit 261 so as to accommodate the sum output and the carry output respectively into the latch 263 and the latch 264. At the same time, in the sign generating circuit 253, the signs of the multiplicand and the multiplier are read from the multiplicand register sign portion 251s and the multiplier register sign portion 252s to take the exclusive OR of both, and to generate the sign of the product so as to be accommodated to the product register sign portion 724s.
(3) Step 2
As the value retained by the latch 257 is the sum of the biased exponents of the multiplicand and the multiplier, the biasing is doubly applied. Therefore, -1023 (actually 2's complement expression is used) in outputted from the bias correction value generating circuit 258. By operation of the selector 255 and the selector 256, the value of the latch 257 and the output of the bias correction value generating circuit 258 in the exponent adder 254 are added and are accommodated again into the latch 257. The product generating adder 265 adds the sum output and the carry output of the multiplying unit 262 retained in the latch 263 and the latch 264 so as to accommodate the addition result into the latch 266. The value accommodated in the latch 266 is the least significant partial product. At the same time, the multiplicand upper, lower selecting circuit 260 reads and outputs the lower 27 bits (the most significant bit is 0) of the multiplicand register mantissa portion 251f. The multiplier upper, lower selecting circuit 261 reads and outputs the upper 27 bits of the multiplier register mantissa portion 252f. The multiplying unit 262 executes the multiplication in accordance with the inputs from the multiplicand upper, lower selecting circuit 260 and the multiplier upper, lower selecting circuit 261 so as to accommodate the sum output and the carry output respectively into the latch 263 and the latch 264.
(4) Step 3
The mantissa adder 269 adds the value retained in the latch 266 and output by the selector 268 and the value 0 of the latch 273. The shifter 271 shifts by 26 bits in the least significant bit direction the data of 55 bits which consists of 54 bits of the addition result in the mantissa adder 269 and 1 bit being added onto the most significant bit side, where the logical OR of the overflow from the product generating adder 265 at the step 2, and the overflow from the mantissa adder 269 at the step 3 was taken in the "OR" gate 270, so as to accommodate the result into the latch 273. The product generating adder 265 adds the sum output and the carry output of the multiplying unit 262 retained in the latch 263 and the latch 264 so as to accommodate the addition result. The value accommodated in the latch 266 is a first intermediate partial product. At the same time, the multiplicand upper, lower selecting circuit 260 reads and outputs the upper 27 bits of the multiplicand register mantissa portion 252f, and the multiplier upper, lower selecting circuit 261 reads and outputs the lower 27 bits (the most significant bit is 0) of the multiplier register mantissa portion 252f. The multiplying unit 262 executes the multiplication in accordance with the inputs from the multiplicand upper, lower selecting circuit 260 and the multiplier upper, lower selecting circuit 261 so as to accommodate the sum output and the carry output respectively into the latch 263 and the latch 264.
(5) Step 4
The mantissa adder 269 adds the value retained in the latch 266 and output by the selector 268 and the output of the shifter 271 retained in the latch 273. The shifter 271 outputs, without shifting, 54 bits of the addition result, as is, in the mantissa adder 269 so as to be accommodated in the latch 273. The product generating adder 265 adds the sum output of the multiplying unit 262 retained in the latch 263 and the latch 264, and the carry output so as to accommodate the addition result. The value accommodated in the latch 266 is a second intermediate partial product. At the same time, the multiplicand upper, lower selecting circuit 260 reads and outputs the upper 27 bits of the multiplicand register mantissa portion 251f, and the multiplier upper, lower selecting circuit 261 reads and outputs the upper 27 bits-of the multiplier register mantissa portion 252f. The multiplying unit 262 executes the multiplication in accordance with the inputs from the multiplicand upper, lower selecting circuit 260 and the multiplier upper, lower selecting circuit 261 so as to accommodate the sum output and the carry output respectively in the latch 263 and the latch 264.
(6) Step 5
The mantissa adder 269 adds the value retained in the latch 266 and output by the selector 268 and the output of the shifter 271 retained in the latch 273. The shifter 271 shifts by 26 bits in the least significant bit direction the data of 55 bits, which consists of 54 bits of the addition result in the mantissa adder 269 and 1 bit being added onto the most significant bit side, where the logical OR of the overflow from the product generating adder 265 at the step 4 and the overflow from the mantissa adder 269 at the step 5 is taken in the "OR" gate 270, so as to accommodate the result into the latch 273. The product generating adder 265 adds the sum output and carry output of the multiplying unit 262 retained in the latch 263 and the latch 264 so as to accommodate the addition result. The value accommodated in the latch 266 is the most significant partial product.
(7) Step 6
The mantissa adder 269 adds the value retained in the latch 266 and output by the selector 268 and the output of the shift 271 retained in the latch 273. When the logical OR of the overflow from the product generating adder 265 at the step 5 and the overflow from the mantissa adder 269 at the step 6 being taken at the logical OR gate 270 are 1, namely, the product of the mantissa portion is 2 or more, the shifter 271 shifts the output from the mantissa adder 269 (at this time, 1 is buried in the most significant bit) by 1 bit in the least significant bit direction so as to accommodate the result in the latch 273. The exponent adder 254 adds the value of the latch 257 and the constant 1 output by the normalized correction value generating circuit 259 so as to be accommodated again into the latch 257. When the value with the logical OR being taken in the logical OR gate 270 is 0, namely, the product of the mantissa portion is 1 or more and less than 2, the output from the mantissa adder 269 is accommodated as is into the latch 273 without shifting since normalization is not necessary. The exponent adder 254 outputs the value of the latch 257 as is by operation of the selector 255 and the selector 256 so as to be accommodated again into the latch 257. The sticky bit generating circuit 272 takes the logical OR of 52 bits with the shift overflow from the least significant bit of 26 bits in the shifter 271 at the step 3 and the shift overflow from the least significant bit of 26 bits in the shifter 271 at the step 5 being combined in it. The sticky bit output is 1 if a bit having a value 1 exists in the 52 bits, and the sticky bit output is 0 if all 52 bits are 0.
(8) Step 7
The round addition value generating circuit 267 determines whether round addition is necessary in accordance with the rounding mode, the value of the least significant bit which is the round bit of the value retained in the latch 273, the sign of the product output by the sign generating circuit 253 (necessary when the round mode is a round toward plus mode and a round toward minus mode) and the value of the sticky bit output by the sticky bit generating circuit 272. The round addition value E shown in FIG. 26 is output when the round addition is necessary, and 0 is output when the round addition is not necessary. By operation of the selector 268, the mantissa 269 adds the round addition value output by the round addition value generating circuit 267 and the value retained by the latch 273. At this time, when overflow is caused in the mantissa adder 269, namely, the mantissa is 2 or more by the rounding up, the shifter 271 shifts by 1 bit in the least significant bit direction the output from the mantissa adder 269 again for normalization (at this time, 1 is buried at the most significant bit). By operation of the selector 255 and the selector 256, the exponent adder 254 adds the value of the latch 257 and the constant 1 output by the normalized correction-value generating circuit 259. When overflow is not caused in the mantissa adder 269, name)y, the mantissa is 1 or more and less than 2, the shifter 1 outputs the value, as is, output from the mantissa adder 269 without shifting, since it is not necessary to effect the normalization. By operation of the selector 255 and the selector 256, the exponent adder 254 also outputs the value, as is, of the latch 257. In any case, the output of the exponent adder 254 is accommodated into the product register exponent portion 274e, and the 53 bits, the output of the shifter 271 except for th least significant bit, are accommodated in the product register mantissa portion 274f so as to complete the processing.
Also, in the conventional floating point data division apparatus, the value of the exponent portion of the divisor is first subtracted from the value of the exponent portion of the dividend so as to obtain the exponent portion of a quotient. As the subtraction values are the difference between the biased exponents, the bias is offset. Therefore, the bias value is added to the subtraction value so as to generate the exponent portion of the quotient correctly biased.
However, in the conventional floating point data addition and subtraction apparatus, the position of the least significant bit (L) for adding the round addition value is fixed for the first time after normalization shift by the barrel shifter 157, and not fixed with respect to the input and output in the adder 154, thus normally resulting in the processing flow of addition or subtraction, normalization, and rounding. Therefore, the addition and subtraction of two mantissas and the addition of the round addition value are required to be respectively effected independently. At least four processing steps in number including the alignment are required as shown in FIG. 8 (a). Also, as the addition or subtraction of the former are effected by the adder 154, and the addition of the latter is effected by the adder 160, two adders are required which presents a problem With respect to increasing the amount of necessary hardware.
In the conventional floating point data multiplication apparatus, the addition of the sum and the carry from the multiplying unit 262, the addition for accumulating the partial products, and the addition of the round addition values are respectively effected independently, and four processing steps are required in the case of the single precision multiplication, and seven processing steps are required in the case of the double precision multiplication. Also, the addition of one former is effected with the product generating adder 265, and the addition of the latter two are effected by the mantissa adder 269, thus requiring two adders, which is a problem in that an increased amount of hardware is needed.
Also, in the conventional floating point data division apparatus, the subtraction value for simply subtracting the exponent portion of the dividend and the exponent portion of the divisor is offset in bias, and a later step for correcting the bias becomes necessary, which presents a problem in that the hardware is required for effecting the bias correction.

Floating point data processing apparatus which simultaneously effects summation and rounding computations

Matsushita Electric Industrial Co., Ltd.


A rail fastener driver apparatus for driving fasteners into ties of a railroad track includes a fastener driving mechanism with a reciprocating element for engaging a fastener and driving it into a tie, a fastener magazine configured for accommodating a plurality of rail fasteners and feeding them sequentially for driving by the element, a fastener feeder mechanism including a fastener holder configured for movement between a first position sequentially receiving one fastener from the magazine and a second position placing the fastener in a driving position for engagement by the driving element and the fastener feeder mechanism configured for lowering and axially rotating the fastener from the first position to the second position. An obstacle accommodation device, and a method of driving rail fasteners are also provided.

The present invention relates generally to railroad right-of-way maintenance machinery, and specifically to machinery used for driving fasteners into rail ties for securing rail tie plates and rails to the ties.
Rail fasteners as contemplated herein include cut spikes, lag screws, hairpin spikes and other types of rail fasteners used for retaining tie plates upon ties, and rails upon tie plates, as are known to skilled practitioners. In some cases in the specification, "spikes" may be used interchangeably with "rail fasteners". The use of the term "spikes" is not intended to limit the scope of the present invention.
During the course of railroad maintenance work, it is common that existing rail fasteners are removed for replacement of rail ties, tie plates, rails and for other maintenance operations. Once the desired maintenance is complete, the fasteners need to be reinstalled. Several types of rail fastener applicators or drivers are known, and suitable models are described in commonly assigned U.S. Pat. Nos. 4,579,061; 4,777,885; 5,191,840 and 5,671,679, all of which are incorporated by reference herein, and all of which are assigned to Nordco Inc. of Milwaukee, Wis.
Such rail fastener driving machines typically include a frame which is either self-propelled or towable along the track, a rail fastener driving apparatus with a fastener driving mechanism such as a fluid power cylinder provided with a reciprocating element for impacting a fastener and driving it into a tie, a fastener magazine configured for accommodating a plurality of rail fasteners and feeding them sequentially for driving by the element, a fastener feeder mechanism configured for conveying fasteners sequentially from the magazine to a location in operational relationship to the driving element.
Such devices typically have a travel position, where the fastener feeder mechanism is held sufficiently above the track to avoid damage by obstacles including the track itself. In addition, during operation, the units typically move between a first or fastener loading position, and a fastener driving position. It is important, for maintaining desired productivity rates, that the latter two positions are closer to the track. To avoid damage to the mechanisms, such units are designed for operation so that either travel is prohibited when these mechanisms are in the latter two positions, or the mechanisms automatically rise to the travel position when the unit begins to move to the next location.
While protecting the typically complicated rail fastener handling and driving mechanisms, this operational precautions tend to limit productivity as measured by the rate of fastener-driving by a particular unit.
Thus, there is a need for a rail fastener driving mechanism which enables greater fastener driving productivity while protecting the fastener driving mechanisms.
There is also a need for a rail fastener driving mechanism which is configured so that the unit can be transported along the track with the fastener driving mechanism in a position closer to the track for more rapid fastener driving and greater productivity.

Rail fastener driver with enhanced fastener positioning


The present invention is directed to a process for producing and separating oil. An aqueous fluid having an ionic content of at most 0.15 M and a total dissolved solids content of from 200 ppm to 10,000 ppm is introduced into an oil-bearing formation. Oil and water are produced from the formation subsequent to the introduction of the aqueous fluid into the formation. A demulsifier and a brine solution having a total dissolved solids content of greater than 10,000 ppm are mixed with the oil and water produced from the formation. Oil is then separated from the mixture of oil, water, demulsifier, and brine solution.

Only a portion of oil present in an oil-bearing formation is recoverable as a result of the natural pressure of the formation. The oil recovered from this "primary" recovery typically ranges from 5% to 35% of the oil in the formation. Enhanced oil recovery methods have been developed to increase the amount of oil that may be recovered from an oil-bearing formation above and beyond that recovered in primary recovery.
Water-flooding, in which water is injected through an injection well into an oil-bearing formation to mobilize and drive oil through the formation for production from a production well, is a widely used method of secondary recovery used to increase the amount of oil recovered from a formation beyond primary recovery. Recently, water-flooding utilizing water having low salinity has been utilized to increase the amount of oil recovered from a formation relative to the amount of oil recovered in a conventional higher salinity water-flood. Low salinity water may be used in place of higher salinity water conventionally used in a water-flood in a secondary recovery, or low salinity water may be used after a conventional higher salinity water-flood to incrementally increase oil recovery over that of the initial water-flood in a tertiary recovery process.
Low salinity water utilized in low salinity water-flooding has a lower ionic strength than connate water present in the formation, typically having an ionic strength of 0.15 M or less and having a total dissolved solids ("TDS") content of from 200 parts per million ("ppm") to 10,000 ppm and a multivalent cation content that is less than the multivalent cation content of the connate water. Injection of low salinity water into a formation may reduce the ionic bonding of oil to the formation within pores in the formation by double layer expansion, leading to a reduction in the rock's adsorption capacity for hydrocarbons. This increases the mobility of the oil in the formation by making the surface of the pores of the formation more water-wet and less oil-wet, permitting the mobile oil to be removed from the pores in which it resides and to be driven to a production well for production from the formation.
In an enhanced oil recovery process utilizing water-flooding, oil and water, and typically gas as well, are produced from the formation together. The oil, water, and gas are separated in a separator to recover the oil from the produced water and gas. Free water is separated and removed from the oil by phase separation. At least a portion of the oil and a portion of the water, however, may be intimately mixed in an emulsion. The emulsion may be treated in a coalescer that helps break the emulsion by causing water in the emulsion (in a water-in-oil emulsion) or oil in the emulsion (in a oil-in-water emulsion) to coalesce and phase separate. The separated phases may then be recovered separately.
Improved processes for separating oil and water produced from an oil-bearing formation by a low salinity water-flood enhanced oil recovery process are desirable.

This patent is subject to a terminal disclaimer.

Process for producing and separating oil


A fitting for a table leg of a folding table which can be folded in when the table is not in use, wherein the table leg is pivotally mounted in a bearing component attached underneath the table plate. In the position of use of the table, the table leg can be locked. A drop lever is pivotally mounted in the bearing component. When the table leg is folded out into the position of use of the table, the drop lever automatically as a result of gravity locks the table leg against a stop serving as an abutment and automatically unlocks the table leg when the table is placed in a stacking position.

1. Field of the Invention
The present invention relates to a fitting for a folding table.
2. Description of the Related Art
Fittings for table legs which can be folded in when the table is not in use are known in the art. The table leg is pivotally mounted in a bearing component attached underneath the table plate. In the position of use of the table, the table leg can be locked.