Apparatus and method for producing fibrous materials in which the apparatus includes an electrospinning element configured to electrospin a substance from which the fibers are to be composed by an electric field extraction of the substance from a tip of the electrospinning element, a collector disposed from the electrospinning element and configured to collect the fibers, a chamber enclosing the collector and the electrospinning element, and a control mechanism configured to control a gaseous environment in which the fibers are to be electrospun.

1. Field of the Invention
This invention relates to the field of electrospinning fibers from polymer solutions.
2. Background of the Invention
Nanofibers are useful in a variety of fields from clothing industry to military applications. For example, in the biomaterial field, there is a strong interest in developing structures based on nanofibers that provide a scaffolding for tissue growth effectively supporting living cells. In the textile field, there is a strong interest in nanofibers because the nanofibers have a high surface area per unit mass that provides light but highly wear-resistant garments. As a class, carbon nanofibers are being used for example in reinforced composites, in heat management, and in reinforcement of elastomers. Many potential applications for nanofibers are being developed as the ability to manufacture and control the chemical and physical properties improves.
Electrospray/electrospinning techniques can be used to form particles and fibers as small as one nanometer in a principal direction. The phenomenon of electrospray involves the formation of a droplet of polymer melt at an end of a needle, the electric charging of that droplet, and an expulsion of parts of the droplet because of the repulsive electric force due to the electric charges. In electrospraying, a solvent present in the parts of the droplet evaporates and small particles are formed but not fibers. The electrospinning technique is similar to the electrospray technique. However, in electrospinning and during the expulsion, fibers are formed from the liquid as the parts are expelled.
Glass fibers have existed in a sub-micron range for some time. Small micron diameter fibers have been manufactured and used commercially for air filtration applications for more than twenty years. Polymeric melt blown fibers have more recently been produced with diameters less than a micron. Several value-added nonwoven applications, including filtration, barrier fabrics, wipes, personal care, medical and pharmaceutical applications may benefit from the interesting technical properties of nanofibers and nanofiber webs. Electrospun nanofibers have a dimension less than 1 μm in one direction and preferably a dimension less than 100 nm in this direction. Nanofiber webs have typically been applied onto various substrates selected to provide appropriate mechanical properties and to provide complementary functionality to the nanofiber web. In the case of nanofiber filter media, substrates have been selected for pleating, filter fabrication, durability in use, and filter cleaning considerations.
A basic electrospinning apparatus 10 is shown in FIG. 1 for the production of nanofibers. The apparatus 10 produces an electric field 12 that guides a polymer melt or solution 14 extruded from a tip 16 of a needle 18 to an exterior electrode 20. An enclosure/syringe 22 stores the polymer solution 14. Conventionally, one end of a voltage source HV is electrically connected directly to the needle 18, and the other end of the voltage source HV is electrically connected to the exterior electrode 20. The electric field 12 created between the tip 16 and the exterior electrode 20 causes the polymer solution 14 to overcome cohesive forces that hold the polymer solution together. A jet of the polymer is drawn by the electric field 12 from the tip 16 toward the exterior electrode 20 (i.e. electric field extracted), and dries during flight from the needle 18 to the exterior electrode 20 to form polymeric fibers. The fibers are typically collected downstream on the exterior electrode 20.
The electrospinning process has been documented using a variety of polymers. One process of forming nanofibers is described for example in Structure Formation in Polymeric Fibers, by D. Salem, Hanser Publishers, 2001, the entire contents of which are incorporated herein by reference. By choosing a suitable polymer and solvent system, nanofibers with diameters less than 1 micron have been made.
Examples of fluids suitable for electrospraying and electrospinning include molten pitch, polymer solutions, polymer melts, polymers that are precursors to ceramics, and/or molten glassy materials. The polymers can include nylon, fluoropolymers, polyolefins, polyimides, polyesters, and other engineering polymers or textile forming polymers. A variety of fluids or materials besides those listed above have been used to make fibers including pure liquids, solutions of fibers, mixtures with small particles and biological polymers. A review and a list of the materials used to make fibers are described in U.S. Patent Application Publications 2002/0090725 A1 and 2002/0100725 A1, and in Huang et al., Composites Science and Technology, vol. 63, 2003, the entire contents of which are incorporated herein by reference. U.S. Patent Appl. Publication No. 2002/0090725 A1 describes biological materials and bio-compatible materials to be electroprocessed, as well as solvents that can be used for these materials. U.S. Patent Appl. Publication No. 2002/0100725 A1 describes, besides the solvents and materials used for nanofibers, the difficulties of large scale production of the nanofibers including the volatilization of solvents in small spaces. Huang et al. give a partial list of materials/solvents that can be used to produce the nanofibers.
Despite the advances in the art, the application of nano-fibers has been limited due to the narrow range of processing conditions over which the nano-fibers can be produced. Excursions either stop the electrospinning process or produce particles of electrosprayed material.

Electrospinning in a controlled gaseous environment


An improved oxazolidine-based hardener to be used with a resorcinol resin or a tannin resin as the adhesive for the bonding of wood articles. Preferably, an oxazolidine is combined with a base such as NaOH and a powdered absorbent such as wheat flour. The adhesive based on the improved hardener can be used to glue wood particles to pass wet strength requirements after the glue is cured at room temperature for under 24 hours. The improved hardener composition is storage stable; it can be prepared anytime before its use, thus eliminating the need to prepare a hardener immediately prior to the glue use. Since it is formaldehyde-free; it eliminates the safety issues associated with handling formaldehyde or paraformaldehyde. Also, the hardener provides flexible gel time or working time. Since the resins can be cured at room temperature, heating in an oven is not needed but could be used to reduce curing time. If radio frequencies are used to cure the resins, the exposure time can be reduced.

Wood is one of the most commonly used natural materials and there is still a relatively abundant supply. However, as more and more articles are being made of wood, the reduction in the supply of large trees and of high quality trees is becoming more serious. Therefore, the forest and lumber industry is trying to make the best use of wood through the use of synthetic adhesives. Examples of articles which use adhesives include particle boards, plywood, oriented strand boards, laminated beams, I-beams, and other engineered woods. An added advantage of making wood products with an adhesive system is that the so-produced woods are sometimes much stronger than natural woods because of the higher physical and chemical stability and the higher strength of glue relative to wood.
One of the most commonly used adhesives in the wood bonding industry is based on phenolic resins. A typical phenolic resin is made from the condensation polymerization of phenol with formaldehyde in the presence of a catalyst such as NaOH. Presently, numerous phenolic resins are tailor-made to suit different types of wood and for different shapes of wood articles. Traditional phenol-formaldehyde resins are chemically not reactive enough, so they have to be cured or used at high temperatures. The use of high temperature not only consumes a lot of energy, but also generates safety issues. The use of high temperatures can cause volatile organic compounds, called VOC's, to evaporate in the ovens. These often-toxic vapors eventually end up being released into the environment, mainly through stack emissions. Another safety concern with traditional phenolic resins is that they always contain some formaldehyde, which is a carcinogen.
If an adhesive can be cured at room temperature, capital and operating costs can be reduced. Therefore, phenolic resin manufacturers and wood manufacturers have concentrated their efforts on developing better adhesives that can cure at room temperature and that are safer to handle and use than traditional phenolic adhesives. The most promising technology that is presently being used is a two-component resorcinol adhesive. One part is a resorcinol-formaldehyde resin that is deficient in formaldehyde; and the other is simply formaldehyde or a formaldehyde donor. This adhesive takes advantage of the high reactivity of resorcinol so as to make possible the curing of the adhesive at room temperature.
Initially, resorcinol-formaldehyde resins were used for these applications. To reduce the impact of the high cost of resorcinol, phenol was later introduced to partially replace some of the resorcinol in the resin. Presently, phenol-resorcinol-formaldehyde resins are widely used as the adhesive for wood bonding purposes. In this two-part adhesive system, one part is usually formaldehyde or paraformaldehyde, called the hardener in the industry. The use of formaldehyde or paraformaldehyde is essential for the adhesive to work. However, formaldehyde and paraformaldehyde bring with them a lot of safety issues, since they are both carcinogens. The transportation, storage, handling, exposure, and stack emissions of these harmful compounds are closely watched by EPA and various other governmental bodies. Paraformaldehyde is presently the most commonly used hardener for resorcinol resins. Paraformaldehyde is a powder, and it is extremely difficult to work with because the dust is very hard to control. It is very toxic, and it readily decomposes and releases formaldehyde, which is very difficult to work with. The handling of paraformaldehyde thus is not very safe and requires special attention. Another disadvantage of paraformaldehyde is that it normally has to be prepared as a dispersion just immediately prior to its use. This is because such dispersions can easily settle and decompose to formaldehyde, which evaporates into the air, resulting in a concentration change of the active ingredient. Therefore, the industry typically has to prepare the dispersion, then use it within a short period of time in order to maintain consistent performance and avoid settling and down time. Therefore, the resorcinol resin-paraformaldehyde adhesive system permits curing at room temperature, but it has not addressed the safety issues of dusting and toxicity.
Recent efforts of wood manufacturers and adhesive manufacturers have been directed to developing hardeners to replace paraformaldehyde, so as to eliminate the dusting, toxicity and safety problems associated with paraformaldehyde and formaldehyde. One of the most promising technologies is based on oxazolidine chemistry. Oxazolidines are made from amino alcohols with formaldehyde. An oxazolidine can be very stable, and no free formaldehyde can be detected, therefore its transportation does not present any exposure problems. An oxazolidine reacts with a resorcinol through chemical transfer, which means that the formaldehyde will only leave the amino alcohol molecule when it is in direct contact with a resorcinol molecule. The whole transfer process does not involve any formation of formaldehyde, thus completely eliminating all the safety issues of paraformaldehyde handling, workplace exposure and emissions. It also does not have the settling problem of paraformaldehyde, thus increasing product consistency and reducing down-time. Resorcinol resin-oxazolidine type adhesives represent a tremendous improvement over resorcinol resin-paraformaldehyde system, and so have gained popularity. However, current oxazolidine hardeners used by the industry have some limitations. A major deficiency of oxazolidine-based hardeners is that the hardener is unable to cure a resorcinol resin at room temperature in less than 24 hours and achieve a strong bond passing the required wet strength (ASTM D 2559). Under similar conditions, paraformaldehyde-based hardeners can cure a resorcinol resin very efficiently at room temperature within 24 hours and provide the needed wet strength. Another limitation is that the oxazolidine-based hardeners typically have a much shorter gel time or working time relative to that of paraformaldehyde-based hardener.
Therefore, it has been the concern of the present inventor to provide a liquid hardener to be used with a resorcinol resin as an adhesive that can cure at room temperature within 24 hours to glue wood articles and which produces strong gluelines passing wet strength specifications. Also, a new liquid hardener should eliminate the safety hazards of formaldehyde and paraformaldehyde and provide a longer gel time for the gluing of wood articles than the present oxazolidine hardeners.

Oxazolidine-based hardeners for the room temperature cure of resorcinol resins in the bonding of wood articles


The etching selectivity is controlled by appropriately changing the dimension of the opening of each contact holes in forming simultaneously a plurality of contact holes of different depth by etching. By forming a dent in advance underlying the region where a contact hole is to be formed, the depth of the contact hole can be increased, whereby difference in the depths of the plurality of contact holes can be reduced. As a result, damage in the underlying layer or under etching in forming a plurality of contact holes of different depth simultaneously by etching can be solved.

1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing thereof, and more particularly, to a technique for solving various problems caused by difference in depths of contact holes in forming a semiconductor device having a plurality of contact holes of different depths.
2. Description of the Background Art
A conventional semiconductor device having a plurality of contact holes of different depths and a method of manufacturing thereof will be described hereinafter taking a DRAM (Dynamic Random Access Memory) as an example.
FIG. 19 is a sectional view of a memory cell portion of a DRAM having a memory cell called a stacked capacitor structure. Referring to FIG. 19, a memory cell of a conventional stacked capacitor structure has a MOS (metal oxide semiconductor) type field effect transistor formed on an active region isolated by a field insulating film 2 on the surface of a semiconductor substrate 1, and a capacitor having a stacked structure formed in the proximity thereof. The MOS type field effect transistor has impurity diffusion regions 3 and 4 which become the source/drain region formed on the surface of the semiconductor substrate 1, and a gate electrode 6a which becomes a word line formed on the surface of the semiconductor substrate in the region sandwiched between the impurity diffusion regions 3 and 4 with a gate insulating film 5 thereunder. A plurality of word lines are arranged in parallel. A gate electrode 6b is located on the field insulating film 2 parallel to the gate electrode 6a. On insulating film 7a and 7b covering the gate electrodes 6a and 6b, respectively, a lower electrode 8, an upper electrode 10, and a dielectric film 9 sandwiched therebetween of a capacitor which becomes the storage node are formed.
The lower electrode 8 of the capacitor is electrically connected to the impurity diffusion region 4 in a contact hole 4a. On the upper electrode 10 of the capacitor, a conductive layer 12 which becomes a bit line is formed with an interlayer insulating film 11 therebetween. The conductive layer 12 is electrically connected to the impurity diffusion region 3 in a contact hole 13 provided in the interlayer insulating film 11.
A relatively planar interlayer insulating film 14 is formed on the conductive layer 12. A conductive layer 15 having a two layered structure of a barrier metal layer 15a such as of TiN and an aluminum alloy layer 15b such as of Al-Si-Cu is formed on the surface of the interlayer insulating film 14. The conductive layer 15 is conductive with the gate electrodes 6a and 6b via a contact hole in a position not seen in the sectional view of FIG. 19. The conductive layer 15 is an interconnection for the purpose of improving conductivity of a word line, and an interconnection that is electrically connected to the surface of the semiconductor substrate 1 or to the surface of the upper electrode 10 of the capacitor in a peripheral circuit portion of the memory cell. A passivation film 16 is formed covering the conductive layer 15 on the interlayer insulating film 14.
The DRAM structured as described above has the conductive interconnection 15 and the semiconductor substrate 1, or the conductive interconnection 15 and the upper electrode 10 of the capacitor electrically connected via a contact hole formed in the interlayer insulating film in the peripheral circuit portion thereof.
The contact hole 20 for electrically connecting the conductive interconnection 15 and the surface of semiconductor substrate 1 is relatively high (i.e. has a depth of d.sub.1) if the interlayer insulating films 17, 18 and 19 are subjected to thermal process for planarization, as shown in FIG. 20, and is formed by anisotropic etching using a resist mask 21 as the mask. If planarization process of the interlayer insulating films 17, 18 and 19 is not carried out, the contact hole 20 is relatively shallow (i.e. has a depth d.sub.2 : d.sub.2 <d.sub.1), as shown in FIG. 21. The contact hole 22 for electrically connecting the conductive interconnection 15 to the upper electrode (cell plate) 10 of the capacitor does not penetrate the interlayer insulating film 17 as shown in FIG. 22, and is formed relatively shallow (d.sub.3 <d.sub.1, d.sub.2) with a resist mask 23 as the mask since the interlayer insulating films 18 and 19 at this position are relatively thin in comparison with the position shown in FIG. 20.
The difference in depth of contact holes 20 and 22 in relation to the thickness of the interlayer insulating films 17, 18 and 19 are shown in specific numeric figures in the following Table 1.
TABLE 1 ______________________________________ Comparison of Contact Hole Depth (unit: angstrom) Penetrated Interlayer Insulating Film Contact hole 20 Contact hole 22 ______________________________________ Interlayer Insulating Approximately 1300 Not Penetrated Film 17 Interlayer Insulating 5000-8500 Approximately 5000 Film 18 Interlayer Insulating 4000-6000 Approximately 4000 Film 19 Contact hole Depth 10300-15800 Approximately 9000 ______________________________________
The reason why the interlayer insulating films 18 and 19 through which the contact hole 20 penetrates have a thickness of a predetermined range is as set forth in the following.
In the case where the contact hole 20 is formed at a valley sandwiched by two regions where an element such as a transistor is formed, as shown in FIGS. 20 and 21, the interlayer insulating films 18 and 19 are planarized by the reflow of a thermal treatment, or by etching back the whole surface by dry etching. It can be appreciated from the comparison of FIGS. 20 and 21 that the thickness at the position for forming the contact hole 20 in the interlayer insulating film 18 and 19 is increased in FIG. 20 where a planarization process is applied in comparison with FIG. 21 where a planarization process is not applied. If a planarization process is not carried out as shown in FIG. 21, the interlayer insulating films 18 and 19 at the position for forming the contact hole 20 is relatively thin, whereby the depth of the contact hole 20 is smaller than the depth of d in the case of FIG. 20. Although this is advantageous from the standpoint of reducing the time required for etching the contact hole 20, a stepped portion will be generated between the region for forming the contact hole 20 and the adjacent region where an element is formed due to difference in the thickness of the interlayer insulating films 18 and 19. This stepped portion will cause resolution deficiency in the resist pattern because a stepped portion exceeding the depth of focus of the exposure device is generated at the time of photolithography for forming the contact hole 20, or at the time of a later photolithography for a conductive interconnection at a later process. Also, if the conductive interconnection is formed of aluminum interconnection and the photolithography process is carried out using a positive resist, an undesirable phenomenon called halation occurs in which the resist pattern for conductive interconnection is exposed and eliminated due to light reflectance from the underlying stepped portion during exposure, in addition to the above described resolution deficiency.
A planarization process for each interlayer insulating film is indispensable to suppress such undesirable phenomenon, and the thickness of the oxide film of the contact hole formation portion depends upon the planarization process.
Referring to FIG. 22 which is a sectional view showing a formation step of the contact hole 22 on the upper electrode (cell plate) 10 of the capacitor, the film thickness of the region for forming the contact hole is not increased even after the above-described planarization process because there is no word line below the upper electrode 10. Also, because the contact hole 22 does not penetrate the interlayer insulating film 17, the depth d.sub.3 of the contact hole 22 is smaller by approximately 6000-7000.ANG. in comparison with the case shown in FIG. 20 where the contact hole 20 has a depth of d.sub.1.
Because a conventional semiconductor device is formed as above with a contact hole 20 of a relatively great depth and a contact hole 23 of a relatively small depth, a process of etching both holes simultaneously will result in the doped polysilicon of the underlying upper electrode 10 of the capacitor being etched to form a hole as shown in FIG. 23 because the contact hole 23 will be excessively overetched if the etching time is set to form thoroughly the contact hole 20. Therefore, when a conductive interconnection having a double structure of a barrier metal layer 31 such as of TiN and an aluminum alloy layer 32 is formed in the contact hole 22, as shown in FIG. 24, the junction between the barrier metal 31 and the upper electrode 10 will be established only at a small region along the inner perimeter of the contact hole 20 to become the cause of conduction deficiency.
Even if the doped polysilicon layer of the upper electrode 10 is not thoroughly penetrated, and the film thickness of the upper electrode 10 is reduced to less than approximately 700.ANG. as shown in FIG. 25, alloy is made of the Ti of the barrier metal layer and the polysilicon, i.e. formation of a TiSi.sub.2 layer 33 progresses due to silicidation as shown in FIGS. 26 and 27 because of being subjected to a high temperature of 800.degree. C. in lamp annealing under an N.sub.2 ambient for the formation of a barrier metal 31. As a result, the doped polysilicon at the bottom of the contact hole 20 and also in the proximity of the side portion of the bottom of the contact hole is absorbed by the Ti to generate a void 34 which is shown in enlargement in FIG. 27. If the void 34 is significant, the upper electrode 10 is disconnected in the worst case. The limitation of the film thickness of a doped polysilicon layer in which a void 34 is generated is generally approximately 700.ANG. although depending on the film nature of the Ti and the lamp anneal temperature. It is therefore necessary to set the film thickness of the doped polysilicon layer to be approximately 1000.ANG. after the formation of a contact hole by dry etching and taking into consideration a manufacturing error margin. It is desired that the generation of the void 34 is prevented without increasing the film thickness in order to reduce the film thickness of the device.
The limitation of adjusting the etching time period will be described hereinafter. In general, the etching time T of dry etching for forming a contact hole is set by including to the etching time T.sub.1 for forming just the deepest contact hole, an overetching time T.sub.2 taking into consideration error in the designed film thickness of each interlayer insulating film which is the film to be etched and the variation error of the etching rate of the dry etching device, i.e. T=T.sub.1 +T.sub.2. The variation error of the etching rate of the dry etching device is caused by difference in the etching rate between semiconductor wafers, difference in the etching rate between wafers, and difference in the etching rate between batches in the case of a batch system dry etching. The film thickness distribution among semiconductor wafers and the distribution of the etching rate are shown in FIG. 28A and 28B. In the case where the thickness of the film to be etched moves towards the thinner direction (in the direction of arrow A in FIG. 28) and the etching rate moves towards the faster rate (in the direction of arrow D in FIG. 28B), there is a high probability of the doped polysilicon of the upper electrode 10 (cell plate) of the capacitor being overetched as shown in FIGS. 23 and 25. Conversely, in the case where the thickness of the film to be etched moves towards the thicker direction (the direction of arrow B in FIG. 28A) and the etching rate move towards a slower rate (the direction of arrow C of FIG. 28B), the deepest contact hole is not thoroughly formed. In the case of the contact hole 20 shown in FIG. 20, there is a high probability of the conductance between the conductive interconnection formed on the interlayer insulating film 19 and the surface of the semiconductor substrate 1 being not established. If the overetching time T.sub.2 is increased, the probability of the generation of the latter will be reduced, but the probability of generation of the former will increase. Conversely, if T.sub.2 is reduced, the probability of the former will be decreased but the probability of the latter will increase. By analyzing the test result of good product selection, the probability occurrence thereof was 5% at 3.sigma. respectively.
Although the probability of the problem will be reduced if the thickness of the doped polysilicon of the upper electrode (cell plate) 10 of the capacitor is increased, such an increase in thickness will result in a greater stepped portion with a greater possibility of the trouble at a later processing step. It is not desirable to employ the means of increasing the film thickness since reduction of the film thickness of each layer is a mandatory condition in the development of a semiconductor device of higher integration density.
The above-described problem becomes further significant in the case of coexistence of a contact hole 24 formed on the surface of the semiconductor substrate 1 and a contact hole 25 formed on the surface of a bit line 12 because the difference in the depth thereof is greater.
The following Table 2 shows the film thickness of the interlayer insulating films through which the contact hole 25 is penetrated and the depth of the contact holes 24 and 25 assuming that the film thicknesses of interlayer insulating films 17, 18 and 19 through which the contact hole 24 in FIG. 29 penetrates are identical to those of the contact hole 20 shown in FIG. 23.
TABLE 2 ______________________________________ Comparison of Contact Hole Depth (unit: angstrom) Penetrated Interlayer Insulating Film Contact hole 24 Contact hole 25 ______________________________________ Interlayer Insulating Approximately 1300 Not Penetrated Film 17 Interlayer Insulating 5000-8500 Not Penetrated Film 18 Interlayer Insulating 4000-6000 Approximately 4000 Film 19 Contact hole Depth 10300-15800 Approximately 4000 ______________________________________


A system and method measures digital images of a workpiece using a measuring computer and a client computer. The measuring computer reads each of the digital images of the workpiece from a source file, and merges all the images to generate a combined image of the workpiece. An object to be measured is selected from the combined image, and an image of the selected object is extracted from the combined image. The client computer measures the selected object on the extracted image, and displays measuring results of the selected object.

1. Field of the Invention
The present invention relates to a system and method for measuring digital images of a workpiece.
2. Description of Related Art
Generally, measuring equipments, are used by development and production to improve production quality. With the improvement of measuring equipment precision, measuring equipment becomes more complex to configure and more difficult to operate.
More recently, there is three-D measuring equipment which has a high precision and a high speed in measuring physical dimensions and geometric tolerances of a production. Normally, to measure physical dimensions and geometric tolerances of a product with a high precision and a high speed, the three-D measuring equipment is employed and programmed for a measuring task with a computer. The computer is configured in the three-D measuring equipment and works with the three-D measuring equipment together.
Standard CCDs are used in the three-D measuring equipment for capturing the images of the production. The standard CCD can identify a pixel corresponding to the product whose length is about 0.01 millimeter. If the resolution of a computer display is 1024 pixels*768 pixels, the image of the workpiece is only displayable up to 10 millimeters in its length. However, when there is a larger workpiece that needs to be measured on a measuring machine, the measuring engineer has to capture a series of images of the workpiece for measurement, and the series of images occupy plenty of memory space.
In this way, it is time consuming and it is worse especially for a user to measure a plurality of larger workpieces on the computer together with the three-D measuring equipment.
What is needed, therefore, is a system and method which can measure images of a workpiece effectively.

System and method for measuring digital images of a workpiece

Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd.


A brake system (10) comprises a disc brake (30) and a drum brake (50), and a hub (20). The hub (20) comprises a mounting portion (20a) generally having the shape of a hollow cylinder. The disc brake (30) comprises a disc (32) mounted on our outer surface of said portion (20c) of the hub for rotation with the hub, the disc (32) also being mounted for axial sliding movement on the hub (20). The drum brake (50) comprises frictional material shoes (56) which are moveable into engagement with an internal cylindrical surface (20e) of said mounting portion (20c) of the hub (20) to act as a parking brake.

This invention is concerned with a brake system eg for a vehicle.
Many vehicles are equipped with disc brakes to fulfil the primary braking function of stopping or slowing the vehicle. Such disc brakes are often operated by a foot pedal and hence do not operate in the absence of the driver. For this reason, the vehicles are equipped with a parking brake which can be held in a xe2x80x9cbrakes onxe2x80x9d condition in the absence of the driver, the parking brake serving to prevent the vehicle from moving from rest. Conventionally, such parking brakes are of the drum brake type, comprising a hollow cylindrical drum and two xe2x80x9cshoesxe2x80x9d comprising friction material. The shoes are mechanically-operated to engage the inner cylindrical surface of the drum with a braking force. Thus, the overall brake system has a considerable weight.
It is common for the disc of a disc brake to be the so-called xe2x80x9ctop-hatxe2x80x9d type comprising an annular inner portion which is bolted to a hub, a joining portion which is generally cylindrical and extends axially of the hub, and an annular friction material-engaging portion joined to the inner portion by the joining portion. In order to save weight, the interior surface of the joining portion is often utilised as the drum of a drum type parking brake, thereby eliminating the necessity for a separate drum. However, where the disc is not of the top-hat type, this solution is not available.
GB 2031538 A, in connection with FIG. 4 thereof, discloses a brake of the enclosed type suitable for use in the agricultural or construction industries. This brake has a hollow cylindrical hub portion of relatively small diameter which provides a mounting for a disc of a disc brake. Axially spaced from but integral with said hub portion is a further hollow cylindrical hub portion of much greater diameter which serves as the drum of a drum parking brake. Thus, the disc mounting and the drum are provided by different portions of the hub.
In WO 98/25804, a disc brake is described in which at least one disc is mounted on a hub. The disc is mounted on the hub by means of mounting means arranged so that the hub and the disc rotate about the central axis of the hub as a unit but the disc can perform axial sliding movement on the hub. The specific example given in WO 98/25804 has two discs mounted on the same hub, both being slidable axially. The brake also comprises a piston and cylinder assembly having its cylinder fixed relative to a suspension link of a vehicle, the cylinder being integrally formed with the link. The system also comprises a caliper fixed relative to the cylinder, the caliper providing supports for friction pads of the system, including pads between the two discs. The pad furthest from the assembly is fixed to the caliper but the remaining pads are slidably mounted thereon. When the piston and cylinder assembly is operated, the pad operated upon by the assembly and the pads between the discs slide on the caliper, and the discs slide on the hub until each disc is engaged on both sides by a pad.
The disc brake of WO 98/25804 operates on a hub which comprises a mounting portion on which the discs are mounted. The mounting portion is generally in the shape of a hollow cylinder, the discs being mounted on the outer cylindrical surface thereof. The disc brake is for a driven hub and the interior of the mounting portion is occupied by a connection between the hub and a drive shaft.
It is an object of the present invention to provide a brake system of the general type disclosed in WO 98/25804, the system being of reduced weight.
The invention provides a brake system comprising a disc brake, a drum brake, and a hub arranged to rotate about a central axis thereof, the hub comprising a mounting portion generally having the shape of a hollow cylinder centred on said axis, the disc brake comprising a disc mounted on an outer surface of said mounting portion of the hub for rotation with the hub, the disc also being mounted for axial sliding movement on the hub, characterised in that the drum brake comprises friction material shoes which are moveable into engagement with an internal cylindrical surface of said mounting portion of the hub to act as a parking brake.
In a brake system according to the invention, the same hollow cylindrical portion of the hub is utilised both as the mounting portion of the disc of a disc brake and also as the drum of a drum brake, thereby avoiding the necessity for a separate drum or drum portion, giving a lighter, simpler and more compact brake.
There now follows a detailed description, to be read with reference to the accompanying drawings, of a brake system which is illustrative of the invention.

Multiple disk brake system with integrated parking brake


A fence system having upright posts and transverse fence rails, formed of hollow rectangular tubular construction and having internal ribs formed within the hollow interior; a plurality of angular mounting brackets defining a transverse insertion portion and an upright attachment portion, and wherein the transverse insertion portions are adapted to make a frictional fit within the interior of said hollow tubular rails, and a plurality of fastening holes in said attachment portions, whereby the same may be secured to a fence post.

Rail systems for enclosing property are known to incorporate a wide variety of designs. A particularly advantageous rail system is based on transverse elongated hollow metal rails. In particular the hollow rails preferably comprise rectangular tubes. It is desirable to provide means for attaching the ends of the rails to upright posts. In addition it is desirable to provide means for supporting balusters between upper and lower rails, at spaced intervals between the posts.
Such rail systems may provide an ornamental system but usually will be required to provide some form of physical restraint. Forces are usually lateral forces, and also vertical forces and it is desirable to ensure that such rails are of adequate strength to resist such forces.
In addition to these factors it is desirable, from the view point of aesthetics and appearance that the metallic hollow tubular rails shall abut securely up against the sides of the posts. It will be borne in mind that all of these systems must be adaptable to a wide variety of different types of property and to variations in terrain, and they must be adapted for installation by service personnel in a systematic and repeatable fashion.


A constant current generating circuit and constant current generating method applied to a chip are provided, where the chip includes a first current generating circuit and a second current generating circuit, the second current generating circuit includes a transistor and an adjustable resistor. The constant current generating method includes: connecting an external resistor to the first current generating circuit to make the first current generating circuit use the external resistor to generate a first current; utilizing the second current generating circuit to generate a second current; adjusting the adjustable resistor in accordance with the first current and the second current to make the second current substantially equal to the first current, where the second current serves as a constant current of the chip.

1. Field of the Invention
The disclosed embodiments of the present invention relate to a constant current generating circuit, and more particularly, to a constant current generating circuit which utilizes a calibrated resistor inside a chip to generate constant current and related method thereof.
2. Description of the Prior Art
Generally speaking, an accurate current source inside a chip is needed to provide a constant current for circuit elements; however, due to that the resistance values of resistors inside the chip may not be accurate as desired, a manner to realize a precise current source is usually by using a bandgap voltage and an external resistor. As mentioned above, the production cost of the chip related design is increased inevitably due to the need for an additional external resistor.

Constant current generating circuit using on-chip calibrated resistor and related method thereof


The present disclosure relates to systems and methods for an intelligent assistant (e.g., a chatbot) that can be used to enable a user to generate a machine learning system. Techniques can be used to automatically generate a machine learning system to assist a user. In some cases, the user may not be a software developer and may have little or no experience in either machine learning techniques or software programming. In some embodiments, a user can interact with an intelligent assistant. The interaction can be aural, textual, or through a graphical user interface. The chatbot can translate natural language inputs into a structural representation of a machine learning solution using an ontology. In this way, a user can work with artificial intelligence without being a data scientist to develop, train, refine, and compile machine learning models as stand-alone executable code.

Machine learning has a wide range of applications, such as search engines, medical diagnosis, text and handwriting recognition, image processing and recognition, load forecasting, marketing and sales diagnosis, chatbots, autonomous driving, and the like. Various types and versions of machine learning models may be generated for similar applications using training data based on different technologies, languages, libraries, and the like, and thus may lack interoperability. In addition, different models may have different performances in different contexts and/or for different types of input data. Data scientists may not have the programming skills to generate the code necessary to build custom machine learning models. In addition, available machine learning tools do not store the various machine learning model components as part of a library to allow for efficient reuse of routines in other machine learning models.
Existing machine learning applications can require considerable programming knowledge by a data scientist to design and construct a machine learning application to solve specific problems. Intuitive interfaces can assist the data scientist construct a machine learning application through a series of queries.
Some organizations can store data from multiple clients or suppliers with customizable schemas. These customizable schemas may not match standardized data storage schemas used by existing machine learning models. Therefore, these other systems would need to perform a reconciliation process prior to using the stored data. The reconciliation process can be either a manual process or through a tedious extract, transform, load automated process prior to using the data for generating machine learning applications.
Machine learning applications based only on metrics (e.g., Quality of Service (QoS) or Key Performance Indicators) may not be sufficient to compose pipelines with minimal human intervention for a self-adaptive architecture. Pre-existing machine learning tools do not combine non-logical based and logic-based semantic services to generate a machine learning application.
Existing machine learning tools tend to maximize classification accuracy over new data from the same source. In doing so, these existing frameworks attempt to compose the best pipeline based on model performance. However, model performance on its own does not cover the cases where the pipeline must be adapted at run-time due to changes in online data metrics or QoS violations.

Chatbot for defining a machine learning (ML) solution


Systems and methods of the present disclosure enable drive filtering with reduced common mode and differential mode harmonics using a drive filter including, common-differential mode inductors connected to an alternating current (AC) power source, where each common-differential mode inductor has a common mode inductance and a differential mode inductance. A differential mode capacitor is connected to each common-differential mode inductors for filtering the differential mode inductances. A first common mode capacitor is connected to each common-differential mode inductor for filtering the common mode inductances, where each first common mode capacitor are commonly connected. A second common mode capacitor is connected to each common-differential mode inductor for filtering the common mode inductances, where each second common mode capacitor are commonly connected. Output contacts are connected to the common-differential mode inductors to connect a load to the AC power source.

Typically, pulse-width modulation (PWM) inverter systems can produce high peak voltages and currents to ground due to common mode voltages, with greater high peak voltage and current risk in systems with longer wires. Such high peak voltages and currents can cause damage to insulation systems, induced shaft voltage, ground leakage and bearing currents, all of which may cause damage to electric motor drive systems.

Integrated inverter output passive filters for eliminating both common mode and differential mode harmonics in pulse-width modulation motor drives and methods of manufacture and use thereof


A universal attachment device for attaching lawn care equipment including but not limited to leaf catchers, plug-core aerators, utility carts, and fertilizer spreaders to the sulky of a commercial walk-behind mower, the attachment device features a mounting shaft; a vertical pivot mount disposed on the first end of the mounting shaft for engaging a mounting plate disposed on the sulky; and a vertically oriented mounting channel disposed on the second end of the mounting shaft, the mounting channel functions to a base attachment shaft disposed on the piece of lawn care equipment or the lawn care equipment directly.

Lawn care customers can and do expect a wide range of services from lawn care providers in addition to lawn mowing. Such services can include but are not limited to fertilizer application, plug-core aeration, leaf and grass clipping removal, and general clean up and removal of twigs, branches, and assorted items at the beginning of each lawn care season. The present invention features a universal attachment device which can allow a single operator with a single mower to utilize a wide variety of tools attached to a standard sulky in order to complete tasks (such as the aforementioned tasks) without the need to purchase specialized equipment for each job.
Any feature or combination of features described herein are included within the scope of the present invention provided that the features included in any such combination are not mutually inconsistent as will be apparent from the context, this specification, and the knowledge of one of ordinary skill in the art. Additional advantages and aspects of the present invention are apparent in the following detailed description and claims.


A method for manufacturing an industrial product encompasses: forming a intermediate product pattern, which implements a part of a intermediate product of the industrial product by a sequence of processes corresponds to a part of a procedure for manufacturing the industrial product; forming an interconnect-changing insulator on the intermediate product pattern; boring sampling contact holes in the interconnect-changing insulator so as to make bare a part of the intermediate product pattern to define sampling sites; delineating evaluation interconnects on the interconnect-changing insulator so that each of the evaluation interconnects can electrically connected to at least one of the sampling sites of intermediate product pattern; and measuring an electrical resistance between subject sampling sites through the evaluation interconnects so as to detect a product defect in the intermediate product pattern.

1. Field of the Invention
The present invention relates to a fabrication method for miniaturized industrial products. In particular, it relates to a fabrication method preferable for development and standardization of a new manufacturing process for a miniaturized structure.
2. Description of the Related Art
For fabrication of a large-scale semiconductor integrated circuit with a minimum feature size F of 100 to 150 nm or less, advanced mask processing technology and lithography technology are needed. Particularly as the degree of miniaturization increases, there is increased difficulty in generating a flawless mask having many fine line-and-space patterns.
In addition to a mask level problem, with fabrication of micro-patterns for a semiconductor integrated circuit, there is a serious issue of generation of interconnect pattern defects or element pattern defects due to characteristics of substrate materials, fabrication environment, defective mask patterns, or lithography tool operating technology.
With a fabrication method for a microscopic semiconductor integrated circuit, one problem that occurs on semiconductor wafers includes fluctuations in pattern ends, which may cause short-circuit failure or open-circuit failure in the pattern of the semiconductor integrated circuit. Typically, ascribable to the fluctuations in pattern ends, an allowable error margin is required within the fabrication procedure so as to suppress the problem, and the fluctuations in pattern ends account for dimensional allowance. Accordingly, when a new fabrication procedure for a semiconductor integrated circuit is scheduled to be developed and standardized, or when designing a new semiconductor integrated circuit, with principal patterns serving as the target semiconductor integrated circuit disposed in central and principal area of a chip area, a plurality of evaluation test patterns (circuits) called "test element group (TEG) patterns" are merged in a part of the semiconductor wafer such as the periphery of the chip area so as to evaluate the fabrication procedure, electrical characteristics, fabrication conditions, and circuit functions by the TEG patterns.
A method of measuring electrical characteristics between terminals (pads) of a process testing pattern called "a process level TEG (PL-TEG) pattern" and a method of evaluating (estimating) yield and the like from the results has been adopted for evaluation of each process levels such as polysilicon film growth, impurity diffusion, and metal film formation (see Japanese Patent Application Laid-Open No. 2003-133385). PL-TEG pattern is a pattern of a specific mask (hereafter called "a process-level evaluation mask") for examining process dependency in order to investigate adverse affects such as causing open-circuit failure or short-circuit failure in the actual device patterns of semiconductor integrated circuit when process conditions for the semiconductor integrated circuit fabrication method vary. The process-level evaluation mask is implemented by closely aligned patterns equivalent to fine line patterns arranged in the semiconductor integrated circuit as a target industrial product, and is intended to easily statistically recognize short-circuit failures or open-circuit failures in the patterns of each process level.
Using semiconductor memory as an example of the target industrial product, each of the chip areas arranged on a semiconductor wafer is occupied by a plurality of semiconductor elements, called memory cells, each of which is configured to store data. Since an increasingly larger number of memory cells may be arranged within the same given area size as micro-fabrication technology of fine patterns advances, the most advanced micro-fabrication technology is typically used for the fabrication of the memory cell patterns during development, and state-of-the-art micro-fabrication technology is used for the fabrication of line patterns and space patterns. Due to this situation in the micro-fabrication technology, production of the process-level evaluation mask is generally carried out at the highest quality presently available, and exclusive masks for flawless patterns are required for examining open-circuit characteristics and short-circuit characteristics of patterns on semiconductor wafers.
Accordingly, production of the process-level evaluation mask is very difficult due to processing limits in each process. Meanwhile, because there are strict demands on transfer of the images of the process-level evaluation mask for examining processing fluctuation in the results of transferring the images onto the semiconductor wafer, the conditions for transferring the images of the process-level evaluation masks onto the semiconductor wafer are strict. Therefore, differences in image-transfer behavior between the process-level evaluation masks and masks routinely employed to the main portion of the semiconductor memory (or the target industrial product) in the actual fabrication sequences (hereafter called "working mask for a target industrial product" or simply "working mask") is an important factor for determination of the processing fluctuation on the semiconductor wafer, "the main portion of the semiconductor memory" excludes peripheral regions of a chip area where TEG patterns are merged on the semiconductor wafer, if the target industrial product is a semiconductor integrated circuit.
Particularly, it is impossible to precisely evaluate processing fluctuation by the exclusive PL-TEG pattern in the earlier technology, the PL-TEG pattern is implemented by a different pattern disposed on the same mask substrate than that of the actual device pattern, taking into consideration loading effects and the like during lithography and dry etching processes of micro-patterns. This problem emanates from difference in the covering rate of the fine patterns between the actual device pattern and corresponding PL-TEG pattern on the mask substrate. Therefore, it required much labor by doubling the job, because an extra job such as separately finding the correlation between the exclusive PL-TEG mask and the working mask becomes necessary, thereby causing an indeterminate factor in the evaluation of the processing fluctuation. In other words, in the earlier technology, the practical meaning of the method of preparing the exclusive PL-TEG mask separate from the working mask is becoming not as important nowadays where the absolute value of dimensions is becoming smaller, and essentially, covering rate and pattern density of the process-level evaluation mask are required to be the same as the covering rate and the pattern density of the working mask.
Furthermore, in the earlier technology, with extremely miniaturized, high accuracy masks, adverse influences of individual differences of the respective working masks increase, and the method using the exclusive PL-TEG mask is reaching its limit, and the production of the exclusive PL-TEG mask itself is becoming difficult.

Method for manufacturing industrial products and combination of masks for manufacturing the same


A method of forming a gate electrode of a multi-layer structure includes a step of supplying a processing gas for poly-crystal film formation and impurities of a P-type into a film formation device, to form a poly-crystal silicon layer doped with P-type impurities, on a surface of a gate film target, a step of maintaining the processing target in the film formation device to prevent formation of an oxide film on the poly-crystal silicon layer; and a step of supplying a processing gas for tungsten silicide film formation and impurities of a P-type into the film formation device, to form a tungsten silicide layer doped with impurities of P-type impurities, on the poly-crystal silicon layer on which no oxide film is formed.

The present invention relates to a laminated structure or multi-layer structure such as a gate electrode formed on a processing target comprising a semiconductor substrate or a glass substrate, and a method of forming the same.
In general, in steps of manufacturing a semiconductor integrated circuit, a desired element or elements are obtained by repeatedly performing film formation, pattern etching, and the like on a semiconductor wafer or a glass plate as a processing target.
For example, when a gate element for an MOSFET is formed on the surface of the wafer, impurities of one conductive type are diffused into positions where a source region 2 and a drain region 4 should be formed, in a wafer W, and a gate oxide film 6 made of, for example, SiO2 is formed on the area between the positions on the surface of the wafer while a source-drain channel is formed below the gate oxide film 6, as shown in FIG. 7A. Further, a gate electrode 8 made of a conductive film is formed on the gate oxide film 6, to form a transistor.
In recent days, the gate electrode 8 does not have a single-layer structure but has a multi-layer structure and has a two-layer structure in most cases, in consideration of conductivity. For example, a gate electrode 8 is formed by sequentially layering a poly-crystal silicon layer 10 doped with phosphorus and a metal silicide layer such as a tungsten silicide layer 11, on a gate oxide film 6.
In accordance with down-sizing and high-integration of a semiconductor integrated circuit in recent days, the processing line width and the gate width are narrowed more and more and the film thickness tends to be thinner and thinner in response to demands for multi-layering. Even though the line width is narrowed, it is demanded that electric characteristics of respective layers and interlayer electric characteristics should maintain conventional performances or attain higher performances. In response to such demands, the gate electrode 8 adopts a two-layer structure consisting of poly-crystal silicon 10 doped with phosphorus and tungsten silicide 11.
A film made of silicon material, e.g., a poly-crystal silicon layer 10 doped with phosphorus tends to easily form a natural oxide film 14 as shown in FIG. 7B on-its own surface when exposed to air, moisture, or the like. If a tungsten silicide layer 11 as a next layer is layered on the silicon layer 10 with such a natural oxide film adhered, tightness of a contact between both of the layers 10, 11 is degraded or sufficient electric conductivity cannot be maintained therebetween, resulting in a problem that the electric characteristics are degraded.
Film formations of the poly-crystal silicon layers 10 are normally carried out by batch processing in which wafers are treated in units each consisting of a number of wafers, e.g., 150 wafers, while film formations of a tungsten silicide layers 11 are carried out by piece-by-piece processing in which film formations are carried out for every wafer. As a result, the time for which one wafer is exposed to air varies between wafers, and the thickness of the natural oxide film varies accordingly. Therefore, wet washing is carried out, for example, with use of HF-based paper immediately before layering the tungsten silicide layer 11, in order to remove the natural oxide film 14 sticking to the poly-crystal silicon layer 10.
However, even when wet washing is carried out immediately before layering the tungsten silicide layer 11, it is very difficult to completely remove the natural oxide film 14 once adhered to the surface of the poly-crystal silicon layer 10, without affecting a subbing layer (i.e., the poly-crystal silicon layer 10) below the natural oxide film 14.
In this respect, there has been a proposal of a method in which a poly-crystal silicon layer 10 doped with phosphorus is formed on a semiconductor wafer in a chamber with use of a cluster tool formed, for example, by concentrating a plurality of chambers with air-tightness maintained between each other, and thereafter, the semiconductor wafer is introduced into another chamber in the same cluster tool, to form a tungsten silicide layer 11, without exposing the semiconductor wafer to air, i.e., without allowing any natural oxide film to have an opportunity to stick to the wafer (ref. Japanese Patent Application KOKAI Publication No. 9-17705).
As described above, if the tungsten silicide layer 11 is sequentially formed without exposing the wafer to air after the poly-crystal silicon layer 10 doped with phosphorus is formed, no oxide film is formed on the way of the manufacturing steps, and therefore, the entire gate electrode has a low resistance. It is possible to respond to design rules strictly limited under down-sizing and high integration.
In this case, however, phosphorus doped in the poly-crystal silicon layer 10 unevenly re-diffuses into the upper tungsten silicide layer 11 through an interface between both of these layers, and therefore, phosphorus is unevenly distributed near the surface of the tungsten silicide layer (e.g., between MOSFETs formed in each wafer), resulting in another problem that the electric characteristic is degraded and/or varies. Also, as a result of this, variation appears between wafers and the manufacturing yield is degraded.
If only a slight portion or portions of natural oxide film can remain on the surface of the poly-crystal silicon layer 10 doped with phosphorus after wet washing is carried out to remove the natural oxide film, the slight portion or portions of natural oxide film prevent phosphorus from diffusing into the upper layer, resulting in no problems. However, when sequential film formation is carried out so that no natural oxide film sticks in response to demands for a low resistance required for down-sizing, a new problem of uneven diffusion of phosphorus as described above appears.
In this respect, explanation will be made in more details with reference to a graph shown in FIG. 8.
FIG. 8 is a graph showing a resistance of a gate electrode with respect to a phosphorus density of a poly-crystal silicon layer and dependence of a variation rate of the resistance, where the longitudinal axis represents the resistance and the lateral axis represents the phosphorus density of the poly-crystal layer. In this figure, a broken line A shows a case where a tungsten silicide layer 11 is formed after the poly-crystal silicon layer 10 doped with phosphorus at a phosphorus density represented by the lateral axis is formed and is thereafter exposed to air to apply thereto a natural oxide film. A continuous line B shows a case where a tungsten silicide layer 11 is formed without exposing a poly-crystal silicon layer 10 to air after the poly-crystal silicon layer 10 is formed. In the figure, black circles show average values of resistance at phosphorus densities, respectively, and lines extending vertically from the black circles as the centers indicate a variation rate (width). As is apparent from the graph, in the case of the broken line A, the resistance is slightly high while variation of the resistance is small and uniform. Hence, it is found that diffusion of phosphorus into the tungsten silicide layer is blocked by a natural oxide film. In contrast, in the case of the continuous line B, the resistance decreases as the phosphorus density increases while the variation rate of the resistance increases much more. Hence, it is found that phosphorus unevenly diffuses into the tungsten silicide layer and this case is not preferable for characteristics.
FIGS. 9A and 9B are graphs for recognizing action of phosphorus where the left longitudinal axis represents the resistance of the tungsten silicide layer, the right longitudinal axis represents the uniformity of the resistance, and the lateral axis represents a wafer number. FIG. 9A is a graph showing the sheet resistance of the tungsten silicide layer of a gate electrode with respect to 25 pieces of wafers and the uniformity thereof where a tungsten silicide layer (Wsix) 11 is formed without forming a natural oxide film on a poly-crystal silicon layer 10 doped with phosphorus. FIG. 9B is a graph showing the resistance of the tungsten silicide layer of a gate electrode with respect to 25 pieces of wafers and the uniformity thereof where the tungsten silicide layer 11 is formed without forming a natural oxide film on a poly-crystal silicon layer 10 not doped with phosphorus. In these figures, a continuous line including white circles shows the sheet resistance of the tungsten silicide layer while a continuous line including black circles shows the uniformity of the sheet resistance. Arrows are used as indications thereof. As is apparent from the graphs, in the case of doping no phosphorus into the poly-crystal layer as shown in FIG. 9B, the value of the sheet resistance is naturally constant and the uniformity of the resistance is stable. In contrast, in the case of doping phosphorus into the poly-crystal silicon layer as shown in FIG. 9A, the resistance of the tungsten silicide layer greatly changes and the uniformity of the resistance is accordingly unstable and degraded greatly. Thus, direct formation of a tungsten silicide layer 11 on a poly-crystal silicon layer 10 doped with phosphorus causes uneven diffusion of phosphorus which leads to characteristic variation and is not preferable.
The present invention has an object of providing a multi-layer structure and a method of forming the same, capable of preventing uneven diffusion of impurities into a tungsten silicide layer as an upper layer from a poly-crystal silicon layer as a lower layer.
As to a first aspect of the present invention, there is provided a method of forming a multi-layer structure, comprising: a step of supplying a processing gas for poly-crystal film formation and first impurities of one conductive type into a film formation device, to form a poly-crystal silicon layer doped with first impurities of one conductive type, on a surface of a processing target; a step of maintaining the processing target in the film formation device to prevent formation of an oxide film on the poly-crystal silicon layer; and a step of supplying a processing gas for tungsten silicide film formation and second impurities of one same conductive type as the first impurities into the film formation device, to form a tungsten silicide layer doped with impurities of the same conductive type as the first impurities, on the poly-crystal silicon layer on which no oxide film is formed. Also, there is provided a multi-layer structure formed by the method.
According to the first aspect, it is possible to obtain a multi-layer structure made of a poly-crystal silicon layer doped with impurities of a conductive type and a tungsten silicide layer (sequentially) formed on and in direct contact with the poly-crystal silicon layer and doped with impurities of the same conductive type as the above-mentioned impurities. In this case, first, the tungsten silicide layer as an upper layer is doped with impurities without uniformity, and therefore, uneven diffusion of impurities from the poly-crystal silicon layer as a lower layer can be negligibly small in comparison with the density of the impurities in the tungsten silicide layer. As a result of this, impurities are kept uniformly diffused in the tungsten silicide layer. Therefore, characteristic variations are reduced and equalized. Second, impurities of one conductive type previously doped in the upper layer or tungsten silicide layer make the upper layer to have a crystal structure, for example, amorphous structure, which may prevent or minimize rediffusion of impurities from the lower layer or poly-crystal silicon layer, so that same effects as those above mentioned are obtained.
According to a second aspect of the present invention, a second poly-crystal silicon layer containing no impurities is inserted (or sequentially formed) as a block layer between a first poly-crystal silicon layer doped with impurities and a tungsten silicide layer containing no impurities, such that the second poly-crystal silicon layer is in direct contact with both the first poly-crystal silicon layer and the tungsten silicide layer. Therefore, uneven diffusion of impurities from the first poly-crystal silicon layer as a lower layer is blocked by the second poly-crystal silicon layer, so that impurities can be prevented from unevenly diffusing into the tungsten silicide layer as an upper layer.
According to a third aspect of the present invention, a second poly-crystal silicon layer having a low impurity density is inserted between a first poly-crystal silicon layer doped with impurities and a tungsten silicide layer containing no impurities. Therefore, uneven diffusion of impurities from the first poly-crystal silicon layer as a lower layer is blocked by the second poly-crystal silicon layer, so that impurities can be prevented from unevenly diffusing into the tungsten silicide layer as an upper layer.
In the first and second aspects, the second poly-crystal silicon layer which serves as a block layer as described above should preferably be formed to be very thin in comparison with the other layers and is set within a range of, for example, about 50 xc3x85 to 500 xc3x85.
According to a fourth aspect of the present invention, only the surface portion of a first poly-crystal silicon layer doped with impurities has an impurity density increased excessively, or a second poly-crystal silicon layer having a high impurity density is directly formed on the first poly-crystal silicon layer. Therefore, impurities do not unevenly diffuse when impurities diffuse into the tungsten silicide layer as an upper layer.
A multi-layer structure as described above is applicable to a gate electrode of a MOSFET, for example.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

Method of forming a laminated structure to enhance metal silicide adhesion on polycrystalline silicon


Disclosed is a tilting device for a steering column comprising: a steering column inclinedly arranged in a rear direction of a vehicle; a bracket located between the steering column and a shroud, a cover that shields the steering column from an outside, to guide the steering column for tilting; and a tilting locking means slidably arranged substantially near to an upper surface of the steering column to enable the steering column to be tilted or not to be tilted.

1. Field of the Invention
The present invention relates to a tilting device for a vehicular steering column, and more particularly, to a tilting device for a vehicular steering column that is capable of preventing a driver's knees from being injured and of adjusting the angle of the steering column by providing a sliding-type tilt lever on the upper side portion of the steering column.
2. Discussion of the Background
In general, a tilting device is so designed for a driver to tilt a steering column by adjusting the position of a steering wheel to accommodate a driver's figure for more comfortable driving.
Various shifting devices have been employed for the driver's safety and the transmission of the operating force to gears. Of these shifting devices, a steering column that transmits the operating force of a steering wheel to a steering gear is generally inclinedly mounted by about 20 to 30 degrees.
It is compulsory to mount a safety device, such as air bag system, in a vehicle in order to protect the driver from the impact to the steering wheel and steering column.
FIG. 1 is a perspective view of illustrating a conventional tilting device including a tilt lever mounted at a lower part of the steering column according to a prior art.
The conventional tilting device includes a key-set 2 provided on a steering column 3 for transmitting the operating force from a steering wheel, an adjustment unit 4 for fastening or adjusting the tilting angle of the steering column 3, and a tilt lever 1 provided on the lower part of the steering column 3 for the hinge-connection between the steering column 3 and the adjustment unit 4.
In addition, a shroud (not shown) can be further provided to cover the outside of the steering column 3 to prevent the interference of unwanted materials from the outside. However, the tilt lever 1 is externally protruded from the shroud to be handled by the driver and furthermore positioned under the lower part of the steering column 3.
The steering column 3 configured as above, can adjust the height of the steering wheel according to the driver's figure. At this time, when the driver lifts up the tilt lever 1, the adjustment unit 4 that is hingedly connected to the tilt lever 1 cooperates with the tilt lever 1, so that the angle of the steering column can be adjusted.
In the conventional tilting device configured as above, however, the driver can be injured due to impact of his/her knees to the tilt lever 1 caused by an accident such as car collisions since the tilt lever 1 is externally protruded from the shroud and positioned under the lower part of the steering column 3 as set forth above.
A shock absorbing material, such as foam, is packed between the shroud and the steering column 3 to increase the driver's safety. Particularly, it is necessary to ensure space of more than at least 25 mm between the tilt lever 1 and the steering column 3 so that the entire parts of the steering column 3 can be protected with the aid of the shock absorbing material. However, in the conventional tilting device, the space between the tilt lever 1 and the steering column 3 is essentially narrow since the tilt lever 1 is configured to hingedly cooperate with the steering column 3 and thus the tilt lever 1 is fastened substantially near to the outer periphery of the steering column. As a result, this configuration and mechanism of the conventional art makes the gap between the tilt lever 1 and the steering column 3 narrow as shown in FIG. 1. Accordingly, there is a difficulty in a process of inserting the shock absorbing material in the shroud, thus leading to the requirement of longer process time.
The information disclosed in this Background of the Invention section is only for enhancement of understanding of the background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art that is already known to a person skilled in the art.


There is provided a turbofan engine having: a fan rotatable about an axis within a case; a first acoustic treatment lining a first portion of the case upstream of the fan; and a second acoustic treatment lining a second portion of the case downstream of the fan, the first acoustic treatment having different noise-attenuating characteristics relative to the second acoustic treatment.

A gas turbine engine is a major contributor to aircraft noise and acoustic treatments in the engine can be used to attenuate some of the noise. However, there are different sources of noise in a gas turbine engine and known configurations of acoustic treatment in gas turbine engines can have limitations in attenuating certain sources of noise. It would be desirable to enhance noise attenuation in gas turbine engines.


In accordance with the present invention, a method, system, and program for controlling the replenishment process in the manufacturing process by maintaining a common database is disclosed. The present invention connects the acquiring entity, supplier, and the replenishment service center (“RSC”) to efficiently coordinate the replenishment process using the days of supply at the RSC as the key benchmark. By allowing access to the common database, the acquiring entity, supplier, and RSC can view and update changes in the replenishment process in real time increasing the communication and efficiency of delivering components to manufacture a product. In addition, the present invention facilitates the ability for the invoice process to be conducted electronically over the computer network.

1. Field of the Invention
The present invention relates in general to a replenishment management system, method, and program and more particularly to a replenishment management system, method, and program which provides just in time delivery to an acquiring entity, which may comprise a distribution center, wholesaler or any other supply chain system of components or products.
2. Description of the Related Art
Availability of components necessary to manufacture a product is a major challenge to the manufacturer of that product. Typically, delivery of components to the manufacturer usually involves three separate parties: the supplier, the replenishment service center ("warehouse or RSC") and the manufacturer. In the most basic sense, the availability of each component needs to be monitored to ensure an adequate supply is available to the manufacturer. The warehouse supplying the manufacturer and the supplier to the warehouse are further challenged to meet the demand for components without over stocking the components. However, maximizing the efficiency of delivering the components has been a constant problem in the prior art. For example, if the manufacturer finds either an increased or reduced demand in the product compared to its forecast, strain is placed throughout the supply chain where overstocking or depletion of components can occur quickly. In addition, if the supplier cannot deliver the components, manufacturers will often not be able to react quickly to meet demand, seek alternative sources, etc. Without keeping large stock of components on-hand in the warehouse, supply problems occur readily. However, keeping large stock has additional problems of its own, such as higher storage costs, an increased loss probability because components become outdated, etc. Moreover, electronic parts tend to reduce in value with time (i.e. a part that the manufacturer purchases in January will cost less in March and much less in June and so on).
Systems in the prior art have attempted to address this replenishment problem using various systems and methods. Internal MRP ("Material Requirement Planning") or ERP ("Enterprise Resource Planning") systems would manage components based on a forecast prepared by the manufacturer. However, forecasts are never precise, and often subject to changes. In recent years, to better match actual production with forecasts calculated by the MRP system, a Just-in-Time ("JIT") concept was developed. In a JIT environment, a network of phones and faxes is used to monitor each point in an assembly line where someone would be responsible for counting each set of components as they are assembled into a product (i.e. a manual pull system). Thereby, the responsible party would order additional components by phone or fax as components are running short. However, such JIT systems require constant monitoring, and still are highly dependent on accurate forecasts. Although better forecasting tools have been developed over the years, replenishment issues have remained a problem for manufacturers. As the manufacturing world begins to move to build-to-order environment, greater demands are expected from the manufacturer to 1) lower total costs in the complete supply chain 2) shorten throughput times 3) reduce stock to a minimum and 4) provide more reliable delivery dates without constraining production due to supply issues.
Accordingly, there is a need in the art for an improved replenishment management system that addresses the concerns of the supplier, the manufacturer, and the RSC.

Replenishment management system and method

International Business Machines Corporation


In an apparatus for determining fibre lengths and fibre length distribution from a fibre material sample, especially in spinning preparation, collected fibre material is automatically conveyable by a conveyor device, is arranged to be supplied to a take-up device that grips it, is separable from the conveyor device and transportable to at least one rotating combing device, each end region of the collected fibre material protruding from the take-up device being combable by combing device, and subsequently detectable by a measuring device. The apparatus permits within a short time a sample preparation founded on a uniform basis and an accurate measurement of the samples.

The invention relates to an apparatus for determining fibre lengths and fibre length distribution from a fibre material sample, especially in spinning preparation. In such apparatus, sample preparation elements may be located upstream of the measuring, evaluating and indicating device, said preparation elements comprising a clamping device and a combing element for the treatment of collected fibre material, the combing element producing a fibre fringe that is used for the measurement.
In the practical operation of spinning, fibre slivers taken from production are brought into a fibre laboratory, where the following testing is carried out:    (a) several slivers are placed by hand in clamps previously opened by hand and are carefully, that is, homogeneously, distributed across the width of the clamp and then the clamp is closed by hand.    (b) The fleece is clamped between two leather-covered plates. The plates are pressed into flat abutment with one another. There is no actually defined clamping point.    (c) The fleece is combed by hand using a single-row straight comb.    (d) A round brush is finally used to brush out the fibre fringe again.    (e) One side of the clamp is offered up to a fibrograph, then the clamp is turned over and the other side is offered up to the fibrograph. Using the fibrograph, two fibre fringes are transported past light sources. The source light passing through falls on light receivers and is registered and evaluated.
To test fibre slivers and flyer spinning frame slubbings, the leaflet "Fibrograph 630" of Spinnlab, Knoxville, Tenn., USA describes how, for preparation of a sample, the fibre material sample is opened and spread out and placed in a fibre clamp. The clamp members hold the fibres in their actual arrangement in sample zones. The randomly connected, overlapping, non-parallel relationship between the fibres remains as it is. When the sample has been thus prepared, the fibre clamp is placed in the fibrograph, which brushes out the fibre fringe, scans the sample optically and displays the result of the measurement.
The known sample preparation is time-consuming. Manual handling and processing of the sample and placing thereof in the measuring apparatus are additional to transportation from the spinning works to the test laboratory. It is a further disadvantage that owing to the individual handling of the sample preparation, the samples are not uniformly consistent. Finally, it is inconvenient that a fibre measurement at the location of the spinning machine is not possible.
It is an aim of the invention to produce an apparatus of the kind described in the introduction that avoids or mitigates the said disadvantages, and which in particular makes possible within a short time a sample preparation founded on an equal basis and allows an accurate measurement of the samples.

Apparatus for determining fibre lengths and fibre length distribution from a fibre material sample, especially in spinning preparation


A Universal Serial Bus (USB) flash drive includes a slim USB device having an end used to couple the USB flash drive to a host and an opposite end and a swivel cap having a side slit that serves as an opening into which the slim USB device travels horizontally, the side slit being disposed along a lateral side of the swivel cap. The USB flash drive also includes a USB device rivet placed into the slim USB device and the swivel cap to pivotally connect them at one of the ends of the slim USB device, so that the slim USB device is pivotally extendable outwardly from the side slit in a closed or open position. The swivel rocker is pivotally extendable outwardly from the opposite end of the slim USB device and when the swivel rocker is extended outwardly, the slim USB device is caused to extend outwardly.

1. Field of the Invention
The present invention relates generally to the field of universal serial bus (USB) flash drives (or devices) and particularly to USB flash drives having an encapsulated and retractable USB device.
2. Description of the Prior Art
As computers have gained enormous popularity in recent decades, so has the need for better and more efficient ways of storing memory. Notable among memory devices are the portable ones that may be carried around by the user to access computers at different locations. This is particularly common in the case of personal computers (PC) where the need often arises to transfer data from one PC to another. Examples of portable memory devices include nonvolatile memory devices such as a universal serial bus (USB) flash drive that is removably connectable to a computer.
USB flash drives are available in various shapes and forms. The USB flash drive needs a USB plug connector to be coupled to a USB port of a host device such as a PC. The USB flash drive generally has a metal casing and a cover which is screwed in or otherwise attached to the casing. To access the USB plug connector, the user needs to open the metal cover and place it in the back on the casing after finishing the work with the USB flash drive. There is therefore the possibility of losing or misplacing the cover because it is completely detached when removed, from the USB plug connector. Furthermore, the possibility of leaving the USB plug connector without a cover is increased thereby adversely affecting the security of the connector.
The need therefore arises for a USB flash drive having a USB device that is secure and that uses a cap that is unlikely to be detached therefrom.

Universal serial bus (USB) flash drive housing a slim USB device and having swivel cap functionalities allowing for two locking positions


The invention deals with an electronics cabinet with a shelving frame of sectional rails 8 on which casings 2,3 are attached. On the insides 19 of the casings 2,3, longitudinal grooves 38 are designed in which contact springs 24 lock into. The contact ridges 27 of these contact springs 24 lie at each neighboring sectional rail 8 when the casings 2,3 are attached.

Electronics cabinets serve to hold devices that are normally built for stationary electronic building groups.
The invention that finds application by the endeavor to sound proof high frequency electronics cabinets whereby shielding effect is exhibited, electromagnetic inflows are provided, or that which contains such devices that cause electromagnetic disturbances that are not allowed to reach the outside. The most difficult leakage points to conquer for these types of cabinets are the narrow vertical and horizontal slots between the casings, i.e., the sidewalls, backwall door, and shelving frame. Therefore, at these critical points, a contact device is inserted which should produce a HF-density electrical contact on the cabinet elements directly neighboring or lying across from it.
It is known for example to place cross-sectional s-shaped stripes of electrical contact springs on the edges of the casings. On the one side the edges spring closed against the electrical contact springs and on the other side they are pressed through spring action against the opposing component (DE 41 27 468). Furthermore it is known to place elastic padding of a conductive material, to insulate the slots, between cabinet elements (DE 43 07 805). On the one hand, the electromagnetic shielding effect of this known measure is unsatisfactory, on the other, they are susceptible to mechanical damages due to their construction, because they extend unprotected over the edges of the casing. An additional problem is reliably keeping the contact points free from lacquer in order to achieve lower electrical cross-over resistance. In addition to this, a housing for electrical devices is known whose metal rails show high frequency insulating clamping cross-bar pieces with pushed-up u-shaped contact springs. Beside these clamping cross-bar pieces longitudinal chambers can be seen. The arrangement is such that when handling the metal surface of the rail on the back side of the clamping cross-bar piece, which lies on the inside of the longitudinal chamber, an electrical contact zone remains unlaquered (DE43 11 246).
The task of the invention is based on the desire to create a cost effectively made and simply assembled electronics cabinet with an especially effective, tough, and stable high frequency type of insulation for the vertical and horizontal slots between certain leakage points on the casing.