An information processor comprises an instruction decoder for executing a subroutine calling instruction including designation of a general-purpose register for calling a subroutine, a circuit for selecting a specific general-purpose register designated by an instruction based on a result of the execution of a subroutine calling instruction among a plurality of general-purpose registers, and a circuit for saving, in a selected general-purpose register, a value obtained by adding a length of a subroutine calling instruction to a program counter value as a return address.

1. Field of the Invention
The present invention relates to information processors, and more particularly, to an information processor in which overhead incurred during processing for calling a subroutine and returning therefrom is reduced.
2. Description of the Related Art
In von Neumann type computers, a program counter (hereinafter referred to as PC) indicative of an address of an instruction to be executed is updated to sequentially read and execute programs stored in a memory. In general, central processing units (hereinafter referred to as CPU) of von Neumann type computers need to store, prior to branch from a main program to a subroutine, an address of an instruction to be executed first upon return from a subroutine (hereinafter referred to as a return address).
Description will be given in the following of a conventional information processor including a CPU having a calling instruction for subroutine processing and an instruction to return from the subroutine.
An information processor according to the first prior art is structured to store a return address in a memory by using a general-purpose register as a stack pointer. In this first prior art, a JAL instruction is used as a subroutine calling instruction and a JMP instruction as a returning instruction. JAL instructions are for calling a subroutine by addressing, while JMP instructions are for returning from a subroutine through a register.
Second prior art is disclosed in Japanese Unexamined Patent Publication (Kokai) No. Showa 63-316134 entitled "Semiconductor Integrated Circuit". This second prior art uses a shift register for subroutine processing in place of a memory used as a stack. In addition, the second prior art uses a CALL instruction as a subroutine processing calling instruction and a RET instruction as a return instruction.
In the following, description will be given of structure and operation of these prior art information processors. The structure of the first prior art is shown in FIG. 5. In the figure, the reference numeral 410 represents an instruction decoder, 440 a PC (program counter), 441 an incrementer which increments the value of the PC440 by "2" or "4" in response to a word change-over signal S34, 501 to 531 general-purpose registers, 500 a general-purpose register whose data is fixed at "0", 600 to 631 two-input AND circuits, 650 a two-input OR circuit, 420 a data bus, and 430 a memory. In the first prior art, the memory 430 is used as a stack for return addresses.
The instruction decoder 410 decodes various kinds of instructions including a subroutine calling instruction and a return instruction and based on the results of the decoding, outputs a read signal (RD signal) S52, a write signal (WR signal) S53, a return signal S54, a save signal S55, register select signals S0 to S31, an address of a subroutine and a word change-over signal S34 indicative of a byte count of a decoded instruction (length of an instruction). In addition, the instruction decoder 410 outputs 32-bit address data onto the data bus 420.
The incrementer 441 at all times receives an output of the PC440 and in response to the word change-over signal S34, outputs to the PC440 a sum of a counter value ("2" or "4") equivalent to the length in bytes of an instruction being decoded and the output of the PC440.
The return signal S54 output from the instruction decoder 410 is supplied to ones of the respective inputs of the AND circuits 600 to 631. The save signal S55 from the instruction decoder 410 is supplied to one input of the OR circuit 650.
The register select signals SO to S31 correspond to the AND circuits 600 to 631, respectively. More specifically, the register select signal S0 corresponds to the AND circuit 600 and the register select signal S31 to the AND circuit 631. The register select signals S0 to S31 are accordingly supplied to the others of the respective inputs of their corresponding AND circuits 600 to 631.
The AND circuits 600 to 630 obtain the AND of the return signal S54 and the register select signals S0 to S30, respectively. The outputs of the AND circuits 600 to 630 are output as select signals for selecting the corresponding general-purpose registers 500 to 530. More specifically when the logical value of the return signal S54 is 11111 and any of the register select signals S0 to S30 attains "1", one of the outputs of the AND circuits 600 to 630 attains "1" to select the corresponding one of the general-purpose registers 500 to 530.
The word change-over signal S34 output from the instruction decoder 410 is a signal which controls the incrementer 441. The word change-over signal S34 takes the logical value "0" when an instruction being decoded is two bytes long and takes the logical value "1" when an instruction being decoded is four bytes long. The incrementer 441 is controlled to add the count value "2" to the PC440 when the logical value of the word change-over signal S34 is "0" and add the count value "4" when the logical value of the word change-over signal S34 is "1".
The AND circuit 631 attains the AND of the return signal S54 and the register select signal S31 and outputs the same to the OR circuit 650. When the return signal S54 is "1" and the register select signal S31 is "1", the output of the OR circuit 650 takes the logical value "1" to select the general-purpose register 531. In addition, when the logical value of the save signal S55 is "1", the output of the OR circuit 650 takes the logical value "1", to select the general-purpose register 531.
The RD signal S52 and the WR signal S53 are supplied to the general-purpose registers 500 to 531. When the RD signal S52 takes the logical value "1", data of a general-purpose register being selected is output onto the data bus 420. When the WR signal S53 takes the logical value "1", data on the data bus 420 is written to a selected general-purpose register.
The instruction decoder 410 outputs an address of a subroutine onto the data bus 420 upon completion of write of a return address to a general-purpose register.
FIG. 6 shows a format of instruction codes to be processed by the information processor illustrated in FIG. 5. For calling a subroutine, a JAL instruction 401a shown in FIG. 6 is executed. Bit numbers 15 to 10 of the JAL instruction 401a represent a field of op codes which direct operation of the JAL instruction 401a. Bit numbers 9 to 0 and 31 to 16 represent a field for setting a displacement value indicative of a branch destination. For returning from a subroutine, a JMP instruction 402a is executed. The JMP instruction 402a is arranged as shown in FIG. 6, in which bit numbers 15 to 10 represent an op code field which directs operation of the JMP instruction. Bit numbers 9 to 5 represent an unused field all set to "0". Bit numbers 4 to 0 represent a field for designating a general-purpose register, which field designates the general-purpose registers 501 to 531 by 5-bit binary numbers. An instruction 400a shows a code arrangement of a register-to-register data transfer instruction (MOV, reg, reg).
With reference to FIGS. 5 and 6, the description will be given of operation for calling a subroutine and for returning therefrom. By decoding the JAL instruction 401a, the instruction decoder 410 outputs the RD signal S52 set to "0", the WR signal S53 set to "1", the return signal S54 set to "0", the save signal S55 set to 11111 and the register select signals S1 to S31 all set to "0" and also outputs the word change-over signal S34 set to "1" because the instruction is four bytes long, and then outputs an address of the subroutine onto the data bus 420.
Here, the JAL instruction 401a is described as follows.
JAL Subroutine Name
Description will be given of processing for executing the JAL instruction 401a to store a return address in the general-purpose register 531. In FIG. 5, when the JAL instruction 401a is decoded by the instruction decoder 410, the save signal S55 and the word change-over signal S34 both attain "1", so that a value which is obtained by incrementing the value of the PC440 by "4" is output as a return address onto the data bus 420. At the same time, the output of the OR circuit 650 attains "1" to select the general-purpose register 531. At this time point, since the WR signal S53 is "1", the return address on the data bus 420 is written to the general-purpose register 531.
On the other hand, since the return signal S54 is "0", all of the AND circuits 600 to 631 output "0". No return address is therefore written to the general-purpose registers 500 to 530.
After the saving of the return address, the instruction decoder 410 outputs an address of a subroutine onto the data bus 420 to set an address of a subroutine called by the PC440, thereby transferring control to the subroutine.
As described in the foregoing, because the general-purpose register 531 is regularly used to save a return address, it is necessary, before returning from a subroutine, to store the contents (return addresses) of the general-purpose register 531 in the memory 430 used as a stack in preparation for a further call to another subroutine as soon as the control transfers to the subroutine. Such stacking of a return address is required because when the JAL instruction 401a is executed to call another subroutine prior to return from a first subroutine, the contents of the general-purpose register 531 are rewritten to lose a return address for the main routine.
For returning from the subroutine, the JMP instruction 402a as a return instruction is executed. 5-bit data of the JMP instruction 402 which designates a general-purpose register is decoded by the instruction decoder 410, so that one of the register select signals S1 to S31 for selecting the designated general-purpose register is output. Moreover, by decoding the JMP instruction 402a, the instruction decoder 410 sets the RD signal S52 to "1", the WR signal S53 to "0", the return signal S54 to "1", the save signal S55 to "0" and one of the register select signals S1 to S31 corresponding to the designated general-purpose register to "1".
The JMP instruction 402a is described as follows.
JMP General-Purpose Register Name!
Process of reading a return address by executing the JMP instruction 402a will be described with reference to FIG. 5. Here, description will be given of a case where a general-purpose register for reading a return address is the general-purpose register 531. In FIG. 5, first under the program of the subroutine, a return address is read from the memory 430 which stores return addresses and stored in the general-purpose register 531. Thereafter, the JMP instruction 402a which designates the general-purpose register 531 is executed. As a result of decoding of the JMP instruction 402a, the instruction decoder 410 outputs the return signal S54 and the register select signal S31 both set to "1", so that the output of the OR circuit 650 attains "1" to select the general-purpose register 531. At the same time, the instruction decoder 410 outputs the RD signal S52 set to "1", so that the value of the general-purpose register 531 is output onto the data bus 420. In addition, the value of the data bus 420 is set to the PC440 as a return address.
In the first prior art shown in FIG. 5, for the processing of return address saving and returning by regularly using the general-purpose register 531, the return address is saved in the general-purpose register 531 at the time of a subroutine call and the value of the general-purpose register is stacked and held in the memory 430 in preparation for a next subroutine call. It is further necessary to read the return address held at the memory 430 onto the general-purpose register 531 at the time of return from the subroutine. Return addresses are therefore transferred so frequently between the general-purpose register 531 and the memory 430 for the return address saving and returning processing that an overhead is incurred.
In this regard, specific description will be given in the following, for example, of a case of double nesting of a subroutine, that is, a case where another subroutine is called without returning from a subroutine to a main routine.
FIG. 7 shows nesting operation of subroutines by the JAL instruction 401a and the manner of saving in and returning to the PC440. FIG. 8 shows return address saving and returning processing and the clock count required for the processing at each step of the nesting operation of the subroutines shown in FIG. 7. Here, the program, which is executed in the direction indicated by the arrow, nests out of a main routine R1 into a subroutine SR1 and further into a subroutine SR2. The stack pointer is implemented not by special hardware but by the general-purpose register 503.
When the JAL instruction 401a is executed at Step 701 in the main routine R1, a return address is saved in the general-purpose register 531 to set an address of the subroutine SR1 to PC440. As soon as the control transfers to the subroutine SR1, at Step 702, the contents of the general-purpose register 531 are stored at an address of the memory 430 indicated by the stack pointer (general-purpose register 503) to increment the stack pointer by "4". From Step 702 on, processing of the subroutine SR1 is executed.
When the JAL instruction is executed at Step 703 in the subroutine SR1, a return address is saved in the general-purpose register 531 to set an address of the subroutine SR2 to the PC440. As soon as the control transfers to the subroutine SR2, at Step 704, the contents of the general-purpose register 531 are stored at an address of the memory 430 indicated by the stack pointer to increment the stack pointer by "4". From Step 704 on, processing of the subroutine SR2 is conducted.
When the processing of the subroutine SR2 is completed, the value of the stack pointer is decremented at Step 705 by "4" to call the contents of the memory 430 at an address indicated by the stack pointer into the general-purpose register 531. At Step 706, execution of the JMP instruction 402a results in setting of a return address to the PC440, whereby the control returns to the subroutine SR1.
Then, processing of the subroutine SR1 follows. When the processing completes, the value of the stack pointer is decremented by "4" to call the contents (return address) at an address indicated by the stack pointer into the general-purpose register 531 at Step 707. At Step 708, the JMP instruction 402a is executed to set a return address to the PC440, whereby the control returns to the main routine R1.
Thus it is necessary to store a return address in a memory (stack) and call a return address from the memory at each time of a subroutine call and return from a subroutine, which causes an overhead. As shown in FIG. 7, when another subroutine is called without returning to a subroutine from the main routine, more overhead is incurred by a subroutine call.
The structure of the second prior art is shown in FIG. 9 in which the value of a program counter is saved in a shift register in order to reduce such an overhead caused by the processing for storing a return address in a memory and for returning as required in the first prior art.
In FIG. 9 which shows the structure of the second prior art, the reference numeral 801 represents a 16-bit address bus, 802 a PC for inputting and outputting 16-bit address data D0 to D15 from/to the address bus 801, 803 an instruction decoder circuit for decoding an instruction code which decodes and outputs specific instruction codes (CALL instruction, RET instruction) onto output signal lines 804 and 805, respectively, according to the time of decoding. 806 represents a bi-directional shift register having a last-in first-out function, in which a plurality of stages of registers 806-1 to 806-n are connected. The bi-directional shift register 806 conducts forward shift and backward shift operation in response to the decode output signals 804 and 805 from the instruction decoder circuit 803. The reference numeral 807 represents a control circuit for controlling input/output of data between the PC802 and the shift register 806.
Operation of the second prior art shown in FIG. 9 will be described. When the CALL instruction is executed at the time of a subroutine call, an address (return address) of an instruction existing subsequent to the above-described CALL instruction in the program is indicated by the PC802. Return address, which is the contents of the PC802, is not saved in the memory. A forward shifting operation of the bi-directional shift register 806 is conducted in response to a timing signal generated by a CALL decode output ("1") of the output signal line 804 of the instruction decoder circuit 803 to save the above-described return address in the bi-directional shift register 806.
Then, when the RET instruction is executed upon completion of the subroutine, backward shifting operation of the bi-directional shift register 806 is conducted in response to a timing signal generated by the RET decode output "1" of the output signal line 805 of the instruction decoder circuit 803, whereby the last return address held in the reverse direction of the bi-directional shift register 806 is output first and returned to the PC802 through the control circuit 807.
In addition, when the CALL instruction is successively executed a plurality of times (in other words, the CALL instruction is executed a plurality of times without execution of the RET instructions), forward shifting operation of the bi-directional shift register 806 is conducted every time the CALL instruction is executed as described above. Then, when the RET instruction is executed after the above-described successive execution of the CALL instructions, the up-to-date data of the return addresses held in the bi-directional shift register is read out onto the PC802 by backward shift of the bi-directional shift register 806. When the same number of the RET instructions as that of the CALL instructions are executed, all the return addresses are taken out of the bi-directional shift register 806.
As described in the foregoing, it is unnecessary to use a memory for the purpose of storing and saving return address data of the PC802. Such an overhead as incurred in the first prior art is therefore eliminated.
In the above-described first prior art, because a specific general-purpose register 531 is regularly used to save a return address, every processing for a subroutine call and every processing for returning from a subroutine require a return address of the general-purpose register 531 to be stored in and returned from a memory. As a result, a return address is so frequently transferred between a general-purpose register and a memory that an overhead is incurred to reduce a processing speed.
In the second prior art structured to save a return address in and return the same to a bi-direction shift register, overhead incurred in saving and returning a return address, which is a shortcoming of the first prior art, is reduced. However, the structure of the second prior art needs provision of another dedicated control hardware including a bi-directional shift register. Large scale CPU and more cost are therefore required.
In addition, weighing speed-up of processing against reduction of circuit scale will find it impossible to adopt such a structure as shown in the above-described second prior art into a single-chip microcomputer and the like which attach great importance to the reduction of circuit scale.

Saving a program counter value as the return address in an arbitrary general purpose register


Systems and methods are provided for managing power consumption of a medical imaging detector by the use of triggering signals, environmental condition data, and/or determination of a variable time interval triggering event that is unique for each power consumption state. Systems and methods are provided for managing power and temperature of a device, after receiving a request for a function to be performed by the device determining an “on” trigger component, an “off” trigger component, associated circuits for performing the received function, providing power to the associated circuits upon the occurrence of the “on” trigger component, and removing power to the associated circuits upon the occurrence of the “off” trigger component. Further, an instruction is described for determining and displaying a variable time interval that is indicative of a time to change from one state to a desired state.

Many medical devices serve the portable healthcare and emergency response markets. Examples of these devices are heart-rate monitors, glucometers, electrocardiogram (ECG) monitors, ultrasound imaging devices, and diagnostic medical imaging devices such as digital radiographic detectors. Regardless of the application, these devices must be small in size, lightweight and battery powered to provide the user of the device with optimum mobility and ease of use. However, the requirements necessary to achieve portability result in severe constraints on space, weight and power dissipation causing an increase in the amount of heat energy generated by the components of the medical device. The primary sources of heat are the various integrated circuit components, and rechargeable batteries that power the device when in use or when battery charging takes place. The net result is that the heat contributes to an overall rise in temperature with both application and structural effects on the medical device. Structural effects or excessive heat generated by small portable electronic devices reduces battery life, reduces component life, reduces the reliability of the device, and increases device failure.
In diagnostic medical imaging devices the problem of heat generation is a greater concern due to high power requirements, usage of complex circuitry for optimal performance that is highly sensitive to heat, and patient safety. In particular, while the high power and high circuit density required by the portable battery powered diagnostic medical imaging devices further exacerbate the problem of heat generation, these devices must satisfy certain medical safety requirements regulating the maximum external surface temperature of the device to insure patient safety. Present medical safety requirements regulating temperature mandate that the maximum allowable external surface temperature of a medical device (i.e., the "skin" temperature) not exceed 50 degrees ° C. (122 degrees Fahrenheit), thereby ensuring that contact with a patient will not result in patient discomfort or burning. More specifically, there several regulations and rules regarding the temperature of medical devices, such as IEC 60601-1 promulgated by the International Electrotechnical Commission. These regulations are known to the practitioners of the art.
In the case of digital radiographic or digital x-ray, the electronics in the detector generates a significant amount of heat during image acquisition, due to their electrical power consumption, but can be operated at reduced power when no image is being taken. These devices include a source for projecting an x-ray beam toward an object to be analyzed, such as a medical patient. After the beam passes through the patient, an image intensifier converts the radiation into a signal. With solid state digital x-ray detectors, the photodiode detector elements produce electrical signals that correspond to the brightness of the picture element in the x-ray image projected onto the detector. The signals from the detector elements are read out individually and digitized for further image processing, storage and display, typically by a computer. However, to achieve the required image quality, some time is required for electronic signal levels to fully stabilize between the image detector being restored to full power and acquisition of an image. This stabilization time to interfere with the process of acquiring the image is undesirable because the patient may be in an uncomfortable position, required to hold their breath for the image, or other reasons.
To add to the complexity of the problem the imaging performance characteristics of the detector vary with the temperature of the panel and the temperature of the pixel array. For optimum imaging performance, the panel temperature must remain within a range of temperatures. Techniques utilizing higher x-ray power and longer exposures are in demand in order to provide better images. Thus, there is an increasing demand to remove as much heat as possible from the x-ray tube, as quickly as possible, in order to increase the x-ray exposure power and duration before reaching the operational limits of the tube. At full power, the electronics of the detector consume sufficient power and generates sufficient heat to require a thermal management control subsystem to maintain the panel within the optimum imaging temperature range. Previous attempts at developing cooling systems to remove the heat energy from the relatively high-density packaging of radiographic digital image detectors have primarily used thermal convection systems. These systems move large volumes of heat absorbing air or fluid through the radiographic digital image detector to remove the heat energy created by operation of the device. This large volume requires open spaces around the digital radiographic detector. The necessity of these open spaces limits the overall density of the storage devices relative to the volumetric space of the storage system. However, this technique depletes the finite amount of energy especially in a portable device.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a reliable, simple and efficient manner to provide a thermal management system in a portable battery powered electronic device, and particularly, in a portable battery powered diagnostic medical imaging device, which addresses the foregoing problems. There is also a need for improved management of power consumption in portable devices such as digital radiographic detector to increase power conservation and increase efficiency.

Digital radiography detector with thermal and power management


A secondary battery includes an electrode assembly including a positive electrode, a negative electrode, a first separator disposed on one side of the surface of the negative electrode and having a thickness T1, and a second separator disposed on the other side of the surface of the negative electrode and having a thickness T2. The thickness T2 of the second separator is larger than the thickness T1 of the first separator. The first separator includes a first porous film having a porosity P1, and the second separator includes a second porous film having a porosity P2. At least one of the first separator and the second separator includes a heat resistant layer. The positive electrode, the first separator, the negative electrode and the second separator are wound together such that the first separator is arranged on the outer side and the second separator is arranged on the inner side.

In recent years, electronic devices are rapidly changing to portable and cordless formats. Compact consumer secondary batteries having a high energy density are used as power supplies for the driving of these devices. Further, large secondary batteries are developed as electrical power storage systems and power supplies for driving electric vehicles. Secondary batteries require characteristics such as high output characteristics, durability and safety.
Incidentally, a secondary battery including a wound electrode assembly tends to have a gradient of the concentration of an electrolytic solution within the electrode assembly. A wound electrode assembly is composed of a positive electrode, a negative electrode and a separator which are wound together. The electrodes have a higher curvature in the inside (the center of the coil) than in the outside, and consequently the porosity tends to be more reduced. If an electrolytic solution has a concentration gradient, ions migrate at nonuniform speeds to cause a decrease in output and to adversely affect cycle characteristics.
Patent Literature 1 proposes a lithium ion battery which includes a first separator disposed on the inner side of a positive electrode plate that is coiled, and a second separator disposed on the inner side of a negative electrode plate that is coiled, and satisfies V2>V1 and T2≥T1, or satisfies V2=V1 and T2>T1 wherein V1 and T1 are the void content and the thickness, respectively, of the first separator, and V2 and T2 are the void content and the thickness, respectively, of the second separator. This battery is designed so that the separator on the inner side of the negative electrode plate which tends to be compressed to a smaller porosity will hold more electrolytic solution.

PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.


A reflection type optical scanning system includes a cylindrical lens having positive power in the sub-scanning direction, a deflector, an image forming curved reflection mirror, and an anamorphic lens between the curved reflection mirror and an object surface to be scanned and having at least one toroidal surface with positive power in the sub-scanning direction, along a light path in this order from a light source side. The deflector is arranged so that light emitted from the cylindrical lens is made incident thereupon at a predetermined incident angle in the sub-scanning direction. The curved reflection mirror is made of a barrel-shaped toroidal surface, a cross-sectional in the main scanning direction being a concave arc having a single center of curvature or an arc and a cross-sectional shape in the sub-scanning direction being an arc having a single center of curvature, with respect to the incident light. The position of the center of curvature varies depending on the image height in the main scanning direction. The curved reflection mirror is inclined so that the light incident thereupon from the deflector is reflected by the curved reflection mirror in the sub-scanning direction at a predetermined angle toward the object surface. The axis of the anamorphic lens is deviated from the optical axis of the optical scanning system in the sub-scanning direction.

1. Field of the Invention
The present invention relates to an optical scanning system for a laser printer, or the like.
2. Description of the Related Art
In typical optical scanning systems of the related art, a polygonal mirror, which deflects light emitted from a light source; and a scanning lens, an f.theta. lens which converges the light reflected by the polygonal mirror onto an image surface to scan the same at a constant speed; are provided.
However, in general, the f.theta. lens is made of a plurality of lenses of a complex shape having toric lens surfaces, hence being difficult to accurately produce the f.theta. lens. If a lens made of a plastic material which can be easily machined is used, the plastic material must have good transparent properties, hence, limiting the selection of materials which can be used. Consequently, a reflection type optical scanning system has been recently proposed in which a reflection mirror with a curved surface is employed for constant speed scanning, in place of an f.theta. lens.
In an optical system using a curved reflector (a curved mirror), it is necessary to provide a half mirror to split incident light from a deflector and emission light from the curved reflector. However, the quantity of light which can be transmitted is reduced by the half mirror. Moreover, in the optical system, the curved reflector must be inclined with respect to the optical axis in the sub-scanning direction. Consequently, a bow (curvature of the scanning lines) is caused.
To eliminate the bow which is caused by the inclination of the curved reflector in the sub-scanning direction, the light is made incident upon the deflector at a predetermined incident angle in the sub-scanning direction.
Recently, a multiple beam scanning system has been proposed in which beams which are spaced in the main scanning direction and the sub-scanning direction are simultaneously moved to carry out a high-speed drawing operation. In such a multiple beam scanning system, it is preferable that the distance between the scanning lines be kept constant. However, there is a possibility that the distance between the scanning lines will vary depending on the image height in the sub-scanning direction. The difference in the curvature between the scanning lines is referred to as a differential bow. The differential bow leads to an irregular or uneven drawing or reduces the drawing efficiency. The differential bow is produced, for example, when the magnification in the sub-scanning direction varies depending on the image height in the main-scanning direction.
A reflection type optical scanning system is disclosed in, for example, Japanese Unexamined Patent Publication No. 8-68957. In this scanning system, the curved reflector is inclined in the sub-scanning direction with respect to the optical axis to split the incident light and the emission light. The light is made incident upon a polygonal mirror at a predetermined incident angle in the sub-scanning direction, so that the curvature of the scanning line caused by the curved reflector can be compensated. Other aberrations can be also effectively corrected. However, the f-number in the sub-scanning direction decreases as the image height in the main scanning direction increases. Consequently, the spot diameter on the surface to be scanned varies and a differential bow is still produced.
In order to eliminate the differential bow produced due to the curved reflector being inclined in the sub-scanning direction, the light rays are made incident on the curved reflector at an incline in the sub-scanning direction. Moreover, due to the correction of surface-tilt of the deflector, the incident light rays become image lines. The scanning line of the light rays reflected from the deflector bend in the sub-scanning direction. Since the image line also inclines, distortion of the wave surface (skew distortion) of the light rays occurs.


An optical fiber lighting apparatus includes an exciting light source, a first optical fiber, a second optical fiber, a wavelength conversion unit, and a reflecting member. The first optical fiber guides the exciting light emitted from the exciting light source. The wavelength conversion unit receives the exciting light exiting from the first optical fiber to generate a wavelength-converted light having a wavelength different from that of the exciting light. The second optical fiber guides at least part of the wavelength-converted light generated by the wavelength conversion unit. The reflecting member reflects, of the reflected scattered light and/or the wavelength-converted light generated by the wavelength conversion unit, at least part of light that has not directly struck the incident region of the second optical fiber, toward the incident region of the second optical fiber.

1. Field of the Invention
The present invention relates to an optical fiber lighting apparatus.
2. Description of the Related Art
There has been proposed an optical fiber lighting apparatus that has LEDs arranged at the proximal end portion of an endoscope and guides light to the light-emitting unit at the distal end of the endoscope via an insertion portion by using a fiber bundle. The fiber bundle is a single bundle on the endoscope distal end side but is separated into three parts on the light source side, which are respectively and directly connected to the LEDs that emit red light, green light, and blue light.
This optical fiber lighting apparatus guides illumination light from the endoscope proximal end portion to the endoscope distal end portion by the fiber bundle, and uses only lenses at a light incident portion that causes light emitted from the LEDs to strike the separated incident ends of the fiber bundle. Accordingly, light that is emitted from the LEDs and does not strike the lenses are not used. The light guide efficiency of the system is poor, and sufficiently bright illumination light is hard to obtain.


The invention relates to a multi-speed transmission on a central axis (6a), comprising a drive-side hollow shaft (4a) and an output-side hub sleeve (I) and two, at least two-stage, planetary gearboxes (EG, NSG), arranged coaxially therebetween or therein, each gearbox having sun gears, planetary gears which are connected to one another via associated frames, and ring gears, and each can be shifted into a direct drive and into a plurality of stepped conversion modes, wherein the first planetary gearbox (EG) is driven on its frame (8) and can be selectively shifted, by means of three clutches (20, 30, 40), into the direct drive or by axially fixing individual sun gears (9c,9d) into said transmission modes, and the second planetary gearbox (NSG) can be shifted by further clutches (50, 60, 70, 80, 90) by means of an axial fixing of the sun gear (204) when the input drive and output drive are shifted between its ring gear (200) or frame (202) into a conversion mode at a low speed and into a conversion mode at high speed and directly into a gear. By means of an axially displaceable control slide, spring-loaded, radially extending coupling rings (e.g 91a, 91b) of a respective gear stage can be released, such that the control slide is guided in helical circular grooves (24 . . . 94) of a coaxial switching drum (6b) and in radial slots that are oriented parallel to the gear axis of a hollow axle (6a) enclosing them, respectively actuating the associated coupling rings.

A similar multi-speed transmission is known from EP 0915 800 B1. This comprises an axle which can be mounted non-rotatably on a bicycle frame, a driver rotatably mounted on the axle, a sleeve rotatably mounted on the axle, a gear shift mechanism provided with a first and a second planetary gearbox arranged in the sleeve and coupled to the driver and the sleeve to provide multiple gear ratios between the driver and the sleeve, the planetary gearboxes comprising at least two sun gears coaxial with the axle, have at least one planet carrier with correspondingly stepped planet gears engaging with the two sun gears and at least one ring gear engaging with the planet gears as well as a shifting device for selecting the transmission ratios by selectively connecting the sun gears to the axle, for which purpose the shifting device has means for selectively connecting the ring gear or the planet carrier of the first and/or second planetary gearbox to a sun gear of the same planetary gearbox. This preferably results in a 7×2=14-speed gearbox, in which a seven-speed gearbox, consisting of a direct gear and two two-stage manual gearboxes, is coupled in series with another gearbox, which has a direct gear and a shiftable planetary arrangement. The gears are shifted with 4 pawls, 3 axial clutches and 6 planetary sets, which are arranged to form three two-stage planetary arrangements. The disadvantage of this arrangement is the low input torque, which results in a preferred chain or belt gear ratio of preferably 2.5. The sun gears are axially fixed with pawls, which requires an internal gearing of the same, which is loaded asymmetrically by the pawls—for space reasons only one per sun gear—and only on one internal tooth. A further disadvantage is that no thru axle can be used.
A further multi-speed transmission is known from EP 2 028 096 A1, in which only 5 planetary sets, formed by a double and a triple stepped planet, but 12 clutches are provided.
The disadvantage of this arrangement is that six of the clutches are pawls which serve to fix the axes of the 4 sun gears. Other clutches, which act axially, have approximately ring gear diameters. In addition, the ring gears must be supported on their large diameters. The shifting mechanism of the transmission is very complex and costly to manufacture. In addition, the stepped planets cannot be supported by roller bearings, since some planets have a small number of teeth (14 or 15 teeth). A 12 mm thru axle is also not realizable. The input gear, consisting of two sun gears, two hollow gears and three triple stepped planets, provides three fast gear ratios in addition to the direct gear. The first gear of this transmission is the direct gear, which is formed by the coupling of planet carrier and ring gear. In the second and third gear, the transmission forms two sub-transmissions, but these are different for each of the two gears. The fourth gear is a simple planetary gearbox driven by the planet carrier with a double-step planet. The overall design results in a high number of different complex parts and a total mass that is significantly higher than the mass of the gearbox known from EP 0 915 800 B1.
Furthermore, multi-speed hub gears with three or four planetary sets are known from U.S. Pat. No. 9,279,480 B2, which can be coupled in various ways by nine clutches.
The clutches are actuated by a camshaft which actuates radial shifting means.
The disadvantages here are the low input torque that can be tolerated and the large number of different, complex production parts.
In the state of the art, transmissions of this type are shifted with pawls, which are supported in apertures in a transmission axle, controlled by cams on a shift shaft, and folded out or in (cf. EP 2028 096 A1; DE 10 2010 051.727 A1). If a gear wheel is to be fixed to the axle, the pawl folds out and engages in an internal toothing of the gear wheel to be fixed. On the one hand, the internal gearing has a notch effect, and on the other hand, the gear wheel is subjected to punctual internal loading. The wall of the hollow axle must be relatively thick-walled due to the high forces and thus have a relatively large diameter. It is known that pawls are difficult to collapse under load. A further switching type is shown in the U.S. Pat. No. 9,279,480 B2, where radial cams actuate the switching means.
Common to all these well-known hubs is that the drive pinion mounted on a hollow shaft has about half—or considerably less—the number of teeth than a pedal crank output blade usually has, because the input forces that can be tolerated are relatively low.
The toothed belts that are now widely used as a means of transmitting power to the rear wheel require a significantly larger number of teeth on the rear wheel because of their rigidity. The e-bikes that have been on the market for several years now enable higher average speeds, which in turn require a high transmission ratio bandwidth. Meanwhile, the 5 mm quick-release axle, which is used to clamp a hub in the rear triangle or fork, is increasingly being replaced by thru axles. In the rear wheel a diameter of 12 mm is common. The thru axle is mostly a long screw with a short 12 mm thread. The thru axle is inserted from one side through a suitable hole, passed through the hollow hub axle and then screwed into the thread of the opposite drop out. When tightening, the connection is preloaded.

Multi-speed transmission with two planetary gears


A system for reliably indexing and separating sidewall core samples obtained with a sidewall coring tool comprises markers made of a magnetic material and a mechanism body made of a combination of magnetic and non-magnetic materials to reliably insert and position markers in between successive core samples. The sidewall core is not altered in any way by the marking process. Further, a flexible rubber boot apparatus is disclosed to ensure the complete transfer of retrieved samples in cases where the sample is broken, shattered or segmented and to ensure that broken, shattered or segmented cores will be retrieved in cases where the borehole is horizontal and the tool must operate in a horizontal position or in any other rotational orientation.

The subject matter of the present invention relates to an improved core marking system for a borehole sidewall coring tool adapted for use in a wellbore.
Sidewall coring tools are used for the purpose of obtaining a sample of a formation traversed by a wellbore. In the following discussion, the terms "sample", "sidewall core", "core sample" and "core" are used interchangeably. In each sidewall coring tool, a marker system is used to mark each sample of the formation in order to obtain an indication of the depth of the sample in the wellbore. For example, U.S. Pat. No. 4,714,119 to Hebert et al, which issued Dec. 22, 1987 (hereinafter referred to as "the Hebert patent") is directed to a sidewall coring tool that is adapted for cutting and obtaining sidewall cores of a formation traversed by the borehole, the direction of the cut being perpendicular to an axis of the borehole. The disclosure of the Hebert patent is incorporated by reference into this specification. However, although the marker system used in connection with the Hebert patent has performed adequately, a need has arisen for an improved, more reliable marker system for use in connection with borehole sidewall coring tools.
The proper operation of a marker or indexing system is important because it is the principal method by which the retrieved sidewall samples are identified and correlated to the depths at which they were taken. Failure to properly identify the cores leads to the loss of all retrieved samples, since the interpretation, analysis and information concerning the retrieved samples is of value only when the correct depth of origin is known. If the depth of origin of one sample is unknown, the origins of all of the samples become subject to question.
Therefore, the potential for failure of the entire operation exists when the marking system malfunctions. In a horizontal wellbore, such a service might not even be attempted if it was believed that no indexing system would be present or available. Typical operational problems, encountered by the operators of a sidewall coring tool, are high borehole fluid density and high borehole fluid viscosity. In gravity feed marking systems, such as those described in U.S. Pat. Nos. 4,449,593 and 4,714,119, proper functioning of the tool relies on having the marker fall into a core storage tube or vessel driven exclusively by the force of gravity. However, fluid densities can be high (sometimes in excess of twice the density of water). As the difference in the fluid density and the marker's density decreases, the buoyancy of the marker increases, and the tendency of the marker to fall decreases. High fluid viscosity is a more significant problem when the viscosity is high. The fluid is essentially a thick gel, and the markers as described in U.S. Pat. Nos. 4,449,593 and 4,714,119 are being held in suspension by the high viscosity fluid. This leads to erroneous placement or lack of placement of markers and subsequent improper indexing of core samples. This combination of high fluid density and high viscosity, which is commonly encountered, can prevent the marker from dropping at all. In high viscosity conditions, the markers tend to stick to the marker kicker and may be retracted when the marker kicker retracts. Examples of marker kicker devices are shown in U.S. Pat. No. 4,714,119 (element 65, "kicker foot") and U.S. Pat. No. 4,449,593 (element 72, "wafer ejector"). The problems presented by borehole fluid conditions exist in both horizontal and vertical tool positions. All of the above problems have been routinely cited by operating field locations as problems which they encounter during field operations.
Another problem involves the debris which exists in and around the core storage area. Debris in the well bore can be present in the form of rock cuttings from the borehole drilling process left in suspension in the borehole fluid or rock fragments knocked loose from the borehole wall by the motion of the entire apparatus. In addition, the drilling of the sidewall sample itself produces debris. Debris obstructions in the area leading to the core storage area can prevent recovery of the sidewall sample. Further, debris can also impede the delivery of the marker to the core storage area if the debris accumulates in front of the marker itself. This prevents the marker from being moved to the proper position. In addition, debris inside the core storage tube occupies space which is designated for core storage, reducing the maximum number of samples which can be recovered.
It has been found that the recovery from an oil well can be substantially increased in some cases by making the wellbore horizontal in the section of the well which will produce the petroleum. Recent improvements in the methods and practices for drilling of wells with horizontal boreholes have allowed horizontal drilling to become much more common place than was previously the case. It is common practice to refer to the well bore deviation with reference to the surface of the earth, so that well bores perpendicular to the surface of the earth are said to be vertical. In the course of evaluation of these wells, it is expected that most wireline formation evaluation tools must be able to operate in a horizontal position. Positioning the tool horizontally presents a new set of problems in addition to those posed by borehole fluid conditions. The system, used by the devices described in U.S. Pat. Nos. 4,449,593 and 4,714,119, has two problems: first, horizontal positioning removes the gravity force required to move the marker into the core storage tube; in these systems, the marker can either fall sideways away from the funnel as it is moved by the marker kicking device or it could fall into the funnel, and, depending on the angular orientation of the tool, fall out of the funnel into the borehole; and second, with the tool mechanism in the horizontal position, pieces of segmented, broken or fragmented cores are lost as the core is being directed to the core tube by the core pusher assembly. For the purposes of evaluation and analysis of the core, it is desirable to have as much of the core sample as possible. In addition, pieces of the core which fall out could jam the mechanism and prevent core removal. Segmented, broken and fragmented cores are observed reasonably frequently during sidewall coring operations. The condition of the core cannot be predicted, nor can it be assumed that recovered cores will be in one piece since the reasons for broken cores are also varying and unpredictable.
Thus a properly functioning marking system is critical for wellsite operations in order to ensure that the sidewall coring tool can be considered for use in the maximum number of potential applications and in different situations. In addition, it is important in all situations that as much of the core be recovered as possible to allow for the optimal analysis of recovered samples.
As a result, the need exists for an improved core marking system for use with a sidewall coring tool, which core marking system will reliably mark, index, and separate both whole and fragmented sidewall core samples regardless of the deviation of the wellbore in which the sidewall coring tool is disposed.

Core marking system for a sidewall coring tool


A plastic lens, comprising: a first edge section having a first outer circumferential edge surface formed substantially parallel to an optical axis of the plastic lens; and a second edge section having a second outer circumferential edge surface formed so as to have a step with respect to the first outer circumferential edge surface, wherein the first outer circumferential edge surface is not coated with a black coating material that suppresses internal reflection of light, and at least a portion of the second outer circumferential edge surface is coated with the black coating material that suppresses internal reflection of light.

1. Field
The present disclosure relates to plastic lenses and lens barrels.
2. Description of the Related Art
When a light beam is incident on an imaging optical system composed of a plurality of lenses, such as a zoom lens system or a single focal length lens system, a portion of the incident light is reflected at an inner surface of an outer circumferential part of each lens. Therefore, the reflected light, which is undesired light, might be cast into the range of an aperture for photographing. If such undesired light reaches an imaging surface, noise such as flare or ghost occurs, and thereby image characteristics are deteriorated.
In order to suppress occurrence of such undesired light that causes noise such as flare or ghost, various kinds of lenses each having an outer circumferential part subjected to black coating have conventionally been proposed.
Japanese Laid-Open Patent Publication No. 11-337707 discloses a lens in which a cut plane as an edge plane of an outer peripheral part is entirely coated with a black non-transmitting coating serving as means for preventing reflection of a harmful light beam.
Japanese Laid-Open Patent Publication No. 2008-129133 discloses an image forming lens for use in an image pickup module, in which a portion of an outer peripheral part of a flange, on which a taper is formed, is coated with an adhesive agent containing a black coating material.
Japanese Patent Publication No. 61-043688 discloses a reflection objective lens having an annular part entirely coated with a black coating material.
Japanese Laid-Open Patent Publication No. 11-326604 discloses a lens in which a taper is formed on a side surface, and each rough surface on an incident surface side where the taper is formed is entirely black coated.
Further, as a lens constituting the imaging optical system, a lightweight and relatively inexpensive plastic lens has been widely used. Also in the case of using such a plastic lens, occurrence of undesired light that causes noise such as flare or ghost needs to be suppressed.
In the case of a lens made of a glass material, a coating material for coloring the lens in black is usually less viscous, and therefore, can be relatively easily applied to a target surface. Accordingly, uneven coating, such as excess/shortage of a coating range or an uneven thickness of a coating layer, is less likely to occur, decentering error is not increased so much, and dimensional accuracy of the lens diameter is not lowered so much.
However, in the case of a plastic lens, a coating material for coloring the plastic lens in black is usually highly viscous, and particularly the thickness of a coating layer is likely to be increased more than necessary, which might cause uneven coating. Accordingly, in order to suppress an increase in decentering error and maintain the dimensional accuracy of the lens diameter, a target surface to be coated should be limited to a portion of a side surface of the lens. Further, if such a highly viscous coating material is applied to a portion of the side surface where a taper is formed, the thickness of the coating layer becomes uneven and the coating range is excessively increased. Accordingly, it is very difficult to suppress an increase in decentering error, and maintain the dimensional accuracy of the lens diameter.


The invention includes a filter element comprising a dielectric substrate and a strip conductive pattern formed on the dielectric substrate. The dielectric substrate has cavities with apertures on the surface of the dielectric substrate. The strip conductive pattern is formed over the apertures of the cavities to serve as inductance. The strip conductive pattern has an approximately uniform line width that effectively improves the production yield and reliability of the filter element.

1. Field of the Invention
The present invention relates to a filter element, and more particularly relates to a distributed constant filter.
2. Description of Related Art
Cellular telephones, radio-Local Area Networks (radio-LAN), and other high frequency communication devices that use a microwave band or milliwave band carrier typically have filter elements, such as low pass filter (LPF) and band pass filter (BPF). The filter elements may be designed using a distributed constant filter formed with a conventional microstrip transmission line. Unlike filter elements that have a composite component consisting of an inductor (L) and a capacitor (C) that are combined to form an L-C circuit having a concentrated or lumped constant L-C parameter, a conventional microstrip transmission line has serially distributed L and C parts formed on a substrate as shown in FIGS. 1 and 2.
FIG. 1 is a plan view illustrating the structure of a conventional filter element 10 formed with a microstrip transmission line. The conventional filter element 10 includes a dielectric (or insulating) substrate 12 such as a ceramic substrate or a printed substrate (e.g., a dielectric, such as silicon dioxide or silicon nitride, is deposited on a substrate and then masked using known fabrication techniques to form a printed dielectric pattern on the substrate). The conventional filter element 10 also includes a strip conductor pattern 14 formed on the dielectric substrate 12, and I/O electrodes 16 and 18 that are electrically connected to the strip conductor pattern 14. The strip conductor pattern 14 includes a first group of segments 20, 22, 24, and 26 that function as inductors and a second group of segments 28, 30, and 32 that function as capacitors. Each inductor segment 20, 22, 24 and 26 has a width (e.g., width 23 of inductor segment 20 as shown in FIG. 1) of about 0.1 millimeters (mm) and a length (e.g., length 21 of inductor segment 20) of about 0.3 mm. Each capacitor segment 28, 30, and 32 has a width (e.g., width 29 of capacitor segment 28 as shown in FIG. 1)of about 5 mm and a length (e.g., length 27 of capacitor segment 28)of about 3 mm. The conventional filter element 10 shown in FIG. 1 is a microstrip line LPF that has an impedance which is varied alternately as a result of forming the strip conductor pattern 14 on the dielectric substrate 12. By forming the strip conductor pattern 14 to have inductor segments and capacitor segments that are optimally sized, a signal in a bandwidth higher than a desired frequency can be attenuated.
An equivalent electrical circuit representation 50 of the conventional filter element 10 is shown in FIG. 2. The inductor segments 20, 22, 24, and 26 correspond to the inductors 52, 54, 56, and 58, respectively. The capacitor segments 28, 30, and 32 correspond to the capacitors 60, 62, and 64, respectively. Because the inductor segments and the capacitor segments in the conventional filter element 10 have a flat structure, the filter element 10 can be formed simultaneously in a process for forming a wiring pattern on a mounting substrate using known printing or lithography techniques.
However, in forming the conventional filter element 10 as described above, a problem arises where the inductance effect (e.g., ability to oppose any change to a electrical current flowing through the filter element) of the equivalent electrical circuit 50 shown in FIG. 9 is reduced due to a parasitic capacitance of the portion of the dielectric between the substrate 12 and the strip conductor pattern 14 that occurs when a signal in the frequency range of microwave and milliwave is transmitted through the filter element 10. Parasitic capacitance, for example, may be the capacitance or collection of charge between a conduction layer, such as the strip conductor pattern 14 and a base, such as the substrate 12. Parasitic capacitance, which degrades the performance of a circuit on a substrate or chip, is not intentionally designed into the chip or circuit but is rather a consequence of the layout of the circuit on the chip. This problem of parasitic capacitance is particularly prevalent when the transmitted signal through the conventional filter element 10 is in the frequency range exceeding 5 GHz.
To prevent the reduction in the inductance effect of the equivalent electrical circuit 50 and to obtain the desired filter performance, the inductance in the conventional filter element 10 is increased by thinning the width of the inductor segments 20, 22, 24 and 26 in the strip conductor pattern 14 shown in FIG. 1. Further, to reduce the passband loss of the filter element 10, the length of each inductor segment 20, 22, 24, and 26 is reduced substantially. Passband loss, defined in decibels (dB), describes the absolute loss across a band of frequencies the conventional filter element 10 is supposed to pass.
By substantially reducing the width and the length of the inductor segments 20, 22, 24, and 26 within the strip conductor pattern 14, the resulting conventional filter element 10 has the following other problems:
1) The inductor segments 20, 22, 24, and 26 may require micrometer (xcexcm) order accuracy in fabrication, making it difficult to obtain a high production yield for the conventional filter element 10.
2) The significantly reduced length of the inductor segments 20, 22, 24, and 26 results in an unintentional strong electromagnetic coupling between respective adjacent capacitor segments 28, 30, and 32, which impacts the desired performance of the filter element 10.
3) The difference in line width between the inductor segments 20, 22, 24, and 26 and the capacitor segments 28, 30, and 32 is significantly large. The line width of one capacitor segment (i.e., 28, 30, or 32 in FIG. 1) may be 10 times that of the one inductor segment (i.e., 20, 22, 24, and 26 in FIG. 1). The large difference in line width causes a large stress at the contact or connection between the inductor segments 20, 22, 24, and 26 and the capacitor segments 28, 30, and 32 as a result of temperature cycling during operation of the conventional filter element 10. The large stress may cause a disconnection between a respective inductor segment and capacitor segment in the strip conductor pattern 14. Thus, the conventional filter element 10 has poor reliability due to this disconnection problem.
4) If a device which generates heat during operation, such as a power amplifier, is mounted on the substrate 12 on which the filter element 10 has been formed, heat from the power amplifier may burn or melt one of the thin inductor segments 20, 22, 24, and 26, causing a disconnection in the strip conductor pattern 14.
Thus, a filter element that is formed with a conventional microstrip line has several significant problems, such as low production yields due to the difference in size in line width of the inductor segments and capacitor segments formed in the conventional microstrip line, and disconnections in the conventional microstrip line due to the stress caused between connections of inductor segments and capacitor segments during temperature cycles of the conventional microstrip line.
The present invention works toward providing an improved filter element that is formed with a microstrip line that has uniform line width to effectively improve the production yield and reliability of the improved filter element. The present invention also works toward providing a fabrication method for producing the improved filter element at high production yield.
The present invention provides a filter element fabricated by forming a strip conductive pattern on a dielectric substrate that has a surface and a cavity with an aperture disposed on the surface of the dielectric substrate, wherein the strip conductive pattern is formed over the aperture of the cavity.
The present invention also provides a filter element fabricated by forming a strip conductive pattern on a dielectric substrate that has a first portion and a second portion, the first portion having a higher relative dielectric constant than the second portion, wherein the width of the strip conductive pattern is maintained constant and the strip conductive pattern is formed over both the first and second portions of the dielectric substrate.
The present invention provides a method for fabricating a filter element that includes a strip conductive pattern on a dielectric substrate, wherein the method for fabricating the filter element comprises forming a cavity with an aperture disposed on the surface of the dielectric substrate, filling a material in the cavity so as to flatten the surface of the dielectric substrate, forming the strip conductive circuit pattern on the dielectric substrate so that the strip conductive pattern is over the aperture of the cavity, and removing the material from the cavity.


This invention relates to a liquid crystal display device that reduces a parasitic capacitance, and a fabricating method thereof.

1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly to a transflective thin film transistor substrate that reduces parasitic capacitance, and a fabricating method thereof.
2. Discussion of the Related Art
A liquid crystal display device controls a light transmittance of a liquid crystal that has dielectric anisotropy, by use of an electric field, thereby displaying a picture. The liquid crystal display device includes a liquid crystal display panel for displaying a picture through a liquid crystal cell matrix and a drive circuit for driving the liquid crystal display panel.
Referring to FIG. 1, a liquid crystal display panel of the related art includes a color filter substrate 10 and a thin film transistor substrate 20 that are bonded together with a liquid crystal 24 therebetween.
The color filter substrate 10 includes a black matrix 4, a color filter 6, and a common electrode 8 that are sequentially formed on an upper glass substrate 2. The black matrix 4 is formed in a matrix shape on the upper glass substrate 2. The black matrix 4 divides an area of the upper glass substrate 2 into a plurality of cell areas where the color filters are to be formed, and the black matrix 4 prevents light interference between adjacent cells and an external light reflection. The color filter 6 is divided into red R, green G, and blue B in the cell areas divided by the black matrix 4. The common electrode 8 formed of a transparent conductive layer on the entire surface of the color filter 6 supplies a common voltage Vcom or a reference voltage when driving a liquid crystal 24. Also, an overcoat layer (not shown) might be further formed between the color filter 6 and the common electrode 8 to level the color filter 6.
The thin film transistor substrate 20 includes a thin film transistor 18 and a pixel electrode 22 that are formed at each cell area defined by the crossing of a gate line 14 and a data line 16 on a lower glass substrate 12. The thin film transistor 18 supplies a data signal from the data line 16 to the pixel electrode 22 in response to a gate signal of the gate line 14. The pixel electrode 22 formed of the transparent conductive layer supplies the data signal from the thin film transistor 18 to the liquid crystal 24.
The liquid crystal 24 having dielectric anisotropy controls the light transmittance by rotating the liquid crystals in accordance with an electric field formed by the data signal on the pixel electrode 22 and the common voltage Vcom of the common electrode 8.
The liquid crystal display panel further includes a spacer (not shown) for uniformly maintaining a cell gap between the color filter substrate 10 and the thin film transistor substrate 20.
The color filter substrate 10 and the thin film transistor substrate 20 of the liquid crystal display panel are formed by use of a plurality of mask processes. One mask process includes many processes such as depositing (coating) a thin film, cleaning, photolithography, etching, photo-resist stripping, inspecting, etc. Specifically, the thin film transistor substrate is manufactured using a semiconductor process and requires a plurality of mask processes, thus its fabricating process is complicated is a major contributor to the manufacturing cost of the liquid crystal display panel.
Further, the liquid crystal display panels are divided into three different types: a transmission type that displays a picture by use of a light incident from a backlight unit; a reflection type that displays a picture by reflecting an external light such as a natural light; and a transflective type that combines the transmission type and the reflection type.
There is a problem in that the transmission type display consumes too much power due to the backlight and the reflection type display cannot display a picture in a dark environment because the reflection type depends on the external light. But, the transflective type display operates in a reflection mode if the external light is sufficient and in a transmission mode using the backlight unit if the external light is not sufficient, thus the power consumption can be reduced versus the transmission type display and the transflective type display is not dependent on external light like the reflection type.
To this end, the transflective type liquid crystal display panel has each pixel divided into a reflection area and a transmission area. Accordingly, the transflective thin film transistor substrate should further include a reflection electrode formed in the reflection area, and an organic insulating film formed to be relatively thick under the reflection electrode in order to equalize a light path length of the reflection area to that of the transmission area. As a result, the number of mask processes increases, so that the related art transflective thin film transistor: substrate has a problem in that its fabricating process is more complicated.
Further, the related art transflective thin film transistor substrate has a pixel electrode that overlaps both side parts of the data line, thus a parasitic capacitance is increased generating problems such as vertical cross talk, increased of power consumption etc.
FIG. 2 is a plan view illustrating a part of a transflective thin film transistor substrate according to the related art, and FIGS. 3 and 4 are cross sectional views illustrating the transflective thin film transistor substrate shown in FIG. 2, taken along the lines I-I′, II-II′.
The transflective thin film transistor shown in FIGS. 2 to 4 includes: a gate line 102 and a data line 104 that are formed on a lower substrate 142 to cross each other with a gate insulating film therebetween to define a pixel area; a thin film transistor 106 connected to the gate line 102 and the data line 104; a reflection electrode 152 formed in a reflection area of each pixel; a pixel electrode 118 formed at each pixel area connected to the thin film transistor 106 through the reflection electrode 152; a storage upper electrode 122 connected to the pixel electrode 118 through the reflection electrode 152; and a storage capacitor 120 formed to overlap the pre-stage gate line 102.
The thin film transistor 106 includes a gate electrode 108 connected to the gate line 102; a source electrode 110 connected to the data line 104; a drain electrode 112 that faces the source electrode 110 and is connected to the pixel electrode 118; an active layer 114 that overlaps the gate electrode 108 with a gate insulating film 144 therebetween to form a channel between the source electrode 110 and the drain electrode 112; and an ohmic contact layer 116 formed on the active layer 114 except in the channel region for being in ohmic contact with the source electrode 110 and the drain electrode 112.
Herein, the gate line 102 and the gate electrode 108 has a double layer structure where a first conductive layer 101 of a transparent conductive layer is deposited and a second conductive layer 103 of a metal layer is deposited thereon.
Then, a semiconductor pattern 115 including the active layer 114 and the ohmic contact layer 116 is formed to overlap the data line 104.
The reflection electrode 152 formed in the reflection area has an embossed shape in accordance with a shape of an organic insulating film thereunder, thereby increasing the reflection efficiency by a scattering effect.
The pixel electrode 118 is connected to the drain electrode 112 through the reflection electrode 152 that is formed at each pixel area and passes through an edge area of a transmission hole 154. The pixel electrode 118 has a double layer structure where the first and second conductive layers 101, 103 are deposited like the gate line 102, and the second conductive layer 103 is opened in the transmission area leaving just the first conductive layer 101 of the transparent conductive layer exposed to a transmission area.
The transmission hole 154 is formed to penetrate from an organic insulating film to the gate insulating film in the transmission area. Accordingly, the length of the light path passing through a liquid crystal layer in the reflection area becomes equal to that in the transmission area, thus the transmission efficiency of the reflection mode becomes the same as that of the transmission mode.
The storage capacitor 120 is formed by connecting a storage upper electrode 122 to the pixel electrode 118 to overlap the pre-stage gate line 102 with the gate insulating film 144 therebetween. The storage upper electrode 122 is connected to the pixel electrode 118 through the reflection electrode 152 passing through an edge area of the transmission hole 154, and the semiconductor pattern 115 further overlaps with and under the storage upper electrode 122.
In this way, in the transflective thin film transistor substrate shown in FIGS. 2 to 4, the pixel electrode 118 with the double structure is formed together with the gate line 102, and the second conductive layer 103 is etched through the reflection electrode 152, and the first conductive layer 101 is exposed in the transmission area. Further, the pixel electrode 118 is connected to the drain electrode 112 and the storage upper electrode 122 through the reflection electrode 152. Accordingly, the transflective thin film transistor substrate may be formed by four mask processes.
On the other hand, as shown in FIG. 4, the reflection electrode 156 connected to the pixel electrode 118 overlaps both sides of the data line 104 with the organic insulating film 148 and a passivation film 146 in between, thus the parasitic capacitance Cdp1, Cdp2 is increased. The vertical cross talk and the electric power consumption are increased due to the increase of the parasitic capacitance Cdp1, Cdp2.
In order to solve this problem, the transflective thin film transistor substrate according to the present invention floats the reflection electrode that overlaps the data line, thereby decreasing the parasitic capacitance.

Liquid crystal display device and method for fabricating the same

Abstract: A liquid crystal display device, including: a gate line with a multi-layer structure having a transparent first conductive layer and an opaque second conductive layer; a data line crossing the gate line with a gate insulating film in between to define a pixel area; a thin film transistor connected to the gate line and the data line; a pixel electrode formed of the first conductive layer in the pixel area, wherein the second conductive layer remains along an edge of the first conductive layer at an edge of the pixel area; a transmission hole that penetrates from an organic insulating film on the thin film transistor to the gate insulating film to expose the first conductive layer of the pixel electrode; a reflection electrode on the organic insulating film extending along a part of a side surface of the transmission hole to connect the pixel electrode and a drain electrode of the thin film transistor; and a floating electrode on the organic insulating film that overlaps both sides of the data line.


The invention relates to a photosensitive resin composition that has the advantages of high developability, good hardness, and good sputtered resistance. The invention also provides a method for manufacturing a color filter, color filter and a liquid crystal display device. The photosensitive resin composition comprises an alkali-soluble resin (A), a compound containing an ethylenically unsaturated group (B), a photoinitiator (C), an organic solvent (D), a pigment (E), and a compound (F).

1. Field of the Invention
The invention relates to a photosensitive resin composition for a color filter in a liquid crystal display device, and a color filter and liquid crystal display device formed by the aforementioned photosensitive resin composition. More particularly, the invention also provides a photosensitive resin composition for a color filter having high developability, good hardness, and good sputtered resistance and a color filter and liquid crystal display device formed by the aforementioned photosensitive resin composition.
2. Description of the Related Art
With a color filter has been applied widely in a color liquid crystal display device, color fax machine, color camera and other office equipments, the production technology of the color filter also tends to diversify, for example, a dyeing method, a printing method, a plating method, and a dispersion method, and wherein the dispersion method is a mainstream. The dispersion method, first, uses chrome/chromium or a photosensitive resin to form a black matrix for shading on a glass substrate, and coats a photosensitive resin (also referred as color photoresist) dispersed with a red pigment on the glass substrate. After the steps of exposure and development, a red pixel can be obtained. Such process is repeated, and a green and blue pixel can be obtained thereby. The red, green and blue pixels are separated by the black matrix, and a pixel color layer is formed on the glass substrate. A protective film is applied onto the pixel color layer as needed. Then, a transparent conductive film is formed on the protective film. After cutting, the color filter is prepared.
In the process of forming the color filter, the pixel color layer out of a needed pattern is removed after development. Even though in a process of brushing, it also needs to make sure the needed pattern not to be damaged or lacked. Japanese Patent Publication No. 1995-234313 discloses using a specific filler to improve the hardness of the pixel color layer.
In order to simplify the process and pursue high transmittance, the protective film is often omitted. However, because omitting the protective film, the pixel color layer of Japanese Patent Publication No. 1995-234313 can not bear strong electron beam and cleavages in a process of sputtering to form the transparent conductive film.
Therefore, a photosensitive resin composition that enhancing the developability, hardness and sputtered resistance at the same time is a target remained to be achieved.

Photosensitive resin composition and uses thereof


Methods and apparatus to modify alternate storage are disclosed. In an example, a method includes receiving an interface from a device in the pre-boot environment, wherein the interface identifies a location of the device and a location of alternate storage on the device and receiving a request for modification of the alternate storage of the device. The example method may also include receiving modification data to be written into the alternate storage of the device and writing the modification data to the alternate storage of the device using the interface in the pre-boot environment.

Processor-based systems, such as personal computers, typically include a motherboard on which a main processor and memory are disposed. Additionally, the motherboard includes a number of slots into which peripherals may be installed. For example, a personal computer may include peripherals such as a hard drive controller, a display or graphics adapter, a network adapter and a modem, each of which is installed into a slot on the motherboard or is in communication with the motherboard through other means.
Each of the peripherals associated with the processor system includes a memory portion that stores configuration or operation information and data for the peripheral. This information and data is commonly referred to as firmware. The firmware is typically stored in some non-volatile (NV) storage, such as non-volatile random access memory (NVRAM), of which flash memory is one particular example.
Ideally, peripherals are bug free and their firmware is timeless. However, in reality firmware upgrades need to be made to correct bugs and to update firmware for interoperability. The firmware on the peripherals is not, however, openly exposed at a user interface that enables user maintenance of the firmware. The motherboard processor is unable to update the peripheral firmware because the basic input/output system (BIOS) of the processor is unaware of the layout, access methods and protection of the firmware on the peripherals. Accordingly, updating peripheral firmware can be very challenging. Adding to this difficulty, there is presently no standard methodology for carrying out firmware updates on peripherals. For example, some peripheral vendors ship operating system (OS)-specific drivers when firmware upgrades are required. However, such upgrades are not OS agnostic, meaning that a special driver must be written for each OS. For example, if a peripheral vendor wants to distribute a firmware upgrade, the vendor must distribute a Linux version, a Windows NT version, a Windows 95 version, etc.

Methods and apparatus to modify alternate storage in a pre-boot environment


A display sign includes a sign mount configured to engage support rails of a ceiling and a graphics display supported by the sign mount and configured for rotation about 360°. A motor may be provided to power rotation of the graphics display.

Signs for displaying information such as promotional information are generally known. In particular, one class of such signs comprises displays that may be suspended from a ceiling for displaying information such as point of purchase advertising or other information. Some signs may be adapted for suspension from a ceiling of the type that has a latticework of crossing members for holding ceiling tiles. Signs that are known in the art as "light thief" signs are so adapted, and may be suspended below a portion of the ceiling housing a light source, with the light from the source used to illuminate display panels of the sign.
The display panels may, for example, drop generally vertically or at an angle from the ceiling, so that they are visible to one looking from the floor towards that portion of the ceiling. A particular sign may comprise two or more display panels, with an example being a light thief sign that has four panels arranged about its periphery.
The lattice work used to support the ceiling tiles and display signs in such circumstances is generally in the form of a grid, with one set of lattice members, referred to herein as support rails, running along what may be though of as an X axis, and a second set running along what may be thought of as a perpendicular Y axis. The ceiling lattice thereby creates a grid with a plurality of substantially square or rectangular "grid cells" created between intersecting X and Y axis support rails. Each of these grid cells generally holds a square or rectangular ceiling tile, with an occasional cell having alight fixture such as a fluorescent ballasts and bulbs with a translucent panel. Generally, light thief signs are used to replace panels below a light fixture so as to be illuminated by the ceiling light source. Light thief signs can also be used to replace non-illuminated panels.
Display signs such as the described light thief displays as known are limited to placement depending on the lattice grid. That is, such display signs are generally limited to an orientation of display that is determined by the lattice ceiling grid orientation. By way of example, if a light thief display has four display panels oriented in a generally square manner, the panels will be displayed parallel to the X and Y axis of the ceiling lattice when the light thief is installed.
Often, this proves disadvantageous. For example, consider a store having a substantially square floor plan with a liquor department in one corner of the store. The main entry door to the store is at the opposite corner of the store. Further assume that a liquor vendor desires to use a light thief to display promotional advertisements using a light thief in the liquor department. Because the panels of the light thief run parallel to the ceiling lattice, however, the display panels are not oriented to the main entry to the store that is diagonal to the location of the liquor department. Disadvantageously, then, consumers entering the store may not be able to easily read or even see the display panels.
Recently, co-owned and currently pending U.S. application Ser. No. 10/103,388 has been proposed. While the teachings of this application meet some of the aforementioned needs, others are left unresolved.


A transistor including an oxide semiconductor layer and having electric characteristics required depending on an intended use, and a semiconductor device including the transistor are provided. In a transistor in which a semiconductor layer, a source electrode layer and a drain electrode layer, a gate insulating film, and a gate electrode layer are stacked in this order over an oxide insulating film, an oxide semiconductor stack composed of at least two oxide semiconductor layers having different energy gaps is used as the semiconductor layer. Oxygen and/or a dopant may be introduced into the oxide semiconductor stack.

1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
In this specification, a semiconductor device means any device which can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all included in the category of the semiconductor device.
2. Description of the Related Art
Attention has been focused on a technique for forming a transistor using a semiconductor thin film (also referred to as a thin film transistor (TFT)). The transistor is applied to a wide range of electronic devices such as an integrated circuit (IC) or an image display device (display device). A silicon-based semiconductor material is widely known as a material for a semiconductor thin film applicable to a transistor. As another material, an oxide semiconductor has been attracting attention.
A transistor including an oxide semiconductor is required to have excellent electric characteristics for application to semiconductor devices with higher performance. In order to achieve excellent electric characteristics of the transistor including an oxide semiconductor, a technique in which low resistance source and drain regions by an aluminum reaction method has been reported (e.g., see Non-Patent Document 1).
For example, a transistor whose active layer includes an amorphous oxide including indium (In), gallium (Ga), and zinc (Zn) is disclosed (see Patent Document 1).

This patent is subject to a terminal disclaimer.

Semiconductor device and method for manufacturing the same

Semiconductor Energy Laboratory Co., Ltd.


The present invention relates to flame-retardant polycarbonate compositions and methods for increasing the flame-retardancy of polycarbonate compositions. An α,ω-alkoxy phenyl phenyloligosiloxane compound and an alkali metal sulfonate salt are added to the polycarbonate compositions. The addition of the α,ω-alkoxy phenyl phenyloligosiloxane compound and the alkali metal sulfonate salt produces a polycarbonate composition having a flame-retardance rating of UL 94V-0 at 2 mm thickness or less.

Polycarbonate polymers are thermoplastic resins that are useful in a number of plastic material applications including, for example, injection molding, extrusion, rotation molding, blow molding, thermoforming, and the like. Polycarbonate thermoplastic resins exhibit a number of advantageous material properties and mechanical properties including, for example, high impact strength, excellent dimensional stability, glass-like transparency, excellent thermal resistance, and low-temperature toughness. These properties, among others, make polycarbonate thermoplastic resins attractive as engineering materials for a wide variety of applications including, for example, automotive and transportation, building and construction, electrical and electronics, telecommunication, packaging, medical, optical/opthalmic, and optical media. In various applications, flame-retardancy is an important property, for example, in electrical and electronics applications, such as appliance and equipment housings and parts.
Weider, et al., in U.S. Pat. No. 5,693,697 describe the inclusion of 0.5% of diphenyl dimethoxysilane as a flame retardant additive in combination with 0.1% of potassium perfluorobutane sulfonate to provide a composition exhibiting a flame retardance UL94-V0 at 2.6 mm. However, the boiling point of the additive is 304° C. at 760 mm Hg, which is too low for typical extrusion compounding and injection molding of polycarbonate (at 300-370° C.).
U.S. Pat. No. 6,727,302, issued to Goossens, et al., discloses poly(methylphenyl-siloxane) as an efficient flame retardant additive in combination with potassium perfluorobutane sulfonate or KSS (potassium diphenylsulfon-3-sulfonate) for polycarbonate.
Ono, et al., in U.S. Pat. No. 6,727,303 provide a flame retardant aromatic polycarbonate resin composition comprising (1) 100 parts by weight of resin components comprising 50 to 100 wt % of an aromatic polycarbonate resin (component A-1), 0 to 50 wt % of a styrene-based resin (component A-2) and 0 to 50 wt % of an aromatic polyester resin (component A-3); and (2) 0.1 to 10 parts by weight of a silicone compound (component B) which contains an Si—H group and an aromatic group in the molecule based on 100 parts by weight of the total of the resin components, wherein the silicone compound is at least one selected from silicone compounds which have (1) an Si—H group content (Si—H content) of 0.1 to 1.2 mols/100 g and (2) a content of an aromatic group represented by the following general formula (1) (aromatic group content) of 10 to 70 wt %:
wherein X's are each independently an OH group or the residual monovalent organic group having 1 to 20 carbon atoms, and n is 0 or an integer of 1 to 5, with the proviso that when n is 2 or more, X's can differ from one another, and molded articles thereof. A halogen-free polycarbonate resin composition having excellent transparency and dripping preventing properties and molded articles thereof is also provided.
WO 2012/107514, in the name of Meyer et al., provides a flame-retardant thermoplastic molding composition. The composition contains aromatic polycarbonate resin, about 0.01 to 0.15 wt.-% of a salt, wherein the salt is an alkali metal or alkaline earth metal salt of perfluoroalkane sulfonic acid, aromatic sulfimide, aromatic sulfonic acid, and about 0.5 to 10 wt.-% of poly- and/or oligo-aryloxysiloxane as flame-retardant synergist. The composition is characterized in that its flammability rating is better than that of aromatic polycarbonate resin containing only inorganic salt of a derivative from aliphatic or aromatic sulfonic acid, sulphonamide or sulfonimide in accordance with UL-94 V standard, while mechanical and optical properties of the compositions are maintained.
There continues to exist a need in the art for ecologically friendly, transparent polycarbonate compositions which are flame retardant.


An agricultural seeding machine includes at least one tool bar, and a plurality of row crop units, with each row crop unit coupled with a respective tool bar. Each row crop unit includes a seed meter; a ground engaging wheel; a continuously variable transmission (CVT) driven by the wheel; and a rotatable drive element coupled between the CVT and the seed meter.

An agricultural seeding machine such as a row crop planter or grain drill places seeds at a desired depth within a plurality of parallel seed trenches formed in soil. In the case of a row crop planter, a plurality of row crop units are typically ground driven using wheels, shafts, sprockets, transfer cases, chains and the like. Each row crop unit has a frame which is movably coupled with a tool bar. The frame may carry a main seed hopper, herbicide hopper and insecticide hopper. If a herbicide and insecticide are used, the metering mechanisms associated with dispensing the granular product into the seed trench are typically relatively simple. On the other hand, the mechanisms necessary to properly meter the seeds, and dispense the seeds at predetermined relative locations within the seed trench are relatively complicated.
The mechanisms associated with metering and placing the seeds generally can be divided into a seed metering system and a seed placement system which are in series communication with each other. The seed metering system receives the seeds in a bulk manner from the seed hopper carried by the frame. Different types of seed metering systems may be used, such as seed plates, finger plates and seed disks. In the case of a seed disk metering system a seed disk is formed with a plurality of seed cells spaced about the periphery of the disk. Seeds are moved into the seed cells with one or more seeds in each seed cell depending upon the size and configuration of the seed cell. A vacuum or positive pressure air differential may be used in conjunction with the seed disk to assist in movement of the seeds into the seed cell. The seeds are singulated and discharged at a predetermined rate to the seed placement system.
The seed placement system may be categorized as a gravity drop system or a power drop system. In the case of the gravity drop system, a seed tube has an inlet end which is positioned below the seed metering system. The singulated seeds from the seed metering system merely drop into the seed tube and fall via gravitational force from a discharge end thereof into the seed trench. The seed tube may have a rearward curvature which reduces bouncing of the seed as it strikes the bottom of the seed trench.
Conventional techniques for providing rotary power to turn individual seed meters on each row unit of a seeding machine include: a central ground drive transmitted through complex shafting systems; hydraulic motors to turn a complex shafting system which in turn fans out to drive each seed meter; or an electric motor on each row unit to provide the rotational drive to control and drive the corresponding seed meter. Each of these approaches has some major cost, space, reliability, or control disadvantages. Mechanical rotary power transmission has many shafts, chains, bearings, and couplers to cross over frame flex and fold pivots. Individual control of seeding rates is not easily accomplished even with hydraulic drives. Electric motor drives are costly but do offer individual rate control including single row drive disconnects. A disadvantage of electric drives besides cost and generating enough electrical power to handle multiple row machines, is power cable handling and routing through the large machine space frames, across flex and fold pivots, etc.
What is needed in the art is a seeding machine with a seed metering system that allows individual control of the seed meters, while avoiding the disadvantages described above.

Ground driven seed metering system with a continuously variable transmission


A power-efficient wireless device is equipped with multiple (N) antennas. Each antenna is associated with a transmitter unit and a receiver unit. The wireless device also has processing units used to perform various digital processing tasks. The transmitter units, receiver units, and processing units may be selectively enabled or disabled. In an idle state, the wireless device may enable only a subset (e.g., one) of the N receiver units and one or few processing units for signal detection and acquisition. For active communication, the wireless device may enable Ntx transmitter units for data transmission and/or Nrx receiver units for data reception, where 1≦Ntx≦N and 1≦Nrx≦N. The enabled processing units may also be clocked at a lower frequency whenever data is transmitted or received at a data rate lower than the highest data rate. The wireless device may go to sleep whenever possible to conserve power.

I. Field
The present invention relates generally to an electronics device, and more specifically to a multi-antenna wireless device.
II. Background
A multiple-input multiple-output (MIMO) communication system employs multiple (NT) transmit antennas and multiple (NR) receive antennas for data transmission. A MIMO channel formed by the NT transmit antennas and NR receive antennas may be decomposed into NS spatial channels, where Ns≦min {NT, NR}. The NS spatial channels may be used to transmit data in parallel to achieve higher throughput and/or redundantly to achieve greater reliability.
A multi-antenna wireless device is equipped with multiple antennas that may be used for data transmission and/or reception. Each antenna may be associated with (1) transmit circuitry used to process a baseband output signal to generate a radio frequency (RF) output signal suitable for transmission via a wireless channel and (2) receive circuitry used to process an RF input signal to obtain a baseband input signal. The multi-antenna wireless device also typically has digital circuitry used to digitally process data for transmission and reception.
Due to the additional complexity associated with MIMO operation, the multi-antenna wireless device may be much more complex than a single-antenna wireless device in a system that can support both single-antenna and multi-antenna wireless devices. The multi-antenna wireless device may thus consume much more power than the single-antenna wireless device. The higher power consumption is undesirable, especially if the multi-antenna wireless device is a portable unit (e.g., a handset) that is powered by an internal battery. The higher power consumption depletes the available battery resources more quickly, which then shortens both the standby time between battery recharges and the on time for active communication.
There is therefore a need in the art for a multi-antenna wireless device that is power efficient.

Power-efficient multi-antenna wireless device