A flip chip is soldered to an array of flexible pillars of compliant dielectric material on a circuit board. Each pillar has an electrically conductive core electrically coupled to the circuit board. The pillars absorb movement due to differences in the coefficient of thermal expansion of the chip and board, and hence reduce the possibility of fatigue failure of the solder joint. The pillars are manufactured by forming a layer of compliant dielectric material on the circuit board, forming blind holes in the layer, filling the holes with electrically conductive material overlapping the edges of the holes, and then laser ablating to remove the compliant dielectric material except where protected by the electrically conductive material.

This invention relates to the direct attachment of flip chips to printed circuit boards (PCBs).
One problem with direct attachment of a flip chip to a PCB is the difference in coefficient of thermal expansion between the chip (made of silicon) and the PCB (made of organic material such as reinforced epoxy resin). This produces stresses on the solder joint, which can result in failure of the joint through fatigue.
One known way of alleviating this problem is to fill the gap between the chip and the PCB with epoxy material. The material is applied in liquid form and drawn into the gap by capillary action. The material takes stresses away from the solder, and has been found to increase the fatigue life of the joint by a factor of ten. However, a problem with this is that the larger the chip the longer the time needed to draw the epoxy material into the gap. Possibly several passes are required to fill the gap completely, which causes problems with manufacturing. Another problem is that, after the gap is filled, removal and replacement of a defective chip is very difficult.
The object of the present invention is to provide an alternative technique for flip chip attachment which avoids these problems.


A method of manufacturing a dental prosthesis to be implanted in a jaw of a patient, including the production of a radiological guide whose image, when the guide is placed in position on the jaw of the patient, can be processed for introducing virtual implants and guide cylinders in a surgically appropriate position; drilling holes into the guide on the basis of information obtained from the processing and placing real guide cylinders into the holes in order to form a surgical guide; placing the surgical guide on a pattern of the patient's jaw and drilling holes into the pattern through the guide cylinders; placing implant analogues into the holes drilled into the pattern; and producing the dental prosthesis on the pattern. Also, an appliance for carrying out the manufacturing method.

The present invention relates to a method of manufacturing a dental prosthesis to be implanted in a jaw of a patient and an appliance used for such an implantation.
Implants are at the moment positioned in four ways:
1. Freehand with a wide cut in the gum and detachment of the latter. Fitting takes place in an archaic manner without any reference or guiding mark with respect to the future prosthesis. Although this technique is the worst and gives results that are often aesthetically, functionally and hygienically disastrous, it is the most widely used. It is also the one that causes the most accidents (rupture of the mandibular nerve, piercing of the sinus, rupture of the cortices, etc).
2. Freehand with a wide cut in the gum and a detachment of the latter, the positioning takes place in a more or less precise manner since the dental laboratory has produced a surgical guide that more or less prefigures the future prosthesis. This technique is the second most widely used but the drawback is that the surgical guide is often unusable because of the cutting of the gum, which prevents the fitting thereof. With this technique there are also often poor results at an aesthetic, functional or hygienic level and accidents as aforementioned are numerous.
3. With the hand guided by drilling guides produced from a computerised plan. This technique makes it possible to place drilling cylinders in these guides at precise points according to the bone or according to the bone and the future prosthesis. Two distinct technologies apply this technique:                Guides are produced from steriolithographic models, that is to say on the basis of images issuing from dental scanning. Artefacts often interfere with the production of these guides not always making it possible to use them through lack of precision.        Guides are produced from an impression and a radiological guide that is produced on the basis of this impression in silicone (rather than on the basis of an image issuing from dental scanning). This radiological guide is then converted into a surgical guide by the insertion of guide cylinders for the drilling and the positioning of implants in the jaw.
These techniques make it possible to reduce damage to the patient and in particular the last technique improves the prosthetic result.
4. Freehand guided by a navigation system (GPS). This technique makes it possible to place an implant more or less precisely. However, it does not prevent all damage to the patient since the drilling is still manual and skidding remains possible. In addition it does not take account of the future prosthesis. This technique is expensive and is the least used.
All these techniques together have the drawback of having to produce the final prosthesis after taking an impression of the jaw where the implants were placed previously, which is carried out several weeks after the positioning of the implants, which is complex and requires many post-operative interventions, which are difficult for the patient.

Method for manufacturing a dental prosthesis and an appliance for implantation thereof


A method for operating a hydraulic brake system of a motor vehicle includes enabling a parking brake function by actuating a pressure generator and an actuator such that the pressure generator and the actuator together generate a total clamping force at a wheel brake, and actuating the pressure generator based on a movement of an actuator element and/or a brake piston, the movement generated by the actuator. The brake system includes the wheel brake having the brake piston, a brake pedal device, the pressure generator configured to actuate the wheel brake, the actuator assigned to the wheel brake and having the actuator element configured to actuate the wheel brake. A force that displaces the brake piston in order to actuate the wheel brake is generated by the pressure generator and/or the actuator.

The disclosure relates to a method for operating a hydraulic brake system of a motor vehicle, wherein the brake system comprises at least one wheel brake, a brake pedal device and at least one pressure generator for hydraulically actuating the wheel brake, and also an electromechanical actuator which is allocated to the wheel brake, said actuator having a movable actuator element, in particular a spindle nut, for actuating the wheel brake, wherein a force for displacing a brake piston of the wheel brake so as to actuate said wheel brake can be generated in each case by means of the pressure generator and actuator, and wherein in order to enable a parking brake function the pressure generator and the actuator are actuated in such a manner that said pressure generator and actuator generate a total clamping force or total braking force on the wheel brake.
Furthermore, the disclosure relates to a device for operating a brake system of this type and also to a corresponding brake system.
Methods, devices and brake systems of the type mentioned in the introduction are known from the prior art. Brake systems of motor vehicles, which brake systems can be operated by the driver of a motor vehicle by means of a brake pedal device, function in general in a hydraulic manner and for this purpose comprise one or multiple brake circuits which are connected to the brake pedal device in a hydraulic manner. If the driver actuates a brake pedal of the brake pedal device, a hydraulic pressure is thus generated in the brake system or the respective brake circuit, said pressure acting on one or multiple wheel brakes in order to displace a brake piston of the respective wheel brake with the result that a clamping force or brake application force is generated by means of which a brake disk is clamped between brake pads of the wheel brake. An adhesive friction is generated by means of the clamping procedure, said friction acting in a braking manner on the brake disk and thereby on a wheel of the motor vehicle, said wheel being connected in a non-rotatable manner to the brake disk. Usually, one or multiple valves which can be actuated are interconnected between the wheel brake and the brake pedal device, which in addition to the brake pedal generally also comprises a master brake cylinder and where appropriate a brake booster, said valves distributing the generated hydraulic pressure to multiple wheel brakes.
In order to fulfill a parking brake function, in which the wheel brake or the wheel brakes permanently maintain a clamping force without it being necessary to provide further energy, it is known to integrate in the brake circuit a pressure generator which can be actuated, said pressure generator being designed to generate a hydraulic pressure in the brake circuit in an automated manner on demand. If the desire to enable a parking brake function is ascertained, the pressure generator is actuated in order to increase the hydraulic pressure with the result that a corresponding braking force is produced at the respective wheel brake. The valves of the brake circuit are subsequently closed in such a manner that the pressure can no longer escape from the wheel brake and as a consequence the braking force is maintained.
It is also known to allocate an electromechanical actuator to the respective wheel brake, said actuator likewise acting on the brake piston in order to produce the clamping force or braking force in an automated manner on demand. In general, an actuator of this type comprises an electric motor whose torque and/or rotational movement are/is transferred by means of a transmission, in particular a spindle system, to the brake piston. It is also possible to maintain the clamping force by means of a self-locking embodiment of the transmission without having to maintain a further energy supply of the electric motor.
Brake systems have also become known in which in order to enable the parking brake function both the actuator and the pressure generator are actuated with the result that the brake piston is moved or influenced by means of superimposed driving forces. However, it is possible for behavior which is unusual to the driver to occur at the brake pedal as a result of this superimposition. If the brake piston is displaced by means of the actuator with the result that the volume for the hydraulic medium in the wheel brake increases, the pressure in the hydraulic system reduces, which leads to the brake pedal moving towards the floor. If the hydraulic pressure subsequently increases, the brake pedal is thus moved backwards away from the floor, as a result of which a forward movement and backward movement occurs that is unusual for the driver.

Method and device for operating a hydraulic brake system, brake system


A method of forming interconnects for submicron integrated circuits that allows use of titanium-tungsten as the interconnect material. The inherent instability of titanium-tungsten to oxidation is addressed by a nitridation process that includes exposing the interconnect to an ambient containing nitrogen (NH.sub.3) at an elevated temperature. Typically, the process is a rapid thermal anneal. A local interconnect may be formed, whereafter an insulating layer can be deposited at a high temperature without causing oxidation within the local interconnect that would adversely affect the resistivity of the material.

Fundamental to the fabrication of integrated circuits is the formation of metallization layers to establish electrical communication within the circuit, as well as to external circuitry. A "chip level" interconnect is a metallization layer for electrically connecting device electrodes, e.g. source, drain, gate, base, emitter or collector. A "packaging" interconnect is a metallization layer to provide electrical contact between a chip level interconnect and an input/output lead.
On a large scale, aluminum metallization is typically used as the interconnect layer at both the chip and packaging levels. Aluminum is easily vacuum-deposited and has a high conductivity. Aluminum alloys may also be chosen for different performance-related reasons. Particularly in the area of packaging interconnects, a well-developed technology exists for the deposition and patterning of these metallization layers.
As circuit density increases, the contact area of a device electrode becomes one of the limiting factors for circuit density and performance. A local interconnect is a chip level interconnect that increases circuit density by providing contact between local polysilicon gate and source/drain regions, as well as contact between intra-device source/drain regions, without requiring the formation of contact holes. By eliminating the need for contact holes, the local interconnects reduce parasitic capacitance and enhance circuit performance.
While local interconnects provide improvements in semiconductor integrated circuit chip technology, process complexities and control difficulties have limited the use of local interconnects. U.S. Pat. No. 4,957,590 to Douglas describes alternative methods of forming local interconnects. One described method, credited as a Hewlett-Packard Corporation invention, is to use a silicide as the local interconnect material. A layer of titanium is deposited over a substrate and, prior to the direct reaction of the titanium with any underlying silicon and polysilicon to form titanium silicide, a thin layer of amorphous silicon is patterned on top of the titanium metal to define an interconnect extending over a silicon dioxide region separating two electrode regions to be interconnected. The patterned silicon layer forms a silicide across the silicon dioxide region upon reacting of the titanium with the silicon. One potential difficulty with this method is that it requires deposition and patterning of an additional layer of silicon to define the local interconnections. A second difficulty is that the titanium silicide is a poor diffusion barrier to conventional semiconductor dopants, such as phosphorous and arsenic. Thus, where the silicide is used to connect n-type regions to p-type regions, any subsequent processing must be performed at relatively low temperatures to minimize the counterdoping that potentially could take place through the silicide interconnect.
The Douglas patent teaches that titanium nitride is a preferred material for forming local interconnects, but that using standard fluorine-based chemistries in plasma etching the titanium nitride provides unacceptable selectivity for achieving submicron geometries. The Douglas patent notes that carbon tetrafluoride (CF.sub.4) etches titanium nitride at twice the rate of titanium silicide, but also etches silicon oxides and photoresists at a rate faster than the titanium nitride. To increase selectivity, Douglas teaches use of a chlorine-bearing agent as a plasma etchant. However, titanium nitride can be difficult to deposit, so that submicron geometries are still difficult to achieve.
Titanium-tungsten is another possible material for fabrication of local interconnects. However, titanium-tungsten is unstable with respect to oxidation. Formation of a local interconnect is followed by fabrication steps which inevitably require high temperatures, such as formation of phosphosilicate glass layers at a temperature of 800.degree. C. The inherent instability of titanium-tungsten with respect to oxidation would result in reactions occurring in the titanium-tungsten film to form a titanium oxide and a tungsten oxide. Because oxidation affects the resistivity of the film, the performance of the integrated circuit would be adversely affected.
It is an object of the present invention to provide a method of forming interconnects, particularly interconnects that contact exposed regions of a semiconductor wafer, wherein the formed interconnects are stable with respect to oxidation and have a low, reproducible sheet resistance and wherein the method is not critically dependent upon process parameters and requires no new tools or technologies. It is a further object to provide a method to form such interconnects that exhibit increased diffusion-inhibiting characteristics.

Nitridation of titanium-tungsten interconnects


A ski for sliding on snow, having a lower sliding surface joined at two lateral surfaces along two lower edges, the lateral surfaces being joined at an upper surface. The ski is constructed such that the central zone of the upper surface of the ski, adapted to receive a binding that adapts to the boot of the user, includes a raised median rib, bordered by two lowered lateral portions; at least one of the front or rear zones of the upper surface of the ski includes a lower median portion, bordered by two raised lateral ribs.

1. Field of the Invention
The present invention is related to skis used for winter sports, and adapted to slide on snow and ice.
2. Discussion of Background and Relevant Information
Conventional skis normally comprise a lower sliding surface that is attached to two lateral surfaces along two lower edges equipped with metallic running edges, the lateral surfaces being joined at an upper surface. The width of the skis is relatively small with respect to their length, their front end being curved upwardly to form a spatula. The thickness of the ski is generally more substantial in the central portion than in the front and rear portions of the ski. In the conventional shapes that are used most often, the width of the lower surface of the ski is smaller in the central portion than in the rear and front portions, the width being maximum in the front portion of the ski, that is, in the vicinity of the spatula.
In known ski structures, the upper surface of the ski is generally an adjusted surface, that is, defined by the longitudinal displacement of a straight transverse line parallel to the lower surface of the ski. In other words, the transverse section of the ski is generally a rectangle or a trapezoid, the longer opposite sides of the rectangle or the trapezoid being formed by the lower surface and the upper surface of the ski, the smaller opposite sides of the rectangle or the trapezoid being formed by the lateral surface of the ski.
The greater thickness in the central portion of the ski confers this central portion with increased rigidity. This central zone is also adapted to receive the bindings that adapt to the user's boot. Conversely, the front and rear zones of the ski, that have lesser thickness, are more flexible, and apt to be elastically deformed when the ski is used. Should one wish to manufacture skis with good flexibility in the rear and front zones, one would have to necessarily provide that such front and rear zones have less thickness.
A first problem that arises in traditional ski structures is that the central zone of the ski, that has relatively greater thickness in order to confer it with greater rigidity, brings about a fairly substantial distancing of the bindings with respect to the lower edges of the ski. The lower edges are those elements that are adapted to bite into the ice while making a turn. The efficiency of the lower edges equipped with running edges is all the better when the connection between the foot of the user and the running edge is more direct. The distancing between the running edge and the binding tends to deteriorate the efficiency of the running edges.
A second problem that arises in known ski structures is that the substantial reduction of the thickness of the front and rear zones of the ski tends to substantially reduce the mass of these front and rear zones, and thus substantially reduces the inertia of the ski, both around a central vertical axis, and around a central horizontal axis, that are perpendicular to the longitudinal direction of the ski. The moment of inertia around the vertical axis, or the rotational axis of the ski, influences the behavior of the ski in rotation, by determining the resistance that the ski generates to a variation in the direction of the movement. A ski with a relatively small moment of inertia, for example, a short ski that is light at its ends, is easier to turn than a ski with a relatively large moment of inertia. But this reduction of the movement of inertia decreases the stability of the ski. Conversely, a ski with a relatively large moment of inertia is especially stable directionally during quick descent, because the stresses exercised laterally on the ski by the inequalities of the slope are better absorbed due to the greater moment of inertia. On the other hand, the moment of inertia around its central horizontal axis, perpendicular to the longitudinal direction of the ski influences the vibratory behavior of the ski. It is known that vibrations can be harmful and lead to a loss of adherence to the ground by the lower edges of the ski, and consequently, to a directional instability.


A marine hatch assembly includes a rectangular ring shaped frame, a hatch cover hinged to the frame and a pivotal adjustment mechanism or adjuster for maintaining the hatch in a predetermined open position. The adjusting mechanism or adjuster includes a pair of telescoping elements one of which has a flexible joint therein. This flexible joint is prevented from flexing by the other of the telescoping elements until that element is withdrawn to a point beyond the flexible joint i.e., when the hatch cover is rotated beyond a predetermined angle. The adjusting mechanism also includes a clamp for maintaining the telescoping elements in a fixed relationship with respect to one another in order to maintain the hatch in a predetermined open position.

Hatch assemblies having pivotal adjustment mechanisms are well known and commonly used in marine vessels or the like to hold up hatch covers and deck hatches. Typically, they consist of various cross sections, often round that slide one inside the other. Their lengths are determined by the varying distance between the attachment points when the hatch is open or closed. One example of a hatch cover is disclosed in the U.S. Pat. No. 3,976,024 of Fellery. As disclosed therein, the stay mechanism includes an espagnolette bolt and means which permit a hatch cover to be rotated through an angle of 180.degree..
When a hatch needs to open more than 90.degree. but less than about 130.degree. most of the available adjusters may be used without problem. However, when a hatch cover has to be rotated 180.degree. an added problem is introduced. In such instances, the lower end of the adjuster will strike the frame unless like the Fellery disclosure, it has an appropriate bend in the adjuster. However, including a bend in the one arm of the adjuster weakens the adjuster and causes the arm to protrude into the hatch opening several inches. For many applications, this intrusion into a cabin is unacceptable since it impacts on head room i.e. it provides an obstacle which may be struck by an individuals head. Furthermore, it prevents a screen from being fitted within a hatch cavity.
Notwithstanding the above, it is important that a hatch cover is sufficiently durable that it reduces the likelihood of an open hatch being inadvertently slammed shut as for example on an owner's or perhaps a child's fingers.
It is now believed that there may be a relatively significant market for an improved hatch assembly which includes an adjustment mechanism in accordance with the present invention.
It is believed that a market exists for a hatch assembly which allows a hatch cover to be open to an angle of 180.degree. without a bent arm and which does not protrude into the cabin or prevent the installation of a screen within the hatch cavity when the hatch is in a closed position.
It is also presently believed that a hatch assembly including an adjustment mechanism in accordance with the present invention provides the aforementioned advantages. In addition, such assemblies can be manufactured at a competitive cost, are durable, unlikely to be inadvertently slammed shut and can be readily installed and/or removed in the same manner as the presently available commercial hatch assemblies. Such assemblies may also be manufactured with a pleasing appearance and are applicable to vessels of various sizes, and are suitable for plastic or metal hatches.

Hatch assembly with a pivotal adjustment mechanism


A method and apparatus control blanking of a display (106) in a communication device (100) such as a battery powered radiotelephone. The communication device (100) includes a clock operated blanking timer 317. When the blanking timer 317 elapses, the communication device (100) blanks the display (106) a predetermined time after a key press of a keypad (108). A switch (310) detects when the communication device (100) is in use. In response to this detection, the communication device (100) maintains supply of operating power to the display (106), overriding the blanking timer 317. When a user is holding the communication device (100) adjacent to the user's head, an earpiece sensor (312) provides an indication of this condition. In response to the indication, the display (106) is immediately blanked to conserve operating power in the battery (124).

Many communication devices are mobile and operate on battery power. Such communication devices generally include a radio receiver and/or radio transmitter for radio communication, a user interface for controlling the communication device, and a rechargeable battery for powering the communication device.
An example of such a communication device is a radiotelephone. A radiotelephone includes a receiver and transmitter and operates in a radiotelephone system. The radiotelephone system includes one or more base stations coupled to the public switched telephone network (PSTN) and configured for completing calls between the radiotelephone and the PSTN. The radiotelephone, or mobile station, is portable and therefore free to move about within a fixed geographic area served by the base station. To improve mobility and user convenience, many radiotelephones are powered by rechargeable batteries. Other examples of such communication devices are paging receivers and land mobile radios.
One design goal for communication devices including radiotelephones is minimization of power consumption from the battery. One reason for this goal is to permit the use of physically smaller, lighter batteries. Such smaller and lighter batteries permit the communication device itself to be physically smaller and lighter, and thereby more convenient for the user. A second reason for minimizing power consumption in a communication device is to extend the operating time of the communication device, which also enhances convenience for the user.
Displays in communication devices are one source of substantial power consumption. Such displays include multi-segment light emitting diode (LED) displays and liquid crystal (LCD) displays. LCD and other displays often include backlighting using one or more LEDs to improve night time visibility of the display. In addition, the display may include individual elements such as LEDs which are selectively energized to provide a user indication. Still further, many communication devices having keypads provide one or more LEDs for backlighting the keypad for visibility in the dark.
One known method of reducing power consumption in a communication device is blanking the display a predetermined time after operation of the keypad. The display is blanked by removing power from portions of the display. Such portions include specific LED segments or LEDs used for backlighting a LCD display. Only one or a few isolated illuminated elements, such as LED indicators, remain energized to provide a visual indication that the communication device is active. By blanking the display, power consumption can be substantially reduced.
The rationale for blanking the display is that there are times when a user no longer needs to see the display. For example, once a user has initiated a telephone call, the user no longer needs to see the display. Also, when the user is not actively using the telephone and the user is awaiting an incoming call, the user does not need to see the display. The display is necessary when entering numbers using the keypad, for verifying accurate entry. The display is also necessary when operating other features of the user interface of the radiotelephone, such as recalling telephone numbers stored in the radiotelephone's memory. Once the call is connected and the user holds the radiotelephone against the user's head during the conversation, the display is not needed by the user and blanking is appropriate. The radiotelephone blanks the display after a preset time delay (such as 8 seconds) following the last keypress or following the opening of a keypad cover. This rationale applies to other types of communication devices as well.
In some instances, blanking can hinder user convenience. This can occur if the user is still holding the communication device in his hand and still wants to see the information on the display. Blanking at such a time is inconvenient for the user. According to current designs, in order to get the information on the display to reappear, the user must press a key on the keypad or close and open the keypad cover. Either action may produce undesired responses, such as changing the state of the communication device or ending an active call. There are other instances when display blanking can hinder user convenience. One of these is while trying to operate the communication device while driving, at times when the user's constant concentration on driving is required for more than 8 seconds. Another example is when using the communication device in the dark, when having keypad backlighting turned off makes it difficult to find keys including a key which will illuminate the display.
Accordingly, there is a need in the art for a method and apparatus for controlling the blanking in a communication device.

Communication device and display blanking control method therefor


An electronic device includes an interlevel dielectric layer formed over a substrate and has a first set of openings and a second set of openings formed through the interlevel dielectric layer. The substrate includes conductive areas. A conductive contact structure is formed in the first set of openings in the interlevel dielectric layer to make electrical contact with the conductive areas of the substrate. A functional component is formed in the second set of openings in the interlevel dielectric layer and occupies a same level as the conductive contact structure.

1. Technical Field
The present invention relates to semiconductor structures and fabrication methods, and in particular to functional structures formed with metal interconnects on a same layer and methods for fabricating the same.
2. Description of the Related Art
Typical conventional integration schemes for forming electrical contacts for transistors in a semiconductor chip include depositing a nitride stop layer on top of finished front end of line (FEOL) devices (e.g., transistors). An oxide layer is deposited and planarized. Contact patterns are formed by lithography on a regular resist, resist on antireflection coating (ARC) mask stacks or multiple layer mask stacks, such as a tri-layer mask stack, which need to be removed in later steps. Plasma etch processes are used to transfer the contact patterns into the oxide layer by opening the ARC layer, etching through the oxide layer, which typically has a different thickness on the top of gate and source/drain areas of the transistors, and then stopping on the nitride stopping layer. The nitride stopping layer is etched through—stopping on silicide layers on top of the gate and source/drain areas.
Current integration schemes and process flows for contact formation etch contact holes and stop on top of the gates and on the top of silicides in the source/drain area. These structures include only conductive materials for forming interconnects between adjacent layers.

Methods for fabrication interconnect structures with functional components and electrical conductive contact structures on a same level


The present invention is directed to interleukin-22 polypeptides and nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptide molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention and to methods for producing the polypeptides of the present invention.

The pancreas is a large gland located behind the stomach and close to the duodenum. It secretes digestive enzymes that enter the small intestine via a duct. These enzymes facilitate the digestion of proteins, fats and carbohydrates. In addition to the digestive enzymes the pancreas also releases insulin and glucagon, which play an important role in sugar metabolism.
Pancreatitis is a disease in which the pancreas becomes inflamed. Damage to the pancreas occurs when digestive enzymes are activated and begin attacking the gland. In severe cases, there many be bleeding into the gland, tissue damage, infection and cyst formation. There are two forms of pancreatitis. An acute form which occurs suddenly and may be life threatening. A chronic form of pancreatitis may arise if the patient persists in drinking alcohol, which results in the reduction of pancreatic function and severe pain and weight loss. There are approximately 50,000 to 80,000 cases of acute pancreatitis in the United States each year. It is more common in men than in women.
Currently, diagnosis of pancreatitis is difficult. Usually pancreatic function tests help the physician determine if there are enough pancreatic enzymes being made. CAT scan can determine if there are abnormalities in the gland itself, such as gallstones, which are frequently associated with this disorder. As chronic pancreatitis is a leading risk factor for pancreatic cancer, it should be treated as soon as the diagnosis is made.
The pancreas is comprised of about 80% acinar cells, 1%–2% islet cells and 10%–15% of cuboidal ductal cells. Acinar cell carcinoma accounts for 1%–2% of pancreatic carcinoma, with an additional 10%–15% of pancreatic carcinoma comprised of acinar cells and other cell types [Nomura et al., Ultra. Path. (1992) 16:317–329]. All of the causes of acute pancreatitis affect the acinar cells in a way that results in the activation and retention of the digestive enzymes, which injure the acinar cell and cause the release of cytokines. The cytokines attract inflammatory cells, especially neutrophils, leading to further secretion of cytokines. It is proposed that the released inflammatory molecules induce pancreatic edema, and local necrosis. Certain studies have suggested that cytokine inhibtors may improve the course of pancreatitis in specific clinical settings.
Interleukin-22 (IL-22) is a newly identified cytokine produced by activated T cells and is related to interleukin-10 (IL-10). IL-22 signals through a receptor complex comprised of CRF2-4, also known as IL-10Rβ, and a new member of the class II cytokine receptor family, interleukin-22 receptor (IL-22R) [Xie et al., J. Biol. Chem. (2000) 275, 31335–31339]. Of the members of this receptor complex, IL-10Rβ is expressed in several tissues while the expression of IL-22R is fairly restricted, with high expression in the pancreas, suggesting that IL-22R is controlling the site of action of IL-22. As an example, murine IL-22 induces changes in gene expression in pancreatic acinar cells of several genes including pancreatitis associated protein (PAP1), a gene overexpressed in acute pancreatitis [Iovanna et al, J. Biol. Chem. (1991) 266, 24664–24669]. IL-22 signaling through a receptor complex that is highly expressed in pancreas, suggests that IL-22 may modulate an immune/inflammatory response in the pancreas, and may be involved in diseases of the pancreas including pancreatitis.

Interleukin-22 polypeptides, nucleic acids encoding the same and methods for the treatment of pancreatic disorders


A coated smooth surface of a substrate repels liquids and viscoelastic materials and can have anti-staining and anti-biofouling properties. The smooth surface can be coated by applying a chemical layer on the surface and a lubricant. Such coated surfaces are useful for use in toilets, urinals, or other devices for the processing of liquids and viscoelastic materials such as solid or semi-solid metabolic waste of human digestive system. Such coated surfaces can also be applied to windows for buildings or vehicles such as automobiles or camera lenses to repel liquids (e.g., rain), ice, frost, insect residues, and birds' feces.

Water shortage is a serious global problem. In areas, such as Africa and India, water is in very high demand for living and agriculture. Numerous researchers have been focused on desalination of brine to generate more water, and on advancing piping system in agriculture to save water. However, much less attention has been focused on water usage for flushing toilets. Specifically, two-thirds of people in the world have access to flushing toilet. See World Health Organization and UNICEF Joint Monitoring Programme. Progress on Drinking Water and Sanitation, 2015 Update and MDG Assessment. Each of them flush a toilet at a frequency 5 times per day on average (around 8 gallon of water), and 30 billion gallon of water is flushed away globally per day. Certain regions such as Brazil make use of rainwater to flush toilets. However, rainwater could cause a number of health problems, especially bacterial infection.
Articles have been developed with modified surfaces for fluid and solid repellency. See, e.g., U.S. Patent Publication No. 2014-0342954; U.S. Pat. No. 4,844,986 and Wang et al. Covalently Attached Liquids: Instant Omniphobic Surfaces with Unprecedented Repellency. Angewandte Chemie International Edition 55, 244-248 (2016).
However, engineered surfaces that are non-sticky to both semi-solid (e.g. feces, wet molding clay, mustard, etc.) and bacteria are not well-studied and developed because these visco-elastic semi-solids and bacteria are sticky to most surfaces. Existing slippery surfaces, including superhydrophobic surfaces and slippery liquid-infused porous surfaces (SLIPS), are either sticky to bacteria (i.e., superhydrophobic surfaces), or not specifically designed for sticky issues of viscoelastic solids (i.e., superhydrophobic surfaces and slippery liquid-infused porous surfaces). See Wong, T.-S. et al. Bioinspired self-repairing slippery surfaces with pressure-stable omniphobicity, Nature 477, 443-447, 2011.
Superhydrophobic surfaces are slippery to water, or even oils using special surface structure designs. However, these surfaces typically lose its repellency under the exposure of biological liquids, such as blood and bacteria fluids. For bacterial fluids, biofilm can form onto the surface structures and destroy the superhydrophobic property. In addition, superhydrophobic surfaces and slippery liquid-infused porous surfaces are not known to repel viscoelastic semi-solids, such as feces or mud.
Accordingly, there is a need for new surface technology that provides a simple solution to repel both liquids and viscoelastic solids for extreme water-saving applications or easy-to-clean medical devices.

Liquids and viscoelastic material repellent and anti-biofouling coatings


Compounds of formula (I″)

1. Field of the Invention
The present invention relates to a particular compound. Moreover, it relates to a production method of the compound, and a glucagon-like peptide-1 (GLP-1) secretion promoting agent, a pharmaceutical composition, a food composition and a cosmetic composition, each containing the compound.
2. Discussion of the Background
In recent years, many studies have been made around capsaicin.
JP-B-3506466 discloses capsaicin glycoside and the like. However, the capsaicin glycoside can reduce the pungent taste of capsaicin but cannot always eliminate the pungent taste completely when it is blended at a high concentration.
In addition, JP-A-2007-326825 discloses a composition for controlling harmful organisms, which contains (a) 4-phenoxyphenyl (RS)-2-(2-pyridyloxy)propyl=ethyl, and (b) capsaicinoid or capsinoid, or a glycoside thereof. However, the specific saccharide residue is not shown and the use thereof is extremely limited.
On the other hand, JP-B-4163631 discloses a fermentation composition of nonpungent chili pepper (Capsicum annuum) and use thereof. However, since such nonpungent chili peppers are generally in the form of oily liquid, the method for improving the purity is limited to extraction, column purification and the like.
Glucagon-like peptide-1 (GLP-1) is a peptide made from the same gene proglucagon sequence as that of glucagon. GLP-1 is one of the incretin factors secreted from the small intestine, and has actions of enhancement of glucose concentration-dependent insulin secretion, Langerhans' islets β cell proliferation, suppression of glucagon secretion, suppression of stomach excretory function, regulation of central appetite and the like. A substance having a GLP-1 secretion promoting action can be utilized as a prophylactic or therapeutic agent for diabetes (particularly type II diabetes) or an anorexigenic agent.

Abstract: Compounds of formula (I″)

Abstract: wherein:                R11, R12, R13, R14 and R15 are hydrogen, hydroxyl, C1-6 alkyl, C1-6 alkoxy, C1-6 alkyl-carbonyloxy, or a G-O— group, and at least one of R11, R12, R13, R14 and R15 is a G-O— group, wherein G is a saccharide residue,        X1 is a single bond, or a methylene group, an ethylene group, a trimethylene group, a vinylene group or —CH═CH—CH2—,        X2 is —CO—O— or —O—CO—,        p and q are integer ofs 0 to 7, and p+q=0 to 8,        Y1 is methylene, ethylene or an alkenylene group having a carbon number of 2 to 15 and 1 to 3 double bonds, and        R16 and R17 are hydrogen, methyl or ethyl, or R16 and R17 form a C3-6 cycloalkyl group, are useful as GLP-1 secretion promoting agents.


Rock detritus created by a drag bit cutter shearing subterranean formation material may flow under a cutter and attach itself to a side surface of a cutter barrel by differential pressure-induced sticking, and dilate. This attached material, confined by hydrostatic pressure, can create and strengthen a barrier between the cutter and virgin rock being cut. The detritus barrier absorbs bit weight and reduces cutter efficiency by impairing contact of the cutter with the virgin rock formation. Increasing friction between the rock detritus and the side surface of the cutter barrel inhibits detritus flow, reduces build up, and allows hydrostatic pressure to contribute to, rather than inhibit, the cutting process. Similar beneficial results may be obtained when hydrostatic pressure drilling fluid is permitted to communicate through holes in the side surface of the cutter, or through an otherwise permeable side surface alleviating detritus sticking due to differential pressure effects.

Rotary drag bits have been used for subterranean drilling for many decades, and various sizes, shapes, and patterns of natural and synthetic diamonds have been used on drag bit crowns as cutting elements, or cutters. When drilling certain subterranean formations, a properly designed drag bit can provide an improved rate-of-penetration (ROP) over a tri-cone bit.
Rotary drag bit performance has been improved significantly with the introduction of polycrystalline diamond compact (PDC) cutting elements, usually configured with a substantially planar PDC table formed onto a cemented tungsten carbide substrate under high-temperature and high-pressure conditions. PDC tables are formed into various shapes, including circular, semicircular, and tombstone, which are the most commonly used configurations. Additionally, the PDC tables can be formed so that a peripheral edge, or edge portion, of the table is coextensive with the sidewall of the supporting tungsten carbide substrate, or the PDC table may overhang the substrate sidewall slightly, forming a "lip" at the trailing edge of the table. In some instances, such as when a portion of the PDC table adjacent the cutting face has been leached of the metal catalyst used to stimulate diamond-to-diamond bonding during formation of the PDC table, a lip may form during drilling due to more rapid wear of the unleached portion of the PDC table to the rear of the leached portion. PDC cutters have provided drill bit designers with a wide variety of potential cutter deployments and orientations, crown configurations, nozzle placements and other design alternatives not possible with natural diamond or smaller synthetic diamond cutters.
While rotary drag bits provide better ROP than tri-cone bits under many conditions, the performance of rotary drag bits can still be improved. Researchers in the industry have recognized that controlling buildup of recompacted rock cuttings, or detritus, on the cutting  face of a PDC cutter is a significant factor affecting cutting performance. Methods used to manage detritus buildup on PDC table cutting faces include mechanical, hydraulic and chemical means of attacking the recompacted detritus.
The aforementioned lip configuration on PDC cutting elements has been observed to improve cutting efficiency by reducing detritus buildup on the sidewall of the cutting element to the rear of the PDC table, but the operative mechanism for this observed phenomenon has not been understood. Moreover, configuring a PDC cutting element with, or to form, a protruding lip adds cost to cutting element fabrication and the increased cost of such cutting elements may not be perceived to be commensurate with the benefits obtained for many applications.
What is needed are straightforward, cost-effective improvements to rotary drag bit cutters to inhibit flow and buildup of detritus over the side surface of the cutter adjacent the formation being cut, to remove recompacted detritus from the side surface of the cutter earlier in the buildup cycle, or both.

Detritus flow management features for drag bit cutters and bits so equipped


Extending sections are positioned along X and Y directions by engagement sections, and positioned along Y direction of a vehicle by positioning sections using mounts of a rear bumper. This makes it possible to accurately indicate a forming position of a vehicular-part mounting hole, which is needed to mount a rear under spoiler, with respect to the rear bumper based on a scribed mark if the extending sections are positioned by using the engagement sections and the positioning sections. Therefore, a worker can form a vehicular-part mounting hole in an appropriate position by merely making a hole in the position of the scribed mark, without requiring a work of removing the rear bumper.

1. Field of the Invention
The present invention relates to a positioning jig for a vehicular-part mounting hole, and is suitable in forming a vehicular-part mounting hole for mounting vehicular exterior parts, such as a front under spoiler, a rear under spoiler (hereinafter, both simply and generally called "under spoiler"), and a rear spoiler, in the vehicle.
2. Description of the Related Art
Recently, for improving aerodynamic characteristics and design characteristics of a vehicle, an under spoiler is mounted on a front bumper or a rear bumper (hereinafter, simply and generally called "bumper"), and a rear spoiler is mounted on a trunk lid.
To mount a vehicular exterior part, such as an under spoiler or a rear spoiler, mounted on a mounting position such as a bumper or a trunk lid, a bolt is inserted into a mounting hole formed in the vehicular exterior part and a vehicular-part mounting hole formed in the mounting position through a clip nut or the like, and the leading end of the bolt is tightened with a screw nut, thereby mounting the vehicular exterior part on the mounting position (see, for example, Japanese Unexamined Utility Model Publication No. 6-49231, and Japanese Unexamined Utility Model Publication No. 2-136788).
If a vehicular-part mounting hole is provided in the bumper on which the under spoiler as the vehicular exterior part is mounted, at a position corresponding to the mounting hole of the under spoiler beforehand, the vehicular-part mounting hole may be externally visible when the under spoiler is not mounted on, and this results in a poor general appearance in design of the vehicle.
To overcome such a problem, conventionally, a scribed mark for forming is provided beforehand in a position in a bumper corresponding to the mounting hole of the under spoiler, and in the rear face of the bumper that is not externally visible. In actually mounting the under spoiler, the bumper is temporarily removed from a vehicle, forming is performed with a pushpin or the like based on the scribed mark on the rear face, and a vehicular-part mounting hole is formed by a drill or the like based on the hole made by the pushpin or the like.
Accordingly, in a work of mounting an under spoiler to a bumper, the bumper must be removed from a vehicle every time for a worker to check a scribed mark provided on the rear face of the bumper with his/her eyes. Therefore, the mounting work becomes complicated, making a work burden on the worker larger, and takes time.
In a work of mounting a rear spoiler as a vehicular exterior part on a trunk lid, as illustrated in FIG. 17, a paper pattern 101 provided with scribed marks 100 beforehand for drilling is positioned on the top face of a trunk lid 102, the trunk lid 102 is pierced with a pushpin or the like based on the scribed marks 100 positioned over the trunk lid 102, and a vehicular-part mounting hole is formed by a drill or the like.
The paper pattern 101 positioned to the trunk lid 102 is, however, formed in the approximately same size as the top face 103 of the trunk lid 102, and is therefore not easy to handle. Further, positioning all four corners of the paper pattern 101 to the four corners of the trunk lid 102 requires a skill, complicating the mounting work, and making a work burden on the worker larger. When the paper pattern 101 is not accurately positioned to the trunk lid 102, it is necessary to reposition all four corners of the paper pattern 101, and the mounting work takes time.
The present invention has been made in view of the above circumstances, and it is an object of the invention to provide a positioning jig for a vehicular-part mounting hole which can dramatically decrease a work burden when mounting a vehicular part, and considerably reduce the time for the mounting work.

Positioning jig for vehicular-part mounting hole


A method for holographic storage data recovery in a holographic storage system is presented. One exemplary method includes detecting a stored image at a detector such that the image is oversampled. A relationship is determined between a location of the detected image and a location of the source image. Pixel information associated with the source image may be obtained from the detected image based on a fractional delay filter. In one example, the image may be oversampled by magnifying the detected image at the detector and/or having a detector with pixel sizes and spacing less than the image pixel size. Further, coefficients of the fractional delay filter may be determined, at least in part, on magnification and shift information of the image based on known registration marks.

1. Field of the Invention
The invention relates generally to holographic data storage methods and systems, and more particularly to methods and systems for holographic data storage recovery by oversampling and fractional-delay filter interpolation.
2. Description of the Related Art
Holographic data storage systems store information or data based on the concept of a signal beam interfering with a reference beam at a holographic storage medium. The interference of the signal beam and the reference beam creates a holographic representation, i.e., a hologram, of data elements as a pattern of varying refractive index and/or absorption imprinted in a volume of a storage or recording medium such as a photopolymer or photorefractive crystal. A spatial light modulator (SLM), for example, can create the data-encoded signal beam. The interference pattern induces material alterations in the storage medium that generate the hologram. The formation of the hologram in the storage medium is a function of the relative amplitudes and polarization states of, and phase differences between, the signal beam and the reference beam. The hologram is also dependent on the wavelengths and angles at which the signal beam and the reference beam are projected into the storage medium. After a hologram is created in the storage medium, projecting the reference beam into the storage medium interacts and reconstructs the original data-encoded signal beam. The reconstructed signal beam may be detected by using a detector, such as CMOS photo-detector array or the like. The recovered data may then be decoded by the photo-detector array into the original encoded data.
In typical holographic data storage systems it is important to align the SLM, detector (i.e., a camera), and the data storage medium such that each pixel of the SLM is projected onto a single pixel of the detector. This alignment is desired for a single hologram or a group of holograms stored by various multiplexing methods including angle, shift, wavelength, correlation, spatial, aperture, phase code, and the like. Aligning the pixels of the SLM, stored holographic image, and detector is commonly referred to as "pixel matching." One objective of pixel matching is to obtain recovered images of data-containing holograms on the detector that have a low number of bits decoded in error in relation to the total bits of the data page, i.e., a low bit error rate (BER).
Performance of a holographic storage system, i.e., the quality of the modulated image, therefore depends at least in part on the alignment of various components such as the SLM with various devices, such as light sources, lenses, detectors, the storage medium, and the like. Generally the position and alignment of the SLM and other device components for reading and writing to the storage medium are mechanically set at the time of manufacturing the holographic storage system. Over time, however, the SLM, detector, or storage medium may become misaligned with various other components of the particular system. For example, temperature change, vibration, shock, and the like may result in slight movements or deformations of the detector, SLM, storage medium, or other optical components. The result may be translational, tilt, or rotational misalignment of the detector with the storage medium or the SLM. Further, in systems with removable storage media, such as a rotating disk or rectangular storage media, the media may be misaligned when inserted into one or more systems for read and/or write operations.
The desired alignment of components in a holographic storage system in the x and y direction is typically on the order of a few microns or less, and the rotation better than approximately 0.001 degree. In addition, the magnification of the system from drive to drive is desirably maintained to a high degree (typically better than 0.01%). The desired magnification generally results in the effective focal length of the lens between different drives to match on the order of tens of micron level. Such matching is difficult to achieve in low cost high volume processes. For example, these constraints on pixel matching may result in a holographic drive system generally having a higher cost, larger size, with increased error rates, and lower storage capacity than otherwise possible.
One strategy proposed for correcting errors arising from pixel misalignment due to improperly positioned system components and the like is to apply image-processing techniques to the recovered hologram image. An example of such a method is described in "Compensation for Pixel Misregistration in Volume Holographic Data Storage," by G. W. Burr and T. Weiss published in Optics Letters, Vol. 26, No. 8, Apr. 15, 2001, the entire contents of which is incorporated herein by reference. Another approach is to adjust or tilt the reference beam to realign the image onto the detector during a read out process. Such a method is described in U.S. Pat. No. 5,982,513 entitled "Method and System to Align Holographic Images," the entire content of which is incorporated herein by reference.
Deficiencies of these and other various methods include, for example, that system parameters are generally known or determined very precisely. Some image processing techniques are computationally intensive, may require repeated iterations to converge, suffer from error propagation, and may require channel transfer characteristics, i.e., point spread functions as it varies over the image. Additionally, there is no soft decision information as used by some error correction codes, for example, turbo codes and Low Density Parity Check (LDPC) codes.
New methods and devices are therefore needed for reliably adjusting for pixel misalignments and recovering holographic stored data with reduced error rates. In particular, methods and systems for processing detected holographic images with misalignments are needed.

Methods and systems for holographic data recovery


A gate array semiconductor integrated circuit device allowing less clock skews is disclosed. The device includes a clock signal driver formed in the part under a power supply interconnection for input-output buffer in a power supply pin region or a ground pin region. The clock signal driver is formed in the power supply pin region and so on which, conventionally, was not utilized, so that the clock signal driver can be large enough to provide a clock signal to each basic cell column. Therefore, the input-output buffer region is not unduly occupied by the clock signal driver, and the connecting pads do not become useless.

1. Field of the Invention
The invention relates generally to semiconductor integrated circuit devices having gate arrays and, more particularly, it relates to layouts of semiconductor integrated circuit devices having less clock skews and noises.
2. Description of the Background Art
With recent advancement of industrial use of a semiconductor integrated circuit device, the needs for each user have been diversified. The life cycle of a product has also been shortened. For that reason, there is an increasing need for designing a circuit free of defect in a short period of time for product development, and then manufacturing the product with less cost of development. Integration of a semiconductor integrated circuit device has also made remarkable advances. While the number of devices included in one chip has been greatly increased, it is becoming very difficult to make up a circuit utilizing them in accordance with the needs for each user. This conflicts with the need of the above-mentioned shorter period of time for development and the reduction in the cost of development.
In order to meet these needs, a semiconductor integrated circuit device including a gate array has been adopted. A gate array is an integrated circuit device including an array of basic cells arranged regularly on a semiconductor substrate. A basic cell is an assembly of devices required for constituting some function. A desired logic circuit may be obtained by combining basic cells into one unit. A gate array is an integrated circuit device which includes an arrangement of basic cells, in which an interconnection for connecting the basic cells has not been formed yet.
FIG. 1 is a typical diagram of a gate array semiconductor integrated circuit device. Referring to FIG. 1, the chip 26 of this semiconductor integrated circuit device includes basic cell columns 28 provided near the center of the surface, having basic cells arranged regularly, an interconnection region 29 provided around the basic cell columns 28, in which later an interconnection is formed for connecting the basic cells to the basic cells and to an input-output buffer which will be described later, an input-output buffer region 27 provided around the interconnection region 29, in which are formed transistors and the like required for forming a circuit for effecting input and output between the basic cell columns and an external circuit, and a pad forming region 35 around the input-output buffer region 27, in which are formed connecting pads 30 for connecting this semiconductor chip 26 with the external circuit, a power supply pad 61 to which an external power supply is connected, and a ground pad 62 to which a ground potential is connected.
Referring to FIGS. 2, 4, and 5, a basic cell 48 included in the basic cell column 28 includes, for example, p channel MOS (Metal-Oxide Semiconductor) transistors 82, 83 formed on an n-type silicon semiconductor substrate 71, and two n channel transistors 84, 85 formed on a P-type well 72 formed on the main surface of the silicon substrate 71.
Referring to FIG. 4, the p channel transistor 82 includes two p.sup.+ diffusion regions 73, 74 formed on the surface of the semiconductor substrate 71 with a prescribed spacing therebetween, a gate oxide film formed on the main surface of the semiconductor substrate 71 between the p.sup.+ diffusion regions 73, 74, and a polysilicon layer 79 formed on the gate oxide film.
The pMOS 83 includes a p.sup.+ diffusion layer 74, a p.sup.+ diffusion layer 75 formed, spaced apart from the p.sup.+ diffusion layer 74, a gate oxide film formed on the main surface of the semiconductor substrate 71 between the p.sup.+ diffusion layers 74, 75, and a polysilicon layer 80 formed on the gate oxide film.
Referring to FIG. 5, the nMOS 84 includes n.sup.+ diffusion layers 76, 77 formed on a p-type well 72 and spaced from each other between a gate oxide film formed on the surface of the p-type well 72 between the n.sup.+ diffusion layers 76, 77, and a polysilicon layer 79 formed on the gate oxide film.
The nMOS 85 includes an n.sup.+ diffusion layer 77, an n.sup.+ diffusion layer 78 formed on the p-type well 72, and spaced apart from the n.sup.+ diffusion layer 77, a gate oxide film formed on the surface of the p-type well 72 between the n.sup.+ diffusion layers 77, 78, and a polysilicon layer 80 formed on the gate oxide film.
A silicon oxide film 81 is formed on the pMOSs 82, 83, and the nMOSs 84, 85. The polysilicon layer 79 of the pMOS transistor 82 and the polysilicon layer 79 of the nMOS transistor 84 are common, forming a gate electrode of each transistor. Similarly, the polysilicon layer 80 of the pMOS transistor 83 and the polysilicon layer 80 of the nMOS transistor 85 are common, forming a gate electrode of each transistor.
The gate array semiconductor integrated circuit device includes a multiplicity of basic cells 48 (FIG. 2) as stated above, arranged regularly in the basic cell columns 28. A transistor group, as stated above, used as an input-output buffer is also formed in advance in the input-output buffer region 27. There is no interconnection for connecting each of these transistors. That is, it can be said that the gate array chip 26 shown in FIG. 1 is an incomplete semiconductor integrated circuit device.
FIG. 6 is a typical diagram showing the process in manufacturing a semiconductor integrated circuit device for each user with use of a gate array chip. Referring to FIG. 6, at first, a process called master design is conducted in which a layout of the gate array chip as shown in FIG. 1 is designed. As a result of the master design, a master mask 87 is obtained. A master slicer 86 is obtained by diffusing impurities on the semiconductor substrate with use of the master mask 87, and forming a polysilicon layer. A plurality of gate array chips as shown in FIG. 1 are formed on the master slicer 86. The manufactured master slicers 86 are stocked.
In manufacturing a new semiconductor integrated circuit device in accordance with a demand of a user, firstly, a circuit which agrees with the users need is designed. Basic circuits, for example, different kinds of logic gates and flipflops are designed in advance, using basic cells, and the result is registered in a library. In accordance with a circuit design for each user, an interconnection for implementing the circuit required by the user on the master slicer 86 is automatically calculated and determined by a computer. This is called an automatic layout interconnection. As a result of the automatic layout interconnection, personalized masks 88, 89 are formed in which an interconnection pattern to be added to the master slicer 86 is only recorded in order to implement an integrated circuit for each user. This process is called a "personalization". The personalized masks 88, 89 accordingly differ in accordance with the need of the customer.
An interconnection is formed on the master slicer 86 with metal and so on in accordance with the personalized masks 88, 89. The semiconductor integrated circuit on which an interconnection is formed is assembled with peripheral circuits, subjected to a final test, and forwarded to the user.
That is, a semiconductor integrated circuit device with use of a gate array may be obtained by stocking a master slicers having a specific arrangement of basic cells as a semi-finished product, and processing it in accordance with the need of each user. Accordingly, a gate array has advantages below.
Firstly, less cost is required for developing a final product. It takes less than in the case in which a specific design is conducted from the beginning for each user because a master slicer common to all the users is used. The time period required for developing a final product is shorter because it is required only to determine what kind of interconnection should be formed on the master slicer. It is possible to effect an automatic layout interconnection by the computer to the gate array with use of a library as stated above, therefore allowing the semiconductor integrated circuit device with a gate array to be developed without error and in a short period of time. Additionally, for example, in developing a large scale computer, it is necessary to make a large number of chips including a multiplicity of gates. In this case, a gate array is suitable because it can be manufactured at a low cost, and a debugging is readily conducted.
As stated above, a gate array is becoming very important in developing a semiconductor integrated circuit device. With improvement in integration of an integrated circuit, however, the number of flipflops or latches included in a gate array is increased. It is also necessary to meet the need that the device should be operated at a high speed. For that, it is necessary to make a skew as small as possible which occurs in a clock signal provided to a flipflop included in each basic cell. A skew is a deviation of the timing of a clock signal supplied to each flipflop.
Consider the case in which pulses 90a, 90b of a clock signal supplied to flipflops at two different points do not deviate from each other in time as shown in FIGS. 7 (a) and (b). The time period T1 is long enough for the cycle time for operating the system. However, as shown in FIGS. 8 (a), (b), considering the case in which a large skew occurs to the pulses 90a, 90b of the clock signal supplied to different flipflops, the cycle time should be made longer, such as T2. Otherwise, the state of each flipflop included in the semiconductor integrated circuit device becomes disordered. That is, when there is a skew, an operating speed of a semiconductor integrated circuit device is not increased. Even if integration of the semiconductor integrated circuit device is increased, its operating speed remains the same.
Accordingly, there has been proposed a method in which a skew is controlled by distributing the clock signal to a plurality of drivers. FIG. 9 is a plan view of a chip 26 of a gate array semiconductor integrated circuit device in which such a method is adopted. Referring to FIG. 9, the chip 26, as well as the gate array semiconductor integrated circuit device shown in FIG. 1, includes basic cell columns 28, an interconnection region 29 provided around the basic cell columns 28, an input-output region 27 provided around the interconnection region 29, and a pad forming region around the input-output region 27, along the outer periphery of the chip 26.
In a part of the input-output buffer region 27, there is provided a clock signal driver 33 connected to one clock input pad 32 formed in the pad forming region 35 for providing a clock signal to the basic cell columns 28 with a sufficient drive capability. In each basic cell column 28 are formed one or a plurality of subdrivers 31 for distributing and providing a clock signal supplied through a clock signal interconnection 34 from the clock signal driver 33, to flipflops in each basic cell column 28 through a clock signal interconnection 36.
In the pad forming region 35, there are formed, in addition to the clock signal input pad 32, signal bonding pads 30 arranged regularly, a pad 61 for power supply to which an external power supply provided to the chip 26 is connected, and a grounding pad 62 to which a circuit in the chip 26 is connected. The pad forming region 35 adjoining the pad for power supply 61, and the input-output buffer region form a power supply pin region 63. Part of the pad forming region 35 adjoining the grounding pad 62 and part of the input-output region 27 form a ground pin region 64.
FIG. 10 is an enlarged plan view of a region 65 including the power supply pin region 63 and the ground pin region 64 shown in FIG. 9. Referring to FIG. 10, in the input-output buffer region, there are formed a power supply interconnection 37 for output buffer connected to the pad 61 for providing the power supply to the output buffer, a ground interconnection 38 for output buffer connected to the grounding pad 62 for connecting each output buffer with an external ground potential, a power supply interconnection 39 for providing the power supply to an input buffer and a prebuffer, and a ground interconnection 40 for connecting the input buffer and the prebuffer with an external ground potential.
In a lower portion of the power supply interconnection 37 for output buffer in the input-output buffer region 27 except the region of the power supply pin region 63 and the ground pin region 64, pMOS transistors 41 for output buffer are formed. Similarly, in the lower portion of the ground interconnection 38 for output buffer, nMOS transistors 42 for output buffer are formed. In the lower portion of the power supply interconnection 39 for input buffer and prebuffer, pMOS transistors 43 for input buffer and prebuffer are formed. In the lower portion of the ground interconnection 40 for input buffer and prebuffer, nMOS transistors 44 for input buffer and prebuffer are formed. The source of the pMOS transistor 41 is connected to the interconnection 37. The source of the pMOS transistor 43 is connected to the interconnection 39. The source of the nMOS transistor 42 is connected to the interconnection 38. The source of the nMOS transistor 44 is connected to the interconnection 40.
In the input-output buffer region 27 adjoining the pad 30 for connection, an input-output cell 91 as shown in FIG. 11 is formed by transistors 41 to 44 shown in FIG. 10.
Referring to FIG. 11, the input-output cell 91 includes an output buffer 92 formed by the transistors 41, 42 and so on, and a diode 94. They are not connected to each other. The input-output cell 91 further includes an input buffer 93 formed by the transistors 43, 44 and so on and a diode 95. They are not connected to each other, either.
Referring to FIG. 12, in the process of personalization, if the input-output cell 91 is used as an output buffer, the output buffer 92 and a logic circuit inside of the chip are connected to each other. The output of the output buffer 92, the input of the diode 94 and the bonding pad for connection 30 are connected together. In this case, the input buffer 93 is not used. Conversely, when the input-output cell 91 is used as an input buffer, the input buffer 93 is connected to the bonding pad 30 and to the internal logic circuit.
The gate array semiconductor integrated circuit devices shown in FIGS. 9 to 12 operate as follows after being personalized. The clock signal driver 33 provides a clock signal externally applied over the clock signal input pad 32, to a subdriver 31 over the interconnection 34 with a sufficient drive capability. The subdriver 31 provides the supplied clock signal to each flipflop in the basic cell columns 28 with a sufficient drive capability. Each flipflop in the basic cell columns 28 operates as a logic circuit formed as a result of personalization.
Among the input-output cells 91 provided in connection with each bonding pad 30 for connection, ones that operate as a buffer for input supply the information externally applied through the bonding pad 30 to the flipflop of each logic circuit within the basic cell columns 28. Among the input-output cells 91, ones personalized as an output buffer supply the outputs of the flipflops of the logic circuit within the basic cell columns 28 to an external circuit through the bonding pad 30 for connection. At this time, each flipflop operates synchronizing with a clock signal applied from the clock signal input pad 32.
FIG. 13 is a plan view of a chip of another example of a conventional semiconductor integrated circuit device in which a specific method is adopted in order to control a clock skew. In FIGS. 9 and 13, the same or the corresponding portions are given the same reference designations and names. Their functions are also the same. Accordingly, a detailed description thereof will not be repeated here.
The semiconductor integrated circuit device shown in FIG. 13 is different from the device shown in FIG. 9 in that it includes, in place of the clock signal driver 33 and the subdrivers 31, a clock signal driver 46 connected to a clock signal input pad 45, and formed within the input-output buffer 27 for providing a clock signal collectively over each clock signal interconnection 47 to each flipflop in the basic cell columns 28.
The chip 26 of the semiconductor integrated circuit device shown in FIG. 13 operates as follows after the processes of personalization. A clock signal is externally applied to the clock signal driver 46 over the clock signal input pad 45. The clock signal driver 46 distributes and provides the clock signal to each flipflop through the clock signal interconnection 47 with a sufficient drive capability.
It should be noted that the clock driver 46 is formed in the region other than the power supply pin region 63 or the ground pin region 64.
The conventional semiconductor integrated circuit device, however, has disadvantages as follows. Firstly, in the case of the semiconductor integrated circuit device shown in FIG. 9, there is a possibility that the performance of each subdriver 31 varies. For that reason, it is possible that there will be a skew in a clock signal supplied from each subdriver 31. As long as the processes of the automatic layout interconnection is effected, using a CAD in the process of personalization, it is difficult to make the same the distances of interconnection between the clock signal driver 33 and each subdriver 31, and to make the same the distances between each subdriver 31 and each flipflop. Accordingly, there is a possibility that a skew due to the difference in the length of interconnection may occur in the clock signal. When each subdriver operates, there may be fluctuation in the ground potential. This fluctuation adversely affects the logic circuit as a noise.
In the semiconductor integrated circuit device shown in FIG. 13, there is a problem that the drive capability of the clock signal driver 46 must be increased as the number of gates included in the device becomes larger. For that, it is necessary to form a large clock signal driver in the input-output buffer region 27, which reduces the number of input-output buffers which may be utilized, and the number of the usable input-output pins. In accordance with Rent's law shown in FIG. 14, as the number of gates included in the gate array becomes large, the number of pins to be provided in the chip is increased. Accordingly, it is necessary to ensure as many usable pins as possible in order to increase integration of the semiconductor integrated circuit device. The use of the large clock signal driver 46 as stated above prevents the improvement in integration of a semiconductor integrated circuit device.
If the gate array is adapted for more purposes, the number of unit cells included therein becomes larger, and the number of devices used as input-output buffer is also increased. A larger area of the chip is also required for the input-output buffer. The use of a large clock signal driver prevents the gate array from being adapted to the wider range of purposes.
Furthermore, as shown in FIG. 13, when the clock signal driver and the ground pin are apart from each other, the inductance therebetween is increased. For that reason, it is possible that the noise appearing on the ground potential is increased. That is, in the case of the semiconductor integrated circuit device shown in FIG. 13, while the skew which occurs in the clock is reduced, the improvement in the performance of the semiconductor integrated circuit device is prevented.

Semiconductor integrated circuit device having gate array


An audio track disabling system and method wherein the track disabling system includes a disk holding assembly, for holding an audio compact disk, and a marking mechanism that includes a marking tip and a marking tip positioning mechanism; and the track disabling method includes the steps of 1) providing a track disabling system that includes a disk holding assembly, for holding an audio compact disk, and a marking mechanism that includes a marking tip and a marking tip positioning mechanism; 2) positioning an audio compact disk onto the disk holding assembly; 3) manipulating the positioning mechanism in a manner to position the marking tip onto a surface of the audio compact disk that is above the audio track to be disabled; and 4) manipulating the marking tip in a manner to create a disabling mark that provides a light blocking obstruction on the surface of the audio compact disk above the audio track to be disabled.

It is often desirable to remove or otherwise disable one or more audio tracks from an audio compact disk. It would be a benefit, therefore, to have a track disabling system for disabling particular tracks on an audio compact disk and a method or disabling a particular audio track on an audio compact disk. Because identifying the correct track on the audio compact disk can be difficult, it would be a benefit if the track disabling system for disabling particular tracks on an audio compact disk included a magnification mechanism for assisting an individual to identify the correct track area. In addition, to further assist the individual in identifying the correct track area, it would be a further benefit if the track disabling system for disabling particular tracks on an audio compact disk also included a user positionable light source to create greater contrast between the inter-track demarcation rings and the track audio data storage areas on the audio compact disk.

Track disabling system and method for audio compact disks


A buffer-layer to minimize the size of defects on a reticle substrate prior to deposition of a reflective coating on the substrate. The buffer-layer is formed by either a multilayer deposited on the substrate or by a plurality of sequentially deposited and annealed coatings deposited on the substrate. The plurality of sequentially deposited and annealed coating may comprise multilayer and single layer coatings. The multilayer deposited and annealed buffer layer coatings may be of the same or different material than the reflecting coating thereafter deposited on the buffer-layer.

1. Field of the Invention
The present invention relates to minimizing defects in components produced by lithography, particularly to the mitigation of substrate defects in reticles or masks utilized in extreme ultraviolet lithography, and more particularly to the use of a buffer layer deposited intermediate a reticle substrate and a reflective coating for mitigating substrate defects in reticles, the buffer layer being formed by a sequential coating and annealing process.
2. Description of Related Art
Extreme ultraviolet lithography (EUVL) systems are being developed for the production of electronic components formed on wafers via reflected radiation. The EUVL systems include reticles or masks that must be essentially free of defects that will print at the wafer which will yield defective components. The reticles, for example, may be fabricated by depositing highly reflective multilayer coatings, such as Mo/Si, on super polished substrates. Any localized structural imperfections on the reticle substrate may nucleate and evolve during the multilayer coating process into a defect that perturbs the reflected radiation field sufficiently to print at the water. Thus, there has been a need for mitigating the effect of small particle contaminants on the surface of the substrate that would nucleate a defect in the reflective coating.
The reticle defect problem may be divided into two components. First, there are the defects associated with the condition of the reticle substrate. These are particles, pits, or scratches on the reticle substrate that nucleate a growth defect in the multilayer coating. Second, there are the defects that are introduced during or after the multilayer coating process, which are particle contaminants that are embedded within or are sitting on the top surface of the coating. A low defect multilayer coating technology based on ion beam sputtering has been developed so that the coatings now being deposited are essentially defect-free, thus the greater risk is the starting conditions of the reticle substrate.
Modeling has been carried out that simulates the growth defects nucleated by spherical particles. The results have indicated that particles as small as about 25 nm in diameter will nucleate defects in multilayer coatings, which can image at the wafer. Hence, all particles of a size greater than about 25 nm must be removed from the reticle substrates prior to the deposition of the reflective coating. Currently, removal of particles from the reticle substrates is carried out by cleaning processes that are expected to be ineffective for the removal of particles of less than about 60 nm, particularly since verification that such small particles exist is difficult.
Prior efforts to resolve the reticle substrate defect problem involved a single layer buffer-layer, see K. B. Nguyen, et al., J. Vac. Sci. Technol. 11:2964 (1993), where a 200 nm thick single-layer amorphous silicon (a-Si) buffer-layer was deposited on the substrate prior to a Mo/Si multilayer deposition in an attempt to smooth out lithographically defined steps (defects) on a silicon surface. This resulted in some reduction in the defect height and the transition at the edges of the step was made less severe by the buffer-layer, which is advantageous. However, the surface roughness of the Si was increased significantly (from 0.2 nm to 0.7 nm), making this process impractical for EUV lithography.
Currently, there is a process having the capability of depositing a-Si approaching 200 nm in thickness with much lower roughness than that observed by Nguyen, referenced above. However, the large stress typically found in smooth, single-layer films like a-Si can limit the applicability of this single-layer approach for the buffer layer.
As an alternative to cleaning and single-layer buffer layers, the invention described and claimed in above referenced application Ser. No. 09/454,715, mitigates the effects of these small particles by depositing a multilayer film as a buffer layer in between the substrate and the reflective coating and the multilayer film can be deposited alone or with annealing during and or after deposition. The purpose of this buffer layer is to reduce the perturbation of the reflective coating due to particles, pits, or scratches on the substrate.
The present invention is an improvement over the technique of application Ser. No. 09/454,715 and involves mitigating the effect of the substrate particles on reticles by sequential coating and annealing. The sequential buffer layer coatings may be single layer or multilayer coatings and of the same or different materials, with either slow or fast post deposition annealing after each coating step.
The buffer layer coatings may be of the same material as the reflective deposited coating. The first buffer-layer may be tailored to flatten-out higher aspect ratio bumps and asperities. The second and subsequent buffer-layer coatings would be tailored to flatten out lower aspect ratio bumps and asperities. A reflective multilayer coating is later deposited on this healed surface to form a reticle blank for extreme ultraviolet (EVU) lithography.
It is an object of the present invention to mitigate the effects of substrate defects in coated reticles used for extreme ultraviolet lithography. A further object of the invention is to provide a reticle substrate with sequentially deposited and annealed buffer layers to mitigate substrate defects. A further object of the invention is to provide sequentially deposited buffer layer between a reticle substrate and a multilayer reflective coating with post annealing of each deposited buffer layer to mitigate the adverse effects of substrate defects. Another object of the invention is to provide a plurality of buffer layers between the substrate and a multilayer coating of a reticle utilized in extreme ultraviolet lithography, each buffer layer being annealed following deposition.
Yet another object of the invention involves the mitigation of substrate defects in reticles for extreme ultraviolet lithography using single layer or multilayer annealed buffer layers that are atomically smooth, have good smoothing properties, have low residual stress, and the multilayer buffer layers exhibit contraction during growth due to intermixing of the interfaces.
Other objects and advantages of the present invention will become apparent from the following description and accompanying drawings. The present invention is directed to mitigate the effects of particles or other defects on a reticle substrate, particularly having a size  less than 60 nm, by depositing annealed single or multilayer films as buffer layers between the substrate and the reflective coatings. The purpose of this buffer layer is to reduce the perturbation of the reflective coatings due to the particles, pits, or scratches on the substrate. Specifically, the sequentially deposited and annealed buffer layers are designed to smooth out the substrate topography to a point where the remaining perturbations are too small to nucleate growth defects in the reflective coating that will print in an EUV lithography tool. The buffer layers are not used as a reflective coating, and thus their reflectivity to EUVL radiation need not be optimized.
The sequential buffer layers exhibit several basic characteristics. The buffer layers provide smoothing behavior, that is, relaxation of the surface height variations due to the particles, pits and scratches on the substrate. The multilayer buffer layers also exhibit volume contraction during growth due to intermixing at the interfaces of the alternating layers. The buffer layers do not substantially increase the high spatial frequency roughness of the substrate surface (e.g., roughness is typically less than about 0.3 nm rms). The buffer layers have sufficiently low residual stress (less than about 500 MPa) so that a total buffer layer thickness of up to about 100 xcexcm can be deposited without compromising the performance and stability of the reflective coating. Finally, the deposition process of each sequential buffer layer should be clean; there should must be substantially no defects added in the process of growing the buffer multilayer.
The buffer layers may be made from materials different from the reflective coating, or from the same materials. Although the buffer layers may be made from the same materials as the reflective multilayer, the buffer layers serve a different function and need not be optimized for high reflectance. For example the multilayer buffer layers may differ structurally from the reflective coating because of the intermixing at the layer interfaces.
Multilayer materials that are atomically smooth and have good smoothing properties may be used as the buffer layer. Multilayer systems that satisfy the above-listed multilayer buffer layer requirements include ion beam sputtered (IBS) molybdenum-silicon (Mo/Si), and MoRu/Be multilayer films. Other potential buffer layer multilayer materials that demonstrate the above-listed characteristics include Me/Si, Me/Be, Me/B, and Me/B4C, and where Me is a metal or alloy such as Mo, W, Ni, Cr, Ru, Rh, MoRu, or MoRh.
In the present invention, the buffer layers are deposited using an ultraclean ion beam sputtering process so that no defects are added in the deposition step. Each deposited buffer layer is annealed by a rapid or slow annealing technique. The buffer layers are deposited with minimal surface roughness and residual stress so that they do not compromise the performance of the reflective multilayer coating deposited on top of the buffer layers. The same ion beam tool can also be used to deposit the overlying reflective coating.
The present invention is a sequential coating and annealing technique to mitigate the effects of small particle contaminants in reticles for EUV lithography. The first step is to deposit a low particulate, very smooth buffer-layer coating which could have a significant amount of film stress; ion beam sputtered Mo/Si multilayer coatings and amorphous Si coatings are two examples. The first buffer-layer coating will likely be tailored to flatten out high aspect ratio bumps and asperities. Due to the significant film stress and the relatively thick substrates needed for the reticles, only a modest coating thickness can be applied at first. The sample is then annealed, either slowly or rapidly, with a temperature compatible with the substrates. Another buffer-layer coating layer is then applied and subsequently annealed, and the procedure is repeated as many times as is necessary to smooth the topology of the coating surface while retaining a surface with a sufficiently low roughness. The second and subsequent buffer-layer coatings could be tailored to flatten out low aspect ratio bumps and asperities. A reflective multilayer coating is later deposited on this healed surface to form a reticle blank for EUV lithography. In addition to Mo/Si, the multilayer coating may be composed of MoRu/Be or Mo/Be; and in addition to a-Si the single layer coatings may be composed of amorphous carbon. The annealing temperature and time would vary depending on the composition of the coating.
There is a strong commercial driving force for increased miniaturization in electronic devices, and EUVL systems have significant potential provided that a critical element thereof, the reflective multilayer reticle, is nearly defect-free.
Thus, the present invention has the potential to make such a system commercially viable.

Mitigation of substrate defects in reflective reticles using sequential coating and annealing

The Regents of the University of California


Neutron detectors including one or more gamma shields over memory dies and methods of making the neutron detectors are provided. The neutron detectors can contain two or more memory dies, neutron-reactant layers over the two or more memory dies, and one or more gamma shields over at least a portion of or an entire of the two or more memory dies. By containing the gamma shield over the at least a portion of or an entire of the two or more memory dies, the neutron detector can detect and discriminate neutrons in the presence of gamma rays.

Conventional neutron detectors generally include a sealed vessel containing a neutron sensitive gas, such as 3He or BF3, and an electrically charged wire having leads which extend outside of the vessel. In operation, incident neutrons react with the gas and produce charged particles. The charged particles change the electrical potential of the wire. A measurement system coupled to the charged wire measures the electrical pulses and uses this information to indicate the presence of neutrons. These types of neutrons detectors are usually undesirably bulky and are associated with poor sensitivity resulting from, for example, electronic noise.
Attempts have been made to produce more portable neutron detectors using semiconductors. For example, 3He is diffused into a semiconductor substrate and used in the detection of neutrons. Neutrons react with the 3He gas and produces hole-electron pairs in a depletion layer within the semiconductor. The hole-electron pairs produce output electrical pulses which appear at the output terminals of the detector. The electrical pulses are utilized for detecting neutrons.
Semiconductor-based radiation detectors generally have a single-crystal substrate with a p-n junction or a Schottky junction. An inverse bias is applied to the depletion layer. When radiation in the form of neutrons, gamma-rays, X-rays, electrons, protons, etc. are absorbed by the material, electron-hole pairs are created. These charges give rise to a current that is a measure of the intensity of the radiation flux detected by the detector.

Arrayed neutron detector with multi shielding allowing for discrimination between radiation types


An apparatus for housing fans includes a mounting body portion and first, second and third fan housings. The mounting body portion has a length, and includes first and second longitudinal sides. The fan housings are operably attached to the mounting body portion. The fan housings also have a length. The sum of the lengths of the fan housings are greater than the length of the mounting body portion. The fan housings include a cable trough. Each of the cable troughs are oriented adjacent to a region of the mounting body portion bounded by each of the fan housings.

Among other uses, fans are presently utilized to reduce the temperature of the various parts of electronic equipment. Typically, these fans are housed within fan housings, which are then placed within an apparatus, which is attached to a side of the equipment for which the fans are meant to cool. Such fan housings have been designed in many ways, encompassing differing shapes and sizes. However, in many respects, the lack of efficiency of these varying designs is readily apparent.
First, in an effort to increase the output of cooling ability of the fans, which is necessary to prevent overheating and possible meltdown of electronic devices, most designs have relied on a "bigger is better" premise, and have increased the size of the fans themselves. However, such a constructive theory has conversely led to other liabilities, including an increase in the required space, the required number of parts, the intensity of labor, the weight, and the cost of production.
As a result, such an increase in size lowered the efficiency of the temperature reduction process, as the amount of cubic feet per minute (CPM) which could be cooled became abated. Also, such a size increase runs contrary to today's electronic world, in which the aforementioned premise applies to ability, speed and power, and not to size. In fact, with the advent of laptop computers, cellular telephones, and the like, most electronic items these days emphasize their reduction in size from items past. In addition, such electronic cooling devices should include a means by which the circuitry used to power such devices can be relied upon almost indefinitely.
Finally, typical cooling devices have the added problem of being assembled in a myriad of ways, thus further increasing the efficiency of the labor involved. Also, a non-uniform method of assembly requires additional parts, such as, for example, longer electric power cables.
Accordingly, it would be desirable to provide an apparatus for housing fans that could maintain proper redundancy and a high CPM, while keeping cost and size down, and which can be oriented in a simple manner.