A new slurry for shallow trench isolation (STI) processing in the chemical mechanical planarization (CMP) in microelectronic industry comprising an aqueous medium having an abrasive; and a compound which has a carboxylic group and an electrophilic functional group. The combination of ceria and/or titania with amino acids to obtain polishing selectivity's greater than 5:1. CMP is used for removing the excess oxide and planarizing the substrate and the trench. The silicon nitride acts as a stop layer, preventing the polishing of underlying silicon substrate.

There are numerous references within the prior art for the removal of dielectric films, silicon dioxide, silicon nitride by Chemical-Mechanical Polishing (CMP) regulated and moderated by the interaction of abrasive particulate within a slurry. Changes in the slurry solution properties have a profound effect on the polishing chemistry and relative removal rates of dielectric films. Common slurry solution properties include pH, temperature, slurry particle composition, its size and shape, degree of agglomeration, and slurry weight percent. While the slurry vendor has control over most slurry properties, the pH and temperature can be controlled during the polishing process and can have a strong influence on CMP results.
CMP relies on mechanical means with chemical activity to remove and ultimately planarize the top film or films on wafers during semiconductor processing. The mechanical action during CMP, including table speed, applied force, pad hardness, etc., are typically used to control rate, planarity, and uniformity. The chemical portion of CMP is usually exploited to achieve selectivity and help deal with issues of pattern dependence such as erosion and dishing. Silica slurries are typically prepared with pH greater than 8, while ceria slurries have pH ranging from 4 to 10. In both cases the pH of the suspension can have a strong effect on polish rate and selectivity. Knowing the effect of pH on rate and film selectivity can be used to help understand and control the CMP process and achieve the desired result.
A study of the pertinent prior art references indicates that there are a few compositions of CMP slurries which provide a fairly high oxide to nitride removal rate selectivity. Those that are known are summarized below, but none of these prior art references have the composition or the wide working range of pH.
Conventional CMP slurries used for polishing oxides typically comprise of an abrasive in alkaline medium (high pH). They polish both oxide and nitride at substantial rates with a selectivity of about 10 or below. Hence new slurries which can provide a very high oxide to nitride selectivity are needed to overcome the problem of polishing nitride and the underlying silicon substrate.
There are a number of prior art patent references for slurries used in CMP: (1) U.S. Pat. No. 5,738,800 issued in April 1998 to Hosali, et al.; (2) U.S. Pat. No. 5,759,917 issued in June 1998 to Grover et al.; (3) EP 0 786 504 A2 published in July 1997 by Kodama et al.; (4) EP 0 846 740 A1 published in June 1998 by Ronay; and (5) EP 0 853 335 A2 published in July 1998 by Morrison et al.
Additional prior art references in the form of technical publications that are related to the present invention are summarized below.
Chemical Mechanical Planarization of Microelectronic Materials; "8.1.2 Shallow Trench Isolation", by J. M. Steigerwald, S. P. Muraka, and R. J. Gutman; ISBN 0-471-13827-4 (Jon Wiley & Son, Inc.1997), pages 273–274. This reference gives a general discussion of the desirability of using Shallow Trench Isolation in place of Local Oxidation of Silicon (LOCOS). While this reference teaches that conventional CMP processes have low selectivity between oxides and nitrides, no insight into a potential correction for this problem is taught.
A High Oxide:Nitride Selectivity CMP Slurry for Shallow Trench Isolation; by Sharath Hosali and Ray Lavoie; in Electrochemical Society Proceedings, Volume 98-7, pages 218–234. This reference teaches a slurry that enhances the selectivity rate between silicon oxide and silicon nitride. The slurry taught has cerium oxide as an abrasive with a proprietary solution that inhibits the removal rate of the silicon nitride. The results of this prior art references indicate a high rate of selectivity for unpatterned wafers, however, the selectivity for patterned wafers is almost the same as with the conventional slurry that it was compared against.
Application Of Ceria-Based High Selectivity Slurry to STI CMP For Sub 0.18 μm CMOS Technologies; by Ki-Sik Choi, Sang-Ick Lee, Chang-Il Kim, Chul-Woo Nam, Sam-Dong Kim, and Chung-Tae Kim; CMP-MIC Conference, Feb. 11–12, 1999. This paper teaches the use of a ceria based slurry for CMP purposes in a STI setting. While, the slurry discussed may have been selective, there is no teaching related to the manufacturing of the slurry. Moreover, in order to prevent dishing from the CMP process, dummy patterns are required. Also, there are some problems related to scratches from the ceria abrasive which require filtering to correct.
A Production-Proven Shallow Trench Isolation (STI) Solution Using Novel CMP Concepts; by Raymond R. Jin, Jeffery David, Bob Abbassi, Tom Osterheld, and Fritz Redeker; in CMP-MIC Conference on Feb. 11–12, 1999. This reference discusses the previously discussed problem of having to use dummy patterns to reduce dishing. The solution offered by this prior art reference is to employ a low selectivity, or no selectivity, slurry for minimizing dishing during over polishing in combination with special system apparatus and polishing heads.
A Wide Margin CMP And Clean Process For Shallow Trench Isolation Applications; by Brad Withers, Eugene Zhao, Rahul Jairath; in CMP-MIC Conference on Feb. 11–12, 1998, pages 319–327. This reference addresses the problems of process cost and complexity due to the need for block masks, pattern resist etch, high selectivity material overlayers or implementation of dummy active areas.
It should be readily apparent from the foregoing discussion that there remains a need within the art for a method of chemical mechanical polishing and a slurry for that purpose that is selective and has the wide working range of pH of the present invention.

Slurry for chemical mechanical polishing silicon dioxide


A system identification module for storing system specific information is described. The system includes a housing, a module connector and a persistent memory for storing system specific data associated with a communications system having a backplane. The housing and the module connector define an enclosure surrounding the persistent memory. The module connector can be electrically coupled to and removed from the backplane connector. The persistent memory can be a programmable read-only memory device. System specific information such as the system serial number, the date of manufacture, the system vintage and the common language equipment identifier (CLEI) code can be remotely accessed using the system identification module.

Electronic equipment used for communications is often structured in a rack mountable shelf format. A shelf typically includes multiple cards, or circuit packs that are interconnected through a backplane. Each card provides a service or function, such as an optical service, an Ethernet service, or a cross connect function. Each shelf can be distinguished from other shelves according to various shelf information, or backplane information, including, for example, product configuration, serial number and date of manufacture. Moreover, each shelf can have a set of unique identifiers such as Ethernet MAC addresses and a shelf serial number.
The task of identifying a shelf embedded in a communications network can be prohibitive due to the number of shelves deployed in the network. Because the backplane information is not known or recorded separately, a technician has to inspect the shelf directly to determine the specific shelf information. Memory devices can be used with the backplane to keep the identifier information. The memory devices are generally soldered or otherwise permanently connected to the backplane. Thus, if a memory device fails, repair of the memory device requires significant work and associated cost to retrieve the backplane and affect replacement of the device.
Accordingly, there exists a need for an identification module to permit retrieval of shelf specific information from shelves deployed in the field. The identification module should be field-replaceable to eliminate the effort and associated cost otherwise incurred when the shelf is removed from the field to replace a failed module. The present invention satisfies this need and provides additional advantages.

System identification module for a communications system


A cooling circuit arrangement includes first and second closed cooling circuits. Each closed cooling circuit has a heat source, a pump and a radiator. By way of the first pump of the first circuit, a coolant can be conveyed to the first radiator and from the first radiator to the first heat source and from the latter to the first pump. By way of the second pump of the second circuit, a coolant can be conveyed to the second radiator and can be conveyed from the second radiator to the second heat source and from the latter to the second pump. Downstream of the first pump and of the second pump, there is provided a first fluidic connection which is controllable by a first valve. Upstream of the first pump and the second pump, there is provided a second fluidic connection which is controllable by a second valve.

Cooling circuits are known in motor vehicles, for example for the purposes of cooling an internal combustion engine. Here, a heat source for cooling, a pump for circulating the cooling fluid and a radiator for cooling the cooling fluid are provided in a cooling circuit. It is also possible for multiple heat sources to be cooled if necessary.
In electric vehicles with at least one electric motor as drive motor, the electric motor as drive motor must typically also be cooled, and also the energy storage which feeds the electric motor must be cooled as required. The incorporation of both heat sources, that is to say electric motor and energy storage, into the cooling circuit does not provide optimum cooling, because the target temperatures and the heat quantity to be dissipated differ considerably for the two heat sources.


A method for reducing formaldehyde emissions from articles prepared from, or which otherwise comprise formaldehyde-emitting compositions, such as formaldehyde-containing resins, is described. The method relates especially to a method for reducing formaldehyde emissions from products such as cellulose laminates, permanent press (wrinkle-free) textiles, floral foams and ceiling or acoustical tiles, which involves isolating the article in an enclosed space with a formaldehyde scavenger, particularly a formaldehyde scavenger carried by a substrate.

Formaldehyde-based resins or formaldehyde-containing resins, such as urea-formaldehyde (UF) resins, phenol-formaldehyde (PF) resins, including PF resins extended with urea (PFU), melamine-formaldehyde (MF) resins, melamine-formaldehyde resins modified with urea (MUF) and the like, find widespread use as adhesives, bonding agents and strengthening agents for making a wide variety of products.
For example, PF and PUF resins in particular have been the mainstays of fiberglass insulation binder technology over the past several years. Such resins are inexpensive and provide cured fiberglass insulation products with excellent physical properties.
Such formaldehyde-base resins, particularly, MF, MUF and UF resins, have been used as binders in acoustical tiles, e.g., ceiling tiles, and PF and MF resins have been used to impregnate or saturate thin fibrous, usually cellulosic, e.g., paper, sheets which are assembled in layers and cured to form protective, decorative laminates.
Formaldehyde itself, or compositions based on formaldehyde or which emit formaldehyde also have long been used to provide permanent press, or wrinkle free characteristics to textiles. Representative of this technology are U.S. Pat. Nos. 6,827,746; 5,885,303; 4,396,390 and 4,108,598.
Rigid but friable foams made from PF and UF resins also are widely used to provide water to cut flowers. These commercially available floral foams usually are formulated as an open-celled, cured PF resin, and have the capability of retaining a significant amount of moisture.
The ability of these formaldehyde-based compositions to provide the necessary performance benefits at a reduced cost relative to other technologies has thus made such formaldehyde-based compositions, including UF, PF, MF, MUF and PUF resins, popular in connection with the preparation of a variety of products that find their way into commercial and residential uses.
One of the drawbacks of using formaldehyde-based compositions in such applications, however, is the potential for formaldehyde emissions from the finished article. It is known that gaseous formaldehyde is released from such articles, some of which is attributable to unreacted formaldehyde in the cured resin binder and some of which may be attributable to degradation or decomposition products generated over time under acidic conditions, elevated temperatures, and/or high humidity from components of the articles.
Thus, there is a continuing need for new methods for reducing formaldehyde emission in products produced using formaldehyde-based or formaldehyde containing compositions.


The present invention is directed to an architecture and mechanism for securely backing up files and directories on a local machine onto untrusted servers over an insecure network.

The invention relates to systems and methods for securely transferring data between a local storage area and a remote storage area.
Many systems and schemes have been devised to "backup" important information on various storage media, i.e. maintain another copy of the information so that the information may be restored should the original copy of the information become damaged or otherwise unavailable. Unfortunately, backup media rarely receive the same protection and attention as the original data itself. Despite the critical nature of backup in recovering from loss due to accidental or malicious failure, it is one of the most overlooked processes when it comes to site security.
Most backup techniques today involve transferring data over a network, which thereby renders the backup data vulnerable to attack at several points. There are several commercial products that offer network-based backup services. See, e.g., http://www.backup.com, http://www.BitSTOR.com, http://www.backjack.com, http://datalock.com, http://www.systemrestore.com, http://www.trgcomm.com, http://www.sgii.com, http://www.veritas.com/us/products/telebackup. The most common technique for protecting backups is to encrypt files locally using a key derived from a passphrase. While such services range in features and in style of architecture, unfortunately, none of them are well-designed from the security point-of-view. Many are in fact insecure as well as inefficient and do not provide the proper level of data authentication and confidentiality.


A security system uses rules to restrict access to objects of a database. These security rules are dynamic because they can adjust when the number of objects in the database is changing. In other words, the security rules can permit access to new objects when new objects are added to, modified, or deleted from the database. With this system, objects can be added to a container by a security administrator or they can be added based upon the triggering or activation of one or more rules. With this system, access to objects in a database is usually determined after each request for access instead of relying on a static permanent list.

Conventional security for accessing objects in databases is usually dependent on the object of interest, meaning that permissions for a user are assigned to an object or a folder of objects. If a user is granted a different permission level for a particular action relating to an object, such as being able to modify a file in a file folder when previously the user had read only access for the file, then it is necessary to change the permission level associated with the object. In the aforementioned case, the object happens to be a file. But the object could also be file folder containing a group of files. Because of its dependency on individual objects, conventional security can be characterized as being "object-specific."
Several problems of the object-specific conventional security manifest themselves in the project management environment where user groups are assigned to a specific folder in a database to store and modify their files. For example, a western geographic region of users maybe required save their files in a "West" folder. Meanwhile, an eastern geographic region of users maybe required save their files in an "East" folder. In the same set of circumstances, the eastern geographic region of users maybe required to have access only to one-half of the contents of the "West" folder. Similarly, the western geographic region of users maybe required to have access only to one-half of the contents of the "East" folder.
With the object-specific conventional security, one way to resolve this problem is to create a duplicate set of the "West" files in which the eastern region employees have access and are stored in the "East" folder. And similarly, a duplicate set of the "East" files in which the western region employees have access can be created and stored in the "West" folder. These duplicate sets of files for each folder are necessary because in the object-specific conventional security model, security is linked or controlled by the folder. The object-specific conventional security model typically does not permit half access to files contained within a database folder. This Conventional security can be characterized as an "all" or "nothing" approach relative to access or permission level for a particular folder.
One problem with maintaining duplicate sets of files is that there could be some uncertainty as to how current the duplicate set of files is relative to the original set of files. Even an automated duplication system would have problems, especially if there are large volumes of files and constant edits being performed by different users on the original set of files. Another problem exists when a user wants to modify the "duplicate" of a file. It would be quite a challenge to have any changes made to a "duplicate" file to be reflective or later saved back into the original file from which the duplicate file was made.
Another way to solve this problem of accessing the same objects by different users of different user groups is to set the permissions directly on each of the required files in the "West" folder instead of setting permissions based upon a folder. Setting permissions based on individual files within a folder could permit eastern region employees to access the files stored in the "West" folder. Likewise, permissions could be set directly on each of the files in the "East" folder to permit western region employees to access the files stored in the "East" folder. But this solution can be quite troublesome because it would require the manual setting of individual permissions for each employee on each affected file.
In other words, another problem of the object-specific conventional security is that it is very difficult to customize permission or access settings for numerous individual users. For example, to customize permission or access settings for 1000 users who have access to 100+ files or file folders would require significant man power because each of the 100+ files or file folders would require custom or individualized settings.
Accordingly there is a need in the art for a security system permits individual customization for numerous users that reduces any work needed to make the customizations. There is also a need in the art for a security system that can permit different tiers of access to different groups of files within the same file folder. Another need exists in the art for a security system that does not require the duplication of files to permit access to information. A further need exists in the art for a security system that is dynamic and which can automatically respond to instantaneous changes to a database such as modifications to existing files or creation of new files. Another need exists in the art for a security system that can support users who can be members of various user groups, who in turn, may have various levels of access.

Controlling access to objects with rules for a work management environment


A device for producing cigarettes in the tobacco processing industry that has a tobacco processing unit and a paper feeding unit, which feeds a paper having LIP strips to the tobacco processing unit, wherein the paper feeding unit has a measurement device, which continuously detects the LIP strips, wherein the measurement device has a microwave resonator, through whose measurement region the paper having the LIP strip is passing, and which detects a shift of the resonance curve and/or a broadening of the resonance frequency.

The present invention relates to a device for producing cigarettes in the tobacco processing industry and a method therefore.
US 2005/0172977 A1, the entire contents of which is incorporated herein by reference, discloses the production of tobacco products with a paper that has relatively low ignition properties. In technical language, such papers are designated as "low ignition propensity (LIP)" papers.
LIP paper is characterized in that the paper strips responsible for the LIP effect have a coating that confers the low ignition properties to the paper. These strips, as is known from WO 2009/157720 A2, the entire contents of which is incorporated herein by reference, for example, have a width of 5 mm and completely surround the cigarette. For producing such tobacco products, the initially named application US 2005/0172977 A1, the entire contents of which is incorporated herein by reference, describes that the LIP paper is unrolled from a roll and fed to a tobacco processing unit of the cigarette machine. In order to be able to conduct the feeding speed and the speed during cutting the processed endless tobacco rods into individual cigarettes corresponding to the LIP strips, the LIP paper has synchronization marks. An optically based marking sensor identifies the synchronization marks on the fed paper, and generates corresponding synchronization signals that control the speed of the subsequent processing steps so that the LIP strips of paper are in the desired position on the cigarette. Further, it is known from US 2005/0172977, the entire contents of which is incorporated herein by reference, to use LIP strips themselves as synchronization marks, and to detect these optically in order to generate synchronization signals for producing the cigarette strips. A disadvantage of optically identifying the LIP strips is that they can form a weak contrast and therefore cannot be optically identified with sufficient reliability.
From US 2009/0301506 A1, the entire contents of which is incorporated herein by reference, a method is known for producing a LIP cigarette paper. The LIP strips are applied as a coating to the cigarette paper.
From WO 2009/027831 A2, the entire contents of which is incorporated herein by reference, a cigarette paper is known that has a wave-like circumferential LIP band. Different shapes are proposed for the wave pattern.
From US 2009/0025742 A1, the entire contents of which is incorporated herein by reference, a LIP cigarette paper is known in which the LIP coating consists of a sodium alginate that is applied as an aqueous solution.
From WO 2008/146170 A2, the entire contents of which is incorporated herein by reference, LIP strips for cigarette papers are known that have a wave-like shape.
From EP 1 449 447 A1, the entire contents of which is incorporated herein by reference, a cigarette is known which has a greater tobacco density in a central core region than in the jacket region surrounding the core region.
From WO 02/43513 A1, the entire contents of which is incorporated herein by reference, a cigarette with LIP properties is known in which the glow of the cigarette is reduced in its diameter by cellulose additive so that the cigarette is self-extinguishing.
From U.S. Pat. No. 6,645,605 B2, the entire contents of which is incorporated herein by reference, a material for a cigarette with LIP properties is known in which a coating is applied on the cigarette paper by a thermoplastic polymer.
From EP 2 177 118 A1, the entire contents of which is incorporated herein by reference, a method for processing a LIP strip is known in which the material of the LIP strip is abraded in a positionally accurate manner for improving the adhesion properties.

Device for producing cigarettes in the tobacco processing industry and a method therefore


A wheel bearing apparatus incorporating a wheel speed detecting apparatus and a method for manufacturing the wheel bearing apparatus has a wheel speed detecting apparatus (21) with a sensor holder (22). The sensor holder (22) includes a steel annular fitting ring (24) to be fit onto the end of the outer member (4). A holding portion (25) of plastic resin is integrally molded with the annular fitting ring (24). A wheel speed sensor (26) is embedded in the resin. An inboard side seal (11) of the seals (11, 12) is arranged between the sensor holder (22) and the outer joint member (14). The maximum diameter of the sensor holder (22) and the constant velocity universal joint (3) is smaller than the inner diameter of the knuckle (N).

Wheel bearing apparatus that supports a vehicle wheel relative to a suspension apparatus incorporating a wheel speed detecting apparatus to detect rotational speed of the vehicle wheel to detect the wheel speed to control the anti-lock braking system (ABS) is known. Such a bearing apparatus generally includes a wheel speed detecting apparatus with a magnetic encoder having magnetic poles alternately arranged along its circumferential direction integrated into a sealing apparatus. The sealing apparatus is arranged between the inner and outer members to contain the rolling elements (balls or rollers). A wheel speed detecting sensor is present to detect the variation in the magnetic poles of the magnetic encoder according to the rotation of the wheel.
On the other hand, the wheel bearing apparatus to support a vehicle wheel has been orderly developed. In the first generation type, a double row rolling bearing is independently adopted provided with seals. In the second generation type, an outer member is integrally formed with a body mounting flange. In the third generation type, a wheel hub is integrally formed with a wheel mounting flange. Also, it is formed with one inner raceway surface of a double row rolling bearing on its outer circumferential surface. In the fourth generation type, a wheel hub is further combined with a constant velocity universal joint. The other inner raceway surface of the double row rolling bearing is formed on the outer circumferential surface of the outer joint member forming the constant velocity universal joint.
Recently, there is a tendency to adopt the fourth generation type to reduce weight and size in order to reduce manufacturing cost. In this case it is difficult to keep a space to mount the wheel speed detecting apparatus because of the integration of the constant velocity universal joint to the wheel hub. In such a wheel bearing apparatus, there is concern that foreign matter may become mingled with magnetic powder that would adhere to a magnetic encoder of the detecting portion of the wheel speed detecting apparatus. This is possible because the wheel speed detecting apparatus is exposed to muddy water and the foreign matters would contact the rotation speed detecting sensor and damage it or the magnetic encoder and thus detract from the detecting accuracy. A wheel bearing apparatus of the prior art which can solve such a problem is shown in FIG. 9.
The vehicle wheel bearing apparatus includes a constant velocity universal joint 51; a wheel hub 53 mounted on the outer circumference of a shaft portion 52 of the constant velocity universal joint 51; a double row rolling bearing 54 arranged both on the outer circumferences of the shaft portion 52 and the wheel hub 53; an inboard side seal 55 to seal the inboard side of the double row rolling bearing 54 arranged on the outer circumference of the constant velocity universal joint 51; and a wheel speed detecting apparatus 56 arranged on the outer circumference region at the inboard side of the double row rolling bearing 54. In the description of the present disclosure, an outer side of a bearing apparatus, when it is mounted on a vehicle, is referred to as the "outboard" side (the right side in FIG. 9), and an inner side of the bearing apparatus when it is mounted on a vehicle is referred to as the "inboard" side (the left side in FIG. 9).
The constant velocity universal joint 51 has a cup shaped outer joint member 57, a joint inner ring (not shown), torque transmitting balls, cage etc. The outer joint member 57 has a shaft portion 52 with splines 58 mating with splines of wheel hub 54. An outer circumferential surface of the outer joint member 57 is formed with an inner raceway surface 57a. In addition an annular recess 60 is formed between the outer joint member 57 and the shaft portion 52 opened toward the double row rolling bearing 54.
The wheel hub 53 has a hollow cylindrical configuration and is integrally formed with a radially extending wheel mounting flange 61. The hollow bore 62 of the wheel hub 53 is formed with splines 63. Another inner raceway surface 53a of the double row rolling bearing 54 is formed on the outer circumference of the wheel hub 53 at the inboard side of the wheel mounting flange 61.
The double row rolling bearing 54 is formed by a double row angular ball bearing. An outer member 59 is integrally formed with a body mounting flange 59b. Its inner circumference is formed with outer raceway surfaces 59a, 59a. An inner member 64 has double row inner raceway surfaces 53a, 57a on its outer circumference. The inner raceway surfaces 53a, 57a correspond to the double row outer raceway surfaces 59a, 59a. Double row balls 66 are contained between the double row inner and outer raceway surfaces, via cages 65. In the present specification, the inner member 64 includes the outer joint member 57 and the wheel hub 53. A seal 67 is arranged at the outboard side of the outer member 59.
The constant velocity universal joint 51, the wheel hub 53 and the double row rolling bearing 54 are assembled together by engaging splines of the wheel hub 53 and the constant velocity universal joint 51. The seal 67 and balls 66 are previously arranged on the outboard side between the outer member 59 and the wheel hub 53. Then the outboard side end of the shaft portion 52 is caulked on the outboard side end face of the wheel hub by bending the outboard side end of the shaft portion 52 radially outward.
The wheel speed detecting apparatus 56 includes a pulser ring 69 and a wheel speed sensor 70. The pulser ring 69 is formed as a disk. A permanent magnet is arranged on the disk. The magnet includes rubber magnet mingled with ferritic powder with N and S poles being alternately arranged along its circumferential direction. A supporting ring 71, having a L-shaped cross-section is press fit onto the shaft portion 52 of the constant velocity universal joint 51. The pulser ring 69 is secured on the supporting ring 71. A metal core 72, forming the inboard side seal 55 for the double row rolling bearing 54, axially extends to cover the annular recess 60.
A relatively long axial labyrinth gap S is formed between the metal core 72 and the outer joint member 57. The metal core 72 is formed with an elongated oval opening through which the wheel speed sensor 70 is inserted. The wheel speed sensor 70 is arranged opposite to the pulser ring 69 and is formed as an active sensor including a magnetic detecting element such as a Hall effect element or magnetic resistance element to vary output in accordance with the magnetic flow direction. IC etc is incorporated into a circuit to rectify the output wave form of the magnetic detecting element.
A knuckle 73, forming part of a suspension apparatus, is formed with a radially through bore 73a. The wheel speed sensor 70 is screwed into the bore 73a. Thus, the wheel rotation speed can be detected by the wheel speed sensor 70 detecting the variation of magnetic flux of the pulser ring 69 when the pulser ring is rotated in accordance with the rotation of the shaft portion 52 of the constant velocity universal joint 51.
As described above, due to the structure of the axially extending metal core 72 of the seal 55 in the double row rolling bearing 54, the wheel speed sensor 70 being passed through and screwed into the knuckle 73 and the annular recess 60 covered by the metal core 72, ingress of foreign matter, such as muddy water, into the annular recess 60 can be prevented.
Reference: Patent Document 1 (Japanese Laid-open Patent Publication No. 301854/2003).
However, since the detecting portion is merely covered by the labyrinth gap S between the metal core 72 and the outer joint member 57, it is insufficient to perfectly prevent the ingress of foreign matter, such as magnetic powder, although direct exposure to the detecting portion to muddy water can be prevented.
In addition, due to the structure of the wheel speed sensor 70 screwed into the knuckle 73 and passed through the opening of the metal core 72, it is difficult to firmly align the securing bore 73a of the knuckle 73 and the opening of the metal core 72. The number of machining processes of the bore or opening is increased and machining accuracy is required. This additionally increases the manufacturing cost of the wheel bearing apparatus.

Wheel bearing apparatus incorporated with a wheel speed detecting apparatus and method of its assembly


A device for step-feeding golf balls one at a time over a tee located beneath a ground play surface, and for reciprocating the tee (and associated golf ball) vertically through an aperture made in the ground play surface. The striking height of the tee is adjustable with a control lever. At the selected upper limit position of the tee, the ball can be struck by a golf club, whereby the resilient tee will swing laterally under the impact blow before returning to its initial upright position. The ground surface edge surrounding the tee passage aperture carries a downturned arcuate lip, defining a generally funnel shape configuration. Hence, during lateral sway of the resilient tee after club impact, the tee body will smoothly conform to the arcuate shape of the lip, without contacting the platform bore edge, before returning to its original upright orientation. This in effect substantially reduces the occurrence of shearing damage about the rubber tee.

U.S. Pat. No. 3,511,507 issued in 1970 to Joseph A. GENTILUOMO discloses a device for repeatedly setting in automatic fashion a golf ball 21 in position over a ground surface 42, thus relieving the golfer from the task of repeatedly bending over to position a ball supporting tee after each ball stroke with a golf club. A golf ball is brought over a tee member automatically under gravity-borne forces, along inclined track 12. A flexible push-pull member 26 is endwisely anchored to the tee member 22. The push member 26 moves the tee member 22 and overlying golf ball 21 along a vertical axis, through an aperture 43 made in the overlying ground surface 42. At its upper limit position, the elastomeric tee member 22 projects upwardly beyond the horizontal plane of the ground surface, through the aperture 43. As the golfer strikes the ball, the tee 22 will usually swing violently against the edge of the aperture 43 in the ground surface, thus laterally shearing the tee member 22. Eventually, the tee member will become sufficiently damaged to require servicing. This will occur at regular, relatively short intervals.
U.S. Pat. No. 3,519,275 issued in 1938 to Meierjohan, and U.S. Pat. No. 2,127,282 issued in 1938 to Beckett, both teach means for step-feeding a series of golf ball, one at a time, to a loading chamber, where a tee member will reciprocate vertically. This step-feeding of the balls occurs through an inclined chute, whereby the balls are fed to the loading chamber under gravity-borne forces. Two gates are provided transversely of the inclined chute at a lengthwisely spaced interval. The first gate, proximal to the loading chamber, constitutes a releasable abutment stop for the lead ball, while the second gate, distal to the loading chamber, constitutes a releasable abutment stop for the ball following the lead ball. With the second gate closed, the first gate is opened, to allow the lead ball to fall into the loading chamber, and then the latter gate is closed; the second gate is then opened, to allow the next ball to take the place of the lead ball and come to abut against the first gate.

Golf ball step-feeding self-teeing device


The invention proposes a transmission system using a reference subcarrier to synchronize a local oscillator 104. The reference subcarrier can be placed at various locations of the band allotted to an operator. The external unit 1 of the reception device comprises frequency-wise selection means 107 which make it possible to select the synchronization subcarrier.

Radio transmission systems of point-multipoint type are known to the person skilled in the art by the initials MMDS (standing for Microwave Multipoint Distribution System), LMDS (standing for Local Multipoint Distribution System) and MVDS (standing for Multipoint Video Distribution System). These systems used for the broadcasting of programmes permit a return link for the subscriber terminals which allows the subscriber to interact with the programme received.
In Europe, provision has been made to implement a system of LMDS type which has 24 broadcasting channels (also referred to as downlinks) having a bandwidth of 33 MHz, and 25 return channels (or uplinks) having a bandwidth of 2 MHz, these channels being situated between 40.5 and 42.5 GHz (for further details on the apportioning of the channels, the person skilled in the art may consult the MPT-1560-RA standard). The system implemented must comply with the ETSI standard 301199 better known as DVB LMDS which among other things makes provision for an oscillator drift of plus or minus 200 kHz for the uplink, the drift being due mainly to climatic conditions. For further information about the systems, the person skilled in the art may refer for example to the patent application WO 2002/33855.
The bandwidth allotted for this type of application has been increased and currently corresponds to a frequency band lying between 40.5 and 45.5 GHz. Provision is also made to segment this band so as to apportion it among several operators.
FIG. 1 illustrates an exemplary distribution network for an operator deploying systems of this type. Base stations ST are deployed over a given zone. A base station ST covers one to four sectors A, B, C and D of finite size. Each sector uses a different frequency band and/or polarization so as to reduce the problems of interference between adjacent sectors.
FIG. 2 shows a configuration where a first operator has deployed three base stations ST and where a second operator has deployed his own base station ST′. A more considerable deployment of the two operators does not pose any problem of interference insofar as the frequencies allotted to the operators are completely different.
Such systems compete with other distribution networks such as satellite, cable or telephone. However, these systems may be used by a cable operator who wishes to extend his network without having to fully cable a given zone. For this purpose, operators desire that the decoders placed at subscribers premises be the same as for cable so as to avoid development overhead costs. Furthermore, it is desired that this type of network be able to serve as wireless bridge for a cable network.
FIG. 3 illustrates a distribution network system serving as relay for a cable network. A base station ST furnished with a transmitter, and possibly with a receiver, broadcasts information destined for a plurality of subscribers. On the subscriber side, an external unit 1 is connected to a cable network 2. A subscriber can connect up to the cable network 2 with the aid of an internal unit 3 which serves as interface to one or more user appliances 4. The external unit comprises an antenna and means for transposing the signals received into a frequency band compatible with the cable network 2 and means for transposing signals to be transmitted to the base station ST. The internal unit 3 is for example a TV decoder or a modem intended for the cable network 2. The user appliance 5 is for example a television, a telephone or a computer.
The production of an external unit requires compliance with transmission conditions related on the one hand to the radio path and on the other hand to the cable path. The DOCSIS standard which relates to cable networks permits a frequency drift of 32 kHz for the uplink and 30 kHz for the downlink. If this frequency drift is taken back to the radio frequency used, it is noted that the stability of the oscillators situated in the external unit 1 must be less than 1 in 1 million. But the external unit 1 is subjected to temperature and climate constraints which make it difficult and hence very expensive to achieve such stability.
A known solution consists in using a reference subcarrier sent by the base station so as to synchronize the external unit. Such a solution is described for example in U.S. Pat. No. 5,844,939. FIG. 4 represents a circuit corresponding to the type of circuit disclosed by the said patent. The signals received are transposed by a mixer 5. From among the signals transposed, a filter 6 selects a portion of band in which only the reference subcarrier should be situated. A phase/frequency comparator 7 compares the filtered frequency with a reference oscillator 8 and operates an oscillator 9 which provides the transposition frequency to the mixer 5. The frequency feedback control thus carried out corresponds to a phase-locked loop which makes it possible to achieve an absolute error in the frequency of the oscillator 9 which is equal to the error in the reference oscillator 8. Additionally, this technique compensates furthermore for the frequency drift of the base station. Moreover, if a return link uses one and the same oscillator to transpose the uplink and downlink, the error in the return link is also compensated.
Such a system may not be used in a cellular distribution network corresponding to FIGS. 1 and 2. The use of a fixed frequency for the entire distribution network would cause interference between the zones using one and the same frequency.

Transmission system with high frequency stability


The present application relates to peptides which bind to a target stain, phenol oxidizing enzyme-binding peptide complexes wherein the binding peptide is attached to the C-terminus of the phenol oxidizing enzyme or is inserted or substituted into the phenol oxidizing enzyme. In a preferred embodiment the phenol oxidizing enzyme is a laccase specifically Stachybotrys oxidase B and variants thereof. The invention provides expression vectors comprising the phenol oxidizing enzyme-binding peptide complex as well as host cells comprising the vectors.

Phenol oxidizing enzymes function by catalyzing redox reactions, i.e., the transfer of electrons from an electron donor (usually a phenolic compound) to molecular oxygen (which acts as an electron acceptor) which is reduced to H2O or H2O2. While being capable of using a wide variety of different phenolic compounds as electron donors, phenol oxidizing enzymes are very specific for molecular oxygen as the electron acceptor.
Phenol oxidizing enzymes can be utilized for a wide variety of applications, including in the detergent industry, the paper and pulp industry, the textile industry, and the food industry. Phenol oxidizing enzymes are specifically used for their color modifying ability for example for pulp and paper bleaching, for bleaching the color of stains on fabric, and for anti-dye transfer in detergent and textile applications. While the prior art does teach various phenol oxidizing enzymes useful in the above mentioned applications, there remains a need for new and more effective phenol oxidizing enzymes having stain bleaching ability, anti-dye transfer properties, and selective stain removal ability. It is a purpose of the present application to create phenol oxidizing enzyme-peptide complexes with increased binding ability to target stains when compared to the corresponding phenol oxidizing enzyme without the binding peptide. A further purpose of the present invention is to provide a phenol oxidizing enzyme-peptide complex having bleaching ability and particularly to provide a phenol oxidizing enzyme-peptide complex having an ability to remove stains obtained from carotenoid chromophore containing compounds such as those found in tomato and paprika.

This patent is subject to a terminal disclaimer.

Nucleic acids and expression vectors comprising carotenoid binding peptides


A solar powered ventilation system for regulating the interior temperature of a motorized vehicle and a method of controlling the same is provided. The vehicle includes a battery pack in electrical communication with at least one motor assembly that is selectively operable to propel the vehicle. The solar powered ventilation system includes a solar panel in electrical communication with a fan and the battery pack. The method includes: determining if sufficient solar load is available; if so, determining the current vehicle power mode; determining if the current battery pack temperature is greater than a threshold battery pack temperature if the vehicle is in “off” or “accessories on” mode; and commanding the solar powered ventilation system to modify the interior temperature of the vehicle to thereby decrease the temperature of the battery pack if the current battery pack temperature is greater than the threshold battery pack temperature.

Conventional automotive vehicles include a powertrain (sometimes referred to as "drivetrain") that is generally comprised of an engine in power flow communication with a final drive system (e.g., differential and wheels) via a multi-speed power transmission. Automobiles have traditionally been powered solely by a compression-ignited or spark-ignited internal combustion engine (ICE) because of its ready availability and relative cost. Hybrid type powertrains, on the other hand, generally employ one or more motor/generator units that operate individually or in concert with an internal combustion engine to propel the vehicle.
One premise behind hybrid-type vehicles is that alternative power is available to propel the vehicle, minimizing reliance on the engine for power, thereby increasing fuel economy. The hybrid powertrain takes advantage of both the ICE and motor/generator(s) to improve upon fuel economy and exhaust emissions. Since hybrid-type vehicles can derive their power from sources other than the engine, engines in hybrid-type vehicles typically operate at lower speeds more often than their traditional counterpart, and can be turned off while the vehicle is propelled by the alternative power source(s). Moreover, many hybrid vehicles use electrical regenerative braking to recharge an internal electrical power storage device.
Electric vehicles (EV) and hybrid electric vehicles (HEV) use battery packs, often comprised of several individual battery modules, to provide current to the motor/generators in order to propel the vehicle and operate vehicle accessories. It is well known that excessively hot temperatures may degrade overall battery performance and reduce battery operational life expectancy. For HEVs, hot temperatures can limit hybrid system performance, which can mean inconsistent operation and lower fuel economy. In addition, hybrid-electric vehicle batteries are generally larger and more complex than traditional Starting-Lighting-and-Ignition (SLI) batteries; thus, replacing HEV battery modules is costly.
When an automobile, hybrid or otherwise, is parked with the windows closed on a sunny day, the solar load can quickly heat both the passenger and trunk compartments well beyond the outside ambient temperature. On a typical 80 degrees Fahrenheit (° F.) sunny day, for example, inside vehicle temperatures can exceed 115° F. With a vehicle soaking in these conditions for a prolonged period of time, an operator that enters the vehicle may experience unbearably hot temperatures upon entering the vehicle. If full hybrid performance were then to be allowed, the batteries would heat even more under normal use, and reduced battery life would result. If hybrid battery usage was limited to protect battery life, hybrid performance would suffer.

Solar powered ventilation system for vehicle and method of operating the same


A method and device for manufacturing curing bladders (2), whereby a curing mold (3) defines, via a first (4) and second (5) half mold and an inner core (6), an inner molding chamber (7) and an outer injection chamber (34) communicating with the inner chamber (7) and consisting of a variable-volume chamber of an injection cylinder (59); the outer chamber (34) being fed with a mass (35) of heated uncured rubber which is injected into the inner chamber (7) with the mold (3) closed and, when cured, is extracted from the mold (3) by opening the inner chamber (7) and extracting the inner core (6).

Tire curing molds generally comprise an upper and lower half mold connectable in such a manner as to define a toroidal chamber for receiving a green tire for curing, inside which tire a bladder is inflated, usually in two successive stages, so that the outer surface of the tire adheres to the inner surface of the mold, and also for defining a toroidal passage for a high-temperature heat exchange fluid.
Due to the mechanical and thermal stresses to which they are subjected and the particular function they are called upon to perform, bladders of the aforementioned type demand an extremely high degree of precision and are mostly either handcrafted or injection molded.
A less expensive known method of producing such bladders is by what is known as "compression molding." According to this process, the bladders are produced using a curing mold comprising two half molds and, possibly, an inner core, which, when the mold is closed, define an inner toroidal chamber of exactly the same shape as the bladder being produced. Prior to closing the mold, a mass of uncured or green rubber is fed inside one of the half molds and, when the mold is closed, is subjected to relatively high pressure so as to force it to move and completely fill the inner chamber.
The above compression molding process involves a number of drawbacks, foremost of which are the need for relatively high-capacity presses for closing molds, and the overall inaccuracy of the finished product. The latter is due to variations in the shape and volume of the inner chamber during actual molding, which inaccuracy results in friction between the moving rubber and the walls of the inner chamber, thus preventing the rubber from faithfully reproducing the shape of the inner chamber when the mold is closed.

Method and device for manufacturing curing bladders


A method for assisting in a handover is provided that includes utilizing a link between a centralized access controller (CAC) and customer premises equipment (CPE) to facilitate a communication session involving a mobile station. The method also includes rejecting a handover from a public network to a cell controlled by the CAC after recognizing, in advance, that sufficient resources are unavailable for supporting a channel to be employed for the handover.

Unlicensed mobile access (UMA) technology provides access to global system for mobile (GSM) and general packet radio service (GPRS) mobile services over unlicensed spectrum technologies (e.g. Bluetooth, 802.11, etc.). By deploying UMA technology, service providers can enable subscribers to roam and to perform a handover between cellular networks and public and private unlicensed wireless networks using dual-mode mobile handsets. With UMA, subscribers receive a consistent user experience for their mobile voice and data services as they transition between networks.
Thus, UMA is a technology for delivering seamless mobility between GSM and wireless local area network (WLAN) access. GSM media and signaling can be tunneled over a broadband Internet protocol (IP) network. This allows converged circuit and packet services to be delivered to a converged terminal. For example, a user with a dual mode GSM UMA handset is able to receive GSM service (voice/short message service (SMS)/GPRS) when in a home environment without using the GSM radio network.
Key to the successful operation of a dual mode solution typified by UMA is the successful handover between a cell corresponding to the un-licensed mobile technology (Bluetooth, 802.11, etc) and a cell corresponding to the licensed frequencies of the public land mobile network (PLMN). A handover to a cell corresponding to unlicensed technology is generally requested by the client, e.g., based on received WLAN signal strength. Further, a trigger to handover from an unlicensed cell to a cell of a PLMN may be generated by the client, e.g., based on received WLAN signal strength, or by the network, e.g., based on metrics derived from the up-link packets. In a dual mode environment, such a handover process is fraught with additional problems and deficiencies compared to the pure cellular handover procedure. Augmenting, optimizing, or enhancing this dual mode handover process presents a significant obstacle for network operators, system designers, and component manufacturers.

System and method for providing enhanced handover performance


The disclosure discloses a cartoonlization processing method for an image, and relates to a field of computational vision, image processing, face recognition, deep learning technologies. The method includes: performing skin color recognition on a facial image to be processed to determine a target skin color of a face in the facial image; processing the facial image by utilizing any cartoonizing model in a cartoonizing model set to obtain a reference cartoonized image corresponding to the facial image in a case that the cartoonizing model set does not contain a cartoonizing model corresponding to the target skin color; determining a pixel adjustment parameter based on the target skin color and a reference skin color corresponding to the any cartoonizing model; and adjusting a pixel value of each pixel point in the reference cartoonized image based on the pixel adjustment parameter, to obtain a target cartoonized image corresponding to the facial image.

Portrait cartoonlization is a commonly used method for image style transformation.
In the related art, current training data of cartoonized portraits are mostly light skin. Therefore, when face style transformation processing is performed by employing a model generated by training, a generated cartoonized face is also a light skin color. That is, a current cartoonlization processing model may only process a user with a light skin color.

Cartoonlization processing method for image, electronic device, and storage medium

BEIJING BAIDU NETCOM SCIENCE AND TECHNOLOGY CO., LTD.


Examples are disclosed herein that relate to a cooking system having multiple heating elements for heating a cooking surface. One example provides a cooking system, comprising a continuous cooking surface comprising a plurality of individually controllable heating zones, and for each heating zone, a temperature sensor configured to detect a temperature for the heating zone separately from the temperatures of other heating zones, and a heating element disposed beneath the heating zone and configured to provide heat to the heating zone. The cooking system further comprises a controller configured to individually control the heating element of each heating zone.

Cooking systems, such as grills, may utilize heating elements to heat a cooking surface for cooking food. Some cooking systems may utilize a continuous cooking surface on which multiple items of food may be cooked at the same time. With such systems, a cook may move food to a center of a heated area of the cooking surface for cooking, and then move the food to the side for maintaining warmth prior to serving.

Cooking system with multiple heating elements


An one-transistor-one-bit (1T1b) Flash-based EEPROM cell is provided along with improved key operation schemes including applying a negative word line voltage and a reduced bit line voltage for perform erase operation, which drastically reduces the high voltage stress on each cell for enhancing the Program/Erase cycles while reducing cell size. An array made by the 1T1b Flash-based EEPROM cells can be operated with Half-page or Full-page divided programming and pre-charging period for each program cycle. Utilizing PGM buffer made of Vdd devices in the cell array further save silicon area. Additionally, a two-transistor-two-bit (2T2b) EEPROM cell derived from the 1T1b cell is disclosed with additional cell size reduction but with the operation of program and erase the same as that for the 1T1b cells with benefits of no process change but much enhanced storage density, superior Program/Erase endurance cycle, and capability for operating in high temperature environment.

The present invention relates generally to nonvolatile memory cell structure, array structure, and operation. More particularly, the present invention relates to improved 1T1b and 2T2b flash-based Electrical Erasable Programmable Read Only Memory (EEPROM) data-oriented cell structures, array structures, and operations.
Nonvolatile memory is well known in the art. The different types of nonvolatile memory that employ a charge retention mechanism include Read-Only-Memory (ROM), Electrically Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), NOR Flash Memory, and NAND Flash Memory. The charge retention mechanism may be charge storage, as in a floating gate memory cell, a so-called Flash-based cell.
The NAND Flash memory cell design has several advantages. Firstly, its cell size is highly scalable and is able to have a cell size that is a factor of approximately four times (4×) larger than the minimum feature size (λ2) of the manufacturing technology. This has held in technologies with feature sizes from 0.25 μm down to 20 nm. This is the smallest nonvolatile memory cell when compared to other nonvolatile cell types. Secondly, NAND Flash memory cell design uses a low-current Fowler-Nordheim tunneling phenomena for both program and erase operations. The Fowler-Nordheim Tunneling allows the program and erase operations to be performed in relatively larger memory unit sizes and a faster speed. The Fowler-Nordheim erase operation is typically performed in a unit of a large sector with sizes ranging from 512 Kb to 2 Mb and 1 ms fast erase time in current specifications. The Fowler-Nordheim program is performed in a unit of a large page size varying from 512 B to 2 KB with a fast speed of 200 us typically in the current specifications.
By contrast, NOR Flash memory device is formed of an array of less-compact charge retaining transistors that are fundamentally connected in parallel, rather than serially in a NAND Flash memory array. Like a NAND Flash memory charge storage transistor, the NOR Flash memory charge storage transistor is also made of the stack-gate cell structure for the floating gate transistors. Each NOR Flash memory cell has a contact metallurgy at each drain and source node to connect each NOR Flash memory cell to the common bit lines and source lines. The cell size for the NOR Flash memory, therefore, is larger than the NAND Flash memory.
As is known in the art, an EEPROM memory array is structured to be a byte-wise erasable structure as compared to block-wise erasable NAND flash memory arrays. EEPROM memory array requires more die area than a NAND flash memory of the same capacity because each EEPROM memory cell pitch is much larger. Conversely, in a NAND flash memory array, the erase circuits are shared by large blocks of cells (often 512×8 bits).
Typically, the three types of nonvolatile memory structures are targeted three different storage markets and technologies are not compatible. The NAND Flash memory has been extensively used as a slow-serial-read, extreme high-density, block-alterable memory array for huge data storage. Conversely, the NOR Flash memory is used as a fast-random-read medium-high-density, sector-alterable memory array for program code storage. Unlike the NAND and NOR Flash memories, the EEPROM memory is broadly used as a fast-random-read, byte-alterable memory array for small data storage.
An EEPROM memory array design has certain disadvantages. The first disadvantage is a large cell size that is the largest among the nonvolatile memory structures. Currently, the EEPROM manufacturing technology process, in real production, is about four generations behind NOR Flash memory manufacturing technology and seven generations behind the NAND Flash memory manufacturing technology. The cell size will be relatively larger as technology migrates below 0.15 μm. In the manufacturing process node above and including 0.18 μm, the EEPROM cell has been realized with a cell area size of about 90 times the minimum feature size (λ2) but will have an area larger than 100 times the minimum feature size (λ2) when migrating below 0.15 μm.
The second disadvantage of the EEPROM memory array design is that a very high bit line programming voltage is required. The programming voltage is as high as 16 V in the cell channel region between its drain and source nodes for performing proper Fowler-Nordheim Program operation. As a result, the EEPROM memory array program operation is the most critical one as compared to NAND Flash memory array and NOR Flash memory array. The very high programming voltage requirement in cell's channel region between the drain and source prevents the EEPROM memory cell area from further scaling below the 0.13 μm minimum feature size. During a higher density page program operation, higher number of bit lines and one word line is charged to the very high programming voltage of 16V in the worst-case. The page size varies from 8 bytes in low-density 2 kb part to 256 Bytes for high-density parts such as 1-2 Mb with page program speed of around 1 ms.
One major advantage of the EEPROM memory design lies in the number of Program and Erase (P/E) endurance cycles. Currently a two-transistor FLOTOX-based EEPROM memory array can endure at least 1 million program-and-erase (P/E) cycles in units of byte or page. Therefore, the two-transistor EEPROM memory array is the best nonvolatile storage memory for those extremely high frequency changing rates of byte-alterable or page-alterable data applications. For example, a two floating gate tunnel oxide (FLOTOX) based EEPROM memory design has been developed for the market need of byte-alterable data-oriented application, keeping the advantage of 1M P/E endurance of traditional EEPROM memory as well as features of fast write speed and relative simple manufacture process. A recent trend for the byte-alterable EEPROM application demands a low-cost high-density storage solution that allows the scaling below 90 nm at higher temperature automotive environment. The drawback of the 2T FLOTOX-based EEPROM cell is its large cell size (for storing one bit) of 90λ2 and high bit line voltage level of about 16 V which limits its channel length scaling. Alternatively, an one floating gate transistor Flash-based EEPROM cell is proposed to reduce the cell size (for storing one bit) to about one-third of that, down to 30λ2. But current operation scheme of the corresponding 1T1b EEPROM cell array in the prior art still requires bit line inhibit voltage level as high as 16 V. Thus the stress to the source line select transistors and bit line select transistors is very high, imposing a big disadvantage of inferior of P/E endurance cycle of just about 300K. Therefore, improved operation schemes as well as new memory array architectures are needed and become objectives of the present invention.

1T1b and 2T2b flash-based, data-oriented EEPROM design


An on-chip system receives raw positive and negative voltages from voltage pumps and provides CMOS-compatible bandgap-type positive and negative reference voltages from which regulated positive and negative Vpp and Vpn voltages are generated. A bitline (BL) regulator and a sourceline (SL) regulator receive Vpp and generate a plurality of BL voltages and SL voltages, and use feedback to compare potential at selected BL nodes and SL nodes to a reference potential using a multi-stage differential input differential output comparator. Reference voltages used to create BL and SL potentials may be varied automatically as a function of addressed cell locations to compensate for ohmic losses associated with different cell array positions. The system includes positive and negative wordline (WL) regulators that each use feedback from selected WL nodes. The system further includes a WL detector and magnitude detector for Vdd and Vpp, and can accommodate multiple level memory (MLC) cells by slewing reference voltages used to output regulated voltages. The system preferably is fabricated on the same IC chip as the address logic and memory array using the regulated potentials.

Flash electrically programmable read only memories ("EPROMs") and flash electrically erasable and programmable read only memories ("EEPROMs") are solid state devices that can persistently store digital data. As shown by FIG. 1, an EPROM-type flash cell 10 typically has a metal-on-silicon ("MOS") structure that includes a substrate 12, source and drain regions 14, 16, a floating gate 18 overlying MOS channel region 20 but separated therefrom by a thin layer region 22 of oxide 24. A control gate 26 is formed overlying floating gate 18. For a flash EPROM, it is necessary to surround the source region with a lightly doped region 15 of like-conductivity type dopant. The substrate or bulk 12 is tied to a potential Vbb that typically is ground.
For the NMOS device depicted, substrate 12 is doped with P-type impurities, and the source and drain regions are doped with N-type impurities. For a flash EPROM, N+ source region 14 is surrounded by an N- region 15. The N- region 15 is included to protect the source junction from the large source-floating gate electric field used to electrically erase the cell. This N- region helps reduce electric field magnitude between source nodes and the first polysilicon layer (not shown) during erase operations.
Of course a PMOS device may be formed by substituting an N-type substrate, and P-type source, drain regions. Generally, NMOS devices are preferred to PMOS devices in that the majority carriers in NMOS devices, electrons, have 2.5 times the mobility of the majority carriers, holes, in PMOS devices, and thus can operate more rapidly. Although an EPROM-type flash cell is depicted, it is to be understood that the present invention may also be used with EPROM, or EEPROM type memory as well.
A Vcg voltage coupled to control gate 26 can affect charge stored on floating gate 18, which charge affects the Vt threshold voltage of MOS device 10. The magnitude of charge on the floating gate controls the minimum (or Vt) voltage Vcg that will turn-on device 10, causing drain-source current to flow across the channel region 20. Device 10 is programmed to one of two states by accelerating electrons from substrate channel region 20 through the thin gate dielectric 22 region onto floating gate 18.
The state of device 10, e.g., how much charge is stored on floating gate 18, is read by coupling an operating voltage Vds across source and drain regions 14, 16. The drain-source current Ids is then read to determine whether data stored in the device is a logic level one or zero for a given control voltage level Vcg. The two logic states may be differentiated by sensing relative current levels, e.g., perhaps 100 .mu.A versus 10 .mu.A.
Two mechanisms are in common use to program a flash EPROM (or to erase a flash EEPROM, whose definitions of erasing and programming are opposite), namely channel-hot-electron ("CHE" ) injection, and Fowler-Nordheim ("FN") tunnelling. Commonly, EPROM-flash devices use FN-erase mode and CHE-program mode operations, which combination is sometimes referred to as ETOX, for EPROM tunnel oxide technology. On the other hand, EEPROM-flash devices commonly use FN-erase mode, and FN-program mode operations.
Table 1 summarizes the application of FN and CHE modes, as well as typical cell voltages for gate, source and drain nodes. As described later herein, the present invention is directed to a medium high voltage pump that can increase a lower Vdd voltage to approximately 5 VDC at high current for coupling to the source or drain of cells to be erased or programmed.
TABLE 1 ______________________________________ ERASE PROGRAM ______________________________________ EPROM- FN: CHE: flash G = -8 V, S = 5 V, D = float G = 8 V, S = 0 V, D = 5 V EEPROM- FN: FN: flash G = 15 V, S = 0 V, D = 0 V G = -8 V, S = 5 V, D = float ______________________________________
Thus, for the EPROM-flash cell depicted in FIG. 1, channel-hot-electron injection is used to program the cell to an off-state in read mode. Using CHE technology, it is necessary to apply a positive high voltage Vcg, e.g., perhaps +8 VDC to +10 VDC to control gate 26, while applying perhaps +5 VDC to drain 16, and 0 VDC to source 14. As hot electrons are accelerated and travel from source to drain, the electric field created by the high Vgs and Vds voltages can pull some hot electrons from the drain to the floating gate. (No electrons will be pulled to the floating gate from the source, which is at ground potential.) When using CHE injection, the drain-source channel current will be approximately 0.5 mA/cell.
Using FN technology, an EPROM-flash cell is erased by coupling perhaps -8 VDC to the control gate 26, +5 VDC to the source, and allowing the drain to float. FN-mode erasing can be accomplished with a tunnel current of approximately 10 nA/cell. (Although one can erase an EPROM-flash cell by providing positive high voltage to the source and grounding the control gate, so doing increases source region junction leak current, and increases hot-hole injection at the source region.)
To program an EEPROM-flash cell using FN technology requires applying approximately -8 VDC to control gate 26, applying +5 VDC to source 14, and floating drain 16. The negative Vcg high voltage and Vs produce a large tunnel electric field that can push electrons from the floating gate 18 to the source 14. (No electrons are pulled out of the floating gate to the drain, as the floating drain will not generate a large electric field.) Unfortunately, this causes hole trapping, and degrades the storage capability and endurance of the memory cell. To erase an EEPROM cell using FN technology, approximately +12 VDC is applied to control gate 26, while drain 16 and source 14 are grounded. As was the case for an EPROM-flash cell, FN erasing can be accomplished with a tunnel current of approximately 10 nA/cell.
Typically the circuitry with which memory cells 10 are used is powered by a single low voltage power supply, a 3.3 VDC battery for example, although batteries ranging from perhaps 1.2 VDC to 5 VDC or higher may instead be used. Positive and negative high voltage pump circuits are commonly used to generate the .+-.12 V (V.sub.pp, V.sub.Pn) or so high voltage necessary to program and erase memory cells from a single lower voltage power supply. In the prior art, separate medium voltage pump circuits are used to generate the +5 V or so (V.sub.Pm) that must be supplied at relatively higher current levels in the few mA range. Usually the source shares a pump circuit with the drain, as the voltages required are the same but are used during different operation modes.
From the foregoing discussions of CHE and FN mechanisms, it will be appreciated that the number of cells that can be erased or programmed in parallel, e.g., simultaneously (or in a "flash"), will often be determined by the pump circuit current output characteristics. For example, if a medium voltage V.sub.Pm pump circuit can provide an average 8 mA output current drain-source, 16 bits can be programmed simultaneously, whereas 100 Kbytes may be erased simultaneously.
Understandably, in designing pump circuits it is important that sufficient program or erase current be provided to at least meet the cell requirements to maintain erasing and programming efficiency. In a system with a 5 VDC power supply (Vdd=5 VDC), 32-bit programming can be achieved, but if Vdd=3 VDC, only 8-bit programming can presently be achieved. It simply is difficult in ETOX systems to provide sufficient 0.5 mA/cell program current at 5 VDC drain voltage when Vdd is less than about 3 VDC. Further, it is necessary to pump a 3 VDC Vdd up to 5 VDC, preferably using an on-chip pump circuit, to even meet the 0.5 mA/cell programming requirements. If an externally created 5 VDC Vdd is available, it may of course provide multiple byte-programming, e.g., four-byte, without recourse to an on-chip high current pump. At present, FN-programming dominates sub-3 VDC Vdd systems, whereas CHE-programming dominates 5 VDC Vdd flash memory systems.
However, in some systems an external source of Vpp may be provided, in which case there is no need to provide an on-chip positive voltage Vpp pump. The presence of an external Vpp supply can result in faster and more efficient erase and program mode operations. Although modern flash memory systems can be operated from a variety of power supplies and power supply values, such systems do not include an on-chip Vdd and Vpp voltage detector. For example, such a Vdd/Vpp detector could be used to disable the Vpp pump circuitry of a generic on-chip system that included a positive voltage Vpp pump, thus conserving operating power.
As shown in FIG. 2, it is common to form an integrated circuit ("IC") 100 that includes a plurality of cells 10 that are arrayed in addressable rows and columns that define a storage array 110. Address logic 120 permits accessing a specific cell in such an array. For example, during a program/read or erase operation, a given cell 10 may be accessed by applying the proper Vgs, Vd, Vs potentials to all cells in a column containing the addressed cell, and to the row containing the addressed cell.
Commonly, a horizontal row of cells having their control gates tied-together defined a word line ("WL"), whereas a vertical column of cells having their drains tied-together define a bit line ("BL"). Source leads in a block of cells are tired-together to define a source line ("SL"). Changing the WL, BL, SL potential for a selected group of cells enables those cells to be programmed or erased or verified. For ease of illustration, address logic 120 is shown as having a single output lead, but in practice there will be multiple output leads, including leads for Vgs, Vd, and Vs.
In typical arrays, the gate node of cells 10 are coupled to a WL by a polysilicon conductor, as zero DC current will be carried by the WL. The cell drain nodes are coupled to a typically metal BL, and the source nodes are coupled to a SL, typically via an N+ diffusion. Whereas the WL carries zero DC current, the BL may carry a total 5 mA DC if eight cells in the same WL are simultaneously programmed. Further, a SL may carry upwards of 5 mA DC current if 64 Kbytes of cells are collectively erased simultaneously.
The WLs are coupled to a row-selected device by an row decoder (or X-decoder), which for ease of illustration may be assumed to be associated with address logic unit 120 in FIG. 2. The BLs are coupled to a column-selected device driven by a column decoder (or Y-decoder), which is assumed to be associated with address logic 120. The SLs are coupled to source control circuit, assumed to be associated with address logic unit 120. If array 120 includes 1 Mbit of flash memory cells, there will be 1,024 WLs and 1,024 BLs configured in horizontal rows and vertical columns.
In FIG. 2, IC 100 preferably operates from a single low voltage power supply Vdd, perhaps a 5 VDC battery, although the trend has been toward Vdd values of 3.3 VDC or 2.5 VDC, with a goal of perhaps 1.2 VDC.
To generate the high voltage necessary to program or erase the various cells from a lower voltage Vdd supply, voltage pump circuits are used. IC 100 will commonly include a positive high voltage pump circuit 130 that outputs a high positive potential V.sub.pp, and a negative high voltage pump circuit 140 that outputs a high negative potential V.sub.Pn. A medium voltage circuit 145 is also used to output a medium high voltage V.sub.Pm, perhaps +5 V at relatively higher current levels, e.g., .apprxeq.5 mA, than are associated with voltages V.sub.pp and V.sub.Pn.
Because the various pump output voltages are not especially well regulated, voltage regulator circuits 132, 142, 147 are also provided. Typically these circuits employ a constant voltage reference such as a bandgap generator. The output voltages from the voltage regulators will be logically presented to selected groups of cells to provide WL, BL, SL potentials as required by the various modes of operation, as exemplified by the values shown in TABLE 1.
Unfortunately, although regulators 132, 142, 147 may do an acceptable job of regulating voltage at the output ports of the voltage regulators, the WL, BL, SL voltages may not be especially well regulated where the voltages are needed: at the gate, drain, and source nodes of the selected memory cells. Such feedback as is used by prior art regulators 132, 142, 147 is typically internal to regulator itself, e.g., a scaled proportion of the voltage at the output port of the regulator is compared to the reference voltage and the output port voltage is adjusted accordingly. However, feedback from the nodes whereat the voltage should be tightly regulated (e.g., the cell nodes) is not employed.
Many factors contribute to variations in WL, BL, and SL potentials as they appear at the nodes of the selected cells. In practice, WL regulation is less troublesome than BL and SL regulation. Because the WL is coupled to the control gate nodes of selected memory cells, no DC current is drawn. However, WL voltage can vary in verification mode due to device body-effect coupling at the X-decoder. The result is that WL voltage varies due to threshold Vt shifts. In contrast to the minimal WL current requirements, BL and SL may each carry perhaps 5 mA of DC current. Ohmic I.times.R type losses in the BL and SL conductive lines from the regulator outputs to the selected array cell nodes can degrade quality of the voltage regulation, and thus reliability of a program or erase operation.
The voltage-changing effects of parasitic active resistances and column select devices can vary from one select path to another, further causing variations in the voltages actually seen by the selected cells. Temperature variations and fabrication process variations can result in some individual memory cells 10 being erased or programmed more effectively within a given amount of time by the WL, BL, SL potentials seen by the cells, than other cells. Essentially, the erase and program currents required can vary from cell to cell. Further, a cell's program and erase Vt can dynamically vary over time during program and erase operations, which will affect current in that cell.
The above-enumerated factors and other uncontrollable effects contribute to make the voltages actually seen at the drain and source nodes of selected memory cells difficult to reliably predict. Consequently, program and erase operations can be unduly stressful to the memory array, and efficiency of such operations will be degraded, to the detriment of product life of the memory system. Thus, it is common to provide a verify mode to confirm effectiveness of an erase or program operation.
For example, in program verifying mode, potential for the selected WL may be about +2 V for a low threshold voltage ("Vt") memory cell, and perhaps +6 V for a high Vt memory cell. In program verifying mode, the BL will be about +1 V, and the SL will be grounded (for 5 V Vdd operation).
In erase verifying mode, the selected WL is set to +3 V to verify Vt for the cell after erasure, while the WL is set to +1 V to verify cell Vt following erase repair operation.
Table 2 below recapitulates the various BL, WL, and SL potentials commonly encountered, although larger magnitude potentials may also be found.
TABLE 2 ______________________________________ BL (drain) WL (gate) SL (source) ______________________________________ Erase: floating -8 V +5 V Program: +5 V +8 V 0 V Erase verify: +1 V +3 V 0 V Reading: +1 V +Vdd 0 V Program verify: +1 V +6.5 V 0 V Erase repair: +5 V >+1 V 0 V ______________________________________
However, the efficiency of program and erase and verify mode operations is dependent upon the accuracy with which the various programming, erasing, or verifying voltages can be maintained, as seen by the selected cell gate, drain, and source leads. Maintaining a well regulated voltage is especially important for read and verify modes. However, as noted, prior art voltage regulation schemes as shown in FIG. 2 do not actually regulate the WL, BL, SL potentials at the memory cell nodes. Accurately regulating WL, BL, SL potentials becomes more critical as MOS device sizes become smaller. For example, in the past, 1 .mu.m MOS devices could tolerate perhaps .+-.10% tolerance or so on the magnitude of these voltages. But for modern 0.3 .mu.m MOS devices, the same 10% tolerance, especially when combined with other variations, can push the MOS devices beyond acceptable tolerances. Thus, it is especially important to regulate WL, BL, and SL potentials as device sizes continue to shrink.
Understandably, applying too much potential to a WL, BL, SL can stress if not destroy memory cells. On the other hand, under potential can result in false reads and incomplete erasures. Thus, efficient programming, erasing, and verifying a memory array requires tightly control WL, BL, and SL potentials, at the cell nodes coupled to these lines.
IC 100 also includes a phase generator circuit 125 that outputs a plurality of non-overlapping different phase pulse trains (here denoted .phi.1, .phi.2, .phi.3, .phi.4) that drive the positive and negative pump circuits 130, 140, 145.
In typical flash memory applications, an erase time of 1 second is regardless of the number of flash memory cells, e.g., cells 10, being erased. However, in practice, the magnitude of the erase current can limit the number of cells or memory bits that can be erased simultaneously. A typical flash memory cell, e.g., cell 10, may require about 10 nA during erase mode operation, and about 0.5 mA during program mode operation. Stated differently, programming current required by a typical memory cell exceeds erase current by about 50,000:1. Because of this current limitation, it is common to block erase 64 Kbits simultaneously, while programming is directed to one byte (e.g., 8 bits) at a time. Typically, to program a byte requires about 0.5 mA/cell.times.8 cells.apprxeq.4 mA at about 5 VDC. Approximately the same current is required to erase a block of 64 KBytes, e.g., 10 nA/cell.times.64 KByte cells.apprxeq.5 mA. Since simultaneous block erase and byte programming would not occur, a single medium voltage pump circuit capable of approximately 5 mA output at V.sub.Pm can suffice.
It will now be appreciated reliable program, erase, and verify operations require tightly regulate WL, BL, SL potentials at the selected memory cell gates, drains, and sources. However from the foregoing it is apparent that prior art approaches have regulated these potentials tightly at the output port of the various voltage regulators, without accounting for variations in these regulated potentials downstream from the regulator output ports.
However, such regulation as is carried out in the prior art leaves much to be desired. For example, Tedrow et al. in U.S. Pat. No. 5,546,042 discloses a voltage regulator for flash memory in which a resistor divider scales-down the regulated voltage to a level appropriate for a voltage comparator. Unfortunately, the resistor divider draws DC current, which can not readily be spared from the pump circuit whose voltage is being regulated. Further, the divider attenuates changes in the regulated voltage, degrading gain of the regulation system such that a precise voltage at the output of the voltage comparator does not ensure a precise output voltage. What would be more desirable is a regulation method that did not draw DC current, and that could pass to a voltage comparator input essentially all (rather than a fraction of) change in the pump voltage to be regulated.
Although U.S. Pat. No. 5,291,446 to Van Buskirk et al. discloses regulation of a positive potential using capacitive voltage division, Van Buskirk's voltage division also down-scales the error or delta component on the voltage being divided, thus reducing overall regulation efficiency. Further, error occurs in Van Buskirk's capacitor division due to leakage currents. Buskirk also generates a first program mode output and a second program-verify mode output, by changing the capacitor-divide ratio. This approach requires an extra capacitor, and becomes less efficient if multiple output voltage levels are required. What would be more useful would be a regulator in which programmable references create programmable output potentials.
U.S. Pat. No. 4,858,186 to Jungroth discloses an open loop circuit for providing a load for charging an EPROM cell. Jungroth does not use a comparator to detect differences between a reference and the desired regulated voltage, but instead directly applies a fixed control voltage to a source follower whose output is to control selected BL voltage. Unfortunately, if BL potential is too low, Jungroth cannot compensate. Jungroth attempts to use a reference column to generate a fixed control voltage. An assumption is made that the reference column should mimic the selected BL, and that by setting reference column voltage and current to desired values, the selected BL should follow suit. However this scheme is deficient because the circuit and layout of the reference column differ substantially from the BL; for example, the reference column has no memory cell (whose channel current can vary 10:1 during programming, to significantly alter BL potential). As a result, relatively poor BL voltage regulation is provided by this prior art approach.
In summary, there is a need for a system of regulation of WL, BL, and SL potentials that provides the necessary regulation where it is needed, at the gate, drain, and source leads of the selected memory cells. Preferably the voltages delivered at these nodes should be regulated so as to be substantially independent of process and fabrication variations, ambient temperature variations, and Vcc or Vdd power supply variations. In achieving these design goals, preferably a measure of the desired voltage at the selected cell nodes should be taken and fedback to the appropriate voltage regulator.
Since an array can include thousands of BLs and SLs, a mechanism for detecting and regulating only the cell node potentials for the selected BLs and SLs should be implemented to save IC chip area required by the implementation. Because modern flash memory systems can be operated from a variety of power sources, there is a need for a system that includes an on-chip Vdd and Vpp voltage detector. On-chip detection of Vdd and Vpp can help fine-tune performance of on-chip regulators. For example, amplitude of the phase generated clock pulses may vary substantially with Vdd power supply variation, and the ability to detect Vdd and fine-tune on-chip pump voltages accordingly can be advantageous. Further, on-chip detection of Vdd and Vpp may be used to disable on-chip voltage pumps, e.g., a Vpp pump, that need not be operated because the system environment provides the necessary magnitude of Vpp. An on-chip Vpp detector could sense the presence of an external source of Vpp and provide a control signal disabling an on-chip Vpp voltage pump.
The present invention provides such a voltage regulation system.

Node-precise voltage regulation for a MOS memory system


Briefly, in accordance with one embodiment of the invention, a technique and device are described that may allow a user to determine if the engine in a classic or antique automobile is original. The common characteristics of the factory applied markings of known original engines may be identified. All or a portion of an unknown engine may then be compared to those common characteristics to determine if the unknown engine was likely stamped using the same stamping tool as the known original engines.

From 1953 through 1982, Chevrolet™ manufactured its Corvette™ automobiles in its manufacturing facility in St. Louis, Mo. (Chevrolet™ and Corvette™ are trademarks of General Motors Corporation, Detroit, Mich.). Beginning in 1955, Chevrolet™ incorporated a plan to address potential quality issues that might arise during the manufacturing process of particular engine options. Consequently, Chevrolet implemented the practice of stamping information on each engine manufactured. This information was individually hand stamped into each engine using a hammer and a stamping device 1 like the one illustrated in FIG. 1.
As shown in FIG. 2A, the engine code information was stamped onto an engine pad 10 of each engine 100. The use of these stamped engine codes began in both of the Chevrolet™ Corvette's™ V8 engine assembly plants beginning in 1955. One plant was located in Flint, Mich., while the other was in Tonawanda, N.Y. Both plants stamped a code relating to the specific manufactured application of the engine. In addition to engine assembly information stamped at Flint and Tonawanda, the car-line plant in St. Louis, Mo., Chevrolet™ stamped a derivative of the vehicle identification number (VIN), again using a hammer and a stamping device like the one shown in FIG. 1.
For example, in 1967 the Tonawanda factory built many V8 engines including Corvette™ specific 427 cubic inch versions. If one of these engines was to be assembled in the 390 horse power (hp) configuration for use in a car that had a 4-speed transmission and smog equipment, an assembly line operator at the factory would stamp the assembly code into engine pad 10 of engine 100 including a suffix of "IM" using stamping device 1. (see arrow 5 of FIG. 2A) This would confirm to workers in the Tonawanda or St. Louis engine manufacturing facility all of the specific sub-components needed for that engine assembly. The stamped assembly code was used to identify the specific application of every engine manufactured. Therefore, versions specific to Corvette™ would have its own suffix code designation.
Thus, Chevrolet™ used the engine stampings as a way to communicate assembly information as the engine and automobile was being built. Once the automobile left the factory, this information had served its intended purpose and was no longer used by Chevrolet™.
Today the Chevrolet™ Corvettes™ manufactured in the 1960's and 1970's are considered by many to be collector items. Like many collector items, the value of a piece depends, often in great part, on its condition and its originality. Given the rarity and popularity of these automobiles, many of these automobiles have become very expensive which, in turn, has created a motivation for some to forge or alter some automobiles in an effort to increase their value. Thus, there is a continuing need to be able to determine if the engine in an automobile is original or a reproduction.

Techniques for verifying the authenticity of the steel stamped information on an engine pad of a classic automobile and apparatus therefor


An illuminated glove assembly for providing illumination to a user, wherein the illuminated glove assembly has a glove with a hand portion and an illumination data controller. The hand portion includes a back portion, fingers, a wrist end and a palm portion. The back portion includes a first pocket with a first opening proximate the fingers and a first terminal end proximate the wrist end. The illumination data controller is configured for selective mounting in the first pocket. The illumination data controller has a housing with a front face, a top surface, a length, a width and a thickness. The front face includes a light source from which light emanates and the width is greater than the thickness.

The preferred invention relates generally to illuminated gloves and, more particularly, to an illuminated gloves assembly that illuminates a wearer's path while worn when ambient light is minimal. The preferred illuminated gloves may be particularly adapted for runners, cyclists, athletes, outdoorsmen, survivalists, everyday use or for any situation where the user or wearer desires light projecting from their hands. The preferred glove assembly includes an illuminated data controller that provides illumination, sensors and wireless communication capabilities.
Gloves that provide a light source to allow a wearer to accomplish a variety of tasks are known. Generally, some such gloves are configured to have a reflective strip or a light diffuser that makes the wearer more visible in conditions where ambient light is poor, but do not provide sufficient light to aid the wearer's vision. Alternately, other gloves are configured to house a light source which illuminates the area immediately in front of the wearer's hand or fingers to aid in performing tasks that require the use of each of the wearer's fingers and/or hands, but similarly do not provide sufficient light to illuminate a great enough area to enable a runner to see more than a very short distance in front of him or her while ambient light is low. Known gloves are also configured to display particular symbols, are relatively cumbersome and lack other features that are desired by users for illuminating a desired area or accommodating various additional accessories while providing a low profile, comfortable and efficient operation and appearance. Such prior art gloves also lack a convenient way to remove and replace the light for use of the gloves without the light and to readily replace the battery associated with the light. These prior art gloves further lack storage pockets or storage features for retaining the wearers items, such as keys, currency, communication devices, energy packs, the light and other relatively modest sized personal items of the user.
Alternative prior art illumination devices also include flashlights or headlamps that must be carried consistently by hand or require the user to turn their head to project the light in desired directions, respectively. Prior art vests may also incorporate lights or lights may be clipped onto a user's clothing, but such lights are also difficult to direct without awkward body movements and such light may be lost and misplaced. Further, flashlights or other handheld lights require occupation of one of the user's hands, thereby reducing the ability of the user to use their occupied hand to complete desired tasks.
It is therefore, desirable to design, develop, manufacture and distribute a glove that provides sufficient light in front of the wearer to enable him or her to see his or her path in conditions with minimal ambient light while simultaneously not restricting the wearer's hands and/or fingers and including adaptability for various accessories or carrying relatively small items and safety features (alarms, et al.). Illuminated gloves of the preferred invention replace clunky and uncomfortable head lamps, light-up vests, clip-on lights, and other handheld lights that limit the use of your hands.