A system and apparatus for generating an extended finite state machine (EFSM) from a specification expressed as a set of data relationships. The specification is written in a specification language designed for the purpose, and is parsed in a conventional fashion. The parsed specification is used as input to the method of the invention, which comprises routines for transforming it into an EFSM including states and transitions. The EFSM thus generated is used as input to a traversal procedure, for ultimately generating validation tests to verify the operation of an implementation of the specification, with one such test being generated for each path traversed through the EFSM. The traversal of the EFSM may be carried out in a conventional fashion or by using applicant's EFSM traversal method. The EFSM's transitions represent functions and test information, and the states represent the status of the EFSM at particular points, given the traversal of a particular path through the EFSM, i.e. the history of execution of the EFSM. Annotations are generated and correlated with the transitions, the annotations comprising value assignments, variable value partitions, input or other events, constraints on the execution of the EFSM, predicates acting as prerequisites for the traversal of their associated transitions, and test statements that will act to verify operation of the implementation when the validation tests are executed. Diagnostic function strings are generated as annotations to transitions, for outputting diagnostic statements reflecting the success or failure of the implementation upon execution of the validation tests.

This invention is directed to an apparatus and method for automatic generation extended finite state machine architectures from software specifications.
In the course of designing a new computer application or operating system, typically one first writes a specification for the application. Such a specification may be tested by automatically generated validation tests, using techniques described below. An important stage in the generation of the validation tests is the transformation of the specification into a finite state machine (FSM), which for a complex specification will typically be an extended finite state machine (EFSM), often in a multi-EFSM architecture (EFSMA) with linking among the EFSMs to form a multiple layer model. It is these EFSMs and EFSMAs that constitute the output of the transformation method of the present invention.
The production of the specification involves specifying the functions the application or system will have to fulfill, defining the types and uses of variables, defining parameters and their relationships, and the other requirements which go into a conventional specification.
Such a specification may be quite extensive. For instance, for the widespread version of UNIX known as POSIX, the specification for the system application program interface (API) for the C programming language runs over 350 pages in the book entitled ISO/IEC 9945-1 (IEEE Std 1003.1)/Information Technology--Portable Operating System Interface (POSIX)--Part I (First Edition Dec. 7, 1990), which is incorporated herein by reference.
Software applications developers, system engineers, end users operating in a UNIX environment and others refer to such a specification whenever they author applications based upon it. Typically, such applications are tested during and after their creation, for internal consistency and to ensure that they perform as intended. Such testing will be referred to herein as validation (or validity) testing.
In the case of POSIX, for example, the above-mentioned IEEE reference provides the complete English-language specification of POSIX for the C programming language. Whenever a programmer writes an application in C to run on the POSIX operating system, this reference must be consulted to ensure that all of the standards are being complied with.
It is a very difficult and involved matter to ensure that an implementation of a long specification is consistent with the specification, and yet this is crucial for the proper operation of the implementation and anything based upon it. Testing and verifying the implementation is particularly important when the specification are for a computer language such as C or an operating system such as UNIX. If, for instance, an operating system based upon POSIX includes errors, those errors will create bugs in all programs that run on the erroneous operating system. Thus, before the implementation of POSIX is ever released, it should be fully tested.
Such an implementation will, for the POSIX 1003.1 specification mentioned above, take the form of a program written in the C language. Thus, the validation tests to be run must verify the correctness of this C implementation of the specification.
The concept of specification testing is represented, for example, by STATEMATE, which provides a system by which a programmer can model a specification and test it. See The STATEMATE Approach to Complex Systems, by i-Logix of Burlington, Mass. (1990); and D. Harel et al., STATEMATE: A Working Environment for the Development of Complex Reactive Systems, IEEE Transactions on Software Engineering, Vol. 16, No. (April 1990). Testing the implementation of a specification (i.e. an application based on the specification), based upon traversal of a graph model based upon the implementation, is discussed in W. H. Jessop et al., Atlas--An Automated Software Testing System, Bell Laboratories, Inc., 13th IEEE Computer Society International Conference, pp. 337-340 (1976) and 2nd International Conference on Software Engineering, pp. 629-635 (1976). Various test selection methods for systems expressed as finite state machines are discussed in S. Fujiwara et al., Test Selection Based on Finite State Models, IEEE Transactions on Software Engineering, Vol, 17, No. 6 (June 1991) and W. H. Jessop et al. Each of the foregoing articles is incorporated herein by reference.
With the STATEMATE system, the user must convert the English-language (as opposed to computer code) specification into a machine-readable coding. Neither STATEMATE nor other prior systems automatically generate validation tests for the actual implementation of the specification, i.e. for applications which are designed to comply with it.
To generate validation tests of an application, the systems described in the Jessop and Fujiwara articles rely upon an expression of the specification as a finite state machine (FSM). Essentially any specification or software application can theoretically be expressed an FSM, whether the modeled entity is state-rich or expressed as data relationships. An "extended" finite state machine adds context to the transitions (i.e. a record of the history of traversal of the transitions). See the Introduction below for a formal definition of EFSM.
FSMs and EFSM(A)s are particularly suited to state-rich problems. A program is state-rich if it controls a system where the state of the system at any given time is important, such as a program to control an automatic teller machine. A specification for an operating system interface or a program routine, on the other hand, is typically data-rich; that is, the specification is described largely in terms of detailed data structures and their relationships.
Although one can, if necessary, generate an FSM to represent a data-rich specification as states with transitions from one state to another, such a model does not serve well as a human-readable specification.
In addition, hand-generated graph models are subject to the limitations of the programmer who creates them, which can lead to testing inefficiencies or inaccuracies, particularly in the case of a data-rich setting. Data-rich problems are particularly unsuited to being expressed as graph models such as FSMs, since they are by definition descriptions of data relationships, not of states and generating and executing such tests is described below, but is primarily the subject matter of applicant's copending patent application, Ser. No. 08/100,006 entitled "Method and Apparatus for Testing Implementations of Software Specifications" (the "ISL Testing" application), which was filed on the same date as the present application.
The disclosure of the present application overlaps extensively with that of the ISL Testing application, since the description of the transformation procedure of the present invention is best explained in proper context, i.e. the generation of tests as a whole and the execution thereof.
The specification used to generate an EFSM(A) is expressed in a computer language, which can be compiled by a processor to generate tests for the specification, by describing data relationships in the input and output to an application programming interface (API). For this purpose, applicant has created a new language called Interface Specification Language (ISL). The specification is thus expressed as ISL source code. When this source code is compiled, the output includes:
(1) an extended finite state machine (EFSM) or a multiple-EFSM architecture, which is a model of the specification; PA1 (2) user documentation for the specified interface; and PA1 (3) validation code, i.e. callable routines allowing compile and run-time validation of parameters to be used before service is provided. PA1 "Method and Apparatus for Testing Structures Expressed as Finite State Machines" (the "PFL" application), Ser. No. 08/100,002, issued as "Method and Apparatus for Generating Tests for Structures Expressed as Extended Finite State Machines," U.S. Pat. No. 5,394,347 issued Feb. 28, 1995; PA1 "Method and Apparatus for Testing Implementations of Software Specifications" (the "ISL Testing" application), Ser. No. 08/100,006; and PA1 "Method and Apparatus for Schematic Routing" (STE Routing), Ser. No. 08/100,001, U.S. Pat. No. 5,408,597 issued Apr. 18, 1995
An EFSM or EFSMA generated by compiling the ISL source contains states, transitions and outputs, with context, event and predicate definitions. These concepts are conventional in the definition of an EFSM. See "ESTELLE--A FDT based on an extended state transition model", ISO TC 97/SC21 DP 9074, September 1985, which is incorporated herein by reference. Each transition in the model contains test information describing the result of satisfying a unique data relationship, or providing flow control to allow only valid combinations of data relationships to be selected. Test information is written in the target test language (C, Ada, FORTRAN, etc.) by the ISL compiler.
The EFSMAs are, in the preferred embodiment, constructed in applicant's Path Flow Language (PFL). The construction and use of EFSMAs are discussed in detail in applicant's copending U.S. patent applications, as follows:
Each of the foregoing patent applications was filed with the United States Patent Office on the same date as the present application, and each of the applications and articles cited above is incorporated herein by reference.
The output models (i.e. EFSMs or multiple-EFSM architectures) allow one of several path generation methods to be used, filling the requirements of exhaustive testing, thorough testing and identification testing as defined in IEEE Std 1003.3--1991/IEEE Standard for Information Technology--Test Methods for Measuring Conformance to POSIX (1991). See also Chow, T., Testing Software Design Modeled by Finite-State Machines, IEEE Transactions on Software Engineering, Vol. 4, No. 3, May 1978. These two references are incorporated herein by reference. In ISL parlance, exhaustive testing may be referred to as "allpaths", and thorough testing or identification testing as "edge cover" or "transition cover".
A given path through an EFSM represents a unique combination of data relationships, and traversing the path produces values for parameters and executable code that correspond to those data relationships, in addition to an API call that, when invoked, traverses the combination of data relationships. The path traversal also produces conditions which will appear in the program shell that is used to test the implementation of the specification.
The process of compiling ISL source into EFSMs is an equivalence transformation-that is, each data relationship or other construct in the original transitions. Thus, although a data-rich specification can be expressed as an FSM, it is very cumbersome to do so, and is not an intuitive way to approach the problem. Moreover, while such a model would be computer-readable, it could not easily be interpreted by humans if complicated data structures are involved. For this reason, FSM-based systems (such as Atlas) are not, in general, useful for data-rich problems. The cited articles do not teach any mechanism for automatically generating validation tests using the specification itself as a starting point.
A system is needed which bypasses the necessity for human intervention in the creation of models to generate testing software against a specification, and which at the same time can produce a set of tests which are accurate and which can be tailored to any degree of comprehensiveness, from testing all possible paths through the model to testing only a few. In particular, a system is needed which allows for modeling of a specification in a manner which is suitable for humans, but which leads directly to an expression of the model which can be used by a computer to generate validation tests for the implementation of the software.

Method and apparatus for generating an extended finite state machine architecture for a software specification


Using a combination of frequency dithering of a PWM counter and a variable time delay circuit yields improved PWM frequency resolution with realizable circuit components and clock operating frequencies. A controllable time delay circuit lengthens a PWM signal during the first PWM cycle. During the second PWM cycle, the PWM period is increased beyond the desired amount, but the delay is reduced during this second PWM cycle to achieve the correct (desired) PWM signal period. The dithering of the PWM signal period enables the time delay circuit to be “reset” so that an infinite delay circuit is not required. The time delay circuit provides short term (one cycle) frequency adjustment so that the resulting PWM cycle is not dithered and has a period at the desired frequency resolution.

Power conversion techniques using pulse width modulation (PWM) controllers typically vary the duty cycle, the phase, or the frequency of the PWM signal to control the flow of power in a power supply. Analog or digital PWM controllers may be used for PWM signal generation. Regardless of the PWM signal generation technique used, the general goal is to provide as much resolution as possible to minimize the output voltage ripple in the power supply.
For analog PWM signal generation, it is difficult to generate stable and consistent frequency PWM signals over temperature, process and when subjected to a range of ambient noise conditions.
The digital generation of PWM signals with high frequency resolution is very difficult. PWM signal generators typically use a digital counter with an associated comparator and PWM period register. The frequency resolution of this typical PWM circuit is determined by the frequency of the clock signal that drives the counter. To obtain one (1) nanosecond of frequency resolution, the counter must be clocked with a 1 GHz (Billion Hertz) signal. In many technologies, this high a frequency of operation is impossible to obtain, the required power consumption is too high, and/or the cost is prohibitive.
Most common power conversion controllers are implemented with analog circuitry that do not require high frequency clocks to achieve frequency resolution. It is know in the art of power supply design to increase the clock rate of the PWM generator counter to improve frequency resolution. This approach works well at lower frequencies for applications such as motor control but becomes impractical for higher frequency power conversion circuits. Very few companies have attempted to provide microcontrollers and/or digital signal processors with high resolution digital PWM generators to serve the power conversion market. Historically, the PWM parameter that was considered important was the duty cycle (PWM pulse width). Only recently, have "resonant mode" power conversion circuits become "fashionable" because of the desire to improve the power conversion efficiency. Resonant mode power conversion uses the PWM frequency to control the flow of power, instead of the PWM duty cycle.

System, method and apparatus having improved pulse width modulation frequency resolution


A thin film transistor and a manufacturing method thereof are provided. In the manufacturing method of the thin film transistor a semiconductive active layer and a semiconductor passivation layer are sequentially formed such that the semiconductor passivation layer protectively covers the semiconductive active layer. Then the stacked combination of the semiconductive active layer and semiconductor passivation layer are patterned by using a same patterning mask so that formed islands of the semiconductive active layer continue to be protectively covered by formed islands of the semiconductor passivation layer. In one embodiment, the semiconductive active layer is formed of a semiconductive oxide.

(a) Field of Invention
The present disclosure of invention relates to a thin film transistor array panel and a manufacturing method thereof. More specifically, it relates to formation of thin film transistors having a semiconductive oxide layer as their active layer.
(b) Description of Related Technology
It has become desirable to make computer display monitors and televisions thin and lightweight, and pursuant to such desire, cathode ray tubes (CRT) are being replaced by liquid crystal displays (LCDs) or organic light emitting devices (organic light emitting diode (OLED) displays). The liquid crystal panel part of an LCD system is a light-shuttering non-emissive device while the organic light emitting device (OLED display) is a self-emissive device. However they both include a thin film transistor array panel having a thin film transistor provided as a switching element per each individually addressed pixel unit.
The thin film transistor typically includes an active switching region (e.g., a semiconductor region) defining a channel area disposed between source and drain areas. However electronic characteristics of the active switching region (e.g., of the semiconductor material) may be detrimentally changed by the specific photolithography and etching processes used for forming different thin films, and the performance of the thin film transistor may be correspondingly deteriorated when the characteristics of the active region are detrimentally changed. Particularly, in the case where the active switching region includes a semiconductive oxide, if the channel-defining layer is exposed to moisture (e.g., water vapor), or external contaminating ions, or to oxygen during the manufacturing process of the thin film transistor, a corresponding chemical oxidation or reduction reaction may occur and may cause the electrical conductivity characteristics of the semiconductive oxide region to be adversely changed.
The above information disclosed in this Background section is only for enhancement of understanding of the technological background and therefore it may contain information that does not form the prior art that is already known or recognized by persons of ordinary skill in the pertinent art.

Thin film transistor array panel and manufacturing method thereof


A RF circuit includes a master PCB, a plurality of slave PCBs and a plurality of antennas. The master PCB includes at least two RF ICs and at least two transceiving diplexer groups for tranceiving different frequency bands. Each transceiving diplexer group includes a plurality of transceiving diplexers transceiving a same frequency band and electrically connected to the RF ICs via PCB tracks without intersection. Each slave PCB includes a frequency division diplexer electrically connected to at least two transceiving diplexers respectively belonging to different tranceiving diplexer groups for respectively transmitting different frequency bands. Each antenna electrically connects to one of the division diplexers.

1. Technical Field
The disclosure relates to radio frequency (RF) circuits and, specifically, to a dual-band RF circuit.
2. Description of Related Art
Wireless communication products using multiple transceiver paths have become more common and have made significant advances in both functionality and data transmission rate.
When a wireless communication device is operated in high and low frequency bands at the same time, two independent sets of transceiving components are required, such as (RF) integrated circuits (IC), transceiving diplexers, and others. Typically, a high frequency IC transmits a high frequency signal to a high frequency transceiving diplexer and a low frequency IC transmits a low frequency signal to a low frequency transceiving diplexer, and then subsequently to a common frequency division diplexer and further, to an antenna.
Referring to FIG. 1, a schematic diagram of a prior RF circuit is shown. A low frequency IC 101, a high frequency IC 102, low frequency transceiving diplexers 111, 113, 115, high frequency transceiving diplexers 112, 114, 116, and frequency division diplexers 121, 122, 123 are located on a printed circuit board (PCB) 10, wherein the low frequency transceiving diplexers 111, 113, 115 and the high frequency transceiving diplexers 112, 114, 116 are arranged in a staggered arrangement. The low frequency IC 101 transmits signals to the low frequency transceiving diplexers 111, 113, 115. The high frequency IC 102 transmits signals to the high frequency transceiving diplexers 112, 114, 116. The low frequency transceiving diplexer 111 and the high frequency transceiving diplexer 112 transmit signals to the frequency division diplexer 121. The low frequency transceiving diplexer 113 and the high frequency transceiving diplexer 114 transmit signals to the frequency division diplexer 122. The low frequency transceiving diplexer 115 and the high frequency transceiving diplexer 116 transmit signals to the frequency division diplexer 123. The frequency division diplexers 121, 122, 123 are connected to antennas 131, 132, 133 via coaxial-cables 141, 142, 143. In this RF circuit, signal transmission lines distributed on the PCB 10 intercross, and some signal transmission lines must be located between different layers of the PCB 10, increasing the circuit layout complexity and the RF path loss.
Therefore, it is desirable to provide a RF circuit that can overcome the limitations described.


A novel nonvolatile memory cell structure is provided using a non-self aligned CMOS process with two independent N+ implants using a two or a three polysilicon layer technology that allows in-circuit electrical erase and reprogramming together with reduction in cell size requirement. The novel memory cell is implemented with a merged transistor structure having an access transistor and a programmable transistor. The memory cell is constructed by having the control gate, formed of a first polysilicon layer, covering a portion of the channel length between drain and source to form the access portion of the merged transistors, and a floating gate formed of a second polysilicon layer overlapping a second portion of the channel length to form the programmable transistor portion of the merged transistor. Such merged transistor structure is equivalent to two transistors in series, a programmable transistor in series with an access transistor. A memory cell structure described in accordance with this invention allows a reduction of the portion of the floating gate covering the programmable transistor portion of the channel length. This results in a reduction in the floating gate to substrate capacitance (C.sub.FB) thereby improving the programming coupling ratio and reducing the overall cell size.

The spectrum of nonvolatile memories available today includes the mask programmed ROM, the fusible link bipolar PROMs, the one time programmable (OTP) ROMs, the ultra-violet erasable EPROMs (UV-EPROMs), and the electrically erasable PROMs (EEPROMs). Mask programmed ROMs are the earliest and least flexible type: once programmed, the stored information cannot be altered. UV-EPROMs offer more flexibility, information stored can be erased using ultra violet (UV) light and then electrically reprogrammed into a new pattern. With a single transistor per memory cell UV-EPROM memory arrays allow very high packing densities and low cost per bit. However, even though UV-EPROMs offer firmware designers more flexibility than the mask programmed ROMs, PROMs and the OTP ROMs, it is still not flexible enough for their needs. For a stored program to be updated, the UV-EPROM has to be taken out of its board and either replaced with another UV-EPROM having the new program or erased by putting it in special UV ovens for 10-20 minutes and then programmed with the new code using special purpose hardware programmers.
While EEPROM memories achieve greater flexibility by allowing in-circuit electrical erase and reprogramming, their high cost and small densities have limited their use. The high cost of EEPROM memories is not only due to their complex process but is also due to the fact that the EEPROM memory cell size is three to four times the size of a UV-EPROM cell for the same technology. The high cost per bit has limited the use of EEPROM chip mostly to applications where the user is expected to customize the system environment according to his needs or where the system configuration needs frequent updates.
The flash erase EEPROM (FEEPROM) is the latest addition to the nonvolatile ROM family members. FEEPROM is meant to bridge the gap between existing UV-EPROM and EEPROM by offering the type of ROM which is both electrically erasable as EEPROM and has the high density and cost efficiency of UV-EPROM. In addition to being electrically erasable, erasure of FEEPROM arrays take only few seconds as compared to erase times of 10-20 minutes for UV-EPROM arrays. This provides FEEPROMs with in-circuit program and erase capabilities.
Several FEEPROM memory cell structures have been described in, for example, S. Mukherjee, et al., "A Single Transistor EEPROM Cell And Its Implementation In A 512K CMOS EEPROM," IEDM, paper 26.1, pp. 616-619 (1985); H. Kume, et al., "A Flash-Erase EEPROM Cell With An Asymmetric Source And Drain Structure," IDEM, paper 25.8, pp. 560-563 (1987); G. Samachisa, et al., "A 128K Flash EEPROM Using Double Polysilicon Technology," ISSC, paper 7.4, pp. 76-77 (1987); F. Masouka, et al., "A New Flash E.sup.2 prom Cell Using Triple Polysilicon Technology," IDEM, paper 17.3, pp. 464-466 (1984).
Typically, a FEEPROM memory cell transistor is considered programmed when it is in the high threshold voltage state, i.e. when its floating gate is negatively charged with trapped injected electrons. FEEPROM memory cell is typically assumed to store a logic "0" when in the programmed state. Similar to UV-EPROM, FEEPROM is programmed by injecting hot electrons into the floating gate of the memory cell. A FEEPROM memory cell is considered erased when it is in the low threshold voltage state, i.e. when its floating gate is depleted from trapped injected electrons. FEEPROM memory cell typically is assumed to store a logic "1" when in the erased state. Erasure is normally achieved via electron tunneling from the floating gate to either an erase electrode as described in Masouka, or to one of the cell junctions as described in Mukherjee, Kume, and Samachisa.
Prior art FEEPROM memory cells are shown in FIGS 1a-1c and 2a-2c. Typically, the prior art FEEPROM memory cells are programmed by applying a voltage (V.sub.CG) on control gate 16, typically of about 12 V-14 V, and a voltage (V.sub.D) on drain 15, typically of about 7.5 V-10 V, while grounding source 14, (V.sub.S =0 V).
FIGS. 1a-1c show an example of a prior art single transistor memory cell 10 in terms of its topographical layout (FIG. 1a), schematic representation (FIG. 1b) and its cross-sectional view (FIG. 1c). When floating gate 18 is electrically neutral or slightly positively charged, memory cell 10 is in the `erased` state, and memory cell 10 has a low threshold voltage (Vte) typically of about 1.5 volts. When floating gate 18 is negatively charged, transistor 10 is programmed, and it has a high threshold voltage (Vtp), typically of about 6.5 volts.
Memory cell 10 is "programmed" by applying a high voltage of about 12 v-14 v to control gate 16 and a high voltage of about 8 v-10 v to drain 15, while grounding source 14. Good capacitive coupling between control gate 16 and floating gate 18 improves the vertical electric field formed between substrate 28 and floating gate 18 to improve the programming efficiency of memory cell 10. The floating gate voltage (V.sub.F) can be expressed by: ##EQU1## V.sub.f =Control gate voltage; V.sub.G =Control gate voltage;
V.sub.D =Drain voltage; PA1 Q.sub.F =Net charge stored on the floating gate; PA1 C.sub.FG =Floating gate to control gate capacitance; PA1 C.sub.FD =Floating gate to drain capacitance; PA1 C.sub.FS =Floating gate to source capacitance; and PA1 C.sub.FB =Floating gate to substrate capacitance.
The voltage coupled to the floating gate from the control gate (V.sub.F) is controlled by the following ratio, also referred to as the programming coupling ratio, ##EQU2## C.sub.TOT =Floating gate total capacitance.
Increasing the programming coupling ratio as expressed in equation (2) increases the efficiency of the floating gate to collect hot electrons and, thus, also increases the programming efficiency of the FEEPROM memory cell. The programming coupling ratio can be increased either by decreasing the floating gate to substrate capacitance (C.sub.FB) or by increasing the floating gate to control gate (C.sub.FG) capacitance. One way to increase this ratio without increasing the memory cell size is by increasing C.sub.FG through the use of special dielectrics of high dielectric constant between floating gate 18 and control gate 16 such as with an oxide nitride oxide (ONO) sandwich which has generally been used in more recent EPROM cells.
The programming efficiency can also be enhanced through enhancing the efficiency of hot electron generation. This can be achieved by having a higher electric field at drain injunction 11 where hot electrons are generated. Enhancement of hot electron generation is accomplished by using a shallower drain junction as well as using P.sup.+ type implant surrounding the drain junction.
Typically, memory cell 10 is "erased" by electron tunneling from floating gate 18 to source 14. This is accomplished by electrically grounding, relative to source 14, control gate 16 while a high voltage pulse of about 14 v-17 v is applied to source 14. Drain junction 15 is left to float to avoid punch through problems between source 14 and drain 15. Electron tunneling is appreciable at relatively high electric fields between 7 Mv/cm to 10 Mv/cm.
To achieve such high electric fields, the thickness of the first gate oxide between floating gate 18 and substrate 28 is reduced to prevent the need to use excessive voltages on chip. However, thinning gate oxide results in processing and reliability problems, and it also reduces the programming coupling ratio causing degradation in programming efficiency. Improving the programming coupling ratio of memory cell 10 necessitates increasing the cell size when the thickness of the first gate oxide is reduced: since the programming coupling ratio is decreased, the cell area must be increased to improve the programming coupling ratio. Improving the programming coupling ratio of memory cell 10 necessitates increasing the cell size. Thus, source 14 of memory cell 10 must withstand a high erase voltage (V.sub.e) without breakdown. Lowering the erase voltage by decreasing the thickness of first gate oxide 26 is also not a solution since the gated diode breakdown voltage is reduced for thinner gate oxides. To increase the gated diode breakdown of the source junction, a deeper doubly diffused N.sup.+ -N.sup.- junction is used.
The floating gate voltage during erase is given by: ##EQU3## V.sub.e =The erase voltage.
For more efficient erasure, V.sub.F, floating gate voltage should be minimized and, thus, the erase coupling ratio, expressed as ##EQU4## should be minimized.
Ideally, it is preferable to have FEEPROM arrays with one transistor per memory cell, a structure similar to UV-EPROMs. However, contrary to the self limiting nature of erasure by UV radiation, electrical erase is not self limiting. FEEPROM memory cell may become partially erased, where only part of the stored electron charge has been removed, or over-erased where the floating gate may become positively charged, depending on the applied erase voltage and applied erase time. An over-erased FEEPROM memory cell threshold voltage may result in a negative threshold voltage causing the over-erased FEEPROM cell to become a depletion transistor memory cell.
Prior art FEEPROM cell structures approached the over-erase problem by using a merged transistor memory cell structure with a single control gate covering the full length of the channel between the drain and source, and a floating gate only covering part of the channel length. Such merged transistor structure is equivalent to two transistors in series, a programmable transistor and an access transistor, but without a separation of the transistors by a physical junction. The programmable transistor controls the programming of the memory cell, while the access transistor limits the current and prevents an incorrect reading of the stored data if the programmable transistor is over-erased into depletion mode. In typical prior art merged transistor FEEPROMs, the part of the channel covered by the floating gate acts as the programmable transistor while the part of the channel covered only by the control gate acts as the access transistor. Such a structure avoids over-erase problems, while reducing the cell size, when compared to conventional merged transistor type EEPROMs.
Shown in FIGS. 2a-2c is a prior art merged transistor FEEPROM memory cell 20. Similar to the prior art EEPROM cells, merged transistor memory cell 20 operates in effect as two transistors in series, an access transistor and a programmable transistor. The access transistor is controlled via access portion (L.sub.a) 17 of control gate 16, while the programmable transistor is controlled via portion (LP) 19 of floating gate 18. The access transistor alleviates over-erase problems by preventing current flow through unselected memory cells of an array of memory cells. Merged transistor FEEPROM memory cell 20 not only provides two series transistors, but it is smaller in cell size than the typical two transistor per cell EEPROM, since memory cell 20 eliminates the physical junction normally separating the two series transistors.
When programmed, the effective threshold voltage of memory cell 20 equals the threshold voltage of the programmable transistor. Even if the programmable transistor is erased into depletion, the overall effective threshold voltage of memory cell 20 will remain positive, limited by the threshold voltage of the access transistor. Thus the effective overall threshold voltage is limited to the higher of either the programmable transistor or the access transistor. To program, floating gate 18 is charged with excess electrons which increases the threshold voltage of programmable transistor region 19 of memory cell 20. With floating gate 18 of memory cell 20 overlapping only drain junction 15, the electrical erase of memory cell 20 is also performed at drain junction 15. Effectively, both programming and erasing of memory cell 20 are thus performed at drain junction 15.
The programming conditions of memory cell 20 are similar to those of memory cell 10. However, programming for cell 20 is inherently less efficient since the lateral electric field is reduced due to the voltage drop across the access transistor. This voltage drop can be compensated by increasing the drain voltage during the programming mode of memory cell 20. However, increasing the drain voltage risks erasure of unselected memory cells of the same column in an array erase.
The erase conditions of memory cell 20 are similar to those of memory cell 10 with the exception that the erase pulse is to be applied to drain junction 15, while source junction 14 is floated.
For memory cell 20, both programming and erasure are performed at the drain junction, which imposes conflicting requirements on the drain junction. Shallow drain with P+ background implant is preferable for improved programming performance, while deeper drain junctions with preferably N- background implant is preferable for better erase performance. Optimizing the drain junction profile for these conflicting requirements typically compromises memory cell performance.
The conditions for the different operating modes of cells 10 and 20 are summarized as shown in Table 1.
TABLE 1 ______________________________________ FEEPROM Operating Modes PROGRAM ERASE READ ______________________________________ Cell 10 V.sub.CG .about.14V 0V .about.4.5V V.sub.D 7-9V float .about.1.75V V.sub.S 0V V.sub.e 0V Cell 20 V.sub.CG 14V 0V .about.4.5V V.sub.D 8-10V V.sub.e .about.1.75V V.sub.S 0V float 0V ______________________________________
Thus, the prior art FEEPROM memory cell structures can be generally classified into single transistor memory cell structure and merged transistor cell structure. In both types of prior art embodiments of FEEPROM memory cell structures, first polysilicon layer (poly1) 11 deposited over substrate 28 between drain 15 and source 14 forms floating gate 18 of memory cells 10 and 20, while second polysilicon layer (poly2) 12 deposited over floating gate 18 forms control gate 16.
Single transistor FEEPROM memory cell structures, such as those described in S. Mukherjee, et al., and Kume, et al., suffer from over-erase problems causing this type of FEEPROM memory cells to result in unreliable erase and programming performance. Single transistor FEEPROM memory cells exhibit over-erase problems at all junction profiles. Even at low erase currents, these cells may erase to voltages below their threshold values if erase time is sufficiently long. The threshold voltage of single transistor FEEPROM memory cell may even become negative changing the memory cell into a depletion device. In a full array erase, these changes in memory cell erase threshold value may result in an unreliable erase of the memory cells due to some memory cells becoming depletion devices. Single transistor FEEPROM memory cells therefore require a strict control of both the erase current and erase time to be exercised. However, even under such conditions, the array erase reliability cannot be guaranteed.
Prior art merged transistor FEEPROM memory cell structure with two polysilicon layer technology as described in Samachisa, et al., avoids the over-erase problem by using an integral select transistor in the part of the memory cell. This approach allows both programming and erasure to be accomplished at the drain junction of the merged transistor. However, this approach requires tight process control to optimize both the erase and programming requirements at the drain junction.
Another embodiment of a prior art merged transistor FEEPROM memory cell structure as described in Masouka, et al., incorporates a triple polysilicon layer technique, where a first polysilicon layer is used as an erase electrode, a second polysilicon layer is used as a floating gate, and a third polysilicon layer formed over the floating gate acts as the control gate of the merged transistor. This approach is disadvantageous since the floating gate is spaced away from the drain junction, requiring higher programming voltages, greater power consumption, and resulting in unreliable programming operation. This type of structure also requires excessively high voltages for both programming and erasure which limits the practicality and manufacturability of this structure.
There is therefore a need for improved FEEPROM memory cells which provides an improvement to memory cell programming and erasure performance, without increasing FEEPROM programming voltage or cell size.

Electrically reprogrammable EPROM cell with merged transistor and optiumum area


A gas cookstove having in its top face an opening forming a recess for accommodating a removable container below which is mounted at least one gas burner supported by a tray retained on the edge of the recess like opening and interposed between a casing and the bottom of the removable container, the cookstove being applicable to the cooking of any foodstuff in a container removably fitted into the top of the cookstove.

The present invention relates essentially to an improved gas cookstove.
The evolution of the technique in the field of the cookstoves has been very small these last years.
In a general manner the cookstoves always have a single function for the cooking at the top namely the cooking of foodstuffs in vessels of various shapes on bare or uncovered fires.
Therefore one is still facing the problem of the cleaning of the top of the cookstove when there is an overflow of the containers. Moreover the heating is localized on the bottom of the vessel, so that the foodstuffs it contains may not be cooked in a homogeneous manner, i.e. with a heating taking place over the whole bottom and peripheral surface of the vessel.
Furthermore if one refers for instance to the document FR-A-2,004,693, there has already been proposed cookstoves the top face of which comprises an opening defining a recess adapted to accommodate a cooking container forming a deep fryer.
However the electrical heating resistor fastened upon the external face of the bottom of the container does not permit to consider this container as constituting a forthwith removable vessel, i.e. as a vessel which may at will and easily be placed within the opening of the cookstove and taken out of this opening, quite like a usual cooking vessel such as a saucepan which one sets quite simply upon the cookstove and which one withdraws after the cooking.


Microbubbles detached from a blood circuit and a blood purification unit are discharged with the use of a backflow generated at the instant that a roller of a blood pump releases a squeezable tube. In a normal rotation step, a region filled with a priming solution after a priming step is closed by a closing unit, and a rotor of a blood pump is rotated normally until a roller of the blood pump releases a squeezable tube to generate a backflow. After the backflow is generated at the release of the squeezable tube by the roller of the blood pump, bubbles are moved by reversely rotating the rotor while disabling the closing by the closing unit. Thus, the bubbles are discharged through a discharge unit.

In general, dialysis treatment is performed by using a blood circuit for allowing blood collected from a patient to extracorporeally circulate and to be returned into the body. Such a blood circuit basically includes, for example, an arterial blood circuit and a venous blood circuit that are connected to a dialyzer (a blood purification unit) including hollow fiber membranes. The arterial blood circuit and the venous blood circuit are provided at distal ends thereof with an arterial puncture needle and a venous puncture needle, respectively. Extracorporeal circulation of blood in the dialysis treatment is performed with the puncture needles puncturing the patient.
In particular, the arterial blood circuit is provided with a squeezable tube connected thereto and a peristaltic blood pump. The blood pump delivers liquid by squeezing the squeezable tube with a roller. When the blood pump is activated, the patient's blood can be caused to extracorporeally circulate through the blood circuit. Therefore, the blood in extracorporeal circulation undergoes blood purification treatment in the dialyzer.
Furthermore, the arterial blood circuit is provided with a priming-solution supply line for supplying a priming solution to the blood circuit. Before the dialysis treatment, a priming process is performed in which a priming solution is supplied through the priming-solution supply line and is discharged through an overflow line, whereby bubbles in the blood circuit are discharged while flow routes in the blood circuit are filled with the priming solution (see PTL 1, for example).
PTL 1: Japanese Unexamined Patent Application Publication No. 2010-273693, the teachings of which are expressly incorporated by reference herein for all purposes.

Blood purification apparatus and method of discharging bubbles therefrom


A correction method for correcting measurement error in data obtained when a stylus tip of a measurement apparatus that moves following the height of a workpiece traces the workpiece along a measurement axis, the measurement error having occurred due to stylus movement in a plane defined by the measurement axis and height directions, the method includes a calibration measurement process of obtaining calibration measurement data that includes shift information on the position of the stylus tip, corresponding to the position of the stylus tip in the height directions while the stylus is moved in the correction target plane and a correction-parameter setting process obtaining a correction parameter value optimal to correct the shift information on the position of the stylus tip, included in the calibration measurement data, for each of the sectors obtained by dividing a measurement range in the height directions.

1. Field of the Invention
The present invention relates to a correction method, computer-readable recording mediums storing computer-executable correction programs and measurement apparatuses, and in particular, relates to an improved method for deriving correction parameters used to correct measurement errors due to the movement of a stylus.
2. Prior Art
Precision measurement apparatuses, such as form measuring instruments, have been used to measure the contours of workpieces. Such a precision measurement apparatus includes a stylus and a pickup unit for the stylus; the stylus moves along a circular arc, depending on the height of a workpiece, when the position of a tracing made by a tip of the stylus is moved on the workpiece along a measurement axis. While the stylus tip traces the surface of the workpiece, the pickup unit obtains coordinate information of the workpiece. According to the obtained coordinate information of the workpiece, the contour of the workpiece is determined.
Some precision measurement apparatuses include a linearly-moving stylus that moves straight depending on the height of a workpiece when a trace position is moved along a measurement axis, and a pickup unit for the stylus.
Precision measurement apparatuses are required to perform more precise measurement than general measurement apparatuses. In a precision measurement apparatus provided with a pickup unit for a pivot-type stylus, however, since the stylus arm moves along a circular arc, the measurement results contain errors. It is very important to reduce these errors appropriately.
Conventionally, data measured by the pivot-type stylus is corrected by a correction method such as that described in the specification, and elsewhere, of Japanese Patent No. 2,727,067, Japanese Patent No. 3,215,325, Japanese Unexamined Patent Application Publication No. 2003-500675, Japanese Unexamined Patent Application Publication No. Hei-03-115,902, or U.S. Pat. No. 5,150,314, to reduce the effects of the measurement errors caused by the circular-arc movement of the pivot-type stylus.
It is also very important for a precision measurement apparatus provided with a pickup unit for a linearly-moving stylus to reduce the effects of the measurement errors caused by the straightness deviations of the straight movement of the stylus.
It has been desired that the correction precision obtained by the conventional method of data measured by a stylus be further improved, but there has thus far been no appropriate technology to achieve this.

Correction method, computer-readable recording medium storing computer-executable correction programs and measurement apparatus


An apparatus or method of the present invention measures carbon monoxide included in a hydrogen-rich reactant gas with high precision, and also measures a lower alcohol or another organic compound included in the reactant gas. A carbon monoxide sensor (1) includes an electrolyte membrane (10), a pair of electrodes (12,14) arranged across the electrolyte membrane (10) to form a sandwich structure, a pair of holders (20,22) for supporting the sandwich structure as well as pair of metal plates (16,18), and an insulating member 24 for connecting the holders (20,22) with each other. A gas flow conduit (28) is joined with one holder (20), and a gaseous fuel is fed to the electrode (12) via the gas flow conduit (28). The electrode (14) supported by the other holder (22) is exposed to the atmosphere. A resistor (34) is connected to detection terminals (20T,22T) of the holders (20,22), and a potential difference between both terminals of the resistor (34) is measured with a voltmeter (32). The voltmeter (32) outputs a signal representing the measured potential difference to an external control system. The control system determines the degree of poisoning and the concentration of carbon monoxide, based on the signal representing the measured potential difference.

1. Field of the Invention
The present invention relates to an apparatus for detecting carbon monoxide included in a hydrogen-containing reactant gas, an apparatus for detecting an organic compound included in the reactant gas, and an apparatus for detecting a lower alcohol included in the reactant gas. The present invention also pertains to the respective methods of detecting carbon monoxide, an organic compound, and a lower alcohol.
2. Description of the Related Art
Fuel cells are known apparatus in which the chemical energy of a fuel is converted directly into electrical energy. The fuel cell generally has a pair of electrodes arranged across an electrolyte, where the surface of one electrode is exposed to reactive gaseous hydrogen or gaseous fuel while the surface of the other electrode being exposed to an oxidizing gas containing oxygen. The electrical energy is generated between the electrodes through the electrochemical reactions occurring by the exposure.
A gaseous fuel supplied to such fuel cells is generated by a reformer, where methanol is steam-reformed according to the following reactions: EQU CH.sub.3 OH.fwdarw.CO+2H.sub.2 -21.7 kcal/mol (endothermic reaction)(1) EQU CO+H.sub.2 O.fwdarw.CO.sub.2 +H.sub.2 +9.8 kcal/mol (exothermic reaction)(2 ) EQU CH.sub.3 OH+H.sub.2 O.fwdarw.CO.sub.2 +3H.sub.2 -11.9 kcal/mol (endothermic reaction) (3)
Carbon monoxide (CO) generated through the reaction expressed by Equation (1) is converted to carbon dioxide (CO2) by the reaction of Equation (2), and thus does not participate in the reforming reaction expressed by Equation (3). The rate of reaction expressed by Equation (1) may be different from the rate of reaction expressed by Equation (2), depending upon the reaction conditions, such as temperature and pressure. Carbon monoxide (CO) generated in the reaction of Equation (1) thus remains and is adsorbed by platinum catalyst or platinum-containing alloy catalyst on the fuel electrode and interferes with the catalytic action of platinum. This is generally referred to as poisoning of catalyst. Generators utilizing such fuel cells accordingly require a structure allowing the presence of carbon monoxide in the gaseous fuel fed from the reformer.
A variety of carbon monoxide sensors have been developed for determining the concentration of carbon monoxide included in a supply of gaseous fuel fed to the fuel cells.
A typical example is a potentiostatic electrolysis-based carbon monoxide sensor, which utilizes potentiostatic electrolysis applied to electrochemical analysis in solutions. FIG. 21 schematically illustrates a conventional potentiostatic electrolysis-based carbon monoxide sensor, which includes three electrodes; that is, a reference electrode P1, a counter electrode P2, and a working electrode P3.
These electrodes P1, P2, and P3 are exposed to a phase of electrolytic solution and a gas phase. When carbon monoxide comes into contact with the working electrode P3, an anode reaction shown below proceeds: EQU CO+H.sub.2 O.fwdarw.CO.sub.2 +2H.sup.+ +2e.sup.-
while a cathode reaction shown below proceeds on the counter electrode P2 exposed to oxygen included in the air: EQU (1/2)O.sub.2 +2H.sup.+ +2e.sup.- .fwdarw.H.sub.2 O
The total reaction is accordingly expressed by: EQU CO+(1/2)O.sub.2 .fwdarw.CO.sub.2
The concentration of carbon monoxide is then determined by measuring the electric current generated through the oxidation of carbon monoxide with an ammeter P4.
This conventional carbon monoxide sensor can determine the concentration of carbon monoxide included in the air with high precision, but is significantly affected by the presence of hydrogen because of its principles of measurement. The conventional potentiostatic electrolysis-based sensor is thus not suitable for determining the concentration of carbon monoxide included in the hydrogen-rich gaseous fuel, which contains only a trace amount of carbon monoxide in an extremely large amount of hydrogen. The sensor naturally has a low sensitivity of detection to hydrogen, which is approximately 1/80 that to carbon monoxide. Since a supply of gaseous fuel fed to fuel cells contains an extremely large amount of hydrogen, the sensor simultaneously detects hydrogen and carbon monoxide and suffers from a problem of low precision in the measurement of carbon monoxide.
Like the potentiostatic electrolysis-based sensor described above, another known carbon monoxide sensor based on catalytic combustion has been developed originally for measuring carbon monoxide included in the air. The problem of poor precision thus arises in the process of measuring carbon monoxide included in the hydrogen-rich gaseous fuel.
Apparatus for detecting organic compounds and those for detecting lower alcohols have also been proposed and utilized.
Known methanol-detecting apparatus, which correspond to both the organic compound-detecting apparatus and the lower alcohol-detecting apparatus, are used for detecting methanol included in gasoline (for example, JAPANESE PATENT PUBLICATION GAZETTE No. H-3-48533). Such an apparatus is constructed as a cell including an ion-exchange membrane and two electrodes arranged across the ion-exchange membrane, where gasoline is fed to one electrode and an electrolytic solution, that is, 10 percent by weight of aqueous sulfuric acid, to the other electrode. On the electrode exposed to gasoline, a reaction expressed by Equation (4) below proceeds to generate carbon dioxide, hydrogen ions and electrons from methanol and water included in gasoline. On the electrode exposed to the electrolytic solution, a reaction expressed by Equation (5) below proceeds to generate water from hydrogen ions permeated through the ion-exchange membrane and oxygen and electrons included in the electrolytic solution. EQU CH.sub.3 OH+H.sub.2 O.fwdarw.CO.sub.2 +6H.sup.+ +6e.sup.- ( 4) EQU (3/2)O.sub.2 +6H.sup.+ +6e.sup.- .fwdarw.3H.sub.2 O (5)
Electromotive force generated between the electrodes by these electrochemical reactions increases with an increase in concentration of methanol included in gasoline. This apparatus accordingly determines the concentration of methanol included in gasoline, based on the electromotive force generated between the electrodes.
These conventional methanol-detecting apparatus, which are used for detecting methanol included in gasoline, that is, a liquid, can not measure methanol included in a gas, especially, a hydrogen-rich gas. Precise measurement of methanol included in a hydrogen-rich gas leads to efficient operation of methanol reformers for generating a hydrogen-rich gas through the reaction of methanol with water or to efficient operation of fuel cells or other mechanisms for generating electrical energy using as a fuel the hydrogen-rich gas generated by the methanol reformer.
This problem is not characteristic of the methanol-detecting apparatus, but similar problems are also found in apparatus for detecting lower alcohols other than methanol or those for detecting other organic compounds, when petroleum, instead of methanol, is used as material of the reformer.

Apparatus for detecting carbon monoxide, organic compound, and lower alcohol


In an image processing apparatus of this invention, an error diffusion processing means having a multi level signal conversion means changes the conversion characteristics of the multi level signal conversion means, e.g., corrects the output value of error diffusion processing, on the basis of an output from a means for detecting a variation in toner attachment amount or image forming condition. That is, this invention executes error diffusion processing as follows when an input dimension is different from an output dimension (e.g., input dimension=reflection factor or density, output dimension=number of gradation levels) with respect to a multi-value conversion means because error diffusion processing cannot be simply performed. The input dimension is set to coincide with the output dimension (an output signal is set to coincide with the input signal), this output signal is changed in accordance with a variation in image density, and an error between the changed output signal and the input signal is calculated, thereby executing error diffusion processing. Even when the gradation characteristics per pixel vary due to the influence of a change in environment or aging, or the number of gradation levels decreases due to the variation, the gradation characteristics in a local area can be maintained good, and initial image quality can be provided over a long period of time.

1. Field of the Invention
The present invention relates to an image processing apparatus, which performs multi-level conversion processing of a document image including a photograph image using an error diffusion method to satisfy faithful gradation reproducibility, and maintains good image quality by minimizing a variation in gradation characteristics under the influence of a change in environment, aging, and the like.
2. Description of the Related Art
In association with an image forming apparatus for printing, copying, or displaying a document original including a photograph image or image data obtained via document creation processing and image edit processing using a computer, an error diffusion method has been proposed as a binary conversion method which can satisfy gradation characteristics of both a photograph image area and a character/line image area, and can provide higher resolution characteristics of the character/line image area than those of an ordered dither method. The error diffusion method is disclosed in R. W. Floyd L. Steinberg: Pro: SID Vol. 17(2), pp 75-77, 1976. In the error diffusion method, a level obtained by multiplying multi level (binarized) errors of already multi level (binarized) pixels around a pixel of interest with a weighting coefficient is added to the pixel of interest, the sum is multi-level (binary) converted by a fixed threshold level, and a multi level (binarized) error generated at that time is distributed to the surrounding pixels. More specifically, in this method, although an output level corresponding to each pixel unit is predetermined multi-level data (binary data), the sum total of errors associated with a local area of an output image corresponding to that of an original image (multi-level image data) having continuous gradation is eliminated or minimized, thus compensating for gradation characteristics. For this reason, input gradation information can be expressed by the number of output levels smaller than that of the gradation levels of input pixel signals.
In such an error diffusion processing means, a multi level signal means a predetermined number of levels such as the number of write levels of an image forming system. In contrast to this, an input signal has a physically different dimension from that of a multi level signal to be output since it is a signal read by, e.g., a scanner or an image created using a computer, and means reflection factor or density information. For this reason, in error calculations, a contradiction upon calculations, i.e., addition/subtractions between different dimensions, occurs.
When the gradation characteristics of an image output from an image forming apparatus for forming an image based on a multi level signal as a result of error diffusion processing vary due to a change in environment, aging, or the like, a gamma correction means or color correction means, a multi level signal conversion means, or the like is externally arranged at the upstream or downstream side of an error diffusion processing unit, so as to calculate correction characteristics in correspondence with a detection result of a variation in gradation characteristics, and to modify, e.g., table contents. However, even in an input/output relationship free from the above-mentioned contradiction upon calculations between different dimensions when no variation in gradation characteristics occurs, if the gradation characteristics of an output image vary, and the gamma table is corrected, the relationship between the corrected input pixel signal and the multi level undesirably changes, thus deteriorating accuracy of error calculations.
Furthermore, in error diffusion processing for performing multi-level conversion using a fixed threshold level, a macroscopic change in gradation characteristics can be eliminated upon practical variations in gradation characteristics and the number of gradation levels corresponding to levels of multi level signals, but deterioration of image quality such as a decrease in resolution, conspicuousness of a texture, and the like cannot be suppressed.


A photosensitive compound whose size is smaller than conventional polymer for photoresist, and which has well-defined (uniform) structure, and a photoresist composition including the same are disclosed. The photosensitive compound represented by the following formula. Also, the present invention provides a photoresist composition comprising 1 to 85 wt % (weight %) of the photosensitive compound; 0.05 to 15 weight parts of a photo-acid generator with respect to 100 weight parts of the photosensitive compound; and 10 to 5000 weight parts of an organic solvent.

The photolithography is a process used to form a circuit pattern of a semiconductor chip or a display element from a semiconductor wafer or a glass for the display element. The photoresist composition is the most essential materials to the photolithography process. Recently, as the patterns for semiconductor devices and the display elements are finer, the need for the photoresist composition having high resolution is more increased.
Conventional acid-amplified photoresist composition includes a polymer resin, a photo-acid generator (PAG), an organic solvent and a base compound as occasion demands. Since the conventional photoresist composition includes the polymer resin as a main component, it has excellent mechanical properties such as processibility, coating stability, etching resistance and can be easily removed after the succeeding process including an etching process, an ion implantation process and so on. However, it has disadvantage in that the resolution of photoresist composition is restricted by the size of polymer resin. That is, in the photolithography process, it is impossible to form the pattern which has smaller size than the photosensitive polymer resin included in a photoresist composition. Also, as the structure of semiconductor changes to a fine structure less than 65 nm, the resist which has a polymer as main component do not offer uniformity for fine patterns. This is because the polymer component which is composed of polymer chains of various structures has randomicity to itself.

This patent is subject to a terminal disclaimer.

Photosensitive compound and photoresist composition including the same

Abstract: In the formula, n is 0 or 1, x is 1, 2, 3, 4 or 5, y is 2, 3, 4, 5 or 6, z is 0, 1, 2, 3 or 4, R, R′ and R″ are independently hydrocarbon group of 1 to 30 carbon atoms, preferably 2 to 20 carbon atoms, and R′″ is a hydrogen atom or hydrocarbon group of 1 to 30 carbon atoms, preferably 2 to 20 carbon atoms.


A semiconductor device includes an active region formed in an upper layer portion of a semiconductor layer of a first conductivity type, and a plurality of electric field relaxation layers disposed from an edge of the active region toward the outside so as to surround the active region. The plurality of electric field relaxation layers include a plurality of first electric field relaxation layers and a plurality of second electric field relaxation layers alternately disposed adjacent to each other, the first electric field relaxation layer and the second electric field relaxation layer adjacent to each other forming a set. Impurities of a second conductivity type are implanted to the first electric field relaxation layers at a first surface density, widths of which becoming smaller as apart from the active region. Impurities of the second conductivity type are implanted to the second electric field relaxation layers at a second surface density lower than the first surface density, widths of which becoming larger as apart from the active region.

Examples of the semiconductor devices (power semiconductor devices) having a breakdown voltage of 100 volts or higher that are used in power electronics include diodes, metal-oxide-semiconductor field-effect-transistors (MOSFETs), and insulated gate bipolar transistors (IGBTs). Those semiconductor devices are provided with the breakdown voltage structure for maintaining breakdown voltage resistance.
For example, the semiconductor device (vertical device) that flows current perpendicularly to the main surface of the semiconductor substrate has a termination structure formed so as to surround a region (active region) functioning as an active element, which serves as the breakdown voltage structure.
The semiconductor device (horizontal device) that flows current in parallel to the main surface of the semiconductor substrate has the breakdown voltage structure formed inside the active region.
The breakdown voltage structure functions to keep high voltage to be generated in the front surface of the main surface of the semiconductor substrate, irrespective of vertical devices or horizontal devices. High voltage is generated in the active region and the end of the semiconductor device in the vertical device, whereas high voltage is generated between electrodes inside the active region in the horizontal device.
Examples of the breakdown voltage of the semiconductor device include a reverse breakdown voltage of a diode and an off-breakdown voltage of a transistor. Such breakdown voltages are both defined as an upper-limit voltage to interrupt current (to flow no current).
While the semiconductor device interrupts current, a depletion layer extends inside the semiconductor substrate. This depletion layer can maintain high voltage. The application of a voltage exceeding the breakdown voltage leads to an avalanche breakdown in the portion inside the semiconductor substrate, in which an electric field is concentrated. As a result, the depletion layer is damaged, which causes short-circuit current to flow.
For example, in a PN junction diode (PIN diode) formed of a low-concentration N-type semiconductor substrate and a high-concentration P-type implantation layer, a depletion layer extends almost over the low-concentration N-type semiconductor substrate while the diode is turned off. Although it is this depletion layer that maintains high voltage, the breakdown voltage is limited due to an electric field concentration at the edge (peripheral edge) of the high-concentration P-type implantation layer.
The formation of a low-concentration P-type implantation layer in adjacent to the edge of the high-concentration P-type implantation layer causes the depletion layer to extend over both of the low-concentration N-type semiconductor substrate and the low-concentration P-type implantation layer. This relaxes the electric field at the edge of the high-concentration P-type implantation layer, increasing the breakdown voltage. This low-concentration P-type implantation layer is normally referred to as a reduced surface field (RESURF) layer or a junction termination extension (JTE). Such a breakdown voltage structure is referred to as a RESURF structure.
Although the depletion layer extends also in the RESURF layer in the RESURF structure, in terms of high breakdown voltage resistance, it is desirable to deplete the RESURF layer almost entirely up to the uppermost surface on a desired breakdown voltage. The condition for the above is defined by an amount of implantation (dose amount, implantation surface density) to the RESURF layer. If the amount of implantation to the entire RESURF layer is uniform, the optimum implantation amount is about 1×1012 cm−2 for silicon (Si) regardless of the concentration of the semiconductor substrate, and is 1×1013 cm−2 (with an activation rate of 100%) for polytype 4H silicon carbide (SiC). These are referred to as a RESURF condition.
The RESURF structure unfortunately has such a drawback that, in terms of high breakdown voltage resistance, an electric field is concentrated also on the peripheral edge of the RESURF layer. This limits the increasing of breakdown voltage to the avalanche breakdown on the peripheral edge of the RESURF layer. In other words, increasing breakdown voltage with the use of the normal RESURF structure is limited.
This problem can be avoided by gradually reducing the amount of implantation to the RESURF layer toward the outside, as described in Non-Patent Document 1 (or Patent Document 3 or 4). This structure divides the portion in which an electric field is concentrated into a plurality of portions, considerably reducing a maximum electric field inside the semiconductor.
The effects similar to those of Non-Patent Document 1 can be achieved also using the RESURF structure in which the amount of implantation to the RESURF layer is reduced stepwise toward the outside, as described in Patent Documents 1 and 2. In Patent Documents 1 and 2, an electric field is concentrated on the peripheral edge of the high-concentration P-type implantation layer, a boundary between the RESURF layers having different implantation amounts, and the outermost edge of the RESURF layer, and thus, the effect of relaxing an electric field is inferior to Non-Patent Document 1. Compared with the RESURF layer having a single implantation amount in its entirety, meanwhile, the portion in which an electric field is concentrated is divided, and thus, a maximum electric field inside the semiconductor substrate can be reduced.

Semiconductor device having a plurality of electric field relaxation layers and method for manufacturing same


A lubricating oil having an ashless nitrogenous TBN source together with ash containing detergent having a TBN in excess of 100, a source of magnesium, and metal dihydrocarbyl dithiophosphate with predominantly or exclusively secondary hydrocarbyl groups is described. It comprises a major amount of an oil of lubricating viscosity having a sulfated ash content between 0.35 and 2 mass percent and A) a nitrogenous TBN source selected from the group consisting of ashless nitrogen containing dispersants, ashless nitrogen containing dispersant viscosity modifiers, oil soluble aliphatic, oxyalkyl, or arylalkyl amines and mixtures thereof; B) a metal salt of an oil soluble acid having a TBN in excess of 100; C) at least 500 ppm (mass) magnesium; and D) at least one metal dihydrocarbyl dithiophosphate. The nitrogenous TBN source provides at least about 1.5 TBN to the finished lubricant. The metal salt of an oil soluble acid provides at least about 40% of the total TBN of the composition. At least 50 mole per cent of the hydrocarbyl groups on the dithiophosphate are secondary. Overbased magnesium sulfonate may be used as the metal salt of an oil soluble sulfonic acid having a TBN in excess of 100 and the additive providing at least 500 ppm (mass) magnesium. The lubricant may be free of aromatic amines having at least two aromatic groups attached directly to the nitrogen. It may have at least 100 ppm (mass) boron and at least 1000 ppm (mass) phosphorous. The boron-to-nitrogen ratio is at least 0.1.

A crankcase lubricant that performs adequately in one engine at given operating conditions does not necessarily perform adequately when used in a different engine or under different conditions. While theoretically, lubricants could be designed for each possible combination of engine and service condition, such a strategy would be impracticable because many different types of engines exist and the engines are used under different conditions. Accordingly, lubricants that perform well in different types of engines and across a broad spectrum of conditions (e.g. fuel type, operating load, and temperature) are desired. Design of crankcase lubricants is further complicated in that the concentrated mixture of chemicals added to lubricating oil basestocks to impart desirable properties should perform well over a broad range of different quality basestocks. Meeting these requirements has been extremely difficult because the formulations are complicated, tests to ascertain whether a lubricant performs well are extremely expensive and time consuming, and collecting field test data is difficult since variables cannot be controlled sufficiently.
Ever more stringent regulation of vehicle emissions make the task even more challenging. Most recently, in North America the maximum permitted level of sulfur present in over the highway diesel fuel has been lowered to 0.05 wt %. A new API category defined as API CG-4 addresses the performance of heavy duty lubricants with low sulfur fuels. At the same time fuel sulfur levels for off-highway equipment may have a higher level. Furthermore, in some geographical regions such as Latin America, fuel sulfur levels remain high for all applications. Lubricants for use in heavy duty diesel engines therefore need to perform acceptably across a range of sulfur fuel levels.
To meet this need the American Petroleum Institute ("API") issues certification licenses for lubricants that pass a panel of tests designed to verify a lubricant's performance in a variety of engines operated at conditions that have been associated with lubrication problems. In addition to the requirements for API licensing, manufacturers of heavy duty diesel engines periodically have required lubricants to pass additional tests before the lubricant can be approved for use with that manufacturer's engines. Lubricants that meet all the certification requirements of heavy duty diesel engine manufacturers and all the requirements for the highest level of the American Petroleum Institute's oil service classifications for both gasoline fueled engines and heavy duty diesel fueled engines are often referred to as universal oils.
Among the many tests that heavy duty diesel lubricants have been required to pass are the Caterpillar 1G2 and the more recent Caterpillar 1M-PC, 1K, and 1N tests. Acceptability of an oil is based on control of oil consumption and piston deposits (top groove fill, top land heavy carbon, and weighted deposits). Stuck piston rings or distress of the piston, its rings, or its liner will also disqualify an oil. The Caterpillar 1N requires a low sulfur fuel (0.05 wt %) while the 1K uses a fuel with traditional sulfur levels (0.4 wt %).
The Mack T-7 test and its successor the Mack T-8 are part of a panel used to determine acceptability of oils for engines manufactured by Mack Truck Company. The Mack T-7 (the Mack Truck Technical Services Standard Test Procedure N0. 5GT 57 entitled "Mack T-7: Diesel Engine Oil Viscosity Evaluation", dated Aug. 31, 1984) tests soot related viscosity increase in diesel engines.
The Mack T-8 (the Mack Truck Technical Services Standard Test Procedure entitled "Mack T-8: Diesel Engine Oil Viscosity Evaluation", dated October 1993) evolved because the fuel injection timing in some newer engines has been retarded to enable the engines to meet emission requirements. At the same time fuels have been reformulated to have lower sulfur content altering physical and chemical properties of the soot. Some engines designed to run on low sulfur fuel with retarded fuel injection have experienced excessively high soot related viscosity increases, excessively high filter pressure drops, and excessive sludge deposits. The Mack T-8 test runs for 250 hours with an engine operating at 1,800 RPM with an applied load 1010-1031 lb.-ft (1369.4-1397.8 newton-meters). Throughout the test, the soot levels, the differential pressure across the oil filter, and kinematic viscosity of the test fluid are measured. The measured viscosities and soot levels are used to interpolate a viscosity at 3.8 wt % soot level. An oil passes the test if that viscosity differs from the lowest viscosity measured in the test by 11.5 cSt or less. If two tests are run the two results when averaged must be 12.5 cSt or less. If three tests are run the three results when averaged must be less than 13 cSt. An additional requirement includes control of filter pressure differential. The Mack T-8 is much more severe than the Mack T-7 test and requires a higher dispersancy level in the fluid.
Another test required of heavy duty diesel lubricants is the CRC L-38 (ASTM D5119). That test is run on a single cylinder laboratory gasoline engine. It is designed to test a lubricant's ability to prevent corrosion of a bearing made from copper and lead, and to prevent sludge and varnish formation.
Heavy duty diesel engines must also perform satisfactorily in off road conditions. The John Deere Company, a manufacturer of farm equipment, is concerned about high temperature performance of lubricants because oil coolers sometimes become covered with mud. The John Deere 6466A High Temperature Engine Oil Test Procedure (JDQ-78) tests high temperature thermal oxidative oil thickening in a heavy duty diesel engine.
Among the many tests required to meet the API SH classification (and its predecessor the API SG classification) are the Sequence IID (ASTM STP 315h part 1), Sequence IIIE (ASTM D553), and Sequence VE (ASTM D5302). The Seq. IID (ASTM STP 315h part 1) monitors an oil's ability to inhibit rust. It is intended to simulate cold winter conditions for short trip driving when condensation on the valve cover creates a corrosive environment. The Seq. IIIE (ASTM D553) measures high temperature oil thickening, sludge and varnish deposits, and engine wear. The Seq. VE (ASTM D5302) measures the lubricant's ability to prevent deposits and wear encountered during low-temperature, light duty operating conditions. Primary rating factors include measurement of sludge, varnish, and camshaft wear in the engine.
Another factor complicating design of lubricants is the well known problem that an additive, or combination of additives, that improves performance in one respect may make the cost of the lubricant too high or may adversely affect performance in another respect.
Ripple U.S. Pat. No. 5,202,036 describes a formulation designed to pass the Caterpillar 1G2, the Mack T-7, and the CRC L-38 tests. U.S. Pat. No. 5,202,036 uses two parameters to indicate the amount (TBN) and source (metal ratio) of basicity of a given material. Total Base Number, "TBN", is an industry standard used to correlate the basicity of any material to that of potassium hydroxide. The value is reported as mg KOH and is measured according to ASTM D2896. "Metal ratio" is a calculated value that relates the total amount of metal present to number of equivalents of metal required to saturate the anion of the organic acid. If the metal ratio is 1, the amount of metal present is the amount required to saturate the anion of the organic acid. If the metal ratio is greater than 1, metal in excess of that required to saturate the anion is present. The term "overbased" may be used to describe any metal salt of an organic acid having a metal ratio greater than 1 though typically overbased sulfonates will be used at metal ratios in excess of 2.
U.S. Pat. No. 5,202,036, describes a lubricant that has a TBN in the range of 6 to about 15 and has a specifically defined dispersant and an alkali or alkaline earth metal salt of an organic acid having a metal ratio greater than at least about 2 wherein the specifically defined dispersant provides from 0.5 to 1.5 TBN and the metal salt component includes a magnesium salt or salts such that the magnesium salts or salts contribute no more than about 30% of the TBN of the composition. The patent does not address tests required for gasoline fueled engines or the Mack T-8 test.
U.S. Pat. No. 4,941,984 to Chamberlin describes a lubricant intended for use with spark ignited engines fueled by gasoline, alcohol, or mixtures of both. It requires a metal detergent that is either a basic magnesium salt of an organic acid or a basic mixture of alkaline earth metal salts of one or more organic acid wherein at least 50% of the metal is magnesium together with a metal (other than magnesium or calcium) salt of either a substituted succinic acid acylated polyamine or a hydrocarbon substituted aromatic carboxylic acid containing at least one hydroxyl group attached to the aromatic ring. Chamberlin defines "basic" when applied to the magnesium salts as follows: "The basic magnesium salt and other basic alkaline earth metal salts . . . are referred to as basic salts because they contain an excess of magnesium or other alkaline earth metal cation. Generally, the basic or overbased salts will have a metal ratio of about 2 to about 30 or 40." He asserts that his lubricants having high levels of basic (i.e. metal ratio .gtoreq.2) magnesium salts when used in alcohol fueled engines or mixed alcohol/gasoline fueled engines minimize corrosive wear and pre-ignition problems associated with alcohol fueled engines. Chamberlin further asserts that his lubricant can be formulated to qualify for API "SG" classification. The Chamberlin patent is not concerned with the unique problems associated with soot related viscosity increase or piston deposits formed in diesel engines.
Another patent addressing a way to use Group II metal hydrocarbyl sulfonates to achieve high TBN while recognizing that they are deleterious in other respects is EP 277,729 to Rollin. Rollin's formulation includes zinc dithiophosphate having both primary (1.degree.) and secondary (2.degree.) character such that the ratio of primary:secondary is from about 1:1 to about 5:1, a succinimide dispersant; and a TBN in finished oil of at least 8. He states the succinimide is necessary to pass friction tests and the upper limit on the amount of succinimide present does not matter to performance but is determined solely by cost. While Rollin reports a significant number of engine tests, no Mack T-7 results are shown. Nor does he show any test results where the metal salt of a dihydrocarbyl dithiophosphoric acid made from secondary alcohol exceeds the amount made from primary alcohol.
Additional patents relating to the use of zinc dithiophosphates made from specific secondary alcohols and used with specific dispersants are U.S. Pat. Nos. 4,904,401, 4, 957,649, and 4,981,602 all to Ripple.
Despite all the work that has gone before, a need remains for lubricants that perform extremely well in diesel tests that use low sulfur fuel, including the Mack T-8 and the Caterpillar 1N, without compromising performance in the older tests and that deliver the requirements for the highest API classification for lubricants intended to be used in gasoline fueled engines--superior resistance to oxidation, rust, and wear.

Crankcase lubricant for modern heavy duty diesel and gasoline fueled engines