A molding-forming method, a molding mold, and a molding production apparatus with which efficient burrs removal is possible without requiring a large apparatus. A molding production method includes, in addition to a molding being formed inside a mold, burrs formed around the molding are separated from the molding. After formation of the molding, air is blown inside the mold on at least a portion of the burrs formed around the molding to cool the same, a projecting member is projected toward the cooled burrs, and the burrs are separated from the molding. After pressing the burrs toward the projecting member by the air blowing, the burr is pressed toward the mold surface facing the projecting member by projection of the projecting member to separate the burr from the molding.

As a molded body formed by molding a resin material, for example, various air-conditioning duct mounted in an instrument panel of an automobile is known. These air conditioning duct can be easily produced by blow molding a parison extruded from a die of an extruder.
On a molded body (i.e. duct) subjected to blow molded body, a burr is formed around the clamped mold, and burr removal process is essential. In general, removal of the burr after blow molding is often performed using a press machine, and the burr around the mold is collectively removed by punching out the burr using a die corresponding to the outer shape of the molded body.
For example, Patent Literature 1 discloses a blow molding method and a blow molding apparatus for performing blow molding in molds. It is described that the cooling efficiency of the burr is improved by positively contacting the burr with the mold. In blow molding, the burr is punched out by a press machine after the burr is sufficiently cooled, which causes a large loss time and is a factor that impairs productivity. According to the technique described in Patent Literature 1, the time required for a series of step from blow molding to removal of the burr become short, and productivity is improved.

Molding production method, molding die, molding production apparatus, burr removal method, and burr removal device


A surgical retractor includes a body portion and first and second retractor arms operatively coupled thereto. The body portion includes a rotatable knob, a first blade holder, and a first blade. The first blade is configured for axial displacement with the first blade holder and angulation relative to the first blade holder about a first axis. The first and second retractor arms include respective second and third blades detachably secured thereto. The first and second retractor arms are transitionable between an approximated configuration and a spaced apart configuration. The second and third blades are configured to angulate about respective second and third axes that are defined by the respective first and second retractor arms.

Disease, the effects of aging, or physical trauma resulting in damage to the spine has been treated in many instances by fixation or stabilization of the affected vertebra. A wide variety of spinal fixation devices have been employed in surgical procedures for correcting spinal injuries and the effects of spinal diseases.
After a partial or complete discectomy, the normally occupied spaced between adjacent vertebral bodies is subject to collapse and/or misalignment due to the absence of all or a part of the intervertebral disc. In such situations, the physician may insert one or more prosthetic spacers between the affected vertebrae to maintain normal disc spacing and/or the normal amount of lordosis in the affected region.
Typically, a prosthetic implant is inserted between the adjacent vertebrae and may include pathways that permit bone growth between the adjacent vertebrae until they are fused together. As is typical, the intervertebral spaces are accessed either anteriorly or posteriorly. It would be desirable to access the intervertebral spaces via a lateral approach.


A non-transitory storage medium storing a scan program executable by a computer of an image processing device including a communication portion communicable with a scanning device and a storage portion storing a certain program, the scan program, when executed by the computer, causing the image processing device to execute: determining processing in which it is determined whether a pseudo image file is read by the certain program; scan-command transmission processing in which, when the image processing device determines that the pseudo image file is read by the certain program, a scan command is transmitted to the scanning device via the communication portion; scanned-data receiving processing in which the image processing device receives scanned data from the scanning device via the communication portion as a reply to the scan command; and scanned-data writing processing in which the received scanned data is written to the pseudo image file.

1. Field of the Invention
The present invention relates to an information processing device communicable with a scanning device and a non-transitory storage medium storing a scan program executable by a computer of the information processing device.
2. Description of the Related Art
Most of application programs that can be executed by an image processing device such as a personal computer (PC) can call a driver of a device by use of an application programming interface (API). The image processing device provides an output to the driver of the device during execution of the program and performs various operations such as printing using a printer communicable with the image processing device.

Non-transitory storage medium storing scan program and information processing device


A method and apparatus for triggering and measuring electrochemiluminescent phenomena using a voltage waveform applied at the voltammetric working electrode which improves the precision and accuracy of measurements. This waveform has a decreasing scan rate in the range of voltages for which electrochemiluminescence is triggered and is substantially sinusoidal in shape in this range. The waveform results from locating the reference electrode of a potentiostat in close potential proximity to its counter electrode, and applying a uniform scanning voltage waveform at the reference electrode. The waveform also can be synthesized digitally, converted to analog form, and applied directly to the working electrode with the reference electrode in close potential proximity to the working electrode.

Measurement techniques for electrochemiluminescence (ECL) derive from electrochemistry (EC) and chemiluminescence (CL). EC deals generally with the relation of electricity to chemical changes and with the interconversion of chemical and electrical energy.
CL based assay or detection techniques generally comprise forming a mixture of a sample containing an unknown amount of an analyte of interest with a known amount of a reactant which is conjugated with a chemiluminescent label. The mixture is incubated to allow the labeled reactant to bind to the analyte and then is separated into a bound and an unbound fraction. One or both fractions are caused to luminesce by, for example, the addition of an oxidant to the fractions. The measured level of chemiluminescence at a specific wavelength is indicative of the amount of the bound or unbound fraction, and one skilled in the art can determine from such measurements the amount of analyte in the sample.
ECL detection techniques provide a sensitive and controllable measurement of the presence and amount of an analyte of interest. In ECL, the incubated sample is exposed to a voltammetric working electrode, i.e., an electrode to which a voltage is applied and into which a current for a redox reaction is passed. The ECL mixture does not react with the chemical environment alone, as does the CL mixture, or with an electric field alone, as in EC, but rather electrochemiluminescence is triggered by a voltage impressed on the working electrode at a particular time and in a particular manner to controllably cause the ECL sample to emit light at the electrochemiluminescent wavelength of interest. The measurement is not the current at the electrode, as in EC, but the frequency and intensity of emitted light.
The operating conditions affecting an ECL measurement should be controlled from sample to sample before and during each measurement. A knowledge of these operating conditions is necessary to provide measurement results which are reproducible within useful limits. Because of the complexity of these conditions, however, and because the specific nature of all the chemical changes and reactions occurring during ECL is not completely known, there are substantial difficulties in reaching this goal.
Employees of the present assignee, under an obligation of assignment to it, have found that techniques which improve the measurement of current in EC do not necessarily improve the measurement of the frequency and intensity of light emitted during ECL. The optimal conditions for ECL measurements must meet different criteria.
The voltage waveform impressed upon the voltammetric electrode of an ECL cell must be sufficient to trigger electrochemiluminescence. This voltage waveform usually is in the form of a uniform voltage sweep starting at a first voltage, moving steadily to a second voltage, moving back through the first voltage to a third voltage and then back again to the first voltage. Other waveforms have been applied in practice, however, and can trigger ECL.
In order to be meaningful, the ECL measurement must be precise, i.e., repeatable within strict limits with the same operating conditions and ECL sample. The measurement also must be accurate, i.e., within acceptable limits of the actual concentration of analyte present in the sample. Since the ECL reaction chemically changes the sample, only one ECL measurement generally can be taken for each sample. These chemical changes occur predominantly within a thin layer of the sample adjacent the working electrode.
Precision and accuracy are sensitive to, among other things, the voltage waveform impressed upon the working electrode to trigger electrochemiluminescence. Although an optimal waveform may exist theoretically for a given sample and operating conditions, achieving this waveform is difficult because of the multiplicity of factors affecting the ECL response. The present inventors have found, however, that certain modifications in conventional waveforms, apparatus and techniques, which effectively diminish the extent to which this waveform is controlled at its operative point adjacent the working electrode, unexpectedly increase the quality of an ECL response and the precision and accuracy of its measurement.

Method and apparatus for conducting electrochemiluminescent measurements


A motorcycle construction permits a rider to assume either a first, elevated crouched racing position, or a second lowered, reclined, feet-forward “custom chopper” position. The motorcycle includes a main frame assembly having a front wheel suspension assembly and a set of handlebars, and a rear wheel suspension assembly with a rear wheel, and a combined engine/transmission assembly. The main frame has a seat for a driver, and a driver footpeg assembly. The footpegs provide a fore position for use with the reclined “custom chopper” position, allowing the driver's legs to be extended in a forward direction for using the fore footpeg position. The footpegs provide an aft position for use with the elevated crouched racing position. A seat moving assembly moves the driver seat between the first elevated position, used with the aft footpeg position, and the second, lowered seat position is used with the fore footpegs position.

This invention relates to a motorcycle being adjustable with respect to seat elevation and footpeg positions with the purpose to accommodate for at least two widely different riding positions and body postures. The motorcycle of the invention may thus be adapted to widely different requirements on the combined "man and machine" when a change in driving environments changes from e.g. a sharply curved road under high speed racing-like driving conditions, to less demanding driving conditions, e.g. slow driving along a straight avenue. The purpose of driving a motorcycle may vary according to the user in question, but many drivers would like to be able to vary between driving fast in a more or less crouched position, and driving with style and doing so in a relaxed manner. Almost all drivers would give priority to driving safely. The motorcycle of the invention provides it all, a racing-like motorcycle including mechanical features allowing the machine to be altered into a laid-back custom cruiser motorcycle for comfortable riding, or vice versa, while rendering particularly foot braking and foot gear shifting control to the rider without interruption.

Motorcycle for adjustable riding postures


A device for ventilating electronic and electrical equipment, subassemblies and components, which are placed in casings, cabinets and subassembly carriers. The device is particularly suitable for slide-in fan modules, which are equipped with axial flow fans and positioned at a relatively small distance from a reception space for the electrical and electronic equipment, etc. to be ventilated. Between the objects to be cooled and the fan unit is provided an air distribution plate, which has punched out air passage openings. In order to achieve a diffuser action and partial direction change of an air volume flow, air deflecting surfaces with a predeterminable inclination and in clearly defined areas are formed by a punching and bending process.

Known slide-in fan modules generally have axial flow fans with vertically oriented fan axes and upper air exit sides. The slide-in fan modules are provided with a cover, which in the vicinity of air exit faces has circular openings.
As a result of a relatively large hub area, in the centre of the axial flow fan and in regions between and outside the air exit faces, so-called "dead areas" arise, in which there is no or only a limited air flow. These "dead areas" have a particularly disadvantageous effect in means or systems, where the slide-in fan modules, in order to save installation space, are positioned at a very limited distance from a reception space with the equipments, subassemblies, components or other objects to be cooled or ventilated. Hot spots can then be formed, which give rise to problems or even to the failure of an equipment, subassembly, etc.
EP 470 926 A1 discloses a ventilation means for consoles equipped with printed circuit boards, in which at least one cooling air-sucking in blower is provided spaced from a reception space for parallel circuit boards. On the lower guide elements engages an air distribution plate, which is placed in the grid of guide elements for the minimum circuit board openings for the blower cooling air flow. Between the blower outlet or an upper edge of a fan slide-in module and the air distribution plate, a storage capacity is formed on the underside of the guide elements where, as a result of the minimum openings and baffles located therein, a pressure is formed, which is intended to lead to a uniform, directed flow. As a result of the height of the storage capacity, which roughly corresponds to that of the fan, an equalizing section is defined. A disadvantage associated therewith is the reduction of the installation space of a cabinet, frame or casing, which is contrary to the constantly increasing demand for an optimum utilization of the installation space.
DE 34 17 451 C2 discloses a slide-in casing constructed for EMC shielding and ventilation from two-shell plates. Each shell is provided with vent openings, which have a slot-like construction and in the case of two adjacent shells are not aligned with one another, which leads to a wave-like flow of the air passing through. The casing is made from plastic and is provided on the inside and/or outside with an electrically conductive coating.
An electrical device with thermally highly loaded electrical components of plate-like carriers described in DE-OS 1 908 825 has cooling lines between the components, which are fixed to the carrier plates in such a way that their slot-like exit openings are directed onto the components.
U.S. Pat. No. 4,214,706 discloses a cooling system for equipment cabinets and circuit boards and subassemblies arranged therein, which has a ventilation chamber with a rectangular cross-section. The outer walls of the ventilation chamber, which are directed towards the circuit boards and electrical sub-assemblies, have elongated openings. To obtain a uniform pressure in the ventilation chamber connected with a frontally positioned blower, a partition with round holes is provided, so that two partial chambers are formed.

Means for the ventilation of electrical and electronic equipment and subassemblies

Knuerr-Mechanik fur die Electronik Aktiengesellschaft


An integrated air conditioner, including a condenser casing to house a condenser and a condenser fan therein, the condenser casing including a front plate, an upper cover extending from an upper edge of the front plate, and a plurality of hinges integrally provided between the front plate and the upper cover, spaced apart from at regular intervals, wherein the upper cover rotates around the hinges be perpendicular to the front plate.

1. Field of the Invention
The present invention relates, in general, to integrated air conditioners, and, more particularly, to an integrated air conditioner having a condenser casing which prevents noise from being generated, and prevents a condenser fan from being damaged or broken, due to contact between the condenser casing and the condenser fan.
2. Description of the Related Art
Typically, air conditioners are classified into two types, the two types being integrated air conditioners and separate-type air conditioners. In the integrated air conditioners, an evaporator, a condenser, and a compressor are installed in a cabinet. On the other hand, in the separate-type air conditioners, the evaporator is installed in an indoor unit, which is placed in a room, while the condenser and the compressor are installed in an outdoor unit, which is placed outside the room.
The cabinet of the integrated air conditioner is partitioned into a first interior chamber, which is placed in the room, and a second interior chamber, which is placed outside the room, by a partition which is vertically arranged in the cabinet. In this case, the evaporator is placed in the first interior chamber, while the condenser and the compressor are placed in the second interior chamber. Further, a cooling fan is placed in the first interior chamber to draw the indoor air into the cabinet and pass the indoor air through the evaporator to be cooled prior to discharging the cool air to the room. A condenser fan is placed in the second interior chamber to draw outdoor air into the cabinet and pass the outdoor air through both the condenser and the compressor prior to discharging the air to the outside, thus cooling the condenser and the compressor.
A condenser casing, which houses the condenser fan and the condenser therein, is also placed inside the second interior chamber. The condenser casing functions to guide air from the condenser fan through the condenser to the outside so that the condenser is effectively cooled.
A conventional condenser casing includes a front plate, two side plates, and an upper cover. The front plate, the two side plates, and the upper cover are integrally formed as a single structure to receive the condenser fan and the condenser in the condenser casing. The upper cover has a thin folding line part at a position which is spaced apart from the front plate by a predetermined distance. The upper cover is bent along the folding line part so that the condenser is installed under the upper cover having a predetermined length.
When the condenser casing having the front plate, the side plates, and the upper cover is prepared, a bending part of the upper cover, corresponding to a rear portion of the folding line part, stands upright to define an opening at a rear section of the upper cover between the two side plates in such a state, the condenser fan and the condenser are installed into the condenser casing, through the defined opening, between the two side plates. Thereafter, the bending part is bent downward and rearward until the bending part is placed horizontally, on a plane with the rest of the upper cover, and a rear end of the bending part is held on an upper surface of the condenser.
However, in the conventional condenser casing, the folding line part of the upper cover is continuously formed from a first side edge to a second side edge of the upper cover, and the condenser fan is installed under the folding line part. Thus, when the bending part of the upper cover is bent horizontally, and the rear end of the bending part is held on the condenser, after the condenser fan and the condenser are installed into the condenser casing through the opening defined between the two side plates, a residual stress in the structure of the upper cover may be generated and remain in the folding line part. Therefore, a portion around the folding line part is apt to sag.
Due to the sagging of the folding line part of the upper cover, the portion around the folding line part may come into contact with the condenser fan. When the condenser fan is rotated in such a state, noise is generated due to the contact between the condenser fan and the portion around the folding line part which sags. Cracks may also be generated in the condenser fan, resulting in damage or breakage of the condenser fan.

Integrated air conditioner having condenser casing


A heat-resistant endless resin belt including a heat-resistant resin sheet, which can be employed in a thermal fixing apparatus, wherein the sheet includes two cutting work parts in an inclined shape. The two parts are overlapped with each other and bonded with an adhesive to form a bonding part. An external shape displacement f(x), measured via a flatness measuring apparatus, which scans the belt in a width direction thereof, satisfies a following formula

1. Technical Field
This disclosure relates to a heat-resistant endless resin belt, a manufacturing method thereof and an image forming apparatus using the heat-resistant endless resin belt. The heat-resistant endless resin belt, serving as a fixing belt or an intermediate transfer belt, may be employed in complex machines such as a copying machine, a facsimile, a printer, etc.
2. Description of the Related Art
In recent years, an image forming apparatus for color printing has been employed extensively and high-speed printing has been developed.
Compared with black-and-white printing, when color printing is performed, because adhered toner is larger in amount at one time, high pressure and high temperature are applied to a recording paper when the recording paper is passed through nip portions between rollers.
When the high-speed printing is developed, further high heat resistance and mechanical strength are required of an endless belt, which passes through nip portions.
The endless belt, for example can be made from polyimide resin.
As one method for manufacturing the endless belt, there is proposed a method of performing cast molding to provide polyimide varnish on an outer peripheral surface of a cylinder made of a metal, and thereafter obtaining a polyimide endless belt by heating and imidizing the resultant polyimide varnish whereto the cast molding is performed. (For reference, see Japanese Application Publication Number Hei7-295396)
However, the above-mentioned manufacturing method may cause the following two main problems. One of the problems is that the imidation process is time-consuming, which incurs a cost increase. The other is that a plurality of molds are required because a new mold is needed whenever the dimensional standard is altered, which increases an initial cost.
In view of the above problems, a manufacturing technique of an endless resin belt at a low cost is proposed (For reference, see Japanese Application Publication Number Hei11-291348). To be specific, the polyimide endless belt is manufactured by adhering a non-thermoplastic polyimide film and a thermoplastic polyimide resin sheet together, whereafter the thermoplastic polyimide resin sheet is melted and bonded.
However, for one thing, it is difficult to make a film thickness of an overlapped portion of a resin film and sheet to be virtually the same as a non-overlapped portion of the film and sheet. For another, bonding without altering a hardness and a surface property of the two sheets cannot be easily executed in practice. Consequently, when a fixed image is formed by the finally manufactured resin belt, there is a problem that a streaky defective image is generated.
It is also proposed that an endless resin belt can be manufactured via forming a groove-like protrusion and recess in a thickness direction at both ends of a polyimide resin sheet, whereafter fitting the protrusion in the recess and bonding (For reference, see Japanese Application Publication Number Hei10-698).
The problem with the aforementioned resin belt which is processed at both ends and is joined by an adhesive (a joined belt will be used hereinafter) lies in the circumferential length accuracy of the belt, which remains to be solved hereafter.
Although the circumferential length accuracy may differ according to specification standards of the image forming apparatus whereto the resin belt is applied and a diameter of the resin belt, the circumferential length accuracy of the resin belt is preferably approximately equal to or less than 0.05 mm.
In particular, when the circumferential length accuracy differs in a width direction of the belt (the axial direction wherein the endless resin belt is stretched), the belt skews, which is transcribed by the recording paper upon printing. Consequently, wrinkling is present on the recording paper.
In addition, when the image forming apparatus is in operation and the belt is in contact with a heat roller and a pressure roller, a perimeter distribution poses a problem of belt skew, which probably causes local shaving of the belt inner surface.
Thus, in order to maintain image quality, it is important to enhance the circumferential length accuracy, namely flatness, in the axial direction of the heat-resistant resin belt which constitutes the image forming apparatus.
There is proposed a flatness measuring method to measure the flatness of the heat-resistant endless belt (For reference, see Japanese Application Publication Number 2007-58059). To be specific, the seamless belt is stretched by a predetermined tensile force via at least two rollers and is set in a non-rotating state. The flatness is measured via surface scanning. In accordance with this method, in order to solve the problem arising at the time of image forming, the flatness is limited to be equal to or less than 5 mm throughout the seamless belt.
However, in the case of the endless resin belt joined at the both ends, various flatness patterns arise, which is rather different from the case with the seamless belt. Therefore, even if the flatness is limited to be equal to or less than 5 mm, the problem that the wrinkling is unalterably transcribed to the recording paper remains unsolved.

Heat-resistant resin belt, manufacturing method thereof and image forming apparatus

Abstract: ∫        0        x                                                                        f                                            (                x                )                                      -                          g                                            (                x                )                                                                                                                  ⅆ          x                      ≤          XL      6800        ,wherein “X” (mm) is a length of the belt in a width direction thereof; “L” (mm) is a perimeter of the belt and “g(x)” represents a displacement of an ideal shape of the heat-resistant resin belt, when g(x)=C (a constant), a left side of the formula is set to be a minimum; whilst when g(x) is a variable, the displacement of the ideal shape of the belt is set.


The method for establishing a connection by a HNB comprising steps of: the HNB transmitting an “attachment request” message to an operation and maintenance center (OMC); the OMC transmitting an “attachment response” message to the HNB; the HNB establishing a connection with an MME indicated by the “attachment response” message. With the method proposed in the present invention, a UE can switch between HNBs in the same CSG through interface X2. Meanwhile, such information as the radio resource management and so on can be exchanged between two HNBs.

A system structure of System Architecture Evolution (SAE) is illustrated in FIG. 1. The system structure of SAE in FIG. 1 is described as following.
User Equipment 101 (hereinafter referred to as UE) is a terminal device used to receive data. 102 EUTRAN, also called ENB, is a radio access network of the LTE SAE, for providing interface through which an LTE mobile station accesses the radio network. Through interface S1, EUTRAN connects to a mobility management entity (MME) 103 and a user plane entity Serving Gateway (S-GW) 104 in the mobile station. 103 MME is adapted for managing mobile context, session context for the UE, and holding user information on security. 104 Serving Gateway primarily provides a function of user plane. An interface S1-MME is adapted for establishing radio access bearer, forwarding messages from UE to MME through a wireless access network. The combination of 103 MME and 104 Serving Gateway is similar to the original 106 SGSN (general packet radio service (GPRS) supporting node). It is possible that both MME and Serving Gateway locate at the same physical entity. 105 PDN Gateway is adapted for the functions like accounting, legally monitoring, etc. And it is possible that both the Serving Gateway and the PDN Gateway locate at the same physical entity. 106 SGSN provides routing for data transmission in existing UMTS. An existing SGSN finds a corresponding gateway GPRS supporting node (GGSN) according to an access point name (APN). 107 HSS is a home subscription sub-system for the UE and is adapted for storing user information such as the current location of UE, address of the serving node, security information on the user, activated packet data protocol (PDP) context for the UE and so on. 108 PCRF provides QoS policy and accounting rules through interface S7.
In general, a user data stream reaches the 104 Serving Gateway through 105 PDN Gateway. Then, through the GPRS tunnel protocol (GTP) channel, data is sent by the Serving Gateway to the ENB where the UE locates in, and now it is sent by the ENB to corresponding UE.
HNB refers to a Node B applied in a home. It also can be applied in such site as a university, a company and so on. HNB is a plug and play device. Difference between an HNB and a general macro node B is that: in general not all UEs can access an HNB. For example, only the UEs in a user's home or that are allowed to access the HNB can access the corresponding HNB. And for the HNB in a company, only the company's staff and its allowed partners can access the HNB. The HNB group (e.g., the HNB in a company) bearing the same access subscriber cluster is called CSG (closed subscriber group). No interface X2 (interface between Node Bs in SAE) exists between general HNBs (e.g., the HNBs in homes) or between an HNB and a macro Node B. Through interface S1, a UE switches between HNBs or between an HNB and a macro Node B.
For an HNB applied in a company or university or the like, a UE frequently moves between two HNBs in the same company. In this case, the switch is always implemented through interface S1 so that great delay causes and efficiency is very poor. In addition, information such as radio resource management and so on can not be exchanged between two HNBs in the same company so that resources can not be utilized effectively.

Method for establishing connection by HNB


A three-dimensional flash memory is provided, and technique to suppress interference caused by an inter-cell insulation layer in a vertical cell and to form a stable vertical channel layer, a technique to reduce a length of wire than a conventional three-dimensional flash memory for overcoming problems of deterioration of chip characteristics such as operation speed and power consumption and difficulty of wiring technique in the manufacturing process, and a technique to improve horizontal density of channel layers and ONO layers are proposed.

A flash Memory device may be an electrically erasable programmable read only memory (EEPROM) and may be commonly used for, for example, a computer, a digital camera, an MP3 player, a game system, a memory stick, and the like. The flash memory electrically controls input/output of data by Fowler-Nordheim (F-N) tunneling or hot electron injection.
The flash memory device has been high-capacity by continuous scaling to be used as a storage memory in various fields. Currently, it is expected to mass-produce 32 Gbit products of 30 nm class, and it is expected to be scaled to below 10 nm with floating gate technology.
For achieving high integration of the flash memory device, it is necessary to replace a two-dimensional structure with a three-dimensional structure. A NAND flash memory device may connect memory cells in a string form without a need for contact formation per memory cell, which is advantageous for implementing various three-dimensional structures in a vertical direction. Accordingly, a three-dimensional NAND flash memory has been recently studied in various ways.
For example, referring to FIG. 19 illustrating an array of a conventional three-dimensional flash memory, the array of three-dimensional flash memory may include common source lines CSL, bit lines BL, and a plurality of cell strings CSTR between each common source line CSL and each bit line BL.
The bit lines are arranged in two dimensions, and the plurality of cell strings CSTR are connected in parallel thereto. The cell strings CSTR may be commonly connected to the common source line CSL. That is, the plurality of cell strings CSTR may be disposed between the plurality of bit lines and one common source line CSL. In this case, the common source line CSL may be plural and the plurality of common source lines CSL may be two-dimensionally arranged. Here, the same voltage may be applied to the plurality of common source lines CSL, or each of the plurality of common source lines CSL may be electrically controlled.
Each of the cell strings CSTR may include a ground select transistor GST connected to the common source line CSL, a string select transistor SST connected to the bit line BL, and a plurality of memory cell transistors MCT between the ground and string select transistors GST and SST. In addition, the ground select transistor GST, the string select transistor SST, and the memory cell transistors MCT may be connected in series.
The common source line CSL may be commonly connected in common to sources of the ground select transistors GST. In addition, the ground select line GSL, the plurality of word lines WL0 to WL3, and the plurality of string select lines SSL, which are disposed between the common source line CSL and the bit lines BL, may be used as electrode layers of the ground select transistor GST, the memory cell transistors MCT, and the string select transistors SST, respectively. In addition, each of the memory cell transistors MCT includes a memory element.
Meanwhile, for meeting high performance and low price demanded by consumers, the conventional three-dimensional flash memory may allow cells to be vertically stacked to increase integration.
For example, referring to FIG. 20 illustrating a structure of a conventional three-dimensional flash memory, the conventional three-dimensional flash memory is manufactured to allow an electrode structure 2015, in which interlayer insulating layers 2011 and horizontal structures 2040 are formed on a substrate 2000, alternately and repeatedly. The interlayer insulating layers 2011 and the horizontal structures 2040 may extend in a first direction. For example, each of the interlayer insulating layers 2011 may be a silicon oxide layer, and the lowermost interlayer insulating layer 2011a of the interlayer insulating layers 2011 may have a thickness thinner than those of the other interlayer insulating layers 2011. Each of horizontal structures 2040 may include first and second blocking insulating layers 2042 and 2043 and an electrode layer 2045. The electrode structure 2015 may be provided in plurality, and the plurality of electrode structures 2015 may be disposed to face each other in a second direction crossing the first direction. The first and second directions may correspond to an x-axis and a y-axis of FIG. 2, respectively. A common source line CSL of a highly doped impurity region, which is disposed between the plurality of electrode structures 2015 to be spaced apart from the plurality of electrode structures 2015 may extend in a vertical direction. The vertical direction may correspond to a z-axis.
Vertical structures 2030 penetrating the electrode structure 2015 may be disposed. As an example, in plan view, the vertical structures 2030 may be arranged in a matrix form aligned along the first and second directions. As another example, the vertical structures 2030 may be aligned in the second direction, but may be disposed in a zigzag shape in the first direction. Each of the vertical structures 2030 may include a passivation layer 2024, a charge storage layer 2025, a tunnel insulation layer 2026, and a channel layer 2027. For example, the channel layer 2027 may be disposed in a hollow tubular shape, and in this case, a buried layer 2028 may be further disposed to fill an inner portion of the channel layer 2027. A drain region "D" is disposed on the channel layer 2027 and a conductive pattern 2029 is formed on the drain region "D" to be connected to a bit line BL. The bit line BL may extend in a direction crossing the horizontal electrodes 2045, for example, in the second direction. For example, the vertical structures 2030 aligned in the second direction may be connected to one bit line BL.
The first and second blocking insulating layers 2042 and 2043 included in the horizontal structure 2040 and the charge storage layer 2025 and the tunnel insulating layer 2026 included in the vertical structures 2030 may be defined as an oxide-nitride-oxide (ONO) layer which is a storage information element of the three-dimensional flash memory. That is, some of the information storage elements may be included in the vertical structures 2030 and the other information storage elements may be included in the horizontal structures 2040. In an example, the charge storage layer 2025 and the tunnel insulating layer 2026 of the information storage element may be included in the vertical structures 2030 and the first and second blocking insulating layers 2042 and 2043 may be included in the horizontal structures 2040.
Epitaxial patterns 2022 may be disposed between the substrate 2000 and the vertical structures 2030. The epitaxial patterns 2022 connect the substrate 2000 to the vertical structures 2030. The epitaxial patterns 2022 may be in contact with at least one layer of horizontal structures 2040. That is, the epitaxial patterns 2022 may be disposed to be in contact with the lowermost horizontal structure 2040a. According to another embodiment, the epitaxial patterns 2022 may be disposed to be in contact with a plurality of layers, for example, two layers of the horizontal structures 2040. Meanwhile, when the epitaxial patterns 2022 are disposed to be in contact with the lowermost horizontal structure 2040a, the lowermost horizontal structure 2040a may be thicker than the other horizontal structures 2040. The lowermost horizontal structure 2040a in contact with the epitaxial patterns 2022 may correspond to the ground selection line GSL of the array of the three-dimensional flash memory described with reference to FIG. 19 and the other horizontal structures 2040 in contact with the vertical structures 2030 may correspond to the plurality of word lines WL0 to WL3.
Each of the epitaxial patterns 2022 has a recessed sidewall 2022a. Accordingly, the lowermost horizontal structure 2040a in contact with the epitaxial patterns 2022 is disposed along a profile of the recessed sidewall 2022a. That is, the lowermost horizontal structure 2040a may be disposed in an inward convex shape along the recessed sidewall 2022a of each epitaxial pattern 2022.
In the conventional three-dimensional flash memory of the above-described structure, because circuit elements such as a transistor, a diode, or a capacitor for the electrode structure 2015 are formed on the substrate 2000 below the electrode structure 2015, as the number of stages in which the horizontal structures 2040 are vertically stacked increases, a length of wires also may become longer, and thus problems such as deterioration of chip characteristics such as operation speed and power consumption may occur and difficulties in wiring technology may be expected in a manufacturing process.
Accordingly, the following embodiments provide a technique for overcoming the above-mentioned problems and difficulties by reducing a length of the wire.
Meanwhile, referring to FIG. 10 illustrating a structure of a conventional three-dimensional flash memory, the conventional three-dimensional flash memory cell includes a channel layer 1010 extending in one direction, an oxide-nitride-oxide (ONO) layer 1020 extending in one direction to surround the channel layer 1010, a plurality of electrode layers 1030 stacked to be perpendicular to the ONO layer 1020, and a plurality of interlayer insulating layers 1040 disposed alternately with the plurality of electrode layers 1030.
A plurality of three-dimensional flash memory cells of the above-described structure are provided to constitute a three-dimensional flash memory. When the three-dimensional flash memory includes two cells as shown in the drawing, two ONO layers 1020 and 1021 included in the conventional three-dimensional flash memory are not adjacent to each other and are spaced apart by a specific distance or more. Accordingly, the two channel layers 1010 and 1011 are also not adjacent to each other and are spaced apart by a specific distance (e.g., an inter-surface distance 1050 between the two channel layers 1010 and 1021 is 100 nm apart).
Therefore, the conventional three-dimensional flash memory has a disadvantage in that horizontal integration of the channel layers 1010 and 1011 and the ONO layers 1020 and 1021 are inferior, and thus it is necessary to propose a technique for solving the problem.
In addition, as the three-dimensional flash memory is integrated at a high stage, there is a process problem in manufacturing a vertical hole. To this end, scaling of each vertical cell is important and a pitch between the vertical cells is very important to reduce a thickness of the electrode layer between the horizontal cells and a thickness of the insulation layer between the vertical cells. Meanwhile, it is difficult to reduce the thickness of the electrode layer in the horizontal direction due to a short channel effect problem and it is difficult to reduce the thickness of the insulating layer in the vertical direction because there is a problem in that inter-cell interference effect is large and the cell characteristics are degraded.
In general, an insulating layer of a silicon oxide layer and a silicon nitride layer is used as the interlayer insulating layer, and the layer has a dielectric constant of 3.9 to 7.5.
Therefore, there has been a problem that, the interference effect of neighboring cells becomes a major obstacle to the pitch scaling of the vertical cells due to the dielectric constant of the interlayer insulating layer during cell operation.
In addition, as the three-dimensional flash memory is integrated at a high stage, a large process problem occurs in manufacturing the vertical hole. Currently, as the number of vertical cells is increased, a vertical step is gradually increased such as the vertical step of about 3 um in the vertical cells having 64 stages and the vertical step of about 4 um in 100 stages.
Therefore, considering a hole size of 70 nm to 100 nm, it is difficult to form a vertical polycrystalline silicon channel having a very large aspect ratio (A/R) after a deposition process of polycrystalline silicon (poly-silicon). In addition, when the vertical step is increased, the vertical hole is formed ununiformly in some vertical region or the hole size is changed in the vertical direction during forming the vertical hole, thereby affecting cell characteristics (e.g., cell Vth change).
Accordingly, a stable vertical polycrystalline silicon formation method and a differentiated chip operation method for vertical cells having different hole sizes are required to secure stable vertical cell characteristics in high-stage three-dimensional NAND flash memories of 100 or more stages.

Three-dimensional flash memory with reduced wire length and manufacturing method therefor


A method for identifying an area of a chip to be probed proceeds as follows. A callout list of failures is obtained from a tester, the list including cell name and pin for each failure. A Def file is interrogated to locate a Def entry matching the cell name, and a cell type, cell location, and cell orientation data is obtained for the cell from the Def file. A Lef file is then interrogated to locate a Lef entry matching the cell type, and the coordinates of the pin are obtaining from the Lef file. A GDS file is interrogated to locate a GDS entry matching the cell type, and the coordinates of polygons listed in the GDS entry are obtained. The coordinates of the pin are then crossed with the coordinates of the polygons to identify overlapping area. The overlapping area is defined as the location to be probed. A driving signal is applied to a stage to align a prober with the location to be probed.

1. Field of the Invention
The present invention relates to an apparatus and method for finding exact locations for probing integrated circuits.
2. Description of the Related Art
Probing systems have been used in the art for testing and debugging integrated circuit (IC) designs and layouts. Various laser-based systems for probing IC's are known in the prior art. In these prior art systems, the DUT (device under test) is driven by an electrical test signal, while a laser beam is used to illuminate the DUT. The laser beam then reflects from the DUT, and the reflection is perturbed according to the DUT's response to the electrical test signals. The reflected beam is then converted to an electrical signal having a waveform corresponding to the reflected beam. This waveform is displayed for the user's analysis.
Some of the test and debug technique used in the prior art include LIVA (Light Induced Voltage Alteration), TIVA (Thermally Induced Voltage Alteration), CIVA (Charge Induced Voltage Alteration), XIVA (Externally Induced Voltage Alteration), OBIC (Optical Beam Induced Current), OBHIC (Optical Beam Heat Induced Current), and OBIRCH (Optical Beam Induced Resistance Change). These techniques probe the DUT to detect a change in the characteristics of certain devices or structures therein to thereby detect a failure or an area that is prone to fail or adversely affect the DUT's performance. According to these techniques, the DUT is driven by an electrical signal, while a laser beam is used to illuminate the DUT to thereby cause either heating, carrier generation, or both. As a result, the electrical output from the DUT is perturbed, and this perturbation is detected and analyzed. That is, under these techniques the laser beam is used only as a perturbing agent, but the detection is done by analyzing the electrical output from the DUT.
Other probing techniques are based on the observation that active devices, such as transistors, emit light upon switching of state. In these systems, the DUT is also energized by test vectors, but no light is used to illuminate the DUT. Rather, an optical system is used to collect the faint light that is emitted upon the switching of the transistor being probed. This techniques is generally referred to in the industry as time-resolved emission (TRE) or time-resolved photon emission (TRPE). A system for performing TRPE probing is commercially available under the trade name EmiScope™ from Credence Systems, Inc. of Milpitas, Calif.
As is known in the art, in order to probe the DUT and obtain meaningful analysis, the location of the probed devices must be specified as accurately as possible. This is especially true for TRPE, as the location from which emission emanates is very small, so that accurate placement of the collection optics is imperative for proper emission collection and proper identification of the device that emits the photons.
FIG. 1 is a schematic of prior art method of identifying probing locations on a DUT. In order to test a DUT, first test patterns (also referred to as test vectors) are generated by an automatic test pattern generator, ATPG 105. The test patterns are then fed to the automated testing equipment (also referred to as automated testing and evaluation) ATE 110. The ATE feeds the test vectors to the DUT, 145, and tests the electrical response of the DUT to the test patterns. The ATE then generates a log of fail results, 115, identifying scan chains and test patterns having failures. The log, 115, is then input to an analysis tool, 120, which performs fault simulation using the log so as to determine potential cells or pins that may be faulty. As is shown by the broken-line double arrow, some commercially available ATPG's contain mechanism to also perform the analysis, so while two separate tools are shown, the generation of test vectors and the analysis of the fail log can be done by the same tool. The analysis tool performs fault simulation to determine potential causes for the fault and then outputs a callout log, 125, which lists all of the cell names and related pins that are likely to result in detection of failures.
The cells and pins identified in the callout list may not be the actual cause of the failures. Therefore, it is a practice in the art to use a debug tester, such as a TRPE tool to investigate the actual cause for the fault. For that purpose, the callout log is used to determine which locations to probe with the TRPE tool. That is, using the callout list a debug engineer needs to perform various manual procedures, 150, to determine where to place the prober. The manual procedure involve reviewing various design databases, 130, reviewing the layout vs. schematic, LVS 135, and reviewing layout designs, 140, so as to provide the results, 160, normally in terms of the coordinates of the corner of the cell to be probed.
As can be understood, the methods used in the prior art to arrive at probing locations are tedious and time consuming. Additionally, in most instances only the coordinates of the corner of the cell to be investigated is obtained, and the prober needs to be scanned over the cell to find the actual proper location for probing. Therefore, there is a need in the art for an automated system that provides more detailed information regarding the locations to be probed.

System and method for determining probing locations on IC


In a light control device for a vehicle, a control portion determines whether an illuminance detected by an illuminance sensor reaches a first reference illuminance, and performs a turning on or off control of lights of the vehicle based on the determined result. When the control portion receives an external environment change signal from an environment change detecting means, the control portion uses a second reference illuminance higher than the first reference illuminance, instead of the first reference illuminance, and performs the turning on or off control when the illuminance detected by the illuminance sensor reaches the second reference illuminance. Accordingly, vehicle lights can be suitably turned on or off in accordance with an external environment of the vehicle.

A conventional vehicle light control device described in JP-A-10-315844 includes an upper side illuminance sensor for detecting an external illuminance at an upper side of the vehicle, and a control portion for controlling turning on or off operation of vehicle lights. The control portion determines whether or not the illuminance detected by the upper side illuminance sensor reaches a predetermined reference illuminance, and controls the turning on or off operation based on this determination.
Furthermore, this vehicle light control device includes a vehicle speed sensor for detecting a vehicle speed, and a light condition setting means. As the vehicle speed increases, the light condition setting means increases the reference illuminance, and decreases a delay time. Here, the delay time is a time from a determination time where it is determined whether or not the detected illuminance reaches the reference illuminance up to an illumination time of the vehicle lights.
Accordingly, when the vehicle runs at a high speed, the reference illuminance is high and the delay time is short. Therefore, when the vehicle runs under an elevated bridge at a high speed, the lights may be momentarily turned on and off, and a passenger in a leading vehicle or an oncoming vehicle may mistakenly feel this turning on or off operation as a passing.
Furthermore, lights provided around an entrance and an exit of a tunnel are generally brighter compared with lights provided inside the tunnel in order to reduce a drastic change in lighting between the inside and the outside of the tunnel on an expressway. Thus, the headlights of the vehicle may be not instantly turned on based on the vehicle speed even when the vehicle enters the tunnel. As described above, in this vehicle light control device, because the reference illuminance and the delay time are controlled by the vehicle speed, it is difficult to suitably control the vehicle lights in accordance with the exterior environment of the vehicle, due to the control being based on the vehicle speed.


In a semiconductor memory including a dynamic random access memory, a memory cell of the dynamic random access memory includes: a semiconductor pillar (a silicon pillar); a capacitor in which one side of the silicon pillar is used as a charge accumulation electrode; and a longitudinal insulated gate static induction transistor in which the other side of the silicon pillar is used as an active region (a source region, a channel formation region and a drain region), and a bit line is connected to the silicon pillar.

1. Field of the Invention
The present invention relates to a semiconductor memory and a method of manufacturing the same, and more particularly relates to a dynamic random access memory that is a semiconductor memory with capacitors and a method of manufacturing the same.
2. Description of Related Art
A dynamic random access memory (hereafter, referred to as DRAM) of a semiconductor memory is provided with single cell transistor 211 and single capacitor 221, as shown in FIG. 11A. A gate of the cell transistor 211 is connected to a word line 231. Further, one diffusion layer of the cell transistor is connected to a bit line 241, and the other diffusion layer of the cell transistor 211 is connected to one electrode of the capacitor 221. Furthermore, the other electrode of the capacitor is connected to a plate electrode.
A memory cell of single-transistor-single-capacitor type having the above mentioned configuration is widely used since it has an advantage over other memory devices in achieving a higher degree of integration. However, there is always demands for even higher degree of integration in DRAM. Enormous efforts have been tried to advance miniaturization of such memory cells.
As a typical DRAM cell, a stack type capacitor cell and a trench type capacitor cell have been put to practical use until now. However, in order to form the memory cells of these types, it is inevitable that their structures become more complex if further reduction of cell area is attempted.
The DRAM memory comprises: a capacitor for accumulating memory charge, a transistor for receiving and outputting the charge, a bit line that is connected to the transistor for writing and reading data, and a word line to control on/off switch action of the transistor. In the DRAM memory cell, major development effort has been spent on how to reduce its cell size.
The reduction of the cell size while maintaining a required amount of the charge to be accumulated in the capacitor of the cell is one of most important issues of the development. Instead of a memory cell in which a capacitor is formed in a flat layout referred to as a planer type, the above mentioned cell structures such as the trench type, the stack type or the like are employed to make the capacitor structure three-dimensional in order to increasing the amount of charging capacitance within a smaller area size. Furthermore, as a material having a higher dielectric constant, for example, tantalum oxide (Ta2O5) and the like are used as an insulation film of the capacitor.
It is popular to use memory cells configured with a folded bit line system as shown in FIG. 11B. Such memory cells have been known to share a higher noise resistance characteristic found in conventional cell read-out operation. However, it is also known that the minimum memory cell area can not be less than 8F2 in such memory cell if the minimum machining dimension is assumed to be F. In order to attain less memory cell size, it is desirable to employ a layout configuration referred to as an open bit line system. FIGS. 11B, 11C show connection diagrams of the memory cells having configurations of the folded bit line system and the open bit line system, respectively.
As shown in FIG. 11, in memory cells with the folded bit line system, memory cells 201, each of which comprises the cell transistor 211 and the capacitor 221, are arranged so as to be connected to every other line of the word lines 231 between the bit lines 241. Further, the memory cells 201 are arranged so as to be connected to every other line of the bit lines 241 between word lines 231.
As shown in FIG. 11C, in memory cells with the open bit line system, the memory cell comprises the cell transistor 211 and the capacitor 221 and arranged so as to be connected to each word line 231 between the bit lines 241.

Semiconductor memory and method of manufacturing the same


A simulcast system (FIG. 16) capable of synchronizing and maintaining synchronization of a plurality of base sites (1602, 1604, 1606, 1608) is coupled to a transmitter controller (226). The plurality of base sites (1602, 1604, 1606, 1608) is capable of transmitting data as radio frequency transmission at substantially the same time. A generator (1808) generates time marks (1708) at a predetermined time period (T). A data divider (1812) divides data into predetermined packets to be interposed between at least a pair of time marks. The data packets (1704) and time marks (1708) are transmitted to the plurality of base sites (1602, 1604, 1606, 1608). The plurality of base sites (1602, 1604, 1606, 1608) includes base site receivers (1603, 1605, 1607, 1607) for receiving the data packets (1704) and time marks (1708) and clocks (1611, 1613, 1615, 1617) for measuring the time (T) between each pair of time marks. Base sites controller (1612, 1614, 1616, 1618) determine when there are variations in time between any pair of time marks and the predetermined time period (T). Timers adjust the delay time at each of the plurality of base sites (1602, 1604, 1606, 1608) in response to variation in time between time marks at the corresponding base site, and delay retransmission of data from the receipt of a start command (1706) by a predetermined delay time determined for each of the plurality of base sites to enable the retransmission of data at substantially the same time by the plurality of base sites (1602, 1604, 1606, 1608).

A number of methods have been proposed or are in use today for automatically synchronizing the message transmissions of transmitters utilized in simulcast transmission systems. These methods of synchronizing the plurality of transmitters require a substantial amount of time to complete a propagation delay measurement sequence. For a large simulcast transmission system, such as one having forty transmitters, delay measurement times of forty seconds and more were typical when each transmitter was sequentially accessed for measuring the individual transmitter propagation delay. One method of reducing the synchronization time is to divide the simulcast system into the smaller transmission regions, the delays were then simultaneously measured for regional transmitters in alternate transmission regions thereby reducing the total time required to synchronize transmissions within the system. This method of measurement of the transmitter delays, although it speeded up the delay measurement process, presented a new set of problems for measuring the delays required to synchronize the transmitters in adjacent transmission regions.
Generally, to synchronize simulcast transmitters, the propagation delay times must be measured for the plurality of transmitters in order to account for difference in propagation delays. Once synchronization is achieved, the synchronization must continually be maintained because of oscillator drift. Incorporating high accuracy clocks in the plurality of transmitters is an expensive option that requires a substantial amount of air time to be devoted to periodic resynchronizing the plurality of clocks located at each of the transmitters to ensure that the clocks are accurately synchronized for the simulcast transmission of the data.
Thus, what is needed is a method and apparatus for maintaining the synchronization of the plurality of transmitters in a simulcast transmission system that is cost effective and does not require a substantial amount of air-time to be devoted to maintaining synchronization periodically.

Method and apparatus for maintaining synchronization in a simulcast system


Semiconductor devices and methods for producing semiconductor devices to be produced by conducting a combination of a step for producing a gate elctrode of a first conductor layer which is piled on a gate insulator, a step for producing a drain region which is connected with an n.sup.+ -region located under the gate electrode by employing the gate electrode as a part of the mask, and a step for piling, on or over the gate electrode, a second conductor layer connected with the n.sup.+ -region through a contact hole produced in the gate electrode.

This invention relates to an improvement applicable to semiconductor devices and methods for producing a semiconductor device. More specifically, this invention relates to an improvement applicable to static random access memories (hereinafter referred to as SRAMs) e.g. a high resistance load type SRAM and a thin film transistor (hereinafter referred to as a TFT) load type SRAM.
An SRAM is classified into a high resistance load type SRAM and a TFT load type SRAM. These SRAMs are involved with various fundamental problems to be further removed, the fundamental problems including e.g. connection of a driver transistor and a load.
A method for producing a high resistance load type SRAM will be described below.
FIGS. 1 through 7 are cross-sectional views of a semiconductor wafer illustrated for describing the process for producing a high resistance load type SRAM available in the prior art. FIGS. 8 through 13 are plan views of a semiconductor wafer corresponding to FIGS. 1 through 7. The cross section of the cross-sectional views is shown by Y--Y line illustrated in FIG. 13.
Referring to FIG. 1, the LOCOS process is conducted to produce a field insulator layer 2 having a thickness of e.g. 4,000 .ANG. on selected areas of a p.sup.- -Si substrate 1. Si.sub.3 N.sub.4 mask layer (not shown) employed for the LOCOS process is removed, and the active regions are exposed. The surface of the active region is oxidized to produce a gate insulator layer 3 having a thickness of e.g. 100 .ANG. on the active region. The gate insulator layer 3 is selectively removed to produce a contact hole 3A by conducting a wet etching process which employs hydrofluoric acid as the etchant.
Referring to FIGS. 2 and 8, a chemical vapor deposition process (hereinafter referred to as a CVD process) is conducted to produce a first poly crystalline silicon layer 4a having a thickness of e.g. 1,500 .ANG.. A gaseous phase diffusion process is conducted to introduce n-type impurities (e.g. phosphorus and arsenic) into the p.sup.- -Si substrate, and an n.sup.+ -region 5' containing n-type impurities by e.g. 1.times.10.sup.21 cm.sup.-3 is produced.
Referring to FIG. 3, a reactive ion etching process (hereinafter referred to as RIE process) is conducted to selectively pattern the first poly crystalline silicon layer 4a for the purpose to produce a gate electrode 4 which actually acts as a wire line or a gate electrode of a driver transistor. A mixture of CCl.sub.4 gas and O.sub.2 gas is employed as the etching gas of the RIE process. An ion implantation process is conducted to introduce arsenic ions (n-ions) into the p.sup.- -Si substrate 1, and a source region 5 and a drain region 6 are produced.
Referring to FIG. 4 and FIG. 9, a CVD process is conducted to produce an SiO.sub.2 layer 7 having a thickness of e.g. 1,000 .ANG.. A RIE process is conducted to produce a contact hole 7A for a ground line shown in FIG. 9. For this RIE process, a resist mask is employed, and a mixture of CHF.sub.3 gas and He gas is employed as the etching gas. A CVD process is conducted to produce a second poly crystalline silicon layer, having a thickness of e.g. 1,500 .ANG. which is patterned into a ground line 8 by conducting a RIE process in which a mixture of CCl.sub.4 gas and O.sub.2 gas is employed as the etching gas.
Referring to FIGS. 5 and 10, a CVD process is conducted to produce an SiO.sub.2 layer 9 having a thickness of e.g. 1,000 .ANG.. A RIE process is conducted to produce a contact hole 9A for a load resister, in the SiO.sub.2 layers 9 and 7. A mixture of CHF.sub.3 and He is employed as the etching gas for the RIE process.
Referring to FIG. 6, a CVD process is conducted to produce a third poly crystalline silicon layer having a thickness of e.g. 1,500 .ANG.. Arsenic ions (n-ions) are selectively introduced to the region which is scheduled to be the feeder of a positive power supply V.sub.cc and a region at which a high resistance load contacts with the gate electrode 4. For this ion implantation process, a resist mask is employed and a preferable dosage and a preferable acceleration energy are respectively 1.times.10.sup.15 cm.sup.-2 and 30 KeV. A RIE process is conducted to pattern the third poly crystalline silicon layer for the purposes to produce a contact part 10, a high resistance load 11 and a feeder 12 of the positive power supply V.sub.cc. A mixture of CCl.sub.4 gas and O.sub.2 gas is employed as the etching gas of this RIE process.
Referring to FIGS. 7 and 11, a CVD process is conducted to produce an insulator layer 13 consisting of an SiO.sub.2 layer having a thickness of e.g. 1,000 .ANG. and a phosphosilicate glass layer having a thickness of e.g. 5,000 .ANG.. A reflow process is conducted to make the surface of the insulator layer 13 flat. A resist process and a RIE process are conducted to produce contact holes 13A for a bit line, in the insulator layer 13.
Referring to FIGS. 7 and 12, a sputtering process is conducted to produce an Al layer having a thickness of e.g. 1 micrometer, and a photolithography process is conducted to pattern the Al layer for the purpose to produce a bit line 14. The significance of the elements e.g. BL etc. which are shown in FIGS. 7 and 12 but are not discussed above will be clear, when FIG. 14 is referred to.
FIG. 13 is the plan view of a finished high resistance load type SRAM produced by the process described above, referring to FIGS. 1 through 12 and the same emblems as were employed in FIGS. 1 through 12 are employed also in FIG. 13. For the simplicity's sake, however, the bit line 14 shown in FIGS. 7 and 12 are not illustrated in FIG. 13.
FIG. 14 is an equivalent circuit of the high resistance load type SRAM produced by the process described above, referring to FIGS. 1 through 13.
Referring to FIG. 14, Q.sub.1 and Q.sub.2 indicate driver transistors, Q.sub.3 and Q.sub.4 indicate transfer gate transistors, R.sub.1 and R.sub.2 indicate high resistance load, WL indicates a word line, BL and /BL indicate bit lines, S.sub.1 and S.sub.2 indicate nodes, V.sub.cc indicates a positive power supply, and V.sub.ss indicates a negative power supply.
The function of the foregoing high resistance load type SRAM will be described below.
The positive power supply V.sub.cc is selected to be 5 V and the negative power supply V.sub.ss is selected to be 0 V. Supposing the voltage of the node S.sub.1 is 5 V and the voltage of the node S.sub.2 is 0 V, the transistor Q.sub.2 is ON and the transistor Q.sub.1 is OFF. Provided the transistor Q.sub.1 is OFF and the resistance thereof is sufficiently higher than that of the high resistance load R.sub.1, the voltage of the node S.sub.1 is kept at 5 V. On the other hand, provided the transistor Q.sub.2 is ON and the resistance thereof is sufficiently less than that of the high resistance load R.sub.2, the voltage of the node S.sub.2 is kept at 0 V.
This operation is, however, involved with a drawback wherein a DC current whose intensity is inverse proportional to the resistance of the high resistance load R.sub.2, flows from the positive power supply V.sub.cc toward the negative power supply V.sub.ss.
Since the quantity of the memory cells integrated in one chip of the foregoing high resistance load type SRAM increases following an increase in integration, the total power consumption of one chip increases, unless the power consumption of a memory cell is decreased. Therefore, the foregoing DC current is required to be decreased. To satisfy this requirement, the value of the high resistance load R.sub.2 and R.sub.1 is required to be increased. In the case where this resistance is increased, however, the potential of the node connected to the driver transistor which is then OFF, S.sub.1 in this case, can hardly be kept stable.
For the purpose to remove the foregoing drawbacks, a TFT load type SRAM was developed.
A method for producing a TFT load type SRAM will be described below.
FIGS. 15 through 23 are cross-sectional views of a semiconductor wafer illustrated for describing the process for producing a TFT load type SRAM available in the prior art. FIG. 24 is a plan view of a TFT load type SRAM. The cross section of the cross-sectional views is shown by Y--Y line illustrated in FIG. 24.
Referring to FIG. 15, the LOCOS process is conducted to produce a field insulator layer 2 having a thickness of e.g. 4,000 .ANG. on selected areas of a p.sup.- -Si substrate 1. Si.sub.3 N.sub.4 mask layers (not shown) employed for the LOCOS process are removed, and the active areas are exposed. The surface of the active area is oxidized to produce a gate insulator layer 3 having a thickness of e.g. 100 .ANG. on the active area. The gate insulator layer 3 ia selectively removed to produce a contact hole 3A by conducting a wet etching process which employs hydrofluoric acid as the etchant.
Referring to FIG. 16, a CVD process is conducted to produce a first poly crystalline silicon layer 4a having a thickness of e.g. 1,500 .ANG.. A gaseous phase diffusion process is conducted to introduce phosphorus (n-type impurities) into the p.sup.- -Si substrate, and an n.sup.+ -region 6A containing n-type impurities by e.g. 1.times.10.sup.21 cm.sup.-3 is produced.
Referring to FIG. 17, a RIE process is conducted to pattern the first poly crystalline silicon layer 4a for the purpose to produce a gate electrode 4 which actually acts as a wire line or the gate electrode of a driver transistor. A mixture of CCl.sub.4 gas and O.sub.2 gas is employed as the etching gas of the RIE process. An ion implantation process is conducted to introduce arsenic ions (n-ions) into the p.sup.- -Si substrate 1, and a source region 5 and a drain region 6 are produced.
Referring to FIG. 18, a CVD process is conducted to produce an SiO.sub.2 layer 7 having a thickness of e.g. 1,000 .ANG.. A RIE process is conducted to produce a contact hole 7A (See FIG. 24) for a ground line. A CVD process is conducted to produce a second poly crystalline silicon layer, which is patterned into a ground line 8 by conducting a RIE process in which a mixture of CCl.sub.4 gas and O.sub.2 gas is employed as the etching gas.
Referring to FIG. 19, a CVD process is conducted to produce an SiO.sub.2 layer 9 having a thickness of e.g. 1,000 .ANG.. A RIE process is conducted to produce a contact hole 9A in the SiO.sub.2 layers 9 and 7. For the process, a resist mask (not shown) is employed and a mixture of CHF.sub.3 and He is employed as the etching gas.
Referring to FIG. 20, a CVD process is conducted to produce a third poly crystalline silicon layer having a thickness of e.g. 1,500 .ANG.. Phosphorus ions (n-ions) are introduced in the third poly crystalline silicon layer. A preferable dosage and a preferable acceleration energy are respectively 1.times.10.sup.15 cm.sup.-2 and 20 KeV. A RIE process is conducted to pattern the third poly crystalline silicon layer to produce a gate electrodes 15 of a TFT, which acts as loads of a TFT load type SRAM. For this RIE process, a resist mask is employed, and a mixture of CCl.sub.4 and O.sub.2 is employed as the etching gas.
Referring to FIG. 21, a CVD process is conducted to produce an SiO.sub.2 layer 16 having a thickness of e.g. 300 .ANG., the SiO.sub.2 layer 16 acting as the gate insulator layer of the TFT. A drain contact hole 16A is produced by applying a wet etching process to the SiO.sub.2 layer 16.
Referring to FIG. 22, a CVD process is employed to produce a fourth poly crystalline silicon layer having a thickness of e.g. 500 .ANG.. An ion implantation process is conducted to introduce boron (n-type impurities) into the regions where sources and drains of a TFT are scheduled to be produced and where the feeder of the V.sub.cc power supply is scheduled to be produced. The ion implantation process is conducted with the dosage of 1.times.10.sup.14 cm.sup.-2 and the acceleration energy of 5 KeV. The region where the feeder of the V.sub.cc power supply is scheduled to be produced is illustrated in FIG. 24. A RIE process is conducted to pattern the fourth poly crystalline silicon layer, and the source region 17, the drain region 18 and channel region 19 of the TFT, and the feeder of the V.sub.cc power supply are produced. A mixture of CCl.sub.4 gas and O.sub.2 gas is employed as the etching gas for the RIE process.
Referring to FIG. 23, a CVD process is conducted to produce an insulator layer 21 consisting of an SiO.sub.2 layer (lower layer) having a thickness of e.g. 1,000 .ANG. and a PSG layer (upper layer) having a thickness of e.g. 5,000 .ANG.. A reflow process is conducted to make the surface of the PSG layer flat. A RIE process is conducted to produce a contact hole for a bit line, on the insulator layer 21. For this RIE process, a resist mask is employed, and a mixture of CHF.sub.3 and He is employed as the etching gas. A sputtering process is conducted to produce an Al layer having a thickness of e.g. 1 micrometer. Thereafter, a photolithography process is employed to produce a bit line 22.
FIG. 24 is a plan view of a finished TFT load type SRAM produced by the process described above, referring to FIGS. 15 through 23, and the same emblems as were employed in FIGS. 15 through 23 are employed also in FIG. 24. For the simplicity's sake, however, the bit line 22 shown in FIG. 23 are not illustrated in FIG. 24.
FIG. 25 is an equivalent circuit of the TFT load type SRAM produced by the process described above, referring to FIGS. 15 through 23, and the same emblems as were employed in FIGS. 15 through 23 are employed also in FIG. 24.
Referring to FIG. 25, Q.sub.1 and Q.sub.2 indicate driver transistors, Q.sub.3 and Q.sub.4 indicate transfer gate transistors, Q.sub.5 and Q.sub.6 indicate load TFTs, WL indicates a word line, BL and /BL indicate bit lines, S.sub.1 and S.sub.2 indicate nodes, V.sub.cc indicates a positive power supply, and V.sub.ss indicates a negative power supply.
The function of the foregoing TFT load type SRAM will be described below.
The positive power supply V.sub.cc is selected to be 5 V, and the negative power supply V.sub.ss is selected to be 0 V. Supposing the voltage of the node S.sub.1 is 5 V and the voltage of the node S.sub.2 is 0 V, the transistor Q.sub.2 is ON, the transistor Q.sub.6 is OFF, the transistor Q.sub.1 is OFF and the transistor Q.sub.5 is ON. Provided the transistor Q.sub.1 is OFF and the resistance thereof is sufficiently higher than that of the transistor Q.sub.5 which is ON, the voltage of the node S.sub.1 is kept at 5 V. On the other hand, provided the transistor Q.sub.2 is ON and the resistance thereof is sufficiently less than that of the transistor Q.sub.6 which is OFF, the voltage of the node S.sub.2 is kept at 0 V.
Under the foregoing conditions, the resistance of the load transistors Q.sub.5 and Q.sub.6 varies following the memorized information. Therefore, a TFT load type SRAM is allowed to memorize information more stably than a high resistance load type SRAM. Since the channels of the load TFTs Q.sub.5 and Q.sub.6 are made of poly crystalline silicon layers and the crystal quality thereof is much worse than that of single crystalline silicon, however, the load TFTs Q.sub.5 and Q.sub.6 are inclined to allow leak current to flow, even under OFF condition. Since a leak current increases the power consumption of a memory chip, the TFTs are required to be made small in size.
FIG. 23 shows that the TFT load type SRAM described above has channels of the load TFTs below bit lines 22 made of the Al layers which is the top layer, remaining the insulator layers 21 including PSG layers therebetween.
This layer configuration allows the Al layers (the bit lines 22) to function as a gate electrode in combination with the insulator layer 21 which functions as a gate insulator layer, resultantly forming a parasitic transistor. Since the potential of the bit line 22 (the gate electrodes of the parasitic transistors) varies between 0 V (V.sub.ss) and 5 V (V.sub.cc ), the transistors Q.sub.6 which are to be OFF become almost ON, resultantly considerably increasing the leak current flowing therein.
For the purpose to remove this drawback, a double gate structure TFT load type SRAM was developed.
This double gate structure TFT load type SRAM has a fifth poly crystalline silicon layer which constitutes an upper gate electrode which have the same pattern as the third poly crystalline silicon layer namely the gate electrode 15 of the load TFT of the TFT load type SRAM described referring to FIGS. 15 through 25, the fifth poly crystalline silicon layer being arranged between the fourth poly crystalline silicon layer which constitutes the source region 17, the drain region, the channel region 19 etc. and the Al bit line 22, resultantly solving the problem.
FIGS. 26 through 28 are cross-sectional views of a semiconductor wafer illustrated for describing the process for producing a double gate structure TFT load type SRAM available in the prior art. The description for the process until the step in which the source region 17, the drain region 18, the channel region 19 of the TFT and the feeder of the V.sub.cc power supply is almost same as the description for the process for producing a TFT load type SRAM. Therefore, the following description will be limited to the steps which follow the foregoing steps.
Referring to FIG. 26, a CVD process is conducted to produce an SiO.sub.2 layer 23 having a thickness of e.g. 500 .ANG.. A RIE process is applied to the SiO.sub.2 layer 23 to produce a contact hole 23A which reaches the fourth poly crystalline silicon layer or the drain region 18 of the TFT.
Referring to FIG. 27, a CVD process is conducted to produce a fifth poly crystalline silicon layer having a thickness of e.g. 1,000 .ANG.. A thermal diffusion process is conducted to introduce phosphorus (n-type impurities) into the fifth poly crystalline Si layer. As a result, the fifth poly crystalline Si layer becomes to contain n-type impurities by e.g. 1.times.10.sup.21 cm.sup.-3. A RIE process is applied to the fifth poly crystalline Si layer to produce an upper gate electrode 24 of the TFT. A mixture of CCl.sub.4 gas and O.sub.2 gas is employed as the etching gas for this RIE process.
Referring to FIG. 28, a CVD process is conducted to produce an insulator layer 25 consisting of an SiO.sub.2 layer having a thickness of e.g. 1,000 .ANG. and a PSG layer having a thickness of e.g. 5,000 .ANG.. A reflow process is conducted to make the surface of the PSG layer flat. A RIE process is applied to the insulator layer 25 to produce a contact hole for a bit line. For this RIE process, a resist mask is employed, and a mixture of CHF.sub.3 and He is employed as the etching gas. A sputtering process is conducted to produce an Al layer having a thickness of 1 micrometer. A photolithography process is applied to the Al layer to produce a bit line 26.
The foregoing TFT load type SRAM or the foregoing double gate structure TFT load type SRAM is allowed to stably function with a small power consumption, when it is produced as is designed. The process for producing either of them is, however, involved with some steps difficult to conduct as are required, including the step for connecting the drain and the gate of a driving transistor.
FIGS. 29 through 32 illustrate cross-sectional views of a semiconductor wafer, the cross-sectional views being illustrated for describing the steps for connecting the drain and the gate of the driver transistor of an SRAM and for clarifying drawbacks inevitably accompanying the foregoing steps.
Referring to FIG. 29, a field insulator layer 2 and a gate insulator layer 3 are produced on a p.sup.- -Si substrate 1 by conducting processes described above for the prior art. A photoresist layer 30 having an opening of the pattern for a contact hole. The contact hole 3A is produced by applying a wet etching process to the gate insulator layer 3, employing the photoresist mask 30. The photoresist layer 30 is removed by employing an O.sub.2 plasma etching process. During this process, the surface of the Si substrate 1 is slightly oxidized.
Referring to FIG. 30, the thin SiO.sub.2 layer produced during the O.sub.2 plasma etching process is removed, before a first poly crystalline silicon layer 4a is produced by conducting a CVD process. A gaseous phase diffusion process is conducted to introduce phosphorus (n-type impurities) into the first poly crystalline silicon layer 4a and the selected area of the top region of the Si substrate 1. As a result, n.sup.+ -region 6A is produced.
Referring to FIG. 31, a RIE process in which a resist mask is employed is applied to the first poly crystalline silicon layer 4a to pattern it, and a gate electrode 4 is produced.
During this process, the surface of the Si substrate 1 is exposed, and a recess 1A unexpectedly turns out to be produced.
Referring to FIG. 32, an n.sup.+ -source region 5 (not shown) and an n.sup.+ -drain region 6 are produced by employing an ion implantation process, by which arsenic ions are introduced into the top surface of the Si substrate 1.
The foregoing description has clarified that the prior art process is involved with two drawbacks. The one is that since an SiO.sub.2 layer unexpectedly produced during the O.sub.2 plasma etching process conducted for removing the photoresist layer 30 must be removed by employing a wet etching process, the gate insulator layer 3 is damaged. Since the gate insulator layer 3 is thin, the dielectric strength thereof is decreased. The other is that a recess 1A is unexpectedly produced on a part of the top surface of the Si substrate 1 during the RIE process conducted to produce the gate electrode 4. If the recess 1A is deep, the resistance of the path connecting the drain region 6 and the gate electrode 4 becomes large.
It is known that a protection layer of a poly crystalline silicon layer arranged to cover a gate insulator layer 3 is effective to prevent the foregoing damage and the resultant decline in dielectric strength from occurring for the gate insulator layer 3.
FIGS. 33 through 35 are cross-sectional views of a semiconductor wafer illustrated for describing the other steps for connecting the drain and the gate of the driver transistor of an SRAM and for clarifying drawbacks inevitably accompanying the foregoing steps.
Referring to FIG. 33, a field insulator layer 2 and a gate insulator layer 3 are produced on a p.sup.- -Si substrate 1 by conducting the process described above for the prior art. A protection layer 31 of a first poly crystalline silicon layer is produced on the gate insulator layer 3 by conducting a CVD process. A photoresist layer 30 has an opening of the pattern for a contact hole. A contact hole 3A is produced by conducting a RIE process conducted with assistance by the resist mask 30 and employing a mixture of CCl.sub.4 and O.sub.2 as the etching gas for Si and a wet etching process conducted employing hydrofluoric acid as the etchant for SiO.sub.2.
Referring to FIG. 34, the photoresist layer 30 is removed by conducting an O.sub.2 plasma etching process. During this process, the surface of the Si substrate 1 is slightly oxidized. The thin SiO.sub.2 layer produced during the O.sub.2 plasma etching process is removed by employing hydrofluoric acid, before a second poly crystalline silicon layer 4b is produced by conducting a CVD process. A gaseous phase diffusion process is conducted to introduce phosphorus (n-type impurities) into the second poly crystalline silicon layer 4b and the top region of the Si substrate 1. As a result, n.sup.+ -region 6A is produced.
Referring to FIG. 35, a RIE process in which a resist mask is employed is applied to the second poly crystalline silicon layer 4b and the protection layer 31 to pattern them, and a gate electrode 4 is produced.
During this process, the surface of the Si substrate 1 is exposed, and a recess 1A unexpectedly turns out to be produced. An n.sup.+ -source region (not shown) and an n.sup.+ -drain region 6 are produced by conducting an ion implantation process by which arsenic ions are introduced.
The foregoing description has clarified that the foregoing improved process wherein a protection layer 31 is arranged between the gate insulator layer 3 and the second poly crystalline silicon layer 4b, has removed a drawback wherein the gate insulator layer 3 is damaged by a wet etching process which is conducted to remove the thin SiO.sub.2 layer which was unexpectedly produced during the O.sub.2 plasma etching process which was inherently to remove the photoresist layer 30.
However, since the process for producing the gate electrode 4 is involved with two independent regions, one of which is the region from which both the first poly crystalline Si layer (the protection layer 31) and the second poly crystalline Si layer 4b are required to be removed and the other of which is the region from which the second poly crystalline Si layer 4b alone is required to be removed, the depth of the recess 1A becomes larger in the foregoing case described referring to FIGS. 33 through 35 than in the case described referring to FIGS. 29 through 32. Therefore, the resistance of the path connecting the drain region 6 and the gate electrode 4 becomes very large, and the path turns out discontinued by some chance. This is a serious drawback which can never be ignored.
Therefore, the first object of this invention is to provide a semiconductor device, wherein the dielectric strength of the gate insulator is not damaged during the production process thereof.
The second object of this invention is to provide a semiconductor device, wherein no recess is produced for the path connecting the drain region 6 and the gate electrode 4 during the production process thereof.
The third object of this invention is to provide a semiconductor device, wherein the dielectric strength of the gate insulator is not damaged and no recess is produced for the path connecting the drain region 6 and the gate electrode 4 during the production process thereof, the production process having less steps.
The fourth object of this invention is to provide a method for producing a semiconductor device, wherein the dielectric strength of the gate insulator is not damaged during the process.
The fifth object of this invention is to provide a method for producing a semiconductor device, wherein no recess is produced for the path connecting the drain region 6 and the gate electrode 4 during the process.
The sixth object of this invention is to provide a method for producing a semiconductor device, wherein the dielectric strength of the gate insulator is not damaged and no recess is produced for the path connecting the drain region 6 and the gate electrode 4 during the process.

Semiconductor device and method for producing semiconductor device


A system, method, and computer program product are provided for managing user access credentials in a computer network. In use, a Security Asset Repository (SAR) is maintained on a first computer connected to a network, the SAR being operable for storing user access credentials to resources on the network. Additionally, a first program residing on a second computer connected to the network is executed by a user, the user having first user access credentials for accessing the second computer. Responsive to executing of the first program, the SAR is accessed by the first program, by employing second user access credentials provided to the first program by the user. Responsive to accessing the SAR by the first program, the first program retrieves third user access credentials from the SAR, the third user access credentials being operable for accessing the SAR by a third computer. Responsive to retrieving the third user access credentials from the SAR, the first program executes a second program residing on the third computer connected to the network, and provides the third user access credentials to the second program. Responsive to providing the third user access credentials to the second program, the SAR is accessed by the second program by employing the third user access credentials, and the second program retrieves fourth user access credentials from the SAR, the fourth user access credentials being operable for accessing resources on the network other than the SAR.

A program requiring network access to a repository of security assets needs to obtain credentials that are required to authenticate to the repository. For interactive programs these can be obtained by prompting the user for the credentials, such as a password or key. For non-interactive programs, such as daemon programs running on server hosts, this becomes difficult.
Sometimes a hardware security module or smart card can be used to store the credentials, but a hardware based solution presents its own problems in terms of cost and hardware compatibility issues, and often requires a PIN to access the device that holds the key or password used to authenticate. Additionally, hardware based solutions may not be an option in a cloud environment. A common solution is to persist the credentials outside of the security asset repository, which undermines the point of having such a repository and creates additional security asset management problems.
There is thus a need for addressing these and/or other issues associated with the prior art.

System, method, and computer program for managing user access credentials in a computer network