A method for timing analysis of a circuit design includes, for each group of one or more instances of a cell of a cell library in the circuit design, determining timing related data for the group according to circuit context of the group in the design. The context includes at least one of a path depth, an output load, and an input slew rate. The determined timing related data are applied to analyze the circuit design.

This invention relates to analysis of timing variation for integrated circuit design.
Static Timing Analysis (STA) is a method for determining timing performance of a digital circuit without requiring the use of simulation patterns (circuit simulation with patterns of input signals). Based on generally the same principals as PERT or critical path analysis, a typical application of STA considers all possible paths through a digital circuit, and predicts whether or not the overall circuit can perform at a given clock speed relative to the underlying manufacturing processes which will be used to produce the chip.
STA is performed with respect to a timing path. A timing path can be considered to have three elements: a data path, a launch clock and a capture clock. The data path is a specific path through combinational elements (also referred to below as a logic elements or logic cells) from the output of one register (e.g., the q or not q output) to the data input of another register. The path through each combinatorial element is considered with respect to an input signal (i.e., rising, falling), and a specific timing arc through that element. For instance, in a representative logic cell with two inputs, A and B, and one output, X, there is a timing arc from input A to output X and another arc from input B to output X. Furthermore separate arcs are specified for when A or B is rising or falling, and there may be conditional arcs depending on the state of another input. For example, a unique arc between A to X might be specified as "from A to X when A is falling and B is low." When timing data are generated for such a cell, each arc can be characterized uniquely using a deterministic numerical simulation, for instance, using SPICE (the industry standard circuit simulator—transistor models tell the circuit simulator how each transistor behaves), for a particular choice of parameters (e.g., transistor model parameters) characterizing the cell.
The launch clock is the path that feeds the clock pin of the first register in the data path, and is measured with respect to the trigger edge or level of clock. This effectively "launches" the data from the first register down the data path.
The capture clock feeds the clock pin of the second register in the path, and is measure with respect to the capture cycle of the clock—such that data arrives at the register and is properly read in.
The launch and capture clocks are typically derived from a common clock signal, for example, from a common point in a branching clock distribution tree.
A timing path (i.e., comprising a data path and launch and capture clocks) is evaluated relative to a timing constraint. A timing constraint is a defined, for instance, in terms of an ability of a register (e.g., flop, latch, etc.) to properly capture the data value from the data path. Other examples of timing constraints relate to state transitions such as reset, clear, etc. but for simplification this discussion focuses on data related timing constraints.
A constraint is generally defined in terms of a timing window of the clock to capture data. Data must be stable at the input of the flop before the active edge of the clock (set up) and stay stable until the trailing edge (hold). If the data signal does not arrive in time (i.e., sufficiently prior to the clock edge), then it may not get latched in (setup). If the data signal changes during the active window, then it will be 'metastable' and the value cannot be trusted (hold). The amount of positive or negative time relative to the constraint is called timing slack. Positive slack is good. Negative slack, which reflects inadequate setup or inadequate hold, is bad, and is generally considered to be a design violation which should be avoided to produce high yields of functioning fabricated circuits.
When STA evaluates a timing path, it tries to find the worst case conditions in order to expose a timing violation. When STA is used to try to find a hold violation (i.e., data does not stay stable during the clock period), it tries to find the earliest arrival of the data signal at the capturing register and latest arrival of the clock edge at that register to capture the data. Conversely, when STA is used to try to find a set-up violation (i.e., data does not arrive in time before the capture clock), then it tries to find the latest the data arrives and the earliest the capture clock triggers the capture of the data.
As introduced above, a model of a cell has a set of parameters, which determine the timing of the cell with respect to each potential arc through that cell, and each parameter has a range that is expected for that parameter based on fabrication and/or environmental (e.g., temperature) variation. Timing of a chip is generally evaluated relative to manufacturing "corners," which are combinations of parameter values with each value at either a maximum or minimum of the expected range for that parameter. As is discussed further below, some parameters are "global" and assumed to take on the same value for all cells in a circuit, and some parameters are "local" and assumed to represent local variation that is independent from transistor to transistor in the circuit, generally modeled as zero-mean random variables. In the discussion below, a "corner" may be a "total corner", which reflects an extreme value for all parameters (local and global), or may be a "global corner", which reflects an extreme value for all global parameters and typical (i.e., zero) values for all the local parameters. Without qualification, in the discussion below, a "corner" generally refers to "total corner."
Generally, one corner is determined (e.g., via deterministic numerical simulation) to be the "fast" corner in that delay through logic cells are expected to be lowest with the corresponding parameter values, and one corner is determined to be the "slow" corner in which delays are expected to the greatest. When timing of a circuit is analyzed at different corners, different problems will generally be exposed. For example, hold violations typically occur at the fast corner, while set-up violations typically happen at the slow corner.
Process models are created by measuring semiconductor foundry manufacturing statistics at a given process node (e.g., 28 nanometer). These manufacturing data are in turn fitted to a SPICE transistor model such as BSIM 4. The transistor data is usually fit to corners as well as to statistical models, as discussed further below. These corners represent the fast and slow extremes of the manufacturing process. The naming convention for the fast and slow corners is SS, FF and TT where the two letters refer to the N transistor and P Transistor respectively. SS means slow n and slow p, FF means fast, and TT means typical.
In order to enable timing analysis of a design in each of the process corners, timing data is determined for each cell in a library of cells (e.g., NAND gate, NOR gate, FLIP-FLOP) at each process corner. This procedure is known as library characterization. The libraries are characterized at each corner (usually SS, TT and FF), as well as with respect to the operating voltage and temperature ranges for the circuit. One approach to this characterization is by evaluating every timing arc in the cell using a deterministic numerical simulation (e.g., using SPICE). The results from this analysis are stored as a library file, usually in the Liberty format. Each arc in each cell is evaluated in SPICE under different load and slew conditions.
The default Liberty format represents a discrete set of load and slew conditions, typically arranged in a 7×7 table of different load×slew conditions. The side inputs (the other pins of the cell) are usually set to the worst case condition, for example, determined by considering all possible side input values from which the worst case is selected. Slew describes the shape of the input ramp of the driving signal. For instance, a 500 picosecond slew describes the transition period of the input signal from low to high or from high to low. This usually means from threshold to threshold, but it can also reference from 0 volts to saturation. The load refers, for example, to the capacitive load on the output of the cell. This will range from a very light or near 0 load to a high load reflecting multiple receivers. So the values in the library can be considered to be a mapping:
(corner, cell, arc, [side inputs,] slew, load, rising/falling)→delay.
In one approach to STA, the library for one corner of timing data is referenced at a time. That is, timing data for different corners are not used together in one static timing analysis of the circuit. As noted before, the SS corner tends to expose set-up violations (slow data), whereas the TT and FF tend to expose hold violations (fast data).
Referring to FIG. 1, in a circuit example, evaluation of a data path from the Q output of a first register 114 to the D input of a second register 116 is evaluated relative to the launch clock path from a common clock signal point 132 to the clock input of the first register 114 and the capture clock path from the common signal point 132 to the clock input of the second register 114. Checking of a setup and hold violation considers the delays along the illustrated path 151, 152 as compared to the delay along the clock path 153 at each of the representative total corners (e.g., SS, FF, and TT). Specifically, the delay of the clock edge through buffer 144, and the delay through flip flop 114 (from clock input to D output), though NAND gate 124, and through XNOR gate 126 is compared to the delay through delay of the clock edge through buffers 146 and 147. The load on each output of a cell is known based on the interconnection of the cells. For a particular timing path and directions of the transitions (rising vs. falling), the slew rates are determined based on known cell characteristics. Then, for those load and slew rates, the particular delays in the tables for each arc in the paths are added to determine the overall delay through the path. The capturing register is specified according to its required setup and hold times, and these specified times are compared to the calculated delays to see if a hold or setup violation is present on that path.
One limitation of traditional corners-based analysis is an assumption that all gates of a circuit are at the SS or FF corner on any given chip. For a given parameter corner, each gate in a path is assume to be at that corner value, and the delays are additively accumulated (i.e., added) along the path. In practice, each gate is not at exactly the same parameter corner, for example, due to the local parameters (on die process variation within the circuit), and the additive accumulation of the delays is not accurate. Although part of the timing variation is related to chip-to-chip (or die-to-die variation), part of the variation is local to one chip (on-die variation). Stated differently, the total variance is a combination of die-to-die variance (global) and on-die variance (local).
Using traditional corners and accumulating the delays at that corner can both overstate and understate relative speed of the launch clock, capture clock, and data path relative to each other. It can exaggerate set-up violations, which causes the designer to have to speed up a path, and in turn consumes too much power (the pessimistic case). It can also understate the speed of the data path or spread between launch and capture clock and miss hold violations (the optimistic case). Note that both of these cases have the undesired effect of reducing production yield—both excessive power and hold violations can cause a chip to fail with respect to its manufacturing specifications.
Another technique, referred to as Advanced on Chip Variation (AOCV), makes use of a table of adjustments to the characterized models, which correct for both the pessimistic and optimistic case. These adjustments are referred to as "derates" can be expressed as multiplicative "corrections" to the timing value that is used. The idea behind AOCV is that as depth increases (number of gates or transistors in a row), local variation will "cancel out" and the overall delay will approach a value predicted by the die-to-die variance of the individual cells and effect of the local variance will cancel out such that is has relatively less influence on the variance of the overall delay.
AOCV supports two kind of indexes—depth and distance. Depth—how many logical cells are in a path—turns out to be a reasonable surrogate for modeling on chip device process variance. Distance on the chip is not generally used, since from a device process variation standpoint it is relatively insignificant. Note that the calculation of depth depends on the type of timing analysis (graph or block vs. path), and the tool (small differences may exist between STA tools). STA, in order to apply the AOCV derate, looks at the logic depth of the overall path, and uses that depth value to find the right AOCV derate table for each of the cells in the path. The derate is used to multiply the delay value for that cell.
An industry standard AOCV table provides eight derate values for a cell (not per arc, just per cell). There are four data values (when the cell is in a data path) and four clock values (when the same cell is in a clock path). These four values are (1) early/rise, (2) early/fall, (3) late/rise, (4) late/fall. For example, when the earliest a signal can arrive at a capture register, the early/rise or early/fall derate values are used, depending on the transition direction of the input signal to the cell in the path. The derates can be considered to be a mapping:
(cell, data/clock, depth, rise/fall, early/late)→derate.
Referring again to FIG. 1, and considering the timing path with launch clock path 151, data path 152, and capture clock path 153, application of AOCV derate values in the case of assessing a possible hold violation, an early clock derate is applied to buffer 144, and late clock derates are applied to each of buffers 146 and 147, while early data derates are applied to gates 124 and 126 and launching flip-flop 114. In some examples, the derates are not necessary applied to each of the launch clock path, the data path, and the capture clock path. An example of depths applied to the gates is buffer 144 having depth 1 and buffers 146 and 147 having depth 2, and gates 124 and 126 having depth 2. Note that different systems may have different definitions of depth without departing from the basic principle described herein. Note also that the depth of a gate depends on the path being considered. For example, gate 124 may have a depth of 2 in the path from register 114 to register 116, but have a depth of 3 on the path from register 112 to register 116.
Although use of standard AOCV tables provides improved accuracy over STA (or use of timing and optimization tools) performed without such derate values, the computation of derate values for cells using conventional approaches yields pessimistic worst case characteristics for the paths in an integrated circuit. There is therefore a need for more accurate prediction of path characteristics based on characteristics of the individual cells. Furthermore, even with improved techniques that reduce the computation required for determining the derate factors, there is a further need to efficiently form data that characterizes cells in a way that can be used to predict path characteristics will lower pessimism that used today.

Database based timing variation analysis


A method and apparatus are disclosed for joining a plastic insert or component to a plastic base having a recess therein. The component is provided with integral projections thereon that are in a circular array with the projections being separated circumferentially from one another by spaces. The projections are force-fitted against the plastic base. The plastic of projections is caused to flow circumferentially into the spaces, and the plastic of the base is caused to flow into the spaces where the plastics are melded together. Then the flowed, melded plastics are brought to a solid condition with spaces now filled with solid, melded plastics that interlock the components to the base against rotation relative to one another and to prevent them from being pulled apart. The preferred component is a boss. The boss may be inserted into a recess in the plastic base, and a shoulder on the boss may abut the plastic base and limit the insertion of the boss into the base.

Molded plastic parts have become increasingly popular, due at least in significant part to their low production cost. Hence, often, one or more components of an assembly are formed of molded plastic. In assembling a final product it is often necessary to fasten the molded plastic parts to other components to produce the final product.
Current production methods for fastening components to a plastic part of low ductility include forming a threaded recess in the plastic part, which serves as a base, and into which a threaded member or fastener is screwed. This has been found to be undesirable in several respects. The brittle nature of polycarbon and other plastics employed makes it difficult to cut threads in the polycarbon base for receiving the threaded member. During thread formation, the brittle polycarbon base material has been found to crack and chip, often making insertion of the threaded fastener difficult or impossible. Also, the chipping reduces the bearing surface area against which the threads of the fastener bear against the base to preclude the fastener from being pulled out of the base. Thus, the load bearing capacity of the threaded member is significantly reduced. bearing capacity of the threaded member is significantly reduced.
Due to the aforementioned difficulties associated with pre-threading brittle plastic base materials, other, less desirable, fastening means have been employed. One such alternative fastening means attempted has been to employ a self-threading screw. However, the brittle nature of the plastic base material precludes the formation of a consistent thread therein, with a resultant cracking of the base.
Alternatively, internally threaded metal inserts have been molded to the base, with the threaded fastener then screwed into the internal threads of the metal insert. However, due to the inherent incompatibility of metals and plastics, the bond therebetween has been found inadequate to maintain bonding of the metal insert to the plastic base when the metal insert is pulled with significant force. Bonding of the metal insert is attained by providing the metal insert with grooves, ridges or knurls and bringing the base plastic to a flowable state whereby the base plastic flows into the grooves, ridges or knurls of the insert. Accordingly, the strength of the bond is only derived from the base plastic, and limited thereby. Hence, upon imposition of significant forces pulling on the metal insert, the insert is pulled from the base, together with any threaded member screwed into the insert. Additionally, formation of the metal inserts adds considerable expense to the overall production cost.
One method currently employed for fastening components to the base which provides the desired bonding strength is a conventional screw and nut assembly. However, this is undesirable in several respects. Functionally, the screw and nut assembly loosens over time, resulting in a loose connection between components. Also, aesthetically, screw and nut assemblies are undesirable due to the requirement of a provision for accommodating the nut or the nut being exposed on one end of the base, rather than allowing for employment of a blind tapping which provides superior aesthetics. Furthermore, the requirement of the metal nut adds undesirable cost to production.
There is a need for eliminating the driving of a metal fastener into the plastic base. This operation of driving the metal fastener requires assembly time and the use of labor. Overall production efficiency could be obtained by eliminating a tapping of a thread into a plastic base and/or the driving of a fastener into the thread in the plastic base. In its preferred form the invention allows elimination of the driving of the fastener into the plastic base thereby increasing overall efficiency in mounting components to a plastic base with a metal threaded fastener.
Also, there is a need to join together plastic bodies such as two plastic components or a pair of plastic sheets or plates with one or more plastic fasteners. While metal fasteners may be used as above-described, there are times when it is desired not to use metal and still join plastic parts or components together to form a composite of the two joined parts. In such instances, it is preferred that the plastic fastener form a strong, secure connection that will not readily loosen as may a plastic screw that is threaded into the parts to join them together. Preferably, the plastic fastener should bond the two plastic bodies together much in the manner that of an integral bond therebetween.
The present invention is also of particular use to molders of plastic parts, such as molded plastic shells or molded plastic bodies that have cylindrical protrusions or bosses thereon to create an attachment area for a screw or other fastening means to secure one body to another body or to a supporting frame, or to attach other elements to the molded plastic body. For example, in the automotive industry, dashboards are molded from plastic with an exterior shell that has the same outside appearance but on the inside, has different bosses to receive screws or other fasteners to secure different instruments which vary depending on the model and/or the instrument options selected by the purchaser. Currently, the automotive company and the molder have one mold for each of the options; and this may result in twenty or more molds to accommodate each internal change of the bosses or reinforcing thick portions on the plastic shell body which has the same outward appearance.
The injection molding of these thick portions or bosses is a time-limiting factor on the molding process because the time needed for the plastic to solidify before part ejection is usually determined by the thickness of the plastic cross-section, and it takes longer to solidify the thicker bosses than the thin shell cross-section.
Also, in a mold, the boss configuration is the highest wear part of the molding die. A pin which is commonly called a core pin is inserted in the center of the boss to create an attachment area for a screw or other method of attaching the shell. This pin is nominally tapered and must be closely controlled because of the amount of pressure and friction the pin must withstand. The pin is normally the highest wear point of the mold and requires the most rework and replacement.
Additionally, strength requirement for the boss may determine what plastic is used for the shell because the strength needed for the bosses used for affixing the shell to another shell or to another part or frame or to mount other elements may outweigh other considerations. That is, the product may be molded with more or larger bosses or higher strength plastic materials than the shell requires in order to provide the strength to the bosses to interconnect the shell with other parts. Additionally, some products that are now molded with integral plastic bosses, e.g., integrated circuit boards or the like, could be made less expensively from plastic flat sheet stock with subsequently attached bosses.
From the foregoing, it will be seen that there is a need for a new and improved method for forming plastic products with integrally attached plastic projections such as bosses.

Method and insert for connecting components to plastic members


A folding hinge for camera stabilization equipment. The hinge includes support connectors having apertures through which cables may be passed to connect a camera with various auxiliary components. An indexing guide pivotally attaches the support connectors so the camera stabilization system can be folded and unfolded with little or no disruption of the cables pr system balance. Locking mechanisms secure the hinges to provide a desired angular relationship between support members connected by the hinge.

FIG. 1 depicts a conventional basic body mounted or hand held camera support and stabilization system 100. It includes a top stage 102 for camera mounting, post 104 and gimbal mechanism 106 for support of a camera and stabilizer system about a common pivot point, a monitor 108 for viewing the camera's image, and a lower support (sled) 110 that interconnects the post, a battery system 112, and miscellaneous electronic systems. Battery power must be supplied to the camera, and the viewer must be functionally connected to the camera, so the image captured by the camera can be seen. As is apparent from FIG. 1, the camera is displaced from the viewer and the battery, and therefore, wires or cables must extend between the camera and these auxiliary components. (The term "cable" as used herein will include any flexible component that can functionally link cameras to auxiliary components such as viewers and batteries.) Typically, to accomplish this connect coaxial cable and stranded copper cables are run through connectors, or via hard wiring, from the lower sled portion 110, up through the post 104, to the top stage 102. Within the top stage section, power and video cables are then typically broken out to external connectors and then connected to the camera. Within this structure the preferred method of running the cables to the top stage section is within the post itself. Doing this helps to protect the cables from damage and also allows for unimpeded operation of the camera stabilization system without concern for having the operator or other equipment being entangled in the cables. The common approach in connecting the post cables to the lower sled portion 110 is either via a hard wired connection through a rigidly attached post or via an interconnect connector attached to a removable post. If a hard wired/rigid post method is employed, the camera stabilization type system is limited as to how compact it can become for storage and transport. When employing the removable post method, the cost of the assembly is increased because of the addition of connectors, and reliability of electrical or optical connections between post and sled is decreased.
Compacting of the camera stabilization system is desired in order to reduce the volumetric space required for storage and transport. Decreasing this size as much as possible allows users of the system to transport the device at a lower cost, and to have it fit more readily in compact spaces such as in cars. In effect, the system is made more portable. In having the ability to compact the system, the durability and reliability of the camera stabilization device must be maintained.
Currently there are a number of schemes to connect the post mechanism to the main lower sled body. They include, for example, mechanically rigid, non-removable or separable post mechanisms with hard wired electrical/fiber optic connections disposed internally within the post and sled. Also used are mechanically removable post mechanisms with connectorized electrical/fiber optic connectors internal to the post and sled. Another mechanically rigid, non-removable or separable post mechanism has hard wired electrical/fiber optic connections external to the post and sled. An external mechanism may also incorporate connectorized electrical/fiber optic connectors.


Perforated retroreflective fabric, trim or tape that comprises a substrate (30) having a first and second sides and a plurality of openings (39) extending between the sides, providing a backing (50) on the first side of the substrate, providing a retroreflective layer (40) on the second side of the substrate, adhering the retroreflective layer to the second side and to the backing through said openings and removing the backing from the first side to strip away the retroreflective layer adhered to the backing through the openings in the substrate.

Retroreflective trim is often used in or provided on the outer layer of garments such as fire fighter garments, construction worker garments, road and rail worker garments and jogging suits. Such garments may be referred to as high visibility safety garments. The reason for providing the retroreflective trim is to reflect available light in dark environments so as to enhance the visibility of the garment to which the trim is applied as well as the wearer of the garment.
In some circumstances law mandates that individuals must wear high visibility garments incorporating retroreflective trim material when engaged in certain activities in adverse light conditions or even in light conditions that are not adverse. Such laws often require high visibility safety garments be worn by people in situations where they may be exposed to hazards from moving plant or equipment, motor vehicles, trains etc.
National and international standards are applicable to retroreflective trim used in relation to the aforementioned garments. Such standards specify various minimum requirements for high visibility safety garments and for trim material used in relation to such garments. For example, retroreflective trim applied used in relation to high visibility garments or other objects may be required to meet minimum threshold requirements for visibility, retroreflectivity and other physical performance properties such as abrasion resistance and wear resistance.
The stringent requirements of the standards applicable to retroreflective trim have meant that existing retroreflective trim is formed as a continuous non-permeable, non-perforated sheet which is not breathable. A problem with existing retroreflective trim is that it does not easily permit the transfer of heat or vapour from perspiration emanating from the wearer of a garment incorporating the retroreflective trim. Accordingly, the wearer of the garment is subjected to a build up of heat and vapour within the garment resulting in stress to the wearer. This problem is significant given that while wearing high visibility retroreflective garments the wearers are frequently engaged in strenuous physical activity or are subjected to warm environments.
Another crucial requirement of retroreflective trim is that the retroreflective component, which is usually a retroreflective coating applied to a substrate, must be strongly bound to the underlying substrate. This is so that the retroreflective trim can meet standards requiring the retroreflective component to be resistant to abrasion resulting from when a garment incorporating the retroreflective trim is worn or washed and from general wear and tear. In fact, this property of the retroreflective trim is crucial to its ability to meet standards applicable to such materials. This is because although a retroreflective trim may initially meet the retroreflectivity requirements after a number of wash cycles the adherence of the retroreflective component to the substrate may degrade to the extent that the retroreflective component may separate from the substrate such that the retroreflective trim no longer meets the minimum threshold standards for retroreflectivity.
Previous attempts to provide a breathable retroreflective trim have involved perforating continuous non porous retroreflective trim with perforating needles. However, the perforated retroreflective trim resulting from this process may be insufficient to meet the standards for retroreflective trim such as retroreflectivity, abrasion resistance and wear resistance. The perforated retroreflective trim when used with high visibility garments may not provide adequate breathability and may be ineffective for allowing or enhancing the transport of heat and water vapour emanating from the wearer from within the garment to the external environment outside the garment and ineffective for enhancing the comfort of the wearer. Further, the perforated retroreflective trim may not result in the retroreflective component or coating being strongly bound to the underlying substrate. Perforated trim resulting from using perforating needles may also have poor appearance and quality characteristics and may be relatively inefficient to manufacture.
The above discussion of acts, materials, devices, articles and the like is included in this specification solely for the purpose of providing a context for the present invention. It is not suggested or represented that any of these matters are known, form part of the prior art base or are common general knowledge in the field relevant to the present invention at the priority date of each claim of this application.
Accordingly, there is a need for a breathable retroreflective trim for use with high visibility garments that is sufficient to meet the standards for retroreflective trim such as retroreflectivity and other physical performance properties such as abrasion resistance and wear resistance. There is also a need for a breathable retroreflective trim in which the retroreflective component or coating is strongly bound to the underlying substrate. Furthermore, there is a need for a breathable retroreflective trim that is efficient to produce and that has superior appearance and quality characteristics. There is yet furthermore a need for a method of producing such breathable retroreflective trims.

Method of producing perforated retroreflective trim


A flip-chip LED, a method for manufacturing the same and a flip-chip LED package are revealed. The LED includes at least one multi-layer reflective layer covered over the outermost layer thereof. The multi-layer reflective layer includes non-conductive reflective layer or combination of the non-conductive reflective layer with conductive reflective layer. The multi-layer reflective layer is manufactured by physical vapor deposition (PVD) with a mask at one time. The mask is used to form a pattern of the multi-layer reflective layer. Thus a photoresist layer is further formed on surface of exposed electrodes. Then a pumping and venting process is used only once during to complete vacuum deposition of each layer of the multi-layer reflective layer in turn.

The present invention relates to a LED, a method for manufacturing the same and a package of the same, especially to a flip-chip LED (light emitting diode), a method for manufacturing the same and a flip-chip package of the same. The flip-chip LED includes at least one multi-layer reflective layer covered over an outer surface of a LED chip except the area with exposed electrodes. The multi-layer reflective layer is produced by physical vapor deposition (PVD) with the same mask at one time.
Refer to TWI423482 (US2011/0014734), TW 573330, TW M350824; U.S. Pat. Nos. 8,211,722, 6,914,268, 8,049,230, 7,985,979, 7,939,832, 7,713,353, 7,642,121, 7,462,861, 7,393,411, 7,335,519, 7,294,866, 7,087,526, 5,557,115, 6,514,782, 6,497,944, 6,791,119; US2011/0014734, US2002/0163302, and US2004/0113156, techniques related to flip-chip LED such as GaN LED, reflective layer of LED, or flip-chip package of LED are revealed. These prior arts provide different techniques for solving problems of LED chip or LED package such as light emitting efficiency, heat dissipation, service life, cost, yield rate, process simplification, and luminous decay. Take U.S. Pat. No. 8,211,722 and US2011/0014734 (Ser. No. 12/505,991) as an example. The U.S. Pat. No. 8,211,722 is continuation-in-part of the US2011/0014734. Refer to U.S. Pat. No. 8,211,722, a flip-chip GaN LED fabrication method is revealed. The chip includes a substrate, an N-type GaN ohmic contact layer, a light-emitting layer, a P-type semiconductor layer, a translucent conducting layer (such as Indium Tin Oxide), a P-type electrode pad, an N-type electrode pad, isolation protection layers and a metallic reflection layer. The metallic reflection layer is generally produced by physical vapor deposition (PVD). However, if the metal reflection layer includes three layer, three a plurality of different masks is required to form a pattern of the metal reflection layer for arranging photoresist layer thereon. Then multiple times (such as three times) of processes (such as PVD) are carried out to form respective layer on the outer surface of the LED (except the area with the electrodes). For example, if the reflection layer includes three layers, three masks are required to form pattern of the reflection layer and arrange the photoresist layer. Then the vacuum deposition process such as PVD is carried out three times to form a multi-layer reflection layer on the outer surface of the LED chip (except the area with the electrodes) in turn. One mask and one pumping and venting process are required during each PVD process. The plurality of masks required and multiple times of PVD processes required for manufacturing the multi-layer reflection layer increase both time and cost. This has negative effect on mass-production and market competitiveness.
Thus there is room for improvement and a need to provide a novel flip-chip LED, a method for manufacturing the same and a package of the same that overcomes the shortcomings mentioned above.

Flip-chip LED, method for manufacturing the same and flip-chip package of the same


A method and apparatus for synchronizing objects is provided. A cache of synchronization constructs is provided and used to synchronize a thread with an object. A free list contains synchronization constructs not allocated to synchronize an object. A synchronization construct is allocated when at least one thread requests synchronization with an object. In response to detecting a collection enabling condition, synchronization constructs allocated to objects not synchronized with any thread are deallocated. A local hash table is assigned to each thread. The local hash table contains synchronization constructs used to synchronize objects to the thread to which the local hash table is assigned.

In multiprocessor computer systems, software programs may be executed by threads that are run in parallel on the processors that form the multiprocessor computer system. As a result, a program may be run in parallel on different processors since concurrently running threads may be executing the program simultaneously. Moreover, if a program can be broken down into constituent processes, such computer systems can run the program very quickly since concurrently running threads may execute in parallel the constituent processes. Single processor, multitasking computer systems can also execute multiple threads of execution virtually simultaneously through the use of various resource scheduling mechanisms well known to those skilled in the art of multitasking operating system design.
The programs running on such computer systems may be object-oriented. In other words, the threads executing the programs may invoke methods of objects to perform particular functions. However, because of software and/or hardware constraints in the computer system, only a predefined number of objects may be allowed to implement functions at one time. For example, an object may require access to a shared computer resource, such as an I/O device, that can only handle one access at a time. Thus, since concurrently running threads may concurrently seek to invoke a method of an object, the object must be synchronized with only one thread at a time so that one thread owns and has exclusive use of the object. In other words, access to an object by a thread must be synchronized so that other threads do not have access to the object while it is synchronized with the thread.
In the past, various approaches have been used to synchronize an object with a thread. These include the use of synchronization constructs like mutexes, monitors, and semiphores. One approach that uses synchronization constructs, the run-time-allocation approach, is described in U.S. patent application No. 08/569805, entitled "OBJECT SYNCHRONIZATION MODULE AND METHOD WITH REDUCED MEMORY REQUIREMENTS", filed by Timothy G. Lindholm and Jonathan Payne on Dec. 8, 1995 (attorney docket no. A-62531).
In the run-time-allocation approach, synchronization constructs are allocated and de-allocated to objects as needed. For example, during run-time, a thread may invoke a method of an object that requires synchronization. A synchronization construct is allocated to the object if a synchronization construct has not already been allocated. When the thread exits the method that required synchronization of the thread with the object, and there are no other threads currently requiring synchronization with the object, the synchronization construct is deallocated from the object.
Synchronization constructs are stored in a data structure in global cache. Managing the allocation of these synchronization constructs to objects involves the use of other data structures which are also stored in global cache. A hash table links an object to its allocated synchronization construct. A free list contains entries identifying the synchronization constructs that are not allocated to any object.
Allocating a synchronization construct to an object entails operations which update the synchronization construct and the data structures used to manage allocation of synchronization constructs. These operations include, for example, updating the synchronization construct with information linking the synchronization construct to the object, creating an entry in the hash table linking the object to the synchronization construct, and removing the synchronization construct from the free list. Likewise, de-allocating a synchronization construct from an object includes operations such as removing an entry in the hash table linking the object to the synchronization construct, and adding the synchronization construct to the free list.
The operations involved in allocating and de-allocating synchronization constructs update data structures (i.e. the hash table, synchronization construct, and free list) in global cache. An update to a data structure in global cache requires a lock of a global data structure to prevent interference to and from other concurrently executing threads that may update the data structures. A lock of a global data structure is herein referred to as a global lock. A thread contending for a data structure globally locked by another thread is delayed until the other thread releases its global lock. Delays such as this one, which are caused by one thread contending for a data structure locked by another thread, are herein referred to as contention delays.
As threads executing in a computer system increase the number of operations performing updates on data structures in global cache, contention delays can often increase to undesirable levels. Thus frequently repeated allocations and de-allocations of synchronization constructs, which involve operations performing updates on data structures in global cache, can cause contention delays to reach undesirable levels.
Based on the foregoing, it clearly desirable to reduce contention delays caused by frequently repeated allocations and de-allocations of synchronization constructs.

Method of synchronizing one of the objects with one of the threads at a time


Methods, systems, and devices for wireless communications are described. Generally, the described techniques provide for improved handling of adjacent channel interference in multi-link aggregation scenarios. In accordance with the described techniques, a device may establish a set of wireless links for communication with a second device, the set of wireless links supporting parallel transmission during at least a first duration of a multi-link session, the set of wireless links including at least a first wireless link and a second wireless link. The device may modify a transmission parameter for the first wireless link or a clear channel assessment (CCA) parameter for the second wireless link, or a combination thereof. The device may then perform the CCA procedure on the second wireless link and transmit at least a first portion of the message on the first wireless link based on the modified transmission parameter or modified CCA parameter.

The following relates generally to wireless communications, and more specifically to design considerations for multi-link aggregation.
Wireless communications systems are widely deployed to provide various types of communication content such as voice, video, packet data, messaging, broadcast, and so on. These systems may be multiple-access systems capable of supporting communication with multiple users by sharing the available system resources (e.g., time, frequency, and power). A wireless network, for example a WLAN, such as a Wi-Fi (i.e., Institute of Electrical and Electronics Engineers (IEEE) 802.11) network may include an AP that may communicate with one or more stations (STAs) or mobile devices. The AP may be coupled to a network, such as the Internet, and may enable a mobile device to communicate via the network (or communicate with other devices coupled to the access point). A wireless device may communicate with a network device bi-directionally. For example, in a WLAN, an STA may communicate with an associated AP via downlink (DL) and uplink (UL). The DL (or forward link) may refer to the communication link from the AP to the station, and the UL (or reverse link) may refer to the communication link from the station to the AP.
Some wireless communications systems may support multi-link aggregation, where transmissions may be transmitted and/or received over two or more links between two wireless devices (e.g., two STAs, an AP and STA, etc.). In some cases, a transmission on one link in the multi-link session may interfere with a transmission on one or more other links of the multi-link session. For example, adjacent channel interference (ACI) may result from leakage of signal power from an adjacent channel (due to inadequate filtering, improper tuning, etc.). ACI may negatively impact a communications system, for example by decreasing throughput on adjacent links, increasing signal processing at communicating devices, or incorrectly causing adjacent links to appear busy or occupied, leading to lost transmission opportunities. Improved techniques for ACI management in multi-link aggregation may be desired.

Considerations for multi-link aggregation


A rotary encoder comprises a rotary plate having a plurality of primary slits defined in the rotary plate in a circular row coaxial with the axis of rotation of the rotary plate. The rotary plate also has at least one reference slit defined therein at a position radially of the circular row of the primary slits. A primary photoelectric detector including a source of light and a photo-sensor positioned one above the other with the circular row of the primary slits intervening therebetween is used to detect the passage of the primary slits therethrough while an auxiliary photoelectric detector including a source of light and a photo-sensor positioned one above the other with the path of travel of the reference slit intervening therebetween is used to detect the passage of the reference slit therethrough.

1. Field of the Invention
The present invention relates to a rotary encoder.
2. Description of the Prior Art
Conventional rotary encoders comprise a rotary plate having a plurality of slits defined therein and spaced an equal distance from each other in a direction circumferentially thereof. These slits are selectively sensed by a sensor during rotation of the rotary plate to determine the angle of rotation of the rotary plate in terms of the number of slits detected and also to determine the peripheral velocity of the rotary plate in terms of the number of slits detected for a given length of time.
With conventional rotary encoders however, the detection of the peripheral velocity of the rotary plate is essentially such as to detect the angle of rotation from a position at which rotation of the rotary plate is initiated. The conventional rotary encoder is unable to detect the angle of rotation of the rotary plate from a specific reference angular position during the continued rotation of the rotary plate.


A retractable wheel assembly for moving an object having a vertical surface for attachment of the wheel assembly, comprising a plurality of arms, each arm having a wheel at one end, a plurality of pivot assemblies for receiving the arms such that when the pivot assemblies are attached to the object, the arms pivot in a vertical plane about the pivot assembly, mounting means for attaching the pivot assemblies to the object, and means for locking the wheel assembly in a retracted position wherein the weight of the wheel assembly maintains the wheel assembly in the retracted position, and for locking the wheel assembly in an extended position wherein the weight of the object maintains the wheel assembly in the extended position.

Typically, moving of heavy or bulky objects over short distances requires the objects to be lifted or dragged to the desired position. This often necessitates the involvement of two or more people. An example of an object that frequently requires movement over short distances and that is too bulky for one person to move and difficult to drag is a picnic table. Previously, others have attempted to attach wheels in various ways to facilitate the movement of objects.
Permanently attached wheels have been described for picnic tables and boats. U.S. Pat. No. 4,974,284 (Campbell) describes a wheel assembly consisting of wheels attached to the opposite legs of a picnic table. The wheels operate independently of each other and are not retractable. U.S. Pat. No. 2,848,229 (Miller) discloses a combination sand box and table. The table is equipped with a pair of wheels fixed to two legs. Again, the wheels are not retractable. U.S. Pat. No. 5,586,803 (Overpeck) discloses a movable picnic table having a pair of wheels mounted to a pair of legs. Foot brackets are attached to the other pair of legs to match the height increase due to the wheels on one pair of legs. The wheels are permanently attached to the legs and are not retractable. U.S. Pat. No. 3,514,154 (Kotler) discloses a folding picnic table having wheels attached to two legs. While the picnic table itself can be folded, the wheels are not retractable.
Foldable assemblies have also been described previously. Such assemblies generally require the insertion or removal of some parts for folding the assembly. U.S. Pat. No. 4,706,983 (Griswold) discloses a retractable wheel assembly used in towing a boat. A leaf spring support pivots about a pin. Another pin, which is removable, secures the leaf spring support to a channel. In order for the assembly to be retracted, the pin has to be manually removed. The pin is inserted back to lock the leaf spring in place for moving the boat. U.S. Pat. No. 4,615,534 (Blain) discloses a movable, foldable wheel support for boats. The foldable wheel support has a pin fitting on to two notches to hold the support in an extended position. The invention employs a closed loop system for raising and lowering of the wheel assembly. The support is folded by pulling upwards a rope loop secured to the support. The support is held in the folded position by securing the rope loop to a swivel attached to the boat. U.S. Pat. No. 3,616,474 (Lindblad), U.S. Pat. No. 3,831,211 (Bustamante), and U.S. Pat. No. 4,040,658 (Mayol) disclose retractable wheel assemblies in which positioning of the wheel in an extended or retracted position is achieved by inserting a removable pin.
Still others have disclosed devices that can be attached at the time of need. U.S. Pat. No. 4,076,305 (Sullivan) discloses a knock-down mobile picnic table and bench assembly having a wheel assembly that is not retractable. The wheels are kept separately and added to the assembly only after it has been stacked for transport.
Thus, while several wheel assemblies are known in the literature, most of the assemblies are either not retractable or require manipulation of parts for retraction. Therefore a need exists for an apparatus for moving objects like picnic tables over short distances, that is simple and easy to use.


A method for recording execution information for a software application executable in a computer system, the computer system including a message queue, the method comprising the steps of: generating the execution information by the software application; and recording the execution information to the message queue for subsequent retrieval, wherein the message queue is accessible by the software application and persistent with respect to the software application.

Software applications at runtime can generate and record execution information for a number of purposes. For example, execution trace information, execution logs, data dumps and debug information can be generated to assist in problem determination in the event that a software application fails. However, recording such execution information routinely during the execution of a software application is burdensome and imposes a further resource requirement over and above that of the software application itself, manifesting as a requirement for further storage and processing throughput. In some environments, the burden of generating and recording execution information at execution time can be so great that it exceeds the resource requirements of the software application itself. For this reason, a decision to include facilities for the generation and recording of execution information in a software application will involve a compromise. The balance is between a resource-efficient, high performance software application and a rich set of execution information for use in, for example, problem determination. However this balance is struck for a particular software application, one of performance and reliability may be compromised.
Execution information, once generated by a software application, can be recorded in a memory associated with the software application, such as a high-speed volatile memory device. Using such memory can alleviate the effect of generating and recording execution information since read and write operations to such memory can be made quickly. However, the use of such fast volatile memory has the disadvantage that the execution information recorded in the memory is lost in the event that the software application fails. To overcome this disadvantage, a software application can record execution information to a non-volatile storage device, such as a disk storage device. However, read and write operations to such storage devices are generally much slower than those to a high-speed memory, and overall application performance can be impacted negatively.
It would therefore be advantageous to provide for the persistence of execution information generated by a software application without placing additional burdens on the software application to undertake the regular recording of such information to a non-volatile storage medium. Further, it would be advantageous to process execution information without placing additional burdens on the software application to undertake such processing.

International Business Machines Corporation


A method for producing a rubber composition containing by weight 5 to 95 parts of natural rubber (NR), 95 to 5 parts of chloroprene rubber (CR), and 20 to 90 parts of carbon black (CB), using a kneading machine, includes a first step of producing a master batch (M1) containing NR and CB; a second step of producing a master batch (M2) containing CR and CB, and a third step of mixing the M1 and M2 with each other to produce a master batch (M3) containing NR, CR, and CB, wherein the amount of CB contained in the M2 is from 40 to 70% by weight relative to the total amount of CB in the rubber composition, and when the M2 is discharged from the kneading machine after the second step, the actually measured temperature of the rubber composition is from 100 to 130° C.

1. Field of the Invention
The present invention relates to a method for producing a rubber composition containing natural rubber (NR), chloroprene rubber (CR) and carbon black (CB), using a kneading machine.
2. Description of the Related Art
Hitherto, in order to attain the vulcanization and the reinforcement of a rubber, an improvement in the function thereof, and the like, a rubber composition has been used in which sulfur, a filler and various chemicals are added to a rubber component. In general, however, powdery are many of sulfur, fillers such as carbon black and silica, and various chemicals such as zinc oxide and an anti-ageing agent. Thus, when these components are blended with a rubber component and the blend is kneaded, these components become into dust to be scattered, so as to cause, for example, problems that a weighing precision thereof is declined and the working environment is deteriorated. About, in particular, the fillers such as carbon black and silica, the ratio of the use amount thereof to that of the rubber component is large. Thus, when the fillers are blended into the rubber composition, it is important to blend the fillers with the rubber component as precisely as possible while the working environment is kept good.
As a method for solving this problem, there is known a technique of blending only a filler beforehand with a rubber component to prepare a master batch. JP-A-2008-179717 describes a technique of using natural rubber or styrene butadiene rubber as a binder component, and blending carbon black with this component to prepare a master batch.
However, the technique described in JP-A-2008-179717 discloses only a technique of making a specific rubber species, such as natural rubber or styrene butadiene rubber, into a master batch. Thus, JP-A-2008-179717 neither describes nor suggests that a master batch technique is used for a rubber composition in which natural rubber and chloroprene rubber are together used, so as to improve carbon black in dispersibility in this composition.


According to one embodiment, a medical image observation apparatus includes a data receiver, a display, and a controller. The controller controls the display to array medical images for each of groups, the medical images being classified into the groups in accordance with at least one of a type of medical image generation apparatus, an imaging condition, an image generation method, an imaging position, an instruction and a setting by an operator, and an imaging date/time, to display medical images corresponding to at least two of the groups, and to scroll the medical images arrayed on a display screen on a group basis based on a scroll instruction of the operator.

A medical image observation apparatus conventionally displays a plurality of medical images to be interpreted in a preset place of a display screen on the series basis. For example, the display regions of the medical images to be interpreted are assigned to the display screen in accordance with the number of series selected by the interpretation doctor (for example, FIGS. 13 and 14).
However, the number of series displayed on the display screen is limited by the size of the display screen or the size of a medical image desired by the interpretation doctor. Hence, the medical image observation apparatus cannot display a medical image needed by the interpretation doctor.


Chemical Vapor Deposition of copper films is enhanced by simultaneously introducing in the reactor vapor of an organometallic copper precursor and copper complex vapor of a volatile ligand or the hydrate of the ligand.

In the electronics industry there is a steady trend towards manufacturing integrated circuitry of increasingly higher speed and larger information storage capacity. This requires the individual electrical devices such as transistors, etc. within the integrated circuitry to be fabricated at an increasingly small scale. The metallic electrical interconnects between the devices also need to be miniaturized. As device and interconnect dimensions approach one-half to one-quarter of a micron, the choice of interconnect metal becomes critical. The large current densities resulting from small interconnect cross sectional areas can lead to major problems such as electromigration, stress migration and voiding where the metal lines become fractured or otherwise physically degraded under operating conditions, a major drawback with aluminum alloys. Metal interconnects also need to provide the lowest electrical resistance path possible since resistance-capacitance delays become a dominant factor in circuit performance at sub half micron levels. The aluminum that is widely used in present day interconnect manufacturing is reasonably conductive (2.7 microhm cm), but needs to be alloyed with 0.5 to 4.0% Cu to minimize the electromigration tendencies of the pure metal. Tungsten, also widely used, is electromigration resistant but is of higher resistivity ( 5.4 microhm cm). Considering these facts, copper should be an excellent interconnect metal as it is both highly conductive (1.7 microhm cm) and electromigration resistant.
Metallic interconnects are typically horizontal lines (runners) or plugs (vias) that wire together devices in microprocessors. At feature sizes of >1 micron these metallic components can be built into the microcircuits by PVD (Physical Vapor Deposition) techniques such as sputtering or evaporation. In essence PVD consists of condensing a metal vapor onto a surface/cp systemdict /curr or channel of a circuit where an electrical connection needs to be formed. Since this is a non-selective metallization, either a postdeposition clean-up (i.e. etch-back) or a predeposition masking of the substrate (i.e. the lift-off technique) is required in order to prepare individual discrete metal components. However, the severe surface topographies presented by sub-micron features preclude the effective use of PVD since this "line of sight" technique cannot provide a uniform conformal coating on such high aspect ratio highly convoluted surfaces. Specific examples of these shortcomings include the phenomena of geometrical shadowing and poor step coverage.
A superior process for producing these microscopic metal features is CVD (Chemical Vapor Deposition). In this technique a volatile metal-organic compound in the gas phase is contacted with areas of a circuit where growth of metal film (i.e. interconnect) is required. A surface catalyzed chemical reaction then occurs which leads to deposition of the desired metal. Since this is a chemical reaction, there is potential for it to provide surface selective metallization. That is, CVD metal deposition can be made to occur at only specific locations compared to the non-selective PVD processes. Also, since the metal film steadily grows on the desired surface it is of a uniform thickness and highly conformal even to severe geometries. In this respect CVD is naturally suited to fabricating submicron high aspect ratio features.
An example of a currently available selective CVD metallization is the deposition of tungsten onto a silicon surface using tungsten hexafluoride as the volatile organometallic precursor (see T. Ohba, et al., "Tungsten and Other Advanced Metals for VLSI/ULSI Applications V," Ed. by S. S. Wong and S. Furukawa, MRS, Pittsburgh, Pa., 273 (1990) ). The chemistry that drives this process can be divided into two steps. Initially the WF.sub.6 reacts with the elemental silicon surface to yield tungsten metal and volatile silicon hexafluoride. Hydrogen gas is then added to the system which reduces further WF.sub.6 at the freshly formed metal surface thereby yielding additional tungsten and HF gas. However, loss of selectivity can be observed and is commonly ascribed to the corrosive nature of HF. T. Ohba, et al., Tech. Dig. IEDM, 213 (1987) teach the use of silane as a reducing agent for WF.sub.6 to achieve higher deposition rates while avoiding the production of HF gas. More recently diethylsilane/hydrogen has also been successfully used to reduce WF.sub.6 under CVD conditions (D. A. Roberts, A. K. Hochberg, A. Lagendijk, D. Garg, S. M. Fine, J. G. Fleming, R. D. Lujan, R. S. Blewer, "The LPCVD of Tungsten films by the Diethylsilane/H.sub.2 Reduction of WF.sub.6 " MRS Proc. ULSI-Vll, 1992, 127).
Desirable selectivities for a copper CVD process include deposition onto conducting metallic or metallic like surfaces such as tungsten, tantalum, or titanium nitride versus insulating surfaces such as silicon oxide. These metallic surfaces provide a diffusion barrier between the CVD copper and the underlying silicon substrate that the device is grown upon.
Copper films have previously been prepared via CVD using various copper precursors. Most of these compounds will only deposit copper metal at temperatures higher than 200.degree. C. Historically, the best known and most frequently used CVD copper precursor is the solid compound copper.sup.+2 bis(hexafluoroacetylacetonate). This highly fluorinated organometallic precursor is significantly more volatile than its parent unfluorinated complex copper.sup.+2 bis(acetylacetonate) and its ease of vaporization readily lends this compound towards CVD processes. The use of this compound as a general precursor for CVD copper metallization was first described by R. L. VanHemert et al. J. Electrochem. Soc. (112), 1123 (1965) and by R. W. Moshier et al. U.S. Pat. No. 3,356,527. Reisman, et al., J. Electrochemical Soc., Vol. 136, No. 11, Nov. 1989 and A. E. Kaloyeros et al., J. Electronic Materials, Vol. 19, No 3, 271 (1990) in two independent studies have also evaluated the use of this compound as a copper precursor for electronics applications. In these studies copper films were formed by contacting vapors of copper .sup.+2 (hfac).sub.2, mixed with either an inert gas (argon) or with hydrogen and contacting the mixture with a heated substrate surface. In the case of using hydrogen the copper .sup.+2 atom in the precursor complex is formally reduced to copper metal while the hfac.sup.-1 ligand becomes protonated to yield a neutral volatile compound. In the case of using an inert gas the copper .sup.+2 (hfac).sub.2 is simply pyrolyzed to give copper metal and fragments of the hfac ligand. Pure copper is generally reported for hydrogen reductions but oxygen and carbon are found in the films obtained by pyrolysis. Copper films have also been prepared from copper .sup.+2 (hfac).sub.2 by plasma enhanced deposition, C. Oehr, H. Suhr, Appl. Phy. A. (45) 151-154 (1988) , laser photothermal decomposition, F. A. Houle; C. R. Jones; T. Baum; C. Pico; C. A. Korae; Appl. Phys Lett. (46) 204-206 (1985) and photochemical decomposition of copper .sup.+2 (hfac).sub.2 ethanol adducts, F. A. Houle, R. J. Wilson; T. H. Baum; J. Vac. Sci. Technol. A (4), 2452-2458 (1986). Some of these methods yield fluorine contaminated films and none are reported to yield selective depositions. Mixtures of water vapor and hydrogen have also been used for the reduction of copper.sup.+2 (hfac).sub.2 (N. Awaya and Y. Arita, Conf. Proc. ULSI-Vll 1992 MRS p345.). Hydrogen reduction of similar volatile copper compounds has also been demonstrated by Charles et al. U.S. Pat. No. 3,594,216 using copper .sup.+2 .beta.-ketoimine complexes at 400.degree. C. to deposit copper metal films onto glass or quartz substrates. No mention of selectivity is made. G. S. Girolami, et al., Chem. Mater. (1) 8-10 (1989) reported using solid copper .sup.+1 t-butoxide to yield copper films by CVD at 400.degree. C., but the resultant films were impure in that they contained 5% oxygen.
One class of CVD precursors known to deposit pure copper metal films below 200.degree. C. are the copper.sup.+1 cyclopentadienyl phosphine compounds described by Beech et al., Chem. Mater, (2) 216-219 (1990), but these are also not reported to be strongly selective towards metallic or metallic like surfaces vs. silicon oxide or similar insulating dielectrics. An additional problem that this particular class of compounds faces for electronics applications is their potential to contaminate microcircuits with phosphorus, an element that is extensively used as a silicon dopant.
Selective deposition of pure copper films by CVD at low temperatures onto metallic substrates using Cu.sup.+1 (hexafluoroacetylacetonate) .L complexes (where L=alkene or alkyne) have been described previously by Norman et al in U.S. Pat. Nos. 5,085,731; 5,094,701 and 5,098,516. Under certain conditions blanket (non-selective) deposition can also be achieved using these precursors (J. A. T. Norman, B. A. Muratore, P. N. Dyer, D. A. Roberts, A. K. Hochberg and L. H. Dubois E-MRS proc. B17 (1993) 87-92). A particularly effective CVD copper precursor is 1,1,1,5,5,5-hexafluoro-2,4-pentanedionato-copper (I) trimethylvinylsilane sold under the trademark CupraSelect by the Schumacher unit of Air Products and Chemicals, Inc., Carlsbad, Calif. This compound, Cu(hfac)(TMVS), is known to deposit quality copper films.

Process for improved quality of CVD copper films


Controlled release pharmaceutical preparations are prepared by homogenizing an organic or inorganic pharmaceutical active substance such as an opium alkaloid or its salts, an opium antagonist or its salts, an aliphatic or aromatic amine derivative or its salts, a phenolate type medicament, or Zn, Fe, Mg, K, Na salts, a fatty acid or its salt necessary to achieve a continuous phase transfer and an ethylene vinyl acetate copolymer and formulating the resulting homogeneous mixture by. a) direct compressing or PA1 b) admixing with a solvent or PA1 c) using a second, auxiliary polymer.. The preparations are suitable for oral or rectal administration or for tissue implantation.

The medical use of ethylene-vinyl acetate copolymers is well known in the art [Biomaterials 2 201 (1981) J.Biomedical Materials Research 15 267 (1981)]. Controlled release pharmaceutical preparations for treating glaucoma, diabetes as well as controlled release contraceptives were prepared by using this copolymer. Because of its high biocompatibility [J. Biomedical Materials Research 15 267 (1981)] various human applications of this copolymer have been permitted by the FDA.
In view of the above, it is surprising that only a few oral applications are reported in the art and even these are developed for use as a mycoderma adhesive flexible films administered into the mouth cavity [Japanese Kokai Tokkyo Koka JP 6305, 756 8805,756, ibid, 61 93, 113 8693,113, ibid 6354, 318 885 4318] or in dentistry [European Patent Application EP 268464.]
No typical oral application, e.g. use as a base for tablets has been described.
In order to provide a preparation for oral administration we have selected morphine sulphate as an example for the active ingredient because retarding the release of this active substance is essential in analgesic treatment and, on the other hand, this medicament represents a whole family of salt-like active substances with excellent water solubility.
Various polymer systems are proposed for retarding the release of morphine sulphate. For example in J. Pharmacol. Methods 1(2) 21 (1978) and J. Pharm. Sci. 69(8) 980 (1980) dimethylsiloxane, in European Patent Application EP 205 282 a mycoderma adhesive cellulose composition, in French Patent Application Fr. 2,576 213 sulphate and carboxylate anion exchanger, in Rev. Asoc. Esp. Farm. Hosp. 11(1) 111 (1987) PVC and Methacel K-15 M, in ACS. Symp. Ser. 348 (1987) polyethylene oxide and in Br.J. Anaesth 61 221 (1988) crosslinked ethylene oxide are described. According to the above prior art references these polymer systems are suitable for retarding the release of the morphine sulphate but do not ensure simultaneously the wide variability of the dissolution profile and the dissolution rate.

Controlled release pharmaceutical preparation and process for preparing same


The address transition detecting circuit includes two identical address transition detecting signal generating module, an inverter and a signal combining module. Both of the two address transition detecting signal generating modules have a unilateral delay circuit for generating an output pulse at the rising edge of the address signal and an output pulse at the falling edge of the address signal. The address transition detecting signal generating module can control the width of the two output pulses by controlling the delay times of the corresponding unilateral delay circuit. The signal combining module outputs the ATD signal having pulses at both the rising edge and falling edge of the address signal. The present application uses two unilateral delay circuits to control the width of the ATD signal at the rising edge and the falling edge of the address signal, thereby significantly preventing the width of the ATD signal from influence of the burr on the address line.

During the operation of an asynchronous circuit system, especially an Asynchronous SRAM ("ASRAM"), a change on the address line indicates the beginning of a new write or read cycle. Although the ASRAM does not have an external clock, a signal similar to the clock is required to trigger some internal circuits to get ready for the write and read operation, such as pre-charging a bit-line or generating a pulse word-line, etc. An Address Transition Detecting ("ATD") circuit is used to detect the change on the address line, and to generate a pulse signal for the internal circuits, and the pulse width is an important parameter for the pulse signal. The result of an over-wide pulse is that, the pre-charging of the bit-line still haven't finished when the address decoding has already finished and the word-line is ready for connection, which leads to the delay of the write or read operation. A too narrow pulse will result in insufficient pre-charging of the bit-line, which leads to the delay of the write cycle. Specially, the narrow pulse may lead to failure of the read operation in case of a pulse word-line.
FIGS. 1A and 1B show two known ATD circuits, both of which can detect the rising edge and the falling edge on the address line simultaneously.
As shown in FIG. 1A, the first known ATD circuit comprises a delay circuit 11, three NAND gates 12, 13 and 14, and an inverter 15. An input signal coupled to the input node of the delay circuit 11 is an address signal A1, and the output signals of the delay circuit 11 are signal A1D and signal A1BD. The signal A1D is a delay signal of the address signal A1, which has a delay at the rising edge and falling edge of the address signal A1. The signal A1BD is the inverting signal of the signal A1D. Two input nodes of the first NAND gate 12 are coupled to the address signal A1 and the signal A1 BD, respectively, and an output node of the first NAND gate 12 outputs a pulse signal ATD1BR at the rising edge of the address signal A1. The address signal A1 is coupled to the inverter 15, and two input nodes of the second NAND gate 13 are coupled to the signal A1D and the signal A1B at an output node of the inverter 15, wherein the signal A1B is the inverting signal of the address signal A1. The output node of the second NAND gate 13 outputs a pulse signal ATD1BF at the falling edge of the address signal A1. Two input nodes of the third NAND gate 14 are coupled to the pulse signal ATD1BR and the pulse signal ATD1BF, respectively, and an output node of the third NAND gate 14 outputs a pulse signal ATD1, which has pulses at the rising edge and the falling edge of the address signal A1.
As shown in FIG. 1B, the second known circuit comprises a delay circuit 21, two CMOS transfer gates 22 and 23, and two inverters 24 and 25. An input signal coupled to an input node of the delay circuit 21 is an address signal A2, and output signals of the delay circuit 21 include signal A2D and signal A2BD. The signal A2D is a delay signal of the address signal A2, which has a delay at the rising edge and falling edge of the address signal A2. The signal A2BD is the inverting signal of the signal A2D. The address signal A2 is coupled to the first inverter 25, and an output node of the first inverter 25 outputs signal A2B, which is the inverting signal of the address signal A2. An input node of the first CMOS transfer gate 22 is coupled to the address signal A2, and an input node of the second CMOS transfer gate 23 is coupled to the signal A2B. The signal A2D is coupled to the gate of an NMOS transistor of the first CMOS transfer gate 22, and the signal A2BD is coupled to the gate of a PMOS transistor of the first CMOS transfer gate 22 and the gate of an NMOS transistor of the second CMOS transfer gate 23. Output nodes of the first CMOS transfer gate 22 and the second CMOS transfer gate 23 output a pulse signal ATD2B, which is coupled to the second inverter 24. An output node of the second inverter 24 outputs a pulse signal ATD2, which has pulses at the rising edge and the falling edge of the address signal A2.
The delay circuits 11 in the first known ATD circuit and the delay circuit 21 in the second known ATD circuit can be implemented by various circuits. FIG. 2A shows an example of a known delay circuit, which comprises six inverters 31, four resistors 32 and four capacitors 33. Four delay modules, each of which comprises one resistor 32 and one capacitor 33, are serially coupled between the first five inverters 31 respectively. An input node of the first inverter 31 is coupled to an input signal IN, an output node of the fifth inverter 31 outputs an output signal OUT0, and an output node of the sixth inverter 31 outputs an output signal OUT1. The first and the third capacitor 33 are coupled to a negative power supply VSS or coupled to ground, and the second and the fourth capacitors 33 are coupled to a positive power supply VCC. FIG. 2B shows the waveforms of the input signal and output signals of the known delay circuit. As shown in FIG. 2B, both of the output signals OUT0 and OUT1 have corresponding delays at the rising edge and the falling edge of the input signal IN, wherein the delay time at the rising edge is DLY-R and the delay time at the falling edge is DLY-F. The delay time DLY-R is close to the delay time DLY-F such that a pulse width of the ATD signal, when the rising edge of the address signal A2 is detected, is equal to a pulse width of the ATD signal when the falling edge of the address signal A2 is detected.
FIGS. 3A and 3B show the waveforms of signals of the first and the second known ATD circuits under normal conditions, respectively. During normal operation, an interval PW_ADD between two neighboring address should be one cycle of a write or read operation (tCYC). That is to say, the interval PW_ADD is equal to tCYC, which is bigger than the width of the ATD signal, i.e. DLY_R or DLY_F. The ATD signal in FIG. 3A is the pulse signal ATD1, which has a width of DLY_R at the rising edge of the address signal A1, and a width of DLY_F at the falling edge of the address signal A1. The ATD signal in FIG. 3B is the pulse signal ATD2, which has a width of DLY_R at the rising edge of the address signal A2, and a width of DLY_F at the falling edge of the address signal A2.
If there are some burrs on the address line due to noises, the interval PW_ADD between two neighboring addresses on the address line will be smaller. The width of the burrs is generally small, and therefore the pulse width of the generated ATD signal directly depends on the width of the burrs and is irrelevant to the width DLY_R or DLY_F, as long as the width of the burrs makes the interval PW_ADD smaller than the width DLY_R or DLY_F. FIGS. 3C and 3D show the waveforms of signals of the first and the second known ATD circuits respectively under the condition that burrs exist. As shown in FIGS. 3C and 3D, the widths of the pulse signal ATD1 at the rising edge and falling edge of the address signal A1 are equal to the width of the burrs, namely equal to the width of PW_ADD, which is smaller than the width of the PW_ADD under normal conditions. The widths of the pulse signal ATD2 at the rising edge and the falling edge of the address signal AD2 are equal to the width of the burrs, namely equal to the width of PW_ADD, which is smaller than the width under normal conditions. As described above, a very narrow width of the ATD signal is dangerous, which may result in failure of the read or write operation.

INTEGRATED SILICON SOLUTION (SHANGHAI), INC.


A battery includes a case, an internal terminal, an external terminal, and an insulator. The internal terminal includes an internal terminal base and a shaft. The internal terminal base is disposed inside the case, with the insulator interposed between the case and the internal terminal base. The external terminal includes an external terminal base and a boss. The external terminal base is disposed outside the case, with the insulator interposed between the external terminal base and the case. The boss extends from the external terminal base. The boss receives the shaft of the internal terminal therethrough. The boss is pressure-welded to the shaft of the internal terminal.

The present disclosure relates to batteries and battery manufacturing methods.
JP 2016-100323 A discloses a battery and a battery manufacturing method. The battery disclosed in JP 2016-100323 A includes: a battery case; an internal terminal disposed inside the battery case; and an external terminal. The internal terminal and the external terminal are swaged together. The battery case is provided with a through hole. The internal terminal includes a shaft inserted through the through hole. At a location outside the battery case, the external terminal is fitted to the shaft of the internal terminal. The shaft of the internal terminal includes an end swaged to the external terminal. This provides a rivet-like structure in which the internal terminal and the external terminal are connected to each other, with the battery case located between a base of the internal terminal and a portion of the internal terminal swaged to the external terminal.
The battery disclosed in JP 2014-11073 A includes: an internal terminal including a shaft; and an external terminal. The shaft of the internal terminal includes an end swaged to the external terminal. The peripheral edge of the end of the shaft of the internal terminal is welded to the external terminal. Welding the internal terminal to the external terminal enhances the conductivity between the internal terminal and the external terminal.
JP 55-122694 A discloses an "electromagnetic welding method".

Battery and battery manufacturing method


A protective structure for a semiconductor sensor integrated in a semiconductor substrate for use in a state that is in direct contact with a measuring medium has a semiconducting layer that is applied to the semiconductor substrate, a metal layer and an insulating layer. The insulating layer is disposed between the semiconducting layer and the metal layer and electrically insulates same.

1. Field of the Invention
The present invention relates to a protective structure for semiconductor sensors, and more particularly a monolithic MIS protective structure for semiconductor sensors.
2. Description of the Related Art
Sensors that are exposed to environmental influences in order to be able to detect measured quantities cannot in any case be protected from electric or electrostatic overstress as effectively as other semiconductor devices. Ion-sensitive field-effect transistors (ISFETs), for example, do not have a metallic gate at which protective structures could be realized. On the contrary, here the gate insulator lies functionally exposed in the channel area of the transistor and is thus vulnerable to electric damaging. Such negative influences are, for example, electrostatic discharges (ESD) or disallowed electrical operating conditions such as excess voltage, polarity inversion and the like.
Ion-sensitive field-effect transistors are used in the analysis of liquid media, for example. In these sensors, for example, a drain-source current is regulated through ions in a measuring medium having direct contact with the gate insulator and causing, depending on the ion charge, an electric field there that influences the drain-source current whereby the measuring medium can be analyzed. Therefore, these sensors are also referred to as field-effect based sensors. For a flawless mode of operation and for the stability of the gate insulator, it is important that these semiconductor sensors are protected from a discharge of static voltages and/or from disallowed electrical operating conditions such as polarity inversions.
Currently, voltage-sensitive sensor structures can be protected by allocating a structure to the sensor element that can incorporate, for example, p-n junctions or also capacitor elements. A substantial disadvantage of protective structures in the form of conventional p-n junctions is the relatively high leakage current, whereby a precise potentiometric measurement can be influenced negatively. On the other hand, capacitors are disadvantageous as protective structures to the effect that they are conducting for alternating currents (e.g. EMC stress) and do not provide effective protection from other disallowed operating cases (polarity inversion).

Protective structure for semiconductor sensors

Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.


A recording medium for sublimation type heat-sensitive transfer recording process, in which an image receiving layer comprising a resin composition containing a dyeable resin and at least one phosphite antioxidant shown in Formulas (1), (2), or (3) is formed on a substrate surface. This recording medium for sublimation type heat-sensitive recording methods has extremely superior light resistance, and the image recorded on this recording medium suffers little fade out or discoloration as a result of exposure to light, so that this recording medium is expected to contribute greatly to the spread of video printers and the like. ##STR1## (In Formula (1), R.sub.1 and R.sub.2 represent H or an alkyl group having a number of carbon atoms within a range of 1-20, R.sub.3 and R.sub.4 represent alkyl groups having a number of carbon atoms within a range of 1-20, X represents H or an atomic group having 1-10 carbon atoms as a main skeleton thereof, and n has a value of 1, 2, 3, or 4.) ##STR2## (In Formula (2), R.sub.5 and R.sub.6 represent H or an alkyl group having a number of carbon atoms within a range of 1-20, R.sub.7 represents an alkyl group having a number of carbon atoms within a range of 1-20, Y represents H or an atomic group having 1-10 carbon atoms as a main skeleton thereof, and n has a value of 1, 2, 3, or 4.) ##STR3## (In Formula (3), RS, R.sub.9, R.sub.10, and R.sub.11 represent H or an alkyl group having a number of carbon atoms within a range of 1-20, Z represents H or an atomic group having 1-10 carbon atoms as a main skeleton thereof, and n has a value of 1, 2, 3, or 4.)

1. Field of the Invention
The present invention relates to a recording medium for sublimation type heat-sensitive transfer recording process which forms a recorded image which has superior resistance to fading when exposed to light.
2. Background Art
Sublimation type heat-sensitive transfer recording process are advantageous in that the level of noise produced during recording is low, the apparatus used therefor is small and inexpensive, the maintenance thereof is easy, and the output time is short. Furthermore, since sublimation type dyes are used, by continuously varying the amount of the exothermic energy, high contrast recording may be easily achieved, and such recording exhibits high density and high resolution. As a result, in comparison with other recording methods, such a method is advantageous, especially for producing full color hard copy, and has been adopted as a recording method for color printers, video printers, and the like.
However, as the image recorded by means of such a sublimation type heat-sensitive transfer recording process is formed by means of sublimable dyes, the light resistance thereof is generally poor, and this is disadvantageous in that fade out and discoloration resulting from sunlight or fluorescent light exposure occurs easily. In order to solve this problem, an ultraviolet absorber or a photostabilizer was generally applied to the image receiving layer of the recording medium, and as a result of this, light resistance was somewhat improved; however, this improvement could not be termed sufficient. In addition, methods have been disclosed, such as that in Japanese Laid-Open Patent Application No. Hei 1-127387, in which a specified phenol antioxidant was applied to the image receiving layer, and that of Japanese Laid-Open Patent Application No. Hei 3-19893, and Japanese Laid-Open Patent Application No. Sho 61-229594, in which a specified phosphorus antioxidant was applied to the image receiving layer, and as a result of using these methods, a small increase in light resistance was observed; however, the degree of fade out and discoloration as a result of exposure to light was still large.

Recording medium for sublimation type heat-sensitive transfer recording process


Securely authorizing access to remote resources may be provided. A method may include receiving a request to determine whether a user device is authorized to access at least one resource hosted by a resource server, determining whether the user device is authorized to access the at least one resource based at least in part on whether the user device has been issued a management identifier, providing a response indicating that the user device is authorized to access the at least one resource in response to a determination that the user device is authorized to access the at least one resource hosted by the resource server, and providing a response indicating that the user device is not authorized to access the at least one resource in response to a determination that the user device is not authorized to access the at least one resource.

Managing authorization for software application ("application") usage is critical to ensuring that sensitive resources are protected from unauthorized access. Depending on the sensitivity of any given application, an array of authorization rules may be necessary to ensure that the resources are adequately protected. Some applications may only require ensuring that an authorized user is requesting the resource. Other applications may require compliance with more stringent authorization rules, such as determining whether the user device executing the application is a secure user device. When dealing with applications that access medical records, financial records, or other resources that may pertain to an individual and contain confidential and/or personal information, even more advanced control over application usage may be desired. To date, application management solutions have not addressed the unique security concerns for authorizing application access to remote resources.


A person identification device obtains information including biometric information of a person, detects the biometric information of at least one person from the obtained information, collates each detected biometric information with the biometric information of at least one registrant associated with group information and stored in a storage unit to thereby identify the person having the biometric information detected from the obtained information, classifies a plurality of successively identified persons into group candidates based on predetermined conditions, divides the persons of the group candidates into groups based on the group information of each person stored in the storage unit, and outputs a grouping result to an external device.

1. Field of the Invention
The present invention relates to a person identification device and a person identification method in which biometric information of some of a face, retinas, mouth, irises, fingerprints, palm patterns, ears and the like of a person, and vein geometry of a part of a human body is obtained to collate the information with at least one or more pieces of beforehand registered biometric information.
2. Description of the Related Art
Heretofore, for example, in a person identification device, biometric information of some of a face, retinas, mouth, irises, fingerprints, palm patterns and ears and the like of a person to be identified, and vein geometry of a part of a human body is obtained, and the obtained information is collated with at least one or more pieces of beforehand registered biometric information to thereby judge whether or not the person to be identified is a beforehand registered person (a registrant). In an access control system which controls an access to a security area or an access to a specific apparatus, or in a monitoring system which monitors people, a device has been developed which executes control in accordance with a judgment result obtained by the person identification device. Various application examples of a person identification method for use in the person identification device include a method of collating biometric information obtained from a person to be identified who stands still with beforehand registered biometric information, and a method of collating biometric information obtained from a person to be identified who is moving, for example, walking with beforehand registered biometric information.
For example, in a passer-by identification device which collates biometric information obtained from a person (a passer-by) to be identified who goes along a passageway or the like with beforehand registered biometric information, identification processing can be executed even while the person to be identified is not especially aware of the identification processing being performed. Such a passer-by identification device for identifying the passer-by also covers a case where a plurality of continuously walking passers-by are identified. In such a case, in a conventional person identification device, even the plurality of continuously walking people are individually subjected to the identification processing one by one. In addition, Jpn. Pat. No. 3617373 (Document 1) describes a technology in which the number of the continuously walking people is measured to prevent missing of people.

Biometric determination of group membership of recognized individuals


Copper wire coated with a layer of zinc is heated to a temperature (T.sub.1) sufficient for the formation of a brass phase .beta., and the temperature is maintained until complete diffusion of the zinc. The thickness of the zinc covering can be chosen in such a way that once the zinc is completely diffused, the wire consists of a brass phase .beta. in its periphery and of copper in its central part. The wire is then heated to a temperature (T.sub.2) necessary for the formation of brass phase .alpha., and the central copper part of the wire is transformed into brass phase .alpha..

For wire electroerosion, one ordinarily uses brass wire whose structure and composition are suited for obtaining a wire which meets the needs arising with regard to mechanical breaking stress as well as conductivity. The manufacture of a brass wire corresponding to this type of alloy is relatively expensive. Added to this is the fact that for each variation in the chemical composition of the wire, it is necessary to devise a new base alloy.

Process for the manufacture of wires with a brass surface, for the purpose of wire electroerosion


A retractable lighting apparatus for the upper surface of a roof of a vehicle includes at least one lighting member adapted to be raised or lowered relative to the upper surface of the roof, and a device for effecting the raising and lowering of the lighting apparatus. The lighting apparatus has its own upper surface and a base component into which at least one telescopic component can be retracted.

There are many applications of the lighting system of the invention however for convenience sake it will be discussed here in relation to emergency and warning lights.
Many vehicles and other objects use light signals to indicate their presence or to provide hazard warnings. In particular most emergency vehicles have an array of sirens and emergency lighting mounted on their roofs. These assemblies are generally large and bulky and provide significant increased drag to a vehicle thereby impeding both performance, handling and fuel efficiency.
Many vehicles, such as unmarked vehicles used by police, have a requirement that any warning or other lighting used to identify the vehicle be otherwise hidden when not in use. This is usually achieved by using removable sirens and flashing lights and locating them on a vehicle roof when required. Clearly this is a clumsy procedure.
Marine vessels too are required to carry lights at night for navigation safety purposes however these generally have to be mounted so that they are not only constantly exposed to the elements but can be easily damaged by contact with berthing facilities and the like.

Retractable telescoping lighting device for roof of a vehicle