A cDNA encoding geranyl diphosphate synthase from peppermint has been isolated and sequenced, and the corresponding amino acid sequence has been determined. Accordingly, an isolated DNA sequence (SEQ ID No:1) is provided which codes for the expression of geranyl diphosphate synthase (SEQ ID No:2) from peppermint (Mentha piperita). In other aspects, replicable recombinant cloning vehicles are provided which code for geranyl diphosphate synthase or for a base sequence sufficiently complementary to at least a portion of the geranyl diphosphate synthase DNA or RNA to enable hybridization therewith (e.g., antisense geranyl diphosphate synthase RNA or fragments of complementary geranyl diphosphate synthase DNA which are useful as polymerase chain reaction primers or as probes for geranyl diphosphate synthase or related genes). In yet other aspects, modified host cells are provided that have been transformed, transfected, infected and/or injected with a recombinant cloning vehicle and/or DNA sequence encoding geranyl diphosphate synthase. Thus, systems and methods are provided for the recombinant expression of geranyl diphosphate synthase that may be used to facilitate the production, isolation and purification of significant quantities of recombinant geranyl diphosphate synthase for subsequent use, to obtain expression or enhanced expression of geranyl diphosphate synthase in plants in order to enhance the production of monoterpenoids, to produce geranyl diphosphate in cancerous cells as a precursor to monoterpenoids having anti-cancer properties or may be otherwise employed for the regulation or expression of geranyl diphosphate synthase or the production of geranyl diphosphate.

Geranyl diphosphate synthase (GPP synthase) is one of a family of enzymes called prenyl transferases that catalyze C.sub.5 elongation reactions to form the linear (acyclic) precursors of the various terpenoid families. GPP synthase catalyzes the condensation of dimethylallyl diphosphate (DMAPP) and isopentenyl diphosphate (IPP) to form geranyl diphosphate (GPP) which is the immediates, C.sub.10 acyclic precursor of the monoterpenes (Wise, M. L. and Croteau, R., in Cane, D. E., ed., "Comprehensive Natural Products Chemistry: Isoprenoids, Vol. 2", Elsevier Science, Oxford, 1997 (in press) (FIG. 1). Farnesyl diphosphate synthase (FPP synthase), a related prenyl transferase, utilizes GPP and IPP as substrates to form farnesyl diphosphates (FPP), which is the immediate, C.sub.15 precursor of the sesquiterpenes (FIG. 1). Another prenyl transferase, geranylgeranyl diphosphate synthase (GGPP synthase), catalyzes the condensation of farnesyl diphosphate and IPP to form geranylgeranyl diphosphate (GGPP) which is the immediate C.sub.20 precursor of the diterpene family (FIG. 1). Other types of prenyl transferases can utilize GGPP and IPP as substrates to form very long chain molecules, such as natural rubber. Poulter C. D. and Rilling, H. C., Accts. Chem. Res. 11: 307-313 (1978); Scolnik, P. A. and Bartley, G., Plant Mol. Biol. Rep. 14: 305, 307 (1996).
The basic reaction mechanism for all of these prenyl transferases is the same, and consists of three steps (see FIG. 2 in which the reaction catalyzed by geranyl diphosphate synthase is presented as illustrative of the general reaction mechanism). With reference to FIG. 2, in the first step an allylic diphosphate ester (2a) is ionized to the stable carbonium ion (2b). The carbonium ion then attacks the double bond of isopentenyl diphosphate (2c) to yield another carbonium ion (2d). In the final step of the cycle, a proton is eliminated from the newly formed carbonium ion (2d) to form a terpenoid containing a new allylic double bond (2e). In the reaction catalyzed by GPP synthase, the allylic diphosphate ester is dimethyl allyl diphosphate (FIG. 1 and FIG. 2). In the reactions catalyzed by FPP synthase and GGPP synthase the allylic diphosphate ester is geranyl diphosphate and farnesyl diphosphate, respectively (FIG. 1).
Unlike FPP synthase and GGPP synthase, which produce GPP as an intermediate and which are nearly ubiquitous (Ogura, K. and Koyama, T., in Ogura, K. and Sankawa, U., eds., "Dynamic Aspects of Natural Products Chemistry" Kodansha/Harwood Academic Publishers, Tokyo, pp. 1-23, 1997), geranyl diphosphate synthase is largely restricted to plant species that produce abundant quantities of monoterpenes. Because both FPP synthase and GGPP synthase produce only negligible levels of GPP as a free intermediate on route to FPP and GGPP (Ogura, K. and Koyama, T., supra), it is geranyl diphosphate synthase that provides the crucial link between primary metabolism and monoterpene biosynthesis and that serves as the essential driver of monoterpene biosynthesis (Wise, M. L. and Croteau, R., supra).
Any attempt, therefore, to exploit recombinant methods to increase the yield of monoterpene-producing (essential oil) species, or to genetically engineer the monoterpene biosynthetic pathway into any non-producing species (e.g., field crops, fruit-bearing plant species and animals) requires access to a geranyl diphosphate synthase gene or cDNA clone. Co-expression of geranyl diphosphate synthase along geranylgeranyl diphosphate (GGPP) which is the immediate C.sub.20 precursor of the with a selected monoterpene synthase, such as (-)-limonene synthase (Colby et al., J. Biol. Chem. 268:23016-23024, 1993), and any subsequent pathway enzymes, should allow production of the corresponding monoterpene product(s) from simple carbon substrates, such as glucose, in any living organism.
Monoterpenes are utilized as flavoring agents in food products, and as scents in perfumes (Arctander, S., in Perfume and Flavor Materials of Natural Origin, Arctander Publications, Elizabeth, N.J.; Bedoukian, P. Z. in Perfumery and Flavoring Materials, 4th edition, Allured Publications, Wheaton, Ill., 1995; Allured, S., in Flavor and Fragrance Materials, Allured Publications, Wheaton, Ill., 1997. Monoterpenes are also used as intermediates in various industrial processes. Dawson, F. A., in The Amazing Terpenes, Naval Stores Rev., Mar./Apr., 6-12, 1994. Monoterpenes are also implicated in the natural defense systems of plants against pests and pathogens. Francke, W. in Muller, P. M. and Lamparsky, D., eds., Perfumes: Art, Science and Technology, Elsevier Applied Science, New York, N.Y., 61-99, 1991; Harborne, J. B., in Harborne, J. B. and Tomas-Barberan, F. A., eds., Ecological Chemistry and Biochemistry of Plant Terpenoids, Clarendon Press, Oxford, 399-426, 1991; Gershenzon, J and Croteau, R in Rosenthal, G. A. and Berenbaum, M. R., eds., Herbivores: Their Interactions with Secondary Plant Metabolites, Academic Press, San Diego, 168-220, 1991.
There is also substantial evidence that monoterpenes are effective in the prevention and treatment of cancer (Elson, C. E. and Yu, S. G., J. Nutr. 124: 607-614, 1994.). Thus, for example, limonene, perrilyl alcohol and geraniol have each been shown to have chemotherapeutic activity against a very broad range of mammalian cancers (see, for example, (1) limonene, Elegbede et al., Carcinogenesis 5:661-665, 1984; Elson et al., Carcinogenesis 9:331-332, 1988; Maltzman et al., Carcinogenesis 10:781-785, 1989; Wattenberg, L. W. and Coccia, J. B., Carcinogenesis 12:115-117, 1991; Wattenberg, L. W. and Coccia, J. B., Carcinogenesis 12:115-117, 1991; Haag et al., Cancer Res. 52:4021-4026, 1992; Crowell, P. L. and Gould, M. N., CRC Crit. Rev. Oncogenesis 5:1-22, 1994; (2) perillyl alcohol, Mills et al., Cancer Res. 55:979-983, 1995; Haag, J. D. and Gould, M. N., Cancer Chemother. Pharmacol. 34:477-483, 1994; Stark et al., Cancer Lett. 96:15-21, 1995 and (3) geraniol, Shoff et al., Cancer Res. 51:37-42, 1991; Yu et al., J. Nutr. 125:2763-2767, 1995; Burke et al., Lipids 32:151-156, 1997. ).
Cancer cells can be modified to produce therapeutic amounts of a monoterpene having anti-cancer properties by targeting the cognate monoterpene synthase protein to cancer cells, or by introducing a monoterpene synthase gene into cancer cells. This approach to cancer therapy is complicated, however, by the fact that the natural distribution of geranyl diphosphate synthase is largely restricted to plant species that produce abundant quantities of monoterpenes. Thus, animal cells do not naturally produce the monoterpene precursor geranyl diphosphate. Consequently, the genetic manipulation of cancer cells to produce endogenous monoterpenes having anti-cancer properties requires the introduction of a gene encoding geranyl diphosphate synthase, together with a gene encoding a monoterpene synthase that produces a monoterpene having anti-cancer properties. Similarly, if the protein targeting approach is utilized, both geranyl diphosphate synthase protein and monoterpene synthase protein must be targeted to cancer cells.
Standard protein targeting techniques can be used to introduce geranyl diphosphate synthase along with a monoterpene synthase, such as limonene synthase (Colby et al., J. Biol. Chem. 268:23016-23024, 1993), into animal cells with specific targeting to tumors. See, e.g., Wearley, L. L., Critical Reviews in Therapeutic Drug Carrier Systems, 8(4): 331-394, 1991; Sheldon, K et al., Proc. Nat'l. Acad. Sci. USA., 92(6): 2056-2060, 1995. In addition, standard gene therapy techniques can be used to target a GPP synthase gene and a monoterpene synthase gene to cancerous cells for endogenous synthesis of monoterpenes having anti-cancer properties. For reviews of gene targeting technology see; Mahato R. I. et al., Pharmaceutical Research 14(7): 853-859, 1997; Rosenthal, F. M. and Mertelsmann, R., Onkologie 20(1): 26-34, 1997; Buckel, P., Trends in Pharmacological Sciences 17(12): 450-456, 1996; Roth, J. A. and Cristiano, R. J., J. Nat'l Cancer Inst. 89(1): 21-39, 1997; Ledley, F. D, Pharmaceutical Research 13(11): 1595-1614, 1996.
To date, extracts containing geranyl diphosphate synthase activity have been isolated from several plant sources, including grape (Clastre et al., Plant Physiol. 102:205-211, 1993); geranium (Suga, T. and Endo, T., Phytochemistry 30:1757-1761, 1991); sage (Croteau, R. and Purkett, P. T., Arch. Biochem. Biophys. 271:524-535, 1989) and Lithospermum (Heide, L. and Berger, U., Arch. Biochem. Biophys. 273:331-338, 1989). Only the enzyme from grape has been purified to homogeneity (Clastre et al., supra).
Table 1 summarizes the limited, available physical and chemical characteristics of geranyl diphosphate synthase isolated from several species.
TABLE 1 ______________________________________ Deduced characteristics of geranyl diphosphate synthase.sup.a ______________________________________ Native molecular weight 66 kDa (V), 70 kDa (M), 73 kDa (L), 100 kDa (S) Subunit configuration monomer (V), dimer (M) Cofactor requirements Divalent metal ions required for catalysis Mg.sup.2+ (M,S,L) or Mn.sup.2+ (P,V) Apparent V.sub.max 9.4 .mu.mol/min/mg (L) 150 nmol/h/mg (S) Apparent K.sub.m IPP 14 .sub..mu.M (L), 8.5.sub..mu.M (V), 7.3 .sub..mu.M (S) DMAPP 83.sub..mu.M (L), 56.8.mu.M (V), 5.6.sub..mu.M (S) pH optimum 7.0 (S), 6.75 (L) Isoelectric point 4.95 (L) 5.42 (M18) Inhibitors Thiol-directed reagents (S), aminophenylethyl diphosphate (V), geranyl diphosphate (L, M) Catalytic enhancers under in vitro 1% v/v Triton-X 100 (P,V,M) conditions ______________________________________ .sup.a Geranyl diphosphate synthase characteristics are compiled from the data disclosed in: Croteau, R and Purkett, P. T., Arch. Biochem. Biophys. 271: 524-535, 1989; Heide, L. and Berger, U., Arch. Biochem. Biophys. 273 331-338, 1989; Suga, T. and Endo, T., Phytochemistry 30: 1757-1761, 1991; Clastre et al., Plant Physiol. 102: 205-211, 1993. Uppercase letters in parentheses designate the following species: (M) Mentha spicata, (v) Viti vinifera, (L) Lithospermum erythrorhizon, (S) Salvia officinalis, (P) Pelargonium roseum. (M18) refers to the "pseudomature" form of the GPP synthase encoded by cDNA clone Mp13.18 from Mentha piperita as described at page 8, supra.
These data reveal that the physical and chemical properties of geranyl diphosphate synthase vary considerably between species. For example, molecular mass varies from 66 kDa (in grape) to 100 kDa (in sage). Similarly, the isoelectric point of geranyl diphosphate synthase isolated from Lithospermum is 4.95, while the "pseudomature" form of mint geranyl diphosphate synthase (i.e., the protein encoded by the cDNA insert of clone Mp 13.18 having the first 48 amino acids deleted from the amino terminus) has an isoelectric point of 5.42. This variation in the physical and chemical properties of geranyl diphosphate synthase isolated from different species is reflected in the fact that the published purification protocols are each significantly different from the others.
Amino acid sequence data for geranyl diphosphate synthase has not been reported in the art. Although several DNA sequences encoding plant-derived FPP synthases and GGPP synthases are available (Scolnik, P. A. and Bartley, G. E., Plant Mol. Biol. Report 14:305-319, 1996), no genes for geranyl diphosphate synthase have thus far been reported.

Washington State University Research Foundation


A varistor includes a ceramic insulating substrate, a varistor section having an outer surface, and first and second external electrodes provided on the outer surface of the varistor section. The varistor section includes a varistor layer on the ceramic insulating substrate, first and second internal electrodes, and first and second via-conductors embedded in the varistor layer and exposing from the varistor layer. The second internal electrode has a portion facing the first internal electrode. The first internal electrode and the portion of the second internal electrode sandwiches at least a portion of the varistor layer. The first and second via-conductors are connected to the first and second internal electrodes, respectively. The first and second external electrodes are connected to the first and second via-conductors, respectively. This varistor has a small thickness and a large mechanical strength.

Electronic devices, such as a portable telephone, have recently had small sizes and high performance, and accordingly had circuits which are arranged densely and which have withstand voltages decrease. This increases breakdown of the circuits caused by an electrostatic discharge pulse generated when a human body contacts terminals of the electronic devices.
In order to prevent the circuits from the breakdown caused by the electrostatic discharge pulse, a conventional laminated chip varistor disclosed in Japanese Patent Laid-Open Publication No. 08-31616 is provided between a ground and a line to which the electrostatic discharge pulse are supplied. The varistor causes the electrostatic discharge pulse to bypass the circuits to reduce a voltage applied to the circuits.
Electronic devices have small sizes and high performance and accordingly, the number of components to address the electrostatic discharge pulse. Particularly for varistors, not only a single varistor but also a varistor array including plural varistors are demanded. Such varistors are demanded to be thin to provide small and thin electronic devices.
Zinc-oxide based material, which the conventional laminated chip varistor disclosed in Japanese Patent Laid-Open Publication No. 08-31616 employs, has a small strength to bending. The conventional varistor necessarily has a certain thickness to provide a predetermined strength, thus hardly having a small thickness. For example, a commercially-available laminated chip varistor having a length of about 1.6 mm and a width of 0.8 mm needs to have a thickness larger than 0.8 mm. If having a thickness smaller than this, the laminated chip varistor needs to have a smaller size, thus hardly providing a thin and large varistor. Accordingly, it is difficult to provide a varistor array including a large number of varistors.


A copy-protected-state indicating MPEG-TS data output unit (3) holds a bit stream obtained by previously compressing and encoding image and/or audio data representing that recording desired by the user has ended in failure because the contents is copy-protected. When copy control information (V2) outputted from an IEEE 1394 interface (1) indicates a copy-protected state, a selecting unit (20) selects copy-protected-state indicating MPEG-TS data (V3) outputted from the copy-protected-state indicating MPEG-TS data output unit (3) and outputs it as to-be-recorded MPEG-TS data (V4). Thereby, the data (V3) is recorded.

1. Field of the Invention
The present invention relates to a copy protection technique for use in devices for recording digital contents (such as D-VHS VCRs or DVD recorders).
2. Description of the Background Art
Recently, digitization of contents distributed, for example, in broadcasts and over the Internet has advanced and VTRs capable of recording and playing back such digital contents or data as it is have been developed. In such digital recording systems, no data degradation occurs even if the data is copied to a recording medium and thus it is easily possible to generate the same duplicate as an original. From this, the necessity for securing a copyright on the contents is in strong demand.
The IEEE 1394 interface (LSI circuit) is becoming a prominent digital interface for use in digital AV (Audio Visual) data communications between digital equipment. One of widely adopted copy protection systems in the IEEE 1394 interface is the 5C DTCP (Digital Transmission Content Protection) scheme standardized by the CPTWG (Copy Protection Technical Working Group).
The 5C DTCP defines three levels of copy protection states for restricting copying of transmission data, namely, "Copy Never" (copy protected), "Copy One Generation" (only one generation of copy permitted) and "Copy Free" (free copy permitted). In data recording, the following control is effectuated according to this status information: (1) When the status information indicates a "Copy Never" state, data recording is not made; (2) when the status information indicates a "Copy Free" state, data recording is made; and (3) when the status information indicates a "Copy One Generation" state, data recording is made after the current status information is changed into "Copy Never" or "No More Copies" which indicates that recording has already been made. Such information is called CCI (Copy Control Information). The CCI is generally contained in transmission data and its storage location and definition vary depending on the data format.
To handle digital contents including such CCI to meet the copyright owner's or user's needs, recording equipment having the function of reading and writing CCI contents is required. However, handling the CCI is not easy for such equipment that records and reproduces transmission data without much concern for the data format (such as D-VHS video recorders or DVD recorders).
The 5C DTCP scheme, therefore, provides an EMI (Encryption Mode Indicator) field indicating CCI contents, inside a transfer packet header so that even the equipment as above described operating without much concern for the data format can readily achieve copy control. As shown in FIG. 5, the CCI in the EMI field is represented as two bits. More specifically, a 2-bit binary value "00" represents a "Copy Free" state; a binary value "01" represents a "No More Copies" state; a binary value "10" represents a "Copy One Generation" state; and a binary value "11" represents a "Copy Never" state. The EMI provides the "No More Copies" state which is not provided by the CCI. This state means that MPEG data in packet data, including CCI indicating a "Copy One Generation" state, has been recorded once and thus no more recording thereof is permitted.
In the IEEE 1394 interface standard, as shown in FIG. 6, a CIP header is added to data transmitted over a bus and further an isochronous packet header is provided. In IEEE 1394 isochronous packet transmission, the EMI is transmitted as part of the isochronous packet header (FIG. 6) as shown in FIG. 7.
The 5C DTCP scheme performs data encryption when copy-controlled data is transmitted, i.e., when the EMI is set to either "Copy Never", "Copy One Generation" or "No More Copies". And, the key to decrypt the data is given only to equipment (sink) authorized by data transmission equipment (source). Thereby the 5C DTCP scheme prevents the CCI from being tapped or tampered with by other unauthorized equipment.
Data encryption is performed in various modes according to the EMI of data: "Copy Never"; "Copy One Generation"; or "No More Copies". Thus, data receiving equipment (sink) should perform data decryption in a mode responsive to the EMI value. Accordingly, even if the EMI value is tapered with during transmission, the sink cannot decrypt data properly, which thereby prevents unauthorized copying.
However, it is impossible to record CCI on a recording medium without changing the data format including CCI or EMI for preventing unauthorized copying on channels; therefore, another CCI for preventing unauthorized copying is required to add to data on the recording medium.
The D-VHS standard defines three levels of CCI called CGMS (Copy Generation Management System) to prevent unauthorized copying of recording data. This CGMS allows easy copy control even with equipment operating without much concern for the data format. In the D-VHS standard, a CGMS field indicating CCI contents is provided in a header of D-VHS recording data.
In the D-VHS standard, when recording data is in the "MPEG-2 transport packet" form, each MPEG-2 transport packet of recording data (188 bytes) is divided into two parts, i.e., 96 bytes of data and 92 bytes of data, and stored in two sync blocks as shown in FIG. 8. These sync blocks are stored in a main code area of a track structure as shown in FIG. 9 and recorded on a recording medium. Herein, the "track" refers to a unit of recording data recorded on a recording medium in the D-VHS standard.
A main header (FIG. 8) is described by a set of 12 sync blocks as shown in FIGS. 10 and 11. In a set of 12 sync blocks, a field composed of two bits, bit 7 and bit 6, of the first byte of the eleventh sync block represents /CGMS data indicating CCI of an MPEG-2 transport packet of recording data.
As shown in FIG. 12, CGMS data is composed of two bits. More specifically, a 2-bit binary value "00" represents a "Copy Permitted" state for permitting copying; a binary value "01" represents a "No Information" state for an invalid value; a binary value "10" represents a "One Generation of Copy Permitted" for permitting only one generation of copying; and a binary value "11" represents a "Copy Restricted" state for restricting copying. The /CGMS field (FIG. 10) in the main header (FIG. 8) holds a value obtained by inverting the CGMS data bits.
In digital recording of data contents received via the IEEE 1394 digital interface with digital recorders such as D-VHS VCRs or DVD recorders, when the EMI of transmission data is set to either "Copy Never" or "No More Copies", either the data recording itself will not be made or invalid data will be recorded since the contents is copy-protected.
If the users try to make recording of contents whose EMI is set to "Copy Never" or "No More Copies" without knowing the CCI of the contents, recording intended by the user will result in failure, in which case the users cannot easily know the cause of the failure at the time of playback. The users thus might possibly mistake it for the breakdown of their recorders and then bring their complaints, for example, against recorder manufactures. This may become a heavy burden on the recorder manufactures.

MPEG data recorder having IEEE 1394 interface


Systems and methods presented herein provide for input/output shipping between storage controllers in a storage system. One storage system comprises a plurality of logical volumes, a host driver operable to process input/output requests to the logical volumes, and a plurality of storage controllers coupled between the server and the logical volumes. A first of storage controllers is operable to receive an input/output request from the host driver for one of the logical volumes, and transfer a command to a second of the storage controllers to retrieve the data of the input/output request. The second storage controller processes the command from the first storage controller, and retrieves the data associated with the input/output request.

Single server high availability (SSHA) storage systems have multiple controllers present in a topology, typically employing Redundant Array of Independent Disk methodologies. In some persistent reservation implementations, one storage controller has exclusive access to a particular set of logical volumes configured from a plurality of disk drives or other storage devices. Another storage controller in this implementation may have exclusive access to another particular set of logical volumes and be able to "see" logical volumes of its counterpart storage controller without being able to access those logical volumes, and vice versa. Because of this, a host driver of the server processing input/output (I/O) requests to the logical volumes may misdirect a request to a storage controller. Serial Attached Small Computer System Interface (SAS) storage controllers overcome this problem by rerouting or "shipping", the I/O request and its associated data over a SAS connection between the storage controllers. But, this implementation requires much computational processing and time to perform the transfer. Cache mirroring (e.g., in a multipath I/O system with storage controller redundancy) is another computationally intensive and lengthy implementation where data is pulled by one storage controller responding to the I/O request and transferred to the other storage controller through the SAS connection between controllers.

Input/output request shipping in a storage system with multiple storage controllers

Avago Technologies General IP (Singapore) Pte. Ltd.


The present invention may provide a small RNA detection sensor comprising: at one end thereof, a first sensing region comprising nucleotides having a sequence complementary to target small RNA; and a PCR-capable region that is coupled to the first sensing region, the small RNA detection sensor to synthesize a replication region complementary to the PCR-capable region by a DNA polymerase by using the target small RNA as a primer, and amplify the PCR-capable region and the replication region.

Small RNAs include microRNA (miRNA), small interfering RNA (siRNA), and Piwi-interacting RNA (piRNA), and these small RNAs regulate gene expression through a mechanism of binding to messenger RNAs (mRNAs), to which small RNAs are complementarily bindable, and cleaving the mRNAs, or inhibiting translation into proteins. Small RNAs are known to play pivotal roles in various biological processes such as cell development and differentiation, programmed cell death, and immune responses, and it is known that the differential expressions of specific small RNAs in cells are associated with various diseases including cancers. Therefore, detecting specific small RNAs with high efficiency is emerging as an essential issue in the fields of medical life research and disease diagnosis.
Existing detection techniques are mainly based on a technique of ligating an adaptor consisting of DNA to the 5′ and 3′ regions of small RNAs, or ligating poly(A) tail RNA to an adaptor, and then converting the resultant structure into cDNA using reverse transcriptase, followed by polymerase chain reaction (PCR) amplification. In these detection methods, the recognition efficiency of a target is too low in the reverse transcription process, and in many cases, since small RNAs have a short length, inaccurate results are often caused by non-specific primer interactions during PCR-based amplification. Besides, by using detection methods such a nucleic acid amplification reaction, it is generally impossible to directly analyze the nucleotide sequences of amplified nucleic acids after the nucleic acid amplification process and to analyze the nucleotide sequences, an additional library production procedure for sequencing is required.

Small RNA detection method based on small RNA primed xenosensor module amplification


Exemplary systems and methods are disclosed for allocating resources in a breeding pipeline to multiple origins. One exemplary method includes accessing a data structure including data representative of multiple origins, in which the data includes, for each of the multiple origins, a trait performance expression or genotypic component information. The exemplary method further includes determining a resource allocation, which allocates n resources among the multiple origins based on a probability associated with the trait performance expressions and/or the genotypic components for the origins, and then allocating the n resources in the breeding pipeline for the multiple origins, based on the determined resource allocation.

This section provides background information related to the present disclosure which is not necessarily prior art.
In plant development, modifications are often made in the plants either through selective breeding or genetic manipulation. Based on the particular selection or manipulation, the resulting plant material is introduced into a breeding pipeline, where plants are then created, grown, and tested. When performance of the plants is at or above an expected threshold, or at a highest performance, for example, for a given phenotype, or where frequencies of genotypes are at or above a certain threshold, for example, etc., the plants may be considered target plants for advancement to further development and/or commercial implementation.
Corresponding reference numerals indicate corresponding parts throughout the several views of the drawings.

Methods and systems for use in implementing resources in plant breeding


According to examples, an apparatus may include a processor and a non-transitory computer readable medium that the processor may execute to initiate a testing process of the apparatus following a boot up of the apparatus, in which a popup message is displayed on the apparatus following the boot up and the popup message blocks performance of the testing process and in which the apparatus is to enter into a lock mode following the popup message being displayed. While the apparatus is in the lock mode, the apparatus may be caused to emerge from the lock mode, in which emergence from the lock mode is to dismiss the popup message from being displayed on the apparatus. In addition, execution of the testing process of the apparatus may be continued following dismissal of the popup message.

Mobile devices, such as mobile phones, tablet computers, and the like, are often tested to ensure that the mobile devices are operating properly prior to the mobile devices being delivered to customers or to distributors. In many instances, testing may be performed on both the hardware and the software of the mobile devices. The testing may include monitoring and trouble-shooting of software applications, content, and the like. The testing may also include verification and validation of hardware and software applications loaded on the mobile devices.

Execution of testing processes on apparatuses


A system and architecture that supports an integrated imaging module for use between networks and portable communications products. The integrated imaging module contains a lens, memory, an input/output device, and a multi-function semiconductor device, such as a Complementary Metal-Oxide Semiconductor (CMOS). Within the design of the multi-function semiconductor device are the functions of still and full-motion digital imaging, image processing, automatic identification, a secure personal database, biometric attribute identification for access control, personal finance information, wireless communication protocols, general purpose processing, and memory. The module may be incorporated into any portable wireless communication product and used to capture text and image data for incorporation into a wireless transmission to a remote device.

Ornamental designs that incorporate digital cameras with cellular telephones and a portable computer into a single housing are known in the art. One example of such a design is shown in U.S. Pat. Des. 405,457 issued Feb. 9, 1999, to Kawashima. A cellular telephone is illustrated essentially affixed to the side of a digital camcorder with each unit interfaced to a central processor, yet for all purposes, each component operates independently of the other. This design is deficient in that the capabilities of the three identified components are not functionally integrated and each is unable to take advantage of the features and benefits of the others. Another example is found in U.S. Pat. No. 5,917,542 issued Jun. 29, 1999, to Moghadam, et al., which refers to a system and method for digital image capture and transmission. A digital camera containing a short term and long term memory capability is combined with a wireless communication means for transmitting individually captured digital images. The design is effective in determining signal strength and assuring successful transmission of an image, but deficient in that the device does not provide the capabilities of automatic identification, voice communication, or other interactive business functions. Other examples of the wireless transmission of video images are also known in the art. In U.S. Pat. No. 4,884,132 issued Nov. 28, 1989 to Morris, et al., a security camera is disclosed that captures images and relays those images to remote stations via wireless transmission. However, the Morris patent is directed to the transmission of video images and does not provide users with a range of complementary functionality.
Numerous examples exist showing various portable computer terminals; some with integrated communication means and a means for reading bar codes. These terminals include large on-board memory capacity, allow for the reading of bar codes and subsequent wireless transmission of the decoded information to a remote site. These terminals are deficient in that they are dedicated to the art of automatic identification and do not provide for the cumulative capability of automatic identification, two-way voice communication, transmission of instantly captured digital images, and the conduct of electronic commerce and personal finance activities, and the advantages appurtenant to such a combination.
Methods for augmenting the functionality of mobile telephones are also known in the art. U.S. Pat. No. 5,887,266 issued Mar. 23, 1999 to Heinonen, et al., discloses a method for using applications in a mobile station. The method requires an application-bearing module, such as a removable PCMCIA memory card, to be physically inserted into and connected with the mobile station or telephone. The application software is then allowed to interact with the mobile station operating system to execute the application. Through this, the on-board memory capacity of the mobile station is effectively increased to allow the inclusion of application software. Unfortunately, this technique also limits the number of applications, and the size of the applications, to only those that can reside fully within the capacity of the removable memory card.
Remote access to or from networked computers is also known in the art. U.S. Pat. No. 5,544,320 issued Aug. 6, 1996, to Konrad refers to a system for access to remote information services. Employed is the concept of distributed processing wherein the architecture specifically avoids providing functionality to a component that is the primary responsibility of another component and, specifically, envisions that the local host be a local multi-user computer system, a workstation, or a Personal Computer. The disclosed design and architecture precludes user mobility, requires significant computer memory, processing power, detailed user input, and a wired telecommunications interface resident at the local host. In U.S. Pat. No. 5,790,977 issued Aug. 4, 1998, to Ezekiel, a host computer system is provided containing access to a remote instrument. In response to a request from the control and data acquisition software running on the host system, data acquired by the remote instrument is forwarded to the host system. This system is deficient in that the remote data acquisition instrument acts as a single purpose slave device unable to perform multiple applications or serve as a means of independently activating functions resident on the remote host computer system.

System and architecture that supports a multi-function semiconductor device between networks and portable wireless communications products


A mist collection device capable of suctioning and recovering mist generated at the time of ejecting a liquid is disclosed. The mist collection device includes an exhaust duct having a suction portion which is installed to extend downwardly to suction external air. The suction portion is provided with a suction port extending in a vertical direction, and an upper end portion, which communicates with the exhaust duct, of the suction portion is installed to protrude in an annular shape from an inner bottom portion of the exhaust duct.

1. Technical Field
The present invention relates to a mist collection device, a liquid ejecting apparatus, and a method for controlling the mist collection device.
2. Related Art
Ink jet printers are widely known as a liquid ejecting apparatus which ejects a liquid onto a medium in the related art. In such a printer, there is a printer capable of performing a printing process by ejecting ink (liquid) onto a transported paper sheet (medium) from nozzles provided in a liquid ejecting head (for example, JP-A-2005-271316).
The printer disclosed in JP-A-2005-271316 includes an exhaust duct and an exhaust fan so as to recover mist generated when the ink is ejected.
Meanwhile, the printer disclosed in JP-A-2005-271316 includes a movable cap for receiving liquid droplets, and a wiper for sweeping the inside of the exhaust duct so as to suppress the mist, which is adhered to an inside wall of the exhaust duct, from flowing down and running down as liquid droplets to stain the paper sheet.
However, if the cap and the wiper are provided, the configuration thereof becomes complicated. Since the inside of the exhaust duct should be frequently swept to prevent the liquid from running down, there is a problem in that the maintenance is inconvenient. For this reason, there has been demand to recover the mist while suppressing the liquid from running down from the exhaust duct.

Mist collection device, liquid ejecting apparatus, and method for controlling mist collection device


A vehicle control system is for a vehicle including a data communications bus extending throughout the vehicle, and at least one vehicle device connected to the data communications bus. The vehicle control system includes a a true controller at the vehicle for controlling the vehicle device via a true command on the data communications bus. The true controller also controls the vehicle device via a respective counteracting command on the data communications bus based upon detecting a rogue controller attempt to control the at least one vehicle device via a rogue command on the data communications bus. The true controller may thus counteract a rogue controller attempt to start the engine, unlock vehicle doors, roll down windows, and/or disarm the vehicle security system, for example.

A remote vehicle control system may be used to permit a user control of one or more vehicle devices from a distance. A typical remote vehicle control system, for example, in a more modern vehicle may include a controller connected to a plurality of vehicle devices via a data communications bus, and a remote transmitter providing the controller with remote control signals. The vehicle devices, for example, may operate the engine starter, the door locks, the power windows, or the alarm system.
An example of such a system is U.S. Pat. No. 5,719,551 to Flick, which discloses a remote transmitter that can remotely control a number of vehicle devices. The controller in the Flick '551 patent is responsive to the remote transmitter and sends command codes over a data communications bus to the vehicle devices. Similarly, U.S. Pat. Nos. 6,275,147, 6,756,885, 6,756,886, and 6,812,829, to Flick also disclose a controller/transmitter used to remotely control a number of vehicle devices via command codes sent over a communications data bus.
U.S. Pat. No. 5,583,479 to Hettich et al. also discloses a vehicle controller connected to a number of vehicle devices via a data communications bus and a remote transmitter in communication with the controller. The Hettich et al. patent further discloses that if the alarm system is not deactivated correctly, then the vehicle devices will be impaired or prevented from working properly.
U.S. Pat. No. 6,232,873 to Dilz et al. discloses a vehicle security system that detects if an original control unit is no longer active. If the security system determines that the original control unit is no longer active, an alternate circuit that remains active in the vehicle activates an electronic immobilization system.
Although conventional remote vehicle control systems operating via the data communications bus have made significant advances in convenience for the user, the overall security may still be an issue. For example, a would-be thief gaining access to the data bus, such as from under the vehicle, may generate rogue commands on the data bus compromising vehicle security. The would-be thief could temporarily connect a rogue controller to the data bus and cause the windows to roll down or the doors to unlock. Once inside the vehicle, the would-be thief could again connect to the data communications bus and start the engine. Of course, if the vehicle had a vehicle security system, the would-be thief could disarm the vehicle security system via the data communications bus.

Vehicle control system and associated method for counteracting rogue command


A method and apparatus are disclosed for performing a transaction at a hand held device. The method comprises the steps of accessing a virtualized operating system and Automated Teller Machine (ATM) application at a hand held device and performing a customer transaction at the hand held device using the virtualized operating system and ATM application.

Many types of Self-Service Terminal (SST) are known which enable a wide variety of customer transactions to be performed at the SST by a customer. For example, an Automated Teller Machine (ATM) is an example of an SST and it is known that users of ATMs can use such machines to deposit and/or withdraw currency notes. The control and operation of an ATM is complex and thus ATMs can be costly to manufacture and operate. Conventionally, a central processor and local data store (typically a disk drive) are provided in an ATM and the data store stores an Operating System (OS) and ATM application used by the ATM. This makes updating the operations which can be carried out at an ATM a time consuming and costly process because ATMs must be updated individually each time a change to the OS or ATM application is to be implemented.
It is known that certain mobile banking applications can be utilized via hand held devices (such as a feature phone, smartphone, tablet, PDA or the like) to perform certain transactions vis-à-vis a financial institution associated with a user of the hand held device. For example, a mobile bank application can be used to enable a hand held device user to view details of their account/s and order statements or authorize a transfer. ATM applications and mobile banking applications can thus be used to perform some similar types of transactions. For example, a customer can use an ATM or hand held device to make a balance enquiry or instruct a bank transfer to be made or to request a statement. However, an ATM application and a mobile banking application are conventionally completely independent. That is to say, they do not use the same mechanisms to communicate with a financial institution such as a bank. As such, when a bank updates an ATM application to offer a new type of transaction a corresponding update to a mobile banking application must also be made separately to enable the new transaction to be offered. This duplication results in increased effort, time and maintenance being required and is also prone to error.


An internal voltage-down power supply circuit includes a voltage-down circuit, a comparator circuit (current mirror amplifier), and a current source control circuit. The comparator circuit (current mirror amplifier) includes a current source (NMOS). When an external power supply voltage is increased, the current source control circuit reduces a control voltage applied to the gate of the current source to reduce the current from the current source. When the temperature becomes lower, the current source control circuit reduces the control voltage applied to the gate of the current source to reduce the current from the current source. Therefore, the closed loop gain of the internal voltage-down power supply circuit can be suppressed from increasing, and unnecessary oscillation of the internal power supply voltage can be prevented even when the external power supply voltage is increased and the temperature during operation is low.

1. Field of the Invention
The present invention relates to internal power supply voltage generation circuits, internal voltage generation circuits, and semiconductor devices, and more particularly, to an internal power supply voltage generation circuit immune to variation in external power supply voltage and temperature, an internal voltage generation circuit immune to variation in power supply voltage, and a semiconductor device immune to variation in internal power supply voltage.
2. Description of the Background Art
FIG. 13 is a circuit diagram showing in detail an internal voltage-down power supply circuit as a conventional internal power supply voltage generation circuit.
Referring to FIG. 13, an internal voltage-down power supply circuit 94 generates and supplies to a control circuit group 63 an internal power supply voltage intVcc. Control circuit group 63 includes a plurality of control circuits which operate according to internal power supply voltage intVcc. Internal voltage-down power supply circuit 94 includes a comparator circuit 67 and a voltage-down circuit 1. Voltage-down circuit 1 is formed of a PMOS transistor. Comparator circuit 67 is formed of a current mirror type amplify circuit. Comparator circuit 67 includes PMOS transistors 7 and 9, NMOS transistors 11 and 13, and a constant current source 69.
An output voltage from comparator circuit 67 is applied to the gate of PMOS transistor 1. PMOS transistor 1 down-converts an external power supply voltage extVcc according to the level of the output voltage to generate internal power supply voltage intVcc. A reference voltage Vref is applied to the gate of NMOS transistor 13 of comparator circuit 67. Internal power supply voltage intVcc generated from PMOS transistor 1 is applied to the gate of NMOS transistor 11 of comparator circuit 67. Therefore, comparator circuit 67 provides a voltage to the gate of MOS transistor 1 so that the level of internal power supply voltage intVcc is equal to the level of reference voltage Vref.
FIG. 14 is a schematic block diagram of a conventional semiconductor device. Components corresponding to those of FIG. 13 have the same reference characters allotted, and their description will not be repeated.
Referring to FIG. 14, a conventional semiconductor device includes four memory arrays 97, and external power supply pad 95, an internal voltage-down power supply circuit 94, a power line 71, and a control circuit group 63. Memory array 97 includes a plurality of memory cells to store data. Internal voltage-down power supply circuit 94 is located in the proximity of external power supply pad 95 provided at the end of the chip. External power supply pad 95 serves to supply external power supply voltage extVcc to internal voltage-down power supply circuit 94. Power line 71 serves to supply internal power supply voltage intVcc generated from internal voltage-down power supply circuit 94 to control circuit group 63.
As described above, a conventional internal voltage-down power supply circuit forms a closed loop in which the output which is internal power supply voltage intVcc is applied to comparator circuit 67. When external power supply voltage extVcc is shifted to a greater value, or when the temperature during the operation of internal voltage-down power supply circuit 94 is low, the channel conductance of the transistors forming internal voltage-down power supply circuit 94 becomes greater to increase the voltage gain of comparator circuit 67 and voltage-down power supply circuit 1. This induces the problem that internal power supply voltage intVcc is easily oscillated unnecessarily which is the output of internal voltage-down power supply circuit 94.
As described above, a conventional semiconductor device has internal voltage-down power supply circuit 94 provided at the end of the chip. If control circuit group 63 that operates according to internal power supply voltage intVcc is arranged remote from internal voltage-down power supply circuit 94, the resistance of power line 71 is increased. This causes the level of internal power supply voltage intVcc in the proximity of control circuit group 63 to become lower than the level of internal power supply voltage intVcc in the proximity of internal voltage-down power supply circuit 94 by the parasitic resistance of power line 71 when the power consumption of control circuit group 63 is increased. It is to be noted that internal voltage-down power supply circuit 94 generates internal power supply voltage intVcc by feeding back internal power supply voltage intVcc in the proximity of internal voltage-down power supply circuit 94. There was a problem that internal voltage-down power supply circuit 94 does not easily follow the variation of internal power supply voltage intVcc in the proximity of control circuit group 93.

Internal voltage generation circuit that down-converts external power supply voltage and semiconductor device generating internal power supply voltage on the basis of reference voltage


A fin transistor includes fin active region, an isolation layer covering both sidewalls of a lower portion of the fin active region, a gate insulation layer disposed over a surface of the fin active region, and a gate electrode disposed over the gate insulation layer and the isolation layer, and having a work function ranging from approximately 4.4 eV to approximately 4.8 eV.

The present invention generally relates to a fabricating technology of a semiconductor device, and more particularly, to a semiconductor device having a fin transistor and a method for fabricating the same.
Presently, since semiconductor devices have become highly integrated, typical 2-dimensional transistors encounter limitations. In that, 2-dimensional transistors are not available for high-speed devices because they cannot meet a demand for high current drivability.
To overcome such limitations, a variety of transistors having a 3-dimensional structure are being proposed, of which one is a fin field effect transistor (fin-FET, hereinafter referred to as a fin transistor). The fin transistor uses three sides as a channel to improve current drivability. On the contrary, the fin transistor is difficult to secure a threshold voltage greater than a certain level due to its three-side channels. Therefore, it is difficult to apply the fin transistor to a cell transistor of a memory device such as a dynamic random access memory (DRAM) because off-leakage characteristics are deteriorated unless securing a threshold voltage greater than a predetermined level in a memory device such as the DRAM.
Accordingly, a technique, which is capable of increasing a threshold voltage of a fin transistor, is required for employing the fin transistor as a cell transistor of the memory device. One of The techniques that has been suggested is a polysilicon layer, doped with p-type impurities such as boron (B), used as a gate electrode of the fin transistor instead of a typical polysilicon layer doped with n-type impurities such as phosphorous (P). Hereinafter, for convenience of the description, the polysilicon layer doped with p-type impurities will be referred to as a P+ polysilicon layer and the polysilicon layer doped with n-type impurities will be referred to as a N+ polysilicon layer. Theoretically, since the P+ polysilicon layer has a work function greater than N+ polysilicon layer by approximately 1.1 eV, it is possible to increase the threshold voltage of the fin transistor by a certain voltage level, e.g., approximately 0.8 V to approximately 1.0 V, by substituting the P+ polysilicon gate electrode for the N+ polysilicon gate electrode. A typical semiconductor device having such a fin transistor is illustrated in FIG. 1.
FIG. 1 illustrates a cross-sectional view of a semiconductor device having a typical fin transistor. Here, the semiconductor device, particularly a memory device, includes a cell region A and a peripheral region B. The cell region is configured with an NMOS transistor. The peripheral region B is divided into an NMOS peripheral region B1 and a PMOS peripheral region B2. A fin transistor having a typical structure is formed in the cell region A of the memory device, whereas a general planar transistor is formed in the peripheral region B.
As illustrated in FIG. 1, an isolation layer 12 is formed in a substrate 11 to define a first active region 11A in the cell region A, a second active region 11B in an NMOS peripheral region B1 of a peripheral circuit, and a third active region 11C in a PMOS peripheral region B2 of the peripheral circuit. The first, second and third active regions 11A, 11B and 11C are separated from one another by the isolation layer 12. A portion of the isolation layer 12 in the cell region A where a gate electrode will pass, is removed through masking and etching processes to form a gap G, thus exposing a top surface and portions of sidewalls of the first active region 11A. The first active region 11A vertically protrudes from the substrate 11 in virtue of the gap G. This protruding first active region serves as a fin active region in the fin transistor.
Second and third gate insulation patterns 13B and 13C and second and third gate conductive patterns 14B and 14C are sequentially formed over the second and third active regions 11B and 11C, respectively. The second gate conductive pattern 14B of the NMOS peripheral region B1 is formed of N+ polysilicon having a low work function, and the gate electrode 14C of the PMOS peripheral region B2 is formed of P+ polysilicon having a high work function.
A first gate insulation pattern 13A is formed on a surface of the exposed first active region 11A. A first gate conductive pattern 14A is formed on the first gate insulation pattern 13A and the isolation layer 12 in the cell region A such that it overlaps the gap G while crossing the first active region 11A. The first gate conductive pattern 14A in the cell region A is formed of P+ polysilicon, thus increasing the threshold voltage of the fin transistor.
However, the typical semiconductor device has several limitations below. In general, the P+ polysilicon has the work function greater than 4.8 eV and the N+ polysilicon has the work function smaller than 4.4 eV. For instance, it is assumed that there are two cases, i.e., one case where a P+ polysilicon gate having a work function of approximately 5.2 eV is formed on a gate oxide layer and an n-type junction, and the other case where an N+ polysilicon gate having a work function of approximately 4.2 eV is formed on a gate oxide layer and an n-type junction. An energy band diagram of each case is shown in FIG. 2. From these energy band diagrams, it can be observed that a band bending phenomenon becomes severe at an interface between the gate oxide layer and an n-type junction by a degree corresponding to a work function difference (φP-φN) between the P+ polysilicon and the N+ polysilicon in the case of using a P+ polysilicon gate electrode. Further, gate induced drain leakage (GIDL) characteristics become poorer in the case of using the P+ polysilicon gate electrode than the N+ polysilicon gate electrode, thus deteriorating data retention characteristics of a memory device. Therefore, to apply the fin transistor with improved current drivability as the cell transistor of the memory device, it is necessary to develop a technology capable of minimizing a band bending phenomenon while increasing a threshold voltage to a certain level or higher.

Semiconductor device having a fin transistor and method for fabricating the same


An elevating device with a latching function including a supporting rack, a supporting seat, a constant force spring and a latching member. The supporting seat moves longitudinally with respect to the supporting rack, and has a shaft rod automatically recovering towards a central line thereof. An arrow-shaped positioning block is installed in a front end of the latching member, a positioning concave slot is formed at bottom ends of a first and a second guiding planes of the positioning block. When the shaft rod moves with the supporting seat in the supporting rack, the shaft rod moves downwardly along the first guiding plane to enter the positioning concave slot forming a latching status. When the shaft rod moves downwardly in the positioning concave slot, the shaft rod is released from the positioning concave slot forming a releasing status, and the shaft rod moves upwardly along the second guiding plane.

1. Field of the Invention
The present invention relates to an elevating device, more particularly to an elevating device with latching function.
2. Description of Related Art
For a better viewing sensation, a display device, especially a flat panel display device, is provided with not only a function of adjusting elevation angle but also a function of adjusting height, so the display device can be more user friendly and meet different needs from users with various body shapes.
Generally, an elevating device used in a display device has a pair of retaining rails and a pair of mobile rails sleeved in the pair of retaining rails, so the pair of mobile rails is able to be longitudinally moved along the pair of retaining rails for adjusting the height of the display device. For providing a positioning function to the display device, a constant force spring is installed between the two mobile rails so the constant force spring can provide an elastic force to balance the net weight of the display device, a supporting seat of the supporting device and the pair of retaining rails.
Though the constant force spring can provide a stepless positioning function to the pair of retaining rails and the pair of mobile rails, a latching mechanism is still needed to install between the two pairs of rails, a conventional structure of "Latching mechanism of elevating device", is herein adopted as examples, when the pair of mobile rails are moved relative to the pair of retaining rails, the pair of mobile rails can be latched by the latching mechanism so as to form a latching status; at this moment, if an upward external force is applied on the display device, said device is not able to be elevated. Only after the latching status is released, the external force applied on the display device is able to adjust the height of the display device through the pair of mobile rails upwardly moving along the pair of retaining rails. So the latching mechanism plays an important role for the application of the elevating device; but a conventional display device is often installed with a push-type or press-type elevation button, so the display device can be adjusted to ascend/descend through pushing or pressing the elevation button. Said operation means may not be convenient to users and the exposed button may be a negative factor to the whole appearance of the display device.
Moreover, the supporting seat provided between the mobile rails of the elevating device is connected to the display device, and the supporting seat can be latched by the latching mechanism so as to position the display device. The latching status is often utilized when packaging the elevating device for reducing the packing volume and lower the transportation cost. The latching mechanism is often served as a downward movement limitation of the supporting seat, so when a user is adjusting the height of the display device, the supporting seat is descended and is in contact with the latching mechanism for forming a latching status. So how to provide an automatic latching and releasing function to the elevating device that is in a certain status, e.g. rotating from a vertical status to a horizontal status, is needed to be developed.


Curable urea formaldehyde binder compositions are provided which are useful in coated abrasive and wood engineering applications, in a time released fashion. The time released curable binder compositions include a urea formaldehyde resin and an aryl phosphite in varying concentrations. The curable binder compositions of the present invention provide desirable working times and faster curing times tinder ambient or near ambient conditions.

This invention relates to abrasive articles in which a thin layer or, more usually, a single layer of abrasive grit is adhesively bonded to a backing. Such products are coated abrasives, more commonly referred to as "sandpaper," and fibrous abrasive pads, for example. Conventionally, glue or thermosetting resins such as phenol formaldehyde resins ("PF resins") and urea formaldehyde resins ("UF resins") have been used in coating formulations. UF resins, which are less expensive than phenolic resins, have been used to reduce the cost in abrasive products. However, current UF resin systems used in the manufacture of coated abrasive products do not provide desirable working times and curing times under ambient or near ambient conditions. The coated abrasive industry is seeking time released curable urea formaldehyde binder compositions in order to have enough working time, yet faster curing to provide a sharp image and non-curled sand paper.
Phenolic resin compositions are known that can cure at ambient temperatures with rapid cure at modestly higher temperatures. Such resins, as in U.S. Pat. No. 5,296,520 to Gerber, provide controlled work time for hardening phenolic resins at ambient temperature using aryl phosphite latent acid catalysts. However, Gerber found that urea and other amide compounds were very effective retarders of ambient temperature hardening of the resin with the aryl phosphite hardening agents.
Nevertheless, UF resins are different from phenolic resins and each have vastly different chemistry and methods of manufacture. UF resins are prepared by a condensation whereby the nitrogen of urea reacts with the carbonyl group of formaldehyde. In contrast, an exemplary phenolic polymer is a phenol formaldehyde resin prepared by aromatic substitution of the multiple activated sites of a phenol, initially by formaldehyde, followed by reaction with other reactive intermediates. In the preparation of phenolic resins, catalysts such as strong base, zinc acetate, and borates can be used to provide phenolic resoles, while strong acid can be used to provide phenolic novolacs. UF resins can be prepared using a strong acid catalyst, such as, for example, sulfuric acid. Structurally, phenolic resins are highly aromatic, and contain aromatic end groups. In contrast, UF resins are amino resins and essentially non-aromatic. Regarding curing properties, phenolic polymers range from thermosetting resoles to thermoplastic novolacs. UF resins are thermosetting resins. Accordingly, PF resin chemistry is not predictive of UF resin chemistry, as shown by Gerber, op.cit.
UF precondensates can be blended with liquid phenolic resin systems. However, such systems are catalyzed by providing a basic environment (pH above 7), in contrast to the acid catalyst used for unblended urea formaldehyde prepolymers.
Accordingly, curable urea formaldehyde binder compositions employing a latent acid hardening component are needled that will provide desirable working times and curing times under ambient or near ambient conditions. The results presented below provide surprising and unexpected improvements in urea formaldehyde based binder compositions.


Reference network embodiments are provided for use in pipelined signal converter systems. The network embodiments are fast and power efficient and they generate low-impedance reference signals through the use of a complimentary common-drain output stage, at least one diode-coupled transistor inserted between transistors of the output stage, and a controller. The controller is configured to provide a backgate voltage to the diode-coupled transistor to thereby establish a substantially-constant output current. The controller is further configured to provide gate voltages to the output stage to establish top and bottom reference voltages about the diode-coupled transistor that are spaced from a common-mode voltage. This reference structure maintains a constant output current as the span between the top and bottom reference voltages is selectively altered. In different embodiments, the diode-coupled transistor is replaced with a bipolar junction transistor.

1. Field of the invention
The present invention relates generally to signal converters.
2. Description of the Related Art
Pipelined analog-to-digital converter systems are capable of achieving impressive resolution and signal-to-noise performance at extremely high sample rates (e.g., 150 megasamples per second). Accordingly, they are useful in a wide range of demanding converter applications (e.g., charge-coupled device imaging, ultrasonic medical imaging, base station processing, digital receivers, digital video, cable modems, digital subscriber line systems, and Ethernet systems).
The speed of a pipelined system is realized by processing an analog input signal through a series of converter stages. Each stage provides a respective digital code and, except for the last stage, each also forms an analog residue signal which is passed to a succeeding stage for further conversion. The respective digital code is typically used to apply a selected one of a set of reference signals to switched-capacitor circuits to thereby generate the residue signal. Because the accuracy of the residue signal is directly related to parameters (e.g., speed, accuracy and impedance) of the reference signals, the generation of these signals is critical to the performance of the converter system.

Fast, efficient reference networks for providing low-impedance reference signals to signal processing systems


A device is provided with a multicore microprocessor unit (21) capable of inter-processor communication, storage (22) for storing a file describing device configuration information, and a device interface (23). Threads of the microprocessor unit are separated: a first processor core drives the OS, and meanwhile, a second processor core drives the device driver for controlling the device interface. While sharing the device configuration information by inter-processor communication, a notification driver interface for notifying the operating system kernel of configuration information on the basis of the device configuration information is loaded and the second processor core controls the device connected to the device interface by reading a scenario sequence file into the notification driver.

In order to connect a computer, such as a personal computer or a smartphone, to peripheral equipment (hereinafter referred to as a "device") and use the device, not only a physical connection between the computer and the device, but also a "logical connection" between the computer and the device is required. With the "logical connection," a device-driver enables the computer to recognize the device and enables the computer and the device to communicate with each other.
The device-driver is typically produced by the device maker as a program exclusively for each combination of a device and an Operating System (OS) and is provided together with the device to users. Such a form of providing the device-driver is used mainly because each device is produced based on a specific standard and specification and additionally the device-driver depends on not only the device but also the OS.


An image processing method and device thereof are provided. The device includes a capture device and a processor. The capture device is adopted for receiving a plurality of frames and comparing at least two adjacent frames to obtain an area selection signal according to a differential value there-between. The processor is connected to the capture device for receiving the area selection signal and to separate each of the adjacent frames into at least two areas. Each of the areas of the adjacent frames is performed by an image processing step respectively, and then the images of the areas are combined to obtain a resulted frame.

1. Field of the Invention
This invention generally relates to an image processing method and device thereof, and especially to an image processing method and device thereof for processing images with running captions.
2. Description of Related Art
A conventional film mode, for example, a common record mode of a movie film, has 24 complete frames per second; therefore, the frame rate is 24 frame/s (or the frequency of the play is 24 Hz). Some other film mode records 30 complete frames per second, or the frequency of the play is 30 Hz. And the conventional broadcasting methods of visual signals, such as cable television and wireless television etc., generally comprise the broadcasting modes of NTSC (National Television System Committee) and PAL (Phase Alternative Line) etc. The broadcasting frequency of the NTSC is 60 Hz which means 60 interlaced frames per second are received at the end-user terminal from the television station. The broadcasting frequency of the PAL is 50 Hz. Wherein, the interlaced frames are, for example, in the odd-number frames, only the scan lines 1,3,5 . . . etc. (so called as the odd-number scan lines) display images. The even-number scan lines do not display any images. In the even-number frames, only the scan lines 2,4,6 . . . etc. (so called the even-number scan lines) display images; the odd-number scan lines do not have images; vice versa.
Therefore, for a film of 30 Hz or 24 Hz film mode, in order to transmit via the NTSC standard at 60 Hz, the processes of 2:2 pull down or 3:2 pull down should be performed before the transmission. FIG. 1 is a drawing schematically showing a view of a conventional frame converting format of a 30 Hz film mode with 2:2 pull down. As shown in FIG. 1, each frame 101,102 to 130 represents a complete image frame with 30 frames per second. Frame 101 is divided into an image frame 101e, which only even-number scan lines appear on the image, and a frame 101o, which only odd-number scan lines appears on the image. Other frames are processed with the same way. Therefore, 60 interlaced frames per second of 101e, 101o, 102e, 102o to 130e and 130o etc. are achieved. Wherein, the frames with suffix "e" represent that only even-number scan lines appear on the images, and the frames with suffix "o" represent that only odd-number scan lines appear on the images (the following uses the same presentations). Thus, the NTSC standard at broadcasting frequency 60 Hz can be accorded.
FIG. 2 is a drawing schematically showing a view of conventional frame converting format of 24 Hz film mode with 3:2 pull down. As shown in FIG. 2, the frames 201, 202, 203 to 224 represent the complete image frames with 24 frames per second. Wherein, the first frame 201 is divided into the interlaced frames 201e and 201o. Further, the second frame 202 is divided into frames 202e, 202o and 202e etc. Furthermore, the third frame 202 is divided into frames 203e and 203o etc. The other frames are processed with the same way. Thus, 60 frames per second of 201e, 201o, 202e, 202o to 224e and 224o etc. are achieved, and the NTSC standard at broadcasting frequency 60 Hz can be accorded.
Besides, an original film at the film mode of 24 Hz, in order to transmit with the PAL standard at 50 Hz, the process of 2:2 pull down should be performed before the transmission. FIG. 3 is a drawing schematically showing a view of the conventional frame converting format of a 24 Hz film mode with 2:2 pull down. As shown in FIG. 3, the frames 301, 302 to 324 represent the complete image frames with 24 frames per second. The first frame 301 is divided into the interlaced frames 301e and 301o. The other frames are processed with the same way. Therefore, frames 301e, 301o, 302e, 302o to 324e and 324o etc. of 48 frames per second are achieved; and with other processes, the PAL standard at broadcasting frequency 50 Hz can be accorded.
Currently, a higher quality playback mode of an image playback device of an end-user terminal, for example, a High Definition TV (HDTV), in order to get better display definition, will first detect whether the received frames are the interlaced frames processed with 2:2 pull down or 3:2 pull down; further, by the Inverse Telecine (IVTC) process, the interlaced frames will be converted into complete frames before they are played back. For example, after receiving the interlaced frames 201e to 224o shown in FIG. 2, the frames 201e and 201o are combined to get the complete frame 201; the frames 202e and 202o are combined to get the complete frame 202; and other frames are processed with the same way. Accordingly, complete frames 201, 201 to 204 of 24 frames per second are achieved. FIG. 4 is a drawing schematically showing a view of a conventional playback mode of a film after the IVTC process performed with 3:2 pull down. Further, according to the mode of FIG. 4, the complete frame 201 as described is played two times to obtain the frames 201p and 201p; the frame 202 is played three times to obtain the frames 202p, 202p and 202p; and other frames are processed with the same way. Finally, 60 frames per second can be played with the playback mode as shown in FIG. 4. Comparing with the playback mode of a conventional TV which 60 interlaced frames per second are played, the frames played with the playback mode as shown in FIG. 4 are smooth without the effects of drop frame, image displacement or image delay.
However, in the conventional broadcasting mode of the visual signal, running captions are frequently added. In general, the running captions are added directly to the interlaced broadcasting frames, for example, added directly to the interlaced frames 101e, 101o, 102e, 102o to 130e and 130o as shown in FIG. 1, or added directly to the interlaced frames as shown in FIG. 2 or FIG. 3. Next, the interlaced frames with the added running captions are transmitted to the end-user terminal.
FIG. 5 is a drawing schematically showing a view of a conventional frame process mode with an interlace mode after adding running captions. As shown in FIG. 5, when the interlaced frames received by an image playback device of an end-user terminal are, for example, the interlaced frames 201e to 224o as shown in FIG. 2 with addition of the running captions 501e, 501o to 530e and 530o, the conventional image playback device will combine the interlaced frames 201e and 201o to a complete frame 551, and combine the interlaced frames 201o and 202e to a complete frame 552, and the other frames are processed with the same way. Accordingly, 60 frames per second frames 551 to 580 can be achieved. It can be noted that the display quality of the running captions achieved by the mode is excellent. However, the definition of the whole frame is deteriorated. For example, the complete frame 552 is composed of the interlaced frames 201o and 202e which are belonged to two different complete frames 201 and 202 as shown in FIG. 2. Consequently, many images with ragged saw tooth are occurred at the intersections of the images in the frame 552. Therefore, a more suitable process method and device for processing the frames with added running captions is imminent and necessary.

Image processing method and device thereof


A gate access system is described where the system includes an imaging system configured to capture an image of an object disposed in a predetermined field of view in response to an image capture signal. The imaging system is also configured to associate time/date data with the image. The time/date data represents a time and a date when the image was captured. At least one gate access panel device is disposed in the field of view and coupled to the imaging system. The at least one gate access panel device is configured to transmit the image capture signal in response to being actuated. A gate transceiver is coupled to the imaging system. The transceiver is configured to transmit the image and the time/date data via a wireless communication channel.

1. Field of the Invention
The present invention relates generally to security systems, and particularly to security gates having an intercom.
2. Technical Background
Security gates are used to control the ingress and egress to residential areas, individual residences, corporate and institutional areas, military bases, and other such controlled areas. Security gates may be operated in a variety of ways. However, the present invention is directed to gate systems that employ a gate intercom for user access. In other words, a visitor to a controlled area speaks to a person inside the controlled space before being allowed to enter. Once permission is granted, a gate opening signal is generated. Gate closure may be effected after a predetermined time delay, or in response to a gate closure signal. The gate closure signal may be generated using any suitable manner.
As noted above, gate systems typically require that a person inside the controlled area be notified when a visitor seeks access to the controlled area. The person is typically notified by a communication channel that includes an electrically wired propagation path, for example, from a gate intercom to an intercom device disposed in the controlled area. The intercom inside the controlled space is typically a component of a communication and control system that provides the user with the ability to receive calls from the gate intercom, speak with the visitor, and control the gate from inside the controlled space.
In one approach that has been considered, wiring is disposed between the gate intercom and an interface to the home telephony wiring. The intercom wiring may be connected to an interface allowing the user to communicate with the gate intercom via the telephone. One drawback to this approach relates to the expense and, in some cases, the difficulty of placing the wiring between the gate and the controlled area.
Thus, in another approach that has been considered, a radio system is employed to link the gate intercom with the controlled area. However, this approach also has drawbacks in that each side of the radio link must employ a radio transceiver. As such, the controlled area must be equipped with both a telephone set for normal telecommunications activity, and a radio transceiver to communicate with the gate intercom.
Security systems often include one or more networked cameras. A program running on a host computer may sequentially poll each camera and display that camera's images in a corresponding window on the display. All of the digital photographs are taken in response to the host computer polling activities and stored sequentially. However, this system has drawbacks in that many of the photographs in the sequence are useless and may not represent visitor activity.
Accordingly, what is needed is a security system that includes a gate access system that captures the image of visitors in response to an actuation of one or more gate access panel inputs. The security system also needs a base station that is configured to receive and store the images along with a time/date stamp for easy retrieval.

Gate access system with visitor imaging and memory


A method is specified for processing the output signals A to F of an optoelectronic scanner (3) in a replay or recording appliance for replaying from or recording onto an optical recording medium having the following method steps: as well as an appliance with a corresponding input circuit of a digital servo controller: first of all, the output signals A to F are supplied directly to an A/D converter (2) without the interposition of a low-pass filter, and are digitized with n-times oversampling. The digitized output signals are then supplied to a k-th order comb filter (4) by means of which undersampling of the signals to the normal sampling frequency (44.1 kHz) is carried out. After this, the undersampled output signals A' to F' of the comb filter (4) are supplied to a trimming and correction circuit (6) in which trimming and correction, of OFFSET and BALANCE are respectively carried out. Finally, the trimmed/corrected output signals A" to F" are supplied to the trimming and correction circuit of a digital servo circuit (1), by means of which a focusing error signal (FE) and a track deviation error signal (TE) are produced.

The present invention relates to a method for processing the output signals of an optoelectronic scanner in a replay or recording apparatus for replaying from or recording onto an optical recording medium, as well as a corresponding appliance having an input circuit of a digital servo controller, suitable for carrying out the method.
Both such a method and the said appliance having an input circuit of a digital servo controller have been known for some time as components of optical disk drives for CDs, magneto-optical disks, CD-Roms, digital video disks etc. In this case, the servo controller is used to ensure that the laser beam which scans the optical recording medium always follows the track of the pits on the recording medium accurately and, despite the optical recording medium having a certain amount of unevenness which cannot be avoided, eccentricity or other disturbance influences are focused at any time with adequate precision onto the information-bearing layer of the recording medium. In the case of the known methods and the corresponding appliances, the output signals of the scanner are first of all supplied to an analogue circuit with a low-pass filter and a trimming and correction circuit, and the focus error signals resulting from this, as well as the track error signals which characterize a track deviation are then digitized at the normal, fundamental sampling frequency of 44.1 kHz or else at twice the sampling frequency, which is likewise normal, of 88.2 kHz in an analogue/digital converter, called an A/D converter in the following text. After this, the digitized signals are made available to the digital servo controller as input values.
The disadvantages of the known method and of the corresponding known appliance are, in particular, that the analogue low-pass filter is essential for suppressing high frequency components, e.g. radio-frequency components, of the two error signals, and that the necessary trimming or the corrections required of OFFSET and BALANCE must be carried out in a relatively complex manner in the analogue domain. The known method and the corresponding circuit of a known appliance possibly require a number of stages of analogue low-pass filters before the A/D conversion, and trimming or correction can be carried out digitally only if each output signal of the optical scanner is digitized separately. Thus, neither the known method nor the corresponding appliance is optimum for integration of a decoder and of a digital servo section, containing an A/D converter and a digital servo controller, e.g. using CMOS technology.

Method for processing the output signals of an optoelectronic scanner in a replay or recording appliance, and a corresponding appliance


Plants with reduced gluten grains and compositions thereof are disclosed herein.

Wheat is the first important and strategic cereal crop for the majority of the world's population and is the most important staple food of about two billion people (36% of the world population). Worldwide, wheat provides nearly 55% of the carbohydrates and 20% of the food calories consumed globally (Breiman and Graur, 1995). Wheat exceeds in acreage and production every other grain crop (including rice, maize, etc.) and is cultivated over a wide range of climatic conditions. The understanding of wheat genetics and genome organization using molecular markers is of great value for genetic and plant breeding purposes.
Proteins are the most important component of wheat grain governing its end-use value. Grain storage protein (GSP) composition is known to determine dough cohesiveness and visco-elasticity. The most abundant GSPs in wheat are the gluten-forming gliadins and glutenins, which account for 60% to 80% of total grain protein.
Coeliac disease is a condition in which the lining of the small intestine is damaged by gluten, a mixture of different storage proteins found in the starchy endosperm of wheat, rye and barley grains as well as in closely related species. The gluten matrix consists of approximately equal mixtures of gliadin and glutenin proteins. Coeliac disease is primarily caused by the gliadin proteins. Specifically, in this disease the villi of the small intestine are destroyed and the lining becomes flattened, seriously impairing nutrient absorption. Typical symptoms are weight loss, foul-smelling diarrhea, vomiting, abdominal pain and swelling of the legs. The only cure currently available is a life-long gluten-free diet strictly avoiding all food and pharmaceutical compositions containing wheat, rye and barley. In addition to Coeliac disease, a number of humans suffer from general intolerance to glutens. The range of this intolerance varies greatly although there are no clear clinical symptoms as in coeliac disease.
Thus, there is a clinical need to reduce consumption of gluten and a corresponding need to develop wheat and other grains with reduced gluten. Although the need has been long felt, the identification of mutations in wheat genes that reduce gluten has proceeded slowly because, among other possible reasons, there is limited genetic diversity in today's commercial wheat cultivars and the wheat genome is complex. Bread wheat is a hexaploid, with three complete genomes termed A, B and D in the nucleus of each cell. Each of these genomes is almost twice the size of the human genome and consists of around 5,500 million nucleotides. On the other hand, durum wheat, also known as macaroni wheat or pasta wheat (Triticum durum or Triticum turgidum subsp. durum), is the major tetraploid species of wheat of commercial importance, which is widely cultivated today. Durum wheat has two complete genomes, A and B, and is widely used for making pasta.
The inventors have identified genes, wherein mutations and modification of said genes produce reduced gluten grains.

This patent is subject to a terminal disclaimer.

Reduced gluten grains and compositions thereof


The office gym exercise kit is a portable exercise kit that provides for a number of exercises to be performed by a user, including arm, leg and back exercises. The kit components are capable of attaching about a chair post and a chair back support to provide the exercises for the user. A flexible body is wrapped around the post and under the base of the chair then secured such that the flexible body remains in place around the chair post. A flexible band is wrapped around the chair back support. Both the flexible body and flexible band have retainers attached thereon. Several elastic straps are included in the kit. The elastic straps may be fastened to the flexible body and flexible band by latching onto the retainers. The user then exercises by extending the elastic straps with arms, legs or the like.

1. Field of the Invention
The present invention relates to exercise equipment, and particularly to an exercise kit adapted to be used with an office chair.
2. Description of the Related Art
Although there are a number of exercise devices on the market, there are few which are portable and fewer still that provide a range of exercise options for an individual exerciser. Many exercise devices are cumbersome and much larger than is convenient to relocate. Additionally, many individuals have the desire to exercise in easily accessible locations without the difficulty involved in obtaining various types of equipment. Thus it is advantageous to have an exercise device that is portable, lightweight and capable of being used in a number of surroundings, such as homes, offices and the like.
One way to provide for various exercises in convenient locations is to use a portable exercise device in combination with home or office furniture or room components such as doors. The related art endeavors to supply a portable exercise device that provides a range of exercise movements. However, there is a need for a portable exercise device that is easily attached to an office or home chair and that allows a user to engage in a great variety of exercise movements. Additionally, there is a need for a portable exercise device that is simply constructed using inexpensive materials.
U.S. Pat. No. 5,690,594, issued Nov. 25, 1997 to R. Mankovitz, describes an exercise apparatus for attachment to a post of a chair. The exercise apparatus has a foot support bar that allows a user's foot to extend along the bar. Wheels are mounted to the foot support and resilient members serve to attach the foot support bar to the post of the chair. The user then sits in the chair and pushes the foot support bar away from the chair, thereby exercising the user.
U.S. Pat. No. 5,599,260, issued Feb. 4, 1997 to Rovinsky et al., shows an exercise device with a roller attached to the post of a chair by an elastic stretchable element. The roller can be employed by the user to exercise either the user's foot or arm. The roller has a piece connected to it to allow for foot placement. Additionally, the user can unfold the roller such that it can be taken into the user's arm for arm exercises.
U.S. Pat. No. 6,099,445, issued Aug. 8, 2000 to Rovinsky et al., describes an exercise device having a rigid frame and a number of exercise elements connected to the rigid frame. The frame is capable of being mounted on the central post of a chair. The exercise elements connected to the frame allow the user to exercise the user's legs, arms, and neck.
U.S. Pat. No. 5,743,838, issued Apr. 28, 1998 to Willis, shows a method of making an exercising device and the device itself. The exercise device has a flexible body that is wrapped about the back of a chair and an elastic member attached to the flexible body. The elastic member can accommodate a limb and the user may extend the elastic member away from the chair in order to exercise the limb.
U.S. Pat. No. 5,141,482, issued Aug. 25, 1992 to Hern, describes an exercise device that is strapped about the back of a chair. The exercise device includes a seat-engaging strap, a chest strap and shoulder straps. The chest and shoulder straps are wrapped about the chest of a user and tension members connect the chest and shoulder straps to the seat-engaging strap that is secured about the chair. When the user leans forward, the resistance from the device tightens his stomach muscles.
U.S. Pat. No. 5,624,360, issued Apr. 29, 1997 to Wilkins, describes a portable exercise device having handgrips, elastic bands and anchor brackets. The anchor brackets are clamped onto a door and joined to the handgrips by the elastic bands. The user then grasps the handgrips and stretches the elastic bands, thereby exercising the user's arms. The device may also be used to exercise other parts of the body, including feet, upper torso, etc.
Other patents showing exercise devices include U.S. Pat. No. Des. 319,273, issued Aug. 20, 1991 to S. Fox (vehicular exerciser); U.S. patent Pub. No. US 2002/0142898 A1, published Oct. 3, 2002 and invented by W. Willis et al. (office exercise furniture); U.S. patent Pub. No. US 2004/0053756 A1, published Mar. 18, 2004 and invented by T. Tremayne (exercise device); U.S. Pat. No. 650,656, issued May 29, 1900 to J. Raabe (exercising apparatus); U.S. Pat. No. 2,160,722, issued May 30, 1939 to J. Cunningham (foot exerciser); U.S. Pat. No. 5,090,694, issued Feb. 25, 1992 to E. Pauls et al. (combination chair and exercise unit).
Additional patents showing exercise devices include U.S. Pat. No. 5,171,295, issued Dec. 15, 1992 to F. Schwalm, Jr. (portable pulley exerciser body fitness apparatus); U.S. Pat. No. 5,178,596, issued Jan. 12, 1993 to N. McIntire (exercise apparatus) ; U.S. Pat. No. 5,324,243, issued Jun. 28, 1994 to W. Wilkinson (universal, portable exercise apparatus adaptable to fit a chair); U.S. Pat. No. 5,362,296, issued Nov. 8, 1994 to L. Wang et al. (chair mounting exercising unit) ; U.S. Pat. No. 6,048,292, issued Apr. 11, 2000 to M. Gasquez (combination arm exercise apparatus and propulsion aid for a wheelchair) ; U.S. Pat. No. 6,117,056, issued Sep. 12, 2000 to T. Cataldi, Jr. et al. (isotonic exercise device attachable to chair); U.S. Pat. No. 6,159,133, issued Dec. 12, 2000 to R. Shugg (seat mounted workout station system); U.S. Pat. No. 6,500,104 B1, issued Dec. 31, 2002 to R. Rich (seat exercise device); International Pub. No. WO 02/056971 A1, published Jul. 25, 2002 (exercise device); Can. Pat. App. No. 2 436 231, published Jul. 25, 2002 (exercise device).
Although the related art addresses portable exercise devices that may be attached to chairs, what is needed is an easily constructed exercise device that may be attached to a wide variety of chairs. In addition, the exercise kit should allow for an extensive range of exercises the user may do.
None of the above inventions and patents, taken either singly or in combination, is seen to describe the instant invention as claimed. Thus an office gym solving the aforementioned problems is desired.