System for producing a stereoscopic image of an object, and displaying the stereoscopic image, the system including a capsule and a control unit, the capsule including a sensor assembly, a processor connected to the sensor assembly, a capsule transceiver connected to the processor, a light source, and a power supply for supplying electrical power to the capsule transceiver, the processor, the light source and to the sensor assembly, the control unit including a control unit transceiver, and an image processing system connected to the control unit transceiver, wherein, the sensor assembly detects the stereoscopic image, the processor captures the stereoscopic image, the capsule transceiver transmits the stereoscopic image to the control unit transceiver and the image processing system processes the stereoscopic image.

Stereoscopic image detection devices are known in the art. Such devices are required to obtain and provide a combination of small cross section and high image quality. It will be appreciated by those skilled in the art that high image quality, in general, is characterized by stereoscopic vision accuracy, color capabilities, high resolution and illumination requirements.
It is noted that conventional methods, which provide stereoscopic images, require a wider optical path than a monocular one. Such a widened optical path enlarges the cross-section required for the detection device considerably. Hence, the requirement for a small cross section is not maintained.
U.S. Pat. No. 5,527,263 to Zobel et al., is directed to a dual optical path stereo endoscope with simple optical adjustment. U.S. Pat. No. 5,776,049 to Takahashi, is directed to a "Stereo Endoscope Imaging Apparatus" and provides a device which utilizes a combination of two optical paths with two CCD units, capable of variable zoom.
Auto-stereoscopic devices, which utilize one optical system to provide a stereo effect, are also known in the art. Such a device is provided in U.S. Pat. No. 5,603,687 to Hori et al., which is directed to a device with two parallel optical axis and two CCD elements. Hori selected an asymmetrical approach, wherein one optical channel has a large aperture for light and details and the other optical channel provides a parallax image for stereoscopic imagery to the proximal CCD.
U.S. Pat. No. 5,613,936 to Czarnek et al., is directed to a stereoscopic endoscope device which utilizes light polarization and time multiplexing in order to transmit each different polarized image corresponding to left and right images multiplexed in time, through one optical channel that transfers images from the lateral side of the endoscope shaft. This endoscope has to be inserted deeper into the human cavity to receive a stereo image. It must also be used with a head mounted display device called "switched shutter glasses" that causes eye irritation. It is noted that according to Czarnek each image is received in 25% of original quality. As much as 50% of the light received fro the object, is lost due to polarization considerations and as much as 50% of the remaining information is lost due to channel switching.
U.S. Pat. No. 5,588,948, to Takahashi et al., is directed to a Stereoscopic Endoscope. The stereo effect is produced by having a dividing pupil shutter, which splits the optical path onto the left and right sides, and the up and down sides. These sides are alternatively projected on a proximal image pickup device, using time multiplexing. According to another aspect of this reference includes a distal CCD, which is divided to left and right sides with a shading member separating them, for achieving space multiplexing.
U.S. Pat. No. 5,743,847 to Nakamura et al., is directed to a "Stereoscopic Endoscope Having Image Transmitting Optical-System and Pupil Dividing Unit that are Axially Movable With Respect to Each Other", which uses a plural pupil dividing means and one optical channel. U.S. Pat. No. 5,751,341 to Chaleki et al., is directed to a "Stereoscopic Endoscope System", which is basically a two channel endoscope, with one or two proximal image sensors. A rigid sheath with an angled distal tip could be attached to its edge and be rotated, for full view.
U.S. Pat. No. 5,800,341 to Mckenna et al, who is directed to an "Electronically Steerable Endoscope", which provides different fields of view, without having to move the endoscope, using a plurality of CCD cells and processing means. U.S. Pat. No. 5,825,534 to Strahle, is directed to a "Stereo Endoscope having a Folded Sight Line" including stereo-endoscope optical channel, having a sight line folded relative to tube axis.
U.S. Pat. No. 5,828,487 to Greening et al., is directed to a "Stereoscopic Viewing System Using a Two Dimensional Lens System" which in general, provides an alternative R-L switching system. This system uses a laterally moving opaque leaf, between the endoscope and the camera, thus using one imaging system. U.S. Pat. No. 5,594,497 to Ahern, describes a distal color CCD, for monocular view in an elongated tube.
The above descriptions provide examples of auto-stereoscopic inventions, using different switching techniques (Time division multiplexing) and polarization of channels or pupil divisions (spatial multiplexing), all in an elongated shaft. When color image pick up devices are used within these systems, the system suffers from reduced resolution, loss of time related information or a widened cross section.
The issue of color imagery or the issue of a shaft-less endoscope is not embedded into any solution. To offer higher flexibility and to reduce mechanical and optical constraints it is desired to advance the image pick-up device to the frontal part of the endoscope. This allows much higher articulation and lends itself easily to a flexible endoscope. Having a frontal pick up device compromises the resolution of the color device due to size constraints (at this time).
U.S. Pat. No. 5,076,687 to Adelson, is directed to an "Optical Ranging Apparatus" which is, in general a depth measuring device utilizing a lenticular lens and a cluster of pixels.
U.S. Pat. No. 5,760,827 to Faris, is directed to "Pixel Data Processing System and Method for Producing Spectrally-Multiplexed Images of Three-Dimensional Imagery for Use in Stereoscopic Viewing Thereof" and demonstrates the use of multiplexing in color and as such, offers a solution for having a color stereo imagery with one sensor. Nevertheless, such a system requires several sequential passes to be acquired from the object, for creating a stereo color image.
U.S. Pat. No. 5,812,187 to Watanabe, is directed to an Electronic Endoscope Apparatus. This device provides a multi-color image using a monochromatic detector and a mechanical multi-wavelength-illuminating device. The monochromatic detector detects an image, each time the multi-wavelength-illuminating device produces light at a different wavelength.
U.S. Pat. No. 5,604,531 issued to Iddan, et al., and entitled "In Vivo Video Camera System", is directed to a system for viewing the inside of the digestive system of a patient. The system includes a swallowable capsule, which views the inside of the digestive system and transmits video data, a reception system located outside the patient, and a data processing the video data. The capsule includes a light source, a window, a camera system such as a CCD camera, an optical system, a transmitter, and a power source.
The light source illuminates the inner portions of the digestive system through the window. The camera system detects the images, the optical system focuses the images onto the CCD camera, the transmitter transmits the video signal of the CCD camera, and the power source provides power to the electrical elements of the capsule. The CCD camera can provide either black and white or color signals. The capsule can additionally include sensor elements for measuring pH, temperature and pressure.
International publication No. WO 00/22975 entitled "A Method For Delivering a Device to a Target Location", is directed to a method for viewing the inside of the digestive system, and discharging medicaments or collecting fluid or cell samples from the environment. The method employs a capsule, which includes a light source, a viewing window, a camera system, an optical system, a transmitter, a power source, and a storage compartment for releasing a medicament or collecting cell samples or fluid. The light source, viewing window, camera system, optical system, transmitter, and power source are similar to those described herein above in connection with U.S. Pat. No. 5,604,531.
One end of the capsule includes a bi-stable spring connected between an inflexible barrier proximal to the capsule and a firm diaphragm distal to the capsule, thus forming the storage compartment. The capsule includes a pouch wall between the firm diaphragm and the capsule end. The firm diaphragm includes a piercing pin for rupturing the pouch wall. The capsule end furthermore includes a permeable area for transfer of fluid to or from the storage compartment.
The spring is extended by heating it, thus moving the firm diaphragm distally. The piercing pin ruptures the pouch wall, thereby allowing controllable amount of the medicament to exit from the storage compartment through the hole pierced in the pouch wall and through the permeable area. Conversely, the bi-stable spring is retracted in order to collect a controllable amount of fluid or cell samples, wherein the fluid transfers to the storage compartment, through the permeable area.


An energy absorbing bracket assembly (20) for supporting a knee bolster (22) on a vehicle instrument panel (12) includes a pair of brackets (30) that are each formed from sheet metal with a construction that is capable of absorbing energy even in confined spaces. Each bracket (30) includes a mounting flange (34) for mounting on the instrument panel (12), a support flange structure (38) for mounting the knee bolster (22), and a vertically extending energy absorbing section (40) having a peripheral portion (42) and a web (44) that extends from the peripheral portion adjacent the mounting flange (34) to the peripheral portion adjacent the support flange structure (38). A pair of peripheral legs (46) and (48) of the peripheral portion are located on opposite sides of the web (44) and cooperate therewith to define a pair of spaced openings (50, 52). The web (44) reinforces the bracket (30) to position the knee bolster (22) but buckles under loading to absorb energy.

This invention relates to an energy absorbing bracket assembly for supporting a knee bolster on a vehicle instrument panel.
Energy absorbing bracket assemblies have previously been utilized to support knee bolsters on a vehicle instrument panel in order to absorb energy when the vehicle seat occupant is moved forwardly during a vehicle impact. However, in some vehicle constructions, there is limited room for such energy absorbing bracket assemblies to be located and still provide an energy absorbing function.
Patents noted during an investigation conducted in connection with this invention include U.S. Pat. No. 4,978,136 Tomita et al.; U.S. Pat. No. 5,201,544 Matano et al.; U.S. Pat. No. 5,273,314 Sakakibara; U.S. Pat. No. 5,311,960 Kukainis et al.; U.S. Pat. No. 5,312,133 Pietila et al.; U.S. Pat. No. 5,326,130 Gedeon et al.; U.S. Pat. No. 5,370,417 Kelman et al.; U.S. Pat. No. 5,456,494 Witkovsky; U.S. Pat. No. 5,482,319 Yoshimura et al.; U.S. Pat. No.5,577,770 Sinner et al.; U.S. Pat. No. 5,584,509 Tekelly et al.; U.S. Pat. No. 5,865,468 Hur; U.S. Pat. No. 5,927,755 Matsuo et al.; U.S. Pat. No. 5,951,045 Almefelt et al.; and U.S. Pat. No. 6,017,059 Taubenberger et al.
An object of the present invention is to provide an improved energy absorbing bracket assembly for supporting a knee bolster on a vehicle instrument panel and capable of absorbing energy even in confined spaces.
In carrying out the above object, the energy absorbing bracket assembly for supporting a knee bolster on a vehicle instrument panel in accordance with the invention includes a pair of brackets that are formed from sheet metal. Each bracket has a mounting flange for mounting of the bracket in a generally vertically extending orientation on the vehicle instrument panel in alignment with one of the knees of a vehicle seat occupant. A support flange structure on each bracket provides for mounting of the knee bolster in front of the seat occupant. Each bracket includes a vertically extending energy absorbing section having a peripheral portion and a web that extends generally in a vertical plane from the peripheral portion adjacent the mounting flange to the peripheral portion adjacent the support flange. The peripheral portion of the energy absorbing section includes a pair of peripheral legs located on opposite sides of the web and cooperating therewith to define a pair of spaced openings. The web reinforces the bracket to position the knee bolster but buckles under loading to absorb energy.
In the preferred construction of the bracket assembly, the mounting flange of each bracket extends perpendicular to the generally vertically extending energy absorbing section thereof to provide mounting on the vehicle instrument panel. The support flange structure of each bracket also preferably extends perpendicular to the generally vertically extending energy absorbing section thereof to provide mounting of the knee bolster. This support flange structure of each bracket also preferably includes two flanges that are respectively aligned with the pair of spaced openings on the opposite sides of the web of the energy absorbing section of the bracket.
In the preferred construction, the peripheral legs of the energy absorbing section of each bracket include reinforcement flanges that extend perpendicular to the web of the energy absorbing section. The reinforcement flanges of the pair of peripheral legs of each bracket have curved shapes that extend between the mounting flange and the support flange structure, preferably with an ogee shape. One of the peripheral legs of each bracket is an upper leg whose reinforcement flange has outwardly convex shapes adjacent the mounting flange and adjacent the support flange structure. The reinforcement flange of the upper leg has an outwardly concave shape between its outwardly convex shapes. The other peripheral leg of each bracket is a lower leg whose reinforcement flange has an outwardly concave shape adjacent the mounting flange and an outwardly convex shape adjacent the support flange structure. The mounting flange of each bracket preferably has a connection to the peripheral portion of the energy absorbing section at a location toward the lower leg from the web.
The objects, features and advantages of the present invention are readily apparent from the following detailed description of the best mode for carrying out the invention when taken in connection with the accompanying drawings.

Energy absorbing bracket assembly for vehicle knee bolster


A lamp is disclosed. The lamp has a housing, at least one light source in the housing, and a reflector. The reflector has a light reflective surface facing said light source. The reflector and its light reflective surface is movable with respect to said light source along a path-of-movement to reflect at least a portion of light from the source to provide an adjustable, generally forwardly directed light beam.

The present invention relates to electrical lamps, such as for example LED lamps, having reflectors.
Many, and perhaps most, lamps with reflectors are such that the reflector is not movable and/or centrally located. However, some have movable reflectors, typically movable with the reflector and light source being commonly mounted and thus moving together. Such movable reflectors typically have one or more hinge-joints about which the reflector (and light source) pivot for adjustment. These arrangements are suitable in several lamp arrangements, and thus have become conventional.
Yet, there is a need for improvement in this field. Such arrangements can be limiting and/or present other problems, such as not providing for side adjustment, limiting component placement and/or otherwise.


A method for controlling a power system control area according to a first and a second control performance standard, wherein operation of the control area determines area control parameter values. The method comprises (a) determining a first compliance target for the first performance standard and a second compliance target for the second performance standard (100/200); (b) determining a first performance standard statistical measure responsive to the control area parameter values from a beginning of a first compliance period to a time at which the first average is determined (108); (c) determining a second performance standard statistical measure responsive to the control area parameter values from a beginning of a second compliance period to a time at which the second average is determined; (d) determining a first area control parameter target responsive to the first performance standard statistical measure (116); (e) determining a second area control parameter target responsive to the second performance standard statistical measure (204); (f) determining a first area control parameter correction responsive to the first area control parameter target and the area control parameter values (150); (g) determining a second area control parameter correction responsive to the second area control parameter target and the area control parameter values (228) and (h) controlling the power system according to one or both of the first and the second area control parameter corrections (154/232).

The electrical power system (grid) includes generating sites, transmission lines, distribution equipment and end uses (loads). The electricity is generated competitively at multiple power plants and transmitted from the generating sites over the transmission lines regulated by the Federal Energy Regulatory Commission (FERC). Generation and transmission of the electricity are usually managed and controlled by regional entities that monitor generating capacity, real-time generation and loads, grid operations, market operations (buying and selling of electricity and delivery of the electricity to the buying party), system security and other aspects of the electric power system. There are a number of organizations responsible for overseeing power generation, transmission and distribution activities. Such controlling organizations include regional independent system operators (ISOs), regional transmission organizations (RTOs), reliability coordinators and utility companies. The transmission lines, which may be located in different states, are typically owned by an electric utility or a transmission company.
For safe and efficient operation of the power system, the generated electricity must instantaneously and continuously match the electrical load (i.e., the consumption and generation must be held in balance). Further the grid alternating current frequency (and thus the frequency of each generating unit) must be maintained within a very narrow range around 60 Hz. Excess generation causes the system frequency to increase while deficit generation causes the frequency to decrease. Although it is impossible to maintain a perfect generation and load balance, active control systems attempt to do this by constantly adjusting the power output of the generators. In addition to load imbalance, system frequency deviations from 60 Hz may also be caused by generators that are not properly meeting their desired generation targets, leading to over-generation or under-generation.
Small frequency deviations (e.g., less than about ±0.05 Hz) do not degrade system reliability or market efficiency (the buying and selling of electricity and transmission of the electricity over transmission lines connecting the generator to the load). Large frequency deviations from the nominal 60 Hz (e.g., 0.1 Hz), such as caused by the sudden loss of a generator can damage generation, transmission and load equipment, degrade product quality (causing lights to flicker, for example), collapse the power system (by triggering protective system actions, for example) and overload transmission lines as the remaining generators supply additional electricity to those lines in an attempt to restore the system frequency. Although the power system is designed to quickly recover from the loss of a generator, recovery typically takes several minutes. For example, the loss of a 2600 MW generator in a relatively small grid causes the frequency to drop by about 0.08 Hz and recover in about 10 minutes. Recovery is typically accomplished by tripping generators off line to overcome an over-frequency condition and shedding load to overcome an under frequency condition
The power system is divided into control areas (there are approximately 153 control areas (CAs) in the United States) with each control area exercising some control over the system frequency. An inter-area control system, referred to as an area generation control system ensures that all areas cooperate to control the system frequency. An area control error (ACE), computed for each area within the AGC system indicates the amount of frequency control coordination that a control area is required to contribute to the inter-area system. Use of the ACE spreads the economic burden of frequency control to all participating generators in all control areas. System reliability is thereby enhanced by avoiding reliance on a few generators for system frequency control, improving the system's ability to respond to transient conditions. The ACE value provides a technique to balance frequency maintenance across the entire system.
A frequency bias term is added to the ACE balancing equation to refine frequency control. The nominal target frequency is periodically increased or decreased by about 0.02 Hz to adjust the long term average frequency. Under normal operating conditions the frequency is controlled very tightly.
Balancing aggregate load with aggregate generation in a control area is accomplished through several services that are distinguished by the time frame over which they operate. Under normal operating conditions (i.e., no system disturbances) these services include regulation and load following. Regulation uses on-line generation capacity or stored capacity that is equipped with automatic generation control (AGC) that can change output quickly to compensate for minute-to-minute fluctuations in area load and unintended fluctuations in generation. A typical large fossil-fired plant thermal generator may be able to ramp 1% of its capacity in one minute. Smaller units can and combustion turbines can ramp faster. Loads are controlled by a load shedding function that can shed or restore loads as desired.
Load following uses on-line generation, stored capacity or load shedding equipment to compensate for the inter-hour and intra-hour load ramping. The regulation and load following differ only in the time period over which they operate.
Control area operators are not required to specifically procure load following generation. Instead, the required generation is procured in the short term energy market responsive to the real time energy prices and expected loads. Regulation, however, requires faster response than obtainable from units responding solely to market conditions, Instead, generators (and potentially energy storage units) offer capacity that can be controlled by the system operator's AGC system to balance the system's generation and load.
The control area operator is responsible for controlling its generating units. The AGC system calculates the control command for each generating unit (that is, each generating unit that is under AGC control) and issues the control signal to the generating unit on a per AGC control cycle basis. The AGC control cycle is the rate at which control signals are issued to the generating units. Typically the control cycle is four seconds, but it can be as short as two seconds or as long as five seconds. Thus the AGC system regulates the power output of the control area electric generators in response to changes in system frequency, loading on the interconnected system and the relation of these two parameters. The AGC system attempts to maintain the scheduled system frequency and established power interchange with other control areas, within predetermined limits. The AGC system monitors and controls power generation with the objectives of minimizing ACE, minimizing operating costs, maintaining generation at fixed (base load) values, maintaining net interchange power to the scheduled interchange power, maintaining actual system frequency at the scheduled frequency, and providing for ramp generation in a linear fashion according as scheduled.
Each control area is not able and not required to perfectly match generation and load. Generating an amount of electricity that is in exact equilibrium with the load is extremely difficult and impractical. Instead, control area operators strive to continually alternate between over and under generation. For example, a control area may impose a target of crossing the break even point (i.e., a zero ACE value) fifteen times per hour.
The North American Electric Reliability Council (NERC) has established rules governing how well each control area must balance load and generation. Control performance standards 1 and 2 (CPS 1 and 2) establish statistical limits on how well each control area must balance minute-to-minute fluctuations without degrading system reliability, where the system comprises multiple interconnected control areas. Since a balanced total system is desired, when one control area fails to balance its load and generation, generation in another control area provides the required balancing energy.
CPS1 and CPS2 are standards that measure overall control area performance. CPS1 measures the relationship between the control area's ACE and the system (i.e., interconnected control areas) frequency on a one-minute average basis for the previous eleven months back from the current minute (i.e., a rolling average). When the current minute is the last minute of the calendar month, the CPS1 indicates the relationship for the previous eleven months plus the current month now ended. The twelve month moving window period includes the current month (to the last day and minute of the current month) and the previous eleven months. Each month refers to an entire calendar month, that is, from the first day of a month to the last day of the same month. For example, if the current date is Mar. 5, 2007, the twelve month period runs from Apr. 1, 2006 00:00:00 to Mar. 31, 2007 23:59:59.
CPS1 represents a correlation of the clock-minute frequency deviation average (where clock-minute average refers to the average of all the instantaneous values (e.g., one measured or telemetered instantaneous value every four seconds) during a clock minute) and the clock-minute ACE average over a rolling 12 month period. When the system frequency is above its reference, under generation benefits the system (interconnected control areas) by lowering the system frequency and improves the CPS1 value. Over generation at such times, however, tends to worsen the CPS1 value. Thus CPS1 distinguishes between generation/load imbalances that help to restore the system frequency (a favorable CPS1 value) and those that degrade the system frequency (an unfavorable CPS1 value). The component parameters of CPS1 are determined every minute but the CPS1 values is evaluated and reported on a 12 month rolling average basis. NERC regulations require that each control area must be no less than 100% compliant with CPS1.
CPS2, a monthly performance standard, sets specific control area limits on the maximum ACE for every real time (clock time) 10 minute period. Control areas are permitted to exceed the CPS2 limit no more than 10% of the time, that is, a 90% compliance with the CPS2 value is required. Thus a control area can have no more than an average of about 14.4 CPS2 violations per day during each month. The CPS2 reference to the current month means a calendar month, Mar. 1, 2007 00:00:00 to Mar. 31, 2007 23:59:59.
There is a need for a method and system that reduces the risk of non-compliance with the CPS1 and CPS2 control performance standards set by regulatory authorities such as NERC.

Apparatus and method for predictive control of a power generation system


A method and apparatus is provided for implementing a memory cell array having a performance-improved critical read path using a boost amplifier configuration. The memory bit line is broken into small segments with a boost amplifier and the bit line is connected to the input of the amplifier. The output of the amplifier drives the global bit line. The amplifier is turned "on" during a "read" and turned "off" during a "write". During a read, one memory cell within one array segment is turned on. The memory cell drives the differential signal on to the local bit line pair. Also during a read, the boost amplifier which attaches to that local bit line is enabled. The boost amplifier amplifies the input signal (local bit line pair) and drives that signal on to the global bit line. Since the bit line is broken into small segments with boost amplifiers, there are many boost amplifiers attached on the global bit line. When enough signal is developed on the global bit line pair, the global sense amplifier is turned on. The bit line is thus quickly pulled to ground thereby significantly improving performance for the critical read path.

In traditional differential signal memory arrays utilizing the standard six device cell, four transistors are configured to form a cross-coupled latch/memory cell for storing data and two transistors are used to obtain access to the memory cell. During a "read" access, differential data stored within the memory cell is transferred to an attached bit line pair. Differential voltage is allowed to develop on the bit lines until sufficient offset between bit lines (100-200 mv) has developed to reliably sense the binary state of the memory cell. With the completion of the read, the differential bit line pairs are clamped together and restored high (to a "high" logic level voltage or "VDD") to cancel the offset generated during the read operation.
During a "write" access, data is written into the cell through the differential bit line pair. In general, one side of the bit line pair is driven low (i.e. to a low logic level potential or ground) and the other side of the differential pair is driven high to VDD minus the threshold voltage of the transistor Vt. Following the write, the differential bit line pair must be restored to VDD prior to the next read/write access to the memory cell. For a traditional memory array, the time required for a sufficient bit line offset development to reliably read the memory cell in addition to the time required to restore one-half of the differential bit line pair ground potential to VDD after a write operation defines the minimum cycle time for the array.
Improvements to either the bit line offset development rate, or the bit line restore time following a write, will increase performance of the memory structure as a whole. For a large array, it is more efficient if the array is organized in long column bit lines, i.e. many rows. However, the length of an array bit line is limited by the signal development time for a read. For an array with a long bit line, the signal development time is therefore the most critical path.
Thus there is a need to provide an improved method and apparatus for the implementation of a boost amplifier circuit which is effective to boost the performance of a critical read path in memory cell arrays having extensive bit line layouts.

International Business Machines Corporation


A wheel loader includes: an upper exterior cover covering an upper side of an engine compartment housing an engine; an exhaust heat vent provided to the upper exterior cover; and a first gutter member and a second gutter member disposed below the exhaust heat vent, the first gutter member and the second gutter member each having a lateral surface defining a rise portion rising from a bottom, the rise portion being attached to the upper exterior cover.

Typical wheel loaders as disclosed in Patent Literatures 1 and 2 have been known as a working vehicle equipped with an exhaust gas aftertreatment device for purifying exhaust gas from an engine. The exhaust gas aftertreatment device, which needs to be protected from gravel and the like raised during operation, is disposed above an engine in an engine compartment and covered by an exterior cover.


Method for support control in machine tools where it is controlled whether an object is arranged correctly on a support surface in the machine tool, where a duct system is used which ends in the support surface, and conducts a medium, and can be pressurized, the final opening of the duct system is covered by the object, and in the duct system the pressure of the medium is reduced at a choke point, the differential pressure is determined before and after the choke point, and is evaluated for support control.

Methods, respectively devices, of this type are known. They are methods which are carried out by means of pneumatics according to the principle of impact pressure. An example for that is presented in FIG. 3. For that purpose in the machine tool a pneumatic duct system which can be pressurized is installed at the support spots, respectively rest spots. This pneumatic system has to be installed in addition to the, if necessary, present, coolant/lubricant duct systems. In the duct system a constant supply pressure is generated. This is done, for example, by means of a pressure control valve. A downstream orifice or choke generates a pressure drop in the duct system. The pressure is measured between orifice or choke, and the measuring surface where air outlet openings are provided through which the air can escape, if no work piece, tool, or the like is positioned there. The pressure between the orifice or choke, and the measuring surface, respectively measuring point, depends on the relation between the orifice or adjustment of the choke, and air gap between the support spots of the work pieces, respectively the rest pieces. The change of pressure resulting from that is collected electrically either directly or indirectly over a pneumatic limit value switch, and processed in the machine control. Depending on the volume of the duct and the required accuracy the indexing time changes.
As the support points, respectively rest points, for the work piece have to be clean all the time it is necessary to clean the rest surfaces continuously from chips which might be there. For that purpose additionally coolant or blast air is used. Therefore the duct system has always to be pressurized in order to prevent also the liquid from penetrating the measuring channels. The secure recognition of the support of an object on the support surface could reasonably, according to the required accuracy, only be realized with pneumatic duct systems which had to be provided, as already mentioned, additionally in support surfaces.
Because of the variable supply pressure in the systems working with the coolant/lubricant, the required accuracy could not be reached in the same way as it could be reached in pneumatically charged systems. In this respect there are no hydraulic systems for support control according to the prior art which work with sufficient accuracy and reliability.
In the prior art there is also a device for pneumatic position control known where, via a pneumatic duct system, the pressure is measured on a choke device in flow direction before and after this choke, and a difference pressure sensor collects the respective differential pressure. However, this is also a support control system already described before, which is equipped for measuring, respectively the support control itself, with an additional pneumatic duct system, and thus becomes very expensive.
Another pneumatic support control installation with a differential pressure sensor is known. This also works by means of a differential pressure, and the evaluation via a differential pressure sensor. For this pneumatic support control system also an additional pneumatic duct system is necessary in addition to the coolant, respectively flushing agent, system of the machine tool.
Another support control system is known from the state of the art which already works with a liquid medium. Here, however, the position of the work piece on a reference surface is determined by a position detector. It determines the position of the work piece because of the counterpressure and the distance. The production of this measurement is also extremely complicated. Additionally the detectors are quite prone to malfunctions because of the effects of humidity.

Grob-Werke GmbH & Co. KG, Industriestrabe


In an image data communication system, a digital image recording apparatus captures a desired still image or moving video image. For a color still image, the digital image recording apparatus compresses the image based on JPEG to create a color GIF (graphics interchange format) file. This file is converted to image data having an amount of data which can be processed with a portable telephone or a portable information terminal. An image sender transfers the image data generated from the digital image recording apparatus to an image distribution server. The image distribution server records the image data in an internal recording apparatus and notifies a recipient that the image is ready for distribution by sending, for example, an e-mail message to the portable telephone or the portable information terminal.

The present invention relates to an image data communication system, and more particularly to an image data communication system and a method thereof for displaying on an image display apparatus an image signal which is generated by imaging a subject. The present invention also relates to an image pickup apparatus and an image data processing method used for the image data communication system.
A portable information device, especially a portable telephone, has a limited image data processing capability and often places limitations on the amount of data and the number of colors as regards available digital images. Accordingly, displaying an image on the portable information device requires advanced knowledge about digital images, such as an image retouching program, for example.
To solve this problem, there are provided cameras dedicated to a portable device for displaying images and a special conversion program for a personal computer. An image is created by using these hardware and software products and is input to the portable device according to a special communication protocol.
According to an available service, an image processing server is provided on the network. An image is once uploaded to the image processing server. The uploaded image is automatically converted according to the amount of data and the number of colors which can be processed on the portable information device. The converted image is then downloaded to the portable information device.
When a dedicated communication protocol is used for entering the created image to the portable device as mentioned above, special-purpose devices or programs are needed, increasing costs and causing a compatibility problem.
According to the above-mentioned method, an image processing server is provided on the network and the created image is uploaded for converting the data amount and the number of colors. This method solves the compatibility problem but necessitates additional communication costs. Currently, a mainstream digital still camera is capable of digital images of more than a million pixels, whereas a portable information device supports images of just several tens of thousands of pixels at the most. This results in uploading data several tens of times larger than the number of pixels finally needed, causing unnecessary communication costs. Since the amount of data is compressed considerably, there is a high possibility of degrading the quality of converted images. The conventional method allows confirmation of the image quality only after completion of all processes. There has been frequently a waste of time, communication costs, and charges for the service.

Image data communication system and method thereof, and image pickup apparatus and image data processing method


A method of fabricating a notched electrical test probe tip preferably includes the first step of providing an elongate electrically conductive blank having a longitudinal planar axis, a first end, and a second end opposite the first end. Preferably, the next step is drilling a central bore substantially parallel to the longitudinal planar axis, the central bore extending at least partially from the first end to the second end. Then, preferably, at least one portion of the blank is removed from the longitudinal planar axis at the first end to an exterior surface of the blank between the first end and the second end to expose a contact surface. In one preferred embodiment, the method may include a step of coating the exterior surface of the blank with insulation.

The present invention relates to an electrical test probe tip capable of establishing an electrical connection to test objects on a circuit board and particularly to rounded or irregularly shaped test objects.
Typical modern circuit boards tend to include a variety of components (hereinafter referred to generally as "circuit board components"). For example, most circuit boards will include one or more integrated circuits with a set of leads, legs, or pins (hereinafter referred to as "leads") on both sides of a package. There are also many rounded or irregularly shaped devices such as ceramic resistors, capacitors, through hole pins. Circuit board components such as those described above often need to be monitored or tested by testing instruments such as oscilloscopes and other measuring, monitoring, diagnostic, and signal processing instruments.
Electronic test probes are used to provide an electrical connection between circuit board components and testing instruments. An electronic test probe generally consists of a probing head, a cable, and a connector. The probing head may have an integral or replaceable probing tip that is suitable for making an electronic contact with electrical components. The probing head is attached to a first end of the cable and the connector is attached to the opposite end of the cable.
As shown in FIG. 1, a conventional test probe tip is generally in the shape of a cone that narrows, similar to the point of a pencil, becoming a sharp point or slightly blunt point. Test probe tips are usually made out of conductive metal such as copper, beryllium copper, nickel-palladium alloy, metal alloy, aluminum, steel, or a similar conductive metal.
Test probes that are used manually require an operator to hold the test probe tip against the circuit board components. Conventional test probe tips having a single point can easily slip off circuit board components, especially rounded or irregularly shaped ones. After slipping off a circuit board component, the exposed conductive material on a conventional test probe tip may, for example, contact two leads at the same time, cause an electrical short, and possibly damage the component.
Approaches have been taken in the past to solve the problems of a conventional test probe tip slipping and contacting two leads at the same time, causing an electrical short.
U.S. Pat. No. 4,783,624 to Sabin (the "Sabin reference") sets forth a contact probe device and, as an example of an alternative to common conical pointed tips, a test probe tip with a "V" cut. As shown in the Sabin reference, the wide portion of the V starts from the outer periphery of the first end of the tip and the narrow portion of the V meets at the center longitudinal planar axis toward the second end. The Sabin contact tip essentially creates two contact points instead of one. These points are unsteady and would tend to slip almost as easily as a single tip. This is a particular problem created with testing rounded or irregularly shaped leads or circuit board components. Further, the Sabin contact tip's design requires that most or all of the tip be exposed conductive material in order to establish good electrical contact with the contact points. The amount of exposed conductive material increases the chance for a short to occur. Finally, the probe tip with a "V" cut would be difficult to create and expensive to produce.
U.S. Pat. No. 5,731,710 to Mizuno et al. sets forth several test probe tips (the "Mizuno tips") that have sharp edges particularly suited for breaking through a surface of a test member so as to establish an electrical connection. In several of the embodiments, a plurality of slits extends radially and axially from a top center of the tip. Although the slitted embodiments of the Mizuno tips would be well suited to probing through hole pins, they would be poorly suited to probing components that are rounded or irregularly shaped. Further, the Mizuno tips appear to have an exterior surface that is exposed conductive material and, therefore, would increase the chance for a short to occur. Finally, the Mizuno slitted tips would be difficult to create and expensive to produce.
U.S. Pat. No. 5,557,213 to Reuter et al. sets forth a spring-loaded electrical contact probe having a tip that has a locking attachment that includes at least one slot and at least one flange. The primary purpose of the slot and flange appear to relate to the locking feature of the locking attachment.

Method of fabricating a notched electrical test probe tip


An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries in the address translation cache are invalidated.

1. Technical Field
This invention generally relates to computer systems, and more specifically relates to the field of addressing schemes in computer systems.
2. Background Art
Computer systems have addressing capabilities that are defined by the computer hardware. The address space of a computer system is the range of addresses available to reference data, instructions, etc., and is determined by the size (in bits) of the address. The address size is one of the fundamental architectural features of a computer system. Early computer systems were single-user computers that could handle only a single task at a time, mapping all data into a single address space, and swapping data into and out of the address space whenever a new task needed to be performed. Later, computers were developed that supported multiple users and processes (or tasks). A computer system that supports multiple tasks must manage the allocation of the address space among the different tasks. That is, the effective addresses specified or computed by programs running in multiple tasks must be efficiently translated into real (physical) addresses used to access memory. More than one such address translation mechanism, or mode, may be provided by a single computer system. Examples of some address translation modes are given next.
Because the address space for all the tasks that might run on a computer system typically exceeds the system's physical address space size, a separate address space is typically allocated to each task, resulting in multiple virtual address spaces. This type of addressing is known as "local addressing", because each task has its own virtual address space that is local to the process, and cannot be seen by other tasks.
Local address translation logic typically provides translation of effective addresses to virtual addresses, and virtual addresses to real (or physical) addresses using tables stored in memory and in registers in the processor. For example, a Segment Lookaside Buffer (SLB) may be used to translate high-order bits of an effective address to high-order bits of a virtual address. In addition, address translation caches may be used to store recently-used address translations, thereby speeding execution of subsequent uses of the same translations. One type of address translation cache translates effective addresses directly to real addresses (ERAT). These caches speed computation by avoiding the two step process of translating an effective address to a virtual address and then translating the resulting virtual address to a real address. However, because effective address space values for different tasks typically must be translated to different virtual and real addresses, when an operating system switches from one task to another, the address translations must be changed, so nearly all of the cached local addressing translations must be invalidated as part of task switch processing. Note that a subset may be reserved by operating system convention for common use in more than one process or for use by the task switch code, so these entries need not be invalidated.
Another addressing mode used by some systems is a static or direct mapping between effective and virtual addresses, so the SLB is not used. For this addressing mode, all tasks share this portion of the effective address space. Thus a task switch does not change any part of the effective to real mapping, so ERAT entries derived from these translations remain valid.
More recently, computer systems have become capable of supporting multiple logical systems on the same hardware complex, through the use of a layer of firmware called a hypervisor. Each logical system image may be referred to as a partition. On such systems, the hypervisor must manage the hardware address translation facilities in a manner that strictly separates the address spaces used by different partitions, because each partition represents an independent system image. Another type of addressing mode supported by these systems is when the operating system thinks it is directly using real addresses, but in reality hardware features managed by a hypervisor interject some other form of address translation. These address translations are inherently global to a logical partition and so should survive task switches within a logical partition, but must be invalidated during partition switches. As a final example, hypervisor real address use is not affected by task switches or partition switches.
In known systems, task and partition switches typically perform a mass invalidation of address mappings, including invalidation of all entries in an effective to real address translation cache. Task switches are common and must typically invalidate the Segment Lookaside Buffer (SLB) anyway, so this mass invalidation might be accomplished as a side-effect of an instruction that invalidates the SLB, for example. By performing a mass invalidation of entries in an effective to real address translation cache, the prior art systems implicitly assume that none of the address translations in the effective to real address translation cache will be valid after a task or partition switch. This assumption, however, is not correct, because some of the address translations in the effective to real address translation cache remain valid even after a task or partition switch. Without an effective apparatus and method for selectively invalidating entries in an address translation cache, the prior art will continue to suffer from the performance penalty that results from invalidating too many entries in an address translation cache, too frequently.

This patent is subject to a terminal disclaimer.

Apparatus and method for selectively invalidating entries in an address translation cache

International Business Machines Corporation


A soft-start circuit includes an error amplifier, a reference voltage ramp circuit, and a minimum current clamp circuit. The error amplifier is configured to generate a difference voltage representing a difference of a feedback voltage and a reference voltage ramp. The reference voltage ramp circuit is configured to generate the reference voltage ramp. The minimum current clamp circuit is configured to clamp an output of the error amplifier to a predetermined minimum voltage.

DC-DC converters typically include one or more switches that are selectively actuated to provide a controlled DC output voltage or current based on a received DC input. The output power is regulated by controlling the pulse width or on time of the signals provided to the converter switch or switches according to an error signal representing the difference between the actual output voltage or current and a desired value. A capacitor is typically connected at the converter output in parallel with a driven load in order to stabilize the converter output voltage and provide a source for load current. At power up, however, the output capacitor is initially discharged, and the difference between the output voltage and the desired value may be large, causing the DC-DC converter to provide large amounts of current to the output. The output capacitor may therefore experience high levels of inrush current during startup. A DC-DC converter may include soft-start circuitry to limit the amount of inrush current provided to the output capacitor during startup.

Self-adjusting DC/DC converter soft-start mechanism


A roller skate which includes a frame, a structure for fixing the frame to a person""s foot, and at least two balls, which are freely rotatably supported by concave rollers. Axes of rotation of the rollers extend in a horizontal direction, transversely to the longitudinal direction of the frame. A roller is located between the two balls which are arranged side by side. The roller bears against both balls during operation.

1. Field of the Invention
The invention relates to a roller skate comprising a frame, means for fixing said frame to a person""s foot, and at least two balls, which are freely rotatably supported by concave rollers, whose axes of rotation extend in a direction, transversely to the longitudinal direction of the frame and in use parallel to a rolling surface.
2. Discussion of the Background
With a similar roller skate, which is known from US patent U.S. Pat. No. 4,076,263, each ball is supported by one roller positioned vertically above said ball and two rollers positioned in front of and behind the central roller respectively. Said rollers are concave. The roller skate is supported on the road surface by means of said balls, whereby the presence of the balls leads to an improved road behaviour in comparison with that obtained with conventional axle-supported, barrel-shaped rollers which roll on the road surface. In particular when braking, said balls exhibit better road behaviour, because the balls can also rotate i-n a direction transversely to the direction of transport. The concave rollers thereby exert a force on the balls, as a result of which the balls are gradually brought to a standstill. One drawback of the known roller skate is the fact that, due to the presence of the relatively large rollers on either side of the balls, the number of balls to be mounted under the frame is limited. This has an adverse effect on the rolling behaviour of the roller skate.
The object of the invention is to provide a roller skate wherein the balls can be positioned a relatively small distance apart.
This objective is accomplished with the roller skate according to the invention in that a roller is present between two balls which are arranged side by side in the longitudinal direction of the frame, which roller bears against both balls during operation.
The diameter of the roller can be selected practically independently of the distance between the two balls which are arranged side by side, so that an optimum freedom of design is obtained.
Another embodiment of the roller skate according to the invention is characterized in that the number of rollers less the number of balls equals 1.
Since the number of rollers is only 1 higher than the number of balls, a relatively simple and inexpensive construction of the roller skate is obtained.


The stator (24) of a permanent magnet axial flux alternator comprises two annular stator components which are each wound with a respective two phase winding arrangement (48). Each of the two phase winding arrangements (48) is wound so that there is no mutual inductance between the windings of each phase. Each phase of the two phase winding arrangements (48) wound on the two stator components has a high internal impedance and is for energising a respective high intensity lamp of a light tower.

This invention relates to an alternator assembly which can provide an output to a plurality of loads and more particularly, although not exclusively, which is operable to provide an initial voltage output sufficient to initiate conduction of each of a plurality of high intensity lamps to be energised followed by a sustaining voltage output to maintain current flow in each of the lamps after the initial conduction.
U.S. Pat. No. 5,808,450 discloses a lighting system which eliminates the need for ballast and voltage regulation in the system by providing an alternator assembly having internal impedance characteristics significantly and substantially above the conventional impedance and by transmitting electrical AC power preferably at a high frequency (say between 200-600 Hz and more particularly between 500-550 Hz) from the alternator usable for direct connection to an associated lamp. In a mobile light tower application, the system preferably has a plurality of lamps and each lamp has a dedicated alternator winding which outputs electrical AC power suitable for direct supply to that lamp. Each winding is preferably formed as a part of a separate alternator unit having its rotor and high impedance output windings. However, an alternator assembly may be provided in which a stator is wound with an appropriate plurality of individual dedicated stator windings, one for each of the lamps to be energised. This would imply the use of a poly-phase machine, one phase for each of the lamps to be energised. However, a poly-phase system operating on a common magnetic circuit would be exposed to inherent mutual inductance between phases. For example, if four lamps were used, this would be proportional to the cosine of 45 degrees (0.707). Thus the reactance of the phases would change and, hence, the luminescence output from each lamp, depending on the number of lamps energized at any one time.
U.S. Pat. Nos. 6,094,011 and 6,239,552 each disclose a discharge lamp lighting system, which does not require ballast between the generator and the lamps wherein the generator includes a plurality of generating coils, one for each lamp, the generating coils being electrically independent from each other. Also a stator of the generator is provided with means by which each of the generating coils is substantially kept from flow of magnetic flux interlinking the other generating coils through the magnetic circuit.
U.S. Pat. No. 4,996,457 discloses a permanent magnet axial flux alternator having a rotor disc between a pair of annular stator discs. Each stator disc carries a winding which has its output connected to a respective load. A magnetic isolator within the rotor isolates the magnets on each side of the rotor and thus isolates each stator disc so that operation of the load connected to one of the stator discs does not affect any operation in the load connected to the other stator disc.
Two forms of alternator assembly which embody this invention and which are for use in a portable light tower are described now by way of example with reference to the specification and the accompanying drawings.


Parallel processing of data may include a set of map processes and a set of reduce processes. Each map process may include at least one map thread. Map threads may access distinct input data blocks assigned to the map process, and may apply an application specific map operation to the input data blocks to produce key-value pairs. Each map process may include a multiblock combiner configured to apply a combining operation to values associated with common keys in the key-value pairs to produce combined values, and to output intermediate data including pairs of keys and combined values. Each reduce process may be configured to access the intermediate data output by the multiblock combiners. For each key, an application specific reduce operation may be applied to the combined values associated with the key to produce output data.

Large-scale data processing may include extracting data of interest from raw data in one or more datasets and processing it into a data product. The implementation of large-scale data processing in a parallel and distributed processing environment may include the distribution of data and computations among multiple disks and processors to make use of aggregate storage space and computing power.


A signal processing system includes a phase-locked loop to provide an output signal used, for example, as a delta sigma modulator operating clock signal. In at least one embodiment, a frame clock that provides synchronization for one or more blocks of data is used by the phase-locked loop as a reference signal. Utilizing the frame clock as the reference signal allows the signal processing system to reduce the number of clock signals present in the signal processing system. In another embodiment, a phase-locked loop includes a loop filter that utilizes a sample and reset circuit, a feed forward integrator, and a feed forward stabilizer to provide a low frequency phase-locked loop bandwidth. In at least one embodiment, the feed forward integrator amplifies capacitance of the sample and reset circuit, which reduces the size of loop filter capacitors and, thus, allows on-chip capacitor integration.

1. Field of the Invention
The present invention relates in general to the field of information processing, and more specifically to a signal processing system and method for generating a clock signal using a low-bandwidth phase-locked loop.
2. Description of the Related Art
Phase-locked loops are widely used in integrated circuits to provide an output signal in a predetermined phase relationship with a reference signal. The phase-locked loop output signal is a multiple of the reference signal. FIG. 1 depicts a classical phase-locked loop 100. The phase detector 102 compares a reference signal Ref having a frequency fref with a phase-locked loop feedback signal FB having a frequency fVCO/N and generates a phase error signal E, where N is a positive real number. Thus, the phase-locked loop 100 increases the frequency fref of reference signal Ref by a factor of N and maintains phase-alignment with the reference signal Ref. The value of the phase error signal represents a difference between phases of the reference signal Ref and the feedback signal FB. The reference signal Ref typically originates from a signal source that produces a periodic signal such as a crystal or ring oscillator. The loop filter 104 acts as a low-pass filter to smooth the phase error signal.
Voltage controlled oscillator (VCO) 106 generates a periodic phase-locked loop output signal PLLOUT having a frequency fVCO=fref×N. The filtered phase error signal E is an oscillator control signal OCS that regulates the frequency of the phase-locked loop output signal PLLOUT. The VCO 106 responds to the phase error signal E by increasing or decreasing the frequency of phase-locked loop output signal PLLOUT to match fref×N. The phase-locked loop output signal PLLOUT feeds back through frequency divider 108 to generate the feedback signal FB. Thus, the phase-locked loop 100 provides the output signal PLLOUT that is intended to have a predefined phase relationship (such as phase alignment) with the reference signal Ref and is a multiple of reference signal Ref. Some embodiments of phase-locked loop 100 substitute a current controlled oscillator (ICO) for the VCO 106. The phase-locked loop 100 operates essentially in the same manner except that the loop filter 104 includes a transconductance amplifier to provide a current based control signal to control the phase-locked loop output signal PLLOUT of the VCO 106.
FIG. 2 depicts an illustrative digital-to-analog signal processing system 200 having a delta sigma modulator 202 that converts oversampled input signal DATA into a series of M-bit output signals, where M is an integer greater than or equal to one (1). In at least one embodiment, the average of the series of M-bit represents the input signal DATA. The digital-to-analog converter (DAC) 204 converts the digital output of delta sigma modulator 202 into an analog signal output signal y(t). The signal processing system 200 is particularly useful for audio applications. For audio applications, the bandwidth of interest for the input signal DATA is generally in the 0 Hz to 25 kHz region. The analog signal generated by DAC 204 can be used for many purposes, such as to drive audio speakers.
The delta sigma modulator 202 and DAC 204 are clocked by the phase-locked loop output signal PLLOUT of phase-locked loop 206. In at least one embodiment, phase-locked loop 206 operates in the same manner as phase-locked loop 100. Serial clock SCLK represents the reference signal used by phase-locked loop 206.
FIG. 3 depicts clock signal timing diagrams 300 of two clock signals typically present in an audio digital-to-analog signal processing system. Clock signal LRCK represents a 'left-right' clock and is also often referred to as a "frame clock". The frame clock signal LRCK identifies sample rates and frames two channels of data that exist in a single data stream. Historically, the equally spaced pulses of frame clock signal LRCK have a fifty percent (50%) duty cycle with the peaks and valleys being assigned to respective left and right channels (or vice versa). Thus, in a two channel system, data received during a peak is assigned to the left audio channel, and data received during a valley is assigned to the right audio channel. The use of the frame clock signal LRCK can be expanded for use in other multi-channel systems by assigning multiple channels to each peak and valley of frame clock signal LRCK.
The serial clock SCLK, also referred to as a "bit clock", is used to clock the shifting of data into or out of a serial data port. The frequency of the serial clock SCLK is directly proportional to a data sampling rate and data word length. The minimum serial clock SCLK frequency is twice the sampling rate times the number of bits in each data word.
The third clock signal (not shown) is a master clock. The master clock is used to derive the frame clock signal LRCK and, thus, has a fixed, proportional relationship to the frame clock signal LRCK.
Referring to FIGS. 2 and 3, the loop bandwidth of the phase-locked loop 200 sets the low-pass cutoff frequency of the VCO control signal. As the loop bandwidth of phase-locked loop 200 narrows, the phase-locked loop 200 becomes slower in responding to phase changes in the reference signal Ref and maintaining a lock on the reference signal Ref becomes more difficult.
The serial clock SCLK has a higher frequency relative to the frame clock signal LRCK. Thus, phase-locked loop 206 has a wide loop bandwidth to track the relatively high frequency serial clock SCLK. A wide bandwidth phase-locked loop 206 is desirable from an integrated circuit standpoint because capacitors in loop filter 104 are relatively small can often be implemented as part of the integrated circuit, i.e. 'on-chip'.
However, the serial clock SCLK is not a particularly stable reference source relative to the master clock and the frame clock signal LRCK. Instability, such as jitter (i.e. phase changes) and frequency shifts, in the reference signal causes the phase-locked loop output signal PLLOUT to also reflect the instabilities of serial clock SCLK.
FIG. 4 depicts an illustrative digital-to-analog signal processing system 400 (DAC system 400) that uses a master clock MCLK as a reference signal for the wide bandwidth phase-locked loop 402. In at least one embodiment, phase-locked loop 402 operates in the same manner as phase-locked loop 100. The DAC system 400 includes delta sigma modulator 202 followed by a pulse-width modulation encoder 404 to convert the serial output of the delta sigma modulator 202 into a representation of the input signal DATA. DAC system 400 also includes a low-pass, digital finite infinite response (FIR) filter 406 typically having 64-taps or less to attenuate energy in out-of-band frequencies. The DAC 408 converts the digital output of the FIR filter 406 into an analog output signal y(t).
A crystal oscillator generates the master clock master clock MCLK. The master clock MCLK is typically more stable and has a higher frequency than the serial clock SCLK and provides a reliable reference signal to phase-locked loop 402. However, the DAC system 400 still uses the serial clock SCLK, the DATA signal, and the frame clock signal LRCK to convert the digital DATA signal into an analog signal. The addition of the master clock MCLK, while addressing the stability issues of the serial clock SCLK, adds an extra level of complexity, electromagnetic issues, and cost to an integrated circuit.
FIG. 5 depicts a Type III RC loop filter 500 which represents an exemplary loop filter of a phase-locked loop such as phase-locked loop 100. In general, the loop filter design can govern the response of a phase-locked loop. The phase error signal E from the phase detector controls the conductivity of switches 502 and 504. A charge pump 501 includes switches 502 and 504 to respectively source or sink current to the RC circuit 506. Switches 502 and 504 can be respective complimentary metal oxide semiconductor (CMOS) p-channel and n-channel transistors. If the phase error signal E indicates a phase increase (UP) is needed for the phase-locked loop output signal PLLOUT to match the phase of the phase-locked loop reference signal, switch 502 conducts to source charge to the RC circuit 506 while switch 504 is nonconductive ("off"). Otherwise, to decrease the phase of phase-locked loop output signal PLLOUT, switch 504 conducts to sink charge from RC circuit 506 while switch 502 is off. In one embodiment, the phase error signal E is split into non-overlapping signals E and Ē (i.e. the inverse of E) to respectively control the conductivity of switches 502 and 504
Equation [1] represents an open-loop, S-domain transfer function for loop filter 500:
                                                        H                                            (                s                )                                      open                    =                                    Icp              ×              Kvco              ×                              (                                  1                  +                                                            RC                      1                                                            s                                                  )                                                    2                            π              ×              N              ×                                                s                  2                                                                  (                                                                                RC                        1                                                                                C                        2                                                                  s                                        +                                          C                      1                                        +                                          C                      2                                                        )                                                                    ,                            [        1        ]            where Icp is the charge pump source/sink current, Kvco is the VCO gain constant, R is a resistor value, C1 and C2 are capacitor values, N is the frequency division constant, and s is a Laplace complex variable.
From equation [1], for low frequency loop bandwidth operation, e.g. below approximately 5,000 Hz, the implementation and performance of RC loop filter 506 can exhibit several drawbacks. For example, the loop filter 500 produces an undesirable ripple in control signal oscillator control signal OCS at low frequencies, such as 48 kHz or less, and high divide ratios, such as 1024:1. Additionally, to achieve low bandwidth operation, capacitors values C1 and C2 will be too large to be implemented on-chip. In at least one embodiment, for an audio application, low bandwidth is at or below 20 kHz. For example, for Icp=10 μA, Kvco=40 MHz/V, and a loop bandwidth of 5 kHz, C1=1.2 nF, which is too large to practically integrate on-chip.
FIG. 6 depicts a dual charge pump, loop filter 600, which represents an exemplary loop filter of a phase-locked loop such as phase-locked loop 100. Embodiments of the components and operation of loop filter 600 are described in U.S. Pat. No. 6,690,240. The loop filter 600 includes a feed forward, reset path 602 to provide loop stabilization and includes an integration path 604. The transfer function of loop filter 600 is based on an average charge from charge pumps 606 and 608. Accordingly, the oscillator control signal OCS is a step function with minimal ripple. However, from the natural frequency equation [2], the phase-locked loop bandwidth is determined primarily from capacitor 614. So, as the corner bandwidth frequency decreases, the value Cint of capacitor 614 increases. For low frequencies, e.g. lower than 5 kHz, capacitor 614 is too large to be integrated on-chip and is, thus, implemented as a discrete component.
Additionally, the reset path 602 has two paths 610 and 612. The two paths 610 and 612 hold the input voltage of gm2 and separate switching noise from charge pump 606 from the ICO 616. However, any mismatch between capacitor Cprop1 and Cprop2 causes an undesirable tone at the switching frequency/2 in the phase-locked loop output signal PLLOUT.
                                          ω            n                    =                                                    Kico                ×                Icp                ×                gm                                                                                1                                            2                                π                ×                Cint                ×                N                                                    ,                            Equation                                          [        2        ]            ωn is the natural frequency of loop filter 600, Icp is the charge pump 606 source/sink current, Kico is the ICO gain constant, Cint represents the value of integrating capacitor 614, N is the frequency division constant, and gm1 is a transconductance amplifier.

Signal processing system with low bandwidth phase-locked loop


Process for the preparation of fluorinated alkanes by contacting a starting material of halogenated alkene or alkane with 1 to 150 molar equivalents based on catalyst of HF, 1 to 30 molar equivalents based on catalyst of a dehydrating agent and less than 100 molar equivalents based on catalyst of a starting material, the catalyst being selected from niobium oxide or tantalum oxide, at a temperature of 0.degree. C. to 185.degree. C. The preferred dehydrating agent is a combination of chlorosulfonic acid and thionyl chloride.

A. E. Feiring, Journal of Fluorine Chemistry, 13, 7-18 (1979) discloses the use of tantalum pentafluoride as a catalyst for the addition of hydrogen fluoride to tetra- and trichloroethane and related compounds. The catalyst is also useful in fluorine-chlorine exchange reactions. However, under the conditions of the batch experiments [HF/CCl.sub.2 .dbd.CCl.sub.2 =2.5, temperature=150.degree. C., reaction time=six hours] catalysts such as BF.sub.3, TaCl.sub.5, Ta.sub.2 O.sub.5, CoF.sub.3, V.sub.2 O.sub.5, ZrCl.sub.4, NbCl.sub.5, HgO, and WCl.sub.6 showed no catalytic activity for the addition of HF to tetrachloroethylene.
The use of tantalum pentafluoride as a catalyst for the addition of hydrogen fluoride to unsaturated compounds has been disclosed and claimed by Feiring in U.S. Pat. No. 4,258,255.
The use of dehydrating agents to prepare anhydrous TaF.sub.5 has been disclosed and claimed in Kim U.S. Pat. No. 4,124,692.
The need to provide an economically attractive process to produce highly fluorinated, hydrogen-containing alkanes useful as alternatives to current products for refrigerants, blowing agents, etc. has sparked interest in this area.
This invention provides a low cost process for the preparation of fluorinated alkanes made by catalyzed HF addition to olefins and/or fluorine for chlorine exchange on chlorinated alkanes using a system comprised of Ta.sub.2 O.sub.5 or Nb.sub.2 O.sub.5, a dehydrating agent(s), e.g., HOSO.sub.2 Cl (chlorosulfonic acid), and SOCl.sub.2 (thionyl chloride) and excess HF.


A method of manufacturing a liquid crystal display device, which comprises the steps of forming an amorphous silicon layer on a substrate, and irradiating, by way of scanning, a linear energy beam onto the amorphous silicon layer, thereby converting an irradiated portion of the an amorphous silicon layer into a polycrystalline silicon layer. The irradiation and scanning of the linear energy beam are performed plural times while shifting the scanning of the linear energy beam so as to allow the irradiation of the linear energy beam to cover every region of the amorphous silicon layer that is desired to be converted into a polycrystalline silicon layer. The scanning of linear energy beam is performed in such a manner that an edge portion of one irradiated region is overlapped by an edge portion of the next neighboring irradiated region in a plurality times of scanning of the linear energy beam thereby forming an overlapped region, and that a boundary to be formed between the overlapped region and non-overlapped region becomes non-linear in shape.

1. Field of the Invention
This invention relates to a method of manufacturing a liquid crystal display device, and in particular to a method of scanning a linear energy beam for crystallizing amorphous silicon into polycrystalline silicon by irradiating the linear energy beam onto the amorphous silicon plural times.
2. Description of the Related Art
As a method of manufacturing a thin film transistor of a liquid crystal display device, there has been developed a method of forming source and drain regions, which is featured in that part of amorphous silicon layer is converted to a low resistance layer by partially polycrystallizing the amorphous silicon layer. As a method of polycrystallizing an amorphous silicon layer, an energy beam is employed to melt and then recrystallize the amorphous silicon layer.
As for the method of irradiating the energy beam, there is proposed in Japanese Patent Unexamined Publication Shou/61-187,222 a method of linearly irradiating the energy beam.
Further, Japanese Patent Unexamined Publication Hei/2-78,217 discloses a method of irradiating a linear energy beam by scanning it plural times in such a manner that an overlapping region is constantly formed between the neighboring irradiated regions of the energy beam.
However, if an overlapping region of energy beam is constantly formed as mentioned above, the irradiation dosage of the energy beam at the overlapping region naturally becomes larger than that in other regions, so that the characteristics of a thin film transistor, in particular, the threshold characteristics thereof is delicately altered, thereby giving rise to a problem of non-uniformity of display image. In particular, if the irradiation of energy beam is carried out so as to constantly form an overlapping region as mentioned above, the non-uniformity of display image is caused to appear in the form of a straight line and in a visually exaggerated manner.

Method of manufacturing liquid crystal display device


This application relates to the field of wireless communications technologies, and in particular, to a data processing method, apparatus, and system. This application provides a data processing method. A transmit device uses a sequence to carry data and a reference signal. The transmit device carries the two channels of data on an odd element and an even element of the sequence, respectively. The transmit device successively maps the sequence that carries the two channels of data to allocated subcarriers, and then sends the data in an orthogonal frequency division multiplexing (OFDM) manner. This application is intended to decrease cubic metric (CM)/peak-to-average ratio of a transmitted signal of an orthogonal frequency division multiplexing OFDM system through sequence design and mapping of the two channels of data to subcarriers, thereby improving link quality of an entire transmission system.

Technologies based on orthogonal frequency division multiplexing (OFDM) have advantages in aspects such as eliminating multi-path interference and being compatible with multiple-input multiple-output (MIMO). Currently, such technologies are employed by most present wireless communications systems, such as long term evolution (LTE) and worldwide interoperability for microwave access (WiMAX) systems.
A next-generation communications system, such as the 5th generation mobile communication (5G), allows a physical uplink control channel (PUCCH) to be sent together with a reference signal (RS) and uplink control information (UCI) on an OFDM symbol. Alternatively, two signals need to be transmitted, and information carried on each signal is modulated to be transmitted on respective sequence elements. If the foregoing two signals are still carried by a sequence in a LTE system, cubic metric (CM)/peak-to-average ratio is increased. However, CM causes a transmitted signal to be distorted when the signal passes through a power amplifier (PA), and extra error vector magnitude (EVM) is generated at a transmit end, which finally lowers demodulation performance of a receive end. To reduce the EVM of a transmitted signal, actual transmit power usually needs to be reduced, but reduction of the transmit power also lowers the demodulation performance of the receive end. Alternatively, a high peak-to-average ratio (PAPR) also decreases the transmit power, and therefore lowers the demodulation performance.
Therefore, a low-CM/PAPR signal transmission method based on an OFDM system is desired to improve link quality.

Signal transmission method, signal reception method, apparatus, and system in wireless communication


Methods for packaging Metarhizium fungal cultures or conidia are described. In one embodiment, the fungal culture is provided within an insect infection chamber that attracts insects, then infects them with a lethal dosage of fungus, where the packaging maintains high humidity within the chamber, allows free exchange of gases, and is impermeable to microbes, including fungal spores, viruses, and bacteria. In a second embodiment, the fungal conidia are packaged under conditions which maintain high viability even after long-term storage at both 25.degree. C. and 37.degree. C., i.e., low relative humidity and oxygen. The conidia can then be reactivated for the use in the control of insects such as cockroaches, flies, ants, soft-bodied insects, turf pests, and caterpillars.

The present invention relates to an improved means and methods of storage and reactivation of entomopathogenic fungal cultures and conidia, especially of the genera Metarhizium.
Insect pathogens are an alternative to the common use of highly toxic chemical insecticides for the control of insect pests. Bacteria such as Bacillus thurigenesis are used with some success as a spray on plants susceptible to infestation with insects such as the gypsy moth. Fungi are another promising group of insect pathogens suitable for use as biological agents for the control of insects. The most common mode of growth and reproduction for fungi is vegetative or asexual reproduction which involves sporulation followed by germination of the spores. Asexual spores, including conidia, form at the tips and the sides of sporogenous cells on the hyphae, the branching filamentous structures of multicellular mycelium. In the proper environment, the conidia germinate, become enlarged,and produce germ tubes. The germ tubes develop, over time, into hyphae which in turn form mycelia. When the insect is inoculated via contact with the living propagules of the entomopathogenic fungi, the infection occurs as soon as the parasite relationship between the fungus and the target insect is established. With the development of infection, the fungus gradually kills the insect.
U.S. Pat. Nos. 5,057,316 and 5,057,315 disclose a method for control and extermination of insects, including roaches, flying insects such as the housefly, and other insects such as the adult form of the corn rootworm. The insects are controlled and exterminated by infection with a fungus that can be pathogenic when administered to the insects in a sufficiently high concentration, by means of an infection chamber. The chamber maintains the spores of a fungus pathogenic to the insects in a viable form, protecting the fungi from the environment (including rain, ultraviolet light and the wind), serves as, or houses, an attractant for the insects, and serves to inoculate the insects with high numbers of spores. The fungal culture provides a continuous supply of spores over a prolonged period of time. The spores attach to the insects and originate germ tubes that penetrate into the insect, which can result in death within three to four days. The chamber design, i.e., shape and color, can be the sole attractants for the insects. Alternatively, food or scents can be used to further enhance the attraction of the insects for the chamber. Although the primary means of infection is by external contact, the insects may also be infected by contact with each other and by ingestion of the spores. In some cases, the ingested fungal conidia can also be toxic.
A historical limitation on the commercial success of insect pathogenic fungi has been their lack of good storage characteristics. Although the chambers described in U.S. Pat. Nos. 5,057,316 and 5,057,315 have been demonstrated to be highly effective both in the laboratory and under actual field test conditions, it is necessary that they withstand shipping and be stable to prolonged storage at room temperature in order to constitute a viable commercial product.
The two most preferred entomopathogenic fungi are Metarhizium anisopliae and Beauveria bassiana. However, only limited success in commercialization of products of these two fungi has been achieved so far because of the obstacles encountered in stabilization, storage, and after-storage reactivation of fungal propagules such as conidia.
There is a series of six stages in the life history of a conidium: formation, maturation, after-ripening, activation, dormancy, and germination. In the dormancy stage, the spore is in a state of reduced physiological activity with an extended period of quiescence, and is most tolerant to the external environmental conditions. There are two types of dormancy: constitutive dormancy involves endogenous constraints that are not overcome simply by supplying conditions suitable for growth; exogenous dormancy is environmentally imposed, and ends when conditions suitable for growth are presented. Exogenous dormancy can be imposed either by withholding a special nutrient required for germination or by the presence of inhibitors, and can be maintained under certain environmental conditions.
It has been known for some time that dried microbial spores, cells, and other type of propagules may be preserved for longer periods of time than fresh ones. However, most scientists accept the generalization that dehydration of living cells may result in massive upheavals of membranes with irreversible loss of the structural and functional integrity (Crowe & Crowe, Stabilization of Membranes in Anhydrobiotic Organisms, In MEMBRANES, METABOLISM AND DRY ORGANISMS, A. C. Leopold, Comstock Publishing Co., Ithica, N.Y., pp. 188-209 (1986); Beker & Rapoport, Conservation of Yeast by Dehydration, In ADVANCES IN BIOCHEMICAL ENGINEERING/BIOTECHNOLOGY, Vol.35 of BIOTECHNOLOGY METHODS, ed. A. Fiechper, Springer Verlag, pp. 127-171 (1987)). This generalization is supported by the fact that there is a significant reduction of germination rate when spores or other types of microbial propagules are dried. Most research work on structural damage caused by dehydration has been focused on yeasts (Beker & Rapoport, 1987). Filamentous fungi produce different types of propagules, and conidium is the one that can be produced abundantly in a short period of time. However, conidia are not tolerant of dehydration. It has been found that conidia of various entomopathogenic fungi are very sensitive to drying processes and lose their viability very quickly (European Patent Application No. 92100010.5 by Eyal, et al.) Efforts have been made to develop mycelium formulations (Australia Patent Application No. P 36 39 508.8 by Andersch, et al.;), however, mycelial formulations are not stable at high temperatures, and have limited applications.
There are several studies on the effect of storage temperature and relative humidity (R.H.) on conidial stability and efficacy of Metarhizium anisopliae and Beauveria bassiana (Daoust & Roberts, Effect of Formulation on the Viability of Metarhizium anisopliae Conidia, J. of Invertebrate Pathology, Vol. 41, pp. 151-160 (1983); Walstad, J. D., "Effects of Environmental Conditions on Two Species of Muscardine Fungi (Beauveria bassiana and Metarhizium anisopliae)", J. of Invertebrate Pathology, Vol. 16, 221-226 (1970)). The results of these studies indicated that conidia of M. anisopliae survived the longest at moderate temperatures in the presence of high R.H. (26.degree. C.+97% R.H. or 19.degree. C.+97% R.H.). However, conidia lost their ability to germinate in a short period of time at 37.degree. C. Germination is the first stage in the establishment of an entomopathogenic fungus.
During transportation and warehouse storage, the temperature could be as high as 37.degree. C. No efforts have been made by the prior art to carefully investigate the status of the conidia that failed to germinate. Although techniques for accelerating and synchronizing germination of conidia of M. anisopliae have been studied by using fresh conidia materials. A period of 10 to 44 hours soaking in distilled water, and a suitable nutrient source are required (Dillon & Charnley, 1985). The conidia of entomopathogenic fungi, such as M. anisopliae and B. bassiana, are hydrophobic in nature. When they are suspended in water, the interface between water and the surface of conidia is characterized by the existence of a high surface tension which prevents the conidia from absorbing water necessary for germination. By carefully examining different surface active agents, it might be possible to alleviate this problem. Surface active agents are characterized by a structure in which the molecule is more or less clearly divided into distinct moieties. One moiety is hydrophilic, and the other hydrophobic. The method employed to quantify the hydrophilic-lipophilic nature of a surface active agent is Hydrophile-Lipophile Balance (HLB) method. In this method, an HLB number is assigned to each surface active agent, and is related by the scale to the suitable application surface active agent. The scale is devised so that the more hydrophilic surface active agents have higher HLB number. Although the HLB method for screening surface active agents has been used to chemical pesticide formulation, the application of HLB method in the screening of suitable surface active agents to reactivate microbial propagules after drying and storage is a new area. Moreover, little is known about the effect of O.sub.2 levels on conidia viability when conidia are stored at different temperature-R.H. combinations. Oxygen is important for the germination of fungal spores.
It is therefore an object of the present invention to provide a method and means for increasing the shelf-life of a pathogenic fungus, especially Metarhizium anisopliae, on a nutrient medium.
It is a further object of the present invention to provide improved packaging for insect infection chambers utilizing a pathogenic fungus.
It is another object of the present invention to provide methods for storage to increase the shelf life of conidia of entomopathogenic fungi, at a higher temperature.
It is a further object of the present invention is to develop a suitable method to reactivate the conidia after storage.