An embodiment of the invention relates to a driving circuit for an emitter-switching configuration of transistors having at least one first and one second control terminal connected to the driving circuit to form a controlled emitter-switching device having in turn respective collector, source and gate terminals. Advantageously the driving circuit comprises at least one IGBT device inserted between the collector terminal and a first end of a capacitor, whose second end is connected to the first control terminal, the IGBT device having in turn a third control terminal connected, through a first resistive element, to the gate terminal, as well as a second resistive element inserted between the gate terminal and the second control terminal. Advantageously, the driving circuit further comprises an additional supply inserted between the first and second ends of the capacitor to ensure its correct biasing.

A so called emitter-switching circuit configuration comprises a connection of a bipolar transistor having a high breakdown voltage and a power MOSFET transistor with low voltage.
Such a configuration is schematically shown in FIG. 1 and globally indicated at 1. The emitter-switching configuration 1 comprises a bipolar transistor T1 and a MOS transistor M1 inserted, in series to each other, between a first and a second voltage reference, in particular the supply voltage Vcc and the ground GND.
The emitter-switching configuration 1 provides that the bipolar transistor T1 is of the HV (High Voltage) type, i.e. a transistor having a high breakdown voltage, while the MOS transistor M1 is of the LV (Low Voltage) type, i.e. a transistor having a low breakdown voltage.
The bipolar transistor T1 has a collector terminal connected to the supply voltage reference Vcc through an inductive load L1 and a control or base terminal connected to a driving circuit 2.
The MOS transistor M1 has in turn a control or gate terminal connected to the driving circuit 2.
The driving circuit 2 comprises:                a first resistive element RB connected to the base terminal of the bipolar transistor T1 and, through a Zener diode DZ, to the ground GND;        a second resistive element RG connected to the gate terminal of the MOS transistor M1 and, through a generator of voltage pulses G1, to the ground GND; and        an electrolytic capacitor CB connected, in parallel, to the Zener diode DZ and having, at its ends, a voltage value equal to VB.
In particular, the electrolytic capacitor CB has the task of storing energy during the turn-off of the bipolar transistor T1, to use it again during a successive turn-on and conduction step of the transistor itself, while the Zener diode prevents the value of the base voltage of the bipolar transistor T1 from exceeding a determined threshold.
The set of the emitter-switching configuration 1 and of the driving circuit 2 forms a device of the controlled emitter-switching type 5.
The emitter-switching configuration, known to the skilled person in the field for a long time, is currently particularly interesting due to the presence on the market of bipolar transistors having a squared RBSOA [Reverse Biased Safe Operating Area] (in emitter-switching configuration) at a current next to the peak one and at a voltage equal to the breakdown voltage BVCES [Breakdown Voltage Collector-Emitter Short], the voltage between the collector and emitter terminals when the base terminal is short-circuited with the emitter terminal, as well as of power MOS transistors having a very low drain-source resistance value when conductive [ON condition], RDSON, and therefore almost assimilable to ideal switches.
Advantages of the emitter-switching configuration are a very low voltage drop in conduction (typical of bipolar transistors) and a high turn-off speed.
During the turn-off, in fact, the current outgoing from the base terminal of the bipolar transistor of the emitter-switching configuration is equal to the current of the collector terminal of this transistor, i.e. a current having a very high value. This determines a drastic reduction both of the storage time and of the fall time, allowing the emitter-switching configuration to work also up to frequencies of 150 kHz.
The driving carried out by means of the driving circuit 2 is very useful and efficient in all those cases wherein the current in the emitter-switching configuration 1 is null, or very small with respect to the nominal one, in the turn-on phase.
In order for this driving to be efficient it is, however, often necessary that the value of the base current during the turn-off phase, IBOFF, multiplied by the storage time, tstorage, is next to the value of the base current in the conduction phase, IBON, multiplied by the turn-on time, ton, i.e.:IBOFF*tstorage>>IBON*tON  (1)
The condition (1) usually occurs when working at relatively high frequencies and with not too high currents, or better when the gain value Hfe of the bipolar transistor is not too low.
In fact, in this case, the driving energy necessary for the conduction is only a little higher with respect to the one recovered during the turn-off phase. It is thus enough to supply the base terminal with a very little power for replacing the unavoidable losses.
FIG. 2 shows the pattern of the values of the voltage VGS between gate and source terminals of the MOS transistor M1, of the voltage between the collector terminal of the bipolar transistor T1 and the source terminal of the MOS transistor M1, VCS, and of the base and collector currents of the bipolar transistor T1 with reference to a flyback converter working at a frequency of 100 kHz and having a null turn-on current since the converter works in a discontinuous way.
When working with applications wherein the value of the current on the device at the turn-on is not null, and at relatively high frequencies (>60 kHz), having to deal with a bipolar device, the phenomenon of the dynamic VCESAT is highlighted. This phenomenon is that, at the turn-on, there exists a certain delay before reaching the value of static voltage VCESAT, it is thus necessary to flood by carriers the base region of the bipolar transistor as quickly as possible to make the value of the voltage VCESAT decrease and to reach the steady value as soon as possible.
For this reason, with the driving circuit 2 of FIG. 1, an excessive dissipation at the turn-ON would be obtained due to the fact that the voltage drop VCE would take a relatively long time (≧2 μs) to reach the saturation value.
Always with reference to the controlled emitter-switching device 5 of FIG. 1, an increase of the VB would only partially reduce the problem of the dynamic VCESAT but it would enormously worsen the performances at the turn-off.
The driving circuit suitable for the applications with non-null collector current at the turn-on has been object of the European patent application No. 03425140.5 (which is incorporated by reference) and it is schematically shown in the annexed FIG. 3, globally indicated at 12. The driving circuit 12 is suitably connected to an emitter-switching configuration 1 to form a device of the controlled emitter-switching type 15.
The driving circuit 12 suitably modulates the base current optimizing both the switch steps and allowing the attainment of the minimum value of VCESAT in the shortest time possible. In the annexed FIG. 4, the waveforms are reported which refer to a converter of the forward type working at a frequency of 110 kHz, where the modulation of the base current can be observed.
The detailed operation and the sizing of the driving circuit 12 are widely discussed in the cited patent application.
Although advantageous under several points of view, this known driving circuit has admitted drawbacks mainly highlighted when the need of applications with collector currents of variable value in a wide range is to be faced.
In these applications, the driving circuit 12, as described in the above indicated European patent application, is in fact sized taking into account the most stressing working condition, i.e. the highest collector current.
Thus a correct saturation level should be ensured for the highest current value, by suitably choosing a base voltage value Vb′ of the bipolar transistor T1, but in so doing, for low collector current values, the device works in over-saturation conditions, obtaining extremely long storage times.
This implies an excessive dissipation at the turn-off, as well as inaccurate control due to the fact that the effective turn-off of the device occurs with delay with respect to the signal supplied by a controller.
It is also possible to use more complex solutions comprising additional circuitries for the control of the storage time, tstorage, through a modulation of the base current.
In this case, however, specific designs of the base driving circuit are to be provided. The circuits thus obtained become difficult to be used with high currents values and they may not allow the connection of a recirculation diode between the collector and source terminals in half-bridge and complete bridge configurations.
In fact, the inductive recirculation current of interest in this case flows in a base loop through a supply capacity, discharging it and flowing then in the base-collector junction instead of flowing in the recirculation diode having the anode connected to the source terminal and the cathode to the collector terminal.

Driving circuit for an emitter-switching configuration


Methods and apparatus are provided for use in testing a memory (220, 230, 240) in a multiprocessor computer system (200). The multiprocessor computer system (200) has a plurality of processing nodes (210-217) coupled in an array wherein each processing node is coupled to at least one other processing node, and a memory (220, 230, 240) distributed among the plurality of processing nodes (210-217). A configuration of the array is determined. An initial configuration of the memory (220, 230, 240) is also determined. The memory (220, 230, 240) is tested over the array according to the initial configuration to identify a bad memory element. The initial configuration is modified to form a revised configuration that excludes the bad memory element.

A computer system is generally defined in terms of three basic system elements: a central processing unit (CPU), memory, and input/output (I/O) peripheral devices. A typical computer system works with a computer program known as an operating system (OS). The OS is a program that manages all other programs in a computer, the user interface, the interface with peripheral devices, memory allocation, and so forth. Each OS is written for a variety of system configurations such as variable physical memory size, various numbers of peripherals connected to the system, etc. and thus it can remain ignorant of the actual system configuration.
On the other hand the basic input/output system (BIOS) is a computer program that uses the actual system configuration to manage data flow between the OS and attached memory and I/O peripherals. The BIOS can translate OS requests into concrete actions that the CPU can take in response. The BIOS is usually stored on a nonvolatile memory device such as a read-only memory (ROM) and may be programmed for the particular system configuration.
The BIOS also manages operation of the computer system after startup and before control is passed to the OS. The BIOS typically performs a memory check after power-on to determine whether the memory physically present in the system is operational and can be used by the OS. The BIOS first determines the amount of memory present in the system. It may use a so-called system management (SM) bus to interrogate the memory devices present in the system and thus to determine the nominal size of the memory. Then the BIOS performs a memory test to detect the presence of bad memory elements and to take corrective action if it finds any. Finally it passes control to the OS but thereafter is periodically called by the OS to perform system specific I/O functions.
Recently multiprocessor computer architectures have been introduced for such applications as servers, workstations, personal computers, and the like. In one such multiprocessor architecture the physical memory is distributed among multiple processor nodes, but the BIOS runs on a single processor (known as the boot strap processor), making the memory test significantly more complex. In known multiprocessor systems if any of the memory elements fail the memory test, the boot strap processor reports the failure on a startup screen and halts the power on sequence.
Accordingly, it would be desirable to have a BIOS that efficiently performs a memory test and takes corrective actions to allow the system to continue operating in a multiprocessor, distributed memory environment despite the presence of the bad memory element. These and other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.

Memory check architecture and method for a multiprocessor computer system


The present invention relates to a linear compressor. A discharge unit of the linear compressor according to an aspect of the present invention includes a discharge cover coupled with the frame. In addition, the discharge cover includes a cover flange portion and a chamber portion. At this time, the cover flange portion includes a flange main body having a main body penetration portion and a main body extension portion provided outward in a radial direction so as to face the main body penetration portion, and a flange coupling portion having a flange coupling hole into which a fastening member for coupling with the frame is inserted.

Generally, a compressor is a mechanical device that receives power from a power generating device such as an electric motor or a turbine to increase pressure by compressing air, refrigerant, or various other operating gases and is widely used over the appliances or the industry as a whole.
Such compressors may be broadly classified into reciprocating compressors, rotary compressors, and scroll compressors.
The reciprocating compressor has a compression space in which a working gas is suctioned or discharged between a piston and a cylinder so that the piston linearly reciprocates within the cylinder to compress the refrigerant.
In addition, the rotary compressor has a compression space in which a working gas is suctioned or discharged between a roller and a cylinder which are eccentrically rotated, and the roller compresses the refrigerant while eccentrically rotating along the inner wall of the cylinder.
In addition, the scroll compressor has a compression space in which a working gas is suctioned or discharged between an orbiting scroll and a fixed scroll, and the orbiting scroll rotates along the fixed scroll to compress the refrigerant.
In recent years, a linear compressor has been developed in which the piston is directly connected to a driving motor which reciprocates linearly in the reciprocating compressor, and the compression efficiency can be improved without mechanical loss due to motion switching and is configured with a simple structure.
In the linear compressor, the piston is linearly reciprocated in the cylinder by the linear motor in the closed shell, and is configured to suction and compress the refrigerant, and then discharge the refrigerant.
At this time, the linear motor is configured such that a permanent magnet is positioned between an inner stator and an outer stator, and the permanent magnet is driven to reciprocate linearly by the mutual electromagnetic force between the permanent magnet and the inner (or outer) stator. As the permanent magnet is driven in a state of being connected to the piston, the piston linearly reciprocates within the cylinder, suctions the refrigerant, compresses the refrigerant, and discharges the refrigerant.
In relation to a linear compressor having such a structure, the present applicant has filed the related art document 1.


A distraction screw includes a proximal portion secured to a first vertebra, a distal portion secured to a second vertebra and an intermediate portion. The intermediate portion is coupled to the proximal and distal portions and is positioned in an intervertebral space. The intermediate portion is configured and adapted to enable distraction of the first vertebra relative to the second vertebra.

Bones and bony structures are susceptible to a variety of weaknesses that can affect their ability to provide support and structure. Weaknesses in bony structures may have many causes, including degenerative diseases, tumors, fractures, and dislocations. Advances in medicine and engineering have provided doctors with a plurality of devices and techniques for alleviating or curing these weaknesses. Typically, weaknesses in the spine are corrected by using devises that fuse one or more vertebrae together. There is a need for variations of a new screw that can be used to distract vertebrae and restore as well as maintain disc height while keeping the lumber vertebrae in its natural alignment through a combination of rigid/semi-rigid or pivoting screw segments.


An automotive headlamp includes: a light source; a movable shade configured to be movable between a first position shielding a part of light emitted from the light source and a second position having a different light shielding volume; a motor configured to generate a driving force to move the shade from the first position to the second position; and a stopper for high beam to fix the movable shade, which has been moved from the first position to the second position, at the second position. The motor is configured such that a motor phase is lag when the motor moves the movable shade to the second position by the driving force generated by supplied power and fixes the same, and an electric current is applied to the motor when the movable shade is fixed at the second position.

1. Field of the Invention
The present invention relates to a technology concerning an automotive headlamp, for example, an automotive headlamp capable of switching light distribution patterns.
2. Description of the Related Art
Traditionally, an automotive headlamp, which has a projector type lamp unit projecting and distributing reflected light forward from a reflector by a projection lens, is known (JP 2010-9766 A). This automotive headlamp is capable of switching light distribution patterns by arranging a movable light shielding shade for light distribution control between the reflector and the projection lens. In this automotive headlamp, the light shielding shade is moved by a motor.
The automotive headlamp described above moves the shade until it abuts against a stopper by driving the motor when a high beam light distribution pattern is formed. The automotive headlamp includes a spring to bring back the shade to a low beam light distribution pattern forming position when the motor is not driven.
However, it is necessary for the automotive headlamp described above to continue supplying power to the motor with the shade abutting against the stopper in order to hold the shade at a high beam light distribution pattern forming position. Therefore, it was found that the motor vibrates and an abnormal noise (high frequency noise) is generated when the power is supplied to the motor when the rotation of the motor is stopped. The generated abnormal noise continues until the motor is turned off.


A method for feeding back confirmation information on a physical uplink shared channel, this method includes: an eNodeB carries, in downlink control information, a number value of the downlink sub-frame corresponding to the confirmation information which is fed back by one uplink sub-frame, and transmits data on a plurality of continuous downlink sub-frames after the sub-frame carrying the downlink control information, wherein the number of the downlink sub-frames which transmit the data is equal to an number of the downlink sub-frames corresponding to the confirmation information fed back by the one uplink sub-frame; after the user equipment receives the downlink sub-frame which carries the downlink control information, the data is received from the downlink sub-frame which transmits the data after this downlink sub-frame, and the confirmation information received is fed back to the eNodeB through a physical uplink shared channel through an uplink sub-frame.

FIG. 1 shows the frame structure of the Time Division Duplex ("TDD" for short) mode of a Long Term Evolution ("LTE" for short) system. As shown in FIG. 1, in such a frame structure, one radio frame of 10 ms is divided into two half frames, and each of which is divided into 10 time slots with a length of 0.5 ms, and two adjacent time slots form a sub-frame with a length of 1 ms. One half frame includes 5 sub-frames. For a Normal Cyclic Prefix ("Normal CP" for short), one time slot includes 7 symbols with a length of 66.7 us, wherein the CP length of the first symbol is 5.21 us, and the CP lengths of the other six symbols are 4.69 us; and for an Extended CP, one time slot includes 6 symbols, the CP lengths of all the symbols are 16.67 us. In this frame structure, the configuration of the sub-frames has the following characteristics:
(1) With reference to Table 1, LTE TDD defines 7 kinds of configuration solutions for the number of the uplink/downlink sub-frames in one radio frame in order to reduce the number of configurations for the number of the uplink/downlink sub-frames. All of the sub-frames can be classified into three categories: one category is a downlink sub-frame, another category is a special sub-frame, and the other category is an uplink sub-frame. As in configuration 1, the sub-frames 2, 3, 7 and 8 are used for uplink transmission, the sub-frames 0, 4, 5 and 9 are used for downlink transmission, and meanwhile the sub-frames 1 and 6 are special sub-frames
(2) The special sub-frame includes 3 special time slots, namely, a Downlink Pilot Time Slot ("DwPTS" for short), a Guard Period ("GP" for short) and an Uplink Pilot Time Slot ("UpPTS" for short), wherein the DwPTS is used for downlink, and at least one symbol is used to transmit the Primary-Synchronization Channel ("P-SCH" for short); the GP is a guard time without transmitting any data; and the UpPTS is used for uplink and may be used to transmit signals such as sounding reference signal and the Random Access Channel ("RACH" for short);
(3) The sub-frame immediately before the special sub-frame is fixedly used for the downlink transmission; and the sub-frame immediately after the special sub-frame is fixedly used for the uplink transmission.
TABLE 1DL/ULProportionConversionConfig-PointSub-frame NumberurationPeriod01234567890 5 msDSUUUDSUUU1 5 msDSUUDDSUUD2 5 msDSUDDDSUDD310 msDSUUUDDDDD410 msDSUUDDDDDD510 msDSUDDDDDDD610 msDSUUUDSUUD
Table 1 shows the LTE TDD uplink/downlink proportion configuration, wherein D represents the downlink sub-frame, U represents the uplink sub-frame and S represents the special sub-frame.
TABLE 2DL/ULProportionConversionConfig-PointSub-frame NumberurationPeriod01234567890 5 ms——1—1——1—11——21———21—2——4————4——310 ms——322—————4——44——————5——9———————6——111——11—
Table 2 shows the number of the corresponding downlink sub-frames when the uplink sub-frames feed back the confirmation information.
In the LTE TDD, a UE should feed back, in Physical Uplink Control Channel ("PUCCH" for short) of the uplink sub-frame in sub-frame n+k (k>3), the acknowledgement/negative acknowledgement message (ACK/NACK) of the data in a Physical Downlink Shared Channel ("PDSCH" for short) of the downlink sub-frame n, and may also feed back the confirmation information ACK/NACK in the physical uplink shared channel for transmitting the uplink data in this uplink sub-frame. Wherein the index of the uplink sub-frame PUCCH is implicitly indicated by sending the serial number of the sub-frame of the downlink data and the smallest index of the Control Channel Element ("CCE" for short) where its corresponding Physical Downlink Control Channel ("PDCCH" for short) is located;
Downlink Control Information ("DCI" for short) Format 0 is used to transmit the control information associated with the PUSCH;
In some configurations of the number of the uplink/downlink sub-frames of the LTE TDD, the number of the downlink sub-frames allocated will be greater than the number of the uplink sub-frames allocated, i.e., one uplink sub-frame should feed back the ACK/NACK information of a plurality of PDSCH sub-frames (Table 2 shows the corresponding number of ACK/NACK when the uplink sub-frames feed back the downlink PDSCH in different configurations in Table 1). Since LTE uplink should satisfy the characteristic of single carrier, one problem which is needed to be solved is how to feed back the ACK/NACK information of a plurality of the downlink PDSCH sub-frames in one uplink sub-frame. One method is to transmit the ACK/NACK information of a plurality of the downlink sub-frames together with the uplink data on the Physical Uplink Shared Channel ("PUSCH" for short).
When the above method is used, if the control channel corresponding to the downlink data is not correctly detected, a User Equipment ("UE" for short) will not feed back the ACK/NACK information, i.e., the situation of Discontinuous Transmission ("DTX" for short) occurs, then the confirmation information corresponding to this downlink data cannot be sent on the PUSCH together with the confirmation information corresponding to other downlink data. Since the eNodeB does not know whether a DTX occurs to the sent downlink data, or to which downlink data the DTX occurs, if the downlink data is still regarded as being all received, it is quite easy to mistakenly feed back an ACK as the confirmation information that should be fed back as an NACK (the DTX should be regarded as the NACK), and further possibly, since the amount of the confirmation information fed back is inconsistent, it results in erroneous detection of the confirmation information of other downlink data, then the situation that the downlink sub-frame data is lost occurs, and UE cannot correctly obtain the information transferred by the received data block, thereby a re-transmission processing by a higher layer being required, which increases additional delay.
However, a technical solution which is able to solve the problem of the lost of the downlink data is still not provided currently.

Method for feeding back confirmation information on a physical uplink shared channel


A gas cooker including a cooktop with at least one burner having a burner crown, a support arranged to receive a cooking recipient above the burner, a sensor for detecting the temperature of the cooking recipient placed on the support, and a control unit for controlling the burner on the basis of sensor output values of the sensor, whereas the sensor is provided outside the burner crown a detachable connection, so that the sensor can be removed when cleaning the gas cooker.

Gas cookers of the above mentioned kind are for example known from DE 601 21 548 T2. The gas cooker described in this document comprises a cooktop with four individual gas burners. Each burner is provided with an individual support element, that can be placed on top of the cooktop for supporting a recipient. A temperature sensor is provided for each burner and extends vertically from the cooktop to be in close contact with the recipient. A gas valve is provided individually for each burner to control the gas flow. The temperature sensor and the gas valve are connected to a control unit, which operates the gas valve on the basis of output values of the temperature sensor. Accordingly, the burner is operated differently throughout different steps of a cooking process without changing the gas flow manually. E.g. the control unit can detect the cooking point of the food inside the recepient by detecting that the sensor output values of the temperature sensor indicate a not rising temperature during operation, so that the gas flow through the burner is reduced and the temperature is maintained to avoid overboiling.
Another embodiment shown in DE 601 21 548 T2 shows a cooktop with four individual burners. Each burner has a support which is formed by four support elements, which are arranged around the burner to receive a cooking recipient located above the respective burner. The support elements are formed integral with the cooktop as cylindrical convexities which are protruding to the upper side of the cooktop. One of the support elements is provided with a temperature sensor for detecting the temperature of the cooking recipient placed thereon. The temperature sensor is located at the upper side of the support element to be in close contact with the recipient. A gas valve is provided individually for each burner to control the gas flow. The temperature sensor and the gas valve are connected to a control unit for operating the gas valve on the basis of output values of the temperature sensor. The general function of the gas cooker according to this embodiment is the same as described above.
Another commonly used gas cooker is described in GB 969 096. It comprises a burner and a support, which is located above the burner for supporting the cooking recipient. The support comprises four legs, which are at their one end side connected to a central ring. On their other end side they are provided with a protruding foot so that an upper supporting surface of the support is provided in an elevated position with respect to the surface of a cooktop. One of the legs is provided with a vertical hole. A temperature sensor extends vertically from the cooktop through the hole to be in contact with a recipient placed on the support. The temperature sensor is connected to a thermostatic control, which operates a gas valve on the basis of sensor output values of the temperature sensor.
During the cooking process the cooktop normally becomes soiled, e.g. by splashes of oil or the like. The major drawback of gas cookers of the above mentioned kind is that their cooktops are difficult to clean. Elements protruding from the cooktop like the temperature sensor represent obstacles which slow down and complicate the cleaning process. At the edges between the cooktop and the protruding temperature sensor, dirt can easily be accumulated and is difficult to remove.
Starting from the above mentioned prior art technology it is an object of the present invention to provide a gas cooker having a cooktop which is easy to clean.

ELECTROLUX HOME PRODUCTS CORPORATION N.V.


A method for a power grid configured to supply current to a plurality of elements of a circuit. The method includes representing the power grid as a graph including a plurality of nodes and a plurality of edges, wherein each node of a portion of the plurality of nodes corresponds to an element of the plurality of elements each modeled as a current source, determining a characteristic matrix A of the power grid, wherein transient behavior of the power grid is represented by a set of linear equations of A*v=i, wherein v is a nodal voltage vector representing nodal voltages of at least a portion of the plurality of nodes and i is a current source vector representing currents supplied to at least a portion of the plurality of elements, identifying first and second partitions of the power grid based on a predetermined criterion, identifying first and second current source subvectors of the current source vector according to the first and second partitions of the power grid, identifying a first shell of the first partition based on worst case nodal voltage sensitivity analysis with respect to the first current source subvector, identifying a second shell of the second partition based on worst case nodal voltage sensitivity analysis with respect to the second current source subvector, and generating an analysis result of transient behavior of the power grid by analyzing, concurrently and independently, the first and second shells of the first and second partitions of the power grid, respectively.

In an integrated circuit, commonly referred to as a chip, electrical power is distributed to the components of the chip over a network of conductors on the chip. With the increasing chip design complexity and shrinking feature size, the design and analysis of on-chip power distribution network become an extremely challenging task, which demands both high computational efficiency and accuracy for analysis tools. For analysis purposes, power distribution network (or power grid) is typically represented by a large-scale linear system in which special purpose, time-domain circuit simulation techniques are applied to identify resistive voltage drop (i.e., IR drop), electromigration and noise failures. It is a difficult task to achieve reasonable tradeoff between accuracy and performance in performing simulation of the extremely large size, flat, irregular power grids used in microprocessor designs.


A machine learning system to rank data within sets is disclosed. The system comprises a ranking module that has differentiable parameters. The system further comprises a cost calculation module that uses a cost function that depends on pairs of examples and which describes an output of the ranking module. Methods of using the disclosed system are also provided.

The amount of data available to information seekers has grown astronomically, whether as the result of the proliferation of information sources on the Internet, or as a result of private efforts to organize business information within a company, or any of a variety of other causes. As the amount of available data grows, so does the need to be able to categorize or label that data so that the data may be more efficiently searched. A related problem is the need to rank data that has been identified as responsive to a search query. One approach is to use machine learning systems for this task.
Machine learning systems include such systems as neural networks and machines using kernel-based learning methods, among others. These systems can be used for a variety of data processing or analysis tasks, including, but not limited to, optical pattern and object recognition, control and feedback systems, and text categorization. Other potential uses for machine learning systems include any application that can benefit from data classification.
When a user performs a search for information, that user typically does not simply want a listing of results that simply have some relation to the search query entered by that user but rather wants to be able to quickly access what that user considers to be the best results from within the listing. This is where ranking is important because high rankings indicate to the user that there is a high probability that the information for which the user searched is present in the highest ranked search results.

Machine learning system and method for ranking sets of data using a pairing cost function


The present subject matter relates to systems and methods for determining quality of data. In one implementation, the method comprises identifying at least one column of the data repository based on an importance index associated with the at least one column, wherein the importance index is indicative of the criticality of the data stored in the at least one column; and retrieving at least one data quality analysis rule associated with the at least one column. The method further comprises assigning a rule weightage parameter to each of the at least one data quality analysis rule and a column weightage parameter to each of the identified columns and analyzing the data stored in the identified columns based on the at least one data quality analysis rule. Based in part on the analysis a data quality score, indicative of the quality of data stored in the data repository is computed.

Data quality is an assessment of the suitability of data to serve its purpose in a given context. Data quality generally pertains to various aspects of the data, which are indicative of the suitability of data, such as accuracy, completeness, update status, relevance, consistency of data across various data sources, reliability, appropriate presentation, and accessibility by various stakeholders. Usually data quality measures include standardizing source data fields; ensuring consistency in the data; validating, certifying, and enriching common data elements; and using trusted data sources.
Other conventional techniques of enhancing data quality include analyzing, and identifying improved standardization, validation, and matching processes; comparing data across or within data sources to check consistency of data; ensuring removal of duplicate data; and developing relationships among common entities from different sources, for example by creating foreign key relationships.
However, in spite of measures implemented to ensure data quality, over time certain errors, inconsistency, and inaccuracy may creep into the data. The cause of degradation of data quality may be caused by various data quality problems, such as data entry errors, limited validation of data at the time of entry, system field limitations, mergers and migrations, data repository migrations across various database management systems vendors, inconsistent standards, discrepancies in data format, difference in structure of data repositories, missing data, data fields filled with default values or nulls, spelling errors and data anomalies.
Poor data quality may adversely impact the functioning of the organization. For example the organization having a poor data quality may suffer from losses arising from extra costs to prepare reconciliations, delay or scrapping migration to a new system, failure to bill or collect receivables, inability to deliver orders, failure to meet contracts and so on.


An exercise mitt is provided for a hand or foot, and which is particularly useful in an exercise form such as yoga in which a practitioner maintains a pose or shifts body position while his/her hand or foot is in contact with a support surface. The exercise mitt is specially configured to address the problem of slippage when the practitioner is practicing an exercise form such as yoga, where the practitioner exerts pressure on a support surface in both downward and outward directions as the practitioner is practicing the exercise form. The mitt comprises a sleeve configured to fit snugly about a portion of a human extremity while permitting portions of the human extremity to extend out of the sleeve. The sleeve has inner and outer surface portions with the outer surface portion configured to contact the support surface as the wearer takes predetermined positions relative to the support surface, the outer surface portion being further configured to resist the human extremity from sliding against the support surface, and the inner surface portion being configured to resist relative movement between the human extremity and the sleeve as the wearer applies pressure against the surface and takes predetermined positions relative to the support surface.

The key to success in yoga is the ability to relax in the yoga poses, so that one's muscles are both strengthened and lengthened, even as one relaxes, breathes deeply, and meditates. Sometimes a pose is held for a considerable length of time, up to ten, or even thirty, minutes. What makes this challenging is the difficulty of the various poses, many of which require the student to exert pressure on the floor (though several different body parts) in both downward and outward directions. Slipping, which can result in failure to properly perform the posture, is a concern, and the control that one must exert to avoid slipping can interfere with one's ability to relax while holding the pose. This can, of course, be a particular problem for beginners.
One product that has been designed to address this problem is referred to as a "yoga mat;" a thin flexible pad, usually around two-and-a-half by six feet, with a rubbery, non-slip surface both on the top and the bottom. The student does the poses on top of the mat, which helps to keep him or her from slipping and also provides some padding for the poses in which the student is sitting or lying on the floor. Yoga practitioners now commonly use this type of mat.
Yoga has, in recent years, expanded dramatically in popularity. Yoga studios have cropped up seemingly everywhere and there are dozens of instructional videos on the market. Displays of these videos, along with yoga props (including, of course, the yoga mat) can be found not only in video and exercise stores but also in health food stores, up-scale supermarkets, department stores, and bookstores.
In the applicants' experience, there are some drawbacks to yoga mats. For example, if a yoga practitioner is traveling, and wants to practice yoga, the practitioner may find it necessary to carry the mat. Moreover, if a practitioner wants to practice in a room that is already carpeted, the practitioner may not feel the need or desire to use a mat. Still further, the aesthetic setting for the practitioner may be important, and the practitioner may prefer a setting that does not use a mat. For example, a yoga practitioner may find it important to practice yoga in a setting that includes beautiful woven wool rugs and may prefer to perform the yoga postures directly on those rugs, but the use of mats may detract from the aesthetics of the setting. In such circumstances, if a mat is not used, slippage can still be an issue for the practitioner.


An oligonucleotide library is described that is1 useful for producing an oligonucleotide of preselected sequence comprising a plurality of oligonucleotide members comprising one or more oligonucleotide species and having the compositional formula (X).sub.a (N).sub.b ; wherein X represents a non-degenerate nucleotide base and N represents a degenerate nucleotide base; "a" represents the number of non-degenerate nucleotide positions and is from 3 to 8; "b" represents the number of degenerate nucleotide positions and is from 0 to 4 but not greater that "a"; and wherein each of the oligonucleotide species is capable of forming a hybridization complex with at least one other of the oligonucleotide species in the library such that a single ligation event of the hybridization complex with another hybridization complex derived from the library produces a ligation reaction product comprising greater than 12 contiguous nucleotide base pairs.

Oligonucleotides are widely utilized in molecular biological manipulations including DNA sequencing, cycle sequencing, polymerase chain reactions, in vitro mutagenesis, cloning methodologies involving polylinkers and adapters, synthesis of genes by hybridization and ligation of multiple oligonucleotides, and the like methods. Traditionally, oligonucleotides are prepared by chemical synthesis methods de novo each time they are required. Chemical synthesis of oligonucleotides is time consuming and costly.
One approach to DNA sequencing is called "primer walking" which utilizes known sequence information of a target nucleic acid to be sequenced to design a distal primer which is then used to obtain additional, downstream sequence information. Although primer walking is conceptually appealing, because of its simplicity and the ordered nature of the sequence information obtained, this method can be is expensive and time-consuming because after each sequence is determined, a new, customized primer must be chemically synthesized. Because a single oligonucleotide synthesis requires the preparation of more oligonucleotide than is required for the single sequencing step to be performed, material is wasted resulting in excess cost, and synthesis time slows the sequential sequencing steps.
Recently, Studier proposed a strategy to simplify the preparation of unique oligonucleotides in the form of a library of pre-synthesized oligonucleotides representing every possible nucleotide sequence in the size range of oligonucleotides from 8 to 10 nucleotides in length. Studier, Proc.Natl.Acad.Sci., 86:6917-6921 (1989). However, the library poses technical difficulties insofar as the library must contain from 4.sup.8 (65,536) to 4.sup.10 (1,048,576) members, respectively, which is generally considered to be so large as to be unmanageable. In addition, oligonucleotides of 8mer to 10mer length are less preferred sequencing primers than longer oligonucleotides of 12mer to 18mer length.
Szybalski proposed the use of a library of hexameric oligonucleotides comprising every possible combination of nucleotide bases, representing a library having 46 (4,096) members, as a means to reduce the size of the library. Szybalski, Gene, 90:177-178 (1990). Theoretically, pairs of hexamers from the library were proposed to be capable of being individually ligated while hybridized to a template to form 12 nucleotide (nt), 18-nt, or 24-nt oligonucleotides in length, thereby forming every possible nucleotide sequence from a library having 4,096 members. This same approach has been described in U.S. Pat. No. 5,114,639 to Blocker. This approach requires ligation of the hexamer pairs in the presence of template DNA (i.e., DNA molecule to be sequenced).
Accordingly, there continues to exist a need for preparing oligonucleotides suitable for priming PCR, cycle-sequencing and the like reactions without de novo oligonucleotide synthesis or the above-described problems. The present invention meets that need.

Oligonucleotide libraries useful for producing primers


The present invention is a method for handling an operation system kernel-provided command via a software-based device driver. The method includes receiving the operation system kernel-provided command from an operation system kernel. The method further includes determining if a kernel virtual address is required for responding to the command. The method further includes initiating a Direct Memory Access (DMA) operation for providing data to the operating system kernel in response to the command when a kernel virtual address is not required for responding to the command. The method further includes allocating a device driver buffer with a DMA address and a virtual address when a kernel virtual address is required for responding to the command.

Currently available methods by which software-based device drivers handle operating system kernel-provided commands may not be conducive to allowing said software-based device driver to have a desired level of portability across various operating system environments.
Therefore, it may be desirable to provide a method for operating system kernel-provided commands which addresses the above-referenced shortcomings of currently available methods.

Method for handling small computer system interface (SCSI) commands via a redundant array of inexpensive disks (RAID) device driver


A method for fabricating an edge termination structure includes providing a substrate having a first surface and a second surface and a first conductivity type, forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate, and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The method also includes implanting ions into a first region of the second GaN epitaxial layer to electrically isolate a second region of the second GaN epitaxial layer from a third region of the second GaN epitaxial layer. The method further includes forming an active device coupled to the second region of the second GaN epitaxial layer and forming the edge termination structure coupled to the third region of the second GaN epitaxial layer.

Power electronics are widely used in a variety of applications. Power semiconductor devices are commonly used in circuits to modify the form of electrical energy, for example, from AC to DC, from one voltage level to another, or in some other way. Such devices can operate over a wide range of power levels, from milliwatts in mobile devices to hundreds of megawatts in a high voltage power transmission system. Despite the progress made in power electronics, there is a need in the art for improved electronics systems and methods of operating the same. Vertical power devices, in which the primary current flows from the top surface vertically down through the substrate, are often used in applications that require high voltage and/or current levels.

Method and system for fabricating floating guard rings in GaN materials


A computer comprising a plurality of processors, each of which are configured to perform operations on data during a compute phase for the computer and, following a pre-compiled synchronisation barrier, exchange data with at least one other of the processors during an exchange phase for the computer, wherein of the processors in the computer is indexed and the data exchange operations carried out by each processor in the exchange phase depend upon its index value.

When performing large scale parallel operations, multiple processors are provided within a computer. Such a computer may be a system in which each processor is provided on a single chip. Each of the processors may itself comprise a plurality of processing units. In some cases, each of the processors may be configured to perform the same set of operations on a different set of data. Each of the processors performs its respective calculations during a compute phase, before exchanging results with one or more of the other processors during an exchange phase. A pre-compiled barrier is imposed between a compute phase and an exchange phase. The exchange of results allows synchronisation to be achieved between different processors that each perform different tasks in the context of a larger operation.
One example of the application of a computer comprising multiple processors is found in the context of machine learning algorithms, for example, in the context of deep neural networks. As will be familiar to those skilled in the art of machine intelligence, a machine intelligence algorithm is based around performing iterative updates to a "knowledge model", which can be represented by a graph of multiple interconnected nodes. Each node represents a function of its inputs. Some nodes receive the inputs to the graph and some receive inputs from one or more other nodes, whilst the output of some nodes form the inputs of other nodes, and the output of some nodes provide the output of the graph (and in some cases a given node may even have all of these: inputs to the graph, outputs from the graph and connections to other nodes). Further, the function at each node is parameterized by one or more respective parameters, e.g. weights. During a learning stage the aim is, based on a set of experiential input data, to find values for the various parameters such that the graph as a whole will generate a desired output for a range of possible inputs. Various algorithms for doing this are known in the art, such as a back propagation algorithm based on stochastic gradient descent. Over multiple iterations based on the input data, the parameters are gradually tuned to decrease their errors, and thus the graph converges toward a solution. In a subsequent stage, the learned model can then be used to make predictions of outputs given a specified set of inputs or to make inferences as to inputs (causes) given a specified set of outputs.
Typically, at least some of the processing of each node can be carried out independently of some or all others of the nodes in the graph, and therefore large graphs expose great opportunities for concurrency and/or parallelism. Each processing unit is a computer that can be used to perform processing associated with a different node. In this way, a plurality of processing units may collectively be used to train a single neural network. This is achieved by applying data parallelism in which each processing unit derives updates to weights for each processing unit of a neural network using a different data set. The updates are then synchronised between the processing units during an exchange phase.
Therefore, it may be understood that when exchanging data between the processors of a computer, each of the processors exchanges different fragments of data at different times. Furthermore, each of the processors may be configured to perform different operations, such as storage of data and reduction, with respect to received data that are dependent upon the position of the respective processor in the computer. There is, therefore, a need to ensure that each processor in the computer performs its respective operations at the appropriate time.

Communication in a computer having multiple processors


An apparatus includes an input unit, a microphone, a control unit, and a voice recognition unit. The input unit is configured to receive a first type input and a second type input. The microphone is configured to receive an input sound signal. The control unit is configured to control a display to display feedback according to a type of input. The voice recognition unit is configured to perform recognition processing on the input sound signal.

The present technology relates to an information processing apparatus capable of performing processing corresponding to an input of voice, an information processing method in the information processing apparatus, and a program encoded on a non-transitory computer readable medium.
There is an information processing apparatus capable of detecting and recognizing voice (voice of a user) and performing processing corresponding thereto. For example, Japanese Patent Application Laid-open No. 2010-217754 describes a voice input apparatus that includes an angle sensor measuring an angle of the voice input apparatus and a distance sensor measuring a distance to a user so as to perform on-off control of a voice input section based on the measured angle and distance. This voice input apparatus enters a voice input mode when detecting that the apparatus is near the user's mouth.

Information processing apparatus, information processing method, and computer readable medium


In order to make it possible to determine the erroneous insertion of an information recording medium at a position close to a recording medium insertion port by utilizing a notch portion provided at the information recording medium, the present invention relates to an electronic apparatus comprising a recording medium insertion port for taking in and out a memory stick having a notch portion used to prevent erroneous insertion and provided in one corner, and an erroneous insertion preventive mechanism provided inside the recording medium insertion port so as to prevent the erroneous insertion of the memory stick, and recording and/or reproducing an information signal using the memory stick. The erroneous insertion preventive mechanism is moved outside for the notch portion of the memory stick to allow the insertion of the memory stick, and is engaged for corners other than the notch portion to hamper the insertion of the memory stick.

1. Field of the Invention
The present invention relates to an electronic apparatus such as a digital video camera recorder (or a camera integral type video tape recorder), an electronic still camera and an electronic book player, using an information recording medium such as IC recording medium normally referred to as a memory stick, a FD (floppy disk) in which a magnetic disk is stored or a disk-shaped recording medium in which an optical disk is stored. The present invention particularly relates to an erroneous insertion preventive mechanism for preventing an information recording medium from being erroneously inserted into an apparatus main body.
2. Description of the Related Art
Generally, there have been hitherto known, as electronic apparatus for recording and/or reproducing an information signal using an information recording medium such as a cassette tape or an FD (floppy disk) having a magnetic tape, a magnetic disk or the like stored in a cassette housing, a camera integral type video tape recorder (to be referred to as xe2x80x9ccamera integral type VTRxe2x80x9d hereinafter), and the like. This camera integral type VTR is constituted by providing a color camera and a video tape recorder integrally with each other and roughly consists of a camera block and a VTR block.
The camera block of the camera integral type VTR is comprised of a lens section fetching an image as a light, a photoelectric conversion section for converting an optical image passed through this lens section into an electric signal and a camera circuit section for processing the electric signal. Also, the VTR block is comprised of a mechanical deck section for holding a cassette tape serving as an information recording medium and recording and reading an information signal on/from a magnetic tape, a VTR circuit section for processing the information signal and a frame section for supporting the VTR circuit section and the mechanical deck section. The magnetic tape stored in the cassette tape is pulled out from within the cassette housing by a tape loading mechanism in the mechanical deck section, wound around a rotary drum and moved at a predetermined speed. A magnetic head attached to the rotary drum comes into contact with this magnetic tape while rotation. The information signal is written to the magnetic tape by this magnetic head or read from the magnetic tape.
As for such a camera integral type VTR or other electronic apparatus, a compact and highly reliable IC recording medium normally referred to as xe2x80x9ca memory stickxe2x80x9d has been recently developed and used as an information recording medium. By employing the memory stick as an expansion memory in addition to the cassette tape which is a conventional information recording medium, it has been possible to increase the recording capacity of recordable information. As a result, the recording capacity of a memory is increased by using the memory stick in, for example, a camera integral type VTR, many still images can be recorded with one memory stick and the convenience of the electronic apparatus of this type can thereby improve.
This memory stick has an outline as shown in FIGS. 21A and 21B. Namely, the memory stick 1 has a generally rectangular, thin, flat case main body 2 and a memory of mass storage capacity included in this case main body 2. A notch portion 3 is provided in one of corners at a tip end side in the insertion direction in which the case main body 2 is inserted into the electronic apparatus, so as to prevent the case main body 2 from being erroneously inserted thereinto. This notch portion 3 is formed into a convex circular arc surface and a concave portion 3a opened forward and laterally is provided on one surface of the case main body 2 of this notch portion 3. Also, many connector pins 4 are provided at the tip end side of the case main body 2. These connector pins 4 are exposed to the same surface as that of the concave portion 3a of the case main body 2. When the memory stick 1 is inserted, the connector pins 4 are connected to apparatus main body-side terminals inserted from a forward opening.
The memory stick 1 having such a configuration is detachably installed into an electronic apparatus from a recording medium insertion port 6 provided at the apparatus main body 5. This recording medium insertion port 6 is a space section having a size corresponding to the memory stick 1. A convex portion 6a engageable with the concave portion 3a of the memory stick 1 is provided in one of deepest corners of the insertion port 6. This convex portion 6a is provided on one surface of the recording medium insertion port 6 and configured such that the convex portion 6a is engaged with the concave portion 3a only when the memory stick 1 is inserted into the recording medium insertion port 6 with a correct posture in correct insertion direction.
However, the electronic apparatus according to the above-stated prior art is configured to employ, as means for determining whether the memory stick 1 is inserted in a normal state or a wrong state, the concave portion 3a of the memory stick 1 and the convex portion 6a of the apparatus main body 5. Whether the memory stick 1 is inserted normally or erroneously can be determined according to whether or not the concave portion 3a of the notch portion 3 is engaged with the convex portion 6a of the recording medium insertion port 6. In addition, since the convex portion 6a is provided in the deepest portion of the recording medium insertion port 6, the concave portion 3a does not reach the position of the convex portion 6a until the memory stick 1 is inserted up to the vicinity of the terminal end. Due to this, the electronic apparatus has problems that it is unclear whether the concave portion 3a is fitted into the convex portion 6a unless the memory stick 1 is inserted into the very end and that determination as to erroneous insertion cannot be made until the final stage.
That is to say, the depth of the notch portion 3 of the memory stick 1 (distance from the tip end of the memory stick 1) is restricted by an internal structure such as a memory and the like stored in the case main body 2 and is actually as small as about 7 mm. As a result, the determination as to the erroneous insertion can be made only immediately before the insertion operation of the memory stick 1 (not beyond 7 mm) is completely finished. This causes a user to be slow to recognize that the insertion direction of the memory stick 1 is wrong during the insertion of the memory stick 1.
Furthermore, the difference between the distance by which the memory stick 1 can be inserted into the apparatus main body 5 during erroneous insertion and the position of the memory stick 1 when the stick 1 is inserted correctly and insertion operation is completed is small (7 mm). For this, it is difficult to determine whether the memory stick 1 is inserted correctly or erroneously only from the insertion state of the memory stick 1. Due to this, if a user makes an erroneous determination and inserts the memory stick 1 from the erroneous insertion position by force despite the fact that the stick 1 is erroneously inserted, then there is a fear that the memory stick 1 and/or the apparatus main body 5 are damaged.
The present invention has been made in view of the above-stated conventional problems. The object of the present invention is, therefore, to solve the above-stated problems by making it possible to determine the erroneous insertion of an information recording medium at a position close to an recording medium insertion port while utilizing a notch portion provided in the information recording medium.
To solve the above-stated problems and the like and to attain the above object, an electronic apparatus recited in claim 1 of the present invention is an electronic apparatus for recording and/or reproducing an information signal using an information recording medium, comprising: a recording medium insertion port for taking in and out the information recording medium having a notch portion used to prevent erroneous insertion in one corner of the information recording medium; and an erroneous insertion preventive mechanism provided inside the recording medium insertion port to prevent erroneous insertion of the information recording medium, is characterized in that the erroneous insertion preventive mechanism is configured to be moved outward for the notch portion of the information recording medium to thereby allow the insertion of the information recording medium, and configured to be engaged for corners other than the notch portion of the information recording medium to thereby prevent the insertion of the recording medium.
An electronic apparatus recited in claim 2 of the present invention is characterized in that the erroneous insertion preventive mechanism has an elastic spring member having a stopper portion protruding forward in an insertion direction of the information recording medium and a support member for allowing the stopper member to be elastically deformed and supporting the spring member.
An electronic apparatus recited in claim 3 of the present invention is characterized in that the support member has a fixed portion for supporting one end of the spring member and a support portion formed integrally with the fixed portion, the support member being provided with a guide groove for moving the stopper portion for the notch portion of the information recording medium and for receiving the stopper portion to generate a reaction force for the corners other than the notch portion of the information recording medium.
An electronic apparatus recited in claim 4 of the present invention is characterized in that the support portion has a pair of support pieces formed to stride the inserted information recording medium and provided to overlap with the guide groove, the pair of support pieces supporting both ends of the stopper portion.
According to the electronic apparatus recited in claim 1 of the present invention and configured as stated above, due to the erroneous insertion preventive mechanism provided inside the recording medium insertion port, when the information recording medium is inserted in a correct state (with a correct posture in correct direction), the hotch portion for preventing the erroneous insertion of the information recording medium allows the passage of the medium and the medium is inserted to reach a predetermined position. On the other hand, when the information recording medium is inserted in a wrong state (which is a state other than the correct state), the corners other than the notch portion hamper the passage of the information recording medium and the medium is not inserted to reach the predetermined position.
According to the electronic apparatus recited in claim 2 of the present invention, the stopper portion of the spring member protrudes forward in the insertion direction of the information recording medium and the support member supports this spring member, whereby the stopper portion is guided by the notch portion and moved outside only when the information recording medium is inserted in a correct state to thereby allow the insertion operation of the information recording medium, and the stopper portion is abutted against the corners other than the notch portion when the information recording medium is inserted in a wrong state to thereby hamper the insertion operation of the information recording medium.
According to the electronic apparatus recited in claim 3 of the present invention, the entire body of the spring member is supported by the fixed portion, a guide groove is provided at the support portion continuous to this fixed portion and the stopper portion of the spring member is inserted into the guide groove, whereby when the information recording medium is inserted ih a correct state, the notch portion moves the stopper portion outside along the guide groove to allow the insertion operation of the information recording medium. When the information recording medium is inserted in a wrong state, the stopper portion is engaged by the corners other than the notch portion inside the guide groove to hamper the insertion operation of the information recording medium.
According to the electronic apparatus recited in claim 4 of the present invention, the stopper portion of the spring member is inserted into the guide groove provided at the paired support pieces so that the pieces overlap each other, whereby when the information recording medium is inserted in a wrong state and the corners other than the notch portion are abutted against the stopper portion, the both ends of the stopper portion are supported by the paired support pieces. It is, therefore, possible to resist the excessive insertion force applied from a user and to prevent the damages of the information recording medium and/or the apparatus main body because of forcedly applying the insertion force.

Erroneous insertion prevention mechanism


A comparator is constituted such that a hit signal .phi.hit is high, before hit check is established in each way of an address array, and such that the hit signal goes low, when a mishit has been established. When a clock frequency is relatively high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check in the address array is established. When the hit check has been established, data read from a way in the data array which has hit is immediately outputted onto a data line and an operation in the way which has mishit is stopped. This novel constitution realizes a high-speed cache operation. When the clock frequency is relatively low, only a way in the data array that has hit is activated after completion of the hit check, thereby reducing power consumption at a low-speed operation.

The present invention relates to a cache memory and, more particularly, to a cache memory suitable for use as incorporated in a microprocessor.
The cache memory is smaller than the main memory in storage capacity but faster in access. Therefore, the cache memory is located very close to the central processing unit (CPU) for the purpose of supplying data held in the main memory to the CPU. A variety of problems about the cache memory are discussed in the ACM, Computing Surveys, Vol. 14, No. 3, 1994, pp. 473-530 and "Computer Organization & Design--The Hardware/Software Interface," Morgan Kaufmann Publishers, pp. 454-527, 1994, for example. The main problems of the cache memory are access time and power consumption.
An example of a conventional cache memory of relatively small power consumption is shown in the NIKKEI Electronics, Feb. 14, 1994, pp. 79-92 (this cache memory is hereinafter referred to as the first prior-art technology). FIG. 2 shows a block diagram of the first prior-art technology.
As shown, the cache memory according to the first prior-art technology is a four-way set-associative cache memory. The set-associative memory is provided as follows. Namely, a plurality of areas that can hold data in a size of blocks in the cache memory are divided into a plurality of rows and a plurality of columns. Each of areas in main memory (not shown) that can hold a data block is divided into a plurality of columns corresponding to the above-mentioned plurality of columns. Block storage areas in the same column in main memory are associated with a given block storage area in the cache memory column corresponding to that same column.
To be more specific, as shown in FIG. 2, in the prior-art cache memory, an address array 200 is composed of four memory mats (also called ways) 206 (namely, way 0, way 1, way 2, and way 3), a decoder 205 commonly provided for these ways, and a precharge and equalize circuit 207, a sense amplifier 208, and a comparator 209 provided for each of the ways. Likewise, a data array 201 is composed of four memory mats 218 (namely, way 0, way 1, way 2, and way 3) and an address decoder 217, a precharge and equalize circuit 219, a sense amplifier 220, and an output buffer 221 provided for each of the ways.
The above-mentioned prior-art cache memory operates as follows. First, access to the four ways 206 is started according to a middle address Am entered from a line 204. Addresses registered in the way 0, the way 1, the way 2, and the way 3 are read and are outputted from the sense amplifiers 208 provided for respective ways (these addresses are also referred to as tags). In the comparator 209 provided for each way, an upper address Au entered from a line 210 is compared with the address read from each way. If a match is found, namely if the cache memory has hit, the comparator 209 asserts a corresponding hit line 211, 212, 213 or 214. Conversely, if a mismatch is found, namely if the cache memory has not hit, the comparator 209 leaves the corresponding hit line negated.
Of the four ways of the data array 200, only one way for which the address array 100 has hit, is activated by the corresponding hit line.
Consequently, the above-mentioned prior-art technology is advantageous in power saving. However, the access time of the entire cache memory is a sum of the access time of the address array 200, the time required for the comparison operation in the comparator 209, and the access time of the data array 201, resulting in a relatively large value. This makes it difficult to enhance the operating frequency of the cache memory.
To overcome such a problem, the present inventors considered a method in which the address array is activated at the same time the data array is activated. FIG. 3 shows a block diagram of a four-way set-associative cache memory 3000 that operates in this method (this cache memory is called a reference technology hereinafter). In FIG. 3, the structures of an address array 300 and a data array 301 are generally the same as those of FIG. 2. The difference between the prior-art technology of FIG. 2 and the reference technology of FIG. 3 lies in that, when the address array 300 is activated, the data array 301 is activated at the same time. The data held in an output buffer 321 of one way among the four ways of the data array 301 corresponding to a way in which hit occurred in the address array 300 may only be outputted to a data line 322. In this method, the address array 300 and the data array 301 are accessed simultaneously, so that the access time of the entire cache memory 3000 is approximately equal to the access time of the data array 301. Thus, the access time of the entire cache memory is relatively short. In this method, however, a way in the data array corresponding to a way in which no hit occurred in the address array is also accessed, so that the power consumption of the data array increases significantly. Further, even if the operating frequency of the cache memory is lowered, the data array operates in the same manner as mentioned above, and therefore, the power consumption is not reduced.
The NIKKEI Electronics, Mar. 27, 1995, pp. 1320 introduces a new RISC (Reduced Instruction Set Computer) processor (a second prior-art technology hereinafter) developed by the assignee hereof and others. Especially, page 16 of the same publication describes a technology for suppressing cache power consumption that follows. Namely, SH7708 employed three methods of suppressing cache power consumption. In the first method, only a way in which hit occurred in the address array is driven. This method was also employed in SH7604, but it is impossible to drive the data array after address array hit determination at high-speed operations, because of the limitation of circuit speed in SH7708. Hence, a circuit constitution for dynamically determining a drive timing of a data array was provided and, if hit determination cannot be made in time, all four ways of the data array are driven. The limit of the frequency for selectively driving one way of the data array is about 40 MHz.

Cache memory employing dynamically controlled data array start timing and a microcomputer using the same


The present invention relates to transducers for converting the spatial position of an object into an electrical signal, more specific to a novel position sensor which has advantages of simplicity, long-term stability and durability. According to the invention, a position sensor comprises at least one body of an elastomeric material, mounting means for mounting a first part of the body to a support, and movable means joined to a second part of the body at a distance from the first part, the movable means being movable to stretch a third part of the body located between the mounting means and the movable means. The sensor has opposed first and second surfaces on the third part, a first electrode on the first surface, and a second electrode on the second surface.

Depending on the range of distances involved, various different physical principles are employed for electrically or electronically measuring linear distance to an object. An example is the reflection of radio waves (RADAR) or light from objects at long ranges of a few hundred meters or more. Medium range position measurements down to maybe one meter can be made by reflection of ultrasound from the object, for example. Short-range measurements of distances below one meter employ a wide variety of inductive, capacitive and resistive distance transducers.
In short-range measurement of the position of an object it is typical for the object to carry an element which is part of a transducer arrangement, or to be physically connected with the transducer. For example, a reciprocating machine part may be connected to the slider of a linear potentiometer or carry an inductive coil which forms part of a moving-coil distance transducer.
It is an object of the present invention to provide a novel position sensor which has advantages of simplicity, long-term stability and durability.

Position sensor comprising elastomeric material


In an embodiment, an apparatus includes a source device including a first current limiter and a second current limiter in parallel with each other and a first transformer and a second transformer; a load device includes a third transformer and a fourth transformer in parallel with each other; and an Ethernet cable is electrically coupled between the source device and the load device, the Ethernet cable including first twisted pair lines and second twisted pair lines. A direct current (DC) voltage is provided to the first current limiter and the second current limiter, the first transformer is electrically coupled to an output of the first current limiter, and the second transformer is electrically coupled to an output of the second current limiter. The DC voltage is transmitted to the third transformer and the fourth transformer in parallel with each other via the first twisted pair lines and the second twisted pair lines. The first twisted pair lines and second twisted pair lines are included in an Ethernet cable electrically coupled between the source device and the load device.

Electronic devices including networking devices and/or networking-related devices can communicate with each other using twisted pairs of insulated wire, such as Ethernet cables. Ethernet cables are capable of transmitting power as well as data between devices. Cables for electronics devices supplying power or data are frequently subject to certain building codes and/or regulatory requirements. For instance, low voltage cables with individual circuits carrying more than 100 Watt (W) are subjected to more stringent building codes and/or regulatory requirements than low voltage circuits carrying less than 100 W.
Many building codes require additional restrictions and protections on low voltage circuits carrying more than 100 W of power in order to reduce the risk of fire if a cable is inadvertently shorted to ground. To safely power an electronic device requiring more than 100 W via an Ethernet cable, multiple independent low voltage circuits can be used that each draw less than 100 W. Among other things, these additional circuits require more electrical components, more expensive electrical components, and/or more complex design than for a single 100 W low voltage circuit.

Power distribution over ethernet connection


A differential amplifier with cascade transistors connected in series to switching transistors is disclosed. The base bias of the cascade transistors is set higher than the output LOW level of the cascade transistors by a preset amount of 0.1 to 0.2V, or lower than the input HIGH level of the switching transistors by the preset amount adding to a forward voltage of a junction diode, to provide a discharge current of the base-emitter junction Cbe from the bias control, or from the upstream stage to drive the differential circuit.

1. Field of the Invention
The present application relates to a differential circuit, in particular, a differential amplifier compensating undershoots appearing in outputs thereof.
2. Related Background Art
It has been known in the field that a differential circuit comprised of bipolar junction transistors (hereafter denoted as BJT) usually accompanies with undershoot in falling edges due to stray capacitors of the BJT. When such a differential circuit drives an optical modulator, the undershoot brings degraded optical output.
A Japanese Patent application published as JP-H08-102622A has disclosed a differential amplifier that suppresses undershoots. FIG. 9 shows a circuit diagram of a differential amplifier disclosed therein where a discharged current of the junction capacitor Cbe between the base and emitter of transistors Q1 (Q2) is fed back in collector current of the other transistor Q2 (Q1) through a driving transistor Q5 (Q6). Thus, the discharge current is compensated from flowing in load resistors, and undershoots appearing in the output due to the current flowing in the load resistor are suppressed.
However, an additional transistor Q5(Q6) is necessary in the conventional circuit shown in FIG. 9, which needs to raise the power supply voltage by at least a base-emitter voltage Vbe, which is typically about 0.8 V. Thus, the power consumption of the amplifier increases.


A method includes applying a composition for forming a resist underlayer film to a substrate having a recess in a surface, and baking the composition for forming a resist underlayer film to form a resist underlayer film for filling at least the recess. The composition for forming a resist underlayer film has a copolymer having a structural unit of following formula (1), a cross-linkable compound, a cross-linking catalyst, and a solvent:

For example, formation of a fine resist pattern on a substrate by a photolithography technique including an exposure step using a KrF excimer laser or an ArF excimer laser as a light source has been known in manufacture of a semiconductor element. Light of the KrF excimer laser or ArF excimer laser incident to a resist film before formation of a resist pattern (incident light) is reflected on a surface of the substrate to generate a standing wave in the resist film. This standing wave is known to prevent formation of a resist pattern having a desired shape. For suppression of generation of the standing wave, formation of an anti-reflective coating that absorbs incident light between the resist film and the substrate is also known. When this anti-reflective coating is provided as a lower layer of the resist film, the anti-reflective coating is required to have a higher dry etching rate than that of the resist film.
Patent Document 1 describes a composition for forming a resist underlayer film including a polymer having at least one sulfur atom in a structural unit. When the composition described in Patent Document 1 is used, a resist underlayer film or an anti-reflective coating that have a higher dry etching rate than that of a resist film can be obtained. On the other hand, when a substrate having a recess in a surface is used in manufacture of a semiconductor element, a gap-filling material that allows the recess of the substrate to be filled or a flattened film is required. However, Patent Document 1 does not describe or suggest recess-filling properties.
Patent Document 2 describes a composition for forming a resist underlayer film containing a copolymer having a triazine ring and a sulfur atom in a main chain. When the composition described in Patent Document 2 is used, a resist underlayer film that has a far higher dry etching rate than that of a resist film, functions as an anti-reflective coating during exposure without decreasing the dry etching rate, and allows a hole (diameter: 0.12 μm, depth: 0.4 μm) of a semiconductor substrate to be filled is obtained.

Composition for forming resist underlayer film and method for forming resist pattern using same

Abstract: wherein R1 and R2 are each independently a C1-3 alkylene group or a single bond, Z is an —O— group, a —S— group, or a —S—S— group, and Ar is an arylene group.


A method of reducing color smearing or color artifacts in a low resolution picture that is subjected to chrominance downsampling prior to display on a display device first upsamples the pixels in each row of the picture to double the picture width, then downsamples the chrominance values to produce a compressed data stream for transmission to the display device, and finally decompresses the compressed data stream for display. In order to maintain the aspect ration of the original picture, each doubled row may be repeated prior to transmission to the display device.

Some display standards require the display of data in a compressed format. For example the PictBridge standard from the Camera & Imaging Products Association (CIPA) allows images to be printed directly from digital cameras to a printer without having to connect the camera to a computer. Such printers currently must conform to at least the Exif/JPEG standard so that products from various vendors are compatible with each other. In the test and measurement field, it is often desired to print out the image that appears on an instrument screen, wherein the screen image represents acquired data. Therefore, it is desirable that the output which is to be printed from the instrument be in a format that is acceptable by printers which conform to the PictBridge standard. That is, the image data should be in the Exif/JPEG format, which requires either 4:2:2 or 4:2:0 chrominance downsampling.
When the original data comes from a low resolution source, such as an oscilloscope screen (typically 320×240, a "quarter VGA" display), reconstruction of the data from the lossy compressed format may cause color distortion or smearing, leading to an improper interpretation of the original data. Using JPEG as an example, the data from the low resolution source is in the form of pixels, each pixel having a luminance value (Y) and a pair of chrominance values (U,V). Where all three values are given for each pixel, the format is referred to as being in a 4:4:4 format. However it is often desired to compress these pixels for transmission or storage, and then later decompress them for display. The Exif2.1 JPEG format specifies that either 4:2:2 or 4:2:0 chrominance downsampling be used for storage and transmission of the original JPEG image data. Chrominance downsampling is specified because the human eye is less sensitive to chrominance variations than to luminance variations.
An example of chrominance downsampling is the following conversion of the first four pixels of a display line:
{4:4:4} [Y0U0V0][Y1U1V1][Y2U2V2][Y3U3V3]
{4:2:2} [Y0U0] [Y1V1] [Y2U2] [Y3V3]
When a printer, for example, converts the 4:2:2 bit stream back into viewable pixels having luminance and both chrominance components {4:4:4}, the following pixels are produced:
[Y0U0V1][Y1U0V1][Y2U2V3][Y3U2V3]
As is apparent, the chrominance components of the decompressed pixels are not identical to those of the original pixels, i.e., U0V0≠U0V1 for the first pixel. This discrepancy occurs because neighboring pairs of compressed pixels are used to reconstruct the decompressed pixels. Within each pair of reconstructed pixels [Y0U0V1][Y1U0V1] or [Y2U2V3][Y3U2V3], is actually sharing a chrominance value from its neighboring pixel. That is, first reconstructed pixel (with luminance value Y0) is using the V1 chrominance value copied from its neighbor on the right, while the second reconstructed pixel (with luminance value Y1) is using the U0 chrominance value copied from its neighbor on the left. This reconstructed pattern is repeated for each pair of adjacent pixels.
Referring to FIG. 1a, a low resolution pixel row is shown with original data that has a solid color transition between pixels 2 and 3. In a low resolution rendering, when recreated after JPEG compression and decompression, this may show up as color smearing or color artifacts, as shown in FIG. 1b, since the original pixels have been approximated for the reconstruction due to the lossy nature of the JPEG compression. In particular pixel pairs 2/3 and 12/13, when recreated, show color artifacts along edges of regions of solid color, where the color artifacts may be of a completely different color than in the original pixel colors. Such artifacts occur when the color transition occurs between pixels in a pixel pair.
What is desired is an apparatus and method of formatting the compressed data such that reconstructing the original low resolution picture from a lossy compressed version occurs without chrominance compression induced color smearing or color artifacts.

Apparatus and method of reducing color smearing artifacts in a low resolution picture


A liquid crystal display includes a plurality of pixel electrodes that are formed in a matrix shape and each of which includes at least two parallelogram electrode pieces each having a pair of lengthwise edges and a pair of oblique edges adjacent the lengthwise edges, and a common electrode that faces the pixel electrodes and that has tilt direction determining members. Transverse center lines of the pixel electrodes that are adjacent each other in a row direction alternate, and the tilt direction determining members that correspond to the pixel electrodes that are adjacent to each other in the row direction are connected to each other in the row direction.

(a) Technical Field
The present disclosure relates to a liquid crystal display.
(b) Discussion of the Related Art
Liquid crystal displays (LCDs) are now widely used as flat panel displays in various kinds of electronic devices. A liquid display typically has two display panels on which field generating electrodes such as pixel electrodes and a common electrode are formed, and a liquid crystal (LC) layer that is interposed between the panels. The LCD generates an electric field in the LC layer by applying voltages to the electrodes, and obtains desired images by controlling the strength of the electric field for determining orientations of LC molecules and polarization of light incident on the LC layer to vary the transmittance of light incident on the LC layer.
The liquid crystal display further includes switching elements that are respectively connected to the pixel electrodes, and a plurality of signal lines such as gate lines, data lines, or the like, that control the switching elements to allow a voltage to be applied to the pixel electrodes.
Among these liquid crystal displays, a liquid crystal display of a vertically aligned (VA) mode has been spotlighted because it has a large contrast ratio and a wide reference viewing angle, in which long axes of the liquid crystal molecules are perpendicular to the upper and lower display panels in a state in which an electric field is not applied. In this case, the reference viewing angle refers to a viewing angle at which a contrast ratio is 1:10 or to a luminance inversion limit angle between grays.
As methods of achieving a wide viewing angle in a liquid crystal display of a vertically aligned mode, there are a method of forming a cutout in a field generating electrode, and a method of forming a protrusion above or below the field generating electrode. Since the cutouts and the protrusions determine a tilt direction of the liquid crystal molecules, the tilt direction of the liquid crystal molecules is decentralized by appropriately disposing the cutouts and the protrusions, thereby widening the reference viewing angle.
The cutouts or the protrusions decrease the aperture ratio, however. In order to increase the aperture ratio, a structure having an ultra-high aperture ratio has been suggested for increasing a size of the pixel electrode to its maximum value. In this case, however, since the distance between the pixel electrodes is short, a strong lateral field is generated between the pixel electrodes. Alignment of the liquid crystal molecules is the scattered due to this lateral field and, as a result, texture or light leakage occurs.
Furthermore, liquid crystal displays of a VA mode have poor lateral visibility as compared to a front visibility. For example, in a liquid crystal display of a patterned vertically aligned (PVA) mode, which is provided with the cutouts, images gradually become brighter in a lateral direction. In the worst case, a luminance difference between high grays does not exist and, thus, pictures may be viewed in a state in which they are broken up.
Therefore, exemplary embodiments of the present invention have been made in an effort to provide an electrode arrangement having advantages of reducing loss caused by texture and thus improving an aperture ratio and transmittance.


An internal combustion engine system includes a spark-ignited internal combustion engine powered by a gaseous fuel. The engine system also includes an air intake in air providing communication with the internal combustion engine. Further, the engine system includes an exhaust system in exhaust gas receiving communication with the internal combustion engine. The exhaust system includes a methane oxidation catalyst through which at least a portion of the exhaust gas flows and an exhaust gas recirculation line in exhaust gas providing communication with the air intake.

Emissions regulations for internal combustion engines have become more stringent over recent years. Environmental concerns have motivated the implementation of stricter emission requirements for internal combustion engines throughout much of the world. Governmental agencies, such as the Environmental Protection Agency (EPA) in the United States, carefully monitor the emission quality of engines and set acceptable emission standards, to which all engines must comply. Generally, emission requirements vary according to engine type. Emission tests for spark-ignited gasoline (e.g., non-gaseous) engines typically monitor the release of carbon monoxide, nitrogen oxides (NOx), and unburned hydrocarbons (UHC). Catalytic converters (e.g., oxidation catalysts) implemented in an exhaust gas aftertreatment system have been used to eliminate many of the regulated pollutants present in exhaust gas generated from gasoline powered engines. For example, some known three-way catalysts include carefully selected catalytic material formulations to specifically oxidize carbon monoxide and unburned hydrocarbons, and reduce nitrogen oxides to less harmful components, present in the exhaust gas. Conventional three-way catalysts are designed to oxidize or reduce such pollutants more efficiently for engines running above the stoichiometric air-to-fuel ratio (i.e., rich conditions).
Recently, due at least in part to high crude oil prices, environmental concerns, and future fuel availability, many internal combustion engine designers have looked to at least partially replace crude oil fossil fuels, e.g., gasoline and diesel, with so-called alternative fuels for powering internal combustions engines. Desirably, by replacing or reducing the use of fossil fuels with alternative fuels, the cost of fueling internal combustion engines is decreased, harmful environmental pollutants are decreased, and/or the future availability of fuels is increased. Known alternative fuels include gaseous fuels or fuels with gaseous hydrocarbons, such as, for example, natural gas, petroleum gas (propane), and hydrogen. The combustion byproducts present in exhaust gas generated by spark-ignited gaseous-powered engines are similar to those present in exhaust gas generated by spark-ignited non-gaseous-powered engines. Accordingly, conventional gaseous-powered engine systems utilize the same oxidation catalysts found in non-gaseous-powered engine systems to oxidize the regulated pollutants generated by gaseous-powered engines.
However, gaseous-powered engines also generate exhaust gas with relatively large amounts of presently unregulated pollutants, such as methane. Traditionally, gaseous-powered engines are operated at rich air-to-fuel ratios (e.g., richer than stoichiometric) in order to reduce oxygen concentrations within the exhaust gas, and thus the formation of carbon monoxide and nitrogen oxides. Operating under such rich air-to-fuel ratios consequently generates very high levels of unburned hydrocarbons, such as methane. Conventional gaseous-powered engine systems do not include oxidation catalysts capable of oxidizing methane. Accordingly, gaseous-powered engine systems allow large amounts methane to escape into the atmosphere.
Additionally, operating a gaseous-powered engine under stoichiometric or richer air-to-fuel ratios results in a relatively low brake thermal efficiency of the engine. Moreover, operating at such air-to-fuel ratios causes high combustion temperatures, which result in high component temperatures in the engine, and the necessity to reduce output power to avoid component failure. However, in view of the premium placed on satisfying exhaust emissions regulations, conventional gaseous-powered engines are designed to meet exhaust emissions regulations at the expense of thermal efficiency and power density.
Further, as recognized by the inventors, some internal combustion engine systems that employ exhaust gas recirculation (EGR) strategies often suffer from the formation of harmful condensates within the air and charge air intake line. For example, the presence of certain emissions in the recirculated exhaust (e.g., CO, CO2, NOx, and UHC) can cause the formation of aggressive acids in the condensate within the intake circuit of the engine should charge temperature fall below the dew point at any location within the intake system. CO and CO2 may result in carbonic acid forming in the condensate within the intake system and NOx may result in the formation of nitric acid within the condensate. Of these two acids, nitric acid is more aggressive and has the greater potential to negatively affect the service life of the components of the intake system.

Exhaust system for spark-ignited gaseous fuel internal combustion engine