A non-aqueous electrolyte secondary battery comprises a negative electrode including a negative electrode active material, a positive electrode including a positive electrode active material, and a non-aqueous electrolyte; the positive electrode active material is LiNi1-y-zMnyCozO2, wherein y and z satisfy 0<y≦0.5, 0≦z≦0.5, and 0<y+z≦0.75; and an upper limit voltage for charging the non-aqueous electrolyte secondary battery is 4.25 to 4.70 V.

The present invention relates to a non-aqueous electrolyte secondary battery, and more specifically, to a non-aqueous electrolyte secondary battery using a specific composite oxide of lithium as a positive electrode active material, and a method for charging the battery.
Lithium secondary batteries typical of non-aqueous electrolyte secondary batteries have high electromotive force and high energy density. Because of these features, lithium secondary batteries are now in increasing demand as the main power supply of mobile communication devices and portable electronic devices. Most lithium secondary batteries commercially available at present use as a positive electrode active material LixCoO2 (x represents the lithium content in the active material and changes depending on the charging and discharging of the battery). However, since a cobalt compound used as a raw material is expensive, research and development for other positive electrode active materials is going on to find an alternative to LixCoO2 with a view toward cost reduction. Of these active materials, a composite oxide of lithium LixCoO2 containing nickel as the main component has been studied eagerly and some are already on the market.
Besides cost reduction, lithium secondary batteries are expected to have higher capacity, higher reliability and longer life. To enhance these characteristics, it is possible to improve positive electrode active materials or to set a higher upper limit voltage for charging.
For example, Japanese Unexamined Patent Publication No. 7-320785 discloses a non-aqueous electrolyte secondary battery with a negative electrode containing a carbon material capable of doping and dedoping lithium, a positive electrode containing a composite oxide comprising lithium and a transition metal, and a non-aqueous electrolyte. And, it is proposed to use a graphite material or a carbon material mixture containing graphite as the carbon material, and to use as the above-mentioned composite oxide LixNiyCo1-yO2 (wherein x and y satisfy 0.05≦x≦1.10 and 0.3≦y≦1.0, respectively), and to set an upper limit voltage for charging to 4.1 V or higher. The object of this invention is to provide a non-aqueous electrolyte secondary battery with high energy density and excellent cycle characteristics.
On the other hand, Japanese Unexamined Patent Publication No. 7-335262 discloses a non-aqueous electrolyte secondary battery with a negative electrode containing as a negative electrode active material a carbon material capable of doping and dedoping lithium, a positive electrode containing as a positive electrode active material a composite oxide of lithium and a transition metal, and a non-aqueous electrolyte. And, it is proposed to use a hard carbon material as the negative electrode active material, and to use as the positive electrode active material LixNiyCo1-yO2 (wherein x and y satisfy 0.05≦x≦1.10 and 0.5≦y≦0.95, respectively), and to set an upper limit voltage for charging the non-aqueous electrolyte secondary battery to 4.0 V or higher. The object of this invention is to provide a non-aqueous electrolyte secondary battery with high capacity and excellent storage characteristics.
Furthermore, Japanese Unexamined Patent Publication No. 2001-68168 discloses two conditions about a lithium secondary battery which comprises a negative electrode, a positive electrode, and a lithium salt-containing non-aqueous electrolyte, and which can be charged and discharged for a plural number of times in a reversible manner. As one of the conditions, it is proposed to set the charge end voltage at 4.5 to 4.7 V; to set the average discharge voltage of the positive electrode relative to an Li reference potential at 4.0 to 4.4 V; to set the discharge end voltage of the positive electrode relative to the Li reference potential at 3.2 V or higher; and to set the volume energy density at larger than 430 Wh/l.
As the other condition, it is proposed to set the charge end voltage of the positive electrode relative to the Li reference potential at 4.5 to 4.7 V, and to use a positive electrode active material containing a composite oxide of lithium which satisfies a general formula LiwMvCoxQ1-v-xO2 (wherein M is at least one kind selected from G, Ti, Zr, Y, and Si; Q is at least one kind selected from Ni and Fe; and w, v, and x satisfy 0≦w≦1.2, 0.01≦v≦0.2, and 0.7≦x≦0.95, respectively). The object of this invention is to provide a lithium secondary battery durable to high voltage.
By the way, with the rising of the upper limit voltage for charging, more lithium is deintercalated from a composite oxide of lithium as a positive electrode active material, thereby naturally realizing higher capacity.
On the other hand, however, there are problems of deteriorating the reliability of the battery and decreasing the charge-discharge cycle life of the battery. One cause of deterioration in the battery characteristics is considered that the rising of upper limit voltage for charging causes distortion or fatigue in the composite oxide of lithium from which lithium is deintercalated. Composite oxide of lithium such as LixCoO2 or LixNiO2 reduces in volume crystallographically in the process of a charging reaction during which lithium is deintercalated. In contrast, it increases in volume crystallographically in the process of a discharging reaction during which lithium is intercalated. The rising of the upper limit voltage for charging deintercalates more lithium, thereby causing further reduction in volume. Consequently, repeating charge and discharge at a higher upper limit voltage for charging causes the material to have more distortion and fatigue, thereby remarkably decreasing the charge-discharge cycle life.
As another cause, it is considered that the chemical activation of the material increases. Composite oxide of lithium such as LixCoO2 or LixNiO2, from which a lot of lithium is deintercalated by the rising of upper limit voltage for charging, are put in a highly oxidized state and become excellent in reaction activity. The composite oxide of lithium in this state undesirably reacts with the non-aqueous electrolyte in the battery. Particularly, when the battery is stored at temperatures higher than room temperature, the reaction between the positive electrode active material and the non-aqueous electrolyte deteriorates the battery capacity. In addition, the gas generated by this reaction fills the battery, increasing the internal pressure of the battery and facilitating the deformation of the battery. It is also probable that a safety mechanism provided to prevent battery breakage operates, making it impossible to use the battery. Therefore, in the case where the upper limit voltage for charging is raised to obtain higher capacity, the battery cannot be in the actual use commercially without solving the aforementioned problems.
In view of these aspects, the means proposed in Japanese Unexamined Patent Publication No. 7-320785 cannot offer sufficient reliability of a battery. The inventers of the present invention have found out that the capacity decreases particularly when the battery is stored in a charged condition, and that the recovery rate of the capacity remains low even after several times of charge and discharge. The inventers of the present invention have also found out that the means proposed in Japanese Unexamined Patent Publication No. 7-335262 deteriorates the charge-discharge cycle life. The positive electrode active materials used in these suggestions are composite oxides of lithium, nickel, and cobalt having different composition ratios. When a carbon material mixture containing a graphite material or graphite is used as the negative electrode active material together with either one of the positive electrode active materials, the charge-discharge cycle life is improved, but it is impossible to obtain sufficient storage recovery characteristics. On the other hand, when a hard carbon material is used as the negative electrode active material together with either one of the positive electrode active materials, the storage recovery characteristics are improved, but the charge-discharge cycle life is insufficient. Therefore, it is hard to obtain high reliability and long life at the same time with these positive electrode active materials.
The means proposed in Japanese Unexamined Patent Publication No. 2001-68168 cannot offer sufficient reliability of the battery, either. The inventers of the present invention have found out that the capacity remarkably decreases when it is stored in a charged state. It is also difficult to obtain high reliability and long life at the same time by using the positive electrode active material LiwMvCoxQ1-v-xO2 (wherein M is at least one kind selected from Ge, Ti, Zr, Y, and Si; Q is at least one kind selected from Ni and Fe; and w, v, and x satisfy 0≦w≦1.2, 0.01≦y≦0.2, and 0.7≦x≦0.95, respectively).
Hence, the present invention has an object to provide a non-aqueous electrolyte secondary with high capacity, high reliability, and long life by properly setting the composition of a composite oxide of lithium which is a positive electrode active material and the charging conditions of the battery using this composite oxide of lithium as a positive electrode active material. The present invention has another object to provide a charging method capable of obtaining a non-aqueous electrolyte secondary battery with high reliability and long life in addition to high capacity, when a specific composite oxide of lithium is used as a positive electrode active material.

Non-aqueous electrolyte secondary battery and method for charging the same

Abstract: It is possible to obtain a non-aqueous electrolyte secondary with high capacity, high reliability, and long life by properly setting the composition of a composite oxide of lithium which is a positive electrode active material and the charging conditions of the battery using this composite oxide of lithium as a positive electrode active material as described above.


A motor includes a rotor module and a stator module. The rotor module includes a plurality of first magnet units, a plurality of second magnet units, a hollow magnetic conductance pillar and a rotating shaft. The first and second magnet units are alternately arranged to form a hollow pillar. An outer surface of the hollow pillar includes a plurality of first surfaces and second surfaces of the first and second magnet units. The first and second surfaces have different magnetic poles. The hollow magnetic conductance pillar and the rotating shaft are disposed in and through the hollow pillar and the hollow magnetic conductance pillar, respectively. The stator module includes a shell and a coil unit. The rotor module is disposed in the shell and the rotating shaft is extended out of the shell. The coil unit is disposed on an inner surface of the shell and around the rotor module.

Innovation, research and development for the improvement of motor output power are one of the major concerns since the beginning of the development of motors. Generally, the improvement of the motor output power may be realized by directly increasing the motor specifications. However, a higher motor output power may lead to a heavier motor weight and a larger motor size, and the way for increasing the motor output power directly through the increase of motor specifications may not suitable for some living supplies or industrial equipments. Thus, for those ordinarily skilled in the art, it is an important object to develop a motor with higher power conversion efficiency.


A non-volatile memory module for preventing system failure and a system including the same, in which the non-volatile memory system includes a first socket and a second socket each having a notch coupler, a first memory module, a memory controller configured to control the first memory module, and a printed circuit board on which the memory controller and the first and second sockets are installed and electrical signal lines are formed between the memory controller and the first and second sockets. The first memory includes a plurality of non-volatile memory devices and stores system software. The first memory module has a structure such that it can be installed at the first socket but cannot be installed at the second socket. The non-volatile memory system may further include a second memory module for an extension of the memory capacity. The second memory module has a structure such that it can be installed at the second socket but cannot be installed at the first socket. Accordingly, system failure caused by misusage of a non-volatile memory module can be prevented.

Optical discs and hard disc drives (HDDs) have usually been used as large-capacity storage media. Recently, however, with the development of semiconductor technology, research and development for replacing an HDD with a non-volatile memory module have been performed. More specifically, NAND flash memory is being considered as a memory that can replace an HDD because it has a high degree of integration and has a low cost with respect to its capacity.
When a NAND flash memory module is used in a storage system, the storage system uses a plurality of NAND flash memory modules. At this time, a system maker or provider usually stores system software (S/W), such as an operating system (OS) and critical application programs, that is essential to system operation in one of the plurality of flash memory modules when manufacturing the storage system. The memory modules other than the memory module storing the system S/W are used to extend the memory capacity of the system. Because the form factors of all memory modules are the same, however, it is highly likely for users to erroneously move the memory module that stores the system S/W or to misuse it.
FIG. 1 is a schematic diagram illustrating a conventional NAND flash memory module system 100. The conventional NAND flash memory module system 100 includes a memory controller 110, a plurality of memory modules 121, 122, 123, and 124, and a plurality of sockets 131, 132, 133, and 134. Each of the memory modules 121 through 124 includes a plurality of NAND flash memory chips MC, each of which is connected with the memory controller 110 via a signal line 140 connecting the sockets 131 through 134 with the memory controller 110. There may be more or less memory modules than the four that are shown.
Typically, the form factors of the four memory modules 121 through 124 are the same. The conventional memory modules 121 through 124 usually include one or more notches in order to prevent the user from misinserting a module. These notches are made in the same standard (for example, they have the same size and the same shape) in all of the memory modules 121 through 124. A notch fits with only a corresponding notch coupler and may be referred to as a physical or mechanical key for preventing misinsertion. The sockets 131 through 134 are also all the same. In other words, the sockets 131 through 134 have the same form factors and have the notch couplers following the same standard.
Users can purchase and use additional NAND flash memory modules in order to extend the memory storage capacity. In this case, there is a possibility that a memory module is not inserted into a proper socket since the form factors of all sockets are the same. In addition, no alarm or warning is given when a user removes a memory module storing the system S/W from the proper socket in the conventional technology and, therefore, the memory module storing the system S/W may be lost or inserted into a wrong socket.
In addition, according to the conventional technology, a separate NOR flash memory for storing a boot code or a boot loader for system booting is installed on a system mother board or a NAND flash memory storing the boot code is used as a memory array for a memory module, which makes the system mother board complex and increases manufacturing cost.

Non-volatile memory module for preventing system failure and system including the same


A programmable gain attenuator (PGA) in particular to be used in a track-and-hold circuit is disclosed. The PGA is located in the feedback path around an operational amplifier. One tap switch is used to connect one PGA section to the output of the operational amplifier. The PGA section is capable of producing a multiplicity of different gain settings by using a multiplicity of secondary resistive devices in a voltage divider, wherein the resistive devices each can be independently coupled to a reference voltage.

The invention pertains to the general field of track-and-hold amplifiers. In particular this invention pertains to the development of programmable gain attenuators, so called PGAs, for track and hold amplifiers.
The general purpose of track-and-hold amplifiers is to accurately track an analog input signal and, at specified times, to accurately hold at its output for a certain length of time the instantaneous value of the input signal. This form of signal conditioning is particularly important ahead of analog-to-digital converters, where the quality of conversion is improved by maintaining a substantially constant value at the input of the analog-to-digital converter during the conversion process.
Programmable gain attenuators are used in various analog signal-processing applications where an electrical signal of varying amplitude must be either amplified or attenuated before subsequent signal processing. Various gain and/or attenuation settings are required to accommodate the wide dynamic range of the electrical signal.
Programmable gain attenuators for track-and-hold amplifiers are known from the state of the art. However as circuits become faster and faster there is a need for providing an improved PGA that can be used in these high frequency circuits.

Programmable gain attenuator for track and hold amplifiers


Methods and apparatus for protecting trace data of a remote debug session for a computing system. In one embodiment, a method includes storing trace data received from one or more trace interfaces to a storage location of a target device, where the trace data is generated from execution at the target device, and where the trace data is protected from an unauthorized access. The method continues with transmitting the trace data to a debug host computer with encryption through a communication channel between the target device and the debug host computer.

A rapid and efficient response to customer-reported issues in computer products is important in maintaining customer satisfaction and minimizing time-to-market. As customers integrate silicon from a computer chip/processor manufacturer in their products, they often encounter issues that are beyond their capacity to resolve without direct debug support from the computer chip/processor manufacturer. Hangs, data corruption, and power-management issues are among the many failure scenarios that typically require analysis using restricted debug features that are protected by locking mechanisms for the exclusive use by the computer chip/processor manufacturer, and these restricted debug features cannot be released externally due to the risk of compromising product security or the intellectual property (IP) rights of the computer chip/processor manufacturer.
When a customer debug scenario requires this level of analysis, it is commonly necessary to transfer systems/computer products to the computer chip/processor manufacturer, or for employees of the computer chip/processor manufacturer to conduct on-site debugging. These approaches are time consuming and inefficient, and remote debugging is often preferable, where the debugging is performed via a communication channel from a site of the computer chip/processor manufacturer to a customer site where the debug target device is operating.
Yet to debug remotely, a secured communication channel needs to be established between the customer site and the debug site of the computer chip/processor manufacturer. Tracing features record the activity of a computing system or component, in part or in whole, over a period of time, and are commonly used in debug and analytical operations. The data collected from the recording is called trace data. Presently no complete security solution exists for the application of tracing features in an off-site customer support application via network-based remote control.

Method and apparatus for protecting trace data of a remote debug session


A booster circuit includes first and second transistors, a first capacitor, a first drive circuit, a second capacitor, a first controller, and a second controller. The first and second transistors are connected in series between a first voltage and a second voltage. One end of the first capacitor is connected to a connection node between the first transistor and the second transistor. The first drive circuit boosts the voltage at the other end of the first capacitor. The second capacitor is connected between the second voltage and a reference voltage. The first controller controls conduction/non-conduction of the first transistor. The second controller inputs any of the first voltage and the second voltage to the second transistor, and thereby controls conduction/non-conduction of the second transistor. The boost circuit is supplied with the reference voltage, a supply voltage, and a boost clock signal, and generates the second voltage by boosting the supply voltage.

1. Field of the Invention
The present invention relates to a booster circuit and a semiconductor integrated circuit device incorporating the booster circuit.
2. Description of Related Art
Along with the recent trend of using low-voltage power, voltage necessary for drive is now often generated by booster circuits. For example, what is sometimes used in a power circuit of a TFT (Thin Film Transistor) driver IC (Integrated Circuit) that drives liquid crystal displays is a booster circuit of a charge pump type using a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). A supply voltage inputted into this booster circuit varies in magnitude depending on a configuration of an electrical power system that supplies a supply voltage to the driver IC. Therefore, different input power voltages may be supplied to the same driver IC. For this reason, a technique has been desired by which a substrate area of the booster circuit is reduced, while achieving efficient boosting and outputting of a wide range of the input power voltages.
Such a booster circuit has been disclosed in Japanese Patent Application Laid Open No. 2005-304126, for example. FIG. 1 shows a configuration of a booster circuit 90 of such a booster circuit. The booster circuit 90 includes P channel MOS transistors P911 to P914, capacitors C1 to C4, P channel MOS transistors P921 and P923, N channel MOS transistors N921 and N923, and gate controllers 500, 600, 700, and 800.
The transistors P911 to P914 are connected in series between a supply voltage VDC1 and a boost voltage VDC3 to perform switching of a charge pump. The capacitors C1 to C4 are respectively connected to these transistors to maintain charge of the charge pump. The capacitor C1 is connected between a connection node of the transistors P911 and P912 and an output node of an inverter 921. The capacitor C2 is connected between a connection node of the transistors P912 and P913 and a voltage VSS. The capacitor C3 is connected between a connection node of the transistors P913 and P914 and an output node of an inverter 923. The capacitor C4 is connected between the supply voltage VDC3 and the supply voltage VSS.
The transistor P921 and the transistor N921 form the inverter 921. The transistor P923 and the transistor N923 form the inverter 923. The gate controllers 500, 600, 700, and 800 supply gate voltages VG1 to VG4 to the transistors P911 to P914, respectively.
The gate controller 500 includes inverters 521 to 523 and a level shifter 531. The gate controller 500 receives input of a boost clock signal VIN2, and applies the gate voltage VG1 to the transistor P911. The gate controller 600 includes inverters 621 to 623 and a level shifter 631. The gate controller 600 receives input of a boost clock signal VIN1, and applies the gate voltage VG2 to the transistor P912. The gate controller 700 includes inverters 721 to 723 and a level shifter 731. The gate controller 700 receives input of the boost clock signal VIN2, and applies the gate voltage VG3 to the transistor P913. The gate controller 800 includes inverters 821 to 823 and a level shifter 831. The gate controller 800 receives input of the boost clock signal VIN1, and applies the gate voltage VG4 to the transistor P914.
The boost clock signals VIN1 and VIN2 are signals whose high-level voltage is the supply voltage VDC1 and whose low-level voltage is the supply voltage VSS. The level shifters 531 and 631 each level-shift the high-level voltage of a corresponding one of these boost clock signals VIN1 and VIN2 from the voltage VDC1 to the voltage VDC2. Moreover, the level shifters 731 and 831 each level-shift the high-level voltage of a corresponding one of the boost clock signals VIN1 and VIN2 from the voltage VDC1 to the voltage VDC3.
The transistors P911 and P912, the inverter 921, and the capacitors C1 and C2 form first boost means, and the transistors P913 and P914, the inverter 923, and the capacitors C3 and C4 form second boost means. This booster circuit 90 performs charge pump operation when supplied with the boost clock signals VIN1 and VIN2. The first boost means boosts the supply voltage VDC1 to generate the supply voltage VDC2, and further, the second boost means boosts the supply voltage VDC2 to generate the supply voltage VDC3.
Here, for simplification of description, the supply voltage VSS as a reference voltage is as assumed to be 0 volt (grounding potential), and the supply voltage VDC1 is assumed to be V volts (for example, 2.8 volts). Moreover, description will be given assuming that the booster circuit 90 ideally operates, and that the supply voltage VDC2 is a voltage having been boosted to 2V volts (for example, 5.6 volts), and the supply voltage VDC3 is a voltage having been boosted to 3V volts (for example, 8.4 volts). Moreover, the transistors include a transistor having a breakdown voltage of approximately V (for example, 3 volts), a transistor having a breakdown voltage of approximately 2V (for example, 6 volts), and a transistor having a breakdown voltage of approximately 3V (for example, 9 volts), and these transistors will be referred to as a low breakdown voltage transistor, a middle breakdown voltage transistor, and a high breakdown voltage transistor, respectively.
FIG. 2 shows a configuration example of the level shifters 531, 631, 731, and 831 (generically referred to as n31). The level shifter n31 includes P channel MOS transistors P31 and P32, and N channel MOS transistors N31 and N32. Clock signals VINP and VINN are inputted into the gate of the N channel MOS transistor N31 and the gate of the N channel MOS transistor N32, respectively. The clock signal VINN is an inverted signal of the clock signal VINP.
The transistor P31 and the transistor N31 are connected in series between the supply voltage VDD and the supply voltage VSS. A connection node between the drains of the transistor P31 and the transistor N31 is connected to the gate of the transistor P32. The transistor P32 and the transistor N32 are connected in series between the supply voltage VDD and the supply voltage VSS. A connection node between the drains of the transistor P32 and the transistor N32 is connected to the gate of the transistor P31. An output signal VLSO whose high-level voltage is level-shifted to the voltage VDD is taken out from this node.
In the case of the level shifters 531 and 631, the voltage VDC2 (2V volts) is supplied as the supply voltage VDD. Therefore, in the level shifters 531 and 631, a voltage of 2V volts is applied between the gate and source or between the gate and drain of each transistor. The breakdown voltage of the low breakdown voltage transistor is inadequate when the breakdown voltage between the gate and source is approximately V volts. In other words, the middle breakdown voltage transistor having a breakdown voltage between the gate and source of approximately 2V volts needs to be used for each transistor of the level shifters 531 and 631.
In addition, in the case of the level shifters 731 and 831, the voltage VDC3, which is 3V volts, is supplied as the supply voltage VDD. Therefore, in the level shifters 731 and 831, a voltage of 3V volts is applied between the gate and source or between the gate and drain of each transistor. The breakdown voltage of the middle breakdown voltage transistor is inadequate when the breakdown voltage between the gate and source is approximately 2V volts. In other words, the high breakdown voltage transistor having a breakdown voltage between the gate and source of approximately 3V volts needs to be used for each transistor of the level shifters 731 and 831.
FIG. 3 shows a configuration of the inverters 521 to 523, 621 to 623, 721 to 723, and 821 to 823. Each inverter has a P channel MOS transistor P20 and an N channel MOS transistor N20 connected in series between supply voltages VDD1 and VDD0. An input signal INPUT is applied to the gate of the transistor P20 and the gate of the transistor N20, and an output signal OUTPUT is taken out from a connection node between the drains of the transistor P20 and the transistor N20. In the case of the inverters 521, 621, 721, and 821, the voltage VDC1 is supplied as the supply voltage VDD1, and the voltage VSS is supplied as the supply voltage VDD0. In the case of the inverters 522 to 523, 622 and 623, the voltage VDC2 is supplied as the supply voltage VDD1, and the voltage VSS is supplied as the supply voltage VDD0. In the case of the inverters 722, 723, 822, and 823, the voltage VDC3 is supplied as the supply voltage VDD1, and the voltage VDC1 is supplied as the supply voltage VDD0.
The inverters 521, 621, 721, and 821 are each supplied with the supply voltage VDC1 and the supply voltage VSS, and perform inversion operation to invert the clock signals VIN1 and VIN2. Therefore, the low breakdown voltage transistor can be used for the inverters 521, 621, 721, and 821. Moreover, the inverters 522, 523, 622, and 623 are each supplied with the supply voltage VDC2 and the supply voltage VSS, and function as an output buffer of the level shifters 531 and 631. Therefore, the middle breakdown voltage transistor needs to be used for the inverters 522, 523, 622, and 623. Further, the inverters 722, 723, 822, and 823 are each supplied with the supply voltage VDC3 and the supply voltage VDC1 and operate. The inverters 722 and 822 receive input of a signal, which changes between the supply voltage VDC3 and the supply voltage VSS, from the level shifters 731 and 831, respectively. The inverters 722 and 822 level-shift the low-level voltage of this input signal from the supply voltage VSS to the supply voltage VDC1. A voltage between the gate and source or between the gate and drain of the transistors included in the inverters 722 and 822 is 3V volts (for example, 8.4 volts). Therefore, the breakdown voltage of the middle breakdown voltage transistor is inadequate, and thus the high breakdown voltage transistor needs to be used. Moreover, the inverters 723 and 823 invert the signals which are outputted from the inverters 722 and 822, respectively, and which change between the voltage VDC1 and VDC3.
Next, operation of the booster circuit 90 will be described. Charge and discharge of the capacitors C1 and C3 are repeated by the switching operation of the transistors P911 to P914 and by the clock signal inversion operation of the inverters 921 and 923. Charge thereby moves to the capacitors C2 and C4, and the charge pump operation is performed. Specifically, the capacitor C1 is charged through the transistor P911, and the charge of the capacitor C1 moves to the capacitor C2 through the transistor P912, thereby to charge the capacitor C2. The voltage VDC2 of the capacitor C2 gradually rises, and reaches a voltage approximately twice (2V volts) the supply voltage VDC1 in the steady state. Moreover, the capacitor C3 is charged through the transistor P913, and the charge of the capacitor C3 moves to the capacitor C4 through the transistor P914, thereby to charge the capacitor C4. The voltage VDC3 of the capacitor C4 gradually rises, and reaches a voltage approximately three times (3V volts) the supply voltage VDC1 in the steady state.
FIGS. 4A to 4H show waveforms indicating voltage change of each part of the booster circuit 90 after reaching the steady state. The boost clock signals VIN1 (FIG. 4A) and VIN2 (FIG. 4B) are signals each having a phase opposite to the other. The high-level voltage is V volts and the low-level voltage is 0 volt.
The level shifters 531 and 631 level-shift the high level of the boost clock signals VIN2 and VIN1, respectively, so that signals whose high-level voltage is 2V volts and low-level voltage is 0 volt are obtained. These signals are each supplied as a gate voltage VG1 (FIG. 4F) of the transistor P911 and as a gate voltage VG2 (FIG. 4E) of the transistor P912. The transistors P911 and P912 are turned off when the gate voltage is at the high level, and turned on when the gate voltage is at the low level. Thereby, as shown in FIG. 4H, a voltage VP1 at one end of the capacitor C1 changes between 2V volts and V volts, and a voltage VM1 at the other end of the capacitor C1 changes between V volts and 0 volt.
The level shifters 731 and 831 level-shift the high level of the boost clock signals VIN2 and VIN1, respectively, to make the high-level voltage 3V volts. Moreover, each of the inverters 722 and 822 further level-shifts the low-level voltage of the thus-level-shifted signal to V volts. Thus, a gate voltage VG3 (FIG. 4D) applied to the gate of the transistor P913 and a gate voltage VG4 (FIG. 4C) applied to the gate of the transistor P914 are obtained. The transistors P913 and P914 are turned off when the gate voltage is at the high level, and turned on when the gate voltage is at the low level. Thereby, as shown in FIG. 4G, a voltage VP3 at one end of the capacitor C3 changes between 3V volts and 2V volts, and a voltage VM3 at the other end of the capacitor C3 changes between V volts and 0 volt.
Here, while the gate voltage VG3 of the transistor P913 and the gate voltage VG4 of the transistor P914 become 3V volts at the maximum, the minimum voltage becomes not 0 volt, but the voltage VDC1, i.e., V volts. A source voltage or drain voltage of the transistors P913 and P914 is 2V volts to 3V volts.
FIGS. 5A to 5F show voltage between nodes in each transistor. As shown in FIG. 5A, a voltage between the gate and source (drain) (VG2-VDC2, VG4-VDC3) of each of the transistors P912 and P914 changes between 0 volt and −2V volts. Moreover, as shown in FIG. 5B, a voltage between the gate and drain (source) (VG2-VP1, VG4-VP3) of each of the transistors P912 and P914 changes between V volts and −2V volts. Further, as shown in FIG. 5C, a voltage between the source and drain of each of the transistors P912 and P914 (VDC2-VP1, VDC3-VP3) changes between V volts and 0 volt.
Moreover, as shown in FIG. 5D, a voltage between the gate and source (drain) (VG1-VP1, VG3-VP3) of each of the transistors P911 and P913 changes between V volts and −2V volts. As shown in FIG. 5E, a voltage between the gate and drain (source) (VG1-VDC1, VG3-VDC2) of each of the transistors P911 and P913 changes between V volts and −V volts. Further, as shown in FIG. 5F, a voltage between the source and drain of each of the transistors P911 and P913 (VP1-VDC1, VP3-VDC2) changes between V volts and 0 volt.

Charge pump-type voltage booster circuit and semiconductor integrated circuit device


A color palette is provided having a plurality input terminals for receiving a plurality of bits of data having an order. A two color path is included which comprises first circuitry coupled to the input terminals for selectively reversing the order of the plurality of bits of data. Second circuitry is coupled to the first circuitry and is operable in a first mode to pass all of the plurality of bits of data received from the first circuitry and in a second mode has at least one word comprising selected ones of the plurality of bits, the selected ones of the bits having a bit order. The third circuitry is provided coupled to the second circuitry and operable to pass all of the bits of data received from the second circuitry in the first mode and operable to selectively reverse the ordering of the selected ones of the bits and pass be at least one word received from the second circuitry in the second mode. The fourth circuitry is further provided coupled to the third circuitry inoperable to receive bits of data passed from the circuitry and select for output as at least one word of true color data at least some of the bits.

Without limiting the general scope of the invention, its background is described in connection with computer graphics, as an example only.
In computer graphics systems, the low cost of dynamic random access memories (DRAM) has made it economical to provide a bit map or pixel map system memory. In such a bit map or pixel map memory, a color code is stored in a memory location corresponding to each pixel to be displayed. A video system is provided which recalls the color codes for each pixel and generates a raster scan video signal corresponding to the recalled color codes. Thus, the data stored in the memory determine the display by determining the color generated for each pixel (picture element) of the display.
The requirement for a natural looking display and the minimization of required memory are conflicting. In order to have a natural looking display, it is necessary to have a large number of available colors. This, in turn, necessitates a large number of bits for each pixel in order to specify the particular color desired from among a large number of possibilities. The provision of a large number of bits per pixel, however, requires a large amount of memory for storage. Since a number of bits must be provided for each pixel in the display, even a modest size display would therefore require a large memory. Thus, it is advantageous to provide some method to reduce the amount of memory needed to store the display while retaining the capability of choosing among a large number of colors.
The provision of a circuit called a color palette enables a compromise between these conflicting requirements. The color palette stores color data words which specify colors to be displayed in a form that is ready for digital-to-analog conversion directly from the color palette. Corresponding color codes having a limited number of bits are stored in the memory for each pixel have a limited number of bits, thereby reducing the memory requirements. The color codes are employed to select one of a number of color registers or palette locations. Thus, the color codes do not themselves define colors, but instead, identify preselected palette locations. These color registers or palette locations each store color data words which are longer than the color codes in the pixel map memory. The number of such color registers or palette locations provided in the color palette is equal to the number of selections provided by the color codes. For example, a 4-bit color code can be used to select sixteen palette locations. Significantly, the color data words can be redefined in the palette from frame to frame to provide many more colors in an ongoing sequence of frames than are present in any one frame. Significantly, the ability to redefine the color data words in the palette allow for the customization of colors on the display from one application to another.
Graphics processing systems may operate in either the Big Endian or Little Endian data formats. The Big Endian and Little Endian formats determine how data are interpreted as a function of the ordering of the words or bits making up a selected data structure. For example, the graphics processor may output a 32-bit word representing either one 32-bit, two 16-bit, four 8-bit, eight 4-bit, sixteen 2-bit or thirty-two 1-bit color code words (each color code word representing one pixel) to the color palette. Each color code word is normally assigned a designator, and for multiple bit color code words, each bit in a word is assigned a designator. Thus, if a 32-bit word from the frame buffer represents four 8-bit color code words to the palette, the 8-bit words may be designated B0-B3 and the corresponding eight bits in each word designated D0-D7. In the Little Endian format, the bit or word with the lowest designator represents the least significant bit or word in the data structure. In this example, bit DO would represent the least significant bit in each 8-bit word and word B0 would represent the least significant color code word in the 32-bit word output from the frame buffer. In the Big Endian format, the bit or word with the lowest designator represents the most significant bit or word in the data structure. In this example, bit DO would represent the most significant bit in each 8-bit word and word B0 would represent the most significant color code word in the 32-bit word received from the frame buffer.
Since the bit and word ordering of the Big and Little Endian formats are essentially mirror images of each other, it is critical that both the graphics processor and the color palette operate in the same format when multiple bit words of pixel data are being output from the system frame buffer to the color palette. Specifically, the mapping of bits from memory to the display screen is performed in terms of the ordering of color code words received from the frame buffer. Further, in the normal operating mode the ordering of the bits in each color code word is critical to providing the proper address to the color palette look-up table. A color palette not operating in the same format as the processor will misinterpret the data from the frame buffer resulting in improper mapping to the display screen and/or improper addressing to the palette look-up table. It should be noted that these Big/Little Endian mode compatibility problems will normally not arise when pixel data is being transferred in only one pixel size (i.e. only in a preselected one of 1, 2, 4, 8, 16 or 32-bits for example). In this situation, the system and the associated palette can be appropriately wired to obtain compatibility, an approach which will not necessarily work when two or more pixel sizes are being supported by the same system.
In currently available color palettes that support more than one pixel size, only one format, Big or Little Endian is typically selected for a particular palette design which limits the possible uses of that particular color palette to those compatible systems using the same format. Thus, two different color palette designs are now normally required to provide color palettes operable in systems using the two different formats. Simply put, the ability to insert a currently available color palette into any system, no matter which format, Big or Little Endian, is lacking.
Due to the advantages of color palette devices, systems and methods, any improvement in their implementation is advantageous in computer graphics technology. Specifically, color palette devices, systems and methods operable in both those systems using the Little Endian format and those systems using the Big Endian would be particularly advantageous. Of particular advantage is the ability to build, test and sell a single color palette device operable in systems using either the Big Endian or Little Endian format in place of two separate color palettes, one for use in Big Endian systems and one for use in Little Endian systems.

Color palette device having big/little endian interfacing, systems and methods


A balloon catheter with improved balloon orientation includes a head, a catheter segment extending from the head, and a balloon disposed on the catheter segment opposite the head. Preferably, the balloon is attached to the exterior of the catheter segment at a proximal location and to the interior of the catheter segment at a distal location to thereby form a balloon which extends distally from the distal end of the catheter segment when inflated. The improved orientation of the balloon helps to prevent contact between the distal end of the catheter segment and anatomical structures of the user, thereby reducing irritation.

1. Field of the Invention
The present invention relates generally to balloon catheters which are used for catheterizing a body cavity. More specifically, the present invention relates to a balloon catheter with an improved balloon orientation wherein the balloon is configured to decrease irritation caused by the catheter while the catheter remains in the body cavity.
2. State of the Art
There are numerous situations in which a body cavity must be catheterized to achieve some desired medical goal. Most frequently, catheterization is performed either to insert substances into or to remove substances from the body. During many of these procedures, it is necessary to keep the catheter in a relatively stable position to perform the desired insertion or removal. With the use of enteral feeding catheters (i.e. catheters which enable the administration of nutritional solutions directly into the stomach or intestines), for example, it is necessary to ensure that the catheter is not accidentally removed from the stomach or intestines. This is true both during the actual administration or removal of fluids, and the time periods in between feedings.
In order to ensure that a catheter is maintained in the proper position, it is common to use a balloon disposed near the distal (patient) end of the catheter shaft. Inflating the balloon causes the balloon to contact the anatomical structure (i.e. a duct or stomach wall) and thereby prevents the catheter from moving out of the proper position. In the case of enteral feeding, a stoma is formed leading into the stomach or intestine. A catheter is positioned to extend through the stoma, so as to form a channel into the stomach or intestines through which enteral feeding solutions may be pumped.
FIG. 1 shows a side view of a balloon catheter, generally indicated at 10, made in accordance with the prior art. The balloon catheter 10, has a head 14 disposed at a proximal end. The head 14 contains valves which regulate the flow of fluids through the balloon catheter 10. The head 14 also prevents the balloon catheter 10 from completely advancing through the stoma and into the stomach or intestine of the user.
To prevent the catheter from being pulled out of the stomach/intestinal wall, a balloon 18 is disposed along a catheter segment 22. The catheter segment 22 includes an elongate catheter shaft 26 and a stiff tip 30 which is attached to the catheter shaft at a distal end opposite the head 14. The catheter shaft 26 is typically made of a medical grade silicone. The stiff tip 30 is also typically formed of a medical grade silicone, but is usually configured to be more rigid than the catheter shaft. The stiff tip 30 assists the physician, etc., in inserting the catheter segment 22 through the stoma.
The balloon 18 is typically attached at a proximal end 18a to the catheter shaft 26 by the use of adhesive, thereby forming a proximal cuff 32. Likewise, the distal end 18b of the balloon 18 is typically adhesively attached to the stiff tip 30, thereby forming a distal cuff 34.
The balloon 18 is advantageous because it allows the catheter segment 22 to be inserted into the stoma while the balloon is uninflated. Once the catheter segment 22 is properly positioned in the stoma, a syringe (not shown) is inserted into a side port 36 of the head 14 and a fluid is injected into the balloon 18 through a lumen (not shown in FIG. 1) of the catheter. The fluid inflates the balloon so that it extends outwardly from the catheter shaft 26 and the stiff tip 30.
While the balloon 18 remains inflated, the catheter segment 22 stays properly positioned in the stoma. If the catheter segment 22 needs to be removed, the balloon 18 may be deflated so that it will not interfere with withdrawal of the catheter shaft 26 and stiff tip 30. In such a manner, the position of the balloon catheter 10 is maintained until removal is desired.
While the configuration shown in FIG. 1 works well for maintaining the balloon catheter 10 in the proper position, the balloon catheter does have disadvantages. A primary disadvantage is discomfort to the user. In order to allow insertion of the catheter segment 22, the catheter shaft 26 and especially the stiff tip 30 must be relatively firm to prevent buckling under insertion pressures. This same firmness, however, makes the distal tip 26 much more prone to irritate anatomical structures which come into contact with the stiff tip 30. This is especially true in the stomach and intestines where the opposing walls of the anatomical structures tend to collapse on each other during physical exertion, or when the cavity has little or no food. As the person moves, the stiff tip 30 repeatedly engages the adjacent anatomical structure (such as the stomach wall) and can lead to considerable irritation and discomfort for the user.
While it would be advantageous to prevent the stiff tip 30 from contacting any adjacent anatomical structures, the balloon 18 provides certain inherent limitations. The balloon 18 must have the proximal and distal cuffs, 32 and 34, to seal form the balloon when fluid is injected into the lumen in communication with the balloon. Additionally, the cuffs 32 and 34 must be of sufficient length to provide a tight and durable seal between the balloon 18 and the catheter shaft 22 which will withstand bending and flexing caused by movements of the user. Thus, several millimeters of the distal tip 26 (and potentially the distal end of the cuff) are left exposed--leaving a significant potential for irritation.
Another disadvantage with the configuration shown in FIG. 1 is that the distal cuff 34 forms a joint 34a at its distal end. The joint 34a provides an abrupt edge which has a tendency to catch on the tissue defining the stoma through which the catheter segment 22 is placed, thereby frustrating insertion of the balloon catheter 10. As the joint 34a catches on the tissue, it can cause the catheter segment to buckle and can also cause irritation.
Thus, there is a need for an improved balloon catheter having a balloon orientation which isolates the firm distal tip from internal body cavity surfaces. There is also a need for an improved balloon catheter which lacks a joint or abrupt edge along the catheter segment which can interfere with catheter placement through the stoma.

Gastric balloon catheter with improved balloon orientation


A lacrosse head comprising a frame, a pocket attached to the frame, and at least one energy absorbing element engaging the frame to absorb energy from an impact to the pocket. Preferably, the frame, which includes a scoop, a throat, and sidewalls, includes energy absorbing elements positioned proximate to the throat and along the sidewalls of the frame. The energy absorbing elements can be positioned on an external surface of the perimeter of the frame. The frame includes pocket attachment apertures and the energy absorbing elements include apertures, wherein the apertures on the energy absorbing elements are substantially aligned with the pocket attachment apertures to secure the energy absorbing elements to the frame.

It will be appreciated by those of ordinary skill in the art that lacrosse is a fast growing sport. It will further be appreciated that lacrosse heads are essential to playing the game. A lacrosse head is a collection, catching, or basket-type, element that attaches to the end of a handle, or lacrosse stick. The lacrosse head is usually molded from polymers, such as duPont Xytel brand nylon. The lacrosse head has an open, or upper, side for catching and discharging a ball and a lower side to which a net or pocket is attached for holding the ball. A lacrosse head has a throat section that includes a ball stop for impacting a ball and a socket for receiving the handle. A pair of sidewalls is attached to the throat section proximate the ball stop and are joined distal from the throat section by a lip or scoop.
In the game of lacrosse, the head is used to catch the ball, hold the ball, and pass or shoot the ball. To this end, there have been several attempts to improve the lacrosse head to enhance the playing of lacrosse.
For example, U.S. Pat. Nos. 4,037,841, 4,270,756, and 6,561,932 disclose the use of cushioning materials placed on the internal surfaces of a lacrosse frame near its base at the ball stop. These cushioning materials are positioned and designed to cushion the impact between the ball and the frame of the lacrosse head once the ball has already been collect, or positioned, within the lacrosse head near the ball stop. These prior art lacrosse heads fail to use cushioning material to absorb energy from an impact between the ball and the pocket of the lacrosse head. As such, the ball has a tendency to rebound or "pop" out of the lacrosse head, which is an unwarranted event during the course of a lacrosse game.
Also, prior art attempts have been made to reconfigure the sidewalls and the ball stop area to improve the performance of a lacrosse head. For examples U.S. Pat. Nos. 5,935,026 and 5,651,549 issued to Dill et al disclose a lacrosse head in which the majority of the head, all the head except for the portion of the head proximal to the throat, lies on a plane below the stick. Additionally, U.S. Pat. No. 5,568,925 discloses an upper wall and a lower wall in which both the upper wall and lower wall curve away from the plane, have a curved base, and then curve back toward the plane.
These patents fail to recognize the need for a flat section separating the divergent and convergent sections near the throat and scope sections of the lacrosse head. Further, the design of the lacrosse head disclosed in U.S. Pat. No. 5,568,925 substantially increases the travel time of a ball through the curvature and reduces the control of the ball during this travel. Also, this curve causes the pocket to be formed further from the scoop. As such, a shot taken with this prior art head is slower and less controlled, which reduces the performance and usefulness of the prior art head during the lacrosse game.
What is needed, then, is a lacrosse head that reduces the energy of impact between the ball and the pocket of the lacrosse head. Preferably, this needed lacrosse head will reduce the rate of deflection of the pocket with respect to the frame upon impact of a ball with the lacrosse head. Additionally, a lacrosse head is needed to properly position the base of the lacrosse head with respect to the scoop and throat of the lacrosse head. This improved design should preferably increase the shot speed and control of a ball traveling from this new lacrosse head. Preferably this lacrosse head carries the lacrosse ball in a position within the lacrosse head that increases the shot speed and accuracy of the shot of leaving the lacrosse head. This needed lacrosse head is presently lacking in the art.


A modular hand grip for use on a firearm, the modular hand grip includes an upper portion, a lower portion and a coupling assembly. A rearward end of the upper portion is configured to engage a top portion of a barrel nut. Lug rails having gaps therein project from an inner surface of the upper portion at opposing sides and proximate edges thereof. The coupling assembly is engagable with a bottom portion of the barrel nut and is attached to the rearward end of the upper portion. The lower portion has opposing side sections, each terminating at an edge. A plurality of spaced apart lugs extend from each edge and are receivable in the gaps in the lug rails of the upper portion and are translatable in one of a forward direction and a rearward direction positioning the lugs under the lug rails.

It is understood that hand-held firearms require some type of handgrip so that the operator can hold the firearm as it is fired. Also, many accessories are available that aid in the proper and/or enhanced operation of firearms and some type of platform or mounting structure is generally provided or available as an accessory for this function. Several problems are prevalent in the firearms industry with respect to hand grip and rail assemblies. Many firearms are operated as automatic or semiautomatic and have a tendency to heat extensively so that handgrips attached directly to the barrel can produce hand burns for the operator if great care is not taken. In addition, anything attached directly to the barrel of a firearm can have a tendency to alter the barrel slightly and any alterations can adversely affect the accuracy of the firearm.
It would be highly advantageous, therefore, to remedy the foregoing and other deficiencies inherent in the prior art.
Accordingly, it is an object the present invention to provide a new and improved hand grip for a firearm.
Another object of the present invention is to provide a handgrip which is not attached to the barrel of a firearm.
And another object of the present invention is to provide a hand grip which can be utilized with existing firearms, and specifically with conventional barrel nuts.

Modular hand grip and rail assembly for firearms


A method for manufacturing polycrystalline silicon with high quality by effectively preventing undesired shape such as giving an rough surface to silicon rods or an irregularity in diameter of the silicon rods. The method for manufacturing polycrystalline silicon includes: an initial stabilizing step of deposition wherein a velocity of ejecting the raw material gas from the gas ejection ports is gradually increased; the shaping step wherein first the ejection velocity is increased at a rate higher than that in the stabilizing step and then the ejection velocity is gradually increased at a rate lower than the previous increasing rate; and a growing step wherein, after the shaping step, the ejection velocity is made slower than that at the end of the shaping step until the end of the deposition.

1. Field of the Invention
The present invention relates to a method for manufacturing polycrystalline silicon, which is for manufacturing a polycrystalline silicon rod by depositing polycrystalline silicon on a surface of a heated silicon seed rod.
Priority is claimed on Japanese Patent Application No. 2007-307445, filed Nov. 28, 2007, the content of which is incorporated herein by reference.
2. Description of the Related Art
As one of methods for manufacturing polycrystalline silicon, there has been known a so-called Siemens method used for manufacturing polycrystalline silicon. This method includes heating a plurality of silicon seed rods, arranged within a reaction furnace, supplying a raw material gas which is a mixed gas of chlorosilane gas and hydrogen gas into the reaction furnace thereby bringing the raw material gas into contact with the heated silicon seed rods, and allowing polycrystalline silicon to deposit on surfaces of the silicon seed rods by pyrolysis and hydrogen reduction of the raw material gas.
For such a method for manufacturing polycrystalline silicon, silicon seed rods which serve as seed cores are fixedly stood on respective electrodes arranged on an inner bottom part of the reaction furnace, with the upper portion of each of the silicon seed rods connected to each other by device of a short connecting member to thereby form a Π shape. A plurality of raw material gas ejection nozzles is dispersively-arranged between the erected silicon seed rods in the inner bottom part of the reaction furnace. When an electric current is applied from the electrodes to the silicon seed rods, the silicon seed rods are heated due to the resistance. Thus, when the raw material gas ejected from the ejection nozzles comes into contact with the surfaces of the silicon seed rods, polycrystalline silicon is deposited and grown in a radical direction to form silicon rods.
In this connection in the prior art, as disclosed, for example, in Japanese Patent No. 3660617, a control is needed to keep the rod surface temperature and the supply amount of the raw material per unit area of the rod surface in respective predetermined ranges until the termination of a deposition except for an initial stage of the deposition. In other words, since the surface area of a silicon rod increases with the growth of the silicon rod, the amount of raw material gas to be supplied is increased in accordance with the growth of the silicon rod.
However, when there is a large number of silicon seed rods thereby becoming closely packed together, there occurs a problem that it may become difficult to uniformly supply the raw material gas to the surface of the silicon seed rods, which results in undesired shape, such as giving an rough surface to silicon rods, and thus lowers the proportion of polycrystalline silicon with a smooth surface which is necessary to be suited as a raw material for manufacturing single crystal silicon. As disclosed in Japanese Patent No. 3660617, the method of merely increasing the amount of raw material gas to be supplied with growth of silicon rods requires an enhanced supply facility and thus grows in cost.
In consideration of the above circumstances, an object of the present invention is to provide a method for manufacturing polycrystalline silicon, which allows producing a larger amount of high quality polycrystalline silicon having smooth surface morphology by effectively preventing a silicon rod surface from being malformed.

Method for manufacturing polycrystalline silicon


A weightlifting apparatus is operative to continuously provide and adjust a force resistant to a torque produced by an exerciser that performs supination of biceps simultaneously with other exercise motions or pronation of triceps simultaneously with other exercise motions.

1. Field of the Invention
The present invention relates to a weightlifting apparatus operative to provide a continuous adjustable resistant force to a muscle-generated force produced by an exerciser that performs supination of biceps simultaneously with other exercise motions or pronation of triceps simultaneously with other exercise motions.
2. Description of the Related Art
Weightlifting apparatus for performing simultaneously two exercise motions are well known in prior art. A typical structure representative of these apparatus includes a bar with rotatably attached handles and changeable weights suspended opposite ends of the bar. The structure is configured to allow an exerciser to simultaneously perform, for example, flexing and supination of biceps or extension and pronation of triceps, wherein the supination motion is characterized by turning the palm upward, whereas the pronation motion is performed by turning the palm downward. Typically, such a structure is operative to generate a controllable force resistant only to a force generated by flexing/extending motion, but not to a torque generated by supination/pronation motion. Accordingly, muscle development controlled by the supination and/or pronation motions may be not as effective as desired.
Another type of the known weightlifting devices operative to simultaneously perform the supination/pronation exercises in combination with other exercises is operative to utilize weightlifting resistance to, for example, simultaneously perform biceps flexing biceps supination exercises. While the resistance to flexing motion is provided by using changeable weights, which can be easily selected from a very wide range to correspond to the muscle development level of the exerciser, the resistance to supination is caused by friction between the rotatable and non-rotatable parts of a handle assembly. Such a structure does not provide for an easy adjustment of resistance. Moreover, the adjustments range from near-zero to locking is very small and cannot be consistently reproduced, since there is no quantifiable indication of actual resistance. The level of resistance in such an apparatus is dependent on geometrical tolerances, the surface finishes and wears resistance of the involved parts and, therefore, may vary greatly from one apparatuses to the other or during usable life of the same apparatus. Another disadvantage of these apparatus is determined by the fact that if the motion is stopped, for example, at the point where the direction is changed from lifting to lowering the apparatus, a friction force provides no resistance to the supination motion of muscles. Also, a force resistant to a torque, which is generated during supination motion, is generated only when the exerciser lifts the apparatus, but not when the apparatus is being lowered, since during that part of the motion (to the starting position) the hands of the exerciser are exposed to pronation resistance. As a result, the intended muscles are loaded only during 50% of the exercise motion.
Still in another example of known apparatus for simultaneously performing two exercise motions, a spring-loaded supination/pronation motion unit is operative to generate a variable resistant depending whether a spring is in a contracted state or an expanded state during an exercise. However, it is a constant resistant force that is particularly beneficial the desired muscle development. In thus configured apparatus, during early stages of the lifting operation, a force created by the spring is directed through the center of rotation of both rotatable handles and totally equals to its normal component, whereas the tangential component is equal to zero. When the positions of the rotatable handle changes during the exercise, the spring force no longer passes through the center of both of the rotatable handles. During the rotational motion of the handles the normal component of the resultant force is gradually decreasing and the tangential component is increasing until the handles are rotated at 90° from the initial position. At this point the resultant force is equal to its tangential component, and the normal component is equal to zero. The resistance to be overcome by the muscles during the supination or pronation motion depends only upon the tangential component responsible for the generation of the resistant torque. Since this component constantly changes, the apparatus does not provide for constant resistance, which, as discussed above, is critical to the muscle development.
Yet another type of known apparatus for simultaneously performing two exercise motions, which utilize weightlifting resistance to multiple motions, allows performing only one or a very limited number of exercises and has a complex structure. Furthermore, the device strictly restricts the motion trajectory.
A need, therefore, exists for a weightlifting apparatus that allows the development of muscles by carrying out at least two exercise motions simultaneously under consistent, continuous and adjustable load.

Weightlifting apparatus for pronation and supination exercises


An electromagnetic drive type actuator comprises a movable plate having a flat surface, a support positioned around the movable plate, an elastic member connecting the movable plate with the support, wirings extending through the support, the movable plate and the elastic member, and a magnetic field generator. The elastic member is elastically deformable and supports the movable plate so as to allow the movable plate to move in directions parallel to the flat surface of the movable plate. The wirings pass currents. The magnetic field generator generates a magnetic field in a space around the movable plate. The magnetic field has a direction orthogonal to the flat surface of the movable plate. The movable plate is moved in the directions parallel to the flat surface of the movable plate by an interaction between the currents flowing through the wirings and the magnetic field generated by magnetic field generator.

1. Field of the Invention
The present invention relates to an actuator having a movable plate allowed to move, and more particularly, it relates to an actuator that displaces a movable plate in directions horizontal to a flat surface the movable plate.
2. Description of the Related Art
Jpn. Pat. Appln. KOKOKU Publication No. 1-35550 discloses a video camera aiming at an increase in resolution of an image by utilizing a piezoelectric actuator. A structure of this video camera will now be described hereinafter with reference to FIG. 11.
As shown in FIG. 11, a solid-state image sensing device chip substrate 610 is supported by two bimorph piezoelectric elements 611A and 611B fixed to a support base 612. Here, the solid-state image sensing device chip substrate 610, the bimorph piezoelectric elements 611A and 611B and the support base 612 constitute a piezoelectric actuator that displaces the solid-state image sensing device chip substrate 610 in directions horizontal to a flat surface of the chip substrate 610.
A light input is transmitted through an imaging lens 613 and image-formed on the solid-state image sensing device chip substrate 610. The bimorph piezoelectric elements 611A and 611B displace the solid-state image sensing device chip substrate 610 in directions vertical to an optical axis with a resonance frequency corresponding to a frame cycle upon receiving vibration pulses generated by a pulse driver 614, a tr, tf control circuit 615 and a trapezoidal wave generation circuit 616.
A timing generation circuit 617 generates necessary synchronization pulses such as a timing signal of a PH/2 delay circuit 618 required to delay a timing of a horizontal read register by a quantity corresponding to ½ of a horizontal pixel pitch PH, a timing signal of a vertical register and others. The solid-state image sensing device chip substrate 610 is driven by a clock driver 619, and an output signal obtained from the solid-state image sensing device chip substrate 610 is processed into a predetermined signal waveform through a preamplifier 620 and a process amplifier 621. A signal reproduction circuit 622 performs processing matching with a spatial sampling point based on first vibration and outputs a result.
Since a reproduced image on a monitor is displayed by adding a field A and a field B, a resolution in the horizontal direction is improved to be two times. That is, the video camera shown in FIG. 11 realizes an increase in resolution of an image by moving the imaging element in directions orthogonal to the optical axis by using the piezoelectric actuator.
The piezoelectric actuator according to the prior art utilizes a piezoelectric material. Therefore, a relationship between a drive signal (applied voltage) and a displacement quantity has hysteresis characteristics.
Further, in the video camera shown in FIG. 11, the bimorph piezoelectric elements 611A and 611B are repeatedly displaced in directions vertical to their flat surfaces in a cycle of 1/30 second or 1/60 second which is a period corresponding to ½ of one frame cycle or ½ of one field cycle. Therefore, there is a possibility that sound waves at a lower frequency involved by that displacement, i.e., vibration sounds may be generated. Since such vibration sounds become noises when recording sounds, it is desired that generation of such vibration sounds is as small as possible in an application of the video camera.


A ball and socket joint assembly for a water vehicle outdrive system pivots both the trim-lift and the rudder as well as provides a reverse thrust without the need of a shifting mechanism. The ball and socket joint assembly includes a control mechanism for generating a user input and directing the outdrive system to rotate freely in a select arcuate path so that the water vehicle can be propelled in a corresponding direction, a ball and socket joint section operably connected to the control mechanism for cooperating therewith to selectively position the outdrive system corresponding to the user input, and a support mechanism for assisting to maintain the ball and socket joint section at a substantially stable position during operating conditions. The support mechanism is selectively operable independently of the control mechanism so that a user may pivot the outdrive during non-operating conditions, for maintenance, repairs and the like.

1. Technical Field
This invention relates to a marine ball outdrive assembly and, more particularly, to a marine ball and socket outdrive assembly for allowing an operator to selectively rotate the outdrive and thereby eliminate the necessity for a separate shift mechanism and other like accessories.
2. Prior Art
The majority of outdrive repair problems are not associated with the drive components (shafts, bearings, etc.) but more often accessory components such as water pumps, shifting mechanisms, water conduits etc., which are typically encased within the outdrive housing along with the drive components. Servicing such accessory components requires a time-consuming and tedious disassembly of the outdrive housing, which typically compromises the housings, seals and shafts that are not the cause of the service. By eliminating the need for a shifting mechanism and associated accessories, many problems associated with conventional accessories disposed with the outdrive housing can be effectively eliminated.
For outdrives powered by an engine, removing the water pump from within the outdrive provides improved operator accessibility for maintenance and also removes the need for water conduits within the outdrive housing. For outdrives powered by an electric motor, the water pump and other accessory components are not needed. Furthermore, diverting outdrive exhaust that is normally discharged in water will help improve water quality and thereby effectively eliminate the necessity for exhaust conduits within the outdrive housing. To move in reverse, the propeller should be pivoted 180 degrees.
Removing such components from the outdrive housing and placing the easily accessible steering mechanism on the exterior of the outdrive housing, makes disassembly of the outdrive a rare necessity and helps preserve the integrity of the outdrive. Moreover, the maneuverability of a water vehicle can be increased by the ability to turn the rudder or propeller position through a full range of 180 degrees. Such a rotational motion is not possible with conventional outdrives having gimbals employed in their respective rudders and trims.


The present invention discloses a process for regenerating titanium-containing catalysts, characterized in that a deactivated catalyst is treated in an acidic solution having a pH value of ≦3, and then dried and calcined. The process is simple in procedure and can make the catalytic activity, selectivity and stability of the regenerated catalyst be recovered to the level of its fresh catalyst.

The reaction of a carbonyl compound with hydroxylamine is a major process for the synthesis of the corresponding oxime compound. For example, cyclohexanone oxime is a key intermediate for producing ε-caprolactam; while ε-caprolactam is an important raw material for organic chemical industries, mainly used as a monomer for synthetic fibers and engineering plastics (e.g., nylon-6). About 91% of caprolactam are produced industrially through a technique route with cyclohexanone oxime as intermediate product, in which cyclohexanone oxime is produced by the reaction of cyclohexanone with hydroxylamine (used in its sulfate or phosphate form). This process for the production of cyclohexanone oxime has a complex technology with multiple process steps and high investment in equipment, and it also has a problem in corrosion and pollution due to use or production of NOx, SOx and the like.
In the early 1980's, in U.S. Pat. No. 4,410,501, Taramasso (Italy) disclosed a novel type of catalytic material—titanium silicalite having an excellent function for selective oxidation of hydrocarbons, alcohols, phenols and the like (EP 0230949, U.S. Pat. No. 4,480,135, U.S. Pat. No. 4,396,783). It has been commercialized to use it for the preparation of catechol and hydroquinone by the selective oxidation of phenol with hydrogen peroxide.
EP 0208311, EP 0267362, EP 0496385, EP 0564040 and so on sequentially disclose a process for preparing cyclohexanone oxime in one step by ammoximation of cyclohexanone with ammonia and hydrogen peroxide catelyzed by titanium silicalite. This novel process features in mild reaction conditions, high yields of desired products, more efficient process, lower investment in equipment, reduced amount of wastes and environmental friend.
Furthermore, applications of other titanium-containing catalytic materials in ammoximation have also been reported. For example, EP 0347926 discloses that the ammoximation of cyclohexanone is carried out by using a catalyst in which titanium dioxide is dispersed on silica, both J. Le. Bars et al., Appl. Catal. A 136(1996) p.69 and P. Wu et al., J. Catal. 168 (1997) p. 400 report other types of Ti-containing crystalline silicate (e.g. Ti-ZSM-48, Ti-β, Ti-MOR and the like) which are used in ammoximation of a variety of aldehyde or ketone compounds.
The reaction of a nitrogenated basic compound with hydrogen peroxide is a major process for the synthesis of the corresponding hydroxylamine. In U.S. Pat. No. 4,918,194 and U.S. Pat. No. 5,320,819, it is reported that oxidation of a nitrogenated basic compound (e.g. secondary amines, ammonia and the like) is carried out by using a titanium silicalite or an amorphous titanium-containing catalyst.
With catalytic reactions being studied increasingly and intensively, more attention has been increasingly paid to the problem on stability of titanium-containing catalysts, especially titanium silicalites , in the ammoximation reaction of cyclohexanone for the preparation of cyclohexanone oxime. EP 0496385 reports that it is necessary to remove the deactivated catalyst periodically, which is to be replaced by a fresh catalyst make-up in order to maintain the desired catalytic activity during the reaction. How to improve the stability of titanium silicate molecular sieve has become a focus.
U.S. Pat. No. 4,794,198 discloses a process for pre-treating catalyst to increase the selectivity and improve the stability of catalyst. P. Roffia et al., Stud. Surf Sci. Catal. 55(1990) p.43 proposes that the catalytic reaction rate can be increased and the non-catalytic reaction thus can be minimized by optimizing the process conditions, e.g. selecting an appropriate solvent and increasing the catalyst concentration and reaction temperature. However, the improvement of the catalyst stability thus achieved is limited, since it has the problem concerning how to utilize and regenerate the deactivated catalyst due to the high cost of the titanium silicalite.
In general, there are two methods for regenerating the deactivated catalyst: washing with a solvent and calcining. In the book Selective Oxidation by heterogeneous Catalysis (2001), p.112, it is indicated that three main deactivation processes of titanium silicalites in the ammoximation of cyclohexanone: (1) slow dissolution of the framework (silicon) with accumulation of Ti on the external surface of the remaining solid, (2) direct removal of Ti from the framework and (3) pore filling by by-products. The book further points out that, the deactivation by pore filling can be partially eliminated by washing the catalyst with t-butanol. The regeneration effect is poor.
CN1302693A discloses a regeneration process of subjecting the catalyst, previously calcined, to a treatment in an aqueous medium with hydrogen peroxide in the presence of inorganic fluorinated compounds, subsequent to thermal treatment. This process is illustrated with an example related to a regeneration procedure of a catalyst deactivated in the ammoximation of cyclohexanone for preparing cyclohexanone oxime, wherein the catalytic activity of the regenerated catalyst can be recovered up to 84% relative to the activity of fresh catalyst. It also points out that if a catalyst is regenerated by thermal treatment only (calcined at 550° C.), the catalytic activity of the regenerated catalyst can be recovered to merely 31% relative to the activity of fresh catalyst. Anyhow, the catalytic activity of the regenerated catalyst obtained by this process is still not fully recovered to the level of fresh catalyst. Moreover, in this process, fluorinated compounds, are used in the chemical treatment thereof, which tend to be toxic and harmful.
CN 1290194A discloses a method of regenerating a supported catalyst covered with gold particles, based on titanium dioxide or titanium dioxide hydrate. The invention is characterised in that the catalyst is regenerated by contacting it with water, a diluted acid or a diluted hydroperoxide solution, to restore its catalytic activity. The catalyst used in this patent is prepared with a "deposition-precipitation" method and used for oxidizing unsaturated hydrocarbons in the gas phase. The dilute acid has a pH value of 4˜7.5, preferably 5.5˜6 and is preferably dilute H2SO4 or HF. Taking the oxidation of propene as an example, the catalytic activity of the catalyst regenerated according to the method of this patent can be recovered up to 80% relative to the activity of fresh catalyst It is impossible to recover the catalytic activity of the regenerated catalyst to the level of fresh catalyst by this method. Furthermore, the patent does not mention the stability of the regenerated catalyst

Process for regenerating titanium-containing catalysts

Research Institute of Petroleum Processing, SINOPEC


Information about the address of file information in a storage device and file information containing an updated version of the file information is recorded in different areas in the storage device before the file is updated, determination is made as to whether or not the information can be read successfully from the storage device (steps 202 and 204), and based on the determination, determination is made as to whether or not data recovery should be performed and, if data recovery should be performed (steps 201 and 203), data successfully read from the storage device is used to record the data in a sector indicated by the address information (step 205).

Recording apparatuses having a recording medium such as a semiconductor memory, magnetic disk, magneto-optical disk, and an optical disk have been widely used as recording apparatuses for recording information in computer systems such as personal computers.
If data is recorded on a recording apparatus capable of random access such as a hard disk drive (HDD) which uses a magnetic disk as its recording medium, the data is not recorded in contiguous areas on the recording medium, but instead, is recorded in clusters, which are the smallest recording units. In the recording apparatus, a file system is used in which a directory entry containing file names and the cluster number of the first piece of data scattered in pieces in the recording apparatus and a file allocation table (FAT) which identifies the order of the pieces of scattered data are used to manage files recorded on the recording apparatus.
A file system which has been used for managing files recorded on such a recording apparatus will be described below.
FIG. 7 shows a configuration of a FAT file system. As shown in FIG. 7, provided in a recording apparatus is a file system including directory entries 701 of a root directory, which are information containing the filenames of recorded files and the starting cluster number of scattered data, clusters 703 which are the smallest recording units for storing real data, and a FAT 702 indicating information about the links between clusters 703 constituting a file. In the example shown in FIG. 7, the directory entry 701 indicates that a file, Data 1, is stored in clusters starting with cluster number 0002 on this recording apparatus. The FAT 702 indicates that the data in Data 1 is arranged in the order of cluster numbers 0002, 0003, and 0004 and the real data in Data 1 is recorded in the areas associated with cluster numbers 0002, 0003, and 0004 of the clusters 703. The FAT 702 also indicates that another file, Data 2 is stored only in the area associated with cluster number 0006.
When a file is created in the recording apparatus, its filename and the starting cluster number are entered in a directory entry 701 of the root directory and information about the links between clusters 703 in the FAT 702 is updated as real data is recorded in each area of the clusters 703. When a file is deleted from the recording apparatus, a portion corresponding to the file to be deleted from the directory entry 701 is set as "Unused" and the link information in the FAT 702 is set as unused in the order in which the clusters are linked.
In this way, each time a file operation is performed on the recording apparatus, the FAT 702 and a directory entry 701 are updated. Therefore, if a power failure causes a file operation to be aborted without performing a normal procedure, the FAT 702 and the directory entry 701 are corrupted, resulting in file corruption and data loss.
In a FAT file system, two file allocation tables 702 with the same size are originally provided so that, in the event that one of them is corrupted, data can be copied from the other to recover file information. The directory entry 701, on the other hand, is not duplicated. Accordingly, in case the directory entry 701 is corrupted, a corrupted file or lost data can never be recovered.
Therefore, a data recovery method as disclosed in Japanese Patent Laid-Open No. 2002-63057 (paragraphs [0001] and [0002] and FIGS. 4 and 5) has been proposed for enabling data to be recovered even if a directory entry 701 is corrupted. In that method, a temporary index as shown in FIG. 8 is created and recorded in a recording apparatus before a directory entry and a FAT are updated and, once an update of the directory entry and the FAT has been completed successfully, the temporary index is deleted from the recording apparatus.
In FIG. 8, reference number 801 denotes a sector number indicating a recording location in the directory entry 701 in the recording apparatus and 802 denotes a flag indicating whether the directory entry 701 and the FAT 702 are being updated. The remaining information items are information originally contained in the directory entry 701.
In the vent a file operation is aborted due to a power failure for example, determination is made during restarting as to whether a temporary index is present or not. If a temporary index is found, data in the temporary index is compared with its corresponding data in the directory entry 701 for recovering the directory entry 701.
According to such a prior-art data recovery method, an abort of a write of data about the size of one sector to a recording apparatus is neglected because of its smallness. This method has a problem that, if a write operation is aborted due to a power failure for example, the temporary index cannot successfully be read during restarting and therefore a recovery process cannot be performed, because determination as to whether or not a recovery process should be performed is made based on a flag in the temporary index.
Another problem with the method is that the temporary index is deleted after a successful update of a directory entry for recovering data and therefore, if file operations are frequently performed, temporary index delete operations are also performed frequently and thus time spent for file update processing is increased.

Data recovery method and data recording apparatus

Matsushita Electric Industrial Co., Ltd.