Inverse gas-chromatography apparatus for investigating the properties of a solid material, having a carrier fluid, comprising at least two fluid components (typically water and an inert gas); a second flow comprising the carrier fluid components and probe material; a temperature controlled column, for holding the solid material; a switch for selectively passing the flow of carrier fluid and the second fluid flow through the column; a detector for detecting the passage of the probe material through the column. The relative proportions of the fluid components in the flow of carrier fluid and the second fluid flow can be controlled.

The invention relates to apparatus and a method for investigating the properties of a solid material by inverse chromatography, and in particular by inverse gas chromatography.
In conventional gas or liquid chromatography, the composition of an unknown multicomponent gas or liquid is determined by injecting the unknown material into a carrier fluid (the xe2x80x9cmobile phasexe2x80x9d, typically helium or nitrogen) which passes through an absorptive column (the xe2x80x9cstationary phasexe2x80x9d). The retention time due to mobile-stationary phase interactions (solid-vapour, vapour-liquid or solid-liquid adsorption) of the various eluted components allows for the composition of the unknown material to be deduced by reference to calibration data. In contrast, in inverse gas or liquid chromatography the properties of an unknown solid material in a column are investigated by passing a known probe through the column. For inverse gas chromatography, the carrier again is typically an inert gas such as helium or nitrogen, and the probe may be a material which is a gas under ambient conditions, or a solvent vapour.
The length of time that the probe is retained in the column is determined by the physicochemical interactions between the probe and the solid material packed in the column. This interaction is governed by a number of mechanisms, the most important of which are surface adsorption, and where the probe is partially soluble in the solid material, bulk solubilisation. Thus, the study of the retention behaviour of a probe can provide important information on the surface and bulk properties of the material in the column.
The use of inverse gas chromatography in investigating various properties of solids, such as adsorption isotherms, adsorption thermodynamics, surface energetics, acid-base interactions, glass transition temperatures, surface area, diffusion coefficients and porosity is described in the book xe2x80x9cPhysicochemical Measurement by Gas Chromatographyxe2x80x9d by J. R. Conder and C. L. Young., John Wiley and Son, 1979 and the article xe2x80x9cDaryl Williams, Inverse Gas Chromatography, Characterisation of Composite Materials: Materials Characterisation Seriesxe2x80x94Surfaces, Interfaces, Thin Films, Chapter 5, 80-103 Butterworth-Heinemann, 1994. This article also discusses in detail the most appropriate experimental method, for example xe2x80x9celution at infinite dilutionxe2x80x9d, xe2x80x9celution of a characteristic pointxe2x80x9d or xe2x80x9cfrontal analysisxe2x80x9d, for determining each of these properties. In addition to influencing the method chosen, the nature of the property under examination will also affect the choice of probe.
In most instruments used for inverse gas chromatography, the probe is a single compound which is introduced into a single component carrier gas flow that is then eluted through the column. For example, J. Chrom. A. 715, 1995, 279-285 discloses an injection system for an inverse gas chromatograph composed of a closed loop vapourisation chamber with a gas sampling valve, which provides multiple injections of the same sample into a single component gas flow at precisely controlled intervals.
A further variation is disclosed in U.S. Pat. No. 4,806,315 (Daigle). This reference is concerned with the ability to measure samples containing water more accurately by adding water vapour to the carrier gas flow, to form in effect, a two component carrier gas flow (e.g., water and helium). However, in the method disclosed, water passes into the flow via a water permeable membrane, and therefore the ratio of the two components (i.e., the humidity of the carrier) is fixed by the physical properties of the membrane. The only way to vary the humidity of the carrier is to dismantle the equipment and replace the membrane with one of a different type and size.
U.S. Pat. No. 4,869,094 (Gilber) relates to a method of determining sorption isotherms of food by inverse gas chromatography. In the method disclosed, a temporary front of water is established in a carrier gas which can be regarded as a two component gas flow composed of water and carrier gas. Although this reference discloses the possibility of investigating the behaviour of a solid material through inverse gas chromatography, under conditions of humidity, it does not disclose any method by which the humidity level can be varied. The two component carrier flow is formed by passing helium through a water trap, and thus the humidity of the flow is fixed at 100%. The only way therefore of changing the concentration of water vapour in the gas flow would be to change the temperature of the water bath surrounding the pre-column and the experimental column. This would, of course, necessitate a change in the temperature of the sample in the column, thereby influencing the behaviour of the material in the column since adsorption phenomena are highly temperature dependant.
According to the present invention there is provided apparatus for investigating the properties of a solid material comprising:
means for generating a flow of a carrier fluid, comprising at least two fluid components;
means for generating a second fluid flow comprising the said carrier fluid components and probe material;
a column, for holding the solid material;
means for selectively passing the flow of carrier fluid and the second fluid flow through the column;
means for controlling the temperature of the column;
a detector for detecting the passage of the probe material through the column, and
means for controlling the relative proportions of the said fluid components in the flow of carrier fluid and the second fluid flow.
Preferably, the carrier fluid is a gas. The probe material may be a gas under normal conditions (e.g. methane) or may be a vapour of a substance normally liquid under normal conditions (e.g. octane).
In a particular preferred embodiment of the invention, one of the said carrier fluid components is water i.e. the means for controlling the relative proportions of the carrier fluid components comprises means for controlling the relative humidity of the carrier and second fluid flows. The ability to vary the humidity of the carrier enables the solid material to be investigated under a wide range of conditions and enables the simulation of conditions which may arise in use. This is particularly important where for example, the solid material is a compound intended for pharmaceutical use.
In another embodiment of the invention the means for generating a flow of carrier fluid comprises:
means for generating a first sub-flow relatively rich in a first said component (for example a stream of an inert gas such as helium);
means for generating a second sub-flow relatively rich in a second said component (for example a saturated stream of the same gas);
means for combining the first and second sub-flows,
wherein the means for controlling the relative proportions of the said fluid components comprises at least one control valve for varying the mixing ratio of the said first and second sub-flows (for example so as to control the humidity of the carrier).
In a further preferred embodiment, a third sub-flow, relatively rich in the probe material is also provided (for example, of humidified helium containing the desired probe material) and mixed with the first and second sub-flows in a desired ratio.
It is therefore possible for variations in the proportions of the carrier components to be made without the need to vary other experimental parameters such as column temperature. Furthermore, since the proportion of components present is not predetermined by the intrinsic properties of the apparatus, as in U.S. Pat. No. 4,806,315, but rather is varied simply by adjusting a control valve, the relative proportions of the fluid components may be varied both before and during an investigation.
Preferably, the second sub-flow comprises both the first and second components (for example, inert gas and water vapour) and the means for generating the second sub-flow comprises a container for the second component in liquid form. The container has an inlet connected to a fluid line, and a vapour space over the liquid, so that a flow of the said first component can be passed through the vapour space, and thereby generate the xe2x80x9csub-flowxe2x80x9d through the said vapour space.
The said inlet will generally be below the liquid level of the second component, so that the first component (the inert gas) bubbles through the second component, on passage through the container.
In a further embodiment of the invention, a second fluid flow (i.e. a probe-containing flow) may be generated in a similar fashion, by bubbling gas through the probe material in liquid form. In this embodiment, the apparatus comprises at least one second container, for containing the probe material in liquid form, the said container having an inlet and an outlet, and means defining a vapour space over the said liquid probe material. A fluid line is connected to the second inlet, for passing a flow of at least one of the carrier flow components through the vapour space.
In this embodiment, the inlet is again preferably below the level of the probe material, so that the first component bubbles through the said probe material, on passage through the container.
By providing more than one such container for different probe material, with appropriate switching arrangements, it becomes possible to switch easily between various types of probe material.
Control valves, which may preferably be operated automatically, under computer control, may be provided for varying the mixing ratio of the said first, second and third sub-flows.
Because the relative proportions of the fluid components in the second fluid flow are varied by altering the mixing ratio of the various sub-flows, any changes to the concentration of components in the fluid flow can be brought about independently of, for example, the temperature of the column.
When the probe is a material which is a gas under normal conditions, the means for generating a second sub flow may comprise simply a fluid line for introducing the probe material, and the means for controlling the relative proportions of the said fluid components may comprise a control valve for varying the mixing ratio of the said probe material and the said two fluid components.
The apparatus may also include an injection port for injecting probe material into the carrier gas flow.
The apparatus in its preferred embodiments permits more than one method of introducing probe material into the carrier gas flow. This allows a number of different types of compounds to be employed as probes.
It is preferable that the apparatus comprises at least two columns since this enables the results from a column packed with the solid material under investigation to be compared with those from an empty column or one containing inert material, and for batch to batch variations and the reproducibility of samples and methods to be examined under identical conditions. A column selector valve may be employed to select the column into which the probe-containing flow is to be passed. A selector valve may also be employed to select the flow which is passed to the column or column selector valve, the selection being made, for example, between a probe-containing flow, and a non-probe-containing flow, the flow which it not selected at any particular time being vented from the apparatus.
In a preferred embodiment, probe-containing flow may be passed though one of the columns, whilst non-probe-containing flow, is passed through another. In this way, one column can be prepared for use while an experiment is being carried out on another column. This is of advantage to an operator since a packed column often needs to be conditioned for several hours or days to allow it to equilibrate before an experiment can be commenced.
The apparatus preferably includes at least three, more preferably, at least 4, and more preferably still, at least 5 temperature zones, and means for controlling independently the temperature in each said zone.
This enables those portions of the apparatus within a particular zone to be set at an optimum operating temperature, rather than a xe2x80x9ccompromisexe2x80x9d temperature under which all parts of the apparatus can function.
In particular, the column and the flow selector valve are preferably in different temperature zones. The column is preferably also in a different temperature zone from the part of the apparatus in which the probe is introduced, particularly when a probe-containing flow sub-flow is generated from a liquid probe material.
The temperature of the zone or zones containing liquid probe material is determined by the physical properties of the fluid components employed, for example its boiling point. However, in order to investigate a wide range of solid material properties, it is desirable to be able to vary the column temperature over a considerably broader range. Thus, the ability to locate the liquid probe material in a different temperature zone from the column provides a considerable advantage.
The column and the injection port are preferably also in different temperature zones.
In a particularly preferred embodiment, the container for the second component (e.g. water) and the container for liquid probe material are in a first temperature zone, the column is in a second temperature zone, and the injection port and selector valves are in a third temperature zone.
It is also advantageous for the various selector valves to be located in different temperature zones from containers for the second component (e.g. water) and for liquid probe material, in order to minimise the risk of condensation of fluid components.
In a further particularly preferred embodiment, the container for the second component (e.g. water) and the container for liquid probe material are in a first temperature zone, the column is in a second temperature zone, the injection port is in a third temperature zone, and the flow selector valves are in a fourth temperature zone.
Where the carrier fluid is a gas, it is an advantage for the injection port to occupy a different temperature zones, since this enables its temperature to be maintained at which allows for the complete vaporisation of any liquid to be introduced through the injection port.
The temperature of the column can preferably be varied from ambient (xe2x88x92298 K) to 100xc2x0 C. (373 K), preferably from 77 to 500 K, and more preferably from 77 to 600 K. The apparatus preferably also comprises means for pre-setting the temperature of at least one of the said temperature zones prior to an investigation of the properties of the said solid material.
The automatic control function of the apparatus may preferably comprise means for pre-programming flow of carrier fluid and the second fluid flow through the column prior to an investigation of the properties of the said solid material, and/or for pre-programming the relative proportions of the said fluid components prior to an investigation of the properties of the said solid material.
The ability to pre-set the experimental conditions allows the apparatus to be programmed to carry out a number of experiments in a row, for example overnight, thus maximising the efficient use of time.
The proportion of each fluid component in the flow of carrier fluid and the second fluid flow can preferably be varied over a range of from 0 to 95 percent, by altering the mixing ratio of the various sub-flows. The concentration of components present may be thus be varied in a step-wise, ramped or modulated manner.
The principal component of the carrier will generally be an inert gas, such as nitrogen, helium or argon, and the probe material will generally comprises at least one organic compound.
In a further preferred embodiment of the invention, the column is straight and is vertically mounted in such a way that the longitudinal axis of the column is vertical.
The use of a straight column allows the column to be packed more easily without gaps or breaks forming during packing. Furthermore, mounting the column vertically prevents gaps or channels developing if the solid material settles during conditioning since any settling will simply shorten the packed length of solid material.
It can therefore be seen that the apparatus is particularly suited for a determining a wide range of properties of a solid material in the column since it is capable of generating a wide range of operating conditions.
Appropriate software may be provided to automate the measurement of, for example, net retention time, net retention volume, specific retention volume, column inlet and outlet pressures, and fluid-solid distribution coefficient, and for determining therefrom properties of the solid material such as heat of adsorption, standard free energy of adsorption, entropy of adsorption, dispersive component of solid surface energy, total uptake per unit of solid material, surface area, thermal desorption, glass transition temperature, phase transition properties, diffusion coefficients, porosity, polymer-polymer interaction parameters, probe-polymer interaction parameters, acid-base surface properties and competitive adsorption.
In another aspect of the invention there is provided, a method of investigating the properties of a solid material comprising:
inserting the solid material into the column of apparatus as described above;
passing the flow of carrier fluid over the solid material;
passing the second fluid flow over the solid material;
detecting the passage of probe material through the column to determine properties of solid material.

Apparatus and a method for investigating the properties of a solid material by inverse chromatography


Provided is a circuit for implementing the coding of a DVI (Digital Visual Interface) standard in a small size of hardware, at high speed, and with low power consumption. In a DVI coding circuit, the input of a number-of-levels comparison circuit 22 for judging which of the number of bits at a level “H” and the number of bits at a level “L” is larger in the input signal of the coding circuit is set at 7 bits. The output of a number-of-transitions decrease circuit 23 for decreasing the number of the transitions between adjacent two bits can be inverted for 4 bits on the basis of the output of the number-of-levels comparison circuit 22. A DC balance circuit 24 for keeping the direct current-wise balance of the output signal of the coding circuit includes a 4-bit register 31, a number-of-levels difference computation circuit 27, a condition decision circuit 28, a bit inversion circuit 29 and an addition circuit 30. The number-of-levels difference computation circuit 27 receives as its inputs the 8 bits of the output of the number-of-transitions decrease circuit 23 and the 4 bits of the input signal of the coding circuit.

As one of high-speed transmission systems for digital image signals, there is the standard of DVI (Digital Visual Interface) (hereinbelow, this standard shall be referred to as "DVI standard", and the specification thereof shall be referred to as "DVI standard specification"). The DVI standard specification can be obtained from "http://www.ddwg.org/downloads.html". A coding system which is handled in the present invention is stipulated on pages 28–29 in DVI standard specification Rev. 1.0 (hereinbelow, this coding system shall be termed "DVI coding system"). The circuits which form the foundation of the DVI coding system, are described in U.S. Pat. No. 6,026,124.
Shown in FIG. 1 is a flow chart of the DVI coding system.
The transmission system of DVI is a system wherein, on a transmission side, the 8-bit RGB (Red, Green, Blue) input signals of image data are respectively coded into 10-bit signals, the resulting parallel 10-bit data are respectively serialized, and four differential pair signals including a clock signal added to the serial data are transmitted.
The DVI coding system codes each 8-bit input signal into a 10-bit signal, thereby to minimize the probability of the transitions between adjacent two bits of the signal and also to balance a "H" level (hereinafter, also referred to as "1") and a "L" level (hereinafter, also referred to as "0"). Minimizing the probability of the transitions between adjacent two bits decreases the number of times when the data change over in the case where the parallel 10-bit data is serialized and transmitted, which is effective to decrease the emission of superfluous electromagnetic waves. Balancing the "H" level and the "L" level eliminates the inter-pair DC-wise deviation of the signals transmitted as differential pairs.
Concretely, in a unit time, an 8-bit image data signal D[0:7] is input for one character, and 10-bit data q_out[0:9] is output for one T.M.D.S. character. "T.M.D.S. (Transition Minimized Differential Signaling)" is a coding system which forms the foundation of the DVI standard, and the "T.M.D.S. character" signifies the coded data of 10 bits.
The coding is done when a signal DE is at the "H" level.
Cnt(t) is a content which is held in an internal register at time "t" in order to keep the balance between a number of "1" and a number of "0" in a plurality of successive T.M.D.S. characters, and it is obtained as the sum of a value calculated by subtracting a number of "0" from a number of "1" and a content Cnt(t−1) held in the internal register at time (t−1). For example, when the signal is "1011000001" at the time "t", a value, which is calculated in such a way that "−2" obtained by subtracting "6" as a number of "0" from "4" as a number of "1" is added to the content Cnt(t−1) held in the internal register at the time (t−1), becomes the value of the content Cnt(t).
By the way, in the figure, N1{x} indicates a formula which returns how many "1" are contained in a multi-bit variable "x". Likewise, N0{x} returns how many "0" are contained in the multi-bit variable "x". Further, q_m[] indicates a result produced by subjecting the 8-bit input signal D[0:7] to processing so as to decrease the number of the transitions between adjacent two bits thereof. The meaning of the number of the transitions between adjacent two bits will be explained, for example, in an 8-bit input signal "10010010". When this input signal is viewed rightwards in succession, there are 5 parts where a value transits from "1" to "0" or from "0" to "1", and hence, the number of the transitions between adjacent two bits is five. Besides, q13 out[0:9] indicates a 10-bit coded output signal further subjected to processing for keeping a DC balance.
As shown at S101 in FIG. 1, according to the standard specification, in order to minimize the probability of the transitions of the signal, the number of bits at the "H" level in the 8-bit input signal needs to be counted so as to discriminate "a case where the number of bits at the "H" level is larger than 4, or a case where the 0th bit is at the "L" level and where the number of bits at the "H" level is 4" from any other case. In the case where the number of bits at the "H" level is smaller, the number of the transitions between adjacent two bits can be decreased by coding with use of XORs, as shown at S102 in the figure. Besides, in the case where the number of bits at the "H" level is larger, the number of the transitions between adjacent two bits can be decreased by coding with use of XNORs, as shown at S103 in the figure. A circuit which incarnates step S101 in the figure in the standard specification, can be realized by combining a bit slice adder 2 and a condition discrimination circuit 3 as shown in a circuit diagram of FIG. 2. However, this circuit expends a long time because the circuit has a large number of stages of gates through which signals must pass till the final result is obtained. For example, in conventional logic circuits of CMOS scheme, in the case of each of full adders FA (7–10), signals need to pass two stages of gates for obtaining a carry signal C, and signals need to pass three stages of gates for obtaining a sum signal S, and in case of each of half adders HA (4–6), signals need to pass two stages of gates for obtaining a carry signal C, and signals need to pass two stages of gates for obtaining a sum signal S. Therefore, signals need to pass at most ten stages of gates till arrival at the condition discrimination circuit 3. In order to obtain the final result, signals need to pass several further stages of gates in the condition discrimination circuit 3.
Besides, as shown at step S102 or S103 in FIG. 1, according to the DVI standard, the number of the transitions is decreased by executing the processing of taking XOR or XNOR between 0th bit and 1st bit of the input bits and thenceforth taking XORs or XNORs between such computed results and the neighboring bits, respectively. When interpreted as stipulated in the DVI standard specification, a circuit for the above processing becomes as shown in FIG. 3. In the circuit, XNORs 11a–11g and XORs 12a–12g are connected in parallel, and either of their results is selected by a selector 13 at a succeeding stage. Also this circuit is disadvantageous in that the circuit has a large number of stages of gates through which signals pass till the determination of the last bit.
Next, according to the DVI standard, a judgment for balancing an output code DC-wise is formed at steps S106 and S107 as shown in FIG. 1. Concretely, there are formed a judgment on whether the content Cnt(t−1) of the internal register at the time (t−1) is plus, minus or zero, and a judgment on whether a number of bits at the "H" level is larger, a number of bits at the "L" level is larger, or a number of bits at the "H" level is equal to a number of bits at the "L" level, after the number of bits at the "H" level and the number of bits at the "L" level have been counted as to the 8-bit signal q_m[0:7] subjected to the processing of decreasing the number of the transitions between adjacent two bits. In accordance with the results of the judgments, the value of the data q_out[0:9] to be output to keep the DC balance is determined, and the internal register is updated at steps S110–S113 as shown in FIG. 1. A circuit for conducting operation which is close to that of a circuit incarnating such processing is illustrated in FIG. 7B of U.S. Pat. No. 6,026,124. A simplified block diagram for explaining the operation of a circuit based on the illustrated circuit, is shown in FIG. 4. First, the signal q_m[0:7] which has been coded so as to decrease the number of the transitions between adjacent two bits is divided into sets each consisting of 2 bits. As to the respective bit sets, whether bit values are "11" or "00" is evaluated by "11"·"00" detection circuits 14a–14d. If the value of each set of 2 bits is "01" or "10", the DC balance is already kept within the 2 bits, and hence, the set is neglected. In accordance with the results of the evaluations, the numbers of "11" and "00" are respectively counted by counters 15 and 16. The differences between the counts of the two counters are computed by subtractors 17a, 17b, and the computed results, the content of the internal register and the value of data q_m[8] are evaluated by a condition decision circuit 18. Either one of output values of the subtractors 17a and 17b is selected by a selector 19 on the basis of the evaluated result, and the sum of the selected value, the output value of the condition decision circuit 18 and the value of a 4-bit register 21 is calculated by a 4-bit adder 20, so as to update the content of the 4-bit register 21 and to output a signal q_out[9] which indicates whether or not the final coded result is to be inverted.
This circuit operates upon receiving the outputs of the circuits for decreasing the number of the transitions, and therefore has the disadvantage that a long time is expended till the obtainment of the final result.
The present invention has an object to overcome the above disadvantages in the DVI coding system, and to provide a circuit which implements the system in a small hardware size, at high speed and with low power consumption.

Semiconductor integrated circuit for realizing coding circuit


The invention relates to a method and device for crushing and mixing soil and a soil improving agent in order to regenerate soft or sticky soil. According to the method of the invention, the soil and the soil improving agent are cut, crushed, and mixed by a crusher (7) in a primary cutting, crushing, and mixing process, and are then struck, crushed, and mixed in a secondary cutting, crushing, and mixing process. The device of the invention comprises the crusher (7), a rotary cutter (13) at the upper part of the crusher (7), a striker (10B) at the lower part thereof, and a conveyor (8) arranged on a vehicle body (3).

At present, it is inevitable that civil engineering work, construction work, etc., are required to be performed on soft ground, such as reclaimed land, in order to promote efficient use of limited space. Such soft ground is usually dehydrated by scattering a hardening agent so that the soil is regenerated. Further, when water supply or drainage works or gas pipe laying works are carried out, the ditches for laying the pipes are usually refilled, using soil which has been dug by construction machines such as hydraulic shovels.
However, watery clay or sticky soil, which has been dug and stirred up by hydraulic shovels or the like, cannot hold itself. Therefore, soil which is not usable for filling the ditches has to be relocated using dump tracks.
Japanese Patent Laid-Open Publication 54-58901 has proposed a soil improving method in order to overcome these problems. According to the publication, a predetermined amount of sticky soil, which is not applicable to filling ditches, is sequentially supplied, contacted with a soil improving agent having wet-hard characteristics in a predetermined ratio, and then crushed and mixed. The publication also discloses a soil improving machine, which comprises a conveyor for relocating sticky soil which is not usable for filling ditches, a cut screw for slicing the unusable soil into layers having a predetermined thickness and for removing surplus soil at an appropriate position, a device for adding a predetermined amount of wet-hard type soil improving agent to a preset amount of soil carried on a conveyor, and a crusher for crushing and mixing the soil and the soil improving agent.
The foregoing soil improving machine, however, crushes and mixes soil and soil improving agent using only one crushing cutter; thus it is difficult to efficiently mix the soil with the soil improving agent.
An impact crushing/mixing machine for dug soil is known in Japanese Patent Publication 4-9586. This machine includes rotary strikers, flexible crushing plates, and a casing which houses a plurality of crushing pieces coupled to the flexible crushing plates, at least a pair of elastic members extending along the flexible crushing plates, and a support for coupling flexible crushing plates in the vicinity of the elastic members.
However, such an impact crushing/mixing machine has a problem in that it cannot crush and mix sticky soil but only deform it.
There is another problem in that a lot of dust is generated when soft ground is dried by hardening agent. There is a further problem in that when a construction site is narrow, construction machines, such as vehicles for scattering hardening agent and vibrating rollers for ramming the land, etc., cannot be simultaneously introduced there. Still further, construction cost is increased when a number of construction machines are used according to conventional methods.

Method of crushing and mixing soil and machine therefor


The outer, sealing cover of an inflatable packer comprises an alternating series of thick and thin annular portions which act to effect greater sealing stresses and to inhibit the propagation of cracks or tears in the elastomeric cover. Bonding with only portions of the underlying slats as well as a tapered contour and spacing from an end fitting act to help to retain the cover in its proper position during running and retrieval as well as decreasing the likelihood of the development of cracks and/or tears.

Inflatable packers or bridge plugs have long been used in wellbore operations. An inflatable packer typically comprises a tubular base and a surrounding, inflatable elastomeric bladder or sleeve. Fluid passages within the tubular body allow fluids to contact the inflatable bladder and expand the bladder radially outwardly to effect sealing engagement with a borehole or well casing.
Since the elastomeric bladder is subjected to both expansion pressure and abrasion or cutting forces, it has been common to surround the exterior surface of the bladder with a plurality of peripherally overlapping, resilient reinforcing slats or ribs. There is generally sufficient overlap of such slats that upon expansion of the inflatable bladder, the slats remain as a surrounding armor protecting the bladder from abrasion and cuts while also preventing extrusion of the bladder elastomer between the slats in a localized area.
Because the slats cannot effect the sealing of the packer against a wellbore or casing, at least some portions of the reinforcing slats are surrounded by and may be bonded to an outer annular elastomeric cover or packing element which, upon expansion of the inflatable packer, comes into pressure sealing engagement with the wellbore or casing.
The outer sealing cover generally comprises either a single or a plurality of annular circumferential elastomeric pieces located on the outer surface of the reinforcing slats. When a single elastomeric piece is employed it may cover only a portion of the longitudinal length of the slats or, alternatively, it may cover the entire outer surface of the slats. Such single piece covers generally have a uniform thickness along their length, the thickness generally being substantial. Such arrangements are described in U.S. Pat. Nos. 3,837,947, 4,832,120 and 5,143,154.
One difficulty with uniformly thick covers is that once a tear or crack develops in the cover, it propagates rapidly over the cover, ultimately resulting in failure of the cover to maintain a seal after more than its initial cycle of use. The failure due to propagation of cracks or cuts over the cover is not ameliorated in multiple piece covers. Multiple piece covers are similarly of a single thickness which does nothing to arrest or retard the propagation of cracks or cuts within the body of a cover piece.
Bonding of the cover to the slats is desirable particularly in a retrievable packer. However, the bonding of the cover to the slats creates yet another source of stress on the cover elastomer as the packer is inflated. Cracks or tears in the cover can result merely as a consequence of inflation and stresses created by the bonding of the cover to the underlying slats which are experiencing flexure and separation.
An additional difficulty with uniform thickness outer covers is that after a typical inflation/deflation cycle of the packer, the exposed blunt ends of the cover can easily be caught in a subsequent running or retrieval movement of the packer resulting in a tearing or pulling off of the cover.


An organic electroluminescence display device and a method of manufacturing the same, configured to prevent IR drop of a second electrode by forming an auxiliary electrode line in an organic electroluminescence display device, are disclosed. The display device is also configured to prevent pixel shrinkage caused by deterioration of an organic electroluminescent layer due to transfer of gases into the organic electroluminescent layer. The out-gassing is prevented by providing a plurality of patterns and/or trenches in the auxiliary electrode line to reduce the contact area between the auxiliary electrode line and the second electrode, thereby lowering heat resistance and optimizing heat transfer during a curing process, and also allowing for removal of remaining gases in an organic film.

This application claims the priority of Korean Patent Application No. 10-2004-98878, filed on Nov. 29, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to organic electroluminescence display devices and methods of manufacturing the same, and more particularly to an organic electroluminescence display device configured to prevent a pixel shrinkage phenomenon caused by deterioration of an organic electroluminescent layer.
2. Description of the Related Technology
An organic electroluminescence display device, such as an organic light emitting diode (OLED) display, has desirable characteristics such as spontaneous emission, wide viewing angle, fast response, small thickness, low production cost, and high contrast. Therefore, much attention has been paid to the organic electroluminescence display device as a next generation flat display device.
An exemplary organic electroluminescence display device comprises an anode electrode, a cathode electrode, and an organic electroluminescent layer interposed therebetween. Electrons and holes supplied from the respective anode and cathode electrodes are combined into electron-hole pairs in an excited state thereof, wherein these excited electron-hole pairs can be referred to as excitons. When the excitons return to a ground state, the energy difference between the excited and ground states is emitted as visible light.
Organic electroluminescence display devices are classified into a passive matrix type and an active matrix type, according to their pixel driving schemes, and the devices are arrayed in an N×M matrix. In a passive matrix type organic electroluminescence display device, the anode and cathode electrodes are arranged perpendicular to each other, and the pixels are driven by line selection. In the active matrix type organic electroluminescence display device, a pixel electrode of each pixel, that is, a display region, is connected to a thin film transistor, and the voltage of the pixel is maintained by capacitance of a capacitor connected to the thin film transistor.
More specifically, in the active matrix type organic electroluminescence display device, each unit pixel includes a switching transistor, a driving transistor, a capacitor, and an electroluminescence (EL) element, such as a light emitting diode. A voltage supply line Vdd is provided as a common power source to the driving transistor and the capacitor. The voltage supply line Vdd controls the current through the driving transistor to the EL element. In addition, an auxiliary electrode line is provided as an auxiliary power source to a second electrode. The auxiliary electrode line provides a current by generating a potential difference between source/drain electrodes and the second electrode.
FIG. 1 is a cross sectional view of an exemplary active matrix type organic electroluminescence display device. Referring to FIG. 1, the conventional active matrix type organic electroluminescence display device 10 comprises a substrate 100 having panel and wire regions A and B, and a buffer layer 105. A semiconductor layer 110, comprising source/drain regions 110c and 110a and a channel region 110b, is disposed on the buffer layer 105 in the panel region A. In one embodiment, the source/drain regions 110c and 110a and the channel region 110b are formed by a patterning process.
The display device 10 further comprises a gate insulating layer 120 disposed over the semiconductor layer 110, and a gate electrode 130 corresponding to the channel region 110b formed on the gate insulating layer 120 in the panel region A. An interlayer insulating layer 140 is formed on the gate electrode 130 over substantially the entire surface of the substrate 100. Following formation of the interlayer insulating layer 140, source/drain electrodes 145 are connected to the source/drain regions 110c and 110a through contact holes 141 formed in the interlayer insulating layer 140 in the panel region A. The semiconductor layer 110, the gate electrode 130, and the source/drain electrodes 145 form a thin film transistor (TFT).
A first conductive pattern 147, comprising substantially the same material as that of the source/drain electrodes 145, is also formed in the wire region B. The first conductive pattern 147 forms the aforementioned auxiliary electrode line. Subsequently, an insulating layer 150, such as a passivation layer and a planarization layer, is formed on the source/drain electrodes 145 and the first conductive pattern 147, and over substantially the entire surface of the substrate 100. Next, the insulating layer 150 formed on the upper portion of the first conductive pattern 147 in the wire region B is removed by a lithography process, for example.
A via hole 155 is formed on the insulating layer 150 in the panel region A to expose one of the source/drain electrodes 145. A first electrode 170 is formed by a patterning process so as to contact the source/drain electrodes 145 through the via hole 155, and extend to the insulating layer 150.
Following formation of the first electrode 170, to the exclusion of the wire region B, a pixel defining layer 175 having an opening 178 is formed on the first electrode 170 and the insulating layer 150. Next, an organic layer 180, including at least an organic electroluminescent layer, is formed on the first electrode 170 exposed by the opening in the panel region A. The organic layer 180 may be formed, for example by a patterning process. A second electrode 190 is formed on the organic layer 180 over substantially the entire surface of the substrate 100. Thereby, the second electrode 190 in the wire region B is electrically connected to the first conductive pattern 147.
In some organic electroluminescence display devices, the first conductive pattern 147 comprises the same material as that of the source/drain electrodes 145 in the panel region A, and a line width of the first conductive pattern 147 may be large. The materials of the first conductive pattern 147, molybdenum (Mo), tungsten (W), and molybdenum tungsten (MoW), have a higher heat capacity than a silicon nitride (SiNx) layer of the insulating layer 150. The "heat capacity" of a substance is the amount of heat energy required to change its temperature by one degree, and has units of energy per degree. Because of the differences in heat capacity between the first conductive pattern 147 and the silicon nitride layer, the first conductive pattern 147 cannot effectively transfer heat to the silicon nitride layer. As a result, reflow is not effectively performed between each of the panel regions during the organic layer curing process. Thereby, the effects of the curing process are different between the panel regions of a display, causing the thicknesses of the organic layers to be different between the panel regions of the display. In addition, gases remaining in the organic layers may cause pixel shrinkage. Specifically, the out-gassing or gases remaining in an organic layer may result in deterioration of the organic electroluminescent layer of the display.
Furthermore, a small line width of the first conductive pattern 147 may cause IR drop at the second electrode. IR drop is a signal integrity effect caused by wire resistance and current drawn from power and ground grids. If wire resistance is too high or the cell current larger than predicted, an unacceptable voltage drop may occur. This results in poor performance and increased noise susceptibility.

Organic electroluminescence display device having auxiliary electrode line and method of manufacturing the same


A drainage catheter system, for draining fluids from body organs such as a kidney or a liver in patients whose natural drainage pathways are blocked, has a main drainage lumen and an obturator channel which may be integral with each other. This system can be easily exchanged for a new catheter system when the main drainage lumen of the initially placed catheter system becomes obstructed or occluded by encrusted deposits or tumor ingrowth. Catheter system exchange is initiated by withdrawal of a pre-installed obturator from the obturator channel of the catheter systems. Obturator withdrawal can be used to actuate release of a catheter loop-retaining thread or drawstring from its loop-retaining state in catheter systems which have pigtail loops. Once the obturator has been completely removed, a conventional flexible-tip guidewire is inserted through the now open or un-obturated, obturator channel. The occluded drainage catheter system is removed over the guidewire, a new (exchange) drainage catheter system is positioned by advancing its main drainage lumen along the guidewire, and the guidewire is removed from the new system. Loop formation and loop retention (for looped catheters), and body-external connection to a suitable drainage collector conclude the exchange of drainage catheter systems.

Various procedures have been described for the exchange of obstructed drainage catheters while maintaining access between the organ to be drained and the patient's skin surface through the original percutaneous tract, i.e., the original pathway of the very first drainage catheter installed in the patient. Descriptions of such prior art drainage catheters, and particularly descriptions of special methods and equipment developed for exchange of obstructed or occluded drainage catheters, indicate the frequent complexity of such exchange procedures and their attendant treatment times, likely patient discomfort and relative risk factors.
Representative descriptions of drainage catheter exchange procedures can be found in the following publications:
1) Use of flexible, 22-gauge Trocar Needle and an Obturator for Obstructed Drainage Catheter Exchange; G. L. McLellan; American Journal of Radiology, 151: 521-522; September 1988. PA1 2) Exchange of Occluded Catheters with Transcatheter and Pericatheter Maneuvers; A. S. Lee, E. van Sonnenberg, G. R. Wittich, G. Casola; Radiology, 163: 273-274; April 1987. PA1 3) Replacement of Obstructed Loop and Pigtail Nephrostomy and Biliary Drains; C. Cope; American Journal of Radiology, 139: 1022-1023; November 1982. PA1 4) Exchange of an Obstructed Loop Nephrostomy Catheter; F. C. Cazenave, M. C. Glass-Royal, K. H. Barth; Cardiovascular and Interventional Radiology, 13: 327-328; 1990.
In contrast to complex drainage catheter exchange procedures of the prior art, the present invention provides improved drainage catheter systems (method and apparatus) for easy exchange by means of a pre-installed obturator in an obturator channel, which may be integral to the catheter system, and which is installed as a part of the catheter system.
Accordingly, it is a feature of the invention to provide a drainage catheter system having at least one main drainage lumen for draining fluid from an organ whose natural drainage pathway is blocked, and having as a component of the catheter system an obturator channel sealed by an obturator which is removed just prior to exchange or replacement of an initially installed and obstructed or occluded drainage catheter system of the present invention by a new drainage catheter system of the present invention.
It is another feature of the invention to provide easy exchange of an obstructed or occluded drainage catheter system through the original percutaneous tract.
It is a further feature of the invention to provide the easy exchange of drainage catheter systems by use of a conventional flexible-tip guidewire.
It is a still further feature of the invention to provide release means associated with the obturator for releasing a drawstring or retaining thread from its catheter loop-retaining position, thereby freeing the catheter loop from retention and readying the drainage catheter system for the exchange procedure.
Briefly described, the present invention provides an easily exchanged drainage catheter system for drainage of fluids from organs such as, for example, a kidney or a liver, or from abscesses. When obstruction or occlusion of the main drainage lumen of the initially installed catheter system requires exchange or replacement, a sealingly fitting obturator is fully withdrawn from an obturator channel integral to the drainage catheter system. In accordance with an aspect of the invention, the obturator as it is withdrawn from the channel, firstly releases a taut drawstring or retaining thread or other retainer of the looped distal end of the drainage catheter. When withdrawn, the obturator provides an open or unobturated channel between the organ to be drained and the outside of the patient's skin surface. A conventional flexible-tip guidewire (of diameter slightly smaller than the diameter of the unobturated channel) is inserted through the open channel, preferably under fluoroscopic monitoring, and is advanced and manipulated so that the flexible tip is guided through the same aperture in the obturator channel which served as the aperture for the obturator, and for the retainer (e.g., the drawstring or loop-retaining thread). Upon completed guidewire advance, the occluded drainage catheter system is withdrawn over the positionally retained guidewire and discarded. An exchange or replacement drainage catheter system (having an obturator pre-installed in its obturator channel) is now inserted by advancing its main drainage lumen along the guidewire until properly positioned, as can be determined by fluoroscopic observation of the distal drainage section of the drainage catheter system within the fluid-collection space of the organ to be drained. The guidewire is withdrawn and the retainer is set. A loop-retaining thread or drawstring retainer is set by being tensioned and clamped so as to form and retain a loop-shaped end section of the drainage catheter system within the fluid-collection space of the organ. A fluid collection bag (or other suitable fluid collection means) is connected by a standard coupling (for example, a so-called Luer Lock) to the main drainage lumen.

Easy-exchange drainage catheter system with integral obturator channel


A light-guiding structure including a plurality of light pipes, a plurality of connecting portions and a fixing socket is provided. The light pipes are disposed on the fixing socket, and the light pipes are connected together by the connecting portions. At least one to-be-destroyed portion is formed between the connecting portions. In addition, the fixing socket has at least one destructive structure for disconnecting the connecting portions from each other by destroying the to-be-destroyed portion. Therefore, the interference caused by the light wave passing through the connecting piece is avoided.

1. Field of the Invention
The present, invention relates to a light pipe, and more particularly to a light-guiding structure for preventing the interference of light waves.
2. Description of Related Art
Generally, most electronic devices take the signal light emitted by light emitting diodes (LEDs) as the indicating signal to show current operation state of the electronic device. However, since the position where the LED disposed from the surface of the casing of the electronic device is usually separated by a distance, a light pipe must be used to transmit the signal light wave, and display it on the surface of the casing.
Referring to FIG. 1, it is a schematic view of the configuration of conventional light pipes. Each LED 100 is disposed on one end of respective light pipe 110, which emits light wave with a different wavelength such as red light, blue light, or green light. When the light wave is transmitted in each light pipe 110, the user can see from each end of light pipes 110 that the indicating lamp is ON or Off state, so as to determine the current operation state of the electronic device.
However, due to the limitation on formation, when the light pipes 110 are fabricated, the light pipes 110 are connected through the plasticizing process by the fixing connecting portion 120, such that the light pipes 110 can be fixed on a suitable position in the electronic device. However, it may cause the light wave transferring from a light pipe 110 to another light pipe 110 through the fixing connecting portion 120, as a result, the light waves are mixed and the light signals are irregular. Therefore, how to prevent the light waves emitted by the LEDs 100 from being transferred into another light pipe 110 is an urgent issue.


An image display apparatus including an image display unit, a light source unit, an illumination optical system configured to guide light from the light source unit to the image display unit, and a display optical system configured to guide light from the image display unit to a viewer is disclosed. With such an image display apparatus, luminance non-uniformity viewed at an exit pupil can be suppressed by intentional provision of uneven luminance distribution to an optical surface that receives light from the light emitting device of the light source unit.

1. Field of the Invention
The present invention relates to an image display apparatus. The image display apparatus according to the present invention is suitable for, for example, a head-mounted display (HMD) and eyeglass displays.
2. Description of the Related Art
Various image viewing apparatuses (image display apparatuses) that are worn on the head and allow image information displayed on an image display device (e.g., liquid-crystal display device) to be viewed as an enlarged virtual image, so-called head-mounted displays (HMDs), have been proposed.
Head-mounted image display apparatuses need to allow a viewer to view a realistic image with a wide angle of view and have a compact lightweight structure.
Among such apparatuses, a HMD that uses a reflective liquid-crystal display device is known (see, for example, Japanese Patent Laid-Open No. 2001-166252, No. 11-125791 (corresponding to U.S. Pat. No. 6,333,820), No. 11-337863 (corresponding to U.S. Pat. No. 6,023,373), No. 2000-010041, and No. 2002-244076 (corresponding to U.S. Pat. No. 7,081,999).
With recent advances in high-definition liquid-crystal display devices, liquid-crystal display devices that have as many pixels as, or even more than, existing displays while at the same time being more miniaturized than existing displays are being developed.
In order to enable a realistic image with a wider angle of view to be displayed using a miniaturized liquid-crystal display device, it is necessary to increase the magnification of a display optical system. However, an increase in magnification leads to an increase in size of the optical system, and inevitably, this tends to an increase in the size of the entire structure of the apparatus.
To miniaturize the optical system while attaining a wide angle of view and enabling display of a high-definition image, an effective way is to use a decentered optical system including an optical element that has a rotationally asymmetric surface.
However, the use of a decentered optical system is prone to cause luminance non-uniformity in an image viewed at an exit pupil of the display optical system.
Additionally, the ratio of light incident on the exit pupil at a viewer side to light that has been optically modulated by a liquid-crystal display device after having emerged from an illumination unit is reduced, and the efficiency of illumination tends to be decreased.
Therefore, in order to miniaturize the entire optical system and also enable a high-definition image with a wide angle of view to be obtained, an important factor is to appropriately set the structure of an illumination optical system for illuminating a liquid-crystal display device and the structure of a display optical system that guides light from the liquid-crystal display device to an exit pupil at a viewer side.


The assembly comprises a flexible bulb 12 defining a pumping chamber 14 and secured at opposite ends by bands 34 to inlet and outlet housings 26. An inlet check valve 18 is supported by an inlet valve wall 38, which is, in turn, supported in a recess 36 in the inlet housing, to control fuel flow to the pumping chamber 14 while preventing reverse fuel flow out of the pumping chamber 14. An outlet check valve 22 is supported by an outlet valve wall 52 which is, in turn, supported in a recess 36 in the outlet housing for controlling fuel flow from the pumping chamber 14 while preventing reverse flow from the outlet housing into the pumping chamber 14. The assembly is characterized by a pressure relief valve, generally shown at 24, disposed between the inlet and the pumping chamber 14 for allowing fuel under a predetermined pressure in the pumping chamber 14 to reverse flow into the inlet. The opposite ends differ only by the inlet valve wall 38 supporting the relief valve 24.

1. Field of the Invention
This invention relates to a hand-held primer assembly for introducing starting fuel into the intake system of an internal combustion engine.
2. Description of the Prior Art
It is well known to use a flexible bulb with an inlet check valve and an outlet check valve to prime an internal combustion engine by manually squeezing the bulb to pump fuel into the engine and to suck fuel into the bulb as it is manually released. Because of the outlet check valve, the downstream pressure can become very high. Some new engines, which are fuel injected, include a vapor separator and float assembly, including a needle valve which is very light and relatively delicate. In fact, unduly high fuel pressure between the bulb and the float assembly could damage the needle valve.
In order to overcome such high pressure in the past, to prevent flooding of the engine, separate return systems have been combined with the flexible bulb, as disclosed in U.S. Pat. No. 3,233,652 to Phillips.
However, there remains a need for a system to relieve such high back pressure without the need of a separate return to prevent overcharging of the engine.


A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by channel erasing to detrap the tunneling oxide of the flash EEPROM cell. The channel erasing consists floating the drain and the second diffusion well and concurrently applying the ground reference potential to the semiconductor substrate and the first diffusion well. Concurrently a first relatively large negative voltage pulse is applied to the control gate, as a first moderately large positive voltage pulse is applied to said source. The method to erase then proceeds with the source erasing to remove charges from the floating gate of the flash EEPROM cell. The source erasing consists of applying a second relatively large negative voltage pulse to the control gate of said EEPROM cell and concurrently applying a second moderately large positive voltage pulse to a first diffusion well. At the same time the ground reference potential continues to be applied to the semiconductor substrate, while the drain and a second diffusion well is allowed to float.

RELATED PATENT APPLICATIONS
Attorney's Docket Number TSMC97-125, "A Novel Method To Improve Flash EEPROM Write/Erase Threshold Closure," Ser. No.: 08/928,217, Filing Date: Sep. 12, 1997, assigned to the Same Assignee as the present invention.
Attorney's Docket Number TSMC97-126, "A Novel Method to Erase A Flash EEPROM Using Negative Gate Source Erase Followed By a High Negative Gate Erase," Ser. No.: 08/928,127, Filing Date: Sep. 12, 1997, assigned to the Same Assignee as the present invention.
Attorney's Docket Number TSMC97-085, "A Bi-Modal Erase Method For Eliminating Cycling-induced Flash EEPROM Cell Write/Erase Threshold Closure," Ser. No.: 08/927,472, Filing Date: Sep. 11, 1997, assigned to the Same Assignee as the present invention.
Attorney's Docket Number TSMC97-099, "A Novel Erase Method Of Flash EEPROM By Using Snapback Characteristic," Ser. No.: 08/957,678, Filing Date: Oct. 24, 1997, assigned to the Same Assignee as the present invention.
1. Field of the Invention
This invention relates generally to a class of non-volatile memory devices referred to as flash electrically erasable programmable read-only memory (flash EEPROM). More particularly, this invention relates to methods and means to erase digital data from a flash EEPROM cell and for eliminating trapped charges from the flash EEPROM cell.
2. Description of Related Art
The structure and application of the flash EEPROM is well known in the art. The Flash EEPROM provides the density advantages of an erasable programmable read-only memory (EPROM) that employs ultra-violet light to eliminate the programming with the speed of a standard EEPROM. FIG. 1a illustrates a cross-sectional view of a flash EEPROM cell of the prior art. The flash EEPROM cell 10 is formed within a p-type substrate 12. An n.sup.+ drain region 14 and an n.sup.+ source region 16 is formed within the p-type substrate 12.
A relatively thin gate dielectric 36 is deposited on the surface of the p-type substrate 12. The thin gate dielectric 36 will also be referred to as a tunneling oxide, hereinafter. A poly-crystalline silicon floating gate 32 is formed on the surface of the gate dielectric 36 above the channel region 34 between the drain region 14 and source region 16. An interpoly dielectric layer 30 is placed on the floating gate 32 to separate the floating gate 32 from a second layer of poly-crystalline silicon that forms a control gate 28.
A p.sup.+ diffusion 18 is placed in the p-type substrate 12 to provide a low resistance path from a terminal 20 to the p-type substrate. The terminal 20 will be attached to a substrate voltage generator Vsub. In most application of an EEPROM, the substrate voltage generator Vsub will be set to the ground reference potential (0 V).
The source region 16 will be connected to a source voltage generator VS through the terminal 22. The control gate 28 will be connected through the terminal 26 to the control gate voltage generator VG. And the drain region 14 will be connected through the terminal 24 to the drain voltage generator VD.
According to conventional operation, the flash EEPROM cell 10 is programmed by setting the gate control voltage generator VG to a relatively high voltage (on the order of 10 V). The drain voltage generator VD is set to a moderately high voltage (on the order of 5 V), while the source voltage generator VS is set to the ground reference potential (0 V).
With the voltages as described above, hot electrons will be produced in the channel 34 near the drain region 14. These hot electrons will have sufficient energy to be accelerated across the gate dielectric 36 and trapped on the floating gate 32. The trapped hot electrons will cause the threshold voltage of the field effect transistor (FET) that is formed by the flash EEPROM cell 10 to be increased by three to five volts. This change in threshold voltage by the trapped hot electrons causes the cell to be programmed.
During the programming process some of the hot electrons will be trapped 42 in the tunneling oxide 36 or in surface states 40 at the surface of the p-type substrate 12. These trapped electrons will cause the threshold voltage of the erased flash EEPROM cell 10 to increase.
To erase the flash EEPROM cell 10 as described in U.S. Pat. No. 5,481,494(Tang et al.), as shown in FIG. 2a, a moderately high positive voltage (on the order of 5 V) is generated by the source voltage generator VS. Concurrently, the gate control voltage generator VG is set to a relatively large negative voltage (on the order of -10 V). The substrate voltage generator VS are set to the ground reference potential. The drain voltage generator VD is usually disconnected from the terminal 24 to allow the drain region 14 to float. Under these conditions there is a large electric field developed across the tunneling oxide 36 in the source region 16. This field causes the electrons trapped in the floating gate 32 to flow to portion of the floating gate 32 that overlaps the source region 16. The electrons are then extracted to the source region 16 by the Fowler-Nordheim tunneling.
Further Tang et al. shows a method for tightening the threshold voltage VT distribution of an array of flash EEPROM cells. The moderately high positive voltage (5 V) that is applied to the source regions of the array of flash EEPROM cells and the relatively large negative voltage that is applied to the control gate insure a tighter distribution of the thresholds of the array of cells. The value of a load resistor between the low positive voltage and the source region is simultaneously reduced to a predetermined value so as to compensate for the increased erase time caused by the lowering of the magnitude of the negative constant voltage.
Referring back to FIG. 1a during the erasure process, some positive charges 38 will be forced and trapped in the tunneling oxide 36. These trapped positive charges 38 will cause the threshold voltage of the programmed flash EEPROM cell 10 to decrease. As can be shown in FIG. 3a, after repeatedly performing write/erase cycling, the combination of the decrease 52 in the programmed threshold voltage 50 and the increase 57 in the erased threshold voltage 55 will cause the separation of the programmed threshold voltage 50 and the erased threshold voltage 55 to close until the flash EEPROM cell 10 fails. At this time the flash EEPROM will no longer be able to operate reliably to store digital data.
Another illustration of the impact of the trapped charges is shown in FIG. 3b. FIG. 3b shows the drain current I.sub.d versus the voltage V.sub.g at the control gate for the cell of FIG. 1b. The set of curves 60 are for a cell that has been erased, while the set of curves 62 are for a cell that has been programmed. As can be seen, after 100K cycles of writing and erasing, the drain current I.sub.d will decrease for a given control gate voltage V.sub.g. Further FIG. 3b shows the change of transconductance G.sub.m versus the voltage V.sub.g at the control gate for the cell of FIG. 1b. The set of curves 64 are for a cell that has been erased and the set of curves 66 are for a cell that has been written. Again, as can been seen, having been exposed to 100k cycles of writing and erasing will cause the transconductance G.sub.m to shift for a given control gate voltage V.sub.g.
U.S. Pat. No. 5,485,423 (Tang et al.) as shown in FIG. 2b, describes a method of erasure of a flash EEPROM. A moderately large positive voltage pulse is generated by the source voltage generator VS. Simultaneously, a negative ramp voltage is developed by the gate control voltage generator VD. The drain voltage generator VG will be disconnected from the drain to allow the drain to float and the substrate voltage generator will be set to the ground reference potential as above described. This method will achieve an averaging of the tunneling field during the entire erase cycle.
U.S. Pat. No. 5,521,866 (Akaogi) and as shown in FIG. 1b describes non volatile semiconductor memory device having a floating gate 30. The memory device is constructed with a n-well 47 diffused into the semiconductor substrate 12 and a p-well 45 diffused into the n-well 47. The source 18 and drain 14 are then diffused into the p-well 45 with a floating gate 30 and control gate 28 disposed on the surface of the semiconductor substrate much as described in FIG. 1. The erasure process involves applying a positive voltage to p-well 45 and the n-well 47.
U.S. Pat. No. 5,596,528 (Kaya et al.) describes a method to program a flash EEPROM array will provide a narrow distribution of threshold voltage. The method eliminates the drain-column line loading effect and overcomes word line stress approach because high voltages are eliminated from the wordlines. The gate compaction is accomplished by reverse biasing the source and the substrate. This limits the channel currents in individual cells. If a cell loses its charge it will be restored by this method.

Mixed mode erase method to improve flash eeprom write/erase threshold closure

Taiwan Semiconductor Manufacturing Company, Ltd.


One embodiment disclosed relates to a computer system. The computer system includes a microprocessor, an operating system, and a memory system. The microprocessor includes a register stack and a register stack engine (RSE), and the operating system includes a kernel. The memory system is configured to have a single memory page that includes both a kernel stack and an RSE stack. The memory system may be further configured such that the kernel stack and the RSE stack grow in opposite directions and such that a uarea data structure is located between those two stacks.

1. Field of the Invention
The present invention relates generally to microprocessors and operating systems.
2. Description of the Background Art
It is common for a computer processor and associated operating system (OS) to have two different levels of resources and protection. One level is referred to as a non-privileged mode or user mode. This mode is typically used by various operating system components, application programs, and other so-called "user" processes or programs. At this level, an execution thread is prevented by the operating system and by the computer processor from performing certain security-critical operations. The thread is also prevented from directly accessing many system resources. The purpose of the non-privileged execution mode is to isolate a user process as much as possible so that it cannot interfere with other user processes or with operating system functions. While a user process may itself crash, it should not be able to crash other programs or the operating system.
The other level of execution is referred to as privileged mode, system mode, or kernel mode. Critical operating system components are implemented in kernel mode. Kernel-mode components are responsible for things like virtual memory management, responding to interrupts and exceptions, scheduling execution threads, synchronizing the activities of multiple processors, and other critical or sensitive functions. Such components, which execute from system mode, are sometimes generally referred to collectively as "the kernel."
The kernel is responsible for supervising the virtual memory system in most computer systems. The virtual memory system is largely responsible for isolating processes from each other. With virtual memory, a process is assigned its own virtual address space, which is not available to other processes. Through its virtual memory, a process has a logical view of memory that does not correspond to the actual layout of physical memory. Each time a process uses a virtual memory address, the virtual memory system translates it into a physical address using a virtual-to-physical address mapping contained in some type of look-up structure and address mapping database.
FIG. 1 shows certain components of a conventional computer system. The illustrated components of the computer system 40 include a microprocessor 41 and a computer-readable storage medium such as memory 42. Although FIG. 1 shows only a single processor, the system might include multiple processors. The multiple processors may be used by multiple different processes or tasks, each having one or more execution threads. The terms task and process as used in this description refer to executing entities within a computer system having their own virtual address spaces. A thread is characterized as having its own context (including registers and memory stack) and as being independently subject to the kernel's scheduling algorithms. The computer system 40, of course, also includes other components that are not shown.
In accordance with conventional computer systems, the computer system 40 includes an operating system and one or more application or user programs that execute in conjunction with the operating system. FIG. 1 shows a portion 43 of the operating system referred to as the kernel, and a single application or user process 44. Although only one user process is shown, a plurality of user processes typically execute from memory 42. As described above, the processor 41 may operate using privileged and non-privileged execution modes. User processes and threads typically run in the non-privileged execution mode, and make calls to system or kernel functions that execute in the privileged execution mode. Additional kernel functions and threads also run in the privileged execution mode to deal with memory faults and other interrupt-based events in accordance with conventional operating system characteristics.
Memory in a computer typically comprises a linear array of bytes. Each byte has a unique address known as its physical address. However, many microprocessors do not typically address memory by the memory's physical address. Instead, memory is addressed using virtual memory addresses. A virtual memory address, which is commonly known as a virtual address, is an address of a location in virtual memory.
Virtual memory addressing is a technique used to provide the illusion of having a memory space that is much larger than the physical memory available in a computer system. This illusion allows a computer program to be written without regard to the exact size of physical memory. One benefit of virtual memory addressing is that a computer program can easily run on a computer with a wide range of memory configurations and with radically different physical memory sizes. Another benefit is that a computer program may be written that uses a virtual memory size that is much larger than the physical memory available on a particular computer system.
Virtual memory may be thought of as a collection of blocks. These blocks are often of fixed size and aligned, in which case they are known as pages. A virtual address may often be broken down into two parts, a virtual page number and an offset. The virtual page number specifies the virtual page to be accessed. The offset indicates the number of memory bytes from the first memory byte in the virtual page to the addressed memory byte. Physical addresses, which represent where data actually resides in physical memory, may also be broken down into two parts, a physical page number and an offset. The physical page number specifies the physical page to be accessed. The offset indicates the number of memory bytes from the first memory byte in the physical page to the addressed memory byte.
A virtual address must be mapped into a physical address before physical memory may be accessed. The mapping is often maintained through a table, known as a page table. The page table contains virtual to physical memory translations. A virtual to physical memory translation consists of a virtual page number and a corresponding physical page number. Because virtual addresses are typically mapped to physical addresses at the level of pages, the page table may be indexed by virtual page numbers. In addition to virtual to physical memory translations, the page table may often contain other information such as the disk locations where pages are stored when not present in main memory and an indication of whether pages are present in memory or residing on a disk. Typically, the operating system inserts and deletes the virtual to physical memory translations that are stored in the page table. In other words, the page table is managed by the operating system.
Virtual memory requires two memory accesses to fetch a single entry from memory. The first access is into the page table. This access is used to map the virtual address into the physical address. After the physical address is known, then a second access is required to fetch the data. In an effort to speed up memory accesses, conventional microprocessors use a special-purpose cache memory to store certain virtual to physical memory-translations. This special-purpose cache memory is often called a translation lookaside buffer (TLB). The number of virtual to physical memory translations in a TLB is typically smaller than the total number of translations in the page table.
When a microprocessor addresses memory through a TLB, the virtual page number that is included in the virtual address is used to interrogate the TLB. If the virtual page number is stored in the TLB, then the TLB outputs the physical page number that maps to the virtual page number. Sometimes the TLB does not contain the virtual page number. This is known as a TLB miss. When a TLB miss occurs, the microprocessor typically requests the operating system to supply the physical page number from the page table. After the operating system supplies the physical page number, the physical memory is addressed. When the operating system supplies the physical page number, an undesirable delay occurs.
A memory stack is a region of reserved memory in which programs store status data such as procedure and function call return addresses, passed parameters, and local variables. The microprocessor, the program, and the operating system can all maintain one or more separate memory stacks.
Logically, a stack may comprise a memory structure organized, for example, as a LIFO (last in, first out) list such that the last data item added to the structure is the first item used. A program can put data onto the stack by executing microprocessor instructions. For example, a "push" instruction typically writes a specified microprocessor register to the stack. A "pop" instruction reads data from the stack. The microprocessor often writes to and reads from the stack automatically in response to certain program flow instructions and other events such as memory faults or interrupts.
As shown in FIG. 2, a memory stack (whether a user memory stack or a kernel memory stack) is typically implemented as a region of virtual memory beginning at a stack base or stack base address. FIG. 2 shows a portion of virtual memory from top to bottom in order of increasing virtual memory addresses. The memory stack is indexed by a pointer referred to as the "stack pointer." When writing to the stack, the microprocessor decrements the stack pointer to the next available address, and then writes the specified data to that address. When reading from the stack, the microprocessor reads from the virtual memory location currently referenced by the stack pointer, and then increments the stack pointer.
A register stack may comprise a number of general registers of a microprocessor, which have been designated for the storage of data required by, and pertaining to, procedures of a stored program being executed by the microprocessor. Specifically, upon execution of a particular procedure, a stack frame associated with that procedure is created within the register stack. The stack frame includes saved registers (containing variables local to relevant procedure), an activation record and a frame marker. When a procedure calls a further procedure, the called procedure in turn creates a further stacked frame on top of the stacked frame for the calling procedure. Accordingly, for a program in which a number of nested procedures are being executed, the register stack may include a corresponding number of stack frames.
A register stack accordingly allows multiple procedures to effectively share a large register file by stacking associated stack frames in both on-chip registers and off-chip memory. The call/return patterns of typical programs exhibit high call/return frequencies with small amplitudes. A register stack significantly reduces the number of stores (i.e., register saves) at procedures calls, and reduces the number of loads (i.e., register restores) at procedure returns.
In accordance with some microprocessors, a register stack engine (RSE) may be used to manage the register stack, saving and restoring the physical registers to and from memory as needed. The memory allocated for the dynamic reading and writing of the registers by the RSE is sometimes called the backing store.

Memory stack architecture for reduced TLB misses

Hewlett-Packard Development Company, LP.


The invention is a method for conducting an interactive lottery game. The game players select both an integer N and a rank R for that integer during a series of game playing intervals. The selections are entered into a computerized tallying database along with a unique personal identifier for each player. The database tabulates all player's selections and generates a most frequently selected rank R and an associated integer N for each playing interval. A game winner is determined by comparing every player's selection of integer N and rank R for each game interval with the most frequently selected rank R and associated integer N for each game interval. A prize is awarded to the winning player.

Lottery type games are well known throughout the world, attracting large numbers of players by offering large prizes. In general, players pick a selection of numbers from a defined range of numbers. Then, at a later time, another single selection of numbers from that defined number range is randomly made. The individual or individuals having made a selection of numbers matching the single randomly made selection is declared the winner and receives a prize.
A number of innovations have been developed relating to various games that allow a large number of individuals to participate with an opportunity to receive a prize. The following U.S. patents are representative of some of those innovations.
Berman et al., in U.S. Pat. No. 5,108,115, disclose an interactive communication system for game participants. Game show audience members and home viewer members pick six numbers from a total pool of numbers. Six random numbers are then selected from the pool, with an individual's selection that matches the random selection winning a prize.
In U.S. Pat. No. 5,213,337 Sherman describes a device for playing a game that receives audio signals from a broadcast, then processes the signals to present questions to the player, the questions based on the content of the broadcast.
Yamamoto et al, in U.S. Pat. No. 5,265,888, disclose a computer game apparatus having selectable levels of difficulty which may be chosen by the individual players.
In U. S. Pat. No. 5,297,802 Pocock et al. describe a televised bingo game system for viewer participation. The players use telephone communication to participate. The system is designed to be totally automated, and has no staff to accept player entries or to operate the televising of the game.
Latypov, in U.S. Pat. No. 5,423,556, discloses an interactive computer game employing a digital computer system with a display and an interactive means for communicating user input to the computer system. The user is given a set time interval to arrange an array of elements on the display to form a predetermined pattern of the elements.
In U.S. Pat. No. 5,545,088 Kravitz et al. describe a television game interactively played by home viewers, a studio audience and on-stage contestants. The game is similar to bingo with the numbers chosen randomly or selected by the contestants upon correctly answering a question.
Fuchs, in U.S. Pat. No. 5,630,753, discloses a gaming machine having a computing unit that displays various symbols. The computing unit predicts the probability of a future occurrence based on the present status of a game.
In U.S. Pat. No. 5,679,075 Forrest et al. describe an interactive multi-media game system where players solve puzzles to progress through a game maze in order to solve a global meta-puzzle.
Fennell, Jr., et al., in U.S. Pat. No. 5,695,400, disclose a method of managing user inputs and displaying outputs in a multi-player game that is played on a plurality of terminals on a network in a manner that compensates for differences in network latency among different terminals.
Thus, it can be seen that for many of the above inventions, the winner or winners are determined strictly based on random probability. In other inventions, the quick recall of facts or the capacity for manual dexterity are responsible for determining the winner. Thus, there exist an unmet need for an interactive game where the input of each player has an effect on determining the outcome of the game, and accordingly the winner or winners.


Disclosed herein are compositions that include oxygen, a sugar or sugar alcohol, and an amino acid, wherein the amino acid is present in an amount sufficient to stabilize the oxygen. Also provided are aqueous diagnostic quality controls or calibration reagents and methods of stabilizing oxygen in a liquid solution.

Aqueous diagnostic quality controls and calibration reagents generally must be stored at 2-8° C. due to the instability of oxygen (pO2) at room temperature. Users may require assays to be performed where refrigeration is not available nearby making expansion of the storage temperature range to 2-30° C. preferable. Thus, storage at 2-8° C. is often times not sufficient for storing diagnostic quality controls and calibration reagents.

Compositions comprising stabilized oxygen and methods of forming the same


Systems and methods for managing a backup process of a database are disclosed. Typically, one or more backup logical unit numbers (LUNs) are identified in a backup management file from one or more available LUNs identified in a universe file are allocated. The backup management file comprises a plurality of data containers, each data container specifying a subset of the one or more backup LUNs capable of backing up a database comprising one or more used database LUNs. One of the plurality of the data containers are allocated for a current backup of the database as indicated in the backup management file. The backup management file is checked and updated as necessary so that the one or more backup LUNs remain available as indicated in the universe file.

1. Field of the Invention
This invention relates to systems and methods for computer storage. Particularly, this invention relates to systems and methods for dynamically determining and managing multiple volumes in a data backup system.
2. Description of the Related Art
Storage management systems are increasingly relying on exploiting storage subsystems and storage subsystem technologies to backup and restore data in a fast, non-intrusive manner. One example is found in the product suite of IBM Tivoli Data Protection For Hardware which utilize IBM Enterprise Storage Server (ESS) subsystems to create backups for databases and applications such as DB2, ORACLE and mySAP. A primary characteristic of this data is that it is typically managed outside of the context of the traditional storage management server, e.g., outside of the context of the TIVOLI storage manager server. In other words, the storage is generally not seen or controlled by the backup server.
One of the first tasks for a user of such a system is to describe the storage that is available from the storage subsystem for use by the local storage management client. For example, the user may have fifty logical unit numbers (LUN) which can be dedicated to the backup application and must be made known to the backup application. Another task for the user is to create a correspondence between a LUN which contains production data (i.e. a source LUN) and another similar LUN (e.g., identical in size and possibly other characteristics) that can contain the backup (i.e. a target LUN). These backups are usually the result of a hardware copy operation (e.g., FlashCopy) from a source LUN to a target LUN.
The original IBM TIVOLI data protection for hardware products introduced the concept of a FlashCopy target file (usually denoted as ".fct" file). The original .fct files were simple text files that comprised one or more pairs of ESS serial numbers. The first serial number in the pair represented a database/application source LUN and the second number represented a target LUN for a FlashCopy operation. When the backup application determined that application data was stored on a source LUN, it would search through the file for the entry which listed the source LUN serial number and chose the paired target LUN serial number as the recipient of the FlashCopy operation. This technique has several drawbacks.
For example, one drawback is that the user must have explicit knowledge (identifying number and size) of which source LUNs are being used by the database application. This means that the user would have to ask the database and/or storage administrator for a list of the LUNs currently being used by the database.
Another drawback is that the target LUN must be preassigned to backup host outside of the context of the backup application. The user would need to determine which host would be used for the backup operation and ensure that the target LUN were already preassigned to that host.
Furthermore, the source-target LUN pairs must be pre-matched by the user. The user would have to know the requirements for matching source-target LUN pairs based on the storage subsystem. For example, the particular IBM ESS subsystem being used requires that either the source and target LUNs be equal in size or the source and target LUNs must be controlled by the same logical control unit which was represented in part of the LUN serial number.
Also, the user must be explicitly aware when the list of source LUNs changes and any changes to the source LUN set must be reflected back in the file. An example of these requirements is that if a DB2 database grows and is using more source LUNs, the user must be aware that this happened and enter a source-target LUN pair for the new source LUN in the .fct file. In addition, conventional systems are also constrained because the source LUN can be associated with only one target LUN and the .fct file allows for only a single backup version to be managed.
One improvement was made to the .fct file when the data protection products began to allow and manage multiple backup copies and the concept of a data container was introduced. The data container was basically a way to group a set of source and target LUN pairs into a logical set. A source LUN serial number could appear in multiple data containers, each entry having a unique LUN pair. With this format, when the backup application would request a container which represented a set of LUN which could contain a backup. The backup application managed the usage of these data containers in such a way that a subsequent request for a data container would yield a different set of source and target LUN pairs which would describe a second copy of the backup data. Unfortunately, this system only addressed the problem of being limited to a single backup version.
In view of the foregoing, there is a need in the art for systems and methods for storage management where the user need not have explicit knowledge (identifying number and size) of the source LUNs. There is also a need in the art for such systems and methods where the target LUN need not be preassigned to backup host outside of the context of the backup application. Further, there is a need for such systems and methods where the source-target LUN pairs need not be pre-matched by the user. As detailed hereafter, these and other needs are met by embodiments of the present invention.

Dynamically determining and managing a set of target volumes for snapshot operation

International Business Machines Corporation


A video recorder for recording a program video in a built-in HDD (hard disk drive) or the like on the basis of EPG data is easily put in a reserve-recording mode. To this end, reserve-recording candidate data is generated from the EPG data with use of recorded program information to facilitate selection of the reserve-recording mode. In a method for reserve-recording a broadcast program, similar program information is extracted from the EPG data on the basis of recorded title data held as the recorded program information, the extracted similar program data is converted to a data format usable for the reserve-recording, and is stored as reserve-recording candidate data upon reserve-recording.

The present invention relates to a method for reserve-recording a program to be reserved such as a TV program, and more particularly to a technique which is effective when reserve-recording is carried out with use of a recorded title (program).
A digital video recorder such as a DVD (digital versatile disc)/HDD (hard disk drive) recorder shows signs of its spread in these years. Such a digital video recorder having a function of reserve-recording a broadcast program based on an EPG (Electronic Program Guide) can automatically record a TV program by previously selecting a program reservation mode.
Program data obtained from the EPG covers about one week (seven days) from the current time, and a desired TV program is reserve-recorded by browsing the EPG and selecting data about the desired program.
One of conventional digital broadcast receivers, can automatically reserve and output a next-time program on the basis of a user's past view history, for example, as disclosed in JP-A-10-229526.

Video recorder and method for reserve-recording a broadcast program