A pressure swing and temperature swing adsorption system is disclosed which continuously purges contaminants such as nuclear, biological and chemical warfare agents from intake air and provides cool clean air to the crew compartment of a vehicle by progressively directing contaminated air through a first adsorption bed to clean the air, while simultaneously directing hot exhaust gases at about 600.degree. F. through a second adsorption bed for purging contaminants therefrom, while simultaneously cooling a third adsorption bed for enhancing adsorption of contaminants in the purging bed upon repeating the cycles of operation.

1. Field of the Invention
The present invention relates to method and apparatus for purifying and thereafter continuously controlling the temperature of a three bed PSA/TSA filtering system which receives air containing hazardous nuclear, biological and chemical warfare agents, and supplying cool clean air to personnel within the crew compartment of a combat vehicle or the like by use of combined pressure swing and temperature swing adsorption technology.
2. Description of the Prior Art
Assignees Veltman et al U.S. Pat. Nos. 4,732,579 and 4,793,832 disclose air purification and temperature controlling systems and methods which use only pressure swing adsorption systems that include two adsorption beds.

Pressure and temperature swing adsorption system


A communication apparatus includes an automatic reception stop circuit. When a transmit frame sent by another communication apparatus is received, the automatic reception stop circuit compares the specific code included in the transmit frame with the values written to the register beforehand. Based on the results of this comparison, the automatic reception stop circuit stops the reception of the transmitted frame that is considered useless by the communication apparatus.

The present invention relates to a communication control circuit for transmission and reception of data, and in particular, to an interface control LSI apparatus for an industrial measurement communication network "field bus".
FIGS. 9 and 10 show an outline of a communication apparatus using a conventional field bus.
In a communication system using a field bus as shown in FIG. 9, each of measurement and control equipments 911, 912, 913 with communication stations to which measurement blocks 908, such as programmable controller, pressure transmitter or flow transmitter, are attached, is connected to a pair of transmission paths 904 to mutual transmission and reception.
A communication block 907 in the measurement and control equipment with a communication station 911 comprises a bus interface circuit 903 connected to a transmission path 904, an interface control circuit or a modem circuit 901, and a host processor or a microcontroller 902 for controlling the interface control circuit 901.
The microcontroller 902 reads the measured values, manipulates actuators, and displays/instructs to external input/output devices relative to the measurement and control block 908.
The microcontroller 902 writes and reads transmit and receive data to and from the interface control circuit 901. During transmission, the interface control circuit 901 outputs TxD and a driver circuit 905 sends this signal out to the transmission path 904.
During reception, a receiver 906 outputs the signal on the transmission path 904 to the interface control circuit 901 as RxD.
When a signal is present on the transmission path 904, the receiver 906 outputs a CD signal to the interface control circuit 901.
FIG. 10 shows a detailed block diagram of the interface control circuit 901.
The microcontroller 902 writes transmit byte (8 bits) data to a transmit FIFO (First In First Out) 1006 in the interface control circuit 901 via a CPU interface 1017.
The interface control circuit 901 monitors the state of the transmission path 904 via a bus interface circuit 903 using the CD signal, and if no other communication station, e.g. 912 and 913, is sending a transmission, a transmission may be initiated.
A series of transmission operations is performed by a transmit state machine 1022 built in the interface control circuit 901, while the microcontroller 902 writes transmit data to a transmit FIFO 1006.
The interface control circuit 901 converts 8-bit byte data (parallel data) into serial data (1018), and adds a preamble and a start delimiter to the beginning of the data as well as 16-bit CRC and an end delimiter to the end of the data in order to form a transmit frame (1020).
These specially added codes are used at the receiver to match the length of one bit, detect the first and last byte positions of the frame, and check the presence of an error.
FIG. 11 shows the structure of a frame. The start and end delimiters include a special code to be differentiated from other components, but the preamble, data and CRC are formed of logical values 1 and 0.
The frame to be transmitted is encoded into Manchester codes (1021), which are then converted into voltage waveforms on the transmission path 904 by the driver circuit 905 in the bus interface circuit 903.
The control equipment with a communication station 911 and the other control equipments with communication stations 912 and 913 normally wait for a reception. When one communication station starts transmission, the voltage waveform on the transmission path 904 is converted into a digital signal (RxD) by the receiver circuit 906 in the bus interface circuit 903, and this digital signal (RxD) is received by the interface control circuit 901.
In FIG. 10, a series of reception operations is performed by a receive-state machine 1005. The received signal is Manchester-decoded (1010); the preamble and the start and end delimiters are removed (1015); and the CRC code is checked for errors (1013).
The serial data is sequentially converted into 8-bit byte data (1011), which is then stored in a receive FIFO 1007.
Once a specified number of bytes of the receive data has been accumulated in the FIFO 1007, an interrupt generator (1024) generates an interrupt signal (INT) to the microcontroller 902 to inform it of the presence of the receive data, and the microcontroller 902 reads the data from the receive FIFO 1007.
Since there are other causes for the generation of the interrupt signal (INT), an interrupt cause status register 1008 indicating a cause of generation of the interrupt signal (INT) is provided to allow the microcontroller 902 to read this register to find the cause of the interruption.
Only the data portion of the receive frame is stored in the receive FIFO 1007, and the CRC code is not written to the FIFO 1007 except in special cases.
After detecting the presence of the receive data, the microcontroller 902 reads the data from the receive FIFO 1007. FIG. 12 shows the main timings for a receiving operation.
The writing to the receive FIFO 1007 is carried out 2 bytes after the data is loaded because the 2-byte CRC code following the data is not written to the FIFO 1007. The modem circuit does not know the length of the data beforehand, so it can not identify the boundary between the data and the CRC code.
Thus, a 16-bit shift register 1012 is provided between a Manchester decoding circuit 1010 and a serial/parallel conversion circuit 1011, so that the first byte of data is written to the receive FIFO 1007 after the third byte of data has been received, and the writing to the FIFO is completed when the end delimiter is detected. Consequently, when the end delimiter is detected, the two bytes preceding the end delimiter are determined to be a CRC code to prevent it from being written to the FIFO.
As shown in FIG. 12, if it is assumed that a threshold for the receive FIFO 1007 is 2 bytes and that the interrupt signal is generated when 2 bytes of data have been accumulated therein, an interruption occurs after the reception of the fourth byte of data, and the microcontroller 902 subsequently notes the presence of the receive data.
Data to be transmitted is not necessarily required by all the stations that are receiving the data.
Even if the communication station does not require the received data, the microcontroller 902 reads the received data to determine whether it is unnecessary, and if so, it outputs a reception stop instruction via a control register 1009 in order to suspend the receiving operation.
FIG. 13 shows a flow chart describing a receiving operation and the stoppage of the reception of the unnecessary data. Namely, data is transferred to FIFO from a condition of "wait for reception" through the operations of "detect received signal", "detect bit synchronization" and "detect byte synchronization".
When the number of data in FIFO comes to a predetermined threshold value, interruption occurs, so that the host processor knows the presence of the data in FIFO. As a result, the host processor reads the data in FIFO and determines if the data is required in the station. If the data is unwanted, the host processor outputs a stop reception signal through the control register 1009 and suspends the data reception operation. If the data is wanted, the reception of the data is continued.
After the reception has been stopped, the reception stop state is maintained until the receive frame has been finished. Once the receive frame has disappeared, the station returns to a reception wait state.
According to the conventional communication apparatuses, all the stations other than a transmitting station which are ready for reception receive data irrespective of whether the data is unwanted, and the host processor reads the receiving data accumulated in the receive FIFO to determine whether the read data is unwanted.
Thus, whenever other stations carry out transmissions, the host processor is activated and consumes power.
In addition, a certain amount of time must pass before the reception stop instruction is issued by the host processor. The example shown in FIG. 12 can not stop the reception before 4 bytes of data portion of the receive frame are received.
This invention has been made in view of the above points, and its object is to maintain the host processor in a sleep mode until the required receive frame has reached the communication station in order to reduce the power consumed by the communication apparatus.

Communication system with data comparison circuit


Systems and methods herein obtain snapshots of one or more applications, while having minimal impact on performance of the applications. Embodiments may involve obtaining snapshots of modified application data within a node without disturbing the operations of the application. Systems may be configured to leverage the fast characteristics of local storage devices while utilizing the advantages provided by the remote storage of data. One or more applications may be preconfigured to record data modifications in one or more associated application state storages located on local memory. Further, one or more systems may operate in the background to identify modifications made to the associated application state storages and to determine an appropriate moment to take one or more snapshots of the stored data and transfer the one or more snapshots to one or more remote locations to be stored. Several factors may be used to determine when an appropriate moment has occurred.

Computing devices execute applications and/or processes. In execution, the applications perform computations, input and output information, etc. all of which generates data. The data can be stored on a storage device local to the computing device or a system remote to the computing device. At any point in time, a computing device may experience a failure and lose the generated data, which may be catastrophic to the application and its users. As such, the industry has developed data recovery systems and methods in order to recover lost data in the event of a partial or complete device failure.
Traditional data recovery systems and methods may be grouped into one of two categories: local data recovery systems and remote data recovery systems. In both types of traditional data recover systems, the individual applications are tasked to be in operational command of the data backup operations, and in doing so, the applications periodically save their current application state. In local data recovery systems, the applications are configured to locally store the changes to the application state or possibly all of its state. In this approach, the application's current state is kept on a local storage device, which may be ideal for application performance and latency reduction; however, this traditional local storage approach requires that the applications dedicate large amounts of space on a storage device local to the computing device to store extra copies of the application data at various points in time. Over time, this sacrificed storage space becomes burdensome and cost prohibitive.
Further, this local recovery method becomes ineffective in the event of a device failure. As explained above, in traditional methods, the applications may save their state to local storage and thus effectively keep the changes to the application state on the local storage device. As such, if the computing device fails, then the local storage device storing the application's states likewise fails, and the data therein is lost. As such, when a device failure occurs, the lost data cannot be recovered.
In light of the inherent shortcomings of the traditional local recovery methods, the industry developed remote recovery systems and methods. In remote data recovery systems and methods, the applications are modified to coordinate with an external data recovery method employed by a storage device remote to the computing device. Moreover, the applications are further modified to periodically save its application state to the remote storage device. However, storing the application state to remote storage causes a new set of problems for the local device and its applications. For example, the application must be modified to send its data to a specific remote location. These modifications are time consuming and complicate the applications. Further, not all applications are modifiable, and as such, the remote recovery solution leaves may applications vulnerable to data loss. Further still, because each application must be modified to communicate with a specific remote system, upgrading a device and adding applications to the device becomes cumbersome and time consuming.
Another drawback of the remote recovery methods is latency. Because the application needs to periodically store its application state remotely, the transmission of the application's state information is in the critical path of the application performance. As such, when the application makes a record of the application's state, it sends the application state to a remote location for storage. Transmitting the application state causes a noticeable lag time in the application's execution because transmitting the application state to a remote storage location takes much more time than storing the application state on a local storage device as was done in the traditional local recovery method.
To resolve this lag time problem caused by traditional remote recovery systems, some traditional remote recovery systems reduced the frequency of creating application states and transmitting the application state the remote location. However, reducing the frequency of transmitting the application states makes the system device more vulnerable to data loss because a long amount of time may have lapsed between the transmission of the latest application state and the device failure. As such, to reduce the data loss vulnerability, some traditional remote recovery methods increase the frequency of transmitting the application states. Yet, increasing the frequency of the remote transmissions circles back to the original problem of traditional remote recovery systems, which increases application latency and causes the user to experience lag time while running the application.

Systems and methods for providing snapshots of applications to remote locations with minimal performance impact


A controller controls switching between a braked state in which a movable meshing part 7 comes close to and meshes with a motor meshing part 6 and a brake released state in which the movable meshing part 7 is separated from the motor meshing part 6.

There is proposed a motor with a brake including a brake that applies a braking force to the motor shaft so as to obtain a higher braking force. The motor with the brake generates the braking force by allowing a first plate (friction plate) integrally rotating with the motor shaft to contact a second plate by a plate driving mechanism. The second plate is provided with a rotation block mechanism that blocks rotation about a motor axial line so that the first plate and the second plate are brought into contact with each other at portions on an outer side as far as possible in a radial direction to thereby generate the braking force (refer to PTL 1: JP-A-2016-127611).


This invention relates to a position/orientation measurement apparatus which can measure a position and orientation while achieving both high stability and precision. An image including indices laid out on a space is captured, and the indices are detected from the captured image. When a plurality of indices are detected, their distribution range is calculated, and an algorithm to be applied in position/orientation calculations is selected according to the size of the range (S3033, S3050, S3060). For example, when the indices are distributed over a sufficiently broad range, six parameters of the position and orientation of an image capture device are calculated as unknowns (S3070). As the distribution range of the indices becomes smaller, the degrees of freedom of unknown parameters to be calculated are reduced (S3035, S3025).

In recent years, extensive research has been conducted on mixed reality, which aims at seamless merging of physical and virtual spaces. An image display apparatus which presents mixed reality can be implemented as an apparatus which displays an image obtained by superimposing images of a virtual space (virtual objects, text information, and the like rendered by computer graphics), which are generated according to the position and orientation of an image capture device onto an image of a physical space captured by an image capture device such as a video camera or the like.
Essential for implementation of such an image display apparatus, is measurement of a relative position and orientation between a reference coordinate system defined on the physical space (a coordinate system on the physical space, which serves as a reference upon determining the position and orientation of a virtual object to be superimposed), and the coordinate system of the image capture device (camera coordinate system). This is because in order to render the virtual object (virtual space image) to fit the position on the physical space, the image of the virtual object must be generated using the same camera parameters as the physical camera parameters of the image capture device with respect to the reference coordinate system. For example, when superimposing the image of the virtual object at a certain position in a physical room, the reference coordinate system is defined on the room, and the position and orientation of the image capture device in the reference coordinate system can be calculated. When an arbitrary virtual pattern or label is to be superimposed on a physical box held by the hands of an observer, the object coordinate system of the box itself is considered as the reference coordinate system, and the position and orientation of the box (reference coordinate system) with respect to the image capture device can be calculated.
As a method of measuring the position and orientation of the image capture device, it is a common practice to lay out or set a plurality of indices (artificial markers, natural features, and the like) on the physical space, to detect the coordinates of projected images of the indices in an image captured by the image capture device, and to calculate the position and orientation of the image capture device based on the relationship with the coordinate information of the indices (for example, non-patent reference 1). However, using this approach, there is a restriction that the indices must always be captured.
On the other hand, an attempt has been made to mount a six-degrees-of-freedom position/orientation sensor using a magnetic sensor, ultrasonic sensor, or the like on the image capture device, and to correct errors of the position and orientation of the image capture device measured by this sensor using information (image information) obtained from an image acquired by capturing indices (for example, patent reference 1 and patent reference 2). With the method disclosed in patent reference 2, when indices are detected in the captured image, errors of sensor measurement values are corrected based on that information. When no index is detected, the measurement values of the six-degrees-of-freedom position/orientation sensor are used, unchanged, as the position and orientation of the image capture device. Because the position and orientation of the image capture device can be obtained irrespective of the presence/absence of the detection of indices, mixed reality can be presented stably.
With the method of patent reference 2, when the number of detected indices is three or more, the six degrees of freedom of the position and orientation of the image capture device are calculated based on the image information. When the number of detected indices is two or one, processing for correcting one of the position and orientation (two or three degrees of freedom) of the image capture device measured by the sensor is applied. More specifically, algorithms used to calculate the position and orientation of the image capture device are switched to have the number of detected indices as judging standards. In this way, even when the position and orientation of the image capture device cannot be calculated based only on the image information (when the number of captured indices is less than three), the position and orientation, which have undergone correction to cancel, as much as possible, errors in the sensor measurement values, can be acquired with reference to the sensor measurement values.
However, with the method of patent reference 1, processing for correcting only one of the position and orientation of the image capture device measured by the sensor based on the image information irrespective of the number of detected indices is applied. With this correction method, upon correcting the orientation, rotation correction values to cancel errors on indices are individually calculated for respective detected indices, and are averaged to calculate a correction value for the orientation measurement value. Upon correcting the position, translation correction values to cancel errors on indices are individually calculated for respective detected indices, and are averaged to calculate a correction value for the position measurement value. Since the degrees of freedom in correction are limited to two or three irrespective of the number of indices, stable solutions can be obtained even when the amount of information is insufficient.    Non-patent reference 1: Kato, et. al.: "An Augmented Reality System and its Calibration based on Marker Tracking", TVRSJ, vol. 4, no. 4, pp. 607-616, 1999.    Non-patent reference 2: J. Park, B. Jiang, and U. Neumann: "Vision-based pose computation: robust and accurate augmented reality tracking," Proc. 2nd International Workshop on Augmented Reality (IWAR'99), pp. 3-12, 1999.    Non-patent reference 3: D. G. Lowe: "Fitting parameterized three-dimensional models to images," IEEE Transactions on PAMI, vol. 13, no. 5, pp. 441-450, 1991.    Non-patent reference 4: Satoh, Uchiyama, and Yamamoto: UG+B: A Registration Framework Using User's View, Gyroscope, and Bird's-Eye View, TVRSJ, vol. 10, no. 3, pp. 391-400, 2005.    Non-patent reference 5: I. Skrypnyk and D. Lowe: "Scene modeling, recognition and tracking with invariant image features," Proc. 3rd International Symposium on Mixed and Augmented Reality (ISMAR'04), pp. 110-119, 2004.    Non-patent reference 6: D. Kotake, K. Satoh, S. Uchiyama, and H. Yamamoto: "A hybrid and linear registration method utilizing inclination constraint," Proc. 4th International Symposium on Mixed and Augmented Reality (ISMAR'05), pp. 140-149, 2005.    Patent reference 1: Japanese Patent Laid-Open No. 2003-222509    Patent reference 2: Japanese Patent Laid-Open No. 2003-279310    Patent reference 3: Japanese Patent Laid-Open No. 2003-344018    Patent reference 4: Japanese Patent Laid-Open No. 2004-233334

Position/orientation measurement method and apparatus


A device for shaping a duct made of plastics material or of deformable elastic material comprises two half-cages molded out of rigid plastics material and fastened together by resilient snap-fastening or hooking, the two half-cages when assembled together defining between them a housing that has the shape which is to be imparted to a portion of the duct. The invention is particularly suitable for mounting ducts of relatively large diameter in the engine compartments of motor vehicles.

Ducts or pipes of relatively large diameter which are mounted in the engine compartments of motor vehicles often need to be provided with shaping devices enabling their section shape to be modified, in particular for flattening purposes, and/or enabling their direction to be modified, e.g. in order to pass round an obstacle, with the need of such devices being due essentially to the lack of space available within the engine compartment, thus requiring certain portions of ducts or of pipes to be bent and flattened in order to make it possible to house them in the desired locations.
At present, such shaping devices are made of rigid plastics material overmolded on the ducts or pipes, thereby giving rise to problems that can be complex. Solid cores need to be placed inside the ducts during overmolding of the above-specified devices and they can be very difficult to remove after overmolding.

Device for shaping a duct of plastic material or material that is elastically deformable


Provided is a developer replenishing cartridge excellent in accuracy with which an image forming apparatus is replenished with a developer irrespective of a use environment even when the developer is in a consolidated state. The developer replenishing cartridge includes: a developer replenishing container and a developer, being removably mountable to a developer replenishing apparatus; in which: the developer replenishing container includes a pump portion that operates so that a state where the internal pressure of a developer containing portion is lower than the atmospheric pressure and a state where the pressure is higher than the atmospheric pressure alternately repeatedly switch with each other; and the developer contains toner having a uniaxial collapse stress at a maximum consolidation stress of 10.0 kPa, of 2.5 kPa or more and 3.5 kPa or less.

1. Field of the Invention
The present invention relates to a developer replenishing cartridge, which is removably mountable to a developer replenishing apparatus and can be used in an image forming apparatus such as a copying machine, a facsimile, a printer, or a multifunction machine having two or more of functions of these apparatus, and a developer replenishing method.
2. Description of the Related Art
Hitherto, a particulate developer has been used in an electrophotographic image forming apparatus such as a copying machine, and the apparatus is configured to print an image while compensating for consumption of a developer in association with formation of the image through replenishment from a developer replenishing cartridge.
A developer replenishing container to be used in such related-art developer replenishing cartridge is, for example, a container described in Japanese Patent Application Laid-Open No. 2010-256894.
An apparatus described in Japanese Patent Application Laid-Open No. 2010-256894 adopts a system involving discharging a developer with a bellows pump provided in the developer replenishing container. A specific method is as described below. The bellows pump is expanded to bring an air pressure in the developer replenishing container into a state where the pressure is lower than the atmospheric pressure, whereby air is taken in the developer replenishing container to fluidize the developer. Further, the bellows pump is contracted to bring the air pressure in the developer replenishing container into a state where the pressure is higher than the atmospheric pressure, whereby the developer is extruded and discharged by a pressure difference between the inside and outside of the developer replenishing container. The apparatus is configured to discharge the developer stably by alternately repeating the two steps. However, there is a risk that the developer is tapped in the developer replenishing container to be excessively brought into a consolidated state by, for example, the vibration at the time of its transportation or storage state of the container. When the excessive consolidated state is established, a phenomenon called flushing in which a large amount of the developer is discharged all at once may occur in such system involving performing discharge control based on an internal pressure fluctuation as described above. In addition, the flowability of the developer fluctuates depending on a temperature and humidity of its storage environment. Accordingly, in order that the developer may be stably discharged with high replenishment accuracy even when exposed to an environmental fluctuation, matching property not only with the developer replenishing container but also with the developer needs to be improved.

Developer replenishing cartridge and developer replenishing method


A system and method for Term Rewriting System hardware design employs a scheduler that incorporates a preference order in scheduling conflicting rules. The scheduler schedules a conflicting rule to execute when its predicate is true, and it is preferred over other conflicting rules in the preference order. The preference order may be, in one embodiment, a user-specified preference order enumerated by a designer. Such an order may be chosen according to efficiency criteria, such that the conflicting rule most essential for efficient hardware will be scheduled to execute on a given state rather than less essential conflicting rules The system and method advantageously permits a schedule to be computed in a time frame polynomially related to the number of rules, and produces more predictable and more easily understood schedules than conventional methods.

1. Field of the Invention
This invention relates generally to the design and synthesis of digital circuits and specifically to the scheduling of rules in a Term Rewriting System (TRS).
2. Background Information
Hardware Description Languages (HDLs) have been used for many years to design digital systems. Such languages employ text-based expressions to describe electronic circuits, enabling designers to design much larger and more complex systems than possible using previously known gate-level design methods. With HDLs, designers are able to use various constructs to fully describe hardware components and the interconnections between hardware components. Additionally, time-dependency and concurrency, important attributes of most digital circuits, can be easily described.
One popular Hardware Description Language is Verilog, first implemented by Phil Moorby of Gateway Design Automation in 1984, and later standardized under IEEE Std. 1364 in 1995. Currently, Verilog is supported by a wide variety of software tools and exists in several different incarnations and versions. One factor that has led to Verilog's popularity is its ability to describe a digital system at several levels of abstraction.
At one level of abstraction, Verilog may operate as a Register-Transfer Language (RTL) in which circuits have, or are abstracted to have, a set of registers. A designer may use an RTL to specify the values of the registers in each clock period in terms of the values of the registers in the proceeding clock period. In this way, an RTL implements a finite state machine (FSM) of the circuit to be specified. While envisioning the circuit as an FSM, the designer explicitly manages concurrency of execution by scheduling the exact cycle-by-cycle interactions between multiple concurrent states. To design a more complex digital circuit, such as a pipelined central processing unit (CPU), using an RTL approach, a designer generally will define a number of modules, each as an FSM. The designer then specifies the interoperations of these modules so that they may operate concurrently.
As hardware systems become more complex, for example if one were to add out-of-order speculative instruction execution to the pipelined processor mentioned above, RTL design becomes increasingly complicated. With added complexity, design mistakes become more common, especially in coordinating interactions between multiple finite state machines. The designer must manage an increasingly complicated mental model to design and interconnect FSMs. This difficulty is compounded by the large size of the RTL code, which makes debugging more difficult.
In an attempt to address these issues, designers have sought to specify digital circuits in "behavioral" terms, rather than in terms of transitions between states. In a behavioral specification, the focus is on the functions performed by the circuit, rather than on individual register values. When several behaviors are described, the designer typically employs multiple threads of computation with message-passing or shared-memory. At another level of abstraction, Verilog may support a behavioral specification approach. Similarly, a behavioral specification may be implemented in other languages such as System C, an open-source kernel that extends the C++ language to enable hardware design.
The behavioral specification approach allows more rapid specification of circuits than RTL design, and, due to its simpler structure, produces specifications that are more easily debugged. Yet, as with RTL specifications, designers of behavioral descriptions still must explicitly manage the interactions between concurrent operations. Also, it is rarely possible or practical to synthesize an equivalent digital circuit directly from a given behavioral specification. Often, the behavioral specification must first be translated into a lower-level specification before synthesis. Finally, formal verification of a behavioral specification is often very difficult or impossible due to the nature of the specification.
To address these and other shortcomings, a hardware design approach centered upon Term Rewriting System (TRS) technology has been developed. Term Rewriting traces its foundations back to 1930s mathematical logic theory, but only recently has been adapted to hardware design. A TRS approach to hardware design employs a list of "terms" that describe hardware states, and a list of "rules" that describe behavior. A "rule" captures both a state-change (an action) and the conditions under which the action can occur. Further, each rule has atomic semantics, that is, each rule executes fully without interactions with other rules. This implies that, even if multiple rules are executed on a given state, they can be considered in isolation for analysis and debugging purposes.
More formally, a Term Rewriting System has rules that consist of a predicate (a function that is logical true or false) and an action body (a description of a state transition). A rule may be written in the following form:rule r: when π(s)=>s:=δ(s)where s is the state of the system, π is the predicate, and δ is a function used to compute the next state of the system. The expression s:=δ(s) comprises the action body of the rule. If π(s) is true, then δ(s) defines the next state of the system. In a strict implementation of a TRS, only one rule may execute on a given state. However, as explained further below, concurrent application of rules is desirable for efficient execution. Therefore if several rules are applicable on a given state, some implementations may allow more than one rule to be selected to update the system. Afterwards, all rules are re-evaluated for applicability on the new state of the system and the process continues until no further rules are applicable. In practice, abstract data types such as arrays and First In First Out (FIFO) queues are often used to make the descriptions more readable.
It has been found that the quality of the hardware generated by a TRS system is dependent on the order and concurrency of the application of the rules. While some rules may be executed concurrently, others conflict (for example, they both attempt concurrent access to a single-ported resource) and must be executed sequentially. Therefore, prior approaches to TRS hardware design have implemented a scheduler to determine which rules will execute in each clock cycle.
One type of scheduler that has been employed is a priority encoder which asserts one executable rule in each clock cycle. This type of scheduler may also include round-robin functionality that ensures that if a rule remains applicable for a sufficient number of consecutive clock cycles then it will be selected for execution. Unfortunately, the efficiency of hardware produced by the priority encoder scheduling method has been found to be inadequate. Further details relating to the priority encoder may be found below.
Another type of scheduler that has been previously implemented is an enumerated scheduler (also termed direct table encoder). In an enumerated scheduler, applicable rules are listed in an enumerated encoder table, a lookup table constructed to contain an explicit listing of the rules that can execute given a certain combination of applicable rules. Such a table is constructed so that the maximum number of non-conflicting rules execute on a given clock cycle. A more detailed discussion of the enumerated scheduler may be found below.
While the enumerated scheduler has been found to generate relatively efficient hardware, computation of the lookup table necessary for the scheduler is computationally intensive and takes an unacceptable amount of processing time. Indeed, as explained more fully below, the best known implementation of an enumerated scheduler requires processing time exponentially related to the number of rules considered, thereby making the scheduler impractical for highly complex systems.
In order to make the TRS approach to hardware design more viable, a more capable scheduler than either the priority encoder or the enumerated scheduler is required. It would be desirable for such a scheduler to generate hardware of equivalent quality to hand-coded RTL design, while not consuming an inordinate amount of processing time, so that it would be practical for highly complex systems.

System and method for scheduling TRS rules


Embodiments of the invention are directed to input devices configured for use with computing devices. The present invention relates to input device configured with a plurality of input members grouped into contoured-shaped bowls on a portion of the input devices. The input device may also be configured for use with multiple hand positions and multiple profiles based on the hand positions. The input device may enable switching between user-programmable profiles, and may include sensory feedback indicating the profiles active on the input device.

Input devices provide a user the ability to interact with a computing device. Exemplary forms of input devices include keyboards, computer mice, stylus, or other similar forms. Most input devices in the form a computer mouse provide a user interacting with the computing device the ability to perform certain activities, including navigation, cursor control, and selection functions.
In some situations, a user's activities with the input device may require greater functionality than that provided by standard input devices. For example, computer games (e.g., massively multiplayer online role-playing game or first-person shooters) may require the user to perform tasks or operations that typically require the user to use two hands to accomplish (e.g., selecting options and controls). Tasks or operations that require two hands are typically accomplished by the user using a second hand interacting with a second device, such as a keyboard input device. This method may result in slower response time and reaction time, as the user's second hand is typically not the dominant hand. The slower response and reaction time may be detrimental to the user experience.
In previous solutions, input devices in the form of computer mice were given an increased button count in order to transfer some of the tasks and operations from the keyboard input device to the computer mouse. However, users found it difficult to keep track of their location within the additional buttons and were forced to constantly visually assess their positions, which resulted in a negative user experience.
Based on the foregoing, there is a need in the art for improved methods and systems for input devices that provide greater functionality and better user experience.


A plurality of interconnect layers are produced on a top side of one or two semiconductor chips, and are mutually isolated from one another in each case by insulation layers that are patterned in such a way that an interconnect layer applied as bridge makes contact with the interconnects applied previously.

Stacks of semiconductor chips can be produced by a procedure in which contact areas are in each case produced at the top sides of the semiconductor chips in a topmost metal layer of the wiring planes, which contact areas are covered with a passivation, a plated-through hole is in each case produced through the passivation and an electrically conductive connection is produced between the plated-through hole and an associated interconnect applied on the top side. The chips are arranged with the relevant top sides facing one another and opposite one another in such a way that the interconnects to be connected to one another are located one on top of the other. The interconnects are permanently connected to one another using diffusion soldering known per se, in particular the SOLID process. In order to produce the soldered connection, a thin solder layer is applied to the relevant interconnects of at least one of the semiconductor chips.
This production method affords the advantage, inter alia, of an additional relatively thin metal plane in the connecting zone (interface) of the two chips which can be used for wiring purposes. By way of example, in this interconnect plane which is provided only for connecting the chips, a rewiring of the chip contacts may be performed or the chips may be contact-connected by means of this plane to interconnects suitable for high frequencies (strip lines).
The connecting plane is formed in a single layer, however, so that the interconnects present therein cannot be bridged. A bridging of the interconnects present in the connecting plane is only possible if suitable electrically conductive connections are provided in one of the metallization planes of the wiring of the semiconductor chips themselves, which connections, via the plated-through holes to the interconnects connected to one another by means of diffusion soldering, short-circuit the interconnects. This requires two plated-through holes (vias) and a metal bridge in the topmost metallization plane of one of the chips that are to be connected to one another. A corresponding adaptation in the design of the metallization planes is therefore required as early as in the production of the chip.


A steering wheel includes a boss, a grip having a substantially rod shape and arranged away from the boss, and a spoke portion connecting the boss and the grip. The grip includes a core for the grip, a coating layer which covers an outer peripheral side of the core, and the decorative body exposed on the upper surface side of the grip. The decorative body has a decorative main body exposed on the upper surface side of the grip and a mounting portion having a long shape, being arranged substantially along the grip, holding the decorative main body and being attached to the coating layer. Mounting fitting portions to be attached to the coating layer is arranged on a lower surface side of the mounting portion and on a side separated from the boss and the spoke portion with respect to the core in a cross section of the grip.

In a related art, as a steering wheel having a configuration in which a decorative body is arranged on a grip portion, there is a steering wheel having a configuration where the decorative body is attached by attaching a locking portion formed so as to extend downward from a rear surface (lower surface) side of the decorative body exposed on an outer peripheral surface side of the grip portion to a mounting base portion formed so as to cover an outer peripheral side of a core material for the grip portion (see, for example, JP-A-2016-68758).


The semiconductor device according to the present invention includes a semiconductor layer, a trench formed by digging the semiconductor layer from the surface thereof, a gate insulating film formed on the inner surface of the trench, and a gate electrode made of silicon embedded in the trench through the gate insulating film. The gate electrode has a high-conductivity portion formed to cover the gate insulating film with a relatively high conductivity and a low-conductivity portion formed on a region inside the high-conductivity portion with a relatively low conductivity.

1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device.
2. Description of Related Art
A trench gate structure is generally known as a structure effective for refinement of a VDMOSFET (Vertical Double diffused Metal Oxide Semiconductor Field-Effect Transistor).
FIG. 9 is a schematic sectional view showing the structure of a conventional semiconductor device including a trench gate type VDMOSFET.
A semiconductor device 401 shown in FIG. 9 includes an N+-type (high-concentration N-type) substrate 402. An N−-type (low-concentration N-type) epitaxial layer 403 is laminated on the N+-type substrate 402. A base layer portion of the N−-type epitaxial layer 403 forms an N−-type region 404. A P−-type body region 405 is formed on a surface layer portion of the N−-type epitaxial layer 403 vertically adjacently to the N−-type region 404.
A first trench 406 and a second trench 407 smaller in width than the first trench 406 are formed in the N−-type epitaxial layer 403.
The first trench 406 is dug in the P−-type body region 405 from the surface thereof to penetrate through the P−-type body region 405, so that the deepest portion thereof reaches the N−-type region 404. A gate insulating film 408 made of SiO2 (silicon oxide) is formed in the first trench 406, to cover the inner surface thereof. A gate electrode 409 made of polysilicon (doped polysilicon) doped with an N-type impurity in a high concentration is embedded inside of the gate insulating film 408.
The second trench 407 is also dug in the P−-type body region 405 from the surface thereof to penetrate through the P−-type body region 405, so that the deepest portion thereof reaches the N−type region 404. A gate insulating film 410 made of SiO2 is formed in the second trench 407, to cover the inner surface thereof. A gate electrode 411 made of doped polysilicon is embedded inside of the gate insulating film 410.
N+-type source regions 412 are formed on a surface layer portion of the P−-type body region 405. Further, P+-type body contact regions 413 are formed on a surface layer portion of the P−-type body region 405, to penetrate through the N+-type source regions 412.
A drain electrode 414 is formed on the back surface of the N+-type substrate 402.
An interlayer dielectric film (not shown) is laminated on the N−-type epitaxial layer 403. A gate wire (not shown) prepared from an Al (aluminum) alloy wire, for example, is formed on the interlayer dielectric film. In the interlayer dielectric film, a contact hole (not shown) is penetratingly formed on a portion where the gate wire and the gate electrode 409 are opposed to each other, so that the gate electrode 409 and the gate wire are in contact (electrically connected) with each other through this contact hole.
The gate electrodes 409 and 411 may be formed by filling up the first and second trenches 406 and 407 with non-doped polysilicon (polysilicon doped with no impurity) and implanting an impurity into this non-doped polysilicon respectively.
More specifically, an oxide film is formed on the surface of the N−-type epitaxial layer 403 including the inner surfaces of the first and second trenches 406 and 407. A deposition layer of non-doped polysilicon is formed on the oxide film, with a thickness for filling up the first trench 406. Thereafter the impurity is implanted into a surface layer portion of the deposition layer of non-doped polysilicon. After this implantation of the impurity, a heat treatment is performed. Thus, the deposition layer of non-doped polysilicon is converted to a deposition layer of doped polysilicon. Thereafter portions of the deposition layer of doped polysilicon located outside the first and second trenches 406 and 407 are removed by etch-back, so that the gate electrodes 409 and 411 made of doped polysilicon are formed in the first and second trenches 406 and 407 respectively.
However, the impurity is implanted from the surface of the deposition layer of non-doped polysilicon, and hence the impurity concentrations of the gate electrodes 409 and 411 are sloped to lower toward deep positions thereof. Therefore, the gate electrodes 409 and 411 disadvantageously exhibit relatively large resistances, due to low conductivities on the bottom portions thereof.
In order to solve this problem, the time for implanting the impurity may be so set as to sufficiently implant the impurity up to the bottom portions of the gate electrodes 409 and 411. In this case, however, an extremely long time is required for implanting the impurity.
On the other hand, the conductivities of the gate electrodes 409 and 411 may be increased by another method of forming the gate electrodes 409 and 411. According to this method, a deposition layer of doped polysilicon having a thickness for filling up the first trench 406 is formed on an oxide film provided on the surface of the N−-type epitaxial layer 403 by depositing polysilicon while doping the same with an impurity. Thereafter portions of the deposition layer of doped polysilicon located outside the first and second trenches 406 and 407 are removed by etch-back.
According to this method, however, silicon embeddability is deteriorated due to the width of the first trench 406 larger than that of the second trench 407. Therefore, a recess is formed on the surface of the deposition layer of doped polysilicon on a portion located above the wider first trench 406. The size of this recess is increased due to the step of etching back the deposition layer of doped polysilicon. Consequently, a large recess 415 is formed on the surface of the wider gate electrode 409, as shown in FIG. 9. When surface washing is performed by repeating oxidation and a hydrofluoric acid treatment after the formation of the gate electrode 409, the size of the recess 415 formed on the surface of the wide gate electrode 409 is further increased.
When the size of the recess 415 is increased, stress may be applied to the gate electrode 409 due to oxidation of the surface of the recess 415 in the surface washing, a crystal defect may be formed in the gate electrode 409. The crystal defect in the gate electrode 409 causes reduction in the source-drain withstand voltage.
When the large recess 415 is formed on the surface of the wider gate electrode 409, the distance from the surface of the interlayer dielectric film laminated on the N−-type epitaxial layer 403 to the surface of the gate electrode 409 is increased. If an etching time for forming the contact hole is set with reference to the surface of the N−-type epitaxial layer 403, therefore, the contact hole may not penetrate through the interlayer dielectric film, and a contact failure may be caused between the gate electrode 409 and the gate wire.
If the etching time for forming the contact hole is set with reference to the surface of gate electrode 409, on the other hand, the N−-type epitaxial layer 403 (the N+-type source regions 412 and the P+-type body contact regions 413) may be dug down to cause the so-called junction leak when other contact holes for contact with the N+-type source regions 412 and the P+-type body contact regions 413 are formed in the interlayer dielectric film along with this contact hole.
While the surface of the deposition layer of doped polysilicon may conceivably be planarized by CMP (chemical mechanical polishing) so that no recess is formed on the surface of the gate electrode 409, the working cost is disadvantageously increased in this case due to increase in the number of the manufacturing steps.
The problem of the contact failure or the junction leak is not restricted to the structure having the first and second trenches 406 and 407 different in width from each other, but may also arise in a structure having trenches identical in width to each other.
FIG. 10 is a schematic sectional view showing the structure of another conventional semiconductor device including a trench gate type VDMOSFET.
A semiconductor device 501 shown in FIG. 10 includes an N+-type (high-concentration N-type) substrate 502. An N−-type (low-concentration N-type) epitaxial layer 503 is laminated on the N+-type substrate 502. A base layer portion of the N−-type epitaxial layer 403 forms an N−-type region 504. A P−-type body region 505 is formed on a surface layer portion of the N−-type epitaxial layer 503 vertically adjacently to the N−-type region 504.
A trench 506 is formed in the N−-type epitaxial layer 503. The trench 506 is dug in the P−-type body region 505 from the surface thereof to penetrate through the P−-type body region 505, so that the deepest portion thereof reaches the N−-type region 504. A gate insulating film 507 made of SiO2 (silicon oxide) is formed in the trench 506, to cover the inner surface thereof. A gate electrode 508 made of polysilicon (doped polysilicon) doped with an N-type impurity in a high concentration is embedded inside of the gate insulating film 507.
N+-type source regions 509 are formed on a surface layer portion of the P−-type body region 505 along the trench 506. Further, P+-type body contact regions 510 are formed on a surface layer portion of the P−-type body region 505, to penetrate through the N+-type source regions 509.
An interlayer dielectric film (not shown) is laminated on the N−-type epitaxial layer 503. A gate wire (not shown) made of Al (aluminum), for example, is formed on the interlayer dielectric film. The gate wire is in contact (electrically connected) with the gate electrode 508 through a gate contact hole (not shown) formed in the interlayer dielectric film. Source wires (not shown) are electrically connected to the N+-type source regions 509 and the P+-type body contact regions 510 through source contact holes (not shown) formed in the interlayer dielectric film.
A drain electrode 511 is formed on the back surface of the N+-type substrate 502.
In order to manufacture the semiconductor device 501, a silicon oxide film is formed on the surface of the N−-type epitaxial layer 503 including the inner surface of the trench 506. A deposition layer of doped silicon is formed on the silicon oxide film. The deposition layer of doped silicon is formed with a thickness for filling up the trench 506 and covering portions of the silicon oxide film located outside the trench 506. Thereafter portions of the deposition layer of doped silicon located outside the trench 506 are removed by etch-back. Thus, the gate electrode 508 made of doped silicon is formed in the trench 506.
However, the deposition layer of doped silicon grows at the same rate on the overall surface of the N−-type epitaxial layer 503 including the side surface of the trench 506. Therefore, a recess is formed on a portion of the surface of the deposition layer of doped silicon located above the trench 506. The size of this recess is increased due to the step of etching back the deposition layer of doped silicon. Consequently, a large recess 512 is formed on the surface of the gate electrode 508, as shown in FIG. 10. When surface washing is performed by repeating oxidation and a hydrofluoric acid treatment after the formation of the gate electrode 508, the size of the recess 512 formed on the surface of the gate electrode 508 is further increased.
When the large recess 512 is formed on the surface of the gate electrode 508, the distance from the surface of the interlayer dielectric film laminated on the N−-type epitaxial layer 503 to the surface (recess 512) of the gate electrode 508 is increased. If an etching time for forming the gate contact hole is set with reference to the surface of the N−-type epitaxial layer 503, therefore, the gate contact hole may not penetrate through the interlayer dielectric film, and a contact failure may be caused between the gate electrode 508 and the gate wire.
If the etching time for forming the gate contact hole is set with reference to the bottom surface of the recess 512, on the other hand, the source contact holes for contact with the N+-type source regions 509 (or the P+-type body contact regions 510) may penetrate through the N+-type source regions 509 and reach the P−-type body region 505 when the same are formed in the interlayer dielectric film along with the gate contact hole, to disadvantageously cause the so-called junction leak.
A DTI (Deep Trench Isolation) technique is known as an element isolation technique for electrically isolating a region provided with a high withstand voltage element such as a high withstand voltage MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) from a region provided with another element when the high withstand voltage element and the other element are mixedly provided on a semiconductor substrate.
FIG. 11 is a schematic sectional view showing the structure of a conventional semiconductor substrate provided with a high withstand voltage element.
The semiconductor substrate is formed by a thick-film SOI (Silicon On Insulator) substrate 601, for example. The thick-film SOI substrate 601 has a structure obtained by laminating an N-type epitaxial layer 604 made of Si (silicon) on a P- or N-type silicon substrate 602 through a BOX (Buried Oxide) layer 603 made of SiO2 (silicon oxide)
A deep trench 605 in the form of a quadrangular ring in plan view is dug in the epitaxial layer 604 from the surface thereof. The deepest portion of the deep trench 605 reaches the BOX layer 603. The deep trench 605 is filled up with polysilicon 607 through an oxide film 606 made of SiO2. A high withstand voltage element (not shown) such as a high withstand voltage MOSFET is formed on a region surrounded by the deep trench 605.
Thus, in the semiconductor device to which the DTI technique is applied, a region surrounded by the deep trench 605 filled up with the polysilicon 607 serves as an element forming region isolated (dielectrically isolated) from the periphery thereof.
In the steps of manufacturing the semiconductor device, an impurity is implanted into the epitaxial layer 604 for forming an impurity diffusion region (source region of the high withstand voltage MOSFET or the like, for example) in the element forming region, and a heat treatment is thereafter performed for activating the impurity. Further, another heat treatment is performed for forming the oxide film 606. When these heat treatments are performed, difference is caused between the quantities of expansion of the epitaxial layer 604 and the oxide film 606 due to the difference between the thermal expansion coefficients of Si and SiO2, and stress resulting from this difference is concentrated on portions around the upper and lower ends of the deep trench 605 in the epitaxial layer 604. When the heat treatments are repeated, therefore, crystal defects resulting from stress concentration may be formed around the upper and lower ends of the deep trench 605 in the epitaxial layer 604.

Semiconductor device and method of manufacturing semiconductor device


The invention relates to a method of listening in to calls between two or more subscribers of a communications network comprising one or more IP networks as well as to a listening server, a call control server, and an IP router for carrying out the method. When the listening server detects a request to monitor one of the subscribers, it determines at least one call control server assigned to the subscriber. Further, at least one IP router is determined which is responsible for a network access point of the subscriber to the IP network or IP networks. The listening server causes the at least one determined call control server to acquire call data associated with calls in which the subscriber is involved. Further, the at least one determined IP router is caused to acquire contents data associated with calls in which the subscriber is involved.

National and international laws require communications network operators to provide mechanisms within the network which enable authorities who have a need to know (police, secret services, . . . ) to monitor telephone conversations of suspicious persons.
The invention is based on the way the problem is solved in a classic telephone network:
At the local switching center of the subscriber to be monitored, the data record of the subscriber is marked and a sort of conference connection is established to the authority. The basic data to be determined for the respective listening process is determined by the switching center by accessing an authority database which is part of the switching center. The whole monitoring mechanism thus forms part of the switching center.
A problem consists in the fact that there are increasing technical possibilities of routing telephone calls through communications networks in whole or in part as VOIP calls (VOIP=Voice over IP; IP=Internet Protocol). Conventional methods are not suited for monitoring this kind of communications traffic.


A thermal head includes a heat storage layer disposed on a substrate surface by lamination, a plurality of heating elements disposed on the heat storage layer, a plurality of individual electrodes, each connected individually to one end-portion of a heating element in the length direction of the resistance, and a common electrode electrically connected to the other end-portions of all heating elements in the length direction of the resistance, wherein the above-described substrate is a Si substrate having a resistivity of 20 mΩ·cm or less, the Si substrate is provided with an exposure region including no heat storage layer, and a contact portion is disposed on the exposure region, so as to keep the common electrode and the Si substrate surface in ohmic contact.

1. Field of the Invention
The present invention relates to a thermal head mounted on a thermal transfer printer, for example, and a method for manufacturing the same.
2. Description of the Related Art
A thermal head includes a heat storage layer made of a highly heat-insulating material, a plurality of heating elements which generate heat by energization, a plurality of individual electrodes, each electrically connected individually to one end-portion of a heating element in the length direction of the resistance of the plurality of heating elements, a common electrode electrically connected to the other end-portions of all heating elements, and a protective layer to protect these plurality of heating elements, individual electrodes, and common electrode, on a substrate having excellent heat-dissipating property and made of Si, a ceramic material, or a metallic material, for example. Such a known thermal head performs printing operation by pressing the heating elements against an ink ribbon and a printing substrate wound around a platen roller while the heating elements are generating heat through the common electrode and the individual electrodes.
In recent years, requirements for high output thermal heads capable of performing high-quality printing with higher definition and high-speed printing have been intensified. Therefore, it is indispensable to reduce common drop (drop in voltage of common electrode) and to improve the printing quality. In order to reduce the common drop, the area and the thickness of the common electrode may be increased so as to reduce the common resistance. However, if the common electrode becomes large or thick, achievement of miniaturization becomes difficult. Consequently, up to now, as shown in FIG. 9, an upper common electrode 15 connected to one end-portion of each of a plurality of heating elements 18 is provided and, in addition, a lower common electrode 16 having an area larger than the area of the upper common electrode 15 is provided as a layer located under a resistance layer constituting the plurality of heating elements 18 with an insulating layer 14 therebetween. The upper common electrode 15 and the lower common electrode 16 are electrically connected to each other through a contact hole 14a disposed at a specific position and, thereby, a common electrode is provided. By forming the common electrode having a two-layer structure composed of the upper layer and the lower layer as described above, the common resistance can be significantly reduced, and both the reduction of the common drop and the miniaturization of the head can be satisfied (refer to Japanese Examined Patent Application Publication No. 6-61947, Japanese Unexamined Patent Application Publication No. 10-34991, and U.S. Pat. No. 6,201,558).
However, it was made clear that when the common electrode had a two-layer structure composed of the upper layer and the lower layer as described above, layers in between the upper common electrode and the lower common electrode short-circuited frequently and leakage currents occurred. Since the contact hole is used in order to ensure continuity between the upper common electrode and the lower common electrode, there is a problem in that the manufacturing process is complicated.

Thermal head including Si substrate and method for manufacturing the same


A navigational aide in the form of a physical model that may be integrated with conventional expedition equipment. The preferred embodiment comprises a hiking staff (5, 6) containing 2-D map data (3) and or 3-D topographical representations (1, 2) corresponding with specific geographic regions and or features. The 3-D surfaces may be sculpted about and along the model. Alternately, cross-sectional elevation profiles of routes may be presented in the form of a 3-D sculpted grooves or flutes along, about, and or around the shaft. A variety of configurations are presented for the purpose of maximizing the effective sculptable areas or edges, and to provide a shrouding effect for the protruding peaks that would otherwise be vulnerable to deformation and uncomfortable to grip. The 3-D elevations may be exaggerated to visually accentuate changes in elevation. Features such as trails may be represented as grooves to facilitate marking progress and position. 2-D cartographic data (7,8,9) may also be presented along with the 3-D data or alone as a mounted map. In an alternate embodiment, the invention comprises a toy for children, inspiring learning imagination and adventurous play. Several methods and materials for both computerized and conventional design and manufacturing are provided. The novel aspects of this invention may be incorporated in the original equipment manufacture, modification of existing equipment, and accessories for attachment to conventional equipment.

1. Field of the Invention
The present invention relates to a navigational aide in the form of physical model conveniently embodied in a generally long and slender shape, comprising three-dimensional (3-D) topographical representations and or two-dimensional (2-D) cartographic data corresponding with geographic regions and features such as mountains, rivers, shorelines, and trails. The preferred embodiment of the invention comprises the navigational aid integrated with a hiking staff. Alternate embodiments include boat paddles, ski poles, and universal attachable accessories and grips for these and other application. Another embodiment, the invention comprises a toy for children, inspiring learning imagination and adventurous play. A variety of geometric configurations are presented for the purpose of maximizing the effective sculptable areas and edges, and to provide a shrouding effect for the protruding peaks that would otherwise be vulnerable to deformation and uncomfortable to handle. The 3-D elevations may be exaggerated to visually accentuate changes in elevation. The novel aspects of this invention may be incorporated in the original equipment manufacture, modification of existing equipment, and attachments for conventional equipment.
2. Related Art
Outdoor adventures into unfamiliar territories are extremely common and adventurers are typically reliant on maps or charts for planning and navigation. For centuries, topographical maps have been the indispensable tools for travel in mountainous regions. Unfortunately, maps are somewhat inconvenient and inefficient to use, as they typically require unpacking, unfolding, refolding, and repacking. In fact, maps are universally despised for their inherent and perplexing resistance to refolding. Some navigational errors result from failures to consult a map attributable to the inconvenience.
Moreover, many people are incapable of, or experience great difficulty in comprehending 2-D graphical information or cartographic data presented on a flat map. The term cartographic data is use here to include all elements of a conventional map such as labels, legends, scales, arrows, annotation, etc. To fully comprehend the information on the map, the reader must mentally transform the non-descript 2-D data into a meaningful 3-D perspective. This process is often difficult time consuming and subject to interpretation and translation errors. Some maps provide a cross sectional representations of the elevation profiles for specific and popular trails. This information can be extremely beneficial as it assists the reader visualization of the topology of the course.
Modern "Global Positioning Systems" also known as GPS provide valuable and accurate information navigational assistance. Unfortunately, GPS systems are small computers and thus, some people are intimidated or otherwise incapable of operating them. GPS systems are ultimately reliant upon electronic components both in the GPS unit and in the satellite systems. In extreme environments basic infallible equipment is preferable over electronics. GPS systems displays are presently limited to 2-D flat screen LCDs that provide only minimal 3-D perspective.
Large format 3-D sculpture type models or dioramas of mountains, trails, rivers, oceans and shorelines of particular interest are often on display at major base camps and ports of significant interest. These models are frequently studied for correlation to 2-D maps to aide in the comprehension and visualization of the actual terrain. The typical slab type model format is an inefficient means of representing the topology of particular routes or trails due to the fact that much of the information off of the trail is generally not significant. Similarly, small-scale 3-D trail models are not particularly viable as they are volumetrically inefficient and inconvenient to pack, carry, and access.
River rafters, kayakers, and canoeists and rely on marine charts to navigate rivers and waterway. Subtle changes in topology and elevation in rivers containing waterfalls and dams may have a dramatic effect on their navigability. The changes in elevation and depth affect the flow rate and velocity of the water that can be significant factors in river boating. Moreover, rivers are often wind back and forth through areas of remarkably similarity appearance making position and progress difficult to monitor. All bodies of water also contain the added fourth dimension of sub-surface topology that is difficult to interpret from maps. Submerged obstacles can be dangerous and are often impossible to see from the surface. Paddling through whitewater rapids requires quick recognition and response to changes in the watercourse. It is often impossible or imprudent to let go of a paddle in order to access a conventional chart.
Fly fishermen are often required to hike along rivers and wade through them in pursuit of their prey. As the terrain around and within the rivers is often rough, fishermen carry wading staffs to aid in hiking and to provide probing and balance while wading in deep water. Fishermen also rely heavily on maps and charts to navigate and understand the waters in which they fish.
Skiers in general, and cross-country skiers in particular, are often required to navigate or track their position relative to terrain, trails or markers on a race course. Cold weather conditions and heavy garments such as gloves make access to maps exceedingly inconvenient.
Outdoor expedition equipment such as hiking staffs, boat paddles, and ski poles have been evolving since antiquity. Modern high technology has been applied to the design and construction of these devices providing enhanced performance with respect to ergonomic comfort, lightweight, and durability. But the basic utility of these devices has not advanced appreciably.

Hiking staff, ski pole, or boat paddle, with integrated topographical representations of trails and or terrain


A method and device for sensing spatial variations and/or temperature variations in the locality of a fiber optic cable 1 is disclosed, wherein a broadband light source 47 is used to shine incident light onto a series of fiber Bragg gratings contained within zones A, B and C. Each zone contains a plurality of fiber Bragg gratings, the plurality of fiber Bragg gratings in any one zone having a substantially identical grating period, and the fiber Bragg gratings in the respective zones having different grating periods. The reflected light from each fiber Bragg grating is returned back down the fiber optic cable 1 and redirected via a 2×1 coupler 51 to a wavelength detection system 53 and a personal computer 63. The combination of wavelength detection system 53 and personal computer 63 allow analysis of the reflected light patterns, as well as providing a user interface which enables detection of the occurrence of a spatial and/or a temperature variation. The location of the said variation along the fiber optic cable 1 is advantageously detectable in terms of the particular zone A, B or C in which the said variation has been sensed.

This invention relates to a fibre optic cable, to a method of sensing spatial variations and/or temperature variations in a structure using a fibre optic cable, and to a device for sensing spatial variations and/or temperature variations in a structure, comprising a fibre optic cable.
The use of fibre Bragg gratings in sensors is well known. U.S. Pat. No. 4,761,073 (incorporated herein by reference) describes a spatially resolving fibre optic cable strain gauge which utilises fibre Bragg gratings, and it is also known to use similar fibre Bragg grating sensors to monitor variations in temperature. Variations are able to be sensed as the period and the effective refractive index of a fibre Bragg grating are altered as a result of a change in strain or a change in the ambient temperature in the locality of the fibre Bragg grating. However, fibre Bragg grating sensors forming the prior art suffer from a lack of spatial accuracy, and as a result the ability to precisely locate the source of strain and/or heat is compromised.
Fibre Bragg gratings are formed in photosensitive fibre optic cables by creating a periodic variation in the refractive index of the core of the fibre optic cable, which acts as a grating to reflect incident light. The wavelength of this reflected light, known as the Bragg wavelength λB, is dependent on the grating period and the effective refractive index of the fibre Bragg grating, according to the equationλB=2neffΛ,where neff is the effective refractive index of the fibre optic cable and Λ is the period of the fibre Bragg grating.
This Bragg wavelength is known to be affected as a consequence of localised spatial and/or temperature variations in the vicinity of the fibre Bragg grating. Fibre Bragg gratings have predictable, well defined responses to spatial and/or temperature variations. These responses are known to be approximately linear at and above room temperature, and fibre Bragg grating sensors operate by measuring the wavelength shift of the Bragg wavelength in response to the aforementioned spatial and/or temperature variations.
The Bragg wavelength shift ΔλB in response to spatial and/or temperature variations in the fibre optic cable in the vicinity of the fibre Bragg grating is brought about by a change in the grating period, and is found by differentiating the above equation to account for changes in the length of the fibre optic cable and/or the temperature in the vicinity of the fibre Bragg grating. This results in
      Δ                                λ      B        =            2                    (                              Λ                                                      ∂                                  n                  eff                                                            ∂                l                                              +                                    n              eff                                                                  ∂                Λ                                            ∂                l                                                    )              +          2                              (                                    Λ                                                              ∂                                      n                    eff                                                                    ∂                  T                                                      +                                          n                eff                                                                            ∂                  Λ                                                  ∂                  T                                                              )                .
There are currently two approaches to making sensors using fibre Bragg grating technology. The simplest approach is to write a plurality of identical fibre Bragg gratings (i.e. gratings with the same grating pitch) along the length of a fibre optic cable. Incident light is reflected by each of these fibre Bragg gratings, the Bragg wavelength of each reflection being the same due to the equality of the fibre Bragg gratings. Spatial and/or temperature variations in the locality of the fibre optic cable would result in a shift of the Bragg wavelength of the light reflected by one or more affected fibre Bragg gratings. This change can be sensed, and hence it is possible to detect that a spatial and/or temperature variation has occurred.
The approximate position of the spatial and/or temperature variations can be obtained by optical time domain reflectometry. In this technique, a very short pulse of light (of the order of 1 ns) is injected into the fibre optic cable and the reflected spectrum measured as a function of time after the pulse injection. This approach is limited in that, although spatial and/or temperature variations in the locality of the fibre optic cable are detectable, there is no provision for the precise location of such variations, given that the resolution of the position information is practically only of the order of a few meters, meaning that only fibre Bragg gratings that are several meters apart can be distinguished.
An alternative approach is to write a plurality of fibre Bragg gratings along the length of a fibre optic cable, each fibre Bragg grating having a unique grating pitch. Incident light is reflected by each of these fibre Bragg gratings, the Bragg wavelength of each reflection in this case being characteristic of a particular fibre Bragg grating. Spatial and/or temperature variations occurring in a particular vicinity will affect one or more of the fibre Bragg gratings in that vicinity, leading to a shift of the Bragg wavelength of the light reflected by the affected fibre Bragg grating or gratings. Analysis of the reflected light patterns therefore enables detection of the occurrence of a spatial and/or a temperature variation. The location of the variation along the fibre optic cable is also detectable by determining from which particular fibre Bragg grating or fibre Bragg gratings the shifted Bragg wavelength emanates. However, the Bragg wavelengths of the fibre Bragg gratings must in this case be sufficiently far apart so that the shift in the Bragg wavelength over the operating range of any grating does not overlap the different Bragg wavelength associated with another fibre Bragg grating. This provides a major restriction on the number of fibre Bragg gratings that can be interrogated with one sensor, introducing a degree of insensitivity to the system as the total number of Bragg wavelengths able to be sensed is severely limited to around 10 with the broadband light sources and spectrometers currently available. This means that a sensor with a fibre optic cable 10 m long will only have one fibre Bragg grating per meter. This creates large gaps where there is no sensitivity as local heating between two fibre Bragg gratings would not be detected. This is unsuitable for applications where a localised "hot-spot", only a few centimeters long, must be able to be detected anywhere along a sensor which may be many meters long.
The insensitivity described above is caused by a practical limit on the length a single fibre Bragg grating can have. Also, larger fibre Bragg gratings typically have a lower reflectivity per unit length, meaning that the reflection returned is an average of the total length of the fibre Bragg grating. In this case, the reflection from a localised "hot-spot" on the fibre Bragg grating would be relatively weak and difficult to detect.
The present invention offers an improvement to the approaches described above.


A seat track assembly is provided for adjusting a seat assembly of an automotive vehicle having a lower track (12) having a plurality of locking windows (74), an upper track (14) slidably mounted to the lower track and having a plurality of first (70) and second (72) support apertures. A locking mechanism (80) is operatively coupled between the lower and upper tracks. The locking mechanism includes a plurality of pins (88) movable in and out of a locked position, wherein the pins project through the locking windows and are supported by the first and second support aperture in a double shearing condition to prevent sliding adjustment of the upper track relative in the lower track.

1. Field of the Invention
The present invention relates to a track assembly for a seat assembly of an automotive vehicle. More particularly, the present invention relates to a seat track assembly having a locking mechanism with a plurality of locking fingers movable between a locked position for interlocking upper and lower tracks of the seat track assembly and an unlocked position disengaged from the tracks to allow sliding movement therebetween.
2. Description of the Related Art
Automotive vehicles include seat assemblies for supporting occupants above a floor in the vehicle. Typically, a seat assembly includes a track assembly that is operatively coupled between the seat assembly and the floor of the vehicle and allows selective forward and rearward movement of the seat assembly relative to the floor. The track assembly typically includes a lower track and an upper track slidably engaged therewith, which allows the sliding movement of the seat assembly relative to the floor. Latch or locking mechanisms are commonly known in the art for interlocking the upper and lower tracks to prevent the forward and rearward movement of the seat assembly relative to the floor.
One type of locking mechanism known in the art utilizes a plurality of locking pawls or pins that engage one or more slots or apertures on the lower track to interlock the upper and lower tracks. Examples of these types of locking mechanisms are disclosed in German patents DE 19735030A1, DE 29700866U1 and in U.S. Pat. Nos. 5,596,910 and 5,564,315.
These type of locking mechanisms do not allow "infinite" or "positive" engagement between the upper and lower tracks. That is, the upper track is not lockable relative to the lower track in any position. Rather, the upper track is adjustable relative to the lower tracks in predetermined increments of adjustment, as the occupant of the seat assembly must properly position the upper track along the lower track until at least one of the pins is aligned with the aperture to engage therewith and interlock the upper and lower tracks. Further, such locking mechanisms typically allow a predetermined amount of play or chuck between the upper and lower tracks.
It remains desirable to provide a seat track assembly having a locking mechanism that provides a minimal increment of adjustment and at the same time minimizes chuck between the upper and lower tracks.

Locking mechanism for seat track assembly


Among other things, a seat includes a base; a back-supporting surface coupled to the base; and a seating surface movable relative to the base in a direction of motion toward and away from the back-supporting surface. The back-supporting surface has a lower portion nearer the seating surface that is movable, relative to an upper portion of the back-supporting surface that is farther from the seating surface, in the direction of motion as the seating surface moves in the direction of motion.

A seat can support a user in a seated position to relieve physical stress associated with standing and to allow the user to engage in one or more sedentary activities for prolonged periods of time. Examples of such activities include working at a computer, reading, watching television, and driving an automobile.
Although sitting can alleviate physical stress associated with standing, the user's body can experience other types of physical stress in the seated position. Examples include stress on the user's back, hip, or neck. The amount of stress placed on parts of the user's body in the seated position can be a combination of the user's posture while in the seated position and the amount of time the user spends in the seated position, among other things. Prolonged periods of sitting can also result in circulatory problems that may cause injury to joints or other physical complications. In some circumstances, prolonged periods of sitting with inadequate support can result in injury to the user.
The immobilization of joints through prolonged periods of sitting can lead to chronic inflammation which may be linked to other diseases, such as heart disease, diabetes, Alzheimer's, stroke, and cancer.


The invention provides copolymers of ethylenically unsaturated monomers and of ethylenically functionalized nanoparticles in the form of their aqueous polymer dispersions or water-redispersible polymer powders, obtainable by means of free-radically initiated polymerization in an aqueous medium and, if desired, subsequent drying of the resultant polymer dispersion, of

1. Field of the Invention
The invention relates to copolymers of ethylenically unsaturated monomers and of ethylenically functionalized nanoparticles in the form of their aqueous dispersions or water-redispersible powders, and to their preparation and use.
2. Description of the Related Art
Polymer dispersions which comprise particles having dimensions in the nanometer range, e.g. particles measuring less than 100 nm in at least one dimension, have a host of innovative properties which are superior to those of composites containing particles which are not so fine, in the micrometer range, for instance. These properties include, for example, light scattering, adsorbency and absorbency, antibacterial properties, or superior scratch resistance and tensile strength. These "nanoeffects" correlate directly to the size of the particles and are lost if the particles exceed certain dimensions.
Furthermore, the desired effects are only particularly pronounced when success is achieved in distributing the particles as homogeneously as possible in the polymer matrix and, if possible, attaching them chemically to it, in order to prevent leaching or agglomeration phenomena and hence a loss of these special properties.
One way of chemically attaching nanoscale metal oxides to polymeric matrices is described for example in DE 10212121 A1 for nano-zinc oxide polymer dispersions. The zinc oxide particles are dispersed in a halogen-containing medium, the dispersion is introduced into an aqueous solution of hydroxyl-containing inorganic polymers, such as of hydrolysed polyalkyl(alkoxy)siloxanes, and then the halogen-containing constituents are removed by distillation. Chemical attachment to the polymer thus takes place via the formation of a Zn—O—Si—O—C bridge and is therefore very unstable with respect to acidic or alkaline cleavage.
Where the particles are silicone resins it is known that they can be used for chemical modification of organic polymers or as binders of coatings in order to increase the resistance of the coatings, for example, to weathering effects, chemical attack and thermal loading. Commercially available products are, for example, silicone polyesters, hybrid systems of silicone resins and organic polymers of the kind used to produce coil coatings. These products are preferably prepared by chemical reaction and bond formation between the silicone resin and the organic polymer. Chemical attachment of the silicone resins to the organic polymer takes place in general by the formation of an Si—O—C bridge between the two, typically in a solvent operation. For aqueous media the literature includes a variety of products comprising combinations of organic polymers with silicone resins or resin-like oligomeric silicone structures, and processes for their preparation:
EP 1256611 A2 describes an aqueous dispersion obtained from a mixture and emulsion of non-free-radically polymerizable alkoxysilanes or their hydrolysis and condensation products with free-radically polymerizable monomers. The silanes or products derived therefrom are hydrolysed and condensed, while the organic monomers are free-radically polymerized. The silanes used in this case are alkyl- or arylalkoxysilanes, for which there can be up to three alkoxy groups attached to silicon. It is possible therefrom, by means of hydrolysis and condensation, to access resins or resin-like oligomers, inter alia.
EP 1197502 A2 teaches the preparation of an aqueous resin emulsion by free-radical polymerization of ethylenically unsaturated monomers in the presence of hydrolysable and condensable mono-, di- or trialkoxyalkyl- or -aryl-silanes which are not free-radically polymerizable.
EP 943634 A1 describes aqueous latices intended for use as coating materials and prepared by copolymerizing ethylenically unsaturated monomers in the presence of a silicone resin containing silanol groups. In this case interpenetrating networks (IPNs) are formed between the polymer chains and the polysiloxane chains.
The silicone resin emulsion polymers obtainable by the stated processes, and also the otherwise well-known physical mixtures of silicone resin emulsions and organic polymer dispersions, for use for example in the field of silicone resin masonry paints, are notable for the fact that the silicone resin and the organic polymer are present, exclusively or predominantly, in the form of physical blends. Chemical bonds between the silicone fraction and the organic fraction form on more of a chance basis, and are Si—O—C bonds, which are susceptible to hydrolysis. The Si—O—C bond is always in competition with the formation of Si—O—Si bridges as a result of condensation of the silanol groups with one another.
The condensation reactions of the silane units or their hydrolysed and partially-condensed oligomers under the hydrolytic conditions of emulsion polymerization cannot be adequately controlled. It is known that alkoxysilanes having short, oxygen-attached alkyl radicals, in particular, have a pronounced tendency, under hydrolytic conditions, to continue condensing until they form solid particles. These particles tend to form precipitates and domains, and hence tend towards separation. The greater the number of alkoxy groups attached to the silicon, the more pronounced this tendency. In a coating material application, this may have an adverse effect in the form of pinholes being formed. Separation may detract from the storage stability and functional capacity of the products.
A more defined attachment of the silicone unit to the organic polymer, via the formation of C—C bonds, may be accomplished by copolymerizing double bond-functionalized silicones with organic monomers. For example, EP 1308468 A1 describes hydrophobically modified copolymers obtained by copolymerizing linear silicones having up to two polymerizable groups in emulsion with organic monomers. A similar approach is taken by EP 352339 A1, in which vinyl-terminated, linear polydimethylsiloxanes are copolymerized with (meth)acrylate monomers. EP 771826 A2 describes the emulsion polymerization of (meth)acrylic esters and vinylaromatics, crosslinking being effected by addition of difunctional silicones containing acrylic or vinyl groups. EP 635 526 A1 describes functional graft polymers which are based on organopolysiloxanes and are obtained by grafting ethylenically unsaturated monomers onto polyorganosiloxanes which contain hydrogen or functional groups, and also ethylenically unsaturated groups.
The preparation of organocopolymer dispersions containing particles is subject matter of EP 1216262 B1 and EP 1235869 B1, where an aqueous dispersion of inorganic particulate solids and organic polymer is prepared using inorganic particulate solids which are characterized by a defined degree of dispersion and a defined electrophoretic mobility and in whose presence ethylenically unsaturated monomers are polymerized. EP 505230 A1 describes the encapsulation of silica particles with organic polymer, the silica particles first being functionalized with ethylenically unsaturated alkoxysilane compounds and then ethylenically unsaturated monomers being polymerized in aqueous dispersion in the presence of the functionalized particles.

Abstract: A) one or more monomers from the group consisting of vinyl esters, (meth)acrylic esters, vinylaromatics, olef ins, 1,3-dienes, vinyl ethers and vinyl halides and, if desired, further monomers copolymerizable therewith, in the presence of

Abstract: B) at least one particle P having an average diameter of ≦1000 nm, which is functionalized with ethylenically unsaturated, free-radically polymerizable groups, characterized in that

Abstract: B2) particles P used are one or more from the group of metal oxides and semimetal oxides, and/or

Abstract: B2) particles P used are silicone resins composed of repeating units of the general formula [R4(p+Z)SiO(4−p−Z)/2] (II), where for at least 20 mol % of the respective silicone resin p+z=0, 1 or 3,

Abstract: and where B1) and B2) are each functionalized with one or more α-organosilanes of the general formula (R1O)3−(R2)nSi—(CR32)—X (I), where X is a radical having 2 to 20 hydrocarbon atoms and containing an ethylenically unsaturated group.