A sample hold circuit and a method for sampling and holding a signal are provided. The sample hold circuit includes a sample unit, a direct current (DC) voltage elimination unit, and a hold unit. When the sample hold circuit is in a first state, the sample unit samples an input signal, and the DC voltage elimination unit lowers a predetermined percentage of the DC voltage in the input signal sampled by the sample unit. When the sample hold circuit is in a second state, the DC voltage elimination unit eliminates the residual percentage of the DC voltage, and the hold unit outputs the alternating current (AC) signal in the input signal sampled by the sample unit.

1. Field of the Invention
The present invention generally relates to a sample hold circuit and a method for sampling and holding a signal, and more particularly, to a sample hold circuit of an analog-to-digital converter (ADC) and a method for sampling and holding a signal.
2. Description of Related Art
Most of physical signals generated in daily life are analog signals. However, since a digital signal is easy to be edited, analyzed, stored and has a better anti-noise capability, in an actual application, the analog signal is generally converted into the digital signal through an analog-to-digital converter (ADC).
The ADC plays an important role in wireless communication systems and portable video image devices, and as the wireless communication systems and the portable video image devices are quickly developed, demand for a high conversion speed of the ADC is increased. In various types of ADC structures, a pipelined ADC can achieve features of high-speed input and fast processing. In a general ADC, a sample hold circuit is generally disposed at a front end thereof, which is used for holding the analog signal. Since a sampling time is very short, a sampling output is a series of discontinuous narrow pulses, so that certain time is required to digitalize each of the sampled narrow pulse signals. Therefore, between two samplings, the sampled analog signal is temporarily stored until a next sampling pulse is received, and such operation is referred to as "hold". According to a basic principle of digital signal processing (i.e. the Nyquist sampling theorem), if the extracted analog signal is required to be accurately and truly rendered, a sampling frequency has to be higher than twice of a maximum frequency. Therefore, the conversion speed of the ADC is usually determined by an operation frequency of the sample hold circuit. As a signal processing speed of the ADC becomes higher, demand for the operation frequency of the corresponding sample hold circuit is accordingly increased. Therefore, to improve the operation frequency of the sample hold circuit to cope with an actual demand is an important subject.
FIG. 1 is a circuit diagram of a conventional sample hold circuit. Referring to FIG. 1, the sample hold circuit 100A includes switches SW1A-SW9A, capacitors C1A-C6A, and an operational amplifier 102A. The switches SW1A, SW2A, SW3A, SW6A, and SW9A are controlled by a first signal PH1 to be turned on when the sample hold circuit 100A is in a sampling state and to be turned off when the sample hold circuit 100A is in a holding state. Besides, the switches SW4A, SW5A, SW7A, and SW8A are controlled by a second signal PH2 to be turned off when the sample hold circuit 100A is in the sampling state and to be turned on when the sample hold circuit 100A is in the holding state. The voltage level of the first signal PH1 and the voltage level of the second signal PH2 are not high voltage levels at the same time. FIG. 2 illustrates the waveforms of the first signal PH1 and the second signal PH2. Referring to FIG. 2, the first signal PH1 and the second signal P112 are two rectangular wave signals reverse to each other. When the first signal PH1 is at a high voltage level, the second signal PH2 is at a low voltage level, and when the first signal PH1 is at the low voltage level, the second signal PH2 is at the high voltage level.
FIG. 3 is an equivalent circuit diagram of the sample hold circuit in FIG. 1 when the sample hold circuit is in the sampling state. Referring to FIG. 3, a short circuit is formed between the end T1 of the capacitor CIA and the end T2 of the capacitor C2A, and the voltage of the ends T1 and T2 is equal to a common voltage VCM, so that the charge provided by the waveform signal VIP and the ground signal VIN is stored in the capacitor C1A and the capacitor C2A. In addition, a short circuit is also formed between the output terminals VOP and VON, and because the voltage of the output terminals VOP and VON is equal to the common voltage VCM, no charge is stored in the capacitor C3A or the capacitor C4A. FIG. 4 is an equivalent circuit diagram of the sample hold circuit 100A in FIG. 1 when the sample hold circuit 100A is in the holding state. Referring to FIG. 4, the switches SW4A and SW5A connected with the capacitors C1A and C2A in parallel are turned on and accordingly respectively form a short circuit path between the two ends of the capacitor C1A and the capacitor C2A, so that the charge stored in the capacitors C1A and C2A when the sample hold circuit 100A is in the sampling state is transferred into the capacitors C3A, C4A, C5A, and C6A. The charge stored by the sample hold circuit 100A in the sampling state can be expressed as:C1A×(VIP−VCM )−C2A(VIN−VCM)  (1)
The charge stored by the sample hold circuit 100A in the holding state can be expressed as:C5A(VRP−VCM)−C6A(VRN−VCM)+C3A(VOP−VCM)−C4A(VON−VCM)  (2)
Based on the charge conservation law, the total charge stored by the sample hold circuit 100A in both states can be expressed as:C1A×(VIP−VCM)−C2A(VIN−VCM)=C5A(VRP−VCM)−C6A(VRN−VCM)+C3A(VOP−VCM)−C4A(VON−VCM)  (3)
Assuming the capacitance of each of the capacitors C1A-C6A is C, foregoing equation (3) is rewritten as:C×(VIP−VIN)=C×(VOP−VON)+C×(VRP−VRN)  (4)
It can be obtained from foregoing equation that (VOP−VON)=(VIP−VIN)−(VRP−VRN), wherein (VRP−VRN) is the direct current (DC) portion in the sampled analog signal, and (VOP−VON) is the alternating current (AC) portion in the sampled analog signal. Thus, the sample hold circuit 100A can eliminate the DC voltage (VRP−VRN) in the analog signal and provide an input signal without the DC voltage (VRP−VRN) at the output terminals VOP and VON.
FIG. 5 illustrates the variation of the voltage difference (VRP−VRN) between the two reference voltages VRP and VRN in FIG. 1 along a time axis. Referring to FIG. 1 and FIG. 5, while in the holding state, the conventional sample hold circuit 100A eliminates the DC signal in an analog signal sampled when the sample hold circuit 100A is in the sampling state by using the capacitors coupled to the input terminals of the operational amplifier 102A and the reference voltages, so as to output the AC portion of the sampled analog signal. Because the conventional sample hold circuit 100A completely eliminates the DC signal in the analog signal at a time in the holding state by using the reference voltages and the capacitors, the voltage levels of the reference voltages are quickly pulled down to a low level when the sample hold circuit 100A enters the holding state. When the operation rate of the ADC increases, the reference voltages cannot return to their original voltage levels in time, so that the DC signal in the analog signal cannot be completely eliminated. As a result, the ADC outputs an incorrect signal.

Sample hold circuit and method for sampling and holding signal


Provided is a depth image generating apparatus. The depth image generating apparatus may include a filtering unit, a modulation unit, and a sensing unit. The filtering unit may band pass filter an infrared light of a first wavelength band among infrared lights received from an object. The modulation unit may modulate the infrared light of the first wavelength band to an infrared light of a second wavelength band. The sensing unit may generate an electrical signal by sensing the modulated infrared light of the second wavelength band.

1. Field
Embodiments relate to a method and apparatus for generating a depth image, and more particularly, to a method and apparatus that may acquire a depth image using an infrared light.
2. Description of the Related Art
Currently, interest on a three-dimensional (3D) image is increasing. A method of obtaining 3D spatial information of an object may include a method of scanning the object using a laser, a method of photographing a depth image using an infrared light, and the like.
A method of generating a depth image using an infrared light may employ a time of flight (TOF) scheme, a coded light triangulation scheme, and the like.
The TOF scheme may obtain depth information that is a distance between an object and a depth camera using a phase difference between an emitted infrared light and an infrared light reflected and returned from the object.
The coded light triangulation scheme may obtain depth information by triangulating a path between a pattern of the emitted infrared light and a pattern of the infrared light reflected and returned from the object.
In general, the above TOF scheme and the coded light triangulation scheme may use an infrared light having a wavelength band of 800 nm to 900 nm since a commercialized silicon based image sensor senses an infrared light of 400 nm to 1100 nm. Also, an infrared light having a wavelength band less than or equal to 800 n may be perceived by eyes of a human being, and a sensitivity of a sensor may be deteriorated with respect to an infrared light having a wavelength band greater than 900 nm.
The infrared light having the wavelength band of 800 nm to 900 nm generally exists in an outdoor sunlight environment. Accordingly, when the depth camera uses the infrared light having the above wavelength band, the depth camera may have difficulty in acquiring a depth image.

Apparatus and method for generating depth image


A method of detecting relief contours in digital images representing an aerial or satellite view of the ground includes the steps of calculating a digital elevation map from two stereoscopic images of the terrain, extracting crest lines in the digital map, projecting the crest lines into one of the stereoscopic images, calculating contours in the image and deciding that a contour is a relief contour if the distance to the closest projected crest line, in the sense of a particular affinity criterion, is below a particular threshold.

1. Field of the Invention
The present invention concerns a method of detecting relief contours in digital images representing an aerial or satellite view of the ground. An application of the method constructs accurate crest lines on a digital elevation map.
2. Description of the Prior Art
Contour detection is a standard problem in image analysis and there are many techniques available. However, these prior art techniques do not address themselves to the nature of the contours and in particular cannot distinguish contours representing relief discontinuities (typically crest lines) from texture contours (for example the boundary between a cultivated field and a forest).
There are many applications of a method of distinguishing relief contours and texture contours. One example is detecting man-made structures in aerial or satellite images. These structures are generally characterized in that they have sharp edges (i.e. crest lines) which can be located to detect the contours of the structure. The prior art methods are evidently insufficient to solve this kind of problem.
The present invention alleviates this insufficiency and proposes a method of analyzing images capable of detecting only contours marking crest lines, exclusively.
For this the method of the invention requires two calibrated stereoscopic images of the same terrain, i.e. two images of the same terrain taken with different but known imaging parameters.

Method of detecting relief contours in a pair of stereoscopic images


A network-based software application for enabling remote authentication of a user during a network session has a server portion for serving session validation information and additional user information when queried, a client portion for configuring and submitting parameters constraining what and how data is to be shared with a querying entity or entities, and a distributed portion for distribution and application at various connected network nodes for enabling those nodes to recognize and interact with the server portion. The application is characterized in that the server portion generates a temporary session token after a first successful authentication by the user at a web site during a network session, the token cached at the host machine of the server portion and at the user's machine or proxy machine and wherein upon navigation by the user to a next web site or form requiring secure authentication, the token is used to identify the user and a remote call is used to validate the user session instead of requiring manual authentication procedures.

Internet browser navigation, typically referred to as "Web surfing" in the art, is well known as a mechanism enabling user access to server-stored electronic information pages on a navigable network such as the Internet network. A typical user navigating the Internet for example may be subscribed to many password-protected Web sites that offer some form of service to the user. Examples of password-protected sites may include financial service sites such as investment, mortgage, and online banking sites, travel sites, certain entertainment and music sites, news service and information sites, and so on.
Typically, a user will have a variety of different passwords and/or personal identification numbers (PIN) that must be provided to successfully log in to many of the types of sites described above. As a result, a user is frequently required to enter login information as new password protected sites or pages are navigated to. A Web browsing session embarked to conduct a large chunk of Web business, for example, may involve several logins during one Internet session. Having to remember many passwords and PIN numbers can be problematic for a user.
One way to deal with this problematic scenario that is known to the inventor has been to aggregate and manage a user portfolio of passwords and other login information at a secure proxy/portal location such that automated aggregation and automated logins, when required are performed using the appropriate stored passwords from the user profile. Although this method is secure and fairly error free, some users are never the less uncomfortable having a third party manage their security passwords and other critical information.
In prior art, a federated convention known as domain name service (DNS) exists that provides a look-up service for IP addresses on a network for navigating purposes. The service finds an IP address for a querying machine. The IP address is a temporary network address comprising numbers separated by dots. IP addresses are both allocated and assigned depending on the type of use and class of the address. Every desktop machine and network server capable of TCP/IP communication has DNS software installed. A client machine that is transient will retain the same IP address only while it is logged on to the Internet during a single network session. While DNS system can identify a specific machine during a multi-site browsing session, it cannot provide any specific user information.
It has occurred to the inventor that if the host of a password protected or otherwise secure Web site or Web function could identify a user remotely by knowing the user ID at a level that is more granular than the IP address and could validate the state of a current session from a reliable source, then it could gain efficiency by servicing the user as logged in
Therefore, what is clearly needed in the art is a distributable user verification system and service that can authenticate user to site hosts along any navigation sequence and enable the user to avoid repeated login procedures that may have otherwise been required along the navigated route.

Method for verifying the identity of a user for session authentication purposes during Web navigation


A method for pattern recognition of indicia composed of alphabetical characters of a language in the form of at least a part of a word. The shape of each character in a word is established by means of a pattern shape recognizer. A probability value designating the relative confidence in the recognition of the character as one of the language characters is assigned to each character. The established shapes of the characters are then sequentially applied to a linguistic recognizer for further processing and the probability values of language structure to each of the language characters is assigned. Then the probability values assigned to the characters in the shape recognizer is combined with the corresponding probability values assigned to the characters in the linguistic recognizer and the path between characters possessing the highest probability values is determined.

Initial approaches to recognize handwritten text have primarily concentrated on criteria to match the input pattern against reference patterns, and to select that reference symbol which best matched the input pattern as the recognized pattern. This family of matching criteria is often called "shape matching". A wide variety of shape-based recognition systems are known in the art. Representatives of such shape-based recognition systems are described in U.S. Pat. Nos. 3,930,229; 4,284,975 and 4,653,107.
Common to all the shape-based systems is that irrespective of the matching criteria used, the information is processed locally, and that such systems are not very accurate in resolving ambiguities among reference patterns which exhibit shape similarity.
The use of character context or linguistic rules as additional information for recognizing characters has been extensive in a variety of fields, such as cryptography, natural language processing, etc. Systems introducing global context and syntax criteria have been offered for improving shape-based recognition, in order to distinguish among members of a "confusion set." A system representative of this approach is described in U.S. Pat. No. 4,754,489. The system of this patent uses conditioned probabilities of English characters appearing after a given character sequence, and probability of groups of English characters to suggest syntax rules.
Another representative system is described in U.S. Pat. No. 4,718,102, which is directed to ideogram-based languages such as Kanji, in which a shape-based algorithm producing a confusion set is disambiguated by simulating human experience. The disambiguating routines are based on actual studies of particular characters.
It appears that the approaches taken heretobefore resulted in systems suffering from the following problems: They are not sufficiently general to cover different languages; require computationally prohibitive time and memory resources; do not include the shape information in a statistical, meaningful fashion; are not adaptive in texts of varying linguistic and syntax content; and operate as post-processes, not contributing to the segmentation of input patterns.


When the trigonometric function of the phase lag of the hydraulic excitation of the runner vanes, which varies in accordance with the combination of the number of runner vanes and the number of guide vanes of a high head pump/turbine, is denoted by cos(.theta..sub.R n), the thickness of the crown along a circle of a diameter at a mid point of the diameter of the outermost periphery of the runner is denoted by t.sub.MC, the thickness of the band is denoted by t.sub.MB, the mean thickness of the crown at the outer peripheral portion of the runner is denoted by t.sub.C, the mean thickness of the band is denoted by t.sub.B, and the rigidity ratio of the crown and band to the runner vane is denoted by K.sub.R taking the rigidity of the runner vane as a reference, the moment coefficient C.sub.MO which is a function of cos(.theta..sub.R N) and the rigidity ratio K.sub.R is selected to be less than 0.5 in accordance with the value of cos(.theta..sub.R n), and relations t.sub.C /t.sub.MC .ltoreq.1 and t.sub. B /t.sub.MB .ltoreq.1 are selected when the value of cos(.theta..sub.R m) is positive and relations t.sub.C /t.sub.MC .ltoreq.1 and t.sub.B /t.sub.MB .ltoreq.1 are selected when the value of cos(.theta..sub.R n) is negative.

This invention relates to a high head pump-turbine having a unitary runner made up of a rigid combination of a circular plate shaped crown (upper plate), a band (lower plate), and a plurality of runner vanes which are arranged to form a circular vane cascade between the crown and band, wherein the flow path height at the outermost periphery between the crown and band is much smaller than the outermost diameter of the runner, and the runner is formed in a flattened state.
FIG. 11 of the accompanying drawings shows a general construction of a conventional high head pump-turbine. A runner 2 is secured to the lower end of a main shaft 1 which is directly connected to a generator/motor (not shown). About the runner 2 are disposed a plurality of guide vanes 3 arranged to form a stationary circular vane cascade as shown in FIG. 12. As shown in FIGS. 13 and 14, the runner 2 is formed as an integral structure including a rigid combination of a circular disc shaped crown 2a, a band 2b and a plurality of runner vanes 2c arranged as a moving circular vane cascade. The upper portion of runner 2 is covered by an upper cover 4, while the lower portion of runner 2 is covered by a lower cover 5, and a runner chamber 6 is defined between the upper and lower covers 4 and 5 for accommodating the runner 2.
When the pump-turbine is used as a turbine, high pressure water is admitted into a spiral casing 7 provided to encompass the runner 2 via stay vane 8, and guide vanes 3 to flow into the runner chamber 6. The water flows uniformly from the outside around the outer periphery of runner vanes 2c, and then flows radially inwardly through peripheral inlet paths defined between these runner vanes 2c, thereby rotating the runner 2. Thereafter, the water is discharged to the outside from the lower end of the main shaft 1 through a draft tube 9.
In a high head pump-turbine installed in a high head pumped storage power station usually having an operating head of more than 400 m, for the purpose of operating the pump-turbine at a high speed and with a small quantity of water flow as a result of high head, the runner 2 is required to have a flat characteristic construction such that the height B of the outermost flow passage between the crown 2a and band 2b is less than 0.1 times outermost peripheral diameter D.sub.O of the runner, and that the number Z.sub.R of the runner vanes 2c constituting a moving vane cascade is selected to be in a range of 6 to 8, and that the number Z.sub.G of guide vanes 3 constituting a stationary vane cascade is selected to be in a range of 12 to 32, so that Z.sub.G is larger than Z.sub.R.
During the operation of such a high head pump/turbine, as above described, the high pressure water flowing into the runner chamber 6 through guide vanes 3 constantly collides with the runner vanes 2c so that the leading edges of the runner vanes 2c in the moving vane cascade of the rotating runner 2 regularly and repeatedly pass by the trailing edge portions of the guide vanes 3 and between the vanes 3 in the stationary vane cascade. As a consequence, the runner is subjected to a regularly varying hydraulic exciting force caused by hydraulic interference between the moving vane cascade and the stationary vane cascade (see FIG. 15). Consequently, in the runner 2, due to the hydraulic exciting force mentioned above, the crown 2a and the band 2b are subjected to a disc vibration having nodes at rigid joints between the crown 2a and the band 2b and the runner vanes 26. Especially, a runner of a flat and disc type of a high head pump-turbine having a height B of the outermost peripheral flow path between the crown and band which is less than 0.1 times the outermost diameter D.sub.o, is subjected to an extremely severe vibration giving rise to a large vibration stress.
The frequency f.sub.H of the hydraulic exciting force acting on the runner 2, when it is rotated at a rated speed, is expressed by a relation Z.sub.G .multidot.N.sub.o /60 (Hz) (where N.sub.o represents the rotational speed (r.p.m.)) because the runner vanes 2c are subjected to Z.sub.G times hydraulic interference corresponding to the number of the guide vanes 3 in the stationary vane cascade during one revolution. In the case where the natural vibration frequency f.sub.N of the runner 2 is close to the frequency fx of the hydraulic excitation, the vibration stress becomes larger due to a resonance phenomenon. Even when such resonance state can be avoided under a condition in which vibration response of the runner 2 with respect to the hydraulic exciting force is large, the vibration stress nevertheless becomes large, thereby hastening runner fatigue which ultimately results in fatigue destruction of the runner 2.
For decreasing the runner vibration stress, a method of avoiding the resonance phenomenon by adjusting the natural vibration frequency f.sub.N of the runner to a level remote from the hydraulic excitation frequency f.sub.H is disclosed in Japanese Laid Open Patent Specification No. 173568/1984. However, this method is not always adequate for the actual state of the runner vibration, and can not attain its objective.
More particularly, in the prior art investigation, the manner in which the hydraulic exciting force acts on the runner and by what mechanism the vibration takes place has not been made clear. For this reason, the fundamental primary factor influencing the runner vibration and the magnitude of the vibration stress have not been correctly understood. Furthermore, it has not been made clear as to in what case the vibration stress increases and countermeasures to prevent this problem have not been developed.
We have clarified the mechanism of the runner vibration and the fundamental primary factor influencing the runner vibration and the magnitude of the vibration stress as disclosed in our technical paper presented in the JSME symposium on fluid engineering No. 900-54, entitled "Vibration Behavior of Runners of High Head Pump-Turbines (first report)", page 40-51 on Aug. 29 and 30, 1990, in Tokyo.
A summary of the technical paper is as follows:
(1) In the past, the runner vibration was considered on the assumption that the runner has the construction of a simple disc. In this paper, however we have considered that the runner consists of a disc shaped crown as a horizontal member, a disc shaped band as another horizontal member and the runner vanes as vertical members arranged to form a circular vane cascade between the two horizontal members, and that the runner is replaced by an annular Rahmen (skeleton structure) formed by a rigid combination of the horizontal and vertical members. This construction is dynamically close to the real state of the runner and thus we have studied the runner vibration.
(2) The rotating runner is subjected to a periodically varying hydraulic exciting force having an amplitude F.sub.VO on each runner vane due to the hydraulic interference (see FIG. 16) between the runner vanes 2c and the guide vanes. Denoting the center angle of the vane array spacing of the runner vane cascade by .theta..sub.R =[2.pi./Z.sub.R) and denoting an integer n[=Z-mZ.sub.R ] having a minimum absolute value of a relative difference obtained by subtracting a positive integer multiple m.multidot.Z.sub.R of Z.sub.R from Z.sub.G, the phase lag of hydraulic exciting forces acting upon adjoining two runner vanes is expressed by an equation .theta..sub.R .multidot.n[=(2.pi./Z.sub.R) (Z.sub.G -mZ.sub.R)] which is expressed by combined functions of Z.sub.G and Z.sub.R.
(3) Due to the effect of the hydraulic exciting forces acting on each of the runner vanes, a dynamic exciting bending moment which varies with the same period as the hydraulic exciting forces is applied to joints of the runner vane to the crown and band. This dynamic exciting bending moment is the product obtained by multiplying by a moment coefficient C.sub.MO the maximum producible exciting moment m.sub.o which is the runner fixed end moment arising because when the rigidity of the crown and band is extremely high, only the runner vane side assumes all of the bending deformation that should be shared by the crown, the band, and the runner vanes. Thus, the exciting bending moment of the joint parts on the joint parts on the runner vane side become M.sub.o (=C.sub.MO m.sub.o), and the exciting bending moment of the joint parts on the crown and band side becomes M.sub.o/2.
The moment coefficient C.sub.MO, that is the moment amplitude ratio (M.sub.o /m.sub.o) in which m.sub.o is taken as a reference can be given by the following theoretical equations by using a trigonometrical function cos(.sub..sub.R n) of the phase leg .theta..sub.R n of the hydraulic exciting force and a function of a rigidity ratio K.sub.R of the crown and band by taking runner vanes as a reference. EQU C.sub.MO =2K.sub.R {1+4(3K.sub.R +1).sup.2 -4(3K.sub.R +1) cos(.theta..sub.R n}.sup.1/2 /(2K.sub.R +1).multidot.(6K.sub.R +1)(1)
Denoting the thickness ratio of the crown and band to the runner vanes by t/tv and the sectional secondary moment ratio by I/I.sub.v, the rigidity ratio K.sub.R of the crown and band to the runner vanes can be calculated by the following equation. ##EQU1##
These equations show that C.sub.MO increases when the thicknesses of the crown and band are increased to increase K.sub.R and that when K.sub.R is made to be extremely large, C.sub.MO becomes 1 and M.sub.o becomes the maximum value of mo.
(4) Due to the action of the dynamic moment at the joints, the crown and band between the runner vanes accompany a disc vibration with displacement in the direction of the axis of the runner rotation wherein the joints of the crown and band to the runner vanes act as a node. Then, at each joint, vibration stress proportional to the exciting bending moment is generated.
(5) Where the damping ratio .parallel. of the vibration (c/2(mk).sup.1/2, where c represents a viscosity damping coefficient, m represents mass and k a spring constant) is made to be constant,, the magnitude of the vibration stress amplitude .DELTA..sigma. varies in direct proportion to a moment coefficient C.sub.MO (=M.sub.o /m.sub.o) representing the magnitude of the dynamic bending moment M.sub.o. The basic influencing factors on C.sub.MO are a phase lag .theta..sub.R n between the hydraulic excitations acting on adjoining two runner vanes and the rigidity ratio K.sub.R of the crown and band to the runner vanes. By decreasing K.sub.R and by keeping the phase lag .theta..sub.R n to be adequate, C.sub.MO can be decreased. Then the vibration stress .DELTA..sigma. can be decreased in direct proportion to C.sub.MO.
(6) Where the effect of the damping ratio of the vibration is taken into consideration, as the rigidity ratio K.sub.R decreases from a large value caused by the decrease of K.sub.R due to a decrease of the thicknesses of the crown and band, the damping ratio .xi. tends to increase due to the attenuation of the spring constant so that the vibration stress amplitude .DELTA..sigma. decreases to a small value less than a decreased level in direct proportional to the decrease of C.sub.MO.


A stationary material mixing apparatus located within a cylindrically-shaped conduit. The material mixing apparatus includes a front face, rear face, cone-shaped module having a base and apex supported on said front face and extending toward an upstream end of the conduit. A channel for introducing an additive to the fluid stream is provided, the additive being introduced at the apex of the cone-shaped module, the material mixing apparatus further being provided with three circular openings positioned 120 degrees from each other and each having a baffle configured therein.

It is common practice to mix particulate solids, liquids and gases with motionless mixers having, as the name implies, no moving parts. Mixers of this category consist of baffles of various types arranged sequentially in a tube or pipe. By a process of division and recombination, separate input components can be mixed or dispersed within one another in travelling through the pipe tube or at its output. Static or motionless mixers are composed of a series of geometrically arranged mixing elements fitted within a pipe or tube, the energy of the flow stream being employed to create mixing between two or more fluids. The goal is to maximize fluid mixing while experiencing the lowest pressure loss possible.
Within the general category of static or motionless mixers, there are those referred to as wafer mixers. They are called wafer mixers because they are generally thin and are designed for applications where length is critical or for mixing low viscosity chemicals into a low viscosity stream at very high velocities. Oftentimes, wafer mixers are used with other static mixing devices as an overall solution to fluid mixing. A wafer mixer can be used at the joinder of two or more pipe lengths by fitting it between connecting flanges as noted in reference to FIG. 2. Oftentimes, wafer mixers are employed to provide mixing when the alternative is to not mix at all. Wafer mixers afford an inexpensive static mixing solution for many applications where some level of mixing is needed. Also, wafer static mixers work best when they are used for constant flow conditions. They are not well suited for applications having large differences between maximum and minimum flow rates.
Although wafer mixers should oftentimes be used with other static mixing devices, one should always strive to provide the maximum mixing efficiency whenever a mixer is employed. Most wafer mixing designs, fail to provide a high degree of turbulence or mixing in the downstream pipe length. Further, many do not provide for the injection and mixing of additives, such as those employed in water treatment. Thus, the present invention is intended to address these issues by providing a wafer mixer of far superior design and efficiency.
These and further objects will be readily apparent when considering the following disclosure and appended claims.


A solar energy converter comprises a thin panel enclosure, at least one solar cell contained within the enclosure, and a thin layer of gel contained within the thin panel enclosure and enclosing the at least one solar cell. The thin panel enclosure has a two-dimensional flat base, short side walls, and a transparent lid separated from the flat base by the short side walls, the short side walls enclosing an interior cavity having a depth substantially smaller than either of the two-dimensional base dimensions. The at least one solar cell has a front surface and a back surface. The thin layer of gel wets both the front surface and back surface of the at least one solar cell and holds the at least one solar cell separate from the base and lid.

Solar energy systems have been used to provide electricity and heat for decades. Designers of all types of energy generation systems continually strive to improve output power efficiency. One current problem in a solar cell energy conversion system is the efficient extraction of low-cost electricity. The conversion efficiency of a photovoltaic cell is the proportion of sunlight energy that the cell converts to electrical energy. Improving efficiency is vital to producing solar cells that are competitive with traditional energy sources, such as fossil fuels and nuclear power. The efficiency of solar cells has increased substantially for the earliest conventional photovoltaic devices from about 1 to 2% efficiency. Current conventional photovoltaic systems convert 7% to 17% of light energy into electrical energy.
What is first needed is a system and method for converting energy in a solar cell with extremely high efficiency. What are also needed are solar cell materials and structures, and solar cell fabrication procedures that are inexpensive while attaining high levels of efficiency in energy generation. A further need is a solar cell configuration that permits collection of sunlight energy for conversion to electricity to increase output power generation.

Solar energy converter using a solar cell in a shallow liquid-gel layer


A linear guide apparatus comprises: a slider body having ball rolling grooves opposed to ball rolling grooves of a guide rail which are extended axially in parallel to each other; end caps secured respectively to both ends of the slider body, each end cap having a ball retainer locking portion in a joining surface which is in contact with the slider body; and a ball retainer having engaging portions which are engaged with the ball retainer locking portion of the end caps, and both side walls each of which defines with an edge of one of the ball rolling grooves of the slider body an opening which is slightly smaller than a diameter of rolling balls. The engaging portions are movably engaged with the ball retainer engaging portions of the end caps so that the ball retainer is movably held on the slider body. Thus, the apparatus is excellent in operability in which the balls are not excessively pushed by the ball retainer.

1. Field of the Invention
This invention relates to an improvement of a linear guide apparatus comprising a guide rail and a slider movable on it through rolling of balls interposed therebetween.
2. Description of the Prior Art
A linear guide apparatus has been disclosed, for instance, by instance U.S. Pat. No. 4,929,095 which comprises: an axially extending guide rail with ball rolling grooves formed in both corner edges between an upper surface and both side surfaces; a slider mounted on the guide rail and movable in an axial direction and having ball rolling grooves formed in an inner surface at positions respectively opposing the ball rolling groves of the guide rail, and a plurality of balls mounted in the mutually opposing ball rolling grooves of the guide rail and the slider, and the slider including a slider body, end caps secured to both ends of the slider body, and a ball retainer held by the end caps which is made up of a rectangular frame-shaped main portion, and engaging portions protruded axially from opposite ends of the main portion, the engaging portions being engaged with ball retainer locking portions formed in the end caps to secure the ball retainer to the slider body.
In the conventional linear guide apparatus, the ball retainer is positively fixed by engaging the ball retainer locking portions of the end caps with the engaging portions of the ball holder as was described above. Hence, the apparatus suffers from the following problems: Components forming the apparatus are unavoidably fluctuated in dimension when manufactured; therefore, it is unavoidable that the end caps are shifted in position when connected to the slider body, the ball retainer is shifted in position when coupled to the end caps, or the engaging portions of the ball retainer is shifted. Hence, frequently the ball retainer secured to the slider is greatly shifted towards the train of balls rolling in the ball rolling grooves of the slider. If the ball retainer is shifted in this manner, it applies a great pressure to the balls, as a result of which the balls are not smoothly circulated, thus adversely affecting the operation of the apparatus. The end caps and the ball retainer are injection-molded products of synthetic resin. Hence, even if the molds thereof are satisfactory, the resultant product is often unsatisfactory; that is, the ball retainer mounted is shifted in position depending on delicate differences of molding conditions. In this case, such unacceptable products will be formed in great quantities, and it will take a great deal of labor and time to fix them. However, it is not desirable to increase the manufacturing accuracy of the components of the linear guide apparatus, because it will increase the manufacturing cost of the latter.


A semiconductor memory device includes: a delay locked loop (DLL) for delaying an external clock to generate a DLL clock signal; an internal command signal generator for generating an internal command signal in response to an external command; a delay circuit for delaying the internal command signal by a delay time corresponding to a delay time of the DLL to output a delayed internal command signal; and an output enable signal generator for generating an output enable signal based on the delayed internal command signal and the DLL clock signal.

The present invention relates to a semiconductor device, and more particularly, to a semiconductor memory device, which generates an output enable signal in synchronization with a DLL clock signal, and a method for driving the same.
Synchronous memory devices, e.g., double data rate (DDR) synchronous dynamic random access memory (SDRAM), are designed to generate a plurality of output enable signals in synchronization with a DLL clock signal (CLK_DLL) and having different pulse widths according to a burst length, and to selectively use one of them according to a column address strobe (CAS) latency.
FIG. 1 is a block diagram of a conventional semiconductor memory device.
Referring to FIG. 1, an internal command signal generator 10 receives external command signals to generate a plurality of internal command signals according to their combination. Examples of the external command signals include a chip select signal CS, a write enable signal WE, a row address strobe signal RAS, a column address strobe signal CAS. Examples of the internal command signals include an internal read command signal IRDP. The internal read command signal IRDP contains information on period (tCK) of an external clock signal CLK_EXT and is a pulse signal activated in response to an external read command (RD).
The synchronous semiconductor memory device such as a DDR SDRAM transfers data to other external devices using a delay locked loop (DLL) clock signal (CLK_DLL) produced by delaying a clock signal CLK_EXT inputted from an external device such as a memory controller. Such a clock synchronization circuit includes a phase locked loop (PLL) and a delay locked loop (DLL). The DLL is widely used in semiconductor devices because it has low noise and can be implemented in a small area compared with the PLL.
FIG. 2 is a block diagram of the DLL 20 illustrated in FIG. 1.
Referring to FIG. 2, the DLL 20 includes a clock buffer 21, a first delay line 23, a second delay line 22, a duty cycle corrector 24, a delay replica model 25, a phase comparator 26, and a delay controller 27. The clock buffer 21 buffers an external clock signal CLK_EXT and an external clock bar signal CLKB_EXT to generate a reference clock signal CLK_REF. The external clock bar signal CLKB_EXT is a clock signal having an opposite phase to the external clock signal CLK_EXT. The second delay line 22 delays the reference clock signal CLK_REF corresponding to the external clock signal CLK_EXT in response to a control signal CTR. The first delay line 23 delays a clock signal produced by buffering the external clock bar signal CLKB_EXT in response to the control signal CTR. The duty cycle corrector 24 corrects duty cycles of output signals of the first and second delay lines 23 and 22 to generate rising and falling DLL clock signals RCLK_DLL and FCLK_DLL. The delay replica model 25 delays the DLL clock signal RCLK_DLL through delay elements located in a clock path to generate a feedback clock signal CLK_FDB. The phase comparator 26 compares a phase of the reference clock signal CLK_REF with that of the feedback clock signal CLK_FDB. The delay controller 27 generates the control signal CTR according to an output signal of the phase comparator 26.
The rising DLL clock signal RCLK_DLL has a phase equal to that of the external clock signal CLK_EXT, the falling DLL clock signal FCLK_DLL has a phase opposite to that of the external clock signal CLK_EXT. For convenience, the DLL will be described, centering on the external clock signal CLK_EXT and the rising DLL clock signal RCLK_DLL.
The DLL 20 generates the rising DLL clock signal RCLK_DLL by compensating a clock delay component occurring while the rising DLL clock signal RCLK_DLL is transferred to a data output terminal of the semiconductor memory device, so that signals used for an input/output of a final data can be synchronized with the external clock signal CLK_EXT.
Referring again to FIG. 1, an output enable signal generator 30 receives the CAS latency CL, the burst length BL, the internal read command signal IRDP, and the rising DLL clock signal RCLK_DLL to generate output enable signals OE0, OE1, OE1.5, . . . , OEN, where n is a natural number or (natural number+0.5).
In other words, the internal read command signal IRDP is a pulse signal that is activated in response to the read command, and the output enable signal OE0 is a signal that is activated after a predetermined time elapses from the activation of the internal read command signal IRDP. The output enable signal OE0 has a pulse width corresponding to the burst length BL. The output enable signals OE1, OE1.5, . . . , OEN are signals that are produced by shifting the output enable signal OE0. The output enable signals OE1, OE1.5, . . . , OEN, except the output enable signal OE0, are signals that are activated in synchronization with rising or falling edges of the rising DLL clock signal RCLK_DLL. Generally, the output enable signal generator 30 is designed to generate a plurality of output enable signals OE1, OE1.5, . . . , OEN in synchronization with the rising or falling edges of the rising DLL clock signal RCLK_DLL, such that the output enable signals can be selectively used according to the CAS latency CL.
FIG. 3 is a block diagram of the output enable signal generator 30 illustrated in FIG. 1.
Referring to FIG. 3, the output enable signal generator 30 includes a delay option unit 31, an OE0 generating unit 32, an OE1 generating unit 33, an OE1.5 generating unit 34, . . . , and an OEN generating unit 35. The delay option unit 31 receives the rising DLL clock signal RCLK_DLL and the CAS latency CL to tune the rising DLL clock signal RCLK_DLL according to the CAS latency CL. The OE0 generating unit 32 receives the internal read command signal IRDP and the burst length BL to generate the output enable signal OE0. The OE1 generating unit 33 receives the output enable signal OE0 and an output signal TN_RCLK_DLL of the delay option unit 31 to generate the output enable signal OE1. The OE1.5 generating unit 34 receives the output enable signal OE1 and the output signal TN_RCLK_DLL of the delay option unit 31 to generate the output enable signal OE1.5. Likewise, the OEN generating unit 35 generates the output enable signal OEN. The OE1 to OEN generating units 32, 33, 34, . . . , 35 perform a reset operation in response to a reset signal OE_RESTB.
The delay option unit 31 includes a plurality of delay elements and a plurality of option circuits in order for the tuning operation. The delay option unit 31 is provided for a domain crossing of the external clock signal CLK_EXT and the rising DLL clock signal RCLK_DLL. The domain crossing is a conversion from a receiver domain to a transmitter domain. That is, the domain crossing is a conversion from a domain in which the read command is recognized to a domain in which data is outputted in synchronization with the external clock signal CLK_EXT. The domain crossing will be described later with reference to FIGS. 5 and 6.
FIGS. 4A and 4B are circuit diagrams of the OE1 generating unit 33 and the OE1.5 generating unit 34, respectively.
Referring to FIG. 4A, the OE1 generating unit 33 includes a transfer gate TGA, a first latch 41, and a first inverter INV1. The transfer gate TGA transfers the output enable signal OE0 to the first latch 41. The first latch 41 latches an output signal of the transfer gate TGA and is reset by the reset signal OE_RESTB. The first inverter INV1 drives an output signal of the first latch 41 to output the output enable signal OE1. The transfer gate TGA is enabled during a period in which the output signal TN_RCLK_DLL of the delay option unit 31 has a logic high level.
Referring to FIG. 4B, the OE1.5 generating unit 34 includes a transfer gate TGB, a second latch 42, and a second inverter INV2. The transfer gate TGB transfers the output enable signal OE1 to the second latch 42. The second latch 42 latches an output signal of the transfer gate TGB and is reset by the reset signal OE_RESTB. The second inverter INV2 drives an output signal of the second latch 42 to output the output enable signal OE1.5. The transfer gate TGB is enabled during a period in which the output signal TN_RCLK_DLL of the delay option unit 31 has a logic low level.
The OE2 generating unit (not shown), . . . , the OEN generating unit 35 have the same configuration as the OE1 generating unit 33 of FIG. 4A, except that the output enable signal generated from the previous stage is inputted to the next stage. An OE2.5 generating unit (not shown), an OE3.5 generating unit (not shown), etc. have the same configuration as the OE1.5 generating unit 34 of FIG. 4B, except that the output enable signal generated from the previous stage is inputted to the next stage.
FIGS. 5 and 6 are timing diagrams illustrating the tuning operation of the delay option unit 31 during the domain crossing.
In FIGS. 5 and 6, it is assumed that it takes 15 ns to output the internal data to the external circuit after the input of the read command in the same semiconductor memory device. In FIG. 5, the period tCK of the external clock signal CLK_EXT is 2.5 ns, the CAS latency CL is 6, the delay time of the delay replica model 25 is 2 ns, and the delay time locked after the locking at the second delay line 22 is 0.5 ns. In FIG. 6, the period tCK of the external clock signal CLK_EXT is 5 ns, the CAS latency CL is 3, the delay time of the delay replica model 25 is 2 ns, and the delay time locked after the locking at the second delay line 22 is 3 ns.
Referring to FIG. 5, the internal read command signal IRDP is generated after a predetermined time from the input of the read command RD. The OE0 generating unit 32 of FIG. 3 receives the internal read command signal IRDP to generate the output enable signal OE0. The pulse width of the output enable signal OE0 is determined by the burst length BL. The output enable signal OE1 is generated in synchronization with a time point 1 of the rising DLL clock signal RCLK_DLL, and the output enable signal OE2 is generated in synchronization with a time point 2 of the rising DLL clock signal RCLK_DLL. The output enable signal OE3 is generated in synchronization with a time point 3 of the rising DLL clock signal CLK_DLL, and the output enable signal OE4 is generated in synchronization with a time point 4 of the rising DLL clock signal RCLK_DLL. The output enable signal OE4.5 is generated in synchronization with a time point 4.5 of the rising DLL clock signal RCLK_DLL.
Meanwhile, the reference clock signal CLK_REF is the buffered external clock signal and is substantially equal to the external clock signal CLK_EXT. The rising DLL clock signal RCLK_DLL is produced by delaying the reference clock signal by "D1" at the second delay line 22 of FIG. 2. In other words, a time point 5 of the rising DLL clock signal RCLK_DLL corresponds to a time point delayed by "D2" at the delay replica model 25 of FIG. 2, that is, a time point 5 of the reference clock signal CLK_REF. In addition, since the reference clock signal CLK_REF is substantially equal to the external clock signal CLK_EXT, the time point 5 of the reference clock signal CLK_REF is substantially equal to the time point 5 of the external clock signal EXT_CLK. When the CAS latency CL is 6, data D0 exactly synchronizes with the time point 5 of the external clock signal CLK_EXT, that is, a sixth external clock signal CLK_EXT after the input of the read command RD. Subsequently output data D1, D2 and D3 exactly synchronize with the external clock signal CLK_EXT.
In FIG. 6, the period tCK of the external clock signal CLK_EXT is 5 ns, the CAS latency CL is 3, the delay time "D2" of the delay replica model 25 is 2 ns, and the second delay line 22 of FIG. 2 has the delay time of "D3" so as to output data in 15 ns. That is, a time point 2 of the rising DLL clock signal RCLK_DLL corresponds to a time point 2 of the reference clock signal CLK_REF, and it is substantially equal to a time point 2 of the external clock signal CLK_EXT. When the CAS latency CL is 3, data D0 exactly synchronizes with the time point 2 of the external clock signal CLK_EXT, that is, a third external clock signal CLK_EXT after the input of the read command RD. Subsequently outputted data D1, D2 and D3 exactly synchronize with the external clock signal CLK_EXT.
Meanwhile, the internal read command signal IRDP is generated after a predetermined time elapses from the input of the read command RD. The OE0 generating unit 32 of FIG. 3 receives the internal read command signal IRDP to generate the output enable signal OE0. The output enable signal OE1 is generated in synchronization with the time point 0 of the rising DLL clock signal RCLK_DLL in FIG. 6, while the output enable signal OE1 is generated in synchronization with the time point 1 of the rising DLL clock signal RCLK_DLL in FIG. 5. The output enable signals generated after the output enable signal OE1 also synchronize with the rising DLL clock signal RCLK_DLL at the time points different from those of FIG. 5.
Therefore, the tuning for the domain crossing must be performed using the delay option unit 31. For example, the output enable signal OE1 must be generated such that it always synchronizes with the time point 1 of the rising DLL clock signal RCLK_DLL. That is, the output enable signal OE1 synchronizes with the time point 1 of the rising DLL clock signal RCLK_DLL by further delaying it by "D4" through the domain crossing. Therefore, the output enable signal OE2 is also synchronized with the time point 2 of the rising DLL clock signal RCLK_DLL.
The delay option unit 31 for the tuning must be configured using a plurality of delay elements and a plurality of option circuits. In addition, as the period tCK of the external clock signal CLK_EXT decreases, a more precise control is needed. Consequently, a larger number of delay elements and option circuits are required.

Semiconductor memory device including delay locked loop and method for driving the same


A method, system, and computer program product for implementing virtual keyboard video mouse (KVM) switching functionality using a processing device in communication with a memory device is provided. Keyboard, video, and mouse signals for a first computer are redirected to be carried over a standardized serial bus connecting the first computer to a second computer. Each of the keyboard, video, and mouse signals are carried at predetermined frequencies. The keyboard, video, and mouse signals on the second computer are identified and separated. The keyboard, video, and mouse signals are passed to an operating system on the second computer. The keyboard, video, and mouse signals are used by the operating system to manage the first computer.

1. Field of the Invention
The present invention relates in general to computers, and more particularly to apparatus, method and computer program product embodiments for implementing virtual keyboard video mouse (KVM) functionality for a target computer system using a portable computer.
2. Description of the Related Art
Computers and computer systems are found in a variety of settings in today's society. Computing environments and networks may be found at home, at work, at school, in government, and in other settings. Computing environments increasingly manage data in one or more datacenter environments apart from the interface that computer users typically associate. In many cases, the storage environments are located across wide area networks (WANs), in which data is sent to/received from the data system located remotely from the host. Datacenters are facilities used to house computer systems and associated components, such as telecommunications and storage subsystems. They generally include redundant or backup power supplies, redundant data communications connections, environmental controls, and security devices.
A datacenter may occupy one room of a building, one or more floors, or an entire building. Most of the equipment is often in the form of servers mounted in 19-inch rack cabinets, which are usually placed in single rows forming corridors between them. This allows personnel to access to the front and rear of each cabinet. In a typical data center environment, each of the rack mount servers shares a connection to a keyboard video mouse (KVM) switch. The user toggles the switch in order to connect to a desired server.
Use of traditional KVM switches presents occasional challenges, however. For example, if more than one person needs to use the console to which the KVM switch is connected, however, the first user must finish his/her task first. Only then may the second user toggle the switch and connect to a second server or system. In addition to the foregoing, each system must be connected via a dongle and cable form factor, and daisy-chained and connected to the shared KVM switch. This situation leads to disorganization among the server cables at the back of the rack. One false connection may lead to losing a connection to the other servers daisy-chained to that particular connector. Finally, the user must implement a separate KVM switch (including an attached keyboard, video, and mouse) for each rack in the datacenter environment.
Alternatives to conventional KVM functionality may reduce these issues, such as use of a virtual network computing (VNC) protocol for remote connection to a particular server. However, VNC also poses challenges on occasion. For example, if a particular server is booting into an operating system, it is impossible to remotely connect to the server using VNC in order for a user to determine what is happening in that server during the boot cycle. In those situations, only a physically connected keyboard, video display, and mouse allow the user visibility into the server and the ability to take an appropriate action.

Virtual KVM functionality for computer systems

International Business Machines Corporation


A gait trainer attachment adapted for use with exercise equipment and a method for using the gait trainer attachment. Embodiments of the gait trainer attachment include a frame, a leg brace, and a compromised limb gait system. The compromised limb gait system attaches the leg brace to the frame and is configured to guide a limb of a user through a simulated gait motion. In aspects, the gait trainer attachment gives an amputee user the ability to use ordinary exercise equipment for rehabilitation and endurance training by providing a leg brace for the compromised limb, a frame designed to attach to exercise equipment, and a connection between the leg brace and frame that guides the compromised limb, thus allowing the user to maintain a biomechanically proper walking motion while exercising.

Physical therapy and rehabilitation are long and difficult processes for patients with compromised limbs or unilateral immobility. Following surgery, amputation patients frequently do not receive adequate healthcare resources to meet their rehabilitation needs. Patients who have had a portion of one of their legs amputated wait, at a minimum, six to eight weeks for a prosthetic limb to be fabricated, and often the time required for the limb to heal and the prosthetic to be fabricated is much longer than that. During this waiting period, the vast majority of patients rely exclusively on wheelchairs for mobility and have limited options for rehabilitative exercise. Similarly, patients with full or partial paralysis of a lower limb, or other conditions that result in a compromised lower limb, may be confined to a wheelchair during recovery and experience only limited rehabilitation or exercise. For weeks, patients are substantially wheelchair-bound and limited to physical therapy sessions for rehabilitation.
This limited mobility of the lower limbs can lead to irreversible physiological breakdowns with severe consequences, such as muscle atrophy, joint contractures, phantom limb syndrome, and acceleration of peripheral artery disease. Additionally, in cases where amputation was required because of a patient's vascular disease, the immobility can accelerate the vascular disease in the remaining, non-amputated limb leading to additional medical treatment. Even where a patient might initially have adequate rehabilitation resources, it is all too common for patients that experience an illness or injury, such as a stroke or amputation, to undergo inpatient rehabilitation for a brief period. Upon returning to their own home, those patients experience a rapid decline because they do not have assistive technology for locomotor training.
Generally, before a prosthetic device can be fabricated, amputation patients are confined to the time and location of their physical therapy sessions for rehabilitation and exercise. Similarly, patients with monoplegia or stroke victims often struggle with limited opportunities for rehabilitation or exercise. While conventional gait training devices assist in guiding the compromised limb of a user through a simulated gait motion, they are not particularly well-suited for use outside of physical therapy sessions or for endurance training because they are cumbersome, prohibitively expensive, and incompatible with common exercise equipment. As a result, amputee or monoplegic patients may find it difficult or impossible to use traditional gait training devices outside of physical therapy sessions or for extended duration endurance training.


A method, apparatus and computer readable storage medium are provided for determining the installation positions of radio devices. Signal propagation time parameters are obtained with each signal propagation time parameter associated with an installation position and an observation position. Each signal propagation time parameter represents a respective signal propagation time value of radio signal(s) traveling between the respective installation and observation positions. A signal propagation time parameter is selected for defining a coordinate system. First point coordinates are selected to represent the installation position associated with the selected signal propagation time parameter, and second point coordinates are selected to represent the observation position associated with the selected signal propagation time parameter. For each installation position represented by the first point coordinates, respective point coordinates are determined that represent the respective installation position at least partially based on the signal propagation time parameter and the first and second point coordinates.

Satellite signal based positioning technologies, which are mainly used outdoors, are usually not suited to deliver a satisfactory performance when used for indoor positioning, since satellite signals of global navigation satellite systems (GNSS), like the global positioning system (GPS) or the Galileo system, do not penetrate through walls and roofs strongly enough for an adequate signal reception indoors. Thus, these positioning technologies are not able to deliver a performance indoors that would enable seamless, equal and accurate navigation experience outdoors and indoors.
Therefore, several dedicated non-GNSS based radio positioning systems for indoor and outdoor positioning have been developed and commercially deployed during the past years. Examples comprise systems that are based on pseudolites, which are ground based GPS-like short-range beacons, ultra-sound positioning systems, Bluetooth low energy (BLE) based positioning systems, cellular network based positioning systems and wireless local area network (WLAN) based positioning systems.
To enable positioning based on such non-GNSS based radio positioning systems, it is however necessary to determine the installation positions of the radio devices of positioning system. Currently, the installation positions of such radio devices are mostly manually captured which is a burdensome, time consuming and expensive procedure.

Determining a plurality of installation positions of a plurality of radio devices


A method for filling a trench within a substrate. There is first provided a substrate having a trench formed within the substrate. There is then formed over the substrate and within the trench a silicon layer. The silicon layer has an aperture formed therein where the silicon layer is formed within the trench. There is then formed upon the silicon layer and filling the aperture a gap filling silicon oxide trench fill layer. The gap filling silicon oxide trench fill layer is formed through an ozone assisted sub-atmospheric pressure chemical vapor deposition (SACVD) method. Finally, the substrate is annealed thermally in an oxygen containing atmosphere to form within the trench an oxidized silicon layer from the silicon layer, where the oxidized silicon layer is contiguous with a densified gap filling silicon oxide trench fill layer simultaneously formed from the gap filling silicon oxide trench fill layer. Through the method, the densified gap filling silicon oxide trench fill layer is formed without a surface sensitivity.

1. Field of the Invention
The present invention relates generally to methods for forming trench fill layers within trenches within substrates employed in integrated circuit fabrication. More particularly, the present invention relates to methods for forming gap filling ozone assisted chemical vapor deposited (CVD) silicon oxide trench fill layers within trenches within substrates employed in integrated circuit fabrication.
2. Description of the Related Art
Integrated circuits are formed from semiconductor substrates within and upon whose surfaces are formed resistors, transistors, diodes and other electrical circuit elements. The electrical circuit elements are connected internally and externally to the semiconductor substrate upon which they are formed through patterned conductor layers which are separated by dielectric layers.
As integrated circuit technology has advanced and integrated circuit device dimensions have decreased, it has become increasingly common within advanced integrated circuits to employ trench isolation methods such as shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods to form trench isolation regions nominally co-planar with adjoining active semiconductor regions of semiconductor substrates. Such trench isolation methods typically employ a chemical mechanical polish (CMP) planarizing method to provide a nominally planarized surface to a trench isolation region formed from a trench fill dielectric layer formed within the trench. Trench isolation regions nominally co-planar with active semiconductor regions within semiconductor substrates are desirable since they optimize, when subsequently forming patterned layers upon those nominally co-planar trench isolation regions and active semiconductor regions, the limited depth of focus typically achievable with advanced photoexposure tooling.
When forming within advanced integrated circuits trench isolation regions within isolation trenches, it has become common to employ as trench fill dielectric layers gap filling silicon oxide layers formed through ozone assisted sub-atmospheric pressure chemical vapor deposition (SACVD) methods and ozone assisted atmospheric pressure chemical vapor deposition (APCVD) methods. Silicon oxide layers formed through such methods are desirable since such silicon oxide layers possess inherently superior gap filling characteristics desirable for trenches of limited dimensions typically encountered in advanced integrated circuit fabrication.
While gap filling silicon oxide layers formed through ozone assisted sub-atmospheric pressure chemical vapor deposition (SACVD) methods and ozone assisted atmospheric pressure chemical vapor deposition (APCVD) methods are thus desirable as trench fill layers within trenches within advanced integrated circuit fabrication, methods through which are formed such gap filling silicon oxide layers are not entirely without problems. In particular, it is known in the art that gap filling silicon oxide layers formed through ozone assisted sub-atmospheric pressure chemical vapor deposition (SACVD) methods exhibit a surface sensitivity dependent upon the substrate layers upon which are formed those gap filling silicon oxide layers. In particular, when employing as substrate layers thermally grown silicon oxide layers which are typically employed as isolation trench liner layers within isolation trenches formed within semiconductor substrates, gap filling silicon oxide layers formed through ozone assisted sub-atmospheric pressure chemical vapor deposition (SACVD) methods exhibit inhibited formation rates. Inhibited formation rates within isolation trenches within semiconductor substrates of gap filling silicon oxide trench fill layers formed through ozone assisted sub-atmospheric pressure chemical vapor deposition (SACVD) methods are undesirable since there is then formed within those isolation trenches gap filling silicon oxide trench fill layers which are particularly susceptible to dishing when subsequently planarized through chemical mechanical polish (CMP) planarizing methods.
It is thus towards the goal of forming within advanced integrated circuits gap filling silicon oxide trench fill layers formed through ozone assisted sub-atmospheric pressure chemical vapor deposition (SACVD) methods, while avoiding a surface sensitivity, that the present invention is generally directed.
Methods and materials through which isolation regions may be formed within isolation trenches for use within integrated circuits are known in the art of integrated circuit fabrication. For example, Nasr et al., in U.S. Pat. No. 5,346,584 disclose a planarization method employing an oxidized patterned polysilicon filler layer as a trench fill layer when forming an isolation region within an isolation trench within a semiconductor substrate. The oxidized patterned polysilicon filler layer provides a relatively planar semiconductor substrate surface which is readily planarized through a chemical mechanical polish (CMP) planarizing method. In addition, Figura et al., in U.S. Pat. No. 5,472,904 disclose a method for simultaneously forming a narrow trench isolation region and a recessed oxide isolation (ROI) region within a semiconductor substrate. The method employs an oxidation barrier formed within a narrow trench within which is formed the narrow trench isolation region, but not within a wide trench within which is formed the recessed oxide isolation region. Finally, Bose et al., in U.S. Pat. No. 5,492,858 disclose a method for forming a planarized trench fill dielectric layer within an isolation trench within an integrated circuit. The method employs within the isolation trench a barrier layer which allows for densifying, through steam annealing, a conformal silicon oxide trench fill dielectric layer which may then subsequently be planarized, while avoiding dishing, through a chemical mechanical polish (CMP) planarizing method.
Desirable in the art are additional methods through which trenches within substrates employed within integrated circuit fabrication may be filled with gap filling silicon oxide trench fill layers formed through ozone assisted sub-atmospheric pressure chemical vapor deposition (SACVD) methods, while avoiding a surface sensitivity. Particularly desirable are additional methods through which isolation trenches within semiconductor substrates employed within integrated circuit fabrication may be filled with gap filling silicon oxide trench fill dielectric layers formed through ozone assisted sub-atmospheric chemical vapor deposition (SACVD) methods, while avoiding a surface sensitivity. It is towards these goals that the present invention is more specifically directed.

Trench filling method employing silicon liner layer and gap filling silicon oxide trench fill layer

Taiwan Semiconductor Manufacturing Company, Ltd.


An anisotropically conductive connector device including a first anisotropically conductive sheet and a second anisotropically conductive sheet. A plurality of conductive path-forming parts each extending in a thickness-wise direction of each sheet are arranged in a state mutually insulated d by an insulating part. The conductive path-forming parts in the second anisotropically conductive sheet each have a diameter smaller than a diameter of each of the conductive path-forming parts in the first anisotropically conductive sheet.

An anisotropically conductive sheet is a sheet exhibiting conductivity only in its thickness-wise direction or having pressure-sensitive conductive conductor parts exhibiting conductivity only in the thickness-wise direction when they are pressed in the thickness-wise direction. As such anisotropically conductive sheets, there have been known those of various structures, such as those obtained by uniformly dispersing metal particles in an elastomer (see, for example, Patent Art. 1), those obtained by unevenly dispersing a conductive magnetic metal in an elastomer, thereby forming a great number of conductive path-forming parts each extending in a thickness-wise direction thereof and an insulating part for mutually insulating them (see, for example, Patent Art. 2) and those obtained by defining a difference in level between the surface of each conductive path-forming part and an insulating part (see, for example, Patent Art. 3).
In these anisotropically conductive sheets, conductive particles are contained in an insulating elastic polymeric substance in a state oriented so as to align in the thickness-wise direction, and each conductive path is formed by a chain of a great number of conductive particles.
Since such an anisotropically conductive sheet has such features that compact electrical connection can be achieved without using any means such as soldering or mechanical fitting, and that soft connection becomes feasible with mechanical shock or strain absorbed therein, it is widely used as an anisotropically conductive connector for achieving electrical connection between circuit devices, for example, electrical connection between a printed circuit board and a leadless chip carrier, liquid crystal panel or the like, in fields of, for example, electronic computers, electronic digital clocks, electronic cameras and computer key boards.
Further, as a means for achieving electrical connection between electrodes to be inspected of a circuit device, which is an object of inspection, and electrodes for inspection formed on the front surface of a circuit board for inspection in electrical inspection of circuit devices such as printed circuit boards and semiconductor integrated circuits, an anisotropically conductive sheet is used in place of a probe member, in which a plurality of pin probes are arranged corresponding to the electrode to be inspected.
That, in which either the probe member or the anisotropically conductive sheet may be used, is known as an inspection apparatus for circuit devices. A circuit board for inspection in this inspection apparatus has inspection electrodes each having a special form. An examples thereof is illustrated in FIG. 13. The inspection electrodes 6 in this circuit board 5 for inspection each have a cocoon-shaped form and are arranged in accordance with a pattern corresponding to a pattern of the electrodes to be inspected in a state inclined at an angle of, for example, 45°.
However, the inspection apparatus having the circuit board for inspection, in which the inspection electrodes of such a special form have been formed has been proved to involve the following problems when electrical inspection of a circuit device having projected electrodes, such as BGA, is conducted by using the anisotropically conductive sheet.
As the anisotropically conductive sheet in the inspection apparatus of the circuit board, is used that having conductive path-forming parts each having a diameter equivalent to the diameter of an electrode to be inspected in that high conductivity is achieved. However, in the circuit board 5 for inspection illustrated in FIG. 13, a pitch of the inspection electrodes 6, i.e., a center distance between inspection electrodes 6 adjoining each other, is substantially equal to a pitch of the electrodes to be inspected, but a clearance between inspection electrodes 6 adjoining each other is considerably smaller than a clearance between the electrodes to be inspected. Therefore, it is extremely difficult to arrange the anisotropically conductive sheet on the circuit board 5 for inspection in such a manner that each of the conductive path-forming parts thereof is located on an inspection electrode 6 to be connected and come into no contact with inspection electrodes 6 adjoining the inspection electrode.
In addition, when an anisotropically conductive sheet having conductive path-forming parts small in diameter is used, it is necessary to make the thickness of the conductive path-forming parts of the anisotropically conductive sheet small for the purpose of achieving necessary conductivity. However, the anisotropically conductive sheet having the conductive path-forming parts small in the thickness thereof is low in irregularity-absorbing property, so that it is difficult to surely achieve electrical connection to electrodes to be inspected when a circuit board, which is an object of inspection, has projected electrodes great in a scatter of projected height.    Patent Art. 1: Japanese Patent Application Laid-Open No. 93393/1976;    Patent Art. 2: Japanese Patent Application Laid-Open No. 147772/1978;    Patent Art. 3: Japanese Patent Application Laid-Open No. 250906/1986.

Anisotropic conductive connector and inspection equipment for circuit device


A system and method for server load balancing that includes server affinity. The system can be incorporated into application servers to support load balancing algorithms for RMI objects that provide server affinity. Server affinity uses smart load balancing for external client connections in such a way that it uses preexisting connection and reduces overhead: the client considers its existing connections to the application server instances when choosing the server instance on which to access a service. If a service is configured for server affinity, the client-side stub attempts to choose a server instance to which it is already connected, and continues to use the same server instance for method calls. All stubs on that client will attempt to use that server instance. If the server instance becomes unavailable, the stubs fail over, if possible, to a server instance to which the client is already connected.

In the field of application servers and distributed systems, clusters of servers are often used to provide highly available and scalable resources. One example of an application server is the WebLogic Server from BEA Systems, Inc. A cluster (such as a WebLogic Server cluster) comprises multiple server instances running simultaneously and working together to provide increased scalability and reliability. A cluster appears to clients to be a single server. The server instances that constitute a cluster can run on the same machine, or be located on different machines. A cluster's capacity can be increased by adding additional server instances to the cluster on an existing machine, or by adding machines to the cluster to host the incremental server instances. Each server instance in a cluster must typically run the same version of the server product.
In terms of how a cluster relates to the environment in which the application server exists, a cluster is usually part of a particular server (e.g. WebLogic Server) domain. A domain is an interrelated set of resources that are managed as a unit. A domain includes one or more server instances, which can be clustered, non-clustered, or a combination of clustered and non-clustered instances. A domain can include multiple clusters. A domain also contains the application components deployed in the domain, and the resources and services required by those application components and the server instances in the domain. Examples of the resources and services used by applications and server instances include machine definitions, optional network channels, Java 2 Enterprise Edition (J2EE) components, Enterprise Java Bean (EJB), connectors, and startup classes. An administrator can use a variety of criteria for organizing server instances into domains. For instance, they might choose to allocate resources to multiple domains based on logical divisions of the hosted application, geographical considerations, or the number or complexity of the resources under management.
In a WebLogic domain, one WebLogic Server instance typically acts as the Administration Server—the server instance which configures, manages, and monitors all other server instances and resources in the domain. Each Administration Server manages one domain only. If a domain contains multiple clusters, each cluster in the domain has the same Administration Server. All server instances in a cluster must reside in the same domain; i.e. you cannot "split" a cluster over multiple domains. Similarly, you cannot share a configured resource or subsystem between domains. For example, if you create a Java Database Connectivity (JDBC) connection pool in one domain, you cannot use it with a server instance or cluster in another domain. (Instead, you must create a similar connection pool in the second domain.).
Clustered server instances behave similarly to non-clustered instances, except that they provide failover and load balancing. The process and tools used to configure clustered server instances are the same as those used to configure non-clustered instances. A server cluster provides the following benefits and features:
Scalability—The capacity of an application deployed on a cluster can be increased dynamically to meet demand. Server instances can be added to a cluster without interruption of service—the application continues to run without impact to clients and end users.
High-Availability—In a cluster, application processing can continue when a server instance fails. Application components are "clustered" by deploying them on multiple server instances in the cluster-so, if a server instance on which a component is running fails, another server instance on which that component is deployed can continue application processing.
Failover—Failover means that when an application component (typically referred to as a "service" in the following sections) doing a particular "job"—some set of processing tasks-becomes unavailable for any reason, a copy of the failed service finishes the job. For the new service to be able to take over for the failed service there must be a copy of the failed service available to take over the job. There must also be information, available to other services and the program that manages failover, defining the location and operational status of all services-so that it can be determined that the first service failed before finishing its job. There must also be information, available to other services and the program that manages failover, about the progress of jobs in process—so that a service taking over an interrupted job knows how much of the job was completed before the first service failed, for example, what data has been changed, and what steps in the process were completed. Many application servers, including WebLogic Server, use standards-based communication techniques and facilities-multicast, IP sockets, and the Java Naming and Directory Interface (JNDI)—to share and maintain information about the availability of services in a cluster. These techniques allow the server to determine that a service stopped before finishing its job, and where there is a copy of the service to complete the job that was interrupted. Information about what has been done on a job is called state. WebLogic Server maintains information about state using techniques called session replication and replica-aware stubs. When a particular service unexpectedly stops doing its job, replication techniques enable a copy of the service to pick up where the failed service stopped, and finish the job.
Load Balancing—Load balancing is the even distribution of jobs and associated communications across the computing and networking resources in the application server environment. For load balancing to occur there must be multiple copies of a service that can do a particular job. Information about the location and operational status of all services must also be available. In addition, WebLogic Server allows services to be clustered—deployed on multiple server instances—so that there are alternative services to do the same job. WebLogic Server shares and maintains the availability and location of deployed services using multicast, IP sockets, and JNDI.
A clustered application or application component is one that is available on multiple server instances in a cluster. If a service is clustered, failover and load balancing for that service is available. Web applications can consist of different types of services, including Enterprise Java Beans (EJBs), servlets, and Java Server Pages (JSPs). Each service type has a unique set of behaviors related to control, invocation, and how it functions within an application. For this reason, the methods that WebLogic Server uses to support clustering—and hence to provide load balancing and failover—can vary for different types of services. The following types of services can be clustered in a WebLogic Server deployment: Servlets; JSPs; EJBs; Remote Method Invocation (RMI) objects; Java Messaging Service (JMS) destinations; and, Java Database Connectivity (JDBC) connections.
Different service types can have certain behaviors in common. When this is the case, the clustering support and implementation considerations for those similar service types may be same. In the sections that follow, explanations and instructions for the following types of services are generally combined: Servlets and JavaServer Pages (JSP); and EJBs and RMI objects. The sections that follow briefly describe the clustering, failover, and load balancing support that WebLogic Server provides for different types of services.
Servlets and JSPs
WebLogic Server provides clustering support for servlets and JSPs by replicating the Hypertext Transfer Protocol (HTTP) session state of clients that access clustered servlets and JSPs. WebLogic Server can maintain HTTP session states in memory, a filesystem, or a database.
EJBs and RMI Objects
Load balancing and failover for EJBs and RMI objects is handled using replica-aware stubs, which can locate instances of the service throughout the cluster. Replica-aware stubs are created for EJBs and RMI objects as a result of the service compilation process. EJBs and RMI objects are deployed homogeneously—to all the server instances in the cluster. Failover for EJBs and RMI objects is accomplished using the service's replica-aware stub. When a client makes a call through a replica-aware stub to a service that fails, the stub detects the failure and retries the call on another replica.
JDBC Connections
WebLogic Server allows you to cluster JDBC services, including data sources, connection pools and multipools, to improve the availability of cluster-hosted applications. Each JDBC service you configure for your cluster must exist on each managed server in the cluster.
JMS
The WebLogic Java Messaging Service (JMS) architecture implements clustering of multiple JMS servers by supporting cluster-wide, transparent access to destinations from any WebLogic Server server instance in the cluster. Although WebLogic Server supports distributing JMS destinations and connection factories throughout a cluster, the same JMS topic or queue is still managed separately by each WebLogic Server instance in the cluster.
However, even given the successes of clustering in the application server environment, a typical problem with today's clustered systems is that they do not suitably address the number of external client connections they handle. Method calls are typically load balanced among the available server instances according to the configured load balancing algorithm. As a result a large number of sockets must be opened and maintained between the external clients and server instances in the cluster. A new approach that disables traditional load balancing for external client connections, but still allows it for less costly server-to-server connections would be of great use in enhancing cluster stability and scalability.

System and method for server load balancing and server affinity


An end of a stacked-structure of conductive and insulating layers above a substrate has a staircase structure. The staircase includes a step pair. The risers of steps are opposed to each other. The step pairs are provided at different levels in the form in the staircase. First contact-plugs are provided on treads of respective steps of the first step part. A second contact-plug is provided in either an intermediate region between the first and the second steps of the step pair or the second step to extend in the stacked structure in a direction in which the conductive and insulating layers are stacked. A CMOS circuit is provided below the stacked structure and is connected to the second contact-plug. The second contact-plug is provided in either the intermediate region on which the first contact-plug is not formed or the second step on which the first contact-plug is not formed.

Semiconductor memories including a three-dimensional memory cell array, in which memory cells are arranged three-dimensionally, have been developed. Word lines of a semiconductor memory each have a stacked structure stacked on a substrate. In order to connect a contact plug to each of the word lines having this stacked structure, a staircase structure (a terrace structure) is formed at an end of the stacked structure. This staircase structure is formed at an end of the stacked structure of each word line by, after a lithography process, repeating an etching process for the word line and a slimming process for a resist film multiple times.
However, repeating the etching process and the sliming process increases variation in the thickness of the resist film, so that a dimensional accuracy of the staircase structure is deteriorated. In order to handle this problem of dimensional variation of the staircase structure, it is necessary to make the length or width of a tread of the staircase structure large. In this case, there is a problem that a layout area of a semiconductor memory is increased. Further, because the sliming process is performed multiple times, a technique is required in which the thickness of the resist film can be made thick and the resist film can be applied with high viscosity. This causes increase of the manufacturing cost of a semiconductor memory.

Semiconductor device and manufacturing method thereof