A system of modular electrohydraulic servovalves is centrally controlled may be used to control the operation of critical hydraulic actuators. A programmable controller operates a group of modular servovalves which each deliver a portion of the total actuator fluid requirements. The flow rate, valve position, and valve pressure of each servovalve is monitored by the controller and compared to expected values in memory to determine whether a servovalve malfunction exists. If so, the controller maintains the required flow rate to the actuator by closing the malfunctioning valve and either activating a spare or proportionally increasing the flow rates of the remaining servovalves to compensate for the loss.

The present invention relates to a high reliability, low-noise, pressurized fluid control system and, more particularly, to a system of one or more modular servo valves operated individually or in groups by a central controller to supply any desired fluid pressure to a hydraulic actuator aboard a submarine or other marine vessel.
Submarines and other ocean going vessels currently utilize a centralized hydraulic power plant which supplies fluid power to a plurality of actuators located throughout the ship. Each actuator performs a specific function, and the power requirements of each varies widely with the application. For example, ram movements in a typical sea water valve actuator may require less than 10 gal/min, while those in an actuator connected to a control surface such as a diving plane or rudder may require over 100 gal/min.
To ensure that a critical component remains operable despite extensive equipment damage or failure, shipboard hydraulic systems generally incorporate some level of redundancy. For example, flood control systems, installed where seawater pipes enter or leave a submarine's power pressure hull, typically employ redundant hydraulic circuits each consisting of a fluid reservoir, pump, and supply/return lines for supplying fluid to an actuator. The redundancy minimizes the effect of component failure in any one circuit so that the actuator is supplied with fluid at all times.
Control surface hydraulic systems, being similarly critical to ship safety, must be very reliable and therefore must presently be designed to include a significant level of redundancy. Typically, control surface rams receive fluid power from two sources via independent valves, in effect, from a normal servo valve (SV) and an emergency control valve (ECV). The SV and ECV are each constructed with the capacity to independently supply all of the pressurized fluid required, at the desired flow rate, to the actuator. Thus, if the SV or other component of the normal fluid supply system fails, a power transfer valve (PTV) in fluid communication with the SV and ECV continues to supply fluid power to the control surface ram by shifting from a normal mode to an emergency mode. In shifting to the emergency mode, the PTV shuts a valve connecting it to the SV and opens a valve to the ECV, thereby maintaining the flow of needed fluid to the actuator.
The benefits of maintaining redundant "back-up" systems, however, is not without cost. In submarine systems, the expense of providing and maintaining duplicate systems for the control surface actuators is particularly large because they must meet large power requirements yet operate at very low noise levels.

The United States of America as represented by the Secretary of the Navy


A terahertz gas spectrometer detection system is provided. The system includes: a terahertz generation module, a gas module, a terahertz detection module and a program-control and acquisition module. terahertz generation module is configured for generating and transmitting terahertz signals with different frequencies; gas module is configured for setting and storing to-be-detected gas, so that terahertz signals with different frequencies pass through the to-be-detected gas; terahertz detection module is configured for detecting amplitude signals of terahertz signals after passing through the to-be-detected gas through field effect transistor detector; program-control and acquisition module is configured for controlling the terahertz generation module to generate and transmit frequency of terahertz signal, and is further configured for acquiring amplitude detection signals of terahertz signals after passing through the to-be-detected gas, and generating spectrogram of to-be-detected gas.

Terahertz wave (THz wave) has a wavelength between infrared and microwave range. Since the levels of vibration absorption of many molecules are located in the range between the far-infrared to terahertz, which are produced by molecules interactions, vibration transitions, dipole rotation and low-frequency vibration of crystal lattice, the fingerprint spectra of these substances can be accurately obtained by terahertz spectroscopy. Therefore, the terahertz spectroscopy can be taken as an effective way to research the structural characteristics of unknown materials of some fields, like in the field of chemistry or material science; moreover, the terahertz spectroscopy may also have its applicative prospect as another effective way to identify the known molecules (such as poisons, drugs and explosives, or the like).
In the prior art, the terahertz spectroscopy detection system has the disadvantage of low sensitivity in a high frequency band. Therefore, the present disclosure provides a terahertz gas spectrometer detection system which is capable of overcoming the above technical problems.

Terahertz gas spectrometer detection system


An over-driven access method and device for ferroelectric memory. When accessing the data stored in a ferroelectric memory, the invention further provides an over-driven current to slightly reduce/raise the voltages in bit lines BL and BL′ to further enlarge the voltage difference therebetween after having raised the plate-line/bit-line voltage using the plate-line/bit-line driven method.

1. Field of the Invention
The invention relates in general to a memory access method and device, and more particularly to an over-driven access method and device for ferroelectric memory.
2. Description of the Related Art
Ferroelectric memory uses ferroelectric capacitor as the storage medium. Ferroelectric capacitor can be polarized to different polarized states, and thus can represent the stored data by means of polarized states. Please refer to FIG. 1, a transitional diagram illustrating the transition of the polarized state of ferroelectric capacitor. The transition of the polarized state of ferroelectric capacitor is hysteresis which means that a greater-than-zero voltage must be applied in order to convert the polarization of a ferroelectric capacitor from a negative state into a positive state and that a smaller-than-zero voltage must be applied in order to convert the polarization of a ferroelectric capacitor from a positive state into a negative state. Seeing that the polarized state of ferroelectric capacitor still can be sustained even in the absence of power supply, the ferroelectric capacitor does have the potential to replace the flash memory which is in current use now. Moreover, the polarized state of ferroelectric capacitor can be changed when the voltage applied onto the ferroelectric capacitor changes, thus has the potential to replace the dynamic random access memory (DRAM) as well.
Apart from having the characteristic of hysteresis, the ferroelectric capacitor has another characteristic, i.e., its capacitance is changeable. The formula for capacitance C is: C=ΔQ/ΔV, wherein Q is the quantity of electric charges; Q is the voltage drop of capacitor. The polarization of ferroelectric capacitor P is proportional to the quantity of electric charges Q, therefore capacitance C is proportional to the slope of the transition curve for polarization in FIG. 1. The larger the slope is, the greater the capacitance will be. It can be inferred from FIG. 1 that the capacitance during polarity transition is larger than that in a stabilized state.
Please refer to FIG. 2A, a schematic diagram illustrating a memory unit of a ferroelectric memory. This memory unit which is in the form of 1T1C consists of one transistor, T, and one ferroelectric capacitor, Cf, with one end of ferroelectric capacitor Cf being coupled to plate line PL. When word line WL is enabled, the voltage drop in ferroelectric capacitor Cf is exactly the voltage difference between plate line PL and bit line BL. Please refer to FIG. 2B, a schematic diagram illustrating another memory unit of a ferroelectric memory. This memory unit which is in the form of 2T2C consists of two transistor, T and T′, and two ferroelectric capacitors, Cf and Cf′. Every memory unit further comprises a sense amplifier SA which is used to amplify the voltage difference between bit line BL and bit line BL′ to facilitate the access to the data stored at the ferroelectric memory. Sense amplifier SA as illustrated in FIG. 2B is a latch sense amplifier further comprising two phase inverters which raises the voltage in the high-voltage bit line to be even higher and reduces the voltage in the low-voltage bit line to be even lower. Sense amplifier SA is initiated when sense amplifier enabling signal SAE is received.
General speaking, there are two methods for the access of ferroelectric memory: the plate-line driven method and the bit-line driven method. Please refer to FIG. 3, a timing chart when plate-line driven method is used to access the ferroelectric memory using the ferroelectric memory in FIG. 2 as an example. At the initial stage, P and P′, the polarized state of ferroelectric capacitor Cf and that of ferroelectric capacitor Cf′, are of positive polarity and negative polarity respectively. Firstly, enable word line WL during period T1 such that transistors T and T′ can be conducted. Next, enable plate line PL during period T2 and raise the voltage in plate line PL to high level. Since the voltage drop of ferroelectric capacitors Cf and Cf′ has changed to be positive, their polarized states P and P′ as shown in the diagram become positive as well. With the change in polarity from negative to positive, the capacitance of ferroelectric capacitor Cf′ becomes larger and stores more electric charges causing bit line BL′ to have a higher voltage accordingly. Following that, enable sensing g amplifier SA to enlarge the voltage difference between bit line BL and bit line BL′ to facilitate the identification of the data stored at the memory unit. Meanwhile, the voltage in bit line BL′ whose voltage is higher will be raised to high level; the voltage in bit line BL whose voltage is lower will be reduced to low level. The voltages in bit line BL′ and the voltage in plate line PL are both at high levels, so the voltage drop in ferroelectric capacitor Cf′ nears zero. The transition for the polarized state P which still remains positive is shown in the diagram. The abovementioned period T1 and T2 are driving stage during which time bit line voltages are differentiated; period T3 is sensing stage.
During period T3, P′, the polarity of ferroelectric capacitor Cf′ which was originally negative prior to accessing stage, becomes positive. In order to restore the original polarized state for ferroelectric capacitor Cf′, some recovery procedures need to be taken. First, disable plate line PL during period T4, so that P′, the polarized state of ferroelectric capacitor Cf′, will become negative for the voltage drop in ferroelectric capacitor Cf′ has already turned negative. Next, disable sense amplifier SA during period T5 such that the voltage in bit line BL will drop immediately causing the voltage drop in ferroelectric Cf′ to be reduced to zero. The original polarized state will thus be restored.
The plate-line driven method enables plate line PL and word line WL first causing bit lines BL and BL′ to generate different voltages according to the polarized states of ferroelectric capacitors Cf and Cf′. The bit-line driven method enables bit lines BL and BL′ before enabling word line WL, so that bit lines BL and BL′ can generate different voltages according to the polarized states of ferroelectric capacitors Cf and Cf′. This has been understood by those who are conventional with this technology and will not be repeated here.
In order to further improve access quality, an over-driven access method is proposed in "A 76 mm2 8 Mb Chain Ferroelectric Memory" (ISSCC, 2001). Please refer to FIG. 4, a schematic diagram for ferroelectric memory 400 according to a conventional over-driven access method. Ferroelectric memory 400 differs from the abovementioned ferroelectric memories in that bit lines BL and BL′ are respectively connected to transistors Q and Q′ and to capacitors Cov and Cov′. Please refer to FIG. 5, a timing chart according to a conventional over-driven method. Suppose the polarized states of cells CL and CL′ are negative and positive respectively at the initial stage. The over-driven access method is used to assist the abovementioned plate-line driven method or bit-line driven method. In the present example, over-driven access method is used to assist plate-line driven method. First, raise the voltage in plate line PL at time t1. Since the polarity of cell CL has already changed from negative to positive, cell CL will have a larger capacitance and have more electric charges to be coupled to bit line BL. Consequently, the voltage in bit line BL will be higher than that in BL′ with a voltage difference of Δv1. Next, reduce over-driven voltage ODV at time t3, so that the voltages in bit lines BL and BL′ will drop accordingly. Owing to a larger capacitance in cell CL, the voltage in bit line BL will drop slower than that in bit line BL′. Due to the introduction of over-driven voltage OVD, Δv2, the voltage difference between bit line BL and bit line BL′, is enlarged and is greater than Δv1. Last, initiate sense amplifier SA at time t5 to raise the voltage in bit line BL to high level and reduce the voltage in bit line BL′ to low level. The contents stored at the present memory unit will be able to be accessed. However, more capacitors and transistors are required in this method resulting in an increase in chip size and manufacturing cost as well.

Over-driven access method and device for ferroelectric memory


A walker is provided which is equipped with detectors for measuring various loads and torques placed thereon by a user including right side and left side loads as well as torque loads on the handles of the walker and having time and distance detectors to allow the ambulation status of a user to be progressively monitored by medical personnel.

In any injury affecting ambulation, balance, or general physical mobility of a patient it is the goal of physical therapy, and medicine in general, to contribute therapy and treatment to the patient in order to restore these abilities to the highest possible level with respect to the circumstances of age of the patient and the degree of injury sustained. This goal dictates a requirement for assessment of patient improvement during the course of therapy. Such assessment of patient improvement is necessary for both evaluation of the quality and kind of therapy as well as for justification to physicians and insurance providers of continuation of the course of therapy.
The ability to measure and document significant improvement in a patient versus de minimis changes in patient physical ability increasingly is becoming necessary for continuation of treatment protocols. In addition, the ability to objectively measure the various aspects of a patient's physical abilities during a course of treatment or healing of an injury can be utilized to detect patient adherence to the recommendations of the physical therapist or physician. Typically, when out of view of treating medical personnel, it is common for patients to neglect recommended therapies such as prescribed exercises or premature use of a healing limb. This can lead to delay in healing as well as further injury. Yet another area where objective data is useful is in the evaluation of work related injuries for determination of the degree of debilitation of the worker and consequently the evaluation of compensation due the worker.
Heretofore, evaluation of a patient during the term of treatment or analysis of patient debilitation largely has been unquantified. Subjective criteria for determination of patient status have been used by therapists and physicians. Typically, the patient will be observed during the course of a series of movements, and the general impressions of the evaluator will be noted and compared over time. Such observational evaluation can be skewed by many different factors such as patient adherence to treatment protocols, patient desire to be deemed fit for work, therapist desire for monetary gain from continued treatment, and even the personal relationship between patient and therapist.
Therefore, an objective method and apparatus for making quantifiable determinations of patient improvement is needed. Such a method and apparatus should permit collection of reproducible, objective data on patient ambulation, balance, and weight bearing status as well as proprioception in injured areas. The ability to objectively document patient status and improvement over a course of therapy can provide valuable information to the patient, the physician and therapist, and improvement in patient therapy by enabling concise communication between physician and therapist and identification of areas of patient progress versus injuries not responding to treatment.
The availability of objective measurements and data can permit development of consistent medical standards for use in determining whether patient improvement is small, but significant, indicating continuation of treatment, or insignificant indicating the treatment should be changed or discontinued. The availability of objective measurements and data can also be used to develop consistent medical standards for normal functionality and levels of functionality/disability. Such standards of medical evaluation can assist in allocation of medical resources to treatments of greatest utility and to those patients exhibiting more than marginal benefit from treatment.
Therefore it is an object of the present invention to provide an apparatus capable of providing objective quantification of patient ambulation and the balance and weight bearing status during ambulation as well as to provide indication of proprioception status of injured areas;
Another object of the invention is to provide documentation of patient response to therapy for evaluation by physicians and physical therapists;
An object of the present invention is to provide a source of objective feedback to a patient as a means of demonstrating patient success in a course of therapy and to encourage the patient to sustain the course of therapy;
Yet another object of the present invention is to provide a means of evaluating marginally successful treatments versus treatments providing substantial benefits for a patient;
Also, another object of the present invention is to provide a means of specific identification of patient difficulties during ambulation;
Another object of the present invention is to allow therapists and physicians to determine areas of patient improvement with respect to an injury versus aspects of the injury which are unresponsive to the course of treatment;
Yet another object of the present invention is to allow collection of objective data in order to establish and evaluate short term and long term goals with respect to a course of therapy;
Still another object of the present invention is to provide an objective measurement of patient adherence to therapy and to allow more accurate determination of appropriate patient discharge from therapy.
Other objects and advantages of this invention will become apparent from the following description taken in connection with the accompanying drawings, wherein is set forth by way of illustration and example, an embodiment of this invention.

Method and apparatus for objective evaluation of patient ambulation, balance and weight bearing status


A battery pack is disclosed. The battery pack includes one or more battery assemblies and a circuit board connected to the battery assemblies. The battery assembly includes first and second battery cells having the predetermined surfaces overlaid on each other. The first and second battery cells each have battery elements accommodated in a container thereof, and cathode terminals and anode terminals are provided at a same height as the predetermined surfaces at a same side. The cathode terminal and anode terminal of the first battery cell are adjacent respectively to the cathode terminal and anode terminal of the second battery cell.

The present application relates to a battery pack configured by combining a plurality of battery cells.
Recently, portable electronic appliances are widely spread including laptop personal computers (PCs), cellphones, and personal digital assistants (PDAs), and lithium ion secondary batteries are widely used as power sources because of their merits such as high voltage, high energy density, and light weight.
In the laptop PCs, for example, cylindrical lithium ion secondary batteries using an electrolytic solution as an electrolyte are often used, but when an electrolytic solution is used, measures against liquid leakage are demanded. As countermeasures for liquid leakage leading to a problem when using an electrolytic solution, a lithium ion polymer secondary battery has been put to practical use by using, for example, a gel polymer electrolyte having a polymer impregnated with a nonaqueous electrolytic solution, or a solid-state polymer electrolyte.
The lithium ion polymer secondary battery includes a cathode, an anode, and a polymer electrolyte. Battery elements having terminals leading out from the cathode and anode are composed as battery cells covered with a container film or the like. The battery pack is configured to be accommodated in a box-shaped plastic molded case including upper and lower cases as well as a circuit board on which battery cells and circuits are mounted.
In the specification, the "battery element" refers to one configured such that a band-like cathode and a band-like anode are laminated by way of a polymer electrolyte and/or separator, and wound in a longitudinal direction while terminals thereof lead out from the cathode and anode. The battery elements are covered with a soft film, being called a battery cell. The battery cell provided with a circuit board on which protective circuits and the like are mounted, and accommodated in a container is called a battery pack.
In an electronic appliance using a battery pack as a power source, a larger capacity is demanded to extend the operation time of the electronic appliance. To increase the capacity of the battery pack, hitherto, a battery pack has been used which is composed of battery assemblies connected in parallel by overlaying a plurality of battery cells of a same shape in one direction, and connecting electrode terminals at upper and lower positions.
A technology concerning a battery assembly composed of a plurality of battery cells is disclosed in Japanese Patent Application Laid-Open No. 2004-47167.
A battery assembly 100 in related art will be briefly explained below. FIG. 1 shows an exemplary configuration of the battery assembly 100. The battery assembly 100 is configured by a plurality of battery cells 102 overlaid such that cathode terminals 111a and anode terminals 111b (or electrode terminals 111 if polarity is not specified) are positioned in a same direction. The electrode terminals 111 of each battery cell 102 are connected to a circuit board 112 by way of a relay tab 113.
The circuit board 112 is provided with various mounted parts, such as a protective circuit including a charge and discharge control field effect transistor (FET) and an integrated circuit (IC) for monitoring a secondary battery and controlling the charge and discharge control FET, and a connector for making connection with external units. The circuit board 112 has contact points to be connected to the electrode terminals 111. The relay tab 113 is composed of a conductive metal plate of aluminum Al, nickel Ni or the like.
FIG. 2 is a side view showing a state in which the battery assembly 100 is connected with the circuit board 112. When connecting the battery assembly 100 and the circuit board 112 with each other, relay tabs 113 are connected to electrode terminals 111 of a plurality of overlaid battery cells 102 by welding, for example. The relay tab 113 connected to the electrode terminal 111 of one battery cell 102 is folded, for example, like a crank, and is connected to the relay tab 113 connected to the electrode terminal 111 of the other battery cell 102. Then, the relay tabs 113 are connected to contact points of the circuit board 112 by welding, for example. In this manner, the electrode terminals of the plurality of battery cells and the circuit board 112 are electrically connected with each other.
In the case of the battery assembly in related art explained so far, the electrode terminals of the battery cells lead out from the bottom side. For this reason, when the plurality of battery cells are overlaid, they are separated by the portion of thickness of the battery cell itself. In the past, to connect the battery cells and the circuit board, electrode terminals have been mutually connected by using conductive relay tabs between the electrode terminals and the circuit board, and then the relay tabs and the circuit board have been connected. In this case, however, an extra space is demanded for connecting the relay tabs, leading to a problem that the space in the battery pack is not used efficiently.
When connecting electrode terminals of a plurality of battery cells mutually, there is a need that one relay tab is folded toward the other relay tab. When the relay tab is folded and used, however, a stress is applied to the folded portion of the relay tab, so that the relay tab may be broken due to vibration or impact etc., and the relay tab and the electrode terminal may be disconnected, leading to a problem that the quality of the battery pack may be lowered.
When fabricating battery cells, a dimension error of about ±1 mm may occur in the position of electrode terminals. For this reason, when connecting electrode terminals of overlaid battery cells by using relay tabs, positioning is difficult, and the working efficiency may be lowered.


The present disclosure relates to a cartridge case processing device to produce and prepare empty cartridge cases (2) comprising a trimmer holder (6) in which a die body (14) is received in the lower section (6.1) and in an upper section (6.2) a bushing (25, 25.1) guided shaft (5) is received on which a cutter (12), an expander die (3) and a decapping pin (15) are coaxially arranged characterized by the integration of an adjusting nut (26) coaxial with the shaft (5) in the upper section (6.2) of the trimmer holder (6), which when turned relative to the shaft (5) leads to the position of the cutter (12) being adjusted in an axial direction.

1. Field of the Disclosure
This invention relates to a cartridge case processing device for producing, preparing or refurbishing empty cartridge cases.
2. Description of the Related Art
High levels of dimensional accuracy are demanded when preparing cartridge cases, in particular for precision ammunition. Firing a cartridge case leads to an increase in its diameter along its entire length as well as to a linear expansion of the cartridge case. A cartridge case deformed by firing the cartridge must be refurbished to a suitable shape to be reused.
In view of the aforementioned prior art, it is the object of the present disclosure to provide a cartridge case processing device for producing, preparing and/or refurbishing empty cartridge cases that allows simple tool-free handling, while simultaneously facilitating precise tooling of the cartridge case.


An image forming apparatus includes a scanner for scanning a light beam over an image carrier, an image forming unit for forming an image on the image carrier corresponding to the light beam scanned over the image carrier by the scanner and a movable supporting member for supporting an image forming medium and conveying the image forming medium to a position where the image on the image carrier is transferred to the image forming medium. The image forming apparatus further includes a first driver for driving the scanner, a second driver for driving the image carrier, a third driver for driving the supporting member, a generator for generating a reference signal, a first controller for controlling the first driver to regulate the scanning speed of the scanner based on the reference signal generated by the generator and a second controller for controlling the second driver to regulate the moving speed of the image carrier based on the reference signal generated by the generator and a third controller for controlling the third driver to regulate the moving speed of the supporting member based on the reference signal generated by the generator.

1. Field of the Invention
The present invention relates to an image forming apparatus such as a color copier or color laser beam printer.
2. Description of the Related Art
The use of color in image forming apparatuses, such as copiers or laser beam printers, is advancing rapidly. In a color copier, a photosensitive drum as an image carrier and a transferring drum as an image forming medium supporting member which supports the image forming medium are rotated in synchronous contact. A light beam corresponding to each of the original color images is scanned over the image carrier by means of a scanning device. Thus, a latent image corresponding to each of the original color images is formed on the image carrier. This latent image formed on the image carrier is developed as color toner images by multiple colored developing agents each corresponding to the original color image. Each of these respective color toner images which has been developed is transferred in succession and superimposed one on another on the image forming medium supported on the transferring drum. By this means a toner image corresponding to the original color image is formed and fixed on the image forming medium.
In this type of color image forming apparatus, the color image is formed by the successive superimposition of each of the color toner images on the image forming medium. Therefore, the most important factor is to prevent color slippage.
The image forming apparatuses, in the prior art are designed to equalize the distance from the exposure position on the image carrier to the transferring position in the direction of rotation and the distance from the leading edge position of the image forming medium to the transferring position in the direction of rotation. Therefore, the formation of the latent image corresponding to each of the colors of the original image is commenced when the leading edge position of the image forming medium on the transferring drum is detected. By this means, the matching between the toner images of each colors is performed.
Furthermore, as one method of preventing color slippage, a control method which concerns the drive of the image carrier and the image forming medium supporting member is disclosed in, for instance, Japanese Laid-Open Patent No. 61-217076. In the control method disclosed in that Patent, a driving mechanism is provided which does not give rise to pitch randomness and color randomness. The image carrier and the image forming medium support member are designed to be driven independently by separate driving devices. Thus the load fluctuations of the image carrier are not transmitted to the image forming medium support member, nor are the load fluctuations of the image forming medium support member transmitted to the image carrier.
However, in this type of image forming apparatus, when executing multiple transferring for each color, the leading edge positions of the toner image on the image carrier and of the image forming medium are matched. Then, when executing the image forming process by means of leading edge position matching between the respective color toner images, the rotational drive of the image carrier and the rotational drive of the transferring drum on which the image forming medium is supported and, moreover, the drive of a polygon mirror as the scanning device which scans the light beam over the image carrier are driven asynchronously. Therefore, when phase slippage occurs between the detection signals which detect the leading edge position of the image forming medium and the horizontal synchronization signals for controlling the image forming process, this phase slippage will accumulate during the execution of the image forming processes for multiple colors. The control of the leading edge position matching of the image forming medium will be affected by this. This results in the problem of color slippage occurring in the image on the image forming medium when the images formed on the image carrier are transferred on the image forming medium.
That is, in a prior art image forming apparatus, when executing multiple transferring for each color, the rotational drive of the image carrier and the rotational drive of the tranferring drum and, moreover, the drive of the scanning device which scans the light beam over the image carrier are driven asynchronously. Therefore, phase slippage occurs between the detection signals which detect the leading edge position of the image forming medium and the horizontal synchronization signals for controlling the image forming process. The control of the leading edge position matching of the image forming medium is affected by this. This results in the problem of color slippage occurring in the image on the image forming medium.


A brake monitoring system for use on a motor vehicle includes a sensor connected to each brake actuator on the motor vehicle for monitoring the position and travel of the brake actuator and for generating and transmitting a brake condition signal; a data processor carried in an axle box associated with each axle and connected to sensors associated with brakes for the axle for receiving, interpreting, storing, and upon request, transmitting the brake condition signal, wherein each data processor includes an auto-address mechanism to identify its position on the vehicle; and a master station, wherein said master station includes a display for identifying a particular vehicle brake, a quantitative indication of the travel on the brake actuator associated with the particular brake, and wherein said visual indicating devices which are indicative of said safety condition of a particular brake.

Vehicle brakes, such as vehicle brakes for heavy vehicles, such as trucks, tractor-trailer combinations and buses, must be inspected and maintained. Degradation and failure of the brakes may result in catastrophic events. As such, the Federal Department of Transportation (DOT) has issued standards to insure that brakes are properly adjusted and operable to stop the vehicles if need arises.
Large vehicle brakes are inspected at check points, such as weigh stations. With such checks, a driver, operator or inspector may crawl under the truck to inspect the travel of the actuator arms to insure compliance with federal and state regulations. Typically the inspection must be done for each brake on a vehicle. In some inspection systems, the driver may have to operate the brakes during the inspection such that the driver stays in the cab of the truck while the inspector visually checks each brake.
Further, under standard practice, it is recommended that drivers/operators perform a brake inspection as part of the normal daily routine before commencing a day's driving. However, because of the difficulties in performing a brake inspection such daily inspection are often not performed. The failure to perform the daily brake inspection is further a result of the difficulties in performing the inspection without the assistance of another.
Brake monitoring systems have been developed previously. As an example, prior systems have attempted to monitor air pressure to determine if the brakes are operating safely. In other systems, a warning is provided after the brake travel has exceeded legal limits. Further, other systems have been developed to provide a visual indication during the visual inspection. The necessity of visual inspection for each brake results in a number of difficulties, including difficulties in obtaining sufficient inspections, failure to fully inspect due to time and effort, etc.
A further system is described in U.S. Pat. No. 7,373,224 directed to a dedicated master station. It should be appreciated that the disclosure of U.S. Pat. No. 7,373,224 is hereby incorporated by reference for all purposes.
However the inventors herein have recognized that such prior systems fail to address multiple and dynamic axle configurations. Further, in contrast to prior systems, the current system provides indication of failed modes. Specifically, in the prior system, a master station could be configured to display the status of each brake with multiple colored lights. Once the brakes were released, the lights for normal brake travel would extinguish, except for marginal or out of limit brakes. Under normal conditions, the system lacked ability to display normal brake-travel. For instance, if a data collector failed, there would be no indication on the Master Station. The operator would have no indication of this failed mode, as no lights would illuminate.
Further, it is noted that the prior systems depended on sensors that were not commercially available and had to be built and manufactured to the design and environmental specifications. Similarly, the prior systems typically relied on modifying the brake pedal to attach an additional sensor to detect pedal activity. This brake pedal modification would require additional long term maintenance, and ran the risk of interfering with normal braking operations.
The present embodiment disclosed herein provides systems and methods for communicating information related to qualitative assessment of the brake system. The qualitative assessment of the brake system may include monitoring of brake travel within set limits. In addition to brake travel, the system may be useful in monitoring the timing of brake system. Such assessment may be used to diagnose air leaks in a vehicle and correct sequencing of the air valves. It should be appreciated that the correct sequencing of a truck's air valves determines the quality of braking. If air valves are not sequencing properly, the truck will need a longer distance within which to stop (sopping power may be exponentially affected depending on the number of air valves not sequencing properly). Depending on which air vale is not functioning and then how many are not functioning, the entire braking system may ultimately jackknife the truck. Air valves sequencing properly assures that the truck will brake straight and in a manner expected.
The disclosed embodiments further provide improved graphical display, industry standard communications and reliable sensors. Moreover, the system is adjustable to accommodate brake systems of different stroke travel. There are numerous versions of drum brakes, each with a specific maximum travel, or stroke. In the disclosed embodiments, system configurations are provided for the type of brake on the vehicle by axle.
As described herein, this system provides reliable readout of all axles, giving the operator the assurance that the system is monitoring all brakes. The Display Unit of the present disclosure is easy to operate, and at first glance, communicates the overall condition of the brake system before embarking on the road. Such communication provides for proper maintenance of the vehicle brake system. As one example, an inspector may take their typical measurements and cross check with the operator regarding the display numbers.
This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. Furthermore, the claimed subject matter is not limited to implementations that solve any or all disadvantages noted in any part of this disclosure.

Brake monitoring system for heavy vehicles


A multifunctional control device and method is used to determine a head channel selecting signal for playback heads of a video tape recorder and for controlling a phase shift direction of a video signal according to a desired reproduction mode. The video tape recorder has four heads, a first pair for use during standard play and a second pair for use during super long play. The heads read out recorded video signals and a first switch is connected to the first pair of heads and a second switch is connected to the second pair of heads for selectively providing outputs to corresponding amplifiers, under control of a servo controller. A third switch is connected to the outputs of the amplifiers for providing outputs under control of a microcomputer. The microcomputer controls the servo controller which in turn controls the speed of a drum motor and a capstan motor. The microcomputer also provides a phase shift direction controlling signal. An output of the servo controller is provided to the microcomputer along with an output of a comparator comparing the outputs of the amplifiers.

Generally, a multifunctional video tape recorder has not only a normal function for reproducing tapes in a normal manner, but also has special functions such as still picture reproducing, slow picture reproducing, high speed reproducing, double speed reproducing and the like. In order to perform the above-mentioned functions, the multifunctional video tape recorder is provided with two pairs of heads which are different in their head widths in the double-azimuth head type. Of the two pairs of heads, one pair are used in a standard play i.e., SP, mode while the other pair are used in a super long play i.e., SLP, mode.
Therefore, in a multifunctional video tape recorder, the reproducing head should be selected in accordance with the designation of the user, and the phase shift direction of the video signal reproduced in accordance with the head thus selected has to be controlled. The controlling of the phase shift direction of the video signal shifted occurs in the video signal reproducing processor unit. In a VHS-type video tape recorder, the phase of the video signal is advanced by 90.degree. for every horizontal line for a given track and conversely, the phase is delayed by 90.degree. for every horizontal line for the adjacent track to the given track, so that a crosstalk component of the reproduced video signal will be removed. The conventional circuit for head selecting and phase shift direction controlling is constituted as shown in FIG. 1, and this circuit will be described as to its operation below.
A microcomputer 100 generates function control data for the reproducing function designated by the user, and this data is supplied to both a servo controller 104 and a multifunctional controller 105. The servo controller 104 controls the speeds of a drum motor M1 and a capstan motor M2 through lines 2 and 3 respectively, by means of the function controlling data which is supplied from the microcomputer 100 through a bus line 1, while the servo controller 104 also controls switching operations of first and second switches SW1, SW2 through a line 4, and sends a head channel selection signal to a multifunctional controller 105.
The multifunctional controller 105 outputs an amplifier selecting signal through a line 6 in accordance with a function control data supplied through bus line 1, the head channel selecting signal supplied through line 4, and a comparing signal supplied through a line 5 from a comparator 103, while the multifunctional controller 105 also outputs a phase shift direction controlling signal through a line 7. Then the switching operation of third switch SW3 is controlled in accordance with the amplifier selecting signal.
First the normal reproducing function will be described. The normal reproducing function can be described based on a classification into the standard play mode and the super long play mode, and special reproducing can also be described based on a classification into the standard play mode and the super long play mode.
First in the case of the standard play mode in the normal reproducing function, the first switch SW1 alternately supplies to a first amplifier 101 video signals read out by first and second heads SP1, SP2 in response to the head channel selecting signal. The first amplifier 101 which receives the video signals through the first switch SW1 amplifies the video signals at a constant amplifying rate, and supplies them to the third switch SW3, while the third switch SW3 outputs the output signals of the first amplifier 101 through a line 8 in accordance with the amplifier selecting signal.
Meanwhile, the phase shift direction controlling signal is generated in response to the azimuth angle of the selected head according to the first and second heads SP1, SP2 which are alternately selected. Thus, if the first head SP1 having an azimuth angle of +6.degree. is selected, the phase shift direction controlling signal is generated as a high logic state while, if the second head SP2 having an azimuth angle of -6.degree. is selected, the phase shift direction controlling signal is generated as a low logic state.
Second, in the case of the super long play mode in the normal reproducing function, the second switch SW2 supplies to a second amplifier 102 the video signals read out alternately by third and fourth heads SLP1, SLP2. The second amplifier 102 amplifies the video signals incoming through the second switch SW2 at a constant amplifying rate to output them to the third switch SW3, while the third switch SW3 transmits the output signals of the second amplifier 102 through a line 8 in response to the amplifier selecting signal. Then each time the third and fourth heads SLP1, SLP2 are selected, the phase direction controlling signal is generated in response to the azimuth angle of the selected head. Thus, if the third head SLP1 having an azimuth angle of +6.degree. is selected, the phase shift direction controlling signal is generated as a high state while, if the fourth head SLP2 having an azimuth angle of -6.degree. is selected, the phase shift direction controlling signal is generated as a low state. Further, in the case of multifunctional reproducing functions, i.e., in the case of the special functions, the tape runs at a speed different from that of the normal reproducing function and therefore, correct readings can not be made from the tape.
Within a single time interval between the change-overs of the head channels, a plurality of video tracks will pass, and therefore, the first to fourth heads SP1, SP2, SLP1, SLP2 will move simultaneously or separately. Therefore, the heads can be selected in synchronization with the comparing signal which is the output of the comparator 103, or the heads can be selected in synchronization with the head channel selecting signal for reading out the video signals from a proper head within a single time interval. In the case of multifunctional reproducing functions, the selections of the heads are made as specified in Table 1--1 below, while the wave patterns of the amplifier selection signals and the phase shift direction controlling signals are shown in FIG. 2. Meanwhile, the heads and amplifiers selected in accordance with the head channel selecting signal and the amplifier selecting signal, and the phase shift direction controlling signal generated in accordance with them, are as shown in Table 1-2 below.
TABLE 1-1 ______________________________________ Function Video head selected ______________________________________ Normal reproducing SP: SP1, SP2 SLP: SLP1, SLP2 Still picture reproducing SP: SP2, SLP2 SLP: SP1, SLP1 Slow picture reproducing SP: SP2, SLP2, SP1 SLP: SLP1, SP1, SLP2 Double speed reproducing SP: SP2, SLP2 SLP: SP1, SLP1 High speed reproducing SP: SP1, SP2, SLP1, SLP2 SLP: SLP1, SLP2 ______________________________________
TABLE 1-2 ______________________________________ Operating Item voltage Selection Remarks ______________________________________ Head channel SP: H SP2 SP1: +6.degree. selecting L SP1 SP2: -6.degree. signal SLP: H SLP1 SLP1: +6.degree. L SLP2 SLP2: -6.degree. AMP selecting H AMP1 AMP1: SP head signal L AMP2 AMP2: SLP head Phase shift H +6.degree. direction L -6.degree. controlling signal ______________________________________
As described above, the conventional circuit for generating the head channel selecting signal and the phase shift direction controlling signal is very complicated because it selects the amplifiers and generates the phase shift direction controlling signal through a multifunctional controller 105.

Multifunctional control type video head selecting device and method thereof


A cam bar assembly for transferring a trolley from driving engagement with a first chain to driving engagement with a second chain wherein the cam bar assembly includes a cam bar having a first longitudinal axis, a cam surface centered about the first longitudinal axis, a second longitudinal axis, and a cam face centered about the second longitudinal axis. The second longitudinal axis is offset from the first longitudinal axis. The present invention is also directed to a power and free conveyor having the cam bar assembly as well as a drive trolley disposed within a free track for movement in a driven direction and having a retractable surface movable between an engaging position and a retracted position. The power and free conveyor also includes a first drive chain, a second drive chain, and a transfer zone having an entrance and an exit. The first drive chain is positioned to drivably engage the drive trolley at the entrance and the second drive chain is positioned to drivably engage the drive trolley at the exit. The cam bar is positioned in the transfer zone to engage the drive trolley and move the retractable surface from its engaging position to its retracted position.

1. Technical Field
The present invention generally relates to material handling conveyors and, more particularly, to a transfer assembly for a chain driven conveyor system.
2. Discussion
A wide variety of conveyor systems are available in the art for transporting articles through a manufacturing facility. For example, power and free (PF) chain conveyor systems which generally include trolleys coupled to move a workpiece. The trolleys are commonly freely movable within a support track which is positioned to place the trolleys in operative engagement with a drive chain having pusher dogs. The dogs drivably engage the trolleys to move the trolleys through the manufacturing area.
In many PF conveyor systems the workpiece and associated trolleys are transferred between separate drive chains so that one of the chains can move the workpiece through a first work area and the second chain can move the workpiece through a second work area. A chain-to-chain transfer assembly is commonly provided in the PF conveyor system to transfer the trolleys between driving engagement with the first chain (the wipe-off chain) and the second chain (the wipe-on chain). More particularly, during the transfer operation, a pusher dog fixed to the wipe-off chain brings the trolley into a transfer zone where the wipe-off and wipe-on pusher dogs could simultaneously engage the trolley. To prevent simultaneous engagement, a mechanical cam is positioned to move the retractable dog of the trolley to a height where the wipe-off chain, but not the wipe-on chain, is engageable with the trolley. The wipe-off chain is therefore able to push the trolley to a point in the transfer zone where the trolley drops off the cam bar and into its engaging position where the wipe-on dog can move the trolley away from the transfer zone.
A representative prior art transfer operation is illustrated in FIGS. 1-5 and includes a wipe-off drive chain 10 that drives a trolley 14 into the transfer zone and a wipe-on drive chain 12 that drives the trolley out of the transfer zone. A cam bar 16 is positioned in the transfer zone between the wipe-off and wipe-on drive chains and is configured to operatively engage a retractable dog 18 on the trolley 14 (FIGS. 3 and 4) to transfer the trolley from driving engagement with the wipe-off drive chain 10 to driving engagement with the wipe-on drive chain 12.
More particularly, the wipe-off drive chain 10 drives the retractable trolley dog 18 onto the cam bar which is configured to raise the trolley dog from a lowered position to a raised position (shown in FIG. 4 and in shadow in FIG. 5). The wipe-off track then curves away from the cam bar such that the wipe-off pusher dog 20 (FIG. 4) is moved out of engagement with the trolley dog 18. If the trolley 14 has sufficient momentum, the trolley dog passes by the forward end 24 (FIGS. 1 and 2) of the cam bar, drops into its lowered engaging position, and is drivably engaged by the next wipe-on pusher dog 22. When the retractable dog 18 is in its raised position, the pusher dog 22 of the wipe-on drive chain 12 is positioned below and operably disengaged from the drive surface 25 of the retractable dog 18 (FIG. 4). The cam bar 16 maintains the retractable dog in this raised position until the rear surface of the retractable dog slides off the cam bar thereby permitting the retractable dog to return to its engaging position. The wipe-on chain dog 22 is then operably engageable with the lowered retractable dog 18 so as to push the carrier trolley out of the transfer zone.
The smooth operation of the PF conveyor system depends upon the efficient transfer of trolleys from the wipe-off drive chain to the wipe-on drive chain. Even a small percentage of missed transfers cause manufacturing inefficiencies. Missed transfers are most common in the prior art design when the wipe-off chain is moving slower than the wipe-on chain 12. With a slow moving wipe-off chain and correspondingly slow moving trolley, the trolley may have insufficient momentum to overcome the sliding friction between the riding surface 26 of the trolley and the cam bar. The trolley then occasionally gets caught up on the cam bar which maintains the retractable dog 18 in its retracted position and therefore not drivably engageable by the pusher dog 22 on the wipe-on drive chain 12. The trolley 14 then sits on the cam bar and obstructs the movement of the next trolley causing a blockage of trolley transfer.
A representative trolley, such as the Dog Magic(copyright) trolley manufactured by Jervis B. Webb Company of Farmington Hills, Mich., the assignee of the present invention, is illustrated in FIGS. 3-5 to include an anti-backup tail 28 located rearward of the riding surface 26. The riding surface 26 includes a lead end 30 and a trailing end 32 while the anti-backup tail 28 includes a rear tip 34 spaced from the trailing end 32 as indicated by reference numeral 36. When the trolley has insufficient forward momentum, the trolley 14 may come to rest with the tail 28 sitting on the cam bar thereby prohibiting the retractable dog 18 from fully returning to its engaging position and preventing the wipe-on pusher dog 22 from operatively engaging the dog 18.
In an attempt to decrease the frequency of the trolley getting caught up on the cam bar, the prior art has used various auxiliary pushing mechanisms (e.g., such as air cylinders that impact the rear of the trolley 14) to increase the forward momentum of the trolley. While these techniques have provided some increase in efficiency, 100% transfer, particularly during slow wipe-off and fast wipe-on speeds, have not been achieved.
In view of the above, a need exists for a cam bar design that more efficiently transfers trolleys from driving engagement with the wipe-off chain to driving engagement with the wipe-on chain. The improved cam bar design addresses both of the above-identified sources of trolley interference: the riding surface of the trolley getting caught up on the cam bar and the anti-backup tail remaining on the cam bar after the retractable trolley dog clears the downstream end of the cam bar. Accordingly, the present invention includes an improved cam bar design having a primary cam bar and a secondary cam bar that is longitudinally separated and axially offset from the primary cam bar. The many advantages of this arrangement include reducing the length of the dead zone, i.e., the zone where the wipe-off and wipe-on chains are each operably disengaged from the trolley and the trolleys momentum is relied upon to clear the cam bars, and arranging the offset of the split cam bars to permit the retractable dog to drop fully into its engaging position even if the trolley stops when the retractable dog is at the downstream end of the secondary cam bar. Under this condition, the anti-backup tail fully clears the first cam bar at approximately the same time the riding surface of the retractable dog drops off the secondary cam bar. This design virtually eliminates missed take-away chain dogs and reduces the possibility of drive torque outs due to trolleys jamming into pusher dogs.
Further scope of applicability of the present invention will become apparent from the following detailed description, claims, and drawings. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art.

Split cam bar for chain-to-chain transfer


A disk change signal generating circuit which uses an index sensor includes an index sensor for generating an index pulse in order to detect a rotation of a floppy disk, a timer for inputting the output of the index sensor into a clear terminal and inputting a clock signal into a clock terminal, thereby generating a counting value in a predetermined frequency, and a disk change signal generating circuit for generating a disk change signal by inputting the output of the timer.

The present invention relates to a floppy disk driving apparatus, particularly to a circuit which generates a disk change signal for detecting existence of a floppy disk inserted thereto.
Conventionally known is a floppy disk driving apparatus with an index sensor which detects the rotation of the floppy disk and a disk-in sensor which detects the insertion of the floppy disk. FIG. 1A and 1B show schematic diagram of the conventional floppy disk driving apparatus.
Referring to FIG. 1A, when a floppy disk is inserted into a floppy disk driving apparatus, light-receiving transistor PQ1 is turned off, cutting off an emitted light from the light emitting diode PD.sub.1 of the disk-in sensor S1. If light-receiving transistor PQ1 is turned off, a logic signal of a line 1 becomes high level signal and then the high level signal is applied to clear terminal a flip-flop FF.sub.1.
Applying disk change reset signal from a controller in the clock terminal CLK of the flip-flop FF.sub.1, thereby outputs the logic high level signal through the output terminal Q of the flip-flop FF.sub.1 and then the disk-in sensor detects the insertion of the floppy disk. Changing the disk change signal logic "high level" outputted from the flip-flop, the controller senses the disk change signal, and thereby regularly controls the floppy disk driving apparatus.
When the floppy disk is ejected from the floppy disk driving apparatus, the disk-in sensor S1 is operated, and outputted logic "low level signal" through the line 1, thereby the output signal of logic "low level signal" is applied to the clear terminal CLR of the flip-flop FF.sub.1 and then the flip-flop is cleared. Thereby, the logic "low level signal" is outputted through the output terminal Q of the flip-flop FF.sub.1. When the disk change signal outputted from the output terminal of the flip-flop FF.sub.1 becomes the logic "low level signal", the controller detects a extraction of the floppy disk.
Referring to FIG. 1B which is a circuit for detecting a rotation of the floppy disk, an index sensor S2 is operated by a cycle the rotation of the floppy disk, thereby an index sensing circuit 10 detects an index pulse. Conventional floppy disk driving apparatus as shown FIG. 1A and 1B comprises the disk-in sensor and the index sensor, thereby a circuit, of floppy disk driving apparatus is complex and requires a large printed circuit board.

Circuit for generating a disk change signal


A dry end section for a paper-making machine for producing a high-bulk tissue is provided. Such a machine comprises a through-air dryer adapted to finally dry a paper web and a through-air drying fabric configured to transport the web through the through-air dryer. A separating device is included for facilitating separation of the web from the through-air drying fabric. A reel is also provided and is configured to receive the web thereon. The web is received directly on the separating device or on a fabric wrapped about the separating device. In some instances, the web may be compressed between the separating device and an adjacent roll or by a web-compressing device disposed along the fabric transporting the web. The web is then transported to the reel directly from the fabric or other support mechanism extending between the separating device and the reel, without free draw of the web. Associated methods are also provided.

1. Field of the Invention
The present invention relates to paper-making machinery and, more particularly, to a paper-making machine and associated method for making a tissue paper with improved tactile qualities while improving the reel-up process.
2. Description of Related Art
In the production of tissue for use in personal hygiene products and the like, it is desired to produce a tissue with good tactile qualities (i.e., silky and soft to the touch) while also achieving a high machine speed and efficiency. The speed and efficiency are often limited by the performance of the dry end of the machine between the final dryer and the winding station or reel-up. Tissue is extremely delicate and difficult to handle, especially at high machine speeds. For example, in some instances, the tissue web is dried by a through air dryer ("TAD"), wherein a through air drying fabric ("TAD fabric") is used to transport the web through the TAD. The TAD fabric is generally an open structured drying fabric. Accordingly, the web will tend to become drawn into the structure of the TAD fabric as the web is processed through the TAD and other processing devices such as, for instance, a molding device, in order to produce a structured three-dimensional fiber network. However, separating the tissue web from the TAD fabric without damaging the web then becomes a difficult and sensitive task.
In addition, due to the generally delicate nature of the tissue web, excessive transfers and handling of the web in the dry end of the machine may result in damage to the web. Such detrimental results may also occur if the web is unsupported between components within the dry end. Further, if a bulky tissue web is produced in the paper-making process, the capacity of the roll on which the web is wound may be undesirably low since the web cannot be tightly wound onto the roll. A loosely wound roll is relatively more difficult to handle and may be undesirably prone to, for example, telescoping with respect to the roll.
Thus, there exists a need for a method and apparatus directed to a dry end of a tissue paper-making machine for making a tissue web providing improved tactile qualities while improving the handling of the tissue web in the dry end. Such an apparatus and method should desirably be capable of addressing the issue of separating the tissue web from a TAD fabric efficiently and at high speed, but without damage. Further, such an apparatus and method should provide for minimal transfers and other handling of the tissue web while providing support for the tissue web throughout the dry end. In addition, the apparatus and method should be directed to reducing the bulk of the tissue web, again with minimal handling and while providing the desired improved tactile quality, in order to increase roll capacity and facilitate handling of the rolls.

Method and apparatus for making a tissue paper with improved tactile qualities while improving the reel-up process for a high bulk web


Apparatus and method for designing an electrical component including a processor and a user interface, enabling a user to input a desired characteristic of the electrical component, such as inductance or quality factor at an operating frequency for an integrated spiral inductor. The processor is configured to determine sufficiently optimal characteristics of the electrical component, combining the user desired characteristic with other preset characteristics of the electrical component, to define a first model of the electrical component, to simulate the model having the combined characteristics to determine performance, and to draw on a rule-set of expert knowledge relating to the general dependency of at least one design criterion, such as a physical, geometrical or performance characteristic, with another design criterion in order to enable modification of the model, thereby iteratively to determine a design solution for the electrical component through one or more simulations and modifications using the rule-set.

Designing and optimizing spiral inductors on silicon has been a painstaking and costly experience, one associated with consecutive silicon spins and several hours of wait with electromagnetic (EM) simulators. Often, the related effort cannot be ported to new silicon processes; moving to a new process with a different metal stack, minimum feature size and grid, means that any spiral optimized at the previous process node will most probably be off in the new one. Overdesign does not apply here; key spiral inductor properties such as quality factor and resonance frequency are largely dependent on parasitics, and these change irregularly between process nodes, especially in the sub-100 nm region.
A variety of methodologies and Electronic Design Automation (EDA) tools have been developed to facilitate synthesis and optimization of inductors in integrated circuits. Each one, however, comes with certain disadvantages.
The methodology of geometric programming (GP) uses a lumped-element inductor model, where each of the parameters is represented by a posynomial expression. The optimization problem with objective (inductance at operating frequency) and constraints (quality factor, self resonance frequency, area) in posynomial form is expressed as a geometric program in convex form that can be solved globally. The major disadvantage of this method is that it requires prior knowledge of the mathematical expressions relating each geometric parameter to inductor performance; this cannot be achieved fully or is impractical in the context of modern silicon processes, where multiple design and manufacturing parameters come into play in the fabrication of an integrated inductor. For instance, there exists no known mathematical formula for relating inductor quality factor to the number and properties of metal layers that can be stacked to construct the inductor's tracks.
Some methodologies in the prior art synthesize and optimize inductors based on 'trained' equivalent lumped-element inductor models. Models are trained using either measurements or simulation results that come from full-wave EM solvers or quasi-static EM solvers. The accuracy of the methodology strongly depends on the accuracy of the measurements or simulation results and on the type of the lumped-element model. A major drawback of this approach is that the model should be separately trained for each manufacturing process or process node and is not globally valid for all processes. This leads to increased setup times, poor re-usability between silicon processes, and other inefficiencies.
Other methodologies rely on physical lumped-element inductor models for the synthesis and optimization procedure. The lumped element values are computed from analytic expressions derived from the underlying physics and parameters related to the process, while measured data are only used for validation. For every process several thousands of geometries are modeled and simulated. The geometric parameters and the simulation results are stored in a database. The synthesis and optimization tool retrieves from the database and delivers the optimal geometry that satisfies the objective and constraints of the problem. The method is fast; its accuracy however depends on the accuracy of the model and the size of the database. Also, this method is by definition not re-usable between processes.

Expert system-based integrated inductor synthesis and optimization


A nonvolatile semiconductor memory device includes a floating gate; an erasing gat; and a control gate. The floating gate is provided on a channel region of a semiconductor substrate through a first insulating layer. The erasing gate is provided on the floating gate through a second insulating layer. The control gate is provided beside the floating gate and the erasing gate through a third insulating layer. The floating gate is U-shaped.

1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and especially relates to a split-gate nonvolatile semiconductor memory device.
2. Description of Related Art
A split-gate nonvolatile semiconductor memory device is known as a nonvolatile semiconductor memory device. For example, Japanese Laid-Open Patent Applications JP-P2001-230330A, JP-P2000-286348A, and JP-P2001-085543A, disclose the split-gate nonvolatile semiconductor memory devices, each of which has an erasing gate.
FIG. 1 is a cross-sectional view showing a configuration of a nonvolatile semiconductor memory device disclosed in JP-P2001-230330A. This nonvolatile semiconductor memory device includes: a floating gate 120 formed on a semiconductor substrate 110 via a gate insulating film 112; an erasing gate 140 formed on the floating gate 120 via insulating films 113 and 114; a control gate (not shown in the figure) formed on one side wall portion of the floating gate 120, the insulating films 113 and 114, and the erasing gate 140 via a insulating film (not shown in the figure) formed to coat the floating gate 120, the insulating films 113 and 114, and the erasing gate 140; and a diffusion region (not shown in the figure) formed on a surface layer of the substrate 110 so as to adjoin the floating gate 120 or the control gate. This nonvolatile semiconductor memory device is provided with the erasing gate 140 directly above the floating gate 120. In the figure, sharpened portions (sharpened portions 121) in upper portions of both ends of the floating gate 120 have a structure in which an electric field tends to be concentrated. Accordingly, an erasing operation is realized by extracting electrons from the sharpened portions 121 to the erasing gate 140.
FIG. 2 is a cross-sectional view showing a configuration of a nonvolatile semiconductor memory device disclosed in JP-P2000-286348A. This nonvolatile semiconductor memory device includes a floating gate 220 and a control gate 230 on a semiconductor substrate 210 having a first diffusion region 251 and a second diffusion region 252. This nonvolatile semiconductor memory device is characterized by having an erasing gate 240 which is formed so as to adjoin the floating gates 220 of adjoining memory cells via a tunnel oxide film 214 and is connected to a first diffusion region 251 with keeping a certain interval. This nonvolatile semiconductor memory device provides the erasing gate 240 on a side of the floating gate 220. In the figure, a sharpened portion (a sharpened portion 221) on an erasing gate 240 side of the floating gate 220 have a structure in which an electric field tends to be concentrated. Accordingly, an erasing operation is realized by extracting electrons from the sharpened portions 221 to the erasing gate 240.
FIG. 3 is a cross-sectional view showing a configuration of a split-gate memory cell disclosed in JP-P2001-085543A. This split-gate memory cell includes a source region 351 and a drain region 352 formed on a semiconductor substrate 310, a channel region sandwiched by the source region 351 and the drain region 352, a floating gate electrode 320 formed on the channel region via a floating gate insulating film 311, a control gate electrode 330 formed on the channel region via a control gate insulating film 312, and an erasing gate electrode 340 formed on the floating gate electrode 320 via an erasing gate insulating film 315. The floating gate insulating film 311 and the erasing gate insulating film 315 include independently separated insulating film, respectively. The nonvolatile semiconductor memory device is characterized in that the floating gate electrode 320 is formed in a self-aligning manner with respect to the control gate electrode 330. In the figure, a sharpened portion (a sharpened portion 321) on an erasing gate 340 side of the floating gate 320 have a structure in which an electric field tends to be concentrated. Accordingly, an erasing operation is realized by extracting electrons from the sharpened portions 321 to the erasing gate 340.
In a nonvolatile semiconductor memory device, its operation speed is increasingly high in these years. For example, as for the nonvolatile semiconductor memory device incorporated in a microcomputer, since an operation speed of the microcomputer itself has been increasingly high, the operation speed of the nonvolatile semiconductor memory device is strongly required to be high. In addition, the nonvolatile semiconductor memory device is required to satisfy requirements of finely miniaturizing a circuit and of lowering an operating voltage.
The inventor has now discovered following facts.
A technique of JP-P2001-230330A discloses a structure in which the erasing gate 140 (a portion facing the sharpened portion 121) is embedded between the two floating gates 120 as shown in FIG. 1. For this reason, the erasing gate 140 and the floating gate 120 face each other at surfaces (a surface 140a and a surface 120a). In this case where the erasing gate 140 and the floating gate 120 face each other at the surfaces, there is a problem that a voltage applied between the erasing fate 140 and the floating gate 120 becomes small in the erasing operation because a coupling capacity is large. For this reason, there is a problem that the erasing operation at a high speed cannot be expected.
Techniques of JP-P2000-286348A and JP-P2001-085543A have a same problem. Specifically, in the technique of JP-P2000-286348A, since the erasing gate 240 and the floating gate 220 face each other at surfaces (a surface 240a and a surface 220a) as shown in FIG. 2, a coupling capacity is large. Similarly, in the technique of JP-P2001-085543A, since the erasing gate 340 and the floating gate 320 face each other at surfaces (a surface 340a and a surface 320a) as shown in FIG. 3, a coupling capacity is large. For this reason, there is a problem that the erasing operation at a high speed cannot be expected.

Split-gate nonvolatile semiconductor memory device


A multi-beam color scanning device is provided with a multi-beam light source unit, a first polygonal mirror that deflects the plurality of light beams emitted by the multi-beam light source unit to scan in a horizontal scanning direction. The scanning beams pass through an fθ optical system and are incident on a second polygonal mirror that deflects the light beams in a vertical scanning direction. The second polygonal mirror deflects the light beams by one line in the horizontal scanning direction at every horizontal scanning thereof. The light beams scan within a predetermined scanning area defined by deflection of the first and second polygonal mirrors. There is provided a light receiving unit that receives the plurality of light beams reflected by an object located within the predetermined scanning area. An operation system obtains a three-dimensional shape and color of the object based on the output of the light receiving unit.

The present invention relates to a multi-beam color scanning device which emits a plurality of beams to an object and obtains a three-dimensional color image in accordance with the beams reflected by the object.
Conventionally, the image scanning device as described above has been widely used. Examples of such an image scanning device are disclosed in Japanese Patent Provisional Publications No. HEI 01-105271 and No. HEI 06-98105. The conventional image scanning device of the above-described type typically includes a polygonal mirror for deflecting light beams in a predetermined direction (i.e., a main scanning direction), and at the same time, an object such as an image formed on a sheet is moved in a direction perpendicular to the main scanning direction.
Recently, an image scanning device for scanning a three-dimensional shape of an object has been desired. However, the conventional image scanning device is configured to capture an image formed on a sheet as a two-dimensional image, and an improved scanning device has been desired.


Lanolin-free lanolin substitute compositions comprising:                A) from about 5 to about 95% by weight, of at least one plant sterol fatty acid ester;        B) from about 1 to about 20% by weight, of at least one polyglyceryl di-polyhydroxy fatty acid ester;        C) from about 1 to about 20% by weight, of at least one polyglyceryl di-fatty acid ester;        D) from about 0.25 to about 10% by weight of at least one glyceryl fatty acid ester; and        E) optionally, from about 1 to 80% by weight of an additive containing a mixture of (i) a vegetable oil, (ii) a hydrogenated vegetable oil, and (iii) a non-petroleum derived wax.

Lanolin is a product obtained by the purification of degras. Degras is a crude grease obtained by the solvent treatment of wool.
Lanolin is a yellowish to gray semisolid containing 25 to 30% water in its hydrous form, and a brownish-yellow semisolid in its anhydrous form. Lanolin contains cholesterol esters of higher fatty acids.
Lanolin is used as a component of pharmaceuticals, leather finishing compositions, soaps and detergents, face creams, facial tissues, hair-set compositions, suntan preparations, and the like.


A PCI bus arbiter is provided as an additional PCI bus in PCI peer-to-peer bus bridge system. A bus control system having the PCI bus arbiter is also provided. The bus control system includes bus masters, a first PCI bus bridge, a second PCI bus bridge, an EISA/ISA bus bridge for changing structures of signals from the bus masters to be suitable for corresponding bus, a first arbiter in a main chip set, and a second arbiter for arbitration process. The second arbiter includes an edge detecting state machine which detects whether a PCI bus is accessed by a bus master, and produces a frame-signal which changes a logic state thereof according to an access condition of the PCI bus. The second arbiter may also include a priority resolve state machine which receives the frame-signal and produces priority values which determine an order of bus masters to use the PCI bus, wherein the priority values are changed according to the frame-signal. The second arbiter can include a hand shake state machine which produces and outputs grant-signals to grant authority to use the PCI bus to bus masters according to the priority value.

1. Field of the Invention
The present invention relates to a PCI bus control system. More particularly, the present invention relates to a PCI bus control system having a PCI bus arbiter.
2. Description of the Prior Art
When more than one bus master in a computer system simultaneously request to use a PCI bus, an arbiter selects a bus master and grants an authority to use the PCI bus to the selected bus master. Thus, the arbiter arranges the sequence to use the bus for the bus masters. Typically, in a main chip set of computer system used for the arbitration processes, a separate arbiter for each of the arbitration processes is not used in the art. On this matter, an exemplar of the contemporary practice is Heil et al. (U.S. Pat. No. 5,392,407, Multi-Port Processor With Peripheral Component Interconnect Port and RAMbus Port, Feb. 21, 1995) discussing a dual-port processor architecture with a first port interfacing to a PCI bus and a second port port interfacing to a RAMBUS channel. Pidgett et al. (U.S. Pat. No. 5,446,869, Configuration And RAM/ROM Control Of PCI Extension Card Residing On MCA Adapter Card, Aug. 29, 1995) discussing a method and apparatus for enabling configuration of a PCI daughter card resing on an MCA adapter card. A PCI/MCA bridge is provided for interfacing the MCA system bus with the PCI bus of the adapter card. Amini et al. (U.S. Pat. No. 5,450,551, System Direct Memory Access (DMA) Support Logic For PCI Based Computer System, Sep. 21, 1995) discussing computer system having a direct memory access (DMA) support mechanism. The computer system includes a central processing unit, a host bridge, an input/output bridge, and an arbitration logic circuit. Based on my study of these exemplars of the contemporary practice and the art, I believe that there is a need for an effective and improved PCI bus control system having a PCI bus arbiter.

PCI bus arbiter and a bus control system having the same


Methods of treating wafers for analyzing defects present therein comprise providing wafers having front side surfaces comprising defective portions and a back side surfaces opposite thereto; and decorating the defective portion of the front side of the wafer with copper.

With the increasing complexity of integrated circuit (e.g., semiconductor) devices, the quality of the wafers upon which the integrated circuits are positioned may be significant. Wafer quality is typically important in achieving desirable device yield and reliability.
Conventional wafer quality usually depends on a number of factors. For example, the quality is often influenced by the quantity of defects present in the wafer. Defects are typically generated during crystal growth. The wafer defects may generally be divided into two types: (1) defects arising from particle contamination and (2) crystal defects originating from silicon ingot growth.
During typical semiconductor wafering processes, single crystal silicon is usually formed by employing a multi-step process on a raw material such as quartzite, for example. The raw material may then be grown into a single crystal ingot by a suitable technique such as a Czochralski (CZ) method or a Float Zone (FZ) method.
An array of patterning and polishing processes are then typically carried out on the grown single crystal ingot. A wafer designed for use in an integrated circuit device is subsequently formed. In particular, the surface of the single crystal ingot is typically trimmed down in attempting to achieve proper size and morphology. After the ingot surface is examined, typically by an x-ray technique, the trimmed ingot may then be adjusted for orientation flattening along the lengthwise direction of the ingot. Typically, ingot etching is subsequently performed in order to potentially remove contaminants which may exist on the ingot surface. The ingot may then be sawed to form silicon slices or wafers. An edge-rounding technique can next be carried out on the edge of the silicon wafers, and a lapping technique may thereafter be performed on the wafer to minimize wafer bending. Contamination which may be present on the slice can be removed by employing a suitable chemical etching technique such as, slice etching, for example.
Next, the wafer is usually subjected to a thermal processing technique known as "donor killing". The "donor killing" process is designed to prevent interstitial oxygen from serving as a donor subsequent to ingot growth. The process is intended to minimize any complications with respect to wafer electrical control that may result in an integrated circuit device.
After the donor killing process, the surface of the wafer is typically polished and cleaned by chemical or mechanical means. Defects or orientations which may be present in the wafer can then be examined. The wafer is then typically subjected to an inspection and, if acceptable, the wafer is packaged for commercial use.
A conventional cleaning process, however, may be limited in the types of contaminants and impurities that it can remove. More particularly, although contaminants such as dust may be removed, potential faults in the wafer like D-defects, oxygen precipitates, stacking faults, and metallic precipitates may not be addressed by the above cleaning process.
Potentially troublesome defects include, for example, COPs ("Crystal Oriented Particles") known as micropits, along with D-defects. As known in the art, "D-defects are defined as deformation defects, namely defects that propagate three-dimensionally so as to disrupt the crystal lattice structure. These defects often adversely affect the yield and reliability of integrated circuit devices, since the defects can impact manufacturing processes involved in producing the devices. Thus, it is typically important to examine the density and deflection distribution of the wafer surface, along with the morphology of the surface. Based on these analyses, adjustments may be made which can allow for increases in device yield prior to a device being used in a wafer.
A conventional method for examining potential wafer surface defects involves laser scattering particle counter (LSPC) technology. In the above method, a bare wafer is typically cleaned with, for example, a solution of SC1 (i.e., ammonium hydroxide, hydrogen peroxide, and water having a molar ratio of 1:1:8 respectively), along with hydrogen fluoride. Subsequently, a constant wavelength laser is typically irradiated on the bare wafer by a laser scattering particle counter. Scattered signal data is then typically generated. As a result, the surface defects of the wafer may be examined.
There are potential problems associated with the above method. First, it is often difficult to accurately measure the amount and distribution of COPs on a wafer. More particularly, COPs are typically found only on the vacancy-rich area of the wafer. As a result, it is often necessary to measure the real diameter of the vacancy-rich area from a COP map acquired by a laser scattering particle counter. When a bare wafer is cleaned with a SC1/hydrogen fluoride solution, however, it may be difficult to distinguish real contamination from the COPs. Moreover, particles often accumulate on defects during COP mapping, and the presence of the particles may distort the level of defects measured from the wafer. Second, it may be difficult to fully detect the defects due to limitations in the conventional scattering particle counters. A conventional scattering particle counter usually has a detection limit of 0.12 .mu.m, and as a result COPs of smaller size may not be observed. Since smaller defects are often found in the peripheral regions of vacancy-rich areas in the wafer, it may be extremely difficult to accurately measure the diameter of the vacancy-rich area. Third, a conventional scattering particle counter technique is often unable to accurately access the size and morphology of wafer defects and, as a result, their position on the wafer surface. Conventionally, defect position is usually observed via the coordination between a LSPC technique and an AFM (atomic force microscope) technique. Nonetheless, the size and defects determined by using an AFM technique may be larger than the size and defects measured by the LSPC technique. Thus, the size, morphology, and location of the defects may not be accurately determined.
There remains a need in the art to address the potential difficulties associated with conventional methods of analyzing wafer defects.

Methods of treating crystal-grown wafers for surface defect analysis


A transmission for an at least partially electrically driven vehicle includes two electric machines which are rotationally driveable in a first direction and in a second direction. The transmission further includes an output shaft at least indirectly operatively connected to the first and second electric machines, a first freewheel clutch that at least indirectly transmits a drive power of the first electric machine to the output shaft with a first ratio when the first electric machine rotates in the first direction, and a second freewheel clutch that at least indirectly transmits the drive power of the first electric machine to the output shaft with a second ratio when the first electric machine rotates in the second direction. Additionally, the transmission includes at least one first gear stage in power flow between the first or second freewheel clutch and the output shaft to rotate the output shaft in a third direction.

DE 10 2015 002 405 A1 describes a vehicle having at least two electric motors and a control device, wherein the electric motors drive at least one shaft. The control device distributes a power to be provided at the at least one shaft onto the at least two electric motors as a function of the power to be provided. The particular electric motor is connected, for example, to a transmission, wherein the electric motors and the transmission are combined to form a drive train.

Transmission and drive device for an at least partially electrically driven vehicle