An improved process for manufacturing cobalt silicide layers uses two capping layers. A first capping layer of titanium nitride prevents the formation of a cobalt/titanium intermetallic. A subsequently formed titanium metallic layer getters impurities from outgassing and the ambient preventing corruption of the cobalt layer. Two rapid thermal annealing steps convert the cobalt at the cobalt/silicon intermetallic into highly conductive cobalt disilicide. The cobalt silicide does not suffer from linewidth dependent increases in resistivity. Therefore, the cobalt disilicide formed by the present method is useful for semiconductor devices with linewidths and feature sizes less than 0.20 .mu.m. The process has wide applicability and may be used to fabricate local circuit interconnects, floating gates, double polysilicon stacked floating gates as well as other uses.

1. Field of the Invention
This invention relates to the field of self-aligned silicide semiconductor structures, and more specifically, to a process designed to form cobalt disilicide (CoSi.sub.2) layers for use in salicide technology.
2. Background & Related Art
In the manufacture of semiconductor devices, silicides, materials formed by the reaction of refractory metals, or near nobel metals, with silicon, are used in a variety of applications. For the past decade titanium silicide (TiSi.sub.2), has been the workhorse of the semiconductor industry due to its low contact resistance, low sheet resistance, and well-understood properties. However, as feature sizes and linewidths decrease below the 0.20 .mu.m level, the drawbacks and shortcomings of TiSi.sub.2, are becoming apparent and more critical. Thus, the effectiveness of TiSi.sub.2 is coming to an end. In the search for an effective replacement numerous alternative materials have been experimented with. One promising replacement material is cobalt disilicide (CoSi.sub.2).
One key use of silicides is in the so-called salicide process. Salicide processing is the manufacture of "self-aligned" silicide gate structures. A typical presently used process is shown in FIGS. 1A-1D. FIG. 1A begins with a self-aligned MOS transistor already formed on a silicon substrate. Such a device features a gate structure, 103, formed on an active semiconductor surface region, 101, lying between field oxide regions, 102, of a semiconductor surface. The gate, 103, lies between spacers, 104, and source and drain regions, 105. The gate, 103, typically features an electrode formed from polysilicon. As shown in FIG. 1B, a silicide structures are typically formed by sputtering titanium (Ti), 106, over the entire semiconductor surface in a physical vapor deposition ("PVD") process. The resulting structure is then heated in a first rapid thermal anneal ("RTA1") process. As shown in FIG. 1C, this causes the titanium to react with the polysilicon in gate region, 103g, and also with the silicon of the source and drain regions, 105d. However, titanium deposited in the spacer and field oxide regions, u, does not react to form silicide. Moreover, the reaction between titanium and silicon in the source, 105d, drain, 105d, and gate, 103g, regions is "incomplete". The unreacted titanium, u, is selectively etched from the surface leaving only the "incompletely" reacted titanium silicide in regions, 103g and 105d. The "incompletely" reacted titanium silicide (TiSi.sub.2) has a crystallographic structure, known as C49. C49 TiSi.sub.2 is an unsatisfactory end product which has high sheet resistance. Titanium silicide requires further processing to obtain the necessary sheet resistance. A second RTA ("RTA2") is performed causing TiSi.sub.2 to change phase, forming a low resistance TiSi.sub.2, known as C54. C54 TiSi.sub.2 has a much lower sheet resistance than C49 and is used as an effective gate contact material.
C54 TiSi.sub.2 has many excellent properties, low junction leakage, low sheet resistance, low contact resistance, etc. However, it has been discovered as feature size and linewidth decrease, titanium silicide becomes a less than satisfactory silicide material. It has been observed that titanium silicide suffers from a linewidth dependent increase in sheet resistance. FIG. 2 shows the relationship between linewidth and sheet resistance of TiSi.sub.2 and CoSi.sub.2. As shown in FIG. 2, as linewidth decreases, the sheet resistance of titanium silicide increases. FIG. 2 shows that as TiSi.sub.2 linewidth decreases below 0.17 .mu.m, the sheet resistance of TiSi.sub.2 radically increases making it a wholly unsuitable material for the newer generation of microprocessors and memory chips.
Various attempts have been made to extend the life of TiSi.sub.2 as a useful process material. This has led to some useful improvements, but due to TiSi.sub.2 's grain structure, these improvements appear to be at an end. The chief limitation on TiSi.sub.2 is the number of nucleation sites. As linewidth decreases, the number of C54 nucleation sites also decreases leading to difficulties in forming low resistance C54 phase titanium silicide. This key factor has been very difficult to overcome in the present art.
Cobalt has been heralded as a promising possible successor material for titanium. The reason for this is shown in FIG. 2. CoSi.sub.2 does not suffer from the linewidth dependent sheet resistance problem. However, CoSi.sub.2 is not without its own unique problems. Unlike titanium, cobalt requires that the silicon deposition surfaces be cleaned (i.e., the native oxide layer etched off) prior to cobalt deposition. Furthermore, cobalt's suffers from extreme sensitivity to incorporation of surface and ambient contaminants during rapid thermal annealing (RTA) which makes a capping layer a virtual necessity. A process flow which addresses some of these problems is set forth in U.S. Pat. No. 5,047,367 by Wei, et al.
The invention of Wei describes a process for forming a titanium nitride/cobalt silicide bilayer for use in salicide technology and as contact via fills. Titanium is deposited on a silicon substrate then coated with a thin layer of Co. These layers are annealed in a nitrogen atmosphere. During anneal, cobalt migrates into the silicon substrate and titanium migrates upwards towards the surface. The surface titanium reacts with the atmosphere to form titanium nitride which protects the underlying cobalt layer. The cobalt then reacts with the silicon layer to form cobalt silicide. This method has the advantage of being a simple process which does not require the removal of the native SiO.sub.2 layer from the Si wafer surface. Additionally, the Ti layer getters the atmospheric and surface impurities from the Co layer preventing its contamination during processing. However, this process suffers from undesirable formation of a CoTi.sub.2 intermediate at the Ti/Co interface which inhibits CoSi.sub.2 formation.
Another present art process for fabricating a CoSi.sub.2 layer, involves the deposition of a titanium nitride (TiN) capping layer over a cobalt layer. This process begins with a silicon substrate having field oxide regions and spacers in place. The Si surface is stripped of its native oxide, then a layer of Co is formed over the surface. Subsequently, a capping layer of TiN is formed over the metallic cobalt. The substrate is then subject to rapid thermal annealing. This process avoids the formation of CoTi.sub.2 by using the TiN cap, which avoids the Ti/Co reaction during processing. However, this process suffers from incomplete reaction of the Co with Si. This incompleteness is more pronounced at narrow linewidths (e.g. less than 0.30 .mu.m) and at intermediate temperatures (e.g. temperatures in the range of 500-600 .degree. C.). The process also suffers from the effects of oxide outgassing which inhibits silicide formation by slowing Co diffusion.
Another method of forming CoSi.sub.2, is the direct formation of a Ti capping layer over the Co layer. Such a process is shown in U.S. Patent No. 5,780,362 by Wang and Maex. The Co layer is formed directly on the semiconductor substrate without stripping the native oxide. Subsequently, a Ti capping layer is formed over the Co layer. Since Ti is an excellent gettering material, the Ti capping layer removes impurities. The Ti layer removes impurities from the RTA ambient, as well as the SiO.sub.2 native oxide layer. This allows Co to react freely with the Si substrate. Unfortunately, this method has the same drawbacks as other methods where metallic Ti directly contacts Co, namely, Ti reacts with Co to form CoTi.sub.2. This consumes Co and hinders the formation of CoSi.sub.2.
What is needed is a method that eliminates the collective drawbacks of the existing techniques and allows the effective formation of a CoSi.sub.2 layer. The object of the present invention is to provide an efficient process for forming a CoSi, layer which does not incorporate impurities from the ambient or from surface outgassing. A further object of the present invention is to avoid the formation of undesirable intermediates, such as CoTi.sub.2, during processing. A further object of the present invention is to avoid process reactions which induce undue stresses in the substrate causing voiding of spacers.

Manufacturing capping layer for the fabrication of cobalt salicide structures


A music processing system that processes music events includes a performance supervisor and a graph object. The graph object defines an ordered graph of music event processors, through which music events are routed. The graph object has a graph interface with methods allowing an application to insert and remove event processors in the graph. In addition, the graph interface has a method that can be called to update a music event data structure that represents the music event. This updating consists up supplying an identification of a music event processor that is next to receive the music event. Each event processor has a processor interface, which includes an initialization method and a process event method for performing the actual processing of a music event. Each processor supports one of a plurality of delivery timing modes, and also supports a subset of available event types. When inserting a music event processor in a graph, an application program can specify which instrument channel the event processor is to act upon.

Musical performances have become a key component of electronic and multimedia products such as stand-alone video games, computer-based video games, computer-based slide show presentations, computer animation, and other similar products and applications. As a result, music generating devices and music playback devices are now tightly integrated into electronic and multimedia components.
In the past, musical accompaniment for multimedia products was provided in the form of digitized audio streams. While this format allowed recording and accurate reproduction of non-synthesized sounds, it consumed a substantial amount of memory. As a result, the variety of music that could be provided using this approach was limited. Another disadvantage of this approach was that the stored music could not be easily varied. For example, it was generally not possible to change a particular musical part, such as a bass part, without re-recording the entire musical stream.
More recently, it has become quite common to represent music as a stream of discrete music "events." As an example, a particular musical note might be represented as a "note event." The note event is represented by some type of data structure that includes information about the note such as pitch, duration, volume, and timing. Many such music events correspond to actions that might be performed by a keyboardist, such as pressing or releasing a key, pressing or releasing a sustain pedal, activating a pitch bend wheel, changing a volume level, changing a preset, etc.
Music events such as these are typically stored in a sequence that roughly corresponds to the order in which the events occur. Rendering software retrieves each music event and examines it for relevant information such as timing information and information relating the particular device or "instrument" to which the music event applies. The rendering software then sends the music event to the appropriate device at the proper time, where it is rendered.
A computer rendering device can have numeral logical devices or instruments, each of which plays notes having different sounds. For example, one instrument might sound like a trumpet, while another sounds like a violin. Each instrument is assigned a channel, and each music event is similarly designated with channel information. Using such channel designations, an author can designate the instrument or instruments which are to receive any particular music event.
As multimedia software has become more complex, software designers have added corresponding complexity to the rendering of event-based music. Today, software developers need the ability to change music parameters as the music is being rendered, in response to various context changes initiated by a user. For example, it might be desired to immediately change the key of a musical performance in response to a user taking a certain action in a game. Alternatively, it might be desired to change some component of the music, perhaps by adding a drum beat or adding sound effects.
To provide flexibility in implementing such features, authoring programs allow developers to develop discrete event processors, sometimes referred to as "tools," that perform simple actions with respect to a music event. Music events are passed through the event processors, in a defined sequence, in order to produce desired effects. Event processors might be used to change the key of a music performance, or to perform more complex tasks such as creating an "echo" effect. Generally, each event processor accepts a music event, either modifies the music event or takes some further action in response to the particular characteristics of the music event, and then sends the music event on to the next event processor.
Although the concept of event processors such as this is very useful, the process of organizing and managing such event processors can be awkward, particularly when application programs are used to install and organize event processors during multimedia presentations. Thus, there is a need for a straightforward and efficient architecture for organizing music event processors and for passing music events between such event processors. The invention described below meets this need.

System and method for arranging and invoking music event processors


A non-volatile semiconductor memory device with a small variation in capacitance-coupling to the stacked gate for memory miniaturization. The device has a memory cell array in which memory cells are arranged in array. Each cell has a first gate and a second gate on a semiconductor substrate. The first gate is formed, via a first gate insulating film, on each of device forming regions isolated by device-isolating insulating films. The second gate is formed on the first gate via a second gate insulating film. The first gate is patterned so that its portion is overlapped on the isolation insulating film from the device forming region. A protective insulating film is provided on the isolation film between the device forming regions and in the vicinity of the first gate. A charge-storage layer of each memory cell has at least two stacked conductive layers with a small isolation width at a low aspect ratio for burying isolation insulating films for high density, to easily fabricate in low cost. The side face of the lowest conductive layer meets the side portion of the isolation region. The highest conductive layer has the same width as or is wider than the lowest conductive layer. The first conductive layer is thin for decrease in aspect ratio for burying the insulating film. The second conductive layer has a specific thickness for attaining a desired capacitance between it and the control gate. The highest layer may be formed in self-alignment with the isolation region and stretched out by isotropic-etching.

The present invention relates to a non-volatile semiconductor memory device having memory cells based on a stacked gate structure, and to a manufacturing method thereof.
What has hitherto been known as anon-volatile semiconductor memory (EEPROM (Electrically Erasable Programmable Read-Only Memory)) capable of electrically reprogramming data, is a flash memory using memory cells taking a MOS transistor structure based on a stacked structure of a charge-storage layer and a control gate.
FIG. 1 is a plan view showing a NOR type EEPROM using those memory cells. FIGS. 2A and 2B are sectional views taken along the lines A–A′ and B–B′, respectively, in FIG. 1.
Isolation insulating films 102 are buried into a memory cell array area on a silicon substrate 101, thereby defining device forming regions 103 continuous in a y-direction at a predetermined interval in an x-direction. Charge-storage layers 105 are provided via tunnel insulating films 104 on the substrate with the device being thus isolated, and a control gate 108 is provided via a gate-to-gate insulating film 107 on the charge-storage layers 105, thus configuring a memory cell. The charge-storage layer 105 is isolated by the isolation insulating film 102 and thus gets independent for every memory cell. The control gate 108 is continuously provided in the x-direction and serves as a word line common to a plurality of memory cells. The control gate 108 and the charge-storage layers 105 are formed in pattern in self-alignment manner so that the side ends thereof are aligned in the y-direction. Then, the control gate 108 is provided with an n-type diffused layer 6 in self-alignment. The memory cell is covered with an inter-layer insulating film 109, and bit lines 110 extending in the y-direction are arranged on the layer 109.
An execution of a data reprogramming process of the EEPROM involves applying a high electric field to between the substrate and the charge-storage layer, to allow a tunnel current to flow through between the charge-storage layer and the substrate, thus modulating a stored charge quantity of the charge-storage layer. A threshold level of the memory cell becomes higher with a larger quantity of negative charge existing within the charge-storage layer, whereas lower with a larger quantity of positive charge existing therein. Accordingly, electron injection into the charge-storage layer raises the threshold level (which may be, e.g., a programming state). On the contrary, pulling out of the electrons from the charge-storage layer lowers the threshold level (which may be, e.g., a data erasing state).
The most important parameter for the data reprogramming of the memory cell described above is a ratio C1/C2 of a capacitance C1 between the charge-storage layer 105 and the substrate 101 to a capacitance C2 between the control gate 108 and the charge-storage layer 105. With the substrate set at an electric potential of 0, when a voltage Vcg is applied to the control gate 108, a voltage Vfg of the charge-storage layer 105 is given such as Vfg=C2·Vcg/(C1+C2). Accordingly, a voltage applied to the tunnel insulating film 104 is determined by a coupling ratio K=C2/(C1+C2)=1/{1+(C1/C2)}.
A generation of a tunnel current requires applying an electric field as high as several tens of MV/cm to the tunnel insulating film. It is required for attaining this that the high voltage Vfg on the order of 10V be applied to between the charge-storage layer and the substrate. The charge-storage layer is coupled to the control gate by capacitance-coupling; hence a high voltage of approximately 20V is needed as the voltage Vcg=K·Vfg to be applied to the control gates. Even when the same voltage is applied to the control gates, if the coupling ratio K is different, the voltage applied to the tunnel insulating film becomes different, to attain different threshold levels for the memory cell. This causes an expansion of a threshold value distribution in the programming state of the memory cell. It is therefore of importance to uniformize the coupling ratio K.
FIG. 3 shows dimensions of the respective elements of the conventional memory cell structure. A capacitance ratio C2/C1 is obtained by using these dimensions in the following formula:C2/C1={Wa+2(d+Tsti++Wing)}Tox/Wa·TonoWing=(Wsti−SL)/2
The capacitance C2 is determined by a face-to-face area between the charge-storage layer 105 and the control gate 108. Hence, variation in the capacitance C2 is caused by variation in thickness of the charge-storage layer and variation in a length Wing (which is so-called a Wing length) of an overhang into the isolation region of the charge-storage layer 105.
Further, there is a high possibility in which the thickness of the charge-storage layer 105 is not uniform as shown in FIG. 3 when the device forming area and the isolation region have different heights. The non-uniformity of the thickness of the charge-storage layer leads to variation in an effective surface areal size of the charge-storage layer. This is also a factor for causing variation in the capacitance C2.
The wing length Wing is determined by an isolation width Wsti and a cut width (a so-called slit width) SL of the charge-storage layer. Cell miniaturization in order to increase the capacity of the EEPROM and decrease the cost thereof, often results in the dimensions of the isolation width Wsti and the slit width SL becoming the minimum width among those decided when the memory cells have been manufactured. In the memory cell described previously, the slit width SL of the charge-storage layer 105 is smaller than the isolation width Wsti and is therefore the minimum dimension. The isolation width in combination with the device forming area, however, determines a pitch of the bit lines, and it is therefore desired that the isolation width Wsti be set small to the greatest possible degree in order to shrink the memory cell array area.
A method utilizing the side-wall remaining technique has already been proposed by the present inventors (K. Shimizu et al. '97IEDM) for achieving a small slit width falling within the range of the small isolation width and smaller than this isolation width. According to this method, the masking material for slit processing is formed in pattern on the charge-storage layer, and thereafter an additional masking material is deposited with the side wall remaining, thereby obtaining a small slit width. FIGS. 4A to 4E show the memory cell manufacturing process described above.
As shown in FIG. 4A, gate material layers 105a are deposited on a silicon substrate 101 through a gate insulating film 104, and masking materials 201 are provided on the layers 105a, thus making a pattern formation so that the gate material layers 105a are left on the device forming area. Then, as illustrated in FIG. 4B, isolation trenches are formed by etching the substrate 101 by use of the masking materials 201, and the isolation insulating films 102 are embedded into these trenches. Subsequently, as shown in FIG. 4C, the gate material layers 105a are deposited again, and masking materials 202 for slit processing are formed in pattern on the isolation insulating films 102.
Further, as shown in FIG. 4D, masking materials 203 are deposited thin and left on only side walls of the masking materials 202 by an isotropic dry etching. A slit-processing window smaller than the minimum processing dimension is thereby formed. Then, gate material layers 105 bare etched by using the masking materials 202 and 203, where by the charge-storage layer 105 taking the stacked structure of the gate material layers 105a and 105b is isolated by the isolation insulating films 102 and thus formed in pattern. Thereafter, as shown in FIG. 4E, a control gate 108 is provided via the inter-gate insulating film 107. The control gate 108 is, as described above, subjected to the isolation processing in the bit-line direction together with the charge-storage layer 105.
According to the method described above, however, after executing the slit processing to isolate the charge-storage layer by etching the gate material layers 105b in the process in FIG. 4D, the surfaces of the isolation insulating films 102 are etched in the process of removing the masking materials 202 and 203 by etching, and, as shown in FIG. 4E, narrow trenches 204 are formed in slit separating portions of the charge-storage layer 105. The trenches 204 formed in the surfaces of the isolation insulating films 102 continuously extend in the bit-line direction the y-direction in FIG. 1) as well as being formed in the section in FIG. 4E wherein the control gate 108 is provided. This trench 204 is extremely narrow, and therefore, deposition of the materials of the inter-gate insulating film 107 and of the control gate 108 to fill these trenches 204, produces etching residues along the trenches 204 in the patterning process thereof. This might cause a gate short-circuit accident. Further, the thickness of the isolation insulating film 102 just under the control gate 108 decreases, and hence, a thin isolation insulating film 102 lowers an isolation function.
As discussed above, in the EEPROM including the memory cells based on the stacked structure of the charge-storage layer and the control gate, with the hyperfine structure of the device, there exists a problem in which a data reprogramming performance declines due to variation in capacitance-coupling that is caused by the ununiformity of the thickness of the charge-storage layer and by variation in descent width of the slit for separating the charge-storage layer. Another problem is that when executing the processing of the slit narrower than the isolation width on the isolation insulating film for separating the charge-storage layers, a layer reduction of the isolation insulating film occurs, and an gate-to-gate short-circuit accident is caused due to deterioration of the isolation performance and the gate residues as well.
Discussed next are well-known structures of several types of memory cells and their disadvantages.
FIGS. 5A and 5B show a first well-known example of memory cell having a STI (Shallow Trench Isolation) structure. FIG. 5A is a plan view, and FIG. 5B is a sectional view taken along the line A–A′ in FIG. 5A.
As shown, isolation trenches 302 are formed in a p-type silicon substrate or p-well 301. Each trench 302 is filled with an isolation material, such as, silicon dioxide. Formed on the entire surface of an element region (channel region) 308 on the substrate that has been subjected to isolation is a thin tunnel-insulating film 4 through which a tunnel current will flow, and a charge-storage layer 5 thereon. Moreover, a control gate 307 is formed on the charge-storage layer 305 via a gate-to-gate insulating film 306. It is shown in FIG. 5B that bottom portions 305a of the charge-storage layer 305 protrude downwardly along the isolation trenches 2.
FIGS. 6A to 6D are sectional views each illustrating a step of manufacturing the STI-cell structure shown in FIGS. 5A and 5B.
As illustrated in FIG. 6A, a dummy insulating film 310 is formed on the semiconductor substrate 301, and a masking material 311, such as, photoresist, is deposited on the insulating film 310. The masking material 311, dummy insulating film 310 and substrate 301 in the isolation region are etched by photolithography so that their side walls are flush with each other to form the trenches 2.
The surface of the trench-side wall is oxidized by thermal oxidation with appropriate requirements. The thermal oxidation results in a "bird's beak" structure formed at each dummy insulating film 310, with the masking material 311 as a mask against the oxidation. The "bird's beak" structure is thicker than an oxide film formed at each trench side wall, thus resulting in a round edge at each trench.
An isolation insulating film is deposited on the entire surface of the semiconductor substrate to fill the trenches 320 with an isolation insulating film 3. The upper surface of the insulating film 303 is polished, or etched back by dry etching or polished by chemical-mechanical polishing (CMP), thus the upper surface of the masking material 311 being exposed (FIG. 6B).
The masking material 311 and the dummy insulating film 310 are peeled off by dry etching or wet etching with chemicals, and a tunnel insulating film 304 and a charge-storage layer 305 are deposited thereon (FIG. 6C).
The charge-storage layer 305 is patterned into slits by lithography on the isolation region, and the gate-to-gate insulating film 306 and the control gate 307 are deposited thereon with gate formation by pattering to finish fabrication of the cell structure (FIG. 6D).
Discussed next with a memory cell operation is the reason for the bottom portions 305a of the charge-storage layer 305 protruding downwardly along the isolation trenches 302.
Data programming to a memory cell having such a tunnel oxide film is performed by modulation of charges stored in the charge-storage layer 5 by charge transfer between the layer 305 and the substrate 301. At least either charge-injection or charge-discharging is performed with FN (Fowler-Nordheim) tunneling. In detail, a high electric filed at 10 MV/cm or more is applied to between the charge-storage layer 305 and the substrate 301 to discharge electrons from the former to the latter or from the latter to the former. The electron discharging will not change the charges stored in the charge-storage layer 305 unless there is no data reprogramming because it is in a complete floating state.
High-voltage application to the charge-storage layer 305 requires voltage application to the control gate 307 for capacitance-coupling therebetween. A high voltage to the control gate, however, forces several transistors that constitute a voltage regulator for generating such a high voltage, input/output switching circuitry, and so on, to have high withstand voltages, thus resulting in a large element region.
A voltage Vfg to be applied to the tunnel insulating film 304 is given by the following expression:Vfg=C2/(C1+C2)Vcgwhere C1 and C2 represent the capacitance between the charge-storage layer 305 and the semiconductor substrate 301 via the tunnel insulating film 304 and that between the charge-storage layer 305 and the control gate 307 via the gate-to-gate insulating film 306, respectively; and Vcg represents a control gate voltage.
As is apparent from the expression that a higher capacitance C2, that is, the capacitance between the charge-storage layer 305 and the control gate 307 via the gate-to-gate insulating film 306, is efficient to lower the voltage to be applied to the control gate 307. A high capacitance C2 can be attained with a large area for the control gate 307 and charge-storage layer 305 facing each other, which is achieved by forming the layer 305 as protruding from the element region to the isolation region as already discussed.
The second well-known memory cell structure described above, however, has two major drawbacks.
The first drawback lies in difficulty attaining a miniaturized width for isolation. Cutting the charge-storage layer 305 into slits on the isolation region requires microfabrication for the slits narrower than widths of the element region and isolation region. Lithography is generally used for slit formation. However, slit formation on the isolation region requires a pattern arrangement such that slit patterns will not overlap the isolation region located thereunder even though the slit patterns displace due to lithography. This results in a wide isolation width even slit patterns are formed as narrower than the isolation width. It is concluded that the well-known memory cell structure fabricated with slit formation using lithography for charge-storage layers has difficulty in miniaturization of isolation region.
The second drawback lies in difficulty attaining a miniaturized width for device areas. The well-known memory cell structure could have an exposed trench side wall during wat etching for peeling off the dummy isolation film. Such an exposed trench side wall produces a parasitic MOS capacitance between the side wall and the charge-storage layer via the tunnel isolation film as already discussed. The smaller the rounded trench side wall end, the worse the cut-off characteristics for the memory cell transistors due to generation of the kink characteristics in the sub-threshold range. Moreover, data-programming by FN-tunneling electron injection with a high voltage to the control gate generates gate electric field mostly on the parasitic MOS capacitance, thus causing dielectric breakdown to the tunnel isolation film.
A further rounded trench side wall can protect the tunnel isolation film from dielectric breakdown. A trench sidewall with excess oxidation for rounding, however, forms a bird's beak at the side wall as discussed above, thus producing an element region width extremely narrower compared when the trench is formed. This requires patterns wide enough for canceling width reduction due to oxidation for rounding of the trench side wall. Moreover, the larger the bird's beak, the more the variation in size thereof, thus causing difficulty in control of miniaturized device size.
As discussed above, the second well-known STI memory cell structure has drawbacks on miniaturization of the isolation width and element region width.
FIGS. 7A and 7B illustrate the second well-known STI structure introduced in the Japanese Un-examined Patent Publication 10-017948 as one example of a STI structure for solving the problems discussed above. FIG. 7A is a plan view and FIG. 7B is a sectional view taken along the line B–B′.
As shown, isolation trenches 2 are formed in a p-type silicon substrate or p-well 301. Each trench 302 is filled with an isolation insulating material 303, such as, silicon dioxide. Formed on the entire surface of the channel region on the substrate that has been subjected to isolation is a thin tunnel-insulating film 304 through which a tunnel current will flow. Formed on the tunnel-insulating film 304 is a charge-storage layer 312, the side wall thereof meeting the end of the isolation region. The isolation insulating film 303 touches the charge-storage layer 312. A portion of the side wall of the charge-storage layer 312 is exposed and faces a control gate 314 via a gate-to-gate insulating film 313 to increase capacity between the charge-storage layer 312 and the control gate 314. The charge-storage layer 312 and the control gate 314 are formed by self-alignment in the vertical direction so that their side walls are flush with each other. An n-type diffused layer 309 is formed between the gates.
FIGS. 8A to 8D are sectional views each illustrating a step of manufacturing the STI-cell structure shown in FIGS. 7A and 7B.
A conductive material 312 that will become a charge-storage layer and a masking material 315 are deposited over the semiconductor substrate 301 via the tunnel-insulating film 304. The masking material 315, the conductive material 312, the tunnel-insulating film 304 and the semiconductor substrate 301 in the isolation region are etched so that their side walls are flush with each other to form trenches 302 (FIG. 8A).
The surface of the trench-side wall is oxidized by thermal oxidation with appropriate requirements before deposition of the isolation insulating film 303. The upper surface of the insulating film 303 is polished, or etched back by dry etching or polished by chemical-mechanical polishing (CMP), thus the upper surface of the masking material 315 being exposed (FIG. 8B).
The isolation insulating film 303 is further etched back to expose a side-wall portion of the charge-storage layer 312, followed by peeling-off the masking material 315 (FIG. 8C).
The gate-to-gate insulating film 313 and the control gate 314 are deposited thereon with gate formation by pattering to finish fabrication of the cell structure (FIG. 8D).
The third well-known STI-cell structure requires no dummy isolation film like the first well-known STI-cell structure. This is because, in the second well-known STI-cell structure, the tunnel-insulating film and the charge-storage layer are deposited before formation of the trenches with the isolation insulating film filled therein. The second well-known structure has no exposed trench-side wall, thus suitable for miniaturization of element region width.
Moreover, this STI-cell structure requires no formation of the charge-isolation layer into slits on the isolation region because it is completely isolated thereon, thus achieving miniaturization of isolation region width in this respect.
On the other hand, the second well-known STI-cell structure has difficulty in miniaturization of isolation region width with respect to a high aspect of trenches filled with the isolation insulating film. As described, the first well-known STI-cell structure has a large area of the charge-storage layer that faces the control gate with a portion of the charge-storage layer protruding along the isolation insulating film. Contrary to this, the second well-known structure attains a large area of the charge-storage layer with its side-wall portion facing the control gate, thus requiring a charge-storage layer thick enough for facing the control gate.
Suppose that an aspect ratio is 2 for an isolation insulating film with no voids when buried into a 0.3 μm-deep trench with a 0.15 μm-thick charge-storage layer. Under the requirements, a 0.275 μm-wide isolation width is offered for burying an insulating film via 0.1 μm-thick masking material; whereas the first well-known STI-cell structure offers 0.2 μm-wide isolation width at a low aspect because of not so narrow charge-storage layer when embedding an insulating film. The second well-known STI-cell structure has restriction of isolation width due to embedding an isolation insulating film, not to slit formation to the charge-storage layer.
As discussed above, a non-volatile semiconductor memory device with the well-known STI-cell structure has difficulty in miniaturization of element region width and isolation width, thus causing restriction of miniaturization of memory cells.

Non-volatile semiconductor memory device and manufacturing method thereof


An apparatus is provided for controlling a joint force of a friction-joint component placed in a torque transmitting mechanism (e.g., transmission) mounted on a vehicle. The friction-joint component is connected to a drive source. The apparatus comprises a guideline producing unit, joint force controlling unit, and drive force controlling unit. The guideline producing unit produces a first target operation guideline for the torque transmitting mechanism and a second target operation guideline for the drive source. The first target operation guideline includes a transmitted torque capacity of the torque transmitting mechanism. The joint force controlling unit controls the joint force based on the first target operation guideline. The controlling unit includes a unit setting a value to the joint force depending on the information regulating the transmitted torque capacity. The drive force controlling unit controls a drive force of the drive source based on the second target operation guideline.

1. The field of the Invention
The present invention relates to a method and apparatus for controlling a drive force of a vehicle, and in particular, to the method and apparatus for controlling a drive force in an vehicle's apparatus in which a running torque (i.e., the drive force) is transmitted from a drive source to a drive shaft via a torque transmission mechanism with a friction-jointed component.
2. Related Art
A conventional integration control system for a vehicle has been proposed, for example, by a United States Patent publication No. U.S. Pat. No. 6,292,741 B1. In this motor vehicle control system, a control system is divided into, at least, a body and compartment, vehicle movement, vehicle electric system, and driving apparatus, and then the driving apparatus is further divided into, at a minimum, a transmission, converter, and engine. Hence the entire control system is gradually divided into smaller systems, so that the entire control system is configured on a hierarchical structure. This hierarchical structure prevents not merely the vehicle control system from being complicated but also man hours necessary for developing the vehicle control system from being increased.
In cases where the entire vehicle system is hierarchised in its integration control, some of conventional different controls are treated at the same hierarchical level because those controls require the same actuator, even though the functional levels of those controls are different from each other. For instance, those controls include a cruise control, which has a function performed at a vehicle level and associates with plural types of controls, and an idling speed control, which has a function performed at an individual level and associates with only a closed control of the engine. Thus, since both the cruise control and the idling speed control are in common with each other in directly controlling an opening of a throttle valve, and those two types of controls are treated at the same level from a viewpoint of only an actuator, i.e., the throttle valve to be operated for achieving the controls. The processing required for the control has been made complicated.
To be specific, a confliction of the controls performed by the same actuator should be avoided. Because controlled variables and other variables for individual control functions are assigned to an actuator, it is necessary to have an additional control to decide which control has priority over the other controls or to give a compromise to those controls. If the actuator has no function for the priority or compromise control, there is a possibility that a conflict will occur among the controls and crews feel something is strange.
In contrast, in performing the vehicle integration control, each function for the integral control is processed as follows. A function at the vehicle level is subjected to control processing for managing the entire vehicle, resulting in that the function is translated into a function at an individual system level. The function at the individual system level is then subjected to control processing at an individual system, resulting in that the function is translated into a function at an actuator level. This results in that, for instance, the foregoing cruise control is executed as control processing at the vehicle level and the idling speed control is executed as control processing at the individual level. In those controls, the upper control processing is designed to perform the foregoing priority control or compromise (matching) control, so that the processing is avoided from being complicated and is executed based on an organized control structure.
The above integration control is not limited to the control of the throttle valve, but is applied to other various types of control, such as control of ignition timing at the engine and control of a regulator of the transmission.
However, when each set of control processing is properly arranged in the vehicle integration control, an inconvenience will occur as follows. It is sufficient for the conventional control that all the processing is carried out to calculate to an amount to be operated of an actuator for operating each function itself. However, it should be required that the integration control calculate, as amounts to be operated, physical amounts at the vehicle level, which are different from an amount to be operated by each actuator. In other words, in the integration control for providing functions at the vehicle level, the physical amounts to be operated should be calculated to be in common with various types of controls or to be applicable to various types of functions.
This calculation for the integration control will now be exemplified about the vehicle transmission, which includes an automatic transmission controlling a joint state of a clutch on controlled hydraulic pressure and a belt-type gearless transmission. In the case of the conventional control that is not carried out as the integration control, the processing carried for instructing the joint state of, for example, the clutch has figured out a hydraulic command value as the physical value for the control. On the other hand, the integration control is required to perform the processing for obtaining a proper operated amount that realizes a function at the vehicle level. Thus, in the case of the processing for commanding the joint state of the clutch, it is required that the processing be carried out to have a physical variable nearer to the vehicle level than a hydraulic command value.
For instance, as shown in Japanese Patent Laid-open publication No. 5-209678, there has been known an apparatus for controlling an output of a drive unit. In this apparatus, employed is a torque-base control that uses engine torque for a physical variable in the control processing.
In the conventional or torque-base control, a premise is made such that, when the engine is controlled to have a desired torque value at a transmission output shaft or drive shaft, a joint state of a friction joint component intervening between the engine and the transmission will not fluctuate whenever any amount of torque is inputted from the engine or transmission. In other words, the conventional technique takes it into account a slip ratio (i.e., transmitted ratio) at a torque converter through which a running torque is transmitted from the engine to the torque converter and transmission.
However, actually, the joint state of the friction joint component varies depending on the magnitude of torque inputted from the engine and torque converter. By way of example, when it is supposed that the transmission according to the conventional technique is provided with a planetary gear and a clutch, there is a premise that the clutch in the transmission provides a complete connected state or a complete disconnected state in any case when the torque is transmitted from the engine and torque converter to the transmission.
However, the joint state of the clutch changes any time depending on gear changes and others. Thus, compared to the torque converter controlled to transmit a necessary amount of torque, the clutch is subjected to a larger number of uncertain factors. When a transmission-output-shaft torque or wheel-rotation torque is adjusted to a desired amount, it is therefore necessary to pay attention to the transmission torque at the friction joint component that varies depending on various factors. With no such a consideration taken, it is impossible to realize the engine output control preventing an improper slip at the friction joint component.

Method and apparatus for controlling joint force of friction-joint component mounted on vehicle


A quick change rotary mower blade assembly includes a mower blade attached to a blade assembly pin that is inserted into an internal bore in a spindle extending through a housing under the mower deck. A blade retainer on the lower end of the spindle has a pair of notches holding and locking the mower blade in place.

One issue that may dissatisfy users and customers of grass mowing machines is the amount of time and difficulty needed to remove and install rotary mower blades for sharpening or replacement. The blades normally are installed with a center attachment bolt and washer assembly that threads into a mower deck spindle assembly. The bolt then needs to be torqued to secure the blade to the spindle assembly. Depending on the size of the mower deck and the number of spindle assemblies, center attachment bolts may be difficult to reach and attach a wrench or socket to each bolt and tighten it sufficiently. Additionally, due to limited ground clearance and accessibility to the underside of the mower deck, there may be limited space to provide adequate leverage to the wrench or socket to break the bolt loose. The amount of torque required to break a bolt loose can be substantial if the blade has not been changed for a long time. This may require an additional lever or wood block to lock the blade into position for proper torqueing of the bolt.
A quick change rotary mower blade assembly is needed that allows removal and installment of the blade without a wrench or socket. A quick change rotary mower blade assembly is needed that is easy to use. A quick change rotary mower blade assembly is needed that does not require application of high torque to a center attachment bolt under the mower deck.

Quick change rotary mower blade assembly


A system wherein a Caller Application is enabled to reduce latency after a First Call to a Data Link Library after which a stub function provides direct access to a selected algorithm's work function for execution by a processor. A Hardware Abstraction Layer receives information from multiple CPU's to determine the appropriately compatible algorithm for the processor that is to be utilized.

1. Field of the Invention
This invention involves methods for improving CPU performance by removing the overhead associated with accessing of alternate algorithms in a computer program.
2. Description of Related Art
In certain performance critical regions of code, there is the need to dynamically switch between different implementations of a function with minimal overhead. An example of this would be an operating system or a disk driver selecting different encryption algorithms for a disk file system. The implementations of these different encryption algorithms would typically be located in functions of modular code like a DLL (Dynamically Linked Library). The operating system or disk driver would determine or call some other code to determine which algorithm it needs. It then executes the implementation for this algorithm by loading the module and/or calling the function. This process in the example is time consuming because of the two main factors that incur overhead.
The first factor is the calls into the functions of modular code. The locations of the functions in modular code are fixed and the application needs to resolve the addresses of these functions upon loading/linking the module. This process of loading and linking the module involves redirecting the application to an import/export table, a stub of code that knows the location of the functions, or some other means of resolving the address. In addition, these redirections introduce possible memory stalls, cache misses, and other factors that add latency. Due to these levels of indirection, making calls into functions that reside in modular code has to go through paths that add overhead to the call.
The second factor that incurs overhead is the dynamic switching to the appropriate implementation of the algorithm. Execution of the switching involves conditional branches that yield some uncertainty about the flow of instructions. It is possible that these uncertainties will cause the processor to make branch mispredictions and execute instructions that add latency. All of these factors that contribute to overhead add up and may lead to an unacceptable performance of the application.
It is therefore important to solve the problem of overhead when switching between different implementations. Once an implementation is selected and it is determined that this implementation will always be used by the application from that point on, then we no longer need the ability to dynamically switch between different implementations and an optimization can be made to directly call the implementation without going through the overhead of the dynamic switching process. This invention accomplishes that by providing a method of placing a stub of code at the entry-point of the time critical function. This stub will determine which implementation of the function is to be called in the current environment. The stub will then patch the application so that the application will directly call into this function without the usual overhead.
One related art method to which the method of the present invention generally relates is described in U.S. Pat. No. 5,121,003, entitled "Zero Overhead Self-Timed Iterative Logic". This related art method is a method which uses a third phase to store data, which allows domino logic gates to be cascaded and pipelined without intervening latches. The inputs to this system must have strictly monotonic transitions during the logic evaluation phase and the precharge signal must be active during only the precharge phase. Furthermore, the pipelined system can feed its output back to the input to form an iterative structure. Such a feedback pipeline is viewed as a "loop" or "ring" of logic which circulates data until the entire computation is complete.
The present invention differs from the above prior cited art in that the prior invention, appears to be a hardware design technique for use in self-timed (as distinct from clocked) logic. As such, the prior cited art does not solve the issue of reducing the overhead incurred when linking two software modules together dynamically. The method of the present invention solves the problem of reducing overhead incurred in dynamically linked software modules, whereas the prior cited art, does not.
Another related art method to which the method of the present invention generally relates is described in U.S. Pat. No. 5,513,132, entitled "Zero Latency Overhead Self-timed Iterative Logic Structure And Method". This related art method is a method where a novel third phase of CMOS domino logic is identified and used in the logic system of the invention to store data. The use of this third phase in addition to the normally used precharge and logic evaluation phases, provides a logic structure of cascaded domino logic gates which are pipelined without intervening latches for memory storage. The memory storage function of the conventional latches are provided by the third logic phase. The novel approach requires that the functional inputs to this system have strictly monotonic transitions during the logic evaluation phase, and requires that the precharge signal must be active during only the precharge phase. Embodiments of the pipelined system according to the invention, are structured so that the output of the pipeline are fed back to the input of the pipeline to form an iterative structure. Such a feedback pipeline is viewed as a "loop" or "ring" of logic. The logic ring circulates data until the entire computation is complete. A method for using the logic structure is also described.
The present invention differs from the above prior cited art in that the cited prior invention appears to be a hardware design technique for use in self-timed linkage (as distinct from clocked). As such, this prior cited art also does not solve the issue of reducing the overhead incurred when linking two software modules together dynamically. The prior cited art is a hardware (H/W) technique for designing asynchronous logic, whereas the method of the present invention is a software technique to reduce overhead.

Method for zero overhead switching of alternate algorithms in a computer program


A dedicated hydraulic line for transmission of a signal device capable of generating one or more unique signals to one or more tools within a subterranean well. Each tool can be equipped with a reader device for receiving signals from and transmitting signals to the signal device. Each reader device can control operation of the tool associated therewith if the reader device is programmed to respond to signals received from the control device. Hydraulic fluid used to operate the tool can be conveyed via the dedicated hydraulic line or a separate hydraulic line. A separate hydraulic line can be used to reset the tool.

1. Field of the Invention
The present invention relates to systems, assemblies and processes for controlling equipment, tools and the like that are positioned in a subterranean well bore, and more particularly, to systems, assemblies and processes for controlling a plurality of equipment, tools and the like that are positioned in a subterranean well bore.
2. Description of Related Art
In the production of fluid from subterranean environs, a well bore is drilled so as to penetrate one or more subterranean zone(s), horizon(s) and/or formation(s). The well is typically completed by positioning casing which can be made up of tubular joints into the well bore and securing the casing therein by any suitable means, such as cement positioned between the casing and the walls of the well bore. Thereafter, the well is usually completed by conveying a perforating gun or other means of penetrating casing adjacent the zone(s), horizon(s) and/or formation(s) of interest and detonating explosive charges so as to perforate both the casing and the zone(s), horizon(s) and/or formation(s). In this manner, fluid communication is established between the zone(s), horizon(s) and/or formation(s) and the interior of the casing to permit the flow of fluid from the zone(s), horizon(s) and/or formation(s) into the well. The well is subsequently equipped with production tubing and convention associated equipment so as to produce fluid from the zone(s), horizon(s) and/or formation(s) of interest to the surface. The casing and/or tubing can also be used to inject fluid into the well to assist in production of fluid therefrom or into the zone(s), horizon(s) and/or formation(s) to assist in extracting fluid therefrom.
Often during the drilling and completion of a well or during production or injection of fluid from or into a well or subterranean environs, it can be desirable to control the operation of multiple tools, equipment, or the like, for example perforating guns, cutters, packers, valves, sleeves, etc., that can be positioned in a well. In the production of fluid from or injection of fluid into subterranean environs, multiple tools and equipment are often positioned and operated in a well bore. For example, a plurality of perforating guns can be deployed within a well bore to provide fluid communication between multiple zones, horizons and/or formations. Upon detonation, these guns file projectiles through casing cemented within the well bore to form perforations and establish fluid communication between the formation and the well bore. Often these perforating guns are detonated in sequence. A plurality of flapper valves can be used in conjunction with multiple perforating guns to isolate the zone, horizon or formation being completed from other zones, horizons and/or formations encountered by the well bore. As another example, packers can be deployed on a tubular and expanded into contact with casing to provide a fluid tight seal in the annulus defined between the tubular and the casing. Flow chokes can be used to produce the well from multiple zones with these chokes set at different openings to balance the pressure existing between multiple subterranean zones, horizons and/or formations so that a plurality of such zones, horizons and/or formations can be produced simultaneously.
Hydraulic systems have been used to control the operation of tools positioned in a well. Such systems have a control system and a down hole valve. The control system includes surface equipment, such as a hydraulic tank, pump, filtration, valves and instrumentation, control lines, clamps for the control lines, and one or more hydraulic controller units. The control lines run from the surface equipment to and through the wellhead and tubing hanger to desired equipment and tools in the well. These control lines are clamped usually along a tubular that is positioned within a well. The control lines can be connected to one or more hydraulic control units within a well for distributing hydraulic fluid to the down hole valves.
Several basic arrangements of hydraulic control lines are used in a well. In a direct hydraulic arrangement, each tool that is to be controlled will have two dedicated hydraulic lines. The "open" line extends from the surface equipment to the tool and is used for transporting hydraulic fluid to the downhole control valve to operate the tool, while the "close" line extends from the tool to the surface equipment and provides a path for returning hydraulic fluid to the surface of the earth. The practical limit to the number of tools that can be controlled using the direct hydraulic arrangement is three, i.e. six separate hydraulic lines, due to the physical restraints in positioning hydraulic lines in a well. The tubing hanger through which the hydraulic lines run also has to accommodate lines for a gauge system, at least one safety valve and often a chemical injection line, which limits the number of hydraulic lines the hanger can accommodate. When it is desirable to control more than three tools in a well, a common close arrangement can be employed in which an open line is run to each tool to be controlled and a common close line is connected to each tool to return hydraulic fluid to the surface. Again, the common close system has a practical limit of controlling five tools, i.e. six separate hydraulic lines.
In another arrangement, a single hydraulic line is dedicated to each tool and is connected to each tool via a separate, dedicated controller for each tool. To open the tool, the hydraulic fluid in the dedicated line is pressurized to a first level. Thereafter, the hydraulic fluid in the dedicated line is pressurized to a higher level so as to close the tool. In a digital hydraulics system, two hydraulic lines are run from the surface equipment to a downhole controller that is connected to each of the tools to be controlled. Each controller is programmed to operate upon receiving a distinct sequence of pressure pulses received through these two hydraulic lines. Each tool has another hydraulic line is connected thereto as a common return for hydraulic fluid to the surface. The controllers employed in the single line and the digital hydraulics arrangements are complex devices incorporating numerous elastomeric seals and springs which are subject to failure. In addition, these controllers use small, inline filters to remove particles from the hydraulic fluid that might otherwise contaminate the controllers. These filters are prone to clogging and collapsing. Further, the complex nature of the pressure sequences requires a computer operated pump and valve manifold which is expensive.
In accordance with the "distribution hub" arrangement, two hydraulic lines are run from the surface to one downhole controller to which each tool to be controlled is connected by its own set of two hydraulic lines. This controller can be ratcheted to any of a number of predetermined locations, each of which connects the control lines of a given tool to the control lines running from the surface to the controller. In this manner, each tool can be operated independently from the surface. By ratcheting the controller to another location, another tool can be operated. This arrangement is expensive due to the large number of components and complex arrangement of seals in the controller and unreliable as it is difficult to get feedback to the surface on the exact position of the controller, especially if the operator has lost track of the pulses previously applied. Thus, a need exists for hydraulic control systems, assemblies and processes for use in controlling multiple tools in a well which is relatively inexpensive, simple in construction and operation and reliable.

Systems, assemblies and processes for controlling tools in a wellbore


A method and apparatus for limiting the effect of interfering transmission on a Global Positioning System (GPS) receiver is disclosed. A first mode of operation of the GPS receiver is provided wherein the AGC of the receiver is operated in a linear state. A second mode of operation of the GPS receiver is provided wherein the AGC of the receiver is operated in a non-linear state. A first signal is provided indicating a presence of a jamming signal. In response to the first signal the GPS receiver is switched from the first mode of operation to the second mode of operation.

The basic functionality of a Global Positioning System (GPS) receiver is to calculate the latitude, longitude and altitude of the GPS receiver's location (i.e. the co-ordinates of the receiver) upon receiving a number of GPS signals from a network of GPS satellites that orbit the earth. The calculation of the co-ordinates of the GPS receiver typically begins by comparing the timing associated with a select number of received GPS signals. After the initial comparison of the received GPS signals, values for timing corrections associated with the select group of received GPS signals are established. The timing corrections are made in order to solve a three-dimensional geometric problem, which has as its solution the co-ordinates of the GPS receiver.
The received GPS signals are typically weak and thus easily interfered with by other radio transmissions in the same or adjacent frequency bands. Interference can be especially problematic when the GPS receiver is co-located with a communications device that includes a radio transmitter such as a cellular telephone. The transmitted signal from the co-located communication device can overload or saturate the GPS receiver front-end designed to receive weak GPS signals. In such a situation, no useful information can be extracted from the received GPS signals originating from the GPS satellites.
One known method of overcoming this problem is by filtering all of the received signals from the GPS antenna before down conversion of the respective transmission signal band by the GPS receiver front-end. Typically a low noise amplifier (LNA) is first used to amplify the signal before further filtering or mixing to another frequency. The result of adopting this approach is that the loss of all signal energies in the filter reduces the sensitivity of the GPS receiver permanently, irrespective of whether or not the co-located communications device is transmitting. This is an undesirable result as the GPS signals received from the satellites are weak and reducing the sensitivity of the GPS receiver further reduces the operability of the system. Additionally, the filter would also occupy space, and add cost to the unit.
Another approach in dealing with the effects of co-located communications device is overcome by the use of a high linearity LNA. This ensures that the LNA is capable of amplifying the GPS signal despite the presence of a large interfering locally generated transmission. The disadvantage of this solution is that such an LNA would consume additional power, which is not acceptable in a portable battery powered device such as a cellular telephone. A filter following the LNA would also be required to provide sufficient rejection of the interfering signal to prevent overload of the next stage of the receiver, typically a mixer. These additional performance requirements increase the size, power consumption and cost of the filter and make implementing a highly integrated receiver design without the additional filter difficult.
There are several prior art schemes that further deal with minimizing the effects of a cellular transceiver and antenna on the GPS receiver operation by blanking GPS signals during operation or transmission of radio receiver signals. These systems are implemented by sending a blanking signal to the GPS receiver upon detecting the presence of a jamming signal outside of the GPS receiver. This does however increase the complexity of system integration as an appropriate dynamic blanking signal needs to be provided.
It is therefore an object of the invention to provide a relatively efficient method for minimizing the effect of interfering transmission without blanking the automatic gain control (AGC) or correlator of the GPS receiver or deactivating the GPS receiver based upon a detected interference.

GPS receiver with improved immunity to collocated transmissions and method therefor


A method and system for detecting an image of an object in an analyzer-based system with a polychromatic x-ray beam from an x-ray source, wherein an analyzer crystal and a detector simultaneously acquire a rocking curve of the x-ray beam for all energies of the x-ray beam. The x-ray beam is diffracted through the object using an asymmetrical monochromator. A detector movement is synchronized with one of the x-ray source or the object. The synchronization includes moving the detector at a first rate that is different than a second rate of the object or the x-ray source, wherein a ratio between the first rate and the second rate is determined by the magnification of the system.

Phase contrast imaging (PCI) is increasingly being considered as an alternative to conventional X-ray imaging. For example, due to its extreme contrast when imaging soft tissue, PCI has the potential to reduce the alarming number of false positives reported in preventive mammography. Additionally, PCI has potential to decrease the deposited glandular dose in the tissue. In particular, analyzer-based imaging (ABI) is one of the methods to obtain PCI images. It has been used to obtain remarkable contrast images of breast tissue (as well as other soft tissue like ligament and muscle) using synchrotron light as well as in compact setups. Ultimately, ABI mammography could improve the quality of current breast imaging technologies while, at the same time, reducing their risks.
ABI can provide three parametric images: an absorption image, a refraction image, and an ultra-small angle scatter image. The absorption image is similar to a digital mammogram. However, ABI completely rejects Compton scatter, producing sharper absorption images compared to current mammography systems. The refraction image is an estimation of the very small deflections in the photon paths produced by small changes in the tissue's density. Finally, the ultra-small angle scatter image measures the dispersive properties of sub-pixel textural components in the tissue.
ABI systems use two or more crystals as very selective angular filters to study the changes in the angular content of the beam when it reacts to the imaged sample. Such crystals are called the monochromator and analyzer, and are commonly made of Silicon (Si) or Germanium (Ge). By rotating the analyzer, the system acquires samples of the Angular Intensity Profile (AIP) of the beam, known as angular images. Angular data is used to retrieve absorption, refraction, and scatter images.
Diffraction Enhanced Imaging (DEI) and Multiple Image Radiography (MIR) are the earliest and most common approaches. FIG. 1 shows a schematic diagram of analyzer system 10, according to the DEI method and system of U.S. Pat. No. 5,987,095, herein incorporated by reference. Crystal analyzer 30 represents a Bragg type crystal analyzer. A double crystal monochromator 11 is used to generate mono-energetic x-ray beam 16. Each crystal of monochromator 11 is constructed of silicon using a (3, 3, 3) lattice planes structure. The lattice planes used in monochromator 11 match those used in crystal analyzer 30. Shutter 14, such as a rotary shutter or the like, can be used to control exposure and limit unnecessary scatter of the beam. A detector is used to detect an image of object 25. In one preferred embodiment according to this invention, the object 25 image is detected with image plate 40 which comprises a photo-stimulable phosphor image plate typically used for radiology. An image recorded on image plate 40 can be digitized, stored, and displayed.
Object 25 and image plate 40 can be scanned together, such as in a direction shown by the vertical arrow in FIG. 1, to provide a two-dimensional radiograph. Ionization chamber 12 can be used downstream of monochromator 11, for example to monitor tuning. Ionization chamber 15, as shown in FIG. 1, which is positioned upstream of object 25, can be used to monitor a radiation dose at a surface of object 25.
Crystal analyzer 30 is positioned between object 25 and image plate 40. Crystal analyzer 30 is fixed spatially with respect to transmitted beam 20, oriented to diffract transmitted beam 20 onto image plate 40. Fine angular control of crystal analyzer 30 can position crystal analyzer 30 at various positions within the rocking curve shown in FIG. 2. FIG. 2 shows a solid line curve representing a theoretical calculation of the rocking curve for crystal analyzer 30. Such theoretical calculation includes effects of x-ray beam 16, as prepared by double crystal monochromator 11. The points on the curve of FIG. 2 represent representative measured points of the rocking curve of crystal analyzer 30. FIG. 2 shows the low angle side and the high angle side of the rocking curve, which are preferably the locations at which two images are detected.
The crystal diffracts incoming light traveling within a very narrow angular range, the center of which is known as Bragg's angle θB. Bragg's angle is energy dependent and can be computed using Bragg's Law:
                                          λ                                                                          m                    =                      2                        d                                                                          sin                                                                                θ              B                                                                                λ          =                      12.383            E                                              (        1        )            where E and λ are the energy and wavelength of the radiation, m is an integer, and d is the spacing between atomic layers within the crystalline structure. The angular acceptance range is known as Darwin width, which is in the μrad range. For example, Si111 and Ge111 have Darwin widths of 4.31 and 10.47, μrad at 59.32 keV, respectively.
Since Bragg's law is energy dependent, previous work in ABI assumed quasi-monochromatic light to be indispensable to obtain meaningful images. Unfortunately, quasi-monochromatic radiation must be obtained by conditioning the beam with the monochromator. Hence, the monochromator absorbs most of the radiation produced by the X-ray source narrowing its energy spectrum. This process causes very few photons to reach the object and detector. As a consequence, the exposure time needed for ABI is currently a limiting factor for its implementation in a clinical setup. After the monochromator, the resulting beam is also narrow in the vertical direction and close to a fan beam in the horizontal direction. Because of that, the conditioned beam has a very wide aspect ratio: typically a few millimeters high versus several centimeters wide. Given this geometry, the samples need to be scanned vertically.
Since exposure times are often the limiting factors in ABI systems, synchrotron light sources (SLS) were instrumental during the early stages of ABI research. Under synchrotron light conditions, the number of photons is high enough to produce low-noise images with a reasonable exposure time, even after conditioning the beam. Using SLS, a number of publications set up the foundations of analyzer-based imaging.
In the recent years, some groups have tried to transition to a compact setup capable of imaging a breast sample in a practical time for clinical applications using conventional x-ray sources (CXS). Inspired by synchrotron research, all previous efforts have been focused on obtaining bright enough near-monochromatic beams by capturing the emission line of a CXS. Despite these efforts compact ABI systems remain to be limited by the long exposure times required for imaging.
Therefore, there is a need for systems and methods for performing X-ray phase contrast imaging using a conventional X-ray source and polychromatic beams, instead of SLS or CXS with quasi-monochromatic light(s), with lower cost and sufficient power density to provide high resolution medical images and shortened exposure times required for imaging.

Apparatus and method for analyzer-based contrast imaging with a polychromatic beam


The present invention provides a simple circuit for measuring the delay time between a driver (DR) and a device under test (DUT), and the (DUT) and a comparator (CP) during the connection state of an I/O test where separate driver and comparator paths are used. In the connection circuit of the I/O test using two I/O common pins to connect to one of the pins of the DUT, a terminal pin of a DUT socket corresponding to the DUT pin is grounded. Furthermore, in the connection circuit of the I/O test using a DR-only pin and an I/O common pin to connect to the DUT pin, the terminal pin of the DUT socket is grounded and a standard comparator is employed.

In conventional semiconductor inspection systems, an ordinary I/O pin electronics circuit includes an I/O common pin 10 which functions as a driver (DR) and comparator (CP) as shown in FIG. 3(a). The DR and CP are connected with a device under test (DUT) to be tested 13 by a cable having a propagation delay time Ta. As is well known in the art, the driver (DR) provides a test signal to the device under test (DUT) and a resultant output signal from the DUT is compared with an expected signal produced by the semiconductor inspection system by the comparator (CP). Also well known in the art, during the test, each DUT is inserted in a DUT socket provided on a test station of the semiconductor inspection system.
FIG. 3(b) is a diagram showing timing for writing and reading operations.
Data R which is read out from the DUT reaches the comparator CP after a propagation delay time Ta. In order to insure that the DUT receives the write data W immediately after the completion of this reading operation, write data W is output from the DR at a time Ta before the writing operation begins in the DUT. Thus, the data W reaches the DUT just as the writing operation begins at the DUT. However, the data W outputted from the driver DR reaches the comparator CP without any delay. Thus, as soon as the data W is output by the driver DR, the data R, which is being read from the DUT, and data W, which is outputted from the DR, interfere (i.e., combine) at the comparator CP. The time during which the interference takes place is twice as long as Ta, so that proper comparison measurements cannot be performed by the comparator CP during this period of time. This period of time is called I/O dead band 20, and is determined by the propagation delay time Ta between the DR and CP and DUT.
In order to measure the propagation delay time Ta, an open circuit is formed at the DUT side as shown in FIG. 4(a). A waveform output from the driver DR is transmitted to the open end of the cable. Thus, the reflection of the transmitted wave returns through the same cable and is detected by the comparator CP. This waveform is shown in FIG. 4(b), and the reflection time can be measured from the waveform by an appropriate measuring instrument such as an oscilloscope, a time interval counter or a time domain reflectometer. Namely, the propagation delay time Ta of the cable is one-half of the time it takes to detect the reflected wave after transmission of the original wave through the cable.
In inspecting a high speed device where the I/O dead band causes a problem, a separate I/O test is performed, wherein the transmission path from the DUT to the CP is separated from the path between the DUT and the DR (see FIG. 5(a)). Due to the split cable configuration of FIG. 5(a), interference will not occur between the data R which is read out from the DUT and data W output from the DR at the comparator CP. Therefore, the proper comparison measurement can be performed by the CP without a dead time. Of course, it will be noted that the waveforms of the read-out data R and output data W interfere at the output of the DR. The collision of these waves will not cause problems because the waves only pass through each other without modulating one another. Moreover, since the waveform from the DUT ends at the DR end, it will not affect the CP end.
If it is desirable to measure the propagation delay time of the cables in the split cable configuration of FIG. 5(a), then the point VT in FIG. 5(a) is placed in a high impedance state (i.e., an open circuit). A signal is transmitted and reflected as before so that the total delay time Tb+Tc can be measured from the DR to the CP through the DUT. However, the delay time Tb from the DR to the DUT and the delay time Tc from the DUT to the CP cannot be separately measured using this method.

Transmission path structure for measuring propagation delay time thereof


A slatted sunroof for a motor vehicle has slats that are lifted and spaced apart at intervals from one another when the roof is open, and in particular are pushed against one another so that their spacing is reduced by contrast with their closed position. A roof liner that is deformable extends, at least when the roof is closed, in an area located below the slats. Fasteners are provided that hold the roof liner against the slats at locations that are regularly spaced and produce an orderly pattern when the roof is opened, especially in the displacement direction of the slats. The sunroof is designed in such fashion that undesired folding of the roof liner because of different degrees of thermal expansion of the roof liner and the slats is prevented. This is accomplished by the fasteners each comprising a retaining element on the slat side and a retaining element on the roof liner side, the retaining elements being connected movably with one another, with the retaining elements on the slat side being fastened to the slats and the retaining elements on the roof liner side being fastened to the roof liner.

This application claims the priority of foreign application no. 98035971.7 filed in Germany on Jan. 30, 1998, the disclosure of which is expressly incorporated by reference herein.
The invention relates to a slatted sunroof for a motor vehicle, with slats that are lifted and spaced apart from one another when the roof is opened with said slats being pushed against one another to reduce their spacing as compared to their spacing in a roof closed position, and with a roof liner that is deformable and extends in an area located below the slats, at least when the roof is closed, with fasteners being provided that hold the roof liner against the slats at points that are regularly spaced for orderly folding when the roof is opened.
To create a visually attractive appearance, slatted sunroofs of this type are covered on the side facing the vehicle interior with a film that forms the roof liner, said film consisting of plastic in particular and possibly laminated with fabric or other materials. In known slatted sunroofs of this type, this roof liner is deliberately fastened to the slats of the slatted sunroof at points which produce an orderly fold pattern in the roof liner when the slats are pushed together, said slats being raised adjacent to one another. In particular this applies to a fold pattern in which the folds of the roof liner extend into the spaces formed between the raised adjacent slats.
The roof liner is attached to the slats by hook-and-loop fasteners or with adhesive tapes or with adhesive applied in strips.
The slats of such a slatted sunroof usually consist of sheet steel, sheet aluminum, extrusion-molded aluminum sections, and plastic. In contrast to this arrangement, the roof liner as a rule consists of plastic film. Consequently, the slats and roof liner normally exhibit different thermal expansion behavior. As a result of the above-described fastening of the roof liner to the slats, at temperatures that differ from the temperature prevailing at the time the roof liner was attached to the slats, different degrees of thermal expansion can create undesired fold patterns in the roof liner. In addition, different temperatures prevail in the slats, which are exposed to the exterior of the vehicle, than in the roof liner, which is exposed to the vehicle interior, and this can also result in an undesired fold pattern because of the different degrees of thermal expansion involved.
The present invention relates to the problem of providing a slatted sunroof of the species recited at the outset in which no fold formation in the roof liner takes place because of different degrees of thermal expansion in the slats and the roof liner.
This problem is solved according to the invention by a slatted sunroof, wherein the fasteners each have a retaining element on the slat side and a retaining element on the roof liner side, said retaining elements being connected with one another so that they are movable with respect to one another, with the retaining elements on the slat side being fastened to the slats and the retaining elements on the roof liner side being fastened to the roof liner.
The invention is based on the general idea of fastening the roof liner to the slats in way that permits relative movement between the roof liner and the slats. It is proposed for this purpose to use fasteners formed by two structural elements that are displaceable with respect to one another, with one element being fastened to the slats and the other element being fastened to the roof liner. This separation into two separate elements makes it possible to make the element to be fastened to the slats from the same material as the slats themselves, or from a material with a thermal expansion behavior that is approximately the same as that of the slat material, and to make the element to be fastened to the roof liner from the same material as the roof liner or from a material that undergoes approximately the same degree of thermal expansion as the roof liner material. In this way, no relative movements caused by temperature changes in the roof liner and in the slats and/or caused by temperature differences between the roof liner and the slats can occur between the roof liner and the element of the fasteners fastened thereto or between a slat and the element of the fasteners fastened thereto. All relative movements take place between the two elements of the fasteners and are compensated there by the connection formed between those elements of the fasteners that permit relative movement. Undesired folding caused by extreme temperature conditions is therefore no longer possible over a wide temperature range.
In one especially advantageous embodiment of the slatted sunroof according to the invention, the retaining element of the fasteners on the slat side can be in the form of a wire or rod that runs transversely to the sliding direction of the slats and is fastened to the individual slats, not over their entire lengths but especially pointwise at a plurality of locations distributed over the length of the rod. The retaining element of the fasteners on the roof liner side is designed as tubular loops into which the corresponding rod is inserted. At the point where the rod is fastened to the respective slat, the loop has cutouts facing the slats, through which cutouts the rod is connected to the respective slat.
Embodiments of the loop fastened to the roof liner and suggestions for fastening the rods to the slats, as well as additional advantages and important features of the slatted sunroof according to the invention, are provided in the claims, drawings, and the following description of preferred embodiments with reference to the drawings.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.


Methods and devices herein are provided for managing atrial (A) pacing in connection with premature atrial contracts (PAC). The methods and devices obtain an atrial pace-on-PAC (APAC) interval and cardiac activity (CA) signals. The methods and devices are configured to: i) during a first cardiac beat; following a ventricular paced (VP) or ventricular sensed (VS) event, activate a timer for a post ventricular-atrial refractory period (PVARP) interval; and determine whether a first atrial refractory (AR) event occurs during the PVARP interval; ii) during a second cardiac beat; in response to the detecting that the first AR event occurred, initiate an APAC interval; during the APAC interval for the second cardiac beat, determine whether a second AR event occurs; and update a count of APAC events when the second AR event occurs; and iii) repeat i) and ii) for multiple cardiac beats, to track the count of APAC events.

Embodiments of the present disclosure generally relate to methods and devices for managing therapy to avoid competitive atrial pacing.
Today, various types of implantable medical devices (IMDs) have been implemented to provide therapies in connection with various arrhythmias, such as bradycardia, tachycardia and the like. A relatively large portion of existing IMDs deliver atrial and ventricular pacing therapies in a dual chamber configuration.
However, a problem may arise when the patient's physiologic behavior negatively interacts with the dual chamber operation of the IMD in a manner that results in competitive atrial pacing, which may result in an arrhythmia. Competitive atrial pacing is the phenomenon where an atrial pacing output occurs soon after a sensed atrial event (e.g., a premature atrial contraction or PAC) that has occurred during the atrial refractory period. Competitive atrial pacing may arise as a consequence of the IMD attempting to modulate the pacing rate and heart rate response to patient activity and physiologic conditions. Competitive atrial pacing may result in adverse outcomes such as Repetitive Non-reentrant Ventriculoatrial Synchrony (RNRVAS), induction of an atrial arrhythmia by pacing during the atrial vulnerable period, and induction of a ventricular arrhythmia via ventricular pacing soon after atrial pacing due to pseudo-psuedo-fusion (atrial pacing simultaneous to an intrinsic ventricular event, resulting in an unintentional blanked ventricular intrinsic event).
Conventional IMDs have attempted to resolve competitive atrial pacing, such as utilizing an algorithm referred to as a non-competitive atrial pacing (NCAP) algorithm, which allows the device to detect a refractory sensed atrial event and extend the IMD's atrial refractory period for a programmed number of milliseconds (200-400 ms in 50 ms intervals, nominally 300 ms). This delays the atrial paced event and allows the patient's physiologic atrial refractory period to end, reducing the likelihood of atrial pacing during the atrial vulnerable period. When an atrial pacing stimulus is delayed by the NCAP algorithm, the IMD attempts to maintain a stable ventricular rate by shortening the following atrial-ventricular (AV) interval, with a minimum AV interval of 30 ms. There are no diagnostics associated with NCAP operation.
When an atrial event is sensed during a post ventricular atrial refractory period (PVARP), the event introduces the potential for three adverse outcomes. For example, repetitive non-reentrant ventricular-atrial synchrony (RNRVAS) may occur, in which an atrial arrhythmia is induced by pacing during the atrial vulnerable period and a ventricular arrhythmia may be induced by pacing soon after an unintentionally blanked ventricular intrinsic event. RNRVAS represents a pacemaker mediated arrhythmia. A retrograde arrhythmia event that occurs during PVARP is ignored and subsequent atrial pacing occurs, however there is functional loss of capture. Subsequently, the device tracks the atrial paced event and utilizes the atrial paced event in connection with determining a timing for a ventricular paced event, which then retrogradely conducts to the atrium. The pattern is then repeated.
The foregoing phenomenon results in loss of AV synchrony in exchange for VA synchrony which reduces hemodynamic stability by removing the contribution of the atrial kick to ventricular filling. The repetitive nature of the foregoing pacemaker mediated arrhythmia also increases the possibility that instead of failing to capture, the subsequent paced event occurs during a vulnerable window of the atrial refractory period and induces an atrial arrhythmia. Further, atrial arrhythmias such as atrial fibrillation are an increasingly prevalent cardiac pathology that among other things, reduces cardiac output.
A need remains for a solution that reduces a T/AF occurrence or burden to improve patient quality of life in clinical outcome.
Another potential adverse outcome is the induction of a ventricular arrhythmia, albeit less likely. The atrial event that occurs during the PVARP interval may subsequently conduct of the ventricle and it is possible that a competing atrial paced pulse may cause the intrinsic event to be hidden by the ventricular blanking period that follows atrial pacing. If an intrinsic VS is blanked by an AP event, the device may track the AP event followed by AVP event which introduces the possibility of inducing a ventricular arrhythmia if that the PA event is delivered during an intrinsic T wave. However, conventional approaches to addressing competitive atrial pacing still experience certain limitations.
Further, one solution that has been attempted for non-competitive atrial pacing is to prevent triggering an atrial tachycardia by delaying a scheduled atrial paced event from occurring within an atrium's relative refractory period. In the foregoing proposed solution, when an intrinsic atrial event occurs during the PVARP, the PVARP is extended by a fixed amount (e.g., 300 ms). In addition, the ventricular pacing interval is maintained on a sliding scale that seeks to maintain a V-V interval, which causes the AV delay to be adjusted between a maximum AV delay down to 30 ms. Adjusting the AV delay in this manner to maintain a target V-V interval can create variability and unpredictability. For example, when the AV interval falls below 80 ms, the system may not achieve the full benefit of the "atrial kick" at the end of the atrial contraction.
A need remains for methods and devices that provide an improved approach for addressing competitive atrial pacing.

Method and device for avoiding competitive atrial pacing


Provided are a method for welding a battery module and a welded structure, and more particularly, a method for welding a battery module and a welded structure, in which a plurality of battery cells provided with electrode tabs are assembled to form a module and a voltage measurement portion of a voltage measurement means is welded to the electrode tabs so as to secure stability against vibrations and external shocks, thereby increasing reliability of voltage measurement and the voltage measurement portion is welded to the electrode tabs using the same kind of materials so as to facilitate an operation and improve productivity.

A vehicle using an internal combustion engine using gasoline or heavy oil as main fuel has a serious effect on pollutions such as air pollution. Therefore, in order to reduce the pollutants, many attempts to develop an electric vehicle or a hybrid electric vehicle have been recently conducted.
Recently, a high output secondary battery using a high energy density non-aqueous electrolyte has been developed. A plurality of high output secondary batteries are connected to each other in series so as to be able to be used in equipment requiring large power for driving a motor such as the electric vehicle, and the like, thereby configuring a large-capacity secondary battery.
As such, a single large-capacity secondary battery is referred to as 'battery cell', and a plurality of battery cells are connected to each other in series or in parallel to form a battery module. After the battery module is completed by forming the plurality of battery cells in the module structure and then additionally assembling a voltage measurement means for measuring voltages of the battery cells and other parts. In this case, the battery cells are provided with electrode tabs to electrically connect the plurality of battery cells, in which the plurality of battery cells are connected by various methods such as clip, compression, welding, and bolting. Further, the voltage measurement means and other parts are additionally assembled around the electrode tabs.
However, the typical battery module may be instable against vibrations and external shocks due to the assembling of the voltage measurement means and other parts and may not implement easy welding due to a difference in materials between the electrode tab and the voltage measurement means. Therefore, the operation of the battery module may not be easy and thus productivity may be reduced.
Therefore, there is a need to develop a method for welding a battery module and a welded structure which may be stable against vibrations and external shocks and may implement an easy operation.
The related art for solving the above problems as described above is disclosed in Korean Patent No. 0760754.

Method for welding battery module and welded structure