A method of winding a web of a polymer film having lateral edges onto a sequence of winding cores to form a sequence of web coils comprising guiding said web by a deflection roller onto a winding drum and then onto a web take-up where the web coils are formed; the winding drum and the take-up each being provided with separate drives for rotating the winding drum and the web coils and for generating a tensile force that acts on said web; the winding drum has a central axis of rotation and a cylindrical contact surface for frictional and essentially non-slipping engagement with the web along a dynamic segment of the contact surface; this segment has a width defined by the web edges and a length defined by a first and a second end line, both extending transversely on the contact surface and parallel to the axis of rotation; the method further comprising continuously monitoring a first value of the tensile force that acts upon the web at the first end line and a second value of said tensile force acting upon the web at the second end line; the drive of the take-up is controlled by the values of the tensile force to obtain a generally smooth appearance of the surface and the end faces of the web coils.. An apparatus is disclosed for carrying out the novel method.

1. Field of the Invention
This invention relates to the art of processing endless webs of flexible materials such as typically polymer films or fibrous materials including nonwovens by continuously winding the moving web onto a sequence of winding cores to produce a sequence of web coils to facilitate handling, storing and further processing of the web material.
2. Description of the Prior Art
Methods and apparatus means for this purpose are well known in the art as disclosed e.g. in U.S. Pat. No. 4,191,341 (EP 17,277) or the references discussed therein and are frequently termed "winders", "web winding machines" or--if used for this specific purpose--"film winders".
A common feature or aim of the more advanced prior art winding methods is that relatively fast-moving webs (e.g. at web speeds of 30 to 300 meters/minute), such as polymer webs emanating from sheet extruders, blow tube extruders or web-processing lines must be wound up continuously, i.e. without interrupting the web stream, to produce an "endless" sequence of coils or web rolls. Generally, empty cores, typically in the form of cardboard tubes, are supplied from a magazine to a start-up winding position or "first station" and made to rotate therein while the web that is still being wound onto the preceding coil is in the main winding position or "second station". Now, the web will be cut transversely to terminate the preceding coil; the "trailing end" of the proceding web section will be on the top surface of that coil. The "leading end" of the subsequent web section is made to be picked up by the empty core in the start-up winding position or station (e.g. by an adhesive or electrostatic charge) while the preceding coil is discharged from the "actual" or main winding position. Then, the "start-up" coil produced in the start-up winding position is transferred without interrupting the winding operation into the main winding position and remains there until that coil has reached its predetermined volume and is terminated by again transversely cutting the web. This sequence from start-up to coil discharge is termed "winding cycle".
Rotation of the cores or of the web coils formed thereon can be achieved by a frictional contact between the coil surface and a driven winding drum in contact with the coil surface (winders of the circumferential or friction type) and/or by a separate drive that actuates the coil, e.g. by rotating its core (termed center winding).
In the first instance, a sufficient contact pressure must exist between the coil and the winding drum and such pressure ("line pressure") should be controllable since different pressures may be needed for different materials and/or different stages of coil completion.
In the second instance no such pressure is employed but a corresponding tractive power of the drive for the coil is used for winding.
Whether a given film web is more expediently processed using a friction winder or using a center winder usually depends on the material properties or the surface properties of the web material, e.g. polymer, and combination machines ("universal" or "multimode" winders) have been disclosed in the above cited art. Such machines are capable of operating either in the friction winding mode and/or in the central winding mode and provide for improved processing or improved economy.
A disadvantage of the prior art universal winders is that the so-called coil finish, that is to say the quality of the finished coil (typically having diameters of 100 to 1000 mm and widths of 5 to 3000 mm) may differ substantially depending on the polymer web material processed and on the operating mode of the winder by friction or center drive.
In order to control the linear pressure at the nip between the coil and the winding drum in the range of from a "zero pressure" and a predetermined positive contact pressure, the multimode winder disclosed in European Patent 17,277 is provided with a force sensor that permits measurement of the pressure exerted by the coil onto the winding drum; then, the contact pressure values thus determined are used to operate a compensator, e.g. a hydraulic cylinder, so as to keep the pressure between the winding drum and the wound coil at a desired predetermined or programme-controlled value, independently of the increasing weight of the supported coil pressing against the winding drum. The coil is supported "dynamically", i.e. held by a pair of arms in an angular position rather than "statically", i.e. supported in vertical direction.
Now, in order to control and maintain those winding conditions as are needed for a satisfactory coil finish with a given web material and notably for maintaining optimum conditions even though the diameter and the weight of the coil will increase during winding, winding operations required that the linear pressure to be maintained between the coil and the winding drum (in the nip), on the one hand, and the tensile force exerted in the web while moving onto the coil, on the other hand, be determined experimentally for each type of web material and each web thickness, and the values thus obtained must be used for computer-controlled operation of the winder.
In other words, the parameters of the winding operation are determined by a given programme that sets and regulates winding conditions for any given web. Thus, true control in the sense of measuring the actual critical parameters of operation and adjusting them as required for optimum coil finish is not possible with such systems.


An integrated processing technique for preparing moisture management textiles or fabrics wherein fibers are treated with compositions which impart a hydrophobic or hydrophilic property such that when incorporated into the fabrication of composite structured textiles or fabrics a hydrophobic inner surface and a hydrophilic outer surface are formed. The integrated processing technique for preparing moisture management textiles also includes finishing the textiles or fabrics to enhance the fabric's liquid water one way transfer properties. The advantage of this invention is the possibility to manufacture the pure cotton woven/knit fabrics with the good moisture management properties.

Multi-dimensional moisture transfer in fibers, textiles, and fabrics is commonly known as the moisture management property. Moisture management in clothing fabric typically refers to the transport of both moisture vapor and liquid away from the body of the clothing wearer. Many researchers consider the moisture management property of a fabric to be a major contributing factor to the perceived comfort a wearer of clothing experiences. For instance, during intense physical exercise an individual's perspiration rate may increase dramatically over the resting rate. Excreted perspiration in the form of liquid and vapor is transferred to those clothing surfaces in close proximity to the individual's skin. Liquid sweat and condensed vapor are desirably absorbed by the clothing fabric and transferred from the fabric's inner surface to the fabric's outer surface. At the outer surface the moisture is evaporated into the surrounding environment and/or is accumulated on the outer surface of the fabric. Fabrics possessing desirable moisture management properties impart a dry feeling to the wearer and are extremely desirable for the manufacture of casual wear, sportswear, or personal protective clothing.
Historically, cotton has been widely used in the manufacture of clothing due to cotton's low cost and extremely comfortable wear properties. However, cotton because of its generally poor moisture management characteristics has not been utilized to the extent it could be.
Conventionally, several attempts have been made to make textiles and fabrics with desirable moisture transport properties. For instance, several attempts have been disclosed in U.S. Pat. Nos. 6,509,285, 6,432,504, 6,427,493, 6,341,505, 6,277,469, 5,315,717, 5,735,145, 4,411,660,and 0,064,639 A1. Some of these attempts, U.S. Pat. Nos. 6,509,285, 6,432,504, and 6,427,493, utilize synthetic fiber to construct fabrics via conventional methods of knitting. Other conventional attempts utilize a cellulose substrate produced via fiber chemical process and non-woven manufacturing processes, as exemplified in U.S. Pat. No. 0,064,639 A1. However, all these conventional routes have utilized either a multi-layer structure design, U.S. Pat. Nos. 6,277,469 , 5,315,717, 4,411,660, or used fabrics with moisture management properties, such as in U.S. Pat. No. 5,269,720 "Moisture Managing Brassiere", U.S. Pat. No. 5,291,617 "Moisture Management Garment", and U.S. patent application Ser. No. 09/759,241, "Composite Textile Material". U.S. patent application Ser. No. 09/759,241 additionally discloses a composite structure with different distributions of hydrophobic or hydrophilic points/areas on the two surfaces.
Conventionally, there does not exist an integrated process of producing textiles or fabrics with a desired moisture management property.

Processing techniques for preparing moisture management textiles


A veneer laminated material formed by improving a laminated material formed in a plate or column shape by stacking a plurality of sheet-like veneers overlappingly with each other and adhering them to each other, and a method of manufacturing the veneer laminated material. The method comprises the steps of forming the veneers into parquet-like veneers formed by longitudinally arranging the plurality of divided small veneer pieces in a parquetry pattern continuously with each other, intersecting the fiber directions of the parquet-like veneers aslant with the longitudinal side ends of the parquet-like veneers, and laminating and forming the veneer laminated material by arranging the fiber directions of the parquet-like veneers adjacent to each other in a laminated layer cross section so as to be reversed to each other and intersected with each other. The fiber directions of the small veneer pieces may be intersected with the cut sides of the small veneer pieces or the fiber directions may be set in the generally same directions as the direction of the cut sides of the small veneer pieces.

As the wood board which is made by laminating veneer sheets by adhesive, glued laminated wood such as laminated lumber, plywood having veneer sheets laminated together such that any two adjacent veneer sheets are arranged with the wood grain thereof oriented perpendicularly to each other, laminated veneer lumber (LVL) in which constituent veneer sheets are laminated together with the wood grain thereof extending parallel to each other, etc. have been known in the art.
General demand for the wood board or panel is changing from plywood to a wood board such as oriented strand board (OSB), which is also referred to as waferboard, wherein the constituent element thereof is not veneer, but smaller pieces of wood called strands which are arranged with the wood grain thereof discrete or interrupted. A reason for such increasing demand for OSB is its greater in-plane shear strength as compared with plywood.
FIG. 6(A) schematically shows plywood in which one of two adjacent veneer sheets thereof has its wood grain extending substantially parallel to one side of the plywood board and the other of the two adjacent veneer sheets has its wood grain extending substantially perpendicular to the above one side of the plywood board, while FIG. 6(B) shows plywood of another type in which two adjacent veneer sheets thereof have their wood grain extending diagonally in opposite directions at about 45° so that the wood grain of the two veneer sheets are oriented perpendicularly to each other (straight and dotted lines in the square frame represent the wood grain directions of the two adjacent veneer sheets, respectively). FIG. 6(C) shows particleboard (PB). Values provided below the square frames in FIG. 6 represent the shear strengths of the respective board materials.
It has been known in the art that plywood which is made by clipping veneer sheets and arranging such clipped veneer sheets with the grain thereof oriented diagonally at about 45° with respect to the ends or lateral sides of the plywood board, as shown in FIG. 6(B), has a shearing strength that is greater than that of particleboard. As shown in FIG. 5, it has been also known that the shear modulus becomes the greatest when the veneer sheets are arranged with the wood grain thereof oriented diagonally at about 45° with respect to shear plane. It has been known in the art, therefore, that veneer sheets may be cut and arranged as shown in FIG. 6(B) to overcome drawbacks of conventional plywood.
Since it is considered that particleboard (PB) shown in FIGS. 5 and 6 has substantially the same elements orientation as the aforementioned OSB, the strength of particleboard is substantially the same as that of OSB and the following description will be made based on such assumption.
However, no such plywood is seen in actual market that is strengthened as described above. A decisive reason for such disuse is that cutting the existing plywood boards for production of the above plywood board will waste substantially half of the material. Thus, even the possibility of the presence of plywood or veneer laminated board of the above-described structure has been very little considered. If the veneer laminated board which overcomes the drawbacks of conventional plywood by having its constituent veneer sheets arranged and laminated together with the grain thereof oriented diagonally at about 45° with respect to the ends or lateral sides of the resulting board is reasonably manufacturable, demand for such board having outstanding characteristics and performance will be created and the provision of such board will be desired by the market.
As shown in the Publication of Laid-open Japanese Patent Application, No. H9-248803, it has been known in the art that a plywood board may be reinforced by providing between any two adjacent veneer sheets of the plywood board an additional veneer sheet whose wood grain are oriented at about 45°, or an angle between 20° and 70°, with respect to the ends or lateral sides of the plywood board.
However, according to this method in which ordinary rotary-cut veneer sheets are clipped diagonally into lozenged or diamond-like shaped veneer sheets, each lozenged veneer sheet is further clipped into a smaller-sized rectangular veneer sheet by cutting off triangular end portions and such rectangular veneer sheet is laminated between any two veneer sheets in the plywood. However, this method of manufacturing plywood is disadvantageous in terms of labor cost and material cost.
According to the method of manufacturing diagonal laminated veneer lumber of the present invention, the constituent veneer sheets are laminated together with the wood grain thereof oriented diagonally with respect to the longitudinal ends or the lateral sides of the resulting board, as a result of which a wood board having a high strength can be produced. Specifically, the method of the present invention is advantageous in that conventional machines and equipment for peeling veneer sheet and clipping such veneer sheet and also the conventional manufacturing line can be used for mass production of the diagonal laminated veneer lumber of the present invention with a small cost and no waste of material.
Such technical and economical effects can bring about other effects as follows.
(1) Presently, no wood board having an in-plane shear strength corresponding to that of OSB is manufactured. The advent of the diagonal laminated veneer lumber of the present invention, whose strength is greater than OSB, can be a new promising product for the plywood industry.
(2) Further processing the diagonal laminated veneer lumber, various kinds of wood products with high performance such as horizontal members or beams and structural wall board can be provided.
(3) One of typical applications where OSB is used in large quantities in North America is the web for I-beam (also called as I-joist), which is due to high in-plane shear strength of OSB as compared with plywood. Since the diagonal laminated veneer lumber has an in-plane shear strength that is still greater than that of OSB, the diagonal laminated veneer lumber can be an effective OSB replacement capable of providing I-beam of a still higher performance.
(4) As described above, using the diagonal laminated veneer lumber of the present invention, horizontal structural member with high strength capability can be made. Thus, the use of such material makes it possible to design a long-spanned architecture with a higher degree of freedom, and the quantities of wall, beam and pillar members for use and hence the total cost for such architecture can be reduced.
(5) Cedar that is one of the typical species of wood in Japan has been suffering from sluggish demand. Cedar has a high strength for its lightweightness and such characteristics of cedar can be enhanced to the greatest extent by the present invention. Thus, cedar can be utilized as a new material and the invention can contribute to promoting the demand of cedar. Additionally, the present invention can be used to promote the effective utilization of wood available from thinning forest.

Diagonal laminated veneer lumber and method of manufacturing the same


The present invention provides a method of and an apparatus for connecting terminals between switches wherein a connection of terminals via a plurality of switches can be established using a necessary minimum number of lines. In order to additionally connect, where terminal 1 and terminal 2 are interconnected via a plurality of switches and lines, terminal 3 to the connection, information, with which it can be identified which one of two switches is nearer to the added terminal, is stored into a short distance memory of each of the switches, and the terminal connection between the switches is adjusted using the short distance memories so that, from among the transit switches and transit lines, the line of the switch which is nearest to the added terminal may be connected to the added terminal. Or, information, with which, for each of occupied terminals, a switch or switches in which a called terminal or terminals are accommodated can be identified, is stored into the connected switch memory of each of the switches, and the terminal connection is adjusted between the switches using the connected switch memories so that, when one of the originating terminal and the terminating terminal and the added terminal are accommodated in one of the switches, the line of the switch and the added terminal may be connected to each other.

1. Field of the Invention
This invention relates to a terminal connection method for a switch, and more particularly to a method of and apparatus for connecting terminals where a network is formed from a plurality of switches.
2. Description of the Related Art
Conventionally, in order to connect terminals via a plurality of switches, a line from an originating switch in which a terminal which has developed a request for connection is accommodated to a terminating switch in which another terminal to which the terminal is to be connected is accommodated is acquired, and connection request information is sent out from the originating switch to the terminating switch.
More particularly, as shown as a conventional example in FIG. 1(a), when a calling person performs, while telephone 64 and telephone 65 are first connected to each other via switches 61, 62 and 63 and lines 67 and 68, a dialing operation in order to call telephone 66 which belongs to switch 63 from telephone 64, dial information is sent to switch 63 via line 69 and switch 62 as well as line 70.
Then, switch 63 connects telephone 66 corresponding to the received dial information to line 70 to establish three-party communication by telephones 64, 65 and 66. In this instance, four lines are used to interconnect telephones 64, 65 and 66.
Meanwhile, as shown as another conventional example in FIG. 1(b), when telephone 64 and telephone 65 are first in a mutually connected condition via switches 61, 62 and 63 and lines 67 and 68 and then a calling person performs a dialing operation in order to call telephone 66 which belongs to switch 62 from telephone 64, dial information is sent to switch 62 via line 69.
Then, switch 62 connects telephone 66 corresponding to the received dial information to line 69 to establish three-party communication by telephones 64, 65 and 66. In this instance, three lines are used to interconnect telephones 64, 65 and 66.
Here, the problem of the prior art resides in that, as the scale of the switched network increases, the number of times by which a situation that an all busy condition of lines is encountered and a necessary service cannot be provided when it is required occurs increases. Accordingly, in order to improve the service capability, a large number of line equipments must be installed.
The reason is: in order to connect terminals via a plurality of switches, a line from an originating switch in which a terminal which has developed a request for connection is accommodated to a terminating switch in which another terminal to which the origination terminal is to be connected is accommodated is acquired, and connection request information is sent out from the originating switch to the terminating switch. Therefore, as the number of switches via which the connection request information is transmitted increases, also the number of lines used increases, and also the probability that an all busy condition is encountered increases.

Method of and apparatus for connecting terminals between stations


The electronic toy of the present invention utilizes numerous switches to detect (1) the actuation of the toy, (2) the identity of a theme card (containing distinct indicia) inserted into the toy, and (3) the position of an indicia selector in relation to the indicia on the theme card inserted in the toy to produce, card specific, and more specifically, card and indicia specific sensory output.

Children enjoy imaginative play, particularly, role play. Such role play toys can provide hours of creative, engaging play for children. Interactivity between the toy and the child using the toy is an important feature. Such role plays also serve other purposes, such as an educational purpose, for instance, reinforcing time-telling, direction following, communication, and other pragmatic social skills. Thus, an interactive, role play toy that provides a wide variety of play patterns that include audio output and visual interaction is highly desirable.


A pumping mechanism is disclosed that includes a plurality of peristaltic pumping actuators configured to selectively and sequentially compress adjacent portions of a first portion of an at least partially compressible pumping element having an inlet that is upstream of an outlet. The plurality of pumping actuators are further configured to reciprocate at a common drive frequency with a first phase offset between each adjacent pair of pumping actuators. The pumping mechanism also includes at least one compensation actuator arranged to selectively compress a second portion of the at least partially compressible pumping element that is disposed between the first portion and the outlet. The at least one compensation actuator is configured to reciprocate at an optimal displacement and at a modulation frequency that is an integer multiple of the fundamental drive frequency and with a second phase offset between the at least one compensation actuator and the adjacent pumping actuator.

1. Field
The present disclosure is related to peristaltic pumping systems and, in particular, intravenous (IV) pumps that include peristaltic pumping systems.
2. Description of the Related Art
Patients in hospitals often receive medications and medical fluids via infusion using an IV pump. One traditional configuration of IV pump uses peristaltic manipulation of a segment of tubing of an IV set to create the flow of medical fluid to the patient. This type of pumping mechanism is simple and reliable and the pumping segment of the IV set is a straight piece of flexible tubing, making this a relatively low-cost IV set.
One drawback to a peristaltic pumping system is that the flow rate varies with time as the "wave" created by the motion of the peristaltic actuators reaches the outlet of the pumping system. The instantaneous flow rate varies about an average flow rate. This variation can result in clinically significant instability of the patient when medications having short response times (half-lives) are being administered to regulate the function of critical organ systems.

System and method for improved flow uniformity in a peristaltic pump mechanism


An image processing apparatus which is adapted for image processing for reading/writing a large amount of data from/into an RAM and which has a high processing speed. A DRAM bus to which an SDRAM unit is connected is connected to a CPU bus through a bus driver so that a CPU can read/write data from/into the SDRAM unit directly to perform synchronous input/output processing between the CPU and the SDRAM unit. Thus, high speed data transfer can be performed, and the driving capability of the RAM bus is heightened by the bus driver so that the capacity of the SDRAM unit can be made large. Consequently, data can be transferred to a large capacity of SDRAM which can store a large amount of data necessary for image processing to make it possible to provide a printer which is both high in processing speed and has a high data capacity.

1. Field of the Invention
The present invention relates to an information processing apparatus adapted for dealing with a large amount of image-forming data in a printer controller, or the like.
2. Summary of the Related Art
FIG. 6 shows the schematic configuration of a printer 1 such as a laser printer, or the like, for performing page printing, which does not embody the present invention. This printer 1 has an image processing portion 5 for receiving print input data from a host side such as a personal computer, or the like, and converting the input data into output data configured so as to be able to be printed by a printing mechanism or engine 2 provided for performing printing on printing paper (or other appropriate recording medium) on the basis of the output data.
The image processing portion 5 includes an input interface circuit portion 11 for receiving input data from the host, a program storage ROM 15 which stores a program, or the like, for interpreting the input data and for converting the input data into output data for generating an image. The image processing portion 5 also includes a font storage ROM 16 which stores font bit map data to convert the input data into data allowed to be printed actually, and a DRAM 14 for storing the output data or storing intermediate data, or the like, generated in the middle of conversion of the input data into the output data. These constitutional parts are connected, through a bus 17, to a CPU 13 which controls conversion in accordance with the program stored in the ROM 15.
After the data input from the host is converted into output data in the image processing portion 5, the output data is supplied to the printing mechanism 2 through a video interface circuit portion 12 connected to the bus 17. As a result, printing is performed page-by-page.
The video interface circuit portion 12 is provided with an FIFO memory for temporarily storing DMA-transferred output data, and a shift register for converting parallel data outputted from the FIFO memory into serial data. Accordingly, the output data serialized in the raster direction is transferred to the printing mechanism 2. Further, control signals such as a command signal, a status signal, etc., can be exchanged between the CPU 13 of the image processing portion 5 and the printing mechanism 2 through the video interface circuit portion 12 so that the CPU 13 can control the printer 1 as a whole.
The image processing portion 5 having the ROMs 15 and 16, etc., connected to the bus 17 to which also the CPU 13 is connected, can be provided inexpensively if the CPU 13 can make direct access to the ROM 15, or the like, at a low speed. However, because it is impossible to use any high-throughput processor as the CPU 13, the image processing portion 5 is unsuitable for processing a large amount of data at a high speed.
Therefore, as shown in FIG. 7, a CPU 18 capable of operating at a high speed is used in a printer 1 for processing a large amount of data at a high speed. In the case where the CPU 18 operates with respect to low-operating-speed memories such as ROMs 15 and 16, etc., a system is employed in which the operating speed difference between the CPU 18 and the ROM 15, or the like, is absorbed by a memory controller 20 connected to the CPU 18 through a high-speed CPU bus 19.
In the image processing portion 6 shown in FIG. 7, the CPU bus 19 and the memory bus 17 connected to memories are independent of each other, so that internal processing can be made at a high speed by using the high-speed CPU 18. However, because the processing speed of the CPU 18 is dominated by the operating speed of memories such as DRAM 14, ROMs 15 and 16, etc., when access is made to these memories, the overall processing speed in the image processing portion 6 cannot be increased significantly despite the fact that the CPU 18 has a heightened operating frequency.
Although the processing speed of the DRAM 14 is relatively high compared with the processing speed of the ROMs 15 and 16, it is of greater importance to improve the input/output processing speed of the DRAM 14 in order to deal with a large amount of data in the image processing apparatus. A synchronous DRAM (hereinafter referred to as SDRAM) supplied with a synchronous clock pulse signal and capable of reading/writing data in accordance with the input clock has been developed so that, for example, the SDRAM can be operated at the same speed as that of the CPU 18 if the SDRAM is supplied with a clock pulse signal of the same operating frequency as that of the CPU 18. Accordingly, the operation of reading/writing a large amount of output data or intermediate data can be carried out at a high speed, so that the processing speed of the image processing portion 6 can be improved.
Because reading/writing is performed through the CPU 18 and the memory controller 20 even in the case where such an SDRAM is used as the DRAM 14, the time for processing in the memory controller 20 is required. Further, because not only the DRAM 14 but also the ROMs 15 and 16 and other interface portions are connected to the memory bus 17, the length of wiring for transmitting signals becomes large. Accordingly, the transmission speed becomes low and reflection as well as radiation noise of signal lines becomes large, so that the operating frequency is limited. Accordingly, the SDRAM capable of operating at the same speed as that of the CPU 18 cannot be utilized effectively.
It is therefore an object of the present invention to provide an image processing apparatus which is so high in processing speed as to be adapted for image processing in which a large amount of data are read-from/written-in a DRAM.
It is another object of the present invention to provide an image processing apparatus in which a large capacity of DRAM is set in the image processing apparatus so that a large amount of data can be inputted/outputted in a short time, and a CPU can make access to the DRAMs at a high speed.
It is a further object of the present invention to provide a printer using the aforementioned image processing apparatus to make image processing speed high to thereby perform high-resolution printing at a high speed.
Further, conversion of a large amount of input data into image-forming output data is required not only in the case of a printer but also in the case where an image is displayed on a display unit.
It is therefore a further object of the present invention to provide an information processing apparatus in which a large amount of data are processed in a short time so that the data can be written-in/read-from a large capacity of DRAM at a high speed.
According to the present invention, therefore, a RAM for storing a large amount of intermediate data or output data for image processing is connected not to a memory bus but to a CPU bus through which data can be directly read-from/written-into the CPU. That is, according to the present invention, an image processing apparatus is provided for converting input data into image-forming output data by using programs or font data stored in at least one ROM unit, and for outputting the image-forming output data. The image processing apparatus according to the present invention includes a CPU, at least one RAM unit for storing at least one of output data or intermediate data converted by the CPU, a memory controller for controlling access to the ROM unit and the RAM unit, a first bus to which the memory controller and the CPU are connected, and a second bus to which the memory controller and the ROM unit are connected. The RAM unit is connected to the first bus.
As described above, the RAM unit, which is capable of performing high-speed processing compared with ROM, is disposed in the vicinity of the CPU so that the CPU can access the RAM unit directly without going through the memory controller. Accordingly, the speed of processing between the CPU and the RAM unit can be improved greatly. Particularly in the image processing apparatus, input/output processing of output data or intermediate data with respect to the RAM unit occupies a large part of the content of processing. Accordingly, when this input/output processing time is shortened, the processing speed of the image processing apparatus as a whole can be improved greatly.
Further, when an SDRAM is utilized as the RAM unit connected to the first bus, the RAM unit can be operated by an operating clock signal which has the same operating frequency as is used in the CPU. Accordingly, reading/writing data from/into the RAM unit can be performed without reducing the processing speed of the CPU and without providing any wait state.
Further, in the image processing apparatus, a large amount of data are inputted into/outputted from the RAM unit. Accordingly, it is necessary to provide a plurality of RAM units. Therefore, when RAM units are connected to a third bus connected to the first bus through a bus driver, a high-speed stable operation can be carried out even in the case where a plurality of RAM units or a single large-capacity RAM unit is connected.
In the case where the processing speed of the CPU is further heightened so that the time of signal propagation through the bus driver becomes a problem, it is preferable that the RAM units are connected to the third bus which is connected to the first bus via a pipeline register. By use of the pipeline register, data having appeared in the third bus connected to the RAM units can be supplied to the first bus to which the CPU is connected in accordance with the clock signal after the passage of a predetermined time of one clock or more. As a result, while the apparent propagation delay time can be set between the RAM unit and the CPU, the length of wiring of each bus can be shortened by insertion of the pipeline register. Accordingly, the image processing apparatus is hardly affected by noise, so that high-speed data communication adapted to a high-speed CPU can be made between the CPU and the RAM unit.
This system in which the first and third buses are connected to each other through the pipeline register to exchange data between the CPU and the RAM unit is useful not only for the image processing apparatus but also for an information processing apparatus in which a large amount of data are read-from/written-into the RAM. Further, by use of the image processing apparatus having a CPU capable of performing high-speed data transfer between the CPU and the RAM unit, a large amount of input data for high-resolution color printing can be processed in a short time. This results in a printer which performs high-quality and high-speed printing.

Image processing apparatus, information processing apparatus and printer


A method and apparatus for preparing an orthotic appliance to correct defects in a foot providing the steps of scanning a foot, creating a three-dimensional model of the corrected foot, milling a positive mold of the corrected foot, forming a uniformly thick orthotic material over the positive mold and milling out the bottom of the orthotic appliance. Also provided is a heel bisector for use in preparing an orthotic appliance.

This invention relates to an improved method and apparatus for making an orthotic appliance to improve performance of a person's foot.
Orthotic appliances and methods for preparing orthotic appliances have been the subject of previously issued patents. The following patents disclose various methods for preparing orthotic appliances.
______________________________________ U.S. Pat. No. Inventor ______________________________________ 4,454,618 Curchod 4,510,636 Phillips 4,876,758 Rolloff et al. 5,054,148 Grumbine ______________________________________
These patents disclose methods wherein the top portion of the orthotic, the portion in contact with the foot when worn, is milled by a milling device from a thick block of orthotic material.
The method of preparing an orthotic appliance can affect the material costs involved. For example, a process that requires milling one or both sides of a block of orthotic material wastes the cuttings made in shaping the orthotic. If a rectangular block of material is used as a starting point, material is wasted both in sizing the orthotic and in the cutting of the particular corrections. If sized blanks of material shaped to the person's general shoe size are used, somewhat less material is lost during cutting, but there is the added expense of stocking blanks of various shoe sizes.
Furthermore, if a particular orthotic prescription calls for a medial flange to extend up above the plane of the orthotic to add arch support, an even larger block of material is necessary. The block of material used in cutting out an orthotic with such a flange is necessarily going to be thicker in a process where both sides are milled. Because of the added cost of wasted material, it would be advantageous that a process for preparing an orthotic minimize the material cut away.
It is an object of the present invention to provide an efficient, inexpensive method for preparing an orthotic appliance while still providing an orthotic appliance with desirable properties.

Method for preparing an orthotic appliance


Methods and apparatus disclosed herein include receiving, at a first provider router that is not an edge router, first route information from a provider edge router. The first route information identifies a customer address in a customer network coupled to the provider edge router. The methods also include replacing, at the first provider router, a first next hop address included in the first route information with a second next hop address. The first next hop address identifies the provider edge router and the second next hop address identifies the first provider router. The methods also include advertising the first route information to a second provider router located in a different region than the first provider router.

Virtual private networks ("VPN(s)") are used to transmit a customer's information across a shared provider network while maintaining the privacy of the transmitted customer information. The VPN includes a customer-controlled portion ("the customer network") having multiple, remote sites ("customer sites") and a provider-controlled portion ("the provider network") to link the remote customer sites. Customer edge routers at the customer sites are coupled to provider edge routers located at the edge of the provider network to couple the customer-controller portion to the provider-controlled portion. The customer's information is isolated from other information transmitted via the shared provider network by using separate routing tables to route information on the VPN. The routing tables, also called virtual routing and forwarding instances (VRFs), are installed in each provider edge router. To enable communication between the customer sites attached to different provider edge routers, the routes in the VRFs are shared among the provider edge routers. As a result, the size of the routing tables can become quite large, thereby placing a strain on provider edge routers. In fact, some provider edge routers lack the memory and CPU processing power needed to effectively operate due to the large and ever-growing size of the routing tables.
Wherever possible, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. As used herein, the phrase "in communication," including variances thereof, encompasses direct communication and/or indirect communication through one or more intermediary components and does not require direct physical (e.g., wired) communication and/or constant communication, but rather additionally includes selective communication at periodic or aperiodic intervals, as well as one-time events.

Methods and apparatus to route traffic in a virtual private network


Pesticidal and/or antimicrobial biological agent-infected hard-bodied arthropod cadavers, such as from the family Tenebrionidae are used to control pest and/or microbial infestations in agriculture, commercial and urban environments.

1. Field of the Invention
This invention relates to compositions for preparing formulated hard-bodied arthropod cadavers, such as, for example, from the family Tenebrionidae such as Tenebrio molitor, containing biological organisms having pesticidal and/or antimicrobial activity; compositions containing formulated hard-bodied arthropod cadavers; and methods for preparing and using formulated arthropod cadavers.
2. Description of the Related Art
Control of pest and/or microbial infestations and the direct loss caused by infestations are costly. Myriad approaches have been pursued to control pests. Various pathogenic biological control agents such as species of nematodes, fungi, bacteria, virus, or protozoa can suppress populations of important pests. These biological control organisms are most often applied in aqueous suspension for control of agricultural pests. Their usage is limited by cost and, or inconsistent levels of efficacy in pest supression following field applications.
Entomopathogenic nematodes are just one example of a biocontrol agent which can be formulated into a carrier to control pests. Entomopathogenic nematodes in the genera Steinernema and Heterorhabditis are obligate parasites of insects which can control a wide variety of economically important pests. These nematodes are commercially applied as infective juveniles in aqueous suspension using various agricultural spray equipment, irrigation systems, or injection techniques (Grewal, Entomopathogenic nematology, Gaugler et al. (Eds), CABI, New York, N.Y., 265-288, 2002; Georgis, Formulation and Application Technology, IN: "Entomopathogenic Nematodes in Biological Control, supra, 173-194, 1990; Koppenhofer, Nematodes, IN: "Field Manual of Techniques in Invertebrate Pathology", L. A. Lacey and H. K. Kaya, Eds., 283-301, 200, Kluwer Academic Publishers, Dordrecht). Entomopathogenic nematodes generally infect their host by entering natural openings in the host. Heterorhabditids also have the ability to enter certain hosts through the cuticle using a tooth. After entering a host, symbiotic bacteria are released, the nematodes molt, reproduce, and after 1-3 generations, dauer stage juveniles emerge. The dauer juvenile stage is the only stage that is capable of surviving and infecting new hosts in the natural environment. Infective juveniles enter the host and release symbiotic bacteria which aid in (a) killing the host, (b) providing nutrients to the nematodes, and (c) releasing antibiotics, which prevent invasion by other microbes; the bacteria, however, cannot survive outside of the host in a natural environment (e.g. soil) without the nematode (Poiner, Biology and Taxonomy of Steinemematidae and Heterorhabditidae, In: Entomopathogenic Nematodes in Biological Control, R. Gaugler and H. K. Kaya, Eds., 23-62, 1990, CRC Press, Boca Raton, Fla.). The number of nematodes produced per insect varies among nematode species, and within species in different hosts. Heterorhabditis bacteriophora Poinar, for example, can produce over 50,000 infective juveniles per Tenebrio molitar larva (Shaprio-Ilan and Gaugler, Production Technology for Entomopathogenic Nematodes and Their Bacterial Symbionts, J. Ind. Microbiol. & Biotech., Volume 28, 137-146, 2002).
Entomopathogenic nematodes are important biological control agents for a variety of economically important pests in agricultural and urban environments (Grewal and Georgis, Entomophathogenic nematodes, IN: "Methods in Biotechnology", Volume 5, Biopesticides: Use and Delivery, F. R. Hall and J. J. Menn, Eds., 271-299, 1998, Totowa, N.J., Humana Press, Inc.; Kaya and Gaugler, Entomopathogenic Nematodes, Annu. Rev. Entomol., Volume 38, 181-206, 1993). The nematodes can be mass-produced using in vivo and in vitro methods (Friedman, Commercial production and development, IN: "Entomopathogenic Nematodes in Biological Control", R. Gaugler and H. K. Kaya, Eds., 153-172, 1990, Boca Raton, Fla., CRC Press; Sharpiro and Gaugler, 2002, supra). More wide-spread use of etnomopathogenic nematodes as biological control agents has been limited by cost competitiveness and inconsistent levels of field efficacy (Shapiro-Ilan et al., Factors Affecting Commercial Success: Case Studies in Cotton, Turf, and Citrus. IN: "Entomopathogenic Nematology", R. Gaugler, Ed., 333-356, 2002, CABI, New York, N.Y.).
Research indicates that entomopathogenic nematodes may also be applied in infected cadavers [(Creighton and Fasuliotis, Heterorhabditis sp. (Nematoda: Heterorhabditidae): A nematode parasite isolated from the banded cucumber beetle Diabrotica balteata, J. Nematology, Volume 17, 150-153, 1985; Jansson et al., Field efficacy and persistence of entomopathogenic nematodes (Rhabditida: Steinernematidae, Heterorhabditidae) for control of sweet potato weevil (Coleoptera: Apionidae) in Southern Florida, J. Econ. Entomology, Volume 86, 1055-1063, 1993)]. In this approach, nematode-infected cadavers are disseminated and pest suppression is subsequently achieved by the progeny infective juveniles that exit the cadavers. Laboratory studies indicate that nematode application in infected hosts may be superior to application in aqueous suspension (Shapiro and Glazer, Comparison of entomopathogenic nematode dispersal from infected hosts versus aqueous suspension, Environ. Entomol., Volume 25, 1455-1461, 1996; Shapiro and Lewis, Comparison of entomlopathogenic nematode infectivity from infected hosts versus aqueous suspension, Environ Entomol., Volume 28, 907-911, 1999). Indeed, experiments conducted in the greenhouse indicated superior pest suppression when nematodes were applied in infected-insect cadavers compared to aqueous applied nematodes (Shapiro-Ilan et al., Superior Efficacy Observed in Entomopathogenic Nematodes Applied in Infected-Host Cadavers Compared with Application in Aqueous Suspension, J. Invertebr. Pathol., Volume 83, 270-272, 2003). Additionally, for in vivo mass production, application of nematodes in infected cadavers can be less costly than aqueous application because it requires less steps in the process and is thus less costly (Shapiro-Ilan and Gauger, 2002, supra). Furthermore, Koppenhofer (2000, supra) reported that entomopathogenic nematodes can survive dry conditions for extended periods if they remain inside a host cadaver. Commercialization of nematode-infected cadavers has been prevented due to problems in storage and application (Koppenhofer, 2000, supra). Nematode-infected hosts stick together or rupture during transport and/or application, which results in reduced efficacy. Formulating nematode-infected cadavers by coating them can overcome problems of sticking or rupturing, and can provide shelf-life, stability and ease of handling (Shapiro-Ilan et al., U.S. Pat. No. 6,524,061, Feb. 25, 2003; Shapiro-Ilan et al., Formulation of Entomopathogenic Nematode-Infected Cadavers, J. Invertevr. Pathol., Volume 78, 17-23, 2001).
Various formulations for entomopathogenic organisms are known, however there remains a need in the art for nematode formulations which maintain infectivity and reproduction levels for effective biological control that requires the least amount of formulation and enhances the use of biocontrol agents thereby reducing reliance on chemical pesticides. The present invention, as described below, is different from related art nematode cadaver formulations.

Application of entomopathogenic nematode-infected cadavars from hard-bodied arthropods for insect suppression

The United States as represented by the Secretary of Agriculture

Virginia Polytechnic Institute and State University

Virginia Tech Intellectual Properties, Inc.


An power voltage generating unit for a radio frequency switch includes a first input and a second input respectively configured to receive a first control signal and a second control signal, wherein the first control signal and the second control signal are configured to control which one of a plurality of paths in the radio frequency switch is enabled, and at least one output, configured to output an auxiliary voltage, derived from at least one of the first control signal or the second control signal, that is used to operate the radio frequency switch. The power voltage may be a voltage used to power an inverting circuit used to enable a selected branch as an isolation branch or shunt branch.

Radio frequency (RF) switches are important building blocks in many wired and wireless communication systems. RF switches are found in many different communication devices such as cellular telephones, wireless pagers, wireless infrastructure equipment, satellite communications equipment, and cable television equipment. As is well known, the performance of RF switches may be characterized by one of any number operating performance parameters including insertion loss and switch isolation. Performance parameters are often tightly coupled, and any one parameter can be emphasized in the design of RF switch components at the expense of others. Other characteristics that are important in RF switch design include ease and degree (or level) of integration of the RF switch, complexity, yield, return loss and, of course, cost of manufacture.
FIG. 5 shows a pseudomorphic High Electron Mobility Transistor (pHEMT) RF switch 500 according to the prior art. The RF switch 500 includes an RF common (RFC) input node 501 and two RF output nodes 502, 503. Coupling/DC blocking capacitors are also shown at each of the RFC input node 501 and the RF output nodes 502, 503 but are ignored for purposes of the instant description. Those skilled in the art will appreciate that such capacitors impede the passage of DC current, yet do not appreciably impact an AC signal.
As further shown, several transistors M51, M52, M53, and M54 are arranged to effect RF communication between the RFC input node 501 and the RF output node 502, or between the RFC input node 501 and the RF output node 503. Specifically, the transistor M51 is arranged between the RFC input node 501 and the RF output node 502, the transistor M52 is arranged between the RF output node 502 and ground, the transistor M53 is arranged between the RFC input node 501 and the RF output node 503, and the transistor M54 is arranged between the RF output node 503 and ground. Each of the transistors M51-M54 includes by-pass resistors (which are not labeled with reference numerals) connected between respective drain and source terminals.
Two control signals VC1 and VC2 applied, respectively, to the gates of the transistors M51 and M53 control which path (the RFC input node 501 to the RF output node 502 or the RFC input node 501 to the RF output node 503) will be taken by an RF AC signal input at the RFC input node 501. In the configuration shown, the control signal VC1 is 3.3V, which turns the transistor M51 on. The control signal VC2 is 0V, which turns the transistor M53 off. In this configuration, the RF path is configured to be the RFC input node 501 to the RF output node 502. The transistors M52 and M54 operate to enable either an isolation branch or a shunt branch depending on which path (the RFC input node 501 to the RF output node 502 or the RFC input node 501 to the RF output node 503) is selected. That is, when the control signal VC1 is high (3.3V), a control signal VC1B applied to the gate of the transistor M52 is controlled to be low, e.g., 0V. With the control signal VC1B low, the transistor M52 is off thereby isolating the path between the RFC input node 501 and the RF output node 502. Meanwhile, a control signal VC2B is set high or equal to the control signal VC1 thus turning the transistor M54 on and creating an AC signal shunt path between the RF output node 503 and ground to ensure that no signal (or very little) is present at the RF output node 503 when the RF output node 503 is not selected to output the AC signal received at the RFC input node 501. As shown in FIG. 5, the several control signals VC1, VC1B, VC2, and VC2B are applied via respective resistors (which are also not labeled with reference numerals).
For high power operation for the RF switch 500 shown in FIG. 5, a voltage of a node 525 must be high enough to not only make the transistor M51 forward biased with a positive Vgs over drive (the control signal VC1−"the voltage at the node 525) to reduce turn-on insertion loss, but also to maintain sufficient reverse bias of the transistor M52 (0− "the voltage at the node 525") to avoid turn-on during high power voltage swings.
For a depletion pHEMT device, threshold voltage (Vth) is about −1V. Due to the relatively large leakage current in a pHEMT device, two back-to-back diodes 520, 521 form a Kirchoff Voltage Law (KVL) node. Specifically, with the control signal VC1=3.3 voltage, the drop across the diode 520 is approximately 0.7V, which causes a voltage of 2.6V to be present at the node 525. With a voltage of 2.6V at the node 525, Vgs for the transistor M52 (which is reversed biased) is 0V−2.6V, or −2.6V. The point here is that as a result of the leakage current, the node 525 is set at 2.6V which is suitable for handling high power RF switch operations, and as a result, no auxiliary biasing is needed to support a high power RF switch implemented with pHEMT devices.
Unlike pHEMT device-based RF switches, silicon-based RF switches permit much less leakage current. As such, silicon-based RF switches operating in high power scenarios require special biasing circuitry and voltages to operate properly. There is accordingly a need to provide cost effective ways of providing such biasing circuitry and voltages in silicon-based RF switching devices.

Apparatus and method for obtaining power voltage from control signals


A process for the dyeing of a fibrous article containing fibers of a polyamide polymer with at least one anionic dye. The process includes immersing the article in a liquid dyeing bath of a substantially nonaqueous solvent medium and heating to a temperature at least equal to the dyeing transition temperature of the fiber. The anionic dye is added to the dyeing bath so that the rate of dye addition is the primary control over the rate of dye uptake by the article.

The present invention relates to the dyeing of fibrous articles containing polyamide fibers with anionic dyes.
Anionic dyes such as acid dyes and pre-metallized dyes are widely used for the dyeing of polyamide fibers in which the nitrogen-containing groups of the polyamide polymer serve as dye sites. In conventional dyeing processes using such dyes, articles containing the polyamide fibers are immersed in an aqueous bath containing a solution of the dye after any pre-treatment processes such as scouring. While a wide variety of dyeing equipment is used, it is typical for all of the dye to be used in the process to be present in the bath initially. The bath containing the dye and the article to be dyed is also usually at a low initial temperature, e.g., 80.degree.-120.degree. F. (26.7.degree.-48.9.degree. C.) increased gradually to an elevated temperature often as high as the boiling point as the dyeing progresses.
While high quality dyeing can be achieved using the conventional dyeing process for some acid dyes such as small molecule "levelling" dyes, dye cycles to achieve levelling with such anionic dyes are sometimes extremely long and are therefore costly. Moreover, with large molecule acid and pre-metallized dyes which are desirable for applications requiring good light and/or wash fastness, there are often severe dye uniformity problems associated with the conventional dyeing process.
Large molecule acid and pre-metallized dyes are often referred to as "structure sensitive" dyes since non-uniform dyeing can result from even minor, and otherwise undetected, variations in the fiber physical structure. While dye-levelling and/or retarding agents can be added to the dye bath to improve dyeing uniformity, such agents sometimes provide only limited increases in dye uniformity and usually have disadvantages including increased initial expense and higher cost to treat the spent dyeing bath. In addition, because of their retarding effect, such chemical agents can sometimes increase dyeing cycles or make it difficult to obtain deep colors or dark shades. Also, dye yields from anionic dyes, i.e., the strength of color produced from a given quantity of dye on the fiber, are sometimes not as high as desired.
Conventional dyeing processes employing aqueous dyebaths typically generate large volumes of wastewater containing substantial quantities of dye and/or chemicals. Disposal of such wastewater is expensive because extensive waste treatment processes may be required before such wastewater can be discharged.

Nonaqueous polyamide dyeing process utilizing controlled dye addition


A method of improving edge rendering of objects includes dilation (or contraction) of an object's tag plane by one or more pixels into the surrounding region, with the adjacent tag region having a corresponding contraction (or dilation). The objects of interest (e.g., white text) are first identified; the corresponding object tag plane is then spread or choked, in a fashion analogous to trapping. In the case of negative text on a tint background, by expanding the tag plane for the negative text object, the text hint would be forced one pixel into the tint object plane everywhere along the perimeter of the negative text. This could then enable greatly improved negative text rendering.

Quite common among digital front ends (DFEs) is the ability to identify object types (text, image, strokes, fill, line art, etc.) embedded in a given page description language (PDL) master. These object types can then be used to optimize the processing of the contone data prior to transmission to the print engine. For some engines, it is possible to supply rendering "hints" or "tags" for each pixel, allowing the engine to optimally render the objects on the page, pixel by pixel. For example, for some printers, the tags are simply halftone screen specifications, and the DFE has complete control over the way each pixel is rendered. Other engines also have the capability to accept tags or hints to optimize rendering, and these are generally assigned based on the object type. For these engines, a tag or hint tells the rendering engine which rendering conditions to use for a particular object. These tags or hints are generally specified for the entire object. Positive tinted text on white, in the case of some printers, is assigned the "text" hint. For some printing systems, for example the Xerox iGen3, the text hint may instruct the engine rendering module to place high-resolution-outline cells at the perimeter of the object (while rendering the body of the text with the default halftone); this technique will generally improve the sharpness of the text. Similarly, negative (white) text on a tinted background may receive the "text" hint, and the background may receive the "fill" hint. For some printers, such as iGen3, outlining is explicitly disabled for the "fill" hint. Since all of the pixels that would be converted to outline cells reside on the "fill" portion of the white text/fill boundary, no outlining would therefore be realized for negative text. This presents a serious image quality defect for white text objects on tinted fills, as the edges of this negative text may appear ragged. The problem can also exist at the boundaries of two different object types in which a hint for one object explicitly disables rendering that would be pleasing at the boundary of the other object.

Method for tag plane growth and contraction for improving object edge rendering


An one wire serial communication protocol method and circuit is provided. The circuit comprises an I/O port, a control machine, a control buffer and a shift register. Date can be transmitted bi-directionally by using one wire, and several different data transmission rates can be used to transmit the serial data.

1. Field of Invention
The present invention generally relates to a serial data communication protocol method and circuit, and more particularly, to a communication protocol method and circuit for bi-directional serial data communication with one wire.
2. Description of Related Art
Data communication method is categorized as serial data communication and parallel data communication. The serial data communication includes the techniques of I2C bus, UART (Universal Asynchronous Receiver Transmitter) and HDQ16 protocol, etc.
FIG. 1 schematically shows a configuration diagram of a conventional I2C bus. As shown in FIG. 1, each device on I2C bus uses SDA (Serial Data Line) 102 and SCL (Serial Clock Line) 104 to transmit data. Data is transmitted uni-directionally with a format of 8 bits serial type on I2C bus. Data also can be transmitted on I2C bus di-directionally, and the standard data transmission rate is 100 kbit/s, although it can be improved to transfer data with a rate of 400 kbit/s.
Transmitting data on the I2C bus is widely accepted currently. FIG. 2, that schematically shows a data transmitting timing diagram of the I2C bus, is used for brief description hereinafter. It is assumed that the Micro-Controller A 106 in FIG. 1 intends to transmit data to the Micro-Controller B 108, and the Micro-Controller A 106 prepares sending data to SDA 102 in interval I of FIG. 2. However, since SCL 104 is in a low level state, the Micro-Controller B 108 will not receive any data from SDA 102. SCL 104 is in a high level state in interval II, in which the Micro-Controller B 108 receives data sent out from Micro-Controller A 106 on SDA 102. Then, SCL 104 turns back to the low level state again in interval III, in which the Micro-Controller B 108 does not receive any data from SDA 102, and the Micro-Controller A releases the usage right of the SDA 102 and the SCL 104.
FIG. 3 schematically shows a block diagram of a conventional UART configuration. FIG. 3 is a partial structure of a whole computer system, and the chip number 8251 (made by Intel is used as the configuration of the UART communication. When the computer intends to sen data to an external peripheral device (not shown), before the transmit buffer 302 sends seri data to the external peripheral device (not shown), the transmit controller 304 performs a confirmation operation with the external peripheral device (not shown) via the TXRDY, TXE, and {overscore (TXC)}
signal lines, so as to confirm whether the external peripheral device (not shown) is ready to receive data or not. Once the external peripheral device (not shown) is ready to receive data the serial data is sent to the external peripheral device (not shown) via the transmission line TXD of the transmit buffer 302, so that the computer can complete the operation of sending data to the external peripheral device (not shown).
Similarly, when the computer intends to receive data from an external peripheral device (not shown), before the receive buffer 306 receives serial data from the external peripheral device (not shown), the receive controller 308 performs a confirmation operation with the external peripheral device (not shown) via the RXRDY, SYNDET/DB, and {overscore (RXC)}
signal lines, so as to confirm whether the external peripheral device (not shown) is ready to send data or not. Once the external peripheral device (not shown) is ready to send data, the serial data is received from the external peripheral device (not shown) via the transmission line RXD of the receive buffer 306, so that the computer can complete the operation of receiving data from the external peripheral device (not shown).
FIG. 4A schematically shows a transmitting timing diagram of a conventional UART configuration. As shown in FIG. 4A, when the computer intends to send data to the external peripheral device, the TXE signal line is in a low level state, and the serial data DATA CHAR1, DATA CHAR2 and DATA CHAR3 are sent to the external peripheral device via the transmission line TXD. While when the TXE signal line is in a high level state, the transmission line TXD stops transmitting the serial data.
Similarly, as shown in FIG. 4, which schematically shows a receiving timing diagram of a conventional UART configuration, whether the computer intends to receive data from the external peripheral device or not is determined based on the status of the BD and RXRDY, and the serial data DATA CHAR1, DATA CHAR2 and DATA CHAR3 are received from the external peripheral device via the receiving line RXD.
In summary, if I2C bus serial communication method having a standard data transmission rate 100 kbit/s and a high speed data transmission rate 400 kbit/s is used to transmit data, it takes a long transmission time for transmitting the great amount of data that is needed for the current environment. Besides, The I2C bus needs two data transmission lines to perform the bi-directional data transmission, which makes it a complicated configuration. If the UART serial communication method is used to perform the bi-directional data transmission, two data lines are still needed and the circuit designed by using UART as the communication configuration is also quite complicated.

One wire serial communication protocol method and circuit


A method, system, and program for dynamic memory management of unallocated memory in a logical partitioned data processing system. A logical partitioned data processing system typically includes multiple memory units, processors, I/O adapters, and other resources enabled for allocation to multiple logical partitions. A partition manager operating within the data processing system manages allocation of the resources to each logical partition. In particular, the partition manager manages allocation of a first portion of the multiple memory units to at least one logical partition. In addition, the partition manager manages a memory pool of unallocated memory from among the multiple memory units. Responsive to receiving a request for a memory loan from one of the allocated logical partitions, a second selection of memory units from the memory pool is loaned to the requesting logical partition. The partition manager, however, is enabled to reclaim the loaned selection of memory units from the requesting logical partition at any time.

1. Technical Field
The present invention relates in general to improved memory management and in particular to improved dynamic memory management of unallocated memory in a logical partitioned data processing system. Still more particularly, the present invention relates to enabling a logical partition to borrow memory from an available pool of unallocated memory managed by a partition manager within a data processing system to maximize use of the total memory in the data processing system.
2. Description of the Related Art
Many computer systems provide for partitioning. Partitioning, which is most typically implemented in server systems, divides the available system resources into logically partitioned groups. In particular, the memory devices, processors, and input/output (I/O) devices are logically partitioned into independent, secure groups of resources. An independent operating system image typically runs on each partition, allowing for multiple operating systems (OSs) to concurrently execute on a computer system, and allowing each partition to function independent of other partitions.
To maintain the independence and security of each logical partition, partition management firmware is typically implemented to manage the allocation of and access to resources for each logical partition. Specifically, with reference to partitioning memory resources, the partition management firmware will allocate a fixed amount of memory from the total available memory to each defined logical partition. The amount of memory allocated to a logical partition is typically decided at partition boot time. Additionally, however, a system administrator may be allowed to change the amount of memory allocated to a logical partition by sending dynamic reconfiguration commands to the partition management firmware to specify the addition or deletion of a specified amount of memory. If the system can meet the reconfiguration request, then the partition management firmware allocates or deallocates memory as requested. While system administrator directed reconfiguration of memory provides some control over memory allocation, it is limited because human intervention is required. In addition, system administrator directed reconfiguration of memory is limited because once memory is allocated, it is owned by the partition receiving the memory, and thus is not accessible by other partitions.
In any computing system, it is typical for the operating system to employ memory saving techniques when the number of free pages within allocated memory reaches a particular threshold. For example, when the number of free pages falls below a safe threshold, the operating system may initiate page stealing to reclaim allocated pages for the free page list.
In a logically partitioned system, however, employing a memory saving technique is not necessarily an efficient use of the total system resources. In particular, in a logically partitioned system, not all the memory resources available within the data processing system may be allocated when one partition reaches a memory use threshold. For example, in a system defined to have four logical partitions, if only two of the logical partitions are actually allocated, then the memory resources designated, but not allocated to the other two logical partitions, remain unused. In addition, it is more common for logically partitioned systems to have access to on-demand memory resources which, when initiated, increase the total memory resources of the system. Thus, a limitation of current logically partitioned systems is that when a partition reaches a memory use threshold, unless the system administrator allocates additional memory to the partition, the partition employs inefficient memory saving techniques, even though there is sufficient free memory in the data processing system.
Therefore, in view of the foregoing, it would be advantageous to provide a method, system, and program for partition management such that when a partition reaches a memory use threshold, then the partition management firmware controls memory loans of unallocated memory to requesting partitions, wherein the partition management firmware can reclaim the loaned memory if the memory is needed for allocation to another partition or the partition can return the memory when it is no longer needed. In addition, it would be advantageous for the memory pool of loanable memory to include on-demand memory, in addition to the fixed memory resources of the data processing system.

Dynamic memory management of unallocated memory in a logical partitioned data processing system

International Business Machines Corporation


A switched mode voltage regulator has a digital control system that includes dual digital control loops. The voltage regulator comprises at least one power switch adapted to convey power between respective input and output terminals of the voltage regulator and a digital controller adapted to control operation of the power switches responsive to an output of the voltage regulator. The digital controller further comprises dual digital control loops in which a first control loop provides high speed with lower regulation accuracy and a second control loop has high accuracy with lower speed. Thus, the digital control system provides the advantages of both high speed and high regulation accuracy.

1. Field of the Invention
The present invention relates to voltage regulator circuits, and more particularly to digital control over a switched mode voltage regulator using dual feedback loops for improved regulation.
2. Description of Related Art
Switched mode voltage regulators are known in the art to convert an available direct current (DC) level voltage to another DC level voltage. A switched mode voltage regulator provides a regulated DC output voltage to a load by selectively storing energy in an output inductor coupled to the load by switching the flow of current into the output inductor. A buck converter is one particular type of switched mode voltage regulator that includes two power switches that are typically provided by MOSFET transistors. A filter capacitor coupled in parallel with the load reduces ripple of the output current. A pulse width modulation (PWM) control circuit is used to control the gating of the power switches in an alternating manner to control the flow of current in the output inductor. The PWM control circuit uses feedback signals reflecting the output voltage and/or current level to adjust the duty cycle applied to the power switches in response to changing load conditions.
Conventional PWM control circuits are constructed using analog circuit components, such as operational amplifiers and comparators. But, it is desirable to use digital circuitry instead of the analog circuit components since digital circuitry takes up less physical space and draws less power. A conventional digital PWM control circuit includes a subtractor that produces an error signal representing the difference between a signal to be controlled (e.g., output voltage (Vo)) and a reference voltage. An analog-to-digital converter (ADC) converts the error signal into a digital signal. The digital error signal is provided to a loop compensation filter having a transfer function H(z) that provides stability for the voltage regulator feedback loop. A digital pulse width modulator (DPWM) then produces a proportional pulse width modulated signal that is used to control the power switches of the voltage regulator.
In order to keep the complexity of the PWM control circuit low, it is desirable to hold the number of bits of the digital signal to a small number. At the same time, however, the number of bits of the digital signal needs to be sufficiently high to provide enough resolution to secure precise control of the output value. If the output voltage needs to be programmable through a large range, it is even more difficult to maintain a small DC error on the subtractor and therefore set point accuracy errors will increase. While the circuit can be made accurate over a wide range by providing adjustable gain and offset, this comes with additional cost and complexity. Moreover, the ADC needs to be very fast to respond to changing load conditions and enable fast transient response of the feedback loop. Current microprocessors exhibit supply current slew rates of up to 20 A/μs, and future microprocessors are expected to reach slew rates greater than 350 A/μs, thereby demanding extremely fast response by the voltage regulator. Very often, fast response time and DC precision are contradictory requirements. The bit size of the digital signal also affects the complexity of the digital circuitry that implements the transfer function H(z) and hence the associated cost.
Thus, it would be advantageous to provide a system and method for digitally controlling a switched mode voltage regulator that overcomes these and other drawbacks of the prior art. More specifically, it would be advantageous to provide a double-loop output voltage control circuit for controlling a switched mode voltage regulator using digital circuitry having better repeatability and accuracy.

Digital output voltage regulation circuit having first control loop for high speed and second control loop for high accuracy


An austenitic stainless steel displaying high temperature oxidation and creep resistance has a composition that includes in weight percent 15 to 21 Ni, 10 to 15 Cr, 2 to 3.5 Al, 0.1 to 1 Nb, and 0.05 to 0.15 C, and that is free of or has very low levels of N, Ti and V. The alloy forms an external continuous alumina protective scale to provide a high oxidation resistance at temperatures of 700 to 800° C. and forms NbC nanocarbides and a stable essentially single phase fcc austenitic matrix microstructure to give high strength and high creep resistance at these temperatures.

Common austenitic stainless steels contain a maximum by weight percent of 0.15% carbon, a minimum of 16% chromium and sufficient nickel and/or manganese to retain a face centered cubic (fcc) austenitic stainless steels crystal structure at cryogenic temperatures through the melting point of the alloy. Austenitic stainless steels are non-magnetic non heat-treatable steels that are usually annealed and cold worked. Common austenitic stainless steels are widely used in power generating applications; however, they are becoming increasingly less desirable as the industry moves toward higher thermal efficiencies by increasing the working temperatures of the generators. Austenitic stainless steels for high temperature use rely on Cr2O3 scales for oxidation protection. These scales grow relatively quickly, and do not function well in environments containing species like water vapor, sulfur, carbon, etc due to inherent limitations of the Cr2O3 scales formed on these alloys. Creep failure of common austenitic stainless steels such as types 316, 321, and 347 has limited the use of these steels at higher working temperatures.
There have been a number of approaches to improving oxidation resistance of austenitic steels for high temperature use. Moroishi et al. U.S. Pat. No. 4,530,720 describes achieving improved resistance by limiting the sulfur content to no more than 0.0035%, carbon to less than 0.1%, and manganese to less than 3%, with silicon from 0.1 to 5.0%. The sulfur content must be very low as the sulfur in an alloy concentrates at the grain boundaries inhibiting the diffusion of chromium, aluminum or silicon to the surface to maintain a protective oxide film at the surface. The C is low with any content included only to improve strength of the steel. If C is used it is preferred to add Ti, Nb, Zr, or Ta to selectively combine with the carbon. Mn is a deoxidizing agent that does not improve the resistance to oxidation. The steel is also improved by the addition of Ca, Mg, Y or rare earth metals that form stable sulfides at up to 0.1%. The silicon is included to improve the oxidation resistance as it forms a desirable oxide at the surface. Although aluminum forms a desirable oxide at the surface Al is limited to only 0.1%, which is an insufficient level to form a protective Al2O3 scale.
Tendo et al. U.S. Pat. No. 5,130,085 teaches the desirability of high Al content, with an Al content of 4 to 6%, C up to 0.2%, Mn up to 2%, Si up to 1%, Mg below 100 ppm, and Ca, Y or a rare earth metal between 30 and 50 ppm by a formulate relative to the quantity of sulfur and oxygen in the alloy. With high levels of Al, the Mg deteriorates the hot workability and is to be avoided. Masayuki teaches that the Al content had to be above 4% or an Al2O3 surface is not formed. Although these alloys form a robust Al2O3 scale, other properties such as creep resistance are inferior. Because of the high level of Al, an extremely high level of Ni is used to maintain the fcc (face center cubic) crystal structure to achieve good creep strength. Al is a strong bcc (body center cubic) phase stabilizer and the bcc polymorph of Fe exhibits poor creep resistance at 500-600° C. The high cost of Ni renders such an alloy economically unviable for many applications.
Kado et al. U.S. Pat. No. 4,204,862 discloses austenitic iron alloys that contain 4.5 to 6.5% Al to give an alumina film. Alloys with less than 4.5% Al lack an alumina film but rather form a spinel oxide surface that spalls and form internal Al2O3. Ni levels of greater than 22% are required for reasonable creep strength and with high Al levels Ni levels of approximately 37% are required for a "creep strength as high as ordinary austenitic stainless steels."
McGurty U.S. Pat. No. 4,086,085 discloses austenitic iron alloys that require 3.5 to 5.5% Al to give an alumina film. Creep resistance is not directly measured, but the patent compares the Fe-20Ni-15Cr-4.5Al alloys disclosed therein to having austenite instability when heated for long periods of time at temperatures of 1000-1200° F. (524-635° C.) and that stability can be achieved at these temperatures only upon increasing the Ni content significantly to about 35%, which significantly increases the alloy's cost. These alloys also suffered from poor hot workability. McGurty U.S. Pat. No. 4,385,934 subsequently disclosed the addition of Y up to 0.1% to provide these alloys with an improved hot workability and resistance to grain growth.
Fukjioka et al. U.S. Pat. No. 3,989,514 discloses austenitic steels with 0.5 to 2.5% Al in conjunction with relatively high levels of Si of 1.5 to 3.5% to achieve a stabilizing subscale of alumina and silica underneath a Cr-rich oxide scale rather than a continuous external alumina scale. Such a scale lacks oxidative stability at high temperatures when exposed to water vapor, C, S, etc. Alloys with both Ti and Nb in the range of 0.10 to 0.12% by weight showed a slight improvement of creep rupture strength at 800° C. relative to Type 310 steel, which has insufficient creep strength for use at high working temperatures such as 800° C.
Ohta et al. U.S. Pat. No. 3,826,689 discloses an alloy having high strength at elevated temperatures. Although Al levels up to 5 wt. % are possible, no Al2O3 scale is reported for these alloys, and no creep state is presented that show high creep strength in an alumina-forming alloy. Again a very high level of Ni is needed to maintain a fcc crystal structure with high Al levels. This structure is achieved by performing a double-heat treatment and water quenching.
Significant gains have been made in recent years in improving creep strength via control of dispersions of MC carbides and carbonitrides (M=Nb, Ti, V) and related phases at the nanoscale. These state-of-the-art alloys currently offer creep strength well above their useful limit from an oxidation standpoint. High temperature creep resistant austenitic steels have been directed to alloy compositions where ultrafine MC carbide dispersions are formed by employment of appropriate processing techniques. These unique stainless steels are described in Maziasz et al. U.S. Pat. No. 4,818,485 and Maziasz et al. U.S. Pat. No. 4,849,169 and are known as high-temperature ultrafine precipitate-strengthened (HTUPS) steels. The inclusion of titanium, vanadium, and niobium were found to give fine carbide particles that contained little chromium carbides or molybdenum carbides and resulting in steels with good creep resistance at 700° C. The creep resistance of HT-UPS steel is comparable to many Ni-based superalloys, which are too expensive for many applications. Unfortunately, the oxidation resistance of their Fe—Cr base oxides scale limits the use of these steels for many applications.
Maziasz et al. U.S. patent application Publication 2004/0191109 discloses stainless steels for improved heat resistance. In one embodiment Al can be included up to 5% by weight to provide an alumina scale. Although the use of this relatively high level of Al yields an alumina scale that provides oxidation resistance, the inclusion of a high level of Al in these alloys results in poor creep characteristics for all tested compositions with Al, as illustrated in FIG. 1 for the Al containing composition disclosed in the application. This poor creep was due to the bcc stabilizing effect of Al, which results in a duplex bcc and fcc matrix microstructure.
It is therefore remains desirable to have an austenitic stainless steel with the creep resistance of the HTUPS steels but with an oxidation resistance provided by an alumina scale. The combination of these features would permit the use of stainless steel in a number of applications that presently require nickel superalloys, or to expand or improve the performance of devices using stainless steel that are limited in their efficiency because of the temperature to which they are constrained due to the poor high temperature properties of the steel. Such applications include components in energy conversion and combustion systems (recuperators/heat exchangers), chemical and process industry components, petrochemical applications, including down-hole drilling. The alloy can be used as a structural component, or as a surface cladding/coating on a less oxidation-resistant substrate or material optimized for other properties such as ferritic stainless steels for ultra-supercritical steam, where high thermal conductivity and low thermal expansion is a critical issue.

Oxidation resistant high creep strength austenitic stainless steel


Provided is a gas cooler for cooling a produced gas on a side from which the produced gas exits, the produced gas being produced by partially oxidizing and gasifying a carbon-containing fuel in a gasification furnace inside a pressure vessel. A distance (SL) between tubes of a tube bundle of a heat exchanger provided inside the gas cooler is set such that the tubes are in contact with each other or adjacent to each other in a gas-flow direction of the produced gas. Since the tubes are in contact with each other or adjacent to each other, a particle flowing with the gas flow is only deposited as a deposited particle in a concave portion between the tubes, whereby the decrease in heat exchange efficiency caused by particle deposition can be suppressed.

An integrated gasification combined cycle (IGCC) has conventionally been developed and put into practical use in order to improve power generation efficiency in a coal-fired power plant, for example.
The integrated gasification combined cycle has advantages in that it uses coal resources with abundant reserves, an air pollutant such as carbon dioxide is emitted less since the thermal efficiency is higher than that of the conventional pulverized coal-fired power generation, and ashes of coal is discharged as vitreous molten slag to have a smaller volume. Accordingly, the development of an integrated gasification combined facility is in progress as a leading technology of the future coal-fired power generation.
The integrated gasification combined cycle here includes: a gas turbine which operates with a fuel that is a coal gas obtained by gasifying coal; and a steam turbine which operates with steam obtained by recovering exhausted heat from the gas turbine (Patent Literature 1).
In recent years, the development of the integrated gasification combined cycle using a pressurized coal gasification furnace is in progress in order to improve power generation efficiency at a coal-fired power plant (Patent Literature 2).
Unlike a conventional combustion boiler, the pressurized coal gasification furnace has a gasification furnace and a gas cooler that are provided in a pressure vessel, the pressure in which is set to 3 MPa, for example.

Gas cooler, gasification furnace, and integrated gasification combined cycle for carbon-containing fuel


‘Elegance LightLavender Splash’ is a new variety of geranium having large flowers and lavender petals with dark red-purple eyes.

The present invention comprises a new and distinct cultivar of Pelargonium domesticum known by the varietal name 'Elegance LightLavender Splash'. The new variety was discovered in Lompoc, Calif. The new variety is a result of cross breeding Light Pink Seedling #4373 (female parent) (unpatented) and Lavender Seedling #3020 (male parent) (unpatented). The purpose of the breeding program was to introduce new regal geraniums that are less sensitive to light and temperature. The new variety is similar in plant type to its female parent, but differs in flower color. Conversely, the new variety is similar in flower color to its male parent, but differs in plant type. 'Elegance LightLavender Splash' is more compact, with earlier and lighter colored flowers than 'Elegance Lavender' (U.S. Provisional patent application Ser. No. 60/603,817). 'Elegance LightLavender Splash' is also very free flowering, has a good response to extra light, and exhibits larger flowers when compared to other varieties known to the breeder. The new variety was first asexually reproduced by cuttings in Connellsville, Pa. The new variety has been trial and field tested and has been found to retain its distinctive characteristics and remain true to type through successive propagations.
The new variety was grown in a glass greenhouse in a 4″ pot in Connellsville, Pa. in a soilless media with constant fertilizer at 200 ppm nitrogen and potassium. The new variety was grown under 16-hour days with supplemental high pressure sodium lamps. The new variety exhibits developed roots at 14 days at an average temperature of 21° C. and has a response time of fifteen weeks from a rooted cutting to flowering in a 12.7 cm. container.

Geranium plant named ‘Elegance LightLavender Splash’


An integrated circuit includes a plurality of internal devices that are tested by setting the states of their data registers to respective levels, first forming a known initialization value and then a functional data value. All the data registers used for testing are coupled as one or more shift registers and by clocking data through a serial scan path, test stimuli can be shifted in and results shifted out. The scan path connections are provided in addition to the usual functional operation signal connections. During functional operation, the data transitions in the scan path signals are disabled to reduce the power dissipation associated with driving the scan path signals.

1. Field of the Invention
The present invention relates to large scale integrated circuits and more particularly to an integrated circuit using a serial scan test with reduced power dissipation.
2. Prior Art
A method used for testing integrated circuits is the scan-path built-in test structure approach. There are many variations to this approach including multiplexed scan, clocked scan, and level sensitive scan design. When incorporating scan-path capability into an integrated circuit (IC), standard register devices are replaced with modified test registers which have a test mode of operation. FIG. 1 shows such a test register 10 for a scan-path structure. The test register 10 has a test data input TDI for receiving test data input signals 11, in addition to the regular functional data input D, for receiving functional data signals 12. Conventional scan enable SE and clock inputs, for receiving scan enable signals 13 and clock signals 14, and a data output Q for output signals 15, are also provided. A series of such test registers are connected together to form a serial shift register or registers allowing test data to be loaded into all the registers in a memory or other device to set up conditions for testing. FIG. 2 shows on exemplary circuit incorporating scan-path testing. After loading test data into the test registers of a device the same scan-path path can be used to observe the result by serial shifting out the state of the registers. Controllability and observability of internal circuit nodes is achieved in this manner and is used for the purposes of fault detection. The integrated circuit may be partitioned for testing purposes into one or more serial shift register chains.
As seen in FIG. 2 conventional scan-path circuits are implemented by connecting the output signal 15 from one register 30 to the test data input TDI of another register 32. In addition to this connection, needed for scan-path capability, the output signal 15 of one register (30) is also coupled to the functional data input D of another register (32) through combinatorial logic or registers 34 to achieve the logic and control functions desired.
A source of power dissipation in an integrated circuit is the charging and discharging of capacitances which occurs when logic signals go through transitions from a high to a low voltage state or a low to a high voltage state. The circuit interconnections between gates and the MOS transistors forming gates both have capacitance that is charged and discharged when logic signals transition. When scan-path signal paths are added to an IC, there is an increase in the capacitance being driven due to the increase in the length of the interconnection and the additional gate load at the test data input of the test register. Thus, an increase in total power dissipation is experienced when scan-path capability is incorporated into an IC. In a large scale integrated circuit there are many such paths that contribute to increased power dissipation.
Further background on scan-path testing is described in Chapter 6 of Submicron ASIC Products Design for Testability Reference Guide 1993, published by Texas Instruments.
Objects
An object of the present invention is to provide an integrated circuit device with a scan-path test structure having reduced power dissipation.

Testable integrated circuit with reduced power dissipation