A method for transmitting data in a multiple input multiple output (MIMO) wireless communication system is disclosed. The method for transmitting a signal to a receiver by a transmitter in a multiple input multiple output (MIMO) wireless communication system includes: generating a bit stream having the size of specific bits through channel coding of data; dividing the bit stream into a first bit stream having a first bit size and a second bit stream having a second bit size; allocating the second bit stream having the second bit size to an antenna sequence codeword on the basis of a signal transmission time; and transmitting the first bit stream having the first bit size to the receiver according to an order of antenna pairs indicated by the allocated antenna sequence codeword.

Field of the Invention
The present invention relates to a wireless communication system, and more particularly to a method for transmitting data in a multiple input multiple output (MIMO) wireless communication system.
Discussion of the Related Art
The present invention relates to a method for transmitting and receiving radio frequency (RF) data, which can provide a more superior BER (Block Error Rate) performance as compared to the SM (Spatial Modulation) scheme for allocating a bit stream to a transmit (Tx) antenna index and the STBC-SM (Space Time Block Coded-Spatial Modulation) scheme in which the STBC scheme is combined with the SM scheme. Prior to describing the present invention, the SM scheme and the STBC-SM scheme will hereinafter be described in detail.
In addition, the present invention modifies a codeword matrix for use in GBD-QOSTBC (Generalized block diagonal quasi-orthogonal space time block code) so that it defines a sequence (composed of an antenna index) capable of being identified by a user equipment (UE) in different ways. GBD-QOSTBC will hereinafter be described in detail.
Assuming that the number of Tx antennas is denoted by MT, the (MT×MT)-sized GBD-QOSTBC codeword matrix is constructed. The Alamouti codeword corresponding to MT=2 is defined as the matrix A(si,sj) as shown in the following Table 1. The symbols si,sj may be complex symbols (i.e., si,sjεΨ) over signal constellation (Ψ).
                                          A                                      (                                                s                  i                                ,                                  s                  j                                            )                                =                      [                                                                                s                    i                                                                                s                    j                                                                                -                                          s                      j                      *                                                                                s                    i                    *                                                                        ]                                                                              (                      where            ,                          i              ∈                              {                                  1                  ,                  3                  ,                                                            …                                                                                2                                            k                                        -                    1                                                  }                                      ,                                                                            j              ∈                              {                                  2                  ,                  4                  ,                                      …                                                                                2                                        k                                                  }                                      ,                          k              =                                                M                  T                                /                2                                              )                                    [                  Equation                                                              1                ]
In the environment (MT=4) based on Equation 1, the QO-STBC code is represented by the ABBA code as shown in the following equation 2.
                              [                                                    A                                            B                                                                    B                                            A                                              ]                =                  [                                                                      s                  1                                                                              s                  2                                                                              s                  3                                                                              s                  4                                                                                -                                      s                    2                    *                                                                                s                  1                  *                                                                              -                                      s                    4                    *                                                                                s                  3                  *                                                                                s                  3                                                                              s                  4                                                                              s                  1                                                                              s                  2                                                                                -                                      s                    4                    *                                                                                s                  3                  *                                                                              -                                      s                    2                    *                                                                                s                  1                  *                                                              ]                                    [                  Equation                                                              2                ]
In Equation 2, a diversity gain capable of being obtained using the ABBA code is still maintained at the value of 2. Therefore, a phase rotation of the (s3,s4) symbol is needed to obtain the diversity gain of 4 corresponding to the number of Tx antennas. The phase-rotated QO-STBC codeword matrix may be defined as shown in the following equation 3.
                              C          4                =                              [                                                                                s                    1                                                                                s                    2                                                                                s                      ~                                        3                                                                                s                      ~                                        4                                                                                -                                          s                      2                      *                                                                                s                    1                    *                                                                                -                                                                  s                        ~                                            4                      *                                                                                s                      ~                                        3                    *                                                                                s                      ~                                        3                                                                                s                      ~                                        4                                                                                s                    1                                                                                s                    2                                                                                -                                                                  s                        ~                                            4                      *                                                                                s                      ~                                        3                    *                                                                                -                                          s                      2                      *                                                                                s                    1                    *                                                                        ]                    =                      [                                                                                A                                                              (                                                                        s                          1                                                ,                                                  s                          2                                                                    )                                                                                A                                                              (                                                                                s                            ~                                                    3                                                ,                                                                              s                            ~                                                    4                                                                    )                                                                                A                                                              (                                                                                s                            ~                                                    3                                                ,                                                                              s                            ~                                                    4                                                                    )                                                                                A                                                              (                                                                        s                          1                                                ,                                                  s                          2                                                                    )                                                                                ]                                              [                  Equation                                                              3                ]
In Equations 2 and 3, s1,s2,s3,s4εΨ may be used, and {tilde over (s)}3,{tilde over (s)}4εejθ1Ψ (where, {tilde over (s)}3=s3·ejθ1,{tilde over (s)}4=s4·ejθ1) may be used. Specifically, in order to modify the Q-OSTBC matrix shown in Equation 3 into a block diagonal matrix (GBD-QOSTBC), a symbol corresponding to an odd index and a symbol corresponding to an even index are defined in different ways in association with the symbols (s1,s2εΨ, {tilde over (s)}3,{tilde over (s)}4εejθ1Ψ) located over the signal constellation. That is, the odd index symbol may be defined as
            s      odd        =                  [                                                            s                1                                                                    s                3                                                    …                                                      s                                                      2                                        k                                    -                  1                                                                    ]            T        ,and the even index symbol may be defined as
      s    even    =                    [                                                            s                2                                                                    s                4                                                    …                                                      s                                  2                                    k                                                                    ]            T        .
The following linear operation is applied to the above symbols, so that new symbols may be defined as shown in Equation 4.
                                          [                                                                                S                    1                                                                                S                    3                                                                    …                                                                      S                                                                  2                                                k                                            -                      1                                                                                ]                    T                =                                                            TDs                odd                                                                                [                                                                                S                      2                                                                                S                      4                                                                            …                                                                              S                                              2                                                k                                                                                ]                        T                    =                      TDs            even                                              [                  Equation                                                              4                ]
In order to discriminate the signal constellation of the newly defined symbols shown in Equation 4, Γ may be defined. In other words, the symbol of Equation 4 may be defined as SjεΓ.
In Equation 4, 2k symbols may be classified into two sets (or two aggregates) according to the odd and even indexes. In this case, the (k×k) matrix T may be a random Hadamard matrix. A phase rotation matrix D for acquiring a maximum diversity gain may be represented by the following equation 5.
                    D        =                  [                                                                      ⅇ                                      jθ                    0                                                                                ⅇ                                      jθ                    1                                                                                ⋱                                                                                ⅇ                                      jθ                                          k                      -                      1                                                                                ]                                    [                  Equation                                                              5                ]
Assuming that the Hadamard matrix
  T  =      [                            1                          1                                      1                                      -            1                                ]  shown in Equation 4 is used, the equation 3 may be re-defined as a block diagonal matrix as shown in the following equation 6.
                                        4                =                              [                                                                                A                                                              (                                                                                s                            1                                                    +                                                                                s                              ~                                                        3                                                                          ,                                                                              s                            2                                                    +                                                                                s                              ~                                                        4                                                                                )                                                                                0                                                                              0                                                                      A                                                              (                                                                                s                            1                                                    -                                                                                s                              ~                                                        3                                                                          ,                                                                              s                            2                                                    -                                                                                s                              ~                                                        4                                                                                )                                                                                ]                    =                                                 [                                                                                S                            1                                                                                S                            2                                                                                -                                                          S                              2                              *                                                                                S                            1                            *                                                                                0                                                                                0                                                                                S                            3                                                                                S                            4                                                                                -                                                          S                              4                              *                                                                                S                            3                            *                                                                                ]                                                          [                  Equation                                                              6                ]
In Equations 4 and 6, the symbols (s1,s2) may be symbols located over the original signal constellation Ψ in which no phase rotation occurs, such that θ0=0 of the matrix D may be decided. In addition, although the conventional QO-STBC codeword matrix (C4) shown in Equation 3 is different from the GBD-QOSTBC codeword matrix () shown in Equation 6, the conventional QO-STBC codeword matrix (C4) and the GBD-QOSTBC codeword matrix () may have the same average BER performance.
In another example of GBD-QOSTBC, the codeword matrix (C8) corresponding to MT=8 may be used. In association with a total of 8 Tx symbols, two symbols are combined into one pair, and symbols of different pairs may belong to the signal constellation having rotated in different phases as shown in the following equation 7.s1,s2εejθ0Ψ, {tilde over (s)}3,{tilde over (s)}4εejθ1Ψ, s5,s6εejθ2Ψ, ŝ7,ŝ8εejθ3Ψ  [Equation 7]
In Equation 7, θ0=0 may be decided. The phase may be determined according to the number of antennas and the modulation order of Tx symbols. Assuming that MT=8 is decided and the BPSK symbol is transmitted,
            θ      1        =          π      4        ,            θ      2        =                  2                π            4        ,            θ      3        =                  3                π            4      may be used. The random Hadamard matrix (T) shown in FIG. 4 may be assumed as shown in the following equation 8.
                    T        =                  [                                                    1                                                              -                  1                                                            1                                                              -                  1                                                                                1                                            1                                                              -                  1                                                                              -                  1                                                                                -                  1                                                            1                                            1                                                              -                  1                                                                                1                                            1                                            1                                            1                                              ]                                    [                  Equation                                                              8                ]
In addition, the codeword matrix (C8) may be represented as shown in the following equation 9.
                              C          8                =                              [                                                                                A                    1                                                                                A                    2                                                                                A                    3                                                                                A                    4                                                                        ]                    =                                                                                [                                                                                S                                1                                                                                S                                2                                                                                -                                                                  S                                  2                                  *                                                                                S                                1                                *                                                                                S                                3                                                                                S                                4                                                                                -                                                                  S                                  4                                  *                                                                                S                                3                                *                                                                                S                                5                                                                                S                                6                                                                                -                                                                  S                                  6                                  *                                                                                S                                5                                *                                                                                S                                7                                                                                S                                8                                                                                -                                                                  S                                  8                                  *                                                                                S                                7                                *                                                                                ]                                                                                A                  1                                            =                                                A                                                        (                                                                                s                          1                                                -                                                                              s                            ~                                                    3                                                +                                                                              s                            _                                                    5                                                -                                                                              s                            ^                                                    7                                                                    ,                                                                        s                          2                                                -                                                                              s                            ~                                                    4                                                +                                                                              s                            _                                                    6                                                -                                                                              s                            ^                                                    8                                                                                )                                                  =                                                                            A                                                                    (                                                                              S                            1                                                    ,                                                      S                            2                                                                          )                                                                                A                      2                                                        =                                                            A                                                                    (                                                                                s                              1                                                        +                                                                                s                                ~                                                            3                                                        -                                                                                s                                _                                                            5                                                        -                                                                                s                                ^                                                            7                                                                                ,                                                                                s                              2                                                        +                                                                                s                                ~                                                            4                                                        -                                                                                s                                _                                                            6                                                        -                                                                                s                                ^                                                            8                                                                                )                                                              =                                                                                A                                                                                (                                                                                S                                3                                                            ,                                                              S                                4                                                                                )                                                                                A                          3                                                                    =                                                                        A                                                                                (                                                                                -                                                                      s                                    1                                                                                +                                                                                s                                    ~                                                                    3                                                                +                                                                                s                                    _                                                                    5                                                                -                                                                                s                                    ^                                                                    7                                                                                ,                                                                                -                                                                      s                                    2                                                                                +                                                                                s                                    ~                                                                    4                                                                +                                                                                s                                    _                                                                    6                                                                -                                                                                s                                    ^                                                                    8                                                                                )                                                                          =                                                                                A                                                                                (                                                                                S                                    5                                                                    ,                                                                      S                                    6                                                                                )                                                                                A                              4                                                                                =                                                                                A                                                                                (                                                                                s                                      1                                                                        +                                                                                s                                        ~                                                                            3                                                                        +                                                                                s                                        _                                                                            5                                                                        +                                                                                s                                        ^                                                                            7                                                                                ,                                                                                s                                      2                                                                        +                                                                                s                                        ~                                                                            4                                                                        +                                                                                s                                        _                                                                            6                                                                        +                                                                                s                                        ^                                                                            8                                                                                )                                                                                =                                                          A                                                                                (                                                                                S                                    7                                                                    ,                                                                      S                                    8                                                                                )                                                                                [                  Equation                                                              9                ]
The matrix A(si,sj) is defined in Equation 1. Assuming that MT=2k=2r is decided at a random condition denoted by r≧2, the GBD-QOSTBC matrix may be generalized as shown in the following 10.
                              C                      2                        k                          =                  [                                                                      A                                                        (                                                                  S                        1                                            ,                                              S                        2                                                              )                                                                                A                                                        (                                                                  S                        3                                            ,                                              S                        4                                                              )                                                                                ⋱                                                                                A                                                        (                                                                  S                                                                              2                                                        k                                                    -                          1                                                                    ,                                              S                                                  2                                                    k                                                                                )                                                                                ]                                    [                  Equation                                                              10                ]
In the codeword matrix shown in Equation 10, a horizontal axis may denote an antenna index, and a vertical index may denote a timeslot index. In the case of MT=6 in which the number of Tx antennas is not denoted by MT=2k=2r, the GBD-QOSTBC codeword matrix may be constructed in association with MT=8. Then, if the last two rows and the last two columns are deleted, the codeword for MT=6 may be constructed.
The SM scheme will hereinafter be described in detail.
In accordance with the SM scheme, binary data is allocated to each Tx antenna index, an antenna corresponding to a bit stream to be transmitted is selected, and the data stream can be transmitted. That is, total amount of information to be transmitted may be the sum of the amount of information allocated to the data stream and the amount of information allocated to the antenna index.
FIG. 1 is a conceptual diagram illustrating the SM scheme. Referring to FIG. 1, it can be recognized that total amount of information to be transmitted is identical to the sum of the amount of information owned by the Tx symbol and the amount of information allocated to the antenna index used to transmit the Tx symbol information. In more detail, assuming that the number of Tx antennas is MT, a maximum of log2MT bits may be allocated to the Tx antenna index. Assuming that the PSK or QAM symbol having the modulation order of M is used, total amount (m) of information capable of being transmitted using the SM scheme may be defined as m=log2(MT)+log2(M). That is, the total amount (m) of information capable of being represented by bits per channel use may be defined as m=log2(MT)+log2(M).
For example, assuming that 3 bits are transmitted per channel use, when the number of Tx antennas is set to 2 and the modulation order is set to 4, the SM scheme may be used as shown in the following Table 1. In Table 1, MT=Nt is set, the number of antennas is an antenna index, and the Tx symbol is an M-PSK or M-QAM symbol.
TABLE 1N1 = 2, M = 4N1 = 4, M = 2InputAntennaTransmitAntennaTransmitbitsnumbersymbolnumbersymbol0001+1 + j1−10011−1 + j1+10101−1 − j2−10111+1 − j2+11002+1 + j3−11012−1 + j3+11102−1 − j4−11112+1 − j4+1
The STBC-SM scheme will hereinafter be described in detail.
It is assumed that the (L×L) STBC codeword is based on L Tx antennas from among a total number (MT) of Tx antennas. Whereas the SM scheme allocates the bit stream to each antenna index, L selected antennas must be continuously used during a timeslot of the STBC codeword length (L) when data is transmitted according to the STBC-SM scheme.
The amount of information (represented by the number of bits per channel use) capable of being loaded on the antenna index and then transmitted may be denoted by
      1    L                ⌊                        log          2                                  (                                                                      M                  T                                                                                L                                              )                    ⌋        .  Therefore, the total amount (m) of information, which is loaded on the Tx symbol (M-PSK or M-QAM) and the antenna index and then transmitted, may be defined as
  m  =                    1        L                          ⌊                              log            2                                          (                                                                                M                    T                                                                                L                                                      )                          ⌋              +                            log          2                                  (          M          )                    .
For convenience of description, it is assumed that
            M      T        =    4    ,      L    =    2    ,            ⌊                        log          2                                  (                                                                      M                  T                                                                                L                                              )                    ⌋        =                  ⌊                                                            log                2                                                    6                                      ⌋            =      2        ,            and                                      M        =          2                    (        BPSK        )            may be used.
2 Tx antennas from among four Tx antennas are selected, and data is transmitted using the Alamouti method during 2 timeslots. 2 Tx antenna indexes are selected from among 4 Tx antenna indexes (1˜4), and 2 bits are allocated as shown in the following Table 2. The STBC-SM codeword corresponding to the selected antenna is shown in the following equation 11. In Equation 11, a vertical axis may denote an antenna index, and a horizontal axis may denote a timeslot index.
TABLE 2Selected antennaAllocated indexesbits(1, 2)00(3, 4)01(2, 3)10(1, 4)11
                                                [                  Equation                                                              11                ]                                                                                χ                1                            =                                                {                                                            X                      11                                        ,                                          X                      12                                                        }                                =                                  {                                                            (                                                                                x                              1                                                                                x                              2                                                                                0                                                                                0                                                                                -                                                              x                                2                                *                                                                                x                              1                              *                                                                                0                                                                                0                                                                                )                                        ,                                          (                                                                                0                                                                                0                                                                                x                              1                                                                                x                              2                                                                                0                                                                                0                                                                                -                                                              x                                2                                *                                                                                x                              1                              *                                                                                )                                                        }                                                                                χ                2                            =                                                {                                                            X                      21                                        ,                                          X                      22                                                        }                                =                                                      {                                                                  (                                                                                0                                                                                x                                1                                                                                x                                2                                                                                0                                                                                0                                                                                -                                                                  x                                  2                                  *                                                                                x                                1                                *                                                                                0                                                                                )                                            ,                                              (                                                                                x                                2                                                                                0                                                                                0                                                                                x                                1                                                                                x                                1                                *                                                                                0                                                                                0                                                                                -                                                                  x                                  2                                  *                                                                                )                                                              }                                                                          ⅇ                    jθ
In Equation 11, it can be recognized that all codeword elements of the codebook χ2 are phase-rotated by θ, such that the distance between symbols defined in two codebooks is maximized, resulting in improved BER performance. The value (θ) may be changed according to the number of Tx antennas and the modulation order, and it is impossible to search for the value (θ) using the closed Form, such that the value (θ) must be experimentally searched for. A detailed description thereof will hereinafter be described with reference to the attached drawings.
FIG. 2 is a conceptual diagram illustrating the STBC-SM scheme. For convenience of description, it is assumed that θ=π/2 is decided as shown in FIG. 2.
x1,x2 may denote BPSK symbols transmitted from respective antennas. Therefore, during two timeslots, one bit is additionally transmitted to each antenna so that a total of 2 bits may be transmitted to the respective antennas. In addition, 2 bits are additionally transmitted to the antenna index, such that a total of 4 bits can be transmitted. In this case, the 4-bit streams may be denoted by u1,u2,u3,u4 as shown in FIG. 2. Assuming that u1,u2 indicates a bit stream allocated to the antenna index and u3,u4 indicates a bit stream allocated to the BPSK symbol and then transmitted, a block diagram shown in FIG. 2 may be acquired.
In the meantime, under the condition that a channel is unchanged during only the timeslot (L<MT), if it is assumed that L Tx antennas are selected from among MT Tx antennas and data is then transmitted at a fixed transfer rate, the STBC-DM scheme transmits some parts of the total amount of Tx data using the SM scheme. As a result, the amount of information, which is located on the Tx symbol and then transmitted, can be greatly reduced as compared to the method for transmitting data using the conventional (L×L)-sized STBC codeword, resulting in acquisition of a BER gain.

Method for transmitting data in multiple input multiple output wireless communication system

INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY


An urgent message apparatus mounted in a vehicle, for transmitting, in an emergency, an urgent message with a backup battery with the use of a low-earth orbit orbiting satellite, detects a current position of the vehicle; a obtaining part obtaining a communication not-possible time zone of the low-earth orbit orbiting satellite, for the current position of the vehicle detected by the position detecting part; calculates a power amount to be consumed when the backup battery is maintained in a transmission standby state during the communication not-possible time zone obtained by the obtaining part; measures remaining power of the backup battery; compares a sum of a power amount required for transmitting the urgent message and the power amount calculated by the calculating part, with the remaining power measured by the measuring part; and determines that charging or replacement of the backup battery is required when the sum is larger.

1. Field of the Invention
The present invention generally relates to an urgent message apparatus mounted in a vehicle, for transmitting, in an emergency, an urgent message with the use of a backup battery by means of a low-earth orbit orbiting satellite, and, in particular, to an urgent message apparatus and system for appropriately warning of timing at which the backup battery should be charged or replaced.
2. Description of the Related Art
An urgent message (or a so-called mayday) apparatus and system are known in which, in an emergency, a backup battery is used, and an urgent message is transmitted with the use of cellular phone telephone network (see Japanese Laid-open Patent Applications Nos. 11-272974, 2000-231686, 2000-324039 and 2000-341196, referred to as patent documents 1 through 4, respectively, for example).
Further, an urgent message apparatus and system are known in which, in an emergency, with the use of a cellular phone instead of an in-vehicle apparatus, and an urgent message is transmitted with the use of a low-earth orbit (LEO) orbiting (not fixed) satellite communication (see Japanese Laid-open Patent Application No. 2001-250183, referred to as a patent document 5, for example).
In the low-earth orbit orbiting satellite communication, in contrast to a case of using fixed satellite communication, a time zone in which communication is not possible may occur even when an earth station is fixed at a same position on the ground, and thus, a system for providing information of a satellite communication possible time or time zone to an earth station user has been proposed (see Japanese Laid-open Patent Application No. 8-181643, referred to as a patent document 6, for example).
It is noted that, nowadays, such low-earth orbit orbiting satellite communication is actually put into a commercial use, for example, by ORBCOMM in the United States, Virginia (see Official site of ORBCOMM, URL: http://www.orbcomm.com/, Oct. 18, 2005, referred to as a non-patent document 1).


A motor apparatus is constructed to compensate for a delay in operation of the motor apparatus, so that the efficiency is improved and noise is reduced over a broad motor rpm range by driving the motor at the optimum timing. The motor driving control circuit of the motor apparatus includes a phase adjustment circuit which inputs signals of the U phase, V phase and W phase output by rotational position signal amplifiers, and performs an adjustment for the respective signals so that the phases are arbitrarily advanced by a ratio corresponding to phase adjustment voltages, an automatic gain control circuit which inputs the output signals of this circuit and the gain of which is feedback-controlled according to the driving currents of the armature coils of the motor, an FG circuit which produces a periodic pulse train from the rotational position signals, and a frequency-voltage conversion circuit which performs a conversion to a voltage corresponding to the frequency of the pulse train, and outputs the converted voltage as a phase adjustment voltage.

1. Field of the Invention
The present invention relates to a phase adjustment circuit which adjusts the phase of a sine wave signal with a first phase, a second phase and a third phase in which the phase difference between the respective phases is 120°, a motor driving control circuit which includes this phase adjustment circuit, and which controls the driving of a three-phase brushless motor such as a spindle motor or the like that causes the rotation of an optical disk, and a motor apparatus including this motor driving control circuit.
2. Description of the Related Art
Conventionally, for example, the motor apparatus disclosed in Japanese Patent Application Laid-Open No. 2002-84772 and Japanese Patent Application Laid-Open No. 2003-111481 is known as a motor apparatus of this type. This motor apparatus is shown in FIG. 4. This motor apparatus 101 includes rotational position detection elements HU, HV and HW which are Hall elements that detect the position of the rotor of the motor and output a rotational position signal, a motor driving control circuit 102 which outputs a PWM signal on the basis of the rotational position signal and a command from a motor control command part (not shown in the figures), and a power driver 103 which causes a driving current corresponding to the PWM signal to flow to the armature coils LU, LV and LW of the motor. The rotational position signal is a three-phase sine wave signal consisting of differential U phase signals HU+ and HU− output by the rotational position detection element HU, differential V phase signals HV+ and HV− output by the rotational position detection element HV, and differential W phase signals HW+ and HW− output by the rotational position detection element HW, and the phase difference between the respective phases is 120°.
The motor driving control circuit 102 includes rotational position signal amplifiers 110 through 112 which are three Hall amplifiers that amplify the rotational position signals HU+ and HU−, HV+ and HV−, and HW+ and HW− at a fixed amplification rate, and output sine wave signals U+, U−, V+, V−, W+ and W−, an automatic gain control (AGC) circuit 113 which advances the phase by 30° for each of the sine wave signals U+, U−, V+, V−, W+ and W−, and which amplifies the signals by a gain corresponding to a control voltage that is output by a torque control circuit 118 and outputs signals UHL, VHL and WHL, and three PWM output comparators 114, 115 and 116 which respectively input the signals UHL, VHL and WHL into the non-inversion terminals, input a triangular wave from a triangular wave generator 117 into the inversion terminals (in common), and output PWM signals of the comparison results. Here, the purpose for advancing the phases of the sine wave signals U+, U−, V+, V−, W+ and W− by 30° is to apply a magnetic field with a timing that causes the rotor of the motor to rotate with maximum efficiency. Furthermore, the torque control circuit 118 outputs a control voltage which controls the automatic gain control circuit 113 in accordance with the driving currents of the armature coils LU, LV and LW, and a torque control voltage TORQUE for controlling the motor rotation speed (motor rpm), which is a command from a motor control command part.
However, there is a delay arising from the wiring and the delay (element delay or circuit delay) caused by the operation of the elements and circuits making up the motor apparatus from the time that the rotational position detection elements HU, HV and HW output the rotational position signals HU+, HU−, HV+, HV−, HW+ and HW− until the corresponding driving currents flow to the respective armature coils LU, LV and LW. The phases are shifted as a result of this delay, so that even if the automatic gain control circuit 113 is set at the optimal phase advance angle of 30°, the magnetic field cannot actually be applied to the rotor at the optimal timing.
Generally, the motor rpm of a spindle motor that causes an optical disk to rotate varies according to the read-out speed and write speed of the optical disk. For example, in the case of a CD-R/RW motor apparatus, read-out is performed at a motor rpm of approximately 4,000 to 10,000 rpm, and writing is performed at a motor rpm of approximately 1,000 to 2,000 rpm. Meanwhile, the above-mentioned delay of the motor apparatus is substantially constant regardless of the motor rpm, and the angle corresponding to this delay increases as the motor rpm increases. For example, if the angle is 1.5° at 1,000 rpm, the angle is approximately 9° at 6,000 rpm. Thus, if the motor rpm increases, there is a great shift from the optimal phase advance angle (30°), so that the efficiency of the motor drops. Furthermore, if the shift from the optimal phase angle is large, the waveforms of the rotational position signals HU+, HU−, HV+, HV−, HW+ and HW− are distorted, and the waveforms of the driving currents of the corresponding armature coils LU, LV and LW are also distorted, so that the noise generated by the motor increases.

Phase adjustment circuit, motor driving control circuit, and motor apparatus


A service layer entity may register to another service layer entity and proactively request to gain access to the local services hosted by the registrar entity. A registrar entity may accept a registree entity's registration request but only grant access of its partial services to the registree entity. If a registree entity does not need to proactively request the services within its registration request message, the registrar entity decides what services may be needed by the registree entity and grants access of those services to the registree entity.

oneM2M Architecture
The oneM2M standard (as provided in neM2M-TS-0001 oneM2M Functional Architecture-V-2.1.0, which is incorporated by reference in its entirety) under development defines a Service Layer called "Common Service Entity (CSE)." FIG. 1 illustrates an exemplary oneM2M architecture that defines a service layer. The Service Layer provides "horizontal" services that can be utilized by different "vertical" machine-to-machine (M2M) systems and applications, such as e-Health, fleet management, and smart homes. Mca reference point 111 interfaces with application entity (AE) 112. Mcc reference point 113 interfaces with another CSE 115 within the same service provider domain and Mcc′ reference point 116 interfaces with another CSE (not shown) in a different service provider domain 117. Mcn reference point 118 interfaces with the underlying network service entity (NSE) 119. NSE 119 provides underlying network services to the CSEs, such as device management, location services and device triggering. CSE contains multiple logical functions called "Common Service Functions (CSFs)", such as "Discovery" or "Data Management & Repository."
Within the oneM2M RESTful architecture, (also known as resource oriented Architecture or RoA) the CSE supports the instantiation of a set of common service functions (CSFs), as shown in FIG. 2. CSF functionality is implemented via resources which are uniquely addressable entities having a representation that can be manipulated via RESTful methods such as Create, Retrieve, Update, and Delete. These resources are addressable using universal resource identifiers (URIs). A resource supports a set of attributes that store relevant information about the resource and may contain references to other resources termed child resources(s). A child resource is a resource that has a containment relationship with a parent resource and whose lifetime is limited by the resource lifetime of the parent
From a deployment perspective, FIG. 3 depicts configurations supported by the oneM2M architecture. oneM2M architecture enables the application service node (ASN), application dedicated node (ADN), the middle node (MN), and the infrastructure node (IN). The ASN is a node that contains one CSE and contains at least one AE. An example of physical mapping is an ASN residing in an M2M Device. The ADN is a node that contains at least one AE and does not contain a CSE. An example of physical mapping is an ADN residing in a constrained M2M Device. An MN is a node that contains one CSE and contains zero or more AEs. An example of physical mapping for an MN is an MN residing in an M2M Gateway. The IN is a node that contains one CSE and contains zero or more AEs. An example of physical mapping for an IN is the IN residing in an M2M Service Infrastructure. There also may be a non-oneM2M node, which is a node that does not contain oneM2M Entities (neither AEs nor CSEs). Such nodes represent devices attached to the oneM2M system for interworking purposes, including management.
Registration
Conventionally, an AE on an ASN, an MN, or an IN performs registration locally with the corresponding CSE in order to use M2M services offered by that CSE. An AE on an ADN performs registration with the CSE on an MN or an IN in order to use M2M services offered by that CSE. An IN-AE performs registration with the corresponding CSE on an IN in order to use M2M services offered by that IN CSE.
The CSE on an ASN performs registration with the CSE in the MN in order to be able to use M2M services offered by the CSE in the MN. As a result of successful ASN-CSE registration with the MN-CSE, the CSEs on the ASN and the MN establish a relationship allowing them to exchange information.
The CSE on an MN performs registration with the CSE of another MN in order to be able to use M2M Services offered by the CSE in the other MN. As a result of successful MN-CSE registration with the other MN-CSE, the CSEs on the MNs establish a relationship allowing them to exchange information.
The CSE on an ASN or on an MN perform registration with the CSE in the IN in order to be able to use M2M Services offered by the CSE in the IN. As a result of successful ASN/MN registration with the IN-CSE, the CSEs on ASN/MN and IN establish a relationship allowing them to exchange information.
In the above described cases, the AE or CSE performing the registration is referred to as a Registree AE or Registree CSE. The CSE on which the AE or CSE is registering is referred to as the Registrar CSE.
Following a successful registration of an AE to a CSE, the AE is able to access, assuming access privilege is granted, the resources in all the CSEs that are potential targets of request from the Registrar CSE.
The followings are some conventional registration regulations:                An AE shall not be registered to more than one CSE (ASN-CSE, MN-CSE or IN-CSE).        An ASN-CSE shall be able to be registered to at most one other CSE (MN-CSE or IN-CSE).        An MN-CSE shall be able to be registered to at most one other CSE (MN-CSE or IN-CSE).        A concatenation (registration chain) of multiple uni-directional registrations shall not form a loop. E.g. two MN-CSEs A and B, cannot register with each other. Three MN-CSEs A, B and C, where A registers to B, and B registers to C, then C cannot register to A.
Conventionally the CSE registration procedure requires the creation of two resources (a <remoteCSE> on the Receiver CSE and a <remoteCSE> on the Originator CSE). The Originator shall be the registree CSE. The Receiver shall be the registrar CSE creating the <remoteCSE> resource initially. FIG. 4 illustrates an exemplary procedure for creating a <remoteCSE> resource. At step 131, originator 121 sends the CREATE Request message. At step 132, receiver 121 processes the registration request message. At step 133, receiver 121 responds with a registration response message that contains the address/URI of the registered CSE. At step 134, originator, upon receipt of the CREATE response message, creates a <remoteCSE> resource locally under its <CSEBase> resource. This resource is representing receiver 121 CSE. Originator 120 provides the appropriate values to all mandatory parameters. At step 135, originator 120 may issue a RETRIEVE Request towards the receiver (same To as for the CREATE request message) to obtain the optional parameters of the <remoteCSE> resource created at receiver 121 as for step 134 (e.g. labels, accessControlPolicyIDs attributes). At step 136, receiver 121 verifies that originator 120 has the appropriate privileges to access the information. At step 137, receiver 121 sends a RETRIEVE response message. At step 138, originator 120 updates the created <remoteCSE> resource for receiver 121 with the information obtained in step 137.
Conventionally, the procedure for AE registration follows the message flow description as depicted in FIG. 5. The Originator is the Registree AE. The receiver (Registrar CSE) allows the creation of the <AE> resource according to the access control policy and information in the applicable subscription profile. The receiver derives the applicable M2M-Service-Profile-ID from the CSE-ID of the Registrar CSE. Note that in FIG. 5, some of the information has been truncated, but may be found in oneM2M-TS-0001 oneM2M Functional Architecture-V-2.1.0.
With reference to FIG. 5, at step 141, if the Registree AE 123 intends to use a security association to perform the registration, a security association establishment procedure is carried out first. At step 142, Registree AE 123 sends the information for the registration CREATE procedure with the following specific information in the CREATE Request message:
From: AE-ID-Stem or NULL.                In case the Registree AE 123 has already registered successfully before, then deregistered and intends to register again with the same AE-ID-Stem value as before, the Registree AE 123 shall include that AE-ID-Stem value into the From parameter.        In case the Registree AE 123 has not registered successfully before and intends to get an M2M-SP-assigned AE-ID-Stem starting with an 'S' character assigned to itself but it does not have any specific value to suggest, it shall set the From parameter to the character 'S'.        In case the Registree AE 123 intends to initiate a fresh registration and has no preference for the AE-ID-Stem value, the From parameter shall be set to NULL.At step 143, the Receiver (e.g., Registrar CSE 124) shall determine whether the request to register the Registree AE 123 meets any of the following conditions. There is a check if the applicable service subscription profile lists a combination of (allowed AE-ID-Stem value and allowed App-ID value) for the Credential-ID and the Registrar CSE-ID that match with the App-ID attribute in the Content parameter of the request and the AE-ID-Stem in the From parameter of the request. The applicable rules for this checking are contained in the <serviceSubscribedAppRule> resource(s) which are linked to by the ruleLinks attribute of the <m2mServiceSubscribedNode> resource(s) associated with the Registrar CSE. At step 144, if the From parameter of the request provides an AE-ID-Stem value, the Registrar CSE checks whether an <AE> resource with an Unstructured-CSE-relative-Resource-ID identical to the AE-ID-Stem value provided in the From parameter of the request does already exist. If so, there is still an active registration using the same AE-ID-Stem on the Registrar CSE and the Registrar CSE shall respond with an error.
With continued reference to FIG. 5, the procedure continues with one for the following cases a)-d), details can be found in oneM2M-TS-0001 oneM2M Functional Architecture-V-2.1.0, which all end in a response of step 149:                Case a) AE-ID-Stem starts with 'S' and AE does not include an AE-ID-Stem (initial registration)—Steps 145a through 148a.         Case b) AE-ID-Stem starts with 'S' and AE includes an AE-ID-Stem (re-registration)—Steps 145b through 148b         Case c) AE-ID-Stem starts with 'C' and AE does not include an AE-ID-Stem (initial registration)—Step 145c         Case d) AE-ID-Stem starts with 'C' and AE includes an AE-ID-Stem (re-registration)—Step 145d Resource Type m2mServiceSubscriptionProfile
Conventionally, the <m2mServiceSubscriptionProfile> resource represents an M2M Service Subscription. It is used to represent all data pertaining to the M2M Service Subscription, i.e. the technical part of the contract between an M2M Application Service Provider and an M2M Service Provider. The serviceRoles attribute of the <m2mServiceSubscriptionProfile> resource contains a list of Service Role IDs (S-RoleID) that are subscribed to in this service subscription.
Service Orchestration Profile
Conventionally, the role of Service Orchestration Profiles is to provide a mechanism for the exchange of service related attributes (i.e. metadata) that can be used for service orchestration as well as other functions such as service discovery. The following attributes are some examples of the Service Orchestration Profile. A profile identifier specifies an identifier of a profile. Profile Semantics specifies a semantic description or an address/link to a semantic description that describes service orchestration attributes contained within the profile. Profile Type specifies the type of profile. Service Orchestration Targets specifies an optional list of targets that service orchestration is to be performed upon (e.g. a service nodes, service layer, or service capability instance). Service Orchestration Schedule specifies scheduling information for when service orchestration is to be performed and/or duration of time for which profile is valid. Service Orchestration Policies specifies policies to qualify performing service orchestration. Service Orchestration Context specifies context information that is applicable to service orchestration. Desired Services specifies the service configuration that an orchestration client is requesting to be orchestrated onto a specified target(s). Supported Services specifies the set of supported services that an orchestration target supports.
Service Layer Message Routing Service
The Message Routing Service is a service that allows a CSE to route and forward messages from its registree AE or CSE (the message may originate from the registree AE or CSE, or the message may be forwarded by the registree CSE) to the target. In general, the Message Routing Service is a service that a registrar entity may provide to a registree entity, and vice versa. The Message Routing Service may be considered as a special service, because by default, the Message Routing Service is mutual and bidirectional. It means that when a registrar entity grants access permission of this Message Routing Service to its registree entity, the registree entity automatically provides the Message Routing Service for the registrar entity as well. Note, this is the default setting of the Message Routing Service, however, the service can be set up as uni-directional. Each of the local services hosted by a SL entity shall have an identifier that is unique among all local services.

This patent is subject to a terminal disclaimer.


A circuit for generating a step-up voltage, in which it can reduce ripples. The circuit includes a high voltage transfer switch, a high voltage switching unit that pumps a high voltage in response to a clock signal and switches the high voltage transfer switch, a high voltage switching controller, which compares a feedback voltage generated by dividing an output signal of the high voltage transfer switch and a variable reference voltage, generates an internal clock signal using the comparison result and the clock signal, and controls the switching of the high voltage transfer switch in response to the comparison result, and a step-up voltage generator that pumps the high voltage in response to the internal clock signal and a plurality of step-up reference voltages and generates an internal step-up voltage. The high voltage transfer switch outputs the internal step-up voltage in response to the output signal of the high voltage switching unit.

1. Field of the Invention
The present invention relates to a circuit for generating a step-up voltage in a non-volatile memory device. More particularly, to a circuit for generating a step-up voltage necessary upon Incremental Step Pulse Programming (ISPP).
2. Discussion of Related Art
Non volatile memory devices, such as a flash memory or EEPROM devices, require a step-up voltage whose voltage level gradually rises upon ISPP. The step-up voltage is internally generated using a voltage higher than an external power supply voltage.
FIG. 1 is a circuit for implementing ISPP employing an externally applied high voltage 25V. It is assumed that the ISPP specification ranges from 16.5V to 21V and a step voltage (STEP) is 0.5V.
Referring to FIG. 1, if an enable signal (EN) is enabled, the external high voltage 25V is output to an output terminal Vout. At this time, to implement the ISPP method, step-up reference voltages (TISPP<7:0>; which may be extended or shortened depending on a step number) are activated from TISPP<0> to TISPP<7> at given intervals. Voltages V0 to V7, which are obtained by dividing the step-up voltage of the output terminal Vout using resistors R1 to R9, are feedback voltages. The voltages V0 to V7 are input to a comparator 11 through NMOS transistors N1 to N8 driven by the step-up reference voltages (TISPP<7:0>), respectively.
The comparator 11 outputs the output signal (Vcom) as a logical low if the level of the feedback voltages V0 to V7 is higher than that of a bandgap reference voltage (Vbg), which is set to 1V. A NOR gate NR1 performs a NOR operation on the output signal (Vcom) of a logical low and an output signal of an inverter IV1 of a logical low, and makes a node LEAK a logical high. A NAND gate ND1 performs a NAND operation on a clock signal (CLK) and the output signal (Vcom) of a logical low and fixes an internal clock signal (CLK1) to a logical high.
At this time, a high voltage switching unit 12 stops the operation of pumping a high voltage (VPP) using the internal clock signal (CLK1) fixed to a logical high. NMOS transistors N11 to N16 are all turned on to connect a driving node SEL of a high voltage NMOS transistor N10 to the ground (VSS). In this case, the high voltage NMOS transistor N10 is turned off, so that a step-up voltage level of the output terminal Vout is lowered.
Meanwhile, if the level of the feedback voltage (V0 to V7) is lower than that of the bandgap reference voltage (Vbg), which is set to 1V), the comparator 11 outputs the output signal (Vcom) as a logical high. The NOR gate NR1 then performs a NOR operation on the output signal (Vcom) of a logical high and the output signal of the inverter IV1, of a logical low, and makes a node LEAK a logical low. The NAND gate ND1 performs a NAND operation on the output signal (Vcom) of a logical high and the clock signal (CLK), and toggles the internal clock signal (CLK1).
At this time, the high voltage switching unit 12 pumps the high voltage (VPP) according to the toggled internal clock signal (CLK1). The NMOS transistor N16 is turned off and accordingly does not connect the ground (VSS) to the driving node SEL. If so, the high voltage NMOS transistor N10 is turned on so that the step-up voltage level of the output terminal Vout rises.
However, the step-up voltage generating circuit constructed above generates a very high voltage of 25V to a minimum 16.5V without any filtering unit. Accordingly, a very great ripple is generated due to the high voltage of 25V. This makes it difficult to implement ISPP.

Circuit for generating step-up voltage in non-volatile memory device


There are provided a semiconductor light emitting device and a method of manufacturing the same. A method of manufacturing a plurality of light emitting nanostructures of a semiconductor light emitting device includes: forming a plurality of first conductivity type semiconductor cores on a first type semiconductor seed layer, each first conductivity type semiconductor core formed through an opening in an insulating film; forming an active layer on each first conductivity type semiconductor core; forming, using a mask pattern, a second conductivity type semiconductor layer on each active layer to cover the active layer, to form a plurality of light emitting nanostructures; and forming an electrode on the plurality of light emitting nanostructures.

A semiconductor light emitting device such as a light emitting diode (LED) or the like is a device emitting light through a material contained therein. LEDs convert energy generated through electron-hole recombination occurring at p-n junctions between p-type and n-type semiconductors into light to be emitted therefrom. Such LEDs have been widely used as light sources in lighting devices, display devices, and the like, and the development thereof is being accelerated.
In particular, as mobile phone keypads, turn signal lamps, camera flashes and the like using GaN-based LEDs are commercialized, the development of general lighting devices using LEDs is being actively undertaken. As the use of LEDs is extended from small portable devices to large, high output, and high efficiency products such as the backlight units of large screen TVs, the headlights of vehicles, general lighting devices, light sources having the characteristics required by the corresponding products have been demanded.
As the use of semiconductor light emitting devices is increased, a method of improving light extraction efficiency thereof is particularly beneficial.

Semiconductor light emitting device and method of manufacturing the same


A pre-condenser is provided for condensation of water at sub-zero degree Celsius temperatures. A brine solution is cooled below 0 degrees Celsius and delivered to the pre-condenser. The brine solution contacts the vapors and gases from a scrubber, thereby condensing the vapors without allowing ice formation. A vacuum system connected to the pre-condenser removes the remaining gases from a top portion of the pre-condenser while the brine solution and condensed vapors are removed and recycled through a bottom portion of the pre-condenser.

1. Field of the Invention
The present invention relates generally to the field of direct contact pre-condensers. More specifically, the present invention relates to a sub-zero condensation vacuum system for pre-condensing water vapor for creating a vacuum.
2. Background of the Prior Art
In glycerine refining or any other steam distillation under vacuum, condensable and non-condensable vapors must be removed from the process stream in order to complete the refining process. The vapors from the process stream are removed by sending them directly in to a vacuum system in which the vapors can be condensed or otherwise removed.
In the area of condensers, it is known to provide a low pressure region into which vapor can exhaust, the condenser also having a condensate chamber for collecting the condensate.
Traditional vacuum systems, such as a steam ejector with contact or surface condensers, or hybrid systems with steam ejectors with condensers and a liquid ring vacuum pump are currently used to evacuate the gases and vapors in the glycerine refining process and in other such processes that require operation under a vacuum and use sparging or stripping steam.


Fluorophore-labeled collagen covalently bound to a cell culture vessel can be used to assay collagen degradation by a variety of cell types, including osteoclasts and tumor cells. Such assays provide a high throughput platform for rapid screening of large numbers of potential modulators of, for example, tumor metastasis or osteoclast differentiation and/or function.

Collagen degradation is involved in a variety of processes, including bone resorption and tumor metastasis. In vitro assays of the collagen-degrading activity of osteoclasts, for example, are invaluable to the discovery of drugs for the treatment of osteoporosis. "TRAP" (tartrate-resistant acid phosphatase) assays detect acid phosphatase produced by mature osteoclasts via either histochemical or immunohistochemical staining. Other existing assays use synthetic calcium phosphate-based matrices as a surrogate bone substrate to detect osteoclast activity, and culture dishes coated with calcium phosphate upon which osteoclasts can be cultured are commercially available.
Some assays use slices of either dentine or bovine cortical bone as a surrogate bone substrate. Stearns, Clin Exp Metastasis. 1998 May; 16(4):332-9, discloses an assay in which osteoblasts first are cultured with 3H-hydroxyproline. The osteoblasts produce 3H-collagen, which is deposited together with other matrix proteins on a culture plate surface. The osteoblasts are removed, and other cells can then be tested for the ability to degrade the deposited 3H-collagen.
Tumor cells secrete collagenases which degrade extracellular matrix components and aid metastasis. Garbisa et al., Cancer Lett. 9, 359-66, 1980; Liotta et al., Cancer Metastasis Reviews 1, 277-88, 1982. Cell-based assays for potential drugs that would block this process would be useful in identifying anti-metastatic agents.
There is a need in the art for sensitive and convenient cell-based assays of collagen degradation that can be used for rapid screening of potential therapeutic agents.

Methods and tools for detecting collagen degradation


Apparatus and method for slicing a food product having a non-uniform cross-sectional area. A laser line scanner scans the cut face of the food product. A line scan camera receives light reflected from the cut face of the food product. The line scan camera is positioned such that the line field of view of the line scan camera intersects the scanning line of the laser line scanner at the cut face of the food product. A controller determines an area of the cut face of the food product using the light reflected from the cut face of the food product and advances the food product to be cut by the cutting device by an amount such that a next slice of the food product cut by the cutting device will have a thickness such that the next slice will be of the predetermined weight based upon the area of the cut face.

In the food industry, it is common to pre-cut various food products, such as meats, before the food products are dispensed to the consumer. As an example, pork chops are commonly cut from a pork loin and marketed to the consumer individually or in packages with a plurality of pork chops in each package.
Various automated systems have been constructed to perform the task of pre-cutting food products, such as meats, to create individual items for the convenience of the consumer. For example, an apparatus could cut pork chops having a consistent thickness resulting in multiple pork chops having a constant thickness.
However, some food products, including pork loins, have a non-uniform cross-sectional area. The shape of a pork loin is not uniform over its length. A pork loin can be bigger or smaller at one end or the other and may vary in cross-sectional area along its length. As progressive cuts made in the pork loin, the cross-sectional area of the pork loin may vary. Thus, successive pork chops cut from a pork loin may be larger or smaller depending upon the actual cross-section of the pork loin where the pork chop is cut. Thus, cutting a plurality of items (e.g., pork chops) from a food product (e.g., a pork loin) with a constant thickness may result in successive pork chops which can vary significantly in weight.
Food products may be sold by weight. Thus, if the weight of individual pork chops vary, the collective of weight of a package of pork chops may also vary. However, since the package of pork chops is being sold to the consumer by weight, different packages of pork chops (all containing the same number of pork chops) may have different prices. The consumer may then need to select accordingly and purchase a package of pork chops reasonably matching the consumer's expectations.
Food products may also be sold by number of items. For example, a package of pork chops may be sold as a package containing a predetermined number of pork chops irrespective of the weight of an individual pork chop. Since the weight of individual pork chops may vary, the weight of a package of a predetermined number of pork chops will also vary. This may result in the consumer getting more or less (weight) depending upon which package is purchased. Thus, differing packages may be more or less desirable for the consumer to purchase.
However, food products may also be sold requiring a precise number of items and a precise weight for those items, either collectively or individually. This dual requirement will not allow a significant variation in weights among the individual items.
Since the cross-section of a food product, e.g., a pork loin, may vary but the weight of each individual item, e.g., pork chop, must stay the same, then the thickness of each individual item must either vary or another operation must be accomplished following the cutting in order to adjust the weight of each individual item. For example, trimming of the edges of a cut pork chop may be done in order to reduce the weight of each pork chop to be consistent among pork chops. However, not only is manual trimming time-consuming but it also results in a significant amount of wasted material.
Prior art optical systems have been employed to attempt to determine the size of a product being cut and to adjust the thickness of the cut in order to control the weight of each individual item being cut.
U.S. Pat. No. 5,267,168, Antonissen et al, Apparatus For and Method of Controlling Slicing Machine, discloses a slicing machine which includes a control system having a camera which views a cut face of a product being sliced. The processing of the image data includes classifying the image data by comparison with an intensity threshold which is varied automatically in accordance with the populations of data and the different classes. A source of illumination (7) is positioned below the face of the product (3) being cut by blade (1). A camera (6) is also set at an angle with respect to the face of the product (3) being cut by blade (1). The source of illumination (7) illuminates the entire face of the product (3) being cut at one time and the camera (6) senses light from a general area facing the product (3) being cut which includes light from the source of illumination (7) being reflected.
U.S. Pat. No. 5,054,345, Weber, Method of Obtaining Constant Weight Portions or Slices of Sliced Food Products, discloses a method for obtaining constant weight portions or slices from sliced food products where, in each case, individual slices or portions of several slices with exactly predeterminable weight can be formed in real time operation during the cutting process by detecting the cut surface area, taking account of the specific weight and computing of the required feed of the product. A light source (52) is set at an angle α with respect to surface (48) of ham (10). The light (54) remitted or diffusely reflected from surface (48) falls as light beam (54) onto video recorder (56) arranged at an angular specular reflection angle β also with respect to surface (48) of ham (10). Again, the light source (52) illuminates the entire surface (48) of the ham (10) and the video recorder (56) records light including light being reflected from surface (48) of ham (10).
A problem with optical systems intended to determine the cross-sectional area of the food product to be cut is that it is difficult for the sensor to determine what light is reflected from the food product and what light is ambient or is reflected from background clutter. Some systems use an amplitude threshold to filter the incoming light signals. However, ambient light or light reflecting from the background may still be of sufficient amplitude to interfere with a proper determination of the cross-sectional area of the cut face of the food product.

Apparatus for slicing a food product and method therefore