According to the method of the invention, control parameters V indicating speed, R indicating turn characteristics and γ indicating a path angle are determined such that these parameters are maintained between limits, and such that one of them deviates as little as possible from a corresponding control input parameter Ri. In order to maintain (as much as possible) the value of R unchanged, V can be varied. The method may include the calculation of the maximum and minimum thrust available.

The path which an air vehicle must follow during flight, the attitude (the pitch and roll) of the vehicle as well as its speed, are controlled by means of actuators associated to several elements of the vehicle, specifically to its propulsion system (the engines) and to the vehicle control surfaces. In other words, in order for the vehicle to follow a desired path with a desired attitude and speed, it is necessary to generate and send suitable control signals to the actuators, such that the actuation of the propulsion system (including the developed thrust) and the position or orientation of each control surface is suitable so that the vehicle may follow the path as desired. The generation of these signals is usually carried out by an on-board computer system of the vehicle from commands generated by a pilot (which can be on board the vehicle or which the pilot controls remotely from a land control station or a station in another vehicle) by a mission management system or by both.
FIG. 1 shows a flight control system for an air vehicle according to the state of the art. As can be seen, the system includes a mission management module 1 (which can have a stored path, for example in waypoint form, or which can receive flight instructions, for example in waypoint form, preprogrammed maneuvers, or the like, generated by a pilot 1A who may be on board the vehicle or who may transmit instructions to the vehicle from a land control station or a control station in another vehicle).
On the other hand, the flight control system comprises a navigation and guidance subsystem 2 comprising a navigation module 2A—which calculates the ground speed and position of the vehicle with respect to the Earth—and a guidance module 2B, which attempts to correct errors such that the real path and speed adapt to the desired path and speed according to the information supplied to the mission management module. To that end, the guidance module 2B usually comprises control laws, the control variables of which are the errors in the path, for example a PID (proportional, integral and derivative) control system.
The navigation and guidance subsystem receives data regarding the current vehicle conditions from the sensors 3. These sensors may include a GPS system, airspeed detectors, altitude detectors, acceleration and angular velocity detectors (for example, in the form of gyroscopes and accelerometers) as well as magnetometers (which provide a magnetic field measurement and can be used to determine the pitch and roll of the vehicle). The navigation and guidance subsystem usually does not receive the data directly from the sensors 3 but through an estimation module 4 which processes the data from the sensors and provides a series of (supposedly) processed data indicating certain flight conditions, for example the vehicle airspeed conditions, its ground speed, the roll, pitch and position of the vehicle with respect to the Earth, as well as data relating to the state of the actuators 6 controlling the propulsion system (the engines) and the vehicle control surfaces (in the event that the required sensors are arranged).
On the other hand, the flight control system comprises what is usually referred to as a primary control module 5 receiving data (d) with respect to the flight conditions from the estimation module 4, as well as control parameters (p) from the navigation and guidance module 2 (or, in some cases, directly from the mission management module 1). Said control parameters p usually comprise:                a parameter V indicating a desired speed;        a parameter R indicating desired turn characteristics (for example, turning radius, turning speed or angle of roll) (rotation usually relates to the rotation of the projection of the path of the vehicle in a horizontal plane); and        a parameter γ indicating a desired path angle (path angle is usually understood as the angle of the path of the vehicle in the vertical plane with respect to the horizontal plane).
These three parameters V, R and γ may relate to the Earth or air; the transformation of Earth-related parameters to air-related parameters (or vice versa) can be carried out directly once the speed of the air is known.
Based on these parameters p and data d, the primary control module 5 calculates the signals s for the actuators of the vehicle: these signals determine how the control surfaces will be oriented as well as the power that the vehicle engines will provide. The state of the art includes a large number of systems and algorithms which can be used for generating the control signals (s) from the control parameters (p) and data (d) regarding the state and condition of the vehicle.
The parameters (p) which the primary control module 5 receives may include:
A) In the case of a vehicle which must "automatically" follow a predefined path or route (established, for example, by means of a series of waypoints known by a mission management system, or by means of high-level commands from a pilot):                a desired speed of the vehicle;        a desired path angle (i.e. the angle which the path of the vehicle follows in the vertical plane with respect to the horizontal plane); and        a desired turning speed or turning radius for turns in the horizontal plane.
(These control parameters are calculated by the navigation and guidance subsystem 2; a large number of systems and algorithms are known in the state of the art for calculating this type of control parameters from the route data which the vehicle has and from data indicating the flight conditions, therefore it is not necessary to herein describe said systems and algorithms in further detail).
B) In the case of a vehicle flying according to basic instructions commanded by a physical pilot:                a desired speed of the vehicle        a desired attitude of the vehicle, i.e. its pitch and angles of roll.
For at least some of the control parameters (p), or combinations thereof, there are usually limits establishing what is usually referred to as an operational envelope and which are used to prevent the system from accepting values of the control parameters which may represent a danger, for example a reduction of the speed under a minimum speed, a turning radius which may represent excessive stress on parts of the vehicle, etc. These limits may vary over time and be a function of the current flight conditions (represented by the data provided by the sensors 3 and estimation module 4). The limits may further be interrelated, for example the envelope for the turning radius (i.e. the limits between which the turning radius may vary) may depend on the speed, etc.
In unmanned air vehicles, the paths to be followed are many times established beforehand and the mission management module 1 is responsible for generating the control parameters (p); it usually does this through the navigation and guidance subsystem although it is also possible to generate the control parameters without resorting to this subsystem.
In the system shown in FIG. 1, the control parameters can be calculated in the navigation and guidance subsystem 2 taking into consideration the real position of the vehicle with respect to a series of waypoints with the intention that the vehicle follows, in the most reliable manner possible, the originally planned path, which is appropriate for reducing the risk of accidents insofar as it is possible (and furthermore the problem represented by recalculating the routes during the flight). However, unexpected (and often unforeseeable) events often occur, for example changes in the atmospheric conditions, problems in the vehicle equipment, exits from the expected route due to an intervention by the pilot from the land station, etc., causing problems for the vehicle in following the planned path, for example for climbing with the originally planned path angle, for example due to an excess of wind in the flight direction, which would make a greater (aerodynamic) path angle necessary, the necessary power in this case possibly being greater that the available power, or due to the fact that the engines do not allow developing the originally planned power. In these cases, a conventional solution to the problem consists of recalculating the route to be followed, something which however may represent a problem given that it may require a high calculation capacity (which may exceed the capacity of the on-board systems of the vehicle) and certain risks (for example, in the case of an unmanned air vehicle, because the system generating the alternative path may not have relevant data relating to obstacles which may be present in the new path, for example mountains, civil aviation airways, etc.; on the other hand, having such data would entail a great computational cost).
Patent document U.S. Pat. No. 6,493,609 describes an automatic envelope protection system for unmanned air vehicles. Basically, an envelope protection subsystem is intercalated between a navigation system (which may basically produce a series of input control parameters calculated from the data of the expected route, for example waypoints, which the navigation system has) and a control system which must calculate the output control signals for the actuators from said input control parameters. To protect the envelopes, the protection system takes corrective actions to modify the input control parameters before they reach the system calculating the control signals for the actuators; for that purpose it is based, among others, on the data relating to the current state of the vehicle, which allows determining if the vehicle is excessively approaching the limits represented by the envelopes. The attempt is made to maintain the real vehicle conditions within certain limits, not the control parameters which are sent to the control module. The attempt is made to maintain the originally planned path, insofar as it is possible, by applying certain offsets to the actuators for a certain time such that values within the envelope are obtained. The possibility of recalculating the originally planned mission or path so as to offset the alternation of the input control parameters forced by the protection system is provided.
Patent document U.S. Pat. No. 6,711,477 describes a similar system and method for numerically determining the flight envelope. Calculation routines are contemplated which may be complex and require a high calculation capacity.
Patent document US-A-2002/0055809 describes a system in which there is a computer in parallel with the flight control computer which analyzes the risk-entailing conditions using fuzzy logic. The results of the analysis are shown to the pilot in order to take the measurements which he/she considers as appropriate.
Patent document U.S. Pat. No. 6,163,744 describes a system for modifying a flight route as a response to changes in certain parameters. In other words, the flight plan, i.e. the mission, is modified.
It is possible that at least some of the known systems can be used for preventing an air vehicle (manned or unmanned) from exiting its flight envelope. However, this is many times obtained in the known systems by recalculating the route or path to be followed, establishing an alternative route. This may involve several problems: it requires sufficient data and calculation capacity to establish a new "safe" route and/or access to a "preprogrammed" alternative route. It has been considered that it would be desirable to reduce the cases in which it is necessary to recalculate the route or choose another alternative route in order to respect the flight envelope. It has likewise been considered that it would be desirable to obtain that the vehicles substantially adapt to the planned route and that the (possibly temporary) deviations of said route (especially in the horizontal plane) are not greater than which is (strictly) necessary for maintaining the vehicle within its flight envelope. It has further been considered that it would be desirable to achieve these objectives with a system that does not require a high calculation capacity, which is performed in real time and which can be incorporated in the flight control systems already existing on the market with a basic knowledge of the vehicle models and a very small computational cost.

Method for controlling control parameters in an air vehicle and system of controlling an air vehicle

Instituto Nacional de Tecnica Aeroespacial “Estaban Terradas”


A hybrid vehicle control device includes an engine start control unit which, at engine start, starts slipping a second clutch, sets a first clutch to a slip-engaged state, and sets the second clutch transmission torque capacity to less than or equal to a set torque limit value during cranking, maintains the slip state and cranks the engine, and when the engine is put in a drive state, controls the first clutch and the second clutch towards a fully engaged state. The engine start control unit is provided with a second clutch torque increase gradient control unit which, when performing cranking processing, performs first increasing processing for increasing the second clutch transmission torque capacity command value at a first increase gradient, and second increasing processing for increasing said value at a second increase gradient more gradual that the first increase gradient.

Conventionally, a hybrid vehicle is known which includes a first clutch capable of varying a transmitted torque capacity between an engine and a motor generator as drive sources, and a second clutch capable of varying a transmitted torque capacity between the motor generator and a driving wheel side (see a patent document 1, for example). In this conventional art, an engine start control is performed during a shift from an EV mode to an HEV mode, wherein the EV mode is a mode where the vehicle is driven only by a driving force of the motor generator, and wherein the HEV mode is a mode where the vehicle is driven by both of driving forces of the engine and the motor generator with the engine started, as follows. In the engine start control, the second clutch is first made to slip, and the driving torque of the motor generator is made to rise, and the first clutch is thereafter engaged to input a rotation to the engine (i.e. cranking the engine). As the engine rotational speed rises thereafter, the first clutch is engaged, and the second clutch is controlled from slip state toward engaged state.
When the second clutch is slipping, the transmitted torque capacity of the second clutch is limited to a limit value (cranking-condition torque limit value) for maintaining the second clutch in slip state, and is increased along with control of the first clutch toward complete engagement.


The present invention is directed to an improved flute-type instrument having a reduced bore diameter in the head section, a conical bore in the intermediate section and a standard sized bore diameter in the main section. The reduced bore diameter in the head section is dimensioned to closely correspond to the circumferential diameter of the mouth hole opening to promote laminar-like flow of air through the mouth opening and into the head section bore.

Flute-type wind instruments generally consist of a cylindrical tube having a central bore extending therethrough. The cylindrical tube includes a head section having a side hole mouth opening over which air is blown to produce a tone, and a main body section having a series of toneholes to play a range of notes.
The central bore extending through the head section and the side hole mouth opening have a critical effect on the quality of the tone produced by flute-type wind instruments. The primary source of the degradation of tone quality, commonly referred to as the "hissing sound," is generated in the head section of flute-type instruments. The "hissing sound" results for the most part from the generation of turbulent flow in the central bore of the head section in the vicinity of the mouth opening.
This undesirable turbulent flow is created in part by the sharp change in the cross-sectional area of the flow path of air blown through the mouth opening and into the portion of the central bore in the head section of the instrument. The cross sectional area of the central bore in the head section of a conventional flute-type wind instrument is about four times larger than the cross sectional area of the mouth opening. The air undergoes an expansion as it flows into the central bore causing non-laminar or turbulent flow in the central bore.

Effects of flow improvement in tapered design


An EPROM array comprises a plurality of floating gate memory cell transistors and a multiplicity of floating gate select transistors arranged so that at least one select transistor controls the current to a group of floating gate memory cell transistors. Each floating gate select transistor remains unprogrammed or substantially unprogrammed even though the floating gate memory cell transistors in the memory array are selectively programmed to store information. The use of floating gate transistors for both memory cell transistors and select transistors simplifies the manufacturing process and improves yield.

EPROMs are well known. One challenge in EPROMs is to obtain a very dense EPROM, thereby to reduce the die size for a given number of memory cells, or to increase the number of memory cells capable of being formed in a die of a given size. U.S. Pat. application Ser. No. 07/539,657 filed Jun. 13, 1990, discloses a particularly dense EPROM, wherein the select transistor normally 5 associated with each floating gate transistor in a memory cell has been removed from the cell and combined with other select transistors to provide a single select transistor for use with a plurality of floating gate transistors. As disclosed in the '657 application, the select transistor is typically an N-channel transistor, while the EPROMs comprise floating gate transistors. Accordingly, the process for manufacturing the array requires two separate masking sequences, one to fabricate the floating gate EPROM transistors and another to fabricate the N-channel select transistors. The N-channel select transistors must be more robust and capable of pulling down a larger current than the EPROM transistors.
Fabricating two different types of transistors during the manufacture of a semiconductor EPROM memory array complicates the manufacturing process and reduces yield. Accordingly, a way is required to reduce the process complexity and thereby increase the yield of the array.


An information processing apparatus for receiving data, such as content data. During the time the content data is being downloaded by a terminal over a communication network, the volume of downloaded data being displayed is made smaller than the actual volume of the content data. When the download processing has substantially come to a close, the data volume is displayed to be 80% on a display unit. The user is able to interrupt the processing partway until the data volume indicating the completion of the downloading is displayed to be 80% on the display unit. After the downloading has come to a close, the operation of an interrupt button or of a power supply button is inhibited to enable reliable billing processing.

Recently, the Internet has become widespread, such that downloading contents such as audio or video data over the Internet for exploitation has come to be practiced frequently. In downloading the contents, billing processing is usually practiced at a time point of completion of the content downloading.
However, if, at a time point of completion of the content downloading, a power source button is intentionally operated in the OFF direction to turn off the power supply of a receiving terminal, only the content data is stored in the receiving terminal, without the billing processing, with the result that the content may be illicitly acquired free of charge.

Information processing method and apparatus for billing


The present invention relates to the field of muscle research, in particular to the discovery of a compound effective for increasing muscle mass, muscle cell differentiation, and oxidation of free fatty acids in muscle, useful in methods of treating muscle-related diseases and disorders as well as for augmenting muscle mass in general. The muscle-related diseases or disorders envisaged to be treated by the methods of the invention include, but are not limited to, muscular dystrophy, and other conditions resulting in muscle atrophy or muscle wasting.

Acrp30 (also known as AdipoQ) is the murine homolog of the human Apm1 protein (this class of proteins is generically referred to as OBG3 herein). The predicted protein structure of Apm1 indicates the presence of: 1) a secreted protein signal peptide, 2) a region containing collagen repeats, and 3) a globular region (FIG. 2), which is highly conserved (FIG. 1).
Acrp30 is a circulating protein that is produced by the adipose tissue (WO 96/39429 which is hereby incorporated herein in its entirety including any figures, tables, or drawings). Acrp30 mRNA levels are significantly reduced in adipose tissue from obese ob/ob mice. Acrp30 expression is greatly increased during adipocyte differentiation and appears to be regulated by insulin. In addition, Acrp30 has been shown to reduce postprandial blood lipid levels, stimulate weight loss, and reduce plasma triglycerides in normal mice, and to promote the reduction of food intake in genetically obese mice (PCT Application No. 99/07736 which is hereby incorporated herein in its entirety including any figures, tables, or drawings).
Studies performed using just the globular region of Acrp30, termed globular Acrp30 (gAcrp30) showed that it effectively reduced body weight in mice on a high-fat cafeteria diet, as well as decreased fatty acid levels, decreased triglyceride levels, and improved glucose turnover in post-prandial tests in mice (See U.S. Provisional Application Nos. 60/176,228 and 60/198,087, both of which are hereby incorporated herein by reference including any drawings, figures, or tables).

Use of Acrp30 globular head to promote increases in muscle mass and muscle differentiation


A temperature transmitter in a process control loop comprises a temperature sensor and a transmitter circuit. The temperature sensor includes a sensor sheath and a sensor element positioned within the sensor sheath. At least one element lead is coupled to the sensor element and extends from the sensor sheath. A sheath lead is coupled to the sensor sheath and extends from the sensor sheath, wherein the element lead and the sheath lead provide signals to be measured. The transmitter circuit includes and A/D converter, a microprocessor and an input-output circuit. The A/D converter is coupled to receive the signals from the element lead and the sheath lead. The microprocessor is coupled to the A/D converter. The input-output circuit is coupled to the microprocessor for communication with the process control loop. The sheath lead allows the transmitter to monitor the sensor sheath's insulation resistance and generation of parasitic sheath-to-lead voltage.

The present invention relates to transmitters used in process control loops. More specifically, the present invention relates to a temperature transmitter having a sensor with a sensor sheath lead.
Process control transmitters are used to measure process parameters in process control systems. Microprocessor-based transmitters include a sensor, an analog-to-digital converter for converting an output of the sensor into a digital form, a microprocessor for compensating the digitized output and an output circuit for transmitting the compensated output to instrumentation and control equipment. Typically, this transmission is over a process control loop, such as a 4-20 mA current loop.
One example of a process parameter is temperature. Temperature is sensed by measuring the resistance of a Resistive Temperature Device ("RTD"), such as a Platinum Resistance Thermometer ("PRT"), or by measuring a voltage output of a thermocouple sensor. For example, the resistance of an RTD can be measured by connecting the RTD in series with a known reference resistance (R.sub.REF) and applying a current common to both resistances. The voltages across each resistance are measured and digitized by the A/D converter. The microprocessor receives the digitized values, calculates the resistance of the RTD based on the digitized values and compensates the calculated resistance for various parasitic effects in the sensor and the transmitter. The resulting resistance value is converted into a corresponding sensor temperature value with a look-up table or a suitable equation by the microprocessor. The output circuit in the transmitter receives the sensor temperature value and provides the value to the process control loop as an analog current level or as a digital value superimposed on the analog circuit according to a known digital communication protocol.
A typical RTD is mounted within a distal end of a sensor sheath, which is typically a long, small diameter metal tube. A metal thermowell surrounds the sensor sheath. The RTD is electrically coupled to the transmitter's electronics through a plurality of element leads which extend from the sensor sheath. A typical RTD includes two, three or four element leads. One problem associated with RTD and other sensors is that the sensor sheath should remain electrically isolated from the sensor element and the element leads. The insulation resistance between the sensor sheath and the element leads may change over time or become shorted resulting in degraded or failed performance.
Another problem associated with temperature sensors is a parasitic sheath-to-lead voltage. A sheath-to-lead voltage is sometimes generated between the sensor sheath and the sensor element because of dissimilar metals being separated by an electrolyte made up of ceramic impurities (ionics) in the sensor and water entering into the system. This voltage may corrupt sensor measurements and result in sensor failure.
A temperature sensor and transmitter are needed which improve or substantially eliminate measurement errors from parasitic sheath-to-lead voltages and variations in insulation resistance.


A nitride semiconductor device is manufactured by the step of forming a nitride semiconductor layer form on a GaN substrate main surface, the step of polishing a back surface of the GaN substrate formed with the above-mentioned nitride semiconductor layer, the step of dry etching the back surface of the GaN substrate subjected to the above-mentioned polishing by using a gas mixture of chlorine and oxygen, and the step of forming an n-type electrode on the back surface of the GaN substrate subjected to the above-mentioned dry etching.

1. Field of the Invention
The present invention relates to a method of manufacturing a nitride semiconductor device for use in a laser diode.
2. Description of the Background Art
Because a nitride semiconductor has a large bandgap, gallium nitride (GaN) has particularly been used for a laser diode (LD). In the LD of GaN, an n-type electrode is formed on the back surface of a GaN substrate. In this case, it is necessary to make the substrate thin prior to the formation of the n-type electrode, and the GaN substrate is polished. This polishing, however, causes an altered layer to be formed on a polished surface of the substrate to increase a contact resistance with the n-type electrode to be formed on this surface. A method of reducing this contact resistance includes a method of performing heat treatment at a high temperature of about 700° C. after the n-type electrode is formed. The processing at such a high temperature, however, presents a problem such that a p-type electrode provided on the GaN substrate is degraded.
A solution to such a problem is a method of dry etching the polished surface using a halogen gas as an etching gas after the polishing of the GaN substrate to remove the altered layer generated on the polished surface, and performing heat treatment at a temperature of not less than 400° C. after electrode formation to reduce the contact resistance with the n-type electrode. (See, for example, Japanese Patent Application Laid-Open No. 2003-347660 (pp. 4-5)).
As the LD advances toward ever smaller size and higher power, power inputted to the LD increases, and a further reduction in the contact resistance of the electrode is desired. The method of dry etching the polished surface using the halogen gas to remove the altered layer still has problems in that there is a limit to the reduction in the contact resistance of the n-type electrode and in that the heat treatment at the high temperature of not less than 400° C. is required to reduce the contact resistance.

Method of manufacturing nitride semiconductor device


A convenient cover opening and closing method, system, and apparatus are described. A cover grasper, adjustable tension, an anchor, and a stabilizer provide the necessary torques so that a cover opens and closes in a controlled smooth manner. Moreover, the apparatus and system may be conveniently removed from and secured to the cover's container, may be secured in a more permanent fashion to the container, or components of it may be secured on the container while others are not.

I. Field
The disclosed embodiments relate to a convenient cover opening and closing method, system, and apparatus.
II. Background
Some containers have covers that are inconvenient to open and close. For example, a standard refuse container has a large cover that is fairly heavy. A person is required to hold the cover up to open it, and the cover wants to slam shut if not held open. This requires a person to use one hand to awkwardly hold the cover open while placing items into and out of the container. Conversely, the cover wants to rotate all the way around and flop down towards the back of the container. If this happens, the cover has to be lifted and rotated all the way back to close it. This is inconvenient as well. Moreover, if a person has physical impairments, it may be extremely inconvenient to open and close a cover. Physical challenges can come from many aspects of life. For example, a war veteran may have lost a limb, or an elder may have debilitating arthritis. Typically, a person who has no physical challenges can use one arm to hold open the cover while placing the item(s) into a container, and this is inconvenient for them. However, a physically challenged person may not be able to do that. They may have use of only a single arm which would require them to put the item down, lift the cover, prop the cover open somehow, then grab the item again, place the item into the container, then close the cover. It also may take more time to place items into and out of the container if the container has a cover like this. Additionally, if the convenient cover opening and closing system is removable from the container, then that may be more convenient than a permanent opening and closing arrangement depending on the application. Therefore, there is a need in the art to provide a convenient cover opening and closing method, system, and apparatus.

Convenient cover opening and closing method, system, and apparatus


Fender mounting accessories are described herein. Fender mounting accessories can include a fender bracket and a fender attachment mechanism. A fender bracket can include a fender bracket and an extension member including an offset mounting flange for coupling with a fender attachment mechanism. A fender attachment mechanism can include an inner flange for coupling to the fender bracket and attachment locations for coupling to a fender.

A fender can be an important part on a vehicle. A vehicle can be, for example, a machine that transports people, cargo, etc. A vehicle may be, for instance, a self-propelled conveyance moving on wheels. For example, a vehicle may include an automobile such as a car, truck, etc.
A vehicle can include a fender. As used herein, the term "fender" refers to a portion of a vehicle that frames a wheel or a set of wheels. A fender on a vehicle can serve a variety of purposes. For instance, a fender may serve an aesthetic purpose. For example, a fender may be styled, shaped, painted, etc. in order to exude a particular outward appearance that may be pleasing to view.
As another example, a fender may serve a utilitarian purpose. For example, wheels on a vehicle in motion may cause debris such as sand, mud, rocks, liquids, and/or other debris to be thrown into the air by the rotation of the wheels of the vehicle in motion. A fender can prevent the debris from being thrown into the air. A fender can be located proximate to a wheel and/or a set of wheels to act as a barrier such that debris thrown into the air by the rotation of the wheels of a vehicle in motion contacts the fender. Accordingly, debris can be prevented from contacting other parts of the vehicle in motion, contacting other vehicles located near the vehicle in motion, etc.


A system for analyzing a sample includes an inspection sub-system and at least one controller. The inspection sub-system is configured to scan a sample to collect a first plurality of sample images having a first image resolution. The controller is configured to generate a defect list based on the first plurality of sample images. The controller is further configured to input images corresponding to the defect list into a neural network that is trained with source data including sample images having the first image resolution and sample images having a second image resolution higher than the first image resolution. The controller is further configured to generate a second plurality of sample images with the neural network based on the images corresponding to the defect list, where the second plurality of sample images have the second image resolution and correspond to the defect list.

Sample analysis systems (e.g., inspection systems) are being designed to perform defect inspection at faster rates. For a typical patterned wafer, a job run may include the following steps: (1) Wafer Loading on pre-aligner; (2) Notch alignment; (3) Wafer Loading on chuck; (4) Wafer Alignment; (5) Defect Scan; (6) Defect Filtering; (7) Automatic/Automated Defect Review (ADR); and (8) Wafer Unloading followed by saving the defect images (and reference images, if any). In this process, the throughput is mostly impacted by defect scan and ADR steps.
In existing ADR schemes, an inspection system/tool, after the inspection scan, switches to the review objective and then goes to each of the defect locations, acquires focus and grabs an image. At times, when the wafer Z-profile is not flat, review may even experience defocus. Some disadvantages of the current ADR process are that longer time is required for ADR (to collect higher resolution images at each of the defect locations), defocus issues may occur due to irregular wafer flatness profile, and there is a risk of physical contact of the review objective with the wafer. Accordingly, there is a need for sample analysis systems and methods with improved ADR schemes.

Super-resolution defect review image generation through generative adversarial networks


An airbag assembly including one or more elongate tether elements that extend through vent openings along travel paths from anchoring locations such that the tether elements extend in sliding relation through the vent openings. The gas emission capacity of the vent openings may be adjustable based on internal cushion pressure.

It is well known to provide an airbag assembly including an inflatable airbag cushion for protecting the occupant of a transportation vehicle. In an automotive vehicle such air bag assemblies are typically located within the hub of the steering wheel and in positions opposing the knees and/or torso of a side passenger. Additional air bag assemblies may be located within the seats and/or door panels for protection of the occupants during a side-impact event.
One particular type of airbag assembly is an inflation driven bolster disposed in opposing relation to an occupant's lower extremities. Such systems typically incorporate an inflatable cushion disposed in an instrument panel behind an outer occupant contact surface in the form of a plate which is covered by a layer of foam with a aesthetic polymeric skin or fabric. Upon activation, the cushion inflates and pushes the plate into contact with the occupant's knees thereby providing early stage dissipation of kinetic energy. By way of example only, and not limitation, one such system is illustrated and described in U.S. Pat. No. 5,931,493 to Sutherland the contents of which are hereby incorporated by reference in their entirety.
As will be appreciated, when an airbag cushion in a knee bolster or other airbag assembly is activated, the pressure is generally proportional to the quantity of inflator gas expelled into the airbag and inversely proportional to the volume occupied by the gas. As the occupant comes into contact with the expanded airbag or outer contact surface, the inflator gas is forced out of the air bag thereby dissipating the kinetic energy of the occupant achieving a so called "ride down" effect. In order to facilitate the discharge of inflator gas from the airbag it is common to incorporate vents in the form of normally open fixed diameter apertures across the walls of the airbag.
In order to provide additional control over the inflation characteristics of the airbag cushion it is known to use tethering elements in the form of straps or webs extending between surfaces of the airbag and anchoring points on structural members. It has also been proposed to use elongate tethers in attached relation to vent closing members to facilitate adjustable venting. Such systems are illustrated and described in U.S. Pat. No. 6,932,385 to Hawthorn et al. the contents of which are hereby incorporated by reference as if fully set forth herein.


An optical switching device for switching linearly polarized optical signal beams includes a plurality of switching cells arranged in matrix form. Each switching cell has spatial light modulators and a polarizing beamsplitter which cooperate to propagate the optical beams received by the device to selected output ports. The device can be three-dimensionally expanded to increase the number of output ports to which the optical beams can be selectively switched, in which case the matrices can share integrally constructed polarizing beamsplitters and SLMs.

This invention relates to an optical switching device and, more particularly, to an electrically controlled switching device for individually directing a plurality of linearly polarized optical beams to selected output ports.
Signal processing systems often employ multiple parallel processors which permit many operations to take place concurrently. These so called parallel processing architectures typically require switching devices capable of efficiently transferring the data signals between such parallel processors. It is particularly advantageous to use optical switching devices to selectively interconnect the multiple parallel processors. For example, optical signal beams provide greater operating bandwidths and superior immunity to electro-magnetic interference as compared with electrical signals.
These optical switching devices must be capable of spatially switching large numbers of light beams while preserving the integrity of the signals communicated by such light beams. One approach generally used in the fabrication of these switching devices is to utilize a plurality of elementary switching cells which in combination provide the overall switching capacity of the device. In these switching devices, it is highly desirable to reduce the number of elementary switching cells required to switch a given number of light beams so that, for instance, the switching device becomes more compact while having lower fabrication costs.
An optical device for switching light beams is proposed by J. B. McManus, R. S Putnam, and H. J. Caulfield in the paper entitled "Switched holograms for reconfigurable optical interconnection: demonstration of a prototype device", Vol 27, Applied Optics, pp. 4244-4250, Oct. 15, 1988. The device proposed by McManus utilizes a plurality of switching cells arranged in a two-dimensional matrix which, in general, can have M columns and N rows of switching cells. Each switching cell comprises a polarizing beamsplitter and a spatial light modulator (SLM) which cooperate to selectively direct light beams externally applied to the matrix to selected outputs. A disadvantage of the device proposed by McManus is that light beams are received only by a single SLM and consequently the switching capacity of the McManus device is restricted to the number of light beams which can be handled by the single SLM. In contrast, a switching device of the same size (e.g., having MxN switching cells) but capable of receiving light beams at each of N SLMs provides an increased switching capacity (here increased by an N factor) over the McManus device. Moreover, the device proposed by McManus is confined to a two-dimensional arrangement of switching cells (e.g., a single two-dimensional switching matrix). In other words, McManus does not suggest how his device can be expanded into a three-dimensional arrangement of switching cells (e.g., a succession of identical two-dimensional matrices positioned parallel to each other). A device having such three-dimensional expansion capability significantly increases the universe of selectable output ports to which the light beams can be switched. For example, if Q is the number of successive two-dimensional matrices positioned parallel to each other, then the number of selectable output ports will increase by a Q factor.
Accordingly, one object of the invention is to provide a two-dimensional optical switching device which can individually and simultaneously direct light beams received by each of multiple SLMs thereof.
Another object of the present invention is to provide an optical switching device which can be three-dimensionally expanded to provide additional selectable output ports for the light beams switched by the device.

Optical device with spatial light modulators for switching polarized light


A method of fabricating a polysilicon LCD device includes forming an active layer on a substrate, forming a first insulating layer having a first thickness and a second insulating layer having a second thickness sequentially on the active layer, forming a photoresist on the second insulating layer, ashing the photoresist, etching first portions of the first thickness of the first insulating layer corresponding to the source and drain electrode regions and the reduced second thickness of the second insulating layer within the first regions to expose source and drain regions of the active layer corresponding to the source and drain electrode regions, and etching a second portion of the second thickness of the second insulating layer to expose a portion of the first insulating layer corresponding to a gate electrode region, forming a gate electrode, a source electrode, and a drain electrode simultaneously on the second insulating layer, forming a passivation layer on the gate electrode, the source electrode, and the drain electrode, and forming a pixel electrode on the passivation layer.

1. Field of the Invention
The present invention relates to a driving circuit for a liquid crystal display (LCD) device and a method of fabricating a driving circuit for an LCD device, and more particularly, to a polycrystalline LCD device.
2. Description of the Related Art
In general, a driving circuit device can be an individual type comprising a display unit for displaying images and a driving circuit unit for driving the display unit, wherein the display unit and the driving circuit unit are connected to each other by a tape carrier package (TCP), for example. Alternatively, the driving circuit device can be an integrated type comprising a display unit and a driving circuit unit formed on the same substrate. Accordingly, the integrated type driving circuit device can be more easily fabricated than the individual type driving circuit device. In the integral type driving circuit device, polysilicon is commonly used as a channel layer since polysilicon has better electric mobility an amorphous silicon. Thus, an LCD using the polysilicon integral type driving circuit device can operate at high speeds. For example, electric moblity of an amorphous thin film transistor (TFT) is 0.1˜1 cm2/Vsec, an electric mobility of a polysilicon TFT fabricated using an excimer laser exceeds 100 cm2/Vsec.
FIG. 1 is a schematic plan view of a polysilicon LCD device according to the related art. In FIG. 1, an integral type driving circuit device includes a display unit 101 having unit pixels arranged in a matrix configuration, and a driving circuit unit 102 arranged along an outer periphery of the display unit 101 for driving devices of the display unit. The driving circuit unit 102 is provided with a gate driver 104 and a data driver 103, and the display unit 101 and the driving circuit unit 102 are formed on the same substrate. In the driving circuit unit 102, a complementary metal oxide semiconductor (CMOS) device includes an PMOS TFT and an NMOS TFT that are connected to the unit pixels of the display unit.
FIGS. 2A to 2I are cross sectional views of a fabrication process for a polysilicon LCD device according to the related art. In FIG. 2A, a substrate 201 is prepared, and a buffer layer 202 formed of a silicon oxidation layer (SiO2) is formed on the substrate 201. Then, an amorphous silicon layer 203 is deposited onto the silicon oxidation layer (SiO2) by a plasma enhanced chemical vapor deposition (PECVD) process at a low temperature. Next, a heat treatment is performed at approximately 400° C. during a dehydrogenation process for removing hydrogen included in the amorphous silicon layer. The dehydrogenation is performed in order to prevent hydrogen included in the amorphous silicon layer from corrupting a crystallization process of the amorphous silicon layer and thereby prevent the substrate from being damaged.
In order to crystallize the amorphous silicon layer, glass is used as a substrate and the substrate is heated. However, during fabrication of the LCD device by the heat treatment, the glass used as the substrate may be deformed by the heat. Therefore, during fabrication of a polysilicon TFT on a glass substrate, a laser annealing method is used to convert the amorphous silicon into polycrystalline silicon by an instantaneous heat treatment at a low temperature. For example, an excimer laser beam is irradiated onto the substrate where the amorphous silicon is formed, thereby converting the amorphous silicon layer into a crystalline silicon layer by annealing. Next, the polysilicon is dry-etched to define an active layer.
In FIG. 2B, a TFT active layer 203a is formed within a display unit region, and an N-type TFT active layer 203b and a P-type TFT active layer 203c are formed within a driving circuit unit region.
In FIG. 2C, a gate insulating layer 204 formed of SiO2 or SiNx and the active layers 203a, 203b, and 203c are formed on the entire surface of the substrate 201. The gate insulating layer 204 protects the active layers 203a, 203b, and 203c and insulates a subsequently-formed upper layer. Then, a gate metal layer is formed on the gate insulating layer 204 by a sputtering method. Next, the gate metal layer is patterned by photolithographic processes to form a gate electrode 205. The gate electrode may be composed of a double layer of Al and Mo in order to provide excellent conductivity and excellent ohmic contact characteristics with an indium tin oxide (ITO) material used as a pixel electrode. Alternatively, the gate electrode may be composed of a single layer of only Mo.
Since the N-type TFT makes use of electrons as carriers, it may generate a leakage current due to the electrons. Accordingly, the N-type TFT is fabricated as a lightly doped drain (LDD) type that effectively prevents the leakage current. Thus, the LDD-type TFT is formed by injecting impurity ions into a polysilicon source/drain region, wherein the impurity ions may include an element, such as Phosphorus or Arsenic, corresponding to the fifth group of the periodic table.
In FIG. 2D, a photo resist pattern 206 is formed to shield the P-type TFT region by a photomasking process that includes exposing and developing processes. Then, N-type ions of a low concentration are injected into the active region of the N-type TFT pixel unit and circuit unit regions. During the phosphorus ion injection, the gate electrode 205 is positioned to function as a blocking mask so that the N-type ions are injected into the source/drain regions. After injecting the N-type ions, the photoresist pattern 206 is removed.
In FIG. 2E, a photoresist pattern 207 is formed to shield the gate electrode 205 and portions of the source/drain region of the N-type TFT pixel unit and circuit unit regions, and the entire P-type TFT circuit unit region. By applying the photoresist 207 as a blocking mask of the injected ions, N-type impurity ions of a high concentration are injected into the source/drain regions of the N-type TFT pixel unit and circuit unit regions, thereby forming LDD-type TFTs. For example, the LDD-type TFTs both include LDD regions 208 having a low impurity concentration and source and drain regions 209 having a high impurity concentration.
In FIG. 2F, a photoresist 210 is formed to cover the completed N-type TFT pixel unit and circuit unit regions. Then, P-type impurity ions are injected into the portions 211 of the active layer of the P-type TFT circuit unit region. Since holes are used as charge carriers, leakage current due to hot carriers is not easily generated in the P-type TFT. Accordingly, the P-type TFT may not include LDD regions. Then, the photoresist 210 is removed.
In FIG. 2G, an insulating layer 214 comprising SiO2 or SiNx is formed on the gate electrode 205, and a contact hole 220 is formed in the insulating layer 214 corresponding to the source/drain regions in the N-type and P-type TFTs.
In FIG. 2H, a conductive layer for a source/drain electrode is formed in the contact hole 220 and patterned, thereby forming source/drain electrodes 215 and 216.
In FIG. 2I, a passivation layer 217 of an organic layer or an inorganic layer is formed on the source/drain electrodes 215 and 216. Then, the passivation layer 217 on the drain electrode of the TFT is removed to form a contact hole 219. Next, a pixel electrode 218 is formed on the passivation layer 217 and connected to the drain electrode 216 through the contact hole 219, thereby completing the LCD device.
Formation of the polysilicon TFTs is a very complicated process although the polysilicon TFTS have excellent operation characteristics. In addition, a plurality of masks are required to fabricate the polysilicon TFT LCD device. For example, since each mask process accompanies a photolithography process, the fabrication process is delayed and results in possible environmental contamination.

Polycrystalline liquid crystal display device and method of fabricating the same having simultaneously formed gate, source and drain electrodes


Micropumps fabricated by micromachining techniques and employing fixed or no-moving-parts valves. As one aspect of the invention, a laser-assisted chemical etching technique is employed for providing smooth-walled, curved configuration necessary to obtain the desired flow characteristics of the valves that are used in conjunction with the micropump.

Miniature pumps, hereafter referred to as micropumps, can be constructed using fabrication techniques adapted from those applied to integrated circuits. Such fabrication techniques are often referred to as micromachining. Micropumps are in great demand for environmental, biomedical, medical, biotechnical, printing, analytical instrumentation, and miniature cooling applications. Just as in larger applications, various pump designs are required for different micropump systems.
The valve components of micropumps may include passive polysilicon check valves, gas-controlled valves with silicon membranes, solenoid-actuated valves with nickel diaphragms, and magnetically or electro-statically driven control valves. Valves that include components that are actuated or otherwise driven can be characterized as active valves. Manufacture and operation of active valves can add substantial complexity and cost to the production of micropumps.
Passive-type valves, such as those having movable polysilicon check valves, can be manufactured with reduced complexity, although these valves can fail when the pumped fluid includes particulates. In this regard, the particulate sizes are of the same order of magnitude as the passages in the micropumps. The passive valves become obstructed by particulates and are, therefore, unable to provide a sufficient seal when required. As a result, such valves have limited effectiveness when employed for pumping fluids that include particulates.
Similarly, active valves that employ substantially rigid sealing membranes or diaphragms are susceptible to seal failure when used to pump fluids containing particulates. The particulates become embedded in the sealing surface as a result of the relatively high pressure applied to the rigid diaphragm as needed to ensure a seal with such a valve. Once the particulates become embedded in the sealing surface, the valve is thereafter prevented from fully closing.
Fixed valves are valves having no moving parts. Fixed valves represent the utmost simplicity and high reliability for pumping fluids. Such valves, which do not include parts that periodically seal and move apart, are especially advantageous for micropump systems used for pumping fluids that include particulates. Moreover, fixed-valve pumps are particularly useful for biological applications that require pumping fluids that contain cells. The cells are not damaged by the fixed valve pumps, as would otherwise occur in moving-parts valves.
The effectiveness of fixed valves can be characterized by the parameter "diodicity," which is the ratio of pressure drop in the reverse-direction fluid flow through the valve to the pressure drop in the forward-direction fluid flow through the valve, for a given flow rate. A basic design consideration for a fixed valve micropump is to develop valve configurations that result in a diodicity greater than 1.0. In this regard, the small size of such valves, and the very low flow range (100 nl/min to 50 ml/min, for example) will typically yield a relatively low Reynolds number, which number is a dimensionless parameter that is proportional to the product of the valve size and flow velocity. Accordingly, the valve configurations must effect the requisite diodicity in flows characterized by low Reynolds numbers, where flow separation and turbulence (with attendant significant pressure losses) are unlikely to occur.
U.S. Pat. No. 1,329,559 discloses a fixed valve that is designated as a"valvular conduit." The conduit is provided with enlargements, recesses, and projections that are said to offer virtually no resistance to the passage of fluids in one direction, yet provide a nearly impassible barrier to fluid flow in the opposite direction. When an oscillating flow of fluid is applied to one end of the conduit, the conduit acts as a one-way valve or fluidic diode, thereby permitting the oscillated or pulsed fluid to be pumped through the conduit. The conduit is mounted to a piston that is rapidly reciprocated to provide the pulsed flow of fluid through the conduit.
The valvular conduit described in U.S. Pat. No. 1,329,559 is full-sized, constructed of metal, and used for delivering fluids with flows that can most likely be characterized as having a relatively high Reynolds number. No insight is provided in that patent as to how such a conduit could be adapted to a micropump system and flows characterized by low Reynolds numbers.
The present invention is generally directed to the fabrication of a micropump that employs fixed inlet and outlet valves. In one preferred embodiment of the invention, the micropump is fabricated by micromachining techniques and operates as a diaphragm pump driven by a piezoelectric actuator and having fixed valves that effect the necessary diodicity of greater than 1.0.
As one aspect of the invention, a laser-assisted chemical etching fabrication technique is employed for providing smooth-walled, curved configurations of portions of the fixed valves. A fabrication technique known as LIGA may also be employed.
As another aspect of the invention, the fixed valves include discrete branches for substantially redirecting the reverse flow therethrough, thereby generating the pressure loss differences requisite for a valve diodicity of greater than 1.0.
As another aspect of the invention, the fixed valves include diffuser and nozzle configurations for generating the relatively high pressure losses in the reverse-flow direction.
The present invention can be implemented in a variety of ways. For example, a micropump fabricated by surface or bulk micromachining techniques can be connected to a fluidic circuit in which is incorporated a fixed valve of the present invention.
The foregoing and additional features and advantages of the present invention will be more readily apparent from the following detailed description, which proceeds with reference to the accompanying drawings.


Circuit arrangement having complementary data input nodes for reception of a dual rail data signal and complementary data output nodes for outputting a dual rail data signal. A connection switch is connected to complementary data nodes by means of which the complementary data nodes can be connected to one another with a low resistance, a control unit is provided for generating a first control signal for the connection switch, and the circuit arrangement is designed to be operated in two operating modes, in which case in a power saving mode, the connection switch is switched by the control unit to have a high resistance, and in a security node, the connection switch is switched by the control unit to have a low resistance when the potential at the complementary data nodes is intended to be equalized.

So-called dual rail circuit technology, which is also referred to as complementary circuit technology, relates to a circuit arrangement design whose security aspects have been improved, in particular for data processing apparatuses. Circuits are normally designed using so-called "signal rail circuit technology". In this case, switching networks are formed microelectronically such that each bit of the information to be processed is represented physically by one and only one electrical node. Switching networks such as these are relatively insecure when subjected to so-called differential current profile analysis, which is often used when unauthorized third parties attempt to access secret information. Differential current profile analysis, which is also referred to as differential power analysis (DPA), is one of the most important methods for attacking, for example, smart cards for security applications. Smart card current profiles measured by statistical methods and their charge integrals calculated over one or more clock cycles are evaluated for a given program or a given algorithm, in which case conclusions about the information to be protected can be drawn from the correlation between the systematic data variation and the respective charge integral, for a large number of programmed versions.
One possible way to make DPA attacks at least considerably more difficult is to interchange or to transmit data between subsystems of an integrated circuit only in an encryption form, as far as possible. One crypto system which is suitable for this purpose is so-called one-time pad encryption. Keys obtained as random sequences are linked bit-by-bit with texts to be transmitted, via an XOR gate. An XOR gate is once again used for deencryption. For the one-time pad crypto system, it is important that each key sequence is used only once for encryption and deencryption, because information relating to plain texts can otherwise be obtained by statistical methods.
This "encrypted calculation" using the single rail circuit technique requires a very large amount of circuit complexity and thus a large surface area, however, and the power consumption is in consequence increased. The dual rail circuit technique is used in order to avoid the need for encryption. From what has been stated above with regard to differential current profile analysis, it can be stated that the circuit components in an integrated circuit should ideally be designed, in order to resist DPA attacks, in such a way that they always produce the same current profile irrespective of the data to be processed. However, this is not reliably the case for the single rail implementation, because the charge integral associated with the time profile of the states of a circuit is a function of those nodes and/or electrical capacitances whose electrical charge levels are changed, that is to say it is highly dependent on the changes in the data to be processed over time.
In contrast to conventional single rail circuit technology, each bit is represented by two nodes k and kq in dual rail circuit technology, with a transmitted bit having a valid logical value when k corresponds to the true logical value b, and kq corresponds to the negated value bn=not(b).
Thus, when the aim is to transmit the value b=1, then this is done by means of a "1" in the node k. At the same time, however, the value "0" is transmitted at the node kq, so that, overall, both a "1" and a "0" are thus transmitted. When the aim is to transmit the value b=0, the value "1" is transmitted at the same time at the node kq. A "1" and a "0" are thus transmitted in both cases. Assuming that the nodes k and kq are physically equivalent, it is no longer possible to use differential current profile analysis to determine whether a "1" or a "0" has been transmitted as the data item. However, this is true only when a signal change actually takes place for each transmitted data item, that is to say the information "1" and the information "0" alternate. If a plurality of identical data items are transmitted successively, the characteristics with regard to the capability for attacks by differential current profile analysis deteriorate.
The desired invariance of the charge integrals is now achieved by inserting a so-called precharge state between two states with valid logical values (b, bn)=(1,0) or (0,1) for which both k and kq are charged to the same electrical potential, that is to say they assume logically invalid values (1,1) or (0,0). A state sequence for the precharge state (1,1) could thus appear as follows:
(1,1)→(0,1)→(1,1)→(1,0)→(1,1)→(1,0)→(1,1)→(0,1)→ . . .
For any such character sequence, it can be stated that the charge on one and only one node is changed from "1" to "0" for each transition (1,1)→(b, bn) and that the charge on one and only one node is changed from "0" to "1" for all (b, bn)→(1,1) irrespective of the logic valid value b of the state bit in question. An analogous situation applies to the state sequences with the precharge state (0,0).
This means that the charge integrals which correspond to these state sequences are independent of the sequence (b, bn) of the logically valid values, provided that care is taken to ensure that the nodes k and kq have the same electrical capacitances. The current profile of a data path implemented in this way thus does not depend on time variations in the data to be processed, and is therefore resistant to differential current profile analysis.
One example of a dual rail implementation of a circuit component is known from DE 102 02 726 A1. The integrated circuit proposed there is a register in a data path. The proposed circuit arrangement is designed consistently using dual rail technology, and thus forms a charge-neutral register.
One problem in designing circuit components using dual rail circuit technology is that the power consumption is considerably greater.

Circuit arrangement having security and power saving modes


Systems and methods are disclosed for detecting framing data in a telecommunications signal. In one embodiment, a frame synchronizer circuit is provided that includes an interface for receiving bits of a telecommunications signal and storage for storing a framing state for the bit positions in the frame, the framing state for a given bit position indicating whether that bit position is a potential holder of the frame synchronization pattern. The frame synchronizer circuit also contains a state update function that determines the current-state for each bit position based on the bit position's previous state, and the value of the most recently received bit in that bit position. The encoding scheme makes use of shorter bit length symbols to represent statistically more frequently occurring states. In one embodiment, a single code word is used to record the state of a sequence of consecutively occurring bit positions that share the same state.

Many digital serial telecommunications signals have a frame structure, with some bit positions within the frame designated to carry payload data, and some bit positions designated to carry transport overhead. Transport overhead includes administrative information needed to successfully transport the payload data, such as parity and frame synchronization data.
A circuit that receives a serial bit stream typically contains a frame synchronizer that monitors the incoming bit stream, finds the frame synchronization pattern, and provides a frame synchronization signal to the rest of the circuit. The frame synchronization signal is based on the position of the frame synchronization pattern within the frame, and is used by the rest of the circuit to extract payload and overhead data from the bit stream.

Systems and methods for frame synchronization


A diagnostic system and method for detecting retardation of a object controlled by a programmable controller. The system may include a microprocessor system with a keyboard, a printer, a memory card, and a telecommunications line which is connected to one or more programmable controllers. This system reads operational commands and signals, representing the completion of an operation, through the telecommunications line. If any retardation occurs, the diagnostic system fetches a series of operation commands, and identifies the logical address where retardation occurs.

1. Field of the Invention
The present invention relates to a diagnostic system for a programmable controller (hereinafter referred to as PC), and more particularity to a diagnostic system enabling the identification of logical addresses where retardations occur during a series of sequential control proceedings.
2. Description of the Related Art
PC's are widely used for controlling a various kinds of controlled objects sequentially with a programmed order.
PC's apply operational commands to actuators such as motors, solenoid valves, etc arranged on various kinds of controlled objects, and output operational commands when PC's sense signals representing the completion of operations output from sensors, such as limit switches for controlling various kinds of controlled objects sequentially with a programmed order.
And if a retardation should occur during a sequential controller proceeding, actions of various kinds of controlled objects are interrupted.
In PC's, however, because many actuators and sensors are connected to PC's, it requires a long time and special knowledge of PC's to determine the cause of a retardation and identify a logical address corresponding to abnormal actuators and sensors.
To simplify an inspection and an identification, PC's with so-called diagnostic function are already suggested (see Japanese Unexamined Patent Application (Kokai) 61-202207).
ON-OFF statuses of contacts arranged on a controlled object are read in this PC synchronizing each sampling time, and logical addresses corresponding to abnormal actuators and sensors are identified by comparing the ON-OFF statuses with a preprogrammed status representing a normal condition.
Therefore, this PC has the following faults.
(1) ON-OFF statuses representing a normal condition must be preprogrammed. PA1 (2) A diagnostic area is limited by capacity of memory which stores an ON-OFF status representing a normal condition and an actual ON-OFF status. PA1 (3) When control logics are modified, modifications for a diagnostic area and diagnostic logic are required.

Diagnostic system and method for detecting retardation of an object controlled by a programmable controller


A coherent optical receiver includes a 90-degree optical hybrid circuit to which a received signal light is input, I-channel and Q-channel photo detectors to which the outputs of the hybrid circuit are input, a clock extraction circuit which reproduces a clock whose speed is the same as a demodulated signal obtained by demodulating the received signal light and which is synchronized therewith, I-channel and Q-channel sampling circuits which sample the signal outputs from the I-channel and Q-channel photo detectors by use of the clock, and a digital signal processing section which digitally processes the sampled signals, converts them to a digital signal, and outputs the digital signal. The digital signal processing section feeds a phase offset signal detected there back to the clock extraction circuit to thereby control the phase of the clock, and compensates dispersion of light within a fiber and phase fluctuation during free-space propagation.

1. Field of the Invention
The present invention relates to a coherent optical receiver which is used for terrestrial optical fiber communications, spatial optical communications between terrestrial stations, spatial optical communications between satellites, spatial optical communications between a terrestrial station and a satellite, and communications between fixed and mobile transmitters and receivers. The coherent optical receiver can be synchronized with a clock extracted from an optical phase modulated signal, and compensate propagation distortion of signals, and can receive signals modulated in two optical modulation schemes; i.e., intensity modulation and modulation for coherent communications.
2. Description of the Related Art
There has been known a coherent communication scheme which utilizes laser light's intrinsic nature as a wave, and transmits a signal by modulating the frequency or phase of the laser light, in contrast to ordinary optical communications in which a signal is transmitted by modulating the intensity of light waves. Such a coherent communication scheme can be used in the optical communication field requiring large-capacity transmission, the fiber information communication field, the optical communication field requiring long-distance transmission, the field of space communications near the earth, and the field of deep space communications. In the coherent communication scheme, optical detection (demodulation) is effected by means of mixing signal light and local oscillation light. A phase-diversity reception scheme has been proposed so as to realize such detection of coherent light (see Patent Document 1).
FIG. 4 is a diagram showing an optical receiver of a phase-diversity reception scheme described in Patent Document 1. PSK-modulated input signal light is transmitted from a transmitter (not shown) to the receiver. In the illustrated receiver, the input signal light is demodulated by means of delay detection utilizing a phase-diversity scheme, which is realized by a 90-degree optical hybrid for splitting the input signal light to quadrature components I and Q, a pair of photo detectors, a pair of 1-bit delay lines for delay detection (demodulation), and a pair of two-input, four-quadrant output analog multipliers. The outputs of the multipliers are added together, whereby a signal component is output.
An AFC circuit includes a frequency discriminator, a LPF (low-pass filter) which allows passage therethrough of components near DC which are necessary for AFC, and a local oscillation light source. The output of the local oscillation light source is supplied to the 90-degree optical hybrid. In the phase-diversity reception scheme, the AFC circuit is configured to reduce to zero the frequency difference between the local oscillation light and the signal light.
As described above, the illustrated receiver can demodulate a PSK modulated signal by means of delay detection utilizing the phase-diversity scheme. However, since phase detection is not performed by digital processing, compensation for fiber dispersion and phase compensation for atmospheric fluctuation cannot be performed. Further, the receiver cannot cope with both intensity modulation and coherent modulation.
Non-Patent Document 1 discloses a phase-diversity reception scheme adapted to digital processing. FIG. 5 is a diagram showing a coherent optical reception apparatus of a phase-diversity reception scheme described in Non-Patent Document 1. In the illustrated reception apparatus, signal light transmitted from a transmitter side is input to a phase-diversity homodyne receiver along with local oscillation light from a local oscillation light source. The homodyne receiver mixes the input signal light and the local oscillation light having the same frequency as the input signal light so as to directly obtain low-frequency electric signals IPD1 and IPD2. The low-frequency electric signals IPD1 and IPD2 have a phase difference of 90° therebetween (SIN and COS waves), and carry pieces of information regarding the amplitude and phase of the optical signal, respectively. The low-frequency electric signals IPD1 and IPD2 are led to a digital processing circuit DSP via respective low-pass filters LPF and analog/digital converters ADC. The digital processing circuit DSP detects a carrier phase, and demodulates data. Normally, the frequency of the local oscillation light must be made coincident with that of the input signal light by use of PLL (phase-locked loop: phase synchronization circuit). In contrast, the illustrated coherent optical reception apparatus does not utilize PLL and absorbs the frequency deviation through the digital processing. However, in reality, achieving transmission speed of a few Gbps in real time is difficult until new devices are developed. Since the reception apparatus shown in FIG. 5 does not employ PLL, a beat attributable to the frequency deviation is superimposed on the output of the homodyne receiver. Therefore, sampling at the analog/digital converters ADC cannot be performed in synchronism with the data signal such that sampling is performed one time in each symbol period. Therefore, when a signal is transmitted at, for example, 10 Gbps, the analog/digital converters ADC must perform high-speed processing of about 100 G samples/S, which is ten times the transmission speed (see FIG. 3).
[Patent Document 1] Japanese Patent Application Laid-Open (kokai) No. 11-41207
[Non-Patent Document 1] Kazuro Kikuchi, "Phase-Diversity Homodyne Detection of Multilevel Optical Modulation With Digital Carrier Phase Estimation," IEEE JOURNAL OF SELECTED TOPICS OF QUANTUM ELECTRONICS, VOL. 12, NO. 4, JULY/AUGUST 2006

National Institute of Information and Communications Technology


A carbazole compound in which the 2-position of a dibenzofuran skeleton or a dibenzothiophene skeleton is bonded to the 3-position of a carbazole skeleton and nitrogen of the carbazolyl group is bonded to the 9- or 10-position of an anthracene skeleton directly or via a phenylene group was able to be synthesized. It was found out that the carbazole compound has an excellent carrier-transport property, favorable film quality, and a wide band gap, and can be suitably used as a light-emitting element material and an organic semiconductor material.

1. Field of the Invention
The present invention relates to carbazole compounds that can be used as a light-emitting element material. The present invention further relates to light-emitting element materials, organic semiconductor materials, light-emitting elements, light-emitting devices, lighting devices, and electronic devices each using the carbazole compound.
2. Description of the Related Art
A display device using a light-emitting element (organic EL element) in which an organic compound is used as a light-emitting substance has been developed rapidly as a next generation lighting device or display device because it has advantages that such a light-emitting element can be manufactured to be thin and lightweight, has very high response speed with respect to an input signal, and has low power consumption.
In an organic EL element, when a voltage is applied between a pair of electrodes between which a light-emitting layer is interposed, electrons and holes injected from the electrodes are recombined to form an excited state, and when the excited state returns to a ground state, light is emitted. A wavelength of light emitted from a light-emitting substance is peculiar to the light-emitting substance; thus, by using different types of organic compounds as light-emitting substances, light-emitting elements which exhibit various wavelengths, i.e., various colors can be obtained.
In the case of a display device which is expected to display images, such as a display, in order to reproduce full-color images, at least light having wavelength components of three colors, i.e., red, green, and blue, is required to be obtained. In the case of a lighting device, in order to obtain high color rendering property, light having wavelength components thoroughly in the visible light region is ideally obtained. Actually, two or more kinds of light having different wavelengths are mixed to be used for lighting application in many cases. Note that it is known that by mixing light of three colors, red, green, and blue, white light emission having high color rendering property can be obtained.
Light emitted from a light-emitting substance is peculiar to the substance as described above. However, important performances as a light-emitting element, such as lifetime, power consumption, and emission efficiency, are not only dependent on a light-emitting substance but also greatly dependent on layers other than a light-emitting layer, an element structure, properties of the emission center substance and a host, compatibility between them, or the like. Therefore, it is true that many kinds of light-emitting element materials are necessary in order to show the growth of this field. For the above-described reasons, light-emitting element materials which have a variety of molecular structures have been proposed (for example, see Patent Document 1).
In particular, high-energy emission of blue light needs an emission center substance having a wide band gap and a host material having a wider band gap; therefore, it is difficult to say the variation of materials that can be used in fabricating a light-emitting element having favorable characteristics is sufficiently wide.

This patent is subject to a terminal disclaimer.

Carbazole compound, light-emitting element material, organic semiconductor material, light-emitting element, light-emitting device, lighting device, and electronic device

Semiconductor Energy Laboratory Co., Ltd.


A layout for packaging a computer rack comprises a transport pallet (2) and a computer rack; the computer rack being associable with casters extending vertically by a first distance relatively to a lower face of the rack. The computer rack is made integral with the pallet by two anchoring means distributed on the underside of the rack on either side of a vertical median plane (P1); the pallet includes two side modules and an intermediate supporting means separable from the remainder of the pallet and allowing the side modules to be connected. The side modules are removably attached to the anchoring means, so as to ensure that the computer rack is maintained in a horizontal position, and that the pallet is spaced away from the underside of the rack by a second distance (H2) smaller than said first distance.

1. Field of the Invention
The present invention relates to the field of high density type computer racks of data centers, network rooms and wiring cabinets. The invention more particularly concerns a layout and a packaging method used in the palletization and depalletization of a computer rack. A computer rack and a transport pallet specific to this original layout are also the object of the present invention.
2. Description of Related Art
In existing conventional methods, the computer rack is brought via its casters onto the upper platform of the pallet through a loading ramp integral with the pallets or added to the latter. The rack is then delivered to the client and then depalletized on site with the same method.
Although presently, these systems are easy to apply, they have a few limits all the same. The depalletization procedure which consists of lowering the rack from its pallet reveals a few deficiencies relating to the safety of the operators but also to the protection of the hardware. Two or even three operators are required for ensuring the lowering of a rack from its pallet. Indeed, the latter may weigh up to 1,200 kg and its dimensions do not allow it to be handled by a single person.
Unexpected phenomena, related to dynamics, may cause falling of the rack. Just to mention a few of them: unstable ramps, a rack which moves diagonally, and leaves its course, a rack which starts to accelerate because it is difficult to hold back because of its mass and its dimensions.
It should also be noted that the height of the palletized and packed rack assembly is limited by the passage height under the upper frame of the doors. So this therefore restricts the useful height of the rack when the trend is to try to maximize it. This useful height is generally expressed in the total number of units U from the EIA-31 0-0 standard, this unit allowing localization and vertical positioning of the computer equipment in a rack [1 U=44.45 mm].
Concretely, because of a door height limited to about 2 meters, a rack, the useful height of which is larger than 36 U, cannot be brought into the operating room with its pallet and its packaging. The latter pallet is generally depalletized outside the buildings. Several drawbacks then appear: the hardware is unpacked regardless of the weather (rain, wind, snow . . . ) and especially before it has reached the room temperature of the receiving room; the rack (maximum 1,200 kg) after depalletization is transported (by using its own carters) up to the room with certain difficulties due to the nature of the flooring and the declivity of the ground. These difficulties are reduced with the use of a handling truck which is much more flexible in use.
However, the use of a truck inside buildings does not allow the use of computer racks with a large height.

Computer rack and transport pallet method for packaging a computer rack


The present invention relates to a contact type finger mouse and an operating method thereof. The contact type finger mouse according to one embodiment of the present invention comprises: a pressure sensor unit for sensing pressure generated between a finger and a fixed surface through a plurality of pressure sensors fixed at a lower part of the finger; a signal processing unit for determining a movement direction and a movement speed value of a mouse pointer on the basis of pressure values acquired through the sensing; and a signal transmission unit for generating control data comprising information on the determined movement direction and the determined movement speed value of the mouse pointer, and transmitting the generated control data to an interworking device.

A type of a display device for delivering information is continuously changed. Recently, according to requirements for a small size, wearable display devices of an eyeglass type or a wristwatch type have become available.
In this manner, as wearable display devices evolve, a new type of a small wearable input device is necessary.

Contact type finger mouse and operation method thereof


A method and apparatus of applying a particulate material to a substrate includes applying adhesive to the substrate and passing the substrate through a chamber in which a particulate material is suspended in a fluid in order to adhere the particulate material to the substrate.

1. Field of the Invention
The present invention generally relates to a method and apparatus for applying a particulate material to a substrate and, more particularly, to a fluidized bed apparatus and method of using such apparatus for applying a particulate material to a substrate.
2. Background of the Related Art
Application of materials to a substrate is commonly performed in order to manipulate various mechanical, chemical, physio-chemical, and/or electronic properties of the substrate. Particulate materials such as powders and fibers represent forms of material that may be applied to a substrate in order to modify the properties thereof. For example, metal substrates may be coated with powdered organic resins. Upon application of sufficiently high temperatures, the resinous particles melt and fuse on the surface of the metal substrate to form a continuous coating that enhances the chemical resistance of the metal substrate.
Particulate materials may also be applied to fibrous substrates, such as aggregations of non-woven and synthetic fibers. The particulate may thereby become enmeshed within the fibrous aggregate. Substrates treated in this way may be used to form absorbent articles including feminine hygiene articles such as sanitary napkins, tampons, and panty liners, as well as diapers and incontinence articles. During the manufacture of such articles, a fluid-absorbing powder (e.g. a superabsorbent powder) is applied to a moving fibrous substrate. The superabsorbent powder is thereby transferred to the surface of the fibrous material or regions within the fibrous material, thus enhancing the absorbent properties of the fibrous substrate.
The application of particulate materials to a substrate may be accomplished by any one of a number of know conventional means. For example, particulates may be applied using mechanical delivery devices such as conduits, nozzle sprayers, and the like.
Unfortunately, using conduits, nozzles, and the like to deliver particulate material to a substrate, particularly a substrate moving at a high speed, is subject to variety of problems. For example, it is difficult to apply the particulate material to a pre-determined, localized area of the substrate. In particular, if the spraying of the powder is not initiated and terminated within a tightly defined time interval, the particulate may be delivered to undesired locations rather than the desired location on the substrate. Furthermore, the particulate material is often subject to spreading, i.e., the particulate does not remain localized on the substrate and the particulate may migrate to locations where it is not desired, thereby contaminating the process. The above problems are compounded for substrates, including fibrous substrates, which are often processed at line speeds that are fast enough to promote scattering of the particulate to undesired locations on the substrate. Therefore, a need exists for a method and apparatus for applying a particulate material to a substrate that overcomes one or more of the above-mentioned drawbacks.

Method and apparatus for applying particulate material to a substrate


A method for detecting an overvoltage signal applied to a semiconductor memory device address pin reduces stress on the device and simplifies the testing process by dividing the voltage of the overvoltage signal and comparing it to a reference voltage, thereby generating a difference signal. The difference signal is buffered by a drive stage which generates a test mode output signal that places the memory device in a test mode. An overvoltage detection circuit for implementing this method includes a comparison signal generator having a resistive voltage divider for dividing the overvoltage signal and generating a comparison signal. A differential amplifier compares the comparison signal to a reference signal from a reference signal generator. The differential amplifier generates a difference signal which is coupled to a drive stage which generates a test mode output signal. The comparison signal generator, the differential amplifier, and the drive stage can be enabled in response to a test mode enable signal.

The present invention relates to semiconductor memory device testing, and more particularly, to a method and apparatus for detecting an overvoltage signal applied to a memory device input pin.
Advances in manufacturing processes and device design have led to improved semiconductor memory devices. Process advances have resulted in highly integrated devices which can store a large amount of information in a small area. Design advances have improved the access speed and power consumption of semiconductor memory devices, as well as the techniques by which the characteristics of a memory device are verified and analyzed. These advances have been especially noteworthy in the area of dynamic random access memory (DRAM).
In a DRAM semiconductor device, an address signal, which is normally used for selecting a specific memory cell, is used in conjunction with control signals /RAS (row address strobe), /CAS (column address strobe), and /W (write) to control read, write, refresh, and test mode operations. However, due to the limited number of control signals that are available, new test modes such as parallel test mode have been developed.
Timing signals for a parallel test mode operation are shown in FIG. 2. (Address signals have been omitted from FIG. 2.) This timing is commonly referred to as test mode timing. By entering a parallel test mode using the timing sequence shown in FIG. 2, data from more memory cells can be accessed than during a normal read or write operation, and the time required for testing all cells of a DRAM semiconductor device is reduced accordingly. For example, if data from four memory cells is accessed during a normal read or write operation, data from sixteen or more memory cells can be accessed in a parallel test mode.
In a parallel test mode, the data from four or more memory cells is compared internally and accessed through one input/output (I/O) pin. If the data from the four or more memory cells which are being tested in parallel are the same, the output from the I/O pin is "1" (high logic level). If any of the data from the four or more memory cells are different, the output is "0" (low logic level). The output information only indicates whether all of the cells tested in parallel have the same data, but does not indicate what the state of the data is.
To provide more information from a parallel test mode operation, a new method has recently been proposed. According to this new method, a parallel test mode is entered using the timing sequence shown in FIG. 2. If the data from the parallel memory cells are all "1s", a "1" is output through the I/O pin. However, if the data in the memory cells are all "0", a "0" is output through the I/O pin. If the data in any of the memory cells are different, the I/O pin is placed in a high impedance state.
To enter this new parallel test mode, overvoltage signal is applied to a specified address pin in addition to the timing sequence illustrated in FIG. 2. Thus, an overvoltage detection circuit is necessary for sensing the overvoltage signal.
A conventional overvoltage detection circuit for placing a semiconductor memory device in a parallel test mode is shown in FIG. 1. The circuit of FIG. 1 includes three NMOS transistors 11, 13, and 15 connected in series and functioning as a diode to transfer the signal Ai to a node N1. The signal Ai is an address signal during normal operation and an overvoltage signal in test mode. An NMOS transistor 17 is connected between a supply voltage signal VINT and node N1 and functions as a resistor. PMOS transistor 19 is connected between nodes N1 and N2 to transfer the voltage signal from node N1 to node N2. An NMOS transistor 21 has a current path connected between node N2 and a ground terminal and is controlled by a signal VREF applied to its gate. Two series connected inverters 23 and 25 receive the signal from node N2 and generate the signal SVAi.
In operation, when a power supply voltage is applied to the circuit, node N1 is precharged to (VINT-Vtn), where Vtn is the threshold voltage of NMOS transistor 17. NMOS transistor 21 is turned on by the reference voltage VREF, thereby pulling the voltage of node N2 to ground. Since PMOS transistor 19 is off, nodes N1 and N2 are electrically disconnected, and the voltage of node N2 forces the signal SVAi to "0". If the voltage of signal Ai is increased to an overvoltage level, the voltage of node N1 is gradually increased through the three NMOS transistors 11, 13, and 15.
If the voltage of node N1 increases to a level greater than (VINT+Vtp), where Vtp is the threshold voltage of PMOS transistor 19, PMOS transistor 19 turns on thereby causing the voltage of node N2 to increase. If the current flowing from node N1 to N2 through PMOS transistor 19 exceeds the current flowing from node N2 to ground through NMOS transistor 21, the voltage of node N2 increases, and if the voltage at node N2 exceeds the trip point of inverter 23, the signal SVAi switches to "1".
The overvoltage level applied to the input Ai is higher than the supply voltage and is only used to place the semiconductor memory device in test mode. Thereafter, the signal Ai is used as a normal address signal.
When a normal supply voltage level of 5 V is used, an overvoltage level of 7 V is applied to Ai to place the device in test mode. However, during test and development of most semiconductor memory devices, supply voltages which are greater than the normal supply voltage are often used. When a higher supply voltage is used, the overvoltage level must be increased accordingly to cause PMOS transistor 19 to turn on. The voltage of node N1 must be greater than (VINT+Vpt) to cause PMOS transistor 19 to turn on.
When a supply voltage which is greater than 5 V is used, an overvoltage level of greater than 7 V must be applied to pin Ai to place the device in test mode. However, applying a voltage greater than 7 V to an address pin stresses the semiconductor device connected to the pin and can result in damage to the device and an accompanying loss of functionality. Moreover, if the supply voltage is varied, the overvoltage level must be varied accordingly, thereby complicating and adding inconvenience to test mode operation.

Overvoltage detection circuit for generating a digital signal for a semiconductor memory device in parallel test mode


A portable hard rock drill rig uses fluids for rotational power and compressed air to achieve a hammer affect. The drill rig is comprised of modular parts configured to allow one or two workers to move the rig over difficult terrain and to assemble the rig within a small area.

(1) Field of the Invention
The invention generally relates to earth drilling systems. More particularly, the invention relates to means and methods of creating portable and versatile earth drilling systems.
(2) Description of the Related Art
Other portable drilling systems are known in the related art. For example, U.S. Pat. No. 6,533,045 issued on Mar. 18, 2003 to Cooper discloses a mounting system secured to the bed of a truck.
U.S. Pat. No. 6,848,515 issued on Feb. 1, 2005 to Orr et al discloses a bulky transport structure to move drilling equipment.
U.S. Pat. No. 4,192,393 issued on Mar. 11, 1980 to Womack et al discloses a portable drilling system suited for helicopter transport.
U.S. Pat. No. 4,161,988 issued on Jun. 24, 1979 to Hart discloses a portable earth core sampling machine using an awkward frame system having a heavy piston component and a rope pulley system.
Thus, there is ample room in the art for the disclosed systems and methods.