Provided are a method and apparatus for sending Hybrid Automatic Repeat Request Acknowledge (HARQ-ACK) information. The method includes: when a terminal employs a physical uplink control channel (PUCCH) format 3 to transmit HARQ-ACK information and the HARQ-ACK information is transmitted over a uplink physical shared channel (PUSCH), determining the number of downlink subframes for serving cells to feed back the HARQ-ACK information; determining the number of encoded modulated symbols required for sending the HARQ-ACK information according to the determined number of downlink subframes; and mapping the HARQ-ACK information to be sent to the PUSCH of a specified uplink subframe according to the number of encoded modulated symbols and sending the HARQ-ACK information. The technical solutions provided by the disclosure are applied to improve the performance of the HARQ-ACK information, and thus improve the data performance.

A radio frame in a Long Term Evolution (LTE) system includes a frame structure of a Frequency Division Duplex (FDD) mode and a frame structure of a Time Division Duplex (TDD) mode. As shown in FIG. 1, in the frame structure of the FDD mode, one radio frame of 10 ms is composed of twenty slots with the length of 0.5 ms and serial numbers of 0-19, and slots 2i and 2i+1 make up a subframe i with the length of 1 ms (wherein, 0≦i≦9). As shown in FIG. 2, in the frame structure of the TDD mode, one radio frame of 10 ms is composed of two half frames with the length of 5 ms, wherein one half frame includes 5 subframes with the length of 1 ms, and subframe i is defined as the combination of two slots 2i and 2i+1 with the length of 0.5 ms (wherein, 0≦i≦9). The uplink and downlink configurations supported by each subframe are as shown in Table 1, wherein "D" represents subframes dedicated to downlink transmission, "U" represents subframes dedicated to uplink transmission, "S" represents special subframes used in the three domains of Downlink Pilot Time Slot (DwPTS), Guard Period (GP) and Uplink Pilot Time Slot (UpPTS).
TABLE 1Schematic table of uplink and downlink configurationssupported by each subframeUplink-Period ofDownlinkdownlink-configur-uplinkSubframe number #ationswitch point012345678905msDSUUUDSUUU15msDSUUDDSUUD25msDSUDDDSUDD310msDSUUUDDDDD410msDSUUDDDDDD510msDSUDDDDDDD65msDSUUUDSUUD
It can be seen from the above table that the Long Term Evolution (LTE) TDD supports uplink and downlink switch periods of 5 ms and 10 ms. If the period of downlink-to-uplink switch point is 5 ms, then special subframes would exist in two half frames; and if the period of downlink-to-uplink switch point is 10 ms, then special subframes would only exist in the first half frame; the subframe #0 and the subframe #5 and the DwPTS are always used for downlink transmission; and the UpPTS and subframes following the special subframes are dedicated to uplink transmission.
In the LTE TDD system, since the uplink and downlink subframes are not in one-to-one correspondence, that is, the HARQ-ACK information of a plurality of downlink subframes needs to be sent in the Physical Uplink Control Channel (PUCCH)/Physical uplink shared channel (PUSCH) of one uplink subframe, wherein the set of downlink subframes associated with the uplink subframe makes up a bundling window. Two methods of sending the HARQ-ACK information are defined: one is a HARQ-ACK bundling method, and the other is a HARQ-ACK multiplexing method. Whether UE (User Equipment) employs the method of bundling or multiplexing to feed back the HARQ-ACK information is configured by the high-layer. The basic principle of the bundling method is to carry out a logical AND operation (time domain bundling) on the HARQ-ACK information of the code word streams corresponding to respective downlink subframes needing to be fed back in the uplink subframe, to obtain the HARQ-ACK information of ½ bit. When a UE has no PUSCH to send in a current subframe, the UE would employ a format of 1a/1b to send the ½ bit HARQ-ACK information in the PUCCH; and when the UE has PUSCH to send in a current frame, the UE sends the ½ bit acknowledge information in the PUSCH after performing certain channel encoding and channel interleaving on the ½ bit acknowledge information. The core principle of the multiplexing method is to utilize different PUCCH channels and different modulated symbols on each channel to represent different feedback states of the downlink subframes that need to be fed back in the uplink subframe, and if there are a plurality of transport blocks on the downlink subframes, then firstly spatial logic AND (also referred to as spatial domain bundling) is carried out on the HARQ-ACK information fed back by the plurality of transport blocks of the downlink subframes, then channel selection is performed, and then the PUCCH format 1b is used to send the HARQ-ACK information. When the UE has no PUSCH to send in a current subframe, the UE would employ the format 1b with channel selection to send the plurality of pieces of HARQ-ACK information on the PUCCH; and when the UE has PUSCH to send in a current subframe, then the UE multiplexes a plurality of pieces of bit acknowledge information with data after certain mapping from HARQ-ACK states to corresponding bits, channel encoding, channel interleaving are performed to the bit acknowledge information, and then sends them on the PUSCH.
The encoding process when the HARQ-ACK information is transmitted on the PUSCH includes: firstly calculating the number Q′ACK of the symbols needed to be encoded according to the formula
            Q      ACK      ′        =          min                    (                              ⌈                                          O                ·                                  M                  sc                                      PUSCH                    -                    initial                                                  ·                                  N                  symb                                      PUSCH                    -                    initial                                                  ·                                  β                  offset                  PUSCH                                                                              ∑                                      r                    =                    0                                                        C                    -                    1                                                                                K                  r                                                      ⌉                    ,                      4            ·                          M              sc              PUSCH                                      )              ;wherein O represents the number of bits of the uplink control information to be sent; MscPUSCH represents the bandwidth for PUSCH transmission in a current subframe, and this value is expressed as the number of carriers; NsymbPUSCH-initial represents the number of symbols except for those used for the Demodulation Reference Signal (DMRS) and the Sounding Reference Signal (SRS) in the initial PUSCH transmission; MSCPUSCH-initial represents the bandwidth in the initial PUSCH transmission, and this value is expressed as the number of carriers; C represents the corresponding number of code blocks after the transport blocks are subjected to CRC and code block division; Kr represents the number of bits corresponding to each code block of the transport block; for an identical transport block, C, Kr and MSCPUSCH-initial are obtained from an initial PDCCH; when there is no initial PDCCH with DCI format 0, MSCPUSCH-initial C and Kr could be obtained in the following two ways: (1) when the initial PUSCH employs semi-static scheduling, they could be obtained from the PDCCH configured by the latest semi-static scheduling; (2) when the PUSCH is triggered by a random access response authorization, they are obtained from the random access response authorization corresponding to the same transport block. βoffsetPUSCH represents βoffsetHARQ-ACK or βoffsetRI, the value is configured by the high-layer. Afterwards, channel encoding is carried out on the HARQ-ACK information, and the bits of the encoded HARQ-ACK information are repeated, until a target length QACK=Q′ACK·Qm is satisfied. The bits of the encoded information are respectively recorded as [q0ACK, q1ACK, q2ACK, . . . , qQACK-1ACK], a corresponding encoding modulation sequence [q0ACK, q1ACK, q2ACK, . . . , qQ′ACK-1ACK] is generated according to a modulation order, and [q0ACK, q1ACK, q2ACK, . . . , qQ′ACK-1ACK] and encoded data and/or other encoded uplink control information are transmitted after channel interleaving.
In order to satisfy the requirements of the International Telecommunication Union-Advanced (ITU-Advanced), the Long Term Evolution Advanced (LTE-A) system, as the LTE evolution standard, needs to support a greater system bandwidth (up to 100 MHz), and needs to be backward compatible with the existing standards of the LTE. On the basis of an existing LTE system, a greater bandwidth could be obtained by combining the bandwidths of the LTE system, and such a technique is called a Carrier Aggregation (CA) technique. The technique could improve the spectrum efficiency of an IMT-Advance system, relieve the shortage of spectrum resources, and thus optimizing the utilization of spectrum resources. The bandwidth of the LTE system using the carrier aggregation could be regarded as a Component Carrier (CC), each Component Carrier could also be called a cell, that is, a spectrum could be aggregated by n Component Carriers (n cells). The resources of a R10 terminal (User Equipment, UE) are composed of n cells/Component Carriers in the frequency domain, wherein one cell is called a Primary cell (Pcell), and the rest cells are called Secondary cells (Scells). For the TDD, the uplink and downlink configurations of the aggregated serving cells are the same.
In the LTE-A TDD, when the HARQ-ACK information is sent on the PUCCH, two sending ways are defined: the PUCCH format 1b with channel selection and the PUCCH format3.
It is also defined in the LTE-A that, when uplink and downlink configurations 1-6 are employed and the number of configured serving cells is greater than 1, or when the TDD uplink and downlink configurations 1-6 are employed, the number of the configured serving cells is equal to 1 and the configuration employs the PUCCH format3, the DAI value in the DCI format 0/4 is WDAIUL, and the specific value is as shown in Table 2. If there is no PUSCH transmitted, or, there is no PDCCH indicating downlink release and there is transmission of corresponding DCI format 0/4, WDAIUL=4.
TABLE 2Corresponding WDAIUL values of DAI in the DCI format 0/4DAIHigh bit, low bitWDAIUL0, 010, 121, 031, 14
When the HARQ-ACK information is transmitted over the PUSCH and it is configured to employ the PUCCH format3 to transmit the fed back HARQ-ACK information, for TDD uplink and downlink configuration 0 or PUSCH transmission not performed according to the DCI format 0/4, BcDL=M, wherein BcDL is the number of downlink subframes for which the UE needs to feed back the HARQ-ACK for the serving cell c, and M is the number of downlink subframes in a bundling window; for the TDD uplink and downlink configurations {1, 2, 3, 4, 6} and PUSCH transmission performed according to the DCI format 0/4, BcDL=WDAIUL; and for the TDD uplink and downlink configuration 5 and PUSCH transmission performed according to the DCI format 0/4, BcDL=WDAIUL+4└(U−WDAIUL)/4┘, wherein U represents the maximum Uc of all serving cells, Uc refers to the accumulative number of the PDCCH indicating the SPS release and the PDSCH received on the serving cell c, and if the UE does not receive the PDSCH or the PDCCH indicating downlink SPS release and WDAIUL=4, the UE would not transmit the HARQ-ACK on the PUSCH.
In the subsequent version, when carrier aggregation is supported, the uplink and downlink configurations of aggregated serving cells could be different, that is to say, the numbers of downlink subframes for which the HARQ-ACK information needs to be fed back for respective serving cells are different, in which case, if the existing solution of transmitting HARQ-ACK information on the PUSCH is still employed, transmission of some invalid HARQ-ACK information would be caused. As shown in FIG. 3, assuming WDAIUL=4, the HARQ-ACK information transmitted over the PUSCH according to the existing HARQ-ACK information transmission solution is 8 bits, but the HARQ-ACK information that actually needs to be fed back is only 5 bits, and 3 bits of invalid HARQ-ACK information are transmitted to a base station, thus affecting the performance of HARQ-ACK information and data.

Method and apparatus for sending hybrid automatic repeat request acknowledge information


The invention is a cosolvent parenteral pharmaceutical formulation of a lazaroid and its pharmaceutically acceptable salts.

1. Field of the Invention
The invention is a cosolvent parenteral pharmaceutical formulation of lazaroid compounds.
2. Description of the Related Art
International Publication No. WO87/01706 based on International Patent Application No. PCT/US86/01797 and U.S. Pat. No. 5,175,281 disclose 21-4-2,6-bis(1-pyrrolidinyl)-4-pyrimidinyl!-1-piperazinyl!-16.alpha.-met hylpregna-1,4,9(11)-triene-3,20-dione (EXAMPLE 83), which is known as tirilazad, and the mesylate salt (EXAMPLE 109) which is known as tirilazad mesylate for use as neurological agents.
The Journal of Pharmacology and Experimental Therapeutics, 269, 145-50 (1994), International Journal of Clinical Pharmacology and Therapeutics, 32, 223-230 (1994) and Pharmaceutical Research, 11(2) 341 (1994) disclose 21-4-2,6-bis(1-pyrrolidinyl)-4-pyrimidinyl!-1-piperazinyl!-16.alpha.-met hyl-5.alpha.-pregna-1,9(11)-diene-3,20-dione (5.alpha.-tirilazad).
U.S. patent application Ser. No. 08/278,633 discloses 21-4-2,6-bis(1-pyrrolidinyl)-4-pyrimidinyl!-1-piperazinyl!-16.alpha.-met hyl-5.alpha.-pregna-1,9(11)-diene-3,20-dione (5.alpha.-tirilazad) and the 5.beta.-isomer (5.beta.-tirilazad) and pharmaceutically acceptable salts thereof.
U.S. patent application Ser. No. 08/361,818 discloses 6.alpha.-hydroxy-21-4-2,6-bis(1-pyrrolidinyl)-4-pyrimidinyl!-1-piperazin yl!-16.alpha.-methylpregna-1,4,9(11)-triene-3,20-dione (6.alpha.-hydroxytirilazad) and 6.beta.-hydroxy-21-4-2,6-bis(1-pyrrolidinyl)-4-pyrimidinyl!-1-piperaziny l!-16.alpha.-methylpregna-1,4,9(11)-triene-3,20-dione (6.beta.-hydroxytirilazad) and pharmaceutically acceptable salts thereof.
U.S. Pat. No. 4,968,675 discloses a parenteral formulation of tirilazad mesylate in citrate buffer. The present invention in addition uses a cosolvent which causes less irritation and pain when used as intended (diluted).
Cosolvents have become widely used as a means for solubilizing drugs for non-parenteral and parenteral (both IV and IM) administration. The effect is dependent primarily upon the polarity of the drug with respect to the solvent (water) and the cosolvent. The degree to which the solubility of a drug can be increased for a particular cosolvent is dependent upon the nonpolarity of the drug and the nonpolarity of the cosolvent. The most frequently used cosolvents are propylene glycol, ethanol, glycerine, and polyethylene glycol. The solubilization curves of a number of pharmaceutically important solutes in cosolvent systems is known, Techniques of Solubilization of Drugs, edited by S. H. Yalkowsky, Marcel Dekker, INC 1981, more particularly see Solubilization of Drugs by Cosolvents, p 91-134.
U.S. Pat. No. 4,794,117 and International Publication No. WO85/04106 disclose that solubilization of hydrophobic pharmaceuticals, e.g. steroids, may be accomplished by solution in polyethylene glycol and addition of aqueous solutions of controlled pH and buffering.
Buffers in parenteral formulations are known.
Journal of Pharmaceutical Science and Technology, 48, 86-91 (1994) discloses that for that particular drug lower acetate buffer concentration caused less irritation than higher acetate buffer concentration. It was further disclosed that citrate buffer concentration of 0.01M caused less irritation than acetate buffer concentration at 0.005M with the particular drug used.

Cosolvent parenteral formulation of tirilazad


This invention concerns a method and system for automatically determining heart rate. The invention can be applied to determining the heart of any animal including humans. The method involves sensing body sounds and transducing them to electrical signals. Digitizing the electrical signals. Emphasizing the heart sound maxima (S1 and S2 signals) relative to noise by filtering, decompression and squaring. Detecting local maxima in the signals as likely S1 signals and generating a threshold amplitude. Selecting maxima that exceed the threshold as surviving likely candidate S1 signals. Screening the surviving candidate S1 against physiologically derived criteria. And, calculating the heart rate from the screened S1.

Vibration of the heart valves generates heart sounds. The valves are forced into vibration at the instants of the valves' closure, caused by abrupt increase of the blood pressure gradient. A first heart sound (S1) is generated at the end of diastole, while a second heart sound (S2) is produced at the end of the systole. The sounds are transmitted through the body and can be heard on the body surface by use of the stethoscope, or be recorded using a sound transducer. Although heart sounds have been recorded in the past, they have not been used to automatically determine heart rate. The major problem being that for each heart beat there are four sounds generated by valve closure, typically grouped in pairs.


A securing bracket for a floor supported laundry appliance, such as a washing machine or a clothes dryer. The securing bracket is connected between the rear legs of the appliance and an adjacent wall to prevent skidding of the appliance on the floor. The securing bracket also includes a shock absorber for dampening vibrations transmitted from the appliance to the securing bracket and an attached wall.

Floor supported laundry appliances, such as washing machines and clothes dryers, experience significant vibrations during the spin and tumbling cycles of the machines. At times, these vibrations can cause the machine to skid on the floor away from its original location.
In an attempt to overcome this problem, it has been proposed to provide the supporting legs of the appliance with skid resistant and vibration dampening pads. While these pads initially provide the necessary skid resistance and vibration dampening, they soon become deteriorated and have to be replaced.
It has also been proposed to connect the appliance to a bracket which, in turn, is connected to the floor or adjacent wall. While this arrangement prevents the appliance from skidding, there is no provision for vibration dampening resulting in the floor or wall eventually cracking; thus releasing the bracket secured thereto.
After considerable research and experimentation, the securing bracket of the present invention has been developed which not only prevents skidding of the appliance on the floor but also dampens the vibration transmitted to the securing bracket.

Securing bracket for a floor supported laundry appliance


Modular infrared heater units for a sauna and methods for constructing a sauna. The infrared heater units include one or more heating elements disposed in a housing. The housing is configured for direct mounting on walls of a structure and includes a pigtail for coupling to a controller. The housing is dimensioned to accommodate a paneling or other cladding on the walls and includes a trim frame that obscures edges of the cladding adjacent to the heater unit. Construction of a sauna unit includes mounting of a plurality of the heater units on walls of the structure; electrically communicably coupling the heater units to a controller; and providing any desired cladding to the interior of the structure.

The popularity of saunas for treatment of a myriad of conditions is ever increasing. With that comes increased interest in incorporating sauna units into residential dwellings and commercial spaces. One available option is a stand-alone, pre-manufactured sauna unit that can be disposed in an existing location. Another option is an integrated sauna unit that is constructed in and potentially as part of the structure at a location. Yet another option is a stand-alone heating unit that can be disposed in a room or other location to provide sauna-like qualities and/or infrared heating to the room.
Construction of such integrated sauna units can be complex and much more expensive than simply disposing a stand-alone unit in an available space. For example, construction may require access to the internal structures at the location, i.e. access to studs or support members in walls, ceilings, etc. Additionally, certain design characteristics like clearance between insulation in the walls of the structure and heating elements of the sauna must be adhered to for safety. A licensed electrician is also likely required to design and provide connections between the heating units and a controller for the sauna unit as well as between the sauna unit and a power grid of the structure.

Modular sauna heater and method for constructing a sauna


Systems and methods for voice mail delivery may include receiving a voicemail by a device of a subscriber, determining if the subscriber is a member of a group of members, and, upon a determination that the subscriber is a member of the group, combining the voice mail message with a second voice mail message received by a member of the group other than the subscriber to generate a combined voice mail message.

The emergence of visual voice mail has made the use of voice mail more convenient and user friendly. This is especially true for heavy users who may have dozens of unread voice mails at one time stored on a server for delivery. Rather than have to serially listen to each individual voice mail message, visual voice mail users are able to see a summary of the incoming messages and select which messages to review and in which order to review them.
Some advanced voice mail systems also will translate voice messages to text messages in order to deliver voice mail messages in a more convenient format for some users under some circumstances. Voice mail indication signals are also used for the convenience of the subscriber to indicate the receipt of a voice mail.
Mobile long term evolution (LTE) networks are also being deployed. Such high speed networks may more efficiently transport voice and data among and between users. Thus there is a need to be able to adapt visual voice mail features and functionality in order to take advantage of LTE.

This patent is subject to a terminal disclaimer.


A gas barrier film includes an anionically functionalized matrix resin and a platy mineral filler. The formed film is surface-treated with a multi-valent metal cation crosslinking agent to stabilize the barrier film against performance loss at elevated levels of relative humidity.

Barrier coatings (layers) which prevent, reduce, or inhibit the permeation of a selected substrate with a gas, vapor, chemical and/or aroma have been widely described, and such coatings are used in a variety of industries, e.g., the packaging industries, automobile industries, paint industries, tire industries etc. Typical barrier materials used in coatings include polyesters, PVDC, polyurethanes, acrylic polymers, etc.
It is well known that the barrier properties of a polymer can be improved by the addition of impermeable plate like structures such as kaolin, vermiculite, montmorillonite and so forth. When the plates are oriented perpendicular to the diffusion (permeation) direction, the diffusing molecules must go around the plates. This leads to significant reductions in the permeability of the polymer. See, for example, E. L. Cussler et al, J. Membrane Sci. 38:161-174 (1988); W. J. Ward et al, J. Membrane Sci., 55:173-180 (1991); Chang, J. et al, Journal of Applied Polymer Science, Vol. 84, 2294 (2002); Yano, K. et al, Journal of Polymer Science A: Polymer Chemistry, 35, 2289 (1997); Lan, T. et al, Chem. Mater. 6, 573 (1994); Messersmith, P. B. and Giannelis, E. P, Journal of Polymer Science A: Polymer Chemistry 33, 1047 (1995); U.S. Pat. Nos. 4,528,235; 4,536,425; 4,911,218; 4,960,639; 4,983,432; 5,091,467; and 5,049,609; and International Patent Application No. WO93/04118, published Mar. 4, 1993, among others.
Some particularly preferred nanocomposite gas barrier coatings are disclosed in the following: U.S. Pat. No. 7,078,453, entitled "Barrier Coating of a Non-Butyl Elastomer and a Dispersed Layered Filler in a Liquid Carrier and Coated Articles", to Feeney et al.; U.S. Pat. No. 7,119,138, entitled "Barrier Coating of a Mixture of Cured and Uncured Elastomeric Polymers and a Dispersed Layered Filler in a Liquid Carrier and Coated Articles", to Feeney et al.; and U.S. Pat. No. 7,473,729, entitled "Barrier Coating Mixtures Containing Non-Elastomeric Acrylic Polymer with Silicate Filler and Coated Articles", to Feeney et al., as well as copending United States Patent Applications Publication Nos. US 2007/0213446, entitled "Barrier Coating of a Non-Elastomeric Polymer and a Dispersed Layered Filler in a Liquid Carrier and Coated Articles", of Feeney et al.; US 2008/0131707, entitled "Concentrated Aqueous Nanocomposite Dispersions for Barrier Coatings", of Feeney et al.; and US 2006/0110615, entitled "Multilayer Nanocomposite Barrier Structures", of Karim et al., the disclosures of which are incorporated herein by reference.
Despite many advances in the art, composite barrier coatings tend to exhibit performance degradation due to elevated relative humidity. The present invention provides coatings which resist such performance degradation upon exposure to elevated levels of relative humidity.

Barrier coatings post-formation treated with multi-valent metal cations


A circuit board, which is formed with bump patterns subject to a narrow variation in height on the surface of the circuit board, and which permits high-density packaging of a semiconductor component thereon. In this circuit board, conductor circuits formed by electroplating are embedded in an insulating base that is formed of a resist layer and an insulating substrate, and bumps are exposed in the surface of the insulating base. The bumps and the conductor circuits are connected electrically with one another by means of pillar-shaped conductors that are formed by electroplating. Each bump is a multilayer structure in two or more layers formed by successively depositing different electrically conductive materials by electroplating.

1. Field of the Invention
The present invention relates to a circuit board having patterns in the form of bumps with a very narrow variation in height projecting from at least one surface thereof, and more specifically, to a circuit board formed having high-reliability conduction structures between its general output and input terminals and conductor circuits and which is capable of high-density packaging of semiconductor devices. The present invention also relates to a bump-type contact head obtained with use of the circuit board, capable of satisfactorily checking even fine-pitch circuit components, such as LSIs, liquid crystal panels, TABs, PDPs, etc., for wiring failures, and which enjoys high accuracy in pitches between inspection terminals and excellent high-frequency characteristics. In addition, the present invention relates to a method for manufacturing these elements with high productivity and at low cost.
Still further, the invention relates to a semiconductor component packaging module of a novel connection structure, using the aforesaid circuit board as a packaging substrate and having various semiconductor components mounted on the substrate by die bonding.
2. Prior Art
Usually, a semiconductor device package, which may be incorporated in various electronic apparatuses such as a computer, portable communication apparatus, liquid crystal panel, etc., is constructed so that one semiconductor device, such as a bare chip, is mounted on a circuit board that is formed with predetermined patterns for conductor circuits, the continuity between this device and the respective output and input terminals of the conductor circuits is established to package the semiconductor device, and the whole structure is resin-molded.
The semiconductor device may be packaged by a method in which it is die-bonded to the circuit board and the output and input terminals of the circuit board and the terminals (lands) of the semiconductor device are wire-bonded, a method in which a flip chip is connected to the output and input terminals of the circuit board by, for example, soldering, or a method in which the output and input terminals of the circuit board and lead terminals of the semiconductor device are directly connected by soldering.
The semiconductor device package manufactured in this manner is incorporated in practical equipment by being mounted on a mother board (packaging substrate) on which the conductor circuits with the predetermined patterns are arranged. Usually, in this case, the area ratio of one semiconductor device package to the mother board ranges from about 1/10 to 1/5, so that a plurality of semiconductor device packages can be mounted on the mother board.
Conventionally, wire bonding is partially used for the mounting on the mother board. To meet the requirement for high-density packaging, however, a novel method has recently started to be widely used such that cream solder is pattern-printed on the lands of the mother board, the terminals (lead terminals or ball grid arrays) of the semiconductor device package are registered on the resulting pattern, and the whole resulting structure is subjected to blanket soldering in a reflow device.
There is a growing tendency for modern electronic apparatuses to become smaller in size, higher in operating speed, and more diverse in function. Accordingly, there is an increasing demand for the development of circuit boards capable of high-density packaging of semiconductor components despite the smallness in overall size.
To this end, it is advisable to use multilayer circuit boards and fine-pattern conductor circuits to be formed. Usually, however, conventional multilayer circuit boards are manufactured by the so-called build-up method, so that they involve the following problems.
In manufacturing a multilayer circuit board by the build-up method, a unit circuit board is first prepared by forming a conductor circuit, which serves as a signal pattern, on the surface of an insulating substrate as a bottom layer. Another unit circuit board, which is formed with another conductor circuit as another signal pattern, is put on the first one for unification. This operation is repeated so that a plurality of unit circuit boards are successively assembled from bottom to top.
In this case, a conduction structure between conductor circuits in each two adjacent layers, upper and lower, usually includes a plurality of through holes bored in a predetermined plane pattern through the unit circuit board in the thickness direction thereof. After the wall surface of each through hole is given electrical conductivity by, for example, electroless plating, electroplating is carried out with use of the conductor circuit in the lower layer as an electrical conduction path, and the respective lands of the conductor circuits in the upper and lower layers are connected electrically by means of the resulting deposit.
In order to effect the high-density packaging, therefore, the through holes should be made small in diameter. Practically, however, the hole diameter can be reduced only limitedly.
Generally, the through holes are formed by drilling, so that their diameter cannot be made very small in consideration of the drilling strength. Normally, the diameter of drilled holes ranges from 150 to 200 .mu.m. The diameter of through holes formed by photolithography ranges from about 100 to 150 .mu.m.
In the case where a deposit is formed on the wall surface of each bored through hole by combining the electroless plating and electroplating, it must secure a certain measure of thickness, since the electrical continuity between the conductor circuits in the upper and lower layers cannot be satisfactory if the deposit is too thin. For good electrical conduction between the conductor circuits, the thickness of the deposit is normally adjusted to about 20 to 30 .mu.m, depending on the type of the circuit board.
In general, therefore, a deposit with a thickness of 15 to 20 .mu.m is formed on the surface of each through hole with a diameter of 150 to 200 .mu.m, in the conduction structure based on the through holes. In the center of each through hole, in this case, exists a dead space with a diameter of about 100 to 150 .mu.m that has no connection with the conduction between the conductor circuits at all.
Also in the case of inner via holes, a dead space with a diameter of about 60 to 70 .mu.m is created if the diameter of each hole is, for example, 100 .mu.m. Thus, the diameter of the conventional through holes or inner via holes can be reduced only limitedly, and has no effect on the conduction between the conductor circuits, inevitably.
Normally, the following operation is carried out to form the deposit on the wall surface of each through hole in each of inner layers that are built up in succession. After electrical conductivity is given to the whole surface of a target inner layer (including the wall surface of each existing through hole or inner via hole) by electroless plating, a thin deposit is formed by electroplating the inner layer surface. Then, a dry film, for example, is sticked on the surface of the deposit so as to cover it, and is exposed and developed to expose only those portions corresponding to the through holes. The resulting structure is further electroplated with the remaining portion masked, whereupon a deposit of a given thickness is formed on the surface of each through hole (and land). Thereafter, the dry film is separated, and the thin deposit on the exposed surface of the inner layer and the deposit formed by the electroless plating are removed by, for example, soft etching.
In manufacturing a multilayer circuit board by building up the individual inner layers, therefore, the aforesaid operation must be repeated for each inner layer, so that complicated manufacturing processes are required. Thus, the manufacture takes long time, inevitably entailing high manufacturing costs.
In the case of the inner via holes, solid conduction structures may be formed between the layers by forming a deposit on the wall surface of each via hole and then embedding, for example, electrically conductive paste in the dead space remaining in the center of the deposit.
In this case, the solid conduction structures may possibly be formed by simultaneously electrodepositing and filling a conductive material in all the via holes by electroplating in place of the embedding of the conductive paste. In the build-up method, however, it is necessary to provide a conduction path separately for an input terminal for electroplating in advance in the first stage of the manufacture, so that the manufacturing processes are more complicated.
In forming a packaging substrate such as a semiconductor device package or a circuit board, such as a mother board, that has a projecting bump pattern on its packaging surface by the build-up method, a bump material is electrodeposited by, for example, electroplating to form the bump pattern with an intended height on a predetermined portion of a conductor circuit in the top layer, among other conductor circuits built: up in succession.
In actual electroplating operation, however, all bumps that constitute the bump pattern cannot be formed with the same height, due to influences of delicate fluctuation in the plating conditions or variation in the flows of electric current to spots for the formation of the individual bumps, so that the bump height varies. In the case where the target bump height is 0.03 mm, for example, the bump height variation is about .+-.0.003 mm.
If the variation in the bump height is too wide, then some bumps will not be connected to the lands of the semiconductor device package even though the lands are positioned for a reflow process. Thus, reliable packaging cannot be effected.
In consideration of these circumstances, it is necessary to minimize the variation in the height of the bumps in the case of the circuit board that has the bump pattern formed on its packaging surface.
A contact head for checking wiring circuits in LSIs, liquid crystal panels, etc. for troubles is a kind of circuit board. Conventionally, in the contact head of this type, pin probes or L-shaped needles are embedded in an electrically insulating rigid material, and are fixed to the body of the head at predetermined pitches so that their respective tip ends can come into contact with predetermined inspection spots in a wiring circuit as an object of inspection. Also, wires are soldered individually to the respective other ends of the probes or needles so that signals for the inspection spots can be fetched from the other ends. On the other hand, there is a bump system in which bumps are formed by, for example, electroplating in specific circuit portions of a circuit board that has a predetermined circuit pattern, or by a film forming method that is used in the field of semiconductor production, and these bumps are operated in place of the aforesaid pin probes or L-shaped needles.
Recently, the circuit patterns of various circuit components as objects of inspection, and therefore, the pitches between the inspection spots have been becoming finer and finer.
To match the fine pitches between the inspection spots, in the case of a pin-probe head, holes to allow the tip ends of the pin probes to project are formed and arranged zigzag at infinitesimal intervals in the surface of the head. In the case of a head that uses L-shaped needles, the needles to be fixed are tiered.
These countermeasures, however, entail operation to fix at regular pitches the individual pin probes or L-shaped needles that increase remarkably in number as the pitches between the inspection spots become finer, and also, operation to solder a wire to each probe or needle. Thus, completion of products requires a great deal of skill and long operating time, so that the resulting heads are very expensive, inevitably. Even after the pin probes or L-shaped needles are fixed to the head, moreover, their respective tip ends require an accurate location and rearrangement therefor. During storage before shipping, furthermore, close attention must be paid not to run the probe or needle tips against other articles.
In the case of a head having tiered L-shaped needles, the respective elongate portions of the needles are arranged parallel to one another. If the frequencies of input and output signals are heightened, for example, to increase the speed of inspection, therefore, the resulting characteristics of the head may be adversely affected to cause inspection errors, in some cases.
In forming bumps of a bump-type head by electroplating, on the other hand, the bump height is subject to a substantial variation, as mentioned before. The wide variation in the bump height is fatal to the head in which all the bumps must be brought securely into contact with their corresponding inspection spots in the wiring circuit, as a vital necessity.
In the case where bumps are formed by means of a thin film manufacturing apparatus, which is used in the field of semiconductor production and is very expensive, the resulting heads are also very expensive, and a mechanism for integrating the heads with probe cards is necessary. Also required is a drive mechanism for moving the bumps upward, in order to bring them into contact with the inspection spots in the wiring circuit at the time of inspection, and downward after the inspection. Thus, the heads obtained are complicated in construction and more expensive.
If an attempt is made to mount semiconductor components on the conventional packaging substrate at high density, the dead space inevitably enlarges with the increase of spots for mounting the components, since the conduction structures are based on through holes or inner via holes, as mentioned before. In a packaging substrate of a certain standard size, therefore, the number of regions for the formation of necessary bump patterns (or lands) for component packaging and the extent thereof are limited, so that the effort toward high-density packaging is restricted. If high-density packaging is intended to be achieved, the arrangement of additional signal patterns is needed, so that the multilayer structure of the substrate or circuit board is bound to be further complicated. Accordingly, wires in the signal patterns are lengthened, so that the reliability of the electrical properties of the resulting packaging substrate may be lowered in some cases.

Circuit board, manufacturing method therefor, and bump-type contact head and semiconductor component packaging module using the circuit board


A battery cover assembly for coupling to a housing of an electronic device, the battery cover assembly comprising: a cover (10) comprising an inner surface (106) and a button slot (101) defined therein; a movable member (20) comprising a main body (21), a button (211) formed on the main body and extending through the button slot, and a catch assembly extending from the main body; and a fixing plate (30) coupled to the cover, with the movable member being sandwiched between the fixing plate and the cover, the fixing plate defining at least one opening, the catch assembly of the movable member extending through the opening and being adapted for engageably securing the cover assembly to the housing (40). The battery cover assembly has a steady structure. The battery cover assembly is convenient to open and close.

As power supplies, batteries are widely used in portable electronic devices such as personal digital assistants (PDAs), cellphones and so on. A battery is generally removably mounted in a receptacle of a housing of an electronic device. The receptacle is generally covered by a battery cover. When the battery is damaged or cannot be recharged any more, the cover is removed from the housing, whereupon the battery can be taken out and replaced with a new one.
A latching mechanism is generally employed in a conventional battery cover, to engage with a housing of the portable electronic device. For example, a battery cover of an Alcatel® OT310 cellphone comprises a latching mechanism. The latching mechanism comprises a pair of hooks arranged at a lower end of the battery cover, and a locking pin arranged at an upper end of the battery cover. Correspondingly, a pair of slots is defined at a lower end of a back side of the housing, and a locking hole is defined at an upper end of the back side. In assembly, the hooks are inserted into the corresponding slots. Then, the battery cover is pressed downwardly such that the locking pins of the battery cover are inserted into the corresponding locking holes of the housing. The battery cover is thus assembled to the housing of the cellphone. The battery cover is simple in structure, and the engagement between the battery cover and the housing of the cellphone is secure. However, during disassembly of the cover from the housing of the cellphone, the battery cover is liable to be damaged because great force has to be exerted on the battery cover to detach the battery cover from the housing of the cellphone. As a result, it is inconvenient for a user to change a battery.
What is needed, therefore, is a new battery cover assembly for a portable electronic device which makes it convenient for a user to detach a battery cover of the battery cover assembly from a housing of the portable electronic device.

Battery cover assembly for portable electronic device

Shenzhen Futaihong Precision Industry Co., Ltd.


A system and method are disclosed for augmented visualization of a planogram of one or more supply chain entities. Embodiments include creating a planogram comprising one or more products, the products associated with a location, and retrieving an image of the planogram and one or more customer segments. Embodiments further include mapping one or more coordinates in an image of a planogram that correspond to the one or more customer segments and rendering an augmented visualization comprising altering the image of a planogram at one or more coordinates to illustrate the one or more customer segments.

Grocery shelving may be quite visually chaotic with hundreds of multicolored products competing to catch a customer's eye. Typically, product packaging and shelf layouts are arranged to increase sale performance. Although this situation may be acceptable in most cases, other situations may require an alternative way of browsing the products on the shelf. For example, to deal with food allergies, many customers must avoid products containing certain ingredients. Often the only way to identify the ingredients in a packaged product is by reading the label on each individual product. Similarly, grocery employees must monitor and dispose of expired products. Ordinarily, the expiration date is printed on the product in an inconspicuous location, which requires the employee to handle and read each individual item to search for expired products. Traditional forms of product packaging and shelf layouts discourage these and other searches for particular product attributes. This inability to quickly identify products with particular attributes is undesirable.

System and method of augmented visualization of planograms


A composition comprising an extruded inorganic support comprising an oxide of a metal or metalloid, and at least one catalytically active metal, wherein the extruded inorganic support has pores, a total pore volume, and a pore size distribution, wherein the pore size distribution displays at least two peaks of pore diameters, each peak having a maximum, wherein a first peak has a first maximum of pore diameters of equal to or greater than about 120 nm and a second peak has a second maximum of pore diameters of less than about 120 nm, and wherein greater than or equal to about 5% of a total pore volume of the extruded inorganic support is contained within the first peak of pore diameters.

1. Technical Field
The present disclosure relates to the production of unsaturated hydrocarbons, and more particularly to a selective hydrogenation catalyst and methods of making and using same.
2. Background
Unsaturated hydrocarbons such as ethylene and propylene are often employed as feedstocks in preparing value added chemicals and polymers. Unsaturated hydrocarbons can be produced by pyrolysis or steam cracking of hydrocarbons including hydrocarbons derived from coal, hydrocarbons derived from synthetic crude, naphthas, refinery gases, ethane, propane, butane, and the like. Unsaturated hydrocarbons produced in these manners usually contain small proportions of highly unsaturated hydrocarbons such as acetylenes and diolefins that can adversely affect the production of subsequent chemicals and polymers. Thus, to form an unsaturated hydrocarbon product such as a polymer grade monoolefin, the amount of acetylenes and diolefins in the monoolefin stream is typically reduced. For example, in polymer grade ethylene, the acetylene content typically is less than about 2 ppm.
One technique commonly used to reduce the amount of acetylenes and diolefins in an unsaturated hydrocarbon stream primarily comprising monoolefins involves selectively hydrogenating the acetylenes and diolefins to monoolefins. This process is selective in that hydrogenation of the monoolefin and the highly unsaturated hydrocarbons to saturated hydrocarbons is minimized. For example, the hydrogenation of ethylene or acetylene to ethane is minimized. An ongoing need exists for improved selective hydrogenation catalysts.

Selective hydrogenation catalyst and methods of making and using same


A constant velocity joint 10 comprises an outer race 12, an inner race 11, balls 14 and a cage 13. The outer race 12 has a partially spherical inner surface 12a provided with plural outer ball grooves 12b. The inner race 11 has a partially spherical outer surface 11 a provided with plural inner ball grooves 11b arranged to correspond to the outer ball grooves 12b. The balls 14 are interposed between the outer ball grooves 12b and the inner ball grooves 11b. The radial distance of the outer ball grooves 12b from the rotational axis of the outer race increases toward an opening end of the outer race 12 in a predetermined zone H, and a contact angle θ between each ball 14 and each outer ball groove 12b decreases toward the opening end of the outer race 12 in the predetermined zone H.

1. Field of the Invention
This invention relates to a constant velocity joint.
2. Discussion of the background
Japanese patent application publication No. 58-214019 discloses a constant velocity joint whose outer race has plural outer ball grooves. The outer ball grooves are undercut so that a bottom of each outer ball groove is located at a longer distance from a rotational axis of the outer race at a longitudinally central portion of the outer ball groove than at its opening end. Because the undercut is not easily forged, machined or ground, the manufacturing cost of the outer ball groove increases.
Another conventional constant velocity joint is a so-called undercut free joint whose outer race has plural ball grooves extending parallel to the rotational axis of the outer race from the center portion to the opening side.


An OCT apparatus includes a wavelength selector provided on an optical path between a light source unit and a pair of optical detection units, and having a wavelength selectivity with equal wavenumber intervals. A differential detection unit detects a differential between two interference lights detected by the two optical detection units, and an information acquisition unit obtains peak values in the temporal waveform of the intensity of the interference lights and acquires information about an object on the basis of the obtained peak values.

In an optical coherence tomography (OCT) apparatus (hereinafter abbreviated as an OCT apparatus) of the related art using a tunable light source, an object is irradiated with light, the wavelength of the irradiation light is continuously changed, and reference light is caused to interfere with reflected light components returning from portions of the object having different depths. By analyzing frequency components included in a temporal waveform of intensity of interference light (hereinafter abbreviated as an interference spectrum), a tomographic image of the object is obtained. The frequency components are analyzed by subjecting the interference spectrum to Fourier transform processing. To obtain a tomographic image that has little distortion and noise, it is necessary to sample the interference spectrum at equal wavenumber intervals and to subject to the interference spectrum to Fourier transform processing.
In the related art, to sample the interference spectrum at equal wavenumber intervals, the timing of wavenumber selection is determined by separating part of the irradiation light and monitoring the part with a detector via an interferometer such as an etalon. In this way, a system for determining the timing of wavenumber selection (a k-trigger generating unit) and a system for detecting the intensity of interference light (a measuring system) are separately provided, and sampling is performed by synchronizing the systems. More specifically, the k-trigger generating unit inputs k-trigger signals (sampling triggers) to the measuring system at equal wavenumber intervals, whereby the interference spectrum is sampled at equal wavenumber intervals (see PTL 1).

Optical coherence tomography apparatus and optical coherence tomography method


A battery monitoring unit and sensors are supplied with a common operating supply voltage to operate. Detection values from sensors are sent to a control circuit by the battery monitoring unit. The control circuit monitors the operating supply voltage using a voltage sensor and additionally determines whether or not the detection values from the sensors before the relay connection falls within a normal range to more accurately detect a power supply reduction abnormality of the battery monitoring unit. Therefore, abnormalities can be detected accurately when the sensor and the battery monitoring unit provided for the secondary battery cannot operate normally due to a reduced operating supply voltage.

A variety of power supply systems for supplying power from a secondary battery to a load are used in hybrid cars and others. In such a power supply system, it is necessary to properly detect abnormalities in a secondary battery.
In this respect, for example, Japanese Patent Laying-Open No. 2002-084669 (referred to as Patent Document 1 hereinafter) discloses a battery pack configured such that a plurality of cell groups each configured to include a plurality of electric cells connected in series are connected in series. For this battery pack, cell-state monitoring means for monitoring a state of each electric cell is provided to allow sensing of abnormalities for each electric cell. In particular, in the configuration disclosed in Patent Document 1, power supply to the cell-state monitoring means is at least partially stopped during a period of time in which the output from the cell-state monitoring means is not referred to by the higher-level abnormality monitoring means, so that power consumption by the cell-state monitoring means can be reduced.
Furthermore, Japanese Patent Laying-Open No. 11-234801 (referred to as "Patent Document 2" hereinafter) discloses a battery ECU detecting a battery abnormal condition based on voltage data or temperature data. In this battery ECU, when any abnormality occurs in a sensor itself that detects the abnormality of the battery, a ventilating fan or an in/out switching valve is switched appropriately so that gases produced from the battery can quickly be exhausted from the car even when the battery abnormal condition takes place repeatedly.
However, the configuration disclosed in Patent Document 1 is unable to sense the abnormality of the cell-state monitoring means itself that monitors the abnormality of the secondary battery. Therefore, during the abnormal condition of the cell-state monitoring means, the secondary battery may not be controlled properly due to wrong information.
On the other hand, in the configuration disclosed in Patent Document 2, as for a sensor determining voltage data or temperature data, a failure in the sensor itself is sensed at the time of hardware failures such as a disconnection or a short-circuit. However, even in the absence of hardware failures such as a disconnection or a short-circuit, the sensor output value (detection value) or the operation of the battery monitoring unit may sometimes become abnormal due to reduction of an operating supply voltage. When an output value from the sensor or the battery monitoring unit is used as a normal value for control or the like without sensing such abnormalities, the state of the secondary battery cannot be controlled accurately, thereby possibly causing an abnormal operation of the power supply system.

Monitoring device for power supply system


The present invention provides an image/graphics data display mechanism for continuously displaying image/graphics data on dual display devices of a computer that contains a Display FIFO and a system memory directly accessed by the computer's CPU, wherein at least one of the display devices is running in a low-resolution mode, the mechanism comprising: determining which of the display devices is running in the low-resolution mode; receiving a power saving signal from the CPU; requesting an access to the system memory, and pre-storing the image/graphics data for the low-resolution device into the Display FIFO; and triggering the CPU power saving process according to a display timing scheme of the other display device.

1. Field of the Invention
The present invention relates to a computer graphic display, and more particularly, to a method for continuously displaying graphics or video data during a non-responding period of a central processing unit (CPU). Herein, the graphics or video data are stored in a system memory that can only be accessed via a built-in memory controller inside the CPU.
2. Description of the Prior Art
The computer is one of the most popular tools that have been closely involved in human daily lives. Almost all professions rely on the computer to make their work more efficient and easier. As the usage of computer grows even further, the need for a higher performance computer is likewise growing and getting bigger. More functions and more capacities are built into a single computer chip, and the clock speed of a central processing unit in a computer increases from the range of mega (106)/second to the range of giga (109)/second within few years. Not only the layout of computer hardware has become more complicated than before, but the coding of computer software application also has grown from millions of lines to billions of lines of code. The achievement of more functions, greater speed, and less power consumption becomes a challenge for the designing of a modern computer.
Conflicts are usually found in saving the consumption of power by a computer while trying to keep up its performance. Higher processing speed and more complex calculation always mean more power consumption. However, not all computer applications require high processing speed and consume large system resources all the time. Dynamically adjusting system operating clock and system resources, thereby reducing system power consumption based on the needs of a computer application is a clever design to keep the system performance high and save the system power consumption at the same time. The present invention identifies a solution to provide a continuous image/graphics display on a dual display devices computer system during a CPU power saving process. The following paragraphs first provide computer display background knowledge, illustrate a couple of common computer system display architectures by examples, and then introduce computer power saving mechanisms and computer system display problems caused by the power saving mechanisms.
With graphic-intensive applications, is a high quality of image data required to be displayed correctly and with precision on a monitor device without any blinking, jittering, or delays. An image with several megabytes data needs to be dumped onto a monitor device per second to accomplish a continuous error free video-on-demand application. Such a graphic-intensive application can be a high-end computer-aided drafting (CAD) application, a multimedia game, MPEG video playback, video conferencing, or one of many other real-time video applications. Typically, a graphic-intensive application contains a huge amount of image data that needs to be timely displayed onto a monitor device. Every complete screen of graphic information, known as a frame, has to be displayed precisely in time to avoid display blinking and jittering; as a result, the graphic processing mechanism needs to decode the image data fast enough. For instance, with a 640.times.480 pixels (horizontal.times.vertical), 32 bits true color, and 30 frames per second graphic application without compression, its image processor needs to process 36.864 megabytes image data per second to be able to display correctly. Moreover, as the typical resolution of a computer display has increased from 640.times.480 pixels to 800.times.600 pixels, 1024.times.768, 1280.times.1024, and beyond, and color information per pixel from 2 bits to 24 bits, 32 bits, and beyond, the processing speed and stability of an image processor also need to be increased multiplicatively.
Typically, to speed up the image processing speed, a computer relies on a graphics processing unit, or a standalone graphics card (GFX, also known as a video card, graphic accelerator card, or a display adapter, etc.) to do graphics display on a monitor device. A graphics card usually contains a specialized processor or processors that are tailor-made for graphic rendering, and a set of memory ranging from one, two, four, eight, or sixteen megabytes and up, so that image frames can be stored in the graphics card. Thus, the set of memory installed in a graphic card is commonly known as a frame buffer.
A graphics card or a graphics-processing unit can be built into a standalone chipset (and mounted on a card) as demonstrated in FIG. 1, or it can be integrated into an existing chipset as depicted in FIG. 2. Referring to FIG. 1, a computer system 10 comprises a CPU 11, a system chipset 12, a data-path chipset 13, a system memory 14, a graphics card (GFX) 15, a frame buffer 16, a first display device 17, a second display device 19, and a built-in memory controller 18 inside the system chipset 12. The system chipset 12 is commonly referred to as the North Bridge (NB), and the data-path chipset 13 is commonly referred to as the South Bridge (SB). Each of the display devices can be a Cathode Ray Tube (CRT) type, a liquid crystal display (LCD), or any other advanced monitors. As a contrast to FIG. 1, in FIG. 2, a graphics-processing unit (GFX) 27 is integrated into the NB 22, and the placements of a CPU 21, a System Memory 24, a Memory Controller 26, a SB 23, a NB 22, and Display Devices 25, 28 are similar to FIG. 1.
Usually, graphics information that is going to be displayed onto the display device is first stored in the system memory, then transferred to a first-in-first-out (FIFO) video memory. The FIFO display mechanism will make a request to access system memory to receive the graphic information. The FIFO display mechanism may be appreciated by a water tank analogy. Similar to water draining out from the bottom of a water tank at a constant rate and refilling from the top of the water tank occasionally, the FIFO display mechanism dumps image data to the frame buffer of the display device at an invariant rate, and receives image data from the system memory every so often. Both the standalone graphics processing unit (as depicted in FIG. 1) and the on-chipset graphics processing unit (as depicted in FIG. 2) can directly access the system memory through the memory controller in the NB. In other words, the request of a system memory access can be made by the graphics processing unit (or the graphics card) without going through the CPU.
In addition to the computer system architectures demonstrated in FIG. 1 and FIG. 2, there are other computer system architectures in use. For instance, two of those computer system architectures are presented in FIG. 3 and FIG. 4. In FIG. 3, a computer system architecture 30 is similar to the standalone GFX computer system 10 shown in FIG. 1 except that the system memory 34 is directly connected to a CPU 31 via a built-in memory controller 38. As the same for FIG. 4 and FIG. 2, both computer system architectures have their graphics processing units built into the North Bridges, but in FIG. 4, the memory controller 46 is inside a CPU 41 and a system memory 44 is directly coupled to the CUP 41 via the built-in memory controller 46. Note that with the computer system architectures sketched in FIG. 3 and FIG. 4, a system memory access requested by the graphics processing units (GFXs) has to go through not only the North Bridges but also the CPUs.
The increase of CPU workload often demands an increase in power consumption and results in a shorter battery life. The increased power consumption may cause a fatal problem to an application running on a mobile computer unit or a laptop computer. As a consequence, a variety of power saving techniques is introduced to the design of modern computers. A couple of power saving techniques are described as follows. When a CPU idles for a predetermined period of time, the CPU clock speed is reduced, and the CPU power supply is turned off. Furthermore, instead of turning the CPU on and off, a mechanism that detects the power consumption level of an application several times every second and self-adjusts the CUP clock rate and power supply level to reduce power consumption is built into a computer. As a result, with the use of the power saving techniques, a battery can last longer and the capacity of a battery may be reduced to achieve the same performance.
Typically, a few microseconds (μsec) to tens of μsec is required to process the power saving mechanism, for instance, to detect the power consumption level of an application so that the CPU clock rate can be reduced. During the execution of power saving mechanism, the CPU is completely idle and waits for the next alternative CPU clock rate to operate. Upon the CPU idle period, the graphics processing unit or the graphics card presented in FIG. 3 and FIG. 4 cannot access the memory controller that is built inside the CPU to obtain the required image/graphics data from the system memory. The present invention provides a breakthrough solution to the conflict between power saving and continuous image/graphics data display in a modern computer design.

Continuous graphics display for dual display devices during the processor non-responding period


A regulating circuit that regulates rotary speed of a pulse-width modulated fan includes a measuring device that determines a period duration (TIst) of a tacho signal (TACH) of the fan, a digital regulating register that acquires a regulation value to drive the fan on the basis of a determined period duration (TIst) and a desired value (Tsoll), a digital control register that adjusts a duty ratio to drive the fan, the digital control register has a smaller register width than the digital regulating register, and a controller that updates the digital control register by evaluating a predetermined number of more significant bits of the digital regulating register.

Regulating circuits that regulate the rotary speed of pulse-width-modulated fans are known. For example, DE 102004002447 B4 discloses a regulating circuit with overtemperature signaling. In that case, the fan regulating circuit contains an input that supplies a temperature-dependent control signal to provide a desired value for the rotary speed of the fan. When a first temperature threshold is reached, an overtemperature warning is signaled by inverting a signal at a first signal output which indicates the current rotary speed of the fan. This and other regulating circuits are particularly suitable to regulate electronically commutated fans which, on account of their connection diagram, are often also referred to as four-wire fans.
FIG. 1 illustrates an exemplary arrangement comprising a pulse-width-modulated fan 1, a regulating circuit 2 and a component 3 to be cooled. Arranged in the region of the component 3 is a temperature sensor 4 which can be used to detect the temperature of the component 3 to be cooled to predefine a regulation value for the regulating circuit 2. In the arrangement illustrated in FIG. 1, the components 2, 3 and 4 are arranged on a common printed circuit board 5 of a data processing device, for example, a computer system or a network component.
Conventional regulation of the fan 1 is described below using FIG. 2. The pulse-width-modulated fan 1 generates a tacho signal TACH, the tacho signal containing, for example, one or two tacho pulses per revolution of the fan wheel. This tacho signal is supplied to a frequency measuring device 6. The frequency measuring device 6 also receives a control signal from a timer device 7. The timer device 7 comprises, for example, a digital oscillator and a control logic unit to determine a window length to measure a frequency by the frequency measuring device 6.
The frequency measuring device 6 determines the number of tacho pulses in the tacho signal TACH which are detected in a time window determined by the timer device 7. For example, the frequency measuring device 6 can determine how many tacho pulses occur in one second. A rotary speed comparator 10 then compares this value NIst with a predefined desired value NSoll determined, for example, on the basis of a measured temperature θ.
The difference between the desired number of tacho pulses NSoll and the actual number of tacho pulses NIst is transmitted to a pulse-width control device 8 as a value ΔN. The difference value ΔN is then used to predefine a duty ratio as a digital value P to drive the fan 1 for a pulse-width modulation device 9 by a function p1(ΔN). The function p1 may be predefined, for example, in the form of a table containing control values P for particular difference values ΔN. A free-running counter of the pulse-width modulation device 9 is then readjusted to the desired duty ratio on the basis of the value P. The pulse-width modulation device 9 generates a pulse-width-modulated signal PWM therefrom and makes the signal available to the fan 1 via a drive line.
Detecting tacho pulses inside a limited measuring time window of one second, for example, reduces the accuracy with which the rotary speed is detected. A rotary speed of 800 revolutions per minute, for example, and two tacho pulses per revolution result in a counter reading of 26 after one second, for example, while the mathematically correct value is 26.67. In the previously described case, an error of approximately 2.5% thus already occurs when detecting the rotary speed.
The measurement could be improved, for example, by extending the time window, but the regulating speed of the regulating circuit 2 would then decrease. Furthermore, particular regulating parameters would additionally have to be complied with to prevent escalation of the fan rotary speed.
As described above, a free-running counter of the pulse-width modulation device 9 is then adjusted to the desired duty ratio on the basis of the determined number NIst of determined tacho pulses. Inexpensive counters of this type have a resolution of eight bits, with the result that a resolution of 0-100% of the duty ratio would be theoretically possible in 255 steps. However, since a sensibly usable frequency of the PWM drive signal for the fan 1 is often predefined within narrow limits, for example, 20-25 kHz, but an oscillator clock of the counter can generally only be divided down into steps of two and/or four, the uppermost possible control value of the pulse-width control device 8 must be limited to a value of lower than 255 to obtain the correct drive frequency. If this is effected to a value of 100, for example, a fan 1 having a maximum rotary speed of 5,000 revolutions per minute already only has a drive resolution of 50 revolutions per minute, depending on the usable bit of the control register. The increase or decrease in a rotary speed of 50 revolutions per minute is already clearly audible. Such audible changes in the operating noise of the fan 1 are often perceived as disruptive by a user of a data processing device.
The driving could be improved, for example, by a higher-quality pulse-width modulation device 9 having a counter with a higher resolution. However, this results in cost disadvantages since the counters present in integrated regulating circuits can then no longer be used.
It could therefore be helpful to describe an improved regulating circuit and a method of regulating the rotary speed of a pulse-width-modulated fan, which method improves the regulating accuracy. In this case, the method is intended to be able to be implemented as easily as possible using hardware or software.

Regulating circuit and method for regulating rotary speed, data processing device, and program code

Fujitsu Technology Solutions Intellectual Property GmbH


A liquid discharging apparatus includes a plurality of liquid channels each having a discharge port, a control electrode extended on a surface defining the liquid channel from the discharge port toward an upstream side in a direction of flow of a liquid, an insulating film which coats the control electrode, and an electric potential control section which controls an electric potential of the control electrode with respect to the liquid. When a predetermined electric potential difference are set between the liquid and the control electrode, a liquid repellence of a surface of the insulating film is lowered due to an electrowetting phenomenon so that the liquid can move toward the discharge port on an area of the liquid channel in which the insulating film is formed. Accordingly, it is possible to provide the liquid discharging apparatus which is capable of discharging a liquid by a simple structure.

1. Field of the Invention
The present invention relates to a liquid discharging apparatus which discharges a liquid.
2. Description of the Related Art
An ink-jet head which discharges ink (liquid) on to a paper or the like is an example of a printing apparatus (ink discharging apparatus) which prints on a printing medium such as a paper. There are various types of such ink-jet heads, such as an ink-jet head which is provided with a channel unit including a plurality of ink channels such as a pressure chamber communicating with a nozzle, and a piezoelectric actuator unit which applies pressure to ink in the pressure chamber (refer to FIG. 1 of U.S. Pat. No. 6,926,382 (corresponds to FIG. 1 of Japanese Patent Application Laid-open Publication No. 2003-326712)). A normal piezoelectric actuator unit includes a plurality of individual electrodes corresponding to each of pressure chambers communicating with the nozzles, a common electrode facing the individual electrodes, and a piezoelectric layer made of lead zirconate titanate (PZT) which is sandwiched between the individual electrode and the common electrode. Further, when a drive voltage is supplied to a desired individual electrode, an electric field is generated in a part of the piezoelectric layer sandwiched between the individual electrode and the common electrode, and the piezoelectric layer is partially deformed. As the piezoelectric layer is deformed, a pressure is applied to the ink in the pressure chamber, and the ink is discharged from a nozzle communicating with the pressure chamber.


Disclosed are .DELTA..sup.9(11) -steroids (VI) and amino substituted steroids (XI) which contain an amino group attached to the terminal carbon atom of the C.sub.17 -side chain, more particularly amino steroids (Ia and Ib), aromatic steroids (II), .DELTA..sup.16 -steroids (IIIa and IIIb), reduced A-ring steroids (IV), .DELTA..sup.17(20) -steroids (Va and Vb) and .DELTA..sup.9(11) -steroids (VI) which are useful as pharmaceutical agents for treating a number of conditions.

Various amino (substituted) steroids are known with the amine substitution on either the steroidal ring system or on the side chain of the D-ring at C.sub.17.
U.S. Pat. No. 4,456,602 discloses steroidal 21-esters in which there is an amino function in the non-steroidal portion of the ester.
In the 3.alpha.-hydroxy series, U.S. Pat. No. 3,998,829 discloses 21-aminomethyl steroids and U.S. Pat. No. 3,983,111 discloses 21-amino steroids where the amino group is cyclized. These patents also disclose reduced A-ring steroids as well as steroids with a hydrogen atom at C.sub.17 and two hydrogen atoms at C.sub.11.
20-Amino steroids are known in the .DELTA..sup.4 -3-keto series with no substitution at C.sub.11 and C.sub.17, see Can. J. Chem., 47, 160 (1969) ; J. Med. Chem., 27, 1690 (1983); U.S. Pat. Nos. 4,377,584 and 4,191,759; Chem.-Biol. Interact., 46, 1 (1983) ; J. Steroid Biochem., 20, 1095 (1984); Inorg. Chim. Acta, 91, 257 (1984), with substitution at C.sub.11, see Steroids 35, 265 (1980) and Biochim. Biophys. Acta, 623, 280 (1980) as well as with substitution at both C.sub.11 and C.sub.17, see Steroids, supra.
20-Amino steroids are known in the .DELTA..sup.1,4 -3-keto series with an 11.beta.-hydroxyl substitution, see Steroids, supra, as well as with 11.beta.,17.alpha.-dihydroxy substitution, see Protides Biol. Fluids, 29, 393 (1982); J. Clin. Chem. Clin. Biochem., 22, 209 (1984); Eur. J. Biochem., 108, 47 (1980); J. Steroid Biochem., 14, 697 (1981), Nature (London) 279, 158 (1979) and Eur. J. Biochem. , 131, 333 (1983) and with 11.alpha.,17.alpha.- dihydroxy substitution, see J. Clin. Chem. Clin. Biochem., 21, 69 (1983). U.S. Pat. No. 4,191,759 discloses 20-amino-.DELTA..sup.1,4 -3-keto steroids without any substitution at the 11 position where the amine substituent is morpholine or piperazine.
21-Amino steroids are known in the .DELTA..sup.4 -3-keto series with no substitution at C.sub.11, see J. Org. Chem., 45, 3084 (1980); J. Org. Chem., 26, 1223 and 5052 (1961); J. Chem. Soc., Perkin Trans. 1, 502 (1972); Great Britain Patent 954,146 and its U.S. equivalent, U.S. Pat. No. 3,123,598; Austrian Patent 249,883; Arch. Biochem. Biophys., 182, 197 (1977) and Khim.-Farm. 2, 26 (1968). In addition 21-amino steroids are known in the .DELTA..sup.1,4 -3-keto series substituted with 11.beta.-hydroxyl, see Arch. Biochem. Biophys., 182, 197 (1977); Int. Conf. Chem. Biotechnol. Biol. Act. Nat. Prod. 2, 135-49 (1981); Analyst (London) 98, 519 (1972); U.S. Pat. Nos. 3,705,150, 4,076,737 and 2,920,999; Nature 191,607 (1961); Hungarian Patent 150,350 and J. Org. Chem., 45, 3084 (1980). For example Hungarian Patent 150,350 discloses dipersolone, 11.beta.,17.alpha.-dihydroxy-21-(4-methyl-1-piperazinyl)pregna-1,4-diene-3 ,20-dione. Further, U.S. Pat. No. 3,705,150 discloses 21-[N-(N'-methyl)piperazinyl]prednisolone.
German Patent 1,087,598 and U.S. Pat. No. 2,920,999 disclose simple 21-amino derivatives of .DELTA..sup.4 -3-keto steroids. The amines include both mono and bis substituted amines. In the cases where the amino group is disubstituted, the two substituents can be cyclized with the attached nitrogen atom to form a heterocyclic amino group (morpholine, pyrrolidine, piperidine, pyridine). The amines were chosen from the group consisting of amino, monoalkylamino, dialkylamino, phenylamino, pyridylamino, benzylamino, picolinylamino, N-alkyl-N-phenylamino, N-alkyl-N-pyridylamino, morpholinyl, pyrryl, pyrrolidyl, piperidino and C-alkylated piperidino, though only N-piperidino, N,N-diethyl and N-methyl-N-phenyl were exemplified. The amino steroids of the present invention while containing the steroid portion of the compounds of U.S. Pat. No. 2,920,999, contain more complex amines.
U.S. Pat. No. 3,144,446 discloses mono and bis quaternary ammonium salts of triethylenediamine. The amines and amino steroids of the present invention do not include triethylenediamine or other bridged amine, only 1-piperazinyl substituted amines.
U.S. Pat. No. 2,665,274 discloses pyridium sats of steroids. In the present invention R.sub.21 and R.sub.210 are taken together with the attached carbon atom to form a heterocyclic ring but not an aromatic ring.
Chem. Abst. 70, 115402v (1969) discloses amino steroids where the amines are morpholino, piperidino and dimethyl. The amines of the amino steroids of the present invention are much more complex than these three simple unsubstituted amines.
A number of 20-amino steroids are known where the 20-amino group is of the general type --NH--(CH.sub.2).sub.x --N(R.sub.1)(R.sub.2) where x is 2 or 3 and R.sub.1 and R.sub.2 are methyl or ethyl. See, for example, Arch. Farmacol. Toxicol. 4, 265 (1978), Lipids 2, 5 (1967), J. Med. Chem. 15, 1129 (1972), ibid 15, 1284 (1972), French Patent 90805, Lipids 11, 616 (1976), U.S. Pat. No. 3,558,608, Chem. Abst. 62, 14784a, ibid 64, 14573e, ibid 65, 2334d, ibid 56, 15583a, b, and i, ibid 57, 12574d, ibid 57, 6225d.
Many 20-amino and 21-amino steroids are known where the amino group is substituted with simple alkyl (C.sub.1 -C.sub.3), aryl (phenyl), simple aralkyl (benzyl), as well as substitu containing hetero atoms (sulfur), esters, acids, amino substituted alkyl, alcohols, ethynyl groups, etc. The amino steroids are known where the amine portion is either mono or disubstituted. In the cases where the amino group is disubstituted, the two substituents can be cyclized with the attached nitrogen atom to form a heterocyclic amino group. These simple cyclic and heterocyclic amines, see U.S. Pat. Nos. 3,523,942, 4,191,759 and 2,920,999, are unlike the complex amine substituents of the present invention. The known 21-amino substituted steroids include simple (substituted) cyclic amines such as 4-(2-hydroxyethyl)-1-piperazinyl [CA 65;20189g]; 4-(2-hydroxyethyl)-1-piperidinyl [83544-11-0]; 4,4-dimethyl-l-piperazinyl, 3-hydroxyethyl-1-piperidinyl, 4-hydroxy-1-piperidinyl, 4-carboxy-1-piperidinyl, 3-hydroxy-1-piperidinyl, 3-carboxy-1-piperidinyl, piperazinyl, bis(hydroxyethyl)amino, 4-acetyl-1-piperazinyl, 4-carboxaldehyde-1-piperazinyl, 1 -piperidinyl, [Int. Conf. Chem. Biotechnol. Biol. Act. Nat. Prod. [Proc.] 1st. Vol. 2, p. 135, 1981]; 4-methyl-1-piperazinyl [Great Britain Patent 2,136,293]; 3,6-dihydro-2,6-dioxo-1(2H)-pyrimidinyl, 5-fluoro-3,6-dihydro-2,6-dioxo-1(2H)-pyrimidinyl, 5-fluoro-3,4-dihydro-2,4-dioxo-1(2H)-pyrimidinyl, 3,4-dihydro-2,4-dioxo-1(2H)-pyrimidinyl, 3,4-dihydro-5-methyl-2,4-dioxo-1(2H)-pyrimidinyl [J. Steroid Biochem. 9, 1155 (1978)]; and 4-morpholinyl [J. Chem. Soc. Perkin Trans I, 502 (1972)].
U.S. Pat. No. 3,697,509 discloses .DELTA..sup.17(20) -21-quaternary amino steroid salts. The .DELTA..sup.17(20) -21-amino steroids (V) of the present invention include pharmaceutically acceptable salts, but not quaternary amine salts.
Japanese published application J8 5043068 discloses azepino(1,2,3-1H)-.beta.-carboline derivatives which inhibit lipid peroxidation and are useful in inhibiting the aging of living bodies.
Some of the free amines of the amino substituent of the amino substituted steroids (XI,) of the present invention are known. See, for example, U.S. Pat. No. 4,492,696.
While some of the free amines of the amino steroids of the present invention are known, such as 2-carboxy-1-piperidine [Aldrich, item P4,585-0], 4-(2-pyridinyl)piperazine [French Patent 7253 M], 4-(2-pyridinylmethyl)piperazine [European Patent application 49,683], 4-(6-methoxy-2-pyridinyl)piperazine [Canadian Patent 679,894], 4-(2-pyrimidinyl)piperazine [U.S. Pat. No. 4,409,223], 4-(3,6-dimethylpyrazinyl)piperazine [Canadian Patent 979,894], 4-(2-methoxyphenyl)piperazine [Aldrich, item M2,260-1], 4-(4-methoxyphenyl)piperazine (Aldrich item M2,300-4], 4-[(3,4-dimethoxyphenyl)methyl)piperazine [French Patent 7031 M], 4-(4-fluorophenyl)piperazine [Aldrich, item 19,133-7], 4-[[4(dimethylamino)phenyl]methyl]piperazine [U.S. Pat. No. 4,421,753], 4-hydroxy-4-[4-(trifluoromethyl)phenyl]piperazine [U.S. Pat. No.3,936,464], (2-diethylaminoethyl)amine [Aldrich, item 12,694-2], [2-(3,4-dimethoxyphenyl)ethyl]amine [Aldrich, item D13,620-4], [2-(2,4-dimethoxyphenyl)-1-methylethyllamine [J. Pharm. Sci. 60, 1232 (1971)], [2-(3,4-dimethoxyphenyl)ethyl][[4-dimethylamino)phenyl]methyl]amine [Chem. Abst. 65:7001f] and (2-pyridinyl)methylamine [Aldrich, item A6,520-4), most are novel.
Great Britain Patent 1,345,640 and U.S. Pat. No. 835,132 generically disclose piperazinyl substituted pyrimidines including those where the substituents are morpholino, monoalkylamino, cycloalkyl, N-benzylpiperazino, --NEt.sub.2, --NHCH.sub.2 CH.sub.2 OH and piperazino. Specifically disclosed are 4-[2-morpholino-6-ethylamino-4-pyrimidinyl]piperazine (named the same way the amines of the present invention are named), see Example 1 and 4-[4-morpholino-2-ethylamino-4-pyrimidinyl]piperazine, see Example 2.
Great Britain Patent 1,390,014 and U.S. Pat. No. 3,980,650 disclose 4-aminoquinazolines. The starting material for Example VI is 1-cyano-4-(2-furoyl)piperazine, N.tbd.C-piperazine-(2-furoyl). One of the amines of the present invention is 4-(2-furanylcarbonyl)piperazine, see PREPARATION A-3. The amine of the present invention differs from the prior art amine in that it does not have a cyano group and does not have a carbonyl group between the piperazine and the furoyl substituent.
Chem. Abst. 85, 78082c (1976) discloses 4-(2-furoyl)piperazine, 4-(2-thienyl)piperazine and 4-(3-thienyl)piperazine. The present invention includes 4-(2-furanylcarbonyl)piperazine, see PREPARATION A-3. The amine of the present invention differs from the prior art compounds in that they do not include the thienyl moiety or do have a carbonyl group separating the piperazine from,the furoyl group.
French Patent 1,413,722 and U.S. Pat. Nos. 3,325,496 and 3,374,173 disclose 2,4,6-triamino-substituted pyrimidines including bis(dialkylamino)piperidino substituted pyrimidine. The present invention includes piperazinyl substituted pyrimidines, not piperidino substituted pyrimidines.
Most of the steroidal 21- (hydroxy derivative) halo (bromine or iodine), mesylate or tosylate starting materials are known, such as 21-bromo-17.alpha.-hydroxypregna-4,9-diene-3,20-dione (U.S. Pat. No. 4,041,055 (Ex 59)], 21-bromo-17.alpha.-hydroxypregn-4-ene-3,11,20-trione [J. Chem. Soc. B., 4, 748 (1970)], 11.alpha.,21-dihydroxypregn-4-ene-3,20-dione [U.S. Pat. No. 4,013,688], 21-bromo-17.alpha.-hydroxypregn-4-ene-3,20-dione [U.S. Pat. No. 4,500,461], 21-bromopregn-4-ene-3,11,20-trione (U.S. Pat. No. 3,983,111], 21-hydroxy-pregna-4,9(11),16-triene-3,20-dione [Tetrahedron Lett. 25, 2581 (1984)], 21-iodopregna-4,9(li)-diene-3,20-dione [95288-91-8], 21-bromopregn-4-ene-3,20-dione [J. Org. Chem., 50, 81 (1985), 11.beta.,17.alpha.-dihydroxy-21-iodo-6.alpha.-methylpregna-1,4-diene-3,20- dione [J. Pharm. Soc., 74, 365 (1985)], 21-bromo-11.beta.,17.alpha.- dihydroxypregna-1,4-diene-3,20 -dione [U.S. Pat. No. 3,856,956], 17.alpha.-hydroxy-21-1 iodo-16.alpha.-methylpregna-1,4,9(11)-triene-3,20-dione [U.S. Pat. No. 3,455,968], 17.alpha.,21-dihydroxy-6.alpha.-methylpregna-1,4,9(11)-triene-3,20-dione [West German DE 3,322,120], 17.alpha.-Hydroxy-21-iodopregna-1,4-diene-3,11,20-trione [J. Med. Chem., 28, 171 (1985)], 21-bromopregna-1,4-diene-3,20-dione [Bull. Chem. Soc. Jpn. 58, 981 (1985)], 17.alpha.,21-dihydroxy-pregna-1,4,9(11)-triene-3,20-dione [West German DE 3,322,120], 17.alpha.,21-dihydroxy-16.beta.-methyl-5.alpha.-pregn-9(11)-ene-3,20-dione [U.S. Pat. No. 4,336,200] and 21-bromo-3.alpha.,17.alpha.-dihydroxy-50.beta.-pregnane-11,20-dione [95044-38-5], however some are novel.

Piperazine compounds which are substituted


An (N−1)/N prescaler is provided, where N is an S power of 2. The prescaler uses only S flip-flops. The (N−1)/N prescaler receives a clock input from a high frequency oscillator, and provides an output line to a counter. The (N−1)/N prescaler receives a divide-by-(N−1) signal from the counter, and responsive to the divide signal, causes the prescaler to divide by a factor of (N−1); otherwise, the prescaler divides by a factor of N.

The field of the present invention is electronic circuits for frequency synthesis. More particularly, the present invention relates to a prescaler electronic circuit for use with a fractional-N synthesizer.
Wireless communication systems transmit and receive modulated radio frequency (RF) signals, generally in accord with one or more telecommunications standards. These telecommunication standards, such as GSM, CDMA, CDMA2000, PDC, PHS, and others, generally set out specific and narrow bands of frequency operation. In order to maintain compliance with the frequency standards, wireless transceivers may use a crystal controlled oscillator to provide a highly accurate and stable frequency source, which controls and maintains the frequency output of a higher frequency local oscillator, such as a voltage controlled oscillator (VCO). In operation, the wireless transceiver may often need to change channels or modes, and therefore the modulation frequency generated by the VCO.
The high frequency VCO generates a high frequency signal at the desired modulation frequency, which is defined in the implemented telecommunication standard. The modulation signal may be, for example, several hundred Megahertz, with some telecommunication standards now operating in the Gigahertz frequencies. Although the VCO generates high frequency signals, the VCO is a relatively unstable frequency source, and is subject, for example, to frequency drift and accuracy errors. In order to increase the accuracy and stability of the VCO, the VCO uses the crystal controlled oscillator as a frequency reference. To do so, a prescaler circuit may be used to divide the VCO signal to a desired lower frequency. A controller in the wireless device determines the desired ratio between the reference oscillator and the VCO, and generates an appropriate divide ratio. Using the selected divide ratio, the local VCO signal is divided to a lower frequency, which is then locked to the reference signal from the crystal controlled oscillator, often by using a standard phase locked loop (PLL) circuit. If there is a difference in frequency between the reference signal and the divided signal, then a feedback loop is used to appropriately adjust the frequency of the VCO. In this way, the VCO frequency is adjusted according to the divide ratio used in the prescaler. In another use, the divide ratio of the prescaler may be changed to generate different signal frequencies. In this way, different lower frequency signals may be readily available for use.
A prescaler typically has two available divide ratios and has an input control line that allows a control circuit to set a first mode where the prescaler divides by a first divide ratio, or set a second mode where the prescaler divides by a second divide ratio. Since the prescaler has at least some components that operate at the frequency of the local oscillator signal, the prescaler circuit needs to be implemented with minimal components, and with structures selected to accommodate timing and power needs. As oscillator frequencies increase, and the demands for stable and accurate frequency sources increase, there are more demands being placed on prescalers.
A typical known prescaler is arranged to divide either at an N factor or at an (N+1) factor. Such a prescaler is often referred to as an N/(N+1) prescaler. Common prescaler values are 4/5; 8/9; and 16/17. In using a prescaler, a control circuit instructs the prescaler to divide an input frequency by a particular divide ratio. The magnitude and range of the required divide ratios are determined according to the frequency of the reference oscillator, the frequency of the VCO, and the requirements of the communication standard that is to be implemented. More particularly, the required communication standard is likely to define specific frequency bands and channel separations that a radio device must use. In practice, it is usual to define the divide ratios according to the minimum channel spacing required by the communication standard. In order to efficiently implement the radio, and to fully use the available frequency spectrum, the divide ratios are almost always contiguous. That is, the prescaler is able to implement every divide ratio at or above a given minimum divide ratio. For example, an 8/9 prescaler is able to implement divide ratios contiguously from a minimum divide ratio of 56. For example, the 8/9 prescaler can divide by 56, 57, 58, 59, and every integer value thereafter. Although the 8/9 prescaler may implement some divide ratios less than 56, it cannot do so contiguously. For example, the 8/9 prescaler cannot practically implement a divide ratio of 55. In a similar manner, the 4/5 prescaler is contiguous from a minimum divide ratio of 12, and the 16/17 prescaler is contiguous from a minimum divide ratio of 240.
To reduce power consumption and space requirements, known prescalers are designed to conserve components, power, and space. Over the years, standard designs have evolved which more efficiently use logic components. For example, the 4/5 prescaler can be implemented using 3 flip-flops and associated logic gates, the 8/9 prescaler can now be implemented using 4 flip-flops and associated logic gates, and the 16/17 prescaler can now be implemented using 5 flip-flops and associated logic gates. Further, it is important to consider how much circuitry must operate at the frequency of the VCO, since the timing requirements for these components tend to be critical, as well as having increased power needs. In known designs, several of the flip-flops typically operate at the VCO frequency. For example, in the 8/9 prescaler, which has a total of 4 flip-flops, 3 of those flip-flops operate at full VCO frequency.
In another consideration, prescalers are designed to implement particularly efficient division algorithms. For example, N is almost always selected to be a power of 2, since this allows a simple bit shift to implement a divide-by-2 function. Other implementations would become unnecessarily complex. However, the selection of simplified electronic arrangements limits the flexibility of the division algorithm. Take for example the division algorithm for a known 8/9 prescaler. Any natural number may be written as D=M*8+A, where M and A are natural, and A is in the range of 0 and 7. As understood by one skilled in the art, a natural number is an integer which is positive or zero. However, implementing a practical 8/9 prescaler usually involves a more restrictive algorithm, which may be written as D=(M−A)*8+A*9. This algorithm is the division process as actually implemented in the electronic components, and illustrates some of the limitations inherent in the 8/9 prescaler. For example, the electronic components are only able to act on natural numbers, and since A has a maximum value of 7, then M must have a minimum value of 7. Otherwise, the term (M−A) results in a negative number. Using this implementation, the minimum value of D is 56 (M=7 and A=0).
Therefore, there exists a need for a frequency prescaler that provides adequate frequency reduction, required frequency resolution, and that can be efficiently and robustly implemented.

Prescaler for a fractional-N synthesizer


A light arrangement in the form of a center high mounted brakelight is shown. A surface light source disposed below a rear window of the vehicle and includes a plurality of diverging light sources, each emitting a diverging light for interference with a hologram assembly affixed to the inner surface of the rear window. The hologram assembly includes a plurality of holograms which were produced by holography by exposure to a converging beam from the area where the surface light source is arranged after mounting said hologram assembly in the vehicle.

The present invention relates to a lamp arrangement for a vehicle and, more particularly to a light using a holographic structure.
An object of the present invention is to provide a light for a vehicle including a holographic structure which is capable of diffracting illuminated light from a light source with good efficiency without increasing the performance of the light source.


A communications system serves as a proxy for a user device in a communications network. The communications system includes a network gateway that receives content in response to a user initiated content utilization attempt from a user device. A computer receives the content from the network gateway and, in response to receiving the content, determines whether the content utilization by the user can be permitted. The computer can also determine whether the content utilization by the user can be completed.

1. Field of the Invention
The present invention relates to the field of communications networks. More particularly, the present invention relates to enforcing digital rights when an end user device attempts to send, receive or utilize content using a communications network.
2. Background Information
A need exists to ensure that an ownership right to limit distribution and utilization of proprietary content is enforced when an attempt is made to transmit or receive the content using a communications network. Presently, many efforts to protect ownership rights on a network are based on limiting the functionality of the content when outside the domain of approved use. For example, a variety of current efforts to enforce an ownership right to limit utilization of content are based upon encryption before the content is distributed to users. Additionally, an owner may arrange for digital watermarks to be added to content before distribution to users. Moreover, an owner of content rights may rely on a digital signature of an authorized user or third-party certifying authority before the authorized user is provided with access to the content by a content distributor. However, encryption, watermarking and digital signatures schemes are not completely effective in preventing unauthorized decryption and electronic forgery, resulting in unauthorized distribution and utilization of the content. Without assurance that ownership rights can be adequately enforced, owners are withholding content from distribution on modern communications networks such as the internet.
Additionally, legacy communications devices may not support enforcement, control and management of digital rights when content distribution is otherwise possible over a modern communications network. Many user devices do not have sufficient memory or processing capability to support a licensing or digital rights management program. For example, a conventional cell phone has limited capability to support license control schemes for enforcement of digital rights.
Accordingly, a need exists to ensure that the transmission or receipt of content by a user is authorized by an owner of rights to the content before the transmission or receipt of the content over the communications network is permitted. Additionally, a need exists for a proxy to determine whether a content utilization or distribution, over a communications network, requested by a communications device is permitted by an owner of rights to the content.
To solve the above-described problems, a communications system is provided for ensuring that digital rights are enforced when a user attempts to initiate a network based content utilization.