A radio frequency (RF) amplifier system includes an RF power amplifier having an input and an output, and a typical gain of 1000 or more between the input and the output. An adaptive feedback channel is coupled between the input and the output of the RF power amplifier. The adaptive feedback channel receives as inputs audio signals for modulation of the input of the RF power amplifier, a frequency command word indicative of a desired frequency and phase of the RF amplifier system, and a control word indicative of a desired power level of the output of the RF power amplifier and of a mode of operation of the RF amplifier system. In response to the inputs, the adaptive feedback channel provides as an output a degenerative feedback signal to the input of the RF power amplifier.

Contemporary radio frequency (RF) power amplifiers lack the dynamic output level control, efficiency, and linearity to meet present and future RF system requirements. Present technology RF power amplifiers utilize an analog Automatic Level Control (ALC) to control RF power output levels. These current designs have limited dynamic control range and less than desired output level stability in applications such as amplitude modulation (AM), frequency modulation (FM), spread spectrum, and special modulation waveform signals. One prior art RF power amplifier control methodology is to shift the active element's bias or operational "Q" point, which changes the gain of one or more amplifier stages, thus controlling the RF output of the power amplifier. Shifting the "Q" point degrades amplifier efficiency and linearity. This degradation is not acceptable in many systems.
Operational amplifiers are well known and were originally used to perform mathematical functions such as addition, sign changing, integration and differentiation in analog computers. Today they are used in many applications. The fundamental theories developed for analog computer modeling required the basic amplifiers to have gains of 60 dB to 140 dB. Once an amplifier met this criterion, simple mathematical formulas were used to describe operational conditions and feedback loops. This includes applications with complex impedance elements that provided integration and differentiation functions, as well as multi-pole filters. The basic theory of operational amplifiers and their applications are well understood because of their use in analog computers.
An operational amplifier contains many individual circuits within the physical package. This combination of circuits is analyzed as a composite element for operational amplifier applications. Operational amplifier circuit or application designs focus on the external feedback loops from input to output and disregard the internal circuits of the packaged amplifier. Applying the same operational amplifier feedback theory to RF power amplifiers has not been practical because the basic operational amplifier criterion of high gain is rarely met in RF amplifiers and because of the presence of parasitic impedance parameters in the feedback loop, which restrict the operational bandwidth of the amplifier. Most contemporary RF amplifiers operate over a wide RF spectrum which generally causes parasitic complex impedances throughout the amplifier circuits. The parasitic parameters may cause undesired performance over the frequency range of the RF amplifier. Some contemporary RF amplifiers utilize degenerative or negative feedback to stabilize individual RF amplifier circuits within the amplifier, but rarely interact between stages. For these or other reasons, most prior art RF amplifier designs do not provide the dynamic output level control, efficiency and linearity over a wide frequency ranges as required in new high performance applications.

Adaptive feedback channel for radio frequency power amplifiers


A mobile terminal can release a point-to-multipoint radio bearer (RB) in an explicit manner or an implicit manner, whereby an explicit RB release mechanism allows the network to explicitly instruct the mobile terminal to release the RB, while an implicit RB release mechanism allows the mobile terminal itself to release the RB without receiving any explicit instructions from the network.

The present invention relates to releasing a point-to-multipoint radio bearer for a multicast or broadcast service in a mobile terminal, and in particular, to determining the releasing of the point-to-multipoint radio bearer by checking a status of the multicast or broadcast service when a data of the multicast or broadcast service is not received for a certain period of time after the mobile terminal establishes the point-to-multipoint radio bearer and receives the data of the multicast or broadcast service.
A universal mobile telecommunication system (UMTS) is a third generation mobile communications system that has evolved from the European Global System for Mobile communications (GSM) that aims to provide an improved mobile communications service based upon a GSM core network and wideband code division multiple access (W-CDMA) wireless connection technology.
FIG. 1 illustrates an exemplary basic structure of a UMTS network. As shown in FIG. 1, the UMTS is roughly divided into a terminal 100 (mobile station, user equipment (UE), etc.), a UTRAN 120, and a core network (CN) 130. The UTRAN 120 includes one or more radio network sub-systems (RNS) 125. Each RNS 125 includes a radio network controller (RNC) 123, and a plurality of base stations (Node-Bs) 121 managed by the RNC 123. One or more cells exist for each Node B.
The RNC 123 handles the assigning and managing of radio resources, and operates as an access point with respect to the core network 130. The Node-Bs 121 receive information sent by the physical layer of the terminal 100 through an uplink, and transmit data to the terminal through a downlink. The Node-Bs 121, thus, operate as access points of the UTRAN 120 for the terminal 100. Also, the RNC 123 allocates and manages radio resources and operates as an access point with the core network 130.
Between various network structure elements, there exists an interface that allows data to be exchanged for communication therebetween.
FIG. 2 illustrates a radio interface protocol architecture (structure) between the terminal 100 and UTRAN 110 that is based upon 3GPP wireless access network technology. Here, the radio access interface protocol has horizontal layers including a physical layer, a data link layer and a network layer, and has vertical planes including a user plane for transmitting data information and a control plane for transmitting control signals. The user plane is a region to which traffic information of a user, such as voice data or Internet-protocol (IP) packets are transmitted. The control plane is a region to which control information, such as an interface of a network or maintenance and management of a call, is transmitted. In FIG. 2, protocol layers can be divided into a first layer (L1), a second layer (L2) and a third layer (L3) based upon the three lower layers of an open system interconnection (OSI) scheme that is well-known in the art of wireless (mobile) communication systems.
Each layer shown in FIG. 2 will now be described. The first layer (L1) uses various radio transmission techniques to provide information transfer service to the upper layers. The first layer (L1) is connected via a transport channel to a medium access control (MAC) layer located at a higher level, and the data between the MAC layer and the physical layer is transferred via this transfer channel. Also, between different physical layers, namely, between the respective physical layers of the transmitting side and the receiving side, data is transferred via a physical channel.
The MAC layer handles the mapping between the logical channels and the transport channels, and provides a re-allocation service of the MAC parameter for allocation and re-allocation of radio (wireless) resources. The MAC layer is connected to an upper layer called a radio link control (RLC) layer through a logical channel, and various logical channels are provided according to the type of transmitted information.
The MAC layer of the second layer (L2) provides services to a Radio Link Control (RLC) layer, which is an upper layer, via a logical channel. The RLC layer of the second layer (L2) can support reliable data transmissions, and can perform a segmentation and concatenation function on a plurality of RLC service data units (RLC SDUs) delivered from an upper layer.
A packet data convergence protocol (PDCP) layer is located at an upper layer from the RLC layer, allowing data to be transmitted effectively via a radio interface with a relatively small bandwidth through a network protocol.
The radio resource control (RRC) layer located at the lowest portion of the third layer (L3) is only defined in the control plane, and controls the transport channels and the physical channels in relation to the configuration, the re-configuration, and the releasing of the radio bearers (RBs).
The radio bearer service refers to a service that the second layer (L2) provides for data transmission between the terminal (UE) 10 and the UTRAN 100 in order to guarantee a predetermined quality of service by the UE and the UTRAN. And in general, the radio bearer (RB) establishment refers to regulating the protocol layers and the channel characteristics of the channels required for providing a specific service, as well as respectively setting substantial parameters and operation methods.
Among the RBs, the particular RB used between the UE and the UTRAN for exchanging RRC messages or NAS messages is called a SRB (Signaling Radio Bearer). When an SRB is established between a particular UE and the UTRAN, a RRC connection exists between the UE and the UTRAN. A UE having a RRC connection is said to be in RRC connected mode, and a UE without a RRC connection is said to be in idle mode. When a UE is in RRC connected mode, the RNC determines the cell in which the UE is located (i.e., the RNC determines the UE location in units of cells), and manages that UE.
Next, multimedia broadcast/multicast service (MBMS) will be described. MBMS refers to a downlink transmission service for providing data services such as, streaming services (e.g., multimedia, video on demand, webcast) or background services (e.g., e-mail, short message services (SMS), downloading), to a plurality of terminals by employing a downlink dedicated MBMS bearer service.
MBMS can be classified into a broadcast mode and a multicast mode. The MBMS broadcast mode refers to transmitting multimedia data to all users within a broadcast area, which is a region where broadcast service is possible. In contrast, MBMS multicast mode refers to transmitting multimedia data to only a certain specified user group within a multicast area, whereby a multicast area, which is a region where multicast service is possible. Thus, an MBMS service may also be referred to as a 'point-to-multipoint service'.
A single MBMS service can consist of one or more sessions, and MBMS data are transmitted to the plurality of terminals via an MBMS bearer service during an ongoing session.
The UTRAN uses a radio bearer (RB) to provide a MBMS bearer service to a terminal. The types of radio bearers used by the UTRAN include a point-to-point (p-t-p) radio bearer and a point-to-multipoint (p-t-m) radio bearer. Here, the point-to-point RB is a bi-directional RB that comprises a logical channel (DTCH: Dedicated Traffic CHannel) and a transport channel (DCH: Dedicated CHannel), and a physical channel (either a DPCH (Dedicated Physical CHannel) or a SCCPCH (Secondary Common Control Physical CHannel)). A point-to-multipoint RB is a uni-directional RB that comprises, as shown in FIG. 3, a logical channel (MTCH: MBMS Traffic CHannel) and a transport channel (FACH: Forward Access CHannel), and a physical channel (SCCPCH: Secondary Common Control Physical CHannel). The logical channel MTCH is configured for each MBMS service provided to a single cell, and is a channel that is used for transmitting user plane data of a particular MBMS service to a plurality of users.
The UTRAN that provides MBMS service transmits, to a plurality of terminals, a MBMS-related control message (namely, a RRC message related to MBMS service data) via a MCCH (MBMS Control CHannel). Examples of an MBMS-related message include a message that informs MBMS service data, a message that informs point-to-multipoint RB data, etc. As shown in FIG. 3, the logical channel MCCH is a point-to-multipoint downlink channel that maps to a transport channel FACH (Forward Access CHannel), which maps to a physical channel SCCPCH (Secondary Common Control Physical CHannel). For a single cell, only one MCCH exists.
A terminal wishing to receive a particular MBMS that uses a point-to-multipoint RB, first receives via the MCCH, a RRC message that includes RB data, and then the point-to-multipoint RB is established with the terminal using such RB data. Thereafter, the terminal continues to receive the physical channel SCCPCH (to which the MTCH is mapped) and obtains the data of the particular MBMS service being transmitted via the MTCH.
When one session of a particular MBMS service that uses a point-to-multipoint RB is completed, the UTRAN transmits a message that instructs the release of the point-to-multipoint bearer, via the MCCH to the terminals that are receiving the particular MBMS service. Also, the UTRAN releases the point-to-multipoint RB established at the RNC and Node B. Meanwhile, a terminal that has received the above-identified message releases the point-to-multipoint RB that had been established with the terminal for the particular MBMS service.
While a particular MBMS service is in progress, one or more sessions for that service may occur in sequence. Here, a session may be defined in various ways. For example, a session may be each complete episode of a multi-episode drama or a session may be certain portions of a sports program, such as scenes that show goals in a soccer match.
When data to be transmitted for a particular MBMS service is generated at the MBMS data source, the core network (CN) 130 informs a session start to the RNC 123. In contrast, when there is no further data at the MBMS data source to be transmitted for a particular MBMS service, the core network (CN) 130 informs a session stop to the RNC 123. Between the session start and the session stop, a data transfer procedure for the particular MBMS service can be performed. Here, only those terminals that have joined a multicast group for the MBMS service may receive data that is transmitted by the data transfer procedure.
In the above session start procedure, the UTRAN that received the session start from the core network (CN) transmits an MBMS notification to the terminals. Here, MBMS notification refers a function of the UTRAN for informing a terminal that the transmission of data for a particular MBMS service within a certain cell is impending. The UTRAN can use the MBMS notification procedure to perform a counting operation that determines the number of terminals that wish to receive a particular MBMS service within a particular cell. The counting procedure is used to determine whether the radio bearer for providing the particular MBMS service should be set as point-to-multipoint (p-t-m) or point-to-point (p-t-p). For selecting the MBMS radio bearer, the UTRAN internally establishes a threshold value. After performing the counting function, the UTRAN may set a point-to-point MBMS radio bearer if the number of terminals existing within the corresponding cell is smaller than the threshold value, and may set a point-to-multipoint MBMS radio bearer if the number of terminals existing within the corresponding cell is greater than or equal to the threshold value.
If a point-to-point radio bearer is to be set, the UTRAN allocates a dedicated logical channel to each terminal (UE) and sends the data of the corresponding service. If a point-to-multipoint radio bearer is to be set, the UTRAN uses a downlink common logical channel to send the data of the corresponding service.
In the related art, the terminals that receive a particular MBMS service upon establishing a point-to-multipoint RB, release the established point-to-multipoint RB only after they receive a message from the system instructing that the point-to-multipoint RB should be released. However, in this case, those terminals that do not receive such message due to poor radio environment conditions or operation errors, cannot properly determine when the established point-to-multipoint RB should be released.
Accordingly, if the terminal is in a temporary data reception pause state and release of the RB is prematurely performed, the terminal cannot receive any MBMS service data that was transmitted after the temporary data reception pause. Also, if the terminal could not determine whether the RB should be released and thus releasing of the RB is not performed when necessary, the terminal must continue to unnecessarily maintain the point-to-multipoint RB, which thus results in a waste of terminal resources. Namely, in the related art, the terminal cannot distinguish between a temporary data reception pause and a RB release situation, and thus cannot properly determine when the point-to-multipoint RB should be released. This results in a problem for the terminal of not being able to effectively control the operations of maintaining and releasing a radio bearer. Thus, the inventors of the present invention recognized such drawbacks of the related art and provided a solution by allowing the terminal (UE) to release a point-to-multipoint radio bearer in either an explicit manner or an implicit manner, to be explained in more detail hereafter.

Apparatus and method of releasing a point-to-multipoint radio bearer


A dielectric resonance device includes at least one dielectric resonator having a hollow frame body often called the "cavity" in the art, cross-coupled dielectric pillars in the frame body, and an earth conductor on the outer surface of the frame body. The frame body has a pair of opposed openings at opposite ends thereof. A plurality of conductive plates are provided each of which has a first end coupled to the earth conductor and a second end. Two printed circuit boards acting as front and rear panel plates are attached to cover the openings, respectively. The second ends of the conductive plates are coupled by soldering to metal films of the first and second printed circuit boards while having the conductive plates folded to be in area-contact with and electrically connected to the printed circuit boards so as to tightly hold these boards. The dielectric resonator is held in a casing together with the conductive plates and the first and second printed circuit boards. An input/output connector is fixedly attached to the casing. This connector has a conductive portion being electrically connected to one of the first and second printed circuit boards.

1. Field of the Invention
The present invention relates generally to dielectric resonators and more particularly to dielectric resonance device including one or a plurality of dielectric resonators each having a hollow frame body with an internal dielectric material disposed therein and a conductive material on the outer surfaces thereof.
2. Description of the Prior Art
In the prior art, TM-mode dielectric resonators are typically arranged to have a hollow frame body, sometimes called the "cavity" in the art, with an internally disposed dielectric material and a conductive material acting as an earth conductor disposed on the outer surfaces of the frame body. To provide easy assembly, these components are arranged in such a manner that the frame body consists of a rectangular cylindrical member having two openings at the opposite ends thereof with the dielectric material being disposed therein, and four outer surfaces (i.e., the top, bottom and two side wall surfaces) on which conductive layers are formed as the earth conductor. The inner dielectric material is comprised of a cross-coupled pillar member having two pillars, one of which extends horizontally to be coupled with two opposed inner surfaces of the side walls of frame body and the other of which extends vertically to be coupled with the other two opposed, top and bottom inner surfaces of the same.
In the manufacture of a multiple-stage dielectric resonance device including an array of dielectric resonators which are sequentially coupled to one another to provide a desired filter function, two adjacent ones of the resonators are disposed so that corresponding openings of the resonators face each other, and a conductive earth plate is attached by soldering to neighboring outer conductors on the outer surfaces of the resonators, thus causing the two adjacent resonators to be fixedly coupled to each other. Such resonator structure has been disclosed, for example, in Japanese Utility-Model Application No. 1-172702.
Unfortunately, such a conventional "conductor-soldering" resonator structure suffers from a problem in that an increased amount of heat may be generated at or in the vicinity of the soldered portions of neighboring dielectric resonators. In addition, soldering is a labor intensive and time consuming process, which causes the manufacturing process to decrease in efficiency while letting it become somewhat dangerous to factory workers.
The reasons for this will be described with reference to FIG. 8. In FIG. 8, there is illustrated in cross-section a prior art dielectric resonator structure, which employs a metal panel that is fixed to one opening of a resonator frame body in the case where two neighboring dielectric resonators are coupled together by soldering a conductive plate at its opposite ends to respective outer conductors of the resonators. As shown in FIG. 8, the frame body has a cross-coupled dielectric pillar member 4 integrally disposed in the inner space thereof. The frame body also has conductive layers 2 acting as the earth conductors which are formed on respective outer surfaces of the frame body. The frame body has a pair of openings at its opposite ends, at which openings two metal panels 8, 9 are disposed. These metal panels are coupled to the frame body using relatively thin conductive plates 6 by soldering each conductive plate 6 at its respective ends to the outer conductor 2 and to one edge of a corresponding metal panel 8 (or 9) opposed thereto. One of the metal panels, i.e., the front panel 8 in this case, has a hole for attachment of a known input/output connector 10 on it while a coupling loop 11 is used for electrically coupling the coupling loop 11 with the front panel 8. The whole structure is packed into a casing 12.
In the prior art resonator structure of FIG. 8, since the metal panels 8, 9 are designed to function also as a part of the casing 12, it is required that these panels be thick enough to provide a certain physical strength as required for the casing 12. In particular, when the input/output connector 10 is attached to and mounted on the metal panel 8, this panel 8 is required to be tough or stiff enough to fixedly hold the input/output connector 10 thereon; otherwise, when the connector 10 is twisted manually by a user, the panel 8 may possibly change shape causing the dielectric resonator to vary in its electric characteristics. To attain such stiffness, the metal panel should be thicker accordingly. However, as the panel thickness increases, the occurrence of heat diffusion becomes more severe during the soldering process at or in the vicinity of soldering portions of the resonator structure. This brings a more serious problem in that when an array of dielectric resonators are combined together into one integral form using a large-size metal panel, not only the resonators but also the metal panel must be preheated using an oven before the execution of the soldering process. This requires labor-intensive manufacturing steps at high temperatures which causes productivity to decrease. Moreover, such a process is dangerous to factory workers.

Method of manufacturing a dielectric resonator device with an opening covered by a printed circuit board and a conductive plate contacting the printed circuit board


A CD drive includes an upper cover, a disk tray, a clamp, a push piece, and a guiding rod. The upper cover includes a guiding track and the disk tray is installed below the upper cover in a slidable manner. Additionally, the clamp is installed on the upper cover in a moveable manner, while the push piece is installed on the disk tray. The guiding rod has a first end fixed on the push piece, and a second end slidably installed in the guiding track. When the disk tray slides in or slides out of the upper cover, the guiding rod will slide along the guiding track and move the push piece to push the clamp upward so as to prevent the clamp from scraping an optical disk.

1. Field of the Invention
The present invention relates to a CD drive, and more specifically, to a CD drive capable of preventing an optical disk from being scraped.
2. Description of the Prior Art
With the development of digital videos and high quality digital products, compact disks (CD) have insufficient capacity and have been gradually replaced by digital video disks (DVD) having much higher capacity. A typical DVD includes two sides for recording data, so that an optical drive for reading the data stored in the DVD has to be designed to avoid scraping any side of the DVD. However, it is difficult for a prior art optical drive to read the DVD without scraping it. As the prior art optical drive is not placed horizontally, an optical disk will slightly touch a clamp of the optical drive when the optical disk is loaded into or withdrawn from the optical drive, which leads to forming scratches on the optical disk. Accordingly, a surface of the optical disk will be damaged due to long-term scratching, and further, the data stored in the optical disk may be destroyed.
For overcoming the above-mentioned problems, a clamp comprising a magnet to magnetically attract an upper cover for preventing the clamp from scraping an optical disk is disclosed in U.S. Pat. No. 6,246,654. Please refer to FIG. 1. FIG. 1 is a schematic diagram illustrating a prior art CD drive 10 having a magnetic clamp. The CD drive 10 comprises an upper cover 12, a clamp 14, a disk tray 16, a turning table 18, and a motor 20. The clamp 14 is installed inside the upper cover 12 in a movable manner, while the disk tray 16 is movably installed between the clamp 14 and the turning table 18. Additionally, the motor 20 is disposed under the turning table 18 and an optical disk 22 is put on the disk tray 16. When the CD drive 10 tries to read data stored in the optical disk 22, the turning table 18 firstly pushes the optical disk 22 upward and clamps the optical disk 22 to the clamp 14 for removing the optical disk 22 from the disk tray 16. Then, the motor 20 will drive the turning table 18 to rotate and a pick-up head of the CD drive 10 can read the data stored in the optical disk 22 thereby. The clamp 14 further comprises a magnet 24 located around a center of the clamp 14, and a yoke 26 horizontally located on an upper surface of the magnet 24. Furthermore, the yoke 16 is utilized to magnetize the magnet 24 in a vertical direction, so that magnetic attracting forces produced by the magnet 24 can act in the vertical direction.
As shown in FIG. 1, when the optical disk 22 is loaded into or withdrawn from the CD drive 10, the turning table 18 moves downward. Then, the vertical magnetic attracting forces produced by the magnet 24 in the clamp 14 act between the clamp 14 and the upper cover 12 for moving the clamp 14 upward and removing the clamp 14 from the optical disk 22. Thereby, the clamp 14 is magnetically attracted to a lower surface of the upper cover 12. Under this condition, since the yoke 24 is placed horizontally on the upper surface of the magnet 24, the magnetic attracting forces acting upward from the magnet 24 are smaller than those acting downward from the magnet 24. Furthermore, because the magnet 24 attracts the upper cover 12 through an inner wall of the clamp 14, the magnetic attracting forces acting upward from the magnet 24 are further weakened. As a result, the clamp 14 is attracted to the lower surface of the upper cover 12 under relatively weak magnetic attracting forces.
When the CD drive 10 reads the optical disk 22, the turning table 18 moves upward and clamps the optical disk 22 to the clamp 14. Accordingly, the optical disk 22 is lifted above the disk tray 16. At the same time, the turning table 18 comes close to the magnet 24 in the clamp 14 so that a distance between the magnet 24 and the optical disk 22 is smaller than a distance between the magnet 24 and the upper cover 12. Consequently, the clamp 14 is attracted downward to tightly hold the optical disk 22 under the vertical magnetic attracting forces acting between the magnet 24 and the turning table 18. Furthermore, since the magnetic attracting forces acting downward from the magnet 24 are larger than those acting upward from the magnet 24, the clamp 14 can be easily separated from the upper cover 12, and the magnet 24 provides the magnetic attracting forces for the clamp 14 to clamp the optical disk 22 more strongly. In the other words, by moving the turning table 18 upward to come closer to the clamp 14 or moving the turning table 18 away from the clamp 14, operations of descending and ascending the clamp 14 under the vertical magnetic attracting forces produced by the magnet 24 can be reversibly switched from one to the other. The detailed explanation is described in U.S. Pat. No. 6,246,654 and will not be discussed herein.
As mentioned above, the magnet 24 is introduced into the clamp 14 in the prior art. When the optical disk 22 is loaded into or withdrawn from the CD drive 10, the clamp 14 attracts the upper cover 12 through use of the magnetic attracting forces produced by the magnet 24 for preventing the clamp 14 from scraping the optical disk 22. However, the magnetic attracting forces produced by the magnet 24 decrease as temperature increases. Furthermore, the clamp 14 is attracted to the upper cover 12 under relatively weak magnetic attracting forces produced by the magnet 24. When the magnetic attracting forces produced by the magnet 24 are too small to attract the clamp 14 to the upper cover 12, the optical disk 22 will be scraped by the clamp 14. In addition, other corresponding techniques can be acquired from U.S. Pat. No. 6,373,813.

CD drive which will not damage an optical disk


An IPS liquid crystal display (200) of a preferred embodiment of the present invention includes a first substrate (201), a second substrate (202), and liquid crystal molecules interposed therebetween. A plurality of gate lines (211) and data lines (212) are formed at the first substrate, thereby defining a plurality of pixel regions. A pixel electrode (233), a common electrode (243) and a TFT (220) are provided in each pixel region, the pixel electrode and the common electrode having a same curved shape. Because the pixel and common electrodes of have a same curved shape with smooth bends, when a voltage is applied, disclination of the liquid crystal molecules does not occur, and the contrast ratio of the IPS LCD is unimpaired. Furthermore, the electric field generated by them is a smooth continuum of multiple domains, and the IPS LCD provides equally fine visual performance at various different viewing angles.

1. Cross Reference to Related Application
This application is related to a co-pending application entitled "Continuous domain in-plane switch liquid crystal display," which is assigned to the same assignee as this application.
2. Field of the Invention
The present invention relates to IPS (in-plane switching) mode LCDs (liquid crystal displays), and particularly to an IPS LCD which provides continuous domains when in a driven state.
3. General Background
A liquid crystal display utilizes the optical and electrical anisotropy of liquid crystal molecules to produce an image. The liquid crystal molecules have a particular passive orientation when no voltage is applied thereto. However, in a driven state, the liquid crystal molecules change their orientation according to the strength and direction of the driving electric field. A polarization state of incident light changes when the light transmits through the liquid crystal molecules, due to the optical anisotropy of the liquid crystal molecules. The extent of the change depends on the orientation of the liquid crystal molecules. Thus, by properly controlling the driving electric field, an orientation of the liquid crystal molecules is changed and a desired image can be produced.
The first type of LCD developed was the TN (twisted nematic) mode LCD. Even though TN mode LCDs have been put into use in many applications, they have an inherent drawback that cannot be eliminated; namely, a very narrow viewing angle. By adding compensation films on TN mode LCDs, this problem can be ameliorated to some extent. However, the cost of the TN mode LCD is increased. Therefore, a totally different driving means called IPS (in-plane switching) was proposed as early as in 1974. Then in 1993, Hitachi Corporation filed its first U.S. patent application concerning IPS LCDs, in which a particular IPS mode LCD was disclosed.
A conventional IPS mode LCD has an upper substrate, a lower substrate, and a liquid crystal layer interposed therebetween. The liquid crystal layer has a plurality of liquid crystal molecules which have a same orientation when not driven, this orientation being parallel to the substrates. Pixel electrodes and common electrodes are disposed on the lower substrate. When a voltage is applied to the electrodes, an electric field is generated between the electrodes. The electric field drives the liquid crystal molecules to rotate, so that they have a new orientation that is still parallel to the substrates. The change in orientation results in a change in light transmission. In other words, the operation of the IPS mode LCD is such that the liquid crystal molecules rotate in a plane parallel with the substrates in order to fulfill optical switching. The displayed image has the important advantage of a wide viewing angle. In basic IPS mode LCDs, the pixel electrodes and common electrodes are each comb-shaped. The electric field of these LCDs in a driven state is along a certain direction. When the displayed image is viewed at different oblique angles, an observer can notice a quite large color shift.
Referring to FIG. 5, this is a top cross-sectional view of a pixel area of an IPS liquid crystal display as disclosed in U.S. Pat. No. 6,459,465 issued on Oct. 1, 2002. The pixel area includes a gate line 113 arranged in a first direction, a data line 115 and a common line 135 both arranged in a second direction orthogonal to the first direction, a pixel electrode 131, a common electrode 133, and a TFT (thin film transistor) 120 positioned at an intersection of the data line 115 and the gate line 113. The TFT 120 has a gate electrode 121, a source electrode 123 and a drain electrode 125, which are connected with the gate line 113, the data line 115 and the pixel electrode 131 respectively. The pixel electrode 131 and the common electrode 133 are spaced apart from each other. The pixel and common electrodes 131, 133 are each generally comb-shaped, with the teeth thereof being zigzagged. First portions of the teeth of the pixel and common electrodes 131, 133 that are aligned in a first direction and are parallel to each other form a first sub-electrode group. Second portions of the teeth of the pixel and common electrodes 131, 133 that are aligned in a second direction and are parallel to each other form a second sub-electrode group.
When a voltage is applied, because the pixel and common electrodes 131, 133 have the zigzagged structures, the electric field (not shown) generated is mainly along two directions. Referring to FIG. 6, the upper portion thereof shows part of the first sub-electrode group, and the lower portion thereof shows part of the second sub-electrode group. The liquid crystal molecules 130 in the upper and lower portions have different orientations, and the LCD exhibits a two-domain display effect. When viewing the LCD display from any oblique angle, the color shifts generated by the two domains counteract each other, and thus the overall color shift of the display is small.
However, the two-domain electrode configuration of the LCD inherently limits the display thereof. Equally good visual performance at various different viewing angles cannot generally be attained.
What is needed is a multi-domain IPS liquid crystal display which has a high contrast ratio and improved wide viewing angle characteristics.

Continuous domain in-plane switching liquid crystal display


Hydrogen ions (40) of high concentration are implanted into an amorphous silicon film (21). By implantation of the hydrogen ions (40), a hydrogen-ion implantation layer (41) is formed in the amorphous silicon film (21). Subsequently, by performing a heat treatment, a columnar grain is formed in a portion of the amorphous silicon film (21) other than the portion in which the hydrogen-ion implantation layer (41) is formed. On the other hand, in the hydrogen-ion implantation layer (41), a granular grain is formed. A granular grain layer (42) has a lot of grain boundaries extending multidirectionally, such as a grain boundary extending along a direction of film thickness of a polysilicon film (44a) and a grain boundary extending along a direction other than that of film thickness of the polysilicon film (44a). Thus, it is possible to achieve a method of manufacturing a semiconductor device which can appropriately suppress variation in threshold voltage which is caused by penetration of dopant.

1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and a structure of a semiconductor device, and more particularly to a method of manufacturing a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a structure thereof.
2. Description of the Background Art
With miniaturization of semiconductor devices, a technique of forming a metal silicide for use in gate, source and drain has been in actual use as one of attempts to increase drain currents of a MOSFET for high-speed operation of circuits. A characteristic feature of the metal silicide lies in its lower resistance value than that of a doped polysilicon. In order to form the metal silicide, a refractory metal film is deposited on a silicon and then a heat treatment such as RTA (Rapid Thermal Annealing) is performed to react the silicon with the refractory metal film. Forming the metal silicide for use in the gate, source and drain lowers the resistance values of the respective regions, thereby increasing the drain currents.
Among kinds of metal suicides well known are a titanium silicide (TiSi2), a tungsten silicide (WSi2), a nickel silicide (NiSi), a platinum silicide (PtSi), a cobalt silicide (CoSi2) and the like. Among them, it is known that even when used in a fine gate electrode whose gate length is 0.1 xcexcm or less, the cobalt silicide can lower the resistance of the gate electrode. On the other hand, it is known that when used in a gate electrode whose gate length is 0.15 xcexcm or less, the tungsten silicide increases the resistance of the gate electrode by the linewidth effect. The cobalt silicide, nickel silicide or platinum silicide does not have the linewidth effect.
Now, reaction of cobalt (Co) with silicon (Si) will be discussed. At 400xc2x0 C., Co begins to react with Si, thereby forming a Co2Si, and the sheet resistance gradually becomes higher. At 450 to 500xc2x0 C., a CoSi is formed and the sheet resistance becomes maximum. Over 600xc2x0 C., a CoSi2 is formed and the sheet resistance becomes lower.
In the process of forming the cobalt silicide, first, a first RTA is performed at 450 to 600xc2x0 C. Next, an unreacted Co is removed and then a second RTA is performed at 650 to 800xc2x0 C. to lower the sheet resistance. Further, when the temperature for the second RTA rises up to 900xc2x0 C., as the Co in the metal silicide is diffused into a silicon substrate, reaching the vicinity of a pn junction of source/drain regions, the amount of leakage currents increases.
FIG. 28 is a cross section showing a structure of a general-type MOSFET in which the cobalt silicide is formed. In an upper surface of a silicon substrate 101, an STI (Shallow Trench Isolation) 102 is selectively formed. On the upper surface of the silicon substrate 101, a gate electrode 104 is selectively formed with a gate insulating film 103 interposed therebetween. On the gate electrode 104, a cobalt silicide 106 is formed. Further, in the upper surface of the silicon substrate 101 formed are source/drain regions 111 which are paired with a channel region which is formed below the gate electrode 104 interposed therebetween, being in contact with side surfaces of the STI 102. On the source/drain regions 111, cobalt silicide layers 112 are formed. On side surfaces of the gate electrode 104, sidewalls 109 are formed with first and second offset films 107 and 108 interposed therebetween.
The reaction of silicidation proceeds through diffusion of refractory metal towards the silicon. Therefore, as shown in FIG. 28, the cobalt intrudes into an interface between the second offset film 108 and the silicon substrate 101, to form an intruding portion 114 of the cobalt silicide layer 112. Further, the cobalt intrudes into an interface between the STI 102 and the silicon substrate 101, to form an intruding portion 115 of the cobalt silicide layer 112.
With miniaturization of the semiconductor devices, when the width of the sidewall 109 becomes 10 nm or less, the intruding portion 114 of the cobalt silicide layer 112 reaches the gate insulating film 103 and the amount of leakage currents at the gate thereby increases. Further, when the depth of the pn junction formed at an interface between the source/drain region 111 and the silicon substrate 101 becomes shallower than the depth of 0.05 xcexcm from the upper surface of the silicon substrate 101, the intruding portion 115 of the cobalt silicide layer 112 reaches a depletion layer of the pnjunction and the amount of leakage currents at the source and drain thereby increases.
Furthermore, in a reaction process of silicidation, the metal silicide sometimes abnormally grows like a spike due to a stress in the phase transition of crystal, and the like. In FIG. 28 shown is an abnormally-grown spike 113 of the cobalt silicide. The cobalt silicide abnormally grows at the temperature of 400 to 450xc2x0 C., to form the spike 113. With miniaturization of the semiconductor devices, when the depth of the pn junction formed at the interface between the source/drain region 111 and the silicon substrate 101 becomes shallower than the depth of 0.1 xcexcm from the upper surface of the silicon substrate 101, the spike 113 reaches the depletion layer of the pn junction and the amount of leakage currents at the source and drain thereby increases.
As one of methods for suppressing generation of the spike which is caused by abnormal growth of the cobalt silicide well known is a preamorphization method. In this method, nitrogen or germanium is ion-implanted to amorphize the silicon substrate in advance before a cobalt film is deposited, and then the cobalt silicide is formed. Preamorphization of the silicon substrate relieves a stress caused at an interface between the silicide and the silicon on reaction, to suppress generation of the spike.
FIGS. 29 to 35 are cross sections showing a method of manufacturing an N-type MOSFET by the preamorphization method in the background art step by step. Referring to FIG. 29, first, the STI 102 is selectively formed in the upper surface of the silicon substrate 101. Subsequently, ion implantation is performed to form a well, a channel stopper layer and a channel dope layer (all not shown). Next, a silicon oxide film 120 is formed on the upper surface of the silicon substrate 101. Subsequently, an amorphous silicon film 121 is entirely deposited by the CVD (Chemical Vapor Deposition) method. Then, phosphorus ions 122 are implanted into the amorphous silicon film 121 by ion implantation.
Referring to FIG. 30, in the next step, the amorphous silicon film 121 and the silicon oxide film 120 are patterned by photolithography and anisotropic dry etching, to form the gate electrode 104 and the gate insulating film 103. Subsequently, a silicon-oxide-based insulating film such as a TEOS (Tetra Ethyl Ortho Silicate) film 123 is entirely deposited by the CVD method. With the temperature at this deposition, the amorphous silicon of the gate electrode 104 begins to become polysilicon (i.e., polycrystallize).
Referring to FIG. 31, in the next step, the TEOS film 123 is anisotropically etched, to form the first offset films 107 on the side surfaces of a gate structure consisting of the gate insulating film 103 and the gate electrode 104. Subsequently, arsenic ions 124 are implanted, to form extension regions 110 in the upper surface of the silicon substrate 101. Further, boron ions 125 are implanted, to form a pocket implantation region (not shown) in the silicon substrate 101. Forming the first offset film 107 is intended to protect the gate insulating film 103 in the ion implantation, to reduce variation in threshold voltage by increasing the effective channel length Leff and reduce the capacitance (gate overlap capacitance) formed between the gate electrode 104 and the extension region 110. Further, forming the pocket implantation region relieves roll-off of the threshold voltage and also suppresses occurrence of surface punch through. The arsenic ions 124 and the boron ions 125 are also implanted into the gate electrode 104.
Referring to FIG. 32, in the next step, a TEOS film 126 and a silicon nitride film 127 are entirely deposited in this order by the CVD method. With the temperature of this deposition, change of the gate electrode 104 into polysilicon further proceeds.
Referring to FIG. 33, in the next step, the silicon nitride film 127 and the TEOS film 126 are anisotropically etched, to form the sidewalls 109 and the second offset films 108. Subsequently, arsenic ions 128 are implanted, to form the source/drain regions 111. The arsenic ions 128 are also implanted into the gate electrode 104. Subsequently, in order to electrically activate the arsenic ions 124 and 128 and the boron ions 125, an RTA is performed at 1100xc2x0 C. With this heat treatment, the silicon substrate 101 is recovered from defects caused by the ion implantation. Further, with this heat treatment, a columnar grain having a grain boundary 105 which extends along a direction of film thickness of the gate electrode 104 is formed in the gate electrode 104.
Referring to FIG. 34, in the next step, in order to amorphize upper surfaces of the source/drain regions 111, in other words, for the above-discussed preamorphization, germanium ions (not shown) are implanted. Subsequently, by sputtering under an argon atmosphere, for example, a native oxide film (not shown) formed on the surfaces of the source/drain regions 111 is removed. Removing the native oxide film is intended to avoid an increase in resistance value of the metal silicide due to the presence of the native oxide film. Next, a cobalt film 129 and a titanium nitride film 130 are entirely deposited in this order. Forming the titanium nitride film 130 is intended to prevent an increase in sheet resistance through natural oxidation of the cobalt film 129, mixing of oxygen into the cobalt film 129 during conveyance of wafers and processing in the device, and the like.
Referring to FIG. 35, in the next step, the first RTA is performed at 400xc2x0 C. Subsequently, the titanium nitride film 130 and the unreacted cobalt film 129 are removed and then the second RTA is performed at 700xc2x0 C. An upper surface of the gate electrode 104 is thereby silicified to form the cobalt silicide layer 106 and the upper surfaces of the source/drain regions 111 are silicified to form the cobalt silicide layers 112.
The above-discussed method of manufacturing a MOSFET in the background art, however, has the following problems.
The First Problem
As shown in FIG. 33, in the gate electrode 104 formed is the columnar grain having the grain boundary 105 which extends along the direction of film thickness of the gate electrode 104. Since the diffusion coefficient of a dopant diffused along the grain boundary is higher than that of a dopant diffused in the grain, the dopant introduced into the gate electrode 104 is diffused mainly along the grain boundary 105 to reach an interface between the gate electrode 104 and the gate insulating film 103. To suppress gate depletion, it is desired to activate more dopant in the vicinity of this interface. When the amount of dopant reaching the vicinity of this interface becomes too large, however, part of the dopant penetrates the gate insulating film 103 to reach the inside of the silicon substrate 101 and as a result, the threshold voltage of the MOSFET goes out of the designed value. This phenomenon is referred to as xe2x80x9cpenetration of dopantxe2x80x9d.
To suppress variation in threshold voltage which is caused by the penetration of dopant, it is necessary to reduce the amount of dopant reaching the interface between the gate electrode 104 and the gate insulating film 103 by some method. Anyway, it is necessary to ion-implant the dopant into the gate electrode 104 densely to such a degree that the polysilicon can degenerate. Accordingly, simple reduction in dose to be ion-implanted into the gate electrode 104 causes some problems, such as an increase in resistance value of the gate electrode 104 and deterioration in current driving capability which is caused by gate depletion. Therefore, simple reduction in dose for ion implantation can not be adopted.
Thus, the background-art method of manufacturing a MOSFET has the problem of not appropriately suppressing variation in threshold voltage which is caused by the penetration of dopant.
The Second Problem
As can be seen from comparison between FIGS. 28 and 35, in the background-art method of manufacturing a MOSFET using preamorphization, it is possible to avoid or suppress generation of any spike 113 due to abnormal growth of silicide. It is not possible, however, to avoid generation of the intruding portions 114 and 115 of the cobalt silicide layer 112 even by the preamorphization method.
Thus, in the background-art method of manufacturing a MOSFET, the intruding portions 114 and 115 of the cobalt silicide layer 112 are still formed. Therefore, this method has a problem of increasing leakage currents at the gate, source and drain as the size of a semiconductor device becomes smaller.
Further, in the step of FIG. 30, the amorphous silicon film 121 is anisotropically etched to form the gate electrode 104, and the gas used in the step of anisotropic etching is free radical, such as CFx. Part of the free radical is accelerated by an electric field between a plasma sheath and a wafer in an etching device, to mix into the silicon substrate 101. The free radical which mixes into the silicon substrate 101 is dissociated into C atoms and F atoms through nuclear scattering caused by collision with silicon atoms. The F atoms become F2 molecule by the heat treatment or become HF molecule through chemical bond with hydrogen atoms in the silicon substrate 101, volatilizing out of the silicon substrate 101. In contrast, the C atoms remain inside the silicon substrate 101, disadvantageously, becoming a source of leakage current.
Furthermore, when the metal silicide is formed in a narrow region of about 0.15 xcexcm or less, the temperature required for phase transition from CoSi of high resistance to CoSi2 of lower resistance rises. Therefore, the metal silicide is flocculated when heated to high temperature, about over 800xc2x0 C., and the metal silicide is disadvantageously broken.
The Third Problem
To suppress the short-channel effect, there is a tendency of forming the extension regions 110 shallower in the upper surface of the silicon substrate 101. When the extension regions 110 are formed shallower, however, the sheet resistance becomes higher and accordingly the current driving capability of the MOSFET is disadvantageously deteriorated.
The present invention is directed to a method of manufacturing a semiconductor device. According to a first aspect of the present invention, the method of manufacturing a semiconductor device comprises the steps of: (a) preparing a semiconductor substrate; (b) forming a semiconductor film of amorphous substance on a main surface of the semiconductor substrate with an insulating film interposed therebetween; (c) introducing an impurity for lowering resistance into the semiconductor film; (d) introducing hydrogen ions or deuterium ions into the semiconductor film; (e) performing a heat treatment to polycrystallize the amorphous substance after the step (d); and (f) patterning the semiconductor film to form a gate electrode on the main surface of the semiconductor substrate with a gate insulating film interposed therebetween.
According to a second aspect of the present invention, in the method of manufacturing a semiconductor device of the first aspect further comprises the steps of: (g) selectively forming an isolation insulating film in the main surface of the semiconductor substrate; (h) introducing hydrogen ions or deuterium ions into the semiconductor substrate; (i) forming source/drain regions which are paired with the gate electrode interposed therebetween in the main surface of the semiconductor substrate within an element formation region defined by the isolation insulating film; and (j) forming metal-semiconductor compound layers on the source/drain regions.
According to a third aspect of the present invention, in the method of manufacturing a semiconductor device of the second aspect, the steps (d) and (h) are performed in the same process after the step (f).
According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device of any one of the first to third aspects further comprises the steps of: (k) forming extension regions which are paired with the gate electrode interposed therebetween in the main surface of the semiconductor substrate; and (l) forming semiconductor layers in which an impurity for lowering resistance is introduced on the extension regions.
According to a fifth aspect of the present invention, the method of manufacturing a semiconductor device comprises the steps of: (a) preparing a semiconductor substrate; (b) selectively forming an isolation insulating film in a main surface of the semiconductor substrate; (c) selectively forming a gate electrode on the main surface of the semiconductor substrate with a gate insulating film interposed therebetween within an element formation region defined by the isolation insulating film; (d) introducing hydrogen ions or deuterium ions into the semiconductor substrate; (e) forming source/drain regions which are paired with the gate electrode interposed therebetween in the main surface of the semiconductor substrate within the element formation region; and (f) forming metal-semiconductor compound layers on the source/drain regions.
According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device of the fifth aspect, the hydrogen ions or the deuterium ions are introduced at least in the vicinity of a corner defined by a bottom surface and a side surface of the isolation insulating film in the step (d).
According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor device of the fifth aspect, the hydrogen ions or the deuterium ions are introduced at least in the vicinity of a corner defined by a side surface of the isolation insulating film and the main surface of the semiconductor substrate in the step (d).
According to an eighth aspect of the present invention, in the method of manufacturing a semiconductor device of the fifth aspect, the hydrogen ions or the deuterium ions are introduced in the main surface of the semiconductor substrate at least in the vicinity of an end portion of the gate electrode in the step (d).
According to a ninth aspect of the present invention, in the method of manufacturing a semiconductor device of any one of the fifth to eighth aspects, the step (f) has the steps of (f-1) forming metal films on the source/drain regions; and (f-2) performing a heat treatment to react the metal films with the source/drain regions, and wherein the heat treatment in the step (f-2) is performed under a hydrogen atmosphere or a deuterium atmosphere.
According to a tenth aspect of the present invention, the method of manufacturing a semiconductor device comprises the steps of: (a) preparing a semiconductor substrate; (b) selectively forming a gate structure on a main surface of the semiconductor substrate; (c) forming extension regions which are paired with the gate structure interposed therebetween in the main surface of the semiconductor substrate; and (d) forming semiconductor layers in which an impurity for lowering resistance is introduced on the extension regions.
According to an eleventh aspect of the present invention, in the method of manufacturing a semiconductor device of the tenth aspect further comprises the steps of: (e) introducing hydrogen ions or deuterium ions into the semiconductor layers; and (f) forming metal-semiconductor compound layers on the semiconductor layers after the step (e).
According to a twelfth aspect of the present invention, in the method of manufacturing a semiconductor device of the tenth or eleventh aspect further comprises the steps of: (g) forming sidewalls in contact with side surfaces of the gate structure after the step (d); and (h) ion-implanting an impurity into the semiconductor substrate with the gate structure and the sidewalls used as an implantation mask to form source/drain regions.
The present invention is also directed to a semiconductor device. According to a thirteenth aspect of the present invention, the semiconductor device comprises a semiconductor substrate; and a gate electrode of polycrystalline substance in which an impurity for lowering resistance is introduced, being selectively formed on a main surface of the semiconductor substrate with a gate insulating film interposed therebetween, and in the semiconductor device of the thirteenth aspect, the gate electrode includes a granular grain layer having a grain boundary not extending along a direction of film thickness of the gate electrode.
According to a fourteenth aspect of the present invention, the semiconductor device of the thirteenth aspect further comprises an isolation insulating film selectively formed in the main surface of the semiconductor substrate; a diffusion layer in which hydrogen or deuterium is diffused, being selectively formed in the semiconductor substrate; source/drain regions which are paired with the gate electrode interposed therebetween, being formed in the main surface of the semiconductor substrate within an element formation region defined by the isolation insulating film; and metal-semiconductor compound layers formed on the source/drain regions.
According to a fifteenth aspect of the present invention, the semiconductor device of the thirteenth or fourteenth aspect further comprises extension regions which are paired with the gate electrode interposed therebetween, being formed in the main surface of the semiconductor substrate; and semiconductor layers in which an impurity for lowering resistance is introduced, being formed on the extension regions.
According to a sixteenth aspect of the present invention, the semiconductor device comprises a semiconductor substrate; an isolation insulating film selectively formed in a main surface of the semiconductor substrate; a gate electrode selectively formed in the main surface of the semiconductor substrate with the gate insulating film interposed therebetween within an element formation region defined by the isolation insulating film; a diffusion layer in which hydrogen or deuterium is diffused, being selectively formed in the semiconductor substrate; source/drain regions which are paired with the gate electrode interposed therebetween, being formed in the main surface of the semiconductor substrate within the element formation region; and metal-semiconductor compound layers formed on the source/drain regions.
According to a seventeenth aspect of the present invention, in the semiconductor device of the sixteenth aspect, the diffusion layer is formed at least in the vicinity of a corner defined by a bottom surface and a side surface of the isolation insulating film.
According to an eighteenth aspect of the present invention, in the semiconductor device of the sixteenth aspect, the diffusion layer is formed at least in the vicinity of a corner defined by a side surface of the isolation insulating film and the main surface of the semiconductor substrate.
According to a nineteenth aspect of the present invention, in the semiconductor device of the sixteenth aspect, the diffusion layer is formed in the main surface of the semiconductor substrate at least in the vicinity of an end portion of the gate electrode.
According to a twentieth aspect of the present invention, the semiconductor device comprises a semiconductor substrate; a gate structure selectively formed in a main surface of the semiconductor substrate; extension regions which are paired with the gate structure interposed therebetween, being formed in the main surface of the semiconductor substrate; and semiconductor layers in which an impurity for lowering resistance is introduced, being formed on the extension regions.
According to a twenty-first aspect of the present invention, the semiconductor device of the twentieth aspect further comprises diffusion layers in which hydrogen or deuterium is diffused, being formed in the semiconductor layers; and metal-semiconductor compound layers formed on the semiconductor layers.
According to a twenty-second aspect of the present invention, the semiconductor device of the twentieth or twenty-first aspect further comprises sidewalls in contact with side surfaces of the gate structure, being formed on the semiconductor layers; and source/drain regions formed in a portion of the semiconductor substrate where neither the gate structure nor the sidewalls are formed.
In the method of the first aspect of the present invention, by introducing the hydrogen ions or the deuterium ions into the semiconductor film, a polycrystalline film at least partially having a granular grain layer can be formed through the heat treatment in the later step. The granular grain layer has a lot of grain boundaries extending multidirectionally, including a grain boundary not extending along the direction of film thickness of the polycrystalline film. Accordingly, the dopant introduced into the polycrystalline film is diffused multidirectionally along a lot of multidirectionally-extending grain boundaries in the granular grain layer. Therefore, the amount of dopant reaching an interface between the gate electrode and the gate insulating film can be reduced. As a result, it is possible to appropriately suppress variation in threshold voltage which is caused by the penetration of dopant, without lowering the impurity concentration in the gate electrode.
Further, when impurities such as oxygen, carbon and fluorine are mixed into the gate, by performing a heat treatment, these impurities are coupled to the hydrogen atoms or the deuterium atoms introduced into the gate, volatilizing, and thus the impurities can be removed from the gate. As a result, it is possible to suppress an increase in resistance of the gate electrode.
The method of the second aspect of the present invention can produce an effect of freeing up a distorted bond of the semiconductor atoms in a region where a stress is concentrated. This method also produces an effect of removing an impurity mixed into the source/drain regions with the hydrogen atoms or the deuterium atoms. Further, this method produces an effect of suppressing generation of an intruding portion of the metal-semiconductor compound layer in the vicinity of a portion below the gate insulating film or in the vicinity of an interface between the isolation insulating film and the semiconductor substrate. Furthermore, this method produces an effect of removing a native oxide film formed on the source/drain region with the hydrogen ions or the deuterium ions.
In the method of the third aspect of the present invention, since the step of introducing the hydrogen ions or the deuterium ions into the semiconductor film and the step of introducing the hydrogen ions or the deuterium ions into the semiconductor substrate are performed in the same process, a manufacturing process can be simplified as compared with a case where these steps are performed in different processes.
In the method of the fourth aspect of the present invention, since the semiconductor layer in which the impurity is introduced is formed on the extension region, it is possible to suppress an increase in sheet resistance of the extension region with the semiconductor layer of low resistance even when the extension region is formed shallower in the semiconductor substrate in order to suppress the short-channel effect.
In the method of the fifth aspect of the present invention, as the first effect, a bond of semiconductor atoms in the semiconductor substrate by the heat treatment and the semiconductor atoms are diffused so as to relieve a stress. At that time, the hydrogen atoms or the deuterium atoms introduced into the semiconductor substrate are coupled to some of the semiconductor atoms, to terminate an unsaturated bond. As a result, the distorted bond of the semiconductor atoms is freed up in a region where the stress is concentrated (in the vicinity of the corner defined by the bottom surface and the side surface of the isolation insulating film, in the vicinity of the corner defined by the side surface of the isolation insulating film and the upper surface of the semiconductor substrate and in the vicinity of the end portion of the gate electrode).
As the second effect, even when impurities such as oxygen, carbon and fluorine are mixed into the source/drain regions, by performing a heat treatment, the hydrogen atoms or the deuterium atoms introduced into the semiconductor substrate are coupled to these impurities, volatilizing, and thus the above impurities can be removed from the semiconductor substrate.
As the third effect, a hydrogen diffusion layer or a deuterium diffusion layer is formed in the vicinity of a portion below the gate insulating film and in the vicinity of the interface between the isolation insulating film and the semiconductor substrate. Since the silicidation reaction is suppressed in these regions as compared with other regions, it is possible to suppress generation of the intruding portion of the metal-semiconductor compound layer.
As the fourth effect, even when the native oxide film is formed on the exposed source/drain regions, the native oxide film is reduced by the hydrogen ions or the deuterium ions introduced into the semiconductor substrate, becoming H2O to volatilize.
For this reason, the native oxide film formed on the source/drain regions can be effectively removed. Therefore, it is possible to reduce the resistance value of the metal-semiconductor compound layer to be formed later on the source/drain regions.
In the method of the sixth aspect of the present invention, a distorted bond of the semiconductor atoms is freed up in a region where a stress is concentrated, specifically, in the vicinity of the corner defined by the bottom surface and the side surface of the isolation insulating film.
In the method of the seventh aspect of the present invention, a distorted bond of the semiconductor atoms is freed up in a region where a stress is concentrated, specifically, in the vicinity of the corner defined by the side surface of the isolation insulating film and the main surface of the semiconductor substrate.
In the method of the eighth aspect of the present invention, a distorted bond of the semiconductor atoms is freed up in a region where a stress is concentrated, specifically, in the vicinity of the end portion of the gate electrode.
In the method of the ninth aspect of the present invention, it is possible to increase the amount of hydrogen or deuterium remaining in the semiconductor substrate, not volatilizing, in the heat treatment.
In the method of the tenth aspect of the present invention, since the semiconductor layer in which the impurity is introduced is formed on the extension region, it is possible to suppress an increase in sheet resistance of the extension region with the semiconductor layer of low resistance even when the extension region is formed shallower in the semiconductor substrate in order to suppress the short-channel effect.
The method of the eleventh aspect of the present invention can produce an effect of freeing up a distorted bond of the semiconductor atoms in a region where a stress is concentrated. This method also produces an effect of removing an impurity mixed into the semiconductor layer with the hydrogen atoms or the deuterium atoms. Further, this method produces an effect of suppressing generation of an intruding portion of the metal-semiconductor compound layer in the vicinity of a portion below the gate insulating film and the like. Furthermore, this method produces an effect of removing a native oxide film formed on the semiconductor layer with the hydrogen ions or the deuterium ions.
In the method of the twelfth aspect of the present invention, by forming the source/drain regions, it is possible to further reduce the sheet resistance of the source and drain and achieve a still higher-speed operation.
In the semiconductor device of the thirteenth aspect of the present invention, the dopant introduced into the gate electrode is diffused multidirectionally along a lot of multidirectionally-extending grain boundaries in the granular grain layer in the process of manufacturing a semiconductor device. Therefore, the amount of dopant reaching the interface between the gate electrode and the gate insulating film can be reduced. As a result, it is possible to achieve a semiconductor device in which variation in threshold voltage which is caused by the penetration of dopant is suppressed.
The fourteenth aspect of the present invention can produce an effect of freeing up a distorted bond of the semiconductor atoms in a region where a stress is concentrated in the process of manufacturing a semiconductor device. This aspect of the present invention also produces an effect of removing an impurity mixed into the source/drain regions with the hydrogen atoms or the deuterium atoms. Further, this aspect of the present invention produces an effect of suppressing generation of an intruding portion of the metal-semiconductor compound layer in the vicinity of a portion below the gate insulating film or in the vicinity of the interface between the isolation insulating film and the semiconductor substrate. Furthermore, this aspect of the present invention produces an effect of removing a native oxide film formed on the source/drain regions with the hydrogen ions or the deuterium ions. Therefore, it is possible to achieve a semiconductor device whose leakage current is reduced.
In the semiconductor device of the fifteenth aspect of the present invention, since the semiconductor layer in which the impurity is introduced is formed on the extension region, it is possible to suppress an increase in sheet resistance of the extension region with the semiconductor layer of low resistance even when the extension region is formed shallower in the semiconductor substrate in order to suppress the short-channel effect.
The sixteenth aspect of the present invention can produce an effect of freeing up a distorted bond of the semiconductor atoms in a region where a stress is concentrated in the process of manufacturing a semiconductor device. This aspect of the present invention also produces an effect of removing an impurity mixed into the source/drain regions with the hydrogen atoms or the deuterium atoms. Further, this aspect of the present invention produces an effect of suppressing generation of an intruding portion of the metal-semiconductor compound layer in the vicinity of a portion below the gate insulating film or in the vicinity of the interface between the isolation insulating film and the semiconductor substrate. Furthermore, this aspect of the present invention produces an effect of removing a native oxide film formed on the source/drain regions with the hydrogen ions or the deuterium ions. Therefore, it is possible to achieve a semiconductor device whose leakage current is reduced.
In the semiconductor device of the seventeenth aspect of the present invention, a distorted bond of the semiconductor atoms is freed up in a region where a stress is concentrated, specifically, in the vicinity of the corner defined by the bottom surface and the side surface of the isolation insulating film.
In the semiconductor device of the eighteenth aspect of the present invention, a distorted bond of the semiconductor atoms is freed up in a region where a stress is concentrated, specifically, in the vicinity of the corner defined by the side surface of the isolation insulating film and the main surface of the semiconductor substrate.
In the semiconductor device of the nineteenth aspect of the present invention, a distorted bond of the semiconductor atoms is freed up in a region where a stress is concentrated, specifically, in the vicinity of the end portion of the gate electrode.
In the semiconductor device of the twentieth aspect of the present invention, since the semiconductor layer in which the impurity is introduced is formed on the extension region, it is possible to suppress an increase in sheet resistance of the extension region with the semiconductor layer of low resistance even when the extension region is formed shallower in the semiconductor substrate in order to suppress the short-channel effect.
The twenty-first aspect of the present invention can produce an effect of freeing up a distorted bond of the semiconductor atoms in a region where a stress is concentrated. This aspect of the present invention also produces an effect of removing an impurity mixed into the semiconductor layer with the hydrogen atoms or the deuterium atoms. Further, this aspect of the present invention produces an effect of suppressing generation of an intruding portion of the metal-semiconductor compound layer in the vicinity of a portion below the gate insulating film and the like. Furthermore, this aspect of the present invention produces an effect of removing a native oxide film formed on the semiconductor layer with the hydrogen ions or the deuterium ions. Therefore, it is possible to achieve a semiconductor device whose leakage current is reduced.
In the semiconductor device of the twenty-second aspect of the present invention, by forming the source/drain regions, it is possible to further reduce the sheet resistance of the source and drain and achieve a still higher-speed operation.
A first object of the present invention is to provide a method of manufacturing a semiconductor device and a structure of the semiconductor device, which can appropriately suppress variation in threshold voltage which is caused by the penetration of dopant without lowering an impurity concentration in a gate electrode. A second object of the present invention is to provide a method of manufacturing a semiconductor device and a structure of the semiconductor device, which can reduce leakage currents at gate, source and drain by avoiding generation of the intruding portion of a metal silicide at an interface between an offset film of the gate electrode and a silicon substrate or an interface between an STI and the silicon substrate. A third object of the present invention is to provide a method of manufacturing a semiconductor device and a structure of the semiconductor device, which can improve the current driving capability of a MOSFET by suppressing an increase in sheet resistance of an extension region even when the extension region is formed shallower in the silicon substrate.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

Method of manufacturing semiconductor device


The line cutter suitable for fitting to the body of a fishing rod is made as a single piece obtained by cutting out and stamping a metal plate. It comprises firstly a main body with a front portion, a rear portion, and two side portions, and secondly two longitudinal prongs extending the side portions of the main body rearwards. The plate is cut out and stamped in such a manner that, when the line cutter is mounted on the body of the fishing rod, the longitudinal prongs and at least the front portion of the main body are in contact with the body of the fishing rod, the rear portion of the main body being raised so as to allow the line to be pass thereunder, and in such a manner that between the rear portion of the main body and the longitudinal prongs, a cutout in the shape of an acute angle on one side defines a cutting zone, while on the other side there is provided a jamming zone for jamming the fishing line. The line cutter is secured to the body of the fishing rod by binding the longitudinal prongs to said body.

A line cutter suitable for fitting to the body of a fishing rod is known from U.S. Pat. No. 4,730,409. That accessory comprises a cutter blade that is sandwiched between two plates that are fixed to each other. One of the two plates is secured to an open semicylindrical part for enabling the accessory to be fitted on the body of the fishing rod by receiving it. Access to the cutter blade takes place via a notch formed in the two assembled-together plates. On either side of the notch, the plates are curved towards the inside of the notch, thereby enabling the fish hook to be held temporarily.
That accessory nevertheless presents drawbacks. The two assembled-together plates and the blade are mounted radially relative to the body of the fishing rod and can thus occupy space greater than the diameter of said body. This can be awkward for the user. Manufacture is necessarily complex, requiring several parts to be made and then assembled together. In addition, when it comes to cutting a fishing line, as shown in FIG. 6 of that document, it requires the user to establish the tension needed for cutting by holding the fishing line in both hands.

Fishing accessory, in particular a line cutter


A corrosion protecting film layer is formed on a non-passivating non-noble metal, such as cobalt, by placing the metal in a dilute solution of Cu.sup.+2 ions and benzotriazole (1 H-BTA). Exposure of the metal to a solution containing Cu.sup.+2 and 1 H-BTA results in a spontaneous interaction of Cu.sup.+2 and the metal to produce a film layer of Cu(I) BTA on the metal surface to create a permanent corrosion protection for the metal. A borate buffer, such as boric acid and a borate, can be added to the solution to adjust the pH of the solution to be in the range between 8 and 9.

The present invention relates to corrosion inhibition and particularly to the formation of a thin film of Cu(I)-BTA for inhibiting corrosion of non-passivating, non-noble metals.
Corrosion is a spontaneous process and a ubiquitous problem for all but a few noble metals. Cobalt is particularly susceptible to corrosion. While cobalt forms a marginally protective passive layer in alkaline solutions, nevertheless corrosion occurs at a rate of 0.2 .mu.m/day in DI water with no evidence of passivation. Moreover, cobalt is a non-noble metal and is thus very susceptible to galvanic attack when in contact with other, more noble, metals. Cobalt and its alloys are widely used in magnetic applications due to its exceptional magnetic properties. For example, thin film magnetic disks and thin film inductive magnetic recording heads may be fabricated from cobalt alloys. These products are particularly intolerant of any corrosion loss, both in fabrication and in use.
While there are various known passivation techniques, few are effective at reducing the corrosion rate of cobalt by significant amounts. An important consideration is that any protection technique have no adverse effect upon the magnetic properties of the material. For example, alloying the non-noble metal with an element such as chromium, thermal oxidation methods or the application of conversion layers are all possible methods of passivating non-noble metals. However, each of these methods has undesirable limitations. It is also possible to control unwanted metallic dissolution in fabrication steps where cobalt or its alloys are in contact with process solutions by the use of corrosion inhibitors. However, many corrosion inhibitors offer only a limited protection of a cobalt workpiece in situ, and even less protection after the workpiece is removed from the environment containing the corrosion inhibitor.
Copper, for example, is a more noble metal than cobalt but has an oxide that is an equally marginal surface passivator. Copper is a viable engineering material, largely as a result of the very effective corrosion inhibiting effect provided by benzotriazole (1 H-BTA) and its derivatives. The 1 H-BTA compound reacts with a metallic Cu surface to form a Cu-BTA film. Depending upon the details of the preparation, the film can be as thin as 2 nm thick. Even such a thin film provides effective corrosion inhibiting effect. Once formed, the thin film reduces the corrosion rate of copper in water (with or without the addition of a corrosion inhibitor) by more than two orders of magnitude.
There is no comparably effective inhibitor known in the art for use with cobalt workpieces. In aqueous solutions, benzotriazole chemisorbs on the surface of the cobalt and reduces the corrosion rate by only one order of magnitude. However, when the cobalt workpiece is then placed in a solution devoid of 1 BTA, the corrosion rate is reduced to only 3 to 5 times less than that of a cobalt workpiece not previously exposed to 1 BTA.

International Business Machines Corporation


A fixing roller in an image forming apparatus (such as a copier) has a fixing heater that is supplied power from a capacitor. The fixing heater, the capacitor, a mechanical switch (such as a relay) and a semiconductor switch (such as a FET) are serially connected. As a cover of the apparatus is opened, an interlock switch is turned on and outputs an off-signal to a CPU, which turns off the semiconductor switch prior to turning off the mechanical switch, and thereby prevents a counter-electromotive voltage due to an inrush current.

1) Field of the Invention
The present invention relates to a method for controlling power supply to prevent counter-electromotive voltage due to an inrush current passing through a fixing heater embedded in a fixing roller of an image forming apparatus, such as a digital copying machine.
2) Description of the Related Art
Japanese Patent Application Laid Open (JP-A) No. 2002-184554, JP-A No. 2003-295659, and JP-A No. 2003-297526 disclose technology for a heating element (fixing heater) of a fixing device used in an electrophotographic image forming apparatus. This technology is such that in addition to a power supply from a commercial power supply, a chargeable auxiliary power supply using an electric double layer capacitor is used to allow fast rising of temperature and thereby enhance effects of power saving.
In the conventional technology, however, if power is supplied from a capacitor to the heating element when the heating element is not heated, a large inrush current passes through the heating element, and counter-electromotive force may occur caused by an inductance component of the heating element. A circuit may be broken by voltage breakdown. To solve such inconvenience, it is desirable to use both a semiconductor switch and a mechanical switch as a switching element for controlling on/off of discharging from the capacitor to the heating element.

Method for controlling power supply to fixing roller in image forming apparatus


A liquid crystal alignment treating agent for optical alignment treatment, whereby it is possible to obtain a liquid crystal alignment film which presents a high and stable tilt angle of liquid crystal and which is excellent in an accumulated charge property by a DC voltage, is provided.

Presently, as a liquid crystal alignment film for a liquid crystal display device, a rubbing alignment film obtained by rubbing a polyimide resin film is commonly employed. However, by such alignment treatment by a rubbing method, it is difficult to treat a large area uniformly, and fine dust or scratches on the alignment film surface formed by rubbing tend to cause deterioration of the characteristics of the liquid crystal device. As a substitute for the rubbing alignment film, an optical alignment film obtainable by irradiating an organic film with polarized UV rays or the like is being strenuously studied.
As fundamental properties required for the liquid crystal alignment film, it may firstly be mentioned that liquid crystal molecules be aligned uniformly, and an optionally set tilt angle be maintained stably. Further, it will also be important that when it is employed in a liquid crystal device, the voltage retention ratio be high, and the accumulation charge by a DC voltage be low. It is known that such properties are substantially influenced by the composition or molecular structure of the liquid crystal alignment film, and various methods have heretofore been studied for the rubbing alignment film. For example, as a method to increase the tilt angle of liquid crystal molecules in a rubbing alignment film, a method of introducing a long chain alkyl group or a fluoroalkyl group to a side chain of polyimide is known (JP-A-2-282726). Further, as a method to improve the properties such as the voltage retention ratio or the accumulation charge by means of a rubbing alignment film, a method of adding an acryl additive to a polymer alignment film has been proposed (JP-A-6-202118).
On the other hand, an optical alignment film is regarded as a prospective substitute for the rubbing alignment film. However, an optical alignment film fully satisfying the same properties as the rubbing film has not yet been found. Particularly, with respect to the alignment regulating power or the stability for liquid crystal, there are many problems yet to be solved.
The present invention has been made in view of the above-mentioned problems and has an object to provide a liquid crystal alignment treating agent whereby it is possible to obtain a liquid crystal alignment film which presents a high and stable tilt angle of liquid crystal when employed as an optical alignment film, and which is excellent in the charge accumulation property by a DC voltage.

Liquid crystal aligning agent, liquid crystal aligning films, and liquid crystal display devices

Abstract: A liquid crystal alignment treating agent which comprises, as resin components, a polyimide precursor or a polyimide obtained by cyclodehydration of the polyimide precursor, and an acryl polymer having repeating units represented by the formula (II):

Abstract: (wherein R3 represents a hydrogen atom, a methyl group or a halogen atom, R4 represents an alkyl group having at least 8 carbon atoms, and k represents a positive represented by the formula (III):

Abstract: (wherein R3 and R5 each independently represents a hydrogen atom, a methyl group or a halogen atom, R4 represents an alkyl group having at least 8 carbon atoms, R6 represents an organic group having an epoxy group, and k and j each represents a positive integer), wherein the acryl polymer having the repeating units represented by the formula (II) or the formula (III) is from 0.01 to 30 wt % based on the whole resin components.


A pet enclosure and waste tray system includes a rectilinear cage, an detachably integrated waste pan removably attached to the bottom portion of the cage, a molded waste tray into which the combination cage and waste pan may be nested, and a dolly upon which the waste tray securely fits. The rectilinear cage has a movable rectilinear section capable of being swung up and away from the cage to facilitate removal of enclosed pets. Nesting material may be introduced into the waste pan which supports and is spaced from the bottom portion of the cage. Due to the proximity of the waste pan to the wire mesh of the bottom of the cage, the nesting material penetrates the cage for the occupant's use. A continuous shoulder along the inside of the waste tray is dimensioned such that the cage is supported by the shoulder when nested within the waste tray. The waste tray has a downwardly curled upper lip receivable on railings extending upward from the dolly to securely support the tray-pan-cage combination. During cleaning of the waste pan, the cage without the nesting material and pan may be securely placed within the waste tray, which can then be easily cleaned. The interior edges below the internal shoulder of the waste tray are smoothly and gradually curved to facilitate cleaning.

Rectangular wire cages are a favorite among pet owners because they are relatively easy to clean and permit a high degree of visibility of and for the cage occupant. Waste from the enclosed pet passes easily through the bottom of a wire cage so that the cage is kept clean, and various types of feeding and amusement devices may be easily affixed to the inside of the cage.
Most animal cages have a sliding or swing door permitting ingress and egress of the enclosed animal. Typically, the wire doors are small relative to the overall size of the cage, making it difficult to access the animal within the enclosure. Removal of the animal from the cage becomes an opportunity for the animal to be injured if the animal thrashes about while attempting its extraction or while attempting to place it within the cage.
Most pet cages include a waste tray which is permanently incorporated into the bottom of the animal cage or, alternatively, the cage is without an integral tray and the animal waste simply passes through the cage interstices onto a waste platform, such as newspaper or other absorbent material. However, most animals prefer to have nesting material for sleeping, resting, and rearing of young. The presence of nesting material complicates the cleaning procedure of a pet cage. When placed inside a wire cage, nesting material tends to collect the waste material from the enclosed animal forcing the animal owner to periodically extract the animal and thoroughly clean the interior of the cage. Nesting material must be periodically removed to hinder the spread of animal parasites and diseases. Removal of the nesting material and cleaning of the interior of a pet cage is a messy undertaking and presents a potential for injury of the animal or, potentially, the animal's owner.
Therefore, there exists a need for a system waste trays to facilitate the cleaning of a pet enclosure.


A method for creating a snapshot copy of a database object includes creating a mirror of the database on a plurality of volumes. A user may provide a request to create a snapshot of a database object to a database utility. The database utility responds to the snapshot request by providing an indication of selected volumes of the mirror that correspond to the database object to a volume manager. The volume manager then creates a snapshot volume for each of the selected volumes of the mirror.

1. Field of the Invention
This invention relates to database storage systems and, more particularly, to techniques for creating snapshot copies of a database.
2. Description of the Related Art
Many business organizations and governmental entities rely upon large databases, sometimes exceeding a terabyte or many terabytes of data, for mission-critical applications. It is common that many such database applications require near-continuous access. For example, many systems such as retail processing databases, airline reservation databases, and financial institution databases must be available to perform transaction processing 24 hours a day. Downtime associated with such systems can be disastrous.
With the growing amounts of data and shrinking acceptable downtime requirements of modern database systems, organizations are sometimes squeezed by the conflicting demands associated with a database environment. For example, secondary operations such as data backup operations, reporting and analysis, and application testing can be of significant importance. However, such secondary operations can interrupt or encumber the normal transaction processing of a host system running a database application.
To minimize these problems, some systems support snapshot capabilities that allow point-in-time copies of data to be created. By creating snapshots of the appropriate storage devices, a frozen image of the database can be created and can then be used to facilitate the secondary operations. For example, the snapshot copies containing the image can be installed on a secondary host that performs the secondary operations. In this manner, availability of the primary host for normal transaction processing can be maximized.
The creation of snapshot copies can be based on data-mirroring technology implemented by a volume manager running on the host system. In a data mirroring configuration, identical copies of data are stored on different physical storage devices. A volume-level snapshot can be created simply by splitting and detaching a mirror containing an image of the data from the original volume. Once the user has completed use of the snapshot volume split from an original, it may be resynchronized (since continued updates to the original volume may have occurred) by reattaching it to the original. Subsequent snapshots may be taken in a similar manner.
While the volume level snapshot capabilities of a volume manager may be utilized to create a snapshot of a database object, several significant problems can be presented. Firstly, storage is typically managed by system administrators or storage administrators who have root privileges which may be required for invoking the snapshot capabilities of a volume manager. In many organizations, database administrators do not have root privileges. Accordingly, the system administrator and database administrator must typically work together to coordinate the database and its storage when creating a snapshot.
In addition, even if the database administrator were granted root privileges, they often do not have the storage management expertise to effectively utilize the snapshot functionality of the volume manager. Creation of a consistent frozen image for a database, especially large databases that use hundreds of disks, is a complicated process and may be error prone. A single error may render the entire frozen image useless.

System and method for creating a snapshot copy of a database