A method for unifying speech user interface and graphic user interface commands includes the steps of receiving (52) user entered text via a GUI, processing (54) the user-entered text, monitoring (60) the user-entered text, adding input context (62) to the user-entered text, and, updating (74, 76, and 78) a speech recognizer with the user-entered text and semantic information. Updating the speech recognizer can include the step of accepting new text information and input context to update a speech grammar (74) and recognition vocabulary of the speech recognizer. The method can include the step of updating the GUI (72) by updating GUI directives (68) and elements (70) to maintain the GUI unified with the speech grammar. The method can further include the step of forming a window (402) enabling the display of a speech interface command as a user constructs the speech interface command using the GUI (400).

In a device with both a speech user interface (SUI) and a Graphical User Interface (GUI), the user is typically faced with learning separate command sets for each of the SUI and GUI. This increases the difficulty of accurately giving commands, especially for the SUI. In addition, speech commands are difficult to remember since they are transient and there is no persistent display of them to help the user remember. Existing systems fail to provide a mechanism to unify the command sets of the GUI and SUI so that the user need only learn a single instance of many of the commands to use in both interfaces.
U.S. Pat. No. 6,075,534 and others describe methods for displaying a dynamically changing menu to control and provide feedback on the operation of the speech recognizer in a GUI. However, no reference can be found that ensures that the GUI menus and dialog box elements are constructed in such a way that by selecting them the user essentially builds the corresponding speech command for an application.

Method and system for unified speech and graphic user interfaces


An apparatus for clustering a point cloud can include: a three-dimensional (3D) light detection and ranging (LiDAR) sensor configured to generate a point cloud around a vehicle and a controller configured to project the point cloud generated by the 3D LiDAR sensor onto a circular grid map to be converted into two-dimensional (2D) points, the circular grid map including a plurality of cells, and to cluster the 2D points on the circular grid map.

In general, a point cloud refers to a set of data on a coordinate system. The point cloud is defined as x-, y-, and z-coordinates in a three-dimensional (3D) coordinate system and typically indicates an external surface of an object.
Such a point cloud may be generated by a 3D light detecting and ranging (LiDAR) sensor. Many modern vehicles are equipped with a 3D LiDAR sensor for detecting surrounding vehicles, lanes, and various obstructions.
Because the 3D LiDAR sensor generates a large number of point clouds in the area surrounding the vehicle, there is a need for efficient clustering technologies. A conventional technology for clustering point clouds projects a point cloud (3D points) onto a two-dimensional (2D)-shaped square grid map to be converted into 2D points. The converted 2D points are then clustered on the square grid map using the "8-neighborhood" technique.
However, when the conventional point cloud clustering technique sets a cell on the square grip map to a large size, points indicating different objects located in a short range are clustered as one. Conversely, when the conventional point cloud clustering technique sets a cell on the square grip map to a small size, points indicating one object located in a long range are separately clustered upon clustering.
As a result, it is difficult to optimally cluster all points indicating a long-range object and all points indicating a short-range object.

Apparatus and method for clustering point cloud


The invention relates to a unit for synchronous extension and retraction of two wire segments that are wound onto a storage spool in such a way that upon a rotary motion of the storage spool in one rotation direction, both wire segments are synchronously unwound, and upon a rotary motion of the storage spool in the other rotation direction they are synchronously rewound, the wire segments being separated from one another and being fastened at their storage-spool ends to the storage spool, the storage spool comprising a catch that is effective in that rotation direction in which the wire segments are unwound from the storage spool, and is releasable via an actuation device. The invention furthermore relates to a motor vehicle using such a unit.

Motor vehicles that comprise a rear access panel that is guided at the bottom in hinges, by way of which it can be pivoted out of a substantially vertical closed position into a horizontal open position, are known in the existing art. In the open position, the rear access panel surface that is then at the top lies flush with the floor of the rear compartment of the vehicle.
In order to limit the pivoting angle of the rear access panel, wire segments that are attached with their free ends in the upper region of the vehicle's body are provided on both sides of the rear access panel. "Wire segments" are also to be understood here as those segments that constitute, for example, cables or other flexible (and thus windable) strands. The wire segments run through openings in the upper corners of the rear access panel to a storage spool arranged centeredly in the interior of the rear access panel. Upon opening of the rear access panel, the wire segments unwind from the storage spool synchronously and at the same speed, until the open position of the rear access panel is reached. The storage spool locks when that position is reached, with the consequence that the rear access panel cannot be pivoted any farther downward.
In the existing art, the two wire segments are part of a single, continuous length of wire that is wound in coiled fashion around the storage spool in such a way that the two wire segments are synchronously unwound in the context of a rotary motion of the storage spool in one rotation direction, i.e. in the case of opening of the rear access panel, and are synchronously rewound in the context of a rotary motion of the storage spool in the other rotation direction, i.e. in the case of closing of the rear access panel. A spring return system ensures that the two wire segments remain tensioned in every position of the rear access panel, and opening of the rear access panel occurs against the action of the spring return system.
The fact that the wire segments are parts of one continuous length of wire makes installation of the length of wire complex and labor-intensive. In addition, it is necessary for the length of wire to be accurately adjusted on the storage spool so that the extended wire segments are always of the same length. The danger nevertheless always exists that the length of wire will slip on the storage spool, with the consequence that the wire segments to be extended and retracted become unequal in length. Damage to the rear access panel can result therefrom.
U.S. Pat. No. 5,531,498 discloses an actuation device for an upwardly openable rear access panel. The actuation device has gas springs, provided on both sides, which are designed with sufficient strength that upon opening, the rear access panel pivots completely into a pivoted-up final position solely as a result of the gas springs. Also associated with the actuation device is a closing device by means of which the rear access panel can be pivoted back downward into its closed position. The closing device comprises two wire segments whose free ends are fastened on the body of the motor vehicle and extend to a storage spool arranged on the rear access panel. There the wire segments are wound on in such a way that upon a rotary motion of the storage spool in one rotation direction, both wire segments are synchronously unwound, and upon a rotary motion of the storage spool in the other rotation direction they are synchronously rewound. The storage spool is driven by an electric motor that is activated when the rear access panel is to be closed. The storage spool is then rotated in such a way that the wire segments are rewound onto it.
The wire segments are not part of a continuous wire, but rather are separate from one another and are fastened with their storage-spool ends on the storage spool by means of enlarged ends engaging into corresponding recesses. Such storage spools are also known from DE 197 41 691 A1.

Unit for synchronous extension and retraction of two wire segments, and a motor vehicle having such a unit


A suspension system for a vehicle includes a roll control device, which includes an actuator, for controlling roll, and a control device including a target control value determining portion determining target control value of the actuator and an operation control portion controlling the actuator on the basis of the target control value. The target control value determining portion determines the target control value on the basis of estimated lateral acceleration when degree of actual lateral acceleration is smaller than a predetermined threshold, and by weighting the estimated lateral acceleration to gradually decrease from one to zero and by weighting the actual lateral acceleration to gradually increase from zero to one when the actual lateral acceleration is greater than the predetermined threshold, the target control value determining portion determines the target control value of the actuator on the basis of the sum of the weighted estimated lateral acceleration and the weighted actual lateral acceleration.

Known suspension systems including a roll control device, and controls of the suspension systems are described in JPH05 (1993)-50819A, JPH05 (1993)-16633A, JPH04 (1992)-166408A. According to the known suspension systems including the roll control device, a control value of the roll control device is determined using actual lateral acceleration which is actually generated lateral acceleration at a vehicle body, and estimated lateral acceleration which is estimated on the basis of vehicle traveling speed and a degree of steering.
According to the known suspension systems, gains of the actual lateral acceleration and the estimated lateral acceleration are varied on the basis of vehicle traveling speed and steering speed, or the like, for determining the control value in order to perform a control based on the estimated lateral acceleration in addition to a control based on the actual lateral acceleration in view of delay of control at initial stage of turning movement of the vehicle, swing back when returning a steering operation member, and excessive slip during the turning movement of the vehicle, or the like. Lateral acceleration is generated not only when a vehicle is turning, but also when a vehicle travels on a rough road even if the vehicle travels straight. Thus, it is desired to avoid the influence of the lateral acceleration when controlling the roll control device. With the foregoing known suspension systems, the aforementioned influence of the lateral acceleration is not considered, and in a practical use, the known suspension systems leave room for improvement.
A need thus exists for a suspension system for a vehicle including a roll control device, which can avoid influence of relatively small degree of lateral acceleration which is not caused by turning movement of the vehicle.


A camera is provided with an image blur reducing function and rotation means. The image blur reducing function is turned off during rotation in a constant-speed drive pattern in which the rotation means rotates the camera at a constant speed from a start to an end of the rotation operation. The image blur reducing function is turned on during rotation in an intermittent drive pattern in which the rotation means intermittently executes drive operation from the start to the end of the rotation operation.

1. Field of the Invention
The present invention relates to a camera equipped with a camera platform (pan/tilt head) and its control method.
2. Description of the Related Art
Japanese Patent Application Laid-Open No. 2001-358982 discusses a technique for reducing or stopping a vibration-reducing function during panning in a typical video camera since if the vibration-reducing function is operated, an image blur is increased or decreased, thereby making an image appear unnatural.
Japanese Patent Application Laid-Open No. 2001-155347 discusses an image blur prevention apparatus that locks a vibration-reducing lens during a pan and tilt operation of a camera which does not need an image blur correction.
Generally, at a moment a camera stops a special high-speed rotation, the camera reciprocally vibrates in the direction of rotation. In the above-described conventional techniques, this vibration is not considered.
For example, in an intermittent rotation in which a camera repeatedly starts and stops rotating, the camera continuously vibrates. Thus, an image to be captured will blur. In this case, during rotation of a camera rotation unit, a vibration-reducing function can reduce the blur of an image to be captured.

Camera having an image blur reducing function and rotation means


An information processing apparatus includes a display control unit that controls display of selection objects related to devices to be operated, which have been selected through first device selection based on information from which a form of a body of an operation subject directed to the devices to be operated is estimated and a device control unit that controls the devices to be operated, which have been selected through second device selection based on information related to a selecting operation performed by the operation subject to the selection objects.

In recent years, a variety of interfaces for controlling devices have been researched and developed with the development of information communication technologies. There are roughly two types of interface as such interfaces. One is a first interface in a form in which a user operates an operation target device in contact with or in proximity to the operation target device. The other is a second interface in a form in which a user operates an operation target device in a remote manner. According to the first interface, the device is controlled by a user's touching operation, button pressing operation, or the like, for example. Meanwhile, according to the second interface, the device is controlled by a user's gesture operation, remote controller operation, or the like, for example.
For example, an invention related to an information input apparatus that provides a user interface in accordance with a distance between a user and an input device is disclosed in Patent Literature 1. For example, a touch operation performed to a touch panel is provided for a short distance, a gesture operation is provided for an intermediate distance, and an operation using a remote controller is provided for a long distance.

This patent is subject to a terminal disclaimer.

Information processing apparatus and information processing method to reduce user burden


A system and method for authenticating a multi-sided die by viewing the die under invisible ultraviolet light. A die body has a plurality of sides of substantially equal area. A plurality of visible markings for indicating a roll of the die are disposed on the die sides. One or more of the markings include a substance which visibly reacts with invisible ultraviolet light. One or more authentication marks including a substance which visibly reacts with invisible ultraviolet light are arranged in a selected pattern on one or more of the die sides. A position of the authentication mark or marks in the selected pattern corresponds to the visible marking having a substance which visibly reacts with invisible ultraviolet light. An overlay key correlates the position of the authentication mark with the visible marking.

1. Field of the Invention
The invention relates to multi-sided die used in games of chance. More particularly, the invention relates to a system for verifying the authenticity of a multi-sided die which is provided with distinguishing characteristics not readily apparent upon ordinary observation. The invention further relates to a method for authenticating such a die.
2. The Prior Art
Multi-sided die or dice are commonly used in games of chance. A die typically comprises a lightweight multi-sided rigid article which is easily shaken, rolled, tossed, thrown or otherwise set into rotational motion by a player. Each side of a die is provided with a visual marking, for example one or more dots or numerals. The visual marking which faces directly up after the die has been set into rotational motion and has come to rest is the result of that throw or roll. A multi-sided die comprising twenty sides is known from U.S. Pat. No. 5,909,874 entitled "Icosahedron Decimal Dice."
When die are used in gambling or wagering, a result of a roll of a die or dice may determine an exchange of money or chips. Accordingly, substantial efforts are made to assure that die used for such purposes are balanced and otherwise adapted to provide an equal chance of rolling any particular result.
A player engaged in a game of chance in which money or chips are exchanged depending on a result of a roll of a die or dice may surreptitiously introduce an altered die or dice into a game in an attempt to skew the odds of obtaining a desired or favorable outcome. Accordingly, there exists a need to assure that a die being used for gambling or wagering purposes is authentic and has not been substituted with a die which is inauthentic and may have been altered to change the probability of rolling any particular result.
It is known to use a source of invisible ultraviolet light, such as a black light, to cause a material or substance including phosphors to react visibly or glow.

Multi-sided die with authenticating characteristics and method for authenticating same


A novel interleukin-1 antagonist active against both IL-1.alpha. and IL-1.beta. and DNA encoding same/re described. Antibodies specific for the novel IL-1 antagonist and prophylatic, therapeutic and diagnostic uses of the IL-1 antagonist in pathologies associated with IL-1 production are also described.

Two distinct genes, designated IL-1.alpha. and IL-1.beta., encode for interleukin-1 (IL-1) proteins IL-l.alpha. and IL-1.beta., respectively.
Interleukin IL-1.alpha. and IL-1.beta. are pleiotropic cytokines, and each, despite little sequence homology between them, exerts a variety of similar effects on different tissues and act on many human pathologies, and particularly on the immune response of the organism and on inflammatory processes. Both proteins have a molecular weight of about 17.5 kDa and are synthesized as a larger precursor molecule having a molecular weight of about 31 kDa.
IL-l proteins are potent inflammatory and pyrogenic cytokines that normally have beneficial effects, but that can also have extremely harmful effects on the organism. For example, IL-1 proteins participate in the pathogenesis of autoimmune pathologies, such as lupus erythematosus, and in particular, they are involved as mediators that provoke damage to tissues, as for example in rheumatoid arthritis.
Many of the biological effects of IL-1 are similar to those observed during sepsis. Recent studies demonstrated that the intravenous administration of IL-1 in a dosage range from 1 to 10 ng/kg gives rise to fever, sleepiness, anorexy, generalized myalgia, arthralgia and cephalea. Since IL-1 has pleiotropic biological activities, many of which negatively influence the organism, the powerful effects of IL-1 should be put under strict physiological control.
The synthesis of IL-proteins is inhibited by anti-inflammatory cytokines, prostaglandins and glucocorticoids and the existence of multiple levels of inhibition of IL-1 points to the necessity for strict control of this mediator. To date, IL-1 is the only cytokine for which an antagonist polypeptide for the receptor has been described; the third known component of the IL-1 family is the antagonist for the IL-1 receptor (IL-1ra).
All three components (IL-l.alpha., IL-1.beta., IL-1ra) recognize and bind to the same receptor on the cell surface (IL-1R); the binding of IL-1.alpha. and IL-1.beta. to IL-1R transmit a signal, whereas the binding of IL-1ra does not. There are two types of IL-1 receptors designated IL-1RI and IL-1RII. IL-1ra is a polypeptide which binds to IL-1RI, and also binds to IL-1RII with less affinity, without any agonistic activity.
IL-lra production is induced in different types of cells, including mononuclear phagocytes, polymorphonuclear cells (PMN) and fibroblasts, by IgG, cytokines and bacterial products. Until now, only two molecular forms of IL-lra have been identified and cloned:
1) secreted IL-lra (sIL-1ra) contains a classical leader sequence of 25 amino acids giving a mature protein of 152 amino acids; PA1 2) intracellular IL-lra (icIL-1ra) lacks a leader sequence and it is predicted that this protein remains intracellular. sIL-1ra and icIL-1ra are generated from the same gene.
The human genes coding for IL-1.alpha. and IL-1.beta. and IL-1ra belongs to the same gene family and are clusterized on chromosome 2 mapping to the q12-q21 region (Eisenberg et al., Proc. Natl. Acad. Sci. USA 88:5232, 1991). The human IL-1ra gene has been partially sequenced and characterized. As shown in FIG. 5, the human IL-1ra gene contains in its 3' region, three exons coding for the C-terminal common part of the three isoforms of IL-1ra (exons 2, 3 and 4 in FIG. 5) and in its 5' region, three exons which can be differentially spliced to generate the three isoforms of the antagonist (exons ic1, ic2 and s1 in FIG. 5). The 3' part of the gene between the promoter of the secreted isoform and the last exon of the gene, as well the region upstream the first intracellular specific exon, have been sequenced (bold line in FIG. 5) (Butcher et al., J. Immunol.153:701, 1994; Lennard et al., Cytokine 4:83, 1992). On the other hand, the part of the gene between the promoter region of sIL-ra and first exon of icIL-1ra was unknown (thin line in FIG. 5).
Transcripts of icIL-1ra1 originate from an alternative starting site and from the splicing of a first alternative exon into an internal splice acceptor site located in the first exon of sIL-lra. The predicted proteins are thus identical except in their NH.sub.2 ends, where the first 21 amino acids of sIL-1ra are substituted by four amino acids in icIL-Ira. The expression of transcripts encoding sIL-lra and icIL-lra is regulated differently, and the biological significance of icIL-lra is still unclear.
Considering that IL-1 is involved in pathogenesis of many diseases, it is evident that there is a need for medicaments which are useful in limiting the harmful effects of IL-1.
Citation of any document herein is not intended as an admission that such document is pertinent prior art, or considered material to the patentability of any claim of the present application. Any statement as to content or a date of any document is based on the information available to applicant at the time of filing and does not constitute an admission as to the correctness of such a statement.

Antibodies to intereleukin-1 antagonists

Applied Research Systems ARS Holding N.V.


An audio control method and audio processing system utilize an ADC to sample an analog audio input signal and convert it to a digital audio signal. A control module determines input signal level from the digital audio signal. Based on different input signal levels, output gain range of the amplifier can be set. In this way, the present invention can prevent speakers being burned out or volume being too low.

1. Field of the Invention
The present invention relates to audio control methods and audio processing systems, and more particularly, to an audio processing system with automatic gain adjustment based on an analog audio input signal.
2. Description of the Prior Art
Please refer to FIG. 1. In a conventional audio processing system 10, speakers 18 produce sounds when an analog audio source signal from an analog audio input source 12 is amplified by an amplifier 14 and the resulting analog audio signal drives the speakers 18. The amplifier 14, according to a control signal from a control device 16, adjusts the gain of the amplifier 14, so as to control the level of the audio signal, such that the speakers 18 can output the sound at different volumes.
However, in the conventional audio processing system 10, the gain range of the amplifier 14 is fixed. Typically, the gain of the amplifier 14 controlled by the control device 16 is set to a middle value of the range in advance. Then, based on audio signals with different signal amplitudes, a user can adjust the volume to an acceptable level via the control device 16. However, because the gain range of the amplifier 14 is fixed, a great deal of inconvenience can be caused if the audio signal is at an extreme signal amplitude. For example, when the audio input signal amplitude is extremely high, and the gain of the amplifier 14 is also set at the upper end of the gain range, the speakers 18 can be overloaded and burn out within just a short period of time. On the other hand, if the audio input signal amplitude is extremely low, even if the gain of the amplifier 14 is set at the highest value of the gain range, the volume at the speakers 18 may still be too low, and will be unable to satisfy the listener. In addition, when the analog audio input source 12 is not inputting an audio source signal, the conventional audio processing system 10 has no way of automatically entering a mute state, but must be manually adjusted by the user.

Audio control method and audio processing system


An information processing system includes a number of database servers deployed onto a number of physical nodes in a distributed manner. Among the database servers, at least two servers taking care of data different from one another are deployed onto the same physical node and at least one server taking care of the same data as any of the at least two servers are deployed onto at least one other physical node. A distribution section distributes connections by monitoring load on each of the physical nodes and moving a connection with a client from a database server on a physical node with load heavier than a target to a database server on a physical node with load lighter than the target so that the connections are distributed to balance the load.

It is desired for an application using a database to improve the database performance and capacity according to the volume of data and the amount of access load. Conventionally, as a technique for improving the scalability of the entire system, there has been known a technique for creating a replica of a database and deploying multiple database servers taking care of all data onto multiple physical nodes in a distributed manner to reduce the load (for example, see Japanese Patent Application Publication No. 2001-175681. There has also been known a technique for dividing the database according to the practical search scope to deploy multiple database servers taking care of the divided partitions, respectively, in a distributed manner. Thus, the databases are deployed onto multiple physical nodes in a distributed manner to create a distributed database environment to enable improvement in transaction performance and availability and fault tolerance of the system.
FIG. 14A is a schematic diagram showing a distributed database environment in a conventional technique. A distributed database environment 500 shown in FIG. 14A includes multiple database servers 510a1 to 510c2 deployed onto multiple physical nodes in a distributed manner. In the distributed database environment 500, database partitioning and partition multiplexing are implemented so that each individual database server 510 will take care of data in a different partition or the same partition. Here, the logical unit of databases managed by a group of database servers 510 taking care of the same partition (e.g., 510a1 and 510a2) is referred to as a distributed database 520 (e.g., 520a). In other words, the distributed database 520 consists of an original database (master) taking care of the same partition and replication database (replica) replicated from the master.
As mentioned above, the database is so divided that the data range taken care of by each individual database server 510 to maintain data consistency can be reduced, and each partition is further multiplexed to distribute these database servers 510 onto multiple physical nodes so that the unit of data taken care of by each individual physical node can be reduced. This can increase the transaction performance, improving the availability and fault tolerance of the system. Further, a replica is created and data is multiplexed as mentioned above so that access load from client applications 530 can be distributed, thus improving the availability and fault tolerance of the system.
In such a distributed computing environment, a technique is generally employed, in which database servers 510 of different distributed databases 520 are combined and deployed onto a physical node 540 as the same physical resource as shown in FIG. 14B to make effective use of limited physical resources. However, when multiple database servers 510 are deployed on the same physical node 540, if access is concentrated to a database server (e.g., database A), the database server (e.g., database A) may place pressure on resources of another database server (e.g., database C′) on the same physical node (e.g., physical node 540a).
In other words, when a configuration is employed in which multiple database servers are deployed onto the same physical node, there arises the problem of a sudden overload or redundant resources. Countermeasures to this problem include a method of adding a replica of a distributed database 520 in which a sudden increase in load has been observed, a method of enhancing the physical node on which the database server 510 with the sudden load increase observed is deployed, and a method of moving the database server 510 onto another physical node having enough resources. However, in an emergency situation, such as a sudden access increasing state, since these operations themselves place heavy load, they would not be adaptive solutions.

Connection distribution for load balancing in a distributed database

International Business Machines Corporation


A carry foreknowledge adder comprise an adding circuit for adding binary numbers A and B of n bits; and a plurality of carry foreknowledge circuit blocks that respectively corresponding to divisional portions obtained by dividing the A and the B through setting a unit length. Each carry foreknowledge circuit block has a plurality of arithmetic operating portions (j, i) in correspondence to each bit, that respectively receive a block carry Cin corresponding to the most significant bit in a lower the carry foreknowledge circuit block from the lower carry foreknowledge circuit block corresponding to lower divisional portion, each arithmetic operating portion arithmetically determining the carry Ci on the basis of the block carry Cin, and outputting the carry Ci to the adding circuit, and each arithmetic operating portion (j, i) has a logic circuit portion which receives the block carry Cin and is arranged on an output terminal side.

1. Field of the Invention
The invention relates to an adder having a carry foreknowledge (carry lookahead) circuit for the purpose of raising a speed of an arithmetic operation and, more particularly, to the improvement for realization of a high speed of an arithmetic operation of a carry foreknowledge circuit.
2. Related Background Art
An adder constructed by a logic circuit is fundamentally an adder of a binary number (1 or 0) of one digit and, in the case of adding an addition number Ai (binary number of one digit) and an adding number Bi (binary number of one digit), when a carry output from one-lower digit is assumed to be a carry input Cin, an addition result Si (binary number of one digit) is shown by the following equation.Si=Ai+Bi+Cin  (1)
In the equation (1) and equations which will be shown hereinbelow, "i" denotes a positive integer such as 0, 1, 2, 3, . . . , shows a current digit number to be arithmetically operated upon, and indicates to which digit of a plurality of digits each of the shown numbers corresponds. A sign "+" shows a logical sum (OR) such as an OR element or the like. Cin denotes the carry output and is also expressed by a binary number of one digit.
Since the addition result Si is expressed by a binary number of one digit and (Ai+Bi+Cin) denotes the OR of three binary numbers, when the addition result Si is outputted, a carry output Ci in the case where a carry occurs is also outputted. The carry output Ci is shown by the following equation.Ci=Ai·Bi+(Ai+Bi)·Cin  (2)
In the equation (2) and equations which will be shown hereinbelow, a sign "." denotes a logical product (AND) such as an AND element or the like.
For example, in a ripple carry adder or the like in which all adders of one digit are serially connected, the adder waits until the carry output (Cin) of a lower digit is arithmetically determined and inputted, and thereafter, arithmetic operations of the addition result Si and the carry output Ci of the upper digit are executed.
A carry foreknowledge circuit is a circuit for checking the generation of the carry output of the lower digit and grasping the carry output corresponding to it. For example, when the OR "Ai+Bi" is defined as a propagation signal Pi and the AND "Ai+Bi" is defined as a generation signal Gi, the equations (1) and (2) are shown by the following equations.Si=Pi+Cin  (3)Ci=Gi+Pi·Cin  (4)
Since "in" of "Cin" indicates a digit which is lower by one digit than the current digit number "i" which is arithmetically operated upon, it can be also shown as "i−1".
Specific examples of the carry output are expressed by the following equations with respect to the lowest digit up to the fourth digit. A general equation is shown at the end.C0=G0+P0·Cin C1=G1+P1·C0C2=G2+P2·C1C3=G3+P3·C2Cj=Gj+Pj·C(j−1)  (5)where, "j" is a positive integer such as 0, 1, 2, 3, . . . .
From the above examples of the carry outputs, by substituting each lower carry output into the upper carry output and developing each equation, the following equations are obtained. A general equation is shown at the end.
                                                        C0              =                              G0                +                                  P0                  ·                  Cin                                                                                C1                    =                                          G1                      +                                              P1                        ·                                                  (                                                      G0                            +                                                          P0                              ·                              Cin                                                                                )                                                                                =                                          G1                      +                                              P1                        ·                        G0                                            +                                              P1                        ·                        P0                        ·                        Cin                                                                                C2                    =                                          G2                      +                                              P2                        ·                                                  (                                                      G1                            +                                                          P1                              ·                              C0                                                                                )                                                                                =                                          G2                      +                                              P2                        ·                        G1                                            +                                              P2                        ·                        P1                        ·                        C0                                                                                =                                          G2                      +                                              P2                        ·                        G1                                            +                                              P2                        ·                        P1                        ·                                                  (                                                      G0                            +                                                          P0                              ·                              Cin                                                                                )                                                                                =                                          G2                      +                                              P2                        ·                        G1                                            +                                              P2                        ·                        P1                        ·                        G0                                            +                                              P2                        ·                        P1                        ·                        P0                        ·                        Cin                                                                                C3                    =                                                                                G3                      +                                              P3                        ·                                                  (                                                      G2                            +                                                          P2                              ·                              C1                                                                                )                                                                                =                                                                                G3                      +                                              P3                        ·                        G2                                            +                                              P3                        ·                        P2                        ·                        C1                                                                                =                                                                                G3                      +                                              P3                        ·                        G2                                            +                                              P3                        ·                        P2                        ·                                                  (                                                      G1                            +                                                          P1                              ·                                                              (                                                                  G0                                  +                                                                      P0                                    ·                                    Cin                                                                                )                                                                                )                                                                                =                                                                                G3                      +                                              P3                        ·                        G2                                            +                                              P3                        ·                        P2                        ·                        G1                                            +                                              P3                        ·                        P2                        ·                        P1                        ·                                                  (                                                      G0                            +                                                          P0                              ·                              Cin                                                                                )                                                                                =                                                                                G3                      +                                              P3                        ·                        G2                                            +                                              P3                        ·                        P2                        ·                        G1                                            +                                                                                P3                        ·                        P2                        ·                        P1                        ·                        G0                                            +                                              P3                        ·                        P2                        ·                        P1                        ·                        P0                        ·                        Cin                                                                                ·                                                        ·                                                                                Cj                    =                                          Gj                      +                                              Pj                        ·                                                  G                                                                                (                                                          j                              -                              1                                                        )                                                                                +                                              Pj                        ·                                                  P                                                                                (                                                          j                              -                              1                                                        )                                                                          ·                                                  G                                                                                (                                                          j                              -                              2                                                        )                                                                                +                                                                                Pj                                                                                …                                                                                P3                          ·                          P2                          ·                          P1                          ·                          G0                                                                    +                                              Pj                                                                                …                                                                                P3                          ·                          P2                          ·                          P1                          ·                          P0                          ·                          Cin                                                                                (        6        )
A circuit to realize the equations (6) is called a carry foreknowledge circuit of j [bit]. According to a carry foreknowledge adder having the carry foreknowledge circuit, by directly executing carry calculations of the upper digits from all inputs of the lower digits, they can be arithmetically calculated in parallel by adding circuits of the respective digits. Unlike a ripple carry adder or the like, since it is unnecessary to wait until the carry output of the one-lower digit (previous digit) is inputted even in the case where the digit number is large, an arithmetic operating speed can be raised.
However, the carry foreknowledge circuit has a problem such that the larger the number of digits is, the larger a circuit scale of the carry foreknowledge circuit becomes at a rate near the square of the digit number. Therefore, in the carry foreknowledge adder, for example, a plurality of carry foreknowledge circuits of about 4 bits (4 digits) are used, a numerical value larger than 4 bits is divided into groups (addition digit groups) every 4 bits (fixed length), and the addition is executed for every group in parallel.
The carry foreknowledge adder preliminarily arithmetically operates in the case where the carry input Cin from the lower group is equal to 0 and in the case where it is equal to 1 in every group and selects one of them on the basis of the carry input Cin from the group of the lower digits. That is, only the selection from two kinds of arithmetic operation results in the group of the upper digits is sequentially made by the carry output from the group of the lowest digits. Since the arithmetic operation is not started by the carry input Cin from the group of the lower digits, total arithmetic operating time is reduced.
FIG. 5 is a block diagram showing an example of a construction of an 8-bit adder using the carry foreknowledge adding circuits of 4 bits.
The left half of FIG. 5 shows the carry foreknowledge adding circuit of 4 bits on the lower side and the right half shows the carry foreknowledge adding circuit of 4 bits on the upper side.
An addition number A0 and an adding number B0 for a lower 4-bit block are inputted to a Pi/Gi generating circuit. A generation signal G0 and a propagation signal P0 of the lowest digit are generated and inputted to the carry foreknowledge circuit of 4 bits for the lower 4-bit block, and a carry output C0 is arithmetically determined. The propagation signal P0 is arithmetically operated upon together with the carry input Cin from the 4-bit adding circuit of the lower digit and an addition result S0 is arithmetically determined.
An addition number A1 and an adding number B1 for a lower 4-bit block are inputted to the Pi/Gi generating circuit. A generation signal G1 and a propagation signal P1 of the second digit from the lowest digit are generated and inputted to the carry foreknowledge circuit of 4 bits, and a carry output C1 is arithmetically determined. A propagation signal P1 is arithmetically operated upon together with the carry output C0 of the lowest digit and an addition result S1 is arithmetically determined.
Similarly, a generation signal G2 and a propagation signal P2 of the third digit from the lowest digit are generated from an addition number A2 and an adding number B2. A carry output C2 is arithmetically determined in the carry foreknowledge circuit. An addition result S2 is arithmetically determined from the propagation signal P2 and the carry output C1. A generation signal G3 and a propagation signal P3 of the highest digit of the lower 4-bit block are generated from an addition number A3 and an adding number B3. In the carry foreknowledge circuit, a carry output C3 is arithmetically determined and an addition result S3 is arithmetically determined from the propagation signal P3 and the carry output C2. The carry output C3 is transmitted to the carry foreknowledge adding circuit on the upper 4-bit side.
In the carry foreknowledge adding circuit on the upper 4-bit side, the carry output C3 is used as a carry input Cin and arithmetic operations similar to those in the carry foreknowledge adding circuit on the lower 4-bit side are executed upon the addition number Ai and the adding number Bi of each digit.
FIG. 6 is a block diagram showing a construction of the Pi/Gi generating circuit of each digit in the carry foreknowledge adding circuit of 4 bits.
As shown in FIG. 6, since the propagation signal Pi is the OR, the OR "Ai+Bi"=Pi can be outputted by inputting the addition number Ai and the adding number Bi to an OR circuit. Similarly, since the generation signal Gi is the AND, the AND "Ai·Bi"=Gi can be outputted by inputting the addition number Ai and the adding number Bi to an AND circuit.
FIG. 7 is a block diagram showing an example of the 4-bit carry foreknowledge circuit in FIG. 5 together with the Pi/Gi generating circuit.
A circuit at the first stage in FIG. 7 is a circuit in which in the Pi/Gi generating circuits shown in FIG. 6 as many as four digits are provided every digit as shown in FIG. 5. The generation signal Gi and the propagation signal Pi of each digit are generated by the circuit at the first stage.
Subsequently, in the first digit (in the case for lower 4 bits; the fifth digit in the case for upper 4 bits) in FIG. 7, the addition number A0 and the adding number B0 of the lowest digit are inputted and the generation signal G0 and the propagation signal P0 are generated by the circuit of the first stage. In an AND circuit AN62, the AND of the propagation signal P0 and the carry input Cin from the lower digit group is arithmetically determined and P0·Cin is outputted. In an OR circuit OR62, the OR of the generation signal G0 and P0·Cin is arithmetically determined and G0+P0·Cin is outputted.
As shown in the above equations (6), since G0+P0·Cin is equal to C0, C0=G0+P0·Cin in the above equations (6) is satisfied.
In the second digit (sixth digit in the case for upper 4 bits), the addition number A1 and the adding number B1 of the second digit from the lowest digit are inputted and the generation signal G1 and the propagation signal P1 are generated by the circuit of the first stage. In an AND circuit AN72, the AND of the propagation signal P0 and the carry input Cin is arithmetically determined and P0·Cin is outputted. In an AND circuit AN73, the AND of the propagation signal P1 and P0·Cin is arithmetically determined and P1·P0·Cin is outputted. In an AND circuit AN74, the AND of the propagation signal P1 and the generation signal G0 is arithmetically determined and P1·G0 is outputted. In an OR circuit OR72, P1·P0·Cin and P1·G0 are inputted and P1·G0+P1·P0·Cin is outputted. In an OR circuit OR73, P1·G0+P1·P0·Cin and the generation signal G1 are inputted and G1+P1·G0+P1·P0·Cin is outputted.
Since G1+P1·G0+P1·P0·Cin is equal to C1 as shown in the equations (6), C1=G1+P1·G0+P1·P0·Cin in the equations (6) mentioned above is satisfied.
Since an explanation is complicated with respect to the third and fourth digits, it is omitted. However, in a manner similar to the above, first, with respect to the third digit, G2+P2·G1+P2·P1·G0+P2·P1·P0·Cin is outputted from an OR circuit OR83. As described in the above equations, G2+P2·G1+P2·P1·G0+P2·P1·P0·Cin is equal to C2. Therefore, C2=G2+P2·G1+P2·P1·G0+P2·P1·P0·Cin in the equations (6) mentioned above is satisfied.
Subsequently, with respect to the fourth digit, G3+P3·G2+P3·P2·G1+P3·P2·P1·G0+P3·P2·P1·P0·Cin is outputted from an OR circuit OR95. As described in the above equations, G3+P3·G2+P3·P2·G1+P3·P2·P1·G0+P3·P2·P1·P0·Cin is equal to C3. Therefore, C3=G3+P3·G2+P3·P2·G1+P3·P2·P1·G0+P3·P2·P1·P0·Cin in the equations (6) mentioned above is satisfied.
As mentioned above, according to the conventional carry foreknowledge adder having the carry foreknowledge circuits, the arithmetic operations are executed in parallel in the adding circuits of the respective digits by directly executing the carry calculation of the upper digits by using all inputs of the lower digits, so that even if the number of digits is large, the arithmetic operating speed is raised.
However, as will be understood from FIG. 7, in the case of outputting the carry output C3 of the fourth digit, first, it is necessary that the carry input Cin from the lower digit group is inputted to an AND circuit AN92 and arithmetically operated by five circuits (5 elements) comprising the AND circuit AN92, an OR circuit OR92, an AND circuit AN98, an OR circuit OR94, and the OR circuit OR95. That is, in the conventional carry foreknowledge adder, the carry output C3 of the fourth digit is outputted only after the carry input Cin from the lower digit group was inputted and passed through the arithmetic operations of a critical path of five elements. The operation such that the carry input is arithmetically operated via the critical path of five elements results in that delay time corresponding to it is caused.
When the equations (6) are examined in detail, the carry input Cin from the lower digit group is necessary only in the last term in the equations (6). If it is shown in the case of the general equation in the equations (6), the last term is the term of the portion of "Pj . . . P3·P2·P1·P0·Cin". If it is shown in the case of the carry output C3 of the fourth digit, the last term is the term of the portion of "P3·P2·P1·P0·Cin".
As a carry foreknowledge adder, since there is a correlation between the digit number and the circuit scale as mentioned above, a plurality of circuits of about 4 bits (4 digits) are often used. Therefore, the case of the 4-bit adder will be considered hereinbelow. In this case, in the arithmetic operations to obtain the carry output C3 of the fourth digit, only the arithmetic operation of "P3·P2·P1·P0·Cin" needs the input of the carry input Cin from the lower digit group. If the circuit of the portion to execute the arithmetic operation of "P3·P2·P1·P0 Cin" can be arranged to the final stage of the carry foreknowledge adder, the arithmetic operations can be preliminarily executed with respect to the terms other than the last term in the equations (6). An amount of arithmetic operations which are executed after the input of the carry input Cin from the lower digit group can be reduced. Thus, the arithmetic operating speed can be raised.
However, hitherto, a circuit for further arithmetically determining the AND of the carry input Cin from the lower digit group and the AND arithmetic operation result of the propagation signals Pi of all digits such as "P3 P2 P1·P0" and the like at the final stage of an arbitrary digit of the carry foreknowledge circuit is not known.


A display pixel circuit having a data line loading circuit with a first capacitor, a first reset circuit coupled with the data line loading circuit, and a diode coupled to the data line loading circuit. The display pixel circuit also includes a second capacitor associated with the diode, and a second reset circuit coupled with the second capacitor. The first reset circuit is configured to reset the first capacitor. The second reset circuit is configured to reset the second capacitor, and the diode is driven by a constant current after resetting the first capacitor and the second capacitor.

1. Field of the Invention
The present invention relates to improvements in an organic light emitting display panel having one or more pixel circuits that includes an organic light emitting diode (OLED) disposed within the pixel circuit, and to improvements in methods of driving the organic light emitting display panel. In particular, the present invention provides an improved pixel circuit with respect to the organic light emitting display panel having an improved gray scale, and an improved driving method for optimally driving the pixel circuit for improving the gray scale.
2. Related Art
A cathode ray tube (CRT) has long been the display device for displaying images on a television. In a CRT display, a gun fires a beam of negatively-charged particles (electrons) inside a large glass tube. The electrons excite phosphor atoms along the wide end of the tube, which causes the phosphor atoms to light up. The video image is produced by lighting up different areas of the phosphor coating with different colors at different intensities. Although the CRT has long been used to display video images, it is bulky. In other words, it order to increase the screen width in a CRT display, the length of the tube must be increased as well in order to give the scanning electron gun room to reach all parts of the screen. Consequently, a CRT having a big screen is heavy and takes up a sizeable space.
A liquid-crystal display (LCD) device is another display device for displaying images. In a conventional LCD device, a built-in backlight is either disposed beside or behind the LCD display. This additional built-in backlight causes the LCD display device to be thick and heavy.
Accordingly, the conventional OLED display panel was introduced to overcome some of the drawbacks of the CRT and LCD display devices. Specifically, the conventional OLED display device includes one or more OLED that can spontaneously emit light without the need to have a built-in backlight. In addition, the conventional OLED provides a large and thin display screen with an image quality and performance equal to or superior to the CRT and/or LCD display device.
The conventional OLED display panel employs a voltage driver to directly modulate the gate voltage of a current source transistor by a voltage signal. However, the voltage driven approach encounters problems with respect to the brightness and/or the gray scale of the OLED. Accordingly, there is a need to have an OLED pixel circuit that improves the gray scale as well as improving the brightness of the OLED. In addition, there is also a need to provide a method of employing a current driver to drive currents to the OLED.

Light emitting device and method of driving thereof


A dummy wiring 25 is provided for simulating an actual wiring 26 connecting semiconductor integrated circuits 2 and 6 on a circuit board. The semiconductor integrated circuit comprises a data output circuit 28 capable of variably setting the slew rate and a circuit 29 for measuring signal delay time between a signal sending point and a signal reflection point (characteristic impedance mismatching point) using the dummy wiring 25, and the delay time so obtained by the measuring circuit is used for the determination of the signal transition time of the output circuit. The transition time of the signal is set at least twice of the signal delay time between the signal sending point and the wiring branch at the nearest end. In this way, signal transmission with alleviated reflection by the reflection point at the nearest end is realized.

The present invention relates to a technique to alleviate reflection of signals caused by discontinuity or mismatch of characteristic impedances in signal transmission lines and ringing induced thereby, and more particularly to a technique effective when applied to semiconductor integrated circuits, electronic devices, memory modules, and motherboards mounted with memory modules.
Due to the maximization of operation speed and the minimization of power and voltage levels in semiconductor devices, there is a trend that the amplitudes of signals transmitted between semiconductor devices are further reduced from those of TTL interfaces. This would increase the relative magnitude of impact from the effect of reflection occurred during signal transmission between semiconductor devices, resulting in increased likelihood of such semiconductor devices to miscomprehend the logic values of the transmitted signals. This would lead to the degradation in the operational reliability of semiconductor devices or electronic devices, which in turn, would be detrimental to the maximization of the operating speed of such semiconductor devices.
As one of the prior art technologies, there is one disclosed in Japanese Patent Laid-Open No. 10-41803/1998, which takes note of such impedance mismatch. The disclosure of which pays attention to the output impedance of a semiconductor device itself, which is one of the factors for impedance matching. That is, it is difficult to give uniformity to the output impedances of semiconductor devices due to process variability etc. Even if such uniformity could be achieved, there still is a possibility of the occurrence of mismatch due to the inductance components of packages or printed boards. Accordingly, the aforementioned disclosure relates to an invention which provides the controllability over the number of the final output stage transistors of an output circuit. There is also another known circuit which is disclosed as an output buffer in Japanese Patent Laid-Open No. 9-307419/1997.

Semiconductor integrated circuit and electronic device


Triarylsulfonium salts of formula I or II are useful as initiators for cationic photopolymerizations:

Almost twenty-three years ago, Crivello and Lam published the first paper describing the use of triarylsulfonium salts bearing anions of poor nucleophilic character as a novel class of efficient photoinitiators for cationic polymerization. Since this initial paper and due to the significant contributions of many other researchers, the field of photoinitiated cationic polymerization has expanded rapidly. Triarylsulfonium salt cationic photoinitiators are in widespread and increasing commercial use and are currently employed in such applications as printing inks, can and beverage coatings, adhesives, as well as in photo- and stereolithography, among many others.
The most common commercially available triarylsulfonium salt photoinitiators consist of a highly complex mixture of related arylsulfonium salts in which the primary components are shown below.

A two-step reaction sequence is used for the synthesis of these materials. In the first step, the condensation of benzene with sulfur monochloride is carried out in the presence of elemental chlorine with aluminum chloride as the catalyst. Thereafter, the resulting mixture of mono- and bissulfonium chlorides are subjected to a metathesis reaction in which the chloride anions are exchanged to provide the active photoinitiator mixture bearing an anion, MtXn−, of poor nucleophilic character. Typically, MtXn− represents a complex anion of the type: BF4−, PF6−, SbF6−AsF6−, or, (C6F5)4B−. The ratio of the different salts as well as the many other minor components obtained is largely determined by the stoichiometry of the reactants in the complex condensation reaction shown above as well as by the conditions under which it is carried out. However, in practice, the mixture of sulfonium salts shown above varies substantially from batch to batch and, since the photosenstivities of the triarylsulfonium salts are different, irreproducible and intolerable reactivity variations in many applications are observed. The marginal solubility of these same photoinitiators in many monomers and functional oligomers may also contribute to the irreproducibility of the photosensitivity in some systems. Many nonpolar monomers and functional oligomers fail to polymerize altogether due to the poor solubility of the photoinitiators. Lastly, and most importantly, it has been noted that the UV irradiation of the above photoinitiators results in the formation of benzene as one of the photolysis products. This takes place during the photolysis of the salts chiefly as a result of the homolytic cleavage of the sulfonium salts to form phenyl radicals and their subsequent hydrogen abstraction reactions. Due to the formation of traces of benzene, triarylsulfonium salt photoinitiators have been recently banned from use in Europe in those applications (e.g. printing inks) in which there is the possibility of food contact.
Despite the drawbacks cited above, triarylsulfonium photoinitiators possess many very attractive features that have played a strong role in their acceptance in many commercial applications. They are highly photosensitive and efficiently initiate very rapid vinyl and ring-opening cationic photopolymerizations on UV irradiation. Formulations containing these photoinitiators with monomers have extremely long shelf lives in the absence of UV light. Moreover, mixtures of monomers and triarylsulfonium salt photoinitiators can be heated to temperatures in excess of 120° C. without initiating polymerization. The excellent thermal latency displayed by triarylsulfonium salts is a very desirable property for all practical applications and greatly aids in both the clean up and in the reuse of photosensitive materials. Commercially available sulfonium salt photoinitiators have strong absorption bands in the short wavelength as well as the mid-region (305 nm) of the UV spectrum that is highly desirable since common mercury arc lamps as well as certain laser light sources have prominent emission bands in this region. As a result, many users have optimized their UV irradiation equipment to accommodate the absorption characteristics of these photoinitiators and it would be advantageous to find replacement photoinitiators with the same or a similar UV absorption response. They are nontoxic and have a low incidence of eye and skin irritation. Lastly, the above triarylsulfonium salt photoinitiators are inexpensive and are not easily replaced on a cost basis by other onium salt photoinitiators such as diaryliodonium salts.
The original Crivello paper mentioned above and subsequent papers disclosed 5-phenyl- and 5-(4-methylphenyl)-thianthrenium salts (Crivello, J. V. and Lam, J. H. W., Polymer Journal (Tokyo, Japan) (1985), 17(1), 73-83; Polymer Photochemistry (1982), 2(3), 219-26; and Journal of Polymer Science, Polymer Chemistry Edition (1980), 18(8), 2677-95). In addition, EP 580552, EP 869393, U.S. Pat. No. 5,731,364, U.S. Pat. No. 4,161,478, disclose use of various classes of thianthienium salts as photoinitiators or photoresists. However, problems associated with current photoinitiators were not recognized at that time. WO 03/008404, WO 03/002557 and U.S. 2003/0017415 disclose thianthrenium salts that lie outside the subject matter of the present invention.
There is, therefore, a need for a replacement for the present commercially available triarylsulfonium salt photoinitiators that preserves the same desirable features as triarylsulfonium salt photoinitiators, but avoids the problems outlined above.

Thianthrenium salt cationic photoinitiators

Abstract: wherein Ar1 and Ar2 are independently polycyclic aryl, substituted aryl, heteroaryl, substituted heteroaryl, or aryl or heteroaryl, pendant from a polymer chain; and MtXn− is a complex anion selected from PF6−, SbF6−, AsF6−, GaF6−, BF4−, (C6F5)4B− and CF3SO2)3C−.


A vest or belt is integrally formed with tubular, pet receiving passageways which extend around the wearer's body and terminate in pocket-like chambers for feeding and retrieval. Outer wall portions of the passageways are transparent so that a pet moving along the passageways can be seen by a spectator. Graphics or indicia depicting the pet's habitat or a pet story are marked on the vest and extend across portions of the passageways masking delineations or depicting the passageways as burrows.

Various prior proposals teach portable animal containers said to be wearable insofar as they are supported by a person's body. For example, U.S. Pat. No. 5,176,102 issued January 1993 to Tracy; U.S. Pat. No. 5,277,148 issued 1994 to Rossignol et al; U.S. Pat. No. 5,419,281 issued 1995 to Williams; and U.S. Pat. No. 5,445,302 issued 1995 to Holtorf all teach individual animal containers having shoulder straps for support by a person's body.
However, in the main, the above are intended for relatively large pets, such as cats and small dogs, and the containers protrude a substantial distance from the carrier's body which can be cumbersome and provide only very limited pet display in particular as the pets are substantially immobilized.
U.S. Pat. No. 3,859,961 issued 1975 to Willinger et al teaches a discrete animal path connecting system comprising rigid, perforate, transparent tubing that may be connected into a variety of configurations so that rodents can be viewed while moving therealong.
However, none of the above is suggestive of the present invention.


A method quickly identifies an irregular graphic shape displayed on a video terminal. In an "off-line" operation, the method associates transparent regular graphic shapes, such as boxes, with the irregular graphic shapes. The regular graphic shapes do not overlap one another and are shaped, sized, and located so that one or more of the regular graphic shapes together approximate each irregular graphic shape. The regular graphic shapes are defined in a data table which includes a single data node for each of the regular graphic shapes. During the execution of an application computer program, the irregular graphic shapes are displayed at the video terminal, but the regular graphic shapes are not displayed. In addition, the application computer program manages a video pointer in real time so that a user may move the video pointer to any location on the display of the video terminal. The program investigates the table of regular graphic shapes to select a node corresponding to a regular graphic shape. The selected regular graphic shape is the one which is defined to overlay the area of the display where the video pointer resides. A corresponding irregular graphic shape is then identified through its association with the selected regular graphic shape. Once the irregular graphic shape has been identified, a predetermined activity, such as displaying a name, may take place with respect to that irregular graphic shape.

The use of graphic displays in connection with personal and other computers has become common place. Such graphic displays may present textual data and graphics. Textual data are commonly associated with literary arts and include information expressed as ASCII data, extended ASCII data, alpha-numeric data, and the like. Graphics are commonly associated with pictorial arts and include pictures, drawings, symbols, and other arrangements of color and shape. Graphics differ from textual data in that the quantity of computer memory needed to store or otherwise define a given visual area is typically substantially more for graphics than for textual data. However, the quantity of data needed to describe a graphics drawing often depends on the nature of the drawing.
Bit-mapping represents a straight-forward technique for defining a graphics image. In a bit-mapped image one or more bits of memory define the nature of each pixel to be enclosed in a graphics drawing. However, video terminal technology has advanced to a state where several hundred thousand pixels are included in each square inch of display. Moreover, pixels may exhibit many different colors, and additional memory is required to specify pixel color. Consequently, a large quantity of memory is required to define a graphics image which occupies an entire video terminal screen, and an entire drawing which may occupy many screens requires an enormous quantity of bit-mapped data.
The amount of data required to define bit-mapped graphics images is far too large to pose a realistic solution for use in many applications which operate on personal computers. For example, an application which seeks to display a variety of maps on a personal computer video terminal could easily consume more than the entire amount of long-term disk memory available on typical personal computers in storing definitions for the maps. Accordingly, various techniques are implemented to encode or otherwise compress this voluminous quantity of data for storage. When displayed, this data is decoded, processed, or otherwise expanded to a bit-mapped form for application to video control circuits and presentation at the video terminal.
Another commonly used technique for encoding graphics data defines perimeters of the objects included in a drawing. Thus, the amount of memory needed to define the drawing depends on the nature of the drawing. Even when a drawing includes several objects and the objects exhibit irregular shapes, sufficient memory space savings result to permit practical use of this technique for many applications which operate on personal computers. However, when a drawing includes several objects or when the objects have irregular shapes, a substantial amount of computer processing must be performed to decode the graphics data before it may be displayed or otherwise manipulated. In the map-displaying application discussed above, a map may include many objects or political regions, and the regions will typically exhibit extremely irregular shapes. Many maps may be encoded for use on a typical personal computer, and a significant amount of computer time must be dedicated to decoding the graphic data for video display or other processing.
The use of pointing devices has also become common place in connection with personal computers. Such pointing devices manipulate a video pointer using a keyboard, joystick, mouse, track-ball, or the like, in combination with controlling software. The pointer system provides display coordinates which define a location on the display where the video pointer should then be positioned. Often times, application software processes graphics data with respect to such display coordinates to identify a specific object indicated by the video pointer. Application specific software then performs an application-related activity with respect to the specified object. For example, computer aided design (CAD) programs often allow a user to select a graphic object using a video pointer. Typical CAD programs then perform some activity, such as enlarging, shrinking, moving, erasing, and the like, on the selected object.
Generally speaking, the computer processing time required to identify a pointer-selected graphic object is much greater for encoded graphic data than for bit-mapped graphic data. Moreover, the computer processing time needed to identify one of several irregularly shaped, encoded graphic objects is much greater than for corresponding regularly shaped, encoded graphic objects because irregular shapes require specification of many parameters to accurately characterize the object. Thus, CAD programs which utilize bit-mapped graphics or which manipulate relatively regular shapes may appear to perform an activity on a selected graphic object in real time. However, extensive delay occurs whenever graphic data encoding is employed with a drawing that includes many objects having irregular shapes.

Using regular graphic shapes to identify a pointer-selected graphic object


Systems and methods of operating multimode 3G/4G communications devices in an overlapping 3G/4G coverage area (e.g., WiMAX or LTE/CDMA EvDO) include determining if a number associated with temporarily-disabled sectors of an available sector set of the multimode device while the device is operational with a 3G base station is at least equal to a threshold number. If the number is at least equal to the threshold number, a scan for a sector in the 4G network to handover the operation of the multimode device from the 3G base station associated with the 3G coverage to a 4G base station associated with the 4G coverage is initiated. A scan for a fixed period of time for a new available sector in the 3G network to be added in the available sector set may be initiated; and, if a new available sector is added to the sector set, it may be redetermined if the number associated with the temporarily-disabled sectors is at least equal to the threshold number, before initiating the scan for a sector in the 4G network.

This disclosure is generally related to high speed wireless packet-based data networks and devices. In particular, this disclosure is related to multimode devices capable of operating in both third and fourth generation ("3G" and "4G") wireless networks. Examples of 3G wireless technologies includes Code Division Multiple Access (CDMA) and Evolution-Data Optimized or Evolution-Data only ("EvDO")/CDMA. Examples of 4G wireless technologies include Worldwide Interoperability for Microwave Access ("WiMAX") technologies and Long Term Evolution (LTE) technologies.

Apparatus and method for multimode device handover


A printing control apparatus prints an image in a size corresponding to a print medium size candidate if a candidate of a print medium size acquired by detecting a print medium size with a sensor is included in a plurality of sizes acceptable for printing in print setting.

1. Field of the Invention
The present invention relates to a printing control apparatus configured to control a printing apparatus to print an image, a printing control method, and a storage medium.
2. Description of the Related Art
Recently, there is a cloud print service that a print server on the Internet transmits print target data to a printer via the Internet and causes the printer to print the data as a cloud service. In this cloud print service, a user gives an instruction for printing to the print server via an apparatus such as a personal computer and the print server which receives the print instruction causes the printing apparatus to execute printing.
In such an environment, sometimes a paper error occurs since the print sheet size of the print target data does not match the size of the print sheet placed in the printing apparatus. Japanese Patent Application Laid-Open No. 2013-37547 discloses a technique by which a print server acquires sheet size information of a printer, and compares the sheet size of print target data and the size indicated by the sheet size information acquired from the printer. Then, when those sizes do not match, the print target data is converted into a sheet size printable by the printer.
For example, if print target data is data such as a print test pattern or access information like a uniform resource locator (URL) to a registration site for a print service user registration or a one-time password, the printing may be enough as long as the printed content can be recognized by the user. In the case that such contents are the print target, the contents may be printed and sufficiently recognized even when the size of the image to be printed does not match the size of the print sheet set on the printer.
When the print data conversion process like the technique described in Japanese Patent Application Laid-Open No. 2013-37547 is executed in printing of such print target data, the conversion process may cause a delay in outputting the print target data and the printing cannot be executed promptly.

Printing control apparatus controlling a printing unit to print an image corresponding to print medium size


In one embodiment of the present disclosure, a phased array antenna system includes a first portion carrying an antenna lattice including a plurality of antenna elements, wherein the plurality of antenna elements are arranged in a first configuration, a second portion carrying a beamformer lattice including a plurality of beamformer elements, wherein the plurality of beamformer elements are arranged in a second configuration different from the first configuration, and a third portion disposed between the first portion and the second portion carrying at least a portion of a mapping including a first plurality of mapping traces on a first surface providing at least a portion of the electrical connection between the plurality of antenna elements and the plurality of beamformer elements, wherein each of the plurality of antenna elements are electrically coupled to one of the plurality of beamformer elements.

An antenna (such as a dipole antenna) typically generates radiation in a pattern that has a preferred direction. For example, the generated radiation pattern is stronger in some directions and weaker in other directions. Likewise, when receiving electromagnetic signals, the antenna has the same preferred direction. Signal quality (e.g., signal to noise ratio or SNR), whether in transmitting or receiving scenarios, can be improved by aligning the preferred direction of the antenna with a direction of the target or source of the signal. However, it is often impractical to physically reorient the antenna with respect to the target or source of the signal. Additionally, the exact location of the source/target may not be known. To overcome some of the above shortcomings of the antenna, a phased array antenna can be formed from a set of antenna elements to simulate a large directional antenna. An advantage of a phased array antenna is its ability to transmit and/or receive signals in a preferred direction (e.g., the antenna's beamforming ability) without physical repositioning or reorientating.
It would be advantageous to configure phased array antennas having increased bandwidth while maintaining a high ratio of the main lobe power to the side lobe power. Likewise, it would be advantageous to configure phased array antennas having reduced weight, reduced size, lower manufacturing cost, and/or lower power requirements. Accordingly, embodiments of the present disclosure are directed to these and other improvements in phase array antennas or portions thereof.

Antenna-to-beamformer assignment and mapping in phased array antenna systems


The present invention relates to a tablet having a flexible and transparent sensing area, comprising: an insulating transparent base material having a first loop antenna and a plurality of comb-shaped first line antennas; and a control substrate having, mounted thereon, a first multiplexer (MUX) for selecting one of the ends of the plurality of first line antennas, an amplifier for outputting a potential difference between an output of the first multiplexer and the first loop antenna, and an MCU (micro controller unit) for generating a first selection signal and, on the basis of the potential difference from the amplifier, sensing the position of an electronic pen from one line antenna. The first loop antenna formed on the transparent base material is combined with a first conductive pattern formed on the control substrate, thereby forming a closed loop. Each of the plurality of first line antennas is connected to each of a plurality of first extending patterns insulatively crossing the first conductive pattern on the control substrate. The plurality of first extending patterns are connected to an input of the first multiplexer.

Recently, there has been the spotlight on electronic devices (tablet operating systems) which are able to be handled by touching a display surface with a finger or an electronic pen, like a smart phone and a tablet computer.
Further, in tablet operating systems, a predetermined electronic pen sensing region should be set up so as to handle an electronic device by using an electronic pen. A position of the electronic pen which touches the sensing region should be calculated, for example in orthogonal coordinates.
One example of such tablet operating systems is disclosed in Korean patent application publication No. 2008-86829 (hereinafter, referred to as the reference document). In the reference document, loop coils for sensing a position of an electronic pen with respect to any one of axis directions are arranged in an overlapping structure in which at least three loop coils are insulated from each other. Thus, at the time of configuring a position detecting region having a loop coil pattern, a laminate structure of at least six layers is required even when configuring the position detecting area using a transparent conductive material such as ITO, etc., and a transparent insulating sheet. Therefore there is a limitation on transparency. Further, flexibility of the position detecting area itself is reduced with overlapping of a multi-layered sheet.
In addition, in order for the respective loop coils to be insulated from each other and for the ends thereof to be connected together, a vertical structure such as a through hole which passes through insulation layers is required. Therefore it was difficult to form such a vertical structure with transparent insulation sheets so that in the prior art there was no choice but to use opaque, thick and hard sheets. In this way, a tablet in the prior art in which the substrate of an opaque and fixed type is used as an electronic pen sensing region has a limitation on usage methods and applications of the tablet.

Tablet having a flexible and transparent sensing area


A variable orifice flow sensor includes a flow conduit member defining a flow orifice and fluidly connecting first and second fluid flow ports, a flapper of magnetizable sheet metal that is mounted in the conduit member by a hinge portion so that the flapper angularly deflects out of the plane of the orifice in response to fluid flow through the conduit member to vary the effective fluid flow cross-sectional area of the orifice in proportion to the flow rate of fluid through the conduit member, and a pressure sensing tap on either side of the flapper. A deflection-limiting surface is provided in the conduit member adjacent the hinge portion. The hinge portion abuts against the deflection-limiting surface when the flapper experiences an angular deflection at least equal to a predefined angle in response to a fluid flow rate that is at least equal to a predetermined value, whereby overstressing of the hinge portion is minimized. In addition, at least one magnet is provided in the conduit member adjacent the flapper, whereby the magnet generates a magnetic field that acts on the flapper so as to force it into a position that tends to minimize the zero flow gap that exists between the flapper and the portion of the conduit member that defines the fluid flow orifice when there is no fluid flow through the orifice.

This invention relates generally to the field of fluid flow sensors. More specifically, it relates to improvements in fluid flow sensors of the variable orifice or variable obstruction area type, that are commonly used, in conjunction with a pressure transducer, to generate a differential pressure signal from fluid (especially gas) flow in a conduit, wherein the value of the differential pressure signal is correlated with a flow rate value. The flow rate value, in turn, may be integrated over time to yield a volumetric value.
Flow sensors of the class described above have become commonly used in medical applications, particularly for measuring the flow rate of respiratory gas in medical ventilators. Specific examples of such flow sensors are found in the following U.S. Pat. Nos. 4,989,456--Stupecky; 4,993,269--Guillaume et al.; and 5,038,621--Stupecky. The variable orifice flow sensors exemplified by these patents employ a hinged obstruction or flapper that is mounted within a flow orifice of known area. The flapper is mounted so that the portion of the total area of the orifice that it opens to fluid flow is proportional to the flow rate through the orifice. The pressure drop across the orifice is proportional to the open area through the orifice. Thus, the differential pressure across the orifice is directly related to the flow rate through the orifice. This pressure differential is sensed by pressure ports upstream and downstream from the orifice. The sensed upstream and downstream pressures are directed to a differential pressure transducer, which generates an analog electrical signal having a value representing the differential pressure value. The analog signal is digitized and input to a microprocessor that is programmed to compute a value representing the instantaneous volumetric fluid flow rate through the orifice.
While flow sensors of the type described above have exhibited acceptable levels of accuracy and reliability, further improvements have been sought. Specifically, the use of such flow sensors in respiratory therapy equipment, particularly medical ventilators, has led to their fabrication from materials, such as stainless steel, that can be sterilized in autoclaves. A flapper made of stainless steel, however, is susceptible to fatigue and failure (especially at its hinged attachment point) due to repeated deflections over long periods of use, and due to overstress in response to high flow rates. This problem could be overcome by strengthening the hinged attachment part of the flapper and by increasing the area of the flapper so that it is not overstressed at high flow rates, but this solution would result in a loss of resolution at low flow rates.
Furthermore, it has been found that the use of stainless steel flappers has, in itself, resulted in the loss of low-end resolution. This is because, during the fabrication process, the stainless steel sheet takes a "set" that results in a flapper that deviates somewhat from a true planar configuration. In other words, the flapper is often slightly curved, so that, when it is installed in the orifice, there is a gap between the flapper's peripheral edge and the annular surface that defines the orifice. This results in a non-zero orifice area at zero flow rate, which, in turn, results in the loss of resolution at low flow rates. Furthermore, to avoid deterioration in accuracy due to exposure to the high temperatures of an autoclave, the flapper is advantageously annealed. The annealing process, however, softens the stainless steel, and the resultant loss of stiffness or rigidity causes the flapper to lose a measurable degree of responsiveness, most noticeable at low flow rates. Thus, the annealing process, while addressing one cause of inaccuracy (high temperature exposure), introduces another cause (loss of flapper rigidity).
Thus, there has been a need for a variable orifice flow sensor with a metal (preferably stainless steel) flapper that is capable of withstanding repeated deflections over a long period of use without fatigue or failure, even with repeated exposure to high flow rates. There has been a further need for such a flow sensor that also yields good low end sensitivity and resolution. There has been a still further need for such a flow sensor that is capable of withstanding repeated autoclaving without deterioration of accuracy over time, and without sacrificing responsiveness.


The present invention relates generally to an apparatus for identifying biological particles. More particularly, the present invention relates to a small apparatus for identifying biological particles, wherein in a single apparatus having a simple structure, a cleaning solution is suctioned to separate the biological particles from a filter and a sample solution is discharged, the discharged sample solution is injected into a plurality of ticket modules, and the biological particles are identified by image analysis for the ticket modules, thereby enabling miniaturization of the apparatus.

The threat of bioterrorism has been increased because biological agents are easy to develop as weapons, and are easy to transport and release. These agents can be widely spread by carriers who travel by public transportation and high-speed transportation means during the incubation period, causing much damage due to psychological panic and severe economic chaos.
As can be seen from the economic and social ramifications of MERES and severe acute respiratory syndrome (SARS), which have recently occurred in many countries, it is predicted that the deadly spread of virus by human-made intentional terror attacks will cause more panic to the public.
Therefore, it is necessary to detect bacteria released into the atmosphere artificially by terrorists in real time and take countermeasures. However, the released bacteria cannot be detected because they stay suspended in the air as invisible fine particles, and due thereto, a specialized detection apparatus is required separately. For this purpose, apparatuses capable of detecting and identifying biological particles have been developed as described in the following patent document.
One example of these apparatuses is configured to separate a filter from field detection equipment for precise identification and analysis of the biological particles, and to analyze the biological particles trapped by the filter in a separate identification device. In this case, the biological particles may scatter around the filter during transfer of the filter, and thus the biological particles may be contaminated by the surrounding environment.
Furthermore, rapid identification and analysis of the biological particles are important. However, such an identification apparatus in the related art is problematic in that it may be difficult to rapidly analyze many kinds of biological particles simultaneously, and the configuration of the apparatus may be complicated and enlarged, thereby making it difficult to move the apparatus.

Small apparatus for identifying biological particles


A surveying system that comprises a position relation calculating processor, a correspondence establishing processor, and an image processor is provided. The position relation calculating processor calculates a positional relation between a coordinate system to which measurement information of a measurement point refers and an image of a surveying field, where a staking point is included. The correspondence establishing processor establishes correspondence between three-dimensional position information of the staking point and two-dimensional position information of a point corresponding to the staking point on the schematic image. The image processor superimposes a symbol that indicates the position of the staking point on the schematic image in accordance with the above correspondence.

1. Field of the Invention
The present invention relates to a surveying system, for which staking out or laying off can be carried out. Further, the invention also relates to a surveying system, which can also process measurement information within the system.
2. Description of the Related Art
In conventional route surveying or site surveying, which involves staking out operations, at least two persons are required. Namely, one person operates a surveying instrument provided with a staking out function, while the other person searches for a staking point with a target, such as a prism or the like. Position data for a plurality of given points, where substantial or actual positions are known, and staking points are pre-installed in a surveying instrument, such as a total station or the like. For example, the surveying instrument is positioned at a second given point with respect to a direction from a first given point, known as a back sight direction. The horizontal angle and the horizontal distance from the instrument point to a staking point with respect to the first given point is indicated on the surveying instrument. The person with the prism or target should stand at about a position that is expected to be near an objective staking point, while the other person measures the position of the prism or target, with the surveying instrument and detects the difference from the position of the objective staking point, so as to instruct the person with the prism or target which direction the prism or target should be moved, by using two-way or gestures. This operation is repeated until the difference between the target and the position of a preset staking point becomes sufficiently small for the two points to be regarded as at equal positions, so that a stake is properly positioned. Further, when a recently developed surveying instrument with an automatic sighting function is used, the above explained staking out surveying can be achieved by one person. Namely, the surveying instrument automatically aims at the prism or target that is held by one staking operator and instructs the operator regarding which direction to move, by sending measurement data via a wireless telecommunication system or through optical signals. The staking operator may seek the given staking point with reference to the transmitted measurement data or the optical signals and move the prism or target.
However, the above surveying operations involving one or two people are cumbersome and require time, since a staking operator is lead to a given staking point by using words and gestures, so that the position of a staking point is not clear for the staking operator. Even when using an automatic sighting surveying instrument, it is still difficult to obtain a proper position of a staking point visually and spatially, so that searching for a given staking point is difficult. Further, when there are a substantial number of measurement points, an unmeasured measurement point might be confused with a measurement point that has already been measured.
Further, in conventional surveying or measurement practice, a picture or image of a surveying area including stations (points which are to be measured) may be taken and recorded with the measurement data on some occasions. On these occasions, an image of a surveying area may be photographed with a separate normal camera not associated with the surveying instruments or with an imaging device integrally installed inside the surveying instruments, as described in Japanese unexamined patent publication No. 11-337336. In this publication, images are captured for each of the measurement points.
However, when an image is taken with a separate normal camera, measurement points are not indicated on the image, so that it is impossible for a user to identify the points on the image that correspond to each of the measurement points. On the other hand, when utilizing a surveying instrument disclosed in the above unexamined patent publication '336, a large-capacity memory is required, since images are captured and stored for each of the measurement points, which in turn causes operating difficulties for a user.