The present invention is directed to a lateral photo-sensing device comprising a first semiconductor layer of a first conductivity type formed on a semi-insulative semiconductor substrate, a second semiconductor layer of a second conductivity type formed on the first semiconductor layer for absorbing a light, a pair of electrodes formed on the second semiconductor layer, rectifying junction being formed between the electrodes and the second semiconductor layer, and a biasing electrode for applying a biasing voltage to the first semiconductor layer. Further the present invention is directed to an opt-electronic integrated circuit using the lateral photo-sensing device and a photo-logic device using the lateral photo-sensing device.

1. Field of the Invention
The present invention relates to a lateral photo-sensing device used for photo-electric conversion or photo-detection, an opt-electronic integrated circuit using the lateral photo-sensing device and a photo-logic device using the lateral photo-sensing device. Further the present invention more particularly relates to a photo-conductive type lateral photo-sensing device used for an opt-electronic integrated circuit (OEIC) or a photo-module for light communication or light information processing, to a opt-electronic integrated circuit (OEIC) used in an optical local area network (LAN) a fiber distributed data interface (FDDI) which has a limited operation band and operates at a high speed, to a photo-receiving OEIC applicable to both long distance and short distance light communications, and to an optical switch for light communication which is usable in a photo-logic operation in an opt-neuro system or an optical computer.
2. Related Background Art
FIGS. 1A, 1B and 1C show examples of prior art lateral photo-sensing devices.
In a first photo-conductive type photo-sensing device shown in FIG. 1A (Japanese Patent Application No. 63-88758), a recess is formed in a semi-insulative semiconductor substrate 5, and a p-type semiconductor layer 6 is formed therein and then an n-type photo-sensing layer 7 is formed. In this manner, a flat lateral photo-sensing device which is easy to isolate is provided. A pair of n-type ohmic electrodes 9a and 9b are formed on the photo-sensing layer 7 as photo-sensing device electrodes. A p-type ohmic electrode 8 formed and the semiconductor layer 6 functions to apply a reverse bias between the semiconductor layer 6 and the photo-sensing layer 7. Holes generated in the photo-sensing layer 7 are collected by the ohmic electrode 8 to improve an operation speed of the device. Further, the photo-sensing layer is depleted to reduce a dark current.
In a second photo-conductive type photo-sensing device shown in FIG. 1B (Japanese Patent Application No. 63-81030), an n-type photo-sensing layer 11 is first grown on a semi-insulative semiconductor substrate 12.
Then, a pair of n-type ohmic electrodes 13a and 13b and a pair of p-type ohmic electrodes 14a and 14b surrounding the electrodes 13a and 13b are formed on the photo-sensing layer 11. The electrodes 14a and 14b function to increase a resistance of a light absorbing layer beneath the electrodes 13a and 13b so that a dark current is reduced and a performance of the device is improved.
In a third photo-conductive type photo-sensing device shown in FIG. 1C (pp 1. Phys. Lett. 54(1), Jan. 2, 1989, pp 16-17), a light absorbing GaInAs layer 24 is formed on semi-insulative InP substrate 21 and AlInAs layer 22 with an intervention of a superlattice layer 23. Then, a barrier enhancing AlInAs layer 26 and a Schottky electrode Al layer 27 are formed on the GaInAs layer 24 with an intervention of a superlattice layer 25. It is then mesa-etched to form a device as shown. Because of the presence of the AlInAs layer 26, the device has a small dark current and exhibits a high response characteristic.
In the first and second photo-conductive type photo-sensing devices described above, the n-type ohmic electrodes are used as the device electrodes. As a result, the device has a relatively large dark current and a large noise and it is not suitable for use as the OEIC. Further, it is not suitable for a high speed operation because of reinfection of carriers.
On the other hand, in the third photo-conductive type photo-sensing device, a responsivity and a response speed are low at a low bias voltage (e.g.-3v). In order to attain sufficient sensitivity and response speed in such a device, a high bias voltage such as vi or higher is required.
Further FIG. 2 shows a conventional circuit configuration used in a prior art photo-sensing OEIC or photo-sensing module. A pin-photo-diode (PD), a metal-semiconductor-metal (MSM) or an avalanche photo-diode (APD) is used as a photo-sensing device 32 for converting a signal light to an electrical detection signal. In order to amplify the detection signal of the photo-sensing device 32, an amplifier circuit comprising an amplifier 34 and a load resistor 36 is connected succeeding to the photo-sensing device 32. While a trans-impedance type amplifier circuit may be connected the electrical signal may be mixed by other methods.
However, when the pin-PD or the MSM is used in the OEIC, a signal detection band is governed by a capacitance and a time constant of a load resistor, and a photo-sensing diameter must be small in order to attain a high operation speed. In such an OEIC, a responsivity does not exceed 1 A/W in principle and no substantial amplification effect is attained. Thus, the amplifier circuit is necessarily complex. In the OEIC which uses the APD, the drive voltage is several tens of volts, which makes it difficult to apply to the OEIC which is operated by a signal power supply. In the approach to mix the electrical signal, the circuit configuration is difficult to design and high integration density OEIC is difficult to attain.
Further more, fibers used for light communication include ones for short distance and ones for long distance. In the optical LAN, a module which is compatible to both applications is required. In general, the fiber for short distance supplies a strong light signal and a fiber for long distance supplies a weak light signal. Accordingly, an AGC function is required to cope with the signals from those fibers. Two prior art techniques to attain the AGC are known. In one approach, an external control circuit is provided to control a gain of a pre-amplifier. (For example, Japanese Patent Application No. 1-217967). In the other approach, this function is provided in the amplifier and the internal circuit produces an average level and varies a bias voltage of the amplifier in accordance with the average level.
However, in the approach to control the gain of the pre-amplifier, heat generation is not negligible, power consumption is high and noise is high. In the approach to change the bias voltage of the amplifier by the internal circuit of the amplifier, additional problems of complexity of circuit configuration and low yield of the manufacture of the OEIC arise.
Further prior art optical switches (a) use a two-dimensional planar wave guide formed on a LiNbO.sub.3 surface or (b) convert a light signal to an electrical signal and process it by an associated electrical circuit.
One photo-logic device (c) directs parallel light signals of vector components to two orthogonal planes of a nonlinear optical material and takes out a secondary harmonic generated at a cross-point of the parallel light signals as a matrix of an optical AND signal. Further, an optical neuro chip used in the photo-operation (d) uses a mask having a transmissibility which is proportional to a synapus load sandwiched between a belt-shaped light emitting diode array and belt-shaped photo-sensing diode array (Optics Letters, Vol. 14, No. 16, Aug. 15, 1989), and an optical memory used for the optical operation (e) uses a parallelly connected pn structure (Optics Letters, Vol. 15, No. 13, Jul. 1, 1990).
However, in the optical switch of (a), the absorption in the LiNbO.sub.3 wave guide is not negligible and a transmissive characteristic is not good. In the optical switch of (b), the structure is complex because the photo-sensing device, IC and light emitting device are integrated.
In the photo-logic device of (c), the output optical AND signal is weak because the nonlinear optical material is used and only two-dimensional processing is permitted. In the devices of (d) and (e), they are not photo-logic devices by themselves and their burden to the associated electrical circuit is large.

Lateral photo-sensing device, opt-electronic integrated circuit using the lateral photo-sensing device and photo-logic device using the lateral photo-sensing device


Before obtaining service from an installed terminal, a mobile unit can be authenticated (subauthenticated) only by the operation of the mobile unit such as an unauthenticated digital camera, etc. using an authenticated mobile phone. A digital camera is radio-connected with an installed terminal, and the digital camera is also radio-connected with a mobile phone of a user. The installed terminal center is notified of the identification code of the mobile phone through the digital camera and the installed terminal. The installed terminal center inquires of the carrier center about the validity/invalidity of the mobile phone. Upon receipt of the notification of the validity of the mobile phone from the carrier center, the installed terminal center permits service to the installed terminal in the installed terminal.

1. Field of the Invention
The present invention relates to a mobile unit authenticating method, and more specifically to mobile unit authenticating method for authenticating a mobile unit of a user when offering service by receiving or transmitting digital contents between, for example, an installed terminal in a store and a user mobile unit.
2. Description of the Related Art
Japanese Patent Application Publication No. 2000-187763 discloses a cashless vending machine system in which a user can purchase articles by using a charging system authenticated by a carrier. In this vending machine system, when a user inputs his or her password for personal identification on his or her mobile phone, the common carrier can authenticate the user (contractor of the mobile phone) using the password. Then, when the user inputs an identification code of the vending machine on the mobile phone, the common carrier allows the user to purchase the specified article on the vending machine through the identification code of the vending machine. If the user selects an article using an article button, the selected article is served to the user, and the purchase record of the article is transmitted from the vending machine to the common carrier. The common carrier then charges the user the purchase price for the article purchased through the vending machine when the telephone rates are charged.
However, when the conventional billing system of the mobile phone is used, and when cashless printing service, music downloading service, etc. are offered to a mobile unit other than a mobile phone such as a digital camera, a solid state portable stereo (MP3 unit, etc.), etc. from an installed terminal, there is the above mentioned problem that a mobile unit has to be operated with the mobile phone, thereby necessarily performing a complicated operation.


A technique of facilitating a coil winding work by continuously winding coils in the same direction, in a stator in which a plurality of coils constituting a coil group of the same phase are respectively arranged so as to include positions at which phases of induction voltage are different, whereby coil groups of three phases are disposed in a ring shape. A stator (102) of the invention has a structure in that a pair of coils (21U1, 21U4) and coils (21U2, 21U3) in which phases of induction voltage are identical in a plurality of coils (21U1 to 21U4) constituting a U-phase coil group (21U) are set as different divided groups, the respective coils (21U1, 21U4) and coils (21U2, 21U3) in the divided group are continuously wound in the same winding direction while arranging crossovers (26U1, 26U3) respectively between the coils (21U1, 21U4) and between the coils (21U2, 21U3), the divided groups are connected in parallel, and a V phase and a W phase are executed in the same manner, whereby lead wires of three-phase coil groups (21U, 21V, 21W) are star connected.

1. Field of the Invention
The invention relates to a three-phase coil stator in which a plurality of coils are arranged in a ring shape. More particularly, the invention relates to a stator suitable for a stator of a brushless motor.
2. Description of the Related Art
Various motors such as an induction motor and a commutator motor have been conventionally used as the motor. However, in recent years, a brushless motor which has high performance has been frequently used. For example, an inner rotor type brushless motor has a structure such that a stator around which a plurality of coils are wound is formed as an outer stator and a rotor having a magnet arranged in an outer periphery is formed as an inner rotor. The stator is produced by applying a coil winding to a stator core in which a teeth portion for winding the coil is protruded to an inner side in a ring shape. However, because a leading end side becomes narrow between the adjacent teeth portions, the act of coil winding tends to be complicated, and it is not easy to improve a space factor or the coil winding. In order to solve such a problem, there has been invented a stator core in which the stator core can be divided at every tooth portion, and each of the tooth portions can be formed in a linear shape at the time of a coil winding work.
For example, JP-A 2002-58181 discloses a stator in which divided core units are structured by forming a crossover between a plurality of divided cores obtained by dividing a stator core into tooth portion units continuously wound, and the divided core units are coupled in a ring shape in such a manner as to form a rotating magnetic field by three phases of a U phase, a V phase and a W phase. According to this configuration, it is possible to continuously wind by appropriately attaching the divided cores to a jig or the like so as to obtain a layout by which a coil winding work can be easily executed, and it is possible to thereafter couple the divided core units in the ring shape. Therefore, it is possible to make the coil winding work easy and it is possible to improve a space factor of the coil winding.
Further, JP-A 10-271770 (1998) discloses a configuration in that coils are continuously wound every phase by forming a crossover between a plurality of core segments divided per a teeth portion unit, a core segment serial body is formed by coupling concave grooves and convex pieces of the core segments, and a stator is thereafter formed by rounding in an annular body. Also in such a configuration, similarly to the above configuration, it is possible to facilitate the coil winding work and improve the space factor of the coil winding.
Further, JP-A 9-191588 (1997) discloses a configuration such that a stator having a ring shape is formed by continuously winding the coil around a linear unit core configured by integrally coupling a thin coupling portion every teeth portions by connecting between the coils by a crossover, and bending the thin coupling portion after finishing the coil winding. Also in such a configuration, similarly to the above configuration, it is possible to facilitate the coil winding work and improve the space factor of the coil winding.
For the most part, the coil of the stator as described above is continuously wound every phase, and the rotating magnetic field is formed by a coil group of three phases of the U phase, the V phase and the W phase. Accordingly, the number of teeth, that is, the number of slots of the stator is set to an integral multiple of three such as 3, 6, 9 and 12. The slot number of the stator is set in accordance with a design concept of the motor. However, the number of poles of the motor, that is, the number of poles of the magnet in the rotor is important in view of the design of the motor, and the number of poles of the magnet is determined while taking a normal rotation speed and a maximum rotation speed of the motor, and a magnitude of the motor into consideration, and the optimum number of slots of the stator is selected in correspondence to the number of poles of the magnet.
As described above, the number of poles of the magnet and the number of slots are determined on the basis of the design concept. However a description will be given here by exemplifying a brushless motor in which the number of poles of the magnet is 8 or 14, and the number of slots of the stator is 12. In this case, a cogging torque is lowered by setting the number of poles of the magnet to 14 in comparison with the case of 8 poles, and there is an advantage in that a large amount of torque can be obtained at a low rotation speed range such as about 1000 RPM.
FIG. 11 shows a configuration of a brushless motor 900 having 8 poles and 12 slots, and FIG. 12 is a schematic view showing a coil polarity thereof. Magnets 91 disposed in a periphery of a rotor 90 are arranged in 8 poles at a uniform interval in a circumferential direction such that N poles and S poles are alternately formed. On the contrary, 12 coils 93a to 93l of a stator 92 are arranged at a uniform interval in a circumferential direction so as to surround the rotor 90. In the brushless motor 900 having 8 poles and 12 slots as described above, as shown in FIG. 11, the coils 93a, 93d, 93g and 93j are arranged so as to form the U phase, the coils 93b, 93e, 93h and 93k are arranged so as to form the V phase, and the coils 93c, 93f, 93i and 93l are arranged so as to form the W phase. This arrangement is assumed to have the best motor efficiency in the brushless motor 900 having 8 poles and 12 slots. Accordingly, for example, on the assumption that the stator 92 is constituted by 12 divided cores, the U-phase coils 93a, 93d, 93g and 93j are continuously wound around four divided cores by forming a crossover between the respective divided cores, and the V-phase coils 93b, 93e, 93h and 93k and the W-phase coils 93c, 93f, 93i and 93l are continuously wound around respective four divided cores while forming crossovers between the divided cores in the same manner, whereby the respective divided cores are coupled in a ring shape on the basis of an arrangement shown in FIG. 11. In this case, in FIG. 11, a circular mark in each of the coils 93a to 93l denotes a winding start of the coil winding, and a square mark denotes a winding end of the coil winding. Winding directions of the coils continuously wound respectively in the U phase, the V phase and the W phase are the same direction. Further, it is preferable that a wire connection of each of the coils 93a to 93l is constituted by a star wire connection in which four coils in each of the phases are connected in series as shown in FIG. 13. Further, for example, the respective coils 93a, 93d, 93g and 93j of the U phase are in conformity to each other in a phase and a magnitude of induction voltage as shown in FIG. 12, and a circulating current does not flow even by connecting wires in parallel. Therefore, it is possible to form a two-star wire connection of two parallels or a four-star wire connection of four parallels, by appropriately cutting the crossover between the respective phase coils.
On the other hand, FIG. 14 shows a configuration of a brushless motor 901 having fourteen poles and twelve slots, and FIG. 15 is a schematic view showing a coil polarity thereof. Magnets 96 disposed in a periphery of a rotor 95 are arranged in 14 poles at a uniform interval in a circumferential direction such that N poles and S poles are alternately formed. On the contrary, a stator 97 has a structure such that 12 coils 98a to 98l are arranged at a uniform interval in a circumferential direction so as to surround the rotor 95 as in the stator 92. However, a coil polarity is different from the stator 92. In detail, as shown in FIG. 14, the coils 98a, 98b, 98g and 98h are arranged so as to form the U phase in which the coils 98a and 98h and the coils 98b and 98g form unlike poles, the coils 98c, 98d, 98i and 98j are arranged so as to form the V phase in which the coils 98c and 98j and the coils 98d and 98i form unlike poles, and the coils 98e, 98f, 98k and 98l are arranged so as to form the W phase in which the coils 98e and 98l and the coils 98f and 98k form unlike poles. This arrangement is assumed to have the best motor efficiency in the brushless motor 901 having 14 poles and 12 slots. In this case, the unlike poles are expressed by with or without a mark "-" on the U, V and W phases in the figure. In the stator 97, in the respective coils 98a, 98b, 98g and 98h in the U phase, for example, the coils 98a and the coil 98b are not in conformity in the phase and the magnitude of the induction voltage but are shifted at 30 degrees, as shown in FIG. 15. Accordingly, if the coils 98a and the coil 98b are connected in parallel, the circulating current flows and the performance of the brushless motor 901 is lowered. Accordingly, as shown in FIG. 16, the coil 98a and the coil 98b, and the coil 98g and the coil 98h are connected in series, respectively. Because the coils 98a and 98b and the coils 98g and 98h connected in series are in conformity in the phase and the magnitude of the induction voltage, the coils are connected in parallel. Further, the other V phase and W phase are connected in the same manner, and the two-star wire connection as shown in the figure is formed.
In the case where the stator 97 is constituted, for example, by 12 divided cores, the continuous coil winding is executed by forming the crossover between two divided cores while changing the winding direction so as to wind the U-phase coils 98a and 98b connected in series in a clockwise direction around one divided core and to wind them in a counterclockwise direction around the other divided core, the continuous coil winding is executed by forming the crossover between two divided cores while changing the winding direction so as to wind the U-phase coils 98g and 98h connected in series in a clockwise direction around one divided core and to wind them in a counterclockwise direction around the other divided core, and the continuous coil winding is executed by forming the crossover in such a manner that the winding direction is inverted every two divided cores in the same manner as the U-phase, with regard to the V-phase coils 98c, 98d, 98i and 98j, and the W-phase coils 98e, 98f, 98k and 98l, as shown in FIG. 14. Accordingly, the divided cores 99a to 99l are coupled in the ring shape, and neutral points in the respective phases are connected. In this case, a circular mark in each of the coils 98a to 98l denotes a winding start of the coil winding, and a square mark denotes a winding end of the coil winding in FIG. 14.
In the stator 97, a so-called flyer-type or nozzle-type coil winding machine is employed for a coil winding work around the divided core or the like. However, taking into consideration a property of the coil winding machine and a simplification of the coil winding work such as a process of the crossover or the like, it is preferable that the continuous coil winding is executed in the same winding direction. Further, taking into consideration an assembling work of the stator 97 and the simplification of the coil winding work, it is preferable to continuously wind the divided cores or the like as many as possible. However, as exemplified by the brushless motor 901 having 14 poles and 12 slots, if coils of the same phase have the arrangement in which the phase and the magnitude of the induction voltage are different, the coils capable of being connected in parallel are limited. Further, if the coils connected in series have unlike poles, the winding direction of the continuously wound coils is inverted. In such a stator, it is impossible to continuously wind all the divided core or the like of the same phase, and it is impossible to make the winding directions of the continuously wound coils identical.
Further, it is necessary to execute the process of the crossover after forming the crossover between the coils so as to continuously wind around the divided cores or the like, and assembling the divided cores or the like as the stator. Herein, as shown in the stator 97, the crossover between the adjacently arranged coils such as the continuously wound coils 98a and 98b, protrudes in an axial direction of the stator 97 from the coils 98a and 98b, and the size of the brushless motor 901 is enlarged at the space corresponding to the protruding amount of the crossover. However, the layout of the divided cores or the like at a time of assembling is deteriorated and the assembling work is difficult to be executed in the case that the length of the crossover is shortened; therefore, it is impossible to make the crossover too short. Further, the thick coil wire is used in the motor having a high torque; therefore, the crossover becomes thick, and a great force is required for forming the crossover bent in the U shape at the adjacent positions such as the coils 98a and 98b so as to appropriately receive the crossover for space saving, so that it is hard to work by a human power.


A frequency switching circuit is controlled by a low address strobe signal XRAS. A sub-boosted power supply generating circuit is driven at a low frequency generated by a first oscillating circuit during the standby of a DRAM, and at a high frequency generated by a second oscillating circuit during the operation of the DRAM. The sub-boosted power supply generating circuit is driven in a shorter cycle during the operation than during the standby. Consequently, charges are supplied to a booster power source to boost the voltage level thereof. Accordingly, even if the period of the operation state is increased, a drop in voltage level of the boosted power supply caused by a transistor off leak current and a junction leak current can be controlled. Thus, the malfunction of a circuit can be prevented from occurring due to the drop in voltage level of the boosted power supply. The drop in voltage level of the boosted power supply can be controlled during the operation of the DRAM so that it is possible to implement a boosted power supply generating circuit which can prevent the malfunction of the circuit from occurring.

The present invention relates to a semiconductor integrated circuit comprising a boosted power supply generating circuit which supplies charges to an internal boosted power supply in a DRAM or the like.
Recently, the capacity of a dynamic RAM (hereinafter referred to as a DRAM) has been increased so that the area of a semiconductor chip has become greater. An increase in chip size is the minus factor of a gain in speed of the access time of the DRAM. A continuous boosting method has been employed as the technology for realizing the gain in speed of the DRAM. The continuous boosting method serves to increase the speed of the operation of the DRAM and is very effective in the extension of a pause time, the enlargement of an operating margin during sense and the like by setting the level of a word line to a boost level in the same manner as a boosting method according to the prior art.
For example, Japanese Laid-Open Patent No. 4-301998 has disclosed the boost technology using the continuous boosting method.
An example of a boosted power supply generating circuit according to the prior art will be described below with reference to the drawings. FIG. 13 is a block diagram schematically showing a boosted power supply generating circuit 100 according to the prior art. In FIG. 13, 101 designates a level detecting circuit, 102 designates an oscillating circuit, 103 designates a sub-boosted power supply generating circuit, 104 and 105 designate a main boosted power supply generating circuit and a potential limiting circuit for operating on receipt of a low address strobe signal (hereinafter referred to as XRAS) respectively, and 106 designates a boosted power supply. The sub-boosted power supply generating circuit 103 continuously operates so as to hold the voltage level of the boosted power supply 106 to a proper level during the standby of a DRAM. In order to reduce power consumption during the standby, a charge supply capability is set lower. The main boosted power supply generating circuit 104 operates only during the operation of the DRAM. A lot of circuits connected to the boosted power supply 106 operate during the operation of the DRAM so that the charges of the boosted power supply 106 are consumed. Consequently, the charge supply capability of the main boosted power supply generating circuit 104 is set higher.
FIG. 9 is an electric circuit diagram showing the detailed structure of the level detecting circuit 101, the oscillating circuit 102 and the sub-boosted power supply generating circuit 103 shown in FIG. 13. As shown in FIG. 9, the level detecting circuit 101 is connected to the oscillating circuit 102 by a control signal line 143 for transmitting a control signal. The control signal line 143 is connected to an input terminal 142 and a node 110 of the level detecting circuit 101 through a NAND circuit. The oscillating circuit 102 is connected to the sub-boosted power supply generating circuit 103 through signal lines 145 and 146. The sub-boosted power supply generating circuit 103 is connected to the level detecting circuit 101 through the boosted power supply 106.
The level detecting circuit 101 generates a control signal for controlling the oscillating circuit 102 based on the voltage level of the boosted power supply 106. The control signal is input to the oscillating circuit 102 through the node 110 and the signal line 143. A NAND circuit, an inverter, a MOS transistor, a NOR circuit and the like are provided in the oscillating circuit 102. The oscillating circuit 102 operates on receipt of the control signal sent from the level detecting circuit 101.
The circuit shown in FIG. 9 has a structure in which an input to the input terminal 142 is set to the "H" level, the voltage level of the boosted power supply 106 is detected by the level detecting circuit 101, and the result thus obtained is reflected in the voltage level (H or L) of the control signal line 143 so that the operation and non-operation of the oscillating circuit 102 are controlled. If the voltage level of the boosted power supply 106 is higher than a set voltage level, the output signal of the node 110 of the level detecting circuit 101 has the "L" level. Consequently, the control signal of the control signal line 143 sent to the oscillating circuit 102 has the "L" level so that the oscillating circuit 102 does not operate. Accordingly, an oscillating signal is not input to the signal lines 145 and 146 so that the subboosted power supply generating circuit 103 does not operate. On the contrary, if the voltage level of the boosted power supply 106 is lower than the set voltage level, the output signal of the node 110 of the level detecting circuit 101 has the "H" level. Accordingly, the control signal of the control signal line 143 has the "H" level so that the oscillating circuit 102 operates. Then, the sub-boosted power supply generating circuit 103 operates so that an oscillating signal is output to the signal lines 145 and 146. The voltage level of the internal side plate of a capacitor 131 (or the internal side plate of a capacitor 132) of the sub-boosted power supply generating circuit 103 is boosted by the voltage level of the capacitor 131 (or the capacitor 132) in response to the. oscillating signal so that charges are supplied to the boosted power supply 106 through a boost power line 147. Consequently, the voltage level of the boosted power supply 106 is boosted.
Recently, members forming an element have become thinner remarkably with the finer structure of the DRAM. For this reason, the potential limiting circuit 105 shown in FIG. 13 is provided in order to limit a voltage applied to the element and ensure the responsibility of the element. The potential limiting circuit 105 limits the voltage level of the boosted power supply 106 to a voltage level which is higher than a predetermined first power level by the threshold voltage of a memory cell transistor.
FIG. 10 is a circuit diagram for explaining the operation of the potential limiting circuit 105. As shown in FIG. 10., the potential limiting circuit 105 comprises a level shift portion 151 and a charge drawing portion 152. A control signal is input to the level shift portion 151 through an input terminal 153. An output which is level-converted by the level shift portion 151 is input to the charge drawing portion 152 through a signal line 154. An NMOS transistor 155 having a threshold voltage which is almost equal to that of the memory cell transistor is provided on the charge drawing portion 152. The NMOS transistor 155 is provided between the boosted power supply 106 and a first power source 156, and the gate of the NMOS transistor 155 is connected to the signal line 154. When the control signal input from the input terminal 153 has the "L" level, the output of the level shift portion 151 is set to the voltage level of the boosted power supply 106, the NMOS transistor 155 is turned ON, and the charges of the boosted power supply 106 are drawn to the first power source 156 so as to lower the voltage level of the boosted power supply 106 to a voltage level (set value) which is higher than the voltage level of the first power source 156 by the threshold voltage of the NMOS transistor 155. It is concerned that the voltage level of the first power source 156 is varied by drawing the charges toward the first power source 156. However, circuits for consuming the charges are connected to the first power source 156 and operates to consume the charges so that the voltage level is kept stable.
The general operation of the boosted power supply generating circuit 100 having each portion formed in the above manner will be described below with reference to FIG. 13 and the like.
When XRAS has the "H" level, that is, during the standby of the DRAM, the oscillating circuit 102 operates on receipt of a signal output from the level detecting circuit 101 so that the sub-boosted power supply generating circuit 103 is driven if the voltage level of the boosted power supply 106 is lower than the detection level of the level detecting circuit 101. Consequently, the charges are supplied to the boosted power supply 106 so that the voltage level of the boosted power supply 106 is boosted. If the voltage level of the boosted power supply 106 is higher than the detection level, the oscillating circuit 102 does not operate. Consequently, the sub-boosted power supply generating circuit 103 is not driven. In this case, the main boosted power supply generating circuit 104 and the potential limiting circuit 105 do not operate.
When XRAS is changed from the "H" level to the "L" level, that is, during the operation of the DRAM, the main boosted power supply generating circuit 104 is driven synchronously with the fall of XRAS. Consequently, the charges are supplied to the boosted power supply 106 so that the voltage level of the boosted power supply 106 is boosted. Consequently, the potential of a word line connected to the gate of the memory cell transistor which stores information is caused to rise. The main boosted power supply generating circuit 104 is driven only synchronously with the fall of XRAS. Hence, the main boosted power supply generating circuit 104 does not have the function of holding the voltage level of the boosted power supply 106. Accordingly, the sub-boosted power supply generating circuit 103 is caused to operate also during the operation of the DRAM so that the charges are supplied to the boosted power supply 106 to hold the voltage level. The main boosted power supply generating circuit 104 has the high charge supply capability. For this reason, there is a possibility that the voltage level of the boosted power supply 106 is increased too much. Consequently, the potential limiting circuit 105 is caused to operate synchronously with the fall of XRAS so that the charges of the boosted power supply 106 are drawn while XRAS has the "L" level. Thus, the voltage level of the boosted power supply 106 is lowered to a set value.
The operation of the output circuit of the DRAM connected to the boosted power supply 106 and the like will be described below with reference to FIG. 11.
As shown in FIG. 11, a control circuit 181 for outputting a control signal S2 on receipt of XRAS, a column address strobe signal (hereinafter referred to as XCAS), an output enable signal (hereinafter referred to as XOE) and a write enable signal (hereinafter referred to as XWE), a NAND circuit 183 for executing the NAND operation of the control signal S2 and an output data signal, and an AND circuit 184 for executing the AND operation of the control signal S2 and the inverted output data signal are provided on the input side of a boost circuit 182. An output circuit 108 is provided on the output side of the boost circuit 182. The output circuit 108 comprises NMOS transistors 185 and 186 connected between a first power source and a ground power source. The NMOS transistor 185 is controlled by the output of the boost circuit 182. The NMOS transistor 186 is controlled by the output of the AND circuit 184. Data is output to an output terminal 189 connected between the NMOS transistors 185 and 186.
FIG. 12 is a circuit diagram showing the internal structure of the boost circuit 182 in FIG. 11. The output of the NAND circuit 183 is sent to an input terminal 201 of the boost circuit 182. The input terminal 201 is connected to one of the electrodes of a capacitor 205 through an inverter 202, a delay circuit 203 and an inverter 204. The other electrode of the capacitor 205 is connected to an output terminal 208 for outputting a control signal to the NMOS transistor 185 of an output circuit. An NMOS transistor 206 is provided between the input terminal 201 and the output terminal 208. The gate electrode of the transistor 206 is connected to a first power source. Furthermore, an NMOS transistor 207 is provided between the input terminal 201 and the output terminal 208. The output of the inverter 202 is sent to the gate electrode of the transistor 207.
In the boost circuit 182 shown in FIG. 12, the output signal is set to the "L" level by the operation of the transistor 207 when the input signal has the "L" level. On the other hand, when the input signal is changed from the "L" level to the "H" level, the voltage level of the output signal is raised to the voltage level -Vth of the first power source by the operation of the transistor 206, wherein Vth is the threshold voltage of the transistor 206.
At this moment, the output of the inverter 204 has the "L" level. For this reason, the capacitor 205 is charged to VDD-Vth. After a delay time determined by the delay circuit 203, the inverter 204 raises the potential of one of the electrodes of the capacitor 205. Consequently, the voltage level of an output signal is set to VDD+.alpha. (.alpha.>0). In other words, when a signal input to the boost circuit 182 is set to the "H" level, the output signal of the boost circuit 182 is set to a higher boost level than that of the input signal.
Referring to the circuit shown in FIG. 11, when the data reading operation is determined, the gate of the NMOS transistor 185 is set to the "L" level by the boost circuit 182 and the gate of the NMOS transistor 186 is set to the "H" level by the AND circuit 184 if an output data signal has the "L" level. Accordingly, the NMOS transistor 185 is turned OFF and the NMOS transistor 186 is turned ON so that Low data is output to the output terminal 189. If the output data signal has the "H" level, the gate of the NMOS transistor 185 is set to a boost level by the boost circuit 182 and the gate of the NMOS transistor 186 is set to the "L" level by the AND circuit 184. Accordingly, the NMOS transistor 185 is turned ON and the NMOS transistor 186 is turned OFF so that High data is input to the output terminal 189.
When outputting the High data, the following problems arise if the gate of the NMOS transistor 185 is not set to a boost voltage. When setting the voltage level of the first power source to VDD and outputting the High data, only the voltage level VDD-Vth is output to the output terminal 189 if the voltage level of the gate of the NMOS transistor 185 is VDD and the threshold voltage of the NMOS transistor 185 is set to Vth. In the case where the potential of the gate of the NMOS transistor 185 is set to a boost voltage VDD+Vth, the voltage level of the output terminal 189 is set to a voltage level of VDD+Vth-Vth=VDD so that the sufficient High data can be obtained. In the output circuit of the DRAM, thus, the gate terminal of the NMOS transistor 185 is set to the boost voltage so that the sufficient High data can be output when reading the High data.
However, the above structure has the following problems.
A first problem will be described below. When XRAS has the "L" level, that is, in operation mode, a junction leak current and a transistor off leak current are generated on a junction portion and a transistor connected to the boosted power supply 106. Consequently, if charge consumption exceeds the charge supply capability of the sub-boosted power supply generating circuit 103, the voltage level of the boosted power supply 106 is gradually decreased. In particular, when the period for which XRAS has the "L" level is longer, the voltage level of the boosted power supply 106 is greatly lowered because the charges are not supplied from the main boosted power supply generating circuit 103. For this reason, there is a possibility that a malfunction occurs to a circuit due to the restore of information in the XRAS cycle, the shortage of a write voltage and the shortage of a read voltage in the next XRAS cycle.
A second problem will be described below. When the potential limiting circuit 105 operates synchronously with the fall of XRAS, the charges are drawn from the boosted power supply 106 before the charges of the boosted power supply 106 are consumed by the rise of the word line. For this reason, when or after the word line rises, the charges should be supplied to the boosted power supply 106 again. Consequently, there is a possibility that useless power consumption is increased or the rising operation of the word line is delayed.
A third problem will be described below. When reading the data, the gate terminal of the NMOS transistor 185 of the output circuit 108 is boosted after the reading operation is determined and it is decided that the output data is High data. In addition, the boost circuit has a delay circuit. Consequently, it takes a long time to read the High data.


A vertically adjustable armrest assembly for a chair having a hydraulic actuator that allows the upper arm of the chair to be raised to a multiple of positions by engaging the hydraulic actuator with a lever located on the underside of the upper arm. The upper arm may also rotate about a horizontal axis allowing the user to orient the upper arm to the most comfortable position for keyboarding.

Various chairs and armrest assemblies have been designed to support a user's forearm and wrist and can be adjusted vertically. However many of these supports only allow for limited movement of the armrest and requires a great deal of pressure to adjust vertically.
For example, U.S. Pat. No. 4,270,798 issued on Jun. 2, 1991 to Coach & Car Equipment Corporation, discloses an armrest which is pivotable through a vertical plane between a horizontally extending, arm-supporting position and an upwardly extending position alongside the seat back. The armrest is also pivotable, in response to a predetermined outwardly directed force against the armrest, through a horizontal plane, between the above-described arm-supporting position and a position in which the armrest extends rearwardly from the seat back.
U.S. Pat. No. 4,429,918 which issued on Feb. 7, 1984 to Syntex (U.S.A.) Inc. relates to an operatory stool.
U.S. Pat. No. 4,438,975 issued to Dentsply Research & Development Corp. on Mar. 27, 1984 relates to a post relatively fixed with respect to seat 16, unless vertical adjustment is desired by means of the hand screw.
U.S. Pat. No. 5,382,079 was issued on Jan. 17, 1995 to Chromcraft Revington, Inc. relates to the adjustable arm including an arm body having an upper housing and a sleeve portion which is slidably mounted on the generally vertical section of the arm frame assembly for vertical adjustment of the chair arm. A latching assembly is connected to the frame assembly and arm body for releasably locking the arm body in a plurality of vertical positions on the frame assembly. Lastly, an actuator, integral with the latching assembly, is provided for disabling the latching assembly.
U.S. Pat. No. 5,393,124 issued to Gary K. Neil on Feb. 28, 1995 relates to an armrest assembly for a chair comprising, an upper arm, support shaft structure associated with the upper arm, the support shaft presenting an axis of rotation for rotational movement of the upper arm, a structure associated with the chair for receiving the support shaft for relative rotational movement of the upper arm relative the receiving structure about the axis, and a structure for radially rotating the position of the upper arm about the axis of rotation to multiple positions as required for the user's comfort.
U.S. Pat. No. 4,907,835 issued on Mar. 13, 1990 to Charles Salter relates to a removable arm rest apparatus for use in a truck cab utilizing an upright tubing structure and a flat arm support member projecting normally outward therefrom.
U.S. Pat. No. 4,917,438 issued on Apr. 17, 1990 to Flight Equipment & Engineering Limited relates to an adjustable-width seating for passenger-carrying vehicles.
U.S. Pat. No. 5,439,267 issued on Aug. 8, 1995 to Steelcase Inc. relates to a chair including a tubular arm support, an armrest, a lateral adjustment mechanism and a vertical height adjustment mechanism. The lateral adjustment mechanism includes a plurality of nested slides. One slide is connected to the vertical height adjustment mechanism. An uppermost slide supports the arm rest. The slides are adjustable laterally with respect to each other to position the armrest with respect to the chair. The vertical height adjustment mechanism includes a tubular liner insertable into the arm support. The liner defines a bore and a plurality of vertically spaced notches or grooves. A latch tube telescopes with the bore of the liner. An upper end of the latch tube is connected to the lateral adjustment mechanism. The latch is pivotally positioned within the latch tube. The latch includes a latch end moveable into and out of engagement with the notches. An actuator engages the latch to move it between locked and unlocked positions.
U.S. Pat. No. 3,339,873 issued on Sep. 5, 1967 to D. H. Hale relates to a stool with a vertically moveable seat wherein a tank disposed under the seat at the top of a hollow reciprocable piston rod and containing air under pressure to accommodate, upon opening a valve between the hollow interior of the piston rod and the interior of the surrounding cylinder by actuation of a plate under the seat above the tank, (a) elevation of the piston rod, the actuating table, the seat and the tank, when the seat is not occupied, by a flow of fluid from the interior of the piston rod through and around a disc flow control into the interior of the cylinder under force of said pressure, and (b) lowering of the piston rod, the actuating plate, the seat and the tank, when the seat is occupied, by flow of fluid from the interior of the cylinder through the disc flow control to the hollow interior of the piston rod counter to said pressure.
U.S. Pat. No. 3,547,394 issued on Dec. 15, 1970, to Cramer Industries, Inc. relates to vertically adjustable articles of furniture and more particularly to an apparatus for adjusting the height of a chair seat.
U.S. Pat. No. 3,711,054 issued to Fritz Bauer on Jan. 16, 1973 relates to a lifting device for the stepless height adjustment of the seat surface member of a chair, stool or the like.
U.S. Pat. No. 4,940,202 issued on Jul. 10, 1990 to Stabilus GmbH relates to a stepless adjustable vertical movement device for chairs, tables or the like articles, which comprises a blockable gas spring which is arranged in a telescopic unit consisting of a telescopic tube and a guide tube and is connected by means of a self-locking taper connection on the one hand with the chair seat or a similar article of adjustable height and on the other hand with a foot part, a simple replacement of the gas spring is to be provided, with security against unintended unscrewing of the gas spring is guaranteed.
U.S. Pat. No. 4,940,202 issued on Nov. 13, 1990 to Suspa Compart Aktiengesellschaft relates to an adjustable-length column for chairs, tables or the like having an upright tube and a gas spring disposed in it. The piston rod of the gas spring is supported against a bottom plate of the upright tube. To assure support of the bottom plate in the face of extremely strong forces in the axial direction of the column at little manufacturing expense, the rim of the upright tube is bent inward approximately semicircularly in cross section. The bottom plate is supported on the end face of the rim.
Each of the prior art devices referred to above present relatively complicated structures having relatively limited mobility of the armrest. Large forces are also required to activate the adjustable-length columns that are located in the seat portions of many of the prior art devices. An advantage to the present invention is the ease in which the armrest assembly can be manufactured, assembled and repaired due to the lack of complexity of the structures. Another advantage is that the amount of pressure that is required to activate the armrest assembly is dramatically reduced, thereby requiring the user to exert only a minimal force for the armrest to be activated.

Vertically adjustable armrest assembly for a chair


A memory system is able to simultaneously access multiple rows in page mode operation. The multiple page memory includes a memory array with multiple internal read registers to improve the effective page cycle time. The multiple page memory of this invention is very effective in graphics applications where multiple page memory access is required. A memory with multiple page random access in accordance with this invention greatly enhances performance by allowing different sources to continue to access the memory in the page mode, in spite of intervening memory accesses by other sources to other rows of the memory. A VRAM with multiple page random access in accordance with this invention provides an even higher performance graphic memory system.

Computer systems and memory systems are well known, and it has been a continuing struggle to provide memory systems with sufficient capacity and sufficient bandwidth to service their associated CPUs and other system components. In a simple computer system, the CPU accesses either memory (such as semiconductor memory, such as static RAMS or dynamic RAMS), and mass storage space, such as disc drives. With increasing speeds available in modern CPUs and peripheral devices such as graphic controllers and direct memory access (DMA) controllers, more and more manipulation is performed in memory, rather than mass storage, due to the significantly greater access speed, and thus bandwidth, of semiconductor memories. Furthermore, with increasing system speed and a greater number of system components capable of reading and writing to the same memory, memory bandwidth requirements have increased dramatically over time. This increased demand placed upon the memory is particularly acute with respect to graphical applications, which over time has significantly increased in resolution and color depth.
With higher resolution and more color depth, the bandwidth requirement for a graphic memory system is tremendous. Prior art graphic memory system architecture typically consists of two sources competing for the memory bus, as shown in the block diagram of FIG. 1. In order to access that portion of the memory which stores the information associated with screen video, that portion of the memory being referred to as the video frame buffer. These two sources competing for the memory bus with respect to graphical needs are the memory reads required for screen refresh, and the memory read/write cycles initiated by the CPU to access the video frame buffer to update the contents of the video frame buffer (or other graphical device.)
To alleviate the competition for the memory bus, the Video RAM (VRAM) was created, which includes a parallel-in/serial-out data register connected to a second data port, and including its own data clock. This second port allows data to be transferred out of the chip at high speed, for example to control the video display, and occurs in parallel with normal reads from and writes to the VRAM, thereby allowing the CPU or other graphical devices to simultaneously manipulate the data within the VRAM without contention problems. Video RAMS are described, for example, in Computer Graphics Principles and Practice, 2nd ed., Foley, van Dam, Finer and Hughes, Addison-Wesley Publishing Co., 1992, pp. 856-862, Section 18.1.4.
DRAM is also usable as a graphic memory when there is an adequate buffer (FIFO) used for screen refresh as well as read ahead and write buffers for the CPU reads and writes. When using DRAM as a graphic memory, buffering is used to allow the DRAM to operate in the page mode as much as possible. When operating a DRAM, a row address is first strobed into the device, followed by a column address, as described in Computer Graphics Principles and Practice, 2nd ed., Foley, van Dam,--Finer and Hughes, Addison-Wesley Publishing Co., 1992, pp. 856-862, Section 18.1.2. A row address defines a plurality of words contained on that row, which plurality of data words can be read out sequentially utilizing a plurality of column addresses, strobes without a requirement for an additional row address strobe. Thus, the plurality of words contained within a row can be quickly read out of the DRAM operating in the page mode (i.e. the words contained in a single ram of the DRAM are all contained on the same "page".) When operating a DRAM in the page mode the number of consecutive page cycles possible depends on the depth of the FIFO, (i.e. the number of words within a row which can be stored in FIFO in response to "a RAS" strobe.) Furthermore, when using a DRAM in the page mode, random cycle (RAS strobe) will most likely be required each time a new source takes over the memory bus or there is a switch from a CPU read operation to a CPU write operation.
More recently, in addition to the CPU being capable of accessing the video buffer, as well as the screen refresh circuitry, certain graphic memory systems include a dedicated graphic engine to draw directly into the memory introducing a third source to compete for the memory bus. As depicted in FIG. 2, such a DRAM system 200 includes DRAM 201, memory controller 210, and a plurality of devices interfacing with memory controller 210. Such devices which compete for DRAM 201 bandwidth, include CRT refresh circuitry 221, CPU 222, graphical engine 223, and video drivers 224. Graphic engine 223 can typically operate on two areas of the memory at the same time (a source and a destination), thus these engines effectively add two sources which compete for the memory bus: a source read operation and destination read/write operation. Once again, these graphic memory systems operate in the page mode in order to improve memory bus bandwidth, utilizing FIFOs for each read source or write source. However, switching between sources still most likely will require a random cycle (RAS Strobe), with its attendant decrease in memory bus bandwidth.
Today's graphic systems mix graphic with video, introducing another source to compete for the graphic memory bus bandwidth, the video. Video itself can also be considered as two sources, one to update the video portion of the frame buffer, while the second, depending on implementation, is to fetch the video data to display or to fetch some sort of mask for updating and/or displaying the video data. In addition, today's graphic engines can operate on more than just two maps (source and destination), sometimes up to four maps (source, pattern, mask and destination). As shown in FIG. 2, a dedicated FIFO is required for each source, and more random cycles are encountered with each switch between the possible sources requiring access to the memory bus, effectively reducing the total bandwidth of the graphic memory system.
Due to the high bandwidth high color depth requirements, today's graphic system usually employs a 64-bit bus architecture and requires from 2 to 4 Megabytes of memory. A cost effective memory system should have low chip count, be quite flexible and upgradable. Thus, wide and shallow memories are preferred over narrow and deep memories. To increase bandwidth, faster page cycle is always the most important criteria. Maintaining page cycle is the next most important criteria. Graphic controllers can improve the likelihood that page mode operation can be maintained by the use of multiple (or wider) FIFOs to store more words when a memory row is accessed, but this can be extremely costly, especially when each FIFO is 64-bit wide and there are FIFOs used with each source. Therefore, some major improvement in graphic memory systems is highly desirable.
A DRAM can be accessed in page mode for one row at a time. Each time a new source claims the memory bus, a random access cycle is likely to be needed, since a different page of memory is almost certain to be accessed. This random access cycle is followed by one or more page cycles. The number of page cycles possible once a given page is selected by the random access cycle is the defined by the depth of the internal FIFO for that source of the graphic controller. When only one source is accessing the memory, then the maximum number of page cycles per row can be achieved. This number is limited to the number of columns in the memory array.
Traditional DRAM uses only one sense amplifier per memory core to store the selected row data, as shown in FIG. 2. "Sense amplifier register" register 202, which acts as a cache line for memory array 203, can typically be accessed three times faster than a random access cycle of memory array 203. For a 256 k.times.16 DRAM, the cache line size is typically 512.times.16. Since there is only one line of cache available, the hit rate for this architecture is very low especially when multiple row addresses are accessed.
Memory interleaving is one prior art technique that can improve page cycle utilization with the conventional DRAM, by increasing the number of cache lines (FIG. 3). In this example, the memory array is divided into two integrated circuits serving as 4 megabit memory arrays 303-even and 303-odd, respectively, each having a 512.times.16 sense amplifier (row) register serving as a cache line. The two cache lines increase the hit rate significantly when alternate row address from the two memory arrays are accessed. However, when the two rows of data are accessed from the same memory array, the hit ratio is the same as that of the traditional DPAM architecture.
Memory interleaving can double the maximum number of page cycles per row, since even and odd display lines are assigned to opposite memory banks, and accessing between consecutive lines can remain in page cycle. When there is a page miss, the RAS precharge time can be hidden if accessing alternates banks.
Memory interleaving, however, still has many disadvantages: it requires more memory, multiple accesses to the even or odd display lines still result in page miss, and interleaving still does not address the likelihood of a page miss whern there is a change of the source of accessing memory (i.e. graphic controller requests data from two different locations of the even line or odd line bank would likely cause a page miss).
FIG. 4 is a block diagram of a prior art memory circuit including memory controller 210, memory bus 211, and dual page memory 401. Dual page memory includes two memory array banks 401-1 and 401-2, each having an associated sense amplifier register 402-1 and 402-2, respectively. In this prior art circuit 400, dual page memory 401 is formed as a single integrated circuit organized into two discrete memory array banks 401-1 and 401-2, with sense amplifier register 402-1 being dedicated to reading and storing data associated with the first data array page 401-1. Similarly, sense amplifier 402-2 is dedicated to reading and storing information associated with the second data array page 401-2. This prior art memory circuit improves bandwidth somewhat, as a page of memory can be stored from first memory array bank 401-1 for subsequent page reads from sense amplifier 402-1 without interfering with similar page reads from sense amplifier register 402-2 with respect to data obtained from memory array bank 401-2. However, whenever a new page stored within either one memory array banks 401-1 and 401-2 is to be accessed, memory device 401 will have a page miss, requiring a RAS operation to load that new page into the appropriate one of the sense amplifier registers 402-1 and 402-2. An extension of this architecture is to further divide the main core to smaller cores. This reduces the chance of cache "miss". This implementation is very similar to increase the cache size in direct map cache.


Such a displaying device that can be easily operated by aged persons and handicapped persons, and an image forming apparatus using the same will be provided. Upon continuously operating an upper button for the predetermined period of time, a set value of a magnification is changed at intervals of numeric change that are different from each other between a voice guide mode activated by a voice guide button and a normal mode. At this time, it is configured in such a manner that the interval of numeric change for the normal mode is smaller than the interval of numeric change for the voice guide mode, i.e., the changing rate of the set value of the magnification for the normal mode is larger than that for the voice guide mode.

1. Field of the Invention
The present invention relates to a displaying device and an image forming apparatus, and in particular, it relates to a displaying device that can be applied to an image forming apparatus, such as a duplicator, a printer and a facsimile, and an image forming apparatus.
2. Description of the Related Art
In recent years, it has been called for urgent attention, associated with the forthcoming aging society, to enhance office environments as social infrastructure where aged persons and handicapped persons can work equivalently to the robust.
In a displaying device of an image forming apparatus, such as a duplicator, a printer and a facsimile, on the other hand, such a constitution is employed for reducing the operation time and for improving the operationally upon configuring the magnification in that the unit value upon changing the displayed magnification is changed corresponding to the time for operating the configuring key.
For example, as proposed in the technique described in JP-A-61-148462, in a magnification configuring method of a duplicator where the duplication magnification is continuously changed during the period, on which the magnification configuring key is being pressed, the period of time, on which the magnification configuring key is being pressed is detected, and associated with the increase of the period of time, the changing amount of the duplication magnification per unit time is increased. Accordingly, the changing amount of the duplication magnification per unit time is increased corresponding to the period of time, on which the magnification configuring key is being pressed, whereby the time required for obtaining the desired magnification can be reduced to improve convenience on operation.
Furthermore, as proposed in the technique described in Japanese Patent No. 2,577,400, in a numeric value configuring method for configuring a numeric value, such as a magnification of a duplicator, while the numeric value is displayed with a displaying unit, the change of the displayed numeric value started upon pressing a numeric value change instructing unit is continuous change by the minimum changing unit during the period starting from pressing the numeric value change instructing unit for a prescribed time, and thereafter, it is totally or partially discontinuous change by plurality of the minimum changing units, whereby the changing rate of the displayed numeric value on the continuous change is the same as that on the discontinuous change, or in alternative, that on the continuous change is larger than that on the discontinuous change. According to the manner of configuring a numeric value, the time required for obtaining the desired magnification can be reduced to improve convenience on operation as similar to the aforementioned technique.
However, there are increasing tendencies that the operation of the image forming apparatus is complicated, and thus, the operation of the apparatus involves difficulties.
In particular, an up and down button frequently used on an operation panel of the current image forming apparatus described in the foregoing has such a specification that is difficult to be used by aged persons and handicapped persons, in which the increment unit time of data after continuous press of the button is shortened.

Displaying device and image forming apparatus


A safety tack has a pin that is extended from a head of the tack in one state and retracted into the head in another state. The pin retracts and extends into and from the head by using a turning mechanism similar to the mechanism that allows a bolt to turn into and out of a complementary component (e.g. a nut). By having the retracted state, the tack can be handled without injury; and by having the extended configuration, the tack can be used to tack one object to another.

Typically, tacks and pushpins have a similar structure in that they both have a head and a pin extending outwardly from the head. The head is typically spherical, cylindrical, or disk-like in shape.
Tacks and pushpins are convenient; however, they can become a hazard. For example, a tack or pushpin can easily go unnoticed on a floor or chair. This hazard is amplified in a busy classroom or workplace. Pushpins are also commonly a hazard for dressmakers and tailors, who handle large quantities of such items. Usually, a dressmaker or tailor will stick himself or herself when reaching for a pin in a container.
In an attempt to resolve the above-described hazards, pushpins and tacks with safety mechanisms (i.e. safety tacks) have been designed. For example, safety tacks are known and described in a number of United States patents (See U.S. Pat. No. 1,857,158; U.S. Pat. No. 2,518,977; U.S. Pat. No. 4,005,507; and U.S. Pat. No. 6,276,030). In the aforementioned patents, the safety tacks provide safety functionality through a spring-type safety mechanism. Unfortunately, a spring-type safety mechanism for retracting and extending a point of a pin in a tack is impractical to manufacture. U.S. Pat. No. 7,004,703 describes a safety tack with an interesting safety mechanism that is not of the spring-type variety. However, the tack disclosed in U.S. Pat. No. 7,004,703 discloses a tack that appears from its design to be flimsy and unable to withstand repetitive use.
Accordingly, there is a need for a safety tack that minimizes the chances of injury and is simple enough to make manufacturing of the tack practical from a cost perspective.


A deployable truss is formed from a plurality of column members connected at their ends where at least some of the column members are formed from column assemblies, each including a plurality of strut members that are at least connected to each other at a first and second end of the column assembly. For added rigidity, strut members of a column assembly may be connected to each other between the first and second ends using, for example, a rigidizable resin, a fixed spacer, or a deployable spacer. Connecting strut members between the ends of the column assembly provides mutual bracing to the strut members and decreases the free buckling length of the individual strut members. Spacers are preferably configured to radially space the strut members away from the longitudinal centerline of the column assembly to increase its moment of inertia, and hence its buckling strength.

Deployable structures made for use in space have generally been linearly deployed systems extended from a fixed base. These structures are commonly referred to as booms and can be divided into two categories: shell and lattice booms. Successful designs share traits of mass efficiency, low packaged volume, and reliability.
One specific type of a shell boom, referred to as a STEM in the space industry, for Storable Tubular Extendable Member, is disclosed in U.S. Pat. No. 3,144,104. A STEM, which typically incorporates a coilable thin metal strip, such as shown in the figures of U.S. Pat. No. 3,144,104, are precurved and form a cylindrical shell when deploying. These devices have found use in low load applications such as antennas and gravity gradient stabilization booms due to their compactness.
In general, a cylindrical shell, or tube, is a simple and mass efficient structure. However, STEMs have strength limitations since the deployed metal strip does not form a closed section. Multiple overlapped STEMs, such as those shown in various figures of U.S. Pat. No. 3,434,674 and methods of interlocking the overlapped section(s) (see, e.g., FIG. 8 of U.S. Pat. No. 3,144,104) have been pursued to increase strength.
STEMs are also limited in utility due to susceptibility to thermally induced bending. In space applications, one side of the STEM can be heated by solar radiation while the other side of the STEM would be shielded from solar radiation by the first side of the STEM. Such inconsistent heating could cause the side of the STEM receiving the solar radiation to expand more than the shielded side of the STEM, resulting in thermal induced bending, and distortion, of the STEM. Distortions in booms are generally undesirable and, in particular, distortions can reduce axial load capability.
A boom loaded axially, as a column, must be very straight to obtain full load capability. In practice, therefore, the ratio of the length to diameter of a boom is generally kept below the point where factors such as manufacturing straightness errors, thermal bending, and unintended minor load eccentricities leave the boom susceptible to collapse by buckling. While such factors will generally depend, at least in part, on the material system used to fabricate the boom, typically the length to diameter ratio of booms that are loaded as columns is maintained well below 80.
For long booms with moderate load and/or higher stiffness requirements, larger diameters are required to limit the slenderness ratio. However, using a boom comprised of a simple thin-walled cylinder will not be mass optimized, if the required wall thickness of the boom is greater than the optimal wall thickness required to meet stiffness requirements. This situation occurs when the optimal wall thickness required to meet stiffness concerns is so thin that the boom wall would have unreliable strength properties due to small manufacturing imperfections in the boom wall. Such imperfections are difficult to avoid and to predict. In addition, as optimum wall thickness decreases, such imperfections are more likely to initiate failure by local wall buckling from loads well below the bulk properties of the material being used to fabricate the boom. This limits the usefulness of thin-walled tubular shell booms, such as STEMs, and is one impetus for using a range of lattice type boom structures in space applications.
A lattice boom typically comprises a number of axially arranged structural elements, which are frequently referred to as longerons. Typically, the longerons are braced in a repeating fashion at intervals often referred to as bays. The longerons are typically rods, or sometimes tubes, and are braced at close intervals to prevent slenderness concerns from arising at the bay level. Structural members used to perform the bracing function are often referred to as battens. Diagonals, or as also sometimes referred to as stays or cross-members, are typically provided along each face of the bays to add structural rigidity. Diagonals, for example, may be in the form of crossing cables, each bearing tension only, or one or more rigid structural members capable of bearing both tension and compression.
One bay of a typical collapsible four-sided lattice structure is shown in FIG. 1 of U.S. Pat. No. 5,016,418, issuing to Rhodes et al., the disclosure of which is hereby incorporated by reference. Each bay, or structural unit, is constructed of structural members connected with hinged and fixed connections at connection nodes in each corner of the bay. Diagonal members along each face of the bay provide structural rigidity and are equipped with mid-length, self-locking hinges to allow the structure to collapse. Many other clever schemes for the articulated folding of repeating bay booms, or truss structures, have been arranged.
For example, U.S. Pat. No. 4,475,323, issuing to Schwartzberg et al., which is incorporated herein by reference, discloses a deployable box truss hoop. U.S. Pat. No. 4,557,097 to Mikulas, Jr. et al., which is also hereby incorporated by reference, discloses a sequentially deployable, maneuverable tetrahedral beam truss structure. U.S. Pat. No. 4,569,176 to Hedgepeth et al., hereby incorporated by reference, discloses a deployable lattice column having three sides and rigid diagonal members formed of rigid elements. U.S. Pat. No. 4,599,832 to Benton et al. ("Benton"), hereby incorporated by reference, discloses an extendible structure that can be collapsed to a shorter length and extended to a longer length. The extendible structure disclosed in Benton comprises a pair of station members interconnected by at least three longeron members. Each longeron member has two longeron elements that are pivoted together so they can fold toward one another or be aligned to form a column. Each longeron element is pivoted to a respective station member. Preloaded diagonal cable stays rigidify the structure when extended, being opposed by buckling springs (or Euler columns) that exert a radially outward resultant force in each bay at the folding point of each longeron member. The articulated lattice configuration disclosed in Benton was used to deploy the solar arrays on the international space station.
Another example of a repeating bay boom or truss structure comprised of collapsible bays formed from articulating members is provided in U.S. Pat. No. 4,677,803 to Mikulas, Jr. et al. ("Mikulas"), which is hereby incorporated by reference. The Mikulas patent discloses a deployable geodesic truss structure. The Mikulas geodesic truss structure includes a series of bays, each bay having sets of battens connected by longitudinal cross-members that give the bay its axial and torsional stiffness. The cross-members are hinged at their mid-point by a joint so that the cross-members are foldable for deployment or collapsing. Hinged longerons may also be provided to connect the sets of battens and to collapse for stowing with the rest of the truss structure. U.S. Pat. No. 5,267,424, issuing to Douglas, and which is hereby incorporated by reference, discloses a "bay" or, as referred to in the patent, a "module" for forming an articulated stowable and deployable mast. Further, U.S. Pat. No. 6,076,770 to Nygren et al., which is hereby incorporated by reference, discloses a folding truss that comprises a number of articulating column members.
Favored designs of articulated truss structures for space applications share traits of high performance in mass efficiency, low packaged volume, and reliability. Joint design is also important to performance of articulated truss structures since joints typically carry risks of reliability, increase the mass of the structure, and limit compaction.
An alternative lattice truss structure with joint-less longerons, and hence higher compaction and lower risk, is the coilable lattice truss boom. Numerous adaptations of this often employed structure exist. For example, U.S. Pat. No. 4,918,884 to Okazaki et al., which is hereby incorporated by reference, discloses an example of a coilable lattice truss that employs a plurality of radial spacers to define bays along a plurality of longerons arranged parallel to one another and attached to a pair of endplates. A pair of diagonal cords are stretched between adjacent radial spacers, between one of the end plates and the uppermost radial spacer and between the other of the end plates and the lowest radial spacer, respectively. A means is attached to one of the paired diagonal cords stretched between one of the end plates and the uppermost or lowest radial spacer to apply a predetermined tension to the diagonal cord. To collapse the truss structure, the longerons are elastically buckled between the radial spacers so as to coil the longerons between the endplates. The transforming of the longerons, and longitudinal position of the radial spacer located at one end of the structure, can be restrained by a means of applying overall axial tension while the structure is being deployed or collapsed. Other examples of coilable lattice truss booms are described in U.S. Pat. No. 3,486,279 to Webb for a deployable lattice column; U.S. Pat. No. 4,334,391 to Hedgepeth et al. for a redundant deployable lattice column; U.S. Pat. No. 4,532,742 to Miura for an extendible structure; and U.S. Pat. No. 5,094,046 to Preiswerk for a deployable mast.
Because the longerons in coilable lattice booms are highly strained when coiled for stowage, the material of choice for such longerons is typically a flexible glass fiber composite, such as an S2 glass fiber composite. As a result, in typical performance regimes, current coilable truss designs possess far in excess of a desirable amount of stowed strain energy, resulting in excessive push forces. This, in turn, requires the use of equipment sized to handle the resulting push force while the truss is in the stowed configuration, as well as when it is being deployed or collapsed. The required additional mass of the deployment mechanism to safely handle the push force of current coilable trusses adds parasitic mass and limits their overall mass efficiency.
Articulated and coilable lattice truss structures have been successful to date in providing low mass solutions to a wide array of lightly-loaded truss structures (relative to terrestrial structures) for use in space applications. But many potential space applications, including, for example, even more lightly loaded or "gossamer" applications and imaging mission applications requiring lightweight and stable structures, call for extendible structures having compaction, stability, and/or mass efficiency requirements that are outside the capabilities of existing structures or are not easily met by such structures. Accordingly, the ever increasingly challenging requirements for compaction, stability, and mass efficiency call for new generation extendible structure solutions.
High-performance graphite fiber composites potentially provide a huge gain in stiffness to weight capability over other available material options, such as flexible glass fiber composites, such as S2 glass fiber composites, and possess very low coefficients of thermal expansion. These are critical traits for future stable gossamer structures. Graphite fiber composite materials have limited applicability in known coilable lattice structures because graphite fiber composite materials have strain capabilities typically two to three times lower than glass fiber composite materials. Therefore, only much smaller, and hence weaker, longer rods can withstand the curvature encountered during stowage. The local buckling strength of a longeron is a function of the rod inertia, which is proportional to the diameter to the fourth power. This limits the utility of graphite composite longerons in currently practiced coilable lattice structure because the maximum diameter graphite longeron (approximately ⅓ that of an S2 glass fiber longeron) that can be used in known coilable structures would possess up to approximately 80 times less inertia. Even granting that a graphite rod is likely to be as much as 4 times stiffer in extensional modulus than a S2 rod, the buckling strength will still be 20 times lower than the heritage material (assuming equal column length).
Graphite fiber composite elements such as rods, and in larger structures, tubes, have been well utilized in articulated lattice structures in recent years. But, as always, the stacking of individual longeron elements restricts compaction capability because slenderness limits constrain the minimum realistic diameter of the longeron elements.
In recent years, numerous inflatable systems, which can use graphite fiber composites, have been under intense development in the hope that such systems would achieve a leap in mass and packaging efficiency, allowing ever larger systems to be packaged within the constraints of affordable launch systems. In practice, it has been difficult to achieve the structural efficiency of an articulated structure with an inflatable system due to mass overhead in non-structural systems such as: bladder materials, thermal barrier layers, node fittings, and inflation equipment and sequencing mechanisms. Inflatable systems are also plagued with structural inefficiencies inherent with the use of folding or rolling collapsed composite tubes. To allow the folding or rolling of collapsed composite tubes, the graphite material must be capable of withstanding high strain, requiring a reduction in fiber stiffness, fiber-to-matrix volume ratios, and/or the use of a woven fabric, which reduces the effective stiffness.
High performance tubular composite systems require composite tubes with maximum structural stiffness and high stability. Composite tubes achieve maximum structural efficiency when constructed from layered-fibers mostly oriented nearly axially to the lengthwise direction of the tube. The most stable composite tube lattice structure would be joined by bonding at composite nodes. However, such systems are not generally collapsible, although some have been proposed. One such proposed system is described in U.S. Pat. No. 6,321,503 to Warren. The mass efficiency of this system is high and the structure is stable, but the compaction ratio is poor. Allowing the tubes to be partially flattened, as described in U.S. Pat. No. 6,343,442 to Marks, increases the compaction, but it is still not satisfactory.
Inflatables, folded, and flattened lattice structures do not have precise kinematics and suffer from reduced stiffness and strength during deployment. Articulated lattice structures have precise kinematics that can be controlled by separate actuators and rate limiting devices. The reliability inherent in the heritage methods of deploying articulated lattice structures is also a key performance parameter. Reliability is another fundamental criteria in the creation of a desirable deployable structure for use in space applications, alongside mass efficiency, compact stowage performance, and stability.
A need, therefore, exists for deployable truss structures that improve on one or more of the above noted deficiencies of currently known deployable truss structures, yet maintain the reliable deployment characteristics of articulated and coilable lattice structures. Preferably, such truss structures would also improve on at least one of the attributes of mass efficiency, stowage volume, and thermal stability, and preferably all three. A need also exists for such structures that can make practical use of high-performance graphite fiber elements. A need further exists for column members that will enable improved deployable truss structures to be built.
An object of the present invention is to meet one or more of the foregoing needs.

Deployable truss having second order augmentation


A machine learning device, which detects an operator, communicates with a database registering information concerning the operator, and learns display of an operation menu based on the information concerning the operator, includes a state observation unit which observes an operation history of the operation menu; and a learning unit which learns the display of the operation menu on the basis of the operation history of the operation menu observed by the state observation unit.

1. Field of the Invention
The present invention relates to a machine learning device, a numerical controller, a machine tool system, a manufacturing system, and a machine learning method for learning display of an operation menu.
2. Description of the Related Art
Conventionally, for example, an NC (Numerical Control) device which controls a machine tool has an operation menu used by a variety of persons (operators). Examples of the operators include persons having various roles and authority levels, such as a developer and a person in charge of an MTB (Machine Tool Builder), an operator (user), and a field engineer.
In the present specification, the NC device also includes, e.g., a CNC (Computer Numerical Control) device. An operation menu for the NC device is displayed on a display device, such as a liquid crystal panel having a touch (position input) function, and is configured to change in accordance with the information displayed on the display device. A display device which displays an operation menu can be, for example, provided integrally with the NC device, but it may also be located at a position away from the NC device in a wired or wireless configuration, or an operation menu on a display device may even be operated in, e.g., the vicinity of a machine tool.
Conventionally, for example, a proposal has been presented to arrange function icons in a matrix as cells and rearrange the function icons in an arrangement desired by the user, in accordance with the numbers of times the icons are used (e.g., Japanese Laid-Open Patent Publication No. 2009-181501). Another proposal has been presented to rearrange menu items in an order suitable for the current user situation, without troubling the user, when a menu for a navigation device is displayed (e.g., Japanese Laid-Open Patent Publication No. 2010-127814). It is also possible to, e.g., set an authority level for an operator who operates a machine tool and change the operation menu in accordance with the authority level (e.g., Japanese Laid-Open Patent Publication No. 2009-086964).
As described above, simply performing arrangement in accordance with the numbers of times menus are used may, for example, result in poor access to a menu desired to be used when a person other than an operator who usually operates the machine, such as a field engineer, operates. A method for detecting an operator and then, for example, rearranging the menus in accordance with the numbers of times they are used for each operator may be possible, but in this case, to obtain a menu screen easy for the user to use, the operator may preferably operate the machine to a certain extent to make the machine perform learning.
When a table defining the order of display items of menus from parameters is prepared in advance to display a menu suitable for the circumstances involved, since changes from assumed circumstances may not be handled dynamically, it may be preferable to manually regenerate a table every time the role or the authority level of an operating person increases.
In consideration of the above-described problems of the conventional techniques, it is an object of the present invention to provide a machine learning device, a numerical controller, a machine tool system, a manufacturing system, and a machine learning method which can display an operation menu optimum for each operator.

Machine learning device, numerical controller, machine tool system, manufacturing system, and machine learning method for learning display of operation menu


A rope or line having a permanent loop of fixed diameter spliced in each end thereof provides for the suspension of innumerable articles in various industries, but is particularly well suited for use in underground mining, where it may be used to support continuous miner machine cables, electric, pneumatic, and hydraulic lines, air ventilation ducts, etc., above the floor of the mine drift. The line is preferably formed of a braided synthetic fiber which has been treated to provide flame retardant properties and which is also electrically non-conductive. Treated, braided polypropylene is a suitable material for the present double looped line. The closed loops are formed by passing the first end of the line diametrically through its opposite portion, and then coaxially through that same portion and diametrically through the portion captured within the hollow braided core to secure the first end therein and to form a closed loop. The second end portion of the line is worked in an identical manner to form an essentially identical second loop. This construction results in a braided line in which the spliced portions are pulled more tightly and securely together when tension is applied to the two opposite loops, thus producing more secure loops which cannot slip when tension is applied. The double looped line may also be provided with bright, contrasting colors for better visibility in areas of low light, as in the mining environment.

1. Field of the Invention
The present invention relates generally to article supports, hooks, loops, and etc., and more particularly to a hollow braided line formed of a length of preferably flame resistant and electrically non-conductive flexible material. The line includes a spliced loop formed at each end thereof, and is used to support and suspend articles such as electrical cables, pneumatic and hydraulic lines, ventilation ducts, etc. in the mining industry, and has further applications in many other industries such as suspending parts being painted from an overhead conveyor system, as well as other applications where good strength and resistance to flame and industrial chemicals is required.
2. Description of the Related Art
Many industries require some means of temporarily supporting or suspending various articles for various purposes, and often have need of a simple yet durable strap or loop which may be used as a hanger for various parts and components. Accordingly, various such devices have been developed in the past, but all have had one or more deficiencies which have rendered them unsuitable for use in demanding industries such as underground mining, where flame resistance, electrical non-conductivity, resistance to chemicals, and good strength, durability, and reliability are absolutely required.
In the past, the various devices manufactured for such purposes have not included all of the above properties, and moreover were not necessarily formed of highly visible materials providing for ease of visibility in darkened areas such as mines and the like. Moreover, such hanger loops, when formed of twisted or braided rope material, were often closed using means which were prone to slippage or damage, thus allowing the loop to open and release any articles being supported thereby. The present hollow braided line with double spliced loops responds to each of the above problems and deficiencies by using a suitable material, and forming a closed loop at each end of the line using that material, which loops are completely resistant to opening when strain is placed upon the line and its loops. A discussion of the related art of which the inventors are aware, and its differences and distinctions from the present invention, is provided below.
U.S. Pat. No. 330,087 issued on Nov. 10, 1885 to Leedham Binns describes an Endless Band Or Cord, comprising a single loop of hollow braided rope or the like which has been formed by inserting each of the opposite ends into the hollow braid opposite one another. The ends which are worked into the body of the rope or line are not interlocked with one another, and while Binns states that they cannot slip, experience has shown that such interwoven (but not interlocked) ends can slip, particularly in lines formed of synthetic materials having relatively low coefficients of friction. Moreover, Binns teaches away from the present double looped line, as he requires that both ends be used to form a single loop. The present invention requires that only a single end be interwoven with the standing portion of the line, thus allowing a loop to be formed at each end of a length of line.
U.S. Pat. No. 2,600,395 issued on Jun. 17, 1952 to John J. Domoj et al. describes a Keyhole Splice wherein the free end of the braided line is worked back through the standing end several times, by penetrating the standing end with a fid. The passages through the standing end are radially offset, so the free end weave through the standing end results in a spiral pattern. The free end does not pass back into the standing end to penetrate back through itself within the standing end, and to be captured within the standing end, as in the loops of the present double loop invention. Rather, the free end terminates outside the standing portion of the line, where it is subject to being snagged or caught on another object.
U.S. Pat. No. 4,962,929 issued on Oct. 16, 1990 to Eugene R. Melton, Jr. describes a Wrist Strap For Attracting An Item Of Sports Equipment To The Wrist. The Melton, Jr. strap is formed from a length of hollow braided line, with one end being inserted back into the hollow core of the free end or length to form a loop. This free end is then passed through the loop, which is left at least somewhat loose to form a configuration somewhat like a slip knot. In contrast, each loop of the present line with double spliced loops is formed by first passing one end of the line diametrically through the opposite portion, and then back through itself within and along the hollow core of the free portion of the line. The result is a loop which cannot slip, nor is any slippage desirable in the present line loops.
U.S. Pat. No. 5,062,344 issued on Nov. 5, 1991 to Thomas F. Gerker describes a Bowline Knot In A Braided Line, wherein a special hook is used to draw a doubled free end of the line back into and through the hollow core. The end remains captured within the core to form a doubled loop, but the two loops meet at the point where the free end enters the hollow core; the Gerker construction cannot provide a substantial length of line between the two loops, as in the present invention. Also, the free end of the line is passed through one of the loops, with the loop being pulled taut around the base of the free end. The captured end of the line is not positively secured within the core of the line, and can pull out, releasing the arrangement, unlike the present double looped line invention.
Finally, U.S. Pat. No. 5,540,703 issued on Jul. 30, 1996 to Boyd T. Barker, Jr. et al. describes a Knotted Cable Attachment Apparatus Formed Of Braided Polymeric Fibers. A small loop or eye is formed in a portion of the cable by passing the working end through the standing length, as in the first step in forming the loop configuration of the present invention. However, the working end is then passed back through the standing length of the line, rather than back into the working end portion within the hollow core, as in the present method. Thus, the size of the Barker, Jr. et al. eye formed may be adjusted by pulling on the working end, as it is not locked within the core of the line by the working end passing back through itself within the core so it cannot escape laterally through the sides of the core, as in the present configuration. Moreover, Barker, Jr. et al. teach away from the present invention wherein a separate loop of fixed size is formed in each of the two opposed ends of the line. Barker, Jr. et al. form the second loop in a different manner from the first loop or eye, similarly to the method used in forming the splice of the Domoj et al. patent, whereas the two loops of the present double looped line are identical to one another. Also, the second loop of the Barker, Jr. et al. cable is constructed to pass through the first eye or loop, whereas the two loops of the present invention are completely separate, and are separated by a length of line therebetween.
None of the above inventions and patents, either singly or in combination, is seen to describe the instant invention as claimed.