There is disclosed a separate structure of a datapath layer and a physical layer within an access network loaded with a V 5.2 protocol in a wireless communication system and communication method between two boards respectively having the datapath layer and the physical layer, which separately forms the protocol board with the datapath layer and the physical layer board section including the multiple physical layer boards with the multiple physical layers and connects the separate two entities using the routing section to allow a protocol to be transmitted and received between the two entities, thereby facilitating the designing of the V5.2 protocol board, the extension of the system and the execution of dualization function of the V5.2 LAYER 3.

1. Field of the Invention
The present invention relates to an access network loaded with a V5.2 protocol in a wireless communication system and more particularly to a separate structure in which a datapath layer and a physical layer are separately loaded onto different boards in the access network loaded with the V5.2 protocol and to a method of communicating a protocol between the two boards respectively loaded with the separate physical and datapath layers.
2. Description of Related Art
Generally, a V5.2 protocol is a signaling interface rule between a system controller and a switching center in a wireless communication system. According to the V5.2 protocol, maximum 16 E1 links (1048 Kbps) each having a transmission rate of 128 Kbps can be used in a single interface and a protocol for protection of communication channels exists when more than one link is used.
The following explain concerns a connection structure between a public switched telephone network (PSTN) switching center and the access network loaded with the V5.2 protocol in the wireless communication system according to a prior art.
FIG. 1 shows the connection structure between the PSTN switching center and the access network loaded with the V5.2 protocol in the wireless communication system according to the prior art. An access network board 10 loaded with the V5.2 protocol is divided into a LAYER 3 110, a data link management layer 120, a datapath layer 130 and a physical layer 140.
The physical layer 140 of the access network board 10 is connected to a PSTN switching center 400 via 16 E1 links. Here, the LAYER 3 110 of the access network board 10 is composed of multiple protocols.
The multiple protocols comprises: a call process channel allocation section 111 for allocating a call process channel; an E1 link switching controller 113 for switching from a selected E1 link to another E1 link when the selected E1 link is out of order; an E1 link controller 115 for blocking or unblocking the E1 link according to a command of a manager; a user port management section 117 for managing a user port connected to the access network board 10; and a voice channel allocation section 119 for allocating a voice channel.
The data link management layer 120 of the access network board 10 manages data link (E1 link) connection with the PSTN switching center 400 and controls flow of data transmission according to a command of each protocol.
The datapath layer 130 of the access network board 10 supports relay mechanism with respect to protocol messages of the LAYER 3 110. The physical layer 140 is a transmission device for transmitting and receiving the protocols between the datapath layer 130 and the PSTN switching center 400 via the E1 links.
Although the V5.2 protocol provides maximum 16 E1 links per interface board according to the prior art, it is nearly impossible to design a system such that all the links are implemented in one board when the V5.2 protocol is actually applied to the system. In other words, according to the conventional access network board 10 loaded with the physical layer 140 connected to the E1 link, two E1 links are connected to one physical layer 140. To cover the 16 E1 links, the access network board 10 needs 8 physical layer boards. However, only two or three physical layer boards can be disposed per access network board 10 in an aspect of actually designing the physical layer 140 board.
Accordingly, the present invention is directed to a separate structure of a datapath layer and a physical layer within an access network loaded with a V5.2 protocol in a wireless communication system and a communication method between two boards separately having the datapath layer and the physical layer that substantially obviates one or more of the limitations and disadvantages of the related art.
An objective of the present invention is to provide a separate structure of a datapath layer and a physical layer within an access network loaded with a V5.2 protocol in a wireless communication system, wherein the datapath layer and the physical layer are separated in the access network board loaded with the V5.2 protocol and the separated datapath and physical layers are connected using a router, thereby facilitating the designing of the access network board loaded with the V5.2 protocol.
Another objective of the present invention is to provide a method of communicating protocol messages between a board with the datapath layer and a board with the physical layer.
Additional features and advantages of the invention will be set forth in the following description, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure as illustrated in the written description and claims hereof, as well as the appended drawings.
To achieve these and other advantages, and in accordance with the purpose of the present invention as embodied and broadly described, in a connection structure between a PSTN switching center and a V5.2 protocol access network including a protocol board comprising a datapath layer and a plurality of physical layers, a separate structure of a datapath layer and a physical layer within the access network loaded with the 5.2 protocol in the wireless communication system, comprises: a plurality of physical layer boards with the plurality of physical layers separated from the protocol board and connected to the PSTN switching center via a plurality of E1 links; a routing section disposed between a group of the multiple physical layer boards and the protocol board with the datapath layer, for designating a protocol transmission path between the datapath layer in the protocol board and one of the multiple physical layer boards and for routing packet data including a protocol message between the designated physical layer board and the protocol board; and a controller for providing a control signal to the routing section to allow the packet data to be routed to the designated physical layer board or the protocol board via the routing section.
In another aspect of the present invention, a method of communicating a protocol between a protocol board having a datapath layer and one of multiple physical layer boards having multiple physical layers, comprises: a forward communication step of transmitting a packet including a message requesting connection, information designating an E1 link and a protocol message to the physical layer board via the routing section and determining whether or not an E1 link corresponding to the information designating the E1 link contained in the packet is normal so as to transmit the protocol message to the PSTN switching center via the corresponding E1 link if the corresponding E1 link is determined to be normal; and a reverse communication step of receiving a protocol message from the PSTN switching center via the corresponding designated E1 link and forming a packet for the protocol message if the received protocol message is normal so as to transmit the normal protocol message to the datapath layer in the protocol board via the routing section.
The forward communication step comprises the steps of: transmitting the packet including a destination address, a source address and the E1 link designating information from the protocol board to the physical layer board via the routing section for request of connection; activating an E1 link corresponding to the designating information contained in the transmitted packet and determining whether or not the corresponding E1 link is stable; forming a packet including state information denoting that the corresponding E1 link is stable and transmitting the packet including the state information of the corresponding E1 link to the protocol board via the routing section if the corresponding E1 link is determined to be stable; forming a packet including the protocol message to transmit it to the physical layer board via the routing section if the protocol board receives the packet including the state information of the corresponding E1 link; transmitting the protocol message contained in the packet to the PSTN switching center via the corresponding designated E1 link if the packet including protocol message is received by the physical layer board; and transmitting a packet including information denoting that transmission of the protocol message has been completed to the protocol board via the routing section if the transmission of the protocol message to the PSTN switching center is completed.
The reverse communication step comprises the steps of: receiving the protocol message and determining whether or not the protocol message is normal if the protocol message is transmitted from the PSTN switching center via the designated E1 link to the physical layer board connected to the designated E1 link; forming the packet by adding a header and an identifier to the protocol message if the received protocol message is determined to be normal and transmitting the packet to the protocol board. via the routing section; and analyzing the packet transmitted from the physical layer board to identify the identifier and the protocol message contained in the transmitted packet.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

SEPARATE STRUCTURE OF A DATAPATH LAYER AND A PHYSICAL LAYER WITHIN AN ACCESS NETWORK LOADED WITH A V5.2 PROTOCOL IN A WIRELESS COMMUNICATION SYSTEM AND COMMUNICATION METHOD BETWEEN TWO BOARDS RESPECTIVELY HAVING THE DATAPATH LAYER AND THE PHYSICAL LAYER


A fitting for fixing an object on a rail, the fitting having a retainer (2) in a sliding body and having a holding and locking element (8.1) arranged so as to be movable relative to the retainer.

The present invention concerns a fitting for fixing an object on a rail.
The device according to the invention serves primarily for the fixing of aircraft seats on corresponding rails in an airplane, but it should not be limited to this, when described hereafter with the aid of this example.
It is known that airplane seats very often need to be shifted depending on the occupancy of the airplane, and this needs to be done as quickly as possible. The subsequent fixing in a desired position must in turn be done very reliably, since the seats need to comply with a definite mandatory speed of acceleration and deceleration.
Most such airplanes are outfitted today with so-called airline rails, which are generally familiar. For a more detailed illustration of an airline rail, refer to DE 202 18 780 U1. The airline rail has an undercut groove to receive a sliding body, while corresponding troughs are formed in the free margins of the groove on both sides.
Fittings are known for the fixing of seats on such airline rails, possessing the aforementioned sliding body, which slides by lateral sliding shoes in the undercut groove and can be displaced in this groove. In order to fix this sliding body, which also has a connection element, in a defined location of the airline rail, a retainer sits on top of the sliding body. This retainer has laterally molded thickenings between every two sliding shoes. If the retainer is lowered, these thickenings travel into the above mentioned troughs of the airline rail, so that now a further shifting of the fitting is no longer possible.
A screw is used for the lowering and fixing of the retainer, whose head presses against the retainer and thereby lowers the retainer downward. The drawback with this is that a very long screw path needs to be traveled, and this both during the lowering and the raising of the retainer. This takes an exceptional amount of time, it is tedious, and it often has the result that the fittings are not properly fixed on the airline rail, so that there might occur a clattering or even a loosening of the fitting. This is extremely undesirable. Such a device in which a screw is used for the lowering and fixing of a retainer is described in U.S. Pat. No. 4,796,837.
In U.S. Pat. No. 4,493,470 another device is disclosed for fixing an object on a rail by means of a fitting which can move with a sliding body along the rails of a groove and which has a retainer, which can be lowered into at least one side groove trough in the rail. The retainer is joined by a cylindrical connection element to the sliding body and is braced against the sliding body and/or against a handling element via a compression spring. For the moving or fixing of the device, only the handling element needs to be activated. The drawback with this device is that here as well a clattering or a loosening of the fitting is not entirely precluded.
Another device for the fixing of an object on a rail by means of a fitting is described in U.S. Pat. No. 5,871,318. In this case, a locking pin is used for the lowering and fixing of a retainer, which is rotated to secure the retainer in at least two height positions relative to the rail. The drawback to this device is that it has a complicated makeup with many components. Furthermore, a proper and secure fixing of the device on the rail is not guaranteed.
Moreover, a device is known from EP 1 794 053 which overcomes many of the aforementioned drawbacks. Sliding body and retainer are connected here by means of a connection element, at whose end facing away from the rail there is a rotary element. The rotary element is designed so that it makes possible the fixation of the retainer, which can be displaced relative to the sliding body, in various positions. A detent trough or detent notch coordinated with the rotary element ensures a noiseless and secure fixation of the retainer in the rail. Furthermore, the rotary element also serves for the fixation of the retainer in the starting position, i.e., when this is not fixed in the rail, but instead can be removed from it or has not even been introduced in it. The elegant design of the rotary element as a bifunctional detention thus enables the sliding shoe to be introduced into the rail, a subsequent movement of the fitting within the rail, and a fixing of the fitting merely by turning the rotary element. Such a turning of the rotary element produces a releasing of the spring-loaded retainer, which then travels into the rail and is fixed there.
The connection element moreover has a threaded segment, by which it is secured in a corresponding threaded borehole of the sliding body. As a rule, for the noiseless and clatter-free fixation of the fitting in the rail the connection element is screwed for a bit into the sliding body, after the retainer has been lowered into the rail. Thus, the rotary element engages on the retainer by its coordinated detent trough, so that once again the fitting as a whole is secured clatter-free in the rail. A screwing of the connection element into the sliding body is done here with a suitable tool. Advisedly, a tool purchase is provided at one end of the connection element, accessible to the user.
The object of the present invention is to improve a device of the above kind and to make possible an easier detention or fixation of the retainer in different positions. The device should furthermore prevent an unintentional and undesirable loosening or even releasing of the fitting from the rail when it has already been fixed in the rail.


For enhanced access control, a client includes a token in each read or write command sent to a block storage device. The block storage device evaluates the token to determine whether or not read or write access is permitted at a specified logical block address. For example, the token is included in the logical block address field of a SCSI read or write command. The client may compute the token as a function of the logical block address of a data block to be accessed, or a metadata server may include the token in each block address of each extent reported to the client in response to a metadata request. For enhanced security, the token also is a function of a client identifier, a logical unit number, and access rights of the client to a particular extent of file system data blocks.

In a shared disk based file system, a plurality of computers share access to block storage devices that store file data. For example, network clients such as Microsoft Windows (Trademark) workstations may use the Common Internet File System (CIFS) protocol to access a shared disk based file system stored in a multi-protocol network file server, and network clients such as UNIX (Trademark) workstations may use the Network File System (NFS) protocol to access the shared disk based file system managed by the multi-protocol file server.
For enhanced data throughput, shared disk based file systems have been developed that permit network clients to share access to the file system by obtaining access permission and file metadata from a metadata server, and then using a high-speed data block access protocol to access the file data in one or more block storage devices. For example, as described in Vahalia, et al. U.S. Pat. No. 6,973,455 issued Dec. 6, 2005, incorporated herein by reference, a client is permitted to send data access commands directly to block storage of a network file server after obtaining a lock on at least a portion of the file and obtaining metadata indicating storage locations for the data in the block storage. For example, the client sends to the file server at least one request for access to a file. In response, the file server grants a lock to the client, and returns to the client metadata of the file including information specifying data storage locations in the block storage for storing data of the file. The client receives the metadata, and uses the metadata to produce at least one data access command for accessing the data storage locations in the block storage. The client sends the data access command to the block storage to read or write data to the file. For a write operation, the client may modify the metadata. When the client is finished writing to the file, the client returns modified metadata to the file server.
Shared disk based file systems are under development that permit a metadata server to grant extent-based range locks within a file to network clients. As described in David L. Black et al., "pNFS Block/Volume Layout," NFSv4 Working Group Internet Draft, Mar. 4, 2007, parallel NFS (pNFS) extends NFSv4 to allow clients to directly access file data on the storage used by the NFSv4 server. This ability to bypass the server for data access can increase both performance and parallelism, but requires additional client functionality for data access, some of which is dependent on the class of storage used. Layout extents returned to pNFS clients grant permission to read from or write to the extents. In general, the server will not be able to prevent a client which holds a layout for a file from accessing blocks of the physical disk not covered by the layout. In environments where the security requirements are such that client-side protection from access to storage outside the layout is not sufficient, pNFS block/volume layouts for pNFS should not be used.
Thus, shared disk based file systems that grant extent-based range locks to the clients and permit the clients to directly access the extents in a network block storage device raise security problems. There are two transports, the transport of the client access to the metadata server, and the transport of the client access to the network block storage device. Both of these transports should be secured, and have access controls implemented on them.
Most single host based file systems implicitly trust the host and the system administrator. The file system software running on the host is able to read and write to any block on the storage device that contains the file system, and the file system is responsible for implementing access controls. For most file systems this means that a super-user (root) can access any file in the file system. Users wishing to protect their data from root access must encrypt it, and ensure that even the super user does not have access to the encryption key.
Network based file systems introduce a new security model. In contrast to the single host file system, a network based file system defines two security domains. The first domain is the server domain, including the meta-data server in pNFS, the network block storage devices, and the server administrator, all of which are trusted. The second domain includes client machines and the client administrators, which are untrusted. As has been typical with NFS3 implementations, the file server administrator can explicitly configure the system such that a root user on a client host has no special privileges. This is often implemented by mapping the root user id (0) to a guest user id. No matter how the client machine is compromised, the file server still implements the access control and determines which data is accessible. Methods exist for securing the communications channel between the client and the file server, and systems like Kerberos can be used to strongly authenticate both the client identity and the user identity.
Shared SAN based file systems like MPFS and pNFS introduce new challenges in maintaining security. In these systems, untrusted hosts are granted read and write access to the storage devices used for the file system. As currently implemented using the standard SCSI-3 block command set (SBC-3), the storage device does not implement access control. In practice, LUN masking (storage groups), or other storage based mechanism are used to implement access control on a per logical unit basis, allowing only specific clients access to the storage. See, for example, Blumenau et al., U.S. Pat. No. 7,093,021 issued Aug. 15, 2006. Once a host is granted access to a logical unit, however, it can access any part of the logical unit. The host can read or write any block of the logical unit, and can possibly corrupt the file system. The assumption to date has been that the clients are in the same trust domain as the server. The assumption of clients being in the same trust domain as the server conflicts with the security model of NFS, and has caused problems such as malicious administrators writing to disks without having the proper rights granted, operator error, writing to disks using commands such as "dd", aggressive disk management software, writing volume labels on all unlabeled disks, and reading from or writing to any range on a disk once gaining access to the disk.
There have been a number of approaches to dealing with the problem of securing client access to a block storage device after the client has been granted access by a file manager or metadata server.
The problem of securing client access to a network-attached storage device after the client has been granted access by a file manager has been discussed in Howard Gobioff et al., "Security for Network Attached Storage Devices," Report CMU-CS-97-185, Oct. 23, 1997, School of Computer Science, Carnegie Mellon University, Pittsburgh, Pa. 15213. One approach to addressing this problem is called a grant-style approach, and another approach is called a capability approach.
In the grant-style approach, a client requests access from a file manager. The file manager grants client access and informs the network-attached storage device of the grant. The network-attached storage device acknowledges the grant. Once the network-attached storage device acknowledges the grant, the file manager provides the client with access information. The client then sends a request to the network-attached storage device, and receives a response.
In the capability approach, the client requests access from a file manager. The file manager responds by returning a "capability" to the client. The "capability" includes capability arguments and a capability key. The capability arguments contain a drive identifier, partition, object identifier, region (byte range), access rights, expiration time, minimum requirements, a basis key, and an audit identifier. The capability key is a cryptographic key used by a client to bind a specific storage device request to a capability through use of a machine identification code (MAC).
To address the problem of securing client access to a block storage device after the client has been granted access by a metadata server, EMC Corporation has used a host based filter driver (hrdp) which filters I/Os to block storage devices. Hrdp first scans all block storage devices looking to see if they have a label identifying an EMC Corp. "CELERRA" brand of storage device. If they do have such a label, a filter is installed which requires device open commands to pass a special flag. Any software that does not pass the special flag on open gets an error instead of a handle to the device. This solution solves some problems of operator error and aggressive disk management software, but still leaves the door open for incorrect install sequences and malicious system administrators. Such administrators can either remove the hrdp software, or can write their own programs and supply the special flag, thus gaining read/write access to the block storage devices.
An additional concern is a buggy host which does not respond to requests to return extents (layouts in pNFS) to the metadata server. In such a situation, either the host must fence itself from storage, which is unlikely since it has already refused to honor protocol requests, or the server must be capable of causing the storage to deny access of such a malfunctioning host.

Access control to block storage devices for a shared disk based file system


The disclosure relates to the servo-control of an electronic circuit that calls for the detection of the power delivered at its output. The disclosed device is essentially constituted by a field-effect transistor with zero bias V.sub.DS mounted between the ground and a matching network at output of the circuit. This transistor behaves either like a capacitor or like a diode. A low-pass filter, connected between the transistor and the network, delivers a detection voltage V.sub.det.

The present invention relates to a device for the detection of power at the output of an electronic circuit such as a power amplifier comprising at least one field effect transistor and one matching network at output.
A matching network at output is understood to mean a network designed to improve or match an electrical characteristic of the circuit. It may be an impedance matching network for example, or a harmonics rejection network in a frequency generator or at the output of an amplifier which, as laid down by a standard, must short-circuit at the second harmonic or to be in an open circuit state at the third harmonic (for example, a class F amplifier). More generally, it is quite rare for an electronic circuit not to have, at its output, a network essentially comprising resistors, inductors and capacitors in order to match it to a specification.
The device according to the invention has been designed for applications in the microwave range (one to several tens of GHZ) but it can also be applied to circuits working at lower frequencies.
The object of this device is the detection of an electrical power present at an output terminal of a circuit: the detection signal can be used to activate an electrical signal that was hitherto dormant, or to servocontrol the supply of a transistor or, again, to trigger an alarm signal for example.
The power detection function is well known per se, and its application is very common in stabilized current or voltage supplies. The principle thereof is given in FIG. 1. In an assembly comprising an electronic circuit 1, such as an amplifier, capable of modulating the current delivered between the input terminals "i" and the output terminals "o", this current I is detected by the voltage created at the terminals of a high value resistor 2. The voltage V.sub.det for the detection of the current I is actually taken at the anode of a diode 3. A high-value resistor 5 at the detection output matches the impedance for the measuring apparatus.
In the device according to the invention, the power detection is achieved by means of a field-effect transistor that is integrated with a matching network comprising at least one inductor and one capacitor. This transistor meets a twofold specification: its gate is grounded and the transistor is not biased, so that it behaves either like a capacitor or like a diode, depending on whether or not it detects a current in the circuit. The field-effect transistor, by its equivalent capacitance, participates in the matching network.

Device for the detection of power at the output of an electronic circuit


A machine for the manufacture of a single-face lined web of corrugated board comprises a pressing device for pressing a liner web against a paper web provided with a corrugation. This pressing device has at least one substantially stationary, open-end pressing belt, which does not move together with the web of corrugated board.

Field of the Invention
The invention relates to a machine for the manufacture of a single-face lined web of corrugated board, comprising two fluted rollers for the production of a corrugation on a paper web, a gluing device for spreading glue on the peaks of the corrugation of the corrugated paper web, a pressing device for pressing a liner web on the peaks, provided with glue, of the corrugated paper web resting on one of the fluted rollers along a contact area, the pressing device having a pressing belt pressable against the fluted roller along a pressing area.

Machine for the manufacture of a single-face lined web of corrugated board

BHS Corrugated Maschinen- und Anlagenbau GmbH


An improved flash memory device having core stacks and periphery stacks which are protected by first and second thin side walls, side spacers over the side walls, and an HTO layer over the stacks, and side spacer. The flash memory device has an intermetallic dielectric layer placed over the HTO layer. A tungsten plug is placed in the intermetallic dielectric layer to provide an electrical connection to the drain of the flash memory device. The additional first and second side walls reduce current leakage between core stacks and the tungsten plug and help to protect the stacks during fabrication.

The present invention relates to nonvolatile memory devices. Even more particularly, the present invention relates to flash memory utilizing periphery and core stacks.
Memory devices such as flash memory or electrically erasable programmable read only memory (EEPROM) are known. U.S. Pat. No. 5,656,513 to Wang et al. and U.S. Pat. No. 5,693,972 to Liu disclose prior art flash memory devices. FIG. 1 is a cross sectional view of an incomplete flash memory structure 10, known in the prior art. Shown as parts of the flash memory structure 10 are a substrate 12, a plurality of core stacks 16 mounted on the substrate 12 in a row forming a word line, and a periphery stack 14 associated with the word line of the core stacks mounted on the substrate 12 spaced apart from the core stacks 16.
A first oxide layer 18 forms a first layer of the periphery stack 14 and the core stacks 16, where the first oxide layer 18 has a first side adjacent to the substrate 12 and a second side opposite from the first side. The first oxide layer 18 for the periphery stack 14 is a gate oxide layer, and the first oxide layer 18 for the plurality of core stacks 16 are tunnel oxide layers. A first polysilicon layer 20 forms a second layer of the core stacks 16, where the first polysilicon layer 20 has a first side adjacent to the second side of the first oxide layer 18 and a second side opposite from the first side of the first polysilicon layer 20. An interpoly dielectric layer 22 forms a third layer of the core stacks 16, where the interpoly dielectric layer 22 has a first side adjacent to the second side of the first polysilicon layer 20 and a second side opposite from the first side of the interpoly dielectric layer 22. A second polysilicon layer 24 forms a second layer of the periphery stack 14 and a fourth layer of the core stacks 16. A silicide layer 26 forms a third layer for the periphery stack 14 and a fifth layer for the core stacks 16. A third polysilicon layer 28 forms a fourth layer of the periphery stack 14 and a sixth layer of the core stacks 16. An antireflective coating (ARC) 29 forms a fifth layer of the periphery stack 14 and a seventh layer of the core stacks 16.
A protective oxide layer 31 is placed over the periphery stack 14, the core stacks 16 and the uncovered surface of the substrate 12, as shown in FIG. 2. A first high temperature oxidation oxide (HTO) layer 32 is placed over the protective oxide layer 31. A first resist mask 34 is placed over parts of the first HTO layer 32 to cover the periphery stack 14 and parts of the core stacks 16 and the drain area.
The parts of the first HTO layer 32 not covered by the first resist mask 34 are etched partially away to create self aligned source spacers 36, as shown in FIG. 3. The flash memory structure 10 is subjected to a deep source implant to form deep source regions 37 for the core stacks in the substrate 12. The first resist mask 34 is then stripped away and a second HTO layer 39 is placed over the first HTO layer 32, self aligned source spacers 36, and the uncovered parts of the core stacks 16 and substrate 12 surface, as shown in FIG. 4.
The second HTO layer 39 is etched away to form source/drain spacers 40, as shown in FIG. 5. The flash memory structure is subjected to a shallow dopant implant to create shallow more highly concentrated drain regions 42 and source regions 43. A third HTO layer 45 is placed over the self aligned source and source/drain spacers 36, 40, and the uncovered parts of the core stacks 16, periphery stack 14 and substrate 12 surface. An intermetallic dielectric layer (IDL) 46 is placed over the third HTO layer 45. A trench is etched into the intermetallic dielectric layer (IDL) 46 and is filled to create a tungsten plug 48 electrically connected to a drain region 42 of a core stack 16.
Problems in the manufacture of flash memory according to the above mentioned process may occur, because etching after the core stacks 16 have been formed may damage the core stacks 16. In addition, process induced charging, caused by processes such as plasma deposition, etching, and chemical mechanical polishing, creates ions which may damage the core stacks 16 by way of trapped charges moving between the tungsten plug 48 and the core stacks through the source/drain spacers 40.
Accordingly, the present invention involves producing a flash memory device on a substrate by: forming a plurality of core stacks on the substrate; forming at least one periphery stack on the substrate; forming an oxide layer on the core stacks the periphery stack and the substrate; applying a protective layer over the oxide layer, etching back the oxide layer and protective layer to form side walls around the periphery and core stacks, applying a first HTO layer over the side walls, etching back the first HTO layer to form self aligned source spacers, doping the uncovered substrate, applying a second HTO layer, etching back the first and second HTO layers to form source/drain spacers, and doping the uncovered substrate, and then applying an HTO layer over the spacers, periphery stack, core stacks and substrate.
Advantages of the present invention include, but are not limited to, providing a flash memory device with reduced damage to the core stacks and reduced current leakage between the plugs and the stacks. Other features of the present invention are disclosed or apparent in the section entitled: xe2x80x9cDETAILED DESCRIPTION OF THE INVENTION.xe2x80x9d

Charge gain/charge loss junction leakage prevention for flash technology by using double isolation/capping layer between lightly doped drain and gate


An apparatus for detecting biometric information of a living body detects a pulse wave and extracts the biometric information of the living body in a non-invasive method. The apparatus for detecting biometric information includes a surface pulse wave measurement unit for measuring a surface pulse wave of an object. The surface pulse wave measurement unit includes at least one light source that radiates incoherent light and at least one photodetector that measures an intensity of light radiated by the at least one light source and reflected from a surface of the object. The surface pulse wave measurement unit measures the surface pulse wave of the object based on a change in the intensity of the light reflected from the surface of the object.

1. Field
Apparatuses and methods consistent with exemplary embodiments relate to detecting biometric information of living body, and more particularly, to detecting a pulse wave and extracting the biometric information of the living body in a non-invasive manner.
2. Description of the Related Art
A method of detecting biometric information, such as, a pulse wave, may be divided into an invasive method and a non-invasive method. Recently, the non-invasive method has been increasingly used because a pulse wave may be detected in a simple manner without causing pain to an examinee.

Apparatus for detecting biometric information of living body


A semiconductor module of an electric power converter includes an IGBT and a MOSFET which are connected in parallel to each other and provided on the same lead frame, either one of the IGBT and the MOSFET is a first switching element and the remaining one is a second switching element, and the conduction path of the second switching element is disposed at a position that is separated from a conduction path of the first switching element in the same lead frame.

Conventionally, as a semiconductor module constituting an electric power converter, a configuration in which an IGBT excellent in performance in a high current region is combined with a MOSFET with excellent performance in a low current region is known.
For example, JP 5863599 and JP 5805513 each disclose a semiconductor module (power module) provided with an IGBT and a MOSFET which are connected in parallel with each other.
This semiconductor module is advantageous in that it has both excellent characteristics of IGBT and MOSFET.
When designing a semiconductor module provided with both the IGBT and the MOSFET, there is a requirement that thermal influence (also referred to as thermal damage) such that the two switching elements thermally interfere with each other is suppressed from occurring.
In response to this demand, the semiconductor module disclosed in JP 58563599 adopts a structure that does not positively cool the MOSFET with high heat resistance so that the IGBT is likely to receive thermal influence from the MOSFET when the temperature of the MOSFET becomes high.
Moreover, in the semiconductor module disclosed in JP 5805513 is constituted that a current flows through the bus bar directly under the MOSFET when the IGBT is energized, and the MOSFET is likely to receive thermal influence from the bus bar in a high temperature state.


A lighting control system that allows for flexible control of low-voltage LED light fixtures connected to an output of a digital power module such that during “normal” operation where the digital power module is receiving electrical power from the building electrical system, the digital power module controls the connected light fixtures according to a first control scheme and in the event of an interruption of building electrical power (“emergency” operation), the system receives backup power and control the connected light fixtures according to a second control scheme.

Distributed lighting systems typically have a central controller and have distributed/remote light fixtures connected to and controlled by the central controller, whereby the central controller receives power from a power source and receives control signals from one or more analog and/or digital control inputs, and, in turn, provides power and control signals to the light fixtures. For example, multiple Light Emitting Diode (LED) light fixtures, which typically use a very small amount of electrical power as compared to "standard" light fixtures that use incandescent or fluorescent lamps, can be connected to central controller by low voltage wiring which provides both power and control to the LED light fixtures.
The central controller may be connected to building power, which may comprise 120V/277V AC in the United States. With conventional lighting, if power to the building is interrupted, it is important to provide emergency lighting in a commercial or industrial space to enable the occupants to safely and quickly exit the building. Emergency power may be provided with a battery that is positioned in the light fixture itself, or may be provided by a backup generator that provides power in the event of a power interruption. In the case of LED lighting, the amount of electrical power that is consumed per light fixture is much lower than in conventional light fixtures, which opens up the possibility for different lighting schemes or configurations during a power interruption.
Additionally, unlike conventional lighting which are substantially controlled as a binary state (e.g., On/Off), LED light fixtures require enhanced control. For example, during a power outage, a conventional light fixture could simply be provided with power from an alternate source (i.e., a battery, a generator, etc.) whereas an LED light fixture not only needs power, but needs a control signal that will set the intensity of the light fixture and the color of the fixture.
However, in the event of a power interruption or failure, the central controller will cease functioning without power. Likewise, the various control inputs to the central controller will cease functioning without power. This means that even if power is provided to the central controller, the various peripheral devices will not be powered and therefore no control signals can be generated to send to the central controller.
So, while LED light fixtures provide some distinct advantages over conventional lighting, the control schemes are much more complicated and the ability to control LED lighting fixtures during a power interruption has been very limited.

Backup power for distributed lighting system and method


Disclosed herein are a positive electrode active material including at least one selected from among compounds represented by Formula 1 below and a lithium secondary battery including the same that is capable of improving lifetime characteristics and rate characteristics while exhibiting excellent safety: Li[LixMyM′(1-x-y)]O2-zAz (1), where M is at least one element selected from a group consisting of Ru, Mo, Nb, Te, Re, Ir, Pt, Cr, S, W, Os, and Po, M′ is at least one element selected from a group consisting of Ni, Ti, Co, Al, Mn, Fe, Mg, B, Cr, Zr, Zn, and second row transition metals, A is a negative monovalent or divalent anion, and 0<x<0.3, 0.2≤y≤0.5, 0≤z<0.5, and 0.2<x+y<0.8.

In recent years, with increased concerns about environmental problems, much research has been carried out into electric vehicles (EV) and hybrid electric vehicles (HEV), which are capable of substituting for vehicles using fossil fuel, such as gasoline and diesel oil, which cause air pollution. Nickel-metal hydride (Ni-MH) secondary batteries have been mainly used as a power source for the electric vehicles and the hybrid electric vehicles. On the other hand, much research has also been carried out into lithium secondary batteries having high energy density, high discharge voltage, and high output stability, and some of the lithium secondary batteries are now commercialized.
In particular, it is necessary for lithium secondary batteries used for electric vehicles to exhibit high energy density and to provide high output within a short time. In addition, it is also necessary for lithium secondary batteries used for electric vehicles to be used for 10 years or more under severe conditions. For these reasons, lithium secondary batteries used for electric vehicles require higher safety and longer lifespan than conventional small-sized lithium secondary batteries. In addition, secondary batteries used for electric vehicles (EV) and hybrid electric vehicles (HEV) require excellent rate characteristics and excellent power characteristics based on the operation conditions of a vehicle.
Carbon materials are mainly used for negative electrode active materials of a lithium secondary battery, and the use of lithium metals and sulfur compounds is under consideration. In addition, lithium-containing cobalt oxides, such as LiCoO2, are mainly used for positive electrode active materials of a lithium secondary battery, and the use of lithium-containing manganese oxides, such as LiMnO2, having a layered crystal structure, LiMn2O4, having a spinel crystal structure, and lithium-containing nickel oxides, such as LiNiO2, is also under consideration.
Among the positive electrode active materials, LiCoO2 is widely used due to its excellent lifetime characteristics and high charge and discharge efficiency, but has low structural stability. In addition, due to the resource limitations of cobalt, which is a raw material, LiCoO2 is expensive, and therefore price competitiveness is low, whereby the massive use thereof as power sources in fields such as electric vehicles is limited.
LiNiO2 is relatively inexpensive, and makes it possible for a battery to have high discharge capacity. However, phase transition abruptly occurs in the crystal structure of LiNiO2 depending on the change in volume of the battery caused by charge and discharge of the battery. In addition, when LiNiO2 is exposed to air and moisture, the safety of LiNiO2 is abruptly lowered.
In addition, lithium manganese oxides, such as LiMnO2 and LiMn2O4, exhibit excellent thermal safety and are inexpensive. However, the use of lithium manganese oxides entails a small charge capacity, poor cycle characteristics, and poor high-temperature characteristics.
For these reasons, much research has been carried out into new positive electrode active materials that have structures other than the above-mentioned structures.
For example, research has been carried out into an oxide containing excessive lithium, e.g. a lithium transition metal oxide containing a high content of Mn, wherein the content of lithium is higher than the content of the transition metal such that a high capacity of 270 or more mAh/g is exhibited at a high voltage of 4.5 V or higher.
However, the oxide containing excessive lithium has a high irreversible capacity. Furthermore, in addition to lithium, oxygen escapes from the active material structure at the time of high-voltage activation to utilize excess lithium. As a result, the active material structure may collapse, and a voltage sagging phenomenon may occur, whereby the deterioration of the battery cell may be accelerated.
Meanwhile, many researchers have proposed methods of using a positive electrode active material containing Li2MnO3 in a layered structure in order to secure the structural stability of the positive electrode active material having such a layered structure. In this case, the positive electrode active material contains a large amount of Mn. As a result, the positive electrode active material is very cheap and exhibits large capacity and high stability at high voltage. After the activation of a flat range of 4.4 V to 4.6 V, however, the transition from the layered structure to the spinel structure is performed, and therefore the contact between domains is weakened. As a result, the positive electrode active material may be excessively structurally changed, whereby the improvement of electrical properties may not be satisfied.
That is, the structure of a secondary battery that exhibits desired lifetime characteristics and safety has not yet been proposed.

Positive electrode active material and lithium secondary battery including the same

Research Affairs of SNU & SNU R&DB Foundation


A power adapter hub is provided, comprising: an AC input port; a power supply circuit coupled to the AC input port for receiving AC power and having a maximum rated output power; and a plurality of output ports coupled to the power supply circuit for supplying DC power to external devices. Upon determining that the total power to be supplied might exceed the maximum rated output power, a DC power supplied through at least one of the output ports is modified, and the modified DC powers are set to ensure that the supplied power does not exceed the maximum rated output power.

Advanced electronic devices are typically connected to power supplies having smart output ports. However, when multiple output ports power supplies are being used, there is a need, which has not been satisfied by the solutions known in the art, to efficiently utilize these ports.
Furthermore, there is a need in the art to optimally prevent situations of overload that might occur in power adapter hubs, so as to minimize adverse effects on electronic devices connected thereto.


A motor comprises a base, a rotor, a stator, and a circuit board. The base includes a sleeve. The stator includes at least one fastener. The sleeve has an inclined outer surface. The fastener extends to the circuit board and abuts the inclined outer surface to fasten the circuit board. A fan comprises a base, a hub, a shaft, a circuit board. The base has a sleeve. The hub comprises a plurality of blades disposed outwardly thereof. The shaft connects to the sleeve and is disposed in the hub. The stator has at least one fastener. The sleeve has an inclined outer surface. The fastener extends to the circuit board and abuts against the inclined outer surface to fasten the circuit board.

1. Field of the Invention
The invention relates to a fan, a motor and a fixing structure thereof, and more particularly, to a fixing structure fastening the stator of the motor and the circuit board.
2. Description of the Related Art
Motors applying the theory of electromagnetism to transform electricity into mechanical energy, such as transmission devices of fans, optical drives or hard disk drives are commonly used.
Referring to FIG. 1, a conventional motor includes a base 11, a stator 12, a rotor 13 and a circuit board 14. The stator 12 and the circuit board 14 are electrically connected and disposed on a sleeve of the base 11. The stator 12 includes a plurality of silicon steel pieces with a wire winding disposed therearound. The circuit board 14 supplies power to the stator 12 so that the motor 1 can be driven. The rotor 13, disposed corresponding to the stator 12, includes a shaft 131, a magnetically conductive shell 132 and a magnetic ring 133. The shaft 131 and the magnetically conductive shell 132 are connected and disposed on the base 11. The magnetic ring 133 corresponding to the stator 12 is circumferentially disposed on the inner wall of the magnetically conductive shell 132. When the circuit board 14 supplies power to the stator 12, the magnetic force generated by electric current in the wire winding of the stator 12 drives the rotor 13 to rotate.
As the conventional motor 1 shown in FIG. 1, one side of the stator 12 facing the circuit board 14 is provided with a plurality of hooks 15. The circuit board 14 is provided with a plurality of through holes 141 corresponding to the hooks 15. The stator 12 and the circuit board 14 are connected and fastened to the base 11 by insertion of the hooks 15 through the through holes 141. The enameled wiring of the stator 12 electrically connects to the circuit board 14 by the spot welding 142. Vibration of motor 1 while operating, may cause the hooks 15 to easily separate from the through holes 141. Spot welding 142 is also susceptible to fatigue and fracture due to stress concentration. Additionally, the through holes 141, disposed corresponding to the hooks 15, occupy area on the circuit board 14. A distance must separate the wiring of circuit board 14 from the through holes 141 thus product design is difficult.
In view of the described disadvantages of the conventional technology, providing a fan, motor, and fixing structure thereof capable of improving the connection between the stator of the motor and the circuit board and alleviating circuit board layout difficulties is desirable.

Fan motor having fixing structure for circuit board


An original image of a physical document is received by a client device, a reduced file containing data indicative of a document type is created based on the original image that is substantially smaller in size than the original image. The client device sends a request including the reduced file to a server for information pertaining to a document type for the physical document, receives location information based on the document type from the server for at least one portion of the original image that contains at least one content item for the physical document, and extracts the at least one portion of the original image based on the location information to generate at least one extracted portion of the image. The client device sends a second request including the at least one extracted portion of the image to the server for the at least one content item. Responsive to receiving the at least one content item from the server device, the client device provides the at least one content item for display.

Mobile devices such as mobile phones, smart phones, tablet computers, etc. are a popular platform for application programs. In many cases, an application program executing on a mobile device may communicate with a server system. A client-server application model is a distributed application structure that partitions tasks or workloads between a provider of a resource or service (a server), and a service requester (a client). Clients and servers may communicate over a computer network, which can involve large amounts of data transfer.

Optimizing data exchange between client device and server


In a clamping device (1) for machine tools (2) that is equipped with a power-operated chuck (5) and an electric drive motor (11) with a changeover function for triggering clamping movements, a motion converter (31) as well as a force accumulator (51) for maintaining the clamping force, which comprises several spring packs (52) supported on an adjustment element (32) of the motion converter (31), the spring packs (52) are each only arranged on one side of the adjustment element (32). In addition, a pressure piece (53) interacting with the adjustment element (32) is firmly connected to several spacer elements (57), each of which carries a stop disc (61) and passes through the spring packs (52) as well as a spacer (66). The spacer elements (57) and the spacers (66) can be adjusted relative to one another and the spacers (66) interact with spacer pins (71) which are guided through the pressure piece (53) and are supported on the wall (24) of the housing (21) opposite to the spring packs (52).

A clamping device of this kind is disclosed in EP 15 150 064. In order to undertake both internal and external clamping by means of the power-operated chuck, in this embodiment several spring packs forming the force accumulator are arranged evenly around the circumference on both sides of pressure pieces acting on the adjustment element of the motion converter. In this case, although the springs are guided on pins screwed into the housing and are alternately clamped by the axial movement of the pressure piece, a defined preload of the springs that are not involved in the particular clamping procedure is not provided. Instead, these springs have the force removed from them and are held with axial play in holes worked in the pressure piece, which as a result of the holes having a diameter larger than the springs, are not suitable for guidance purposes.
Apart from the fact that this means two force accumulators with a large number of spring packs are required for both clamping directions, the axial play on the force accumulator which is not loaded means that when the clamping direction is reversed there is the requirement for this clearance to be crossed before any clamping force can be established. The adjustment range to be specified for the motion converter must consequently be made relatively large, and also it is necessary to cover a dead travel before clamping force is established. Despite the significant constructional complexity, this means that a satisfactory operating method is not provided. Furthermore, it is a disadvantage that a defined middle position of the pressure piece cannot be achieved because during a clamping procedure, a signal is only available and able to be evaluated once an adjustment movement of the pressure piece to which a signal ring is attached takes place.

Abstract: Due to this embodiment, the spring packs (52) are always preloaded and do not have any axial play, and the adjustment movements of the pressure piece can thus be registered and evaluated directly. Rather, the spring packs (52) have a defined preload at all times, with the effect that the operating method is improved compared to embodiments of prior art.


A lock nut comprising an internally threaded body having an internally threaded bore and one groove opening at the bore and a second groove opening at the outer surface, the grooves are axially spaced apart and configured to divide the body into first and second end ring portions and a thin axially relilient intermediate portion integral with the end portions. The body has a plurality of internally threaded openings extending inwardly from the outer surface and externally threaded secews threaded into the internally threaded openings and configured to wedge the end ring portions axially away from each other when the screws are threaded into the openings.

Threaded parts are subject to various errors during forming including errors in the thread flank angle and flank shape, and lead errors. In addition, there is an unavoidable clearance between thread connected parts so that the pitch diameter of the nut and male thread are not the same. On threads having angled flanks such as the commonly used 60 degree flank angle, the thread clearance can allow a lock nut to tilt or cock relative to the spindle or shaft and cause an end face on the lock nut to be out of square with the axis of the spindle or shaft. An out of square end face on the lock nut can cause deformation of the spindle or shaft by off-center forces and or uneven bearing preload.
Various different lock nuts have heretofore been made. Some lock nuts such as disclosed in U.S. Pat. Nos. 4,086,946 and 5,454,674, press inserts or weakened thread sections of the lock nut radially inwardly against the threads on the spindle. These lock nuts only provide locking engagement of the lock nut to the spindle or shaft at circumferentially spaced locations and do not eliminate thread clearance evenly around the entire circumference. U.S. Pat. No. 4,557,652, discloses a lock nut having two separate annular members that are interconnected by elastomeric plugs or a elastomeric ring and the two members can be foceably separated by screws threadly mounted in one of the members for adjustment parallel to the axis of the member, to separate the members for locking. Pins are provided to slidably and non-rotatably interconnect the two members, but some relative angular movement can occur due to necessary clearances between parts.
Adjustable lock nuts have also been made in one piece with one internal and one external groove dividing the lock nut into a load carrying section and a locking section, and a thin intermediate section that integrally connects the load carrying section and the locking section. As disclosed in U.S. Pat. No. 4,043,692 (FIGS. 5), the locking section is adapted to be drawn toward the load carrying section by bolts paralleling the axis of the lock nut and threaded into the load carrying section. However, such lock nuts cannot be used in applications where there is insufficient clearance at the end of the lock nut to enable access to the adjusting bolts with a suitable wrench.


A data replication system having a redundant configuration including dual Fibre Channel fabric links interconnecting each of the components of two data storage sites, wherein each site comprises a host computer and associated data storage array, with redundant array controllers and adapters. Each array controller in the system is capable of performing all of the data replication functions, and each host xe2x80x98seesxe2x80x99 remote data as if it were local. Each array controller has a dedicated link via a fabric to a partner on the remote side of the long-distance link between fabric elements. Each dedicated link does not appear to any host as an available link to them for data access; however, it is visible to the partner array controllers involved in data replication operations. These links are managed by each partner array controller as if being xe2x80x98clusteredxe2x80x99 with a reliable data link between them.

The present invention relates generally to error recovery in data storage systems, and more specifically, to a system for providing controller-based remote data replication using a redundantly configured Fibre Channel Storage Area Network to support data recovery after an error event which causes loss of data access at the local site due to a disaster at the local site or a catastrophic storage failure.
It is desirable to provide the ability for rapid recovery of user data from a disaster or significant error event at a data processing facility. This type of capability is often termed xe2x80x98disaster tolerancexe2x80x99. In a data storage environment, disaster tolerance requirements include providing for replicated data and redundant storage to support recovery after the event. In order to provide a safe physical distance between the original data and the data to backed up, the data must be migrated from one storage subsystem or physical site to another subsystem or site. It is also desirable for user applications to continue to run while data replication proceeds in the background. Data warehousing, xe2x80x98continuous computingxe2x80x99, and Enterprise Applications all require remote copy capabilities.
Storage controllers are commonly utilized in computer systems to off-load from the host computer certain lower level processing functions relating to I/O operations, and to serve as interface between the host computer and the physical storage media. Given the critical role played by the storage controller with respect to computer system I/O performance, it is desirable to minimize the potential for interrupted I/O service due to storage controller malfunction. Thus, prior workers in the art have developed various system design approaches in an attempt to achieve some degree of fault tolerance in the storage control function.
One prior method of providing storage system fault tolerance accomplishes failover through the use of two controllers coupled in an active/passive configuration. During failover, the passive controller takes over for the active (failing) controller. A drawback to this type of dual configuration is that it cannot support load balancing, as only one controller is active and thus utilized at any given time, to increase overall system performance. Furthermore, the passive controller presents an inefficient use of system resources.
Another approach to storage controller fault tolerance is based on a process called xe2x80x98failoverxe2x80x99. Failover is known in the art as a process by which a first storage controller, coupled to a second controller, assumes the responsibilities of the second controller when the second controller fails. xe2x80x98Failbackxe2x80x99 is the reverse operation, wherein the second controller, having been either repaired or replaced, recovers control over its originally-attached storage devices. Since each controller is capable of accessing the storage devices attached to the other controller as a result of the failover, there is no need to store and maintain a duplicate copy of the data, i.e., one set stored on the first controller""s attached devices and a second (redundant) copy on the second controller""s devices.
U.S. Pat. No. 5,274,645 (Dec. 28, 1993), to Idleman et al. discloses a dual-active configuration of storage controllers capable of performing failover without the direct involvement of the host. However, the direction taken by Idleman requires a multi-level storage controller implementation. Each controller in the dual-redundant pair includes a two-level hierarchy of controllers. When the first level or host-interface controller of the first controller detects the failure of the second level or device interface controller of the second controller, it re-configures the data path such that the data is directed to the functioning second level controller of the second controller. In conjunction, a switching circuit re-configures the controller-device interconnections, thereby permitting the host to access the storage devices originally connected to the failed second level controller through the operating second level controller of the second controller. Thus, the presence of the first level controllers serves to isolate the host computer from the failover operation, but this isolation is obtained at added controller cost and complexity.
Other known failover techniques are based on proprietary buses. These techniques utilize existing host interconnect xe2x80x9chand-shakingxe2x80x9d protocols, whereby the host and controller act in cooperative effort to effect a failover operation. Unfortunately, the xe2x80x9chooksxe2x80x9d for this and other types of host-assisted failover mechanisms are not compatible with more recently developed, industry-standard interconnection protocols, such as SCSI, which were not developed with failover capability in mind. Consequently, support for dual-active failover in these proprietary bus techniques must be built into the host firmware via the host device drivers. Because SCSI, for example, is a popular industry standard interconnect, and there is a commercial need to support platforms not using proprietary buses, compatibility with industry standards such as SCSI is essential. Therefore, a vendor-unique device driver in the host is not a desirable option.
U.S. patent application Ser. No. 08/071,710, to Sicola et al., describes a dual-active, redundant storage controller configuration in which each storage controller communicates directly with the host and its own attached devices, the access of which is shared with the other controller. Thus, a failover operation may be executed by one of the storage controller without the assistance of an intermediary controller and without the physical reconfiguration of the data path at the device interface. However, the technology disclosed in Sicola is directed toward a localized configuration, and does not provide for data replication across long distances.
U.S. Pat. No. 5,790,775 (Aug. 4, 1998) to Marks et al., discloses a system comprising a host CPU, a pair of storage controllers in a dual-active, redundant configuration. The pair of storage controllers reside on a common host side SCSI bus, which serves to couple each controller to the host CPU. Each controller is configured by a system user to service zero or more, preferred host side SCSI IDs, each host side ID associating the controller with one or more units located thereon and used by the host CPU to identify the controller when accessing one of the associated units. If one of the storage controllers in the dual-active, redundant configuration fails, the surviving one of the storage controllers automatically assumes control of all of the host side SCSI IDs and subsequently responds to any host requests directed to the preferred, host side SCSI IDS and associated units of the failed controller. When the surviving controller senses the return of the other controller, it releases to the returning other controller control of the preferred, SCSI IDS of the failed controller.
In another aspect of the Marks invention, the failover is made to appear to the host CPU as simply a re-initialization of the failed controller. Consequently, all transfers outstanding are retried by the host CPU after time outs have occurred. Marks discloses xe2x80x98transparent failoverxe2x80x99 which is an automatic technique that allows for continued operation by a partner controller on the same storage bus as the failed controller. This technique is useful in situations where the host operating system trying to access storage does not have the capability to adequately handle multiple paths to the same storage volumes. Transparent failover makes the failover event look like a xe2x80x98power-on resetxe2x80x99 of the storage device. However, transparent failover has a significant flaw: it is not fault tolerant to the storage bus. If the storage bus fails, all access to the storage device is lost.
U.S. Pat. No. 5,768,623 (Jun. 16, 1998) to Judd et al., describes a system for storing data for a plurality of host computers on a plurality of storage arrays so that data on each storage array can be accessed by any host computer. There is an adapter communication interface (interconnect) between all of the adapters in the system to provide peer-to-peer communications. Each host has an adapter which provides controller functions for a separate array designated as a primary array (i.e., each adapter functions as an array controller). There are also a plurality of adapters that have secondary control of each storage array. A secondary adapter controls a designated storage array when an adapter primarily controlling the designated storage array is unavailable. The adapter communication interface interconnects all adapters, including secondary adapters. Interconnectivity of the adapters is provided by a Serial Storage Architecture (SSA) which includes SCSI as a compatible subset. Judd indicates that the SSA network could be implemented with various topologies including a switched configuration.
However, the Judd system elements are interconnected in a configuration that comprises three separate loops, one of which requires four separate links. Therefore, this configuration is complex from a connectivity standpoint, and has disadvantages in areas including performance, physical cabling, and the host involvement required to implement the technique. The performance of the Judd invention for data replication and failover is hindered by the xe2x80x98bucket brigadexe2x80x99 of latency to replicate control information about commands in progress and data movement in general. The physical nature of the invention requires many cables and interconnects to ensure fault tolerance and total interconnectivity, resulting in a system which is complex and error prone. The tie-in with host adapters is host operating system (O/S) dependent on an O/S platform-by-platform basis, such that the idiosyncrasies of each platform must be taken into account for each different O/S to be used with the Judd system.
Therefore, there is a clearly felt need in the art for a disaster tolerant data storage system capable of performing data backup and automatic failover and failback without the direct involvement of the host computer; and wherein all system components are visible to each other via a redundant network which allows for extended clustering where local and remote sites share data across the network.
Accordingly, the above problems are solved, and an advance in the field is accomplished by the system of the present invention which provides a completely redundant configuration including dual Fibre Channel fabric links interconnecting each of the components of two data storage sites, wherein each site comprises a host computer and associated data storage array, with redundant array controllers and adapters. The present system is unique in that each array controller is capable of performing all of the data replication functions, and each host xe2x80x98seesxe2x80x99 remote data as if it were local.
The xe2x80x98mirroringxe2x80x99 of data for backup purposes is the basis for RAID (xe2x80x98Redundant Array of Independent [or Inexpensive] Disksxe2x80x99) Level 1 systems, wherein all data is replicated on N separate disks, with N usually having a value of 2. Although the concept of storing copies of data at a long distance from each other (i.e., long distance mirroring) is known, the use of a switched, dual-fabric, Fibre Channel configuration as described herein is a novel approach to disaster tolerant storage systems. Mirroring requires that the data be consistent across all volumes. In prior art systems which use host-based mirroring (where each host computer sees multiple units), the host maintains consistency across the units. For those systems which employ controller-based mirroring (where the host computer sees only a single unit), the host is not signaled completion of a command until the controller has updated all pertinent volumes. The present invention is, in one aspect, distinguished over the previous two types of systems in that the host computer sees multiple volumes, but the data replication function is performed by the controller. Therefore, a mechanism is required to communicate the association between volumes to the controller. To maintain this consistency between volumes, the system of the present invention provides a mechanism of associating a set of volumes to synchronize the logging to the set of volumes so that when the log is consistent when it is xe2x80x9cplayed backxe2x80x9d to the remote site.
Each array controller in the present system has a dedicated link via a fabric to a partner on the remote side of the long-distance link between fabric elements. Each dedicated link does not appear to any host as an available link to them for data access; however, it is visible to the partner array controllers involved in data replication operations. These links are managed by each partner array controller as if being xe2x80x98clusteredxe2x80x99 with a reliable data link between them.
The fabrics comprise two components, a local element and a remote element. An important aspect of the present invention is the fact that the fabrics are xe2x80x98extendedxe2x80x99 by standard e-ports (extension ports). The use of e-ports allow for standard Fibre Channel cable to be run between the fabric elements or the use of a conversion box to covert the data to a form such as telco ATM or IP. The extended fabric allows the entire system to be viewable by both the hosts and storage.
The dual fabrics, as well as the dual array controllers, dual adapters in hosts, and dual links between fabrics, provide high-availability and present no single point of failure. A distinction here over the prior art is that previous systems typically use other kinds of links to provide the data replication, resulting in the storage not being readily exposed to hosts on both sides of a link. The present configuration allows for extended clustering where local and remote site hosts are actually sharing data across the link from one or more storage subystems with dual array controllers within each subsystem.
The present system is further distinguished over the prior art by other additional features, including independent discovery of initiator to target system and automatic rediscovery after link failure. In addition, device failures, such as controller and link failures, are detected by xe2x80x98heartbeatxe2x80x99 monitoring by each array controller. Furthermore, no special host software is required to implement the above features because all replication functionality is totally self contained within each array controller and automatically done without user intervention.
An additional aspect of the present system is the ability to function over two links with data replication traffic. If failure of a link occurs, as detected by the xe2x80x98initiatorxe2x80x99 array controller, that array controller will automatically xe2x80x98failoverxe2x80x99, or move the base of data replication operations to its partner controller. At this time, all transfers in flight are discarded, and therefore discarded to the host. The host simply sees a controller failover at the host OS (operating system) level, causing the OS to retry the operations to the partner controller.
The array controller partner continues all xe2x80x98initiatorxe2x80x99 operations from that point forward. The array controller whose link failed will continuously watch that status of its link to the same controller on the other xe2x80x98farxe2x80x99 side of the link. That status changes to a xe2x80x98goodxe2x80x99 link when the array controllers have established reliable communications between each other. When this occurs, the array controller xe2x80x98initiatorxe2x80x99 partner will xe2x80x98failbackxe2x80x99 the link, moving operations back to newly reliable link. This procedure re-establishes load balance for data replication operations automatically, without requiring additional features in the array controller or host beyond what is minimally required to allow controller failover.

System for data replication using redundant pairs of storage controllers, fibre channel fabrics and links therebetween

Hewlett-Packard Development Company, L. P.


According to various embodiments, a circuit arrangement may be provided, comprising a driver circuit configured to deliver a switching signal to a power switch such that the power switch controls a load current, a gate-back regulation circuit selectively connected to the driver circuit and the load current, and a diagnostic circuit configured to provide an enabling signal, which allows the gate-back regulation circuit to become active; and wherein the enabling signal is dependent at least in part on a condition independent of the load current.

In circuit arrangements which have a power transistor for switching or regulating a current flowing through a load, it may be necessary to measure a load current flowing through the power transistor. A sense transistor is provided which is connected in such a way that it is operated at approximately the same source, gate, and drain voltages as the power transistor, i.e., the same operating point. The current through the sense transistor is then directly related to the load current; the ratio of the currents through the power and the sense transistors is called KILIS ("K"):
  K  =                    I        load                    I        sense              .
If operated at exactly the same operating point, K will remain constant. However, due to manufacturing differences, the transistors are not operated at the same operating point. K will have a "spread" between a minimum and a maximum value. As the accuracy of K is important for the circuit arrangement, this spread should be kept within prescribed bounds. FIG. 7 illustrates typical diagnosis behavior of K for a diagnosis current proportional to a load current under different operating conditions. In particular, maximum and minimum values of K at various load currents are shown, indicating the spread of K.
With gate back regulation ("GBR") the power and sense transistors are operated at a constant drain voltage. It is common to use GBR to improve accuracy at low load currents. The principle is to regulate the drain-source voltage to a constant voltage by decreasing the gate voltage.
In systems with GBR, sudden activation of a high-current load can cause a load step (i.e., a current jump) of sufficient magnitude resulting in a significant voltage drop over a corresponding module switch. The normal lag in operation of GBR during a load step with such a voltage drop may inadvertently trigger an under-voltage shutdown in a microcontroller. This case is illustrated in FIGS. 8A and 8B, in which a circuit arrangement 800 includes a module 801, a pre-regulator 804, a microcontroller 803, and a load switch 802. In case module 801 is turned on, the current (IOUT in FIGS. 8A and 8B) may be low, such that module 801 operates in GBR mode. Load switch 802 is turned on, causing VOUT to decrease, which requires some time to return to its previous level. An undervoltage condition, as seen in FIG. 8B, could then occur.
Additionally, power consumption may be affected by whether GBR mode is used. This is illustrated in FIG. 9, which compares power consumption for various currents with and without GBR mode.

Circuit arrangement and a method for operating a circuit arrangement


A method, apparatus, and product for reducing resource footprints for printer operation outputs, comprising: specifying a print job rendering criteria; receiving a request to print a print job having a page number amount; and automatically selecting and printing a portion of the print job as a function of the print job rendering criteria, wherein the portion has a page number amount smaller than the print job page number amount. The print job rendering criteria may comprise a set maximum number of pages to print during one printing session, where the portion to print is less than or equal to the maximum number of pages. Where the print job comprises a plurality of document components, automatically selecting and printing a portion of the document may comprise selecting a subset of the plurality of components as a function of the identified component relevance to each selected component and printing the representation.

Green computing is sometimes defined as the study and practice of using computing resources efficiently. Typically, technological systems or computing products that incorporate green computing principles take into account economic viability, social responsibility, and environmental impact. A typical green computing method includes implementing environmentally friendly products, like those with the Energy Star rating, in an efficient system that maximizes energy use.
A multitude of different types of printers exist in almost every industry, including many older, inefficient models, for example including those without the Energy Star rating. Many of these inefficient printers are widely used in offices and homes, having become a standard piece of any computing system. Since printers are used so regularly, a green computing method is needed specifically to reduce the amount of excess waste that occurs during printing based on the availability and use of inefficient printers.
One goal of green computing is for computing products to create smaller carbon footprints through source reduction. A carbon footprint is the gauge of the impact that commercial activities have on the environment in terms of the amount of greenhouse gases produced. Source reduction involves the practice of creating, purchasing, and using materials in ways that reduce the amount of waste created. Known source reduction methods implemented to reduce printing tasks generally include, for example: printing only when a hard copy is needed, saving e-mails and other documents to a computer hard drive or on a diskette, reading e-mails and other documents on-line or on-screen, using the highest-quality printing setting only for final copies while using "economy" settings for drafts, and printing multiple pages per sheet. Such methods do not offer ways to reduce printer usage associated with accidental or excessive printing, or offer ways to reduce the carbon footprint of printers through reducing waste of energy and other resources associated with the unintentional printing.
Thus, there is a need for improved methods and systems that address the above problems, as well as others.

International Business Machines Corporation


In a computer game, a game situation is analyzed using states of a plurality of game elements by determining a state for each of the plurality of game elements, generating a representation of a Voronoi diagram among the game elements, using at least some of the game elements as Voronoi sites and performing an analysis of the game situation using the Voronoi diagram. The analysis can be spatial analysis and/or tactical analysis to determine a move of a computer-controlled entity based on the tactical analysis. The game space might represent playing spaces for soccer, baseball or basketball. The state of a game element might include momentum, speed, and direction of travel, velocity and/or team association of the game element. For a soccer game analysis, multiple Voronoi diagrams might be generated and the analyses done using the multiple Voronoi diagrams.

The present invention relates to computer games in general and more particularly to analyzing game situations and displaying analysis results in graphical forms in a computer game.
A typical competitive computer game involves a human opponent and a computer opponent. Such competitive computer games include chess, auto racing, fantasy games, and sports games. For a game to retain the interest of the human opponent, it should be a good enough opponent that the human opponent does not win every time. Thus, there is an element of analysis required in all but the simplest competitive computer games. This analysis is done on a current game situation and might be used by the computer game to determine a next move of the computer opponent.
For example, where the game is chess, the computer game is programmed :to analyze a game situation, namely the current location of the chess pieces on the chess board and possibly also the history of moves made by the human opponent, and then make a decision as to what move to make in response to that game situation. The rules of chess constrain the analysis and responses and the computer need only decide, for each move, which of sixteen or fewer pieces to move to one of a few dozen spaces in a board constrained to only 64 distinct locations. Therefore, determining all of the possible moves is a simple matter. Of course, computer opponents in chess are difficult to program, but that is because moves must be anticipated many moves into the future.
With racing games, the computer-operated racecar or object just needs to be moved along a track quickly. With fantasy games, the possible actions can be arbitrary. Sports games and other competitive games that simulate real-world activities in a realistic way are more difficult in part because the field is not a small discrete set of positions and the game must behave as the human opponent would expect in the corresponding real-world activity.
As one example, the game of soccer involves several players and a ball that are free to move anywhere in a continuous two-dimensional space (possibly a three-dimensional space if player jumps and ball height are taken into account). Soccer strategy involves many considerations, such as trying to position players so that one player can kick the ball to a teammate without interference from a player on the opposing team. In order for a computerized soccer game played between a human opponent and a computer opponent to be interesting, the computer opponent must present a challenge to the human opponent and therefore, the computer game must perform in depth analysis of the game situation and determine how to move and manipulate the computer opponent team members to present that challenge. Preferably, the computer analysis is efficient enough that, given some limited amount of computing power available to the computer game, the game can analyze a game situation and fashion a suitable response in real-time.
In a computer game, one embodiment of the present invention provides for analyzing a game situation using states of a plurality of game elements by determining a state for each of the plurality of game elements, generating a representation of a Voronoi diagram among the game elements using at least some of the game elements as Voronoi sites and performing an analysis of the game situation using the Voronoi diagram. The analysis is a spatial analysis that might be used as the basis of a tactical analysis to determine a move of a computer-controlled entity. In a specific embodiment, the game space is a two-dimensional soccer field and the game elements are players having associated teams. The game space might be a three-dimensional game space. The game space might represent a baseball field, a basketball court or other game space besides a soccer field.
The state of a game element might include momentum, speed, direction of travel, velocity and/or team association of the game element. The analysis for a soccer field might include determining passing lanes between players of the computer-controlled team. For a soccer game analysis, multiple Voronoi diagrams might be generated, such as Voronoi diagrams for each team""s players without the goalies, diagrams for each team""s players with the goalies and diagrams for combinations of two teams"" players with and without goalies and the analyses done using the multiple Voronoi diagrams.
Other features and advantages of the invention will be apparent in view of the following detailed description and preferred embodiments.

Use in computer games of voronoi diagrams for partitioning a gamespace for analysis


The present disclosure includes the production of a mutant plant resistant to an herbicide of the phosphonomethylglycine family, e.g. glyphosate. Compositions and methods are provided for editing a nucleotide sequence of interest in a cell employing a guide polynucleotide/Cas endonuclease system, wherein the Cas endonuclease is guided by a guide polynucleotide to recognize and optionally introduce a double strand break at a specific target site into the genome of a cell. The nucleotide sequence of interest to be edited can be located within or outside the target site that is recognized by a Cas endonuclease. More specifically, compositions and methods are provided for editing an enolpyruvylshikimate-3-phosphate synthase (EPSPS) nucleotide sequence in a cell. The methods and compositions employ a guide polynucleotide/Cas endonuclease system to provide for an effective system for editing EPSPS nucleotide sequences of within the genome of a cell. Also provided are compositions and methods for the production of glyphosate tolerant plant cells, plants explants, seeds and grain.

Herbicide resistant plants may reduce the need for tillage to control weeds thereby effectively reducing costs to the growers. Development of crops with increased herbicide resistance has been a major breakthrough in current agriculture practices as it has provided farmers with new weed control options.
One herbicide which is the subject of much investigation in this regard is N-phosphonomethylglycine, commonly referred to as glyphosate. Glyphosate inhibits the shikimic acid pathway which leads to the biosynthesis of aromatic compounds including amino acids, hormones and vitamins. Specifically, glyphosate curbs the conversion of phosphoenolpyruvic acid (PEP) and 3-phosphoshikimic acid to 5-enolpyravyl-3-phosphoshikimic acid by inhibiting the enzyme 5-enolpyruvylshikimate-3-phosphate synthase (referred to as EPSPS). Plant genetic engineering methods have been used to modify EPSP synthase DNA and the encoded proteins, and to transfer these molecules into plants of agronomic importance. Variants of class I EPSPS have been isolated (Pro-Ser, U.S. Pat. No. 4,769,061; Gly-Ala, U.S. Pat. No. 4,971,908; Gly-Ala, Gly-Asp, U.S. Pat. No. 5,310,667; Gly-Ala, Ala-Thr, U.S. Pat. No. 5,866,775) that cause resistance to glyphosate. However, many EPSPS variants are not effective enzymes for use in plants (Padgette et. Al., in "Herbicide-resistant Crops", Chapter 4 pp. 53-83. ed. Stephen Duke, Lewis Pub, CRC Press Boca Raton, Fla. 1996). One class I EPSPS variant, T-102-I/P-106-S(TIPS) that is operably linked to a heterologous promoter has been shown to provide glyphosate (N-phosphonomethylglycine) resistance to transgenic maize plants (U.S. Pat. No. 6,040,497).
There remains a need for the development of herbicide-resistant crops and for glyphosate resistant crops in particular. There is also a need to develop herbicide-resistant plants of agronomic value that contain mutated genes obtained through gene editing wherein the mutation of the gene results in herbicide resistance.
Compositions and methods for producing mutant plants that exhibit herbicide resistance, and glyphosate resistance specifically, are provided.

Compositions and methods for producing plants resistant to glyphosate herbicide


According to one embodiment, an ultrasonic probe includes a plurality of ultrasonic transducers, an electronic circuit, an insulative heat conductive spacer and an electrical heat supporting element. The electronic circuit is electrically connected to a plurality of transducers on one side. The insulative heat conductive spacer contacts with another side of the electronic circuit. The electrical heat supporting element has a contact region that makes contact, in a first surface, with the insulative heat conductive spacer, and a supporting structure that supports the insulative heat conductive spacer to have a predetermined thickness, and diffuses heat generated by the electronic circuit from the contact region.

As an ultrasonic probe utilized in ultrasonic diagnostic apparatuses, there is an array-type ultrasonic probe in which a plurality of ultrasonic transducers are arrayed. Recently, in particular, a two-dimensional array probe makes its market debut, in which a plurality of ultrasonic transducers is two-dimensionally arrayed, allowing three-dimensional scanning for a diagnostic target region of an object.
In an ultrasonic probe having a huge number of ultrasonic transducers (i.e., the number of channels) typified by such a two-dimensional array probe, the number of wiring required for transmission and reception between the ultrasonic probe and the body of the ultrasonic diagnostic apparatus is also apt to be a huge number. This may consequently lead to a large-sized ultrasonic probe and a reduction in cable-operability.
To prevent such a problem, a means is provided so that at least part of electronic circuits for executing ultrasonic transmission and reception is provided, as ASICs (Application Specific Integrated circuits), in an ultrasonic probe, not in an ultrasonic diagnostic apparatus, and after generating a drive signal, or making the number of received signals in a predetermined signal number, in the ultrasonic probe, these signals are then sent to the ultrasonic diagnostic apparatus body. In this case, to miniaturize the ultrasonic probe, there may be a case where the ASIC is provided as a bare chip. (In general, an ASIC is encapsulated in a package, such as plastic, and the package is mounted on the board. The wording "an ASIC as a bare chip" means an ASIC in a state of being free from such a package. By mounting an ASIC as a bare chip on a board, for example, miniaturization by one package can be realized.)
However, if an ASIC is provided in an ultrasonic probe, there is a need to diffuse a quantity of heat generated by the ASIC. If the ASIC provided in the probe is a bare chip, the diffusion of the quantity of heat generated by the ASIC is a further significant technical problem. In order to efficiently diffuse the quantity of heat generated by such an ASIC and a quantity of heat generated by each ultrasonic transducer, conventional ultrasonic probes adopt methods such as using a cooling medium to aggressively cool heat (active cooling method), or a method of diffusing heat by contacting a heat conductive member with the heat source without using a cooling medium (passive cooling method).