Method for determining the bounding box of a computerized graphic shape comprising one or more primitives described in vectorial mode, wherein the bounding box is calculated by applying analytical mathematical formulas to the vectorial description of the primitives constituting the shape without preliminarily performing a phase of drawing and displaying of the shape through resolution of the vectorial primitives that compose it.

1. Technical Field of the Invention
The present invention relates in general to computer graphics and to vectorial image processing. The present invention more specifically concerns a method for the calculation of the bounding box of vectorial graphic shapes, in the context of vectorial image processing; by the term "bounding box" there is intended the smallest rectangle that circumscribes a digital graphic shape when the latter is positioned on a page (for instance a Web page), or however displayed on a screen, for instance the screen of a Personal Computer, or printed on a support of paper or other material.
2. Discussion of the State of the Art
The trend in modern developments in the field of Web and graphic interfaces is toward solutions of the declaratory type. The application software is written using more and more complex semantics and at a high level, so as to facilitate and to accelerate the project and implementation tasks. This is made possible thanks to the availability of engines for the interpretation of high-level and more and more sophisticated and complex languages. Many of these engines have been developed in the field of the Web, because the HTML (HyperText Markup Language) paradigm is the most common for the development of complex software applications. There are several examples of this type of engines. The Web browsers themselves, normally exploited by the users for the navigation in the World Wide Web, are interpreters of the HTML syntax (or of evolutions thereof), which is a specialization of the XML (eXtensible Markup Language) syntax. The Flash technology is another example, not limited to the graphic aspects, but also with functionality of application intelligence. XAML (eXtensible Application Markup Language) and XUL (XML User interface Language) by Microsoft and Mozilla, respectively, are other examples of engines that associate application logics to the creation of Graphical User Interfaces (GUI) through scripting languages capable of extending the functionalities, for instance allowing queries on remote databases, access to Web services or use of the network interfaces.
At the base of all these solutions there is a bidimensional (2D) vectorial graphic interpretation engine, capable of interpreting a syntax of the XML type transforming it into graphic primitives compliant with the used rendering libraries (in the field of computer graphics, the term "rendering" identifies the process of render, i.e. of generation of an image starting from a description thereof, for instance a mathematical description, provided in a determined language and interpreted by the graphic engine).
As known in the field, the vectorial modality provides for a generic digital graphic shape to be represented through one or more primitive graphic shapes (primitive curves), like for instance segments, circles etc. Every primitive curve is described through a respective mathematical equation on the base of parameters (so-called "control points") apt to univocally identify it.
The vectorial representation modality of graphic shapes is advantageous since it operates with continuous functions and allows a total control of the primitives, and therefore of the graphic shapes to be represented. Particularly, by modifying the number and the position of the control points of the primitives it is possible to trace almost any graphic shape. Additionally, the vectorial representation modality occupies less memory resources compared to other representation modalities (like for instance the raster modality), and also the amount of data to be transferred (for instance through a network connection) is limited.
The graphic interpretation engines, particularly those of vectorial type, have the purpose of providing to the programmer high-level semantic constructions for the development of sophisticated graphic interfaces. The offered functionalities can be summarized in the following macrofamilies:                bidimensional shapes: elementary geometric images (primitives) are foreseen, like circles, rectangles with rounded edges, ellipsis, lines, polygons and polygonal lines (non-closed broken lines). Additionally, complex images are foreseen, known as "paths", that are described as sets of elementary geometric images, with the addition of Bezier curves, with the purpose of allowing the greatest possible graphic flexibility. The concept of transformation is associated with the primitives, which in the 2D case is an affine 2D transformation;        "fill & stroke": by this terms there are intended graphic primitives displayed using separate concepts of contour and filling. These constructions have vectorial characteristics different from each other: the contour is characterized by thickness, hatch, modes of junction and termination; the filling has instead associated therewith the concept of mode of filling (this is meaningful in particular for non-convex images). However, these constructions also have vectorial characteristics in common, known as "paint servers", that identify the color by which the shape, that corresponds to the semantic construction, is drawn. The color can have simple characteristics, as in the case of solid color, or complex characteristics, as in the case of linear or radial color gradients. In this last case, the gradients are described by a vector that describes the direction of variation of the color, and by a list of "stop colors" that describes the trend of the colors in the form of a broken curve where the interpolation between two adjacent stop colors is linear.        video, images and audio: an important semantic functionality is the ability to insert and to check multimedia contents inside the displayed graphic scene;        animations: these are semantic constructions for modifying in a predetermined way the temporal evolution of the properties of the primitives;        interaction: the graphic engine is able to manage user events (like for instance movements of the mouse, clicks, inputs of keyboard commands) and to trigger the start, the end or in general to modify the temporal evolution of animations;        script and DOM (Document Object Model): the constructions described above, even being very powerful, cannot cover the whole range of possible functionalities needed by an author. The ability to describe through a program non-predefined behaviors is made possible by the ability of the graphic engine to execute interpreted high-level code, like Java or Javascript. The possibility to use interpreted code involves the availability of an API (Application Programming Interface) that the code can invoke for accessing in reading and writing the semantic information of the primitives. In order to be able to enter and update by means of a program the content of such information, the so-called DOM is generally used, which is a mode of representation of the documents structured as an object-oriented model.
The dominant feature is the vectoriality: all the graphic primitives and the contour constructions (animations, interaction, scripting) are always described and used in vectorial mode.
There are many examples of standardized or proprietary engines that offer semantic functionalities referable to those described above; one of these is the Scalable Vector Graphics (SVG) engine of the W3C (World Wide Web Consortium).
In general, a vectorial graphic engine receives a description of a vectorial graphic scene to be drawn. The graphic scene is normally described in XML and it is composed by a hierarchy of nodes (father and children) represented by a tree of inheritance. The nodes can be "container" type nodes, that is, they are not susceptible of a graphic representation but act as containers of other nodes, or the nodes can be shapes or graphic primitives, that is, they do have a graphic representation.
A problem of significant complexity is the calculation of the bounding box of a graphic primitive. This functionality is essential for the following reasons:                use by the interpreted script code: in order to be able to manipulate the properties of complex primitives, or of groups of complex primitives, the calculation of the bounding box needs to be made available on the API of the DOM, that allows the author to check the encumbrance of the complex and composed primitives;        vectorial features expressed in relative way: the gradients of the vectors can for instance be represented in the system of coordinates of the complex primitive (instead of being represented in the user reference system used by the primitive that exploits it, or even in document coordinates);        manipulation of the graphic objects through visual editing tools of the WYSIWYG (What You See Is What You Get) type: the movement, the rotation, the scaling of the dimensions of the graphic primitive inside the scene through visual paradigms using pointing tools like a mouse and a keyboard usually exploit the concept of bounding box drawn around to the primitive(s) selected by the user at a given time.
The bounding box, also known in literature as "Minimum Bounding Rectangle" (MBR), has the followings features:                it has to be calculated as the smallest rectangle that contains the complex image without intersecting it;        it shall not take into account the transformations that the complex image receives in inheritance from the primitives that contain it. This is due to the strongly hierarchical semantics of SVG. A primitive can be contained by other elements (fathers). The propagation of the node properties from the father node to the child node follows different rules depending on the properties: in the case of affine transformations, the applied rule is the accumulation.
The bounding box information is not strictly linked to the current drawing of the scene. Particularly, the necessity of providing the bounding box information also to the script code that is executed inside the scene foresees that the calculation of the bounding box might be requested also in respect of primitives that are not subsequently visible, which are not in the drawing branch of the tree that describes the scene, or that have a series of inherited parameters that do not follow the inheritance rules of the tree. For instance, it may be necessary to have the bounding box of a group of primitives taking into account the transformation inherited from their fathers. This means having available the encumbrance of the complex primitive before every transformation that projects it into the general scene. Another example that shows how it may be possible to require the calculation of the bounding box for composed primitives that are not visible is the case of the creation of a description branch of the scene through a program (through a script code): in this case the code can create a branch of description of the scene and it may require the bounding box thereof before this is inserted in the main tree.
From a functional point of view, the task of calculating the bounding box of a complex primitive is to be associated with the part of the graphic engine that manages the drawing, that is, that phase that transforms the information present in the tree description of the scene into bidimensional drawing, graphic primitives.
In modern rendering techniques, due to the increasing complexity of the scenes to be drawn, the hardware acceleration made possible by the graphic processors (for instance, Graphic Processing Unit—GPU) is exploited. Machines devoted to the management of the graphics are fed with series of primitives in a complex processing chain (a pipeline). Many types of processing pipelines exist, the most common being those used in three-dimensional videogames through APIs known as Direct3D (Microsoft) and OpenGL (Linux etc.). In general, the rendering process is under the control of a processing unit different from the main CPU, or however under the control of a processing task different from that managing the remaining of the application.
In general, as for instance described in S. Conversy J. D. Fekete, "The svgl toolkit: enabling fast rendering of rich 2D graphics", Technical Report 02/1/INFO, Ecole des Mines de Nantes, 2002, in order to be able to require to the renderer (the hardware processing unit or the firmware or software task that performs the operations necessary for the rendering) to calculate the bounding box, it is necessary to send thereto the list of the primitives and the related properties, and then wait for the renderer task to take over the information, and feed the draw processing pipeline; the processing pipeline shall thereafter execute all the operations waiting in the queue and eventually it provides the result. Particularly, for calculating the bounding box the renderer simulates the process of rendering of the branch of tree inside which there is the primitive, as if the renderer should display the graphic shape described by the primitive, even if the display on the screen of the primitive is not necessary.
Since, normally, the processing pipelines are exclusively able to draw pixels and not primitives expressed in vectorial way, it is necessary (through software or using hardware functionalities provided for in the pipeline) to decompose the vectorial primitive in simple linear primitives (for example lines or triangles) compatible with the way of operation of the pipeline; this operation is known as tessellation. After the tessellation, the calculation of the bounding box is relatively simple, since it is a by-product of the tessellation operation results (consisting in the identification of the minimum and of the maximum—in the selected system of coordinates—among all the generated vertexes).
U.S. Pat. No. 6,512,847 shows a technique for the calculation of a frame around a Bezier curve. The frame corresponds to a Bezier curve that approximates the trend of the original Bezier curve spaced apart of an arbitrary distance. In this case, an approximation is employed that eventually imposes the definition of a "mid point" inside the curve through known algorithms and the related calculation of the new "control points" decomposing the curve in sub-curves of lesser length.
WO 2004/100071 proposes a method for the analytical deformation of Bezier curves; the deformation is set through an interaction with the user keeping fixed the initial and final controls points and sectioning or joining different curves for best approximating the desired deformation. The requisite of providing curves parallel to the original one is not considered.

Method for the calculation of the bounding box of vectorial graphic shapes


A fulfillment server (16) for managing ATP data in a distributed supply chain planning environment receives an ATP request (30) from one of multiple clients (12). The ATP request (30) includes multiple request line-items that each correspond to a desired product. The fulfillment server (16) then generates one or more component ATP requests (32) based on the request line-items and communicates component ATP requests (32) to at least one of multiple local fulfillment managers (14). In response, the fulfillment server (16) receives component quotations (34) from the local fulfillment managers (14), each corresponding to a component ATP request (32) and each including product availability information for the corresponding desired product. The fulfillment server (16) generates a quotation (36) that includes product availability information for all desired products, according to the component quotations (34), and communicates the quotation (36) to the client (12).

Large and complex supply chains are typically managed by multiple planning organizations, each supporting one or more planning engines appropriate for the needs of the organization. For example, one organization might support a supply chain planner (SCP) engine, another might support a factory planner (FP) engine, and another might support yet another type of planning engine. As a result, matching of supply and demand, product allocation, and order promising and fulfillment tasks are likely to be managed using a variety of logically or geographically distributed planning engines. This presents numerous difficulties for customers and suppliers alike.
A lack of detailed visibility into extended supply chain operations often prevents companies from quoting accurate delivery dates and meeting customer orders in a timely manner. Even when there is adequate visibility, a lack of integration between front-end and back-end business objectives may result in lower margin products using up capacity, important market channels receiving worse service than less important market channels, and other sub-optimal commitments. Also, once delivery date and other commitments have been made, it is necessary to monitor the commitments throughout the production and logistics execution process to determine the effect of unexpected supply and demand changes. Accordingly, in a distributed supply chain planning environment, there exists a need for a single and consistent interface to the customer for order promising and fulfillment. The inability to provide such a capability negatively impacts order capture rates, delivery performance, and administrative costs associated with inventory, order processing, and other activities.
Despite numerous attempts in recent years, none have succeeded in creating an effective solution to manage order promising and fulfillment tasks across a network of computers in a distributed supply chain planning environment. While some companies have developed acceptable front-end or "customer-centric" solutions, and others have devoted tremendous energy to achieving suitable back-end supply chain optimization solutions, none have successfully integrated these front-end and back-end solutions to intelligently manage order promising and fulfillment tasks in this environment. As a result, for example, companies routinely over-promise and then lose money attempting to fulfill the commitments they have made, usually with mixed success. To compete effectively in the growing global Internet-based economy, companies must be able to make accurate commitments, aligned with business objectives of the company, and to fulfill their commitments in an efficient and profitable manner.
Furthermore, in such multi-enterprise endeavors, it is often economically or at least politically infeasible to completely re-deploy systems throughout the supply chain. Thus, for a solution system to be routinely deployable in most situations, it must have the ability to accommodate existing systems such that their capabilities are extended while allowing more sophisticated replacement systems to be subsequently introduced. The solution system must ultimately be able to productively co-exist with such existing or replacement systems. Previous techniques for the management of order promising and fulfillment are inadequate to meet these needs.

System and method for managing ATP data in a distributed supply chain planning environment


An endoscope system includes a first endoscope having a first observation optical system with a first viewing angle and a first illumination optical system; and a second endoscope having a second observation optical system with a second viewing angle wider than the first viewing angle and a second illumination optical system. A second illumination region of illuminating light that is emitted by the second illumination optical system and has a predetermined illuminance is wider than a first illumination region of illuminating light that is emitted by the first illumination optical system and has a predetermined illuminance, at any imaging distance that is pointed in an observation direction from a distal end of an insertion portion of each of the first endoscope and the second endoscope.

1. Field of the Invention
The present invention relates to an endoscope, and more particularly to an endoscope system including two endoscopes that are different from each other in viewing angle.
2. Description of the Related Art
Conventionally, an endoscope has been widely used in a medical field and the like. The endoscope is employed to observe organs and the like inside a body cavity by inserting an elongate insertion portion into the body cavity, and to operate various treatments by using a treatment instrument that is inserted into a treatment instrument insertion channel, if necessary. A bendable portion is provided at a distal end of the insertion portion, and an observation direction of an observation window of the distal end portion is changed by manipulating a manipulating portion of the endoscope.
A viewing angle of the conventional endoscope is, for example, 140° (degree), and an operator observes inside the body cavity by an observation image corresponding to the viewing angle. When the operator desires to observe a region outside a region corresponding to a field of view during the observation inside the body cavity, the operator can bend the bendable portion to observe such region.
On the other hand, an endoscope having a wider viewing angle has been proposed to allow an observation of a wider region. The endoscope has an advantage that the observation is easily performed and a region necessary to be treated is easily found since an imaging region is widened by having the wide viewing angle (for example, see Japanese Patent Application Laid-Open No. H4-102432).


A cutting nozzle for a gas torch, such as a postmixed oxy-fuel gas torch, comprising a body with a torch end adapted to engage the gas torch, a discharge end, and a peripheral surface between the torch end and the discharge end. The body has a plurality of bores for respectively conducting fuel gas, preheat oxygen and cutting oxygen through the nozzle, each of the plurality of bores extending from the torch end and terminating in a respective discharge orifice at the discharge end of the body. A set of the plurality of bores are preheat oxygen bores connected to an oxygen source at the torch end for discharging the preheat oxygen at the discharge end. A plurality of air bores each have an inlet orifice located on the peripheral surface of the body and open to an air source, and a discharge orifice in or proximal to the discharge end.

Oxy-fuel gas cutting torches are commonly used for cutting ferrous alloys and some non-ferrous metals, as cuts can be effected through very thick billets. In operation, an oxy-fuel torch directs an ignited stream of oxygen and fuel gas onto the surface of the metal to be cut. The metal is thus heated to its ignition temperature, at which point a stream of cutting oxygen directed at the surface oxidizes the heated metal to effect the cut.
The cutting torch may be one of a premixed or a postmixed type torch. In a premixed torch, preheat oxygen and fuel gas are mixed within the torch head before being discharged for ignition. In a postmixed cutting torch, the preheat oxygen and fuel gas are discharged from the torch in unmixed streams. Turbulence in the discharged streams mixes the oxygen and fuel gas before ignition occurs. A principal advantage of the postmixed cutting torch is that it is not subject to flashback, a potential hazard associated with the use of premixed torches. Flashback occurs when the oxygen and fuel gas mixture in a premixed torch ignites within the torch head. Postmixed torches are therefore commonly employed for heavy industrial applications where a torch is subjected to considerable heat. A further advantage of the postmixed torch is that postmixed nozzles produce a longer and wider heat zone than premixed nozzles. This permits the postmixed torch to operate farther from the work, decreasing the heat stress on the torch and increasing the service life of the nozzle.
Many prior art postmixed nozzles for oxy-fuel gas torches operate in substantially the same way. A stream of cutting oxygen is discharged from an axial bore in the nozzle. A plurality of fuel gas discharge orifices arranged in a concentric ring around the axial bore discharge preheat fuel gas and a second plurality of gas discharge orifices arranged in an outer concentric ring discharge preheat oxygen which acts as an envelope that surrounds the fuel gas stream. As the gas streams flow toward the workpiece, a mixing of the fuel gas and the oxygen occurs and the mixture ignites to heat the workpiece.
An example of a prior art postmixed oxy-fuel gas cutting torch and nozzle is taught in the U.S. Pat. No. 6,277,323 which issued to Bissonnette on Aug. 21, 2001. That patent describes a combination cutting torch and nozzle assembly for postmixed oxy-fuel cutting using an annular streams of preheat oxygen gas surrounding a fuel gas stream. The nozzle assembly is secured to the head of the cutting torch by a hollow retaining nut which forms an annular gap with the nozzle assembly for discharging the outer preheat oxygen gas stream. The preheat oxygen gas is connected to a pure oxygen source (e.g., 99%+purity), and therefore discharges a sizable volume of pure oxygen during operation, to ensure a high flame temperature. Hence, pure oxygen consumption is an important cost factor in the operation of postmixed oxy-fuel gas cutting torches.

Cutting nozzle for a postmixed oxy-fuel gas torch


A new and distinct Malus domestica (Borkh.) apple tree variety is provided which exhibits a columnar tree type, moderate growth vigor, and Vf-resistance against scab. The new variety yields late maturing and ornamental fruits. The fruit color is medium red and the fruit size is large relative to other ornamental apples.

The present invention comprises a new and distinct cultivar of ornamental apple tree botanically classified as Malus domestica (Borkh.) and known by the varietal name 'ROSALIE'. The new variety is the result of a cross between 'Aneta' (female parent, unpatented) and 'Maypole' (male parent, U.S. Plant Pat. No. 6,184). The cross resulting in 'ROSALIE' occurred in the Spring of 1994 at 310 meters above sea level with a mean annual temperature of 7.7° C. and a mean annual precipitation of 680 mm. The purpose of the breeding program was to develop varieties of a columnar tree type with a unique appearance and resistance to scab. The new variety was discovered in 2002, with the first fruiting and flowering of the original seedling in The Czech Republic. Subsequently, the new variety was asexually reproduced in The Czech Republic by budding/grafting on apple rootstocks in the Spring of 2003.
The new variety is similar to 'Aneta' in that it exhibits the presence of Vf-resistance against scab. However, the new variety differs from 'Aneta' as 'ROSALIE' has a columnar tree type, reddish-purple flower color, smaller fruit size, and red-colored fruit flesh. Further, the new variety is similar to 'Maypole' in its columnar tree type, compact growth habit, purple color of unopened flowers, reddish-purple opened flower color, prominent petal veins, red fruit skin color, and red colored fruit flesh. However, the new variety is different from 'Maypole' as its petal shape is ovate instead of broadly elliptic, its petal position is overlapping instead of touching, and its fruit form is broadly globose conical versus globose conical. Further, the new variety has a larger fruit size, shorter fruit stalk, exhibits the presence of Vf-resistance against scab, and longer fruit persistence than 'Maypole'. The new variety is also similar to 'Redspring' (unpatented) in columnar apple tree type, red fruit skin color, and Vf-resistance against scab. However, 'Redspring' produces dessert apples, while the apples of 'ROSALIE' are only for ornamental use. The following characteristics also distinguish the new variety from other varieties known to the breeders:                Late fruit ripening, ornamental, diploid variety;        Columnar tree type;        Trees exhibit medium vigor;        The growth habit is compact with very short internodes;        Single flower type with a shallow cup form;        Unopened and opened flowers are reddish-purple;        Large fruit size relative to other ornamental apples;        Broadly globose-conical fruit shape;        Medium red fruit color;        Fruit flesh color is predominantly red with some white present;        Long fruit persistence; and        Vf-resistance against scab.
The new variety has been trial and field tested and has been found to retain its distinctive characteristics and remain true to type through successive asexual propagations.

Institute of Experimental Botany AS CR, V.V.I (UEB)


Apparatus and methods are disclosed for rapidly counteracting a transient low-pressure condition, that can occur intermittently in the exhaust section of a power plant or other such industrial facility upstream of exhaust fans as a result of an event that interrupts the generation and/or flow of exhaust gases, using jet nozzles disposed in the exhaust section and connected to a source of pressurized air or other suitable momentum material. By orienting the jet nozzles in a direction generally opposite to the flow of exhaust gas and actuating the system to release a burst of compressed air, for example in the event of a power plant interruption, the low-pressure condition can be ameliorated preventing damage to the exhaust section.

Power plant boilers typically are subject to an instant fuel flow interruption, or Main Fuel Trip (MFT), due to a multitude of safety and/or equipment protection reasons. When large boilers experience such an instantaneous fuel flow interruption, the hot gasses exiting the furnace rapidly contract as the furnace and flue gas temperatures decay. At the same time, the system Induced Draft and Booster fans continue to force flue gas through and out of the system, with the result that a vacuum condition can occur in the furnace, boiler casing and the associated ductwork upstream of the fan(s). Destructively high vacuum conditions resulting from these factors have caused boiler casing failures and ductwork collapses at numerous power plant installations.
Conventional methods of accommodating these occasional high vacuum conditions include the following:                1. Passive Protection. Passive protection is achieved by designing the boiler and ductwork to withstand the maximum negative pressure that could reasonably occur during a MFT or similar incident.        2. Active Protection. Active protection refers to implementing a mechanism or procedure for rapidly arresting or reducing the negative pressure-generating capability of the fan(s). This is typically accomplished by closing the fan inlet dampers, closing the fan inlet guide vanes, or changing the fan blade pitch for axial flow fans.
While the passive protection method, namely, designing all components to withstand the maximum transient vacuum conditions, is effective, the expense is often excessive. For flue gas treatment system retrofits, re-design and stronger reinforcements for the boiler casing and ductwork may be prohibitively expensive.
The active protection method of control can often also be effective, but it always involves making one or more system compromises. This is because the repositioning of the large dampers or fan blades requires a significant period of time, and during this period of time negative pressures continue to build in the system. There are conditions at some plants where unacceptable negative pressure transients result in spite of these control actions. The generic problem is further exacerbated by the common use of large axial fans for many flue gas retrofit projects. These axial-type fans have inherently slower control/response actions, and hence tend to give larger transient vacuum conditions for a MFT incident.
Accordingly, the prior art approaches to this problem are expensive, are only effective some of the time, and/or impose serious system design and operation limitations.

Furnace and ductwork implosion interruption air jet system


The drive circuit elements mounted on a heat resistant substrate for composing a thermal head were covered with a protective layer made of epoxy resin in the prior art. This epoxy resin is greatly different from the heat resistant substrate in the coefficient of linear expansion and is relatively high in Young's modulus, and therefore due to rise or fall of temperature in the manufacturing process, the shrinkage of the protective layer is greater than the shrinkage of the heat resistant substrate, and hence the heat resistant substrate is warped. Such warp may be eliminated by selecting a resin having a coefficient of linear expansion almost same as the coefficient of linear expansion of the heat resistant substrate as the material for the protective layer.

1. Field of the Invention
The present invention relates to a thermal head, and more particularly to improvements of the material for the protective layer for covering the plural drive circuit elements used for heating and driving a heating resistance element row of a thermal head.
2. Description of the Prior Art
FIG. 2 is a sectional view of a typical thermal head 1, which is referred to in the explanation of the prior art below, as well as the embodiment described below. The thermal head 1 comprises a heat resistant substrate 2 possessing an electric insulating property made of ceramics such as aluminum oxide Al.sub.2 O.sub.3. On the heat resistant substrate 2, a heat reserve layer 3 made of glass or similar material is formed, as being extending in a band form in the direction vertical to the sheet of paper in FIG. 2. At one side in the direction crossing the longitudinal direction of the heat reserve layer 3, for example, silver paste is printed to form a thick film common electrode layer 4.
Covering the entire surface of the heat resistant substrate 2, a resistance element layer 5 made of tantalum nitride Ta.sub.2 N or the like is formed. On the resistance element layer 5, in the upper part of the thick film common electrode layer 4, a thin film common electrode 6 extending parallel to the thick film common electrode layer 4 is formed of aluminum or other metal material, by thin film technology such as sputtering and etching. Relating to the heat reserve layer 3, on the opposite side of the thin film common electrode 6, plural band-shaped individual electrodes 7 are formed in plural rows in the direction vertical to the sheet of paper in FIG. 2, and the resistance element layer 5 enclosed by these thin film common electrode 6 and individual electrodes 7 is composed as a heating resistance element row 8 made of plural heating resistance elements.
On the individual electrode 7, plural drive circuit elements 9 for heating and driving selectively the heating resistance element row 8 are disposed parallel to the array direction of the heating resistance element row 8. To the drive circuit elements 9, thermal printing data and various control signals are supplied through signal lines 10 formed simultaneously when forming the individual electrode 7 on the heat resistance substrate 2. The drive circuit elements 9 possess bumps 11 for realizing connection with the individual electrode 7 and signal lines 10, which are connected by face-down bonding.
To the signal lines 10, an external wiring substrate 12 is connected. The external wiring substrate 12 comprises a support film 13 made of synthetic resin material, and a circuit wiring 14 formed on the support film 13. On the other hand, the heat resistance substrate 2 is adhered onto a cooling plate 15, with adhesive, which is formed by press forming or die-cast forming of, for example, aluminum. On the cooling plate 15, the external wiring substrate 12 is fixed through a spacer 16 made of synthetic resin material. Covering the thin film common electrodes 6 and individual electrodes 7, a wear-resistant layer 17 is formed by thin film technology such as sputtering, and the plural drive circuit elements 9 are entirely covered in the array direction with a protective layer 18 made of epoxy resin or the like.
This conventional thermal head involved the following problems.
(1) The protective layer 18 is made of epoxy resin. The epoxy resin has a coefficient of linear expansion of 2.0.times.10.sup.-5 .degree. C..sup.-1, and the ratio b/a of the coefficient of linear expansion b of the epoxy resin to the coefficient of linear expansion a of the substrate 2 is 2.74, which is significantly different from 0.73.times.10.sup.-5 .degree. C..sup.-1 of the ceramics used to compose the heat resistant substrate 2. The epoxy resin has a relatively high modulus of elasticity of 1300 kg/mm.sup.2.
On the other hand, to form the protective layer 18, an epoxy resin is applied to coat the entire surface of the plural drive circuit elements 9, and is hardened by heating at, for example, 120.degree. to 150.degree. C. Afterwards, when cooling to ordinary temperature of, for example, 25.degree. C., due to the difference in the coefficient of linear expansion, the protective film 18 shrinks more than the heat resistant substrate 2, and what is more the modulus of elasticity of the protective layer 18 of the epoxy resin is relatively large, so that the heat resistant substrate 2 may be warped in the direction vertical to the sheet of paper in FIG. 1.
In such warped state, when adhering the heat resistant substrate 2 and cooling plate 15, the layer thickness of the adhesive layer becomes nonuniform along the array direction of the heating resistance element row 8, and heat dissipation from the heating resistance element row to the cooling plate 15 becomes nonuniform. Such nonuniformity causes uneven contrast and lowers printing quality in thermal recording. As a result, the working efficiency drops in relation to positioning in this adhesion step. Besides, in connection of the signal lines 10 and external wiring substrate 12, positioning precision is lowered, and the job efficiency drops.
To prevent such inconveniences, if attempted to straighten the warp of the heat resistant substrate 2 by external force after hardening of the protective layer 18, the peripheral edge of the protective layer 18 may be easily cracked because of the large modulus of elasticity of the protective layer 18. In the event of such crack, for example, water may invade into the protective layer 18 to corrode the individual electrodes 7, or due to progress of corrosion, the individual electrodes 7 may be disconnected.
To avoid such problems, it is conventionally known to use a silicon resin for the protective layer 18. Such silicon resin is a so-called silicone rubber, and although its coefficient of linear expansion is also very different from that of the heat resistant substrate 2, it is relatively small in the modulus of elasticity. Accordingly, if a difference is caused in the contraction against the heat resistant substrate 2 due to temperature drop after forming the protective layer 18, the protective layer 18 is deformed elastically so that the heat resistance substrate 2 will not warp.
When using such silicon resin, however, since the elasticity is low, the hardness is low, and it is easily deformed when an external force is applied in the manufacturing process or during use, and the drive circuit elements 9 may be broken. Accordingly as in the conventional thermal head 1a in FIG. 1, a head cover 25 to cover the entire vicinity of the protective layer 18 is needed, and the number of parts increases, and the manufacturing process is complicated. The head cover 25 incorporates an elastic pressing member 27 inside of a groove 26 at a position opposite to signal lines 10, and the head cover 25 is fastened to the cooling plate 15 with a screw 28 through external wiring substrate 12 and spacer 16, and the external wiring substrate 12 is pressed and fixed to the signal lines 10.
Such protective layer 18 may contact with, in actual use, thermal paper 19 or transfer film, and in the case of silicon resin, the coefficient of friction is large when contacting, and paper jamming is likely to occur.
As described herein, the protective layer 18 of the conventional thermal head 1 is made of epoxy resin or silicon resin, and these resins involve the problems as mentioned above.


A system for electronic image signal processing is described for use in a system including high speed film scanning apparatus and residual based hierarchical storage and display apparatus wherein full resolution luminance and half resolution color signals are processed to directly generate tonescale corrected full resolution scene luminance signal for image encoding without the creation of full resolution intermediate RGB images.

In the art of electronic imaging, particularly in the special application of film scanning, digitizing and storage, film images are scanned to produce a data output representative of the red, green, and blue (RGB) image signals. Such a scanner is disclosed in U.S. Pat. No. 5,045,932.
The scanning apparatus disclosed in U.S. Pat. No. 5,045,932 includes two types of linear array sensors. One is a full resolution imager spectrally sensitive to "luminance" like information, referred to as a full resolution luminance sensor. The other is a lower resolution tri-linear imager spectrally sensitive to red, green, and blue (RGB) image information, referred to as a half resolution tri-linear RGB sensor. A line being scanned is imaged onto the array through a beam splitter. Luminance information is generated by spectrally tailoring luminance channel sensitivity to approximate luminance. The luminance sensor "sees" light from red, green, and blue channels.
Scene luminance tonescale information is not provided by the luminance sensor. Signal processing is described which interpolates the color data up to full resolution, extracts detail information from the luminance channel, and adds the detail information to each of the R, G, B channels to form full resolution RGB scanned data. The RGB data is interpolated up to full resolution before processing, and the luminance sensor is used to generate detail information only. This full resolution RGB data can be further converted to luminance, chrominance (YCC) data through the use of look-up tables and color matrices. It is known to use a linear matrix to convert the full resolution RGB information to obtain luminance, chrominance information. Because the scanned luminance channel is formed in film transmission space, independent of the RGB sensor, the luminance channel provides image detail with incorrect scene tonescale information. In addition, the full resolution chrominance output must be subsampled for use in certain residual-based hierarchical storage and display devices.
Typically, the scanned data signals are compressed by known methods such as described in U.S. Pat. No. 4,969,204 to reduce storage requirements which provide for image decomposition and recomposition and make available reduced resolution versions of an original image for quick display. The method disclosed in U.S. Pat. No. 4,969,204 makes use of a full resolution luminance, Y, and two low resolution chrominance C.sub.1 C.sub.2 signals to encode an image in a more efficient color space than that using RGB signals.
This hierarchical image decomposition system accepts corrected, full resolution luminance and full resolution chrominance data as an input and provides a hierarchical family of reduced resolution image files as output. Chrominance data is subsampled by 2X before processing as full resolution chrominance is not stored or retained. The system recomposes an image for display by converting the YCC data back to RGB space through the use of look-up tables and matrices. Therefore the luminance data must carry tonescale information.
Scanning systems as in U.S. Pat. No. 5,045,932 and color space conversion systems as in the U.S. Pat. No. 4,969,204 can be used in combination to produce a YC.sub.1 C.sub.2 signal for hierarchical image compression. However, this process is overly complex because it scans with full resolution luminance and low resolution RGB sensors, converts the data to full resolution RGB, then converts the full resolution RGB to subsampled chrominance and full resolution luminance. In addition, such processed luminance information for encoding does not provide the same tonescale as luminance information generated from tonescale corrected RGB data.

System for electronic image signal processing to provide a tonescale corrected full resolution luminance and two half resolution chrominance signals


One embodiment of the present invention provides a system for moving balances from at least one source account into a target account and subsequently reversing the movement. The system operates by receiving a request for a move/merge operation to move the balances from source accounts to the target account. In response to the request, the system creates a list of changes to the source accounts and the target account that are involved in moving the balances. The system stores this list of changes into a memory for later retrieval during a move/merge reversal operation. Next, the system performs the move/merge operation by applying the list of changes to the source accounts and the target account. When the system subsequently receives a request to reverse the move/merge operation, the system reverses the move/merge operation by retrieving the list of changes from the memory and applying the inverse of changes in the list to the source accounts and the target account. In a variation the on above-embodiment, the system validates the move/merge operation according to a set of business rules before performing the move/merge operation. For example, the set of business rules may ensure that the source and target accounts belong to the same financial statement category or the same business entity. In a further variation on the above embodiment, the system additionally creates move/merge audit journal entries to facilitate future auditing of the changes made during the move/merge operation.

1. Field of the Invention
The present invention relates to computer-based accounting systems. More specifically, the present invention facilitates reversibly moving or merging account balances from at least one source account into a target account in a general ledger accounting system.
2. Related Art
Move/merge operations are often used in general ledger accounting systems to facilitate corporate restatements, reclassifications or chart of account modifications. As the name implies, a move/merge operation moves balances from one account to another or xe2x80x9cmergesxe2x80x9d multiple balances into one.
Move/merge operations can be used for a variety of reasons. (1) A move/merge operation can be used to reflect the results of a corporate reorganization where the responsibility for a cost center is moved and the cost center number is changed to fit into the numbering scheme of the new owner. (2) In another example, when two organizations are being merged, a move/merge operation can be used to compare current balances of the merged organization against the combined balances of the separate organizations. (3) A move/merge operation can additionally be used to change a general ledger account number to facilitate a change in reporting requirements; for example, in moving a balance from an asset to a liability or from a revenue to an expense.
Many existing general ledger systems provide move/merge functionality. However, this move/merge functionality is not well-controlled. In current systems, move/merge operations are typically run in batch mode, with little if any error checking. Balances can be moved between balance sheet and income statement accounts, changing historical balances from those previously reported, and even causing an entity""s balance sheet to no longer balance. In current systems, it is even possible to move balances from one legal entity to another, causing the general ledger of each legal entity to be out of balance.
Additionally, once move/merge operations are processed, there is presently no easy way to xe2x80x9cundoxe2x80x9d the results of the move/merge operation. The only way to undo a move/merge operation is to restore general ledger balances back to a prior version of the general ledger balances, and to repost any entries subsequently posted after the move/merge operation. Hence, a user is typically unable xe2x80x9cundoxe2x80x9d the results of a move/merge operation because the undo operation must typically be performed with MIS resources.
Finally, in current systems, when balances in the general ledger are moved, the balances no longer reconcile back to the subledger that created the transactions. For example, assume the general ledger has one accounts payable account, which is only posted by the accounts payable system. In this case, the general ledger can be reconciled back to the accounts payable system. However, if the accounts payable balance is moved to another account, reconciliation is no longer possible.
In some systems, the user has the option of changing the underlying transactions to identify the target account instead of the source account. If the transactions are changed, the general ledger balance is supported by the posted transactions. However, there is no longer a link between the general ledger transactions and the transactions sent to the general ledger by the subledger. Consequently, if the transactions are not changed to reflect the target account, the balances in the general ledger can no longer be reconciled back to the underlying transactions.
Hence, what is needed is a system that supports a move/merge operation can be easily reversed without undesirable side effects.
One embodiment of the present invention provides a system for moving balances from at least one source account into a target account and subsequently reversing the movement. The system operates by receiving a request for a move/merge operation to move the balances from source accounts to the target account. In response to the request, the system creates a list of changes to the source accounts and the target account that are involved in moving the balances. The system stores this list of changes into a memory for later retrieval during a move/merge reversal operation. Next, the system performs the move/merge operation by applying the list of changes to the source accounts and the target account. When the system subsequently receives a request to reverse the move/merge operation, the system reverses the move/merge operation by retrieving the list of changes from the memory and applying the inverse of changes in the list to the source accounts and the target account. In a variation the on above-embodiment, the system validates the move/merge operation according to a set of business rules before performing the move/merge operation. For example, the set of business rules may ensure that the source and target accounts belong to the same financial statement category or the same business entity. In a further variation on the above embodiment, the system additionally creates move/merge audit journal entries to facilitate future auditing of the changes made during the move/merge operation.

Reversible move/merge operation for a general ledger


A synchronous semiconductor memory device includes a clock input circuit receiving an externally applied clock signal to produce an internal clock signal, a signal input circuit taking in an externally applied signal to produce an internal signal, a first delay circuit delaying an externally applied snooze mode signal by a first delay time for supplying to a clock input circuit, and a second delay circuit delaying the externally applied snooze mode signal by a second delay time for supplying to the signal input circuit. The clock input circuit and the signal input circuit are disabled when the internal snooze mode signal is active. The semiconductor memory device takes in the external signal and produces an internal signal in synchronization with the internal clock signal. Upon switching over to the snooze mode, the operation is performed in accordance with the external signal in the cycle in which the snooze mode is designated, and the internal operation is inhibited in the subsequent cycles. Upon release from the snooze mode, the internal clock signal is produced in the cycle subsequent to the cycle in which the release from the snooze mode is designated, and the signal input circuit is enable in and after the clock cycles subsequent to the cycle in which the internal clock signal is produced.

1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device which operates in synchronization with an externally applied clock signal having a predetermined cycle, and in particular to a structure of a signal input portion of the synchronous semiconductor memory device operable in a low power consumption mode.
2. Description of the Background Art
A microprocessor internally has a cache memory of a small storage capacity. In order to improve a system performance by reducing a wait time of the microprocessor at the time of cache miss, such a structure may be employed that the microprocessor is externally provided with a memory having a relatively large storage capacity, which is used as a secondary cache. The memory used as the secondary cache operates in synchronization with an external clock signal such as a system clock. Since it is not necessary to take a margin with respect to skew of a signal into consideration, and a deciding timing of input/output data is determined by the clock signal, fast input and output of data are allowed, and cache miss penalty can be suppressed.
FIG. 1 schematically shows a whole structure of a conventional synchronous semiconductor memory device operating in synchronization with a clock signal. The synchronous semiconductor memory device shown in FIG. 1 includes an SRAM (Static Random Access Memory) array 1 having a storage capacity of 32k.32-bits. One word consists of 32 bits. SRAM cells included in array 1 have the same structure as memory cells included in a conventional SRAM, and are formed of flip-flops.
The synchronous semiconductor memory device further includes input circuits 2a-2r which receive externally applied signals and produce internal signals. Input circuit 2a receives an externally applied address signal. Input circuit 2b receives a burst mode control signal MODE which determines a mode of changing the addresses in a burst mode as will be described later. In the burst mode, when one address is designated, data of memory cells at four addresses are continuously read or written.
Input circuit 2c receives a snooze mode signal /ZZ. In the snooze mode, the semiconductor memory device stops its operation, so that the power consumption of the semiconductor memory device is minimized.
Input circuit 2d receives a burst mode advance signal /ADV. When burst mode advance signal /ADV is active, address signals are automatically generated in the semiconductor memory device.
Input circuit 2e receives an externally applied clock signal CLK. Internal clock signal CLK produced by input circuit 2e determines the timing of taking in the external signals and the timing of inputting and outputting data. At the time of rising of internal clock signal CLK, the externally applied address signal is taken in, and valid input/output data is written/read.
Input circuits 2f and 2g receive address status signals /ADSC and /ADSP, respectively. Address status signal /ADSC is supplied from a controller which controls transference of data between the semiconductor memory device used as the secondary cache and a main memory used as the main storage. Signal /ADSP is supplied from a processor using the above semiconductor memory device as the secondary cache. Input circuits 2h-2k receive byte write enable signals /BW1-/BW4. Byte write enable signals /BW1-/BW4 designate enabling of data writing for each byte of one word of 32 bits (4 bytes).
Input circuit 21 receives a main byte write enable signal /MBW which allows writing of data in a unit of byte. When main byte write enable signal /MBW is active, writing of data of a word can be performed in a unit of byte.
Input circuit 2m receives a global write enable signal /GW which enables writing of data for all bytes of one word.
Input circuits 2n-2p receive chip select signals /S1, S2 and /S2, respectively. Chip select signal /S1 is supplied from the processor, and chip select signals S2 and /S2 are supplied from the controller.
Input circuit 2q receives an output enable signal /OE designating a data reading operation. Input circuit 2r receives a flow through mode signal /FT designating a data outputting mode. Flow through signal /FT determines whether the output data is to be output via a register or via the register which is set to the through state.
Internal snooze mode signal /ZZ (in the following description, the internal and external signals are denoted by the same reference characters) sent from input circuit 2c is supplied to all the other input circuits 2a, 2b and 2d-2r. When internal snooze mode signal /ZZ is at the low level of active state, all the internal signals sent via input circuits 2a, 2b and 2d-2r are inactive.
The synchronous semiconductor memory device further includes an internal control signal generating circuit 3 which produces internal control signals in response to the internal signals sent from input circuits 2d-2p and internal clock signal CLK sent from input circuit 2e. The output signals of internal control signal generating circuit 3 are decided in response to rising of internal clock signal CLK. Internal control signal generating circuit 3 includes a gate circuit 3a receiving burst mode advance signal /ADV from input circuit 2d and internal clock signal CLK sent from input circuit 2e. Gate circuit 3a outputs a signal at the high level when internal burst mode advance signal /ADV is at the low level and the internal clock signal CLK is at the high level.
Internal control signal generating circuit 3 further includes an OR circuit 3b which receives internal byte enable signal /BW1 from input circuit 2h and internal main byte enable signal /MBW from input circuit 21, an OR circuit 3c which receives internal byte enable signal /BW2 from input circuit 2iand internal main byte enable signal /MBW, an OR circuit 3d which receives internal byte enable signal /BW3 from input circuit 2j and internal main byte enable signal /MBW, an OR circuit 3e which receives internal byte enable signal /BW4 from input circuit 2k and internal main byte enable signal /MBW, an AND circuit 3f which receives an output signal of OR circuit 3b and internal global write enable signal /GW from input circuit 2m, an AND circuit 3g which receives an output signal of OR circuit 3c and internal global write enable signal /GW, an AND circuit 3h which receives an output signal of OR circuit 3d and internal global write enable signal /GW, an AND circuit 3i which receives an output signal of OR circuit 3e and internal global write enable signal /GW, an NOR circuit 3j which receives internal address status signal /ADSP from input circuit 2g and internal chip select signal /S1 from input circuit 2n, a gate circuit 3k which receives internal address status signal /ADSC from internal circuit 2f and an output signal of NOR circuit 3j, and an AND circuit 31 which receives an output signal of gate circuit 3k and the internal clock signal from input circuit 2e. Gate circuit 3a supplies the burst advance instructing signal to a burst counter 7 which will be described later. An output signal ADSN from AND circuit 3i defines a latch (strobe) timing for the address in this semiconductor memory device, and instructs burst counter 7 to take in least significant two bits A0 and A1 of the latched address.
Internal control signal generating circuit 3 further includes an OR circuit 3m receiving output signals of gate circuit 3j and AND circuit 3f, an OR circuit 3n receiving output signals of gate circuit 3j and AND circuit 3g, an OR circuit 3o receiving output signals of gate circuit 3j and AND circuit 3h, an OR circuit 3p receiving output signals of gate circuit 3j and AND circuit 3i, and a gate circuit 3q receiving internal chip select signals /S1, S2 and /S2 from input circuits 2n, 2o and 2p, respectively. Gate circuit 3q outputs a chip select signal which is active when both internal chip select signals /S1 and /S2 are at the low level and internal chip select signal S2 is at the high level.
OR circuits 3m-3p output the signals which instruct writing of data for corresponding bytes of a 4-byte word. Writing of data of the respective bytes is instructed when internal clock signal CLK is at the high level and respective output signals of OR circuits 3m-3p are at the low level.
The semiconductor memory device further includes an address register 4 which takes in and latches the address signal from input circuit 2a when address strobe (status) signal ADSN from internal control signal generating circuit 3 is active, write registers 5a-5d which take in and latch inverted signals of the output signals of OR circuits 3m-3p included in internal control signal generating circuit 3 in response to rising of internal clock signal CLK, and a chip select register 6 which takes in and latches an internal chip select signal CS in response to activation of address strobe (status) signal ADSN. Write registers 5a-5d output the signals which instruct writing of respective bytes of the 4-byte word. Chip select register 6 outputs the signal CS which enables write/read of data from/to memory cell array 1 of the semiconductor memory device.
Burst counter 7 takes in and outputs address signals A0 and A1 at least significant two bits from address register 4 when address status (strobe) signal ADSN from internal control signal generating circuit 3 is active. Upon each rising of the output signal of gate circuit 3a included in internal control signal generating circuit 3, burst counter 7 changes the taken address signals and outputs the burst address signals A1' and A0'. The manner in which burst counter 7 changes address signals A0 and A1 at the least significant two bits is determined by internal mode designating signal MODE from input circuit 2b. Address signals A0 and A1 may be changed in a linear mode in which the value successively changes by one, or in an interleaved mode in which the value changes in a predetermined order, e.g., of 0-2-1-3. The address signals from address register 4 and address signals A1' and A0 from burst counter 7 are supplied in parallel to row and column decoders which are provided to memory cell array 1.
The semiconductor memory device further includes a write/read control circuit 9 which supplies signals controlling write/read of data in accordance with the output signals of write registers 5a-5d, the output signal of chip select register 6 and internal output enable signal /OE from input circuit 2q, an input/output buffer 10 coupled to data input/output terminals, an input register 11 which takes in and latches write data from input/output buffer 10 in accordance with internal clock signal CLK and the output signal of internal write/read circuit 9, write drivers 12a-12d which write internal write data into selected memory cells in the memory cell array in accordance with the write instructing signal from internal write/read control circuit 9, and an output register 13 which transmits data of the selected memory cells in memory cell array 1 to input/output buffer 10 in accordance with the read instructing signal from internal write/read control circuit 9. Output register 13 operates in accordance with internal flow through signal /FT which is supplied from input circuit 2r, and determines enable/disable of register circuits of output register 13. When internal flow through signal /FT is active, output register 13 holds data for one clock cycle before transmitting the data to input/output buffer 10. When flow through signal /FT is in the inactive state of high level, output register 13 is set to the through state, and immediately transmits the data of a selected memory cell transmitted from memory cell array 1 as received. Internal snooze mode signal /ZZ is also supplied from input circuit 2c to input/output buffer 10.
Internal write/read control circuit 9 includes an AND circuit 9a which receives the output signal of write register 5a and output signal CS of chip select register 5, an AND circuit 9b which receives the output signal of write register 5b and chip select signal CS from chip select register 6, an AND circuit 9c which receives the output signal of write register 5c and chip select signal CS from chip select register 6, an AND circuit 9d which receives the output signal of write register 5d and chip select signal CS from chip select register 6, an OR circuit 9e which receives the output signals of write registers 5a-5d, a gate circuit 9f which receives the chip select signal from chip select register 6 and internal output enable signal /OE from input circuit 2q, and a gate circuit 9g which receives the output signals of OR circuit 9e and gate circuit 9f. The output signals of AND circuits 9a-9d are supplied to write drivers 12a-12d as internal write instructing signals, respectively.
Gate circuit 9f outputs a signal at the high level when chip select signal CS from chip select register 6 is at the high level of the active state and internal output enable signal /OE from input circuit 2q is at the low level. Gate circuit 9g outputs a signal at the high level when the output signal of OR circuit 9e is at the low level and the output signal of gate circuit 9f is at the high level. Therefore, gate circuit 9f outputs a signal at the high level when the semiconductor memory device is set to the selected state and the data output (read) is designated. Gate circuit 9g outputs a signal at the high level when all the data write instructing signals are inactive and the data read or output is designated.
Output register 13 transmits the selected memory cell data from memory cell array 1 to input/output buffer 10 in synchronization with internal clock signal CLK, when the output signal of gate circuit 9g is at the high level. Input register 11 includes register circuits, which are provided corresponding to respective AND circuits 9a-9d, and are activated when AND circuits 9a-9d supply the signals at the high level, respectively. Further, input register 11 takes in the write data from input/output buffer 10 in response to rising of the internal clock signal, and transmits the write data to write drivers 12a-12d corresponding to the activated write instructing signals. Now, operation will be described below with reference to timing charts of FIGS. 2 and 3.
Referring first to FIG. 2, data read operation in the burst mode will be described. At clock cycle 0, address status (strobe) signal /ADSP is set to the low level, and chip select signal /S1 is set to the low level. Also, initial address AD0 is supplied from the processor at cycle 0 (T1 cycle). At clock cycle 1, address status signal ADSN from internal signal generating circuit 3 is set to the high level in response to rising of clock signal CLK, and address register 4 takes in and latches the address signal (initial address AD0) from input circuit 2a. In response to rising of internal address status signal ADSN, burst counter 7 takes in 2-bit address signals A0 and A1 from address register 4 as the initial burst address signals and outputs the same. When data is to be output, all signals /BW1-/BW4, /MBW and /GW for controlling the writing are at the high level, and the write enable signals at the low level are latched into write registers 5a-5d in response to rising of clock signal CLK. Meanwhile, the output signal of gate circuit 3q is set to the high level (signals S2 and /S2 are set to the high and low levels, respectively), the internal chip select signal is set to the high level, and chip select register 6 stores this chip select signal CS at the high level in response to rising of internal address status signal ADSN. In the semiconductor memory device, memory cells in memory cell array 1 are selected in accordance with the address signals sent from address register 4, and the burst counter 7 and data of the selected memory cells are transmitted to output register 13. When flow through signal /FT is at the low level indicating the flow through mode, output register 13 does not hold the data even if internal clock signal CLK is applied thereto, and transmits the data of the memory cells selected in memory cell array 1 to input/output buffer 10 in accordance with the high level signal from gate circuit 9g in internal write/read control circuit 9. Input /output buffer 10 transmits the data supplied from output register 13 to the data input/output terminals in accordance with the read instructing signal (i.e., output signal of gate circuit 9g) from internal write/read control circuit 9.
When flow through signal /FT is at the high level, output register 13 performs the latch operation in accordance with internal clock signal CLK. Specifically, it latches the data of the selected memory cells transmitted from memory cell array 1, and will supply the latched memory cell data to input/output buffer 10 in the next clock cycle 2. Thus, in the flow through mode, data Q0 of the memory cell designated by initial address AD0 is output at the clock cycle (clock cycle 1) immediately subsequent to the cycle (clock cycle 0) in which initial address AD0 is applied. In contrast, when the flow through signal /FT is at the high level indicating the pipeline mode, data Q0 of the memory cell designated by initial address AD0 is output after elapsing of wait cycle T2W of one clock cycle.
In the subsequent clock cycle 1, address status signal /ADSP is maintained at the high level, and burst advance signal /ADV is set to the low level. In this case, the output signal of gate circuit 3a included in internal control signal generating circuit 3 attains the high level in response to rising of clock signal CLK, and the address counter output from burst counter 7 changes. Thereby, the address signal changes in accordance with the sequence designated by the mode signal MODE, and data Q1 of the memory cell at the next address is output. Every time clock signal CLK rises, burst advance signal /ADV is set to the low level and address status signal /ADSP is set to the high level, whereby the addresses are successively designated under the control of burst counter 7, and data Q1-Q3 of the memory cells corresponding to these addresses are read at the respective clock cycles (i.e., clock cycles T2).
In the data write operation, data can be likewise written in the bust mode. In this case, both signals /ADSP and /S1 are set to the low level to set the initial address. At this time, the output signal of gate circuit 3a is set to the high level, the output signals of OR circuits 3m-3p attain the high level, and write registers 5a-5d store inactive write enable signal. Therefore, data writing is not performed in this cycle. In the next clock cycle, address status signal /ADSP is set to the high level, and signals /BW1-BW4, /MBW and /GW for controlling the data writing are set to the intended states, so that, in the following clock cycles, data can be successively written into four addresses starting from the first designated initial address (write data is latched with a delay of one clock cycle, as will be described later).
In the data write operation necessary ones of, write control signals /BW1-/BW4, /MBW and /GW are set to the active state. At this time, signal /ADSP is at the high level, and the output signal of NOR circuit 3a is at the low level. If global write enable signal /GW is at the low level, all the output signals of OR circuits 3m-3p are at the low level, and write registers 5a-5d take in and latch the active write enable signals at the high level in response to rising of clock signal CLK. All the output signals of AND circuits 9a-9d attain the high level, all write drivers 12a-12d are activated, and data of 32 bits (i.e., data of one word) supplied from input register 11 is written into the selected memory cells in memory cell array 1. The output signal of gate circuit 9g is at the low level because the output signal of OR circuit 9e is at the high level, output register 13 is inactive, and input/output buffer 10 is set to the data writing state. At this time, burst advance signal /ADV is set to the low level at the rising of clock signal CLK, as is done in the read operation, whereby addresses are successively designated under the control of burst mode counter 7, and data can be written into the memory cells corresponding to the internally designated addresses.
FIG. 3 is a timing chart showing the data write operation. As shown in FIG. 3, address AD0 taken in at write cycle 1 is stored in address register 4 in this cycle 1, and write data D (AD0) taken in at cycle 2 is stored in input register 11. When data write is designated in cycle 2, the data stored in input register 11 is written into the memory cells designated by the address stored in address register 4. Data D (AD1) supplied in clock cycle 3 is written into the memory cells at address AD1 which was taken in at clock cycle 2. When data read is designated in clock cycle 3, data Q (AD2) of the memory cells corresponding to address AD2 are read in the subsequent clock cycle 4 (in the case of pipeline output mode).
When flow through signal /FT is set to the high level and the data read is performed in the pipeline mode, access to the initial address requires a wait cycle T2W of one clock cycle. However, the access time with respect to clock signal CLK is determined by only the delay time of the output portion included in input/output buffer 10. Therefore, fast clock access (i.e., access relative to the clock) can be achieved. In the burst read cycle (T2), the wait cycle is not required. Therefore, data can be read fast. As compared with the case where flow through signal /FT is at the low level of active .state and data read is performed in the flow through mode, data reading in this burst mode (pipeline mode) requires the wait cycle Taw, so that data transmission efficiency thereof is relatively low. However, such an advantage can be achieved that even a semiconductor memory device of a relatively low operation speed can achieve the fast clock access (for fast operation, an expensive BiCMOS process must be employed).
FIG. 4 is specifically shows a structure of the input circuit shown in FIG. 1. In FIG. 4, address status signals /ADSC and /ADSP are represented by one address status (strobe) signal /ADS. Likewise, write enable signals /BW1-/BW4, /MBM and /GW are represented by one write enable signal /WEN. The input circuits for signals MODE and /FT are not shown in FIG. 4. These signals are directly applied to burst counter and input/output register via the input circuit as shown in FIG. 1. Input circuits 2b and 2r for these signals MODE and /FT are supplied with internal snooze mode signal ZZ from input circuit 2c receiving external snooze mode signal /ZZ.
Input circuit 2c is formed of an inverter IV1 receiving snooze mode signal /ZZ externally supplied via an input terminal 30a. Input circuit 2e receives external clock signal CLK applied via an input terminal 30b and internal snooze mode signal ZZ from input circuit 2c, and produces the internal clock signal INT.CLK. An input circuit 20a receives address status signal /ADS via an input terminal 30c, and also receives internal snooze mode signal ZZ. An input circuit 20b receives write enable signal /WEN via an input terminal 30d, and also receives internal snooze mode signal ZZ. Input circuit 2a receives the address signal via an input terminal 30e, and also receives internal snooze mode signal ZZ. An input circuit 20c receives input data DQ(D) via an input terminal 30f, and also receives internal snooze mode signal ZZ. Input circuit 2g receives output enable signal /OE via an input terminal 30g, and also receives internal snooze mode signal ZZ.
Each of input circuits 2a, 2e, 2g and 20a-20c is formed of an NAND gate NR receiving internal snooze mode signal ZZ and the signal from the corresponding input terminal, and an inverter IV2 receiving the output signal of NAND gate NR.
The output signals of input circuits 2e, 20a, 20b, 20c and 2g are supplied to internal circuits 35a-35f, respectively. Internal circuits 35a-35f correspond to the input circuits included in the input/output buffer and the internal control signal generating circuit shown in FIG. 1. For example, internal circuit 35a corresponds to gate circuit 3a and write registers 5a-5d. Internal circuit 35b corresponds to NOR circuit 3j and gate circuits 3k and 31 in FIG. 1. Internal circuit 35c corresponds to, for example, OR circuits 3b-3e and AND circuits 3f-3i. Internal circuit 35d corresponds to address register 4. Internal circuit 35e corresponds to the input buffer included in input/output buffer 10 in FIG. 1. Internal circuit 35f corresponds to gate circuit 9f in internal write/read control circuit 9 shown in FIG. 1.
When the processing stops and it is determined that an external access to the semiconductor memory device is not necessary, the processor sets the external snooze mode signal /ZZ to the high level. When only holding of data in a DRAM (Dynamic Random Access Memory) which is a main storage is to be performed in a battery-powered personal computer for example, snooze mode signal /ZZ is set to the high level of active state. In this case, as shown in FIG. 5, external snooze mode signal (EXT.) /ZZ is supplied asynchronously to external clock signal EXT.CLK. Internal snooze mode signal (INT.)ZZ is set to the low level of active state after elapsing of a delay time of inverter IV1. When internal snooze mode signal (INT.)ZZ is set to the low level, output signals of input circuits 2e, 2a and 20c are fixed to the low level. Therefore, charging and discharging are not performed in input circuits 2e, 20a-20c, 2a and 2q, so that power consumption can be reduced. In this case, the internal signal at the low level of active state may be supplied to the internal circuits. Even in this case, each external control signal is latched by the register in response to rising of internal clock signal INT.CLK as shown in FIG. 1, so that internal operation of the semiconductor memory device is inhibited due to stop of generation of internal clock signal INT.CLK.
However, snooze mode signal /ZZ is supplied asynchronously to external clock signal EXT.CLK (CLK). Therefore, when external snooze mode signal (EXT.)ZZ is set to the high level at substantially same timing as rising timing of external clock signal (EXT.)CLK, for example, as shown in FIG. 6, the following problem arises.
Input circuit 2c is formed of inverter IV1, and has a delay time of, e.g., several nanoseconds. As shown in FIG. 6, therefore, when external snooze mode signal EXT./ZZ is set to the high level at the same timing as rising timing of external clock signal EXT.CLK, internal clock signal INT.ZZ attains the low level after elapsing of delay time Td of input circuit 2c. For example, in clock input circuit 2e, delay by Td therefore occurs in the timing of cutting off external clock signal EXT.CLK applied to input terminal 30b. Consequently, external clock signal EXT.CLK which is applied during delay time Td passes through input circuit 2e, and internal clock signal INT.CLK attains the high level for that period. Operation similar to the above is performed in the other input circuits. Therefore, when write enable signal /WEN is set to the low level in this state, the input register operates in accordance with internal clock signal INT.CLK, and internal chip select signal (INT.)CS attains the high level. Also, the address signal is latched by the register, and data is written into a memory cell in accordance with the erroneously latched address signal. This results in a problem that the memory cell data to be stored is destroyed.
In particular, if all the input circuits have the same common structure as shown in FIG. 4, the internal signals may be held at the active state during the snooze mode, which increases the possibility that malfunction, particularly, writing of erroneous data is performed due to internal clock signal INT.CLK generated in a spike-like form.
In the synchronous semiconductor memory device, the external signals are taken in at rising of internal clock signal INT.CLK, and its internal operation is determined depending on the states of taken signals. Therefore, if a similar problem occurs also at another input circuit, malfunction of a circuit may occur due to generation of an unexpected internal signal in this synchronous semiconductor memory device.
If external snooze mode signal EXT.ZZ is lowered at substantially the same timing as the rising timing of external clock signal EXT.CLK in order to terminate the snooze mode operation, this results in generation of internal clock signal INT.CLK, so that a similar problem arises.
In order to avoid the above problems, it is necessary to deactivate all the external control signals upon entering of the snooze mode. For example, upon entering of the snooze mode, it is necessary to deactivate signal /WEN and all chip select signals CS (S2, /S2, /S1) and set address status signal /ADS to the high level in order to prevent the setting of the data write state. Therefore, whenever the memory device enters or exits the snooze mode, an external processing unit must set the states of not only snooze mode signal EXT./ZZ but also other signals, resulting in a problem that a load to the external processing unit increases when entering the snooze mode.

Synchronous semiconductor memory device operable in a snooze mode


The present invention refers to a triple-band antenna array for cellular base stations operating at a first frequency band and at a second frequency band within a first frequency range, and also at a third frequency band within a second frequency range. Said triple-band antenna array comprises a first set of radiating elements operating at the first frequency band, a second set of radiating elements operating at the second frequency band, a third set of radiating elements operating at both the third and the first frequency bands, and a fourth set of radiating elements operating at both the third and the second frequency bands. The radiating elements are arranged in such a way that at least some of the radiating elements of the first set are interlaced with at least some of the radiating elements of the third set, and at least some of the radiating elements of the second set are interlaced with at least some of the radiating elements of said fourth set. Further the invention relates to a slim triple-band base station for mobile/cellular services that includes in its radiating part two or more of said triple-band antenna arrays.

The Universal Mobile Telecommunications System (UMTS), also known as the third generation of wireless communications systems, is currently being added to the 1st and 2nd generation of wireless communications systems (such as for instance GSM850, GSM900, DCS, PCS1900, CDMA, or TDMA) and has stimulated the demand for multiband antenna arrays and, in particular, for triple-band base station antenna arrays. Such triple-band antenna arrays integrate the 1st, 2nd, and 3rd generation of wireless communications systems.
A typical cellular service requires a network of base stations, each of them comprising several base station antenna arrays, to provide coverage to the users of said cellular service. The antenna arrays are the radiating part of the base station. Usually, the radiating part of the base station is composed by nine or three independent antenna arrays that give service to, for example, a specific part of a city, a village, a road, or a motorway. Since the radiating part of the base station is composed by several antenna arrays, the dimensions of a conventional base station are large and the resulting base station has a significantly big visual impact.
One possibility to enable a base station to provide coverage for three different mobile communication systems is to use for example three single-band antenna arrays (for example one for GSM900, another for DCS and a third one for UMTS). Since typical base stations split their area of coverage into three different sectors, three single band antenna arrays are required for each of said sectors, which means that the triple-band three-sector base station might require up to a total of nine antenna arrays. As an alternative, and in order to reduce the antenna array count for the base station, two out of the three operation bands could be combined in a dual-band antenna array (such as for instance DCS and UMTS). In this case only two antenna arrays would be necessary in each sector, resulting in a total of six antenna arrays for a triple-band three-sector base station. The use of multiple single-band antenna arrays (or a combination of single-band and dual-band antenna arrays) in a triple-band base station will typically lead to bulky and mechanically complex structures, hardly disguisable with the surrounding environment. Furthermore, a large antenna array count will likely result in a costly solution.
As an alternative, some conventional triple-band antenna arrays that are used today for base stations make use of a side-by-side configuration, in which three single-band antenna arrays are arranged one next to another along the direction defined by the width of the single-band antenna arrays and packed in a single dielectric enclosure or radome.
Although, this approach reduces the number of antenna arrays in the base station to just three (i.e., one per sector), it still performs poorly in terms of minimizing the visual impact of the base station, as the dimensions of these antenna arrays, specially their width, are significantly larger than the dimensions of a single-band antenna array.
Nowadays, local, regional and/or national governments and public administrations are concerned about the visual impact of the base stations in their cities, mainly because of the large size of the antenna arrays. As governments and public administrations endeavor in minimizing the visual impact of the base station of cellular communications networks, it is becoming more and more difficult for network operators and mobile service providers to acquire new sites and/or obtain the license to set up new base stations in cities and villages around the world.
The visual impact due to the size and number of antenna arrays in a base station has been a rising issue for network operators and consumers, creating the demand for smaller-sized antenna arrays for base stations, with which to reduce substantially the visual impact of the base station but without compromising the level of performance and functionality of current solutions.
Adjustable electrical down-tilt techniques for antenna array systems are very well known in the related background art.

This patent is subject to a terminal disclaimer.

Slim triple band antenna array for cellular base stations


A soil moisture sensor to be implanted in soil. The sensor has a conductive metal housing, perforated to pass moisture to and through a filter liner which lines an internal cavity. A transfer matrix is confined in the liner and is abutted by a buffer tablet of compacted gypsum. An electrode matrix abuts the tablet and bridges a pair of spaced-apart electrodes. Water, or absence of water, in the electrode matrix provides a measure of moisture in the soil as a function of electrical conductivity between the electrodes.

The monitoring of moisture in soils by measuring conductivity between two electrodes is well known. An example is found in Larson U.S. Pat. No. 4,531,087 issued Jul. 23, 1985. The Larson device is typical of sensors which have two spaced-apart electrodes packed in a porous medium, protected by a filter medium which excludes particulates but passes moisture. The conductivity of the medium between the electrodes is measured to reflect the level of moisture in the porous medium.
The conductivity (or electrical resistance) of the region occupied by the porous medium is not a strictly linear function of the moisture content in the soil. Still, properly interpreted it can give the agronomist or gardener valuable information regarding the moisture at some depth in the soil, and can give him guidance concerning the need for irrigation or watering. Simplistically stated, when the porous region is completely dry, there will be no, or at the most minimal, conductivity. A very low or no meter reading will result if current flow is measured. If resistance to a given applied voltage is measured, the inverse of this reading will occur. When the sensor is fully wetted, the conductivity will be at a maximum, and there will be a higher meter reading reflecting this fact.
There is a serious problem. A sensor to be economically practical must be able to function in a wide variety of soils and be responsive to a wide variety of waters. No matter how wet the sensor would be with distilled water, for example, there would always be a low or no reading because conductivity of such water is very low.
It is an object of this invention to provide a sensor whose conductivity is less affected by the variations in concentration of the salts dissolved in soil waters before it reaches the sensitive part of the sensor, and which assures that the water will always have at least some conductivity. The sensor's output is therefore more reliably related to the moisture content of the soil than in previously known sensors such as the Larson sensor.
It is tempting to assume that a sensor of this type should have only two readings- one responsive to no moisture, and another responsive to the presence of sufficient moisture to form a circuit between the two electrodes. Fortunately the actual pattern Is somewhat more complicated. While a graph relating conductivity to moisture content is likelier to be steep in any event, it is not an abrupt curve. As the soil moisture decreases, the conductivity will begin to decrease. It is this decrease and the rate of decrease which the agronomist will watch for, because it will alert him to the fact that the soil is drying out as the consequence of suction exerted by the crop. Properly instrumented, this sensor will give the user adequate notice of the change of moisture content and thus of the demands of the crop. Also, when water is thereafter applied to the soil, a gradual increase in conductivity will signal the rise in the moisture content at the sensor. The rate of change gives information valuable in determining the amount of water to be applied, and at what rate, to satisfy the needs of the crop, as well as to avoid over saturation of the ground with attendant waste of water or excessive loss of water, which could lead to crop damage.
Thus, this sensor is intended as a measurement of the soil moisture at the sensor s level, and of its rate of change.
This invention enables a single sensor to be used for the above purposes in a wide variety of waters, while still providing readings which are consistent with a given meter calibration that can be established at the factory. This is accomplished by providing in the sensor itself a substantial source of electrolyte ions which will assure conductivity whenever moisture is present. It is provided in such a way as to remain effective over a long period of time.
There are other problems solved by this invention. These sensors are placed in soils Which are subjected to occasional variable physical loads, and to stray electrical currents. One can damage or destroy a sensor, and the other can cause faulty or stray readings. This invention provides a strong conductive metal case which resists the physical loads, and which provides a shield that excludes many atray currents. As a consequence, this invention provides a remarkably improved and long-lived sensor to detect soil moisture, and to detect the change and rate of change in moisture content at critical times.
It is another object of this invention to provide a sensor structure which includes only a minimum number of parts, and which can be manufactured to a high degree of consistency from one sensor to another.

Electrical sensor for sensing moisture in soils


A method for dressing a honing tool using a dressing tool which during the dressing operation rolls at an axial intersection angle with the honing tool. The teeth thereof which move into engagement with the teeth of the dressing tool each have an upper face which is to be dressed and tooth flanks which are also to be dressed.

Field of the Invention
The invention relates to a method for dressing a honing tool which is intended for the fine machining of the teeth of a toothed wheel. For the dressing processing operation, there is used a dressing wheel which, during the dressing operation with the honing tool which is intended to be dressed, continuously rolls at an axial intersection angle so that teeth which are formed on the dressing wheel move into engagement with teeth which are formed on the honing tool and which each have an upper face which is intended to be dressed and tooth flanks which are also intended to be dressed.
Description of Related Art
The honing of toothings or toothed wheels is a fine machining method involving cutting using a geometrically non-defined blade in order to process toothed wheels. In this instance, hardened toothed wheels are generally honed using a honing tool which is also referred to as a honing wheel, honing ring or honing stone. The honing tool comprises, for example, a synthetic resin or ceramic bond in which hard material grinding grains of white corundum, sintered corundum or boron nitride are embedded.
As a result of the continuously operating toothed wheel honing method, it is possible above all to correct short-wave toothing deviations. These may lead to noises which are very unpleasant for the human ear. As a result of their high-frequency nature, they may further have a negative effect on the service-life of the respective component.
During the honing processing operation which is carried out continuously, the toothed-wheel-like honing tool and the toothed wheel which is intended to be processed roll on each other in a synchronous rotation. The toothing of the honing tool and toothed wheel mesh in this instance at an axial intersection angle which is adjusted between the skewed rotation axes of the honing tool and toothed wheel.
As a result of the rolling rotation and the axial intersection angle, there is between the tooth flanks of the honing tool and the tooth flanks of the toothed wheel which is intended to be processed during rolling contact a sliding relative movement which brings about the chip removal on the toothed wheel. The sliding movement of the honing tool in contact with a tooth flank of the toothed wheel is composed of a radial movement which is produced by the rolling rotation and an axial movement which is produced by the axial intersection angle. The axial and radial components of the sliding movement result in the processing marks which are characteristic of toothed wheel honing and which can be seen as "herringbone patterns" on the tooth flanks of the toothed wheel which has been completely processed.
As a result of the toothed wheel honing operation, it is particularly possible to positively influence the noise behaviour and the load-bearing capacity of a toothing as a result of the correction of short-wave toothing deviations and the introduction of residual compressive stresses in the region of the toothed wheel edge zone.
The honing tool is dressed before the first use in the new state and after a specific period of use. The dressing operation serves to correct production-related or wear-related shape deviations of the honing tool from the optimum desired shaping in each case and thus to sharpen the respective tool with respect to the geometry thereof.
In particular with internally toothed honing tools, so-called honing rings, the dressing is generally carried out in two steps. In a first step, the outside or internal diameter of the honing ring is dressed using a generally cylindrical dressing roller. In a second step, the tooth flanks of the honing ring are then dressed using a toothed dressing wheel.
The result of this operating method is that the dressed upper surfaces and a respective dressed tooth flank of a tooth of the honing ring converge in the region of the tooth tip in a sharp-edged upper corner. The path described by this upper corner during the honing operation changes over the useful length of the honing tool. In the new state, as a result of the sharp-edged upper corner on the toothed wheel workpiece in the tooth base region, there is produced a sharp notch which reduces the tooth base load-bearing capacity or tooth base strength of the toothing of the toothed wheel. This effect decreases as the useful length of the honing tool decreases, that is to say, as the wear or repeated dressing operations increase. As a result of wear and repeated dressing, with honing tools which are constructed, for example, as a honing ring, the radius of the base rounding which is produced is increased.
For the honing processing of toothed wheels for which fine machining of the tooth base region is also required, there is therefore artificially produced a state of the honing tool which would be produced during use only after a specific period of use or after a specific number of dressing operations. The effective period of time for which the honing tool can be used is thereby significantly shortened compared with the useful period for which the honing tool would actually be able to be used starting from the new state. The artificial shortening of the service-life naturally leads to increased tool costs.
Modern gear mechanism constructions increasingly demand, that during the honing processing operation of toothed wheels, the tooth base region is also honed in order to also achieve optimum load-bearing capacities in the tooth base region by means of optimisation of the surface state. In this instance, it is desirable to prevent steps in the surface nature or the geometry in the region of the transition between the respective tooth flank and the adjacent tooth base region.

Method for dressing a honing tool and method for honing a toothed wheel