The cementing collar described herein is designed primarily for cementing operations in oil or gas wells. The basic assembly includes a collar, an outer sleeve slidable in the collar, and an inner sleeve slidable in the outer sleeve. The collar and outer sleeve each have cementing ports therein. When the assembly is being run into the well casing, the collar and both sleeves are secured by shear pins in a position such that the cementing ports are closed. To open the cementing ports a trip bomb is dropped into the casing to engage a seat inside the outer sleeve. This causes the pins to shear and permits the outer sleeve to move down to a position in which the sleeve ports line up with the collar port. After cementing has been completed, a plug is flowed down the casing to engage the inner sleeve. Fluid pressure is applied behind the plug to shear the pins a second time. This moves the outer sleeve further down to a position in which the cementing ports are again closed.

When boreholes are drilled to recover oil or gas the well casing dropped into the hole is usually cemented at the lower end of the hole, and at other locations above the lower end. In cementing the lower end of the casing, usually called primary cementing, a cement slurry is passed down through the casing and up into the annular space between the casing and the borehole. Cementing above the lower end of the borehole is usually done later than the primary cementing job, that is, during the productive life of the well. These later operations are usually referred to as secondary cementing, or stage cementing.
In a stage cementing operation, as the name suggests, the borehole annulus is cemented in separate stages, beginning above the primary cementing job and working up the borehole. Special tools have been developed for use in stage cementing to make the operation more convenient and to save on the amount of cement required. Most of these tools have an upper sleeve and a lower sleeve, which are slidable inside a collar having cement ports therein. In the "running in" position both sleeves are fastened to the collar by shear pins. In this position the cementing ports are closed off by the sleeves. To commence the cementing operation, a plug is flowed down the casing to seat on the lower sleeve. Fluid pressure is then applied behind the plug to shear the pins holding the lower sleeve and thus move the lower sleeve down to a point where the cementing ports are uncovered. Following completion of cementing, a second plug is seated on the upper sleeve and fluid pressure applied behind the plug shears the pins holding the upper sleeve. This allows the upper sleeve to move down and close off the cementing ports.
Stage cementing tools of the type described above frequently have operating problems. For example, when the second plug (the closing plug) seats on the upper sleeve several inches of cement slurry are trapped between the second plug and the first plug (the opening plug), which remains seated in the lower sleeve. When the upper sleeve moves downwardly, therefore, it must work against the trapped cement. Because of this obstacle, the amount of fluid pressure required to move the upper sleeve to its closed position can sometimes be very near to the burst pressure rating for the well casing.

Cementing collar and method of operation


A circuit protection arrangement comprises a series switching circuit that is intended to be connected in a line of the circuit and will switch to an open state when subjected to an overcurrent, and a shunt switching circuit that is open under normal operating conditions but will shunt the overcurrent across the load of the circuit or to ground when triggered by the series switching circuit. Preferably the series switching circuit comprises a switching transistor (4) that is controlled by a control transistor (6), and the shunt switching circuit comprises a shunt switching transistor (9) that is controlled by a shunt control transistor (11) which is itself controlled by the series switching circuit. The shunt switching circuit may be connected to ground or it may be connected to a back-up load or voltage foldback device such as a triac.

1. Field of the Invention
This invention relates to arrangements and devices for protecting electrical circuits from overcurrents, for example from overcurrents caused by equipment faults or transient overcurrents caused by lightning, electrostatic discharge, equipment induced transients or other threats.
2. Introduction to the Invention
Many circuit protection devices have been proposed for the protection of electronic circuits from overcurrents and overvoltages. For example voltage controlled triacs are employed for protecting certain systems such as telephone circuits from overvoltages. The devices are connected between the lines and ground and will fire in order to shunt any voltage transient when the transient voltage on the line reaches a predetermined value (typically 200 V) and will remain in their on state until the current passing through them is reduced to below a certain value, the holding current. Such devices have the disadvantage that once they have fired they can be latched in their on state by the dc power source of the telephone line which is quite capable of delivering short circuit currents in the order of 200 mA. While conventional triacs normally have a holding current of up to 50 mA, triacs having higher holding currents, for example 300 mA, need to be employed in order to overcome the latching problem. However, these traics have the disadvantage that, when subject to certain transients, they may switch incompletely and remain at a high voltage of 200 V or thereabouts while passing a current of 200 mA with the result that the device and possibly other equipment may be violently damaged. One circuit that has been proposed for use with telephone systems is described in French patent application No. 2,619,262. This circuit comprises a combined overvoltage and overcurrent protection device in which a comparison circuit compares the voltage on one of the lines with a reference voltage and, if it is greater, the transient is shunted across the load and a series electronic switch is opened. This device, however, suffers from the disadvantage that it will not be triggered by a system failure leading, for example, to a short circuit and damage to the series switch may occur due to the currents experienced. In addition, a significant amount of the overcurrent transient may pass through the device before the series switch is opened. The device has the further disadvantage that the voltage protection circuit merely limits the transient voltage to a maximum value. Since significant transient current flows through this part of the circuit, unacceptable heating can occur.


A floatation unit comprised of a generally rectangular air bag, and having an inflation hose and valve, is disclosed. Four grab loops project from the four corners of the air bag, two of the corners also including hooks for engaging a water craft's gunwale, the other two of the corners including cinch straps. A pair of the floatation units is used to stabilize a water craft by engaging the hooks of each to opposing gunwales of the craft, and tensioning their cinch straps beneath the craft. A pair of floatation units is also used to displace space with a water craft, thereby reducing its likelihood of sinking if swamped. For displacement, each of the pair of units is hooked to a thwart within the water craft, and their cinch straps are tensioned between them to suspend the units securely between the thwarts. A pair of the units may also support a seat panel between them, the seat panel having corner loops through which the cinch straps pass. A person can be supported substantially upright in the water on the seat panel. Upright support is also possible if a person passes each leg through a gap between an air bag and its cinch straps, the straps of each unit being attached to one another of the same unit. And, a single floatation unit may support a person in a generally prone position in the water if the person's torso is through a gap between the air bag and the attached cinch straps, the upper chest and arms being atop the air bag while the hips and legs hang free for kicking.

1. Field Of The Invention
The present invention relates generally to floatation devices, and more specifically to multi-purpose floatation apparatus for stabilizing water craft, for displacing space in water craft and for supporting persons, and to methods of using this apparatus.
2. Description Of The Related Art
Throughout the history of humankind's construction and use of water craft, various stabilizing devices such as outriggers and pontoons have been employed to minimize the likelihood of tipping over. Such stabilizers are primarily fitted to narrow-beamed boats, such as canoes and the like, to offset their inherent tendency to tip. However, complex hardware and apparatus suited only to permanent installation often make previously-available stabilizers impractical to use.
It has also been found advantageous to employ displacement apparatus in water craft to keep it from sinking, if swamped. Various high volume, low density solid materials and air-filled bladders have been used for this purpose. However, each of those currently available tends to be fashioned to fit a water craft of a particular shape and dimensions.
It would be particularly expedient if a single, highly adaptable floatation apparatus were available to serve as a water craft stabilizer or, alternatively, to displace space within the interior of a water craft. Further advantages would be derived from the apparatus if it could be adapted to supporting a person in water for recreational or emergency use.


A parallel transmission method includes a submethod of transmitting portion for transmitting parallel data of a plurality of channels as encoded data of a plurality of lines and a submethod of receiving portion for decoding parallel data of a plurality of lines from encoded data of the plurality of channels. The submethod of transmitting portion includes the steps of multiplying the frequency of a clock by a predetermined number to generate a multiplexing clock, separating input signals composed of parallel data of a plurality of channels and additional data for code transformation into a plurality of groups, transforming parallel data into serial data with the multiplexing clock, mutually substituting the resultant data of the plurality of channels from time to time, and generating encoded data containing the additional data of the plurality of lines. The submethod of receiving portion includes the steps of synchronizing encoded data of the plurality of lines with the additional data, substituting the resultant data of the plurality of lines in the inverse order of the transmitting portion, removing the additional data from the resultant data, successively arranging the resultant data of each group, dividing the frequency of a transmission clock by a predetermined number to generate an original clock, and transforming serial data of each group into parallel data.

1. Field of the Invention
The present invention relates to a parallel code transmission method and an apparatus thereof. In particular, the present invention relates to a transmission line code processing method for transmitting signals between boards in a computer or a transmission processing unit or between two distant units.
2. Description of the Related Art
Conventionally, as computer techniques, signals are exchanged between internal boards of a computer and between external units in parallel. These signals are transmitted with pair cables and/or coaxial cables. However, the pair cables and coaxial cables have limitations with respect to bit rate and distance. In addition, it is known that skewing involved in a parallel data transmission (deviation of relative delay between channels) becomes a characteristic problem as the distance of the cables and the speed of data transmission increase. Thus, in consideration of the bandwidth and the transmission loss of the pair cables and coaxial cables, the maximum transmission bit rate and the maximum transmission distance thereof are at most of the orders of several 10 Mb/sec and 10 m, respectively. In other words, the use of these cables has been limited to applications of short distance and low bit rates. In addition, since the size, thickness, and weight of these cables are not suitable for applications of long distance, there are many problems to solve.
On the other hand, in recent years, as the processing speeds of the processors increase, those of computers proportionally increase. Thus, the processing speeds of signals exchanged between internal boards of a computer and between external units increase. In addition, from a flexibility point of view of the unit layout, the transmission distance of signals is becoming longer.
Moreover, with respect to transmission processing units which transmit these signals, the current mainstream of sound transmission services of the conventional public telephone networks is being replaced with broad-band integrated services digital networks (B-ISDN) which will provide full motion video transmission services requiring 1000 times wider transmission bandwidth. These B-ISDN technologies have been intensively studied worldwide. In these developing technologies, demands of high processing speeds of signal interfaces between internal boards and between external units and long distant transmission are becoming strong year after the year.
From the above-mentioned situation, in the field of computers and transmission processing units, there are demands for accomplishing interfaces which can transmit a large number of high speed signals for a long distance without deterioration of these signals. For these demands, optical parallel transmission techniques using optical fiber cables have been studied.
As so-called optical parallel transmission codes for transmitting parallel codes in optical level, for example, 4B6B code is presented in "Fundamental Study of Optical Parallel Transmission System", Document No. 2408, 70-th Anniversary National Conference of Institute of Electronics, Information and Communication Engineers (1987). This document describes a transmission line coding technique for encoding input data and transmitting the encoded data in parallel in optical level without a multiplexing process. In other words, this document does not mention techniques for simplifying the overall construction of the optical parallel link and for reducing the power consumption thereof. The simplification of the construction of the transmission line coding processing portion and the reduction of power consumption thereof are becoming important matters to solve in the conventional transmission systems as well as the optical parallel transmission system.
Generally, in the coding format "m+f" of the parallel-serial transformation (where m is the number of inputs, and f is "1" additional code), when codes are transformed with one parallel-serial transforming circuit, as the value m increases, the number of serial data increases. Thus, the transmission line speed increases. As a result, the circuit cannot be accomplished easily. On the other hand, when the value m is small, since the transmission line speed rise ratio given by (m+1) / m increases, the transmission efficiency decreases. Moreover, when codes are transformed with a plurality of parallel-serial transforming circuits, the value m which is input to each parallel-serial transforming circuit decreases. Thus, the transmission line speed rise ratio given by (m+1) / m increases.

Parallel code transmission method and apparatus of the same


The disclosure relates to methods, devices, and computer programs in mobile communications. More specifically, the proposed technique relates to delayed device activation. In particular the disclosure relates to enabling a communication module in a wireless node in response to receiving a sensor output. The disclosure proposes a method, performed in a first wireless node comprising a disabled communication module, for initiating communication with a second wireless node. The method comprises providing access to a sensor, receiving, from the sensor, a sensor output indicating that wireless communication is required, enabling, in response to receiving the sensor output, the communication module in the wireless node, and initiating an initial communication with the second wireless node using the enabled communication module.

3GPP Long Term Evolution, LTE, is the fourth-generation mobile communication technologies standard developed within the 3rd Generation Partnership Project, 3GPP, to improve the Universal Mobile Telecommunication System, UMTS, standard to cope with future requirements in terms of improved services such as higher data rates, improved efficiency, and lowered costs. In a typical cellular radio system, wireless devices or terminals also known as mobile stations and/or user equipment units, UEs, communicate via a radio access network, RAN, to one or more core networks. The Universal Terrestrial Radio Access Network, UTRAN, is the radio access network of a UMTS and Evolved UTRAN, E-UTRAN, is the radio access network of an LTE system. In an UTRAN and an E-UTRAN, a User Equipment, UE, is wirelessly connected to a Radio Base Station, RBS, commonly referred to as a NodeB, NB, in UMTS, and as an evolved NodeB, eNB or eNodeB, in LTE. An RBS is a general term for a radio network node capable of transmitting radio signals to a UE and receiving signals transmitted by a UE.
The next generation mobile communication technologies standard developed within the 3GPP is the fifth-generation, 5G, wireless networks. 5G is said to be the enabler for machine to machine, M2M, services and Internet of Things, IoT, with more capacity, lower latency and supporting low power consumption for connected devices.
In a couple of years, 50 billion devices are expected to be connected through wireless networks, hence enabling the 4th industrial revolution or the so called Internet of Things, IoT, era. Only the imagination limits the possibilities and applications within this field, however, some features are likely to be common for a great many of them.
The IoT has been defined in Recommendation ITU-T Y.2060 (June 2012) as a global infrastructure for the information society, enabling advanced services by interconnecting (physical and virtual) things based on existing and evolving interoperable information and communication technologies. Hence, in IoT, devices communicate with other devices. This is also referred to as Machine Type Communication, MTC, or Machine to Machine, M2M, communication. The communication may be achieved using peer-to-peer communication, i.e. Device-to-device, D2D, communication or over radio communication networks. In this type of communication people are less or never involved, instead it is the machines themselves that communicates with each other.
One 3GPP standard that is being formed to address the requirements of IoT is the so called Narrowband IoT, NB-IoT, standard which is a new narrowband radio technology standard within in the scope of the 3GPP LTE evolution. The NB-IoT technology will provide improved indoor coverage, support of massive number of low throughput devices, low delay sensitivity, ultra-low device cost, low device power consumption and optimized network architecture.
Power consumption is one parameter that is vital for the enablement and success of IoT. Ten years' longevity is a timeframe adopted by industry and which requires great resource frugality both in the communications modules as in the sensor or actuator modules of the device. Hence a great deal of work is put into defining communications protocols allowing for extended communications intervals, poor synchronization, low signal amplitudes etc. Consequently, in order for IoT to really break through, longevity is a necessity.
Hence, there is a need for a more efficient way to control the power consumption in IoT devices to prolong the battery lifetime.


A process for producing a semiconductor device comprising the steps of: forming a metal wiring layer containing copper as the main component on a semiconductor substrate; forming an insulating film on the entire surface of the resulting semiconductor substrate; removing the insulating film only from a place where a wire of gold or aluminum is to be bonded, in order to expose a part of the metal wiring layer; forming a layer of copper silicide or a layer of a compound of copper and boron in a surface layer of the exposed part of the metal wiring layer; and bonding a wire to a surface of the layer of copper silicide or the layer of the compound of copper and boron.

1. Field of the Invention
The present invention relates to a semiconductor device and a process for producing the same. More particularly, it relates to a semiconductor device and its production process which allows direct bonding of a wire on a metal wiring layer containing copper as a main component without need to form an aluminum pad for bonding.
2. Description of Related Art
A metal wiring layer containing copper is of low electric resistance and exhibit good resistance to migration. For this reason, it can reduce signal delay owing to the metal wiring layer in a integrated circuit of a semiconductor device. Especially when the semiconductor device is operated at high-density current, the metal wiring layer containing copper can ensure high reliability. From this viewpoint, copper has begun to be used as a material for the metal wiring layer in place of aluminum.
At present, the metal wiring layer containing copper is used mainly in the semiconductor device having a high-speed logic circuit such as a microprocessor. For packaging the semiconductor device, utilized is a flip-chip technique in which a bump is formed on the semiconductor device (semiconductor chip). In the semiconductor device for general use, bonding is performed using a wire of gold or aluminum. This bonding involves heating at about 200xc2x0 C. at the lowest. Since copper is easily oxidized to its inside at this temperature, it is difficult to perform the bonding without affecting the quality of the devices.
To cope with this inconvenience, proposed are methods of providing an aluminum pad on the metal wiring layer of copper with or without intervention of a diffusion-barrier layer of metal (see Japanese Unexamined Patent Publications Nos. HEI 8(1996)-78410 and HEI 11(1999)-135506).
One example of the above-mentioned methods is now explained with reference to FIGS. 3(a) to 3(e).
A diffusion layer 10 is formed on a silicon substrate 1, and thereafter, an insulating film is formed of SiO2, SiN or the like as an interlayer dielectric film 2. Subsequently, a contact hole is opened in the interlayer dielectric film 2. An adhesion promoting layer 4 is formed of TiN by CVD for enhancing the adhesion of the interlayer dielectric film 2 to a copper wiring layer 5 formed later. This adhesion promoting layer 4 also functions as a diffusion-barrier film for preventing diffusion of copper from the copper wiring layer 5 to the interlayer dielectric film 2. By forming a copper film on the adhesion promoting layer 4 by DC sputtering, the contact hole is filled with a copper film 5xe2x80x2 (see FIG. 3(a)).
Subsequently, an anti-reflection film 11 is formed on the copper film 5xe2x80x2 (see FIG. 3(b)).
Next, the copper film 5xe2x80x2 is formed into the copper wiring layer 5 having a desired pattern by photolithography step and etching step. Subsequently, a surface protection film 12 is formed of an insulating film such as of SiO2, SiN or the like on the surface of the copper wiring layer 5. Further, the surface protection film 12 and the anti-reflection film 11 are selectively removed to expose a part of the copper wiring layer 5. Thus a pad region 7a is opened (see FIG. 3(c)).
After the pad region 7a is opened, a diffusion-barrier layer 3 such as of TiN and an oxidation-resistant metal film 13 such as of AlSiCu are formed in thicknesses of about 20 to 100 nm and about 2 xcexcm, respectively, in the opening of the pad region 7a. Subsequently, the diffusion-barrier layer 3 and the oxidation-resistant metal film 13 are left existing only in the vicinity of the pad region 7a (FIG. 3(d)).
By adopting this construction in which the copper wiring layer 5 in the pad region 7a is covered with the oxidation-resistant metal film 13, it is possible to prevent the oxidation of the copper wiring layer 5 during bonding not only by ultrasonic wire bonding, according to which a bonding face is heated to 200xc2x0 C. or higher, but also by thermocompression wire bonding, according to which the bonding face is heated to 400xc2x0 C. or higher. FIG. 3(e) illustrates a state in which a wire 8 is bonded in the pad region 7a.
FIG. 4 is a schematic sectional view of an example of semiconductor device having two copper-containing wiring layers to which a wire is bonded as disclosed by Japanese Unexamined Patent Publication No. HEI 11(1999)-135506. This semiconductor device is produced as follows; first, a copper wiring layer 5b formed by a damascene method is covered with an insulating film 6, and a bonding pad portion is opened. Thereafter, the insulating film 6 is covered with an aluminum-containing film 9, and the aluminum-containing film 9 is partially removed by photolithography step and etching step so as to remain in the bonding pad portion; next, a wire 8 of gold, aluminum or the like is bonded to the bonding pad portion. In the figure, 2a to 2d denote interlayer dielectric films, 3a to 3c diffusion-barrier films, 4a and 4b copper-diffusion-barrier films and 5a a copper wiring layer.
In the method shown in FIGS. 3(a) to 3(e), the diffusion-barrier layer and the oxidation-resistant layer are formed on the entire surface, and then selectively removed by photolithography step and etching step in such a manner that they remain in the bonding pad portion. Accordingly, this method requires a large number of production steps, and involves an increase in production costs.
The method shown in FIG. 4, in which a pad of the aluminum-containing film is formed as a bonding pad on the copper wiring layer, requires the addition of the step of depositing either aluminum or aluminum and a diffusion-barrier metal, and a photolithography step and etching step or a chemical mechanical polishing step. For this reason, this method requires more production steps than aluminum interconnecting, and involves an increase in the production costs.
Accordingly, the present invention provides a process for producing a semiconductor device comprising the steps of: forming a metal wiring layer containing copper as the main component on a semiconductor substrate; forming an insulating film on the entire surface of the resulting semiconductor substrate; removing the insulating film only from a place where a wire of gold or aluminum is to be bonded, in order to expose a part of the metal wiring layer; forming a layer of copper silicide or a layer of a compound of copper and boron in a surface layer of the exposed part of the metal wiring layer; and bonding a wire to a surface of the layer of copper silicide or the layer of the compound of copper and boron.
Further, the present invention provides a semiconductor device comprising a metal wiring layer containing copper as a main component on a semiconductor substrate; and a layer of copper silicide or a layer of a compound of copper and boron for bonding a wire, the layer being formed in a surface layer of a part of the metal wiring layer.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.

Semiconductor device and its production process


A teleoperated surgical system includes a component such as a master control or a multi-jointed mechanical system that is configured for manual manipulation and a detection module configured to analyze movement of the component and detect uncontrolled movement of the component. Uncontrolled movement may be identified by detecting movement only on joints that gravity can move, but no movement on joints that are not subject to movement caused by gravity. In response to detection of uncontrolled movement of the component, the detection module can cause the system to switch to a safe mode of operation.

Teleoperated or computer assisted medical systems often employ a master control that a physician or other medical personnel can use to control actuated slave medical instruments. A medical instrument may, for example, include a tool such as a scalpel, forceps, or a cauterizing tool, and a surgeon may operate a master control similar to a joystick to provide control signals to a control system. The control system can then convert the control signals into actuation signals that drive actuators to move the instrument, for example, to cut, clamp, or cauterize a patient's tissue so that the tool movement follows the master control movement. One potential concern for such systems is inadvertent or uncontrolled movement of the master control, because a patient could be injured if uncontrolled movement of the master control causes uncontrolled operation of the tool that interacts with a patient's tissue. Surgeons can be trained to avoid situations where uncontrolled movement is possible, but additional techniques or fail safes may be desirable to prevent uncontrolled movement.
One way to reduce the chance of uncontrolled movement of the master control is to restrict movement of the mechanical components of the master control. For example, a master control may be balanced or actively driven so that gravity does not cause the master control to drift away from any position in which a physician may leave the master control. Other ways to reduce the chance of uncontrolled movement of an instrument may use a "locked" mode that decouples the master control from the instrument, so that in the locked mode, movement of the master control does not cause corresponding movement of the instrument. The locked mode might be automatically activated when a physician is not in the proper position for use of the master control. In particular, the system may default to the locked mode unless sensors detect that a physician is in the proper position for use of the system including, for example, being in position to view any movement of an end effector of the medical instrument. However, after a physician has taken a medical system out of the locked mode, the physician might release a master control while remaining in position to use the medical instrument. Releasing the master control under such circumstances may create the risk of the master control moving without physician input, resulting in uncontrolled motion of the medical instrument. For example, gravity compensation in the master control may be imperfect, or a physician's knee or hand may accidentally bump the master control while the physician is in position to use the instrument and the instrument is not in the locked mode.


A process and apparatus that enable continual self-adaptation of dynamic transmission devices (saSTDs), allow xe2x80x9csmartxe2x80x9d filtering of information for transmission from one element to another within a network of interacting elements, such as a xe2x80x9cneural networkxe2x80x9d. An adaptation algorithm (MapSA) incorporated in STDs allows multiple parameters of STDs (which determine its filtering properties) to continuously adapt simultaneously and interdependently. In this manner, complex correlations can be established between the parameters in all STDs within a network of interacting elements. The process according to the invention therefore establishes unique patterns of connection parameters within the network which in turn dictates a novel sequence of information processing steps by the network.

The invention relates to a method and apparatus pertaining to dynamic transmission lines which allows multiple parameters, that control smart operations of dynamic transmission lines, to self-adapt simultaneously according to novel filter functions of the input to the transmission line and the unfiltered response of the target element. This formula or apparatus allows an unlimited number of smart transmission lines to be incorporated into networks of interacting elements.
Networks of interacting elements must be connected by transmission lines. Normally a great deal of effort is made to ensure faithful transmission from one element to the next, and many learning algorithms relate to strengthening or weakening the transmitted signals as a means of controlling the interaction between the elements. However, transmission lines may not always be inert in their transmission; that is, they may actually interact with the transmitted information, thereby modifying their transmission capability and hence the information transmitted. In the brain, for example, neurons are thought to communicate via such complex xe2x80x9csmart connectionsxe2x80x9d.
Such an active role of the transmission line could vastly amplify the information processing capability of a network of interacting elements since the transmission line carries out a xe2x80x9csmart operationxe2x80x9d by selecting to transmit only a subset of information. However, if a network contains millions or billions of such xe2x80x9csmart connectionsxe2x80x9d (hereinafter called smart transmission devices or STDs), it is essentially impossible to set the properties of each STD so that all the xe2x80x9csmart operationsxe2x80x9d carried out by the STDs in the network are compatible with each other. The present invention solves this apparent impossibility of orchestrating smart operations of a vast number of STDs.
The invention is directed to a process and apparatus for converting STDs into multiparameter self-adapting transmission lines (hereinafter called saSTD""s). STDs allow smart filtering of information transmitted from one element to another within a network of interacting elements, such as a xe2x80x9cneural networkxe2x80x9d and a multiple parameter supra-algorithm (hereinafter called MapSA) allows for control of the smart operation. MapSA serves to align the functions of even billions of STDs, allowing each one to transmit information compatible to the other. Such orchestration of a vast number of smart operations in a network could form the basis of a new generation of robots, computers, software programs, electronic circuits and network communication lines.
In order for information (represented by a series of binary electrical pulses) to be transmitted along a communication line from one brain cell to the next, the information must pass through a transfer station called a xe2x80x9csynapsexe2x80x9d. Synapses are essentially electrochemical transducers that convert a binary electrical signal (a pulse of set amplitude) into an analog chemical signal which, in turn, produces an analog electrical signal (a pulse of variable amplitude) in the target cell. About 50 years ago, it was suggested that these synapses can change their transmission strength and that such changes may form the basis of memory storage in neural networks (See D. Hebb, xe2x80x9cThe Organization of Behavior,xe2x80x9d J. Wiley and Sons, New York, 1949). In other words, Hebb originally declared that the strength of transmission lines (also referred to as the xe2x80x9cweightxe2x80x9d or xe2x80x9cgainxe2x80x9d of synaptic transmission) is a plastic parameter. Many different algorithms have been formulated in the past to alter the value of the synaptic gain which are published and form the basis of patents (see for example, Alkon et al., U.S. Pat. No. 5,402,522).
Recently is was declared that the non-linear transfer of information between neurons can also change (H. Markram and M. Tsodyks, 1996; Nature, 382, 807-810). The non-linear transmission of information across synapses is due to a delicate sequence of utilizing the gain of the synapse (gain is equivalent to all available xe2x80x9cresourcesxe2x80x9d of the synapse). For example, a synapse may begin using only a small fraction of its resources and then facilitate progressively increasing use of resources as each pulse of information arrives at the synapse. In addition, every time the resources are spent by the synapse, it takes time to replenish them, which leads to depression of transmission at a time when the information traffic is high.
The interplay between utilization, facilitation and depression results in rapid changes in transmission capacity from one moment to the next. The result is that the information that arrives in the synapse is not faithfully transmitted, but actually filtered in a complex non-linear manner; hence the term xe2x80x9csmart operationxe2x80x9d. Utilization, facilitation and depression are then three crucial parameters of STDs which determine their smart operation. These parameters are also referred to as xe2x80x9ckinetic parametersxe2x80x9d. NOTE: non-linear transmission does not refer to non-linear summation and complex transfer functions that determine how a single cell adds up the multiple analog information; rather, the invention relates to non-linearities in the communication lines (STDs) not in the elements of a network, which are usually seen as the processing elements (PEs).
The major difficulty in connecting PEs in a network via STDs is how to set the values of kinetic parameters that together determine the smart operation of a vast number of STDs. Using the MapSA, the STD is controlled with a device that first assesses the importance of the contribution of each kinetic parameter before determining how the parameter setting should change. The MapSA is different from any prior art in that functions are provided to evaluate the role of the parameters themselves in the transmission as compared to each other (i.e. in a relative manner) and, based on the results of the evaluation, the settings of the parameters are changed. In prior systems, the contribution of the entire synaptic output to the response of the target neuron formed the basis of adjusting the gain of the transmission.
The inventor""s studies of the functional significance of such dynamics indicate that MapSA could align any number of smart operations carried out by STDs across a network; a hitherto unimaginable and unsolvable task since the transmission of as many as 1014 STDs may need to be aligned. In other words, the information transmitted by each STD in the entire meshwork would become compatible and complementary with that transmitted by every other STD, allowing transmission of a multitude of small fragments of related information and spontaneous coagulation into a coherent and complete representation of an image, sound, smell etc., and therefore represent the most efficient form of information processing possible in networks.
An object of the invention is to provide a process and apparatus to construct saSTDs which can then be incorporated into networks of interacting elements. Since MapSA solves the problem of using STDs in networks this invention allows for a new generation of networks with virtually limitless capacity for change.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.

Method and apparatus for constructing a self-adapting smart transmission device to control information transmission between elements of a network


In a fixing unit 230, a medium introducing port 250 is provided near a gripping part 230a of a housing 230, and a sheet material 90 to be subjected to a fixing process is guided to the medium introducing port. A shutter 260 is provided slanted at a given angle with respect to a gripping surface 240 of the gripping part 230a of the fixing unit 230 such that the shutter has a fulcrum at a part thereof, which is closer to the gripping part 230a of the fixing unit 230, at the medium introducing port 250, and the shutter 260 is turnable to a position to close the medium introducing port 250 while resisting the urging forces of the twisted springs 270.

The present invention relates to a fixing device in use for an image forming apparatus of the electrostatic recording type, such as a copying machine, a facsimile or a printer.
A conventional image forming apparatus based on an electrophotographic system operates in the following way. A photosensitive member as an image carrying body is charged by a charger. The charged photosensitive member is irradiated with light containing image information to thereby form a latent image on the photosensitive member. The latent image is developed, with a developing device, into a toner image. The toner image is transferred onto a recording medium to form or reproduce a picture on the medium.
With colorization of the image, there is proposed a color image forming apparatus of the tandem type for forming a full color image. This type of the image forming apparatus is provided with a plurality of image forming units each executing the image forming process as mentioned above. Color toner images of cyan, magenta, and yellow, and preferably black are formed on photosensitive members provided for those colors. At transfer positions on the photosensitive members, those toner images are superimposed one on another, and transferred onto an endless intermediate transfer body.
The image forming apparatus of the toner image transfer type includes a fixing device. The fixing device contains a fixing nip part formed with a couple of rollers. The fixing nip part nips and transfers the recording medium. When the recording medium passes through the nip part, the toner image, not yet fixed, on the recording medium is fused under pressure, and is fixed on the recording medium. Since the fixing unit heats the toner for its fusing, temperature of the rollers is high.
For example, it has proposed in JP-A-2001-249562.
When the fixing device is detached from the image forming apparatus immediately after the printing operation ends, a message to inhibit the worker from touching the hot rollers is visually presented for the purpose of jamming removal or part replacement.
However, it is inevitable that the worker will touch the hot rollers carelessly or accidentally. Accordingly, use of only the message is not sufficient for giving a sure warning to the worker.

Image forming apparatus having a removable fixing device

Matsushita Electric Industrial Co., Ltd.


2-Keto-L-gulonic acid, an ascorbic acid intermediate, is prepared by cultivating a microorganism of the genus Citrobacter in an aqueous nutrient medium in the presence of 2,5-diketo-D-gluconic acid.

This invention relates to the preparation of 2-keto-L-gulonic acid by microbiological means.
2-keto-L-gulonic acid is a valuable intermediate in the preparation of ascorbic acid (vitamin C), an essential vitamin for human nutrition. Processes for converting 2-keto-L-gulonic acid to ascorbic acid, for example by heating in the presence of a base, are well known in the art.
Only a limited number of microorganisms are known in the art to be effective for the reduction of 2,5-diketo-D-gluconic acid to form 2-keto-L-gulonic acid, as shown for example in U.S. Pat. Nos. 3,963,574, 3,922,194 and 3,959,076. Microorganisms of the genus Citrobacter have not previously been disclosed to be effective in this reaction.


This invention relates to a lead-free solder alloy composition and a method of preparing a lead-free solder alloy, wherein the lead-free solder alloy composition includes a ceramic powder added to a lead-free solder of Sn-(0.1 to 2) wt % Cu, Sn-(0.5 to 5) wt % Ag, or Sn-(0.1 to 2) wt % Cu-(0.5 to 5) wt % Ag. According to this invention, a novel lead-free solder alloy, which functions as a replacement for a conventional lead-free solder, is provided, thus exhibiting superior spreadability, wettability, and mechanical properties than a conventional lead-free solder.

Typically, Sn—Pb-based lead solder has been used as the most effective binding material for electronic devices for a long time. However, when an electronic device using a solder is discarded, lead (Pb) contained in the solder is eluted by acid rain thereby polluting groundwater. Furthermore, such component has been identified as an environmental pollutant because it harms the human body, for example, deteriorating intelligence and reproductive function, when absorbed by the human body. Such lead solder is particularly utilized as a binder for mounting small electronic parts such as semiconductor chips or resistor chips on a printed circuit board.
In particular, the use of lead (Pb)-containing products is strictly limited, and Sn—Pb solder is being replaced with lead-free solder. A variety of restrictions for prohibiting the use of Pb in micro-electronic devices have been imposed. Thus, Sn—Pb solder has to be replaced with Pb-free Sn—Ag solder to develop an environmentally friendly lead-free solder. For this reason, in recent times, when solder alloy is manufactured, the use of lead is restricted or excluded, whereby many attempts have been made to develop an environmentally friendly lead-free solder composition.
Technology relevant to the lead-free solder is proposed in Korean Patent Nos. 0209241 and 0814977.
As disclosed in Korean Patent Nos. 0209241 and 0814977, a lead-free solder composition, and a high-temperature system lead-free solder composition and an electronic device and a printed circuit board using the same, are briefly described below.
The lead-free solder composition comprising tin (Sn), silver (Ag), bismuth (bi) and indium (In), which is disclosed in Korean Patent No. 0209241 (Prior Art 1), is composed of 82 wt % to 93 wt % of tin (Sn), 2 wt % of silver (Ag), 3 wt % to 10 wt % of bismuth (Bi), and 2 wt % to 6 wt % of indium (In).
However, indium (In) needed to form the lead-free solder composition of Prior Art 1 is expensive, and a solder containing bismuth (Bi) may become brittle due to deteriorating ductility with increasing amount of bismuth (Bi).
FIG. 1 is a mimetic diagram schematically showing the principle of inhibiting the generated amount of an oxide of a lead-free solder composition in Korean Patent No. 0814977 (Prior Art 2). As shown in FIG. 1, the high-temperature system lead-free solder composition of Prior Art 2 comprises 2 wt % to 5 wt % of copper, 0.001 wt % to 1.0 wt % of nickel, 0.001 wt % to less than 0.05 wt % of silicon, 0.001 wt % to 0.2 wt % of phosphorus, 0.001 wt % to less than 0.01 wt % of cobalt, and the remainder of tin.
However, the high-temperature system lead-free solder composition of Prior Art 2 also needs indium which is expensive and thus, there is a problem in that the use of indium is limited.
Although not shown in the drawing, recently attention has been focused on the development of solders comprising Sn, Ag, Bi, Cu, In, and Zn, particularly a composition composed of Sn, Ag and Cu. However, the aforementioned respective lead-free solders have various problems. For example, Zn is sensitive to oxidation and resulting decrease in solderability. Solder including Bi is decreased in ductility with an increase in Bi content, thus causing brittleness. Sn—Cu solder is inexpensive, but has very poor wettability. Solder containing In is expensive. Solder containing Ag readily forms a coarse needle-shaped intermetallic compound Ag3Sn, thus decreasing solderability and joint strength. Consequently, not only solder including lead-free solder, but also the aforementioned disadvantages (especially wettability) have to be minimized.
Moreover, Sn-0.7Cu, Sn-3.5Ag, and SAC305 solder (96.5 wt % Sn-3.0 wt % Ag-0.5 wt % Cu) microstructures include a dendritic phase and a eutectic phase composed of Sn, Ag3Sn, and Cu6Sn5. However, the shape and structure of Ag3Sn and Cu6Sn5 are regarded as important in terms of reliability of the solder. If the amount of Ag is greater than 2 wt % in the matrix, a coarse plate of Ag3Sn may be formed, undesirably worsening soldering properties. On the other hand, if the amount of Ag in the Sn—Ag alloy is less than 2 wt %, a liquid temperature may be increased, a coexistence region of a liquid phase and a solid phase is enlarged, and the strength of the joint may decrease. Hence, the growth of intermetallic compounds has to be inhibited using a ceramic nanopowder-reinforcing agent as an additive.

Lead-free solder alloy composition and method for preparing lead-free solder alloy


A shaft seal that is preferably a radial shaft seal has a sealing element of polyfluorocarbon that is provided with a sealing lip. The sealing element contacts a surface to be sealed under a radial force action acting in a radial direction of the shaft seal. An elastomer element is provided that is acting on the sealing lip and loads the sealing lip in a direction toward the surface to be sealed. The elastomer element supports the sealing element. The sealing element is resting flat on a face of the elastomer element, wherein the face is facing away from a medium side of the shaft seal.

The invention concerns a shaft seal, in particular a radial shaft seal, with at least one sealing element of polyfluorocarbon, preferably polytetrafluoroethylene, that is provided with a sealing lip that is contacting a surface to be sealed under radial force action.
In shaft seals in the form of radial shaft seals, polyfluorocarbon, in particular polytetrafluoroethylene, is used as a material for the sealing elements because of its special physical and chemical properties. The sealing elements are embodied as annular disks whose radial inner area is elastically bent for forming the sealing lip. In case of polyfluorocarbons, in particular polytetrafluoroethylene, creeping can be observed. Moreover, these materials have a relatively minimal mechanical strength. Creeping of this material has the result that the sealing action decreases. In order to counteract this creeping action, the radial pretension that is acting on the sealing lip is therefore increased. This causes however a correspondingly greater wear of the sealing lip. In sealing applications, it is therefore difficult to find a balance between seal-tightness and wear.
In order to achieve this balance, it is known to add to the sealing element different fillers, for example, glass fibers, carbon fibers, bronze and the like. These additives however require a complex and expensive manufacture.
The invention has the object to configure the shaft seal of the aforementioned kind in such a way that its seal-tightness during its period of use is substantially maintained while its manufacture is constructively simpler and less expensive.

Shaft seal, especially radial shaft seal


A polyolefin microporous breathable film having improved tear and impact strength as well as a soft feel is provided by a film including a polypropylene precursor film and a filler. Other embodiments include a second polymer component.

1. Field
This invention relates generally to a polyolefin microporous breathable film and method of making same. More specifically this invention is directed toward filled polypropylene microporous breathable films having an improved Water Vapor Transmission Rate (WVTR), high tear strength, high dart impact strength, and a soft feel.
2. Definitions
As used therein the term "extrusion" is intended to include extrusion, coextrusion, extrusion coating, or combinations thereof, whether by tubular methods, planar methods, or combinations thereof.
An "oriented" material is defined herein as a material which, when heated to an appropriate temperature above room temperature (e.g., 96° C.), will have a free shrink of about 5% or greater in at least one linear direction.
Unless specifically set forth and defined or otherwise limited, the term "polymer" as used herein generally includes, but is not limited to, homopolymers, copolymers, such as, for example, block, graft, random and alternating copolymers, terpolymers, etc. and blends and modifications thereof. Furthermore, unless otherwise specifically limited, the term "polymer" shall include all possible molecular configurations of the material. These structures include, but are not limited to isotactic, syndiotactic and random molecular configurations.
The term "polyethylene" as used herein refers to families of resins obtained by substantially polymerizing the gas ethylene C2H4. Polyethylenes having densities ranging from about 0.900 g/cc to about 0.935 g/cc are typically called low density polyethylenes (LDPE).
The term "linear low density polyethylene" (LLDPE) as used herein for a type of polyethylene to be employed in the film of the invention, refers to the copolymers comprised of a major amount of ethylene with a minor amount of one or more comonomers selected from C3 to about C10 or higher alpha olefins such as butene-1,4-methyl petene-1, hexene-1, octene-1, etc. in which the molecules thereof comprise long chains with few side chains or branched structures achieved by low pressure polymerization. The side branching which is present will be short as compared to non-linear polyethylenes. The molecular chains of a linear polymer may be intertwined, but the forces tending to hold the molecules together are physical rather than chemical and thus may be weakened by energy applied in the form of heat. Linear low density polyethylene has a density preferably in the range from about 0.911 g/cc, more preferably in the range of from about 0.912 g/cc to about 0.928 g/cc for film making purposes. The Melt Flow Index of LLDPE generally ranges from between about 0.1 to about 10.0 grams per ten minutes and preferably between from about 0.5 to about 3.0 grams per ten minutes. LLDPE resins of this type are commercially available and are manufactured in low pressure vapor phase and liquid phase processes using transition metal catalysts. LLDPE is well known for its structural strength and anti-stress cracking properties. Also, LLDPE is known for its favored properties in the heat shrink process, and thus is well suited to make a heat shrinkable film as discussed above. Also, very low density linear low density polyethylenes (VLDPE) may be employed, and such have a density from about 0.010 g/cc to about 0.860 g/cc, or less.
The term "polypropylene" as used herein which polypropylene is a type of polyolefin that may be employed in the film of the present invention, refers to families of resins obtained by substantially polymerizing the gas propylene, C3H6.
By varying the comonomers, catalysts and methods of polymerization, properties such as density, melt index, crystallinity, degree of branching, molecular weight and molecular weight distribution can be regulated over wide ranges. Further modifications are obtained by other processes, such as halogenation, and compounding additives.

Method of making microporous breathable film


The present invention provides methods for determining whether activated carbon can be used for removing viruses or a certain virus from a sample containing a target protein.

The most commonly used processes for purifying target proteins such as, e.g., monoclonal antibodies, typically employ an engineered cell line (e.g., a mammalian or a non-mammalian cell line) capable of expressing the target protein. Such a target protein may either be secreted into the cell culture media or it may be expressed intracellularly and recovered following lysis of cells expressing the protein.
The target protein typically needs to be subjected to a series of purification steps to separate the target protein from various impurities, e.g., cells, cell debris, DNA, host cell proteins etc.
A typical purification process usually entails subjecting the cell culture feed or media (in case of a secretory target protein) or cell lysate (in case of an intracellular target protein) to a variety of steps, including one or more chromatography steps to isolate or purify the target protein. For example, in case of a secretory target protein, e.g., a monoclonal antibody, the cell culture media is typically subjected to a clarification step followed by a capture step followed by one or more of a cation exchange bind/elute chromatography step and an anion exchange chromatography step.
CHO cells are commonly used for the production of monoclonal antibodies. A typical CHO cell culture feed contains 103 to 109 viruses or virus-like particles and the removal of such viruses or virus-like particles is especially important during the purification process, as many of the target proteins are therapeutic proteins which are directly administered to patients. Generally, virus removal is evaluated based on the amount of total virus removal achieved by the entire purification process, which is desirable to be equal to or exceeding 18 logs, especially in cases where regulatory approval is required.
Generally, each step of a typical purification process is shown to remove some amount of viruses, however, the amount is usually less than 18 logs; and therefore, additional purification steps must be included in the process for adequate virus removal. It is important to establish whether or not a particular purification step can remove a certain amount of virus in order to ensure that adequate virus removal is achieved by the various purification steps in a purification process.
Guidance for virus safety evaluation of samples, e.g., biotechnology products, can be found in "Harmonized Tripartate Guideline: Q5A Viral Safety of Biotechnology Products Derived From Cell Lines of Human or Animal Origin. Fed. Reg. 63(185) 24 Sep. 1998," prepared under the auspices of the International Conference on Harmonization of Technical Requirements for Registration of Pharmaceuticals for Human Use (ICH).
Activated carbon has previously been used in water purification applications to remove viruses as well has been incorporated in filtration units for non-specific removal of substances, which may include viruses, from biological fluids, e.g., blood (e.g., see, U.S. Pat. No. 8,123,940)
Further, U.S. patent application Ser. No. 13/565,463, filing date Aug. 2, 2012, incorporated by reference herein in its entirety, describes the use of activated carbon in combination with other media for removal of proteinaceous impurities (e.g., host cell proteins) and DNA from a sample containing a biomolecule of interest (e.g., an antibody).
Lastly, U.S. Provisional Patent Application Ser. No. 61/769,269, filing date Feb. 26, 2013, incorporated by reference herein, describes the use of activated carbon for the selective removal of a protein from a mixture of proteins by changing solution conditions.

Method of determining virus removal from a sample containing a target protein using activated carbon


A multilayer wiring structure for electromigrationproof comprises a first wiring layer and a second wiring layer separated each other by insulating layer. Each of the first and second wiring layers consists of a core portion and a cladding portion. The core portion consists of a metal having a high resistance to electromigration such as gold or a metallic material having gold as the principal constituent. The cladding portion consists of a material having a good adhesion to the insulating layer. Such material is what selected from tungsten (W), titanium-tungsten alloy (TiW) and molybdenum (Mo). The insulating layer preferably consists of organic insulating material having a good surface-flatness such as polyimide.

The present invention relates to an electromigration-proof structure for a multilayer wiring on a semiconductor device, and more particularly to a semiconductor device with multilayer interconnection structure having an interlayer insulating film with excellent surface flatness and a metallic wiring with high resistance to electromigration.
A multilayer wiring structure is extremely effective in semiconductor integrated circuits such as LSI for increasing the level of integration and the packaging density and for decreasing the chip size. In such a case, it is necessary to keep the surface of the interlayer insulating film flat in order to suppress defective step coverage and breaking failure of the upper layer metallic wirings and to obtain a highly reliable multilayer wiring structure.
For these reasons, in the prior art multilayer wiring structures of the above description, organic coating films or the like are used as the interlayer insulating films. In addition, those films are normally used also for passivation films (covering and insulating films). As for a metallic wiring for each layer, Al (aluminum) film has been used to have a good adhesion to the insulating film.
However, in the prior art semiconductor device with multilayer wiring structure as described in the above, the wiring metallic film having Al as the principal constituent has a low resistance to electromigration. Accordingly, these has been a difficulty to use the Al wirings in high speed devices requiring a large current due to a short lifetime of the wirings.
On the other hand, the lifetime of the wirings can be prolonged by using a metallic wiring with Au (gold) as the principal constituent that has a high resistance to electromigration. However, there is another difficulty in putting it to practical use in the conventional structure because of the disadvantage that the adhesion of Au to the interlayer insulating film and the passivation film is poor. For evaluation of the adhesion of a film, it is usual to employ a peeling test which makes use of an adhesive tape. According to this method, adhesion between a film and an underlying material is evaluated in the form of a comparison with the adhesion between the adhesive tape and the film. More specifically, a "block" pattern of squares with side of about 1 mm is incised on the film using a diamond cutter or the like, the adhesive tape is stuck on it and then stripped, and the adhesion is evaluated by counting the number of peeled "blocks" bonded to the tape. For the adhesion performance of the film, it is required in this evaluation method that the number of peeled "blocks" should always be zero. According to the result of the investigation for the combination of Au and an insulating film, the insulating film that can satisfy the standard was only nitride film formed by plasma CVD method. Since, however, the step coverage of this film is extremely poor, it is not possible to apply this film to a flattened multilayer interconnection structure such as is of interest to the present invention.
It is, therefore, a primary object of the present invention to provide a wiring structure having a metallic wiring which can maintain the surface flatness of the interlayer insulating film and the passivation film, and has a high resistance to electromigration.

Electromigrationproof structure for multilayer wiring on a semiconductor device


An optical element driving circuit flexibly configures energy sources to cause illumination with an optical output element, such as a flash lamp. The energy sources include an illumination capacitor and a capacitive voltage divider circuit coupled with the optical output element. The illumination capacitor may be charged to a first voltage and a boost capacitor of the capacitive voltage divider circuit may be charged to a second voltage that is a fraction of the first voltage. The optical element driving circuit also includes a triggering circuit coupled with the capacitive voltage divider circuit. The triggering circuit is configured to place a sum of the first voltage and the second voltage across the optical output element.

1. Technical Field
This application relates to optical element driving circuits and, more particularly, to setting a voltage level across an optical output element.
2. Related Art
Emergency warning systems often include visual alarms, such as strobe lights or flash lamps. Many strobe alarms include driving circuits which rely on a step-up transformer to prime a flash lamp for illumination and one or more capacitors to store energy to cause the illumination using the flash lamp. Flash lamps are designed to operate within a specified voltage range which must be met to ensure reliable flash lamp operation. Prior driving circuits sometimes employed voltage doubling circuits to drive the flash lamp and cause the illumination. However, the voltage must be carefully controlled not only to correctly generate the desired amount of illumination, but also to prevent component damaging arcing and other undesirable effects. Therefore, a need exists for an optical element driving circuit that provides reliable flash lamp operation at appropriate voltages.


An array of non-volatile memory cells arranged in rows and columns is provided. Each memory cell is composed of a transistor made up of a gate, a source, and drain and a capacitance section. Each memory cell is connected to a row decoder through a wordline, to a column decoder through a bitline, and to a source decoder through a sourceline. Arranged in a path extending from a bitline to a sourceline through a transistor is an anisotropic resistance section, e.g., a diode, exhibiting different voltage-current characteristics for different levels of voltages applied thereacross. Because of such arrangement, leakage current occurring to a deselected memory cell in a reading operation can be reduced or can be eliminated. Read errors due to leakage current can be avoided and the power consumption can be reduced.

This invention relates to a non-volatile semiconductor memory having an array of non-volatile memory cells and relates to a method for driving a non-volatile semiconductor memory.
Many such non-volatile semiconductor memories have been known in the art. Japanese Patent Application (Pub. No. 5-28778) and Japanese Patent Application (Pub. No. 4-15953) each disclose a non-volatile semiconductor memory, wherein source decoders are connected to separate sourcelines associated with separate memory cell sources. Referring now to FIGS. 42-44, a non-volatile semiconductor memory of a conventional type having an array of nonvolatile memory cells is illustrated. FIG. 42 outlines in block form a conventional non-volatile semiconductor memory structure. Shown in FIG. 42 are a memory cell array 101, a row decoder circuit 102, a column decoder circuit 103, and a source decoder circuit 104. FIG. 43 is a circuit diagram depicting a part of the memory cell array 101. Referring to FIG. 43, therein are shown TRANSISTORS T11-Tmn, WORDLINES W1-Wm, BITLINES B1-Bn, SOURCELINES S1-Sm, and COLUMN SELECTION TRANSISTORS ST1-STn. Each TRANSISTOR T11-Tmn has a source, a drain, and a gate underlying which is a floating gate (i.e., a capacitance section). The memory cell array 101 has an array of memory cells arranged in m rows and n columns, each memory cell having therein a TRANSISTOR T. Each of the gates of TRANSISTORS T11-T1n in the first row is coupled to WORDLINE W1, and each of the gates of TRANSISTORS T21-T2n in the second row to WORDLINE W2, and each of the gates of TRANSISTORS Tm1-Tmn in the mth row to WORDLINE Wm. Each of the sources of TRANSISTORS T11-T1n in the first row is coupled to SOURCELINE S1, and each of the sources of TRANSISTORS T21-T2n in the second row to SOURCELINE S2, and each of the sources of TRANSISTORS Tm1-Tmn in the mth row to SOURCELINE Sm. Each of the drains of TRANSISTORS T11-Tm1 in the first column is coupled to BITLINE B1, and each of the drains of TRANSISTORS T12-Tm2 in the second column to BITLINE B2, and each of the drains of TRANSISTORS T1n-Tmn in the nth column to BITLINE Bn. Such arrangement is called an NOR-type structure in which transistors are arranged at points where WORDLINES W1-Wm and BITLINES B1-Bn cross one another. Here, WORDLINES W1-Wm run parallel with SOURCELINES S1-Sm. Whereas WORDLINES W1-Wm are connected to corresponding ROW DECODERS RD1-RDm of the row decoder circuit 102, SOURCELINES S1-Sm are connected to corresponding SOURCE DECODERS SD1-SDm of the source decoder circuit 104. BITLINES B1-Bn run in the cross direction to WORDLINES W1-Wm and SOURCELINES S1-Sm and are connected to the column decoder circuit 103 via SENSE AMPLIFIERS SA1-SAn. If, in a TRANSISTOR T, the capacitance section has a memory state of "one" when the electric potential of the gate is above Vt (the threshold voltage) and when V.sub.DS (the drain-source voltage) is above a predetermined value, then a current flows through a PATH P (P11-Pmn) extending from a certain location of a BITLINE B to a SOURCELINE S through TRANSISTOR T. On the other hands, if the capacitance section has a memory state of "zero", then no electric current flows.
Referring now to FIG. 44, a reading operation of extracting data out of a conventional non-volatile semiconductor memory is explained. The writing and erasing of a non-volatile semiconductor memory, e.g., an EEPROM (electrically-erasable, electrically-programmable, read-only-memory), is performed by greatly changing a transistor threshold voltage level. If a transistor is in a high threshold voltage state above Vcc (the reading supply voltage), this is called a "zero" state. On the other hand, if a transistor is in a low threshold voltage state below Vcc, this is called a "one" state. These transistor state definitions are used hereinafter throughout the specification.
A conventional reading operation of extracting data out of, for example, a memory cell having therein TRANSISTOR T22 (hereinafter called MEMORY CELL (T22)) is now explained. WORDLINE W2, which is a selected wordline, is set to Vcc (the reading supply voltage), for example, 5 V. On the other hand, WORDLINES W1, W3-Wm, which are deselected wordlines, are set to Vss (the ground level), for example, 0 V. At the same time, SOURCELINE S2, which is a selected sourceline, is set to Vss. On the other hand, SOURCELINES S1, S3-Sm), which are deselected sourcelines, are set to Vrm (the reading intermediate voltage level), for example, 1 V, or are brought to a "float" while being kept at Vrm. BITLINE B2, which is a selected bitline, is set to Vrm via a corresponding sense amplifier. On the other hand, BITLINES B1, B3-Bn, which are deselected bitlines, are set to Vss or are brought to a "float" while being kept at Vss. Practically, a bitline is connected to a respective sense amplifier and a slight bitline potential variation from Vrm occurs. However, for the purpose of simplifying the description, it is assumed that the bitline potential stays constant. Although it has been described that deselected sourcelines and deselected bitlines may be brought to a "float", the description will be made on condition that a deselected sourceline is set to Vrm and a deselected bitline is set to Vss. MEMORY CELL (T22) in the "zero" state passes no current and no current flows through BITLINE B2 accordingly. If MEMORY CELL (T22) has a "one" state, a current flows from BITLINE B2 to SOURCELINE S2 through MEMORY CELL (T22). By detecting the presence or absence of a current flowing in BITLINE B2, a read is accomplished.
In the above-described semiconductor memory, SOURCELINE S1 is at Vrm so that SOURCELINE S1 and BITLINE B2 are at the same electric potential. This produces greater resistance to a current flowing from BITLINE B2 to SOURCELINE S1. Therefore, MEMORY CELL (T12) is unlikely to be misread, thereby increasing the margin of reading.
In semiconductor memories having an array of non-volatile memory cells, control of writing and erasing operations may not be a solution to improving variations in the memory cell threshold-voltage and a memory cell is likely to be over-depleted to have a negative threshold voltage. During fabrication of non-volatile semiconductor memories, variations in the memory cell threshold voltage are caused by processing variations including variations in the impurity concentration and variations in the size. Additionally, as the level of integration increases, dimensional errors and the like produce larger threshold voltage variations. Further, the semiconductor memory industry is now trying to reduce the operating voltage of non-volatile semiconductor memories of large integration as low as possible, to provide low power memories for the purpose of solving heat problems. Therefore, the center of the distribution of threshold voltages among individual memory cells now shifts to lower voltage ranges. Such, however, produces some problems. For example, as the dimensions of non-volatile semiconductor memories decrease and as the scale of integration increases, the probability of part of memory cells in an array being over-depleted increases.
If MEMORY CELL (T22) in the "one" state is read when MEMORY CELL (T12), which is a deselected memory cell and which is coupled to the selected BITLINE B2, is in an over-depletion state, then an electric current flows through BITLINE B2 and the potential of BITLINE B2 drops. At this point in time, a current flows from SOURCELINE S1 at Vrm into BITLINE B2 through MEMORY CELL (T12), whereupon the potential of BITLINE B2 is brought back to Vrm. If BITLINE B2 makes no potential transitions, this may cause SENSE AMPLIFIER SA2 coupled to BITLINE B2 to make an incorrect detection that MEMORY CELL (T22) has a "zero" state, although MEMORY CELL (T22) has in fact a "one" state. Read errors may result. Conventional non-volatile semiconductor memories produce the problem that read errors are likely to occur because of existence of depleted memory cells.
In a conventional non-volatile semiconductor memory, in a reading operation (see FIG. 44), even when a deselected memory cell, e.g., MEMORY CELL (T11), is slightly depleted, an electric current flows from SOURCELINE S1 into BITLINE B1 which is a deselected bitline. Such a current causes no read errors because it flows in a deselected bitline but increases the amount of power required. In a conventional non-volatile semiconductor memory, a deselected sourceline and a deselected bitline are brought to a "float". However, in such a case, a transitional current is created for every reading operation, and low power dissipation cannot be accomplished during a fast reading operation.
Even if writing and erasing operations are controlled by performing a verification operation, there still exist large variations in the memory cell property and a memory cell is depleted having a threshold voltage of 0 V or less. Variations in the memory cell threshold voltage are caused by processing variations including variations in the impurity concentration and variations in the size. Additionally, as the level of integration increases, dimensional errors and the like produce larger threshold voltage variations.
The threshold voltage of non-volatile memory transistors, especially the threshold voltage of non-volatile memory transistors having a stack-type floating gate, is drain voltage-dependent. This is explained with reference to FIGS. 46, 47a-b and using formulas expressing the relationship of capacitance versus electric potential. FIG. 46 shows in cross section a transistor having a stack-type floating gate structure. FIGS. 47a, 47b are graphs each showing the relationships of drain current, Id, versus gate voltage, Vg in trial products of the present invention having a stack-type floating gate structure and in usual MOS transistors. In FIG. 46, 61 is a floating gate. 62 is a control gate. 63 is a drain. 64 is a source. 1 is a semiconductor substrate. Dielectric layers are not shown in the figure. Cc is the floating gate-control gate capacitance. Cd is the floating gate-drain capacitance. Cs is the floating gate-source capacitance. Cb is the floating gate-semiconductor substrate capacitance. Vcg is the voltage applied to the control gate 62. Vfg is the electric potential of the floating gate 61. Vd is the drain voltage. Vs is the source voltage. Vb is the electric potential of the semiconductor substrate 1. As shown in FIG. 47b, in the usual MOS transistor there is almost no difference in the threshold voltage between when Vd=0.1 V and when Vd=2.0 V. A threshold voltage viewed from a floating gate, VTfg, is almost independent of Vd and stays constant. On the other hand, as shown in FIG. 46, the floating gate 61 and the drain 63 are in capacitive coupling relationship. Upon application of Vd to the drain 63, the potential of the Floating gate 61, Vfg, drops by rd Vd (rd=Cd/Ct) as shown in the following formulas. Additionally, a threshold voltage viewed from the control gate 62, VTcg, drops by rd Vd/r because of Vd. As a result, as shown in FIG. 47a, in the non-volatile memory transistor having a stack-type floating gate structure, there is a difference of about 0.3 V (usually 0.2-0.4 V) in the threshold voltage between when Vd=0.1 V and when Vd=2.0 V.
Ct=Cc+Cd+Cs+Cb PA1 r=Cc/Ct, rd=Cd/Ct, rs=Cs/Ct, rb=Cb/Ct PA1 Vcg=(Vfg-rd Vd-rs Vs-rb Vb)/r PA1 VTcg0=(VTfg -rs Vs -rb Vb )/r PA1 VTcg=VTcg0-rd Vd/r PA1 an array of non-volatile memory cells arranged in columns and rows, wherein each said non-volatile memory cell has a transistor and a capacitance section, said transistor being composed of, at least, a gate, a source, and a drain; PA1 a plurality of wordlines, wherein each said wordline is connected to each of said gates in a row of said memory cell array; PA1 a plurality of bitlines, wherein each said bitline is connected to each of said drains in a column of said memory cell array; PA1 a plurality of sourcelines, wherein each said sourceline is connected to each of said sources in a row of said memory cell array; PA1 a row decoder circuit for selecting among said plurality of wordlines; PA1 a column decoder circuit for selecting among said plurality of bitlines; PA1 a source decoder circuit for selecting among said plurality of sourcelines; PA1 a plurality of anisotropic resistance sections; PA1 wherein: PA1 a plurality of sense amplifiers, each of the sense amplifiers requiring a reference electric potential; PA1 a plurality of reference dummy cells, each of the reference dummy cells being arranged in each said bitline; PA1 wherein: PA1 said memory comprising: PA1 a plurality of sense amplifiers, each of said sense amplifiers requiring a reference electric potential; PA1 a plurality of reference dummy cells, each of said reference dummy cell being arranged in a said bitline; PA1 wherein: PA1 an array of non-volatile memory cells arranged in columns and rows, wherein each said non-volatile memory cell has a transistor and a capacitance section, said transistor being composed of, at least, a gate, a source, and a drain; PA1 a plurality of wordlines, wherein each said wordline is connected to each of said gates in a row of said memory cell array; PA1 a plurality of bitlines, wherein each said bitline is connected to each of said drains in a column of said memory cell array; PA1 a plurality of sourcelines, wherein each said sourceline is connected to each of said sources in a row of said memory cell array; PA1 a row decoder circuit for selecting among said plurality of wordlines; PA1 a column decoder circuit for selecting among said plurality of bitlines; PA1 a source decoder circuit for selecting among said plurality of sourcelines; PA1 a plurality of anisotropic resistance sections; PA1 wherein: PA1 said non-volatile semiconductor memory comprising: PA1 an array of non-volatile memory cells arranged in columns and rows, wherein each said non-volatile memory cell has a transistor and a capacitance section, said transistor being composed of, at least, a gate, a source, and a drain; PA1 a plurality of wordlines, wherein each said wordline is connected to each of said gates in a row of said memory cell array; PA1 a plurality of bitlines, wherein each said bitline is connected to each of said drains in a column of said memory cell array; PA1 a plurality of sourcelines, wherein each said sourceline is connected to each of said sources in a row of said memory cell array; PA1 a row decoder circuit for selecting among said plurality of wordlines; PA1 a column decoder circuit for selecting among said plurality of bitlines; PA1 a source decoder circuit for selecting among said plurality of sourcelines; PA1 said drive method comprising the steps of:
.thrfore.Vfg=r Vcg+rd Vd+rs Vs+rb Vb PA2 each said anisotropic resistance section is arranged in a path from a said bitline to a said sourceline through a said transistor; PA2 each said anisotropic resistance section has voltage-current properties which are different for different levels of voltages applied across said anisotropic resistance section; PA2 each said anisotropic resistance section has a forward direction in which a current flows therethrough with lesser resistance and a reverse direction in which a current flows therethrough with greater resistance. PA2 the reference electric potential is generated in one of two adjoining bitlines. PA2 an array of non-volatile memory cells arranged in columns and rows, wherein each said non-volatile memory cell has a transistor and a capacitance section, said transistor being composed of, at least, a gate, a source, and a drain; PA2 a plurality of wordlines, wherein each said wordline is connected to each of said gates in a row of said memory cell array; PA2 a plurality of bitlines, wherein each said bitline is connected to each of said drains in a column of said memory cell array; PA2 a plurality of sourcelines, wherein each said sourceline is connected to each of said sources in a row of said memory cell array; PA2 a row decoder circuit for selecting among said plurality of wordlines; PA2 a column decoder circuit for selecting among said plurality of bitlines; PA2 a source decoder circuit for selecting among said plurality of sourcelines; PA2 a plurality of anisotropic resistance sections; PA2 wherein: PA2 selecting, from among said plurality of bitlines, a bitline associated with a memory cell to be read by means of said column decoder circuit; PA2 selecting, from among said plurality of sourcelines, a sourceline associated with said memory cell by means of said source decoder circuit; PA2 setting the electric potential of said selected bitline and the electric potential of said selected sourceline such that the electric potential relationship of said selected bitline versus said selected sourceline agrees with said forwarding direction of said anisotropic resistance section, and setting the higher of said selected bitline's electric potential and said selected sourceline's electric potential as a reading electric potential; PA2 setting the electric potential of deselected sourcelines to an electric potential level above the lower of said selected bitline's electric potential and said selected sourceline's electric potential but below said reading electric potential. PA2 said reference electric potential is generated in one of two adjoining bitlines; PA2 said drive method further comprising the steps of: PA2 each said anisotropic resistance section is arranged in a path from a said bitline to a said sourceline through a said transistor; PA2 each said anisotropic resistance section has voltage-current properties which are different for different levels of voltages applied across said anisotropic resistance section; PA2 each said anisotropic resistance section has a forward direction in which a current flows therethrough with lesser resistance and a reverse direction in which a current flows therethrough with greater resistance PA2 wherein: PA2 selecting, from among said plurality of sourcelines, a source line associated with a memory cell of said memory cells to be read by means of said source decoder circuit; PA2 selecting, from among said plurality of wordlines, a wordline associated with said memory cell; PA2 setting the electric potential of said selected wordline to a given electric potential level; PA2 setting the electric potential of all of said bitlines to a first electric potential level; PA2 setting the electric potential of said selected sourceline to a second electric potential level higher than said first electric potential level for reading said memory cell.
There are produced variations in the memory cell threshold voltage because of the heterogeneous distribution of impurity concentrations during manufacture and because of the condition of how voltages are applied to individual sections. On the whole, the distribution of threshold voltages among individual memory cells falls within a certain range. FIG. 45 is a graph showing an example of the distribution of threshold voltages. In the graph, the abscissa indicates the non-volatile memory threshold voltage and the ordinate indicates the frequency. In an NOR-type memory cell array, a threshold voltage is controlled by a verification operation to have a rather high value, to eliminate read errors. Curve A-B of FIG. 45 illustrates a type of memory cell threshold voltage Vt distribution in the high threshold voltage condition (i.e., the "zero" state). Curve C-D of FIG. 45 illustrates a type of memory cell threshold voltage Vt distribution in the low threshold voltage condition (i.e., the "one" state). As already explained, in a reading operation, Vt, which is Vd-dependent, drops 0.2-0.4 V, resulting in the threshold voltage Vt distribution represented by Curve A'-B' and resulting in the threshold voltage Vt distribution represented by Curve C'-D'.
In the low threshold voltage condition, in order to guarantee a reading current (above 50 .mu.A) that starts flowing when Vccmin (the minimum of Vcc) is applied to the control gate of a memory cell, the memory cell must have a threshold voltage lower by about 1.0 V than Vccmin (see Point B' of FIG. 45), although such depends on the sensitivity of sense amplifier as well as on the memory cell mutual conductance. In an NOR-type memory cell array, in order to prevent a deselected memory cell from being misread, a sum of leakage currents of deselected memory cells coupled to a single bitline must be sufficiently lower than a reading current (above 50 .mu.A), and a memory cell in the low threshold voltage condition must have a threshold voltage above 0.5 V (see Point A'of FIG. 45).
If Vcc=3 V and Vccmin=2.7 V in the low threshold voltage condition, then a potential difference between Point A' and Point B of FIG. 45 must be below 1.2 V. If it is assumed that there is a threshold voltage drop of 0.2-0.4 V caused by Vd, then the width of the Curve A-B threshold voltage distribution must be below 1.0 V. These are the minimum requirements. In an actual memory, control margins for verification must be considered. Much more severe control on the distribution of threshold voltages Vt among individual memory cells is required, particularly in the low threshold voltage condition. The semiconductor industry is now trying to reduce the operating voltage of non-volatile semiconductor memories of large integration, to accomplish low power dissipation for solving heat problems. As Vcc (the reading voltage) becomes lower, it is necessary to control the threshold voltage distribution in a much more severe manner. For example, where Vcc is around 3.0 V, even a drop in the threshold voltage caused by Vd cannot be ignored. This results in increasing the probability of some memory cells being over-depleted.
A memory cell in the high threshold voltage condition must have an off state even when Vccmax (the maximum of Vcc) is applied thereto. A leakage current of that memory cell must be sufficiently lower than a reading current (above 50 .mu.A) but greater than Vccmax by about 0.5 V (see Point C' of FIG. 45). Apart from the above, there are no other rigorous limitations for a memory cell in the high threshold voltage condition. Greater threshold voltage provides better advantage when considering reading operations only, thereby providing a greater threshold voltage control margin.
When considering improvement in the writing operations and improvement in the number of times a write/erase operation is executed, a lower threshold voltage is preferable. However, when considering only reading operations, there is no need to lower a threshold voltage. The present invention pertains to reading operations, so it is assumed here that greater memory cell threshold voltage provides better advantage.
In a reading operation of extracting data out of the FIG. 42 non-volatile semiconductor memory, Vrm (the reading intermediate voltage) is applied to a selected bitline coupled to the drain of a target memory cell. This causes the threshold voltage of deselected memory cells coupled to that selected bitline to drop, thereby increasing the possibility that over-depletion occurs. Vrm is applied to the drains of MEMORY CELLS (T12) and (Tm2) as well as the sources thereof and their threshold voltages viewed from the floating gates increase by the substrate bias effect. However, if Vrm=1.0 V, then the substrate bias effect is only about 0.1 V and is cancelled by a drop in the threshold voltage caused by Vs. Accordingly the threshold voltage viewed from the control gate decreases more.
Accordingly, if MEMORY CELL (T22) in the low threshold voltage condition is read when MEMORY CELL (T12), which is a deselected memory cell and which is coupled to the selected BITLINE B2, is being over-depleted, then an electric current flows through BITLINE B2, and BITLINE B2 slightly drops in potential. At this point in time, a current flows from SOURCELINE S1 at Vrm into BITLINE B2 through MEMORY CELL (T12), whereupon the potential of BITLINE B2 is brought back to Vrm. If BITLINE B2 makes no electric potential transitions, this may cause SENSE AMPLIFIER SA2 coupled to BITLINE B2 to make an incorrect detection that MEMORY CELL (T22) has a high threshold voltage condition, although MEMORY CELL (T22) has in fact has a low threshold voltage condition. Reading errors may result. Additionally, improvements in the mutual conductance necessary for accomplishing high-speed reading operations become difficult to accomplish.

Non-volatile semiconductor memory having an array of non-volatile memory cells and method for driving the same

Matsushita Electric Industrial Co., Ltd.


An ozone storage/recovery method comprises a process for supplying an ozone-containing gas, generated by an ozone generator, to an ozone adsorbent tank filled with an ozone adsorbent contained at least one high-silica material selected from the group consisting of a high-silica pentasil zeolite, a dealumination faujasite and a mesoporous silicate, causing the adsorbent to adsorb ozone at a temperature of 0.degree. C. or below, and storing the ozone, and a process for desorbing the ozone adsorbed by the adsorbent in the ozone adsorbent tank and recovering the ozone from the adsorbent tank, whereby ozone can be supplied as required.

The present invention relates to an ozone storage/recovery method and a system therefor, capable of generating ozone with use of low-priced night electricity in the main, storing it, and discharging it as required.
Ozone is a clean oxidizing agent that is free from secondary environmental pollution and easy to handle, and therefore, is widely used in the fields of sterilization, cleaning, oxidative bleaching, etc.
In general, however, ozone is decomposed so easily that it cannot be stored in a gas cylinder or the like. Conventionally, therefore, ozone is used hot from a silent-discharge ozone generator, ozone generator with an ultraviolet lamp, water-electrolysis ozone generator, etc.
More specifically, the ozone generator is installed on the scene of use, and ozone is obtained by operating the generator only when it is needed. According to this method, however, it is hard for users to cope with load fluctuations.
Ozone is produced by using the silent-discharge ozone generator or water-electrolysis ozone generator in the main. However, the cost of power supply for operating these generators accounts for a high percentage in the unit cost of ozone manufacture. Since the demand for ozone is restricted by time and fluctuates, on the other hand, there has been a request for the development of an ozone storage device from which an ozone-containing gas with a given concentration can be taken out as required.
To attain this, the gas may possibly be liquefied when it is stored into an adsorbent so that it can be taken out when needed. However, these storage methods have the following problems.
In general, ozone easily decomposes and liquefying it requires great energy, so that the liquefying method is impractical.
Silica gel is a well-known ozone adsorbent. Its ozone adsorptivity is so low. Also, the silica gel strongly adsorbs water, if any, in advance of ozone. Thus, water is stored in silica gel, so that the ozone adsorption amount is lowered correspondingly. Further, a sizable amount of ozone decomposes while it is being adsorbed by silica gel, so that the ozone recovery is reduced considerably. For the long run, furthermore, silica gel may possibly be powdered due to the adsorption of water. In consequence, the ozone storage apparatus that uses silica gel lacks in utility.


A mixture in the form of slurry obtained from mixing a soybean protein, sugar and water is placed between a pair of electrodes. Then, an electroconductive heating process is applied to the mixture under an applied voltage between the electrodes for a predetermined time period, thereby obtaining the sheet-like biodegradable molded article. In this method, the biodegradable molded articles have a homogeneous structure and can be prepared in a short period of time without increasing the cost of equipment of creating unfavorable working conditions.

The present invention relates to a method for manufacturing biodegradable molded articles which can be decomposed by microbes, bacteria, etc., in the soil.
Generally, plastics are used as materials for molded articles such as containers, packaging materials, etc. However, plastics have the following disadvantages which give rise to problems in their waste treatment after use. In such molded articles the biodegradability thereof is extremely low and sometimes even a toxic gas is generated when incinerated. Thus, the difficulties in the waste disposal (burying, incinerating, compositing, etc.,) of the plastics create serious social problems.
In place of the described molded articles made from plastics, recently biodegradable molded articles have been used which can be decomposed by microbes, bacteria, etc., in the soil. As described, since the biodegradable molded articles can be easily decomposed in the soil, the problem associated with the waste disposal of the conventional molded articles made from plastics can be eliminated. Moreover, such biodegradable molded articles are safe to use as containers for foods.
Conventionally, the described biodegradable molded articles are manufactured by placing a biodegradable raw material in a mold heated beforehand to a predetermined temperature, and with an application of conventional thermal conductive heating. Alternatively, the biodegradable molded articles may be formed in any shapes as desired with an application of pressure by means of a high pressure press.
However, the above-noted conventional heating process creates the following problems.
1) From the heated mold, heat is dissipated not only to the materials placed in the mold, to be heated, but also into the area surrounding the mold, thereby presenting the problem of poor energy efficiency. PA1 2) Furthermore, because of this excess heat dissipation, the temperature of the area surrounding the manufacturing device increases, thereby resulting in unfavorable working conditions; and PA1 3) Since a long time is required for entirely transferring heat to the materials to be molded placed in the mold, it is difficult to complete the process in a short time, thereby resulting in low productivity. PA1 4) In order to complete the process in a short time, if the mold heated beforehand to a higher temperature is used, a great difference in temperature arises between the surface portion of the molded article and the inside portion of the molded article, thereby presenting the problem of non-homogeneous structure of the resulting molded article; and PA1 5) Since the mold must be heated to a predetermined temperature beforehand, excess energy as well as time is required. PA1 1) The device itself becomes larger in size, and the production facilities of large scale are required; PA1 2) Large noise and great vibrations occur in the manufacturing process, thereby presenting the problem of unfavorable working conditions; and PA1 3) Since the method requires the generation of high pressure, it is necessary to be cautious during the dangerous operation.
Meantime, the method to be preformed under an applied pressure by means of the high-pressure press creates the following problems.

Method for manufacturing biodegradable molded articles