An upright surface treating appliance includes a main body, a surface treating head connected to a yoke, and a stand. To provide a compact appliance the yoke and the stand are pivotable independently relative to the main body about a common pivot axis. This can also enable the yoke and the stand to be rotatably connected to the main body using one or more common connectors or bearings.

Surface treating appliances such as vacuum cleaners are well known. The majority of vacuum cleaners are either of the "upright" type or of the "cylinder" type (also referred to canister or barrel machines in some countries). An upright vacuum cleaner typically comprises a main body containing dirt and dust separating apparatus, a pair of wheels mounted on the main body for maneuvering the vacuum cleaner over a floor surface to be cleaned, and a cleaner head mounted on the main body. The cleaner head has a downwardly directed suction opening which faces the floor surface. The vacuum cleaner further comprises a motor-driven fan unit for drawing dirt-bearing air through the suction opening. The dirt-bearing air is conveyed to the separating apparatus so that dirt and dust can be separated from the air before the air is expelled to the atmosphere. The separating apparatus can take the form of a filter, a filter bag or, as is known, a cyclonic arrangement.
In use, a user reclines the main body of the vacuum cleaner towards the floor surface, and then sequentially pushes and pulls a handle which is attached to the main body of the cleaner to maneuver the vacuum cleaner over the floor surface. The dirt-bearing air flow drawn through the suction opening by the fan unit is conducted to the separating apparatus by a first air flow duct. When dirt and dust has been separated from the air flow, the air flow is conducted to a clean air outlet by a second air flow duct. One or more filters may be provided between the separating apparatus and the clean air outlet.
An example of an upright vacuum cleaner with improved maneuverability is shown in WO2009/030885. This upright vacuum cleaner comprises a barrel-shaped rolling assembly located at the lower end of the main body for engaging the floor surface to be cleaned, and which rolls relative to the main body for allowing the main body to be rolled over the floor surface using the handle. The rolling assembly is rotatably connected between a pair of ducts which each extend to one side of the main body. The main body of the vacuum cleaner houses separating apparatus for separating dirt from a dirt-bearing air flow drawn into the cleaner head. To increase the stability of the vacuum cleaner, and to make efficient use of the space within the rolling assembly, the motor-driven fan unit for drawing dirt-bearing air into the suction opening is located within the rolling assembly.
A yoke extending about the external periphery of the rolling assembly connects the cleaner head to the main body. The yoke is pivotably connected between the ducts to allow the main body to be reclined relative to the yoke between an upright position and a reclined position for maneuvering the vacuum cleaner over a floor surface. The pivot axis of the yoke is substantially co-linear with the rotational axis of the rolling assembly. The cleaner head is connected to the forward, central part of the yoke by a joint which permits the yoke to be rotated relative to the cleaner head. These connections allow the main body to be rotated about its longitudinal axis, in the manner of a corkscrew, while the cleaner head remains in contact with the floor surface. As a result the cleaner head may be pointed in a new direction as the main body is rotated about its longitudinal axis. As the main body is pushed over the floor surface using the handle, the vacuum cleaner moves forward along the direction in which the cleaner head is pointed, thereby allowing the vacuum cleaner to be smoothly and easily maneuvered over the floor surface.
The vacuum cleaner comprises a stand for supporting the main body in its upright position, and which is moveable relative to the main body to a retracted position to allow the vacuum cleaner to be maneuvered over the floor surface when in its reclined position. The stand comprises a pair of legs, each pivotably connected to a protrusion extending outwardly from a respective one of two ducts for conveying an air flow to and from the separating apparatus. The pivot axis of the stand is spaced from the pivot axis of the yoke so that when the main body is in an upright position the pivot axis of the stand is located above and rearwardly of the pivot axis of the yoke.


A catalytic solution for electroless deposition of metals, wherein at least a part of the acid, contained therein along with a soluble salt of a noble metal and a soluble salt of a metal of group IB or VIII of the periodic system, is an aliphatic sulphonic acid capable of forming stable and catalytically active complexes, such as methane-sulphonic acid.

The present invention relates to the formulation of aqueous catalytic solutions intended to activate non-conductive surfaces and to allow subsequent electroless deposition of metals, and more particularly the formulation of solutions containing one or more noble metals capable of rendering catalytically active a non-metallic surface with respect to the solutions for the electroless deposition of metals such as copper, nickel, cobalt, and alloys thereof.
Electroless metallization is mainly practised on surfaces of non-conductive materials, such as plastics, glass and ceramic, and has a particular importance in the industry of ornamental articles and, in the electronic industry, for the manufacturing of printed circuits with through holes.
A method of activation hitherto used comprises a step of catalyzation of the non-conductive surfaces, in which the surface to be metallized is made to adsorb active catalytic nuclei which are adapted to produce, when the piece is immersed in the subsequent suitable solution, the reaction of electroless deposition of a thin conductive metal layer suitable for allowing the successive step of electrolitic deposition.
All noble metals, both of the gold group and of the platinum group, can produce activating solutions; at the present time, however, the noble metal which is mostly used in the industry as a catalyst is palladium.
By utilizing this metal, the process of activation can be carried out according to two methods: according to the first method, the articles to be metallized, whose surface has been suitably cleaned and treated, are immersed first in a solution, acidic because of the presence of hydrochloric acid, containing stannous chloride, and then, after a thorough washing, in a solution, also acidic due to the presence of hydrochloric acid, containing palladium chloride.
This method gives rise to considerable disadvantages, both because of the poor stability of the solutions and of the poor adherence between the metal deposit and the support. This latter is an extremely serious disadvantage, in particular in the production of electric through-hole printed circuits, where often the plastic support is coated with a thin copper lamina on one or both sides. In fact, in the presence of copper surfaces, the acid solution containing the noble metal deposits, by chemical displacement, a non-adherent layer of noble metal, which needs to be mechanically removed from the surface of copper laminate, thus giving rise to a considerable increase in the cost of production and rendering practically impossible the practice of automated processes.
The second method, according to the known techniques, consists in catalyzing a non-conductive or partially conductive material (as in the case of the laminates for printed circuits) in a single-step catalytic solution resulting from the mixture and the respective products of reaction between the three components which so far have been deemed to be basic for obtaining catalytic solutions which are sufficiently active and stable even after many weeks, by avoiding the formation of precipitates or crystallization; such components are hydrochloric acid, stannous chloride and palladium chloride.
Although it is possible, theoretically, to use other soluble palladium and tin salts, preference has always been given to the use of halides, such as palladium chloride and stannous chloride, since the presence of chloride ions at high concentration has always been deemed to be irreplaceable and essential. Although also other halogenic acids may be used, hydrochloric acid is preferred.
It should also be noted that not only the presence of hydrochloric acid (HCl) at high molar concentration has always been considered as fundamental for attaining active catalysts stable during their preparation, but it has always been considered as indispensable for such acid to be present also, at a high concentration, in the solutions which are subsequently diluted, to allow their industrial utilization. In fact, a low concentration of mineral halogenic acid gives rise to instability of the system, with the consequent loss of catalytic activity and precipitation or crystallization of the components of the mixture.
The resulting need of operating, even in the diluted phase, with aqueous solutions containing 20-30% by volume of hydrochloric acid, has always been the cause of very serious disadvantages as regards both the plants and equipments and, especially, the health of the operators, owing to the continuous formation, in the working rooms, of fumes which are highly corrosive and detrimental to the respiratory organs. Even if, according to recent studies of some authors, the concentration of free hydrochloric acid may be considerably reduced, in the dilution step for industrial purposes, by utilizing other sources of chloride ions (Cl.sup.-), such as for example the chlorides of the alkali metals, nevertheless, high concentrations of the mineral halogenic acid are always been deemed indispensable in the preparation of the concentrated catalyst. Moreover said technique, which has been introduced recently, has some practical disadvantages, such as an extremely high saline concentration (near to saturation point) of the industrially used solutions with a low concentration of noble metal, a lower stability of the system, with the consequent tendency to the formation of precipitates, and the poor industrial practicability of the operation of dissolving large quantities of a solid salt. Examples of the proposals mentioned hereinabove are described in U.S. Pat. No. 3,874,882 and the article by Feldstein in the review "Plating", June 1973, 60-611 (1973).

Catalytic solution for the electroless deposition of metals


Two closed loops including a base bias controlling circuit are provided in a single ended push-pull amplifier. The base bias controlling circuit controls base bias voltages of respective transistors constituting the final stage of the push-pull operation so that a predetermined small amount of collector current flows via each of the collector-emitter paths of the transistors irrespective of the presence and absence of the input signal. Because of the predetermined collector currents, none of the transistors is held at cutoff in operation, thereby preventing the occurrence of the crossover distortion.

In a conventional Class B push-pull amplifier the output signal (the amplified signal) includes distortion components due to the highly curved arcuate portion in the V.sub.BE (voltage across the base and emitter of the output transistor) to I.sub.C (collector current of the transistor) characteristics. This distortion appears around the boundry between the positive and negative waves respectively amplified by first and second transistors which constitute the final stage of a push-pull arrangement, and is usually called crossover distortion. To prevent the occurrence of such distortion in operation of a push-pull amplifier, push-pull amplifiers are usually used in Class AB operation. In such a Class AB push-pull amplifier, a suitable amount of a bias voltage is applied to each of the transistors so as to shift the operating point of the transistors. However, it is impossible to perfectly eliminate the crossover distortion from the output signal of such a Class AB push-pull amplifier since the curve of the arcuate portion in the V.sub.BE to I.sub.C characteristics is not of the second order. Further, when such a Class AB push-pull amplifier is used as a SEPP (single ended push-pull) circuit, the crossover distortion becomes remarkably large due to the existence of a base bias stabilizing circuit which has a constant voltage characteristic. These drawbacks of the conventional push-pull circuit will be further discussed in detail with reference to the accompanying drawings.


A method of increasing the testability of sequential circuit designs with use of a clock transformation technique. Circuit states which are difficult to reach, but are nonetheless required to detect at least one fault of the circuit, are automatically identified. In accordance with one illustrative embodiment, estimations of joint line probabilities are compared with a preselected threshold value to identify hard-to-reach states. Then, commonly clocked flip-flops which must be simultaneously assigned values in order to reach the identified states are partitioned into independently clocked groups of flip-flops. In this manner, hard-to-reach circuit states are transformed into easy-to-reach states, which, in turn, results in transforming difficult-to-detect faults into easy-to-detect faults.

The problem of adequately testing digital logic circuits has grown substantially more complex over the years with the rapid increase in the complexity of the logic circuits being designed and fabricated. Most modem approaches to this problem involve the use of sequential test generation (STG) systems which are charged with the task of automatically generating a comprehensive test plan for a given sequential circuit design. Such an STG system is provided with a description of the circuit design, typically in terms of its constituent circuit elements (e.g., logic gates and flip-flops) and the interconnections among those elements and to the circuit's primary inputs and primary outputs. The STG system then automatically generates circuit stimuli which, when applied to the primary inputs of a fabricated instance of the given circuit design, will result in a response at the circuit's primary outputs which will identify (with a reasonable degree of certainty) whether the fabricated circuit is operating in accordance with the given circuit design.
Since the number of possible malfunctions which a fabricated circuit may theoretically exhibit is extremely large, STG systems typically perform their task (and measure the quality of their result) based on a fault "model" in which only a comparatively small number of possible malfunctions are considered. The most common such model, the "stuck-at" fault model, enumerates the set of malfunctions in which each circuit lead (i.e., each input to and each output from a circuit element) may be individually "stuck" at one of its possible values (e.g., logic 0 or logic 1). In this manner, the number of possible faults to be considered is limited to twice the number of circuit leads. The "stuck-at" fault model has become well accepted as providing a reasonable correspondence to the set of likely physical errors which typically result from the fabrication process.
Most STG systems select one of the modelled faults at a time, and attempt to generate tests (i.e., circuit stimuli) which will be able to "detect" that fault. That is, the system's goal is to find circuit stimuli which, when applied to the primary inputs of a "defective" circuit (i.e., one which has the given fault), will result in a response at the circuit's primary outputs which differs from that of a properly operational circuit. Usually, these circuit stimuli am generated as a result of an exhaustive search procedure involving substantial trial and error. For most typical circuit designs, however, quite a few of the faults may be extremely difficult to detect, making STG a very complex and time-consuming problem.
Much of the attention in the field of test generation, therefore, has focused on the problem of circuit "testability." In other words, STG can be made easier by modifying the circuit to be tested so as to improve its testability, without affecting the (normal) operation of the circuit. Specifically, the testability problem can be alleviated by applying certain Design for Testability (DFT) techniques in the circuit design. The two most popular DFT techniques are referred to as "full scan" and "partial scan" design. Using full scan, all the circuit flip-flops are replaced by scanable flip-flops which are connected so as to operate like a shift register during testing. In partial scan, only a subset of the flip-flops are transformed into scan flip-flops, reducing the fabricated circuit area overhead and possibly avoiding delay penalties by not scanning the flip-flops on the critical paths. But in many circuits, a large fraction of flip-flops need to be scanned to achieve a high fault coverage, and in synthesized circuits, a large percentage of paths are critical. Moreover, an expensive sequential test generator needs to be employed. Another drawback of scan techniques is the large test application time, resulting from the fact that every test vector to be applied needs to be scanned in through a series of flip-flops.
Recently, several DFT techniques based on controlling the clock have been proposed. For example, in V. D. Agrawal, S. C. Seth, and J. S. Deogun, "Design for Testability and Test Generation with Two Clocks", Proc. 4th Int'l. Symp. on VLSI Design, pp. 44-51, January 1991, the flip-flops are partitioned into two groups controlled by independent clocks during testing. That is, while the common flip-flop clock remains commonly operable during normal circuit operation, the flip-flop groups may be independently clocked when the circuit is in a test mode of operation. In K. L. Einspahr, S. C. Seth, and V. D. Agrawal, "Clock Partitioning for Testability", Proc. 3rd Great Lakes Symp. on VLSI, pp. 42-46, March 1993, the above concept is generalized to multiple groups. Specifically, the flip-flops are divided so that flip-flops in a loop (of length greater than one) are split between two or more groups. The main advantage of this method is that global feedback can be logically cut by keeping the corresponding clock inactive. However, this technique is inconsistent across circuits, because it targets only their cyclic structure. Moreover, it is not applicable to circuits having only self-loops. And in K. L. Einspahr, S. C. Seth, and V. D. Agrawal, "Improving Circuit Testability by Clock Control", Proc. 6th Great Lakes Symp. on VLSI, 1996, the same authors combine independent clock groups with partial scan to achieve full controllability for all flip-flops.
In S. H. Baeg and W. A. Rogers, "A New Design for Testability Method: Clock Line Control Design", Proc. Custom Integrated Circuits Conf., pp. 26.2.1-26.2.4, 1993, the flip-flops are also partitioned into different groups with independent clocks during testing--however, in this case, all flip-flops within a loop are kept in the same group. Thus, test generation is simplified because there are no loops among groups. Unfortunately, there are several drawbacks to this approach. On the one hand, if the circuit has many self-loops, the number of partitions increases and thus the area overhead and test application time increase proportionally. On the other hand, the presence of a loop covering all flip-flops results in no partitioning at all, making the technique inapplicable. Because of the partitioning objective, the designer cannot control the amount of DFT that can be applied. Also, a specialized test generator is necessary to take advantage of the partitioning.

Increasing testability by clock transformation


In a mask ROM, for each of the memory cell groups, a load circuit connected to data lines for the respective memory cell group, a sense amplifier, and a switching circuit are provided. The switching circuit selectively connects one of the data lines which are simultaneously selected, to the sense amplifier. A data line for a dummy memory cell is also connected to the sense amplifier.

1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a high-speed read mode.
2. Description of the Prior Art
As the processing speed of microprocessors have been remarkably improved in recent years, a semiconductor memory device is increasingly required to operate at a high speed. Accordingly, some improved semiconductor memory devices have been developed (for example, "A 20ns 1Mb CMOS Burst Mode EPROM" by B. ASHMORE et al., 1989 IEEE International Solid-State Circuit Conference). These devices perform the normal random access more rapidly, and have a high-speed read mode. In the high-speed read mode, the read operation can be performed more rapidly, though the access methods are limited somewhat.
FIG. 5 shows a prior art mask ROM (Read Only Memory) which has such a high-speed read mode. In the mask ROM, one column select line C.sub.i is designated by decoding high order bits of an input address. Then, a plurality of transistors Q.sub.i0 -Q.sub.in in a data line selection circuit 11 are turned on, so as to select a plurality of data lines D.sub.i0 -D.sub.in corresponding thereto. Any one row select line W.sub.j is designated by decoding low order bits except for the least significant bits of the input address. One column select line C.sub.i and one row select line W.sub.j are designated, so that a plurality of memory cells 12 are simultaneously selected.
The memory cells 12 comprise transistors Q.sub.ij0 -Q.sub.ijn, respectively. Each of these transistors Q.sub.ij0 -Q.sub.ijn is a MOSFET, and is formed in a semiconductor fabricating process in such a manner that the threshold voltage thereof is high when storing logical "1", and the threshold voltage becomes similar to that of the normal enhancement type when storing logical "0". Therefore, when one row select line W.sub.j is designated to become HIGH, the transistors Q.sub.ij0 -Q.sub.ijn of memory cells 12 corresponding to the column select line W.sub.j are normally off ("1") or normally on ("0"), in accordance with the logic state.
When the plurality of transistors Q.sub.i0 -Q.sub.in in the data line selection circuit 11 are turned on by the designation of the column select line C.sub.i, the transistors Q.sub.ij0 -Q.sub.ijn of memory cells 12 selected by the row select line W.sub.j are connected to sense amplifiers 13, respectively. As a result, the potentials of the data lines D.sub.i0 -D.sub. in selected by the column select line C.sub.i gradually change to HIGH ("1") or LOW ("0"), respectively, in accordance with the logic states of the connected transistors Q.sub.ij0 -Q.sub.ijn . These weak potentials are amplified by the respective sense amplifiers 13, in order to be valid.
In the normal random access, one of bank select lines P.sub.0 -P.sub.n is designated to be HIGH in accordance with the least significant bits of the input address. Thus, only one of transistors Q.sub.p0 -Q.sub.pn in a switching circuit 14 is turned on through which the output of the sense amplifier 13 connected to the corresponding one of data lines D.sub.i0 -D.sub.in is sent out to an output buffer 15. Therefore, in the normal random access, the logic state stored in one memory cell 12 designated by the input address can be read out via the output buffer 15.
When the logic state of memory cell 12 is read out through the corresponding one of the data lines D.sub.i0 -D.sub.in in this way, also the potentials at the remaining data lines D.sub.i0 -D.sub.in which are not selected by the switching circuit 14 have already become valid by the respective sense amplifiers 13. In this condition, when another one of the bank select lines P.sub.0 -P.sub.n is switched to be HIGH, the logic state of the corresponding memory cell 12 can be immediately read out without waiting for the potentials of the data lines D.sub.i0 -D.sub.in to be valid. Therefore, in the high-speed read mode, for example, the; least significant bits of the input address are automatically generated by an address counter, etc., so that the bank select lines P.sub.0 -P.sub.n are sequentially switched to be HIGH, whereby the transistors Q.sub.p0 -Q.sub.pn in the switching circuit 14 are sequentially turned on. Thus, the logic states of a plurality of memory cells 12 are sequentially read out through the plurality of data lines D.sub.i0 - D.sub.in simultaneously selected by one column select line C.sub.i.
As shown in FIG. 6, the input address becomes valid at time t.sub.10. In response to this, one column select line C.sub.i and one column select line W.sub.j are designated to be HIGH. Then, the data lines D.sub.i0 -D.sub.in are connected to the respective sense amplifiers 13, and the potentials of the data lines D.sub.i0 -D.sub.in change to be valid at time t.sub.11. Since the bank select line P.sub.0 has been designated to be HIGH at this time, the output of the sense amplifier 13 connected to the data line D.sub.i0 is sent out to the output buffer 15. Next, the bank select line P.sub.1 is switched to be HIGH at time t.sub.12, and the output of the sense amplifier 13 connected to the data line D.sub.i1 is sent out to the output buffer 15. Thereafter, the bank select lines P.sub.2 -P.sub.n are sequentially switched to be HIGH, so that the outputs of the sense amplifiers 13 connected to the corresponding data lines D.sub.i2 -D.sub.in are sent out to the output buffer 15.
As a result, the reading from the first memory cell 12 comprising the transistor Q.sub.ij0 requires the time period of t.sub.11 -t.sub.10 which continues until the potential of the data line D.sub.i0 becomes valid, as in the normal random access. On the contrary, since the potentials of the data lines D.sub.i1-D.sub.in simultaneously selected are already valid, the logic states of the corresponding memory cells 12 respectively comprising transistors Q.sub.ij1 -Q.sub.ijn can be immediately read out by switching the bank select lines P.sub.1 -P.sub.n in the succeeding readings.
However, in the above-mentioned prior art semiconductor memory device, it is required to provide the sense amplifiers 13 respectively on all data lines D.sub.i0 -D.sub.in which are simultaneously selected by one column select line C.sub.i, in order to set a high-speed read mode. Therefore, as the number of bits which can be simultaneously read out for a high speed reading increases, the number of sense amplifiers 13 must be increased. This causes the occupied area on a chip and the power consumption to increase.
Therefore, the prior art semiconductor memory device with a high-speed read mode has a problem in that if the number of bits which are simultaneously read out increases, the chip area and the power consumption increase.

Semiconductor memory device with shared sense amplifiers


An edible oil and fat composition comprises a phospholipid and a glyceride mixture comprising 5 to 100 percent by weight of a diglyceride. The phospholipid is a decomposition product of natural lecithin. It is stable and suitable for food and a cooking oil.

1. Field of the Invention
The present invention relates to edible oil/fat compositions (the in this description term "oil/fat composition(s)" shall mean composition(s) containing oil and/or fat, as principal component, and other desired components, and more particularly to edible oil/fat compositions comprising a diglyceride-containing glyceride mixture and a phospholipid having a specified composition, and thus having the advantages of good stability against oxidation and heat which may occur during cooking, for example, deep- and pan-frying, roasting, and baking, and of providing little greasy or oily distastefulness and no heavy feeling in the stomach when taken in a raw state, as such when contained in salad dressing, mayonnaise, or the like.
2. Description of the Prior Art
In these days there are used various edible oils most of which include soybean oil, rapeseed oil, corn oil, cotton seed oil, safflower oil, sunflower oil, and sesame oil either alone, respectively, or in combination, in the form of a mixture or composition. More recently, there is a tendency for consumers to like light or soft taste and flavor (referred to as taste/flavor hereinafter) rather than heavy or rich foods. Because it is difficult to mix with digestive juice compared with other essential nutrients, such as, proteins and carbohydrates, the fats and oils tend to stay for a longer time in the digestive tract, and this is considered a cause of physiological discomforts, such as, a heavy feeling in the stomach caused by taking largeamount greasy or oily food, but they are very important for making the taste and appearance better. An actual problem with oils and fats therefore resides in the incompatibility between their effect which may cause physiological discomforts, such as greasy distastefulness and a heavy, feeling in the stomach, and their effect of improving the taste/flavor and appearance.
In addition, edible oils and fats plays important role for cooking from the aspect of function, for example, in order to prevent food material from burning and sticking to cooking utensils, baking molds, top plates, for instance, during the baking cakes or breads, or frying in a pan.
On the other hand, there are a number of surface active agents used as mold-releasing agents for use in cooking, for example, baking sponge cakes or frying eggs, so as to prevent dough or eggs from burning and sticking and above all, lecithins are known as specifically effective for this purpose. Thus vegetable oils containing lecithin(s) added thereto are used as mold releasing oils. Lecithins also have a anti-spattering effect for cooking, and for this reason, lecithin-added oils are available on the market as "reduced-spattering oil for roasting on iron plate".
The term "lecithins" refers herein to phospholipid mixtures containing, as major gradients, phosphatidyl choline, phosphatidyl ethanolamine, and so on. Typical lecithins are obtained from soybean or egg yolk by extraction and purification.
Natural lecithins including lecithins from soybean and egg yolk are labile and, even if protected by oil or fat, turn black brown (browning phenomenon) as the result of heating. The decomposition and denaturation products emit a bad smell and an offensive odor, resulting in an impairment in the taste/flavor of food. For this reason, the uses and amounts of lecithins are limited at present. For the purpose of overcoming the difficulty with respect to lecithins, some approaches have been made, for example modification, such as hydroxylation, of lecithins (U.S. Pat. No. 3,661,605), and the use of specified HLB lecithins (U.S. Pat. No. 3,896,975). Japanese patent publication B 61-48520, Japanese patent publication A 54-126 206 and Japanese patent publication A 54-127 408 disclose the use of mixtures of lecithin with salts of organic acids and amino acids. The problem is not substantially solved.


A testing system for carrying out electrical testing of at least one first through via forms an insulated via structure extending only part way through a substrate of a first body of semiconductor material. The testing system has a first electrical test circuit integrated in the first body and electrically coupled to the insulated via structure. The first electrical test circuit enables detection of at least one electrical parameter of the insulated via structure.

As is known, a generic electronic integrated circuit is provided in a die (or, as used hereinafter, a chip) of semiconductor material, which is obtained, at the end of the manufacturing process, by dicing a wafer. The wafer generally comprises an active layer (for example, formed by a surface portion of a substrate), integrating one or more electronic components (either active or passive, for example transistors), or parts thereof, and one or more metallization and electrical-insulation layers extending on the active layer, to obtain the electronic components and their electrical interconnections.
The electrical connection between the electronic integrated circuit within the chip and an external electronic system is in general provided by conductive contact pads carried by an outer top surface of the chip, and electrical-connection wires that extend from the conductive pads towards similar connection elements of the external electronic system (this connection technique is generally known as "wire bonding" technique). In particular, the conductive pads form the terminations of electrical lines present in the chip and are designed for conveying information signals or power signals (among which electrical-supply signals for the electronic integrated circuit).
An alternative technique of electrical connection envisages use of conductive elements, projecting contact protuberances, or conductive balls or bumps, or conductive lands, directly connected to the conductive pads of the chip and set between the conductive pads themselves and similar connection elements of the external electronic system. In this case, the connection technique is usually defined as a "flip-chip technique", in so far as it envisages that the chip will be turned upside down in such a way that its outer top surface, which carries the conductive pads, is arranged facing the printed circuit board, or further electronic device, of the external electronic system.
In the field of electrical connections of electronic integrated circuits, moreover known is the use of the so-called through silicon vias (in what follows simply "through vias"), i.e., interconnections of conductive material that extend vertically through the chip of the electronic integrated circuit, enabling electrical connection of elements of the circuit, integrated at various levels of the structure of the chip, with an external surface thereof. The through vias are developed vertically through the chip and the corresponding substrate in such a way that, at the end of the manufacturing process, i.e., in their final form of use, they will be accessible from the outer surface of the chip designed for connection with the printed circuit board, or further electronic device, of the external electronic system, for example by being electrically contacted by the contact elements (bumps, balls, or lands) carried by said surface.
Generally, the through vias are electrically insulated from the substrate that they traverse in so far as they are insulated both laterally and underneath by an electrical-insulation region, for example constituted by dielectric material, in such a way as to avoid the presence of leakage currents towards the substrate itself.
FIG. 1 shows in a schematic and simplified way a generic electronic integrated circuit (IC) 1, provided in a wafer 2, comprising a substrate 3 of semiconductor material, integrated within which are, at least in part, electronic components 4, for example MOSFETs (as indicated schematically). In particular, the substrate 3 has a front surface 3a, in a position corresponding to which the electronic components 4 are provided, and a back surface 3b, opposite to the front surface 3a.
Arranged on the substrate 3, on one or more levels superimposed on one another, are electrical-insulation and metallization layers, schematically represented in FIG. 1 by an insulation layer 5, arranged on the front surface 3a of the substrate 3, and at least one metallization layer 6, arranged on the insulation layer 5. In a known way, appropriate structures, either conductive or insulating, of the electronic components 4 may moreover extend on the substrate 3 (for example, to obtain a gate oxide and a gate conductive structure of a MOSFET). In addition, the insulation and metallization layers 5, 6 provide the electrical connections between the electronic components 4, and the electrical connections towards the outside of the electronic integrated circuit 1.
Moreover, a passivation layer 7, of insulating material, extends on the metallization layer 6; contact pads 8 are opened in the passivation layer 7, are electrically connected to the metallization layer 6 and are designed to be electrically contacted from the outside. The outer surface of the passivation layer, designated by 7a, is a front outer face of the wafer 2.
In particular, in the substrate 3 the electronic components 4 are provided through appropriate processes designated as a whole by FEOL (Front End of Line), whereas the remaining electrical-insulation layers 5, metallization layers 6 that provide the electrical connections towards the outside, and the passivation layer 7 are designated as a whole by BEOL (Back End of Line).
Moreover one or more through vias are formed inside the wafer 2, designated as a whole by 10, including conductive interconnections that extend vertically through the substrate 3 and possibly traverse one or more of the electrical-insulation and metallization layers 5, 6, so as to define electrical connections between the electronic components 4, the metallization layers 6, or the contact pads 8, towards the back of the substrate 3. In particular, by way of example, FIG. 1 shows a first through via 10′, which extends from the front surface 3a towards the back of the substrate 3, being designed to contact a region of an electronic component 4 (for example, a region of a MOSFET); a second through via 10″, which extends from a metallization layer 6 towards the back of the substrate 3; and a third through via 10″′, which extends from the outer surface 7a of the passivation layer 7 towards the back of the substrate 3, being designed to contact a contact pad 8.
It is noted that, after their formation, the through vias 10 are generally insulated and "embedded" within the substrate 3 of the wafer 2, being separated from the back surface 3b of the substrate 3 by a portion of material having a given thickness.
For example, the through vias 10 may be obtained as described in United States Patent Applicant Publication No. 2005/0101054, or in "Wafer Level 3-D ICs Process Technology", of Chuan Seng Tan, Ronald J. Gutmann and L. Rafael Reif, pp. 85-95, Springer-Verlag New York Inc., which are incorporated by reference.
FIG. 2 shows the electronic integrated circuit 1 at the end of the manufacturing process: a final step of thinning the back of the substrate 3 (with known techniques of lapping, or "back grinding") exposes a portion of the back end of the through vias 10, which may in this way be contacted electrically from outside. Following upon the thinning process, the substrate 3 has a reduced thickness, for example even of less than 50 μm.
In one of the possible assembly processes, the wafer 2 is next diced so as to define a plurality of chips, each of which contains a respective electronic integrated circuit.
At the end of the manufacturing process, the through vias 10 thus traverse the entire substrate 3, providing a direct electrical connection from the electronic components 4 to the metallization layers 6 within the chip, or to the contact pads 8 from the back surface 3b of the substrate 3 (which in this case forms an outer back face of the chip), or more in general one or more electrical connections from the so-called "top" (i.e., the front part) of the chip, to the so-called "bottom" (i.e., the back part) of the chip.
The use of the through vias 10 may particularly advantageous for providing three-dimensional packaging structures for the electronic integrated circuits (the so-called "3D-packaging techniques"), which have been recently proposed in the field of semiconductors in general and of microelectromechanical systems (MEMS) in particular.
It is noted that, in a way that is usual in this sector of the art, the term "package" is here used for designating, as a whole, the casing, or covering structure, which surrounds, totally or partially, the chip or chips of semiconductor material of the electronic integrated circuit, enabling electrical connection thereof with the outside (for example, connection to a printed circuit of a corresponding external electronic system).
In a known way, 3D-packaging techniques envisage alternatively: vertical stacking of two or more packages, each enclosing one or more electronic integrated circuits (the so-called "package-level 3D packaging"); vertical stacking of two or more chips or dice (the so-called "chip-level 3D packaging"); and vertical stacking of two or more wafers (the so-called "wafer-level 3D packaging"). In particular, in the latter case, the wafers are stacked on one another and then diced before they are enclosed within a corresponding package. Clearly, to be able to provide the electrical connections between the electronic integrated circuits in the various wafers appropriately arranged through vias may be required.
The use of three-dimensional structures enables an increase in the density of the interconnections, at the same time reducing the length thereof, thus reducing also the parasitic effects; it may thus be possible to increase their performances. The use of through vias may thus be advantageous in a wide range of applications, in particular for reducing the length of the connections between the various chips, dice, or wafers.
The above use entails, however, various problems of production, linked, for example, to the etching processes required for forming vias/trenches having a small diameter (even of less than approximately 10 μm) and a large depth within the chip, or to the alignment processes between the wafers, chips, or dice. Also in the light of the critical aspects of the production process, and given the nature of electrical interconnection performed by the through vias, it would be advantageous to be able to verify proper operation thereof (for example before manufacturing the integrated circuits and in particular before completing dicing of the wafer of semiconductor material), and in particular to verify the resistance of the path offered to the electric current circulating through the through vias and moreover verify the presence of possible leakages and parasitic phenomena, for example, in regard to the substrate.
In this regard, so-called "automatic test equipment" (ATE) are known, which perform an automatic procedure of testing and electrical sorting the various chips within a wafer of semiconductor material (before the corresponding dicing) so as to select the chips operating properly for their subsequent packaging. This operation is known as "electrical wafer sort" (EWS) or "wafer sort" (WS) and envisages execution of appropriate electrical tests on the electronic integrated circuits in the various chips.
As shown schematically in FIG. 3, a testing apparatus, designated as a whole by 15, designed to test the electrical characteristics of a wafer, once again designated by the reference number 2, as in FIGS. 1 and 2, comprises a chuck 16 (incorporated in an electromechanical apparatus referred to as "prober", not illustrated herein), on which the wafer 2 to be tested is arranged, and a probe head 17, which is provided with a plurality of probes 18 (in a high number, ranging from several hundreds to several thousands) and can be actuated so as to approach the front face 7a of the wafer 2, thereby the probes 18 electrically contact the contact pads (not illustrated herein) of the wafer 2 in an appropriate way. To this end, the probe head 17 is coupled to a printed-circuit board 19, containing appropriate electronic circuits interconnected to an ATE (not illustrated herein), and to an electromechanical actuation system (not illustrated herein either). In use, the probe head 17, via the probes 18, may be electrically coupled with the electronic integrated circuits contained in the wafer 2 so as to measure one or more electrical parameters thereof. The ensemble of the probe head 17, of the probes 18, and of the printed-circuit board 19 constitutes a so-called "probe card".
The testing apparatus 15 may, however, be inadequate for testing the through vias 10 at the level of the wafer of semiconductor material. In fact, the through vias 10 have terminations that are electrically insulated from, and embedded within, the substrate 3, being thus inaccessible for the probe head 17 and the corresponding probes 18. An altogether similar consideration applies to testing of through vias 10 in a stacked structure of a three-dimensional type.
In addition, the use of the probes may prove incompatible for testing through vias (also when the test is carried out after thinning the substrate, i.e., with a back portion of the through vias accessible from the back of the substrate itself). In fact, the tendency is known to progressively reduce the dimensions of the through vias, which can have dimensions of even less than approximately 10 μm; this reduction of the dimensions may render it very difficult to obtain a reliable electrical contact between the tip of the probe and the through via, since the typical size of the surface of the tip of the probe is 10 μm-15 μm greater than a corresponding dimension of the through via (also on the basis of the requirements of the test current that is to flow through the contact).
The direct contact between the probes 18 and the through vias 10 may thus damage the surface of the through vias 10, with consequent problems of loss of electrical efficiency of the interconnections in the three-dimensional stacked structures. The same problem may also arise when a conductive element (for example a bump) is formed on the through vias to obtain an electrical connection between two chips in the three-dimensional structure. In fact, in any case, the reduction of the area of contact between the probe 18 and the through vias 10 (also due to the morphology of the two surfaces in contact and to the presence on these surfaces of other non-conductive materials, such as, for example, contaminating particles, etc.) may cause an increase of the electrical resistance of the contact, overheating the contact area and locally raising the temperature even by some hundreds of degrees centigrade, upon the passage of the electrical test current.
The circumstances listed hereinafter may render still more problematical the electrical contact between the probes and the through vias: certain testing equipment is provided with probes that run on the surface of the contact pads for improving the performance of the electrical contact; the probes are not always well aligned to one another and do not maintain their centering over time; moreover, there may occur imprecise alignment between the probes and the wafer, after the operations of positioning of the chuck that carries the wafer on which the test operations are to be carried out.
In addition, when the electronic integrated circuit to be tested has a high density of through vias, it may also happen that the distance between the through vias is smaller than the minimum distance possible between two probes (due to the technology of production, for example, 50 μm), thus rendering impractical or impossible the provision of a system of a traditional type for testing the through vias.
It follows that there does not exist up to now a solution that enables electrical testing of through vias, in particular in three-dimensional structures that envisage vertical stacking of two or more wafers or chips, and in particular there does not so far exist a testing technology that is scalable with the reduction of the dimensions of the through vias, i.e., such that it is possible to reduce the dimensions of the probes by the same factor with which the dimensions of the through vias are reduced.

System and method for electrical testing of through silicon vias (TSVs)


A tree stump coring apparatus and method of coring a tree stump using the same is provided. The tree stump coring apparatus includes an elongated cylindrical cutting blade of a hollow tubular body rotatable about a vertical axis with cutting blades on an open lower end of the cutting blade for mounting on a vehicle such as a skid steer loader which provides a means to rotate the cutting blade and a means to move the cutting blade in a generally vertical direction downwardly to core a tree stump and upwardly to remove the tree stump core from the ground.

Once a tree is cut down a problem resides in removal of the tree stump. There are several methods available for removing tree stumps. Mechanical removal tends to be the most efficient and quickest method. Mechanical removal includes grinding the tree stump away with tree stump grinding machines having a cutting head comprising a large rotating disc equipped with cutting teeth. An operator moves the cutting head over the stump grinding it away little-by-little. There are horizontal axis stump grinders where the cutter rotates about a horizontal axis of rotation, and vertical axis stump grinders where the cutter rotates about a vertical axis of rotation. Stump grinders have a disadvantage of being a relatively dangerous piece of equipment to operate and exposing the operator to the possibility of great injury. Additionally, stump grinders have a tendency to throw debris which may include stones out of the hole in the ground which constitutes a safety problem. Horizontal axis stump grinders further have a disadvantage of positioning the drive shaft and bearings below ground level while being moved through the stump and exposing them to dirt and rocks. Additionally, relatively large discs are required in order to grind deep enough to remove the roots of medium and large stumps. Large diameter disc cutters require more power which cannot be supplied by small horsepower vehicles. Vertical axis stump grinders have solved several of the problems of horizontal axis cutters, but disadvantages still remain, including the throwing of debris.
An alternative, and often a less than desirable method includes decomposition of the tree stump. If left alone after tree removal, the stump will gradually decay in the ground, from natural fungus and bacteria. This process can take from one to several years, depending on the size of the stump, the species of tree, and the soil conditions. Commercial chemical products are available that are marketed as increasing the decomposition rate of tree stumps. However, few, if any of these products decompose the stump much faster than natural decay processes. The decomposition method has the obvious disadvantage in the time required for the tree stump to decay.
Another alternative method of tree stump removal is digging the tree stump out. Large equipment such as a backhoe can accomplish the job efficiently, for smaller stumps. However, hand digging the stump can be very difficult, even for the stumps of small trees. Digging is limited only to smaller tree stumps, and is labor intensive and time consuming.
Yet another alternative method of tree stump removal is pulling the tree stump from the ground. Pulling is undesirable as it is limited to very small tree stumps, requires attaching the tree stump to a vehicle by rope or chain, and generally results in tearing and lifting the root system upward along with the stump. An uplifted root system can damage adjacent structures and vegetation, and result in additional repair work or work to remove the root system.


A locator device for generating buried asset data is disclosed. The device includes an elongated housing accommodating at least two sensors, wherein each sensor is for reading analog radio frequency (RF) signals from a buried asset, wherein the at least two sensors having a known distance between them, and wherein the housing may be oriented either horizontally or vertically, a sensing device for sensing an orientation of the elongated housing, and a processor for reading RF signals from the buried asset, applying an orientation filtering process to the signals based on the orientation, converting the signals into buried asset data having depth data, position data and electrical current data for a buried asset, and, a display unit for displaying the buried asset data in a graphical user interface, wherein the buried asset data corresponds to the RF signals that were read.

Utility lines, such as lines for telephones, electricity distribution, natural gas, cable television, fiber optics, Internet, traffic lights, street lights, storm drains, water mains, and wastewater pipes, are often located underground. Utility lines are referred to as "buried assets" herein. Consequently, before excavation occurs in an area, especially an urban area, an excavator is typically required to clear excavation activities with the proper authorities. The clearance procedure usually includes contacting a central authority that in turn notifies the appropriate utility companies. Subsequently, each utility company must perform a buried asset detection procedure, which includes visiting the excavation site, detecting the relevant buried assets and physically marking the position orientation of the buried asset using temporary paint or flags. Upon completion of this procedure by the appropriate utility companies, excavation can occur with the security that buried assets will not be damaged.
Conventional locators (commonly known as "pipe or cable locator receivers") are portable, self-contained electronic devices carried by a field operator who walks over the target pipe or cable and receives an electromagnetic or acoustic signal from the buried conductor. A transmitter in the locator applies a signal to the buried asset. The locator includes detection antenna arrays, signal processing hardware and software, a display screen and power supply management circuits. The locator's display screen displays position, orientation and depth information of the buried asset to the operator.
Some prior art locators comprise portable upright or vertical profiles that use a receiver with at least two vertically separated antennas or sensors. This type of locator requires the operator to manually move the device across the above surface target area, searching for electromagnetic fields radiating from the underground conductor or buried asset. The operator then manually narrows the search area by moving the locator device through space so it is eventually positioned directly above the underground asset. Typically a peak or null response is presented to operator in visual or audible form. The vertical positioning of the sensors permit a depth calculation from the device to the target conductor. Once the target has been located, the operator can mark the position of the buried asset with a flag or paint marking device. Similarly, some prior art locators comprise portable horizontal bar profiles containing multiple separated antennas or sensors on a horizontal axis. As opposed to locators having vertically separated antennas or sensors, the horizontal type of locator is placed in a fixed stationary position above surface in an area believed to contain the buried asset. The horizontal bar type locator analyzes the signals directly under the device and remains in a static position while doing so. Complex vector algorithms predict the position of the buried asset relative to the horizontal bar's position and the user is presented with this data on a visual display. If no target is detected the operator is advised to reposition the device.
Both of these prior art devices have their advantages and disadvantages (speed, accuracy, operator skill requirements, cost, type of target conductor) and a variety of problems can result if both are not used to locate and accurately find the depth and position of a buried asset. Often two separate locaters—one horizontally oriented and one vertically oriented—are needed. Carrying around, maintaining and handling two, separate locator devices can be cumbersome and physically exhausting for a locate technician. Further, requiring two separate locator devices increases the complexity of the locating process, increases the associated costs (i.e., two locators must be purchased), and reduces reliability, since the malfunction of either locator leads to time lost. Further, it can be cost prohibitive for organizations that require large numbers of locators for their workforce to purchase the number of locators they require.
Therefore, a need exists for improvements over the prior art, and more particularly for methods and systems that increase the usability, reduce the complexity, and lower the costs of devices and systems that detect buried assets.

Buried asset locator device that takes orientation of device into account during sensing process


According to various embodiments, an electronic device and a method of providing information about an access point (AP) may include: confirming one or more access points (APs) outside an electronic device; starting a connection to the selected AP of the one or more APs through a communication circuit; acquiring AP information corresponding to the selected AP from the selected AP during the connection to the selected AP; determining characteristics of the selected AP based on at least the AP information; and displaying a first notification in association with the selected AP based on the characteristics including a first group and a second notification in association with the selected AP based on the characteristics including a second group through the display.

Recently, with the advent of a smart phone, the use range of wireless communication service has been gradually expanded to video communication, provision of various multimedia through the Internet connection, etc., besides voice communication. Accordingly, a demand for various applications besides ultrahigh speed data transmission has greatly increased and the number of user accessing WiFi networks (WiFi network or wireless local area network (WLAN)), which provides an ultrahigh speed wireless access and is more cost-effective and simpler, to use the Internet has rapidly increased. The WiFi network is a local area network that uses repeaters, that is, access points (AP) to access the Internet within a predetermined range where the APs are installed.
Recently, as the WiFi network is widely used for various electronic devices including a smart phone, the case in which a number of users within a limited area simultaneously accesses one AP has increased. Since the APs does not have security cryptogram at an early stage of production, a security issue of the electronic devices connected to the APs may arise
For security setting of the AP, a user needs to access a web page that may set the security of the AP. For this purpose, the user needs to directly confirm a default gateway address value of the corresponding AP and input the confirmed default gateway address value to an address window of browser.

Electronic device and method of providing information about the access point (AP)


A system for injecting chemicals into a geothermal well near the bottom of the well bore for optimum efficiency. The system includes a spool assembly with a master valve for control of the geothermal flow and a secondary outlet formed of an angle to permit the chemical injection chamber to be lowered into the well. The secondary outlet is attached to the main spool in such a way as to allow internal thermal expansion while permitting the chemical injection chamber to be fed by capillary tube to the bottom of the well bore. The chemical injection device includes an injection chamber through which the chemical is disbursed and a segmented sinker bar to provide the necessary weight to carry the chamber to the bottom of the well against the geothermal well flow. An annular seal assembly in the spool prevents leaking by being pressure energized by the geothermal production fluid. As a result, production can continue during the chemical injection process.

I. Field of the Invention
This invention relates to a system for injecting chemicals into a geothermal well and, in particular, to a spool and injection assembly which allows safe insertion of the injection assembly and internal casing expansion during insertion of the injection assembly through a secondary outlet independent of the master valve.
II. Description of the Prior Art
Geothermal wells produce steam from heated subsurface areas. The wells are drilled and completed utilizing oilwell drilling equipment although techniques differ for such wells including the use of larger well bores, well casings and surface wellhead valves and fittings. Steam from the geothermal wells flow from near the bottom of the well bore through the casing and surface valves in large enough volumes to power turbines for producing electricity. The distinctiveness of producing steam from geothermal wells brings operating complications specific to the geothermal industry that include corrosion problems and the build-up of scale on metal casings and surface valves. This corrosion and scaling faced by the geothermal industry limits the useful life and production capabilities of the geothermal well. In order to control this corrosion, various chemicals have been developed although they must be deployed near the bottom of the well.
The prior known method for entering the well with a chemical injection device capable of injecting chemicals near the bottom of the well involved opening of the master valve and inserting tubing from the surface to the bottom of the well. However, the open condition of the master valve for chemical injection creates a potentially dangerous situation since the master valve cannot be closed without destruction of the injecting tubing or damage to the master valve.

Geothermal well chemical injection system


A broadband linearizer for use with a power amplifier. The broadband linearizer includes a preamplifier, a postamplifier and a broadband linearizer bridge coupled between the preamplifier and postamplifier. The linearizer bridge comprises a power divider for coupling power to linear and nonlinear arms, and a power combiner for combining outputs of the linear and nonlinear arms. The linear arm includes a first equalizer and a delay line, and the nonlinear arm includes a distortion generator and an attenuator. A second equalizer is coupled between the power combiner and the postamplifier. A control circuit controls settings of the preamplifier, the broadband linearizer bridge, and the postamplifier. The control circuit outputs voltage bias and constant current signals to control operation of the broadband linearizer. The broadband linearizer provides for independent, flexible gain and phase control that can mate with different kinds of power amplifiers, such as travelling wave tube amplifiers and solid state power amplifiers having various gain and phase performance.

The present invention relates generally to power amplifiers, and more particularly, to a miniature broadband linearizer for use with power amplifiers.
Heretofore, Lockheed Martin Corporation has developed a broadband linearizer that is implemented using passive FET technology. This broadband linearizer is discussed in a paper entitled "MMIC Linearizers for C and Ku-Band Satellite Applications", by R. Dorval, published in 1998 IEEE MTT-S International Microwave Symposium Workshop".
Nippon Electric Company (NEC) manufactures linearizers for use with power amplifiers. Such linearizers are disclosed in a report entitled "INTELSAT-VII Linearizer for Ku-Band TWTA", and a "Linearizer for Ku-Band TWTA Performance Specification" (Specification No. E021307). The NEC linearizers use commandable switched frequency bands to cover a wide bandwidth. However, the basic design for each band of the NEC linearizers are narrow band. Also, the NEC linearizers use FET amplifiers as nonlinear elements.
Alcatel has developed a linearized channel amplifier that uses a MMIC amplifier as a nonlinear element.
AEG (Daimler-Benz AG) has developed a linearizer preamplifier that includes a nonlinear Schottky diode circuit, a phase shifter and three MMIC amplifiers. This preamplifier is disclosed in a paper entitled "Pseudomorphic Ku-Band GaAs HFET Linearizer Preamplifier Front End for Satellite TWT-Amplifiers", published in the 1995 IEEE GaAs IC Symposium.
In general, however, these conventional linearizers also do not provide for a simple, compact low cost design that does not involve complex commandable switched band selection operation.
Accordingly, it would be advantageous to have a broadband linearizer that may be used with a power amplifier to improve the linearity and efficiency performance of the power amplifier across a wide frequency bandwidth.


A process for manufacturing semiconductor components, especially diodes. The process entails first bonding two semiconductor wafers of different conducting types (p and n), according to a silicon-fusion bonding process (SFB), thereby forming a bonded wafer assembly with a p-n junction. The bonded wafers are then partitioned into a plurality of semiconductor elements by the cutting of grooves into the bonded wafers to a depth which extends at least to the p-n junction. Each of the plurality of semiconductor elements thus formed has an individual p-n junction with sides exposed by the grooves. The sides of the semiconductor elements are then subjected to etching and passivation. The upper and lower surfaces of the bonded wafer assembly are then metal-coated. Finally, the semiconductor elements are separated from each other by a sawing operation.

A process is known from German Patent Application No. 38 15 615 for producing a high-blocking power diode, that results from doping a semiconductor material by diffusion. Boron and phosphorous are applied to the two main surfaces of a semiconductor body, and then in a first diffusion phase these two doping substances are brought to a particular diffusion depth-by warming the semiconductor body, to which they were applied, to a certain temperature. Also known is the use of doping foils for applying doping substances, which are placed on the semiconductor body. Suitable conditions for the first diffusion step are a diffusion temperature of, for example, 1200.degree. C. and a diffusion time of 30 hours in an oxidizing atmosphere. This diffusion process is also connected with a "getter" process, which provides for a sufficiently high charge-carrying lifetime. Next, thin metal layers are applied to the two exposed surfaces of the semiconductor body, where the kind of metal layer is determined by the field of use. For solder processes, for example, the layer sequence Al/Ni (aluminum/nickel) or Cr/Ni/Ag (chromium/nickel/silver) is suitable. Next, the semiconductor body is divided into chips by a sawing or other separation process. After the division, the individual chips are soldered between two contacts, that are composed advantageously of copper. After this soldering process, both surfaces of the chip ends are completely covered by solder and the contacts. The pn-junction that has been exposed on the sides and damaged by the sawing process is then etched with moist chemicals in a hot potash lye or in plasma, in order to eliminate the damages. Because of the covering of the chip-end surfaces by solder and the contacts, they are well protected against removal during the etching process. Then the prepared power diode can be covered with plastic, for example, so that it is protected passively and against environmental influences. Only when the power diodes are finally assembled and packaged can they be measured electrically and thus tested.
For the production of Zener (breakdown) diodes, the following process is known: A process used for the production of mesa diodes is used with epitaxy and photolithography steps. In addition, V-shaped grooves are etched, where the entire production takes place in clean-room conditions. Maintaining clean-room conditions leads to relatively high costs. For production of Schottky diodes, a photolithography step is likewise used and clean-room conditions are necessary. Also critical for series production is the contact between metal and silicon (Si), since this determines a well-defined state for the Si surface. Schottky diodes exhibit relatively high blocking-state currents and are not pulse-resistant.
Finally, it is also known that epitaxy layers and photolithography steps under clean-room conditions are necessary in the production of plane diodes.
In known processes for producing high-blocking diodes, the desired doping is first produced in a diffusion process, and then both wafer sides are metal-coated with, for example, Ni/Au (nickel/gold). Then both sides are coated with paint for protection of the metal coating against the following production steps. Next a grid is sawed, where the separation cuts are maintained by a specially V-shaped saw. Then an acid etching takes place within the grooves. Then, for passivation, the grooves are filled with polyimide paint by means of a doctor blade. Then the paint is stripped from the metal coating by a plasma stripper. Finally, separation into individual chips takes place by sawing.

Process for manufacturing semiconductor components


An automated system coordinates, controls and polices installation of customer premise equipment (CPE) for telecommunications services and provides continuing service assurance. The system verifies equipment availability on service request, schedules a qualified technician to install the CPE, and assigns distribution equipment resources to the CPE. The system notifies the technician of the installation date. The equipment resources are auto-assigned to the CPE to facilitate installation procedures. The system also auto-detects installation of the CPE and auto-enables service when the CPE is installed. Customer record creation and maintenance is automatic, and installation or operation of unauthorized equipment is inhibited. Post-installation monitoring and automatic scheduling of repair for system or equipment faults ensures continuing service assurance. The advantage is reduced service delivery time, reduced operations costs and increased customer satisfaction.

Telephone companies around the world are realizing that it is possible to include existing twisted-pair loops in their next generation broadband access networks. Hybrid Fiber Coaxial (HFC), which is well suited to analog and digital broadcast, is proving to be less than ideal for carrying voice telephony, interactive video and high-speed data communications at the same time. Fiber To The Home (FTTH) is still prohibitively expensive in a marketplace that is driven by competition rather than cost. An alternative, which is now commercially practical, is a combination of fiber cables feeding neighborhood Optical Network Units (ONUs) with final leg connections through existing twisted copper pairs used for providing telephone service. This network topology is commonly referred to as Fiber to the Neighborhood (FTTN). It uses fiber optic cable to deliver broadband services to distribution points in high-density neighborhoods or Multiple Dwelling Units (MDU), such as apartment buildings, condominiums and the like.
One of the enabling technologies for FTTN is Very high rate Digital Subscriber Line (VDSL). VDSL transmits high-speed data over short reaches of twisted copper pair telephone loops at downstream rates of up to 53 megabits per second over short loops, with slower speeds over longer loops. Upstream rates are slower but up to 19 megabits per second on short loops can be achieved. The data channels on VDSL are separated in frequency from bands used for Plain Old Telephone Services (POTS) and Integrated Services Digital Network (ISDN). This enables service providers to overlay VDSL on existing telephone services. Consequently, converged service offerings that permit television, high-speed Internet, and telephone services to be offered concurrently over the same twisted pair are now available. As is well understood, the delivery of such services requires complex interworking of different service provider networks. Converged services are therefore complicated to provision and provisioning can contribute significantly to start-up costs.
The provisioning of broadband services to customers has long been recognized as an area in which competitive advantage can be gained, provided the process can be at least partially automated. For example, U.S. Pat. No. 5,903,372, which issued on May 11, 1999 to Czerwiec, describes an Optical Network Unit (ONU) for installation in the neighborhood of primary and secondary video service subscribers. The ONU includes a switch matrix card for installation in the ONU with connections to POTS cards for a number of primary subscribers over a corresponding number of twisted pair copper loops. Twisted pair copper loops are also adapted to permit switch connection to switchable video cards. The switchable video cards permit video services to be enabled and disabled using a remote control work station without the dispatch of a service technician. While this invention has merit, it does not address service provisioning and service assurance.
The problems associated with the provisioning of telecommunications services remain, as do the problems associated with telecommunications service assurance. There therefore exists a need for a method and system that facilitates telecommunications service provisioning and service assurance in order to reduce start-up costs and ensure customer satisfaction by providing telecommunications services that are rapidly and reliably enabled on a promised installation date, and consistently and efficiently maintained on a continuing basis.

This patent is subject to a terminal disclaimer.

Method and system for facilitating telecommunications service provisioning and service assurance


Disclosed is a guided orthopedic bone reamer (10a) for cutting a profile relief shape (21a) into a joint bone (20). The reamer (10a) has a cutting head (30a) and an axial guide assembly (70). The cutting head (30a) has a profile cutting form (24a) with a rim (34) and an apex (38a). The apex (38a) connects to the cutting form (24a) by a set of struts (94). An axial guide assembly (70) has one end (44a) fixed to the apex (38a) and at the other end has a bayonet mechanism (76) connectable to a drive handle. Rim cutting teeth (36a) are set into the rim (34) to cut a cylindrical profile (21a), and bevel cutting teeth (96) integral to the struts (94) cut a bevel (25) onto the cylindrical form (21a) cut into the bone (20). A guide pin bore (12a) passes through the apex (38a) and the guide assembly (70) concentric with the axis of rotation (18) to receive a guide pin (14) to guide the reamer (10a) in cutting alignment relative to the joint bone (20) to be cut.

The invention relates to a bone shaping system made up of an instrument holder and a surgical instrument, i.e., a surgical tool head, for attachment to the holder. The holder includes a shank equipped with a head designed to receive an instrument, and an annular locking component mounted so as to slide about the shank, under the head, equipped with locking means which cooperate with the head so as to lock the instrument on the head, and pushed against the head by a helical spring. The present surgical tool head is disposed to mate with and attach to the head of the tool holder. An example of a tool holder suitable for practice with the present invention is disclosed in U.S. Patent Application Publication No. 2005/0251145, the content of which is incorporated herein by reference.
One such system is described in European Patent 0782840, the content of which is incorporated herein by reference thereto, and includes a shaft (10), equipped at one end with a cutting head holder (12) which has a bayonet joint and lock. A hemispherical or conical rotary cutting head (1) has inner radial rods (4) to engage with the bayonet joint. The cutting head contains an axial guide tube (5) between the inner ends of the radial rods and a central aperture (3) to receive a twist drill (9) which makes a hole in the middle of the recess formed by the cutting head. The lower end of the guide tube has one or more notches to receive corresponding studs on the twist drill so they rotate together. Other systems provide for reshaping of the bone, but the tool itself generally obstructs the view of the bone lobe during cutting.
A total hip replacement procedure removes the organic stem of a bulbous bone joint replacing it with an artificial one. This is a relatively radical surgical procedure, and alternative processes exist that attempt to preserve the natural joint. One such procedure places a hard, external prosthetic cap over a resurfaced bulbous bone joint. The cap has an external spherical surface which mates with a hip socket. The cap is often made of metal and has precise interface dimensions which must be matched to the bone of the joint in order for the cap to properly fit over the joint, and to properly function in its corresponding prosthetic hip socket. Therefore, there is a need for cutters capable of cutting and shaping the bulbous bone joint in preparation for the reception of a prosthetic cap. Such an application presents other challenges in guidance and control, particularly, that of ensuring that the stem of the bulbous bone joint is not damaged in the process. Still further, what is needed therefore is a system which enables controlled cutting and reshaping of the bulbous bone joint in preparation for the reception of a bone cap prosthesis. In particular, what is needed is a reamer capable of cutting the bulbous bone joint to closely receive a bulbous bone joint prosthetic cap.


DAC design uses a passive reconstruction filter. The reconstruction filter includes a notch filter and series peaking filter. The notch filter provides notch filtering at the DAC clock frequency. The peaking filter increases signal bandwidth while attenuating frequency content at harmonics of the DAC clock frequency. The notch filter can be an LC notch filter with a notch inductor Ln and a notch capacitor Cn. The peaking filter can be a series peaking inductor Ls (shunted with a filter capacitor Cp). In a differential configuration, the passive reconstruction filter can be ±LC notch filters (with ±Ln notch inductors), and the peaking filter can be ±Ls peaking inductors coupled in series to the ±LC notch filters. The ±Ln notch inductors, ±Ls peaking inductors can be mutually wound as single inductors. For an example direct conversion RF transmit chain, IQ± signal paths are implemented with differential DAC designs including passive reconstruction filters.

Technical Field
This Patent Disclosure relates generally to digital to analog converters.
Related Art
Digital to Analog Converters (DACs) convert digital data into a sequence of impulses that are then processed by a reconstruction filter to band limit the DAC output, removing spurious high-frequency content. Reconstruction filters are also referred to as anti-imaging filters in that they prevent imaging by smoothing the DAC output waveform to remove image frequencies above the Nyquist limit. For example, in the case of RF transmitter applications, reconstruction filters remove DAC images prior to upconversion.
Reconstruction filters can be implemented with active RC filter circuits, avoiding the use of external inductors. Disadvantages of active reconstruction filters include power consumption, and sub-optimal noise and linearity.

Digital to analog converter with passive reconstruction filter


An image stabilizing device for a camera includes an image stabilizing means for preventing an image blur of the camera and a control means for changing a function of the image stabilizing means in accordance with a photometry or focus mode of the camera.

1. Field of the Invention
The present invention relates to an improvement of an image stabilizing device for a camera, capable of preventing an image blur caused by a hand shake (or vibration).
2. Related Background Art
Various types of conventional image blur compensation devices have been proposed, as disclosed in Japanese Laid-Open Patent Application No. 63-49729.
In order to prevent an image blur on a focusing plane, which blur is originated by a hand vibration, an optical axis eccentric means as a target control object is moved by a feedback control mechanism to suppress the image blur.
For example, a hand vibration (normally an oblique vibration of a camera with respect to a photographic optical axis) of the camera is detected as an acceleration signal, the acceleration signal is integrated by a signal processing system to obtain a velocity signal (and then a deviation signal), and the optical axis eccentric means is driven in a direction to suppress the camera vibration (i.e., a direction to suppress the image blur).
FIG. 25 shows a basic arrangement of an image blur compensation device including the above signal processing system. The image blur compensation device includes an acceleration detector 101 for detecting an oblique movement of a camera (not shown) with respect to the photographic optical axis of the camera as an acceleration signal a. The detected acceleration signal a is integrated into a velocity signal v by a first integrator 102. The velocity signal v is converted into a deviation signal d by a second integrator 103.
An actuator 105 is operated to drive a radially movable optical axis eccentric means 104 (normally a focusing lens system) of the camera in accordance with the deviation signal d.
A position sensor 106 constitutes a position detecting means for detecting an actual deviation of the optical axis eccentric means 104. A signal from the position sensor 106 is fed back to an input system of the actuator 105 through an operational amplifier 107, thereby forming a feedback loop for causing driving control to correspond to the vibration deviation.
On the other hand, various proposals have been made for photometry systems and autofocus (AF) systems for cameras.
Known photometry systems are a system having an average photometry mode for performing uniform photometry on the entire frame, a system having a spot photometry mode for performing photometry of only the central portion of the frame, and a system having an evaluative photometry mode for performing photometry with optimal weighting on the basis of conditions such as a back light state and a main object position.
When the image blur compensation device is combined with the above photometry modes, their effects cannot often be sufficiently enhanced.
More specifically, in the spot photometry mode, a photographer or user usually performs spot photometry of a main object and retries framing to obtain a desired frame. At this time, when an image blur compensation function mode is set, the compensation function is effected because a slight change in framing is detected as a hand vibration. As a result, current framing cannot be changed, or a desired frame cannot be obtained.
The following AF modes are proposed for the above AF system:
1) One-shot AF (or single AF): AF inhibited once an in-focus state is obtained; PA1 2) Servo AF (or continuous AF): AF performed repeatedly; and PA1 3) Moving object anticipation servo AF: AF performed to compensate for an AF tracking delay occurring in a high-speed moving object during a release operation during an AF operation. PA1 1) Since a stationary object is often focused in the one-shot AF mode, a hand vibration is generally discriminated in this mode. PA1 2) Since an irregularly moving object is traced in the servo AF mode, a change in framing is large. PA1 3) Since an object moving in one direction is focused in a moving object anticipation servo AF mode, a camera movement is one-directional camera movement, i.e., panning.
However, when the image blur compensation device is combined with an autofocus device (AF device), and this combination is applied to a camera or the like, the effect of the combination cannot often be sufficiently enhanced. In order to distinguish a hand vibration of a photographer from panning or a change in framing in the image blur compensation device, types of blurs are classified to estimate a photographer's intention. Processing such as a change in blur compensation range is performed on the basis of this estimation, thereby improving operability.
When a camera having a plurality of AF modes is used in a given AF mode, framing unique to the given AF mode is often performed. For example, the following operations may be assumed.
In the conventional arrangement, blur actions in the above AF modes are not estimated, and the photographer's intention is estimated from only a blur signal. As a result, the conventional arrangement is not necessarily convenient.
Many applications relating to AF devices and autoexposure (AE) devices have been made. Of these applications, there is provided a device utilizing the AF and AE devices to determine focus and aperture states so that a plurality of different objects are focused. For example, in Japanese Laid-Open Patent Application No. 63-85722 filed by the present applicant, a photographic lens is shifted to focus an object at the first distance by an AF device, and focus detection is performed for an object at the second distance. A defocus amount at the second distance with respect to the first distance is obtained, and an aperture value and a focus position are obtained so that the first and second objects are set in the in-focus state. The focus control lens position and the aperture value are controlled on the basis of the operation result, and photographing is performed. A photograph focused on both the objects at different distances can be obtained. This exposure control mode is called a depth priority AE mode.
When the image blur compensation device is used in combination with the depth priority AE mode, their effects cannot often be sufficiently enhanced.
When many functions such as image blur compensation, focus control, and exposure control are automated, it is important to determine the first operation of each function in consideration of the operability of the camera. In general, each function is selected in an automatic or manual mode, and then one operation member such as a switch turned on upon depression of, e.g., a release button to the half stroke is used as a trigger switch for starting all the functions. However, in the depth priority mode, at least two focus detection operations are performed in the depth priority mode, and a change in framing is performed every detection. An image blur detector in the image blur compensation device detects a change in framing as a large blur. A large deviation signal is generated in the blur detector after a change in framing occurs. When the release button is depressed to perform focus detection in this state, the image blur compensation device is operated. Accurate image blur compensation cannot be performed by the large deviation signal in the image blur detector. In addition, an object cannot be caught within the focus detection frame due to an abnormal behavior of the image blur compensation mechanism. Therefore, accurate focus detection cannot be performed.


An array multiplier utilizing a predetermined recoding algorithm minimizes operating speed by using two different radices. Special product terms must be formed to implement the recording algorithm. In order to avoid delaying the computation of partial products until after the time special products are formed, two recoding radices may be used. Partial products can be calculated from terms formed by a smaller sized radix during the same time the special product terms are being calculated. Initial use of the smaller radix eliminates an immediate need for the special product bits which improves multiplier speed by minimizing time required to form a final product.

It is well known that as digital multipliers are implemented vor very large operand bit sizes, the complexity, speed of operation and size of circuitry become very large problems. These factors are the primary limitations preventing fast, powerful large-scale integrated multipliers from being commonly used. Others have commonly sought to solve the multiplier size problem by reducing the number of additions required to implement a multiplication operation. Recoding of the binary inputs in accordance with a recoding algorithm such as Booth's algorithm, Modified Booth's algorithm or further Modified Booth's algorithm significantly reduces the number of additions required. Recording schemes typically utilize bit pair recoding meaning that two bits of a binary input are grouped together to require only one addition of an input operand, typically labeled "X", rather than an addition for each bit of the input operand. Recoding schemes larger than bit pair recoding have been used but have the associated disadvantage of introducing further complexity. An example of a recoding multiplier which uses four bit recoding is illustrated by Diedrich et al. in U.S. Pat. No. 4,745,570 entitled "Binary Multibit Multiplier". Diedrich et al. teach a multiplier which uses five adder carry chains to perform a sixteen by N multiply, where N is an integer. The Diedrich et al. multiplier uses five bit groupings for the recoders and form the required X3, X5 and X7 "special product" terms of operand "X" before permitting the addition associated with the first recoding to proceed. Therefore, four adder carry delays due to each of the four recoders exist in addition to a carry delay due to the formation of the special product terms. The speed of the multiplier is directly related to the total number of carry delays.


A cutting device for arranging a cut around the anus of a slaughtered animal, which cutting device comprises:. a positioning rod for insertion into the anus of a slaughtered animal; PA0 a rotatably drivable cylindrical beaker-shaped knife which is placed coaxially round the positioning rod and whereof the free end is provided with a cutting edge; and PA0 pressure means and suction means comprising a conduit extending through the positioning rod, debouching on the peripheral surface of the positioning rod at a distance from the cutting edge and connectable to a pressure source and an underpressure source respectively for generating an overpressure and an underpressure respectively at the position of the debouchment of that conduit.. The device has a pressure conduit and a suction conduit, which conduits are connectable to a pressure source and an underpressure source respectively, which pressure conduit debouches on the peripheral surface of the positioning rod and which suction conduit debouches in the space bounded by the beaker-shaped knife.

The invention relates to a cutting device for arranging a cut around the anus of a slaughtered animal, which cutting device comprises:
a positioning rod for insertion into the anus of a slaughtered animal;
a rotatably drivable cylindrical beaker-shaped knife which is placed coaxially round the positioning rod and whereof the free end is provided with a cutting edge; and
pressure means and suction means comprising a conduit extending through the positioning rod, debouching on the peripheral surface of the positioning rod at a distance from the cutting edge and connectable to a pressure source and an underpressure source respectively for generating an overpressure and an underpressure respectively at the position of the debouchment of that conduit.
Such a device is known from NL-A-73 06059. In this known device a conduit debouches on the peripheral surface of the positioning pin which is alternately connectable to an underpressure source and a pressure source. The cut away anus of a slaughtered animal, particularly poultry, can first be sucked fixedly and subsequently removed form the device by energizing the pressurized air source.
The drawback to the known device can be that feces still come out of the anus, whereby the sterility of the slaughtered animal is lost. Feces that may still be adhering to the positioning rod can also find their way onto or into the slaughtered animal. This could be prevented by removing the cutting device very carefully. In the rather rough and ready slaughterhouse business this is however not really possible.
It is therefore the object of the invention to provide a cutting device of the type referred to in the preamble wherein it is ensured that the slaughtered animal is not contaminated during removal of the cutting device.
This is achieved according to the invention with a device having a pressure conduit and a suction conduit, which conduits are connectable to a pressure source and an underpressure source respectively, which pressure conduit debouches on the peripheral surface of the positioning rod and which suction conduit debouches in the space bounded by the beaker-shaped knife.
The suction conduit can debouch on the inner surface of the knife or on the peripheral surface of the positioning rod.
In this latter case the device can have the feature that the pressure conduit and the suction conduit debouch at a mutual axial distance on the peripheral surface of the positioning rod.
It is noted that the debouchments of the conduits can take a multiple form and be placed for instance in distributed manner.
By actuating the pressure source which can generate a gaseous or liquid medium an overpressure can be excited in the space between the positioning rod and the rectum, whereby fecal remnants are pressed into the rectum. Fecal remnants arriving at the embouchement of the suction conduit can thus be removed from the space bounded by the knife. If desired, this removing can be stimulated by energizing the underpressure source. After completing the handling of the slaughtered animal the overpressure within the knife can attribute to a ready removing of the animal. It should be noted that the options given here are only alternatives subjected to the user's wishes.
When the cut is made the skin around the anus is held stretched, which has a positive effect on the cutting action. The overpressure generated inside the beaker-shaped knife by the pressure means can also ensure that fecal residues are transported to the suction means. This also reduces the risk of fecal residues dripping out of the beaker-shaped knife.
The device preferably has the feature that the or each debouchment of the pressure conduit is located between the free end of the positioning rod and the or each debouchment of the suction conduit.
A practical embodiment is that wherein the pressure conduit and the suction conduit extend in axial direction through the positioning rod in mutual coaxial relation.
This variant can be characterized by an axial bore in the positioning rod bounding the suction conduit and by a tube placed therein which bounds the pressure conduit and separates the pressure conduit from the suction conduit.
In order to prevent as far as possible damage to the anus of a slaughtered animal the device preferably has the feature that the free end of the positioning rod has a smooth, rounded shape. This embodiment can have the particular feature that the free end of the positioning rod has a rotation-symmetrical widening.
In a subsequent embodiment the device has the feature that the positioning rod has a rotation-symmetrical widening in the region of the debouchments of the pressure conduit and the suction conduit.
Advantageous is that alternative embodiment, in which the widening has a recess in the region of the or each debouchment of the pressure conduit. When the positioning rod is rotated in the anus the debouchment of the pressure conduit hereby remains clear thereof. This avoids damage to the rectum and the anus wall by the edges of the debouchments. At the suction mouth this problem does not occur since the anus wall has a more robust structure there in view of the presence of the sphincter muscle at that location and the transition to the exterior of the animal.
A simple structure is obtained with an embodiment in which the positioning rod and the knife are coupled fixedly to one another. The above description relating to the recessed location of the debouchment of the pressure conduit already relates thereto.
In order to counter imbalance the embodiment is recommended which has the feature that the rotational axis and the axis of inertia mutually coincide.
The invention will now be elucidated with reference to the annexed drawing, in which:


A valve-operating lever comprising a valve arm including a first aperture defining a valve arm engagement portion. The lever also includes a connector member having an outside surface and a first stop. The connector member and the first stop cooperate to define a first engagement portion. A first portion of the connector member overlays a portion of the valve arm adjacent the first aperture, and the valve arm engagement portion engages the first engagement portion.

The present invention relates generally to internal combustion engines. More particularly, the present invention relates to a direct lever for controlling valve opening and closing.
Internal combustion engines include valves that are operated at precise intervals to allow fuel and air to enter a cylinder or to allow exhaust gas to escape. Typically, a cam shaft driven by the engine actuates the valves to control the timing.
Many engines include valve-actuating levers that actuate push rods to open and close valves. The actuating levers include one arm that rides on a cam and a second arm that actuates the push rod. One such valve-actuating lever is disclosed in U.S. Pat. No. 6,349,688 to Gracyalny. However, the valve-actuating lever of Gracyalny is costly to manufacture and requires precise techniques to maintain the necessary tolerances.