The invention concerns a method for flow control in a peer-to-peer live streaming communication network comprising a plurality of nodes characterized in that the rate at which a node sends information to another node increases proportionally to the quantity of information present at node which has not yet reached node and decreases proportionally to a value attached to the link connecting node to node.

Consider a peer-to-peer network with a distinguished node called the source. The source wants to send a stream of bytes to a set of nodes in the peer-to-peer network called the receivers at a fixed rate (i.e. each receiver needs to receive data at the specified rate). The remaining nodes in the peer-to-peer network are called helpers and their role is to relay information. They do not have any rate requirements.
In the peer-to-peer network, each node has a fixed set of outgoing links towards neighbouring nodes over which it sends out data. We call these links overlay links. An overlay link from a node i to its neighbour node j uses several underlay links. In a real setting such an overlay link can be assimilated with a UDP flow from host i to host j in an IP network, while an underlay link can be assimilated with a physical link connecting two IP routers.
If node i sends data to node j on the overlay link (i,j) at a rate c then all the underlay links used by link (i,j) need to support rate c in addition to any other traffic they might be transmitting. Underlay links can be shared among overlay links. Thus, if an underlay link is being used simultaneously by two overlay links which transmit data at rates c1 and c2 respectively, then the underlay link will be used to send data from both overlay links at rate c1+c2.
Underlay links have a maximum rate at which they can be used. We introduce the natural concept of feasible rate allocation: a set of rates for the overlay links supported by the underlay links (i.e. all underlay links are used at rates lower than the maximum rate which they can sustain).
The congestion control problem can be formulated as a cost minimization problem. We can assign a real cost to each rate allocation. This cost characterizes the level of congestion in the network for that specific rate allocation. We obtain a global cost function defined on the set of all possible rate allocations. Equivalently, the global cost can be represented as the set of marginal overlay link costs (or overlay link prices). Among all feasible rate allocations such that all of the receivers' rate requirements are satisfied, consider a rate allocation achieving the minimum global cost. We call such a rate allocation a globally optimal allocation for the chosen global cost function.
Example of Cost Function Capturing Congestion and ISP Requirements:
A specific set of link prices can be defined as follows: For a particular overlay link e from node i to node j, we set its price to have the following two additive components:                the first one proportional to the observed packet Round Trip Time (RTT) from node i to node j—the congestion term,        the second one a constant defined by the Internet Service Provider (ISP) (e.g. the sum of the weights of the underlay links used by the overlay link e)—the ISP term.
The price functions described above have the following properties: the congestion term of the price is inversely proportional to the spare capacity of the overlay link, while the ISP term can be set by the ISP to specific values chosen to avoid intense usage of specific underlay links in the underlying physical topology.
Then any mechanism which guarantees convergence to overlay link rates forming a globally optimal allocation for the cost function defined above performs ISP-friendly congestion control for peer-to-peer live streaming systems.
Prior art knows, through the publication "Minimum cost multicast over coded packet networks" (Desmond S. Lun, Niranjan Ratnakar, Muriel Medard, Ralf Koetter, David R. Karger, Tracey Ho, Ebad Ahmed, and Fang Zhao. IEEE/ACM Trans. Netw., 14 (SI):2608-2623, 2006), a message passing scheme which computes a globally optimal allocation. The scalability of this approach is limited due to the fact that messages relative to each receiver need to be passed throughout the network. Thus the number of state variables to be maintained at each node scales linearly with the number of receivers.
Prior art also knows, through the publication "Min-cost selfish multicast with network coding" (S. Bhadra, S. Shakkottai, and P. Gupta. Information Theory, IEEE Transactions on, 52 (11):5077-5087, 2006), a so-called UESSM selfish routing algorithm. It is shown that UESSM converges to the min-cost flow allocation for a particular type of cost function. This approach has the same scalability limitations as the above-cited publication by Lun et al.
Consider a peer-to-peer network as defined previously which does not contain any helper nodes. Thus, the source wishes to convey a stream of bytes to all the other nodes in the network at a fixed rate. Previously described solutions in the publications by Lun et al. and Bhadra et al. also apply to this case, but they maintain the same scalability issues.
In "Utility maximization in peer-to-peer systems" (Minghua Chen, Miroslav Ponec, Sudipta Sengupta, Jin Li, and Philip A. Chou. In SIGMETRICS '08: Proceedings of the 2008 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, pages 169-180, New-York, N.Y., USA, 2008. ACM), the authors wish to maximize a utility function. The authors present a solution involving packing a polynomial number of depth-1 and -2 Steiner trees for multisource multicast. The scalability of their approach is again limited as it requires all peers to maintain data exchanges with all other peers.

Distributed flow mechanism for peer-to-peer streaming


A power-on reset circuit is provided which holds an integrated circuit device in a reset mode until at least two conditions are satisfied: supply voltage Vcc must be above a specified value and sense amplifiers in the device must be able to operate properly. Delay circuits and Schmitt trigger circuits also improve the stability of the signal which releases the device from its reset mode.

A power-on reset circuit is used in an integrated circuit device to prevent logic circuits in the device from being used when the power supply voltage Vcc is not sufficient for the logic circuits to operate properly. Power-on reset circuits typically include a Vcc detect circuit which detects when Vcc has risen to a level sufficient to operate logic gates in the device. CMOS circuits will begin to operate marginally when Vcc is above the higher of Vtn and Vtp, where Vtn is the threshold voltage of N-channel transistors in the CMOS circuits and Vtp is the threshold voltage of P-channel transistors in the CMOS circuits. But CMOS circuit operation will be more reliable when Vcc is above Vtn+Vtp. To provide a guard band, Vcc detect circuits typically provide a detect signal when Vcc has risen to a higher voltage, for example 2Vtn+Vtp or 2Vtp+Vtn.
FIG. 1 shows a block diagram of such a circuit. In addition to Vcc detect circuit 110, which provides a high output signal at NR10 when Vcc has risen to 2Vtn+Vtp, delay block 120 provides a time delay on the output signal at node NR10. Reset circuit 180 provides an override reset signal in response to an externally provided reset signal. Schmitt trigger circuit 130 has a higher trigger point to rising input signals and a lower trigger point to falling input signals, and thus prevents multiple changes in reset signal on R11 in the event of small variations in the signal on NR10. Buffer 138 converts the R11 signal to the output signal on R12.
In some integrated circuit devices, however, the power-on reset circuit may release the integrated circuit device from the reset mode before all circuits in the device are able to operate properly.

Power-on reset circuit including dual sense amplifiers


A deflection yoke for CRTs, designed to easily correct a misconvergence in a vertical direction of a frame without being rotated during a frame correction step, is disclosed. The deflection yoke has a coil separator composed of a screen part, a rear cover part and a neck part. A plurality of horizontal and vertical deflection coils are set on the internal and external surfaces of the coil separator and generate horizontal and vertical deflection magnetic fields. A correction means is provided on the rear cover part of the coil separator and corrects the vertical magnetic field in addition to frame dispersion. A position adjusting means is provided at a position between the rear cover part and the correction means and holds the correction means on the rear cover part while allowing the position of the correction means relative to the rear cover part to be finely and precisely adjustable. This deflection yoke precisely and stably corrects both the frame dispersion and the vertical magnetic field. In the correction means, two correction pieces are connected together into a single structure by a guider. This guider also almost completely prevents the correction pieces from being undesirably displaced on or removed from the rear cover part, thus improving the operational reliability of the deflection yoke.

1. Field of the Invention
The present invention relates to deflection yokes and, more particularly, to a mounting device provided on the coil separator of such a deflection yoke for allowing a frame correction means to be easily and precisely mounted to the coil separator of the deflection yoke.
2. Description of the Prior Art
As well known to those skilled in the art, deflection yokes for CRTs (cathode ray tubes) of TV receivers or computer monitors have been typically classified into a plurality of types, for example, saddle-toroidal type yokes and saddle-saddle type yokes.
As shown in FIG. 1, a deflection yoke 10 is typically mounted to the neck part 2 of a CRT 1. Such deflection yokes 10 are generally classified into two types, or saddle-saddle type deflection yokes of FIGS. 2 and 3 and saddle-toroidal type deflection yokes of FIGS. 4 and 5, in accordance with a coil structure.
Such a deflection yoke 10 is used for appropriately deflecting the B (blue), R (red) and G (green) light beams, emitted from a BRG electron gun 3 set within the neck part 2 of the CRT 1, upward, downward, leftward and/or rightward, thus allowing the light beams to precisely reach the desired positions on the fluorescent screen of the CRT 1 and to form a desired picture on the screen.
FIGS. 2 and 3 show the construction of a conventional saddle-saddle type deflection yoke. In such a conventional saddle-saddle type deflection yoke, a plurality of saddle-type horizontal deflection coils 12 are installed on the internal surface of the screen part of a generally conical coil separator 11 at upper and lower portions as shown in the drawings. In addition, a plurality of saddle-type vertical deflection coils 13 are installed the external surface of the screen part of the coil separator 11 at left and right portions.
A ferrite core 14, having a generally cylindrical shape, is provided on the external surface of the screen part of the coil separator 11 for correcting the magnetic field formed by the vertical deflection coils 13.
On the other hand, a plurality of coma free coils 15 are mounted to the external surface of the coil separator 11 at a position around the neck part and are used for correcting the coma formed by the vertical deflection coils 13.
FIGS. 4 and 5 show the construction of a conventional saddle-toroidal type deflection yoke. In such a conventional saddle-toroidal type deflection yoke, a plurality of horizontal deflection coils 12 are installed on the internal surface of the screen part of a generally conical coil separator 11 at upper and lower portions as shown in the drawings. In addition, a ferrite core 14, having a generally cylindrical shape, is provided on the external surface of the screen part of the coil separator 11. In addition, a plurality of toroidal-type vertical deflection coils 16 are installed on the external surface of the above ferrite core 14 at upper and lower portions.
On the other hand, a plurality of coma free coils 15 are mounted to the external surface of the core separator 11 at a position around the neck part and are used for correcting the coma formed by the vertical deflection coils 16.
However, such conventional deflection yokes have the following problems. In the case of the saddle-saddle type deflection yoke of FIGS. 2 and 3, it is necessary to mount the ferrite core 14, having the vertical deflection coils 13, on the external surface of the coil separator 11 having the horizontal deflection coils 12. However, a frame misconvergence may be easily induced in both the dimension dispersion of the ferrite core 14 and the winding dispersion of the vertical deflection coils 13 during a process of locking the ferrite core 14 to the external surface of the coil separator 11.
That is, both a misconvergence in a vertical direction and a misconvergence in a horizontal direction are formed in such a conventional deflection yoke as shown in FIGS. 6 and 7.
Such misconvergences are corrected as follows in the prior art. That is, the misconvergence in the horizontal direction may be corrected by a correction piece 20. Such a correction piece 20 is set on the rear plate 11a of the coil separator 11 as shown in FIG. 8 and corrects the magnetic field in the horizontal direction. On the other hand, the misconvergence in the vertical direction may be corrected by correcting the magnetic field in the vertical direction. Such a correction of the vertical magnetic field may be accomplished by controlling the volume of a circuit board (not shown) provided on a sidewall of the coil separator 11 or by rotating the deflection yoke 10 around the CRT 1.
In the prior art, the desired correction of the vertical magnetic field may be somewhat effectively accomplished by controlling the volume of the circuit board or by rotating the deflection yoke 10. However, such a correction of the vertical magnetic field performed by controlling the volume of the circuit board undesirably gives bad effects on the environmental magnetic field, such as the magnetic field in the vertical direction. This forces an additional correction process to be necessarily performed to correct the environmental magnetic field. On the other hand, the correction of the vertical magnetic field performed by rotating the deflection yoke 10 around the CRT 1 undesirably gives bad effects on a final processing step, or on an ITC step, thus deteriorating work efficiency during such an ITC step.
Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and an object of the present invention is to provide a deflection yoke, which is designed to easily correct a misconvergence in a vertical direction of a frame, and which is not rotated during a frame correction step, thus being free from requiring an additional correction step or affecting an ITC step.
In order to accomplish the above object, the present invention provides a deflection yoke, comprising: a coil separator composed of a screen part positioned around a screen of a CRT, a rear cover part extending from the screen part to the back and covering a rear portion of the CRT, and a neck part extending from the rear cover part to the back and covering an electron gun of the CRT; a plurality of horizontal and vertical deflection coils set on the internal and external surfaces of the coil separator and used for generating horizontal and vertical deflection magnetic fields; a correction means provided on the rear cover part of the coil separator and used for correcting the vertical magnetic field in addition to a frame dispersion; and a position adjusting means provided at a position between the rear cover part and the correction means and used for holding the correction means on the rear cover part while allowing the position of the correction means relative to the rear cover part to be finely and precisely adjustable.
In the above deflection yoke, the correction means comprises: two guide rails formed on the rear cover part in a way such that the two guide rails are oppositely positioned around the neck part of the coil separator, with a guide groove being axially formed along an inside surface of each of the guide rails; two correction pieces movably set in the guide grooves of the guide rails and used for correcting the vertical magnetic field in addition to the frame dispersion; and a guider connecting opposite outside ends of the correction pieces to each other into a single body.
The correction pieces are preferably formed of a metal, and the guider is preferably formed of a plastic material.
The correction pieces are integrated with the guider into a single structure by inserting the correction pieces into the guider during a molding process of forming the guider.
In the above deflection yoke, the position adjusting means comprises: a plurality of fixed teeth formed on the external surface of the rear cover part at positions around the guide rails; and a plurality of movable teeth formed on the lower surface of the correction means and used for movably engaging with the fixed teeth of the rear cover part.
The movable teeth are formed on the lower surface of each end portion of the guider of the correction means.
The rear cover part is also provided with an elastic piece at a position corresponding to the correction means, the elastic piece having an upward elasticity so as to prevent an undesirable displacement of the correction means relative to the rear cover part.
The fixed teeth are formed on the above elastic piece.


A semiconductor memory device includes two memory cell array sections, a single clock signal line, a clock signal generating section and a multiplexer section. The clock signal generating section generates a single first clock signal based on a second clock signal externally supplied and outputs the first clock signal onto the clock signal line. The first clock signal has twice of a frequency of the second clock signal. The multiplexer section is connected with the clock signal line and outputs first data and second data respectively read out from the two memory cell array sections in order during one period of the second clock signal in response to the first clock signal on the clock signal line.

1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a synchronous type semiconductor memory device of a double data rate.
2. Description of the Related Art
Conventional, a memory apparatus like 128-M DDR-SDRAM (Double Data Rate Synchronous Dynamic Random Access the memory) is known. FIGS. 1A and 1B are block diagrams showing the outline circuit structure of the memory apparatus. Referring to FIGS. 1A and 1B, the memory device is comprised of a clock signal generating section 120, a memory cell array 1102-1, a memory cell array 2102-2, a data amplifier 1106-1, a data amplifier 2106-2 and an output circuit 108. The clock signal generating section 120 generates internal clock signals ICLK1 and ICLK2 from an external clock signal ECLK and a signal ECLKB as an inversion signal of the signal ECLK. A column decoder (not shown) to specify a Y address and a sense amplifier (not shown) to detect data read from a memory cell are provided in each of the memory cell array 1102-1 and the memory cell array 2102-2. The output circuit 108 has a multiplexer (MUX) 110 and an output latch buffer 114.
Data is read out from the memory cell array 1102-1, is amplified by the data amplifier 106-1 and is outputted on a data bus 10L. Also, data is read from the memory cell array 2102-2, is amplified by the data amplifier 106-2 and is outputted on a data bus 20L. If the data on the data bus 10L is an odd number side, the data on the data bus 20L is an even number side, and if the data on the data bus 10L is the even number side, the data on the data bus 20L is the odd number side.
The multiplexer (MUX) 110 of the output circuit 108 outputs the data on the data buses 10L and 20L to the output latch buffer 114 via a data bus Mout in order in response to the two internal clock signals ICLK1 and ICLK2 which are supplied from the clock signal generating section 120. The output latch buffer 114 outputs the data from the multiplexer (MUX) 110 to an output terminal Dout in order in response to the external clock signals ECLK and ECLKB. In this way, the data of the odd number side and the data of the even number side are outputted during one period of the external clock signal.
FIGS. 2A to 2H are timing charts showing an operation of the conventional memory device shown in FIGS. 1A and 1B. As shown in FIGS. 2A and 2B, the external clock signals ECLK and ECLKB are supplied to the clock signal generating section 120. As shown in FIGS. 2C and 2D, the clock signal generating section 120 generates the internal clock signals ICLK1 and ICLK2 from these external clock signals ECLK and ECLKB. That is, the internal clock signals ICLK1 and ICLK2 are generated to synchronize with the rising edge or falling edge of the external clock signals ECLK or ECLKB, respectively. In this way, the internal clock signals ICLK1 and ICLK2 have the frequency the same as the external clock signal. The internal clock signals ICLK1 and ICLK2 have approximately the same phase as the external clock signals ECLK and ECLKB.
The data DATA1 of the odd number side and data DATA2 of the even number side read out from the memory cell array 1102-1 and the memory cell array 2102-2 are amplified by the data amplifiers 106-1 and 106-2 and are outputted on the data buses 10L and 20L during one period of the internal clock signal, respectively, as shown in FIGS. 2E and 2F.
The above internal clock signals ICLK1 and ICLK2 are supplied to the multiplexer (MUX) 110. As shown in FIG. 2G, the multiplexer (MUX) 110 selects the data DATA1 on the data bus 10L in response to the rising edge of internal clock ICLK1 and outputs it to the output bus Mout. Next, the multiplexer 110 selects the data DATA2 on the data bus 20L in response to the rising edge of the internal clock ICLK2 (the falling edge of the internal clock ICLK1) and outputs it to the output bus Mout. As shown in FIG. 2H, the output latch buffer 114 outputs the data DATA1 and DATA2 from the output terminal Dout in response to the external clock signals ECLK and ECLKB, respectively. In this way, the two data DATA1 and DATA2 can be read out during one period of the external clock signal.
In such a DDR-SDRAM, a layout is often used in which a plurality of memory cell arrays are arranged on both sides of a chip, and a single clock signal generating section 120 is arranged on the center of the chip. The output circuit 108 containing the multiplexer 110 is provided for each memory cell array. The two internal clock signals ICLK1 and ICLK2 generated by the clock signal generating section 120 are supplied to each output circuit 108 as a pair, as shown in FIG. 3.
In 256-MB DDR-SDRAM, a clock signal of 166 MHz is used as the external clock signal, whose one cycle is about 6 ns. In this case, one read cycle is about 3 ns. When a high frequency clock signal is used in this way, there is a case where data cannot be read out right due to the difference between the propagation delay times of the internal clock signal, when the wiring lines for the internal clock signals are different in the length from the clock signal generating section 120 to each output circuit 108. For this reason, the wiring line of the internal clock signal is generally designed for the wiring lengths from the clock signal generating section 120 to the respective output circuits 108 to be equal, for elimination of the difference in the propagation delay time. For this purpose, as shown in FIG. 3, the wiring lines for the two internal clock signals ICLK1 and ICLK2 needs be arranged to be equal in length for the output circuits. However, in the conventional DDR-SDRAM, the mask design becomes complicated and also a chip area is wasted. Especially, when a multiple bit output circuit structure is adopted like the 16-bit output, the arrangement of the clock signal wiring lines becomes very difficult.
Also, as mentioned above, when the internal clock signal is generated using the rising edge or falling edge of the external clock signal, there is no guarantee that the duty ratio of the internal clock signal is 50%. When the duty ratio is not 50%, the durations of the internal clock signals ICLK1 and ICLK2 in the high level are different, and there is a case that the operation margin cannot be secured.
In addition, in a high speed operation DDR-SDRAM, because the period of the read cycle is short, the margin for the setup reduces. Therefore, it is desirable that the internal clock signal used for the reading operation is supplied before the reading cycle. Contrary, when the internal clock signal is too early supplied, the internal clock signal is supplied before the previous cycle ends so that there is possibly erroneous operation.
In conjunction with the above description, a clock system of a semiconductor memory device which uses a frequency multiplier is disclosed in U.S. Pat. No. 6,157,238. In this reference, an external clock signal source generates external clock signals. A controller has a master frequency amplifier and a master DLL circuit. Each of a plurality of DRAMs has the frequency multiplier and the DLL circuit. The frequency multiplier generates an internal clock signal, which has twice of the frequency of the external clock signal, from the external clock signal. The frequency multiplier has a delay circuit, a logical device and a buffer. The delay circuit generates a phase delayed clock signal based on the external clock signal. The logical device generates the internal clock signal based on the external clock signal and the phase delayed clock signal. The buffer buffers the internal clock signal and supplies it.
Also, a semiconductor memory device is disclosed in Japanese Laid Open Patent Application (JP-P2000-298983A). In this reference, the semiconductor memory device has first and second memory sections and an output section. The first memory section stores or outputs data in the rising edge of the clock signal, and the second memory section stores and outputs data in the falling edge of the clock signal. The output section outputs the data from the first and second memory sections in response to the rising edge and falling edge of the clock signal. One of the first and second memory sections, which outputs data first, is arranged near the output section.
Also, a clock multiplying circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 11-163689). In this reference, a delay circuit has a plurality of delay elements and generates a multi-phase clock signal from the clock signal with an optional duty ratio. A period sensing section detects the number of delay elements necessary to delay the input clock signal for one period. A selecting section outputs a selection signal from the delayed clock signal based on the detected number of delay elements. The multiple clock generating section generates a clock signal with the duty ratio of 50% from the input clock signal through the logic inversion in the rising edge of the selection signal.
Also, a semiconductor integrated circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 11-66854). In this reference, each of a plurality of first delay circuits of a delay circuit sequence has first to fourth nodes. The third node is connected to the first node of the adjacent delay circuit, and the fourth node is connected to the second node of the adjacent delay circuit. When the first node is connected to the first power supply during a first period while a first control signal is connected to a first power supply, the second to fourth nodes are connected to a second power supply, the first power supply and the second power supply in order, respectively. Also, when the fourth node is connected to the first power supply during a second period while the first control signal is connected to the second power supply, the third, second and first nodes are connected to the second power supply, the first power supply and the second power supply in order, respectively. Thus, an internal clock signal is generated with no phase difference from an external clock signal.
Therefore, an object of the present invention is to provide a semiconductor memory device in which a single clock signal is supplied to each of output circuits provided for memory cell arrays.
Another object of the present invention is to provide a semiconductor memory device in which an operation margin can be taken widely.
Still another object of the present invention is to provide a semiconductor memory device in which a chip area can be used effectively.
Yet sill another object of the present invention is to provide a semiconductor memory device in which four data can be read out a double data rate.
Also, it is an object of the present invention to provide a semiconductor memory device in which an internal clock signal is generated from external clock signals to have twice of the frequency of the external clock signal and to have the duty ratio of 50%.
In an aspect of the present invention, a semiconductor memory device includes two memory cell array sections, a single clock signal line, a clock signal generating section and a multiplexer section. The clock signal generating section generates a single first clock signal based on a second clock signal externally supplied and outputs the first clock signal onto the clock signal line. The first clock signal has twice of a frequency of the second clock signal. The multiplexer section is connected with the clock signal line and outputs first data and second data respectively read out from the two memory cell array sections in order during one period of the second clock signal in response to the first clock signal on the clock signal line.
It is desirable that the clock signal generating section generates the first clock signal to have a phase more progressive by a predetermined phase than the second clock signal.
In another aspect of the present invention, a semiconductor memory device includes a first data bus which transfers first data, a second data bus which transfers second data, a third data bus, a clock signal generating section and a multiplexer section. The clock signal generating section generates a single first clock signal from a second clock signal, and the first clock signal has twice of a frequency of the second clock signal. The multiplexer section receives the first data and the second data from the first data bus and the second data bus within one period of the second clock signal, respectively, and outputs the first data and the second data to the third data bus in order within the one period of the second clock signal in response to the first clock signal.
The semiconductor memory device may further include a plurality of memory cell arrays, each of the plurality of memory cell arrays may include a first memory cell array section and a second memory cell array section. The multiplexer section is provided for each of the plurality of memory cell arrays. The first data and the second data are respectively read out from the first memory cell array section and the second memory cell array section in one of the plurality of memory cell arrays and are supplied to the multiplexer section corresponding to the one memory cell array through the first data bus and the second data bus. In this case, the clock signal generating section may be provided for the plurality of memory cell arrays, and the clock signal generating section may supply the first clock signal to a plurality of the multiplexer sections in a same delay time. Also, the multiplexer section may include a selecting section and a control clock signal generating section. The selecting section may transfer the first data to the third data bus in response to a control clock signal and then transfers the second data to the third data bus in response to an inversion signal of the control clock signal. The control clock signal generating section may generate the control clock signal during the one period of the second clock signal in response to the first clock signal.
In this case, the selecting section may include a first transfer gate connected with the first data bus and the third data bus to transfer the first data to the third data bus in response to the control clock signal, and a second transfer gate connected with the second data bus and the third data bus to transfer the second data to the third data bus in response to the inversion signal of the control clock signal. Also, the control clock signal generating section may have a D-type flip-flop with a reset terminal. The inversion output terminal of the D-type flip-flop is connected with a data input terminal thereof. The control clock signal is outputted from an inversion output terminal of the D-type flip-flop in response to the first clock signal, and the D-type flip-flop is reset in response to a reset signal supplied to the reset terminal.
Also, it is desirable that two periods of the first clock signal corresponding to the one period of the second clock signal are equal to each other in time length. In addition, it is desirable that the clock signal generating section generates the first clock signal to have a phase more progressive by a predetermined phase than the second clock signal. Otherwise, it is desirable that the clock signal generating section generates the first clock signal based on one of a rising edge and a falling edge of the second clock signal.
In still another aspect of the present invention, a semiconductor memory device includes a first data bus which transfers first data, a second data bus which transfers second data, a third data bus which transfers third data, a fourth data bus which transfers fourth data, and a fifth data bus. A clock signal generating section generates a single first clock signal from a second clock signal, and the first clock signal has twice of a frequency of the second clock signal. A multiplexer section receives the first to fourth data from the first to fourth data buses, respectively, outputs the first data and the second data to the fifth data bus in order in a first period of the second clock signal, in response to the first clock signal, and outputs the third data and the fourth data to the fifth data bus in order to a second period of the second clock signal subsequent to the first period.
The semiconductor memory device may further include a plurality of memory cell arrays, each of the plurality of memory cell arrays may include first to fourth memory cell array sections. The multiplexer section is provided for each of the plurality of memory cell arrays. The first to fourth data are read out from the first to fourth memory cell array sections in one of the plurality of memory cell arrays, and are supplied to the multiplexer section corresponding to the one memory cell array through the first to fourth data buses. In this case, the clock signal generating section may be provided for each of the plurality of the memory cell arrays, and the clock signal generating section may supply the first clock signal to a plurality of the multiplexer sections in a same delay time.
Also, the multiplexer section may include a selecting section which transfers the first to fourth data to the fifth data bus in response to first to fourth control clock signals, and a control clock signal generating section which generates the first and second control clock signals during the first period of the second clock signal in response to the first clock signal, and generates the third and fourth control clock signals in the second period of the second clock signal. In this case, the selecting section may include a first transfer gate connected with the first data bus and the fifth data bus to transfer the first data to the fifth data bus in response to the first control clock signal, a second transfer gate connected with the second data bus and the fifth data bus to transfer the second data to the fifth data bus in response to the second control clock signal, a third the transfer gate connected with the third data bus and the fifth data bus to transfer the third data to the fifth data bus in response to the third control clock signal, and a fourth transfer gate connected with the fourth data bus and the fifth data bus to transfer the fourth data to the fifth data bus in response to the fourth control clock signal. Also, the control clock signal generating section has a counter with a reset terminal. The counter counts the first clock signal to output the first to fourth control clock signals, and the counter is reset in response to a reset signal supplied to the reset terminal.
Also, it is desirable that adjacent periods of the first clock signal corresponding to one period of the second clock signal are equal to each other. Moreover, it is desirable that the clock signal generating section generates the first clock signal to have a phase more progressive by a predetermined phase than the first clock signal. Otherwise, it is desirable that the clock signal generating section generates the first clock signal based on one of a rising edge and a falling edge of the clock signal.
In yet still another aspect of the present invention, a method of reading out data from a specified one of a plurality of memory cell arrays, may be achieved by (a) generating a single first clock signal from a second clock signal, the first clock signal having N times (N is an integer more than 1) of a frequency of the second clock signal; by (b) transferring the first clock signal to the plurality of memory cell arrays in a same delay time; by (c) generating N control clock signals from the first clock signal; and by (d) outputting N data read out from the specified memory cell array during one period of the second clock signal, in response to the N control clock signals as a series of the N data.
It is desirable that the first clock signal has a phase more progressive by a predetermined phase than the second clock signal.

Semiconductor memory device with single clock signal line


A system for detecting and tracing a (D)DoS attack and identifying the attack source, which system simplifies the judgment reference to determine whether a (D)DoS attack is present. The number of source addresses of the packets transmitted via the Internet line is monitored. When the number of the source addresses has reached a predetermined number or a predetermined ratio within a predetermined time, it is judged that an unauthorized attack is present. Moreover, where the hop number of the packet is different from a hop number corresponding to the transmission source information, the packet is judged to be malicious.

Patent document 1 Japanese Patent Laid-Open No. 2003-318987 bulletin    Patent document 2 Japanese Patent Laid-Open No. 2003-234784 bulletin
The Denial of Service attacks, widely observed in recent years, transmits a large volume of spurious communication packets targeted at specific enterprises and organizations to disrupt their services. Such (D)DoS attacks obstruct other regular business communications by consuming a major portion of the link bandwidth and/or the processing resources of the server. This obstructs the routine work, hinders users from accessing services, the poor response time results in longer connection hours which in turn leads to increase in invoice amounts.
A DoS attack is a method of sending a large number of unwanted packets to a target equipment. When the volume of incoming packets is more than the processing capacity of the target equipment, the equipment will not be able handle the regular communication packets from regular users. In this case the equipment is effectively disabled; users cannot access its services.
In this case, one can think of a service which monitors and records the value of the Source address field in the header part of the offending packet, refuses to receive any further packets from these offending addresses (DDoS attack sources) and also sends a termination signal to the source of the offending packet.
However, this type of a defense against DDoS becomes a problem when the attack comes from several sources
Attempting to sent a "refusal to receive" to the source of each of the (D)Dos packet sources would exhaust the resources of the local host and network.
Thus by sending packets with randomly spoofed source addresses, an effective (D)DoS attack is achieved; it cannot be filtered and cannot be blocked.
In Patent-1 for example, if a very large volume of mail has been received, the To address (destination address) included in the header part of the E-mail is overwritten to allow load distribution among mail servers.
Patent document 2 adopts the procedure that only emails which have a proper reply address are judged to be valid. So all mails will be checked for valid reply addresses. The faked sources will not be able to receive replies properly and will be rejected.

Unauthorized information detection system and unauthorized attack source search system


The invention relates to an interface apparatus for making input and output of appliances having display such as computer, word processor, information appliance and television, comprising recognizing means for recognizing the shape or move of the hand of an operator, display means for displaying the features of the shape or move of the hand recognized by the recognizing means as special shape in the screen, and control means for controlling the information displayed in the screen by the special shape displayed in the screen by the display means, wherein the two-dimensional or three-dimensional information displayed in the screen can be selected, indicated or moved only by changing the shape or moving the hand, so that the interface apparatus of very excellent controllability and high diversity may be presented.

The present invention relates to an interface apparatus for input and output of information apparatus such as computer and word processor and appliance having a display such as television.
In a kind of conventional interface apparatus, it is designed to display a cursor at a coordinate position detected by the mouse on a display screen, for adding some other information to the information in the display device, or changing or selecting the displayed information.
FIG. 30 shows an outline of this conventional interface apparatus. In FIG. 30, reference numeral 501 denotes a host computer, and 502 is a display, and virtual operation buttons 503, 504, 505 are displayed in the display 502 by the host computer 501. Reference numeral 506 represents a mouse cursor, and the host computer 501 controls the display so as to move in the screen in synchronism with the move of the mouse 507, on the basis of the moving distance of the mouse 507 detected by the mouse 507. As the user moves the mouse 507, the mouse cursor 506 is moved to the position of a desired virtual operation button in the display screen, and by pressing a switch 508 on the mouse 507, an operation button is selected so as to instruct action to the host computer 501.
In this conventional construction, however, the mouse or the input device is necessary in addition to the main body of the appliance, and a table or area for manipulating the mouse is also needed, which is not suited to portable information appliance or the like. Besides, by manipulation through the mouse, it is not a direct and intuitive interface.

Matsushita Electric Industrial Co., Ltd.


A remote access session is established between client and host computers with the assistance of a gateway. The gateway requests the host computer to send a plurality of data packets to different external addresses and monitors the network ports used for these outgoing packets. The gateway then uses the network port information to predict which port the host will use to transmit future outgoing data packets. A similar process is performed on the client computer. The gateway then directs the client computer to send further data packets to the network address and the predicted port of the host computer. Similarly, the host computer is directed to send further data packets to the network address and predicted port of the client computer. The computers are then directly connected together so that further data communications bypass the gateway.

In many situations, users have computer systems to which they must have constant access. A typical example is an office computer system that may have important files or sophisticated software running on it. This computer may be part of an office system or network that is not generally accessible outside of the office. However, the user may still want to use this computer when the user is at home or traveling. The solution is a remote access system that allows the user to connect to the office computer from another remote computer over a network, generally the Internet. Once connected, the user can enter keyboard and mouse commands into the remote computer and the commands will be transmitted to, and processed by, the office computer just as if the user had entered the commands into the office computer. Similarly, screen displays generated at the office computer are transmitted to, and reproduced by, the remote computer.
In traditional remote access solutions there are two components: the "host computer" (the computer being accessed) and the "client computer" (the computer used to access the host). The terms "host" and "client" can also be used to refer to the respective components of the remote access software. For example, host software runs on the host computer and client software runs on the client computer. The host software accepts a connection over a network, such as the Internet, from the client software, and after an initial authentication phase, a remote access session begins.
During a remote access session, the client computer can reproduce the screen display generated by the host. The client computer can also relay mouse and keyboard input for execution on the host computer. In addition, the client computer usually provides a user interface for accessing, manipulating and transferring files on the two systems that take part in the session.
In order to operate properly, a remote access system must be able to efficiently transfer information between the client and host computers and this efficient transfer requires a stable connection. If the client and host computers are directly connected to the network with static network addresses, establishing this stable connection is relatively easy. However, firewalls and NAT (Network Address Translation) routers that change or mask network addresses are becoming increasingly common, and dynamic network addresses are typically assigned to home users who access the Internet. Therefore, setting up a traditional remote access system in which the client computer directly contacts the host computer is not always practical as the difficulty of the task often exceeds the technical capabilities of the user.
In order to solve this problem, remote access systems introduce a third component, called a "gateway" that is connected to the network. The gateway is usually a combination of hardware and software that receives incoming connections over the network from both the client computer and the host computer. The gateway is often a server that is connected to the Internet and is typically located in a datacenter that is off-site for both the host computer and the client computer.
In a gateway-based remote access system, the host computer usually initiates a connection to the gateway, for example, when it boots up and thereafter maintains a constant connection with the gateway. The client computer usually connects to the gateway only when a user action initiates such a connection to begin a remote access session. When the gateway receives a connection request from the client computer, the gateway will authenticate the client computer, called a client "instance" and determine which host computer (called a host instance) the client instance has requested to contact (and which host instances the client instance is allowed to contact). When the requested host instance is identified, then the gateway will forward data between the respective client and host instances. In particular, whenever the host instance wishes to send data to the connected client instance, it sends the data to the gateway instead. Similarly, when the client instance wishes to transmit data to the connected host instance, it sends the data to the gateway. In either case, the gateway receives the incoming data and forwards it to the appropriate recipient.
A gateway solves the problem introduced by firewalls, NAT routers and dynamic network addresses, since neither the client computer nor the host computer attempt to contact each other directly; they both contact the gateway instead. Typically, the gateway is configured so that it is always accessible, usually through a common Internet protocol, such as HTTP or HTTPS. Thus, any computer that is configured to perform simple Internet-related tasks, such as browsing the World Wide Web, can be converted into a host computer and be a remote access target simply by installing and running the remote access host software.
However, there are two drawbacks to this typical prior art approach. First, there is increased data transmission latency. Each data packet traveling between the client computer and the host computer must be routed through the gateway. Since the gateway often is located remotely from both the client and host computers, the extra traveling distance will introduce unwanted delays in packet transit times. Second, the organization responsible for the gateway will incur high bandwidth costs as a large amount of data must travel through their infrastructure. Consequently, it would be beneficial to both the end users operating the client and host computers and the organization providing the gateway if the data flow between the client and host computers could be shifted so it avoids the gateway and travels directly between the client computer and the host computer.

This patent is subject to a terminal disclaimer.

Method and apparatus for remotely controlling a computer with peer-to-peer command and data transfer


When a laser beam machining command is detected in a pre-processing step in which a machining program is analyzed to create execution data for carrying out a laser beam machining operation, a drive for rotation command is outputted to a means for driving an impeller, and when it is detected that the rotational speed of the impeller has reached a predetermined speed within a predetermined time period, laser beam machining is started. If the rotational speed of the impeller has failed to reach the predetermined speed within the predetermined time period, an alarm is outputted. With this arrangement, the rotation of the impeller, which is necessary for the protection of optical components, can be controlled properly without the need of separately defining impeller rotation-related commands in the machining program.

Already known are laser beam machines, in which an impeller rotatable at high speed is arranged between an optical component forming a light path and a workpiece to be machined, to prevent contaminants such as sputters, oil mist, etc. produced during machining from adhering to optical components of the laser beam machine.
A principal part of a conventional laser beam machine of this type provided with an impeller rotatable at high speed is schematically shown in the sectional side elevation of FIG. 7. In the figure, a laser beam emitted from a laser oscillator is reflected at a mirror 2 in a machining head 1 toward a parabolic mirror 3 and then focused by the parabolic mirror 3 to irradiate a workpiece 4 to be machined. Also, an assist gas is introduced into the machining head 1 from supply means, not shown, through a pipe 5, and then supplied to the workpiece 4 after being throttled by a nozzle 6 mounted to a distal end of the machining head 1, thereby melting the workpiece 4 for machining by the interaction of the laser beam and the assist gas.
An impeller is arranged between the parabolic mirror 3, which is the endmost optical component for the laser beam emission, and the workpiece 4. The impeller 7 comprises a rotary shaft 9 to be rotated at high speed by a motor M as rotating means, and a plurality of vanes 10 attached radially to the rotary shaft 9, and repels contaminants 8 scattering from the surface of the workpiece 4, thereby preventing the contaminants 8 from adhering to the parabolic mirror 3. That is, the impeller 7 functions as a contaminant repellent member.
The impeller 7 is rotated by the motor M at such a high speed that the contaminants 8 scattering from the surface of the workpiece 4 during machining are struck by at least one vane 10 without fail while they pass through the rotating vanes 10 from below. The scattering contaminants 8 are thus surely repelled by the vanes 10, whereby the contaminants 8 are prevented from reaching the parabolic mirror 3.
In the conventional laser beam machine, however, rotation of the impeller 7 is controlled by means of general-purpose commands which are independent commands designed for ON/OFF control of external equipment; therefore, rotation of the impeller 7 cannot be controlled unless such commands are specified in a machining program.
The following is an example of a machining program for a conventional laser beam machine equipped with the impeller 7:
______________________________________ Line No. Statement ______________________________________ 1. L P[1] 100 mm/sec FINE 2. DO[1] = ON 3. LASER START 4. L P[2] 100 mm/sec CONT 100 5. L P[3] 100 mm/sec FINE 6. LASER END 7. DO[1] = OFF 8. [END] ______________________________________
In the above program, the statements of Line No. 1, 4 and 5 are declarations for commanding movements to target positions P[1], P[2] and P[3] which have respectively been defined in advance in the machining program, moving speeds, interpolation types and the like. The statement of Line No. 3 is a declaration for commanding a pre-flow (preliminary emission of the assist gas) and the start of emission of the laser beam. The statement of Line No. 6 is a declaration for commanding the end of emission of the laser beam and an after-flow (continued emission of the assist gas for a predetermined time), and the statement of Line No. 8 is a declaration for commanding the end of the program. The statements of Line No. 2 and 7 are independent general-purpose commands used for ON/OFF control of external equipment; in the above example, the commands are used for ON/OFF control of the motor M which controls the rotation of the impeller 7.
As long as contaminants 8 scatter from the workpiece during a laser beam machining, the motor M must be driven to rotate the impeller 7, and therefore "DO[1]=ON" must be defined before the statement "LASER START". Further, at a stage in the program where a laser beam machining for a specific part is ended or the entire machining program ends, "DO[1]=OFF" must be defined to stop the rotation of the impeller 7. Setting of these statements for ON/OFF control is left entirely to an operator who prepares the machining program. Thus, if the operator forgets setting the rotation start command "DO[1]=ON", laser beam machining is carried out with the impeller 7 stopped, thereby causing the fear of having the contaminants 8 adhere to the parabolic mirror 3. Even though the rotation start command is set at a proper location, contaminants 8 will not be fully repelled if laser beam machining is started before the rotational speed of the impeller 7 reaches a predetermined speed, possibly contaminating the parabolic mirror 3. Further, if the statements for ON/OFF control are frequently used in cases where laser beam machining is started after it is ascertained that the rotational speed of the impeller 7 has reached the predetermined speed, loss of time associated with increase of the rotational speed is accumulated, prolonging the overall machining time.

Method and apparatus for starting laser beam machining with optical component protection


A memory management method applicable to a data storage device is provided. The memory management method includes steps of: requesting a private memory space from a host; recording a reserved memory space given by the host; dividing a mapping table into a plurality of sub-mapping tables; determining whether a capacity of the reserved memory space is sufficient to store the sub-mapping tables; and if yes, uploading the sub-mapping tables to the reserved memory space via an interface logic.

In general, a data storage device includes a plurality of electronic components such as a control unit, a flash memory and a dynamic random access memory (DRAM), and such data storage devices have been widely used in a variety of data storage applications. While a data storage device provided with a DRAM has higher performance, it comes with higher hardware cost. In order to reduce costs, some data storage device manufacturers do not employ DRAM, but only use built-in static random access memory (SRAM) in the control unit as a data buffer.
However, since the capacity of the static random access memory built in the control unit is small, the performance of the data storage device is poor. Therefore, how to solve such problem has been a very important issue.

Data management method applicable to data storage device


One embodiment includes a network apparatus at a store for allowing digital amenities to be accessed at the store by a mobile device of a user. The network apparatus includes a network interface, a storage module to keep digital amenities and a computing module. The network interface can be designed to couple to the mobile device at the store, and to a computing device outside the store. The network interface can be designed to recognize the mobile device at the store based on a piece of software related to the store in the mobile device. The computing module can be designed to help the mobile device to access a first digital amenity from the storage module in view of the piece of software. Based on the access, a second digital amenity from the computing device can be pre-stored at the storage module.

Field of the Invention
The present invention relates generally to providing digital information, and more particularly to providing digital information for local access.
Description of the Related Art
Mobile devices have been spreading like wild fire. Even very young children are using them extensively. For years, the main application of mobile devices has been making phone calls. But with the proliferation of smart phones and other types of high-performance mobile devices, people have been using these devices for numerous other applications, such as playing games and watching videos. Another major development is the significant increase in the popularity of cloud computing, where the applications are stored in large data farms. Remotely accessing large bandwidth applications quickly has become a major burden to the networks.
Imagine you are at an Internet café trying to watch a movie from a video site via a cellular network. It is on a Sunday and a major game, such as the Super Bowl, is played. Assume a number of customers are using the network with their mobile devices to watch the game. At the same time, other customers are using the network to access and play high-speed video games that need a lot of bandwidth. Very likely, watching your movie would not be a satisfying experience because the amount of time to download your movie is too long. With limited bandwidth and reduced speed, other customers probably would not be in much better shape than you. Such annoyance will lead to customer dissatisfaction of the Internet café, adversely affecting their business.
It should be apparent from the foregoing that there is still a need for better information access via wireless devices.

Systems and methods to provide digital amenities for local access


A complemental series of handheld, tactile devices in kit form to assist in behavioral modification training techniques as well as utilizing the techiques of "resisted movement" and "successive approximation". Each positioner device is handheld, with one portion protruding from the lips and the other portion loosely fitting on the patient's hard plate. Different shapes are introduced to the tongue and lips on each respective device. A commonalty within the interdependent positioner devices is presented by an elongated palatal base defining a convex upper surface to engage the palate, a manipulable handle projecting from the base and the respective devices are further characterized in configuration. Variations in configuration such as elongation, thickenings and apertures of the positioners involve primary modification to the palatal base and adjacent interconnection of the handle, whereby upon activation the patient may exercise his tongue and lips to achieve consonantal speech sounds, perfect swallowing techniques, and aid in mastication.

In the normal function of speech production, mastication and swallowing, the functioning tissues of the oral cavity consist of mobile and nonmobile structures. Mobile structural elements include the tongue, cheeks, lips and the soft palate, whereas the nonmobile elements are the hard palate, mandible and teeth. The structures interact in specific combinations to produce speech, swallowing and mastication. For example, to initiate and execute a swallow, the teeth are brought together, lips are closed, intraoral pressure is built up, the anterior portion of the tongue presses against the anterior portion of the hard palate, and the tongue dorsum rolls posteriorly over the palate, which forces saliva or a food bolus into the pharynx. For speech articulation, precise contacts are needed whereby consonantal sounds are produced by touching the palate with the tongue in very specific accurate contact areas, and vowels by permitting varying air streams to flow. For mastication of food, all of the oral musculature are brought into play, viz.: the tongue, lips and cheeks aid in carrying the food bolus to the teeth, a food table, and in preventing the food from dispersing during trituration.
The tongue, being the major articulator of the oral structures, must adjust for each speech sound. The tip, the edges and the base thereof must move some times as fast as thirty times per second, and each movement must hit the target, hard palate and teeth, at which it is aimed, with extraordinary accuracy. If it misses by even a fraction of an inch, the wrong sound will be produced.
A mature speaker relies heavily for this performance on touch, sense of cutaneous pressure, and kinesthesis, awareness of position and movement of the speech mechanism. The reliance includes more than sensations of touch and kinesthesis, it includes the neural process by which one perceives his body in relation to objects and space. It is this perceptual system by which we are literally in touch with our environment. The "feel" of speech is thus vital for normal performance, and plays a role in the speech transmitter system.
The speech transmitter system has at least two roles. It has an afferent role in transmitting the code of nerve impulses generated by the speech receptors to central parts of the speech system. The system also has an efferent role in transmitting patterns of motor impulses from the central speech system to the peripherial speech effector system. The tactile-kinesthetic transmitter system is utilized in speech control and monitoring function. If these speech receptors are not receiving and converting stimulation into codes of nerve impulses, there is dysfunction of the transmission system and reduced significant impulses of the central speech regions. As a result, there occurs a reduction in transmission of the motor impulses that have been organized in higher centers. Thus, decreased sensory input leads to decreased motor output which results in inaccurate production of speech. Equally, sensory and motor controls are involved in the feeding and swallowing mechanisms.
An abnormal oral environment may show impairment due to abnormality of the nonmobile and or mobile elements. Whereas the palate, mandible or teeth are nonmobile, they may be amenable to correction or reconstruction by surgical and or prosthetic intervention, such as is not within the purview of the present invention. Abnormalities of the mobile features of the oral environment may be the result of structural deficiency, such as a cleft palate, other congenital anomaly or cancer surgery of the tongue as an acquired defect. Functional impairment also may be congenital, developmental or acquired. Development of abnormal muscle patterns leading to oral and facial imbalances is present in "tongue thrusting". Acquired neurological functional abnormalities are due to stroke and head injuries. When there are disturbances of the neurogenic motor controls for speech, individuals will experience difficulty with strength, range of motion and or coordination of movements of the tongue, lips and soft palate, resulting in unintelligible speech and or swallowing. Individuals experiencing these difficulties are named "dysarthric", their speech may sound slurred, dysrythmic or hypernasal.
Current speech pathology intervention, that is speech therapy, aims at improving strength, range of motion and coordination of speech musculature. One known method of improving the strength of contact, the range of motion and the accuracy of the tongue and lips is called the "resisted movement" technique. For example, if the individual has difficulty in raising the anterior part of the tongue, the clinician applies graded pressure in a downward direction to the tongue while requesting the individual to attempt to lift his tongue against this resistance. The procedure may succeed in increasing or triggering additional muscular activity and the tongue tip may show increased movement upwards. Three or four maneuvers by the clinician should precede each request for the patient to raise the tongue without the presence of the downward pressure. The device generally available and used is a tongue depressor. Such training requires individual sessions between patient and speech therapist. One objective of such tongue exercises is to improve the strength, range of motion and accuracy of the tongue-palate contacts for speech and swallowing. The available capacity must be directed into specific neuromuscular patterns to achieve different maximal accuracy. This is accomplished by helping the patient through a process of "successive approximations" until accurate tongue-palate contacts are made.
A second possible approach is the placement of a prosthesis which provides palatal augmentation to compensate for tongue movement dysfunction. These prostheses must be designed individually to fit the patient and the use of such prostheses is limited by several factors: First, the patient's teeth must be suitable to support a prosthesis properly; a maxillofacial prosthodontist is needed to design, produce and fit the device; and finally, the cost must be considered.

Devices used to improve speech, swallowing and mastication


A scale for fast determination of weights including a platform and a load cell transducer. Output of the transducer is converted to a digital signal, processed by a low pass digital filter, and weights computed as a function of the sequence of digital signals by means of an algorithm which compares a first estimate of the weight to the break points of a postal rate chart and uses the first estimate if it is not within a predetermined distance of a break point, and otherwise determines a second, more accurate estimate. The platform and transducers are combined to form a structure which does not have any significant resources below the cut-off frequency of the filter.

The present application and co-pending, commonly assigned U.S. applications Ser. Nos. 767,391, 07/768,793 and 07/768,143, filed on even date herewith, and U.S. Pat. No. 5,082,072, relate to a project of the assignee of the subject invention, and share common elements of disclosure.
The subject invention relates to scales and a method of operating such scales to rapidly determine weights. More particularly, the subject invention relates to postal scales and the like.
Postal scales are well known. Such scales weigh a mail piece, and determine the appropriate postage for that mail piece as a function of the weight.
Mailing systems where a mail piece is transported onto a postal scale, the appropriate postage is determined and used to set a postage meter, and the mail piece is then transported to the postage meter for imprinting with a postal indicia representative of the postage amount are also known. One such system is described in U.S. Pat. No. 4,742,878; issued: May 10, 1988; to the inventors of the subject invention. In such systems there is a constant need to increase the rate a which the scale can determine the weight of a mail piece in order that the throughput of the system can be increased.
U.S. Pat. No. 4,787,048; issued: Nov. 22, 1988; to the inventors of the subject invention, discloses one approach to decreasing the time required for a postal scale to determine the weight of a mail piece. The system disclosed in this patent takes advantage of the structure of postal rate charts, i.e., the function which relates the weight of a mail piece to the appropriate postage amount. As can be seen in FIG. 1, such rate charts provide a constant postage value for all weights between pairs of predetermined breakpoints. The system of the '048 patent takes advantage of this by use of an algorithm where a first estimate of the weight is made and used to determine the postage amount, unless the first estimate is within a predetermined distance of a breakpoint, in which case a second more accurate estimate is made.
Another approach to providing high throughput mailing systems has been the use of vibrating tray scales to determine the weight of a mail piece where the weight is estimated as a function of the frequency at which a scale tray vibrates after a mail piece is placed upon it and the system is excited. Such a system is described in the above mentioned, commonly assigned U.S. Pat. No. 5,082,072. While such prior art systems have proven generally satisfactory there is still a need for a scale system and method of operation which are suitable for use with load cell technology while still providing desired high throughput rates for mailing systems and the like.

Scale for determining the weight of an item within a predetermined time


A process for controlling layer spacing in mixtures of smectic liquid crystal compounds comprises the step of combining a liquid crystal composition having a net negative thermal layer expansion in at least one tilted (or latent tilted) smectic mesophase and a liquid crystal composition having a net positive thermal layer expansion in at least one tilted (or latent tilted) smectic mesophase, each of the compositions comprising at least one smectic or latent smectic liquid crystal compound. The process enables control of layer spacing in the tilted smectic mesophase(s) and thereby control or suppression of chevron layer geometry.

Devices employing liquid crystals have found use in a variety of electrooptical applications, in particular those which require compact, energy-efficient, voltage-controlled light valves, e.g., watch and calculator displays, as well as the flat-panel displays found in portable computers and compact televisions. Liquid crystal displays have a number of unique characteristics, including low voltage and low power of operation, which make them the most promising of the non-emissive electrooptical display candidates currently available. However, slow response can impose limitations for many potential applications. Speed of response becomes especially important in proportion to the number of elements which have to be addressed in a device, and this limits the potential use of some types of liquid crystals.
The modes of liquid crystal displays that are most extensively employed at the present time are twisted nematic (TN), supertwisted birefringence effect (SBE), and dynamic scattering (DS), all employing nematic or chiral nematic (cholesteric) liquid crystals. These devices are based upon the dielectric alignment effects (Freedericksz effect) of the nematic and/or chiral nematic liquid crystal (or mixtures of nematic or chiral nematic liquid crystals) upon application of an electric field. The average molecular long axis of the liquid crystal material takes up a preferred orientation in the applied electric field, the orientation of which is dependent on the sign of the dielectric anisotropy of the material or mixture, and this orientation relaxes upon removal of the applied electric field. This reorientation and relaxation is slow, on the order of a few milliseconds.
Although nematic and chiral nematic liquid crystals are the most extensively employed, there are liquid crystal devices that employ more highly ordered smectic liquid crystals. These devices are also based on the dielectric reorientation of the liquid crystals, and response times are on the order of milliseconds.
A recent advance in the liquid crystal art has been the utilization of tilted chiral smectic liquid crystals, which are also termed ferroelectric liquid crystals, in devices which give microsecond switching. Ferroelectric liquid crystals were discovered by R. B. Meyer et al. (J. Physique 36, 1-69 (1975)), and fluorine-containing ferroelectric liquid crystal materials have recently been developed (see, e.g., U.S. Pat. No. 4,886,619 (Janulis), U.S. Pat. No. 5,082,587 (Janulis), and U.S. Pat. No. 5,262,082 (Janulis et al.)). Ferroelectric liquid crystals possess a macroscopic electric dipole density which is perpendicular to the molecular tilt direction and parallel to the smectic layer planes. This provides a much stronger coupling of the molecular orientation to an applied electic field than is available via the dielectric anisotropy. Furthermore, the coupling is polar, so that reversal of an applied electric field can be effectively used to control molecular orientation.
A high speed optical switching phenomenon was discovered for ferroelectric liquid crystals by N. A. Clark et al. (see Appl. Phys. Lett. 36, 899 (1980) and U.S. Pat. No. 4,367,924). Clark developed a surface-stabilized ferroelectric liquid crystal display (hereinafter, SSFLCD) which enabled bistable operation not possible in any of the device applications described above. The SSFLCD has been recognized as having high potential in regard to information content, viewing angle, contrast ratio, and switching time, but development of the SSFLCD has been hindered by problems with defects in the liquid crystal layer structure. These defects arise due to layer shrinkage upon cooling (through the temperature ranges associated with the tilted smectic mesophases) and the resulting formation of a "chevron" layer structure (see, e.g., the discussion by T. P. Rieker et al. in Phys. Rev. Lett. 59, 2658 (1987) and Ferroelectrics 113, 245 (1991), as well as the discussion by Y. Ouchi et al. in Jpn. J. Appl. Phys. 27, L1993 (1988)). Since the defects result in, e.g., a poor contrast ratio and unstable bistability, researchers have earnestly sought means for avoiding the formation of a chevron structure.
European Pat. Publication No. 405,868 (Fujitsu Limited et al.) discloses a liquid crystal composition which exhibits a bookshelf structure. The composition comprises a mixture of ferroelectric (i.e., tilted chiral smectic) liquid crystal compounds, the mixture containing a predetermined amount of a chiral ferroelectric liquid crystal compound having a specific naphthalene ring structure.
Takanishi et al. describe (in Jpn. J. Appl. Phys. 29, L984 (1990) and Mol. Cryst. Liq. Cryst. 199, 111 (1991)) the spontaneous formation of a quasi-bookshelf layer structure in new ferroelectric liquid crystals derived from a naphthalene ring.
Mochizuki et al. obtain both bookshelf and quasi-bookshelf layer structures by using a "naphthalene base liquid crystal mixture with a rubbed polymer orientation films panel" (see Ferroelectrics 122, 37 (1991)).
Research Disclosure 34573 (1993) discloses ferroelectric liquid crystal mixtures having a high percentage of perfluoroether-containing liquid crystal compounds. The mixtures exhibit a spontaneous bookshelf layer structure and have been formulated with negative layer expansion materials to reduce temperature dependence of the layer thickness.
A bookshelf structure obtained by application of an electric field has been reported by M. Johno et al. in Jpn. J. Appl. Phys. 28, L119 (1989) and is also described in U.S. Pat. No. 5,206,751 (Escher et al.).
A bookshelf structure obtained by oblique vapor deposition techniques has been reported by A. Yasuda et al. in Liquid Crystals 14, 1725 (1993).

Process for controlling layer spacing in mixtures of smectic liquid crystal compounds

Minnesota Mining and Manufacturing Company


Systems and methods for managing data replication between data storage resources with differing capabilities. A system can check whether capabilities of a primary data storage system are different from capabilities of a secondary data storage system. Such checking can be performed based on a release version of each of the primary and secondary data storage systems. If the capabilities of the respective data storage systems are determined to be different, then the system can make a determination as to whether or not the difference can be rectified. If the difference can be rectified, such as by enabling/disabling certain features of the primary and/or secondary data storage system, then the system can perform such a rectification and proceed with provisioning of data to be replicated. If the difference cannot be rectified, then the system can prevent the provisioning of the data and notify an administrator of the data storage systems.

The present application relates generally to data storage systems and methods, and more specifically to systems and methods of managing a replication of data between data storage resources with differing and/or incompatible capabilities.
In recent years, activities related to creating, gathering, storing, and/or accessing computer data have become increasingly vital to commercial, academic, and governmental organizations. To protect such computer data from data storage errors, data corruption, and/or data loss due to hardware failures, software failures, and/or natural or man-made disasters, such organizations have generally implemented some level of data protection. A conventional system for implementing such data protection can employ a data storage technique known as data replication, in which an organization's data at a primary storage site are copied and stored at a secondary storage site. For example, the secondary storage site may be in the same physical location as the primary storage site, or in a physical location that is remote from the primary storage site. The conventional system can be configured to perform such data replication automatically in response to a deficiency at the primary storage site, such as reaching a low free-storage threshold, detecting a failure of an internal component, etc. In this way, a burden or opportunity for error placed on a user of the conventional system can be reduced.

Apparatus and methods for inter-version replication checking


Embodiments of a processor are disclosed for performing arithmetic operations on variable-length and fixed-length machine independent numbers. The processor may include a floating point unit, and a logic circuit. The number unit may be configured to receive an operation, and first and second operands. Each of the first and second operands may include a sign byte, and multiple mantissa bytes, and may be processed in response to a determination that the operands are fixed-length numbers. The logic circuit may be further configured to perform the received operation on the processed first and second operands.

Technical Field
The embodiments disclosed herein relate to integrated circuits, and more particularly, to processors and floating point number units.
Description of the Related Art
Processors are used in in a variety of applications ranging from desktop computers to cellular telephones. In some applications, multiple processors or processor cores, may be connected together so that computation tasks may be shared among the various processors. Whether used individually, or as part of group, processors make use of sequential logic circuits, internal memory, and the like, to execute program instructions and operate on input data, which may be represented in a binary numeral system. Processors are often characterized by the size of individual data objects, such as, 16-bits, for example.
Modern processors typically include various functional blocks, each with a dedicated task. For example, a processor may include and instruction fetch unit, a memory management unit, and an arithmetic logic unit (ALU). An instruction fetch unit may prepare program instructions for execution by decoding the program instructions and checking for scheduling hazards, while arithmetic operations such as addition, subtraction, and Boolean operations (e.g., AND, OR, etc.) may be performed by an ALU. Some processors include high-speed memory (commonly referred to as "cache memories" or "caches") used for storing frequently used instructions or data.
As the size of data objects increased, numbers could be represented in different formats allowing for greater precision and accuracy. The processing of such data objects may require multiple program instructions in order to complete a desired function. For example, in some bit slice applications, by executing multiple program instructions over multiple processing cycles on a processor designed process 16-bit data objects, a 32-bit data object may be processed.
Some processors may employ coprocessors, or other dedicated hardware, to perform more complicated arithmetic operations, such as, floating-point multiplication for example. Such coprocessors may be fabricated on a separate integrated circuit chip, or may be included as a separate functional block within a processor. While the use of dedicated arithmetic hardware may result in improved computation performance in some applications, the format of numbers being processed may be specific to a given hardware implementation. In such cases, additional program instructions may be required to allow different processor hardware to operate on a common set of data objects.

Processing fixed and variable length numbers


A color deleting apparatus includes an image reading device for reading a color original document and for producing R, G, B signals for each pixel, a monochrome generator for producing a gradiation image signal based on the R, G, B signal, a color judging circuit for judging whether the R, G, B signal is carrying chromatic information or achromatic information, and a deleting circuit for deleting the gradiation image signal when the color judging circuit judges that the R, G, B signal is carrying chromatic information. Thus, the colored areas in the color original document are completely deleted in the copied image.

1. Field of the Invention
The present invention relates to a color deleting apparatus for use in a digital color copying machine, a color facsimile machine, or the like, to delete color markings from an original document.
2. Description of the Prior Art
Recent digital color copying machines are equipped with various editing functions in addition to the original copying function to reproduce an original color document with high precision. One editing function is, for example, to color the original document copied by a conventional monochrome copying machine, or to change a specific color of the original document to a different color.
In addition to the above, there is a desire to change a copy from a color marked document to a non-color marked document. In other words, there is a desire to provide such a copying machine that when a document with color markings or with color stamps is set, a copied document with no color markings or no color stamps is reproduced. Such a color deleting function is desired to be added to the conventional copying machines so as to easily delete the chromatic area of the document except for the achromatic area.
The conventional copying machines have not been provided with the above-noted color deleting function by simply deleting the chromatic area from the document, but instead, the color deleting function is achieved by the use of the aforementioned color changing function, as explained below.
In FIG. 8, a block diagram of a prior art color image processing apparatus is shown, wherein reference numbers 201, 202, 203 and 204 represent an image reading means, a position indicating means, a detecting means and a color changing means, respectively.
The conventional color image processing apparatus shown in FIG. 8 operates in the following manner.
The image reading means 201 reads a color image of the original document using an image sensor such as a CCD (charge-coupled device), and outputs color data of decomposed three colors (digital data). The position indicating means 202 which is comprised of a digitizer and the like can input the positional data of a pixel at one arbitrary point by designating the one point within the area having an approximately constant density of the color image. The detecting means 203 detects the maximum and minimum values of the density of N.times.N pixels in the periphery of the pixel designated by the position indicating means 202 in the color data of three colors. The color changing means 204 compares the maximum and minimum values detected by the detecting means 203 with the color data of three colors supplied from the image reading means 201, thereby determining whether the pixel is within the area of the designated density, and changing the color of the area to a different color depending on the determining result. Accordingly, in the prior art color image processing apparatus, a color is deleted by indicating the color that is desired to be deleted from the original document and changing it to white. Such a copying machine is disclosed, for example, in Japanese Patent Laid-Open Publication 62-192862. Other prior art copying machines are disclosed in Japanese Patent Laid-Open Publication 62-131667 and in European Patent Publication EP 0,363,146 A2.
According to the aforementioned method, however, if a plurality of colors are desired to be deleted, the designation of the color should be repeatedly carried out one by one.
Moreover, only the color within the designated range of density which is between the maximum and minimum detected density can be deleted in the aforementioned method, and the color beyond the designated range cannot be deleted.
Furthermore, when the color copying machine is of a type which carries out four sequential copying operations of yellow, cyan, magenta and black images, the forming of a monochromatic copy takes a relatively long time.

Image copying apparatus having means for deleting color portions of an original image


This disclosure discloses a touch display screen, a manufacturing method thereof and a display device. The touch display screen comprises: an opposite substrate, an array substrate, and a liquid crystal layer located between the opposite substrate and the array substrate, a side of the opposite substrate facing the liquid crystal layer being provided with a black matrix. The touch display screen further comprises: a first touch electrode, an insulating layer and a second touch electrode arranged in stack successively at a side of the opposite substrate back to the liquid crystal layer. The first touch electrode and the second touch electrode are located within an area corresponding to the black matrix respectively. The first touch electrode comprises a plurality of first touch sub-electrodes distributed along a first direction. The second touch electrode comprises a plurality of second touch sub-electrodes distributed along a second direction perpendicular to the first direction.

With rapid development of the display technology, the touch panel has spread all over people's life gradually. The touch panel can be divided into Add on Mode Touch Panel, On Cell Touch Panel and In Cell Touch Panel according to the composition structure.
At present, a screen with the Add on Mode Touch Panel is a liquid crystal display screen with the touch function constituted by producing the touch screen and the liquid crystal display screen separately and then fitting them together. The completion of an entire screen with Add on Mode Touch Panel needs several turnovers of the primary product and two or more processing, and the manufacturing process is complex. Hence, in addition to the relatively high overall turnover cost and the processing cost, because the touch screen and the liquid crystal display screen are not integral, the precision problem exists when the two are fitted on a particular product line. Moreover, in the touch screen, the indium tin oxide (ITO) is generally used as the material of the touch driving electrode and the touch sensing electrode and they are manufactured on the protective glass. In such a way, although the transparency of the ITO can be utilized without considering the wiring position thereof, in fact, the ITO may result in absorption and reflection to the emitted light from the liquid crystal display screen, and the problems of high light reflectivity and low transmissivity may occur. In addition, due to the influence of the air gap between the liquid crystal display screen and the protective glass and the material of the glass, the light transmissivity will be reduced. Moreover, the thickness, the quality and the use cost of the product will also be increased by using the protective glass.

Touch display screen, a manufacturing method thereof and a display device

BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.