Aspects of the disclosure provide a method for semiconductor wafer manufacturing. The method includes utilizing a subset of lower level masks in a mask set to form multiple modular units of lower level circuit structures on a semiconductor wafer. The mask set includes the subset of lower level masks and at least a first subset of upper level masks and a second subset of upper level masks. The first subset of upper level masks defines intra-unit interconnections. The second subset of upper level masks defines both intra-unit interconnections and inter-unit interconnections. The method further includes selecting one of at least the first subset of upper level masks and the second subset of upper level masks based on a composition request of a final integrated circuit (IC) product and utilizing the selected subset of upper level masks to form upper level structures on the semiconductor wafer.

The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
In the semiconductor industry, circuit designers design a product via a plurality of stages. In an example, the circuit designers decide system-level functional specification and architectures of the product in a system design stage. Further, the circuit designers convert the system-level functional specification into a register transfer level (RTL) description in a RTL design stage. Then, the circuit designers create circuit layout with patterns to define circuits in a physical design stage. Based on the circuit layout, a set of photomasks is generated. The photomasks are used in a semiconductor manufacturing facility to define structures corresponding to the circuits on semiconductor wafers.

Method to produce a semiconductor wafer for versatile products


Methods, systems, and storage media are described for adjusting a bitrate for a data stream according to user consumption of the data stream. In embodiments, a computing device may determine a virtual resolution based on an absolute resolution of a display device associated with the computing device and a relative display size of the display device. The relative display size may be based on a user position and an absolute display size of the display device. The computing device may request data stream segments of a data stream encoded at a bitrate based on the virtual resolution, and provide the data stream segment for display on the display device. The virtual resolution may also be based on user attributes and/or device attributes. Other embodiments may be described and/or claimed.

As computing devices become more prevalent, and as more devices become connected to the internet, network throughput and/or bitrate optimization is becoming more important. Most throughput and/or bitrate optimization technologies are implemented on the network operator's end, such as by optimizing the physical network design and/or network topology or by optimizing how data flows to network consumers. However, most throughput and/or bitrate optimization technologies are not implemented at the network consumer's end.
Additionally, most network consumers are usually offered a subscription or data plan that is expressed as a maximum data transfer rate in bits per second. For example, when a user subscribes to a 100 Megabit per second (Mbps) plan, not only does the user often get a lower data transfer rate, especially during peak usage times, but the subscription usually does not guarantee lagless or seemingly delay free data streaming. The reasons for this are based on the physical network design and/or network topology. For example, various cables and/or wires used to communicate data have a finite length and diameter, which limits the amount of data that may be transferred over the cables and/or wires. Furthermore, with wireless networks, network congestion and/or environmental factors often limit the amount of data that may be transferred to a computing device. Current techniques for mitigating network congestion or otherwise allocating network resources include the use of complex algorithms for managing traffic, such as monitoring traffic types, shifting network resources between subscribers, prioritizing the allocation of network resources to traffic types that are more sensitive to delays, and/or collision avoidance schemes.
However, the current techniques for mitigating network congestion or otherwise allocating network resources do not typically account for a user's experience and/or interaction with user context when adjusting or allocating network resources.

Adaptive data streaming based on virtual screen size


A method, system, and manufacture for authorizing an untrusted client device for access on a content management system. The content management system receives a request from an untrusted client device to access content on the content management system. The content management system sends an authentication key to the untrusted client device. The content management system then receives the authentication key from a trusted client device. Based on the matching authentication key, the content management system transmits data to the untrusted client device in accordance with any additional instructions that the trusted client device may have sent.

Synchronized online content management systems allow users to easily store data online and share the data without having to worry about transporting storage media such as CD-ROMs, flash drives, or memory cards between two different computing devices. One of the promises of cloud computing is that once you store your data in the "cloud," you can access the data with any device you want from anywhere you want. People frequently use these cloud-based online content management systems to access data from their personal computers, mobile phones, and tablet devices. However, being able to access all of your data from every device you may come across may not be ideal in certain situations. Some computing devices might be inherently insecure in their design. Other devices are shared by strangers who cannot always be trusted. Still other devices might have been already compromised by malware or a computer virus. Thus, a user might not want to expose all of her data, which may include personal, sensitive, or confidential information, to those devices that she cannot completely trust.
For example, a library customer who uses a publicly shared computer terminal, a lecturer who needs to deliver a presentation on an unfamiliar laptop computer at an academic conference, and a subway commuter who forgot to bring his own smart phone and now has to borrow a stranger's phone to access an important business document, all have one thing in common: they may all feel uncomfortable about potentially exposing sensitive information to an unfamiliar and untrustworthy computing environment. In each of these situations, the user cannot be entirely sure that the device that he or she is using for the first time is securely designed, is not shared by exploitative users, and has not fallen prey to malicious software.
The current solution for situations like these is simply to be wary of these pitfalls and not access sensitive or confidential data when the device cannot be reasonably trusted. This is because most content management systems do not allow access management on a per-device basis. In other words, it is often impractical or impossible to control access with a fine-grain precision when it comes to assigning different access privileges to different devices. Therefore, the need for a more versatile, robust, and convenient method of authorizing untrusted computing devices is paramount.
In addition, for non-traditional computing devices, such as smart televisions and smart appliances, which offer only a very limited user interface, it can often be very cumbersome and unwieldy to pair those devices to a content management system. For example, armed only with a remote control and lacking a full-size keyboard, televisions are notoriously challenging to interact with, especially when the users need to input complex information such as a username and password. Sharing data with such limited-purpose devices can be difficult.

Authorizing an untrusted client device for access on a content management system


A Direct Memory Access (DMA) controller incorporates a memory test circuit that executes, using a dedicated system, repetitive memory read and write test phases such as are executed in conventional memory test methods by programs.

1. Field of the Invention
The present invention relates to circuits for testing a memory, in particular a Random-Access Memory (RAM) in a microprocessor system.
2. Discussion of the Related Art
For testing a memory, there are several methods for detecting different types of abnormal situations, such as memory cells stuck at a determined value, shorted or open address or data lines, etc. By testing a memory using several methods and by adequately analyzing the results, an exhaustive memory test can be performed, thus allowing localisation of all abnormal situations. Test methods are described in IEEE Transactions on Computers, Vol. C-27, No. 6, June 1978, "Efficient Algorithms for Testing Semiconductor Random-Access Memories". In this document, various works on test methods are referred to.
FIG. 1 schematically represents a conventional microprocessor system. Such system includes a Central Processing Unit (CPU) 1, a Read-Only Memory (ROM) 2, a Random-Access Memory (RAM) 3, and a Direct Memory Access (DMA) controller 4, that are connected to a microprocessor bus comprised, for example, of a 16-line data bus D, and a 24-line address bus A.
Conventionally, in order to test the RAM 3, microprocessor 1 executes a test program whose instructions are stored in ROM 2. This test program is executed, for example, at power on of the system, or at regular time intervals.
When testing the RAM 3, microprocessor 1 generally executes, for each cell of the RAM to be tested, at least one write and one read in the RAM together with several instruction reads from ROM. During a memory test, a large number of accesses are made to ROM, which causes the test to be substantially slowed down because accesses in ROM are particularly time consuming.
In practice, an exhaustive test of a 2-megabyte RAM, which is a common value, lasts for approximately four hours; during this period, the microprocessor cannot be used to perform other tasks. Hence, such a test is executed as seldom as possible.
Additionally, a program that executes an exhaustive memory test occupies approximately 20 kilobytes, which is a substantial value involving non-negligible extra cost in mass produced microprocessor systems.
In order to accelerate test programs, one could envisage storing the instructions of the test program in a battery backed-up RAM. However, such an approach is expensive and much time would still be spent on the numerous instruction reads.
It would also be possible to test memories without resorting to a test program but by using a hard wired system in the form of a specific test circuit connected to the microprocessor bus. However, it is not desirable to provide an additional integrated test circuit that has to be inserted on a microprocessor board, because such a solution would involve extra costs for mounting and designing microprocessor boards.

Circuit for testing microprocessor memories


A spoiler arrangement for a motor vehicle includes a carrier configured to attach on a body of the motor vehicle. At least one lamella is arranged on the carrier and includes a longitudinally extended flexible and elastic bending rod and at least one surface segment. The surface segment is connected to the bending rod along a side edge.

Adjustable spoiler arrangements for motor vehicles are well-known in the prior art. They are used to adequately adjust the wind resistance of a motor vehicle and, for example, are supposed to perform a spoiler or aerodynamic function only within a predetermined speed range of the motor vehicle. In a comparatively low speed range, a spoiler extended to its action position can be rather hindering. When driving in a comparatively high speed range, movable spoiler arrangement can be provided not only at the rear but also at the vehicle front, by means of which the flow properties and the wind resistance of the motor vehicle can be improved and optimized.
Popular movable spoiler arrangements comprise a plurality of movable, e.g. slidable or pivotable components, which frequently are to be adequately moved and adjusted by means of separate drives, e.g. by means of actuating drives
For example, form DE 10 2012 020 738 A1, a flexible front spoiler system having a pneumatic actuation is known.


A fluorescent lamp device includes a transparent sealed container which is filled with a working gas, an electron emitting unit which extends into the container and which is operable to emit electrons that interact with the working gas to generate short-wave ultraviolet energy, and a light emitting member which is disposed in the container and which is made of an insulator material. The light emitting member has an external surface coated with a layer of fluorescent material that converts the ultraviolet energy into visible light.

1. Field of the Invention
This invention relates to a fluorescent lamp device, more particularly to a fluorescent lamp device which provides a stronger light output per unit area.
2. Description of the Related Art
Referring to FIG. 1, a conventional fluorescent lamp device is shown to comprise a transparent sealed glass tube 11. The glass tube 11 has an inner peripheral surface coated with a layer of fluorescent material 12, such as a fluorescent metal salt or a phosphorescent metal salt, and is filled with a low pressure working gas 13 that contains mercury vapor. A pair of electrodes 14, 15 are installed respectively at two opposed ends of the glass tube 11 and are connected to a ballast 16 which provides a starting voltage and which limits current flow and to a starter 17 which is used to heat the electrodes 14, 15.
When the lamp device is energized, a low-current glow discharge forms in the starter 17. The heat from this glow is sufficient to form a short circuit through the starter 17. The full output voltage of the ballast 16 then causes current to flow through the electrodes 14, 15, thereby heating and causing the electrodes 14, 15 to emit electrons. At this time, the starter 17 is open circuit and cools. The electrons interact with the mercury atoms of the working gas 13 so as to generate short-wave ultraviolet energy. The fluorescent material 12 on the inner peripheral surface of the glass tube 11 converts the short-wave ultraviolet energy into visible light. However, the intensity of the visible light emitted out of the glass tube 11 is reduced due to the shielding effect of the fluorescent material 12 on the glass tube 11. To increase the intensity of the visible light, the length of the glass tube 11 must be increased so as to increase the amount of the fluorescent material 12. However, increasing the length of the glass tube 11 results in occupying space and in inconvenience of assembly. In addition, it is noted that a conventional fluorescent lamp .device is usually provided on a ceiling such that the upwardly projecting visible light is useless. Although the provision of a reflector on the conventional fluorescent lamp device for reflecting the upwardly projecting visible light has been proposed, the reflector is distant from the glass tube so that the efficiency of the reflector is reduced.

5F, No. 17, Alley 4, Lane 217, sec. 3, Chung-Hsiao E. Rd.


This invention is applied to dual mode provided receiver capable of coinciding with both TDMA system and the non-TDMA system so as to provide a DC offset cancel circuit preferable for each communication method having a compact structure. In case where a predetermined time slot is allocated as an offset quantity detection time in the TDMA system, a first feedback loop is activated and corresponding to detection signals corresponding to differential output signals OUT, XOUT by a comparator 2, a detection result is updated in the holding section 3 according to a strobe signal STB and held therein. Output signals from the holding section 3 are fed back to an amplifier 1 through a selection section 5 and a DC offset is cancelled out. In case where the offset quantity is detected successively, a second feedback loop is activated and then, detection signals from the comparator 2 are identified by a filter section 4, and fed back to the amplifier 1 through the selection portion 5, so that the DC offset is cancelled out.

1. Field of the Invention
The present invention relates to cancellation of DC offset component that is likely to be included in an output signal, more particularly to a receiver used for mobile communication such as cellular phones.
2. Description of Related Art
Mobile communication appliances such as cellular phones rapidly prevailing in recent years need to meet demands on miniaturization, weight saving, and multi-function design. To meet such demands, in place of superheterodyne system conventionally used for a radio processing section, there has been widely employed direct conversion system that does not require an intermediate frequency signal (IF signal) and directly converts a radio frequency signal (RF) into a baseband signal. Since this system does not require a section for processing an IF signal, circuit scale of it can be compressed more than that of the superheterodyne system, which contributes to miniaturization, weight saving, and multi-function design of mobile communication appliance kind.
However, since the direct conversion system directly converts an RF signal into a baseband signal, this system cannot remove unnecessary DC offset components whereas DC offset components in an IF signal were removed by a band-pass filter or the like in the superheterodyne system. Accordingly, the direct conversion system requires a particular circuit for canceling DC offset.
FIG. 8 through FIG. 11 show examples of DC offset cancel circuits conventionally used. Out of those, examples of circuit structure shown in FIG. 8 through FIG. 10 are suitable for communication system such as called FDMA (frequency division multiple access), CDMA (code-division multiple access) or the like. FDMA and CDMA are communication system for receiving RF signals that succeed in terms of time. On the other hand, circuit structure shown in FIG. 11 is suitable for communication system such as called TDMA (time division multiple access) or the like. TDMA is communication system for receiving RF signals that do not succeed in terms of time. In the following descriptions, against TDMA system, communication system for receiving RF signals that succeed in terms of time will be mentioned as non-TDMA system.
It should be noted that FDMA (frequency division multiple access) is communication system that different frequencies are allocated to respective channels and CDMA (code-division multiple access) is communication system that different codes are allocated to respective channels. In both FDMA and CDMA, receiving signals succeed in terms of time. On the other hand, TDMA (time division multiple access) is communication system that channels are allocated to time slots each of which has its predetermined time length and RF signals circulate in each channel. Accordingly, receive operation is conducted in predetermined time slots only.
FIG. 8 shows circuit structure 110 directed to first prior art. In the circuit structure 110, there are provided highpass filters (HPF) 101, and 102 in signal paths that lead to differential output signals OUT, XOUT from differential input signals IN, XIN, respectively, through an amplifier (AMP) 11, whereby DC offset is cancelled. In FIG. 8, the highpass filters (HPF) 101, and 102 are provided at input side and output side of the amplifier (AMP) 11, respectively, whereby DC offset components are cut out in double. Other than this manner of DC offset cancellation, the first prior art can be structured with either one of the highpass filters (HPF). There are structured the highpass filters (HPF) 101, and 102 including capacitor elements in the signal paths, and, on demand, further including resistance elements between output side of the capacitor elements and reference voltage. In the circuit structure 110, DC offset is filtered in a form of analog signal and finally cancelled. Circuit structure as such is suitable for non-TDMA system where signals that succeed in terms of time are dealt.
FIG. 9 shows circuit structure 120 directed to second prior art. In the circuit structure 120, differential output signals OUT, XOUT are integrated by an integration circuit 103 and fedback to differential input signals IN, XIN, whereby DC offset is cancelled. The integration circuit 103 is constituted by a comparator 12 and a time constant circuit that is constituted by connecting two couples of a resistance element and a capacitor element (R101 and C101, R102 and C102) between differential input side and differential output side of the comparator 12. Differential output signals OUT, XOUT inputted through the resistance elements R101 and R102 include AC signal components as AC component and DC offset component as DC component. However, the integration circuit 103 integrates the differential output signals OUT, XOUT depending on time constant determined by the two couples of resistance element and capacitor element (R101 and C101, R102 and C102) and only predetermined DC offset components of those signals are feedback to an amplifier (AMP) 11. Although FIG. 9 shows structure that a feedback signal is directly fedback to differential input signals IN, XIN, it is possible to feedback a feedback signal to a point other than the input signals IN, XIN if it is a point capable of adjusting DC offset components of the amplifier (AMP) 11. For example, a feedback signal can be feedback to a bias current source to an input-stage differential pair of the amplifier (AMP) 11. Circuit structure as such is suitable for non-TDMA system where signals that succeed in term of time are dealt.
It should be noted that the comparator 12 is a circuit that has a predetermined gain and outputs a signal depending on differential signals of differential output signals OUT, XOUT.
FIG. 10 shows circuit structure 130 directed to third prior art. In the circuit structure 130, differential output signals OUT, XOUT are compared at a comparator 12 and differential output signals as comparison result are fedback to an amplifier (AMP) 11 through a lowpass filter constituted by two couples of a resistance element and a capacitor element (R103 and C103, R104 and C104), whereby DC offset is cancelled. The differential output signals OUT, XOUT and the comparison result include signal components as AC component and offset components as DC components. However, only predetermined DC offset components are extracted by the lowpass filter 104 and fedback to the amplifier (AMP) 11. Different from the case of FIG. 9, FIG. 10 is structured such that a feedback signal is feedback to an internal circuit such as bias current source to an input-stage differential pair of the amplifier (AMP) 11. The circuit structure 130 filters analog signals through the lowpass filter 104 and calculates a correction value of DC offset components. Circuit structure as such is suitable for non-TDMA system where signals that succeed in term of time are dealt.
FIG. 11 shows circuit structure 140 directed to fourth prior art. In the circuit structure 140, differential output signals OUT, XOUT are compared at a comparator 12 and then, converted into digital signals by an AD converter 18. To these digital signals, digital processing is applied by a digital signal processing circuit (DSP) so as to output correction signals against DC offset components. Since the correction signal is a digital signal, the signal is converted into an analog signal by a DA converter 17 and fedback to an amplifier (AMP) 11. In case a predetermined time slot in a predetermined communication time cycle is set as offset-quantity detecting time like TDMA system, a correction value obtained by signal processing and calculation is stored in the digital signal processing circuit (DSP) 13 or the DA converter 17, whereby DC offset is cancelled. In the circuit structure 140, an analog signal is converted into a digital signal through signal processing and a correction value and then, a correction value of DC offset component is calculated. Circuit structure as such is suitable for TDMA system where a predetermined time slot in a predetermined communication time cycle is provided as offset-quantity detecting time and a correction value of DC offset components in the next communication time cycle is determined during this predetermined time slot.
Furthermore, as communication system of mobile radio communication appliances, different communication systems actually diversify region by region: PDC, a kind of FDMA, is prevailed in Japan whereas GSM, a kind of TDMA, is prevailed in Europe. Furthermore, there has been raised and considered W-CDMA system as the next generation communication system. Therefore, there is possibility that another different communication system will coexist with the W-CDMA system while a transitional period to the next generation communication system. So, it is considered convenient that a single communication appliance is compatible with pluralities of communication system. Due to demand as such, there have been proposed dual-mode-structured receivers capable of coping with both communication system, namely, TDMA system and non-TDMA system. FIG. 12 specifically shows circuit structure capable of changing over switches of a DC offset cancel circuit. In FIG. 12, selection circuits 105 and 106 change over switches like that in case of TDMA system, the DC offset cancel circuit uses the circuit structure 140, whereas in case of non-TDMA system, the DC offset cancel circuit uses the circuit structures 110 and 120 or 130.
However, the dual-mode-structured DC offset cancel circuit having changeover-circuit structure as shown in FIG. 12 must include both the DC offset cancel circuit 140 suitable for TDMA system and the DC offset cancel circuits 110, 120, or 130 suitable for non-TDMA system. The dual-mode-structured DC offset cancel circuit further requires the selection circuits 105, 105, 106, 106 that control and select between the two types of DC offset cancel circuits and a control circuit (not shown) for outputting control signals. Inclusion of such circuits makes circuit scale large, which is problematic for mobile communication appliances such as cellular phones for which miniaturization and weight saving design are required.
Furthermore, it is conceivable to apply the circuit structure 110 through 130 suitable for non-TDMA system, directed to first through third prior art, to TDMA system. However, for securing propagation of signal components without being cut out in non-TDMA system, only DC offset components must be cut out by setting frequency band of the highpass filters 101 and 102 in the first prior art to sufficiently low frequency. Furthermore, for securing propagation of signal components, only DC offset components must be fedback as correction value in such a manner that time constant of the integration circuit 103 of the second prior art is set sufficiently large or, frequency band of the lowpass filter 104 of the third prior art is set sufficiently low. Any of these countermeasures intends to make a capacitor value of the capacitor elements C101 through C104 sufficiently large. Therefore, in case the circuit structure 110 through 130 are used for TDMA system where a predetermined time slot in a predetermined communication time cycle is allocated to each channel and a signal is received only while the predetermined time slot, rising time of a signal received during a predetermined time slot is likely to be long. Due to long rising time, there is fear that the circuit structure 110 through 130 cannot keep up with high-speed operation, which is problematic.
Vice versa, it is also conceivable to apply the circuit structure 140 suitable for TDMA system, directed to the fourth prior art, to non-TDMA system. However, in TDMA system, a predetermined time slot in a predetermined communication time cycle is allocated to each channel for receiving a signal as well as other predetermined time slot is allocated for offset quantity detection time, and operations of each channel and offset quantity detection are conducted in predetermined time slots allocated for each of them. Therefore, such communication system is hard to apply to non-TDMA system where special time for offset quantity detection cannot be secured. This is problematic.


A power-saving circuit for a digital video display device includes a TMDS driving unit converting a TMDS data signal and a TMDS clock signal, a display driving unit driving a display unit based on the horizontal/vertical synchronous signals and the digital video signal input from the TMDS driving unit, a clock signal detecting unit outputting a first or a second level of a clock detecting signal depending on the TMDS clock signal, a controller outputting a first-level of a power-saving signal when the first level clock detecting signal is input, and outputting a second level of power-saving signal when the second level clock detecting signal is input, and a power supply unit supplying a voltage to respective components, and cutting off the supply of the voltage to respective components depending on the level of the power-saving signal or the clock detecting signal.

1. Technical Field
The present invention relates to a power-saving circuit for a digital video display device, and more particularly to a power-saving circuit for a digital video display device for detecting whether a transmission minimized differential signaling (TMDS) clock signal is input and performing a power-saving mode according to the detection result.
2. Description of the Related Art
In general, an analog video display device employing a cathode ray tube (CRT) and a digital video display device employing a liquid crystal display (LCD) are widely used for a desktop computer and a portable computer, respectively, wherein the digital video display device employs an analog interface mode and a digital interface mode.
The digital video display device of the analog interface mode has an advantage capable of being directly substituted for the existing analog video display device, whereas the digital video display device of the digital interface mode has an advantage capable of being simple and facilitating the impedance match, so that most portable computers employ the digital video display device of the digital interface mode.
With reference to FIG. 1, FIG. 1 illustrates a power saving circuit 100 of a conventional digital video display device. Operation of the digital video display device of a conventional digital interface mode will be schematically described with reference to FIG. 1 as follows.
In general, graphic card built in a computer main body compresses and encodes horizontal/vertical synchronous signals and a digital video signal into a TMDS data signal and outputs the TMDS data signal to the digital video display device together with a TMDS clock signal. A TMDS driving unit 10 of the digital video display device decompresses the TMDS data signal Data received on line 6, along with a clock signal Clock on line 2 and outputs the horizontal/vertical synchronous signals Hsync and Vsync and the digital video signal DE.
A TMDS signal conversion method is a technology of decoding high-speed serial data received at a receiving side as parallel data and then encoded into the high-speed serial data to be transmitted from a transmitting side, which is widely used in the digital video display device.
The horizontal/vertical synchronous signals Hsync/Vsync and the digital video signal DE output from the TMDS driving unit 10 are input into a display driving unit 12, so that the display driving unit 12 drives a gate driver and a source driver. At this time, a controller 14 carries out a power-saving mode in accordance with whether the horizontal/vertical synchronous signals Hsync/Vsync input from the TMDS driving unit 10 exist.
Since a TMDS signal input to the TMDS driving unit 10 from outside the TMDS driving unit 10 is of a high frequency and a small amplitude, it is difficult for the controller 14 to directly recognize whether the TMDS signal is input. In general, the controller 14 receives the horizontal/vertical synchronous signals Hsync/Vsync output from the TMDS driving unit 10 and indirectly determines whether the TMDS signal is input. That is, if the controller 14 does not receive the horizontal/vertical synchronous signals Hsync/Vsync from the TMDS driving unit 10, the controller 14 enables the digital video display device to carry out a power-saving mode and the controller 14 supplies a power saving signal PS to a power supply unit 16. When the controller 14 receives the horizontal/vertical synchronous signals Hsync/Vsync, the controller 14 enables the video display device to return to a normal mode. The power supply unit 16 supplies an appropriate voltage Vcc to the TMDS driving unit 10, the controller 14 and to display driving unit 12. In order for the controller 14 to determine whether the TMDS signal is input through the TMDS driving unit 10, electric power should be supplied all the time to the controller 14 and the TMDS driving unit 14, even in a power-saving mode.
However, since, in the conventional digital video display device, such as illustrated in FIG. 1, the controller 14 and the TMDS driving unit 10 should be supplied with electric power all the time even in a power-saving mode as stated above, there is a problem in that the power consumption is increased when using the standard of the display power management system (DPMS) of the Video Electronics Standard Association (VESA) for video electronic equipment.
In order to solve the above stated problem, it is an object of the present invention, among other objects of the present invention, to provide a power-saving circuit for a digital video display device capable of satisfying the DPMS standards through the reduction of electric power consumption in a power-saving mode by detecting whether a TMDS clock signal is input, carrying out a power-saving mode according to the detection result, and stopping the driving of respective components including the TMDS driving unit during the power-saving mode operation.
In order to achieve the above object, and other objects of the present invention, an embodiment of a power-saving circuit according to the present invention includes: a TMDS driving unit for converting a TMDS data signal input together with a TMDS clock signal to the TMDS driving unit into horizontal/vertical synchronous signals and a digital video signal based on a TMDS signal conversion mode; a display driving unit for driving a display unit based on the horizontal/vertical synchronous signals and the digital video signal input to the display driving unit from the TMDS driving unit; a clock signal detecting unit for outputting a first level of a clock detecting signal when the TMDS clock signal is not input to the TMDS driving unit and outputting a second level of the clock detecting signal when the TMDS clock signal is input to the TMDS driving unit; a controller for outputting a first level of a power-saving signal when the first level of the clock detecting signal is input to the controller from the clock signal detecting unit, and outputting a second level of the power-saving signal when the second level of clock detecting signal is input to the controller from the clock signal detecting unit; and a power supply unit for supplying a voltage to the TMDS driving unit, the controller, the clock signal detecting unit and the display driving unit, for cutting off the supply of the voltage except to the controller and the clock signal detecting unit when the first level of the power-saving signal is input to the power supply unit from the controller, and for providing the supply of the voltage to the TMDS driving unit, the controller, the clock signal detecting unit and the display driving unit when the second level of the power-saving signal is input to the power supply unit from the controller.
In order to achieve the above object and other objects of the present invention, another embodiment of a power-saving circuit according to the present invention includes: a TMDS driving unit for converting a TMDS data signal input together with a TMDS clock signal to the TMDS driving unit into horizontal/vertical synchronous signals and a digital video signal based on a TMDS signal conversion mode, the TMDS driving unit stopping driving an operation for signal converting when a first level of a power-down signal is input to the TMDS driving unit, and the TMDS driving unit starting the driving of the operation for signal converting when a second level of the power-down signal is input to the TMDS driving unit; a display driving unit for driving a display unit based on the horizontal/vertical synchronous signals and the digital video signal input to the display driving unit from the TMDS driving unit; a clock signal detecting unit for outputting a first level of a clock detecting signal when the TMDS clock signal is not input to the TMDS driving unit, and outputting a second level of the clock detecting signal when the TMDS clock signal is input to the TMDS driving unit; a controller for outputting the first level of the power-down signal to the TMDS driving unit and also for outputting a first level of a power-saving signal when the first level of clock detecting signal is input to the controller from the clock signal detecting unit, and for outputting the second level of the power-down signal to the TMDS driving unit and for outputting a second level of the power-saving signal when the second level of the clock detecting signal is input to the controller from the clock signal detecting unit; and a power supply unit for supplying a voltage to the TMDS driving unit, the controller, the clock signal detecting unit and the display driving unit, the power supply unit for cutting off the supply of the voltage except to the controller, the clock signal detecting unit and the TMDS driving unit when the first level of the power-saving signal is input to the power supply unit from the controller, and the power supply unit for providing the supply of the power to the TMDS driving unit, the controller, the clock signal detecting unit and the display driving unit when the second level of the power-saving signal is input to the power supply unit from the controller.
In order to achieve the above object and other objects of the present invention, a further embodiment of a power-saving circuit according to the present invention includes: a TMDS driving unit for converting a TMDS data signal input together with a TMDS clock signal to the TMDS driving unit into horizontal/vertical synchronous signals and a digital video signal based on a TMDS signal conversion mode; a display driving unit for driving a display unit based on the horizontal/vertical synchronous signals and the digital video signal input to the display driving unit from the TMDS driving unit; a clock signal detecting unit for outputting a first level of a clock detecting signal when the TMDS clock signal is not input to the TMDS driving unit, and for outputting a second level of the clock detecting signal when the TMDS clock signal is input to the TMDS driving unit; and a power supply unit for supplying a voltage to the TMDS driving unit, the clock signal detecting unit and the display driving unit, for cutting off the supply of the voltage to the TMDS driving unit and the display driving unit, but not to the clock signal detecting unit, when the first level of clock detecting signal is input to the power supply unit from the clock signal detecting unit, and for providing the supply of the voltage to the TMDS driving unit, the clock signal detecting unit and the display driving unit when the second level of the clock detecting signal is input to the power supply unit from the clock signal detecting unit.
In order to achieve the above object and other objects of the present invention, a still further embodiment of a power-saving circuit according to the present invention includes: a TMDS driving unit for converting a TMDS data signal input together with a TMDS clock signal to the TMDS driving unit into horizontal/vertical synchronous signals and a digital video signal based on a TMDS signal conversion mode, the TMDS driving unit stopping driving of an operation for signal converting when a first level of a clock detecting signal is input to the TMDS driving unit, and the TMDS driving unit starting the driving of the operation for signal converting when a second level of the clock detecting signal is input to the TMDS driving unit; a display driving unit for driving a display unit based on the horizontal/vertical synchronous signals and the digital video signal input to the display driving unit from the TMDS driving unit; a clock signal detecting unit for outputting to the TMDS driving unit the first level of clock detecting signal when the TMDS clock signal is not input the TMDS driving unit, and for outputting the second level of the clock detecting signal to the TMDS driving unit when the TMDS clock signal is input to the TMDS driving unit; and a power supply unit for supplying a voltage to the TMDS driving unit, the clock signal detecting unit and the display driving unit, for cutting off the supply of a voltage except to the TMDS driving unit and the clock signal detecting unit when the first level of the clock detecting signal is input to the power supply unit from the clock signal detecting unit, and for providing the supply of the voltage to the TMDS driving unit, the clock signal detecting unit and to the display driving unit when the second level of the clock detecting signal is input to the power supply unit from the clock signal detecting unit.
Accordingly, the present invention promotes satisfaction of the DTMS standards through the reduction of the power consumption by detecting whether a TMDS clock signal is input to the TMDS driving unit, carrying out a power-saving mode according to the detection result, and stopping the driving of the respective components including the driving of an operation for signal converting in the TMDS driving unit during the operation in the power-saving mode.

Power-saving circuit and method for a digital video display device


Performance measurement and/or malfunction detection of rotating machinery can be accomplished by using one or more strain measuring devices attached to a journal bearing housing, using the strain measuring device or devices to generate an electrically measurable output in response to a change of a force in at least part of the journal bearing housing, using a Wheatstone bridge circuit to convert the electrically measurable output to an analog electrical signal, converting the analog electrical signal to a digital electrical signal and analyzing the digital electrical signal to determine the performance of the machinery and/or existence of a malfunction in the rotating machinery.

The present invention relates to rotating machinery and the measurement of strain to determine performance and/or detect malfunctions in rotating machinery. Rotating machinery can use fluid film bearings, which are also called journal bearings, hydrostatic bearings, hydrodynamic bearings, and babbitt bearings. In one embodiment, the present invention relates to systems and methods that measure strain to determine performance and/or detect malfunctions of rotating equipment that uses fluid film bearings.
Strain is a measurement of a material's change in dimension when introduced to stress. The equation for strain is: (δL/L) where δL is the change in length in one dimension of the material from its unstrained state and L is that same unstrained length. Strain in materials is directly proportional to stress, by the equation σ=E*ε where σ is stress in units of pressure, E is Young's Modulus, a value unique to the material and ε is the strain experienced by the material. The units of stress are in force over area, giving a direct relationship between the stress and force applied to the material. Given these three equations, strain in a material having a force applied to it can be directly related to the magnitude of the force. If this force is cyclic, as in rotating and reciprocating equipment, the strain in the material will show magnitude and frequency relatable to the force.
In rotating machinery that uses fluid film bearings, the force experienced by the shaft and bearing can be difficult to measure. The non-linear nature of the fluid in the bearing means that readings taken with an accelerometer rarely display all frequencies in the system and with incorrect magnitude ratios. Proximity probes, which monitor the position of the shaft within the bearing, may indicate issues with running conditions or the shaft itself but do not monitor the health of the rotating machinery itself. By measuring the strain experienced in and/or proximate to the bearing, direct condition monitoring is possible and shows the best possible representation of the force felt by the bearing and related components of a rotating machine during operation.
Manufacturers want to increase profit margin and decrease greenhouse gas emissions. Improvements in production equipment reliability can be a direct path towards achieving these objectives. Equipment efficiency improvement through increased reliability can directly improve the bottom line. Less evident is the impact to emissions that occurs by improperly discarding failed equipment—causing environmental waste—and then purchasing replacement machines—requiring additional energy to produce.
Machinery health monitoring, or condition monitoring, is widely considered one of the best paths towards improving equipment reliability. The customary practice in condition monitoring programs, often used to guide maintenance for large numbers of machines, is vibration acceleration readings to detect faults in machinery. For rotating and reciprocating machinery, vibration analysis methods have been developed to connect vibration signatures to specific components, faults, and operating conditions, but strain has historically not been used. The current state of the art based on vibration requires either an expensive permanent sensor installation or resources to support a portable system in which data are collected and analyzed manually. Sensor installs are often invasive and the portable collection intervals are difficult to manage at an appropriate frequency due to manpower shortage. In both cases, expert analysts must be employed for data interpretation because the current state of the art automated analysis algorithms are inaccurate at best.
Prior art automated analysis tools are inaccurate because the parameters they measure are based on the kinematics (i.e. motion), of the system. These prior art tools read the vibration displacement, velocity, or acceleration of the system, but proper analysis requires an understanding of the input forces. An analyst using measured input kinematics must infer the applied forces based on additional system parameters such as mass, stiffness, and damping. Since every system is different, the path to that inference is inconsistent, and often inaccurate.
Measuring and interpreting strain data puts the analyst much closer to measuring the actual input force. The kinematics of the system are irrelevant since measuring strain essentially bypasses these variables. Measuring strain is a "leapfrog", so to speak, over the prior art.
Interpreting strain data would significantly improve the automated analysis algorithms and therefore provide an enticement for installing more permanent monitoring systems, which collect more data with more precision than a portable temporary analysis tool. Installations of strain-based measurement tools can be less invasive and therefore more cost effective than the prior art. Wireless data transfer and localized power technology can be more easily justified with strain-based measurement tools than with the prior art tools. Wireless technology, solar energy, thermal power generation, and battery technology are all ready to be adapted to strain-based measurement applications.
Fluid film bearings are widely used. These bearings theoretically have infinite life due to their inherent lubrication. However, error during operation and maintenance can cause fluid film bearings to fail. As an example of a failure mode for a fluid film bearing, consider a main engine bearing that is provided contaminated oil containing wear particles from somewhere else in the engine. These wear particles can score the surface of the bearing, causing increased friction and distortion of the bearing geometry. The added friction can increase the oil temperature, which typically reduces oil viscosity. The deformed geometry and altered viscosity can compromise the hydrodynamic wedge, leading to a change in the pressure distribution of the fluid film bearing. Increased oil temperature can also increase the temperature of the babbitt material. The increased temperature and pressure can cause the babbitt to displace or wipe, further compromising geometry of the fluid film bearing. Eventually there is a chance that the babbitt will become so distorted that it disrupts the formation of any fluid wedge, and the shaft will crash within the fluid film bearing.
Fluid film bearing failures can be difficult to predict, especially when compared to rolling element bearings. Furthermore, successful condition monitoring of fluid film bearings can pose a much greater challenge than for rolling element bearings. Rolling element bearings typically have low internal damping, and solid paths of transmission, which allows:                (a) vibrations to reach the bearing casing linearly;        (b) accelerometers to measure the vibrations of the bearing casing; and        (c) identification of any fault signatures in the resulting accelerometer signal or signals.
For fluid film bearings, a fluid such as oil or air separates the shaft from the bearing surfaces during normal operation. This fluid film can have much higher damping properties than for rolling element bearings, which can make the system higher order, and non-linear. Therefore, case-mounted accelerometers external to the shaft can be unreliable for monitoring fluid film bearing faults because vibration of the case does not necessarily correlate to shaft vibration in a fluid film bearing. It is therefore desirable not to rely exclusively on accelerometers for fluid film bearing condition monitoring. Other technologies such as temperature trending, proximity sensing using eddy current probes, and/or the use of lasers can also be unfeasible or overly complex or costly for some fluid film bearing applications, and it is desirable not to rely exclusively on these technologies for fluid film bearing condition monitoring.
It is desired to have a more accurate, simpler, and/or lower cost system and method for monitoring fluid film dynamics and the condition of a fluid film bearing in order to improve the prognostics of devices that utilize fluid film bearings.
It should be understood that the drawings are not necessarily to scale. In certain instances, details that are not necessary for an understanding of the invention or that render other details difficult to perceive may have been omitted. It should be understood that the invention is not necessarily limited to the particular embodiments illustrated herein.

This patent is subject to a terminal disclaimer.

Strain based systems and methods for performance measurement and/or malfunction detection of rotating machinery


A technique for coding color components of video signals wherein a color component of an image signal sequence is filtered into a plurality of subband image signals. One or more pixels of a first subband image signal are coded using one or more bits of a first quantity of bits. The first subband image signal reflects an image structure of a color component of the image signal sequence. The first subband includes low spatial and temporal frequencies of the color component. A second quantity of bits is used for coding one or more pixels of a second subband image signal. This second quantity of bits comprises one or more bits of the first quantity of bits not used in coding pixels of the first subband image signal. One or more pixels of the second subband image signal are coded using one or more of the second quantity of bits. The second subband image signal reflects image object motion information of the color component of the image signal sequence. A third quantity of bits is provided for use in coding one or more pixels of a third subband image signal. The third quantity of bits comprises one or more bits not used in coding either the first or second subband image signals. One or more pixels of the third subband image signal are coded with one or more of the third quantity of bits. The third subband image signal reflects edges of moving image objects, such as horizontal or vertical edges.

Good quality, low bit rate color video coding is required for such applications as video teleconferencing over existing and future networks, as well as CD-ROM storage. An effective low rate coder should remove the redundancies due to temporal and spatial correlations along with perceptually irrelevant components of an image sequence.
Subband digital coding techniques are well known in the art. See, e.g., N. S. Jayant and P. Noll, Digital Coding of Waveforms: Principles and Applications to Speech and Video (1984).
Subband coding techniques have been used for image coding in a three-dimensional spatio-temporal subband framework as described in G. Karlsson and M. Vetterli, Three Dimensional Subband Coding of Video, Proceedings ICASSP (1988), 1100-1103. The technique described there employs multidimensional filtering to generate spatio-temporal frequency bands or subbands using so called quadrature mirror filters. These latter filters are described, e.g., in J. D. Johnston, A Filter Family Designed for Use in Quadrature Mirror Filter Bands, Proceedings ICASSP (1980).

Subband color video coding using a reduced motion information subband


A large volume cement mixer that is readily mobile and can be set up for use with a concrete batch plant at a given location. The cement mixer is carried on an elongated frame having wheels on one end and a gooseneck connection on the front end for towing purposes. A longitudinally movable carriage is carried on top of the elongated frame and the carriage is adapted to carry a large cement mixer mounted thereon. In operation, the elongate frame is braced in approximately 45.degree. angle attitude as the carriage supports the cement mixer in generally horizontal, rotatable fixture. Hydraulic devices are provided for rotating the cement mixer during the mixing mode of operation and, after completion, the carriage structure is hydraulically controlled to move upward along the elongate frame to a dump position whereupon the cement mixer is rotated forward and the mixed concrete is allowed to fall to a discharge position.

1. Field of the Invention
The invention relates generally to mobile-type batch plants and, more particularly, but not by way of limitation, it relates to an improved portable cement mixer that can be set up to function with an existing type of mobile batch plant to enable large volume concrete mixing and distribution.
2. Description of the Prior Art
The prior art includes various types of batching plants, both permanent and mobile installations, and these batching plants are intended to function with the conventional cement mixing truck, i.e., the batching plants serving to weigh and deliver the ingredient components while the mixing trucks function to mix and deliver the concrete to a construction site. The mobile batch plant that is identified as prior art herein is the subject matter of the invention disclosed in U.S. Pat. No. 4,775,275, issued on Oct. 4, 1988 and entitled "MOBILE BATCH PLANTS". The inventor is not aware of any prior type of mobile mixing plant suitable to carry out the combinative function as set forth in the present specification.

Portable large volume cement mixer for batch operations


Jagged vertical or diagonal transition artifacts in interlaced to line doubled progressive scan converted television signals are detected and areas of the television picture having such artifacts are subjected to vertical averaging such that the resolution of the jagged transitions is reduced, thereby softening, "greying" or "fuzzing" the jagged transitions and causing them to appear smooth. Thus, highly contrasted lines appearing in a sawtooth pattern, which are extremely perceptible, are replaced with a flash of what might be characterized as "fuzziness," which is not perceptible. The eye no longer perceives the jagged artifacts. Moreover, areas of reduced vertical and horizontal resolution, resulting from the vertical averaging, do not create any new artifacts and are not perceived by the eye. Artifacts are detected by comparing pixels in corresponding positions in the scan lines of the line doubled progressively scanned television signal. The detection scheme looks for sawtooth patterns by determining if there are differences among pixels in more than one set of three adjacent lines. When a sawtooth pattern is detected, the uncorrected signal in the sawtooth region of a scan line is faded to a vertically filtered or averaged signal just prior to the onset of the sawtooth artifact region and then faded back to the uncorrected signal just subsequent to the sawtooth artifact region. The sawtooth correction signal, which controls fading to and from a filtered video signal, is expanded in all directions horizontally and vertically somewhat beyond the region of the detected artifact in order to insure that all of the artifact is suppressed.

A well-known "line-doubling" technique employs the conversion of an interlaced television signal (such as employed in the NTSC, PAL and SECAM systems), in which two time consecutive interleaved fields of scan lines represent a frame, to a non-interlaced or progressively scanned television signal, in which all of the scan lines in the frame are scanned out sequentially. The result, in the case of NTSC, is that 525 scan lines are presented every one-sixtieth of a second rather than 262.5 scan lines, thus potentially doubling the vertical resolution to the full frame resolution of 525 lines. Typically, line doublers employ, at least part of the time, field merging or inter-field interpolation, which provides a full doubling of the vertical resolution. Pairs of fields are combined to form a single progressively scanned frame. Such arrangements are described in U.S. Pat. Nos. 4,876,596; 4,967,271; 4,982,280; 4,989,090 and 5,159,451, each of which hereby is incorporated by reference in its entirety. Such an arrangement is also described in allowed U.S. Pat. No. 5,291,280, which is hereby incorporated by reference in its entirety.
One problem resulting from field merging is that there is a time difference between fields in the interlaced television signal. Thus, a moving object may be in different locations from field to field and, if two such fields are combined to form a single frame, the vertical and diagonal edges of objects moving horizontally or diagonally appear as ragged sawtooths rather than smooth curves. Line doubling is lost along such transitions. The sawtooth effect is exacerbated if the reproduction system employs vertical enhancement.
One solution to this problem is to employ some type of scan line or intra-field interpolation in regions of the television picture display in which movement is occurring. An improved technique for providing intra-field interpolation in areas of the picture having motion is set forth in said U.S. Pat. No. 4,989,090.
A potential problem with switchable inter-field/intra-field interpolation line doublers is that motion may not be properly detected at all times, thus allowing the above mentioned jagged vertical or diagonal transition artifacts to appear briefly and intermittently. Such arrangements may have particular difficulty in consistently switching correctly between operating regimes when operating on an interlaced television signal that has been subject to data compression or standards conversion (as from PAL to NTSC, for example).
Another known solution to the problem is to recognize when the source of the interlaced television signal is a motion picture film. In the United States, 24 frame per second motion picture films are applied to the 30 frame per second NTSC television signal by means of a "3-2 pulldown ratio," such that a patterned sequence of 3 film frames, 2 film frames, 3 film frames, etc. are carded by consecutive television fields. By identifying pairs of interlaced fields carrying the same film frame, the pairs may be merged to generate essentially perfect line doubled progressively scanned frames, each representing a motion picture frame. Such techniques are described in said U.S. Pat. No. 4,876,596 and 4,982,280.
However, the motion picture film detection arrangement is also subject to problems. For example, a video edit (rather than a film edit) may disrupt the 3-2 pulldown ratio, causing merged television fields to be derived from different film frames. Thus, until the film pulldown ratio detection circuitry resynchronizes itself (typically one to four fields of the input interlaced television signal), the ragged sawtooth transition artifacts, described above, may appear at the edges of moving objects. Although the undesired effect is fleeting, it is perceptible to the eye, occasionally disturbing an otherwise near perfect line doubling arrangement.
The last discussed problem may also arise in the motion picture film source line doubling arrangement when the input interlaced television signal fades from a film source to a video source. In that case, the system, as described, for example, in said U.S. Pat. No. 4,982,280, continues to operate in its "film mode" for a few fields before recognizing the loss of the 3-2 pull down pattern and switching to an inter field/intra-field interpolation arrangement of the sort described above. During those few fields before changeover from the film mode of operation, the same sort of ragged sawtooth artifacts may be generated if there is motion between the fields. In addition, the problem may also arise when the interlaced television signal derived from a motion picture source has been imperfectly data compressed or standards converted.
One solution to the problem of video edits disrupting the 3-2 pulldown ratio is set forth in said allowed U.S. Pat. No. 5,291,280, of applicant Yves C. Faroudja. The solution requires the use of a field delay and relatively complex circuitry in order to "look ahead" for video edits. Such a solution adds a further one field delay to the four field delay which is typically employed in line doubling progressive scan converters, resulting in a perceptible delay between the picture and undelayed audio. Thus, such an arrangement requires the use of a high quality audio delay, adding further cost and complexity.

Suppression of sawtooth artifacts in an interlace-to-progressive converted signal


Rinse aids for dishwashing machines comprising. (1) an alkyl polyglycoside,. (2) an alkyl polyglycol ether, and. (3) an organic carboxylic acid wherein the rinse aid is substantially free from foam inhibitors and thickeners.

International patent application WO 88/09369 describes water-based liquid detergents for dishwashing machines which contain 0.5% to 20% by weight of a mixture of alkyl polyglycosides corresponding to the formula R--O--(Z).sub.x H, where R=C.sub.8-16 alkyl, Z=a glucose unit and x=1-3, preferably 1-2 and more particularly 1-1.4, and low-foaming nonionic surfactants corresponding to the formula R.sub.1 --O--(EO).sub.n (PO).sub.m H, where R.sub.1 =C.sub.6-22 alkyl, n=1-40 and m=1-15, and 10% to 60% by weight of alkali metal citrates. Detergents such as these are unsuitable as rinse aids.
It is known that, where modern phosphate-free low-alkali detergents are used in dishwashing machines, lime and silicate coatings can be formed both on the washed articles and in the interior of the machine because the calcium binding capacity of such detergents is lower than that of conventional phosphate-containing products. Troublesome lime and silicate coatings are formed in particular when the rinsing water of the dishwashing machine is unsoftened or insufficiently softened and a water hardness of 4.degree.dH is exceeded. In cases such as these, lime and silicate coatings can be effectively avoided by the introduction of citric acid into the final rinse cycle via the rinse aid. However, since the quantities of rinse aid normally added during the final rinse cycle are very small (3 ml to 6 ml), the citric acid content in rinse aid formulations intended to guarantee the effective inhibition of bloom has to be relatively high to achieve an adequate acid or complexing capacity. High citric acid contents support the effect of phosphate substitutes and guarantee spotless dishes.
European patent application 432 836 (Unilever) describes rinse aid formulations for dishwashing machines which contain only one surfactant selected from alkyl polyglycosides and, as further ingredients, foam inhibitors and thickeners. They do not contain any of the acid normally present in rinse aids.
Foam inhibitors are an essential ingredient of these formulations because alkyl polyglycosides are generally high-foaming and would cause unacceptable foaming of the described rinse aid formulations when used in a dishwashing machine. However, foam inhibitors are only effective if they are insoluble in the medium to be foam-inhibited. Accordingly, the alkyl polyglycoside solutions and the foam inhibitors are also immiscible with one another in the disclosed examples of rinse aids. Accordingly, two phases would exist unless a thickener--which provides for a certain homogenization--had been used to disperse them.
However, the latent inhomogeneity caused by the foam inhibitor remains a disadvantage of such a formulation. The foam inhibitor and surfactant solution of the rinse aid separate after only a short storage time, despite the content of thickener. A product such as this is of course unsuitable both for consumers of branded goods and for bulk consumers because the products required in both these cases are required to remain stable in storage over prolonged periods, but at least for one year. Accordingly, the only suitable formulations are single-phase formulations in which all the ingredients are homogeneously dissolved and which not only remain stable in storage, but also do not separate during the heating and cooling phase of the rinse cycle, i.e. show phase stability at temperatures in the dishwashing machine of 0.degree. to 65.degree. C. The low temperature is necessary because warehouses are generally not heated in winter. Accordingly, temperatures around freezing point are entirely realistic. On the other hand, the known products are so viscous--as long as they are homogeneous--that they cannot be poured in through the rinse aid dispenser of a domestic dishwashing machine.
In addition, rinse aid formulations containing only alkyl polyglycosides as their surfactant component do not wet plastic articles sufficiently, if at all, so that the clear rinse or clear drying effect is unsatisfactory in their case.
Today, only those formulation ingredients which are totally biodegradable under detergent legislation may be used in detergents, including rinse aid formulations. Accordingly, the problem addressed by the present invention was to find an ecologically and toxicologically satisfactory formulation which would be equivalent in its performance properties to commercial rinse aids and which would not have any of the disadvantages mentioned above.

Dishwashing machine rinse aids containing APG, alkyl polyglycol ether and organic carboxylic acid


A Focused Electric Field Imprinting (FEFI) process and apparatus provides a focused electric field to guide an unplating operation and/or a plating operation to form very fine-pitched metal patterns on a substrate. The process is a variation of the electrochemical unplating process, wherein the process is modified for imprinting range of patterns of around 2000 microns to 20 microns or less in width, and from about 0.1 microns or less to 10 microns or more in depth. Some embodiments curve a proton-exchange membrane whose shape is varied using suction on a backing fluid through a support mask. Other embodiments use a curved electrode. Mask-membrane interaction parameters and process settings vary the feature size, which can generate sub-100-nm features. The feature-generation process is parallelized, and a stepped sequence of such FEFI operations, can generate sub-100 nm lines with sub-100 nm spacing. The described FEFI process is implemented on copper substrate, and also works well on other conductors.

There exist today several innovative manufacturing technologies to meet the demand for the production of components with features in the range of a sub-micron to several hundred micrometers. They are classified into two basic groups (Rajurkar et al, 2006): (i) lithography based micro fabrication processes, which are capable of micro and sub-micrometer size features, and (ii) micro manufacturing processes, which are capable of micro and miniaturized part fabrications. Unfortunately, we are rapidly approaching the limit of traditional processing methods for functionalizing and processing inexpensive miniaturized devices. Clearly, a major challenge remains in the micro-manufacturing community to develop flexible, robust and large-scale fabrication methods that are economical and also environmentally friendly.
Traditionally, the lithography based processes employ either material addition (e.g., Physical Vapor Deposition "PVD", Chemical Vapor Deposition "CVD", and electro-deposition) or material subtraction (e.g., UV and e-beam lithography) to produce micron and submicron scale surface patterning. However, such processes are naturally limited by macro-scale phenomenon such as diffusion or thermal gradients. Any patterning scheme utilizing deposition methods must create and maintain a tight gradient (in the nanometer range) in driving force to control deposition and transport rates. Although subtraction processes such as electron or ion beam writing possess very high resolution capabilities for local patterning, they are sequential and cumbersome (due to macro-scale positioning requirements) with limitations in the materials they can modify and strict requirements of surface planarity. Thus, direct extension of lithographic based fabrication facility, with its attendant high cost of ownership (COO) and the required capital outlay of upwards of $3 Billion are somewhat impractical for miniaturized components for targeting inexpensive and rapid throughput.
For example, the MicroStepper described by Miller et al. (2000) can achieve sub-100-nm patterning, but the equipment is expensive and requires planarized surfaces with roughness of the order of 0.1 times the wavelength of the ultraviolet light.
Non-lithographic based processes can also be classified as additive and subtractive processes (see Rajurkar et al, 2006 and the references therein for an exhaustive list of processes). Out of this list, we focus our attention on mechanical micromachining vs. electro-physical and chemical processes (ECP). In mechanical micromachining, a direct contact with the work piece is established, with good geometric correlation between the tool path and the work piece. While they possess high material removal rate, these methods, however, are not suitable for very hard or very fragile, e.g., low dielectric porous materials. In addition, they induce significant level of residual stresses, and possess additional limitations on dimensional tolerances and minimum gage requirements (Liu et al, 2004). On the other hand, ECP offer distinct advantages by not contacting the work-piece, especially in electro discharge machining (EDM) and electrochemical machining (ECM). The ECP eliminates the drawback due to elastic spring back and the minimum gage requirement to sustain the cutting forces. In addition, they are quite economical for small batch productions (IWF, 2002). The ECP processes have been successfully employed in aerospace, automobile, and other industries for shaping, cutting, debarring and finishing. These processes provide solutions for manufacturing small and very precise components and micro-systems for the watch industry, micro-optics (telecommunications), medicine (processing biocompatible materials, medical implants) and chemical industry (micro-reactors).
ECM process can provide excellent performance for large and contoured surfaces. It also provides low material waste and very little tool wear. Complex shapes ranging from hard to machine titanium and wasp alloys aircraft engine casings (McGeough, 1974), to miniaturized LIGA processes are common utilization of ECM (Friedrich et al., 1997; Dunkel et al, 1998, Craston et al, 1988; Husser et al, 1989). While the EC process has found major applications in IC fabrications such as in Damascene Cu Plating (Andricacos, 1999) and in electrochemical mechanical planarization of wafers (Steigerwald et al, 1997; Huo, et al 2004), most ECM processes, however, are not environmentally benign. They also give rise to thermal and environmental concerns. The finished surface comes in contact with corrosive chemicals, which may accelerate corrosion and necessitate post-ECM cleaning of the finished surface (Wilson, 1971). Maintaining an ECM tool over a long period of time has also proved difficult.
The electrochemical process described by Mazur et al. (2005) is environmentally benign. However, it is only meant for polishing or planarization, and cannot imprint a specified pattern on a surface.
The traditional lithography or other contact printing processes also require extremely tight tolerances in surface roughness and planarization. This makes surface preparation for such processes quite expensive, often requiring chemical mechanical planarization "CMP".
Thus, capability for printing on wavy surfaces is also required for flexible IC devices, where performing CMP is very difficult. Therefore, there is a need in the industry for a device that produces sub-100 nm patterns through a non-contact process. The conventional available devices that can produce such patterns are expensive, and also typically require polished or planarized surfaces.

Apparatus for focused electric-field imprinting for micron and sub-micron patterns on wavy or planar surfaces


A detector for measuring scanning ion beams in radiation therapy sequentially includes a first high voltage electrode, a first spacing member, and a segmented electrode. The first spacing member is connected to the first high voltage electrode and the segmented electrode to form a first ionization cavity. The first ionization cavity is formed with a plurality of first reading electrodes and a plurality of second reading electrodes therein. A second spacing member and a second high voltage electrode are further sequentially disposed. The second spacing member is connected to the second high voltage electrode and the segmented electrode to form a second ionization cavity. The first reading electrodes and the second reading electrodes are respectively formed in the first ionization cavity and the second ionization cavity. With the first reading electrodes and the second reading electrodes in different directions, highly accurate space resolution, space dosage and scanning speed are achieved.

Cancer, also referred to as malignant tumors, is a result of abnormally proliferated cells that further invade other parts of a human body, and is one main cause for human deaths. Cancer can be treated by surgery, chemotherapy, radiation therapy, immunotherapy, monoclonal antibody therapy or other therapies. Among the above treatments, radiation therapy frequently serves as a most direct or auxiliary method for treating cancer. By killing cancer cells, reducing tumors and damaging genetic substances of cells with radiation, radiation therapy prohibits cell growth or dividing to further control the growth of cancer cells.
For example, the U.S. Patent Publication No. 20150031933, "Range Shifter and Particle Radiotherapy Device", discloses a common radiotherapy device. The particle therapy device includes an accelerator that generates a particle beam, a plurality of treatment rooms, a plurality of irradiation devices, and a plurality of range shifters disposed in the irradiation devices. The particle beam enters the treatment rooms from the accelerator. The irradiation devices are respectively disposed in the treatment rooms, and irradiate the particle beam onto an irradiation area of an irradiation target. Each range shifter includes a transmissive plate and a holding portion that holds the transmissive plate. By adjusting the thickness of the transmissive plate, the particle beam may be given with different attenuation amounts, such that the energy of the particle beam can be adjusted.
In general use, a detector is also used in conjunction to confirm the accuracy of parameters of the particle beam and the amount of radiation transmitted. In a conventional treatment, a large-area radiation exposure is applied, and a range of radiation is limited using a predetermined shield manufactured according to a size of tumors. Thus, the measurement of a specific position is usually performed by a two-dimensional detector or a small-size detector (single-channel). In a new ion treatment, the position of tumors is scanned using small-size ion beams at a scanning speed of 20 m/sec, and the dosage can be controlled by controlling the scanning speed. However, due to an excessively large space resolution and an inadequate measuring speed, a conventional detector is incapable of accurately measuring such scanning ion beams. Therefore, there is a need for a solution that is capable of increasing the space resolution and measuring speed to accurately measure the parameters and radiation dosage.

Detector for measuring scanning ion beams in radiation therapy


A method, computer program product, and computer system for receiving, by a computing device, a speech signal from a speaker via a plurality of microphone zones. A temporal cue based confidence may be determined for at least a portion of the plurality of microphone zones. A power cue based confidence may be determined for at least a portion of the plurality of microphone zones. A microphone zone of the plurality of microphone zones from which to use an output signal of the speaker may be identified based upon, at least in part, a combination of the temporal cue based confidence and the power cue based confidence.

Generally, speech continues to gain importance in human-machine interaction. This may apply to multiple aspects of life, including, for example, voice-activated commands or phone conversations in a vehicle. Some vehicles may be equipped with multiple microphones in various locations in the car to allow multiple passengers to take advantage of voice-activated features. For instance, the driver may have a dedicated microphone, the passenger may have a dedicated microphone, etc. In this non-limiting example, it may be beneficial to determine which passenger is speaking, which may be difficult given the acoustic environment, close proximity of passengers, etc. However, current processes of Speaker Activity Detection (SAD) in multi-microphone systems may not be as robust, accurate, or as efficient as needed to satisfy the expectations of the end users.

System and method for temporal and power based zone detection in speaker dependent microphone environments


When the input signal IN1 changes from a ground voltage GND to a first voltage -E1 and from the first voltage -E1 to the ground voltage GND, the output potential of the -E2 system flip-flop circuit changes gradually. The inverted signal from the -E1 system inverter circuit is supplied to the -E2 system inverter circuit earlier than the output signal (high-potential signal) of the -E2 system flip-flop circuit. This eliminates a period of time when all the MOSFETs in the -E2 system inverter circuit turn on simultaneously, thereby reducing a through current in the -E2 system inverter circuit. Consequently, the circuit operation can be stabilized by decreasing through currents flowing in the -E1 system inverter circuit and the -E2 system inverter circuit using the output signal of the -E2 system flip-flop circuit as an input.

1. Field of the Invention
The present invention relates to a semiconductor integrated circuit with a level shifter circuit and, more particularly, to a semiconductor integrated circuit used to decrease a through current in an inverter circuit which uses an output signal of the level shifter circuit as an input signal.
2. Description of the Related Art
FIG. 1 is a block diagram of a conventional interface circuit between a low-voltage system (referred to as a -E1 system hereinafter) and a high-voltage system (referred to as a -E2 system hereinafter). The interface shown in FIG. 1 is connected between a -E1 system logic circuit 1a and a -E2 system logic circuit 5, and comprises a -E1 system inverter circuit 1, a -E2 system flip-flop circuit 2, and a -E2 system inverter circuit 3. The -E1 system inverter circuit 1 and the -E2 system flip-flop circuit 2 constitute a voltage conversion circuit (level shifter circuit). The -E1 system logic circuit 1a outputs a digital input signal IN alternating between the ground voltage GND and a first voltage (first power supply voltage) -El (low voltage). The -E1 system inverter circuit 1 receives the input signal IN and outputs a signal IN (the inversion signal of signal IN). The -E2 system flip-flop circuit 2 uses the input signal IN and the output signal e,ovs/IN/ of the -E1 system inverter circuit 1 as input signals, and is connected between the ground voltage GND and a second voltage (second power supply voltage) -E2 (high voltage). The -E2 system inverter circuit 3 waveform-shapes the output signal of the level shifter circuit or the output signal of the -E2 system flip-flop circuit 2, and supplies the shaped signal as the input signal to the -E2 system logic circuit 5.
FIG. 2 shows a concrete arrangement of the interface circuit of FIG. 1, which is composed of complementary MOSFETs formed on an N-type semiconductor substrate. The -E1 system logic circuit 1a and -E2 system logic circuit 5 of FIG. 1 are not shown in FIG. 2. The -E1 system inverter circuit 1 is composed of a P-channel MOSFET P11 and an N-channel MOSFET N11. The gate of each of the P-channel MOSFET P11 and N-channel MOSFET N11 is supplied with the input signal IN1. One end of the current path of the P-channel MOSFET P11 is grounded and the other end is connected to one end of the current path of the N-channel MOSFET N11. The other end of the N-channel MOSFET N11 is supplied with the first voltage -El. The output terminal of the -E1 system inverter circuit 1 supplies the inverted signal IN1. The -E2 system flip-flop circuit 2 is composed of P-channel MOSFETs P12 and P13 and N-channel MOSFETs N12 and N13, and uses the input signal IN1 and the inverted signal IN1 as input signals and outputs a signal alternating between the ground voltage GND and the second voltage -E2. The -E2 system flip-flop circuit 2 outputs a signal of opposite phase to the input signal IN1. Specifically, the flip-flop circuit 2 outputs a signal at the level of the second voltage -E2 when the input signal IN1 is at the level of the ground voltage GND, and outputs a signal at the ground voltage GND when the input signal IN1 is at the first voltage -El. The gate electrodes of the P-channel MOSFETs P12 and P13 are supplied with the input signal IN1 and the inverted signal IN1, respectively. One ends of the current paths of the P-channel MOSFETs 12 and 13 are grounded, respectively. The other end of the current path of the P-channel MOSFET P12 is connected to one end of the current path of the N-channel MOSFET N12. This connection point is connected to the gate electrode of the N-channel MOSFET N13 and the input terminal of the -E2 system inverter circuit 3d. The other end of the current path of the P-channel MOSFET P13 is connected to one end of the current path of the N-channel MOSFET N13. This connection point is connected to the gate electrode of the N-channel MOSFET N12. The other ends of the current paths of the N-channel MOSFETs N12 and N13 are supplied with the second voltage -E2. To stabilize the circuit operation, the amplification factors of the P-channel MOSFETs P12 and P13 and the N-channel MOSFETs N12 and N13 constituting the -E2 system flip-flop circuit 2 are set as follows: gm.sub.p12 >gm.sub.N12, gm.sub.p13 >gm.sub.N13, gm.sub.p12 =gm.sub.p13, and gm.sub.N12 =gm.sub.N13. Where gm.sub.p12 is the amplification factor of the P-channel MOSFET P12, and gm.sub.N12, gm.sub.p13, and gm.sub.N13 indicate the amplification factors of the corresponding MOSFETs. The -E2 system inverter circuit 3d is composed of a P-channel MOSFET P14 and an N-channel MOSFET N14. One end of the current path of the P-channel MOSFET P14 is grounded and the other end is connected to one end of the current path of the N-channel MOSFET N14, the other end of which is supplied with the second voltage -E2. The connection of the gate electrodes of the P-channel MOSFET P14 and the N-channel MOSFET N14 is the input terminal of the -E2 system inverter circuit 3d. The connection of the other end of the current path of the P-channel MOSFET P14 and one end of the current path of the N-channel MOSFET N14 is the output terminal of the -E 2 system inverter circuit 3d. At the output terminal, an output signal OUT1 is supplied.
FIG. 3 is a timing chart for the operation of the interface circuit of FIG. 2. The operation of the interface circuit will be explained when the input signal IN1 changes from the ground voltage GND (high level) to the first voltage -El (low level), as shown in FIG. 3(a). As shown in FIG. 3(a), when the input signal IN1 is at the ground voltage GND, the inverted signal IN1 is at the first voltage -El as shown in FIG. 3(b). A point A is at the second voltage -E2, a point B is at the ground voltage GND, and the output signal OUT1 is at the ground voltage GND, as shown in FIGS. 3(c) through (e). In this state, as shown in FIG. 3(c), the potential at the point A equals the second voltage -E2, the N-channel MOSFET N13 is off and the point B remains at the ground voltage GND. In this state, since the N-channel MOSFET N14 is off, a through current does not flow in the P-channel MOSFET P14 and N-channel MOSFET N14. In this state, when the potential of the input signal IN1 changes to the first voltage -E1 as shown in FIG. 3(a), the potential of the inverted signal IN1 goes to the ground voltage GND, causing the P-channel MOSFET P12 to turn on and the P-channel MOSFET P13 to turn off. Therefore, the potential of the point A corresponds to the resistance division ratio (voltage division ratio) of the P-channel MOSFET P12 and the N-channel MOSFET N12. According to the relationship between the amplification factor gm.sub.p12 of the P-channel MOSFET P12 and the amplification factor gm.sub.N12 of the N-channel MOSFET N12, the potential of the point A changes gradually from the second voltage -E2 to the ground voltage GND, as shown in FIG. 3(c). On the other hand, the change of the potential at the point A places the N-channel MOSFET N13 in an ON state and the potential at the point B changes from the ground voltage GND to the second voltage -E2, as shown in FIG. 3(d). As a result, the N-channel MOSFET N12 goes to the OFF state and the potential at the point A changes from the second voltage -E2 to the ground voltage GND. In this way, because the potential at the point A is determined by the resistance division between of the p-channel MOSFET P12 and N-channel MOSFET N12 and the interaction with the potential of the point B, it changes gradually without a normal CMOS operation which is seen in the -E1 system inverter circuit 1. As describe above, in accordance with the potential at the point A changing from the second voltage -E2 to the ground voltage GND, the P-channel MOSFET P14 turns off and the N-channel MOSFET N14 turns on. This causes the potential of the output signal OUT1 to change from the ground voltage GND to the second voltage -E2.
Then, the operation of the interface circuit will be explained when the input signal IN1 changes from the first voltage -El to the ground voltage GND, as shown in FIG. 3(a). When the input signal IN1 is at the first voltage -E1, the inverted signal IN1 is at the ground voltage GND, the point A is at the ground voltage GND, the point B is at the second voltage -E2, and the output signal OUT1 is at the second voltage -E2. In this state, because the point A is at the ground voltage GND, the P-channel MOSFET P14 turns off, with the result that a through current does not flow in the -E2 system inverter circuit 3. In this case, when the input signal IN1 changes to the ground voltage GND, the inverted signal IN1 goes to the first voltage -El. This causes the P-channel MOSFET P12 to turn off and the P-channel MOSFET P13 to turn on. As a result, the potential at the point B corresponds to the resistance division ratio of the P-channel MOSFET P13 to the N-channel MOSFET N13. According to the relationship of gm.sub.p13 >gm.sub.N13, the potential at the point B gradually changes from the second voltage -E2 to the ground voltage GND. On the other hand, the change of the potential at the point B causes the N-channel MOSFET N12 to turn on. The potential at the point A thus changes to the second voltage -E2. The change of the potential at the point A causes the N-channel MOSFET N13 to go to the OFF state. Therefore, the potential at the point B finally equals the ground voltage GND and the potential at the point A goes to the second voltage -E2. In this way, since the potential at the point A is determined by the resistance division between the P-channel MOSFET P13 and N-channel MOSFET N13 and the interaction with the potential of the point B, it changes gradually without a normal CMOS operation, as seen in the -1 system inverter circuit 1. The second voltage -E2 at the point A is supplied to the gate electrodes of the P-channel MOSFET P14 and the N-channel MOSFET N14. This causes the P-channel MOSFET P14 to turn on and the N-channel MOSFET N14 to turn off, placing the potential of the output signal OUT1 at the ground voltage GND.
FIG. 4 shows a second conventional interface circuit. The interface circuit of FIG. 4 differs from that of FIG. 2 in the following points. In FIG. 2, the input terminal of the -E2 system inverted circuit 3d is connected to the gate electrode of the N-channel MOSFET N13 and the connection of the other end of the current path of the P-channel MOSFET P12 and one end of the current path of the N-channel MOSFET N12. In contrast, the input terminal of the -E2 system inverted circuit 3d of FIG. 4 is connected to the gate electrode of the N-channel MOSFET N12 and the connection of the other end of the current path of the P-channel MOSFET P13 and one end of the current path of the N-channel MOSFET N13. The remaining parts of the interface circuit of FIG. 4 is the same as that of FIG. 2, so that the same parts as those in FIG. 2 are indicated by the same reference characters and their explanation will be omitted. Further, the interface circuit of FIG. 4 differs from that of FIG. 2 in that the former supplies the output signal of an opposite phase to the input signal IN1. Specifically, in the interface circuit of FIG. 4, the output signal of the -E2 system inverter circuit 3d equals the second voltage -E2 when the input signal IN1 is at the ground voltage GND, and the same output signal goes to the ground voltage GND when the input signal IN1 is at the first voltage -El. Therefore, the inverted signal IN1 and the potentials at points A and B change as shown in FIGS. 3(b) through (d).
However, when the input signal IN1 changes from the ground voltage GND to the first voltage -E1 as in the first conventional example, the potential at the point B changes gradually, and the -E2 system flip-flop circuit does not perform a normal CMOS operation and changes gradually. This causes a period of time when the P-channel MOSFET P14 and N-channel MOSFET N14 turn on simultaneously, permitting a through current to flow through the -E2 system inverter circuit 3 between the ground voltage GND and the second voltage -E2. Further, when the input signal IN1 changes from the first voltage -E1 to the ground voltage GND, the potential at the point A does not perform a normal CMOS operation and changes gradually. This causes a period of time when the P-channel MOSFET P14 and N-channel MOSFET N14 of the -E2 system inverter circuit turn on simultaneously, permitting the through current to flow between the ground voltage GND and the second voltage -E2.

Level shifting low to high supply voltage interface circuit