A method of evicting a cache block from a congruence class in a cache of a multi-processor computer system. After a cache miss, one of the cache blocks in the congruence class is selected for eviction based on the cache coherency states of the cache blocks. Any block having an Invalid state is preferably selected but, if such a block is not present, then one is preferably selected that has an invalid-type state, such as the new Hover state. If there are many blocks in the Hover state, then the least recently used is deallocated. If neither of these types of blocks are present, then a block is preferably selected for deallocation which is in the Modified state. This intelligent approach to victim selection generally improves cache performance.

1. Field of the Invention
The present invention generally relates to computer systems, and more particularly to a method of selecting a cache line (victim) for deallocation from a cache used by a processor of a computer system.
2. Description of the Related Art
The basic structure of a conventional multi-processor computer system 10 is shown in FIG. 1. Computer system 10 has several processing units, two of which 12a and 12b are depicted, which are connected to various peripheral devices, including input/output (I/O) devices 14 (such as a display monitor, keyboard, and permanent storage device), memory device 16 (such as random access memory or RAM) that is used by the processing units to carry out program instructions, and firmware 18 whose primary purpose is to seek out and load an operating system from one of the peripherals (usually the permanent memory device) whenever the computer is first turned on. Processing units 12a and 12b communicate with the peripheral devices by various means, including a generalized interconnect or bus 20. Computer system 10 may have many additional components which are not shown, such as serial and parallel ports for connection to, e.g., modems or printers. Those skilled in the art will further appreciate that there are other components that might be used in conjunction with those shown in the block diagram of FIG. 1; for example, a display adapter might be used to control a video display monitor, a memory controller can be used to access memory 16, etc. The computer can also have more than two processing units.
In a symmetric multi-processor (SMP) computer, all of the processing units are generally identical, that is, they all use a common set or subset of instructions and protocols to operate, and generally have the same architecture. A typical architecture is shown in FIG. 1. A processing unit includes a processor core 22 having a plurality of registers and execution units, which carry out program instructions in order to operate the computer. An exemplary processing unit includes the PowerPC.TM. processor marketed by International Business Machines Corp. The processing unit can also have one or more caches, such as an instruction cache 24 and a data cache 26, which are implemented using high speed memory devices. Caches are commonly used to temporarily store values that might be repeatedly accessed by a processor, in order to speed up processing by avoiding the longer step of loading the values from memory 16. These caches are referred to as "on-board" when they are integrally packaged with the processor core on a single integrated chip 28. Each cache is associated with a cache controller (not shown) that manages the transfer of data between the processor core and the cache memory.
A processing unit can include additional caches, such as cache 30, which is referred to as a level 2 (L2) cache since it supports the on-board (level 1) caches 24 and 26. In other words, cache 30 acts as an intermediary between memory 16 and the on-board caches, and can store a much larger amount of information (instructions and data) than the on-board caches can, but at a longer access penalty. For example, cache 30 may be a chip having a storage capacity of 256 or 512 kilobytes, while the processor may be an IBM PowerPC.TM. 604-series processor having on-board caches with 64 kilobytes of total storage. Cache 30 is connected to bus 20, and all loading of information from memory 16 into processor core 22 must come through cache 30. Although FIG. 1 depicts only a two-level cache hierarchy, multi-level cache hierarchies can be provided where there are many levels (L3, L4, etc.) of serially connected caches.
In an SMP computer, it is important to provide a coherent memory system, that is, to cause write operations to each individual memory location to be serialized in some order for all processors. For example, assume a location in memory is modified by a sequence of write operations to take on the values: 1, 2, 3, 4. In a cache coherent system, all processors will observe the writes to a given location to take place in the order shown. However, it is possible for a processing element to miss a write to the memory location. A given processing element reading the memory location could see the sequence 1, 3, 4, missing the update to the value 2. A system that implements these properties is said to be "coherent". Virtually all coherency protocols operate only to the granularity of the size of a cache block. That is to say, the coherency protocol controls the movement of and write permissions for data on a cache block basis and not separately for each individual memory location.
There are a number of protocols and techniques for achieving cache coherence that are known to those skilled in the art. At the heart of all these mechanisms for maintaining coherency is the requirement that the protocols allow only one processor to have a "permission" that allows a write to a given memory location (cache block) at any given point in time. As a consequence of this requirement, whenever a processing element attempts to write to a memory location, it must first inform all other processing elements of its desire to write the location and receive permission from all other processing elements to carry out the write. The key issue is that all other processors in the system must be informed of the write by the initiating processor before the write occurs. Furthermore, if a block is present in the L1 cache of a given processing unit, it is also present in the L2 and L3 caches of that processing unit. This property is known as inclusion and is well known to those skilled in the art. Henceforth, it is assumed that the principle of inclusion applies to the caches related to the present invention.
To implement cache coherency in a system, the processors communicate over a common generalized interconnect (i.e., bus 20). The processors pass messages over the interconnect indicating their desire to read or write memory locations. When an operation is placed on the interconnect, all of the other processors "snoop" (monitor) this operation and decide if the state of their caches can allow the requested operation to proceed and if so, under what conditions. There are several bus transactions that require snooping and follow-up action to honor the bus transactions and maintain memory coherency. The snooping operation is triggered by the receipt of a qualified snoop request, generated by the assertion of certain bus signals. Instruction processing is interrupted only when a snoop hit occurs and the snoop state machine determines that an additional cache snoop is required to resolve the coherency of the offended sector.
This communication is necessary because, in systems with caches, the most recent valid copy of a given block of memory may have moved from the system memory 16 to one or more of the caches in the system (as mentioned above). If a processor (say 12a) attempts to access a memory location not present within its cache hierarchy, the correct version of the block, which contains the actual (current) value for the memory location, may either be in the system memory 16 or in one of more of the caches in another processing unit, e.g. processing unit 12b. If the correct version is in one or more of the other caches in the system, it is necessary to obtain the correct value from the cache(s) in the system instead of system memory.
For example, consider a processor, say 12a, attempting to read a location in memory. It first polls its own L1 cache (24 or 26). If the block is not present in the L1 cache, the request is forwarded to the L2 cache (30). If the block is not present in the L2 cache, the request is forwarded on to lower cache levels, e.g., the L3 cache. If the block is not present in the lower level caches, the request is then presented on the generalized interconnect (20) to be serviced. Once an operation has been placed on the generalized interconnect, all other processing units snoop the operation and determine if the block is present in their caches. If a given processing unit has the block of data requested by processing unit in its L1 cache, and that data is modified, by the principle of inclusion the L2 cache and any lower level caches also have copies of the block (however, their copies are stale, since the copy in the processor's cache is modified). Therefore, when the lowest level cache (e.g., L3) of the processing unit snoops the read operation, it will determine that the block requested is present and modified in a higher level cache. When this occurs, the L3 cache places a message on the generalized interconnect informing the processing unit that it must "retry" it's operation again at a later time, because the actual value of the memory location is in the L1 cache at the top of the memory hierarchy and must be retrieved to make it available to service the read request of the initiating processing unit.
Once the request from an initiating processing unit has been retried, the L3 cache begins a process to retrieve the modified data from the L1 cache and make it available at the L3 cache, main memory or both, depending on the exact details of the implementation which are not specifically relevant to this invention. To retrieve the block from the higher level caches, the L3 cache sends messages through the inter-cache connections to the higher level caches, requesting that the block be retrieved. These messages propagate up the processing unit hierarchy until they reach the L1 cache and cause the block to be moved down the hierarchy to the lowest level (main memory) to be able to service the request from the initiating processing unit.
The initiating processing unit eventually re-presents the read request on the generalized interconnect. At this point, however, the modified data has been retrieved from the L1 cache of a processing unit and the read request from the initiating processor will be satisfied. The scenario just described is commonly referred to as a "snoop push". A read request is snooped on the generalized interconnect which causes the processing unit to "push" the block to the bottom of the hierarchy to satisfy the read request made by the initiating processing unit.
The essential point is that, when a processor wishes to read or write a block, it must communicate that desire with the other processing units in the system in order to maintain cache coherence. To achieve this, the cache coherence protocol associates with each block in each level of the cache hierarchy, a status indicator indicating the current "state" of the block. The state information is used to allow certain optimizations in the coherency protocol that reduce message traffic on the generalized interconnect and the inter-cache connections. As one example of this mechanism, when a processing unit executes a read it receives a message indicating whether or not the read must be retired later. If the read operation is not retried, the message usually also includes information allowing the processing unit to determine if any other processing unit also has a still active copy of the block (this is accomplished by having the other lowest level caches give a "shared" or "not shared" indication for any read they do not retry). Therefore, a processing unit can determine whether any other processor in the system has a copy of the block. If no other processing unit has an active copy of the block, the reading processing unit marks the state of the block as "exclusive". If a block is marked exclusive it is permissible to allow the processing unit to later write the block without first communicating with other processing units in the system because no other processing unit has a copy of the block. Therefore, it is possible for a processor to read or write a location without first communicating this intention onto the interconnection, but only where the coherency protocol has insured that no other processor has an interest in the block.
The foregoing cache coherency technique is implemented in a specific protocol referred to as "MESI," and illustrated in FIG. 2. In this protocol, a cache block can be in one of four states, "M" (Modified), "E" (Exclusive), "S" (Shared) or "I" (Invalid). Under the MESI protocol, each cache entry (e.g., a 32-byte block) has two additional bits which indicate the state of the entry, out of the four possible states. Depending upon the initial state of the entry and the type of access sought by the requesting processor, the state may be changed, and a particular state is set for the entry in the requesting processor's cache. For example, when a block is in the Modified state, the addressed block is valid only in the cache having the modified block, and the modified data has not been written back to system memory. When a block is Exclusive, it is present only in the noted block, and is consistent with system memory. If a block is Shared, it is valid in that cache and in at least one other cache, all of the shared blocks being consistent with system memory. Finally, when a block is Invalid, it indicates that a valid copy of the addressed block is not resident in the cache. As seen in FIG. 2, if a block is in any of the Modified, Shared or Invalid states, it can move between the states depending upon the particular bus transaction. While a block in an Exclusive state can move to any other state, a block can only become Exclusive if it is first Invalid.
The blocks in any set-associative cache are divided into groups of blocks called "sets". A set is the collection of blocks that a given memory block can reside in. For any given memory block, there is a unique set in the cache (a congruence class) that the block can be mapped into, according to preset mapping functions. However, several different blocks in main memory can be mapped to any given set. The number of blocks in a set is referred to as the associativity of the cache (e.g. 2-way set associative means that for any given memory block, there are two blocks in the cache that the memory block can be mapped into). When all of the blocks in a set for a given cache are full and that cache receives a request, whether a "read" or "write," to a memory location that maps into the full set, the cache must evict one of the blocks currently in the set. The cache chooses a block by one of a number of means known to those skilled in the art (least recently used (LRU), random, pseudo-LRU, etc.) to be evicted. If the data in the chosen block is modified, that data is written to the next lowest level in the memory hierarchy which may be another cache (in the case of the L1 or on-board cache) or main memory (in the case of an L2 cache, as depicted in the two-level architecture of FIG. 1). By the principle of inclusion, the lower level of the hierarchy will already have a block available to hold the written modified data. However, if the data in the chosen block is not modified, the block is simply abandoned and not written to the next lowest level in the hierarchy. This process of removing a block from one level of the hierarchy is known as an eviction. At the end of this process, the cache no longer holds a copy of the evicted block.
A typical LRU eviction mechanism is shown in FIG. 3. A cache (L1 or a lower level) includes a cache directory 32, an LRU array 34, and control logic 36 for selecting a block for eviction from a particular congruence class. The depicted cache is 8-way set associative, and directory 32 has a specific set of eight blocks for a particular congruence class (the cache entry array, not shown, also has eight blocks per class). Each congruence class in the directory has a corresponding collection of LRU information associated with it in LRU array 34.
If a cache miss occurs, and if all of the blocks in the particular congruence class have been previously filled in response to earlier read and write operations, then one of the cache blocks in congruence class must be selected for victimization. This selection is performed using the LRU bits for the congruence class in LRU array 34. For each congruence class, there are a plurality of LRU bits, for example, three LRU bits per block for an 8-way set associative cache. The LRU bits from each block in the class are provided as inputs to control logic 36 which has an 8-bit output to indicate which of the blocks is to be victimized, according to known algorithms which examine the LRU bits from each block. This output can be coupled to a multiplexer which passes on an indication of the cache block to be used for eviction.
One problem with prior art SMP systems relates to the eviction of a block having a data value which is in a coherency state that suggests it should not be evicted. For example, in the prior art MESI protocol, a particular congruence class might have several members which are in the Modified state, and several members which are in the Invalid state, and the least recently used block may be any of these blocks. In the case where a Modified block is the least recently used, that block will be evicted rather than one of the Invalid state blocks. This outcome is undesirable since it is likely that the Modified block would be accessed again by the processor core in the near future. Similarly, it might be preferable in some instances to evict a Modified block rather than evicting a Shared block, but conventional deallocation mechanisms are incapable of performing such intelligent victim selection. This inefficiency imposes a performance degradation and is a limitation of the prior art systems. It would, therefore, be desirable to devise an improved victim selection mechanism which made use of coherency state information. It would be further advantageous if the method were easily applied to new coherency states as well.

Cache with enhanced victim selection using the coherency states of cache lines

International Business Machines Corporation


A method for detecting stall of a multiphase motor operated in a sinusoidal micro-stepped mode. The method comprises: a) measuring at least one phase current and/or measuring the sum of all phase currents at regular time intervals synchronous with the micro-steps, b) calculating the difference between the measured phase current at a first moment and the measured phase current of the same phase at a previous moment and/or the difference between the measured sum of all phase currents at a first moment and the measured sum of all phase currents at a previous synchronous moment, c) analyzing the series of obtained current differences so as to generate a stall detection signal.

Stall detection aims at detecting if a motor is not rotating or is blocked. Prior art methods for stall detection in a synchronous multiphase motor are based on back electromotive force (BEMF) measurements. When a synchronous multiphase motor is driven in sine mode, the sinusoidal BEMF voltage increases in a linear way with the speed of the motor. When the motor speed goes from normal to zero this can be detected by monitoring the BEMF drop. In prior art solutions the BEMF voltage is measured by using one floating phase on which the BEMF voltage can be measured. This has, however, as disadvantage that this floating phase is not contributing to the motor power. Besides decreasing the motor power, this also causes unwanted or noisy torque ripples.
Therefore, solutions are sought for stall detection whilst driving all phases of the multiphase motor. US20160013743A1, for example, discloses a method for stall detection based on motor current increase during stall. However, this does not work in all cases. This method cannot be used for low-speed motors with low-BEMF level. The current increase due to the absence of the low-BEMF is too small for reliable detection.
In view of these stall detection problems, there is room for improved methods and circuits for stall detection of a multiphase motor which is driven using sinusoidal micro-stepping.

Method and electronic circuit for stall detection


A mediator system (and associated methods and computer program products) for mediating a communication between a client and a plurality of providers within a network is described. The mediator system may include logical machines including a first receiving machine configured to receive a request message from the client, a first sending machine configured to send answer messages back to the client, a processing machine configured to handle the received request message internally represented as a request object, a second sending machine configured to send outgoing request messages to the providers, and a second receiving machine configured to receive incoming answer messages from the providers. The machines can be scheduled separately from being executed, and the request object may be split into subrequests, where each of those subrequests may be further decomposed into subsubrequests that may be sent out in parallel to the providers.

Message-based interactions in Enterprise Application Integration (EAI) or BusinesstoBusiness (B2B) scenarios introduce a new level of complexity, especially if the partners involved in those scenarios have different notions on how these interactions should happen. Heterogeneity not only occurs at the data level, which means that the partners use different message formats, but also on the protocol/process level, which means that an expected number and a flow of messages within an interaction step may also differ between the partners involved. It is possible for example that one partner may always expect a confirmation for messages it has sent out to other entities whereas those entities do not necessarily acknowledge all received messages. Furthermore, it is possible that a receiving partner may expect information to be sent in pieces, i.e., in several messages, whereas a sending partner will provide all necessary information within a single message and expect a single answer.

System and a method for mediating within a network


A method is disclosed for varying a mechanical property of a material at two depths. The method involves the application of at least two laser pulses of different durations. The method involves a determination of the density of the material from the surface to each depth, a determination of the heat capacity of the material from the surface to each depth, and a determination of the thermal conductivity of the material from the surface to each depth. Each laser pulse may affect the density, heat capacity, and thermal conductivity of the material, so it may be necessary to re-evaluate those parameters after each laser pulse and prior to the next pulse. The method may be applied to implantation materials to improve osteoblast and osteoclast activity.

Manufactured materials are often used in human and animal bone and joint replacement implantation procedures. Examples of such implants are replacement knee and hip joint components, and dental crowns and bridges. Ideally, such implants would last beyond the life expectancy of the recipient. However often the manufactured material fails in situ and a further replacement is needed. Failure of implants and the revision surgery associated with their replacement present an increasing burden to society, especially with higher life expectancies and the modern disposition to obesity. In the United States, mortality caused by hip fractures alone accounts for approximately 1% of all deaths, resulting in an estimated 33,100 life-years lost annually. In 2004, fractures accounted for 1 to 2% of total health care costs, amounting to a $20 to $40 billion burden that is projected to rise to between $40 and $80 billion in 2015. The American Academy of Orthopedic Surgeons reports an increase in partial hip replacements in the United States from 112,000 in 1998 to 240,000 in 2004. A hip replacement lasts for only about 10 to 15 years and sometimes even fails within the first year. In 2004, there were 46,000 revision hip surgeries.
Many techniques have been developed to control the bulk properties of advanced materials, such as those used in implants. Techniques have also been developed for the preparation and modification of the surface of advanced materials. However, in many applications of advanced materials the structuring of bulk properties and surface properties are inadequate to meet all of the desired characteristics of advanced materials. Examples of such circumstances are at points of interface with other materials where localized stresses may cause a material failure. What are needed therefore are techniques to modify the properties of advanced materials through a controllable depth, such as at localized points of interface with other materials

Method of varying a physical property of a material through its depth


A turbo refrigerator (1) includes: a turbo compressor (5) to which a gas-phase component (X3) of a refrigerant from an economizer (3) is supplied, wherein the turbo compressor (5) includes a first flow path (R10) through which a compressed refrigerant gas (X1) flows, and a connecting pipe (5b) connected to the first flow path (R10) and a second flow path (R3) through which the gas-phase component (X3) of the refrigerant flows, and the diameter of the connecting pipe (5b) reduces toward the first flow path (R10) from the second flow path (R3).

In the past, in a turbo refrigerator, heat transport has been performed by circulating a refrigerant between a condenser and an evaporator, condensing the refrigerant compressed in a turbo compressor, in the condenser, and evaporating the condensed refrigerant in the evaporator.
In order to efficiently vaporize the refrigerant in the evaporator, it is desirable that there is less of a gas-phase component which is contained in the refrigerant which is supplied to the evaporator. For this reason, as shown in, for example, Patent Document 1, an economizer is installed ahead of an evaporator, and thus a gas-phase component of a refrigerant which is supplied to the economizer is removed, and the removed gas-phase component of the refrigerant is returned to a turbo compressor.
Patent Document 2 and Patent Document 3 disclose the detailed configuration of a site where in Patent Document 1, the removed gas-phase component of the refrigerant is returned from the economizer to the turbo compressor.


A method of producing extruded ceramic products by extruding a ceramic forming material through an extruding opening, includes a step of coating a liquid, which is nonvolatile at ordinary room temperatures, on a surface of an extruded ceramic product. The liquid is preferably coated on the surface with the aid of capillary action. An apparatus for producing extruded ceramic products includes a forward end portion having an extruding opening for extruding a ceramic forming material and a guide passage for introducing the ceramic forming material into the extruding opening, a liquid supply section provided on the forward end portion for supplying a liquid, which is nonvolatile at ordinary room temperatures, to an outer surface of a product of the ceramic forming material extruded from the extruding opening, and a liquid supply device for supplying the liquid to the liquid supply section.

This invention relates to a method and an apparatus for producing extruded ceramic green products, and more particularly to a method and apparatus for producing ceramic honeycomb structures as catalyst carriers.
In order to produce, for example, ceramic honeycomb structures up to the present, after a ceramic material has been mixed and kneaded in a kneader, the kneaded product was extruded in column-shaped bodies in suitable sizes from a vacuum auger machine and the column-shaped bodies were supplied into a plunger molding machine from which the bodies were extruded.
FIG. 1 illustrates in section a vacuum auger machine to be used for the purpose described. The vacuum auger machine includes a vacuum kneading section having a screw-type mill 23 and a vacuum chamber 24 for kneading the ceramic material to obtain ceramic batches for forming the products, a ceramic batch transfer section having an auger 25 for transferring the ceramic batches in the vacuum chamber 24, and a column-shaped green product forming section having a forming column ring 1 for forming the ceramic batch transferred by the auger 25 into column-shaped green products. These sections are located on a frame 27.
The screw-type mill 23 is used for transferring the ceramic material supplied from a ceramic material supply opening 22 into the vacuum chamber 24, while the ceramic material is being kneaded. In the vacuum chamber 24, bubbles and the like in ceramic batches supplied as kneaded batches for forming are removed and the ceramic batches are loosened when falling by gravity and then supplied to the ceramic batch transfer section.
The ceramic batch supplied into the ceramic batch transfer section is transferred while being compressed by the auger. When the ceramic batch is transferred by the auger, it passes through a grid drum 9 to be crushed and loosened so as to remove laminations included in the ceramic batches. Thereafter, the ceramic batch passes through a guide passage 19 of the forming column ring 1, while being formed into a column-shaped green product which is then extruded at an extruding opening 11 as shown by an arrow A in FIG. 1.
The resultant column-shaped green product is cut in predetermined lengths by a cutter (not shown) provided on a side of the outlet of the forming column ring 1. The column-shaped products of the predetermined lengths are then supplied to a plunger molding machine (not shown) preparatory to a next process. In this case, the column-shaped products must have diameters and lengths permitting the products to be inserted into a cylinder of the plunger molding machine. These column-shaped products are then caused to pass through an extruding die of the plunger molding machine, thereby producing honeycomb structures.
The above explained method is so-called "batch process", wherein the column-shaped products extruded from the extruding opening 11 of the vacuum auger machine shown in FIG. 1 have to be loaded one by one into the plunger molding machine for the next process by means of a movable loading machine.
In this case, however during this loading process the column-shaped products stay in a stock yard for a period of time until they are loaded into the plunger molding machine. During such an awaiting period, moisture tends to evaporate from surfaces of the column-shaped products to be locally dried and hardened. Moreover, such a drying may take place until they are extruded from a plunger cylinder of the plunger molding machine in the next process.
The dried outer surfaces of the column-shaped products detrimentally affect resultant products having a predetermined shape obtained through an extruding die by an actuation of a ram head by means of a hydraulic plunger. In more detail, the hardened surfaces make rough outer surfaces of extruded honeycomb structures or the hardened portions of ceramic batch mix with inner material of the formed structures to cause strains therein or forming grooves of a forming die are partially clogged with the hardened ceramic material to cause defects in the extruded honeycomb structures.
In the batch process, moreover, the honeycomb structures extruded from the plunger molding machine are left as extruded until next drying process. In the same manner above described, therefore, the honeycomb structures are partially dried and suffer cracks or uniform construction of the structures can not be obtained in the next drying and firing processes so that strains imperatively remain in the structures. In general, the outer surfaces of the extruded products are considerably dried by frictional heat caused by contact resistance between the ceramic batch and extruding dies.

Method for producing extruded ceramic products


To provide a liquid crystal display device having high quality display by obtaining a high aperture ratio while securing a sufficient storage capacitor (Cs), and at the same time, by dispersing a load (a pixel writing-in electric current) of a capacitor wiring in a timely manner to effectively reduce the load. A scanning line is formed on a different layer from a gate electrode and the capacitor wiring is arranged so as to be parallel with a signal line. Each pixel is connected to the individually independent capacitor wiring via a dielectric. Therefore, variations in the electric potential of the capacitor wiring caused by a writing-in electric current of a neighboring pixel can be avoided, whereby obtaining satisfactory display images.

1. Field of the Invention
The present invention relates to a semiconductor device having a circuit constructed of a thin film transistor (hereinafter referred to as TFTs) and a method of manufacturing the same. For example, the present invention relates to an electro-optical device typified by a liquid crystal display panel, and electronic equipment having such an electro-optical device mounted thereon as a part.
It is to be noted that a semiconductor device as used herein throughout the present specification denotes a general device which functions by utilizing semiconductor characteristics, and that electro-optical devices, semiconductor circuits, and electronic equipments are all semiconductor devices.
2. Description of the Related Art
Techniques for structuring a thin film transistor (TFT) using a semiconductor thin film (having a thickness on the order of about several to several hundred nm) formed on a substrate having an insulating surface have been in the spotlight in recent years. Thin film transistors are widely applied to electronic devices such as an IC or an electro-optical device, and in particular, development of the TFT as a switching element of a liquid crystal display device is proceeding rapidly.
In order to obtain high quality images in the liquid crystal display device, an active matrix type liquid crystal display device that utilizes TFTs as switching elements to be connected to respective pixel electrodes which are arranged in matrix is attracting much attention.
It is necessary that the electric potential of an image signal is held in each pixel electrode connected to the TFTs until the next write-in time in order to perform good quality display in the active matrix type liquid crystal display device. Generally, the provision of a storage capacitor (Cs) in each pixel holds the electric potential of the image signal.
Various proposals have been made for the structure and the formation methods of the above stated storage capacitor (Cs). However, from the viewpoint of reliability or simplicity of the manufacturing process, it is preferable that, of the insulating films for structuring a pixel, a gate insulating film of a TFT, which has the highest quality is utilized as a dielectric of the storage capacitor (Cs). Conventionally, as shown in FIG. 18, a capacitor wiring that becomes an upper electrode is first provided by utilizing a scanning line, and then the formation of the storage capacitor (Cs) is carried out by using the upper electrode (capacitor wiring), a dielectric layer (gate insulating film), and a lower electrode (semiconductor film).
Also, from the viewpoint of display performances, there is a demand for giving pixels larger storage capacitors as well as making the aperture ratio higher. Efficient utilization of a back light is improved if each pixel has a high aperture ratio. Consequently, the amount of back light for obtaining a predetermined display luminance can be restrained, and therefore attainment of a power-saving and small scale display device can be achieved. Furthermore, each pixel is provided with a large storage capacitor, thereby improving the characteristic of each pixel in holding display data, to improve the display quality. In addition, in case of point sequential driving of the display device, a signal storage capacitor (sample hold capacitor) is required in the driver circuit side of each signal line. However, with the provision of a large storage capacitor in each pixel, a surface area occupied by the sample hold capacitor can be made smaller, and therefore the display device can be made smaller.
Such demands become problems in proceeding with the progress of making the pitch of each display pixel microscopic which accompanies the progress of making a liquid crystal display device smaller and high definition (increasing the number of pixels).
There is an additional problem in that it is difficult to make a high aperture ratio and a large storage capacitor compatible with each other in the above stated conventional pixel structure.
An example in which a conventional pixel structure having the size of a pixel formed to 19.2 xcexcm in accordance with the design rule of Table 1 is shown in FIG. 18.
A characteristic of the conventional pixel structure is that two wirings (a scanning line and a capacitor wiring) are arranged parallel to each other in relation to the continuous formation of the two respective wirings, the scanning line and the capacitor wiring. In FIG. 18, reference numeral 10 denotes a semiconductor film, 11 denotes a scanning line, 12 denotes a signal line, 13 denotes an electrode, and 14 denotes a capacitor wiring. Note that FIG. 18 is a simplified top view of the pixel, and therefore a pixel electrode that is connected to the electrode 13 and a contact hole that reaches the electrode 13 are both not shown in the figure.
Thus, in the case of structuring the storage capacitor with a upper electrode (capacitor wiring), a dielectric layer (gate insulating film), and a lower electrode (semiconductor film), all the circuit elements (a pixel TFT, a storage capacitor, a contact hole, ect.) necessary for structuring a circuit of the pixel become elements relevant to a gate insulating film. Accordingly, these elements constituting the circuit elements are arranged almost planarly within each pixel.
Therefore, it is crucial to efficiently layout the circuit elements that are necessary for constructing the circuit of the pixel in order to attain both a high aperture ratio and a large storage capacitor of each pixel within the regulated pixel size. In other words, from the fact that all the circuit elements are in connection with the gate insulating film, it can be said that it is essential to improve the efficiency of utilizing the gate insulating film.
Thus, from the above perspective, an efficient planar layout of the example of the circuit structure of a pixel of FIG. 18 is shown in FIG. 19. In FIG. 19, reference numeral 21 denotes a single pixel region, 22 denotes a pixel opening region, 23 denotes a storage capacitor region, 24 denotes an A region, and 25 denotes a portion of the TFT and a contact region.
With respect to the area of the pixel opening region 22 which is 216.7 xcexcm2 (aperture ratio of 58.8%) as shown in FIG. 19, it is composed of the areas of the storage capacitor region 23 which is 64.2 xcexcm2, the portion of the TFT and the contact region 25 which is 42.2 xcexcm2, and the A region 24 which is 34.1 xcexcm2.
The A region 24 is a segregation region of the scanning line and the capacitor wiring which originated from the fact that a wiring portion for mutually connecting a region that functions as a gate electrode of a TFT, the scanning line and the capacitor wiring are arranged parallel to each other. The gate insulating film of the A region is not rendered its original function, becoming a cause of reducing the efficiency of layout.
Further, in the case of the above structure, there is a problem in that the demand for a capacitor wiring resistance has become strict.
In a normal liquid crystal display device drive, the writing-in of the electric potential of the image signal to the plurality of pixels connected to each scanning line is performed consecutively in the scanning line direction (in the case of the point sequential drive) or all at the same time (in the case of the linear sequential drive).
In terms of arranging the capacitor wiring and the scanning line parallel to each other in the pixel structure as stated above, the plurality of pixels connected to the respective scanning lines are connected to a common capacitor wiring. Therefore, opposing electric currents for a plurality of pixels corresponding to the pixel writing-in electric current continuously or simultaneously flow in the common capacitor wiring. In order to avoid a reduction in display quality caused by the electric potential variation of the capacitor wiring, it is necessary to sufficiently lower the capacitor wiring resistance.
However, widening the width of the wiring for lowering the resistance of the capacitor wiring means that the surface area of the storage capacitor is enlarged while the aperture ratio of the pixel is reduced.
The present invention has been made in view of the above problems as a solution for the designing side, and therefore has an object to provide a liquid crystal display device having high quality display by obtaining a high aperture ratio while securing a sufficient storage capacitor (Cs), and at the same time, by dispersing a load (a pixel writing-in electric current) of the capacitor wiring in a timely manner to effectively reduce the load.
The structure of the invention disclosed in the present specification is a semiconductor device, characterized by comprising:
a first wiring on an insulating surface;
a first insulating film on said first wiring;
a semiconductor film on said first insulating film;
a second insulating film on said semiconductor film;
a second wiring and a gate electrode to be connected to said first wiring on said second insulating film;
a third insulating film on said second wiring and said gate electrode; and
a third wiring to be connected to said semiconductor film on said third insulating film.
In the above-mentioned structure, the semiconductor device is characterized in that the semiconductor film and the second wiring overlap via the second insulating film.
Further, in the above-mentioned respective structures, the semiconductor device is characterized in that a storage capacitor is formed with the second insulating film as a dielectric in a region where the second wiring and the semiconductor film overlap via the second insulating film.
Further, in the above-mentioned respective structures, the semiconductor device is characterized in that an impurity element that imparts a conductivity type is doped into the region of the semiconductor film where the second wiring overlaps via the second insulating film.
Further, in the above-mentioned respective structures, the semiconductor device is characterized by further comprising an electrode to be connected to the semiconductor film and a pixel to be connected to the electrode on the third insulating film.
Further, in the above-mentioned respective structures, the semiconductor device is characterized in that the first wiring and the second wiring are arranged in a direction orthogonal with each other.
Further, in the above-mentioned respective structures, the semiconductor device is characterized in that the first wiring is arranged in a direction orthogonal to the third wiring.
Further, in the above-mentioned respective structures, the semiconductor device is characterized in that the gate electrode is formed on a different layer from the first wiring.
Further, in the above-mentioned respective structures, the semiconductor device is characterized in that the gate electrode is patterned into an island shape.
Further, in the above-mentioned respective structures, the semiconductor device is characterized in that the first wiring comprises a scanning line.
Further, in the above-mentioned respective structures, the semiconductor device is characterized in that the second wiring comprises a capacitor wiring.
Further, in the above-mentioned respective structures, the semiconductor device is characterized in that the third wiring comprises a signal line.
Further, in the above-mentioned respective structures, the semiconductor device is characterized in that the second insulating film comprises a gate insulating film.
Further, in the above-mentioned respective structures, the semiconductor device is characterized in that the gate electrode is made of a film having as its principal constituent an element selected from the group consisting of poly-Si, W, WSix, Al, Ta, Cr, or Mo which have been doped with an impurity element that imparts a type of conductivity, or a lamination film of a combination of these elements.
Further, the structure of another invention is a semiconductor device, characterized by comprising:
a plurality of signal lines arranged parallel to each other at a predetermined interval and connected to a signal line driver circuit;
a plurality of scanning lines arranged parallel to each other at a predetermined interval and connected to a scanning line driver circuit; and
a capacitor wiring arranged parallel to the signal line.
Further, in the above-mentioned structures, the semiconductor device is characterized in that the scanning lines are orthogonal to the signal lines.
Further, in the above-mentioned respective structures, the semiconductor device is characterized by further comprising a thin film transistor having a gate electrode connected to the scanning line which is orthogonal to the signal line and a pixel electrode connected to the thin film transistor.
Further, in the above-mentioned respective structures, the semiconductor device is characterized in that the gate electrode is formed on a different layer from the scanning line.
Further, in the above-mentioned respective structures, the semiconductor device is characterized in that the gate electrode is patterned into an island shape.
Further, the structure of the invention to attain the above structure is a method of manufacturing a semiconductor device, characterized by comprising:
a first step of forming a first wiring on a substrate having an insulating surface;
a second step of forming a first insulating film on the first wiring;
a third step of forming a semiconductor film on the first wiring;
a fourth step of forming a second insulating film on the semiconductor film;
a fifth step of forming a first contact hole reaching the first wiring by selectively etching the first insulating film and the second insulating film;
a sixth step of forming a gate electrode on the second insulating film overlapping a portion of the semiconductor film and connected to the first wiring through the first contact hole;
a seventh step of forming a third insulating film on the gate electrode;
an eighth step of forming a second contact hole reaching the semiconductor film by selectively etching the second insulating film and the third insulating film; and
a ninth step of forming a third wiring on the third insulating film connected to the semiconductor film through the second contact hole.
Further, in the above-mentioned structure, the manufacturing method is characterized in that a second wiring is formed on the second insulating film to overlap a portion of the semiconductor film in the same step as forming the gate electrode.
Further, in the above-mentioned structure, the manufacturing method is characterized by further comprising a step of partially thinning the second insulating film that overlaps the second wiring after the step of forming the second insulating film on the semiconductor film.
Further, in the above-mentioned structure, the manufacturing method is characterized in that the second insulating film is a gate insulating film, the first wiring is a scanning line, the second wiring is a capacitor wiring, and the third wiring is a signal line.

Semiconductor device and method of manufacturing thereof

Semiconductor Energy Laboratory Co., Ltd.


An electronic discussion system including discussion terminals for writing and managing opinion information and clients for accessing the discussion terminals through a network. The electronic discussion system comprises a discussion apparatus for storing contents of input opinions so as to have correspondence relationships with discussion topics to which the contents pertain, contents of opinions having correspondence relationships with discussion topics in which registered users participate further having correspondence relationships with user divisions corresponding to the registered users; a participated discussion reading (client) terminal responsive to an operation instruction from a registered user, for referring to and displaying contents of opinions stored in the discussion server and having a corresponding relationship with a user division corresponding to the registered user; and a non-participated discussion reading (client) terminal responsive to an operation instruction from a user other than the registered users, for inputting an instruction for selecting a discussion topic, and obtaining and displaying contents of opinions stored in the discussion apparatus and having a correspondence relationship with the selected discussion topic.

The present invention relates to an electronic discussion system, and particularly to an electronic discussion system for exchanging information among a plurality of users through a network.
Heretofore, as an electronic discussion system using a network, there is a known electronic discussion system of the electronic bulletin board type, comprising a server machine including a function to accept requests for permission to present opinions (or messages) and a function to give permission to read opinions (or messages), and a client machine for accessing the server machine to perform opinion editing and writing processes. Information exchange in the electronic discussion system as described is achieved by storing information of all opinions in the server machine serving as a bulletin board.
As a system for sharing documents on the network, the xe2x80x9cReference System of Documents Scattered in the Networkxe2x80x9d revealed in JP-A-03-152641 is known by which a plurality of users refer to documents on the network.
In the electronic discussion system of the electronic bulletin board type according the prior art mentioned above, the server machine includes both the function to accept opinions (or messages) and the function to give permission to read opinions (or messages), for which reason, when many users participate in a discussion at the same point in time, the server machine is accessed concurrently by a number of client machines. Therefore, the processing load on the server machine is so heavy that the apparent processing performance of the system that is felt by the users trying to access it decreases greatly, which has been a problem.
In the prior art, the electronic discussion system is arranged such that, basically, only one server machine is used to record and manage all opinions (or messages) received, so that the load on the storage capacity in the server machine increases or decreases in proportion to the total amount of received opinion information. Another problem with the prior art is that as the total amount of received opinion information increases, the load on the storage capacity in the server machine increases. Accordingly, in a majority of the electronic discussion systems currently in use, this problem is avoided, as a rule, by limiting the kinds of opinion information to be recorded and managed to text data which imposes a relatively lesser load on the storage capacity.
The present inventors conducted the study from a standpoint of a user interested in discussions on many kinds of topics. Such a user makes access to the server machine charged with entry and management of opinions in various kinds of discussions at least once during a specific period of time to check to see if there is any opinion deserving attention. However, all unread opinions obtained by accessing the server machine are rarely objects of interest, and if no such opinion has been recorded, a problem is that accesses that have been made end up being wasteful.
With the foregoing in mind, the present invention has been made by the present inventors.
Therefore, a first object of the present invention is to provide an electronic discussion system in which even if requests to accept opinions (or messages) or grant permission to read opinions (or messages) concurrently come from a number of client machines, the processing load on the server machine will not become too large.
A second object of the present invention is to provide an electronic discussion system in which even if the total amount of received opinion information increases, the load on the storage capacity of a specific server machine is prevented from becoming too large.
A third object of the present invention is to provide an electronic discussion system which obviates the need to access the server machine only to check the contents of opinions.
To achieve the first and second objects mentioned above, the electronic discussion system according to the present invention includes servers for writing and managing opinion information, and clients for accessing the servers through a network, recording the opinion information in said servers, and referring to the opinion information which has already been recorded and which is being managed, wherein the servers comprise at least one storage server for holding detailed contents of various pieces of opinion information; and at least one discussion server for holding opinion indexes showing the storage locations of opinion contents of various pieces of opinion information corresponding to the opinion indexes, and wherein the clients comprise an opinion (or message) writing client for transferring and writing an opinion index made from newly received opinion information and the content of the newly received opinion itself into the discussion server and the storage server, respectively and a reading client for referring to the opinion indexes and the contents of the opinions which were recorded respectively in the discussion server and the storage server and which are being managed.
In the present invention, the discussion server holds many kinds of opinion list files classified by a topic, so that any of the opinion indexes can be selected as the object to express one""s opinion about or the reading object. The reading client machine, responding to a specified reading instruction, searches the discussion server for the opinion indexes in the list files, which correspond to a specific topic as the reading object, and displays those opinion indexes. The reading client also and searches the storage server for an opinion content corresponding to a specific opinion index selected from the displayed opinion indexes and displays that opinion.
In the method described above, a part of the process related to expressing an opinion to a discussion and reading the contents of a discussion is executed by a client machine making the request to execute the process. Also, even if a number of client machines concurrently send requests for a process to express or read an opinion, the processing load will not become too heavy on a specific server machine. Moreover, a plurality of server machines (at least one discussion server and one storage server) are provided so that one piece of information about an opinion is divided into an opinion index and an opinion content when it is stored, and therefore even if the total amount of received opinion information increases, the load on the storage capacity on a specific server machine will not become too large.
To achieve the third object, in the present invention, the reading client machine is either a participating discussion reading client machine, for which at least one of the topics of discussion has been specified as a steady reading object, or a non-participating discussion reading client machine without any specified steady topic for reading. The discussion server machine holds a discussion participants list including information about the discussion topics specified as the steady reading objects by the participating discussion reading client machines, additionally records the opinion indexes sent from the opinion writing client machine onto the related opinion list file, and allots, according to the discussion participants list, the opinion indexes to all of the participated discussion reading client machines, for which topics have been specified as steady reading objects. Further, in the present invention, a user division server holding multiple kinds of list files of allotted opinion indexes sent from the discussion server and classified by the topics is provided for each group of participating discussion reading client machines. Each group includes at least one participating discussion reading client machine. The participating discussion reading client machine, according to a specified reading instruction, searches for the opinion indexes in the allotted opinion list file from the corresponding user division server, and displays the opinion indexes, and searches for an opinion content corresponding to a specific opinion index selected from the displayed opinion indexes, and displays the opinion.
Under the above arrangement, when any opinion is presented to a discussion in which a certain user is participating, since the opinion index of the received opinion is automatically allotted to the client machine that user is using or to the user division server to which the user belongs, it is not necessary for the user to check if there is any opinion which is of interest by making access to the discussion servers or the storage servers which are often located in relatively remote places.

Electronic discussion system for exchanging information among users creating opinion indexes in accordance with content of each options


A method of making a semiconductor device includes forming a passivation layer overlying a semiconductor substrate, the semiconductor substrate having a first region and a second region, wherein the first region is a conductive pad and the second region is adjacent to the first region. The method further includes forming a first protective layer overlying the passivation layer and forming an interconnect layer overlying the first protective layer. The method further includes forming a plurality of slots in the second region and forming a second protective layer overlying the interconnect layer, wherein the second protective layer fills each slot of the plurality of slots. The method further includes exposing a portion of the interconnect layer through the second protective layer; forming a barrier layer on the exposed portion of the interconnect layer; and forming a solder bump on the barrier layer.

Modern integrated circuits are made up of millions of active devices such as transistors and capacitors. These devices are initially isolated from each other, but are later interconnected together to form functional circuits. Typical interconnect structures include lateral interconnections, such as metal lines (wirings), and vertical interconnections, such as via openings and contacts. Interconnections are increasingly determining the limits of performance and the density of modern integrated circuits. On top of the interconnect structures, bond pads are formed and exposed on the surface of the respective chip. Electrical connections are made through bond pads to connect the chip to a package substrate or another die. Bond pads can be used for wire bonding or flip-chip bonding. Flip-chip packaging utilizes bumps to establish electrical contact between a chip's I/O pads and the substrate or lead frame of the package. Structurally, a bump actually contains the bump itself and an "under bump metallurgy" (UBM) located between the bump and an I/O pad.
Wafer level chip scale packaging (WLCSP) is currently widely used for its low cost and relatively simple processes. In a typical WLCSP, post-passivation interconnect (PPI) lines such as redistribution lines (RDLs) are formed on passivation layers, followed by the formation of polymer films and bumps. The PPI formation processes known to the inventors, however, have polymer film peeling issues, which may induce weak interfaces in the PPI structure and cause failures in the device.

Method of making a semiconductor device having a post-passivation interconnect structure

Taiwan Semiconductor Manufacturing Company, Ltd.


A device electrically interconnects a high voltage cable to a bushing of a deadfront electrical apparatus or switchgear. The device comprises a feed-through bushing and a separate U-member. The U-member can be installed onto, or removed from, the bushings without having to disconnect the ground. A driver mechanism applies a force to the U-member at a location substantially midway between two parallel legs of the U-member for installing or removing the U-member without cocking of the legs. The U-member carries female contacts which are engageable with male contacts of the bushings.

The invention relates to methods and apparatus for making and breaking electrical connection with electrical equipment such as transformers, switchgear, or cables.
Deadfront switchgear has been replacing livefront apparatus because of the safety, lower cost and increased operability of the deadfront system. Since there is no exposed voltage, safety is increased for both the operator and the public. In addition, the ability to operate easily and efficiently either with grounded, visible break connection points or loadbreak connection points by means of hotstick operation with a one or two man crew, lessens the operating danger. The deadfront system has proven to be extremely reliable with very low failure rate.
In practice, 600 ampere T-connectors have been used in these deadfront systems because they permit deadfront connection and visible disconnection by hotstick while the device is grounded. Visible disconnection is achieved by backing the T-connector off the 600 ampere bushing with a tool operated by a shotgun stick. One of the drawbacks to the use of T-connectors, however, is the bulky and stiff 600 ampere cable attached to the T-connector which makes it difficult to handle the T-connector.
It has also been proposed to interconnect T-connectors by means of a generally U-shaped member in which the legs of the "U" carry male contacts which connect with female contacts of the T-connectors. The legs are interconnected by a buss portion which includes means for connecting a ground wire and provides access to a threaded actuator in each leg for applying the U-member to the T-connectors. This is accomplished by rotating the actuators alternately in step-by-step fashion, i.e., by advancing a first leg incrementally, and then a second leg incrementally, and then the first leg, and so on, until both legs are fully mounted on the bushings. Removal of the U-member is achieved by performing that operation in reverse. Such U-members avoid the need to insert and remove the T-connectors as often, thereby lessening the frequency at which it is necessary to manipulate the stiff 600 amp cables. However, in order to access the actuators, it is necessary to remove the ground connector from the bight portion of the U-member. This creates a danger if the system is accidentally re-energized before the ground can be re-established.


A chair has a frame, a main link having an inner end pivoted on the frame about an inner axis fixed relative to the frame and an outer end defining an outer axis parallel to the inner axis. An outer arm has an inner end pivoted at the outer axis on the outer axis of the main link and an outer end carrying a footrest. An inner wheel is fixed nonrotatably on the frame at the inner axis, and an outer wheel is fixed nonrotatably on the inner end of the outer arm at the outer axis. A chain, belt, or the like connected to both of the wheels couples same together for joint synchronous rotation. A drive can pivot the main link about the inner axis and thereby pivot the outer arm about the outer axis.

A recliner chair has a footrest that can move between a retracted position extending vertically and tucked underneath a front edge of the seat cushion and an extended position extending horizontally and positioned in front of and generally level with the seat cushion. The footrest moves into the extended position as other elements of the chair's mechanism tilt the chairs backrest rearwardly and normally also lower a rear end of the seat cushion or raise its front end.
The standard mechanism for shifting the footrest is formed by a pair of horizontally spaced scissor linkages having unequal legs to effect the arcuate and twisting movement of the footrest. These linkages have to be identical and function identically to ensure smooth movement of the footrest.
Not only are these scissor linkages fairly complex so that they add considerably to the cost of the chair, but they present a real danger of pinching the user or the user's clothing. It is critical to keep anything delicate out of contact with the scissor link-ages since they can damage or, at the very least, dirty anything that touches or gets tangled in them.

Stanzwerk Wetter Sichelschmidt GmbH & Co. KG


A system which integrates the multiple instruction queues and the branch target cache (BTC) of a high performance CPU design into a single physical structure. Effectively, the queues are merged into the BTC in such a manner that, at any point in time, most of this structure functions as a BTC while certain entries function as instruction queues.. By using parts of the BTC to serve as instruction queues, the inefficiency of separate queue structures is eliminated and the queues are implemented with the greater device density characteristic of the RAM structure which the BTC core is based on. This merging of these structures also substantially simplifies the instruction queue control and the routing of instruction words between BTC entries and queues.

As computer designers have designed increasingly higher performance implementations of various computer architectures, a number of classes of techniques have been developed to achieve these increases in performance. Broadly speaking, many of these techniques can be categorized as forms of pipelining, caching, and hardware parallelism.
For most architectures, branching or (sequential) control transfer type instructions are an important class of instructions. For high performance implementations, this is particularly true due to the break in the sequential fetching of instructions that is implied by branches, jumps, calls, and returns. This stems from the attempt to maximize the pipelined, parallel processing of multiple instructions during each clock cycle. This characteristic results in the need to fetch subsequent instructions into the CPU pipeline at a rate approaching one per clock cycle.
While processing physically sequential instructions (in main memory), this is relatively easily attained since fetch address generation and instruction fetch latency can be appropriately pipelined. When a control transfer instruction is encountered, though, this instruction fetching process must be redirected to the target address of the instruction and fetching restarted. This inherently prevents fetching of the correct next instruction to be processed without delay, and is often further exacerbated by the need to first calculate the target address.
One technique that can be used to eliminate or hide the negative performance impact of control transfer instructions is to utilize a branch target cache (BTC). This structure functions as a specialized form of instruction cache which holds only the first several target instructions of a control transfer. By associating each BTC entry with the address or program counter of the control transfer instruction, the BTC can be accessed based on the fetch address of a control transfer instruction. By doing this in parallel with the decoding of what turns out to be a control transfer, the first target instruction can be "fetched" out of the BTC immediately after fetching of the control transfer instruction and substituted for the sequentially fetched instruction which is no longer desired.
The contents of the BTC entry are "fetched" or transferred into an instruction queue from which the CPU instruction decoder's instruction register is loaded. Depending on the typical instruction fetch latencies within an implementation, this queue may have the capacity to hold several words of fetched instructions. The capacity of a BTC entry may similarly be several words in size so as to hide the latency involved in restarting instruction fetching after a control transfer.
In any case, all of the instruction words in the BTC must be transferred to the instruction queue and in a sufficiently short period of time so as to not hold up the decoding of target instructions.
When a control transfer instruction is encountered without an associated BTC entry, instructions are, of course, fetched into the instruction queue directly from memory. In addition, a new BTC entry will be set up so that future encounters of the control transfer will find target instructions in the BTC. As instruction words are received from memory during this first encounter, they are also loaded into this new BTC entry.
While many CPU implementations employ a single instruction queue, higher performance designs will employ multiple queues in conjunction with parallel or interleaved fetching down multiple instruction streams. For example, the CPU will initially be processing one sequential instruction stream. When a conditional control transfer is encountered, a new stream is created starting at the target address. While the direction of the control transfer remains uncertain, fetching down both the sequential and target streams will be performed in conjunction with further pipeline processing down the stream predicted as more likely to be the correct branch direction. (Note that in the case of unconditional control transfers, the original queue can be immediately reused for the new fetch stream.)
Additional queues may also be present to support similar handling of further conditional control transfer instructions encountered on the predicted instruction stream while the first conditional control transfer remains unresolved. While a diminishing returns effect quickly sets in, usage of three instruction queues (and support for up to two unresolved conditional control transfers at a time) can be justified in very high performance implementations utilizing deep pipelining.
With CPU implementations such as this, though, substantial hardware costs can be incurred for the instruction queues themselves (each of which may be up to 32 bytes in size) for support circuitry for managing the queues and for routing instruction words between various elements. As conditional control transfers are encountered and as they are resolved as having been mispredicted, instruction processing must switch between the appropriate instruction queues. In parallel with this, interleaved fetching of instruction words in multiple queues and loading into associated new BTC entries must take place. As far as routing, the instruction register must be loadable from each of the queues; each queue loadable from the BTC and memory; and the BTC from memory in parallel with loading of a queue.

Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence


The present disclosure relates generally to a protocol to treat or prevent diseases or conditions associated with pathological forms of amyloid beta (Aβ), including Alzheimer's disease. Enabled herein is a reagent for use in the treatment and prophylaxis of Aβ-associated pathological conditions.

Field
The present disclosure relates generally to a protocol to treat or prevent diseases or conditions associated with pathological forms of amyloid beta (Aβ), including Alzheimer's disease. Enabled herein is a reagent for use in the treatment and prophylaxis and diagnosis of Aβ-associated pathological conditions.
Prior Art
Bibliographic details of the publications referred to by author in this specification are collected alphabetically at the end of the description.
Reference to any prior art in this specification is not, and should not be taken as, an acknowledgment or any form of suggestion that this prior art forms part of the common general knowledge in any country.
Alzheimer's disease is a degenerative brain disorder characterized histologically by neuritic plaques found primarily in association with the cortex, limbic system and basal ganglia. These neuritic plaques comprise a cleavage product of amyloid precursor protein (APP), a type I transmembrane glycoprotein.
The cleavage product of APP is β-amyloid peptide or Aβ. Incorrect processing of APP can result in pathological forms of Aβ (Tanzi et al. (1996) Neurobiol Dis 3:159-168; Hardy (1996) Ann Med 28:255-258; Schenk et al. (1999) Nature 400:173-177). These pathological forms include Aβ1-42 and Aβ1-43 which have been detected as predominant species in the neurite plaques.
Bard et al. (2000) Nature Medicine 6:916-919 showed that peripheral administration of antibodies directed against Aβ can reduce plaque burden. Bard et al. (2003) Proc. Natl. Acad. Sci. USA 100:2023-2028 subsequently showed that Fc-mediated phagocytosis by microglial cells or macrophages is associated with plaque clearance. Hence, antibody therapy has the potential to treat Alzheimer's disease.
This is supported by non-Fc-mediated mechanisms being found to be associated with Aβ clearance in immunotherapy (Bacskai et al. (2002) J. Neurosci. 22:7873-7878; Das et al. (2003) J. Neurosci. 23:8532-9538).
One attempt at immunotherapy was the humanized antibody, Bapineuzumab or Bapi, developed by Pfizer and Johnson & Johnson. Bapi targets neurotoxic Aβ (Salloway et al. (2009) Neurology 73:2061-2070) at the extreme N-terminus in a helical conformation (Miles et al. (2013) Sci Rep 3:1-8) [doi:10.1038/srep01302]. Such Aβ forms with the N-terminal truncations comprise approximately 60% of Aβ deposits in the Alzheimer's diseased brains. Bapi was, however, shown to be toxic at higher doses.
Another antibody is Solanezumab (Eli Lilly). This antibody targets monomeric Aβ in the mid-region of the peptide and was partially efficacious in mild cases of Alzheimer's disease (Hardy (2014) N Engl J Med 370(4):377-378).
However, it appears that Solanezumab may be ineffective at reversing the symptoms in the later stages of Alzheimer's disease (Panza et al. (2014) Expert Opin Biol Ther:1-12 PMID 24981190).
Crenezumab (Genentech Inc.) also targets the mid-region of AB. It appears to stimulate microglia to a level sufficient to clear Aβ but without inducing an inflammatory response (Adolfsson et al. (2012) J. Neuroscience 32(28):9677-9689).
Ponezumab (Pfizer) targets the C-terminal end of Aβ1-40 but is unable to bind to elongated forms such as Aβ1-42 and Aβ1-43. Ponezumab was not efficacious in reducing biomarkers of Alzheimer's disease or cognitive decline (Liu et al. (2014) Mol Neurobiol:PMID 24733588). Another monoclonal antibody which has the same binding specificity as Ponezumab is referred to as Mab 2286 (Rosenthal et al. USSN 2011/038861, 2004/0146512 and 2007/0160616). Mab 2286 also does not bind to Aβ1-42 and Aβ1-43.
There is a need to further develop an immunotherapeutic approach to the treatment of disease conditions associated with toxic Aβ forms and their diagnosis.

Antibody therapy for amyloid beta disease

St. Vincent's Institute of Medical Research


A stud for ultrasonic insertion into a strip of material generally comprises a shank having a head portion and an entering portion on opposite ends thereof. The head portion is ultrasonically insertable into the strip, and the entering portion is insertable into an aperture in a workpiece. The head portion comprises a positive stop means for locating a level of insertion of the head portion into the strip. Means for providing pull out resistance is disposed on the head portion above the positive stop means, and means for providing torsional resistance is disposed on the head portion between the positive stop means and the means for providing pull out resistance. A body portion is located on the head portion above the means for providing pull out resistance. A unique method is also provided for ultrasonically inserting the stud into the strip.

The present invention relates generally to a uniquely constructed stud which is ultrasonically insertable into a strip or segment of plastic material and a unique and novel method for ultrasonically inserting articles into such a strip or segment. The invention more specifically relates to a stud having a unique configured head which can be ultrasonically inserted into a strip of material to attain a pre-formed configuration comprised of a plurality of studs, and a novel method for ultrasonically inserting those studs into the strip or segment.
The inserting and embedding of a stud in a strip of plastic material is well known. For instance, the patent to Murdock et al., U.S. Pat. No. 2,860,082, discloses one way for embedding a plurality of studs in a protective body or strip. This method requires a preformed strip in which to insert the studs, and also requires the utilization of a substrate and glue-like combination in order to seal and fix the studs within the strip.
Utilization of this method may not be attractive to some because it does not allow for easy alteration of the stud configuration in the strip. To change the stud configuration, an entirely new strip must be machined, adding the significant costs of retooling. Also, the use of the substrate and glue-like combination can be messy as well as costly. Additionally, because of the multiple steps in the method, and the multiple parts in the construction, the Murdock method can be time consuming and labor intensive, thereby adding to the cost of utilization.
Alternative methods for inserting and encapsulating studs in a strip of material are available. Some of those methods produce constructions similar to that disclosed and illustrated in the patent to Egner, U.S. Pat. No. 294,676, and the patent to Ryder, U.S. Pat. No. 4,753,560. Many of these methods employ the techniques of injection or insert molding of the plastic material about the studs. These methods are quite expensive due to the high priced machinery required, and also provided some of the same, above-detailed drawbacks. For instance, to change the configuration of the studs on the strip, a new mold must be machined, resulting in high retooling costs.
The improved method of the present invention for inserting studs into a strip employs the techiques of ultrasonic welding. Ultrasonic welding is a process whereby the material composing the strip is excited by ultrasonic energy to its melting point. The melted or deformed material then flows around and engages a stud to be inserted under the influence of natural or applied forces. As the ultrasonic energy is removed, the temperature of the material recedes from its melting point, thereby returning to its solid phase, and firmly retaining the stud within the strip.
However, the utilization of ultrasonic welding by the methods of the prior art has some drawbacks, making it unattractive for some applications. Specifically, the prior art methods utilizing ultrasonic welding require a hole or other aperture of sufficient size to accept and stud to be pre-formed in the strip or segment of plastic material. Some methods require the addition of an insert into the pre-formed hole and ultrasonically welding to the aperture walls. The stud would then be inserted into the pre-formed hole. The step of pre-forming the hole makes these methods time consuming and labor intensive, leading to greater costs. Additionally, the requirement of the insert adds to the cost of utilizing these methods.
The stud and the method of ultrasonic insertion of articles into a trip or segment as provided by the present invention eliminates many of the drawbacks present in the prior art.

Ultrasonic insert stud and method of assembly


A high bay compact fluorescent light fixture having a reflector/refractor mounted to a socket mounting plate assembly having a top portion, a bottom portion, and at least one sidewall. Removably mounted to the top portion of the socket mounting plate assembly is a ballast housing having a plurality of lamp powering ballasts located therein. A plurality of sockets are mounted to the bottom portion of the socket mounting plate assembly. The high bay compact fluorescent light fixture design eliminates the need for a collar to connect the reflector/refractor to the fixture and further makes the design more compact.

1. Technical Field of the Invention
The present invention relates to a high bay fluorescent light fixture. More particularly, the invention provides a high bay light fixture having a compact design in which the reflector/refractor is supported by a socket mounting plate assembly.
2. Description of the Related Art
Various light fixture designs used in high bay applications use a collar to attach a reflector/refractor to a fixture assembly. However, the use of a collar requires more vertical space between the light fixture and the reflector as well as causing higher manufacturing and assembly costs. This cost, in turn must be passed on to the consumer of the light fixture.
In view of the deficiencies in the known high bay light fixtures it is apparent that a light fixture is needed eliminating the use of a collar and having a compact design, good illumination characteristics, as well as easy assembly.
It is an object of the present invention to have a high bay fluorescent light fixture with a compact mounting plate design.
It is a further object of this invention to eliminate the need for having a collar to support a reflector/refractor.
It is still an even further object of this invention to support the reflector/refractor from the socket mounting plate assembly.
More particularly the invention comprises a high bay compact fluorescent light fixture, having a reflector/refractor with a first end and a second larger end, a socket mounting plate assembly having a top portion, a bottom portion, and at least one sidewall, each of the at least one sidewall connecting the top portion and the bottom portion, the top portion having a ledge around a peripheral edge and an upper bracket attaching the reflector/refractor to the socket mounting plate assembly, a plurality of substantially equidistantly spaced sockets depending from the socket mounting plate assembly, and a ballast housing removably attached to the top portion of the socket mounting plate assembly having a plurality of lamp powering ballasts therein in electrical communication with the plurality of sockets.
The high bay compact fluorescent light fixture of the present invention has a socket mounting plate assembly with vertical sidewalls and at least one upper bracket extending from the at least one sidewall through the top portion. The upper bracket and the ledge retain the reflector/refractor to the socket mounting plate assembly. Alternatively, the socket mounting plate assembly may have angled or bevelled sidewalls. The at least one sidewall is comprised of a plurality of brackets.
The high bay compact fluorescent light fixture has a plurality of sockets mounted in a plane which may be normal to the socket mounting plate assembly. The high bay compact fluorescent light fixture has a reflector/refractor which may be acrylic and translucent.
Alternatively, the high bay fluorescent light fixture may or may not have a socket mounting plate assembly of unitary construction. If a non-unitary construction is used the high bay compact fluorescent light fixture may further comprise a retaining clip for holding the bottom portion against a peripheral edge of the angled or beveled sidewall.
All of the above outlined objectives are to be understood as exemplary only and many more objectives of the invention may be gleaned from the disclosure herein. Therefore, no limiting interpretation of the objectives noted are to be understood without further reading of the entire specification, claims and drawings included herewith.

High bay compact fluorescent light fixture


A lockbox includes a body and a lid connected to body and pivotable between a closed position and an open position. The body defines an enclosure and includes a body aperture and the lid includes a first lid aperture positioned adjacent to the body aperture when the lid is in the closed position, such that insertion of a padlock shackle through the body aperture and the lid aperture prevents pivoting movement of the lid from the closed position to the open position. The lockbox includes a slot intersecting one of the body aperture and the lid aperture for insertion of an item into the enclosure when the lid is in the closed position. A padlock shackle inserted through the body aperture and the lid aperture prevents passage of an item through the slot.

Many safety lockout devices are provided for restricting access to equipment and control instruments, including, for example, electrical components, such as switches, dials and push buttons, and fluid system components, such as valves and pressure regulators. Industrial and commercial equipment are often provided with or assembled with a key-operated lockout mechanism (e.g., a locking bracket and padlock or similar structure) to facilitate the restriction of access to or operation of the equipment.
In some applications, the authorization of multiple technicians or other authorized personnel is required to allow access to, or operation of, a locked out system or piece of equipment, for example, to comply with established safety procedures. In such an application, the use of multiple keys controlled by multiple users may be required to unlock the one or more lockout mechanisms to place the equipment in an operable condition.


A laser strainmeter has a plurality of sensor resonators, each comprising a multiple reflection interferometer having a pair of concave mirrors (8) which are secured to the inner wall of a container (1) to face each other in the diametrical direction of the container so that the optical axes of the sensor resonators extend in different directions. The laser strainmeter further has a reference resonator comprising a multiple reflection interferometer having a pair of concave mirrors (12) which are disposed in the vicinity of the sensor resonators, and which are held at a fixed distance. Laser light having the same resonance frequencies as those of the associated resonators are transmitted from laser oscillators to the resonators through optical fibers (3). A change in distance between the pair of concave mirrors of each of the sensor resonators is obtained from a difference in resonance frequency between each sensor resonator and the reference resonator, thereby obtaining a strain change of a medium in which the container is buried.

The present invention relates to a laser strainmeter for observing small strain changes of a medium, e.g., the earth's crust, by measuring changes of diameters of a cylindrical or spherical container buried in the medium.
Precise observation of small strain changes of the earth's crust is important to studies of solid earth science or for practical purposes such as earthquake prediction or prediction of a volcanic eruption. In order to precisely measure small strain changes of the earth's crust, it is important to avoid the influence of change of temperature on the surface of the earth, or the effect of rain or an atmospheric pressure change. Accordingly, the conventional practice is to dig a borehole in the ground so deep as to reach bedrock and to install a strainmeter to the bottom of the borehole with cement or mortar.
Strainmeters of the type described above include Sakata-type borehole three-component strainmeter (Shoji SAKATA AND Haruo SATO, BOREHOLE-TYPE TILTMETER AND THREE-COMPONENT STRAINMETER FOR EARTHQUAKE PREDICTION, J. Phys. Earth, 34, Suppl., S129-S140, 1986). According to the Sakata-type borehole three-component strainmeter, deformation of a cylindrical container buried in a borehole is converted into volume changes of liquid contained in chambers of the container, and the volume changes are electrically detected. The Sakata-type borehole three-component strainmeter provides high resolution, and since it has minimal portions which involve solid friction, the apparatus is not affected by the shock of an earthquake. Accordingly, the strainmeter has the advantage of high stability. There is another borehole-type three-component strainmeter which is based on changes of bore diameters. For example, changes in diameter in three directions are enlarged by a combination of mechanical levers, and detected in the form of electric signals.
For future more effective earthquake prediction and more detailed observational studies in earth science, there is a need for a strainmeter which provides higher resolution than the conventional three-component strainmeter as described above. On the other hand, a strainmeter which is capable of operating under high-temperature conditions is demanded for prediction of volcanic eruptions. Further, there is an increasing demand for measurement in a borehole as deep as 10 km or more, which is attained by ultra-deep boring, and a strainmeter capable of enduring high temperature at that depth is demanded. Further, when it is considered to use a strainmeter as a seismometer for detecting a seismic wave, the strainmeter must function accurately in a high-frequency region.
However, the above-described conventional borehole-type three-component strainmeter suffers from the problem that, since it uses a liquid, phase change takes place at high temperature, causing the strainmeter to fail to function as desired. Further, the strainmeter cannot detect short period phenomena such as seismic waves because of the viscous resistance in the flow path. In addition, the conventional borehole-type three-component strainmeter requires a multicore cable. In view of installation in deeper boreholes or on the bottom of the sea, it is preferable to minimize the number of conductors constituting the cable for easy handling. In this case, the number of conductors of the cable is reduced by introducing a carrier device. However, it is desirable not to use a carrier device because carrier devices are generally incapable of withstanding high temperature. The existing borehole-type three-component strainmeter further involves the problem that since the overall length is long for reasons of structure, if it is combined with other observation devices to form an integrated observation system, the overall length becomes undesirably longer. The above-described mechanical borehole-type three-component strainmeter involves solid friction and backlash. Therefore, the degree of accuracy is inevitably low, and it cannot withstand a shock in particular.

Multicomponent laser strainmeter using Fabry-Perot interferometers

Science and Technology Agency National Research Institute for Earth Science & Disaster Prevention


A method of disinfection of foodstuff involving the use of hydrogen peroxide in combination with anti-microbial agents selected from the group consisting of benzoic acid, and phosphoric acid, at low concentration, to substantially reduce the microbial count in food-related application.

Disinfection is a worldwide problem within the foodstuff industry and numerous efforts have been made with additives to attempt to reduce the microbial load on fresh muscle foods. Some of the techniques used have been by chilling or dipping the products with antimicrobial compounds. However, the use of antimicrobial compounds has been limited due to its efficacy as well as cost.
U.S. Pat. No. 3,792,177 to Nakatani et al. relates to a method for improving the quality of foodstuff by the addition to the foodstuff of a mixture of a water soluble metal phosphate-hydrogen peroxide adduct and a water soluble acid metal phosphate, the ratio of said adduct to said metal phosphate being about 1 part by weight to from about 0.5 to about 9 parts by weight.
U.S. Pat. No. 4,915,955 to J. Gomori relates to a process for preparing a storage stable concentrate comprising admixing (i) an inorganic acid such as 75% phosphoric acid, 65% aqueous nitric acid or 69% aqueous sulphuric acid in water with (ii) a silver composition selected from silver salts and silver salt complexes and (iii) an organic acid stabilizer selected from e.g. tartaric acid and/or citric acid.
EP B1 87 049 relates to a disinfectant for hospitals, schools, breweries, laundries, etc. comprising a composition comprising 1-15 % H.sub.2 O.sub.2, 1-30% phosphorous compound, 0.1-5% metal chelating agent, 0-20% surfactant and the rest water.
CA 1 146 851 relates to a composition for disinfection of dental and medical equipment by the use of a composition comprising H.sub.2 O.sub.2, Tetronic 908 and H.sub.3 PO.sub.4, benzotriazole, Acitrol and deionized water.
U.S. Pat. No. 5,264,229 relates to a commercial process for extending the shelf life of poultry and seafood by introducing food grade H.sub.2 O.sub.2 and foodgrade surface active agents into the chiller water to wash off bacteria on the surface of the food product. The agents are alkylaryl sulfonates, sulfates, sulfonates of oils and fatty acid, sulfate of alcohols and sulfosuccinates.
Chen et al. reported 1973 that immersion of fresh poultry meat into ice water containing polyphosphates extends the shelf life of the meat and that the immersion of fresh chicken parts in a 3% polyphosphate solution controll gram-positive microccoci and Staphyloccoci, but that certain gram-negative organisms tolerated the addition of 1-6% phosphate. Foster and Mead reported 1976 that Salmonella growth in minced chicken breast meat was inhibited by using 0.35% polyphosphate solution followed by storage at -2.degree. and -20.degree. C.
The term "shelf-life" usually refers to the period of quality deterioration by decreasing nutritional value, color changes, development of off-flavors, and/or textural changes occurring during storage. Microbial spoilage that results in physical and chemical changes is one of the principal factors responsible for the relatively short shelf-life of muscle foods.
Said prior art, however, say nothing about the findings which constitute the basis for the present invention, namely that a combination of hydrogen peroxide and an anti-microbial agent selected from benzoic acid and phosphoric acid, and combinations thereof, at low concentration effectively reduces the microbial count on foodstuff, especially fresh muscle foods.


Shown is an apparatus and method for cracking stone fruit nuts. The apparatus includes a frame (2) supporting a set of spaced apart jaw including a first jaw (4) and a second jaw (5) defining between them a gap (6), which is tapered down from the inlet (7) to the outlet (8). The first jaw (4) is adjustably secured to the frame (2) for adjustment of the size of the gap (6). The second jaw (5) is movably supported by the frame (2) and secured to drive means configured to rotatably move the second jaw (5) relative to the first jaw (4) with a tangential motion resulting in the continuously change of the size of the gap (6). To crack the shell, the stone fruit nut is located between the jaws and repeatedly pressed and rolled between the jaws from the inlet (7) to the outlet (8).

The pecan, which is a large deciduous tree (Carya illinoinensis) is a species of hickory native to Mexico and the south-central and southeastern regions of the United States. A pecan, like the fruit of all other members of the hickory genus, is not truly a nut, but is technically a drupe, a fruit with a single stone or pit, surrounded by a husk. The husks are produced from the exocarp tissue of the flower, while the part known as the nut develops from the endocarp and contains the seed. The husk itself is aeneous, oval to oblong, 2.6-6 cm long and 1.5-3 cm broad. The outer husk is 3-4 mm thick, starts out green and turns brown at maturity, at which time it splits off in four sections to release the thin-shelled nut.
Today, the U.S. produces between 75% and 85% of the world's pecans, with an annual crop of 180-240 thousand metric tons, in-shell basis, from more than 10 million trees. Historically, the leading pecan-producing state in the U.S. has been Georgia, followed by Texas, New Mexico, Arizona, Louisiana, and Oklahoma. Pecans are also grown in Alabama, Florida, Arkansas, Kansas, Missouri, South Carolina, and Hawaii. Outside the United States, pecans are grown in Australia, Brazil, China, Israel, Mexico, Peru, and South Africa.
The seeds (nuts) of the pecan are edible, with a rich, buttery flavor. They can be eaten fresh, dried, roasted or used in cooking, particularly in sweet desserts. One of the most common desserts with the pecan as a central ingredient is the pecan pie, a traditional Southern U.S. dish. Pecans are also a major ingredient in praline candy.
The pecan nut meat is dicotyledonous, having two halves. An unbroken nut meat is classified by the USDA (United States Department of Agriculture), as a separated half, which has not been significantly damaged. (To qualify as a half kernel, the kernel may not have more than one eighth of the kernel missing, inclusive of the joiner piece between the two halves.)
Cracking and shelling pecans and removing the edible nut meat with minimal breakage is the ultimate aim of all pecan nut processing operations. Modern mechanical shelling operations typically recover between 50%-75% unbroken nut meats. Many shelling operations in Mexico have resorted to shelling by hand in order to achieve a higher percentage of unbroken nut meats. The difference in price received between unbroken and broken nut meats is substantial and the additional indirect losses incurred from breakage include, amongst others, loss of small pieces and nut meat dust to waste, additional labour cost in sorting pieces, a higher degradation and potential for development of rancidity factor in pieces and a higher percentage contamination of pieces with shell.

Apparatus and method for cracking stone fruit nuts