The invention concerns a climatic cabinet, in particular, a climatic cooling cabinet, whose interior is loaded or unloaded with specimen slides, with the aid of a transporting device. The loading and unloading take place through a loading opening which can be closed with a door, which opening is adapted, in its size, to the dimensions of the specimen slides and is located in a sidewall of the climatic cabinet. The climatic cabinet also has a gas supply device, whose at least one gas exhaust opening is situated in such a way that the cross-section of the loading opening is covered by a gas curtain, in the area of the gas exhaust openings when gas is supplied.

The interior of the climatic cabinet is, as a rule, accessible through a door, which is large enough, so as to set up a holding rack in the interior and to take it out of the interior. Furthermore, the interior can be cleaned and maintained through the door.
The holding rack is preferably loaded with specimen slides automatically with the aid of a suitable transporting device. Since the opening of the large main door would lead to sensitive disturbances of the climatic conditions in the interior, it has been proposed that a separate air lock be used for the loading and unloading of the specimen slides, which has the smallest possible passage cross-section and is only just large enough, so as to bring the specimen slides into the interior with the aid of the transporting device and to bring them out from the interior. Since only a very small opening in the outer wall of the climatic cabinet must be unblocked for the transporting of the specimen slides back and forth, the effects on the climatic conditions in the interior are clearly less and a continuous operation of the climatic cabinet without serious disturbances of the climate in the interior is possible.
Such a device is described, for example, in WO 98/05753 A1. The climatic cabinet described there has, in addition to a main door in the opposite, back wall, another smaller opening, which is used to transport specimen slides in and out of the interior. The smaller back opening, which is designated as a window opening, can be closed with a door. One or more carousels are used as a holding rack for the specimen slides in the interior of the climatic cabinet.
By using the reduced window opening in transporting specimen slides into the climatic chamber or out of it, the effects of the outside atmosphere on the interior can be clearly reduced, but not completely eliminated. Thus, when the small window is opened, there is also a certain exchange of the atmosphere and an influence on the temperature. Usually, that is the limit to the disturbance. In some special cases, however, there may be an impairment of the climate in the interior of the climatic cabinet. If, for example, the climatic cabinet is used as a climatic cooling cabinet, a small quantity of moisture is dragged in from the surrounding atmosphere into the interior of the climatic chamber every time a specimen slide is transported in. The moisture accumulates gradually in the interior and condenses or freezes because of the reduced temperature in the interior. If the moisture on specimen slides condenses or freezes, then this can lead to damage to the microorganisms or cell cultures and to a contamination of the specimens.
U.S. Pat. No. 6,467,285 B2 describes a climatic cooling cabinet, which is very similar to the apparatus of WO 98/05753 A1. The climatic cooling cabinet has a carousel to hold specimen slides in its interior, which are automatically transported into the interior with a transporting device and again conveyed out of it. Also, the transport does not take place here through the main door of the climatic cabinet, but rather through a smaller transporting air lock. There is a difference from WO 98/05753 A1 here, however, in that the air lock is constructed as a chamber, which can be closed on both sides, both with respect to the interior of the climatic cabinet and to its outside and which can be climatized itself alone. In order to move a specimen slide into the interior of the apparatus, the outer door of the air lock chamber is first opened, and the specimen slide is pushed into the air lock chamber while the inner door of the air lock chamber is closed. Then, the outer door of the air lock chamber is also closed, and a dry gas is introduced into the air lock chamber from a single inlet, which empties into an upper, inner section of the chamber, so as to expel the moisture from the air lock chamber and cool it. Subsequently, the inner door of the air lock chamber is opened, and the specimen slide is transported from the air lock chamber to the carousel and laid there. To transport the specimen slide from the climatic cooling cabinet, the steps are carried out in the reverse sequence. By means of the measures described, the influence on the climate in the interior of the climatic cooling cabinet by the outside atmosphere is reduced even more than in the case of WO 98/05753 A1. The apparatus, however, is constructed in a rather complicated manner and the transporting of each specimen slide takes a relatively long time, since the specimen slide must spend a longer period of time in the air lock chamber, until the dry gas has completely displaced the atmosphere in the air lock chamber.

Climatic cabinet and, in particular, a climatic cooling cabinet


A semiconductor device includes a semiconductor substrate having a main surface, and a multi-layered wiring layer formed on the main surface of the semiconductor substrate, the multi-layered wiring layer having a plurality of wiring layers insulatively laminated, wherein the melting points of the plurality of wiring layers are set gradually lower in a direction towards the higher-level side.

This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a multi-layered wiring structure and a method for manufacturing the same.
Recently, various types of LSIs are used in the main portions of computers and communication devices and the performances of the computers and communication devices are closely related to the performance of the LSI itself. The performance of the LSI itself can be improved by enhancing the integration density thereof, that is, reducing the size of elements.
Since the aspect ratio of the contact hole increases as the size of the element is reduced, it is difficult to form a continuous conductive layer in a plug because of breakage of a wiring metal in the plug, that is, breakage of the wiring metal at a stepped portion when the wiring metal is formed by the conventional sputtering method. Therefore, a method for embedding tungsten in the plug and forming a wiring metal (an aluminum alloy in most cases) thereon is used. However, with this method, since a metal embedded in the plug and a wiring metal are different from each other, there occur problems that the reliability is lowered, different tools are required for embedding the metal into the plug and forming the wiring metal and the number of steps is increased.
In order to solve the above problems, the reflow technique for simultaneously forming the plug and the wiring metal is studied. The reflow technique is a technique for causing a metal to flow by use of the high-temperature sputtering method or the like, but most of the reflow techniques now studied are to form stacked several wiring layers at the same reflow temperature.
When the metal wirings of several layers are formed at the same reflow temperature by use of the reflow technique, the metal wiring of the underlying layer is subjected to the same heat treatment several times and a void occurs therein to lower the reliability of the wiring.

Semiconductor device and method for manufacturing the same


Signal edge sharpener circuitry is operably connected to the word lines in a memory array to pull up a rising edge of a signal on the word line and/or to pull down a falling edge of the signal on the word line. Pulling the signal up and/or down reduces the amount of time the word line is asserted and reduces the amount of time between precharge operations.

Different types of memory circuits are used in electronic devices for various purposes. Read only memory (ROM) and random access memory (RAM) are two such types of memory circuits. A ROM circuit permits data to be read from, but not written to, the ROM circuit and retains its stored data when power is switched off. As such, a ROM circuit is typically used to store programs that are executed when the electronic device is turned on.
A RAM circuit allows data to be written to, and read from, selected memory cells in the RAM circuit. One type of a RAM circuit is a static random access memory (SRAM) circuit. A typical SRAM circuit includes an array of addressable memory cells arranged in columns and rows. When a memory cell is to be read, the memory cell is selected by activating both a row word line and the column signal lines (bl and blb lines) connected to the memory cell. Typically, the column signal lines are precharged prior to the performance of a read or a write operation.
Improvements in fabrication techniques for memory devices allow the memory devices to be fabricated in smaller and smaller packages. With a smaller memory device, the resistance and the capacitance of the row word lines increase due to the material used in the row word lines and the geometry of the row word lines. The resistances of the row word lines increase because the geometry of the word lines is smaller. Additionally, the row word lines are closer to each other in a smaller package, which in turn increases the capacitance of the row word lines. The increased resistances and capacitances cause the rising and/or falling edges of a signal on a row word line to require more time to reach a particular signal level (e.g., a high signal level or a low signal level). This in turn causes the amount of time between precharge operations to increase because a precharge operation cannot begin until the signal on the word line has reached the particular signal level.

Memory device with signal edge sharpener circuitry


A process for the offset printing of a receiving medium with a functional pattern comprising in any order the steps of: applying a printing ink to a printing plate and wetting the printing plate with an aqueous fountain medium containing a solution or a dispersion containing at least one moiety having at least colouring, pH-indicating, whitening, fluorescent, phosphorescent, X-ray phosphor or conductive properties.

Lithographic printing presses use a so-called printing master such as a printing plate which is mounted on a cylinder of the printing press. The master carries a lithographic image on its surface and a print is obtained by applying ink to the image and then transferring the ink from the master onto a receiver material, which is typically paper. In conventional lithographic (offset) printing, both ink and an aqueous fountain solution (also called dampening liquid) are supplied to the lithographic image which consists of oleophilic (or hydrophobic, i.e. ink-accepting, water-repelling) areas as well as hydrophilic (or oleophobic, i.e. water-accepting, ink-repelling) areas. In so-called driographic printing, the lithographic image consists of ink-accepting and ink-abhesive (ink-repelling) areas and during driographic printing, only ink is supplied to the master.
Plate materials include those based on UV-exposure through a mask or image-wise exposure with a laser followed by processing with solubilization in the case of positive plates or insolubilization in the case of negative plates, and those for processing using laser-ablation techniques, such as used in typical computer-to-plate plates or plate materials which are not ablative and do not need wet processing. Known examples of such non-ablative processless plate materials contain a so-called 'switchable' image-recording layer, i.e. a layer of which the affinity towards ink or an ink-abhesive fluid can be converted upon image-wise exposure from one state to the opposite state, e.g. from hydrophilic to oleophilic or from ink-accepting to ink-abhesive. Such materials are based on                switchable polymers (e.g. EP 924 102) which can be image-wise converted from a hydrophobic state to a hydrophilic state (WO92/09934; EP 652 483) or vice-versa (U.S. Pat. No. 4,081,572; EP 200 488; EP 924 065);        thermally induced coalescence of thermoplastic polymer particles in a crosslinked binder (U.S. Pat. No. 3,476,937; EP-A 882 583; Research Disclosure no. 33303); and        thermally induced rupture of microcapsules and the subsequent reaction of the microencapsulated oleophilic compounds with functional groups on cross-linked hydrophilic binders (U.S. Pat. No. 5,569,573; EP 646 476; EP 949 088).
In offset printing a fountain solution and then the ink are applied to the printing plate on a drum and they are transferred to an intermediate (rubber) roll, known as the offset blanket, from which they are printed onto paper sheets transported between the impression cylinder and the intermediate (rubber) roll.
The fountain solution is transferred via a series of rolls to the printing plate or a fine emulsion of ink and the fountain solution are prepared on an ink roll which is then applied to the plate. The fountain solution conventionally acts as a weak sacrificial layer and prevents ink from depositing on the non-image area of the plate and has the function of rebuilding the non-printing (desensitized) areas of the printing plate during a press run. This is usually realized with acid, usually phosphoric acid, and gum arabic, the acid and gum combining to form a molecule that helps the adsorption of the gum to the metal of the plate and thereby making a hydrophilic surface. Fountain solutions have historically contained isopropyl alcohol to reduce the surface tension and thereby to provide for more uniform dampening of the printing plate, but, by eliminating (or greatly reducing) the isopropyl alcohol as a fountain solution additive, printers are able to reduce VOC (volatile organic compound) emissions significantly. In such fountain solutions isopropyl alcohol is replaced with lower volatility glycols, glycol ethers, or surfactant formulations. Conventional fountain solutions may also contain anti-corrosion agents, pH-regulators and surfactants.
WO 01/88958 discloses in claim 1 a method of forming a pattern of a functional material on a substrate comprising: applying a first pattern of a first material to said substrate; and applying a second functional material to said substrate and said first material, wherein said first material, said second functional material, and said substrate interact to spontaneously form a second pattern of said second functional material on said substrate, to thereby form a pattern of a functional material on a substrate.
WO 01/88958 further discloses in claim 27 a method of forming a pattern of a functional material on a substrate comprising: non-contact printing a first pattern of a first material on said substrate; and applying a second functional material to said substrate and said first material, wherein said first material, said second material, and said substrate interact to spontaneously form a second pattern of said second functional material on said substrate, to thereby form a pattern of a functional material on a substrate.
WO 01/88958 also discloses in claim 47 a method of forming a pattern of a functional material on a substrate comprising: non-contact printing a first pattern of a first material on said substrate; and applying a second functional material to said substrate and said first material, wherein said first and second functional materials are selected to have a sufficient difference in at least one property of hydrophobicity and hydrophilicity relative to one another such that said first material, said second functional material, and said substrate interact to spontaneously form a second pattern of said second functional material on said substrate, to thereby form on said substrate a second pattern of said second functional material, wherein said second pattern is the inverse of said first pattern, to thereby form a pattern of a functional material on a substrate.
WO 01/88958 also discloses in claim 57 a method of forming an electrical circuit element, comprising: applying a first pattern of a first material on a substrate; and applying a second material to said substrate and said first material, wherein said first material, said second material, and said substrate interact to spontaneously form a second pattern of said second material on said substrate, thereby forming an electrical circuit element.
WO 01/88958 also discloses in claim 110 an electrical circuit element comprising: a substrate; a first pattern of an insulating material applied to said substrate; and a second pattern of an electrically conducting material applied to said substrate and said first material, wherein said insulating material, said electrically conducting material, and said substrate interact to spontaneously form a second pattern of said electrically conducting material on said substrate when said electrically conducting material is applied to said substrate having said first pattern of said insulating material applied thereon.
WO 01/88958 also discloses in claim 123 an electronic device comprising: a) a first element comprising i) a first substrate; ii) a first pattern of an insulating material applied to said substrate and iii) a second pattern of an electrically conducting material applied to said substrate and said first material, wherein said insulating material, electrically conducting material, and said substrate interact to spontaneously form a second pattern of said electrically conducting material on said substrate when said electrically conducting material is applied to said substrate having said first pattern of said insulating material applied thereon; b) a second circuit element comprising i) a second substrate; ii) a third pattern of an insulating material applied to said second substrate and iii) a fourth pattern of an electrically conducting material applied to said second substrate and said third material, wherein said insulating, electrically conducting material, and said second substrate interact to spontaneously form a fourth pattern of said electrically conducting material on said substrate when said electrically conducting material is applied to said substrate having said third pattern of said insulating material applied thereon; and c) an electrically connection between said first and second circuit elements.
WO 01/88958 also discloses in claim 127 a Radio Frequency (RF) tag comprising a pattern of a non-conductive first material on a substrate and a coating of an electrically conductive second material disposed over said substrate and said first material, wherein said first material, said second material, and said substrate interact to spontaneously form a second pattern of said second material on said substrate, to thereby form an Inductor-Capacitor (LC) resonator on said substrate.
WO 01/88958 also discloses in claim 141 a mechanical device comprising: a) a first component comprising: i) a first substrate; ii) a first pattern of first material to said first substrate and iii) a second pattern of material applied to said first substrate and said first material, wherein said second pattern of said second material is spontaneously formed by the interaction of said first material, said second material and said first substrate; and b) a second component comprising i) a second substrate; ii) a third pattern of a third material applied to said second substrate and iii) a fourth pattern of a fourth material applied to said second substrate and said third material, wherein said fourth pattern of said fourth material is spontaneously formed by the interaction of said third material, said fourth material and said substrate; and wherein said first and second components are oriented in a such a way that the second and fourth patterns oppose each other, and are selected from the group consisting of identical patterns, inverse patterns, and any mechanically useful combinations.
In 2001, Hohnholz et al. in Synthetic Metals, volume 121, pages 1327-1328, reported a novel method for the preparation of patterns from conducting and non-conducting polymers on plastic/paper substrates. This method, "Line Patterning" (LP), does not involve printing of the polymers and incorporates mostly standard office equipment, e.g. an office type laser printer. It is rapid and inexpensive. The production of electronic components, e.g. a liquid crystal and a push-button assembly were reported.
It has been found that aqueous solutions and dispersions of intrinsically conductive polymers upon coating upon a surface with hydrophobic and hydrophilic areas eventually exclusively permeate to the hydrophilic areas, but at a speed which makes such processes industrially impracticable. There is a need for a mass-production process for producing conductive patterns of intrinsically conductive polymer. There is also a need for a mass-production process for other functional patterns such as fluorescent, phosphorescent, X-ray phosphor and pH-indicator patterns.

Process for the offset printing of patterns via the fountain medium


A data inspection method includes the steps of (a) writing original test data in a memory region, (b) reading the test data from the memory region, and (c) comparing the read test data with the original test data, so as to make a data inspection. The test data is formed by a plurality of cell data. Each of the cell data includes a delimiter indicating a boundary between two adjacent cell data, a cell number indicating an order within the test data, a cell data length indicating a data length of the cell data, and pattern data. Each of the cell data in the test data has a cell data length which is variable.

1. Field of the Invention
The present invention generally relates to data inspection methods and apparatuses, and more particularly to a data inspection method and a data inspection apparatus for inspecting data which are written and read by an information processing apparatus.
2. Description of the Related Art
Conventionally, a storage medium such as a semiconductor memory and a storage device, and a peripheral device of an information processing apparatus are tested by writing test data to a write address of the storage medium. The test data written in the storage medium is read from the same address as the write address, and a data inspection is made by comparing the read test data and the test data.
The conventional test data has a value which is represented by a predetermined number of bits, such as 16 bits. The value of the test data continuously increases or decreases. That is, the test data is made up of a continuous data which continuously increases or decreases.
According to the continuous data which is conventionally used as the test data, it is possible to detect a fault when the test data written at a certain address and the test data read from this certain address differ. However, there was a problem in that it takes an extremely long time in order to detect a range of the fault and to determine the type of fault. This is because a complex logic system is required to determine if the fault is caused by a data dropout, data overlap or duplication, data mixing, data transformation or the like. The determination of the data mixing involves detection of a location where the data is mixed, and the determination of the data transformation involves detection of a location where a data xe2x80x9c1xe2x80x9d is transformed into a data xe2x80x9c0xe2x80x9d, for example.
In addition, when the information processing apparatus makes a write access to the external storage device, such as a hard disk drive, the following operations are involved. In terms of hardware, the write access starts from reading data from the semiconductor memory. The data read from the semiconductor memory are transferred to a channel input/output controller via an internal bus and a cache within a CPU, and the data are transferred from the channel input/output controller to the external storage device via an external bus and an input/output controller. The data transferred to the external storage device are written into a storage medium in logical blocks. When the operations described above are carried out by use of an operating system (OS), further processes of the OS are required, such as paging, and conversion between logical blocks and physical blocks. Therefore, even if the fault is detected by use of the continuous data, there was a problem in that it is extremely difficult to specify the exact location where the fault is generated.
Accordingly, it is a general object of the present invention to provide a novel and useful data inspection method and data inspection apparatus, in which the problems described above are eliminated.
Another and more specific object of the present invention is to provide a data inspection method and a data inspection apparatus which can specify a location of a fault when the fault is detected, and determine the kind of fault by a simple logic system.
Still another object of the present invention is to provide a data inspection method comprising the steps of (a) writing original test data in a memory region, (b) reading the test data from the memory region, and (c) comparing the read test data with the original test data, so as to make a data inspection, where the test data is formed by a plurality of cell data, each of the cell data includes a delimiter indicating a boundary between two adjacent cell data, a cell number indicating an order within the test data, a cell data length indicating a data length of the cell data, and pattern data, and each of the cell data in the test data has a cell data length which is variable. According to the data inspection method of the present invention, it is possible to specify the location of a fault generated in the cell data based on the cell data length of the cell data, because the cell data length of each cell data is variable.
A further object of the present invention is to provide the above data inspection method which further comprises the steps of (d) recognizing a cell data dropout, a cell data overlap or a cell data switching based on a size relationship of a cell number of the cell data in the read test data and an anticipated cell number, and whether or not the read test data includes a cell data having the anticipated cell number, if the cell number of the cell data in the read test data differs from a cell number of the cell data in the original test data. According to the data inspection method of the present invention, it is possible to recognize the kind of fault.
Another object of the present invention is to provide a data inspection apparatus which makes a data inspection by writing original test data in a memory region, reading the test data from the memory region, and comparing the read test data with the original test data, comprising test data generating means for generating the test data from a plurality of cell data, where each of the cell data includes a delimiter indicating a boundary between two adjacent cell data, a cell number indicating an order within the test data, a cell data length indicating a data length of the cell data, and pattern data, and each of the cell data in the test data has a cell data length which is variable. According to the data inspection apparatus of the present invention, it is possible to specify the location of a fault generated in the cell data based on the cell data length of the cell data, because the cell data length of each cell data is variable.
Still another object of the present invention is to provide the above data inspection apparatus which further comprises recognizing means for recognizing a cell data dropout, a cell data overlap or a cell data switching based on a size relationship of a cell number of the cell data in the read test data and an anticipated cell number, and whether or not the read test data includes a cell data having the anticipated cell number, if the cell number of the cell data in the read test data differs from a cell number of the cell data in the original test data. According to the data inspection apparatus of the present invention, it is possible to recognize the kind of fault.


The present invention discloses a high-capacity broadband access method, comprising: a broadband subscriber initiating an access request to an access unit; the access unit sending the subscriber authentication information to a control unit via a route switching unit; the control unit authenticating the subscriber with an internal or external authentication, authorization and accounting server, returning the authentication result to the access unit via the route switching unit, and sending the configuration information to the accessed subscriber; the route switching unit and the access unit accomplishing configuration of the subscriber information, allocating corresponding resource to the subscriber, and establishing a data channel for network access of the subscriber. The present invention also discloses a high-capacity broadband access device and a system thereof.

A broadband access network system comprises subscriber access devices (DSLAMs or LAN SWs), a network aggregation device (ATM switch or Ethernet switch), a BAS (Broadband Access Server), and an authentication, authorization and accounting (AAA) server.
The network architecture of an existing broadband access network is shown in FIG. 1: the subscriber access devices support the subscriber lines aggregation function. The subscriber lines may be digital subscriber lines, Category 5 twisted-pairs, or optical fibers. Each subscriber access device can aggregate tens, hundreds, or thousands of subscriber lines and forward data messages from subscribers to one or a plurality of uplinks. The subscriber access devices can forward data messages from uplinks to the subscribers. The subscriber access devices typically work in L2 mode, i.e., it only processes link layer information in the data messages and forwards the messages according to the address information on the link layer. In order to ensure the security and QoS of subscriber access, the subscriber access devices usually assign a separate virtual channel on the link layer to each subscriber. In general, subscriber access devices include DSLAM devices, Ethernet switches, and wireless LAN access point devices, etc.
The network aggregation device connects the subscriber access devices to the broadband access server. The network aggregation device also works in L2 mode, i.e., it only processes link layer information in the data messages and forwards the messages according to the address information on the link layer. Since the network aggregation device has to support aggregation of many broadband subscribers, it is difficult to assign a separate virtual channel on the link layer to each subscriber; instead, it can assign a separate virtual channel on the link layer to each subscriber access device. In general, network aggregation devices include ATM switch and Ethernet switch, etc.
The broadband access server terminates the subscribers accessing link layer, i.e., it receives user ID and password, and sends them to the AAA server for authentication; if the authentication is passed successfully, the broadband access server authorizes the subscriber for Internet access. During the subscriber uses Internet, the broadband access server performs metering for the network use (duration or traffic), creates essential accounting data, and sends the data to the AAA server. The link layer protocols terminated by the broadband access server include Ethernet, ATM, and PPP protocols, etc. The broadband access server also achieves security control of subscriber's accessing network and provision of value-added services.
The AAA server stores and manages subscriber's account number and password information; during the authentication of a subscriber, it receives the subscriber's account number and password from the broadband access server, verifies them, and provide the subscriber with an authority according to the subscriber's access authority state. During the subscriber's accessing of the network, the AAA server collects the essential accounting data from the broadband access server, calculates access charge for the subscriber, and records the accounting data.
In the system shown in FIG. 1, access, aggregation, and authentication management of subscribers are implemented in three different types of devices. The three types of devices are independent to each other. During service distribution, not only the subscriber information has to be configured on the AAA server, but also subscribers-related link information is required to be configured on the three types of devices. Since all traffic of subscribers have to flow through the broadband access server, and the broadband access server has to provide duplication function for each broadband multicasting subscriber when the multicast is provided for the subscriber, thus the broadband access server will become a bottleneck of multicasting traffic.
In the existing solution of broadband access of network, the access devices are low-capacity subscriber access devices; usually, such a subscriber access device can provide accesses for tens of to hundreds of subscribers. Though the subscriber access capacity can be increased to thousands of subscribers through cascading a plurality of subscriber access devices, it is difficult to further increase the number of subscribers.
Due to the low capacity of subscriber access devices, the aggregation device has to be utilized to aggregate the subscriber access devices and then connect them to the broadband access server. In this case, the broadband access server resides on a higher network layer and manages more subscribers, resulting in the following problems: 1. the broadband access server becomes a single point of failure and a performance bottleneck; 2. the access and aggregation layers have weak control capability, the network performance is affected by the broadcasting traffic of the subscribers on the access layer, and the access layer has weak ability on anti-attacks from illegal accessed subscribers; 3. since the subscriber link layer is terminated centrally, especially in case that PPPoE protocol is used, the copy of multicasting traffic has to be accomplished at the broadband access server, resulting in a traffic bottleneck and bringing difficulty to provision of the multicasting service.
To overcome the above disadvantages, the prior art has employed a way of implementing broadband access server function at subscriber access devices. That is to say, the following functions are implemented on the access devices at the network edge: termination of the subscriber accessed link layer, authentication of subscribers, and authorization of subscriber's accessing Internet. In this way, access control of subscribers is implemented at the network edge, and thereby the performance bottleneck and single point of failure problems of central broadband access servers are overcome. Since the control of subscribers is performed at the network edge, the security of network access layer is ensured, and the broadcasting traffic from subscribers is filtered at the network edge, thereby the capacity of the access layer is increased; since the termination of subscribers is accomplished at the network edge, the problem of performance bottleneck of multicasting service is not present. However, the technical solution still has the following disadvantages:
1. difficulty in IP address planning: there are numerous subscriber access devices and each access device has to be allocated with a IP address pool separately; there are too many routes in the network due to the excessively allocated IP address pools, and therefore it is unable to enable a plurality of access devices to share the same IP address pool, resulting in waste of address resource due to unbalance address allocation. In the case of insufficient address resource, especially when the number of addresses is less than the total number of subscribers but is more than the number of concurrent access subscribers and the growth of number of concurrent access subscribers connected to each access device is unpredictable, it is difficult to plan addresses among the access devices, and thereby the situation of unavailable subscriber access often occurs locally due to insufficient addresses.
2. Difficulty in central management and reduction of operation and maintenance cost, heavy maintenance work;
3. Difficulty in cost reduction due to complicated devices on the access layer;
4. Insufficient support to value-added services due to simple access devices.

Broadband access method with great capacity and the device and the system thereof


A system and a method for multiplying data throughput in a SCSI bus includes identifying multiple frequencies within a bandwidth of a SCSI bus. A binary value is assigned to each one of the multiple frequencies. One of the multiple frequencies is selected. The assigned binary value of the selected frequency corresponds to a set of bits to be transmitted during a first sampling cycle. The selected frequency is transmitted on the SCSI bus during the first sampling cycle.

1. Field of the Invention
The present invention relates generally to computer bus systems, and more particularly, to methods and systems for increasing the data throughput of SCSI bus systems by frequency and/or phase modulating the data transmitted via the bus.
2. Description of the Related Art
A typical computer system may include a computer and peripheral devices such as, for example, storage devices that are interconnected by data buses. For the computer to transfer data to and from the storage device, an input and output connected by differential drivers may be utilized. Within a computer system, it is often desirable to connect a variety of peripherals to the system bus of the computer itself for communication with the central processing unit and other devices connected to the computer. A variety of bus types may be used for this purpose.
To access and control certain types of peripheral devices connected to a computer system, the computer generally utilizes host adapter cards (or controllers) attached to the computer's internal bus. The computer may also have peripheral device controllers built into the motherboard. These device controllers coordinate and manage the data communication to and from the peripheral devices through the various computer busses included in the computer. Device controllers can include a video display adapter, an integrated drive electronics (IDE) controller, a small computer system interface (SCSI) controller, or other similar cards or chips, which control peripheral devices.
Device controllers can communicate with the peripheral devices through one or more busses connecting the computer with the peripheral devices. For example, by use of software device drivers, a host computer can instruct a SCSI chip within the SCSI controller to manage a specific peripheral device and control the data transfer between the peripheral device and the host computer. Therefore, it is important to have optimum throughput through a bus so controllers and peripheral devices may communicate with each other in an optimum manner.
FIG. 1A illustrates an example of a computer system 10. The computer system 10 includes a computer 12, a disk drive 14, a tape drive 16, and any number of other peripherals 18 such as card reader units, voice input/output, displays, video input/output, scanners, etc. The computer and peripherals in this example are connected via a SCSI bus 20, although a wide variety of other types of buses may also be used.
Any number of computers or hosts may be present in computer system 10 and be connected to SCSI bus 20. Each computer may also contain a variety of hardware and software. By way of example, computer 12 includes a monitor 30, a motherboard 32, a wide variety of processing hardware and software 34 and a SCSI host adapter card (or interface card) 36. Host adapter card 36 provides an interface between the microcomputer bus of computer 12, located on motherboard 32, and SCSI bus 20.
SCSI is a universal interface standard for connecting disks and other high performance peripherals to microcomputers. There are both parallel SCSI and serial SCSI interfaces. While exemplary parallel SCSI interfaces are discussed herein, the concepts and principles taught can also generally be applied to series SCSI interfaces. However, it should be appreciated that computer system 10 is an exemplary system, and other interface standards having characteristics similar to SCSI may also be used in such a computer system.
In one example, SCSI bus 20 is an 8-bit parallel flat cable interface (18 total signals) with handshakes and protocols for handling multiple hosts and multiple peripherals. The parallel flat cable interface has both a synchronous and an asynchronous mode, and has defined software protocols. In the embodiment shown, the SCSI bus uses differential drivers, although SCSI is also available with single wire drivers. SCSI interface cards (such as card 36) plug into most microcomputer buses including VME, Multibus I and II, PCI, ISA, VL, EISA and MCA. In another embodiment, SCSI bus 20 is a 16-bit parallel cable interface (27 total signals). In other embodiments motherboard 32 has SCSI adapter card 36 incorporated into the motherboard itself, and a separate, plug-in adapter card is not needed. SCSI bus 20 is a multi-drop bus typically produced as a flat cable that connects from a computer 12 to any number of peripherals. In this example, disk drive 14, tape drive 16, and other peripherals 18 connect to SCSI bus 20 by tapping into the bus. In other examples, it is also possible for any number of peripherals to be included within computer 12 in which case SCSI bus 20 may also be present inside computer 12.
Disk drive 14 includes the physical disk drive unit 40 and SCSI controller card 42 and other internal cables and device level interfaces (not shown) for enabling the unit to communicate with computer 12. After connecting to disk drive 14, SCSI bus 20 continues on to connect to tape drive 16. Tape drive 16 includes the physical tape drive 50, SCSI controller card 52, and other internal cables and interfaces (not shown) for communicating with computer 12.
In a typical SCSI data transmission system, a transmitter is connected to a receiver by transmission lines. When data is transferred from the transmitter to the receiver, which may happen, for example, when the SCSI controller card 52 transmits data to the disk drive 14, data can be sent where one bit is sent in a clock cycle at given frequency. If a data transmission is double clocked, one bit may be sent per half cycle so that two bits of data may be sent during one full clock cycle. Therefore, at maximum, prior art systems are generally not capable of sending more than 2 bits per full clock cycle. Consequently, at a frequency of, for example 80 MHz, 160 Mbits of data per second may be sent. This severely limits the amount of data throughput that may be transmitted through a bus such as, for example, the SCSI bus 20.
FIG. 1B shows a diagram 50 illustrating a time progression in relation to data transmission in a typical data transmission bus. Double transition clocking, (also referred to as dual edge clocking or double clocking as used herein) can be utilized in data transmission so both the leading edge and the trailing edge of the clocking signal are used to clock a data line sampling. In this example, data sent through a bus is double clocked so two voltage signal levels corresponding to a bit content of "0" and "1" respectively are utilized to transmit data from the transmitter to the receiver. As is well known by one skilled in the art, digital data is transmitted using a single bit "0" or a single bit "1". In this environment, a signal level voltage of 0 volts corresponds to the bit content of "0" and a signal voltage of 5 volts corresponds to the bit content of "1". A clock signal 52 is coordinated with digital signal 54 so each of the clock edges initiates a signal level output as shown by data initiation 56 at time t1.
Unfortunately, after a certain frequency is reached, data transmission through a bus is limited due to numerous constraints. For example, a particular bus has a certain max bandwidth with a cut off frequency. Typically, the clock cutoff frequency is 40 MHz, and any frequency beyond 40 MHz is very difficult to utilize. Therefore, even with double clocking, it is very difficult to achieve greater than a raw data transfer rate of 80 Mbytes per second (40 Mbytes per second×2 for double clocking) in SCSI systems. Unfortunately, when the cutoff frequency is reached, the signal becomes so degraded due to increased noise levels that it is extremely difficult if not impossible to tell if the digital signal is transmitting a "0" or a "1". Consequently, after the certain frequency is reached, data throughput speed is limited and data transmission speeds can be a bottleneck in data processing operations.
In view of the foregoing, what is needed is a new and improved methodology for optimizing data transmission methods by enhancing digital data throughput through a SCSI bus. Such an approach would thereby ensure proper initialization of the computer system.

System and method for frequency and phase modulating data on a SCSI bus or a serial SCSI link


A nut and seat assembly is provided for a clamp. A nut is tightened onto a bolt and a clamp member has a seat for the nut and an aperture defined by prongs. The bolt is inserted laterally into the aperture and the nut is tightened axially against the set. Tightening the nut onto the seat prevents outward movement of the prongs away from the bolt as the nut holds the prongs in place.

The present invention relates to a nut and seat assembly for a clamp, to a clamp comprising that assembly and to methods of fastening articles such as pipe work using clamps.
A metal clamp is known for securely and hygienically attaching pipe work, typically for attachment of a flexible plastic outer hose onto a more rigid, inner metal pipe. Such clamps are in wide application, in particular in the food and hygiene industries, and as such these clamps need to comply with strict requirements for hygiene including integrity of clamping action and sealing between the pipes clamped.
The known clamp, made of metal, comprises upper, middle and lower clamping jaws, pivoted by a drilled pivot and using a connecting pin. This type of pivot is, however, rather expensive, especially in a mass-produced item such as the known clamp. Further, the clamp is made from a relatively large number of components, and it would be desirable to make a clamp with fewer components.
In use, the known clamp is opened and closed a number of times, and it is a further problem that it is easy for the bolt and/or the nut to become separated from other parts of the clamp. The clamp then has to be discarded because it is incomplete.
It would be desirable to be able to make this type of clamp in a plastics material, but the differing strengths of plastics versus metal mean that it is not possible to copy the metal clamp and simply make it out of plastic.
Lastly, the known metal clamp operates satisfactorily and there are no significant complaints about the clamp in use.


The present invention relates to a method for separating at least one solid-body layer (4) from at least one solid body (1). Thereby, the method as claimed in the invention comprises the steps:                creating a plurality of modifications (9) by means of laser beams within the interior space of the solid body (1) to form a detachment plane (8),        producing a composite structure by arranging or producing layers and/or components (150) on or above an initially exposed surface (5) of the solid body (1), wherein the exposed surface (5) is an integral part of the solid-body layer (4) to be separated,        introducing an external force into the solid body (1) for generating tensions within the solid body (1), wherein the external force is so strong that the tensions initialize a crack propagation along the detachment plane (8),        wherein the modifications for forming the detachment plane (8) are created before producing the composite structure.

A series of components in the semiconductor industry are required on thinned solid-body layers and substrates. Since thin substrates are difficult to manage within the scope of usual processes however, and also wafers can only be produced up to a specific thickness using conventional wire sawing processes, the most frequent form of production for such components on thin substrates entails grinding off or thinning the backside of the substrate after processing is finished.
Thereby, a conventional wafer is processed at the end before the finally desired substrate thickness is produced by removing the excess material at a grinding and polishing step at the end. This circumstance is unfavorable for two reasons: on the one hand, valuable material is lost to some extent during the grinding step, and on the other hand, the grinding/polishing step has the potential for a total loss of the already processed components due to substrate damage, which already contain a large part of the wafer's added value.
Another method for thinning solid bodies is revealed by the publication WO2014/177721A1. In accordance with this method, a polymer layer is attached to a solid body. By tempering the polymer layer, tensions within the solid body are then generated, by means of which a solid-body layer is separated from the remaining solid body.
In the publication DE 10 2012 001 620 A1, the use of an additional sacrificial layer between the solid body and the polymer film is described, which is used for the improved removal of the polymer film after the splitting step by chemically decomposing or detaching the sacrificial layer, for example, by means of adding suitable reactants. However, the long duration, which can last for up to several hours that pass until the polymer layer is completely removed, is unfavorable with regard to this method. This severely limits industrial use. In order to accelerate the process of removing the polymer, there is the possibility of introducing additional driving forces by means of a corresponding pretreatment in the form of suitable tensions that also act at room temperature. These lead to an increase in the contact surface for the reactants or the solvent and promote the decomposition or the detachment and removal.
Furthermore, from WO 2010/072675 A2, it is known to provide fillers within the polymer in order to be able to influence the thermal expansion coefficients or the elasticity modulus on a local level. However, it has been shown that such fillers often impair the adhesion of the polymer to the surface of the solid body to be separated so that sufficient force transmission is no longer possible.

Method for thinning solid body layers provided with components


A method and apparatus are provided for determining correlation length of body tissue, metals, crystals, or other materials, substances and the like having an ordered internal stucture (hereinafter structures) and for utilizing such correlation length to test, classify or otherwise characterize the structure. The structure is scanned using standard ultrasonic scanning technology and the output from such scan is processed to determine correlation length in one dimension (length), two dimensions (area), three dimensions (volume). A fourth dimension of time may also be used with one or more of the other three dimensions in the correlation length determination.

There are a number of fields in which improved noninvasive and nondestructive testing and characterization techniques are required. In the field of medicine, various noninvasive testing techniques currently exist, such as ultrasonic scanning and x-rays, which produce images of bone or tissue. Such images are useful for detecting abnormalities in size or shape of an organ, for detecting blockages or other abnormalities in arteries or for detecting fractures in bones. However, such images generally do not reveal chemical or other structural changes in tissue or bone which may be useful in the early diagnosis of various medical problems. For example, a change in bone structure might be indicative of the onset of osteoporosis, while changes in the organization of certain cells within an organ might be an early indication of cancer. Other organ diseases, including those of the heart, lung, liver and kidney, might also result in organizational changes in all or a portion of the affected organ which, if detected, could be used for diagnostic purposes. Further, since a noninvasive procedure such as ultrasonic scanning which does not involve any known risk or substantial discomfort to the patient may be performed at frequent intervals, such a technique could also be utilized to determine the effectiveness of various treatment regimens so that such regimens may be adjusted to meet the needs of the patient.
Similarly, with the aging infastructure in the United States and other countries, aging airline fleets and the like, there is an increasing need for a capability to nondestructively test structures, composite materials and equipment before problems develop. Again, various techniques are currently available which can detect cracks, breaks, bends or similar abnormalities which would turn up when an image of a structure, including hidden structures, is produced. However, problems in such structures can also arise as a result of oxidation, structural fatigue, or other compositional or structural changes which may occur as a result of time, use, shocks or corrosion which might not show up in an image of the structure.

Method and apparatus for the characterization of tissue or other structure


An executable module includes a dynamic data area that contains all data that may be changed by execution of the executable module. A header in the module includes a start address and an end address for the dynamic data area. The executable module is loaded in a memory. An alternate memory area is allocated in the memory. The dynamic data area is copied to the alternate memory area. The memory is mapped so that execution of the executable module modifies exactly one of the dynamic data area and the alternate memory area. A hash value is computed for the executable module. The hash value includes exactly one of the dynamic data area and the alternate memory area. The unmodified memory area is copied to the modified memory area and the hash value is recomputed to re-establish the executable module in a known state.

Computer processing units (CPUs) may read instructions from a memory and read and write data to the memory in response to the instructions. The result of executing an instruction on given data is entirely predictable in the absence of an error in the CPU. However, it is possible that an error will occur in the CPU or that the data or instruction will be erroneously altered when being transferred between the memory and the CPU. Further the results of executing an instruction may depend on the data presented to the instruction. If unexpected data is presented, it is possible that logical errors in the instruction sequence will produce unexpected and undesirable results. In the extreme, the unexpected data could alter the instructions as stored in memory leading to severely compromised results from the execution of an instruction sequence, particularly if the unexpected data is maliciously introduced.
A computer system, which may include one or more CPUs coupled to one or more memories of various types, may load executable modules into the memory. The executable modules may contain executable instruction sequences, code, and data. The CPU may be instructed to execute the code using the provided data.
In an effort to reduce the susceptibility to unexpected and undesired results from the execution of instruction sequences in an executable module, the executable module may be tested to determine if it is as expected before the CPU is instructed to use the executable module. If the executable module as seen by the CPU does not exactly match what is expected, the results of executing the module become unpredictable. The contents of the executable module may be checked by computing a hash value.
A hash value is a value obtained by combining the contents of the executable module according to a defined logical procedure known as a hash function. The hash function is designed so that the value is highly unique to the contents of the executable module and extremely sensitive to any change in the contents. Further, the hash value may be such that it is extremely difficult to deliberately create content to produce a specific hash value. Thus if the executable module produces the expected hash value, it can be assumed that the module has the expected content with an extremely high degree of confidence.
It may be desirable to re-establish that the executable module is the expected module in a condition that can be executed to predictably produce the expected results. This may be accomplished by recomputing the hash value and checking the hash value obtained against the expected hash value.
If an expected hash value for the executable module was not available when the module was initially loaded, a hash value may be computed and saved at load time. The load time hash value may be used to re-establish the executable module as being in the same condition as on the initial load.
The executable module may contain data that is altered by the expected execution of the instructions. These expected alterations will change the hash value and lead to the determination that the executable module is not in the condition where execution of the module is known to produce the expected and desired results. Thus it may be necessary to reload the executable module to re-establish the condition where execution of the module is known to produce the expected and desired results.
Hashing a loaded executable module image may be part of establishing a trusted execution environment. Changed data within the module image in memory means that any hashing function applied to the module before execution will not have the same result if applied after the module starts executing. This means that in order to re-establish a trusted environment, the module may need to be reloaded from flash memory or disk. The reload processor can be slow and disruptive to other system operations. For example, reloading the image may require execution of an SMI (System Management Interrupt). This may block other system interrupts while the image is loaded and hashed by the SMI handler code.

Method and apparatus to preserve a hash value of an executable module


A transflective LCD device includes an array substrate and a color filter. The substrate includes a plurality gate lines, a plurality of common lines, and a plurality of data lines substantially crossing the gate lines to define a plurality of sub-pixel regions. Each sub-pixel region has a reflective area and a transmissive area. Two of the reflective area of two adjacent sub-pixel regions in the same column are juxtaposed to each other. The color filter has a plurality of sub-pixel regions respectively aligned with the sub-pixel regions of the array substrate. The color filter includes an insulating layer disposed on the reflective area of a respective sub-pixel region. An LC layer is disposed between the array substrate and the color filter.

(1) Field of the Invention
The present invention relates to an LCD (liquid crystal display) device, and more specifically to a transflective LCD device.
(2) Description of the Prior Art
Due to development in the technology, multi-media products, such as mobile phones, notebook computers, digital cameras, PDAs and display screens, become more common and the demand for LCD (liquid crystal display) device is increasing day-by-day.
The LCD device can be generally classified into three types, namely: (1) transmissive (2) reflective and (3) transflective depending on supply of the light source. A backlight module is used in the transmissive LCD device and consumes a great amount of power source. Under the high ambient light (i.e. sunlight), the device has poor display ability. In the reflective type, the transmissive electrode layer is replaced by the reflective electrode layer and the device generally depends on the ambient light as the light source. Therefore, no backlight module is utilized in the reflective LCD device, but the latter suffers from non-uniform reflective brightness, thereby causing insufficient of the reflective brightness and cannot be operated under the dark environment. The transflective LCD device simultaneously has transmissive and reflective regions in order to avoid the disadvantages encountered during use of the transmissive and reflective LCD devices.
The transflective LCD structure includes an array substrate, a color filter (CF), and a liquid crystal (LC) layer. The array substrate includes a plurality of sub-pixel regions. Each sub-pixel region has a transmissive area and a reflective area. The CF has a plurality of sub-pixel regions, which are respectively aligned with the sub-pixel regions of the array substrate. The CF includes an insulating layer disposed on the reflective area of each sub-pixel region. The liquid crystal display layer is disposed between the array substrate and the color filter.
Presently, there are two transflective types. In the first type, the insulating layer is disposed on the color filter. In the second type, the insulating layer is disposed on the array substrate. The insulating layer is also called the adjustment layer since it is used to alter the thickness of the LCD layer in the reflective and transmissive areas.
Referring to FIG. 1a, a conventional transflective LCD is shown. Transflective LCD includes an array substrate 120, a color filter 110 (will be named CF later), an LC layer 130. The array substrate 120 includes a plurality of sub-pixel regions 100. Each sub-pixel region 100 has a reflective area 102 and a transmissive area 101.
The CF 110 includes a plurality of sub-pixel regions, which are respectively aligned with the sub-pixel regions 100 in the array substrate 120. Each sub-pixel region in the CF 110 has an insulating layer 140 aligned with the reflective area 102. The liquid crystal display layer 130 is disposed between the array substrate 120 and the color filter 110. An optical film 150 is further disposed on an external surface of the CF 110. Each of the sub-pixel regions 100 in the CF 110 has Red; Green and Blue colors arranged in the row manner and a plurality of the sub-pixel regions 100 cooperatively form the image on the display panel.
The array substrate 120 includes a plurality of TFTs (thin film transistor) (not shown in the drawing). The array substrate 120 further includes a reflective electrode 170 disposed on the reflective area 102 and a transmissive electrode 160 disposed on the transmissive area 101 of each of the sub-pixel regions 100. In addition, a backlight module 180 is disposed below the array substrate 120.
The external light and the backlight module 180 cooperatively supply light source to the transflective LCD panel. Flow of current through the TFTs (not numbered in the drawing) results in change of electric field between the array substrate 120 and the CF 110, thereby causing turning of the crystal molecules within the LCD layer 130, which, in turn, alters the polarization thereof such that the optical film 150 filters the different biasing light beams so as to achieve the respective brightness in each pixel. When no current is passed through the TFTs, no change is caused in the electric field such the crystal molecules within the LCD layer 130 extend vertically, thereby totally preventing passing of the light beams through the LCD layer 130.
Since the insulating layer 140 has two inclined structures at two sides; the crystal molecules thereat extend in predetermined angles, thereby forming light leakage regions 103 respectively. The light beams passing the leakage regions 103 are partially prevented and partially allowed, thereby lowing the image contrast.
Referring to FIG. 1b, another conventional transflective LCD is shown. Transflective LCD includes an array substrate 120, a CF 110, an LC layer 130 and generally similar to that of FIG. 1a. The only difference resides in that the insulating layer 140 is disposed on the reflective area 102 of the array substrate 120. This conventional transflective LCD works similar to the previous structure, and has the light leakage problem.
When using within a housing or outside of the housing, the transflective LCD panel is provided with appropriate brightness depending on the light strength of the surrounding. In case of dark state due to the light leakage in the LCD layer, the image contrast of the display panel will get lower.
Referring again to FIGS. 1a and 1b, the array substrate 120 further includes a plurality gate lines 121 and a plurality of common lines 122 generally and respectively parallel to the gate lines 121. Each common line 122 is disposed in an adjoining area between two adjacent sub-pixel regions 100 while each of the gate lines 121 is disposed between the reflective and transmissive electrodes 170, 160 of the respective sub-pixel region 100 with the reflective electrode 170 spanning across the gate line 121. A predetermined gap is defined between the reflective electrode 170 and the transmissive electrode 160 of each sub-pixel region 100 in order to prevent electrical communication therebetween.
Since no shielding is provided to cover the gap formed between the reflective and transmissive electrodes 170, 160 of the respective sub-pixel region 100, a Black Matrix 111 is provided on the CF 110 aligned with the gap so as to prevent occurrence of light leakage. According to the prior art technology, though the Black Matrix 111 can effectively prevent the light leakage between the reflective and transmissive electrodes 170, 160 of the respective sub-pixel region 100, but reduces the aperture ratio of the LCD panel.


A fluoroelastomer composition contains a peroxide-curable solid fluoroelastomer and a peroxide curative agent combined therewith, and, a bisphenol-curable liquid fluoroelastomer and a bisphenol curative agent combined therewith. The solid fluoroelastomer/peroxide curative when combined with the liquid fluoroelastomer/bisphenol curative results in a composition exhibiting improved polymeric properties including improved flowability at room temperature and improved fluid resistance and sealability at a wide range of temperatures.

Various fluoroelastomer compositions are known for use as seals, gaskets, or other rubber articles. Exemplary compositions are described in U.S. Pat. Nos. 6,221,971, 4,603,175, and 4,048,261, all incorporated herein by reference. In certain compositions, the poor or less-than-optimum flowability of the composition complicates the use of the polymeric composition in state-of-the-art processes, including injection molding, compression molding, and transfer molding.
Stated another way, the cure rate of the fluoroelastomer compositions at typical curing temperature must be inhibited or prolonged to facilitate optimum flow or viscosity of the composition during processing. By prolonging the cure rate, the fluoroelastomer composition remains flowable throughout processing and therefore, premature hardening or curing of the polymer is prevented.
Recent United States EPA requirements require improvements in partial zero emission values (EPA-PZEV) and low evaporative volatiles (LEV II). Known sealants such as silicone that exhibit higher relative permeability must be reconsidered for use in certain environments. California currently regulates the seals of an automotive engine under the Sealed Housing for Evaporative Determination (S.H.E.D.) test. The automobile is subjected to various temperature extremes during a three-day period while the ambient environment is monitored for its volatile organic concentration (VOCs). The range will be anywhere from 3.5 milligrams per vehicle per three days. Silicone seals are more permeable than fluoroelastomer seals and will not be good candidates under the new EPA requirements.
Silicone is currently favored in the seal industry because it is easily processed and has good heat resistance. Silicone also has generally good temperature properties. The seal may lose dimensional stability and swell up to 40% greater in volume thereby cracking the part interface (e.g. a cam cover) associated therewith.
Polyurethane is also known for its use as a seal. However, polyurethane begins to break down at 220° F. In general, the engineering preference is a seal maintaining its integrity to at least 300° F.
Many known fluoroelastomeric compositions simply do not exhibit preferable flow properties. Other compositions may exhibit favorable flow properties but lack other desirable properties. For example, certain compositions may not provide suitable oil resistance, water resistance, ozone resistance, high or low temperature resistance, tensile strength, elongation, and/or compression set, for example.
It would therefore be an improvement in the art to provide fluoroelastomeric compositions that exhibit as many of the desirable properties as possible while still providing enhanced flowability and processing.


Compounds of formula II are provided:

The invention relates to novel piperazine and homopiperazine derivatives which are effective platelet ADP receptor inhibitors. These derivatives may be used in various pharmaceutical compositions. In particular, the derivatives may be used in pharmaceutical compositions effective for the prevention and/or treatment of cardiovascular diseases, particularly those diseases related to thrombosis.
Thrombotic complications are a major cause of death in the industrialized world. Examples of these complications include acute myocardial infarction, unstable angina, chronic stable angina, transient ischemic attacks, strokes, peripheral vascular disease, preeclampsia/eclampsia, deep venous thrombosis, embolism, disseminated intravascular coagulation and thrombotic cytopenic purpura. Thrombotic and restenotic complications also occur following invasive procedures, e.g., angioplasty, carotid endarterectomy, post CABG (coronary artery bypass graft) surgery, vascular graft surgery, stent placements and insertion of endovascular devices and protheses. It is generally thought that platelet aggregates play a critical role in these events. Blood platelets, which normally circulate freely in the vasculature, become activated and aggregate to form a thrombus with disturbed blood flow caused by ruptured atherosclerotic lesions or by invasive treatments such as angioplasty, resulting in vascular occlusion. Platelet activation can be initiated by a variety of agents, e.g., exposed subendothelial matrix molecules such as collagen, or by thrombin which is formed in the coagulation cascade.
An important mediator of platelet activation and aggregation is ADP (adenosine 5′-diphosphate) which is released from blood platelets in the vasculature upon activation by various agents, such as collagen and thrombin, and from damaged blood cells, endothelium or tissues. Activation by ADP results in the recruitment of more platelets and stabilization of existing platelet aggregates. Platelet ADP receptors mediating aggregation are activated by ADP and some of its derivatives and antagonized by ATP (adenosine 5′-triphosphate) and some of its derivatives (Mills, D. C. B. (1996) Thromb. Hemost. 76:835–856). Therefore, platelet ADP receptors are members of the family of P2 receptors activated by purine and/or pyrimidine nucleotides (King, B. F., Townsend-Nicholson, A. & Burnstock, G. (1998) Trends Pharmacol. Sci. 19:506–514).
Recent pharmacological data using selective antagonists suggests that ADP-dependent platelet aggregation requires activation of at least two ADP receptors (Kunapuli, S. P. (1998), Trends Pharmacol. Sci. 19:391–394; Kunapuli, S. P. & Daniel, J. L. (1998) Biochem. J. 336:513–523; Jantzen, H. M. et al. (1999) Thromb. Hemost. 81:111–117). One receptor appears to be identical to the cloned P2Y1 receptor, mediates phospholipase C activation and intracellular calcium mobilization and is required for platelet shape change. The second platelet ADP receptor important for aggregation mediates inhibition of adenylyl cyclase. Molecular cloning of the gene or cDNA for this receptor (P2Y12) has recently been reported (Hollopeter, G. et. al. (2001) Nature 409:202–207.) Based on its pharmacological and signaling properties this receptor has been previously termed P2YADP (Fredholm, B. B. et al. (1997) TIPS 18:79–82), P2TAC (Kunapuli, S. P. (1998), Trends Pharmacol. Sci. 19:391–394) or P2Ycyc (Hechler, B. et al. (1998) Blood 92, 152–159).
Various directly or indirectly acting synthetic inhibitors of ADP-dependent platelet aggregation with antithrombotic activity have been reported. The orally active antithrombotic thienopyridines ticlopidine and clopidogrel inhibit ADP-induced platelet aggregation, binding of radiolabeled ADP receptor agonist 2-methylthioadenosine 5′-diphosphate to platelets, and other ADP-dependent events indirectly, probably via formation of an unstable and irreversible acting metabolite (Quinn, M. J. & Fitzgerald, D. J. (1999) Circulation 100:1667–1667). Some purine derivatives of the endogenous antagonist ATP, e.g., AR-C (formerly FPL or ARL) 67085MX and AR-C69931MX, are selective platelet ADP receptor antagonists which inhibit ADP-dependent platelet aggregation and are effective in animal thrombosis models (Humphries et al. (1995), Trends Pharmacol. Sci. 16, 179; Ingall, A. H. et al. (1999) J. Med. Chem. 42, 213–230). Novel triazolo [4,5-d] pyrimidine compounds have been disclosed as P2T-antagonists (WO 99/05144). Tricyclic compounds as platelet ADP receptor inhibitors have been disclosed in WO 99/36425. More recently, sulfonylureas and related compounds have also been disclosed as specific ADP receptor inhibitors in WO 01/57037. The target of these antithrombotic compounds appears to be the platelet ADP receptor mediating inhibition of adenylyl cyclase.
Despite these compounds, there exists a need for more effective platelet ADP receptor inhibitors. In particular, there is a need for platelet ADP receptor inhibitors having antithrombotic activity that are useful in the prevention and/or treatment of cardiovascular diseases, particularly those related to thrombosis.

Abstract: Compounds of formula II are provided:

Abstract: wherein A, J and L are independently a direct link or a divalent linking group. The compounds are useful in the treatment of thrombosis.


A semiconductor device includes a capacitor with an insulator having an improved durability. In the semiconductor device, a capacitor lower electrode 11 of the cylindrical capacitor includes a standing wall portion 11b which is formed of a polysilicon layer having a large crystal grain diameter (1000.ANG.-10000.ANG.).

1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method of the same, and in particular, to a dynamic random access memory (DRAM) and a manufacturing method of the same.
2. Description of the Background Art
Owing to remarkable spread of information equipments such as a computer, demand for semiconductor memory devices has been rapidly increased. In particular, semiconductor devices having such functional features as large-scale memory capacities and high-speed operations have been demanded. Correspondingly, technical development has been progressed for high integration, high-speed responsibility and high reliability of the semiconductor memory devices.
Among the semiconductor memory devices, a DRAM (dynamic random access memory) has been known as a device capable of random input and output of memory information. In general, the DRAM is formed of a memory cell array, which is a memory region storing a large amount of information, and a peripheral circuitry required for external input and output.
FIG. 34 is a block diagram showing a construction of a conventional DRAM. Referring to FIG. 34, a DRAM 150 includes a memory cell array 151 for storing data signals of memory information, a row and column address buffer 152 for externally receiving an address signal which is used for selecting the memory cell forming a unit memory circuit, row and column decoders 153 and 154 which decode the address signal to designate the memory cell, a sense refresh amplifier 155 which amplifies the signal stored in the designated memory cell to read the same, data-in and data-out buffers 156 and 157 for data input and data output, and a clock generator 158 for generating a clock signal.
The memory cell array 151 occupying a large area in the semiconductor chip is formed of a plurality of memory cells for storing unit memory information disposed in a matrix form. FIG. 35 is an equivalent circuit diagram showing memory cells for 4 bits forming the memory cell array 151. Each memory cell is formed of one MOS (Metal Oxide Semiconductor) transistor and one capacitor connected thereto. Such memory cell is referred to as a memory cell of one-transistor and one-capacitor type. The memory cells of this type have simple structures and the degree of integration of the memory cell array can be easily increased, so that they have been widely used in DRAMs of large capacities.
The memory cells of the DRAMs can be classified into several types based on their structures of the capacitors. Among several types of the capacitors, a stacked type capacitor has such a feature that a major part of the capacitor may be extended over a gate electrode and a field isolating film, so that areas of opposed surfaces of electrodes of the capacitor can be increased and thus the capacitor capacitance can be increased. Since the stacked type capacitor has the foregoing feature, a sufficient capacitor capacitance can be ensured even if elements are miniaturized to a higher degree in accordance with the high integration of the semiconductor device. As a result, stacked type capacitors have been widely used in accordance with the high integration of the semiconductor devices. The semiconductor devices are now being further integrated, and the stacked type capacitors complying with it are now being developed. More specifically, a stacked type capacitor of a cylindrical form, which is intended to ensure an appropriate capacitor capacitance even if the semiconductor device is further integrated and thus has further miniaturized elements, has been proposed, e.g., Japanese Patent Application No. 02-89869 (1990).
FIG. 36 is a plan showing a conventionally proposed DRAM provided with cylindrical stacked type capacitors. FIG. 37 is a cross section of the DRAM taken along line X--X in FIG. 36.
Referring to FIGS. 36 and 37, the proposed DRAM in the prior art includes a silicon substrate 201, an element isolating oxide film 202 formed on a predetermined region of a major surface of the silicon substrate 201 for isolating elements, source/drain regions 206a, 206b, 206c and 206d, which are surrounded by the element isolating oxide film 202 with predetermined spaces therebetween and are located at opposite sides of a channel region 220, gate electrodes 204b and 204c formed on the channel regions 220 with gate oxide films 205 therebetween, word lines (gate electrodes) 204d and 204e formed on the element isolating oxide film 202 with a predetermined space therebetween, and insulating films 207 covering the gate electrodes 204b, 204c, 204d and 204e. The source/drain regions 206a and 206b and the gate electrode 204c form a transfer gate transistor 203 of one of the memory cells. The source/drain regions 206a and 206c and the gate electrode 204b form the transfer gate transistor 203 of the other memory cell.
The proposed DRAM in the prior art further includes a buried bit line 208 electrically connected to the source/drain region 206a, an insulating film 209 covering the buried bit line 208, a base portion 211a forming a storage node (capacitor lower electrode) 211 which is electrically connected to the source/drain region 206b and extends over the insulating films 207 and 209, a standing wall portion 211b which is formed on the base portion 211a and extends perpendicularly to the silicon substrate 201 from the outermost edge of the base portion 211a for forming the storage node 211, a capacitor insulating film 212 covering the base portion 211a and the standing wall portion 211b, a cell plate 213 (capacitor upper electrode) covering the capacitor insulating film 212, an interlayer insulating film 214 covering the cell plate 213 and having a flat surface, interconnection layers 215 formed on the interlayer insulating film 214 and corresponding to the gate electrodes 204b, 204c, 204d and 204e, respectively, and a protection film 216 covering the interconnection layers 215. The base portion 211a and standing wall portion 211b, which form the storage node 211, as well as the capacitor insulating film 212 and the cell plate 213 form a cylindrical stacked type capacitor 210 for accumulating the charges corresponding to the data signal. The base portion 211a and the standing wall portion 211b, which form the storage node 211, are formed of polysilicon layers. The capacitor insulating film 212 is formed, e.g., of a nitride film. The cell plate 213 is formed of a polysilicon layer.
FIGS. 38-51 are cross sections showing a manufacturing process (first-fourteenth steps) of the DRAM shown in FIG. 37. Referring to FIGS. 37 and 38-51, the manufacturing process of the conventional DRAM will be described below.
First, as shown in FIG. 38, the element isolating oxide film 202 is formed on the predetermined region of the major surface of the silicon substrate 1 by an LOCOS method.
Then, as shown in FIG. 39, a thermal oxidation method is used to form the gate oxide film 205, and then the gate electrodes (word lines) 204b, 204c, 204d and 204e are selectively formed. The insulating film 207 covering the gate electrodes 204b-204e are formed by two oxide film forming steps and two etching steps. The gate electrodes 204b, 204c, 204d and 204e covered with the insulating film 207 are used as a mask for ion implantation, by which impurity is ion-implanted into the surface of the silicon substrate 201. Thereby, the source/drain regions 206a, 206b, 206c and 206d are formed.
Then, as shown in FIG. 40, a high-melting point metal layer, e.g., of tungsten, molybdenum or titanium is formed and then is patterned into a predetermined shape. Thereby, the buried bit line 208 directly connected to the source/drain region 206a is formed. The insulating film 209 is formed to cover the buried bit line 208.
As shown in FIG. 41, a CVD method is used to form a polysilicon layer 211b doped with impurity on the whole surface of the silicon substrate 201.
As shown in FIG. 42, the polysilicon layer 211c is covered with an insulating layer 235 formed of, e.g., silicon oxide film (SiO.sub.2). The thickness of this insulating layer 235 determines the height of the standing wall portion 211b which forms the storage node (the lower electrode of the capacitor).
As shown in FIG. 43, resist (not shown) is applied to the surface of the insulating layer 235, and lithography is used to pattern the same into a predetermined shape. Thereby, a resist pattern (capacitor insulating layer) 236 is formed. The width of the resist pattern 236 determines the space between the adjacent capacitors.
As shown in FIG. 44, the resist pattern 236 is used as a mask for applying anisotropic etching, by which the insulating layer 235 is selectively removed. Thereafter, the resist pattern 236 is removed.
As shown in FIG. 45, the CVD method is used to form a polysilicon layer 211d containing the impurity on the whole surface. The thickness of this polysilicon layer 211d is smaller than the thickness of the polysilicon layer 211c formed thereunder.
As shown in FIG. 46, a thick resist 237 is formed to cover the whole surface of the polysilicon layer 211d. Etchback is applied the resist 237 to expose the polysilicon layer 211d covering the upper surface of the insulating layer 235.
As shown in FIG. 47, the etching is applied to the exposed polysilicon layer 211d (see FIG. 46), and subsequently the etching is applied to the insulating layer 235 (see FIG. 46) in a self-aligned manner to remove the same. Thereby, the surface of the polysilicon layer 211c is partially exposed. Also, the standing wall portion 211b forming the storage node 211 is completed.
As shown in FIG. 48, the exposed polysilicon layer 211c (see FIG. 47) is removed in a self-aligned manner by the anisotropic etching. Thereafter, the resist 237 (see FIG. 47) is removed. Thereby, the base portion 211a forming the capacitor lower electrode (storage node) 211 is completed. Thus, the capacitor lower electrode (storage node) 211 formed of the base portion 211a and the standing wall portion 211b is completed.
As shown in FIG. 49, the thin capacitor insulating film 212 formed of e.g., a silicon nitride film is formed on the surface of the capacitor lower electrode 211.
As shown in FIG. 50, the cell plate 213 made from electrically conductive polysilicon is formed on the whole surface. Thereby, the stacked type capacitor 210, which includes the base portion 211a and standing wall portion 211b forming the capacitor lower electrode 211 as well as the capacitor insulating film 212 and cell plate 213 is completed.
As shown in FIG. 51, the cell plate 213 is covered with the thick interlayer insulating film 214. The interconnection layer 215 of, e.g., aluminum having a predetermined shape is formed on the surface of the interlayer insulating film 214.
Finally, as shown in FIG. 37, the surface of the interconnection layer 215 is covered with the protection film 216. By the foregoing steps, the memory cells of the conventional DRAM are formed.
As stated before, in the conventional DRAM, the standing wall portion 211b, which forms the cylindrical capacitor lower electrode (storage node) 211, is made of polysilicon.
The polysilicon generally has microscopical unevenness on its surface. FIG. 52 is an enlarged view of a portion of the polysilicon layer 211d indicated by A in the manufacturing step of FIG. 45. Referring to FIG. 52, the polysilicon layer 211d formed on the side surface of the insulating layer 235 has the surface roughness of about 1/10 of its thickness. For example, if the polysilicon layer 211d has the thickness of 1000.ANG., its surface 300 has the roughness of about 100.ANG.. The unevenness of the surface of the polysilicon layer 211d is caused by the grain boundary. More specifically, the polysilicon layer 211d includes silicon crystal grains having different grain diameters in a range from about 200.ANG. to about 500.ANG.. Therefore, the crystal grains have different growth rates, and thus some grains grows more rapidly than others. As a result, the microscopical unevenness is formed in the upper surface of the polysilicon layer 211d.
Referring to FIG. 37, in a macroscopical view, the cell plate 213 has an angular end 213a which is formed on a surface of a bent portion of the standing wall portion 211b with the capacitor insulating film 212 therebetween. FIG. 53 is an enlarged cross section showing a portion B of the DRAM shown in FIG. 37. Referring to FIG. 53, the end 213a of the cell plate 213 opposed to the bent portion 301 of the standing wall portion 211b 301 has a protruding shape.
As stated above, in the prior art, the surface 300 of the standing wall portion 211b microscopically has the unevenness (see FIG. 52), and the end 213a of the cell plate 213 macroscopically has the protruding shape (see FIG. 53). The microscopically uneven surface 300 of the standing wall portion 211b and the macroscopical protruding end 213a of the cell plate 213 disadvantageously reduce the durability of the capacitor insulating film 212 in the prior art. More specifically, the microscopical unevenness of the surface 300 of the standing wall portion 211b causes irregular electric field applied to the capacitor insulating film 212, resulting in reduction of the durability of the insulating film. Further, the electric field is concentrated at the end 213a of the cell plate 213, which also reduces the durability of the capacitor insulating film 212.

Semiconductor device having a polysilicon capacitor with large grain diameter


Provided is a waterproof sound-transmitting membrane 1 including: a solid resin film 2 having a plurality of through holes 21 formed therein; and a treatment layer 3 having water repellency and formed on at least one of two surfaces of the resin film 2 that are opposite to each other in the thickness direction. The treatment layer 3 has openings 31 at positions corresponding to the through holes 21. The air permeability of the waterproof sound-transmitting membrane 1 is 100 seconds/100 mL or less in terms of Gurley number.

Conventionally, in electrical products such as mobile phones, digital cameras, digital video cameras, and remote controllers, a housing containing an audio device such as a microphone and a speaker is provided with an opening for allowing transmission of sounds, and a waterproof sound-transmitting membrane is used to cover the opening. As an example of such a waterproof sound-transmitting membrane, Patent Literature 1 describes a porous membrane obtained by stretching a sheet made of polytetrafluoroethylene (PTFE).

Waterproof sound-transmitting membrane and electrical product


A voltage level shift system transitions a voltage signal between two components and includes a first inverter, a signal pass subsystem, a pull-up transistor, a second inverter, and a third inverter. The first inverter is coupled to the signal pass subsystem. The signal pass subsystem is coupled to the pull-up transistor, the second inverter, and the third inverter. The signal pass subsystem includes a first passgate and a second passgate. When an input voltage transitions from a logic low to a logic high, the first inverter inverts the logic high input signal to a logic low and passes this signal through the passgate subsystem. The second inverter receives the logic low signal and immediately inverts it to transition the output signal from a low logic to a logic high. The logic high output signal, turns off the pull-up transistor. When the input signal transitions from a logic high to a logic low, the first inverter receives the signal and generates a logic low signal that passes through the passgate subsystem. The second inverter receives the logic low signal and immediately inverts it to transition the output signal from a logic high to a logic low. The logic low signal places the pull-up transistor in an on state to turn off the p-device in the circuit. A method for transitioning a voltage signal between two components is also disclosed.

1. Field of the Invention
The present invention relates to a voltage level shift system and method, and more particularly, to a voltage level shift system and method between a core device and a peripheral device.
2. Description of the Related Art
Conventional voltage level shift circuits for use between a core power supply and an input/output ("I/O") portion in a microchip are known. Conventional voltage level shift circuits shift a voltage signal from a lower voltage level at the core power supply, e.g., 2.5 volts, to a higher voltage level necessary for the I/O portion of the microchip.
FIG. 1 illustrates a conventional voltage level shift circuit 10. The conventional voltage level shift circuit 10 includes an input signal line 12, a first inverter 15, a n-channel metal-oxide semiconductor field-effect transistor ("MOSFET") 20, a second inverter 25 a p-channel pull-up transistor 30, a low voltage supply rail 35, a high voltage supply rail 40, and an output signal line 42. The low voltage supply rail has a voltage of V.sub.DDL =2.5 volts and the high voltage supply rail 40 has a voltage V.sub.DDH =3.3 volts.
The input signal line 12 is coupled to the core power supply (not shown) and the first inverter 15. The first inverter 15 is coupled to the low voltage supply line 35 and the n-channel MOSFET 20. The n-channel MOSFET is coupled to the low voltage supply line 35, a drain of the p-channel pull-up transistor 30, and the second inverter 25. A source of the p-channel pull-up transistor 30 is coupled to the high voltage supply line 40 and a gate of the pull-up transistor 30 is coupled to the output signal line 42. The second inverter 25 is coupled to the high voltage supply line 40 and the output signal line 42.
When the conventional voltage level shift circuit 10 receives a voltage signal that transitions from a high voltage to a low voltage (e.g., 2.5 volts to 0 volts) from the core power supply, the input voltage signal is inverted to a logic high by the first inverter 15 to a voltage of 2.5 volts. The 2.5 volt signal is passed by the n-channel MOSFET 20 to the second inverter 25.
The n-channel MOSFET 20, however, reduces the voltage signal by a threshold voltage, V.sub.T =0.7 volts, so that the second inverter 25 receives only a (V.sub.DDL)-(V.sub.T)=1.2 volt signal (2.5 volts (V.sub.DDL)-0.7 volts (V.sub.T)). The second inverter 25 must wait for the p-channel pull-up transistor 30 to pull the voltage level up to VDDH=3.3. volts, and the triggering signal for the second inverter 25 will not be more than (V.sub.DDL)-(V.sub.T) volts. Therefore, the voltage signal transition from a logic high to a logic low in conventional voltage level shift circuits 10 will have more delays than a transition from a logic low to a logic high.
Thus, conventional voltage level circuits 10 are not suitable for low-input voltage applications because the voltage drop through the n-channel MOSFET 20 is too large to allow the second inverter 25 to invert the voltage signal to trigger transitions between low and high in a timely manner. That is, the time required to pull-up the voltage to an adequate level that allows the second inverter 25 to invert the signal adds delays to the operation of the circuit. These delays slow down overall circuit performance and result in decreased overall system performance. Moreover, conventional voltage level shift circuits 10 require greater system resources, for example, a greater power draw to accommodate for the need to raise voltage levels to a level that is necessary to properly perform functions such as properly transitioning between logic lows and highs in a timely manner.
Therefore, there is a need for a voltage level shift system and method that allows for signal transitions between two signal levels in a manner that increases overall system performance with less power consumption.


Techniques for accelerating training through optimization of the psychophysiological state of the trainee are provided. These techniques include an adaptive performance training system configured to acquire, analyzed, display, and translate data that reflects the psychophysiological state of the user, including the electrical activity of the brain (EEG), the heart (EKG), the musculature (EMG), respiration and other parameters that characterize the state of the user in real-time. The system includes a plurality of feedback mechanisms for providing visual, auditory, and/or tactile feedback based on the current psychophysiological state of the user and for facilitating moving the user toward a goal psychophysiological state for performing a particular task and for optimizing performance of that task.

There are numerous methods available for detecting physiological signals including electroencephalograph (EEG), electrocardiograph (EKG), and electromyography (EMG) and for translating these signals into meaningful feedback to provide information to the user regarding their psychophysiological state. This is most frequently done in a controlled laboratory environment involving multiple computers and trained technical staff. In addition, the majority of the applications described involve training the user to increase or decrease simple derivative measures of EEG such as the alpha or theta bands or increasing or decreasing heart rate or a specific pattern of muscle activity.
It is theorized that each of the major sub-bands of biofeedback EEG (delta, theta, alpha, beta) correspond with unique subjective characteristics of an individual. The delta band is observed most clearly in deep sleep, the theta band in light sleep and drowsiness, the alpha band in a variety of wakeful states involving creativity, calm and inner awareness, and the beta band in alert wakeful situations with external focus. One problem with laboratory based feedback training is that it is conducted in a constrained environment with relatively limited number of stimuli, situations or tasks that the subject is supposed to learn how to handle. Specifically, training is typically confounded with few distracters that tend to be perceived as artificial and become predictable after some time spent in the lab. In effect, the knowledge gained or skills learned may not transfer well to real-world applications and the retention times are short. Repeated visits to the laboratory are then required for the user to maintain the control over physiological states.
Many different approaches have been taken to EEG biofeedback to achieve mental state control. For example, U.S. Pat. No. 4,928,704 describes a biofeedback method and system for training a person to develop useful degrees of voluntary control of EEG activity. EEG sensors are attached to cortical sites on the head for sensing EEG signals in a controlled environmental chamber. The signals are amplified and filtered in accordance with strict criteria for processing within time constraints matching natural neurological activity. The signals are filtered in the pre-defined bands of alpha, theta, beta and delta, and fed back to the monitored person in the form of optical, aural or tactile stimuli. In another example, U.S. Pat. No. 4,949,726, U.S. Pat. No. 5,024,235, and U.S. Pat. No. 5,406,957 describe an EEG Neurofeedback apparatus for training and tracking of cognitive states which measures bioelectric signals in bandwidth windows to produce a composite amplitude by a fast Fourier transform on an amplified signal. Selected bandwidths are displayed and monitored by computer to enable training of a person being monitored with audio or verbal feedback. All these systems are lab-based, and cannot be applied in the field. In addition, the definition of desired or target mental states is given 'ad hoc' without any reference to mental states of subjects who are considered experts in a task at hand.