A toilet device comprising a toilet bowl which is provided with a seat, a flushing water inlet and an outlet for waste water. The toilet bowl is installed at a predetermined level above the floor. The distance and the position of the toilet bowl can be changed in relation to the floor by means of a device. The comfortable toilet device can also be used as urinal in a hygienic manner and can be equally used by different sized person, i.e. adults and children.

The invention relates to a toilet device with a bowl having a seat, an inlet for flush water and an outlet for waste water, wherein a device is provided which allows the lifting and tilting of the bowl in a direction towards the user into an ordinary position of the urinal.
A toilet device of this type is known from document D1 (=JP-A-03158535). D1 describes a toilet device with a bowl 6 equipped with a seat 7 having an inlet aperture for flush water and an outlet aperture for waste water (see FIGS. 1, 3-7), wherein the bowl is height adjustable (see FIG. 7), and wherein an adjustment to an ordinary urinal is provided (see FIG. 4) by an additional tilting to the front (see FIG. 1).
The latter toilet device has the disadvantage that the removal of the waste water is achieved by a hose coupling. Rapid clogging and soiling can be expected for such a solution, since the hose couplings in general do not feature smooth and straight surfaces. The detached adjusting elements are a further disadvantage of this toilet device, because the adjustment of the toilet device leads to a risk of injury.
It is an object of the invention to provide a toilet device of the above-mentioned type wherein the waste water device 12, 20, 31, 32 ensures a safe draining of the waste water in every position of the bowl 10, whereby the water level in the drain trap 12 is kept on its position, and which efficiently enables a lifting and tilting of the bowl 10 by simple means.
For a toilet device of the above-mentioned type, the latter object is solved by connecting the waste water outlet to a U-shaped articulated tube 20 being uniformly bended at both ends, the front end of which is telescopically connected via a drag bearing 22 in a flexible manner to the drain trap 12 being uniformly bended at its end, and the back end of which is telescopically connected via a drag bearing 22 in a flexible manner to the uniformly bended beginning of the vertical waste pipe 31, 32 for the drain of waste water.
It is one advantage of the toilet device according to the invention that the waste water is discharged via tubes whereby the likelihood of soiling and clogging of the waste water outlets is not larger than with conventional toilet devices. The latter embodiment ensures that even during a permanent loading with waste water the water level in the drain trap 12 is retained on the same level in any position of the bowl, thereby preventing a smell annoyance.
Preferred embodiments of the invention are subject matter of the dependent claims.
The preferred embodiment of the toilet device according to claim 2 of the present invention enables the inflow of flush water in every position of the bowl 10.
In the preferred embodiment of the toilet device according to claim 3 of the present invention the U-shaped articulated tube 20 in combination with the support structure 13 constitute the load-bearing and guiding elements of the bowl 10.
Therein, the device for adjusting, e.g. enlarging, the vertical distance of the drag bearing 14 at the flush water tube 13 to the drag bearing 22 at the waste pipe 31, 32 being in a vertical position during use, is realized in a way which permits a lifting and tilting of the bowl 10 to an ordinary position of the urinal.
By using a toilet device according to the present invention, the device 30, 34, 40, 60 for lifting and tilting of the bowl, the scouring pipe 51, and the vertical waste pipe 31, 32 can be placed behind a facing wall 71, so that the bowl in the default position optically resembles the appearance of a wall-hung toilet.
The device for lifting and tilting of the bowl may be realized in a way which allows the moving of the bowl via electromagnetic devices of via hydraulic devices. When using a hydraulic device, it is in particular advantageous to use the existing pressure of the water conduit for lifting and tilting of the bowl.
The provision of the device 30, 34, 40, 60 for lifting and tilting of the bowl also allows an adjustment of the sitting height of the bowl or the height of the tilted bowl used as a urinal.
The device 30, 34, 40, 60 for lifting and tilting of the bowl enables the use of the toilet device according to the present invention as a device facilitating the standing up of respective disabled persons.

Toilet device that can be transformed into a urinal


The invention provides a method, system, and network entity for improving Soft Handover (SHO) Gain in networks, preferably in CDMA networks, comprising the step of determining the network performance in the UL (uplink) or in the DL (downlink), or both in the UL (uplink) and in the DL (downlink), and of measuring and tuning at least one or more of those parameters, preferably system outputs, that are directly related to SHO Gain, so as to control, preferably maximise, SHO Gain. The determination of the network performance provides an indicator of when and where SHO Gains are needed. The invention can be implemented in the RNC and/or BS and can e.g. be part of RAN, e.g. an UTRAN solution as well as IP RAN.

The invention generally relates to a method and system to optimise soft handover gain in networks such as CDMA (Code Division Multiple Access) networks, or wideband code division multiple access (WCDMA) systems such as the universal mobile telecommunication system (UMTS).
In CDMA Radio Access Network Optimisation several methods are used for tuning the network performance. Soft Handover is one of the important optimisation areas because it has significant influence on system quality, capacity and coverage. Soft Handover may provide, for uplink, Rx diversity, separate decoding at each NodeB, selection combining at RNC (based on frame reliability indicator), and for downlink, double signal power, double interference, improved fading statistics. Different DL power control commands are possible, or a combination of soft values.
Soft-handover (SHO) means that a user equipment (UE) may be connected to two or more base stations (BS) when moving from one cell to another. In general, application of SHO makes it possible to have seamless (transparent) handover and improved coverage. However, SHO requires a higher average transmit power level from BS's in the network, also know as the SHO overhead. The SHO overhead is in general a function of the handover parameters Window13 Add and Window13 Drop.
For optimising the Soft Handover (SHO) usually a parameter "Soft Handover (SHO) Overhead" is measured and tuned. This value is easy to measure. The metric, i.e. measured value of "SHO Overhead" is tuned to a (arbitrary) specific target value. This target value is determined based on uniform traffic distributions and provides decent network performance for such cases. The target for the "SHO Overhead" in the tuning is also often set to a value which is acceptable in terms of the allowed capacity for the backbone network, e.g. BTS-RNC (Base Transceiver Station, Radio Network Controller) links. The importance of the "Soft Handover Overhead" metric is to make sure that the overhead in terms of the number of connections per cell is not excessive.

Method and system to optimise soft handover gain in networks


A method, system, and computer-readable storage medium are disclosed for editing a digital image with automatic conversion of region modalities. Input comprising an instruction to perform an operation on a first portion of the digital image may be received. The first portion of the digital image may comprise data defined by a first region modality. The operation may be applicable to data defined by a second region modality. In response to receiving the input, the first portion of the digital image may be automatically converted from the first region modality to the second region modality. The operation may be automatically performed on the converted first portion of the digital image (i.e., as defined by the second region modality).

1. Field of the Invention
This application is a continuation of U.S. application Ser. No. 11/610,285, which was filed on Dec. 13, 2006, now issued as U.S. Pat. No. 7,831,108.
2. Description of the Related Art
Digital image editing is the process of creating and/or modifying digital images using a computer system. Using specialized software programs, users may manipulate and transform images in a variety of ways. These digital image editors may include programs of differing complexity such as limited-purpose programs associated with acquisition devices (e.g., digital cameras and scanners with bundled or built-in programs for managing brightness and contrast); limited bitmap editors suitable for relatively simple operations such as rotating and cropping images; and professional-grade programs such as Adobe Photoshop®, Adobe Illustrator®, and Adobe AfterEffects® (all available from Adobe Systems, Inc.) with large and complex feature sets.
Digital images may include raster graphics, vector graphics, or a combination thereof. Raster graphics data (also referred to herein as bitmaps) may be stored and manipulated as a grid of individual picture elements called pixels. Suitable image editors may be used to modify pixels (e.g., values such as hue, brightness, saturation, transparency, etc.) on a pixel-by-pixel basis or as a group. A bitmap may be characterized by its width and height in pixels and also by the number of bits per pixel. Commonly, a color bitmap defined in the RGB (red, green blue) color space may comprise between one and eight bits per pixel for each of the red, green, and blue channels. An alpha channel may be used to store additional data such as per-pixel transparency values. A black and white bitmap may require less space (e.g., one bit per pixel). Raster graphics are often used for photographs and photo-realistic images.
Vector graphics data may be stored and manipulated as one or more geometric objects. The geometric primitives (e.g., points, lines, polygons, Béizier curves, and text characters) may be based upon mathematical equations to represent parts of digital images. Suitable image editors may be used to perform operations on these objects such as rotation, translation, stretching, skewing, changing depth order, and combining with other objects. Vector graphics are often rasterized, or converted to raster graphics data, in the process of displaying the data on a display device or printing the data with a printer. While raster graphics may often lose apparent quality when scaled to a higher resolution, vector graphics may scale to the resolution of the device on which they are ultimately rendered. Therefore, vector graphics are often used for images that are sought to be device-independent, such as in typesetting and graphic design.
Many digital image editing operations may be applied selectively to a portion of the digital image. A digital image editor may provide more than one way to define a portion of a digital image on which an operation is sought to be performed. These ways of defining a portion of a digital image are referred to herein as "region modalities" or "modalities." Suitable region modalities may include paths, masks, and selections.
A path may comprise a vector description of a line, curve, or enclosed object (e.g., a polygon). Vector-based tools such as a pen tool, a freeform pen tool, a type tool, a rectangle tool, a polygon tool, a line tool, and other suitable tools may be used to generate paths. Suitable path-based operations may be applied to paths. For example, a path may be stroked so that another tool (e.g., a paintbrush) may modify the region along the path.
A mask may typically comprise any image having a single color channel (e.g., a grayscale image). Masks may be used for various purposes. For example, an alpha channel may be a raster image mask which is used to form one component of a color image or the single component of a grayscale image. A layer mask may be used to modulate the blending of two layers (e.g., by removing or "masking" a portion of one or more layers from the final image). A soft mask may comprise a raster image mask having some values which lie between the minimum and maximum values. Suitable mask-based operations may be applied to modify the mask. For example, various filters (e.g., Gaussian blur, median filter, add noise, reduce noise, fragment, unsharp mask), image adjustments (e.g., levels, curves, brightness/contrast, shadow/highlight), and other operations (e.g., resizing, cropping, thresholding, rotation, perspective distortion) may be applied to masks.
A selection may represent a region of interest in the digital image and may include one or more pixels (comprising one or more color channels) and/or geometric objects. A selection may be represented by a raster image mask having a single channel indicating per-pixel or per-object membership (full, none, or partial) in the selection. In most digital image editors, selections may be generated in various ways. For example, a marquee tool may permit the selection of rectangular or elliptical areas in an image. A lasso tool may allow the user to draw a freehand selection area. A magic wand tool may permit the selection of parts of an image based on a color range of pixels. Facilities such as edge detection, masking, alpha compositing, and color and channel-based extraction may also be used to generate selections. The pixels and/or objects in the selection may be contiguous or non-contiguous. Suitable selection-based operations may be applied to modify the selection itself. For example, a border operation may produce a selection that borders the edges of the original selection. Expand and contract operations may respectively make the selection larger or smaller. A smooth operation may smooth out irregularities in the selection. A feather operation may add softness to the edges of the selection.
Therefore, various region modalities such as paths, masks, and selections may comprise various ways of defining a portion of a digital image for localized image processing. However, certain image editing operations may be configured for application only to a path, only to a mask, or only to a selection. Although some image editing programs may provide facilities for manually converting paths, masks, and selections to one another, these facilities may be cumbersome and time-consuming to use.

This patent is subject to a terminal disclaimer.

Universal front end for masks, selections, and paths


A method of polishing the diamond-surfaces generates abraded powder less, enables the polishing member to maintain an extended life and to be easily controlled, makes it possible to obtain the surfaces of a high degree of smoothness, and can be easily applied to polishing rugged three-dimensional surfaces, too. A method of polishing the diamond-surface by using a polishing member that has a metal-surface that easily reacts with carbon or of a carburizing metal, irradiating the diamond-surface with a laser beam prior to polishing the diamond-surface with the polishing member, following the irradiation with the laser beam, the polishing is conducted by rubbing a laser beam-irradiated portion with the polishing member.

As is well known, the diamond which is a crystal of carbon has been used for a variety of applications owing to its very high hardness, excellent resistance against abrasion as well as excellent slipping property, heat conductivity and high refractive index. For instance, it has been used for the tools for cutting, such as cutting tool, end mill and file, metal molds for plastic machining, such as punch and dies, sliding members such as valve lifter and bearing, heat-radiating members such as heat sink, electronic circuit boards and optical parts such as lens and window.
In order for their properties to be exhibited to a sufficient degree, these diamond products must have the diamond-surface polished to assume smooth surface.
The diamond-surface had so far been mechanically polished by using grains or a grind stone of diamond requiring extended periods of time. Besides, since both of them are abraded, there occurred such problems as short life of the tool and not being suited for polishing rugged three-dimensional surfaces. In an effort to improving the above defects, therefore, various kinds of polishing methods have now been proposed.
A patent document 1, for example, proposes a polishing method which conducts the polishing by using a polishing member constituted by a metal that easily reacts with carbon in the diamond crystals, applying ultrasonic waves onto the polishing member, and pushing the polishing member onto the surfaces of the diamond while the polishing member is undergoing ultrasonic oscillation. Here, examples of the metal that easily reacts with carbon include a γ-Fe-containing stainless steel, titanium (Ti), zirconium (Zr) and tantalum (Ta).
A patent document 2 proposes a polishing method by using, as a grind stone, an intermetallic compound of at least one metal element selected from the group consisting of Al, Cr, Mn, Fe, Co and Ni and at least one metal element selected from the group consisting of Zr, Hf, V, Nb, MO, Ta and W, and pushing the grind stone onto the diamond-surface that is moving relative thereto while, as required, heating the grind stone at 100 to 800° C.
A patent document 3 proposes a method of polishing the diamond-surface by focusing the laser beam on the diamond-surface.
A patent document 4 proposes a method of polishing a diamond film by sliding a metal and the diamond relative to each other at a point where the two are contacting to each other while continuously varying the temperature over a range of 700° C. to 1000° C. at the portion where the metal and the diamond are contacting to each other.


The present invention is a passive filter for controlling the return path loss in a communication system having a forward path and return path. The filter comprises first and second terminals, a passive filter network, and a compensation circuit. The passive filter network is coupled to the first and second terminals and to ground. The filter network has a first passband which passes signals in the forward path and a second passband which passes signals in the return path. The filter network includes a passive attenuator network which attenuates signals in the return path by a predetermined amount as the signals pass through the second passband. The compensation circuit is coupled to the passive filter network, and is configured to compensate for expected perturbations in the frequency response of the second passband of the filter network.

1. Technical Field
The present invention relates generally to a multi-band filter used in a multi-channel communication system, such as a two-way CATV cable system. The present invention relates more particularly to a multi-band filter providing a predetermined amount of attenuation in one of the bands of said filter.
2. Background Art
In some multi-channel communication systems, it is desirable to selectively control the loss at several points in at least one of the channels of the system. One example of such a system is a community antenna television (CATV) system, having a two-way communication capability. In such a system, RF television program signals are transmitted from a headend to a subscriber end over a particular frequency band. This band is referred to as the forward (or downstream) path (or channel) of the CATV system. Other signals are transmitted from the subscriber end to the headend, or to some other upstream station. These other signals are transmitted in a different frequency band (higher and/or lower) than the forward path frequency band, and this different band is usually referred to as the return (or upstream) path (or channel) of the CATV system.
Coupled between the headend and subscriber end of the CATV system, there is a system of coaxial and/or optical cables. A typical cable system architecture includes a main trunk cable connected between the headend and a trunk/bridger station. One or more feeder cables feed off of the trunk/bridger station. Each feeder cable contains a number of taps disposed along the length of the feeder cable, and each tap contains a number of ports. A drop cable is connected between each port and a subscriber end. A television receiver is located at the subscriber end, and for a system offering two-way communications, the subscriber end will also have a terminal which transmits signals upstream, in the return path of the cable system.
Cable operating companies are now offering to their subscribers advanced communication services in the return path, including addressable converter operation, Pay Per View transactions, telephony, interactive digital networks, and computer data transmission. In order to offer such services in a reliable manner, certain problems in the return path must be addressed. For instance, many CATV cable systems are designed primarily for forward path operation. The loss (or attenuation) values of each tap are selected to provide proper signal levels at the drop cables, at forward path frequencies. The forward signal at each successive tap port is designed to have the same level at the highest design frequency. This insures a proper forward signal level to each subscriber.
Due to the forward tap design, the loss in the return path varies widely with every tap. This causes a corresponding variance in the signal levels in the return path. This variance in signal level imposes severe design constraints on subscriber terminal transmitters (e.g., set-top addressable converters), and adversely affects the ability of headend receivers to properly detect the return path signals. Significant improvements in the return path performance can be achieved by controlling the loss variance in the return path. If the loss at each tap port can be made substantially uniform, the total variance can be brought down to an acceptable level.
Another problem that must be addressed is interference (or "ingress") entering the return path at the subscriber end. Such interference is caused by radio frequency, electrical and electromagnetic sources, and enters the return path through damaged or insufficiently shielded subscriber drop cable, corroded "F" connectors, and internal subscriber wiring and hardware. As a result of the forward tap design, the taps contributing most to ingress are those having lower attenuation values (i.e., those taps at the distal end of the feeder cables).
An article by Dean A. Stoneback and William F. Beck, entitled "Designing the Return System for Full Digital Services", dated 1995, p. 269-71, (hereinafter "Stoneback" Article"), suggests that by reducing the loss variance in the return path (i.e., equalizing or balancing the return path), ingress can be reduced to a manageable level. Thus, the Stoneback Article suggests that by addressing the loss variance problem, the ingress problem can be satisfactorily resolved in most cases.
A practical and effective approach to balancing the return path loss must satisfy several requirements. First, the devices used to balance the loss must be inexpensive because of the large number of such devices needed to be distributed throughout the CATV cable system. Second, the devices must be small and light weight, because such devices need to be deployed on cables, tap ports, within the taps themselves, inside network interface devices, in on-premise enclosures, pedestals, ground blocks, etc. In many applications, the device should be housed in a small housing containing connectors at each end. Third, it is most desirable to leave unaffected the forward path response when employing the loss balancing devices. The loss chosen for the return path should be independent of the forward path response.
The Stoneback Article suggests two alternative methods of balancing the return path loss. The first is to employ a diplex filter with flat loss in the return band. The second method is to use an equalizer which covers the entire forward and return frequency bands. The diplex filter approach is discouraged by the Stoneback Article, because of the heretofore prevailing view that the device which adds flat loss in the return path is more difficult to manufacture.
Diplex filters have been used for processing both the forward and return paths in a CATV cable system. Examples of such use are disclosed in U.S. Pat. Nos. 5,434,610 to Loveless; 5,425,027 to Baran; 5,130,664 to Pavlic et al.; and 4,963,966 to Harney et al. The patents to Loveless and Pavlic show conventional circuit architectures for diplex filters employing flat loss. Such architectures employ a network of separately connected devices, each of which has a separate housing and associated connectors. Such assembled networks are more susceptible to interference pick-up than a singly packaged network. In addition, such architectures are too large and expensive for the CATV loss balancing application hereinabove described. Furthermore, as mentioned by the Stoneback Article, the flat loss device is more difficult to manufacture than an equalizer approach.
The use of equalization filters, as described in the Stoneback Article, also has drawbacks in the contemplated CATV loss balancing application. The forward path system architecture must be reconfigured, usually with an unfavorable reduction in system dynamic range performance. In addition, the loss chosen for the return path is not independent of the loss established in the forward path. Moreover, wideband (e.g., 5-750 MHz) equalization filters are more difficult to design and match than diplex filters. An example of a CATV system employing an equalizer is disclosed in U.S. Pat. No. 5,379,141 to Thompson et al.


An etching system and method. In the method, layers are etched on a plurality of substrates using a single amount of etchant to form a predetermined pattern on each of the layers, wherein an etching period varies according to an accumulated process number of substrates. The system includes an etching equipment including an etching processor for etching layers on a plurality of substrates using a single amount of etchant to form a predetermined pattern on each of the layers, and a loader for temporarily holding cassettes in which the substrates are stored; and a controller for controlling operations of the etching equipment. The etching equipment changes an etching period according to an accumulated process number of the substrates.

(a) Field of the Invention
The present invention relates to an etching system and a method for fabricating microelectronics devices such as a semiconductor device or a liquid crystal display (LCD). More particularly, the present invention relates to an etching system and a method that varies an etching period according to the accumulated number of microelectronics devices being etched.
(b) Description of the Related Art
Microelectronics devices such as a semiconductor device or an LCD are formed by integrating a plurality of minute patterns. The patterns are formed by a variety of fabrication steps, one of which is an etching process. There are two main types of etching in microelectronics fabrication: wet etching and dry etching. A wet etching method uses liquid etchants while a dry etching method uses plasma.
The conventional wet etching process for an LCD will be described hereinafter.
In the LCD manufacturing process, it is necessary to form metal patterns of gate lines and data lines. These metal patterns are etched using an etchant containing nitric acid (HNO3). A large number of LCDs repeatedly use the same etchant of a certain amount in order to reduce the manufacturing costs. However, the more LCDs are etched (in other words, an xe2x80x9caccumulated process numberxe2x80x9d increases) in the same etchant of a certain amount, the less nitric acid component remains in the etchant, resulting in a lowered etching rate. Thus, if LCDs are etched for the same period of time without considering the accumulated process number of substrates that the etchant fabricated, a critical dimension (CD) of the metal patterns increases as the accumulated process number increases.
FIG. 1 shows a graph illustrating a relation between the accumulated process number and the CD in the conventional process for manufacturing an LCD.
In the conventional process for manufacturing an LCD, LCDs are etched for a predetermined amount of time (at an overetching rate), without considering the accumulated process number. As shown in FIG. 1, in the conventional process for manufacturing LCDs, the CD increase has an almost linear relationship with the increase in the accumulated process number. Accordingly, the conventional LCD manufacturing process requires changing the etchant when the accumulated process number reaches a certain value (CDo), e.g., 300 devices, where the CD also reaches its tolerance point.
As a result, the conventional LCD manufacturing method wastes etchants a lot, thereby increasing the overall manufacturing costs.
The present invention has been made in an effort to solve the above problems.
It is an object of the present invention to provide an etching system and a method for fabricating microelectronic devices that varies the etching period according to the accumulated process number of microelectronic devices that the etching system has handled.
To achieve the above object, the present invention provides an etching system and a method. The method according to the present invention etches the layers on a plurality of substrates using the same etchant of a certain volume to form a pattern on each of the layers, but changes the etching period according to the accumulated process number of substrates.
According to a feature of the present invention, the LCDs are etched at first for a period of T1 until the accumulated process number reaches N substrates, and are etched for a period of T2 when the accumulated process number goes beyond N substrates.
According to another feature of the present invention, the etching period varies for each different accumulated process number.
According to yet another feature of the present invention, substrates are etched using a functional value of a process time with regard to the accumulated process number.
According to still yet another feature of the present invention, optimal etching periods for different accumulated process numbers are obtained through experimental tests, and the optimal etching periods are stored in a memory and used to perform etching.
The etching system includes an etching equipment having an etching processor for etching layers on a plurality of substrates using an etchant to form a predetermined pattern on each of the layers, and a loader for temporarily holding cassettes that store the substrates; and a controller for controlling operations of the etching equipment. The etching equipment changes the etching period according to an accumulated process number of the substrates.
According to a feature of the present invention, the controller transmits to the etching equipment a first operation recipe including a first etching period T1 when the accumulated process number is between 1 and N substrates, and a second operation recipe including a second etching period of T2 when the accumulated process number is N+1 or more substrates; and wherein the etching equipment performs etching according to the first operation recipe and the second operation recipe.
According to another feature of the present invention, the controller receives data corresponding to the accumulated process number from the etching equipment when a cassette is loaded on the loader, and transmits the first operation recipe or the second operation recipe to the etching equipment according to the received data.
According to yet another feature of the present invention, the etching equipment etches substrates using the etching period that varies depending on each different accumulated process number.
According to still yet another feature of the present invention, the etching equipment etches substrates using a functional value of a process time with regard to the accumulated process number, the functional value being stored in a memory, and the etching equipment uses the functional value to perform etching.
According to still yet another feature of the present invention, optimal etching periods for different accumulated process numbers are obtained through tests, and the optimal etching periods are stored in a memory and used for etching by the etching equipment.

Variable time etching system according to the accumulated number of devices being processed and a method for etching in the same manner


A multi-processor system with dynamic power optimization for an integrated circuit and methods thereof are described. An input rate control signal is generated responsive to at least one input data stream. An output rate control signal is generated responsive to an output of the plurality of processors. The input rate control signal and the output rate control signal are monitored. The at least one input data stream is partitioned in response to the input rate control signal. The partitioned data is distributed to at least a portion of the plurality of processors. The plurality of processors is operated in a plurality of modes responsive to the monitoring.

Programmable logic devices ("PLDs") are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array ("FPGA"), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks ("IOBs"), configurable logic blocks ("CLBs"), dedicated random access memory blocks ("BRAMs"), multipliers, digital signal processing blocks ("DSPs"), processors, clock managers, delay lock loops ("DLLs"), and so forth. As used herein, "include" and "including" mean including without limitation.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points ("PIPs"). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more "function blocks" connected together and to input/output ("I/O") resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays ("PLAs") and Programmable Array Logic ("PAL") devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these programmable logic devices ("PLDs"), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms "PLD" and "programmable logic device" include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
As demand for processing data expands, the demand for throughput expands. In order to accommodate an increased throughput, more than one high-speed serial interface may be used, and several serial data streams may be converted to parallel form for parallel data processing. Parallel data processing may be used to address the expanding need for increased bandwidth and throughput.
FPGAs are well positioned for parallel data processing. FPGAs may have multiple processors, such as multiple embedded DSPs, multiple embedded microprocessors, or multiple processors instantiated in field programmable logic gates ("FPGA fabric"), or a combination thereof, along with having multiple high-speed serial interfaces.
While there may be times, such as during high usage intervals, where parallel data processing may be useful, there also may be times when having so many resources committed to parallel data processing may not be as useful due to power utilization.
Accordingly, it would be useful to provide a multi-processor system that dynamically adjusts performance for power reduction.

Multiprocessor system with performance control based on input and output data rates


An applicator for applying a liquid or semi-liquid product to a surface, the applicator being of substantially longitudinal or elongate shape, including a central core defining a structure which is porous so as to allow the applicator to be loaded by capillarity internally; and a covering of flocking arranged all around the central core, at least over part of its length, so as to allow the applicator to be loaded by capillarity externally. The invention also relates to an applicator assembly using an applicator according to the invention.

1. Field of the Invention
The invention relates to a device for applying a liquid or semi-liquid product, such as a cosmetic product, to a surface. By way of example, the invention can be used for applying lipstick, nail varnish, mascara, anti-wrinkle care cream, etc., but can also be used for applying non-cosmetic products, such as adhesive.
2. Discussion of the Background
Conventionally, especially for eyeliners used in the field of cosmetics, the product is applied mainly using two techniques.
In a first technique, the applicator has a felt tip with longitudinal parallel fibers. Such an applicator is described, for applying freckles, in French Patent 2,085,208 and mainly comprises a reservoir made, for example, of plastic, and closed at one of its ends by a leaklight cap. The reservoir contains a felt wick. The end of the reservoir remote from the cap has a conical shape and tightly grips a dispensing tip of which one end is in contact with the wick and the other end is outside the reservoir for applying the product to the surface to be treated.
The drawback of this type of applicator relates mainly to its excessive product retention and also to its lack of gentleness. This is particularly unfortunate for applicators of the eyeliner type. Furthermore, this type of applicator is not well suited to the application of compositions which contain pigments of excessively large size.
According to a second known technique, the product, in the case of an eyeliner, is applied using a pen called a flocked pen. By way of example, such a pen is in the form of an elongate conical applicator tip with a pointed extremity. The tip may be molded from thermoplastic, for example polyurethane. According to this technique the surface of the tip is partially, or even completely, covered with flocking consisting of polyamide, rayon or cotton fibers with a diameter of approximately 70 mm and a length of approximately 1.2 mm.
The latter technique, even though it gives the possibility of applying make-up gently to provide an attractive look, does however have the drawback of lacking autonomy.

Applicator for applying liquid or semi-liquid product, and applicator assembly using such an applicator


An electronic component mounting device according to the invention includes a bonding head for holding and pressure bonding an electronic component to a mounting substrate, a local stage provided with a support surface formed in an area which is almost equal to or slightly larger than that of a mounting surface of the electronic component and serving to support a pressure bonding force from an antimounting surface of the mounting substrate through the support surface, a length measuring mechanism for measuring a distance between the bonding head and the mounting substrate, thereby calculating a virtual plane in a predetermined mounting position on the mounting substrate, and a tilting and moving mechanism for tilting and moving the bonding head and the local stage, thereby causing a normal of the virtual plane in the mounting position to be coincident with an action line of the pressure bonding force, and the pressure bonding is carried out along the normal.

The present invention relates to an electronic component mounting device and a method of manufacturing an electronic device, and more particularly to an electronic component mounting device for sequentially mounting a plurality of electronic components on a mounting substrate and a method of manufacturing an electronic device constituted by mounting the electronic component on the mounting substrate using the electronic component mounting device.
As an example in which an electronic component is mounted on a mounting substrate, there is taken an electronic device for flip-chip connecting a semiconductor chip to a mounting wiring board. The electronic device generally has a structure in which a space portion between the mounting substrate and the electronic component mounted on the mounting substrate is filled with an underfill resin. In an example of an actual manufacturing process, there is employed a method of connecting a plurality of electronic components to a mounting substrate having a large area one by one in a matrix and finally making a division as each electronic device.
In recent years, however, a reduction in a thickness of the mounting substrate has been progressed and a warpage is inevitably generated on the mounting substrate. As will be described below, the warpage might cause a breakdown and breakage of a connecting portion of the mounting substrate and the electronic component. For this reason, a countermeasure has variously been investigated.
FIG. 15 shows an example of a method of mounting an electronic component which has conventionally been executed in order to eliminate the warpage by the applicant. First of all, a mounting substrate 102 having a warpage generated thereon (see FIG. 15A) is decompressed and adsorbed through a batch adsorbing and fixing stage 112 and is thus corrected into a state in which the warpage is not generated. In that state, the mounting substrate 102 is heated to a predetermined temperature through a heater (not shown) provided in the batch adsorbing and fixing stage 112 and an electronic component 103 held on a bonding head (not shown) is subjected to pressure bonding to the mounting substrate 102, thereby carrying out a flip-chip connection (see FIG. 15B). After a plurality of electronic components 103 is sequentially connected in a matrix, the decompression and adsorption of the mounting substrate 102 through the batch adsorbing and fixing stage 112 is released so that the mounting step is completed. At this time, an action for causing the mounting substrate 102 to recover into an original warping state (hereinafter referred to as a "warpage recovery") is generated in an electronic device 110 on which the electronic component 103 is mounted (see FIG. 15C).
On the other hand, an electronic component mounting device 200 described in Patent Document 1 is taken as a conventional example of a mounting device capable of carrying out a flip-chip connection having a small warpage (see FIG. 16). The electronic component mounting device 200 comprises a chip adsorbing block 201 including heating means 202 and a stage 223 including substrate adsorbing means 227 and substrate cooling means 225, and has such a structure that the heating means 202, the substrate adsorbing means 227 and the substrate cooing means 225 are operated at the same time. For the action, a substrate 205 is adsorbed and held on the stage 223 and a flip-chip 203 adsorbed and held on the chip adsorbing block 201 is heated and pressurized onto the substrate 205 through a plunger 204, and at the same time, the substrate 205 is forcibly cooled from the stage 223 side.
[Patent Document 1] JP-A-2004-47670
In the case in which the mounting substrates are decompressed and adsorbed in a batch as described above, however, a recovery of a deformation of the substrate, that is, a warpage recovery is generated in the release of the decompression and adsorption. Therefore, a breakdown and breakage of a flip-chip connecting portion, for example, a crack 111 in FIG. 15C might be caused, for example.
Moreover, the electronic device is moved and delivered between a flip-chip connecting step and an underfill resin filling step as a normal manufacturing process. Also in the meantime, a drop in a temperature and a deformation of the mounting substrate therewith might be generated, and therefore, there has also been an obvious problem in that the breakdown and breakage of the connecting portion is caused thereby.
In a process for mounting an electronic component which is carried out by heating a whole mounting substrate according to the conventional art, furthermore, the mounting substrate has a high temperature. In the case in which an underfill resin is filled at the same time, therefore, there is a problem such as a filling failure caused by curing the underfill resin.

Using a simultaneously tilting and moving bonding apparatus


Radio frequency (RF) front end circuitry includes first RF multiplexer circuitry and second RF multiplexer circuitry. The first RF multiplexer circuitry is a quadplexer, while the second RF multiplexer is a triplexer. The RF front end circuitry is configured to support the transmission and reception of signals within a first operating band, a second operating band, and a third operating band. Further, the RF front end circuitry is configured to support carrier aggregation configurations between the first operating band and the third operating band and the second operating band and the third operating band.

FIG. 1 shows a table describing a number of wireless communications operating bands in the wireless spectrum. One or more of the operating bands may be used, for example, in a Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Long Term Evolution (LTE), or LTE-advanced equipped wireless communications device. The first column indicates the operating band number for each one of the operating bands. The second and third columns indicate the uplink and downlink frequency bands for each one of the operating bands, respectively. Finally, the fourth column indicates the duplex mode of each one of the operating bands. In non-carrier aggregation configurations, a wireless communications device will generally communicate using a single portion of the uplink or downlink frequency bands within a single operating band. In carrier aggregation applications, however, a wireless communications device may aggregate bandwidth across a single operating band or multiple operating bands in order to increase the data rate of the device.
FIG. 2A shows a diagram representing a conventional, non-carrier aggregation configuration for a wireless communications device. In this conventional configuration, a wireless communications device communicates using a single portion of the wireless spectrum 10 within a single operating band 12. Under the conventional approach, the data rate of the wireless communications device is constrained by the limited available bandwidth.
FIGS. 2B-2D show diagrams representing a variety of carrier aggregation configurations for a wireless communications device. FIG. 2B shows an example of contiguous intra-band carrier aggregation, in which the aggregated portions of the wireless spectrum 14A and 14B are located directly adjacent to one another and are in the same operating band 16. FIG. 2C shows an example of non-contiguous intra-band carrier aggregation, in which the aggregated portions of the wireless spectrum 18A and 18B are located within the same operating band 20, but are not directly adjacent to one another. Finally, FIG. 2D shows an example of inter-band carrier aggregation, in which the aggregated portions of the wireless spectrum 22A and 22B are located in different operating bands 24 and 26. A modern wireless communications device should be capable of supporting each one of the previously described carrier aggregation configurations.
The various carrier aggregation configurations discussed above can be performed between two or more frequency division duplexing (FDD) bands, two or more time division duplexing (TDD) bands, or a combination thereof. Generally, a wireless communications device will aggregate bandwidth when receiving data (i.e., during downlink), but will use a single operating band when transmitting data (i.e., during uplink). However, carrier aggregation may also be used during data transfer to increase uplink throughput.
FIG. 3 shows a schematic representation of conventional radio frequency (RF) front end circuitry 28 configured to support at least one carrier aggregation configuration. The conventional RF front end circuitry 28 includes a first antenna 30A, a second antenna 30B, antenna switching circuitry 32 coupled to the first antenna 30A and the second antenna 30B, RF filtering circuitry 34 coupled between the antenna switching circuitry 32 and a number of input/output nodes 36 (shown individually as 36A through 36H), and transceiver circuitry 38 coupled to the input/output nodes 36. The RF filtering circuitry 34 includes first RF multiplexer circuitry 40A, second RF multiplexer circuitry 40B, and third RF multiplexer circuitry 40C. The first RF multiplexer circuitry 40A is a quadplexer, while the second RF multiplexer circuitry 40B and the third RF multiplexer circuitry 40C are duplexers. Details of the first RF multiplexer circuitry 40A, the second RF multiplexer circuitry 40B, and the third RF multiplexer circuitry 40C are shown in FIGS. 4A through 4C.
FIG. 4A shows a block diagram of the first RF multiplexer circuitry 40A. The first RF multiplexer circuitry 40A includes a first filter 42A coupled between a first common node 44 and a first one of the input/output nodes 36A, a second filter 42B coupled between the first common node 44 and a second one of the input/output nodes 36B, a third filter 42C coupled between the first common node 44 and a third one of the input/output nodes 36C, and a fourth filter 42D coupled between the first common node 44 and a fourth one of the input/output nodes 36D.
FIG. 4B shows a block diagram of the second RF multiplexer circuitry 40B. The second RF multiplexer circuitry 40B includes a fifth filter 42E coupled between a second common node 46 and a fifth one of the input/output nodes 36E and a sixth filter 42F coupled between the second common node 46 and a sixth one of the input/output nodes 36F.
FIG. 4C shows a block diagram of the third RF multiplexer circuitry 40C. The third RF multiplexer circuitry 40C includes a seventh filter 42G coupled between a third common node 48 and a seventh one of the input/output nodes 36G and an eighth filter 42H coupled between the third common node 48 and an eighth one of the input/output nodes 36H.
The RF filtering circuitry 34 is configured to selectively pass RF transmit signals and RF receive signals within a first operating band (band A), a second operating band (band B), and a third operating band (band C) between the antenna switching circuitry 32 and the transceiver circuitry 38. As discussed below, the RF filtering circuitry 34 facilitates at least one carrier aggregation configuration in the conventional RF front end circuitry 28.
A filter response of the first filter 42A includes a pass band configured to pass RF transmit signals within the first operating band (band A) provided at the first one of the input/output nodes 36A to the first common node 44 while attenuating other signals. A filter response of the second filter 42B includes a pass band configured to pass RF receive signals within the first operating band (band A) received at the first common node 44 to the second one of the input/output nodes 36B while attenuating other signals. A filter response of the third filter 42C includes a pass band configured to pass RF transmit signals within the third operating band (band C) between the third one of the input/output nodes 36C and the first common node 44, while attenuating other signals. A filter response of the fourth filter 42D includes a pass band configured to pass RF receive signals within the third operating band (band C) between the first common node 44 and the fourth one of the input/output nodes 36D, while attenuating other signals. A filter response of the fifth filter 42E includes a pass band configured to pass RF transmit signals within the second operating band (band B) between the fifth one of the input/output nodes 36E and the second common node 46, while attenuating other signals. A filter response of the sixth filter 42F includes a pass band configured to pass RF receive signals within the second operating band (band B) between the second common node 46 and the sixth one of the input/output nodes 36F, while attenuating other signals. A filter response of the seventh filter 42G includes a pass band configured to pass RF receive signals within the first operating band (band A) and RF receive signals within the second operating band (band B) between the third common node 48 and the seventh one of the input/output nodes 36F, while attenuating other signals. A filter response of the eighth filter 42H includes a pass band configured to pass RF receive signals within the third operating band (band C) between the third common node 48 and the eighth one of the input/output nodes 36G, while attenuating other signals.
The conventional RF front end circuitry 28 is capable of operating in a standard (i.e., non-carrier aggregation) mode in any one of the first operating band (band A), the second operating band (band B), and the third operating band (band C). To operate in a standard mode in the first operating band (band A), the antenna switching circuitry 32 couples the first RF multiplexer circuitry 40A to the first antenna 30A and the third RF multiplexer circuitry 40C to the second antenna 30B. The transceiver circuitry 38 provides an RF transmit signal within the first operating band (band A) to the first one of the input/output nodes 36A, where it is passed by the first filter 42A to the first common node 44, and, subsequently, to the first antenna 30A via the antenna switching circuitry 32. RF receive signals within the first operating band (band A) received at the first antenna 30A are passed to the first common node 44 via the antenna switching circuitry 32, where they are then passed by the second filter 42B to the second one of the input/output nodes 36B and processed by the transceiver circuitry 38. RF receive signals within the first operating band (band A) received at the second antenna 30B are passed to the third common node 48 via the antenna switching circuitry 32, where they are then passed by the seventh filter 42G to the seventh one of the input/output nodes 36F and processed by the transceiver circuitry 38. The RF receive signals provided to the third RF multiplexer circuitry 40C are generally used as multiple-input-multiple-output (MIMO) diversity receive signals to improve the quality of reception of the conventional RF front end circuitry 28. The antenna switching circuitry 32 may switch the first antenna 30A and the second antenna 30B as desired to improve transmit and/or receive reception from the conventional RF front end circuitry 28.
Without changing the connections made by the antenna switching circuitry 32, the conventional RF front end circuitry 28 may also operate in a standard mode in the third operating band (band C). In such an operating mode, the transceiver circuitry 38 provides an RF transmit signal within the third operating band (band C) to the third one of the input/output nodes 36C, where it is passed by the third filter 42C to the first common node 44, and, subsequently, to the first antenna 30A via the antenna switching circuitry 32. RF receive signals within the third operating band (band C) received at the first antenna 30A are passed to the first common node 44 via the antenna switching circuitry 32, where they are then passed by the fourth filter 42D to the fourth one of the input/output nodes 36D and processed by the transceiver circuitry 38. RF receive signals within the third operating band (band C) received at the second antenna 30B are passed to the third common node 48 via the antenna switching circuitry 32, where they are then passed by the eighth filter 42H to the eighth one of the input/output nodes 36H and processed by the transceiver circuitry 38. The RF receive signals provided to the third RF multiplexer circuitry 40C are generally used as MIMO diversity receive signals to improve the quality of reception of the conventional RF front end circuitry 28. The antenna switching circuitry 32 may switch the first antenna 30A and the second antenna 30B as desired to improve transmit and/or receive reception from the conventional RF front end circuitry 28.
To operate in a standard mode in the second operating band (band B), the antenna switching circuitry 32 couples the second RF multiplexer circuitry 40B to the first antenna 30A and the third RF multiplexer circuitry 40C to the second antenna 30B. The transceiver circuitry 38 provides an RF transmit signal within the second operating band (band B) to the fifth one of the input/output nodes 36E, where it is passed by the fifth filter 42E to the second common node 46, and, subsequently, to the first antenna 30A via the antenna switching circuitry 32. RF receive signals within the second operating band (band B) received at the first antenna 30A are passed to the second common node 46 via the antenna switching circuitry 32, where they are then passed by the sixth filter 42F to the sixth one of the input/output nodes 36F and processed by the transceiver circuitry 38. RF receive signals within the second operating band (band B) received at the second antenna 30B are passed to the third common node 48 via the antenna switching circuitry 32, where they are then passed by the seventh filter 42G to the seventh one of the input/output nodes 36G and processed by the transceiver circuitry 38. The RF receive signals provided to the third RF multiplexer circuitry 40C are generally used as MIMO diversity receive signals to improve the quality of reception of the conventional RF front end circuitry 28. The antenna switching circuitry 32 may switch the first antenna 30A and the second antenna 30B as desired to improve transmit and/or receive reception from the conventional RF front end circuitry 28.
To operate in a carrier aggregation mode of operation using the first operating band (band A) and the third operating band (band C), the antenna switching circuitry 32 couples the first RF multiplexer circuitry 40A to the first antenna 30A and the third RF multiplexer circuitry 40C to the second antenna 30B. The transceiver circuitry 38 then provides an RF transmit signal within one of the first operating band (band A) and the third operating band (band C) to either the first one of the input/output nodes 36A or the third one of the input/output nodes 36C, respectively. RF receive signals within the first operating band (band A) and the third operating band (band C) are passed to the first common node 44 via the antenna switching circuitry 32, where they are then respectively passed by the second filter 42B and the fourth filter 42D to the second one of the input/output nodes 36B and the third one of the input/output nodes 36C and processed by the transceiver circuitry 38. RF receive signals within the first operating band (band A) and the third operating band (band C) are passed to the third common node 48 via the antenna switching circuitry 32, where they are then respectively passed by the seventh filter 42G and the eighth filter 42H to the seventh one of the input/output nodes 36G and the eighth one of the input/output nodes 36H. Accordingly, the conventional RF front end circuitry can transmit a signal in the first operating band or the second operating band while simultaneously receiving signals within both operating bands. The RF receive signals provided to the third RF multiplexer circuitry 40C are generally used as MIMO diversity receive signals to improve the quality of reception of the conventional RF front end circuitry 28. The antenna switching circuitry 32 may switch the first antenna 30A and the second antenna 30B as desired to improve transmit and/or receive reception from the conventional RF front end circuitry 28.
While the conventional RF front end circuitry 28 can be used in carrier aggregation configurations between the first operating band (band A) and the third operating band (band C), the structure of the RF filtering circuitry 34 does not allow for the aggregation of bandwidth between the second operating band (band B) and the third operating band (band C). As discussed above, it is desirable for RF front end circuitry to support as many carrier aggregation configurations as possible for maximum flexibility. Further, the conventional RF front end circuitry 28 requires eight filters. In general, it is desirable to minimize the number of filters used to support these carrier aggregation configurations in order to minimize the space consumed by the RF front end circuitry and the complexity thereof.
In light of the above, there is a need for RF front end circuitry with support for additional carrier aggregation configurations and less filters.

Radio frequency front end circuitry for carrier aggregation


Systems, methods, and computer program products are provided for performing an authorization check for a user. In one implementation, a data processing system is provided that includes means for storing first data descriptive of at least one directed acyclic graph and for storing second data descriptive of an assignment of a user to a first node of the graph. The data processing system also includes means for receiving an access request of the user, the access request specifying a second node of the graph. Furthermore, the data processing system includes means for determining a least common ancestor of the first and second nodes of the graph and means for performing an authorization check adapted to grant authorization for the access request if the least common ancestor of the first and second nodes is the first node.

A user's right to read and write specific data objects stored in a data processing system may be specified in his or her user profile. Manual maintenance of such user profiles is a tedious and error prone task. For example, if an organizational structure of a company changes, the respective user authorizations also need to be changed. This may require a manual update of a large number of user profiles that are afflicted by the organizational change.
Structural user authorization is a concept that aims to reduce this drawback. For example, SAP's authorization system as implemented in SAP R/3 (commercially available from SAP AG, Walldorf, Germany) has a structural authorization concept, as described in SAP Authorization System—Design and Implementation of Authorization concepts for SAP R/3 and SAP Enterprise Portals, IBM Business Consulting GmbH, SAP Press (see Chapter 2.3.5, page 52).

Systems and methods for performing authorization


A vehicle remote control key system and a method of processing a signal in the system are provided. The system includes a remote control key that is configured to send out a radio frequency (RF) signal that includes an identification (ID) and operation information to remotely control a target vehicle based on a remote control key operation. In addition, a controller is configured to determine whether the ID of the received RF signal is available and perform the remote control when the ID is available and the controller retransmits the RF signal to a vehicle in the vicinity of the target vehicle when the ID is unavailable and increases a count bit, which stores the number or times of retransmission in a frame, by one when retransmitting the RF signal.

(a) Field of the Invention
The present invention relates to a vehicle remote control key system and a signal processing method thereof.
(b) Description of the Related Art
In general, automotive remove control key systems are used to lock and unlock the vehicle doors with a remote control key or used to support an automotive remote control function such as remote start. In the existing automotive remote control key systems, when a user operates the remote control keys, the keys send out a radio frequency (RF) signal of 433 MHz and vehicles within the range that the RF (radio frequency) signal reaches change from a sleep mode to a wake-up mode with a substantially low current to determine whether the received RF signal is an available signal.
FIG. 1 schematically illustrates an exemplary structure of an RF frame from an existing remote control key. Referring to FIG. 1, when an RF receiver of a vehicle receives an RF signal, the ECU (Electronic Control Unit) that controls the vehicle does not wake up, and the RF module wakes up for a short period of time and determines availability of the identification (ID) by checking the received RF frame. When the ID is not an available signal, the RF receiver goes back into the sleep mode with a low current to reduce a dark current. When ID is an available signal, the RF receiver is configured to detect the operation function (Function) and perform the corresponding instruction.
However, since the existing remote control keys are required to have a lifespan of at least two or more years with substantially small batteries, they are limited in output of RF signals. In other words, since the RF signals from remote control keys usually reach about 30 m on the average, when a vehicle is out of the range, an RF signal fails to reach the vehicle and the vehicle may not be remotely operated. Further, when a vehicle is parked in a wide parking lot or many obstacles are present in the vicinity of the vehicle, the transmission distance of RF signals reduces, and the vehicle may not be remotely controlled.
The above information disclosed in this section is merely for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.

Vehicle remote control key system and signal processing method


A provisioning system receives network element information from a wireless communication network that characterizes a virtual network element. The provisioning system determines that the virtual network element is active and that a provisioning data link is not operational between the virtual network element and the provisioning system. The provisioning system determines a network address for the virtual network element. The provisioning system exchanges network signaling with the virtual network element using the network address to establish the provisioning data link. The provisioning system transfers provisioning data to the virtual network element over the provisioning data link.

Wireless user devices exchange wireless signals with wireless communication networks for data services like voice-calling, internet-access, and machine communications. The wireless communication networks have wireless access points that exchange the wireless signals with the wireless user devices. The wireless access points exchange corresponding user data and network signaling with network elements like packet routers and network controllers. The network elements process the user data and network signaling to deliver the data services to the wireless user devices. Popular wireless communication networks comprise Long Term Evolution (LTE) and Fifth Generation New Radio (5GNR).
In the past, each network element was typically a computer with wireless networking software. For example, an older packet router might comprise a single computer having data transceivers, memory, and microprocessors that host an operating system and a routing applications. New network elements have been virtualized. A virtual network element typically comprises a networking application, guest operating system, and virtual machine. A computer that executes virtual network elements still comprises data transceivers, memory, and microprocessors. To serve the virtual network element, the data transceivers, memory, and microprocessors host another operating system and virtual switches.
The virtual switches hosted by the computer communicate with the virtual machines in the virtual network elements. Thus, a multitude of virtual network elements may share the data transceivers, memory, and microprocessors, and operating system over the virtual machines and virtual switches. Network virtualization adds both reliability and efficiency since the networking software is not physically tied to a dedicated set of data transceivers, memory, and microprocessors.
To improve efficiency, the wireless communication networks have network controllers that continuously start and stop the virtual network elements as user demand changes. To improve reliability, the virtual switches and machines allow data transceivers, memory, and microprocessors to be replaced without disrupting the operation of the virtual network elements. A popular form of network virtualization is Network Function Virtualization (NFV). NFV features NFV Infrastructures (NFVIs) that host Virtual Network Functions (VNFs). The VNFs exchange user data and network signaling with the wireless access points to deliver the data services. NFV also has NFV Management and Orchestration (MANO) control to start and stop the VNFs.
The wireless communication networks also have provisioning systems to configure their virtual network elements. For example, a provisioning system may update the routing data in a packet router or load a new control software in a network controller. The provisioning systems establish provisioning links to the virtual network elements when it is time to perform the provisioning and tear down the provisioning links when the provisioning is complete. Unfortunately, the provisioning systems in the wireless communication networks do not efficiently and effectively provision their virtual network elements.


There is provided a lightweight plaster board having a cellular porous plaster core, excellent in adhesion to a covering base paper for a plaster board, free from dry-out in side edge parts of the plaster board, and with no disadvantage in workability for driving a nail into the plaster board. The plaster board includes a plaster core having a front surface, a back surface, and four side surfaces, and at least one covering base paper that covers the front surface, the back surface, and the at least two opposite side surfaces of the plaster core. The plaster core includes one or more hard edge parts each including one of the side surfaces covered with the covering base paper, one or more high-density parts including the front surface or the back surface, not including the side surface covered with the covering base paper, and having a density substantially equal to the density of the hard edge part, and a low-density part having a density less than the densities of the hard edge part and the high-density part and contacting with the hard edge part and the high-density part. The hard edge part does not include a position in which a nail is driven.

Plaster board has been widely used as a building material for the interior from the viewpoints of fire resistance, sound insulation, workability, and economy. The "plaster board" is a board-shaped body in which a plaster-based core (plaster core) is covered with a base paper for plaster board (simply, referred to as a base paper below). Generally, a plaster board is fabricated by the following steps (1)-(5).
(1) A calcined plaster, an adhesion assistant, a set accelerator, foam, and other additives, and water, etc., are kneaded by a mixer so as to obtain a calcined plaster slurry (simply, referred to as a slurry below).
(2) While the plaster slurry is provided onto a lower-side (front surface-side) base paper (a front surface covering base paper) that is supported and moves on a long moving belt, opposite parts of the front surface covering base paper are folded so that margins of those parts reach to a back-surface side of the plaster board.
(3) At the back-surface side of the plaster board, margins of another upper-side base paper (a back surface covering base paper) are overlapped with the margins of the folded parts of the front surface covering base paper, wherein paste is applied on the margins of the back surface covering base paper.
(4) The slurry spread by and covered with the front surface covering base paper and the back surface covering base paper through a molding machine is molded into a board shape through the molding machine.
(5) After the slurry is hardened, the hardened plaster board is roughly cut, subjected to forced-drying, and cut into a product size.
As a representative base paper for plaster board, a front surface covering base paper located on one surface of a plaster core and a back surface covering base paper located on the opposite surface of the plaster core are provided. The front surface covering paper covers opposite side-surfaces of the plaster core and the margins of the front surface covering base paper are pasted with the margins of the back surface covering base paper.
In order to save on the weight of the core, conventionally a cellular porous plaster core has been fabricated by introducing foam into a plaster core. For example, the cellular porous plaster core has been fabricated by adding a foaming agent into plaster slurry.
However, a core formed from only foamed plaster has two disadvantages. First, the hardened cellular porous plaster core is comparably fragile, and the cellular porous core is easy to crack and break as a nail is driven into the cellular porous plaster core under construction. The term of "nail" used herein means a component for holding a plaster board on a member, including not only a nail used for fixing the plaster board to a wooden substrate under construction of a building but also a machine screw (or a screw thread) used for fixing the plaster board to a metallic substrate (stud). Second, the cellular porous plaster core does not necessarily adhere to the base paper.
Regarding such problems, Japanese Laid-Open Patent Application No. 4-505601 discloses a plaster board characterized in that a single foamed slurry containing a comparably "easier broken foam" than foam in the conventional foamed slurry is deposited on a base paper and dried, an interface area containing fibers originating from the base paper and plaster originating a plaster core between the base paper and a surface of the plaster core and a layer containing no fiber adjacent and approximately parallel to the interface area are included, which layer includes plaster having fewer voids and greater density than in the central parts of the plaster core, which central part of the plaster core includes a multi-layer core having a plurality of discontinuous voids equal to or less than 1705 per square centimeter and approximately uniformly distributed throughout.
According to the conventional technique, a "separation" defect such that the paper on one surface of the plaster board is easily peeled from the plaster board can be significantly improved by a thin layer proximate to this paper and containing no fiber of the paper, and the strength of the plaster board can be significantly reduced by forming voids fewer and larger than the conventional voids in the hardened plaster board.
Additionally, in order to improve the adhesive property between the plaster core and the base paper, for example, Great Britain Patent No. 741140 discloses the technique of molding a plaster board by applying high-density slurry containing no foam on the adhesion surface of the base paper uniformly and thinly by a roller and providing low-density slurry containing foam onto the high-density slurry and then covering the low-density slurry with the base paper or providing another base paper on the surface of which the high density slurry containing no foam is applied uniformly and thinly by a roller.
Furthermore, Japanese Laid-Open Patent Application No. 5-148001 discloses a technique of molding a plaster board by providing high-density slurry containing an adhesive between a spreader roll and an idler roller, transferring slurry that adheres to the surface of the spread roller to the adhesive surface of the base paper so as to provide a thin plaster stratum on the adhesive surface, and providing low-density slurry containing foam onto the plaster stratum.
Next, drying of the plaster board is given as a large factor on fabrication in regard to adhesion of the plaster board. That is, in regard to the plaster board in a forced-drying process, generally, a drying rate in regard to a side edge part or side edge part area of the plaster board is comparably faster than a drying rate in regard to a central part of the plaster board. For this reason, in the side edge part or side edge part area, the degradation in the strength and the failure of adhesion (that is, dry-out) due to excessive drying easily occurs.
As a method of preventing the dry-out, for example, U.S. Pat. No. 2,762,738 discloses a technique of preventing the dry-out by providing high-density slurry from sub-mixers provided above both margins of the front surface covering base paper respectively onto the side edge portions of the slurry provided from a main mixer on the front surface covering base paper so as to form a plaster board, and making the core density at both side edge parts of the plaster board be larger than the density in the central part.
Similarly, Japanese Laid-Open Patent Application No. 9-511702 discloses an apparatus for forming a coating and side edge portions of a comparably high-density plaster slurry on a covering base paper by means of a coating roller rotating opposite to the moving direction of the covering base paper, and then forming a core including comparably low-density plaster between the side edge portions on the coating.
The length of the coating roller in the axial directions is smaller than the width of the covering base paper. Accordingly, the covering base paper with a normal width extends over the ends of the coating roller, and some slurry leaks out near both ends of the coating roller on the margins or the outside of the covering base paper. The base paper with a coating film is transferred on a deck along a transportation route of the base paper and an additional high-density slurry is poured onto the margins of the covering paper so as to form a rigid edge (hard edge) part. The apparatus for forming a core is provided with means for providing comparably low-density plaster slurry between the side edge portions on the coating.
However, in regard to a plaster board including a multi-layer core formed from a single foamed slurry disclosed in Japanese Laid-Open Patent Application No. 4-505601, plaster is hardly ever or never stuck to the base paper due to density deficiency and the dry-out phenomenon in the side edge parts of the plaster board in formation of the plaster board and subsequent forced-drying, so that the defect of no base paper remaining on the plaster panel may occur. In order to reduce such a dry-out phenomenon, for example, as disclosed in Japanese Laid-Open Patent Application 11-501002, there is a method of preparing another high-density slurry and providing it onto the side edge parts of the plaster board so as to mold the plaster board. In this case, the area of the hard edge part originating from the high-density slurry becomes too large. Accordingly, when a nail is driven into the plaster board under construction, workability and/or subsequent finishing may be provided with such a disadvantage that the nail cannot sufficiently enter into the plaster board or the nail can enter but the head of the nail projects, at a nailing position along the side edge parts of the plaster board in the longitudinal directions.
In the conventional techniques disclosed in Great Britain Patent No. 741140 and Japanese Laid-Open Patent Application No. 5-148001, a plaster containing no foam may be too hard to practically function as an optimal material for a plaster board. Also, in a roll coater used in the fabrication method of these plaster boards, since the rotational direction of a spreader roll is the same as the transportation direction of a base paper, a slurry spread by the roller tends to adhere to the roller surface due to the tackiness of the slurry. As the result, the thickness of a thinly applied slurry layer is not constant along the transportation direction of the base paper. Furthermore, since the slurry adhering to the surface of the spreader roll is a reaction hardening type, in which calcined plaster as the main component contacts with water to harden, the slurry is hardening in progression and the gap between a spreader roll and an idler roller becomes narrower, during the rotation of the spreader roll. Consequently, the amount of the slurry provided onto the surface of the spreader roll and transported is reduced, so that the thickness of a thinly applied slurry layer varies with time so as to be not constant. On the other hand, after application of the slurry, even if a lump removing plate is provided across the entire roller along the longitudinal directions in order to remove a residual slurry on the roller surface, the removed slurry falls on the surface of a thinly applied slurry layer from the lump removing plate and consequently it is difficult to provide a slurry layer with a uniform thickness. Moreover, as slurry adhering to the side surface of the roller, etc., hardens and grows so as to make contact with a base paper, slurry causes cutting of the paper etc. As a result, such a problem that the production line has to be stopped persists.
Also, in the conventional technique disclosed in U.S. Pat. No. 2,762,738, since low-density and high-density slurries are separately prepared by a main mixer and a sub-mixer so as to be provided onto the central part and the margin of a base paper, respectively, fabrication processes and process management for the plaster board are cumbersome and complex, and the size of a hard edge part of the fabricated plaster board is not sufficiently controlled.
Similarly, in the conventional techniques disclosed in Great Britain Patent No. 74110 and Japanese Laid-Open Patent Application No. 5-148001, since two slurry mixers for preparing coating slurries for two base papers are used in addition to a main mixer, a configuration is required in which the controls of the mixers are difficult. Additionally, combining a plaster core and a base paper is disclosed by sticking a dense gypsum plaster slurry, particularly slurry containing a binder such as starch, etc. in the latter patent application, to the base paper by an applicator roller. However, there is no description for problems in regard to the dry-out and hard edge.
Additionally, the slurry in the main mixer used in the apparatus in Japanese Laid-Open Patent Application No. 9-511702 contains plaster, water, a forming agent, and a stabilizer, etc. and has a composition for forming the comparably low-density plaster slurry. Also, almost all of the air bubble contained in the slurry poured into the roller coating are removed by providing the foamed slurry from the main mixer through a pipe line to a high-speed beater and stirring the slurry by using a rapidly rotating wing of the high-speed beater. Thus, the slurry provided onto the roll coater or the margin of the covering base paper is a comparably high-density slurry. Accordingly, first in order to form a single foamed slurry, since the calcined plaster slurry and the foam are considerably stirred in the mixer, this conventional technique causes the problems of loss of the foam and ununiformity in the size of the air bubbles and the voids. Also, since defoaming capability of the high-speed beater has a limitation, it is difficult to provide the desired high-density slurry continuously and stably. Moreover, foam removed from the slurry provided onto the roll coater is wasted and the foaming agent and labor spent for forming foam are also wasted. Additionally, since the additional high-density slurry (hard edge slurry) is provided onto the margins of a cover sheet (base paper) provided with a slurry coating by the spreader roll through the pipe line, such problems that it is difficult to control the size of the hard edge part and it is difficult to drive a nail into the plaster board easily occur.


An input/output device comprises a bonding pad, a signal transport circuit, and a blocking unit. The signal transport circuit has a first terminal connected to the bonding pad and a second terminal connected to a core circuit of an IC product. The signal transport circuit is capable of transporting a signal either from the bonding pad to the core circuit or from the core circuit to the bonding pad. The blocking unit has a control terminal and is coupled between the bonding pad and the signal transport circuit. The control terminal is coupled to receive an enable signal. The blocking unit ties the bonding pad to a predetermined voltage level when the enable signal is de-asserted, thereby blocking the signal transport provided by the signal transport circuit. The blocking unit unties the bonding pad from the predetermined voltage level when the enable signal is asserted.

1. Field of the Invention
The invention relates to input/output devices in an integrated circuit (IC) product and more particularly to input/output devices capable of blocking external interference signals from other input/output devices.
2. Description of the Related Art
As mobile communication has become increasingly popular, radio frequency (RF) technology has progressed and various wireless protocols, such as Bluetooth, 802.11a/b/g, GSM, TDMA, have been introduced. Some wireless protocols transmit and receive signals simultaneously, while others, such as TDMA, require that signals be transmitted and received in turns or utilizing different time slots.
For protocols requiring separate of transmission and reception, a transmitter in an RF IC is turned on while a receiver in the same RF IC is turned off, and vice versa. Ideally the transmitter and receiver operate independently and do not interfere with each other. The board on which the RF IC is mounted, however, provides a signal path that causes an unwanted feedback signal from a receiver to a transmitter, thus, output signal quality suffers during signal transmission.
FIG. 1 illustrates the origin of the feedback signal during signal transmission. In a transmission mode, transmitter 12 on an RF IC amplifies an internal signal to generate output signal 20 for radiation by antenna 16 on a board. The board typically comprises metal straps, vias and the like for constructing signal paths to convey signals. Although the signal path for output signal 20 may not be directly shorted by a signal path for a receiver in a receiving mode, the conductors on the board inevitably form parasitic capacitors that provide leakage paths for signals, particularly for high power signals. For example, parasitic capacitor 18 in FIG. 1 provides a leakage path for output signal 20, such that leakage signal 22, which is part of the output signal 20, jumps to conductor 19 on the board and heads to the input of receiver 14 in the same RF IC. Leakage signal 22 may be transferred by receiver 14 to feedback signal 10 and sent to transmitter 12 finally deteriorating output signal 20. That kind of leakage signal 22 or feedback signal 10 should be removed or minimized, if possible.

Input/output device capable of blocking external interference signals