Described herein is a method employing acoustic data from a patient's abdominal cavity to predict potential onset of postoperative ileus (POI) in patients recovering from surgery. According to one embodiment of the method, the rate of intestinal motility events, as well as the change in the rate across specific time periods, is analyzed to predict, or rule out, potential onset of POI. The current risk assessment may then be reported, and used to determine a course of treatment, such as rapidly advancing diet in low risk patients according to enhanced recovery after surgery protocols. The method can be applied at the patient's bedside by a nurse or other medical provider, and used to determine the POI risk assessment for the patient.

All publications herein are incorporated by reference to the same extent as if each individual publication or patent application was specifically and individually indicated to be incorporated by reference. The following description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
Bowel paralysis is a prevalent and expensive condition following a wide range of surgeries, particularly those involving the abdominal cavity.1-3 When prolonged or complicated, postoperative ileus (POI) can worsen patient outcomes, increase cost of care, and lengthen the hospital stay.4,5 Delayed oral feeding can lead to poor wound healing, increased infection, or need for parenteral nutrition.1 Because of the high prevalence and impact of POI, the condition costs over $1.75 billion annually in the U.S.4,5
Use of Enhanced Recovery After Surgery (ERAS) protocols have led to measurable improvements in outcomes following abdominal surgery.6-9 These protocols expedite postoperative feeding so patients can eat quickly and be discharged rapidly. Although ERAS protocols are generally safe and reduce length of stay, between 4 and 25% of patients cannot tolerate feeding and require nasogastric tube decompression or bowel rest.10-14 When this occurs it can lead to patient complications, increased hospital stay, increased costs, and even death.
Monitoring for development of POI is generally imprecise and subjective. Clinical assessments rely on observation, intermittent physical examination, assessments for flatus (e.g. "passing gas") or stool passage, and use of a stethoscope to monitor bowel sounds. If needed, clinicians may obtain an abdominal X-Ray or CT scan to look for signs of POI, such as distended intestines, but these methods are expensive, time consuming, and resource intensive. Additionally, it requires the patient to be exposed to radiation, and specialized technicians are required to review the findings.
Thus, there is an unmet need for an objective marker that could predict which patients are at risk of developing POI and which patients will uneventfully recover GI function. Such a capability could help medical staff expedite recovery for low risk patients, yet delay feeding or make other adjustments to treatment for those patients likely to experience complications.

Methods for prediction of postoperative ileus (POI)


A composition includes a polymer including extending chains, side chains, or branches. One (or more) of a plurality of a first strand of nucleic acid is attached to each of a plurality of the side chains. One (or more) of a plurality of a second strand of nucleic acid, which is complementary to the first strand of nucleic acid, is complexed to each of the plurality of the first strand of nucleic acid to form a double strand of nucleic acid on each of the plurality of the side chains. At least one fluorescent compound is associated with the double strand of nucleic acid on each of the plurality of the side chains.

The following information is provided to assist the reader in understanding technologies disclosed below and the environment in which such technologies may typically be used. The terms used herein are not intended to be limited to any particular narrow interpretation unless clearly stated otherwise in this document. References set forth herein may facilitate understanding of the technologies or the background thereof. The disclosure of all references cited herein are incorporated by reference.
Virtually every imaginable aspect of biological systems has succumbed to labeling through fluorescent probes that have been developed over the years. Fluorescent dyes coupled to affinity binders such as antibodies are common reporters in fluorescence microscopy, flow cytometry and microplate assays as well as in protein and nucleic acid blots. Despite the advent of competing approaches such as recombinant peptide tagging and mass spectrometry, antibody based detection remains the most broadly applicable means of localizing and quantitating specific components in a complex sample. Labeled secondary antibodies make stable and specific complexes with unlabeled primary antibodies, providing the foundation for most immunofluorescence protocols.
The number of target molecules per surface area or volume unit is a key variable in biological detection applications. To detect functionally important proteins with a natural low expression level, there remains a need to enhance the detectable signal The most straightforward way to enhance fluorescence signals is to increase the number of fluorophores available for detection. However increased labeling of proteins can lead to precipitation of the protein.
As an alternative, signal amplification methods can be used to get brighter signals. In catalytic reporter deposition (CARD) methods, the high turnover rate of enzymes like horseradish peroxidase and alkaline phosphatase generate high density labeling of a target protein or nucleic acid in situ. Hence in both immunohistochemical and immunoassay applications, careful control of timing is an essential prerequisite to obtain quantitative and re-producible results.
To avoid these potential limitations of amplification methods, an alternative is to increase the number of labels directly on affinity binders. A typical IgG antibody molecule has about ninety lysine residues, of which at most thirty can be modified under forcing conditions. However, maintenance of functional properties typically requires a degree of labeling of less than ten dyes per IgG, representing a low fraction of modification with individual fluorescent dyes. Antibodies labeled with more than four to six fluorophores per protein can exhibit reduced specificity and binding affinity. With higher degrees of substitution, the fluorescence obtained per added fluorophore is typically much lower than expected or calculated, due to self-quenching.
The use of soluble and relatively stable fluorescent proteins such as the phycobiliproteins, conjugated to anti-bodies could overcome the limitations arising from the high loading of low molecular weight dyes. On a molar basis, the fluorescence yield of a phycobiliprotein is equivalent to at least 30 unquenched fluorescein or 100 rhodamine molecules at comparable wavelengths. Further, fluorescent polystyrene microspheres heavily loaded with fluorescent dyes have been used as immuno-fluorescent reagents to deliver strong signals.
However, all current labeling schemes for fluorescent dyes suffer from one or more significant drawbacks. It remains desirable to provide straightforward and readily usable compositions, systems and methods for providing bright signals in fluorescent detection systems.

Nucleic acid-polymer conjugates for bright fluorescent tags


A bill accumulating storage unit is provided for use with a paper currency acceptor, the storage unit comprising a presser plate on one side of the currency pathway therein and a spring loaded currency support platform on the opposite side of the currency pathway. The presser plate is pivotably mounted to the eccentric center section of one or more cranks having concentric end sections journalled for rotation in the walls of the storage unit. Elongated stacker arms are mounted at a first end to a concentric end of the crank for conjoint rotation therewith. The second end of the stacker arm is coupled to a motorized rotatable drive cam at a location offset from the axis of rotation of the cam so that when the cam is rotated, stacker arms reversingly rotate the cranks so that the presser plate is forced by the eccentric crank center sections to pass through the currency pathway and into the storage area and back, causing a piece of paper currency in the pathway to be transferred by the presser plate into the storage area and to be secured therein by spring loaded platform as the presser plate returns to its starting position. The drive cam has a detent in its circumference which responsively engages the actuator of a microswitch as the cam reaches a position corresponding to the presser plate returning to its starting position.

Paper currency acceptors have become well known in these days of escalating prices. Their usage is commonly applied to vending machines and the like, which often require the deposit of money in amounts inconvenient to carry in coin. Since these units can accept money, it is desirable for these units to employ a device for the accumulation and storage of accepted bills so that extended periods of unattended currency collection is possible. Examples of such currency acceptors and storage units can be found in U.S. Pat. Nos. 4,884,671; 4,540,081; 4,011,931; 4,418,824; and 4,678,072.
The bill accumulating storage units illustrated in the aforementioned references suffer a number of disadvantages. The most common of these disadvantages is the design of the storage units in a manner which makes them an integral component of the currency accepting device. Consequently, those bill storage mechanisms cannot be retrofitted to other currency acceptors.
Furthermore, many of the prior designs employ extremely complex mechanisms to push the accepted bill from the bill passageway into the spring loaded storage section of the bill accumulator. Such devices are costly to manufacture and assemble and can require heightened maintenance, which further increase the cost of operation of these devices.
Other weaknesses of prior designs include the use of linear acting solenoids to motivate the bill pushing plates which must overcome the force of a spring loaded plate in the bill storage area. Since these solenoids are given a short pulse of power by the control circuitry to transfer the bill into the storage section from the bill pathway, there are no provisions for verifying that the solenoid and bill pusher have successfully traversed their full range of motion when pushing a bill into the storage section. This can become a particular problem when a number of bills have already accumulated in the storage section, thus causing the spring in the storage section to be at least partially compressed. In this condition, significantly higher effort is required from the solenoid to overcome that spring pressure when pushing subsequent bills into the storage area.
In other machines where a linear actuator is used, a spring is often used which is oriented opposite the actuation direction in order to return the bill pushing mechanism to a rest position out of the way of the bill accumulator inlet passageway. Here, again there are no provisions to verify that the actuator spring has fully returned the pusher mechanism to that rest position. Additionally, the orientation of the return spring opposite the actuation direction makes necessary the additional requirement that the solenoid exert even higher effort to overcome the return spring force when pushing a bill into storage section. This condition exacerbates the previously mentioned problem, requiring a larger and more costly solenoid to provide the elevated levels of effort necessary for operation.


Siloxane fluids containing novel siloxane polymers prepared from mixtures of disilanes, disiloxanes and silylmethylenes, and a method for recovering fully alkylated linear and cyclic siloxanes with disilane, disiloxane and silylmethylene bonds, such as from methylchlorosilane residue cleavage bottoms, are disclosed.

It has long been known in the art that methylchlorosilanes can be prepared by the direct reaction of particulate silicon and methyl chloride in the presence of metallic copper or silver catalyst. These reactions are disclosed in the literature, e.g. Rochow, U.S. Pat. No. 2,380,995 and Rochow, U.S. Pat. No. 2,383,818. In addition to dimethyldichlorosilane, a variety of other silanes can be formed such as tetramethylsilane, trimethylchlorosilane, methyltrichlorosilane, silicon tetrachloride, trichlorosilane, methyldichlorosilane and dimethylchlorosilane.
In addition to dimethyldichlorosilane, which is generally viewed as the most commercially attractive methylchlorosilane, a residue is produced during the formation of the methylchlorosilane crude. The residue is comprised of products in the methylchlorosilane crude having a boiling point above about 70.degree. C. at atmospheric pressure. The residue contains such materials as disilanes, for example, symmetrical 1,1,2,2-tetrachlorodimethyldisilane, 1,1,2-trichlorotrimethyldisilane, disiloxanes, silylmethylenes and other higher boiling species, for example, trisilanes, trisiloxanes, trisilylmethylene, etc.
It is further known in the art that certain components in the residue, mostly the highly chlorinated disilanes such as 1,1,2,2-tetrachlorodimethyldisilane and 1,1,2-trichlorotrimethyldisilane, can be "cleaved" in accordance with the teachings of Bluestein, U.S. Pat. No. 2,709,176, to produce useful methylchlorosilane monomers. Cleavage of the highly chlorinated disilanes can be effected by anhydrous hydrogen chloride in the presence of a tertiary amine catalyst to form monomers. The monomers are then distilled overhead and the remaining distillate, also known as the residue of the residue, is comprised of unreacted disilanes, disiloxanes and silylmethylenes. Prior to the present invention this residue of the residue was typically considered to have little or no commercial value.
It has now been found that a substantial portion of the residue of the residue stream can be converted into a useful product by hydrolyzing the components of this stream to form a silicone fluid comprising a novel siloxane polymer. Surprisingly, these silicone fluids have now been found to be a suitable replacement for linear and branched linear methyl siloxane polymers or fluids, such as emulsions and antifoam compounds.
Further, it has now been found that the residue of the residue stream provides a source for fully alkylated linear and cyclic siloxanes with disilane, disiloxane and/or silylmethylenes bonds.

Siloxane fluid from methylchlorosilane residue waste


A tracking error signal detection device employing a differential phase detection method includes first and second differentiators which remove direct current components in first and second signal groups in which a phase difference between the first and second signal groups changes in accordance with a tracking error signal, and which differentiate the first and second signal groups, first and second analog/digital converters which sample and quantize signals output from the first and second differentiators, respectively, a Hilbert transformer performing a 90-degree phase shift on one of signals output from the first and second analog/digital converters, a delay circuit delaying one of the signals output from the second and first analog/digital converters by an amount of delay equal to that caused by the Hilbert transformer, and a phase comparator calculating a phase difference between a signal output from the Hilbert transformer and a signal output from the delay circuit.

1. Field of the Invention
The present invention relates to a tracking error (TE) detection device using a DPD (differential phase detection) method which is employed in an optical disc apparatus, for example, and the optical disc apparatus.
2. Description of the Related Art
In general, optical controllers include TE (tracking error) detection devices (circuits) employing DPD methods in order to generate tracking error signals in ROM discs. The TE detection devices employing the DPD methods are currently realized by analog circuits which operate at high speed and which have high accuracies (refer to Japanese Patent No. 3336778, Japanese Unexamined Patent Application Publication No. 57-191839, Japanese Unexamined Patent Application Publication No. 57-181433, Japanese Unexamined Patent Application Publication No. 63-148433, Japanese Unexamined Patent Application Publication No. 07-296395, Japanese Unexamined Patent Application Publication No. 63-131334, Japanese Patent No. 3065993, Japanese Patent No. 3439393, Japanese Unexamined Patent Application Publication No. 2006-260645, and Japanese Patent No. 3769888, for example)
In response to recent development of a system LSI (large-scale integration) technique, a technique of integrating analog signal processing and digital signal processing so that the analog signal processing and the digital signal processing are performed using an identical chip has been developed. This technique is also applied to controller chips of optical discs. In response to such development of digital signal processing, there are strong demands for integrations in order to obtain digital chips in TE detection devices employing DPD methods.
To meet such demands, three techniques will be described hereinafter as first to third examples.

Tracking error signal detection device and optical disc apparatus


Provided is an electronic device including: a piezoelectric element; a vibration plate to which the piezoelectric element is joined for vibration; and a housing to which the vibration plate is joined. Vibration sound, which is transmitted by vibrating a part of a human body, is generated by the vibration plate. The vibration plate includes, in a plan view thereof, a first area including a joining portion with the piezoelectric element and a second area located further away from the joining portion than the first area is, and rigidity in a first area is lower than rigidity in the second area. With the above configuration, sound leakage or the like is reduced, and usability of the electronic device is improved.

Patent Literature 1 listed below describes that air conduction sound and bone conduction sound are known as sound that is transmitted from an electronic device such as a mobile phone to a human being. It is also described that air conduction sound is sound perceived by an auditory nerve of a user as a result of an eardrum being vibrated by an air vibration that is created by a vibration of an object and that travels through an external auditory canal down to the eardrum. Furthermore, it is described that bone conduction sound is transmitted to the auditory nerve of the user through a part of a user's body (e.g. a cartilaginous portion of an external ear) that is in contact with the vibrating object.
Patent Literature 1 also describes that, in a mobile phone that transmits sound to the user by air conduction sound and bone conduction sound, a rectangular plate-shaped vibration body configured by piezoelectric bimorph and a flexible material is attached to an outer surface of a housing via an elastic member. It is also described that upon application of a voltage to the piezoelectric bimorph of the vibration body, the piezoelectric bimorph is expanded and contracted in a longitudinal direction, thereby vibrating the vibration body. Furthermore, it is described that, when the user places the vibration body in contact with an auricle, air conduction sound and bone conduction sound are transmitted to the user.


A digital camera system comprises a digital camera and a cradle unit, which are electrically connected via a connector and a connection terminal. The cradle unit is provided with an operation-code generator and a light emitter. When an external display mode is selected by operating an operational section of the digital camera, the operation-code generator generates an operation code as an analog signal. This analog signal is sent to the light emitter. Upon receiving the analog signal, the light emitter emits an infrared signal of the operation code toward a TV monitor to change the TV monitor into an external input condition.

1. Field of the Invention
The present invention relates to a digital camera system in which a digital camera is connected to a cradle via which data is transferred to an external apparatus and an image is outputted to an external display.
2. Description of the Related Art
In recent years, a digital camera is not only used alone but also often connected to an external apparatus of a personal computer (hereinafter, abbreviated as PC) and so forth to transfer image data to the PC. The digital camera is sometimes connected to an external display of a TV monitor and so forth to output an image and to show it on a large display.
Meanwhile, the digital camera has great advantages in right weight, small size and good portability. Thus, it is preferable to make a number of parts, which are built in a camera body, as small as possible. Many of the digital cameras accompany appurtenances called as cradle assembly and docking station, for example. Such an appurtenance is provided with a power-supply function and a relay function including an interface (I/F) for connection with the PC and the TV monitor, such as described in Japanese Patent Laid-Open Publication No. 2002-232769. In the following description, the cradle assembly and the docking station are designated as a cradle unit.
In a case that the above-mentioned cradle unit pertains to the digital camera, the cradle unit is provided with an attachment portion, a shape of which corresponds to a bottom portion of a camera body. By setting the digital camera to the attachment portion, a connector provided at the digital-camera side is joined to a connection terminal provided at the cradle-unit side so that the digital camera is electrically connected to the cradle unit. Since an electric power is supplied from the cradle unit to the digital camera in this state, it is possible to use the digital camera for a long time without caring the remainder of battery.
However, as to the digital camera described in the above-noted Publication No. 2002-232769, when the digital camera is set to the cradle unit via which the digital camera is connected to both of the PC and the TV monitor, it is necessary to change over the TV monitor to an external-input condition so as to display an image, which is outputted from the digital camera, on the TV monitor. Moreover, when the power supply is turned off, it is necessary to turn on it. Much time is taken for carrying out such operations of the TV monitor in addition to a booting operation and other operations of the PC and the digital camera. Before displaying the image on the TV monitor, it is necessary to perform many operations. Further, small operation buttons provided on the digital camera have to be handled in the state that the digital camera is set to the cradle unit. This causes to take much more time for the operation.


A rotary wing aircraft is provided with longitudinally oriented counter-rotating rotors with circumferentially spaced variable pitch elongated rotor blades connected at their opposite ends to rotatable support rings mounted on the aircraft fuselage. Rotor downwash may be guided laterally and longitudinally by respective sets of moveable guide vanes. Propulsion may be obtained by an engine providing thrust and power take-off for driving the rotors. An auxiliary or second engine may be drivingly connected to the rotors.

The continuing rapid development of aviation technologies with respect to aircraft structures, propulsion systems and navigation systems augers well for expanded use of aircraft by professional aviators and the general public. However, one drawback to the continued proliferation of general aviation aircraft, for example, is with respect to the space needs for fix-winged aircraft as well as conventional rotary wing aircraft. Fixed wing aircraft, of course, require substantial space for take-off and landing operations and conventional rotary wing aircraft require substantial space for storage. Accordingly, there has been a continuing need to develop aircraft which have short take-off and landing (STOL) or substantially vertical take-off and landing (VTOL) capabilities.
Certain efforts have been made to develop rotary wing aircraft with rotors which are characterized by elongated blades arranged in a circular pattern and secured to ring-like support structures at opposite ends of the blades. However, prior art efforts have been focused primarily on rotary wing aircraft with rotors which are arranged for rotation about axes normal to the longitudinal axis of the aircraft and its direction of flight. Certain efforts have been put forth to develop rotary wing aircraft of the general type discussed above which have rotors arranged longitudinally. However, prior art efforts have indicated to be complicated and lacking stability in the event of failure of one or more rotor sets and space requirements for prior art rotary wing aircraft have been, generally, similar to the needs of conventional helicopter aircraft.
Accordingly, there has been a continuing need and desire to provide aircraft which are compact, stable in flight, capable of STOL or VTOL operations and which meet the conventional needs of general aviation as well as commercial aircraft. It is to these ends that the present invention has been developed.


A register file circuit according to some examples of the disclosure may include a memory cell, a header transistor circuit, and a driver circuit. The header transistor circuit may include one or more PFET headers in series with the PFETs of the memory cell with the gate of the PFET header for the row being written being controlled with a pulse write signal from the driver circuit. In some examples of the disclosure, the header transistor circuit may include an NFET pull-down inserted between a virtual-vdd and ground to discharge the virtual-vdd node reducing the contention during a write operation and a clamping NFET in parallel with the PFET header to clamp the virtual-vdd node to slightly below the threshold voltage of the pull-up PFET in the memory cell to ensure the pull-up PFET is barely off and prevent the virtual-vdd node from discharging all the way to ground.

As processors become more complex, the energy used by the processor increases and the need to maximize the energy usage becomes more important. In order to maximize processor energy efficiency, processor designs reduce the supply voltage (VDD) for applications with low-performance requirements (scaling). For example, register file circuits require a minimum operating VDD (VMIN) to successfully perform a write operation. Since register file arrays are distributed across a processor, the register file circuits and the processor logic share the same VDD. For this reason, the register file VMIN for a write operation limits the overall processor VDD scaling and the potential energy benefits. As shown in FIG. 1, the register file VMIN results from a contention path between the NFET transfer device (N4) attempting to bring node "T" to ground and the PFET pull-up device (P1) attempting to hold node "T" to VDD. Because the other NFET transfer device (N3) passes a weak "1" (VDD−Vt), where Vt is the transistor threshold voltage, into the complimentary node "C" and to the gate of P1, the P1 device stays partially on and resists the N4 device in bringing node "T" to ground. This contention is exacerbated as VDD reduces, especially when the process skews toward slow NFET devices and fast PFET devices. Since designs need to operate across all process corners, this contention limits the VMIN of register file circuits and consequently limits the processor energy efficiency. From simulations of a conventional processor, the register file VMIN results in a loss of more than 26% in processor energy savings.
Accordingly, there are long-felt industry needs for methods that improve upon conventional methods including the improved methods and apparatus provided hereby.
The inventive features that are characteristic of the teachings, together with further features and advantages, are better understood from the detailed description and the accompanying figures. Each of the figures is provided for the purpose of illustration and description only, and does not limit the present teachings.

Register file circuit and method for improving the minimum operating supply voltage


The configuration of a whitener encoder used in a wireless LAN is simplified, thereby reducing the size of the circuit. The present weight of an n-bit interval is calculated by a counter that counts up when the transmitted data is "1", and counts down when it is "0". The weight for data already sent out is calculated by a counter that counts up when the transmitted data is "1", and counts down when it is "0". Whether or not the transmitted data is inverted is determined by comparing only the most significant bits, which are the sign bits of the counter, with a comparator circuit. A large circuit need not be used.

1. Field of the Invention
The present invention relates to a processing unit, and, more particularly, to a processing unit for a whitener encoder used for a wireless LAN.
2. Description of the Prior Art
A wireless LAN (local area network) is set forth in a standard being provided by the IEEE 802.11 Committee. An algorithm on the white encoder is described in a publication, "Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications," Draft Standard IEEE 802.11, Jan. 26, 1996 (P 802.1103), by Institute of Electrical and Electronics Engineers, Inc., pp. 179-180, 183-184, and 189.
First, a transmission frame used by the wireless LAN is described in FIG. 7. A start frame delimiter (SFD) 54 is sent following a preamble 53 in which "1" and "0" are repeated. After a header 55 containing information indicating transmission data length and a transmission frame is sent following SFD 54 informing a receiver that valid data follows, transmission data 56 is sent.
The transmission data 56 has a variable length. A whitener encoder inserts and sends one stuff bit 52 in every 32 bits. To suppress DC bias in a transmission frame, the whitener encoder inverts the transmission data 56 during certain 32 bits segments.
The stuff bit 52 is set to a "1" bit and inserted before the 32-bit interval in which the transmission data 56 is bit inverted. This enables the receiver to receive proper data by bit inverting the transmission data 56 again when the stuff bit 52 is a "1" bit. Here, a cyclic redundancy check (CRC) 57 for error checking is appended to the end of the transmission frame.
FIG. 8 is a block diagram showing the configuration of a conventional processing unit. The processing unit in the figure is configured according to the whitener encoder algorithm described in IEEE 802.11. The operation of a conventional processing unit is described below by referring to FIGS. 7 and 8.
First, the parallel format input transmission data is converted into a serial data format by a parallel-serial converter circuit 11. Then, the transmission data converted into the serial data format is randomized by a scrambler 12.
The scrambled data is input into an n-bit shift register 13. Here, n=32 is assumed. The shift register 13 takes out data from the transmission data 56 in the transmission frame in every 32 bits. Then, an adder circuit 31 weighs and adds the 32-bit data thus taken out by bit. This is to execute "bias.sub.-- next.sub.-- block=Sum {weight (b (0)), . . . , weight (b (32))}" in the above-mentioned algorithm of IEEE 802.11.
b(1) to b(32) indicate the data taken out by the 32-bit shift register 13. b(0) is the stuff bit 52. This stuff bit 52 is a bit inserted in a frame in every 32 bits by a stuff bit insertion circuit 14. The initial value of the stuff bit 52 is b (0)=0.
The weight is +2 when the transmission data 56 is "1," and -2 when it is "0". For example, weight (b (1))=+2 for b (1)=1, while weight (b (1))=-2 for b (2)=0.
The adder circuit 31 is reset when the frame transmission is started, and also reset after calculation for every 32 bits. The resetting causes the adder circuit 31 to have a value of "0".
Here, it is assumed that the result calculated by the adder circuit 31 is "bias," and the result calculated by the adder circuit 32 is "accum." Then, a comparator circuit 33 determines whether or not bias*accum>0. This means to execute "If {[accum*bias.sub.-- next.sub.-- block>0] then . . . }" in the algorithm. The comparator circuit 33 has an output of "0" if the determination result is bias*accum>0, and an output of "1" if the determination result bias*accum<0.
When the output of the comparator circuit 33 is "0", bit inversion is performed by a bit inverter circuit 15 for the data in the interval of 32 bits used for the calculation of bias when each bit is sent out. This is to execute "Invert {b (0), . . . , b (N)}" in the algorithm. On the other hand, when the output of the comparator circuit 33 is "1", the bit inversion is not performed.
When the output of the comparator circuit 33 is "0", inversion is performed on the output of the adder circuit 31 (bias) by a sign inverter circuit 34. This is to execute "bias.sub.-- next.sub.-- block=-bias.sub.-- next.sub.-- block" in the above algorithm. On the other hand, when the output of the comparator circuit 33 is "1", the bit inversion is not performed.
As described above, the adder circuit 31 adds transmitted data in every certain interval of 32 bits, and the adder circuit 32 adds the results obtained by the adder circuit 31. The result from the adder circuit 32 is saved in a register 35. Then, the comparator circuit 33 compares the value of the adder circuit 31 with that of the register 35 in every interval of 32 bits. According to the result of the comparator circuit 33, the sign inverter circuit 34 operates to invert the sign of the result of the adder circuit 31, and the bit inverter circuit 15 to invert the transmitted data "1" and "0". The output of the bit inverter circuit 15 becomes transmitted data TX.
Operation of a conventional whitener encoder is described by referring to the timing charts of FIGS. 9 and 10, and the block diagram of FIG. 8. FIGS. 9 and 10 show an example where 89h ("h" indicating a hexadecimal number, the same applying to the following) as a header (section of intervals A1 and A2 of FIG. 9), data of 75h, E7h, and B6h are sequentially transmitted from the least significant bit (hereinafter called "LSB"), and 19h, 59h, 05h, 31h, 26h, B1h, 9Ah, and 4Ch are transmitted as the transmitted data after scrambling (section of B1, C1, B2 and C2 of FIGS. 9 and 10) from LSB. For example, when 19h is transmitted from LSB, it is transmitted as "10011000".
Although in FIGS. 9 and 10 data in the interval A1 are not depicted, it is the same as the data in the interval A2. Data in an interval B1 are shifted 32 bits by the 32-bit shift register 13, and transmitted as transmitted data in an interval B2. Similarly, data in an interval C1 is transmitted in an interval C2.
Such shifting by 32 bits occurs because transmission should be performed after determining whether data during an interval of 32 bits is bit inverted after calculating weight based on the data according to the weight calculation method, which is described later.
The adder circuit 31 adds data in the interval of 32 bits with weight. The weight is +2 when the data is "1", and -2 when it is "0". For example, when 19h described above is added with the weight, it is +2-2-2+2+2-2-2-2=-4.
In timing (1) of FIG. 9, since there are 19 "1" bits and 13 "0" bits in the interval A1, the adder circuit 31 provides a result of addition of (+2.times.19)+(-2.times.13)=+12. For the interval A1 or the header section, the result of the adder circuit 31 is accumulated in the register as it is.
In timing (2) of FIG. 9, the adder circuit 31 adds data in the interval B1 including the stuff bit SB. Here, since there are 12 "1" and 21 "0", the result is (+2.times.12)+(-2.times.21)=-18.
In addition, in this timing, the comparator circuit 33 compares the addition result of the adder circuit 31 with the value of the register 35. In this case, since the output of the adder circuit 31 multiplied by the output of the register 35 is less than zero, no signal for inverting the data is output to the sign inverting circuit 34 and the bit inverting circuit 15.
In FIG. 9, the output of the comparator circuit 31 is "1". In other words, since the data inversion is not performed, the output of the sign inverting circuit 34 is "-18", and the bits in the interval B1 is transmitted in the interval B2 as it is without bit inversion. The adder circuit 32 adds the output "-18" of the sign inverting circuit 34 and the output "+12" of the register 35, and obtains a value of -6. The addition result of the adder circuit 32 is accumulated in the register 35.
Similarly, in timing (3) of FIG. 10, the adder circuit 31 adds data in an interval C1 including the stuff bit. Here, since there are 14 "1" bits and 19 "0" bits, the result is (+2.times.14)+(-2.times.19)=-10. In addition, in this timing, the comparator circuit 33 compares the addition result of the adder circuit 31 with the value of the register 35. In this case, since there is provided a result of the output "-10" of the adder circuit 31 multiplied by the output "-6" of the register 35 is greater than zero, the comparator circuit 33 outputs a signal for inverting the data to the signal inverting circuit 34 and the bit inverting circuit 15.
In FIG. 10, the comparator circuit 33 has the output of "0". That is, since the data is inverted, the sign inverting circuit 34 has an output of +10, and transmitted data in the interval C2 is bit-inverted data in the interval C1. The adder circuit 32 adds the output "+10" of the sign inverting circuit 34 and the output "-6" of the register 35, and obtains a value of "+4". The result of the adder circuit 32 is accumulated in the register 35.
Since the stuff bit SB is "1" in an interval in which the transmitted data is bit inverted, the receiver checks to determine whether or not the stuff bit SB is "1", and, if so, inverts subsequent 32 bit data again, and returns them.
The effect of suppression of DC bias by the whitener encoder is described. For example, if the interval C2 is not inverted, the output value of the register 35 after the completion of the interval C2 becomes +12-18-10=-16, so that the transmitted data are shifted toward "0". Then, when the interval C2 is inverted, the value of the register becomes +12-18+10=+4 as described above. In this case, it is reversely shifted towards "1" but not significantly. Thus, the DC bias on the transmitted data can be suppressed by adjusting the number of "1" and "0" in the transmitted data.
As described above, the conventional unit comprises, in addition to a shift register and a stuff bit insertion circuit, two adder circuits for calculating weight, a sign inverting circuit for inverting the result of weight calculation, a register for holding the results of weight calculation in the past, and a comparator circuit for determining whether or not the transmitted data is inverted. Thus, one disadvantage is that the circuit configuration of the processing unit is large. The size of the circuit configuration is described in the following.
First, a description is given for the internal configuration of two adder circuits 31 and 32. An example of the configuration of the adder circuit 31 is shown in FIGS. 11-17. In these figures, similar components are designed by like references.
Input terminals are terminals d15-d28 shown in FIG. 11, terminals d0-d10 shown in FIG. 14, a terminal d29 shown in FIG. 16, and terminals d11-d14 and d31 shown in FIG. 17. In addition, output terminals designated by ">>" in these figures are assumed to be connected to the input terminals with the same references as the output terminals and designated by ">>."
Furthermore, a terminal SUM of FIG. 17 is a 6-bit bus type output terminal, and shown by a thick line for convenience. One bit of the 6-bit terminal SUM of FIG. 17 leads to the input of FIG. 17 from the output of FIG. 15.
The adder circuit 31 with such a configuration performs the operation described above. It will be obvious that an equivalent circuit may be configured by using various gates. The adder circuit 31, configured as shown in FIGS. 11-17, has about 330 gates.
An example of the configuration of the adder circuit 32 is shown in FIG. 18. The adder circuit 32 comprises two input terminals dina and dinb, and an output terminal dout. The input terminals dina and dinb are of a 6-bit bus type, while the output terminal dout is of a 7-bit bus type. All of them are indicated by thick lines for convenience. It is assumed that the most significant bit of seven bits of the output terminal dout is not used, and the remaining six bits are used. Here, the adder circuit 32 shown in the figure has about 39 gates.
The above-mentioned conventional processing unit comprises, in addition to these adder circuits 31 and 32, a register 35 and comparator circuit 33. The register has about 34 gates, while the comparator circuit 33 has about 60-70 gates.
Therefore, the conventional unit has as many as 330+39+34+60=463 gates in total for the adder circuits 31 and 32, the register 35 and the comparator circuit 33, and consequently the circuit is very large.


A method of treating breast cancer that is at least partially ER+ is disclosed. The method comprises administering at a tumor site in a mammalian subject a pharmaceutically acceptable form of Fe(II) or Fe(III) in a suitable carrier. A four-part program aimed at eradicating breast cancer includes (a) local treatment and prevention of spread from a contained breast site, preferably using local administration of a ferric iron composition, (b) treatment of disseminated (metastatic) breast cancer, (c) reduction in the risk of developing breast cancer, preferably by enhancing dimeric/polymeric IgA and polymeric IgM inhibition of estrogen responsive cell growth, and (d) protection against cancer causing agents.

1. Field of the Invention
The present invention generally relates to methods and compositions for the eradication of cancers of the mucosal endothelial tissues. More particularly, the present invention relates to the use of such compositions and methods for breast cancer risk reduction, prevention and treatment.
2. Description of Related Art
For women with breast cancer, the term "eradication" has different meanings depending upon the state of their disease. Additionally, for women still disease free, eradication means preventing the development of breast cancer. Today, there are no known preventions for breast cancer. Although many risk factors have been identified for breast cancer (76-78), reduction of overall risk from the current United States level of one-in-eight has not been achieved short of the use of the anti-estrogen tamoxifen as a preventative (79). However tamoxifen is only for use by very high-risk women (79). It is not for use with the general population, both because of adverse side effects and because of disruption of reproductive capacity. Accordingly, tamoxifen is under evaluation for high-risk women, but is not considered appropriate for use as a standard preventative due to its serious side-effects and causation of a number of endocrine problems. Treatment with tamoxifen for more than five years may in fact induce breast cancer. It is now recommended that this therapy be limited to only five years. This does not cover the span of a women's lifetime. Based on knowledge today, it may be possible to reduce risk by alterations of life style and diet, but these are at best fractional gains and offer no assurances. Even women who lead very health-risk conscious lives still develop breast cancer. A successful mass prevention is a primary goal in the fight against this disease.
For women diagnosed with breast cancer, the current most effective eradication methods begin with various surgical procedures (i.e. mastectomy or breast conservation surgery or more commonly lumpectomy). Without doubt, removing a primary tumor is an effective first step of eradication provided tumor cells have not escaped to other body sites. Given that we understand that escape is a possibility, or that multiple unrecognized tumor foci are present in one or both breasts, many breast cancer patients opt for radiation therapy, adjuvant chemotherapy and/or tamoxifen treatment even when they are diagnosed as node negative. The term "node negative" indicates that cancer cells have not moved to the axillary nodes from the breast. Commonly however, it is thought useful to "shrink" primary tumors before surgical removal. Today this is done by systemic chemotherapy or radiation therapy. Patients with node negative estrogen receptor positive (ER+) breast cancer may also be treated with anti-estrogen (e.g. tamoxifen) as is often done for postmenopausal women. Depending upon age and physical condition, anti-estrogen therapy is now a common alternative for many postmenopausal women.
For breast cancer patients who are axillary node positive (either ER+ or ER−), additional treatment is essential including those noted above. There is no doubt that these modalities have a major positive impact on long term survival, but it is likewise clear to basic cancer investigators and cancer clinicians alike that the failure rate is significant even despite frequent quoting of favorable statistical data. Currently, node positive women without other evidence of dissemination can be treated by standard chemotherapy and/or radiation therapy. However, node positive patients with ER− tumors are at risk no matter the therapy utilized. For these women, the use of anti-hormone therapy is not as effective as with patients with ER+ tumors.
It is with the diagnosis of metastases to liver, bone, brain, lung, etc., that another more serious level of the eradication issues arises, and standard chemotherapy is most often not effective. For reasons both known and unknown, these cases have a very poor prognosis. Current chemotherapy can sometimes retard metastatic cancer growth, but as cancers spread they become progressively more therapy resistant. The level of public concern about this issue is clear from anticipation of the benefits of such new drugs as Herceptin®, which is a monoclonal antibody against the HER2 receptor. Introduction of Herceptin® was accompanied by widespread reports in the news media that heightened expectations. Unfortunately, even this new family of biopharmaceuticals is not an effective means of eradication. At best, Herceptin® provides only a small increase in survival time and then only in combination with chemotherapy and only with a minority of treated patients (70). While other types of drugs are under investigation, the magnitude of the disseminated cancer problem remains undiminished.
Iron deprivation has been discussed as a means of eliminating cancer cells (39,40), but the focus has been on two technologies that, used alone, have not worked. First, those investigators have considered iron deprivation via treatment with chelators that bind the metal and thereby render it metabolically inactive. Chelation alone has not removed enough iron from the body to be effective as an anticancer program (41). This is to be expected, for it is known that iron is retained in organs and tissues with a biological half-life of about 2000 days. Most likely, chelation alone will not be an effective therapy.
Currently, the primary effort in breast cancer research aimed at eradication of the disease is intensely focused by powerful technology that permits identification of a large number of genes, and by the human genome project that promises to solve the cancer problem. To date, these technologies have provided valuable information but have failed to move to the next level of application, cancer eradication.
A brief historical overview of breast cancer research over the past four decades points to numerous periods of advancement, each with its own promise of defeating cancer. For example, during the 1960s investigators were encouraged by newly identified enzyme and metabolic changes in cancer cells. It then seemed clear that these changes were the cause of cancer and that its end was near. During the 1970s, the beginnings of molecular biology (then called microbial genetics) yielded new found information that was thought certain to lead to the end of many human diseases, including cancer. Investigations in the field of endocrine cancer research, during the 1980s, focused on how hormones caused cell growth and developed animal models to study hormone dependent cancer. At that time, serum-free defined animal cell culture was being developed (1) and new substances called growth factors were being explored (2). Also during that period, another major advancement was the discovery of the estrogen receptor (ER) and the hypothesis that it alone controlled estrogen dependent cell growth (3-5). Some investigators did not accept all of the ER hypothesis (6-8), however, and thought that estrogen-inducible growth factors (estromedins) were necessary (6,9,10). It appeared clear at that time that growth factor research would untangle the cancer enigma. Today cancer scientists know this is not the case.
Along with the growth factor research came the "oncogene" explosion of the 1990s, which promised an end to cancer. Today, cancer investigators are inundated by scores of gene changes in cancer. The list grows weekly. A GENBANK search of "breast cancer hot spots" yielded more than 100 "hits" on several chromosomes. This cornucopia of genetic information obscures two facts: First, very few breast cancers can be traced to germ line DNA changes (11). Most are not inherited. Notable exceptions are BRCA1 and BRCA2, which represent at most 1-10% of breast cancers in the United States (31-33). Given that the incidence of breast cancer now approaches 1 in 8, the majority of breast cancers have other origins. Second, sophisticated new molecular technology has identified changes in expression of at least 100 mRNAs in breast cancer cells (11). There is promise of hundreds of gene/expression changes (11-13). It is very unlikely they are all causative or even critical to breast cancer. The tempting scenario is to investigate each mRNA or gene to define its role. Of course, this represents years of work for researchers, and still leaves open the question: "Will this lead to breast cancer eradication"?
It is known that eighty percent or more of breast cancers are invasive ductal carcinomas that arise from ductal cells (85,86) or precursors of ductal cells (85,87). Based on the current state of knowledge, there is no genetic lesion to explain the 70% of breast cancers now termed "sporadic". Certainly the BRCA1 and BRCA2 genes are responsible for at most a small percentage of breast cancers in this country (88-91). Lesions in the p53 gene were initially thought to be important in as many as 15 to 50% of breast cancers (92-94). However, it was far from clear which mutations are causally related to breast cancer onset or which actually constitute secondary changes leading to loss of function of this tumor suppressor gene in the different types of breast cancer (i.e. ER+ or ER−). A more recent study has rightly pointed out the confusion regarding p53 mutations and breast cancer patients (96). Studies of p53 mutations have yielded a wide range of results depending upon the methods employed (97). One useful fact is that the results average about 30 to 40% for loss of heterozygosity at the p53 gene (97). This means the remaining gene may be a "hot spot" (i.e., a chromosomal loci or gene that is frequently altered in breast cancer specimens). However, at this time, there is not sufficient evidence to support the use of p53 as a guide to selection of therapy modalities for breast cancer (98).
In fact, today it is very difficult to explain the great many mutations and other types of genetic expression alterations that are known in breast cancer cells (11). Based on the findings with breast and other types of mucosal cancers, such changes include mutations, translocations, amplifications of oncogenes, loss of heterozygosity (LOH), and allelic imbalances (12,13,100-102). How do all of these happen? Are environmental carcinogens in such high abundance that they explain these data? Despite the concentrated focus given to environmental carcinogens as causes of breast cancer (20,95,99), that hypothesis has failed to move forward to the level of accepted scientific fact. Ways to reduce the risk of developing breast cancer, ways of preventing its occurrence, and ways to treat existing cases of localized and metastatic breast cancer are urgently needed. Even with the very best of treatments currently available, a longer-term plan is still needed in which prevention is the first line of eradication. A successful prevention will be, preferably, safe and have low or negligible side effects. It should be capable of reducing risk for the majority of women, independent of their economic circumstances. It should cause little or no disruption of life-style or reproductive capacity.


The present invention relates to a solid image pick-up unit which can restrict a variation in the leakage charge quantity at the light emitting time and non-emitting time of the LED and in which a signal charge quantity can be increased and adjusted without increasing the number of LED. A photodiode is connected to two sample-hold transistors for transferring charges to two sample-hold capacitors respectively through a transfer transistor, and is also connected to a reset transistor and an amplification transistor through the transfer transistor. Further, the amplification transistor is connected with an address transistor. The two sample-hold capacitors are disposed at positions symmetrical with the center of the n-diffusion layer of the photodiode.

The present invention relates to an amplification-type solid image pick-up unit and a method of driving the same, and relates more particularly to an amplification-type solid image pick-up unit which can improve an S/N ratio and which can adjust sensitivity easily and a method of driving this solid image pick-up unit.
As an example of the MOS-type image sensor that has been used conventionally, there has been known a one having a structure as described in the Japanese Patent Application No. 8-275949 which is a prior application made by the inventor of the present invention.
FIG. 1 a diagram for showing a circuit structure of the main portion of the image sensor described in the Japanese Patent Application No. 8-275949.
In FIG. 1, this image sensor has a photodiode 2 connected to a reset transistor 6 and an amplification transistor 8 through a transfer transistor 4. A circuit structured by a transfer transistor 10a and sample hold capacitor 12a and a circuit structured by a transfer transistor 10b and sample hold capacitor 12b are connected in parallel respectively between the transfer transistor 4 and the amplification transistor 8.
The amplification transistor 8 has its drain connected to the source of an address transistor 14 and has its source connected to a vertical signal line 16. The gate of the address transistor 14 is connected to a horizontal address line 18. Further, the amplification transistor 8 is connected to a horizontal selection transistor through the vertical signal line 16 and a differential circuit not shown.
In the above-described structure, it becomes possible to cancel a variation in the threshold value of the amplification transistor 8 by taking a difference between the potential of the vertical signal line 16 when the gate of the amplification transistor 8 has been reset and the potential of the vertical signal line 16 when a signal component is being applied.
According to the image sensor of the structure as shown in FIG. 1, it is not so arranged that a signal charge obtained from the photodiode 2 is taken out directly. However, it is so arranged that the simultaneity of the signal charges obtained from the photodiode 2 is obtained by providing the capacity for holding signal charges from the photodiode 12, that is the sample hold capacitor 12a and 12b.
In the image sensor shown in FIG. 1, a light emitting diode (LED) not shown is used for deciding a light applied from the outside to an object of which image is to be picked up. In other words, a signal of only a background light such as a sun beam or an indoor light other than the light emitted by the LED and a signal of a light which is a combination of the background light and the light emitted by the LED are photoelectrically converted by the photodiode 2 and are then taken into the sample hold capacitors 12a and 12b. Then, a difference between the signal charges taken into these sample hold capacitors 12a and 12b is taken. However, when the LED is used, there arises a problem that the image sensor has a leakage of charges easily.
Although it is possible to cancel the leakage to some extent by taking a difference in the case of an external light, leaking charges depend on the distribution of the surrounding light and are not uniform on the plane. Therefore, there is a problem that there arises a difference between the quantity of leakage at a first time of storage after the LED has emitted a light and the quantity of leakage at a second time of storage after the LED has not emitted a light, for example, depending on the layout of the diffusion layer area of the transistors connected to the sample hold capacitors for holding the signal charges. Furthermore, the S/N ratio becomes poorer because of the variation in the leakage quantity.
Further, according to the above-described Japanese Patent Application No. 8-275949, since light emitting time and light emitting intervals are made shorter in order to restrict variation of the external lights, the light emitting volume becomes smaller if the number of LED cannot be increased for cost reason. To avoid this difficulty, it may be considered suitable to increase the LED light emitting time to a double. However, this often leads to a doubling of the dark current and the leaking quantity although the total light emitting volume of the LED is not doubled because of the characteristics of the LED. Accordingly, this does not contribute to improve the S/N ratio although the signal volume is increased.
On the other hand, when the number of LED is increased, the number of photon emitted is increased. However, if the number of LED is increased, it becomes impossible to reduce the size of the unit. Moreover, a larger power source is required because a large volume of current becomes necessary at one time. Therefore, a method which makes it possible to increase the sensitivity of the sensor without increasing the number of LED or without increasing the light emitting time has been required.
Further, according to the method described in the mode of implementation in the Japanese Patent Application No. 8-275949, the photodiode is saturated by the dark current the strong external light signal component at the time of adjusting the sensitivity. In order to use the unit within the range in which the photodiode is not saturated, the sensitivity adjusting operation must be repeated by many cycles. However, this has a problem of extremely limiting the number of signal storage operation because of the characteristics of the capacitors.
In order to eliminate the above-described problems, it is an object of the present invention to provide a solid image pick-up unit which can restrict the variation in the leakage charge quantity at the light emitting time and non-light emitting time of the LED, which makes it possible to increase the signal charge quantity without increasing the number of LED and which can carry out sensitivity adjustment easily, and a method of driving this unit.
According to the present invention, there is provided a solid image pick-up unit having a unit cell laid out in a matrix two dimensional shape, by having a light receiving unit, an amplifying unit for amplifying a signal detected by the light receiving unit, a selecting unit for selecting a cell thereof and a resetting unit for resetting the light receiving unit, on a semiconductor substrate, wherein the unit cell has at least two storage units for storing a signal corresponding to a light quantity received by the light receiving unit, the semiconductor substrate is structured by a first conductive type and has a difference detecting unit for detecting a difference between signals stored in the at least two storage units, the light receiving unit is structured by a first diffusion layer area of a second conductive type opposite to the first conductive type, the at least two storage units are structured by a second diffusion layer area of a second conductive type, and a first diffusion layer area of the storage units is disposed at a position symmetrical with the center of the first diffusion layer area of the light receiving unit.
Further, according to the present invention, there is provided a solid image pick-up unit having a unit cell laid out in a matrix two dimensional shape, by having a light receiving unit, a detecting unit for detecting a signal charge by transferring a signal from the light receiving unit, an amplifying unit for amplifying a signal detected by the detecting unit, a selecting unit for selecting a cell thereof and a resetting unit for resetting the light receiving unit, on a semiconductor substrate, wherein the detecting unit is structured by first and second detecting units connected in series, the solid image pick-up unit includes a storage unit connected between the first detecting unit and the second detecting unit, and the resetting unit also resets the amplifying unit and the storage unit.
Further, according to the present invention, there is provided a solid image pick-up unit having a unit cell laid out in a matrix two dimensional shape, by having a photodiode, a transfer transistor for transferring a signal from the photodiode, a detection transistor for detecting a signal charge transferred by the transfer transistor, an amplification transistor for amplifying a signal detected by the detection transistor, a selection transistor for selecting a cell thereof, a reset transistor for resetting the photodiode and a sample hold capacitor for holding a signal corresponding to a light quantity received by the photodiode, on a semiconductor substrate, wherein the solid image pick-up unit includes a slice transistor to be connected to the photodiode through the transfer transistor and includes a slice capacitor having one end of an electrode thereof connected to the source and drain area of the slice transistor and having the other end of the electrode connected to a pulse circuit, and the other end of the source and drain area of the slice transistor is connected to the gate of the amplification transistor through the detection transistor, one end of the sample hold capacitor is connected to a connection section between the detection transistor and the amplification transistor, and the reset transistor is connected to a connection section between the transfer transistor and the gate of the slice transistor.
Further, according to the present invention, there is provided a solid image pick-up unit having a unit cell laid out in a matrix two dimensional shape, by having a photodiode, a transfer transistor for transferring a signal from the photodiode, a detection transistor for detecting a signal charge transferred by the transfer transistor, an amplification transistor for amplifying a signal detected by the detection transistor, a selection transistor for selecting a cell thereof, a reset transistor for resetting the photodiode and a first capacitor for holding a signal corresponding to a light quantity received by the photodiode, on a semiconductor substrate, wherein the solid image pick-up unit includes a second capacitor different from the first capacitor and connected to the gate of the amplification transistor, and the first capacitor has its one end connected to the photodiode through the transfer transistor and has the other end connected to the gate of the amplification transistor through the detection transistor, and the photodiode is connected to the reset transistor.
According to the present invention, there is provided a solid image pick-up unit having a unit cell laid out in a matrix two dimensional shape, by having a light receiving unit, an amplifying unit for amplifying a signal detected by the light receiving unit, a selecting unit for selecting a cell thereof, a resetting unit for resetting the light receiving unit and at least two storage units for storing a signal corresponding to a light quantity received by the light receiving unit, on a semiconductor substrate, wherein a selection of the storage units is carried out during an operation of the light receiving unit.
Further, according to the present invention, there is provided a method for driving a solid image pick-up unit having a unit cell laid out in a matrix two dimensional shape, by having a light receiving unit, a transfer unit for transferring a signal detected by the light receiving unit, an amplifying unit for amplifying a signal transferred by the transfer unit, a selecting unit for selecting a cell thereof, a resetting unit for resetting the light receiving unit and at least two storage units for storing a signal corresponding to a light quantity received by the light receiving unit, on a semiconductor substrate, wherein the method includes a first step of turning on the transfer unit and the resetting unit and injecting a charge into the light receiving unit and the storage units, a second step of discharging a charge injected into the storage units, a third step of transferring a signal detected by the light receiving unit to the storage units by keeping the transferring unit on, and a fourth step of reading out a charge stored in the storage units.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

Solid image pick-up unit and driving method therefor


An underwear system has a basic support structure comprising a waistband supporting a pair of leg straps that cross in the crotch region, and provide for openings at the front and rear, defined by the leg straps. The leg straps also define side openings on which leggings can be supported. Various attachments can be secured to the basic leg strap structure for protecting both female and male bodily parts.

The present invention relates to articles of apparel, and in particular, to underwear which are suitable for use by male and female wearers.
Men and women's undergarments are frequently restrictive and retain and contain the heat generated by the body causing dampness due to perspiration.
In addition, undergarments that elevate and press the male reproductive organs against the pubic area of the torso are believed to adversely influence the production and operation of sex hormones and anabolic metabolism with respect to the process of adaptation and acquisition of athletic fitness. Associated with this is lower sperm counts or less viable sperm being produced.


Provided is a multiple-input multiple-output (MIMO) data transmission method. A transmitter generates a transmission symbol by adding a parity symbol to a predetermined number of data symbols, generates a preprocessed symbol by multiplying the predetermined number of transmission symbols by a preprocessing matrix in units of blocks, selects a transmission antenna associated with a non-zero transmission symbol among preprocessed transmission symbols constituting the preprocessed symbol, and transmits the preprocessed symbol via the selected transmission antenna. A receiver receives a signal transmitted from the transmitter, estimates a preprocessed symbol and a transmission antenna index from the received signal, and restores the transmission symbols using the estimated preprocessed symbol and transmission antenna index.

1. Field of the Invention
The present invention relates generally to a Multiple-Input Multiple-Output (MIMO) communication system, and in particular, to a MIMO data transmission method for improving spectrum efficiency using a data multiplexing technique.
2. Description of the Related Art
The increasing demand for various broadband services such as high-speed Internet access and high-quality video services as well as the recent development of semiconductor and display device technology. There is ongoing research to more efficiently utilize the limited frequency resources for broadband wireless data transmission service in the 3rd generation (3G) and 4th generation (4G) mobile communication technology fields. Various techniques such as Spatial Division Multiple Access (SDMA), Space-Time Coding (STC), and Beam Forming based on a MIMO antenna system have been recently provided toward this end.
The MIMO system uses the STC technique to divide a channel into a plurality of independent spatial channels using multiple transmission antennas and multiple reception antennas and to secure the capacity.
A Vertical Bell Labs Layered Space Time (V-BLAST) algorithm, which is a well-known MIMO technique, can obtain spectrum efficiency of 20 to 40 bps/Hz for actual signal-to-noise ratio (SNR) range and bit error performance in an indoor rich scattering propagation environment. The high spectrum efficiency results from a multiplexing gain by parallel data transmission. The V-BLAST technique uses its unique detection algorithm different from the joint detection algorithm. That is, the detection algorithm of the V-BLAST technique first decodes the highest-power signal, and continuously decodes the highest-power signal among the signals remaining after canceling an influence of the decoded signal from each of the received signals. Such a decoding method is called optimum ordering (OR) and successive interference cancellation (SIC).
However, in order to increase the spectrum efficiency, the V-BLAST technique simultaneously transmits independent data streams via multiple transmission antennas, so a receiver suffers inter-channel interference (ICI) and the ICI increases with the number of the transmission antennas.
In addition, the V-BLAST technique is inoperable when the number of transmission antennas is greater than the number of reception antennas. Further, the V-BLAST technique cannot expect high performance even when the number of transmission antennas is equal to the number of reception antennas.

Method for transmitting data in a MIMO communication system

The University Court of The University of Edinburgh Old College