Static timing analysis attempts to exhaustively analyze all critical paths of a design. With ever decreasing geometries and ever increasing design complexity, manually identifying timing violations with standard static timing analysis can be very complex and time consuming. A static timing analysis tool can advantageously manage multiple runs having different modes and corners and automatically merge the results generated by the runs. The STA tool can perform the runs either in parallel or in series. Advantageously, the STA tool can save the full timing analysis generated by each run and then extract information from these saved results to form merged results for the design. These merged results can provide different levels of analysis coverage, supply path information at various levels of detail, allow selectable accessibility to information, and highlight propagation of timing changes/violations in the design.

1. Field of the Invention
The present invention relates to static timing analysis and in particular to distributed static timing analysis with merged results.
2. Description of the Related Art
Ignoring timing violations during design implementation can result in designs that fail to meet performance specifications or even fail in silicon. Given tight market windows and multi-million dollar re-spin costs, these design failures can be financially devastating to semiconductor companies. Therefore, design engineers are increasingly demanding techniques to identify timing violations in a design. One such technique, called static timing analysis, attempts to exhaustively analyze all critical paths of a design.
A limited number of static timing analysis (STA) runs, e.g. to provide a minimum time analysis and a maximum time analysis, can be sufficient for large process geometries and/or simple designs. FIG. 1A illustrates an exemplary run 100 in which an STA tool 102 receives a design (e.g. a gate-level description) and an STA set-up 101. STA tool 102 performs the static timing analysis and generates results 103 indicating any timing violations as well as coverage of the static timing analysis. At this point, a user could review results 103 and then attempt to fix the conditions that could be causing the timing violations, if present.
Unfortunately, with process geometries reaching 130 nm and below, gate counts exceeding 30 million, and designs growing in logic and core complexity, identifying timing violations with standard static timing analysis is rapidly becoming one of the most challenging problems for design engineers. Specifically, multiple runs of static timing analysis are typically required to take into account different modes (e.g. test mode, normal operation mode, power-down mode, etc.) as well as corners (e.g. process parameters including minimum and maximum temperature, minimum and maximum voltage, etc.).
FIG. 1B illustrates a flow wherein a user (e.g. a design engineer) 112 uses a design and a generic STA set-up 110 as well as potential set-ups 111 (indicating specific modes and corners available to user 112) to perform multiple runs 10A, 100B, and 100C. For example, in run 10A, STA tool 102A receives a design and an STA set-up 101A that indicates a specific mode and corner for analysis. STA tool 102A performs the static timing analysis and generates results 103A indicating any violating paths as well as coverage of the static timing analysis using that specific mode and corner. In run 100B, STA tool 102B considers design and STA set-up 101B (same design, but different mode and/or corner) to generate results 103B. Similarly, in run 100C, STA tool 102C considers design and STA set-up 101C (same design, but different mode and/or corner than those indicated in design and STA set-ups 101A and 101B) to generate results 103C. Note that STA tools 102A-102C are running independently. That is, STA tools 102A-102C could be running on the same computer or on different computers and could be running at the same time or at different times.
As STA tools 102A-102C complete their analysis, user 112 can review the results of the static timing analysis and perform debugging 113, as necessary, to mitigate timing violations. Of importance, user 112 must manually perform this user analysis/debugging 113 on results 103A-103C. Unfortunately, results 103A-103C typically form large, complex files in which each critical path in the design must be individually extracted for path profiling. Moreover, performing a comprehensive static timing analysis using available modes and corners can take many runs, e.g. 100-200 runs. Therefore, managing and/or merging the results from these runs can be very complex and time consuming.
Therefore, a need arises for a system and method of efficiently managing multiple static timing analysis runs using multiple modes/corners.

System and method for providing distributed static timing analysis with merged results


Methods for producing a chipped wood surfacing material having unusually high shock absorbing capabilities are provided. The chipped wood is processed in order to give it a very high shock absorbing quality. This invention also relates to chipped wood having these unusually high shock absorbing characteristics.

Children's playgrounds and other recreational areas present opportunities for physical activity and challenge. Such areas often have equipment such as swings, slides, climbing nets and ladders. Because children can be expected to use equipment in unintended and unanticipated ways, playground equipment and their surrounding fall zones should be as safe as possible. The fall zone is the area under and around the equipment where protective surfacing should be present. For example, the fall zone for a slide is at least six feet from the perimeter of the slide with a possible larger fall zone at the front exit of the slide chute, depending on the height of the slide.
The Consumer Product Safety Commission has long recognized the potential hazards that exist with the use of playground equipment. A Commission study of playground equipment-related injuries treated in U.S. hospital emergency rooms indicated that the majority of injuries resulted from falls from equipment. Tinsworth, Deborah Kale, and John T. Kramer, Playground Equipment-Related Injuries and Deaths, U.S. Consumer Product Safety Commission, Washington D.C. (April 1990). These injuries were primarily falls to the ground surface below the equipment rather than falls from one part of the equipment to another part of the equipment.
Several different surfacing materials are currently used in play areas. Examples of such surfacing materials include asphalt, concrete, hard packed dirt, grass and turf, unitary synthetic materials and loose-fill materials. Unitary synthetic materials are generally rubber mats or the like. Loose-fill materials are materials such as wood mulch, sand, gravel or shredded tires.
These various types of surfacing material have different degrees of shock absorbency. Obviously, a fall onto a hard surface is more likely to cause a serious injury than a fall onto a surface with a higher degree of shock absorbency. Head impact injuries from a fall on any kind of surface have the potential for being life threatening. The more shock absorbing a surface can be made, the less likely the injury will be severe or life threatening. It should be recognized, however, that depending on the circumstances of the fall, an injury may occur even if a highly shock absorbing surface material is used in a recreational area.
Biomedical researchers have developed a testing method to determine when a head impact injury may be life threatening. This test evaluates the shock absorbing properties of a recreational area surfacing material. The test is performed by dropping an instrumented metal headform onto a sample of the material and recording the acceleration/time pulse during the impact. Researchers have established that if the peak deceleration of the headform during impact does not exceed 200 times the acceleration due to gravity (200 g's), a life-threatening head injury is not likely to occur. Handbook for Public Playground Safety, U.S. Consumer Product Safety Commission, Washington D.C. (1991) (hereinafter "Handbook for Public Playground Safety").
The term "critical height" is used to describe the shock absorbing performance of a surfacing material. It is defined as the maximum height from which the instrumented metal headform, upon impact, yields a peak deceleration of no more than 200 g's when tested in accordance with the procedure described in American Society for Testing Materials, Standard Specification for Impact Attenuation of Surface Systems Under and Around Playground Equipment, ASTM F1292 (Philadelphia, Pa.; May 1991) (hereinafter "ASTM F1292").
Table 1 gives the critical heights for various surface materials. The tests were conducted in accordance with the ASTM F1292 procedure.
TABLE 1 ______________________________________ Critical Heights (in feet) of Tested Materials Compressed Uncompressed depth depth Material 6 inches 9 inches 12 inches 9 inches ______________________________________ Wood mulch 7 10 11 10 Double shredded 6 10 11 7 bark mulch Uniform wood 6 7 >12 6 chips Fine sand 5 5 9 5 Coarse sand 5 5 6 4 Fine gravel 6 7 10 6 Coarse gravel 5 5 6 5 ______________________________________
The Americans with Disabilities Act of 1990 ("ADA") prohibits discrimination on the basis of disability in employment, public services, transportation, telecommunications and public accommodations, including many services operated by private entities. 42 U.S.C. .sctn. 1210 et seq. It prohibits denying full and equal enjoyment of "goods, services, facilities, privileges, or accommodations" to disabled individuals with respect to any place open to the public. 42 U.S.C. .sctn. 12182. Existing structures, new construction, and alterations are all within the scope of the ADA's public accommodations provisions. Title III of the ADA includes within the definition of public accommodation: "a park, zoo, amusement park, or other place of recreation;" a school, including nursery schools; a day care center; and a gymnasium, health spa, or "other places of exercise or recreation." 42 U.S.C. .sctn. 12181. Public playgrounds, therefore, should be surfaced with a material so that physically challenged individuals may have access to playground equipment.
Hard surfacing material, such as asphalt or concrete allows recreational areas to be accessible to disabled individuals. These types of surfaces, however, are not otherwise suitable for use under and around playground equipment because of the high risk for injury due to a fall on the surface. Hard packed dirt is also not recommended because its shock absorbing properties can vary considerably depending on climatic conditions such as moisture content of the soil and temperature. It can be hazardous for children to play on very dry or frozen ground because of the lack of shock absorbance of these surfaces. Similarly, grass and turf are not recommended because their effectiveness in absorbing shock during a fall can be reduced considerably due to wear and environmental conditions. Handbook for Public Playground Safety.
Loose-fill materials such as sand and gravel are more shock absorbing than concrete or hard packed dirt, but these types of surfacing material have the disadvantage of inhibiting the maneuverability of wheelchairs, walkers, tricycles, bicycles, strollers and other wheeled items. Wheeled vehicles cannot easily move across sand and gravel. Further, the critical height values for sand and gravel materials decrease when the materials are compressed. Such compression can be expected from repeated use in high traffic areas of the playground. Also, moisture in sand can cause the critical height value for this material to decrease.
A disadvantage of unitary materials is that the material itself is very expensive. Unitary materials can be as much as ten times more expensive than the inventive surfacing material. Also, the ground underneath the synthetic material often must be made level and uniform before the unitary material is laid, which can be costly process. Further, this type of material may not drain well after storms because of puddles that may form on the surface. Another disadvantage is that synthetic materials can leach chemicals into the environment.


A voltage converter provided with charge pumps in which conventional rectifier diodes are replaced by output transistors. The output transistors at the same time act as voltage stabilizers. This also renders the ripple value of the voltage at the output terminal low when no smoothing capacitor, or a smoothing capacitor with a comparatively low capacitance value, is coupled to the output terminal.

1. Field of the Invention
The invention relates to a voltage converter comprising a first supply terminal, a second supply terminal, an output terminal; a first charge pump comprising a first capacitor with a first and a second electrode, first means for alternately coupling either the first electrode of the first capacitor to the first supply terminal and the second electrode of the first capacitor to the second supply terminal, or the second electrode of the first capacitor to the first supply terminal; a second charge pump comprising a second capacitor with a first electrode and a second electrode, second means for alternately coupling, in phase with the first means, either the first electrode of the second capacitor to the first supply terminal and the second electrode of the second capacitor to the second supply terminal, or the second electrode of the second capacitor to the first supply terminal; and a first unidirectional element coupled between the first electrode of the first capacitor and the output terminal.
2. Discussion of the Related Art
Such a voltage converter is known from European Patent 0,626,750 and serves for generating a DC voltage which is higher than the supply voltage of the voltage converter. The voltage converter may be used, for example, in integrated circuits in cases in which a portion of the integrated circuit requires a DC voltage of a higher value than the value of the supply voltage. The first means comprise a first transistor which is coupled between the first supply terminal and the first electrode of the first capacitor, and a first inverter whose output is coupled to the second electrode of the first capacitor and whose input is coupled to an output of a pulse generator. The second means comprise a second transistor which is coupled between the first supply terminal and the first electrode of the second capacitor, and a second inverter whose output is coupled to the second electrode of the second capacitor and whose input is coupled to the output of the pulse generator. The known voltage converter also comprises a third and a fourth charge pump with third and fourth means. The third and the fourth charge pump and the third and the fourth means are of identical construction as compared with the first and the second charge pump and the first and the second means, respectively. The third and the fourth means operate in counterphase to the first and the second means. During a second phase, the second charge pump supplies a DC voltage to a control electrode of a transistor of the fourth charge pump; during a first phase the fourth charge pump supplies a DC voltage to a control electrode of the second transistor. The first capacitor is charged in the first phase by means of a coupling of the first electrode of the first capacitor to the first supply terminal via the first transistor, and by means of a coupling of the second electrode of the first capacitor to the second supply terminal via the output of the first inverter. The potential at the first electrode of the first capacitor reaches a value which is substantially equal to the potential at the first supply terminal because in the first phase the potential at the control electrode of the first transistor is approximately twice as high as the potential at the first supply terminal, so that the first transistor also remains in the conducting state when the potential at the second electrode of the first transistor approaches the potential at the first supply terminal. In the second phase, the potential at the first electrode of the first capacitor is approximately twice as high as the potential at the first supply terminal owing to a coupling of the second electrode of the first capacitor to the first supply terminal via the output of the first inverter. The first transistor is non-conducting in the second phase. The rectifier diode transfers a quantity of charge from the first capacitor to a load which is coupled to the output terminal. The potential at the first electrode of the first capacitor drops as a result of this, so that a voltage ripple arises at the first electrode of the first capacitor. Since the voltage difference across the rectifier diode is constant by first-order approximation, the voltage ripple at the first electrode of the first capacitor causes a voltage ripple at the output terminal.
It is a disadvantage of the known voltage converter that a smoothing capacitor with a comparatively high capacitance value must be coupled to the output terminal for obtaining an output voltage with a low ripple value.


A battery drawer for a cordless telephone or other apparatus that operates from both regular AC power and battery power and that has a stand-by battery recharging system and associated battery charging circuit. The battery drawer is slidably mounted in a body and is configured to receive and hold at least one rechargeable battery. A combination ejector and electrical circuit maker is associated with the battery drawer. The combination ejector and electrical circuit maker establishes an electric circuit between the battery charging circuit and the at least one rechargeable battery when the battery drawer is in a closed state, operates to eject the battery drawer from the body, and electrically opens the electric circuit between the battery charging circuit and the at least one rechargeable battery when the battery drawer is in an open state. Increased safety is afforded to users by disconnecting the battery drawer from the charging circuit when the battery is replaced in the drawer.

1. Field of the Invention
The present invention relates generally to apparatus for holding, storing, and charging batteries.
2. Background of the Invention
Electronic equipment must receive a supply of power from a source of electricity. Most electronic equipment available today is powered directly from an alternating current (AC) source, such as a conventional wall outlet. Other, generally portable, devices are typically powered by batteries that must be periodically replaced after the batteries in use run down.
For convenience and economic reasons, rechargeable batteries are often employed in equipment that relies on batteries for power. Such batteries are well-known and come in several varieties, including Nickel-Cadmium(Ni-Cad) and Nickel metal Hydride (NiMH), to name just two. Such batteries are also available in a myriad physical configurations.
Some electronic equipment operates from both conventionally available AC power and battery power. For example, a cordless telephone typically includes a base station that is powered via an AC outlet and a cordless handset that is powered by a battery, or batteries (hereafter "batteries"). In most cordless telephones available today, the batteries that provide power to the cordless handset are rechargeable. When the cordless handset is mounted in the base station, the base station is configured to recharge the batteries in the cordless handset such that the batteries maintain the greatest possible amount of charge.
Despite the constant charging of the cordless handset batteries, it is not uncommon for the batteries to run down during prolonged use such that the handset can no longer be used. Some cordless telephone systems have, in view of this problem, standby batteries that are stored in the base station of the telephone and separately re-charged. Thus, when the cordless handset batteries run down, it is possible to simply swap the handset batteries with second, or stand-by, batteries that are stored and charged within the base station. The run down handset battery is then re-charged within the base station. In some cases, the batteries in the base station may also be used to provide stand-by power to the base station itself in the event of a power failure, wherein AC power is not available.
FIG. 1 is a schematic representation of selected portions of a conventional cordless telephone base station 100 and its interconnection with second or stand-by batteries. Base station 100 typically comprises a printed circuit board (PCB) 105 that includes electronic components that provide telephony functionality, along with assorted other features such as telephone number memory, caller ID functionality and display features. In addition, PCB 105 might also include a power supply 107, or at the very least, a means for distributing power, received from plug or transformer 110, which is plugged into a conventional AC wall outlet.
To support second, or standby, batteries, PCB 105 (or some other portion of the internal components of base station 100) includes a battery charging circuit 114 that includes output terminals 116a, 116b. Output terminals 116a, 116b are connected via wires 118 to a drawer 122 that includes terminals 120a, 120b.
Drawer 122 typically has a shape that is consistent with the type of batteries that base station 100 and a handset use. Drawer 122 is preferably spring loaded (e.g., via springs 125) and biased to be pushed toward the exterior of base station 100. Drawer 122 is held in place within the body of base station 100 by way of a user-movable latch (not shown).
To replace or swap batteries, a user simply displaces the latch, which causes the drawer to automatically and at least partially eject itself from base station. This state is shown in FIG. 1. The user then removes the batteries present within drawer 122 and inserts rundown batteries and closes drawer 122. While this seemingly simple battery replacement procedure would not be expected to be potentially dangerous, there is, in actuality, the possibility that a user could be unexpectedly electrically shocked. Specifically, terminals 120a, 120b are, even when drawer 122 is in its open state, in contact with battery charger output terminals 116a, 116b via wires 118. Since base station 100 may be a telephone apparatus, it is typically connected to outside telephone wires. In addition, base station 100 is connected to an AC source of power through plug or transformer 110. Accordingly, in the event of a lightning strike to the power lines or telephone lines, or in the event of a malfunction in base station 100, any of which could cause unexpectedly high voltage/current levels within the circuitry of PCB 105, it is possible that such unexpectedly high voltage/current levels could be transferred across wires 118 and be present at terminals 120a, 120b with which a user may easily come into contact when performing a battery replacement procedure.
In view of the possible danger associated with replacing a battery in known devices, there is a need for improved battery storage, holding and recharging systems.

Mechanically isolated battery charging apparatus


A hot beverage machine includes a heating unit having a fresh water intake. A fresh water line supplies fresh water to the fresh water intake of the heating unit. A residual fluid line is coupled to the fresh water intake of the heating unit through an on-off valve for conducting fluids to a collection container. A device for letting off residual steam and residual water from the heating unit includes a heat-exchanging and heat-storing condenser having a residual line section coupled to the residual fluid line, a fresh water line section coupled into the fresh water line and a heat storing medium that is connected for conducting heat between the residual line section and the fresh water line section.

The invention relates to a device for letting off residual steam and residual water from the heating unit of a hot beverage machine, for example a coffee machine.
With known fluid systems in coffee machines and other hot beverage machines, it is generally desirable to remove any residual water in the heating unit which remains after the coffee extraction or the hot water release. Once the machine is turned off, such residual water is vaporized into steam as a result of existing residual heat or is present in the form of residual water and/or flash water, and is allowed to collect in a collection container that is generally installed inside the coffee machine. The same steps are taken if, following the process of generating steam to supply to a steam nozzle or a frothing nozzle, the heating unit is cooled down with fresh water until it reaches a temperature for preparing coffee. That is to say, unused steam and, if necessary, hot water are also released into the collection container. The steam generated during this operation is also referred to as residual steam or flash steam since its pressure is reduced as compared to the steam generated during the operation, in particular through opening a residual fluid line and shutting down a water pump which otherwise pumps fresh water into the heating unit that is typically designed as a flow-through heating unit.
A corresponding device, known from practical operations, for letting off residual steam, comprises a residual fluid line which is connected via an on-off valve to the heating unit, so as to conduct fluids, and which leads to a collection container in the coffee machine. The disadvantage of this device is that some of the residual steam within the coffee machine can escape uncontrolled and can thus affect components inside the coffee machine, particularly the electronic components. These components can be damaged and/or can fail completely and undesirable micro-biological cultures can form even faster. The removal of the residual steam and residual water outside of the housing generally was not planned because of the related danger of scalding.

Device for letting off residual steam and water from the heating unit of a hot beverage machine


A MUSE sound decoder detects a broadcasting/non-broadcasting identification flag included in the control signals in an applied MUSE signal to determine whether the MUSE signal is broadcasted or non-broadcasted. The MUSE sound decoder further includes a frame synchronization protection circuit for protecting frame synchronization over a predetermined frame synchronization protection time period when the frame synchronization pattern is not detected at the proper timing. The frame synchronization protection circuit sets the frame synchronization protection time period to a long time period when the MUSE signal is determined to be a broadcasted MUSE signal, and to a short time period when the MUSE signal is determined to be a non-broadcasted MUSE signal. Appropriate muting of a sound signal can be carried out according to the condition of the received MUSE signal.

1. Field of the Invention
The present invention relates to sound decoders, and more particularly, to a sound decoder for decoding, for example, a MUSE sound signal of NI-DPCM (Nearly-Instantaneous Differential Pulse Code Modulation) format that is multiplexed in a high definition television signal of MUSE (Multiple Sub-Nyquist Sampling Encoding) system format.
2. Description of the Background Art
In a high definition television signal of MUSE system (referred to as a MUSE signal hereinafter) proposed by Nippon Hoso Kyokai (NHK), a MUSE sound signal of NI-DPCM format (referred to as an NI-DPCM sound signal hereinafter) is multiplexed within the vertical blanking period of a MUSE video signal. Therefore, a MUSE sound decoder is required for extracting and decoding the NI-DPCM sound signal from the MUSE signal in receiving and reproducing such MUSE signals.
A typical MUSE signal television receiver generally contains a MUSE sound decoder for extracting and decoding a NI-DPCM sound signal that is multiplexed in a MUSE signal transmitted via a broadcasting satellite and received by an antenna and a baseband signal (BS) tuner, or an externally supplied MUSE signal reproduced from a recording medium by a reproduction equipment such as a MUSE disk player or a MUSE-VCR. Such a MUSE sound decoder is incorporated not only in MUSE signal television receivers, but also in various video equipments that process MUSE signals, and is also used as a unit in various environments wherein MUSE signals are processed. Such a MUSE sound decoder is disclosed in, for example, Japanese Patent Laying-Open No. 2-11076.
Prior to the description of a MUSE sound decoder, the principle of forming an NI-DPCM sound signal to be multiplexed in a transmission MUSE signal will be described schematically. The formation of such an NI-DPCM sound signal is described in detail in IEEE TRANSACTIONS ON BROADCASTING December 1987, Volume BC-33, No. 4, pp. 188-196 "Sound Transmission for HDTV Using Baseband Multiplexing into MUSE Video Signal" by T. Takegahara et al.
FIG. 1 is a schematic block diagram of a typical structure of a MUSE sound encoder for forming an NI-DPCM sound signal. Referring to FIG. 1, an analog sound signal supplied from a sound signal source (not shown) via an input terminal 1 is converted into a digital sound signal by an A-D converter 2 (A-mode sound data: sampling frequency 32 kHz, number of quantizing bits 15 bits/B-mode sound data: sampling frequency 48 kHz, number of quantizing bits 16 bits). This digital sound signal is provided to an NI-DPCM encoder 3 where the A-mode sound data of 15 bits and the B mode sound data of 16 bits are compressed to differential data of 8 bits (8 ranges) and 11 bits (6 ranges), respectively. The details of NI-DPCM encoding is described in the above mentioned document, and will not be described here.
The NI-DPCM sound signal provided from NI-DPCM encoder 3 is word-interleaved in the sample word direction in a word interleave circuit 4 to be supplied to one input of an adder 5. An error correction code generated from an error correction code generating circuit 6 is supplied to the other input of adder 5 to be multiplexed into the NI-DPCM sound signal. Following a BCH error correction process by a BCH error correction circuit 7, the signal is bit-interleaved by a bit interleave circuit 8. The above mentioned interleave and error correction processes are described in the aforementioned document, and will not be described here. The bit-interleaved NI-DPCM sound signal is supplied to one input of an adder 9. A frame synchronizing signal having a predetermined bit pattern of 16 bits and a control code of 22 bits from a signal generating circuit 10 is applied to the other input of adder 9 to be multiplexed into the NI-DPCM sound signal. As a result, a sound data bit stream of 1.35 Mbit/seconds is provided at a frame frequency of 1 kHz from adder 9.
FIG. 2 shows the bit arrangement of 1 frame (1350 bits) in A-mode, for example. FIG. 3 shows the bit allocation on a bit interleave matrix. The head frame synchronizing signal of each frame shown in FIGS. 2 and 3 has a fixed bit pattern of 16 bits of "0001001101011110".
As shown in FIG. 1, the NI-DPCM sound signal of 1.35 Mbit/sec provided from adder 9 is frame-interleaved in an inter-frame interleave circuit 11 to be provided to a binary to ternary conversion circuit 12, where the signal is converted into data of ternary format. The ternary data provided from binary to ternary conversion circuit 12 is converted into ternary data having sampling rate of 12.15 MHz in a time compression circuit 13 to be provided to a sampling frequency conversion circuit 14. The NI-DPCM signal has the sampling rate converted from 12.15 MHz to 16.2 MHz in sampling frequency conversion circuit 14 to be supplied to one input of an adder 15. The other input of adder 15 is supplied with a digital MUSE video signal having sampling rate of 16.2 MHz from a video signal source (not shown), whereby the above-described NI-DPCM sound signal is multiplexed within the vertical blanking period thereof. As a result, a MUSE signal of 16.2 MHz is provided from adder 15 to be output via a terminal 16. Thus, a MUSE signal provided from a MUSE encoder is converted into an analog signal to be transmitted by a broadcasting radio wave, or to be recorded on a recording medium such as an optical disk or a magnetic tape.
FIG. 4 is a block diagram showing a structure of a conventional MUSE sound decoder for decoding a sound signal from a MUSE signal that is formed in the above-described manner.
Referring to FIG. 4, an analog MUSE signal received via a broadcasting satellite or reproduced from a recording medium by a reproduction equipment is supplied to an input terminal 21. The analog MUSE signal is then converted into a digital signal by an A-D converter 22 to be provided to a sound signal gate 23. The NI-DPCM signal multiplexed in the vertical blanking period of the MUSE signal is separated by sound signal gate 23 to be provided to a sampling frequency conversion circuit 24.
The NI-DPCM signal of ternary format has the sampling rate converted from 16.2 MHz to 12.15 MHz by sampling frequency conversion circuit 24 to be provided to a ternary to binary conversion circuit 25. The ternary signal of 12.15 MHz is converted into a binary signal by ternary to binary conversion circuit 25 to be provided to a time expansion circuit 26.
The binary signal is converted into a baseband signal of 1.35 Mbit/sec by time expansion circuit 26 to be provided to an interframe de-interleave circuit 27. Since the provided signal is interframe-interleaved by the aforementioned inter-frame interleave circuit 11 (FIG. 1), this signal is de-interleaved by interframe de-interleave circuit 27 to have the proper frame order. Then, the signal is provided to a bit de-interleave circuit 28 and a frame synchronization detection circuit 34.
Since the NI-DPCM signal provided to bit de-interleave circuit 28 is bit-interleaved by the aforementioned bit interleave circuit 8 (FIG. 1), this signal is bit de-interleaved so as to be restored to a signal arranged in the sample word direction. The bit de-interleaved NI-DPCM sound signal, produced by circuit 28, provided to an error correction circuit 29, where error correction is carried out according to a BCH code. Then, the signal is provided to a word de-interleave circuit 30. Since this signal is interleaved in the sample word direction by the aforementioned word interleave circuit. 4 (FIG. 1), this word interleaved signal applied to circuit 30 is word de-interleaved so as to remove the interleave of the sample word direction thus restoring the word interleaved signal to a signal with the original one frame.
The output of word de-interleave circuit 30 is provided to an NI-DPCM decoder 31 to be restored to a digital sound signal. The principle of decoding by an NI-DPCM decoder is described in detail in the aforementioned document. The digital sound signal provided from NI-DPCM decoder 31 is converted into an analog signal by a D-A converter 32, and from there, provided to an output terminal 37, via a mute circuit 33.
The output of interframe de-interleave circuit 27 is also provided to a frame synchronization detection circuit 34 to detect a frame synchronizing pattern of 16 bits for each frame of the NI-DPCM sound signal. In other words, if the 16 head bits of the NI-DPCM sound signal of each frame is determined, by frame synchronization circuit 34, to exactly possess a bit pattern of "0001001101011110," a frame synchronization detection flag is generated and provided to a frame synchronization protection circuit 35.
In an abnormal case where frame synchronization detection circuit 34 determines that the frame synchronization pattern is temporarily missing, or w an erroneous detection is made over a short period, frame synchronization protection circuit 35 protects the frame synchronization by generating an internal frame signal of the proper frame frequency over a predetermined frame synchronization protection time period. If the above described abnormal state still remains even after the lapse of the aforementioned predetermined frame synchronization protection time period, frame synchronization protection circuit 35 provides a mute signal to a mute circuit 33 to mute the analog sound signal provided from D-A converter 32. The mute of the output sound signal is canceled by the proper detection of a frame synchronizing pattern by frame synchronization detection circuit 34. Various timing signals used in the decoder are generated even during the above described abnormal state from a timing signal generating circuit 36 according to an internal frame signal provided from frame synchronization protection circuit 35.
When a MUSE signal is transmitted as a broadcasting radio wave, the signal to noise (S-N) ratio is often degraded due to an influence of an external environment, such as the weather. Although error corrections by BCH codes and various interleaves are possible for the transmitted sound data, per se, as described in association with FIG. 1, there is no error correction provided for the frame synchronizing pattern of 16 bits located at the head of each frame data. Therefore, there may be partial portions missing from the frame synchronization pattern, having a bit length of 16 bits, due to degradation of S-N ratio. Because frame synchronization detection circuit 34 of the MUSE sound decoder generates a frame synchronization detection flag only when a complete frame synchronizing pattern of 16 bits is received, and does not generate a frame synchronization detection flag even if one bit is missing, there will be cases where the frame synchronization is frequently not detected in the case of degradation of S-N ratio due to aggravation of the radio wave by the weather. If the predetermined frame synchronization protection time period for the generation of the aforementioned mute signal is reduced, and set to a time period of 5 frames, for example, the mute will be applied frequently at a short cycle and even for sufficiently audible output sound signals which include some noise due to S-N ratio degradation, thereby resulting in disagreeable sound.
If the frame synchronization protection time period is lengthened, for example to 64 frames, for the purpose of suppressing frequent mute of such sound output, a problem is encountered that will be described hereinafter. A reproduced MUSE signal, provided from a reproduction equipment such as a MUSE disk player or a MUSE-VCR, has a constant S-N ratio, so that the abnormal state of not detecting frame synchronization owing to continuous S-N ratio degradation in a broadcasting radio wave is unlikely to occur. However, dropout easily occurs in the reproduced MUSE signal due to variation in the mechanical system of the reproduction equipment. Also, sound data as well as the synchronizing signal of a MUSE video signal may be missing completely over several frames at the time-of special reproduction or halt. In these cases, a significant amount of noise is generated. Although dropout of a relatively short time period can be compensated, owing to various error correction processes applied to the NI-DPCM sound signal, as described above, dropout over a long time period can not be compensated. It is effective to apply mute to sound output for such a missing signal. However, a long frame synchronization protection time period (for example, a time period of 64 frames) results in the generation of a substantial amount of noise since muting of the sound output is not immediately effective when dropout occurs in a sound signal.

Broadcast/non-broadcast MUSE signal sound decoder with a variable protection period


A portable terminal with a position-variable display comprising a main body for inputting information and controlling communication, a folder coupled to the main body, a display unit rotationally disposed on the folder for displaying image information, a rotating means for providing angular rotation of the display unit along a plane of the folder, and a sliding means for moving the display unit in a direction along a length of the portable terminal.

1. Field of the Invention
The present invention relates to a portable terminal, and more particularly to a portable terminal with a position-variable display capable of producing images in a wide format and a long format.
2. Description of the Related Art
Generally, a portable terminal is a communication device allowing a user to transmit and receive a voice signal to and from another user anywhere in the world. Because information and communication technologies have rapidly developed, range of uses for portable terminals have expanded. For example, portable terminals are capable of accessing the Internet and receiving television (TV) signals. They are also capable of photographing still or dynamic objects and transmitting and receiving photographed images to and from another user. Due to the various functions of the portable terminal, technology for displaying image information has become important. Therefore, research and development of image displaying technologies has been active.
Referring to FIG. 1, a portable terminal comprises a main body 100 for inputting information and controlling communication, a folder 200 having a display 210 for outputting the information as an image, a hinge coupling module 300 for hinge-coupling the folder 200 to the main body 100 so that the folder 200 may be folded onto the main body 100, a rotating module 400 disposed at the hinge coupling module 300 and the folder 200 for rotating the folder 200 around an axis lying parallel with the length of the folder 200, a microphone unit 110 mounted on the main body 100, and a speaker unit 220 mounted on the folder 200.
The main body 100 comprises a main body casing 120 forming the outer appearance of the main body 100, a plurality of function keys 130 arranged on a surface of the main body casing 120, and circuit components mounted inside the main body casing 120. A battery 140 is detachably coupled to a side of the main body 100. The folder 200 comprises a folder casing 230 for externally exposing the display 210 and a plurality of circuit components mounted inside the folder casing 230. The speaker unit 220 is mounted on the folder casing 230 at the upper portion of the display 210.
The display 210 may be a liquid crystal display (LCD) screen formed in a rectangular shape, wherein the length direction of the display 210 is identical to the length direction of the folder 200. The hinge coupling module 300 has a hinge axis for coupling the main body 100 to the folder 200. A camera 150 is mounted on the hinge axis.
When the portable terminal is not in use, but is carried by the user, the folder 200 may be folded onto the surface of the main body 100 where the function keys 130 are installed. When the user uses the portable terminal, the user opens the folder 200 from the main body 100. After opening, the folder 200 may be angularly rotated by using the hinge coupling module 300 disposed at one side of the main body 100 as an axis, wherein the length direction of the angularly-rotated folder 200 is positioned approximately on the same line as the length direction of the main body 100. In addition, the length direction of the display 210 coupled to the folder 200 is also positioned approximately on the same line as the length direction of the main body 100. When the user holds the main body 100 and watches the display 210 so that the front surface of the main body 100 can be positioned in front of the user, an image displayed on the display 210 is outputted on a long screen having a relatively smaller horizontal length than a vertical length.
When the user transmits and receives voice information to and from another user, the user uses the microphone unit 110 mounted on the main body 100 and the speaker unit 220 mounted on the folder 200. The speaker unit 220 can provide voice information such as songs or bell sounds.
Additionally, when the user watches television or observes other image information, such as a movie through the Internet, the user may select a wide screen format having a relatively larger horizontal length than a vertical length for vividness of images. In such a case, when the folder 200 is folded onto the main body 100, the folder 200 may first be rotated from the main body 100 by approximately 90° using the hinge coupling module 300 as an axis. Subsequently, the folder 200 may then be rotated by approximately 90° using the rotating module 400 as an axis.
The front surface of the folder 200 rotated by approximately 90° using the rotating module 400 is positioned approximately parallel to the side surface of the main body 100, wherein the length direction of the folder 200 is approximately perpendicular to the front surface of the main body 100. In addition, the display 210 fixedly coupled to the folder 200 is positioned approximately parallel to the side surface of the main body 100, wherein the length direction of the display 210 is approximately perpendicular to the front surface of the main body 100.
Accordingly, when the user holds the main body 100 so that the side surface of the main body 100 is positioned in front of the user, the length direction of the display 210 is positioned in the horizontal direction of the user. An image outputted to the display 210 is in a wide format having a relatively larger horizontal length and a vertical length, which is suitable for the position of the display 210.
The main body 100 comprises a sensing module for sensing the position of the folder 200 and an image output corrector for changing the position of the output image according to the position of the folder 200 sensed by the sensing module. For example, when the position of the folder 200 is changed from a long format to a wide format or vice versa, the position of the output image is changed according to the changed position of the folder 200. Therefore, a slanted, inverse or otherwise skewed screen image is never displayed on the display 210 despite having a changed position of the folder 200. Thus, the user can conveniently enjoy the image.
Furthermore, when the user inputs still or dynamic image information using the camera 150, the user can input wide format image information having a relatively larger horizontal length than a vertical length by positioning the length direction of the display 210 in the horizontal direction.
As described above, when the user watches a movie or television programming through the portable terminal, the user can watch a wide format image having a relatively large horizontal length as well as a long format image having a relatively large vertical length, and is thus provided with better services.
However, operation of the wide format can be problematic in the portable terminal. For example, in order to view a wide format image, the folder 200 which the display 210 is fixedly coupled to must first be rotated by approximately 90° using the hinge coupling module 300 as an axis and then rotated by approximately 90° using the rotating module 400 as an axis. Further, the user must rotate the main body 100 by approximately 90° so that the side surface of the main body 100 is positioned in front of the user in order to have an unobstructed view of the screen.
Another problem arises because the portable terminal cannot stand alone while in the wide format configuration. Hence, while the user watches the wide screen, the user must hold the portable terminal. This causes discomfort in the user, especially when the user is watching a movie or observing an image for a lengthy amount of time. Accordingly, if the user happens to drop the portable terminal due to fatigue, components of the portable terminal will be damaged because of the portable terminal's relatively low structural integrity resulting from the folder 200 being positioned vertically to the main body 100. Therefore, the user's enjoyment of the portable terminal is lessened.

Portable terminal with position-variable display and method


A semiconductor device package is provided with integrated antenna for wireless applications. The semiconductor device package comprises a substrate including a semiconductor chip mounted thereon; a protective layer covering the semiconductor chip; a metal pattern mounted on the protective layer; and a first connective member connecting the semiconductor chip and the metal pattern. According to this configuration, the semiconductor device package is capable of being easily manufactured while minimizing the electrical distance between the metal pattern for use as an antenna and the semiconductor chip.

1. Field of the Invention
The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package in which a metal pattern and a semiconductor chip may be easily connected, and a method of manufacturing the same.
2. Description of the Related Art
As a frequency resource for a next generation information communications service, a frequency in the millimeter wave band, a high frequency resource of 30 GHz or more, has been actively studied.
This frequency in the millimeter wave band may transfer a large amount of information at high speed using wideband characteristics. In addition, the frequency in the millimeter wave band does not suffer interference from other frequencies in adjacent geographical areas, due to significant electrical wave attenuation in the air. Therefore, the frequency in the millimeter wave band is advantageous in that it may be re-used.
As a result, the development of an information communications service and system using the frequency in the millimeter wave band, as well as and research into, and development of, various components required for the information communications service and system have been actively conducted.
Meanwhile, in a communications device for the millimeter wave band, an electrical connection distance between an antenna and a semiconductor chip is very important. That is, in the communications device for the millimeter wave band (particularly the 60 GHz band), as a distance between the antenna and the semiconductor chip increases, radiation loss of an antenna increases. Therefore, the semiconductor chip and the antenna may be disposed as closely as possible and then be electrically connected.
To this end, in the communications device according to the related art, an antenna is disposed at a position significantly adjacent to a semiconductor package in which a semiconductor chip is embedded, and the antenna and the semiconductor package are connected at the shortest possible distance.
However, in the case of the related art, a process of separately manufacturing each of the semiconductor package and the antenna and then mounting both thereof on a substrate to thereby be electrically connected needs to be performed. Therefore, a manufacturing process may be complicated.
Further, in the case of the related art, an antenna power feeding structure is complicated, such that a manufacturing process is difficult. As a result, analysis of an influence on a process error may be difficult.
Therefore, the development of a new type of semiconductor package in which an antenna and a semiconductor chip may be disposed as closely as possible has been urgently required.

Semiconductor device package with integrated antenna for wireless applications


A coffee filter pack apparatus has a coffee filter bag formed with a plurality of coffee filter sheets attached together to form a plurality of enclosed spaced therein, each enclosed spaced having a plurality of measured amounts of predetermined ground coffee. One of the coffee filter sheets has indicia thereon to indicate the direction of flow of heated water through the coffee bag during brewing of the coffee. A method of making a coffee filter bag includes the steps of selecting predetermined amounts of first and second ground coffee, closing each into attached first and second coffee filter bags, and labeling the combined coffee filter bags to indicate the direction of flow of heated water therethrough.

The present invention relates to a coffee filter pack and especially to a coffee filter pack designed to improve the taste of coffee made in an auto-drip coffee maker.
In the past, it has been common to provide both coffee and tea leaves in filter bags. In the case of tea leaves, the bags are typically provided with a string with a predetermined amount of tea leaves in a filter bag which is then dangled in a cup of hot water for making hot tea. In the case of coffee, filter bags are typically a pancake-shaped disc made of two coffee filters enclosing a predetermined amount of ground coffee therebetween which can be placed in an auto-drip coffee maker. The heated water is dripped onto the coffee filter pack and into a coffee pot. This type of filter pack has the advantage of having the ground coffee premeasured and avoids having to place a separate filter within an auto drip coffee maker. It also allows for easy cleanup since the ground coffee remains stay within the filter pack so that the filter pack can be easily removed and thrown away. Coffee filter packs are typically made in an amount so that one, two, or three coffee filter bags can be placed within the auto drip coffee maker for making the coffee stronger or weaker as desired.
The coffee filter pack of the present invention includes dual coffee filter packs with different amounts and different types of coffee within each divided filter pack section. The coffee pack identifies the top from the bottom of the pack to allow the coffee to filter in one direction of travel to produce the desired result.
A coffee filter pack apparatus has a coffee filter bag formed with a plurality of coffee filter sheets attached together to form a plurality of enclosed spaced therein, each enclosed spaced having a plurality of measured amounts of predetermined ground coffee. One of the coffee filter sheets has indicia thereon to indicate the direction of flow of heated water through the coffee bag during brewing of the coffee. A method of making a coffee filter bag includes the steps of selecting predetermined amounts of first and second ground coffee, closing each into attached first and second coffee filter bags, and labeling the combined coffee filter bags to indicate the direction of flow of heated water therethrough.


A semiconductor device includes an N-well arranged in the principal surface of a P-type semiconductor substrate, an N.sup.+ well contact arranged in the principal surface of the N-well, and an N.sup.+ buried region arranged to the bottom of the N-well.

The present invention relates generally to semiconductor devices and more particularly to complementary insulated-gate field-effect transistors (CMOSs).
One of the conventional semiconductor devices is disclosed, e.g. in JP-A 58-201353. This semiconductor device is constructed such that, when excessive surge or electrostatic discharge (ESD) voltage is applied to an input/output terminal, the existence of an N.sup.+ buried region formed to the bottom of an N-well contributes to a reduction in the current amplification factor h.sub.PE of a PNP bipolar transistor, and a shunt resistance between the emitter and the base thereof. This results in restrained latchup so called.
However, the above semiconductor device has the following problems:
First, due to reduced capacity of the PNP bipolar transistor to bypass ESD current, ESD current is concentrated on one of the pull-up and pull-down diodes in a protective element, resulting in lowered breakdown strength of the semiconductor device with respect to ESD current;
Second, due to high-temperature annealing of the semiconductor device during a fabrication process, N-impurities within the N.sup.+ buried region can be diffused in the upper portion thereof to increase the surface concentration of N-impurities in the N-well. This reduces breakdown voltage of a P-channel insulated-gate field-effect transistor (PchMOSFET) formed in the principal surface of the N-well, resulting in difficult control of a threshold value thereof; and
Third, due to reduced on-resistance of a lateral power transistor formed in another N-well, the N.sup.+ buried region cannot show sufficiently high concentration of N-impurities. If two N.sup.+ buried regions are formed separately, the fabrication process of the semiconductor device will be complicated, resulting in increased manufacturing cost.
It is, therefore, an object of the present invention to provide semiconductor devices which show improved anti-latchup characteristic and sufficiently reduced on-resistance of a power transistor with cheaper manufacturing cost.

Complementary insulated-gate field-effect transistors having improved anti-latchup characteristic


A glove according to the present invention comprises a main body wearable with respect to a hand, the main body comprising finger parts, a back-of-hand part connected to the finger parts, a wrist part connected to the back-of-hand part and serving to protect a wrist, and impact alleviating members for alleviating an impact provided in the finger parts and the back-of-hand part and on a back-of-hand side of the wrist part, wherein the impact alleviating members provided in the finger parts continuously extend from base parts of the fingers through fingertips and has such a flexibility that can follow a bending action of the fingers.

1. Field of the Invention
The present invention relates to a glove, more particularly to gloves used in lacrosse, ice hockey, baseball and the like.
2. Description of the Related Art
Gloves used in lacrosse are necessarily designed to hold a stick with a strong grip in order to receive and throw a ball with a handle of the stick whose edge is provided with a net portion held with hands. Further, the glove is required to have a superior impact resistance with respect to the hands because the sticks used in the game quite often clash with one another in order to steal the ball, and a strong impact from the sticks used by a competing team is thereby applied to the hands.
Therefore, a thick impact alleviating member serving to absorb and alleviate any impact imposed on the hands is inserted mainly on a back-of-hand side of the glove. The impact alleviating member is formed from a light foamed material made of resin and provided around a wrist part, in a back-of-hand part, and on the back-of-hand side of finger parts of the glove. A palm side of the glove is formed from a relatively thin outer skin so that the stick can be firmly held. The palm-side outer skin is provided with a mesh fabric or the like so that generated sweat can be effectively released.
The impact alleviating member is provided on the back-of-hand side of the finger parts except for parts corresponding to joints of the fingers so that the stick can be firmly held. Therefore, the fingers can be easily bent at the joints.
Because of the foregoing structure, the hands are inevitably vulnerable to the impact when the joint parts are subjected to the competitor's attacks from the sticks intensely clashing with one another in stealing the ball. As a result, the players' hands may be wounded or fractured.


A paper feeding sensor mounted in the paper shredder is composed of a microswitch and a detection rod capable of triggering the microswitch so as to actuate two cutters of the paper shredder. The detection rod is received in a receiving cell of the paper guiding grid plate of the paper shredder such that the detection rod is pushed to trigger the microswitch by a paper which is fed into the receiving cell of the paper guiding grid plate.

The conventional paper shredder is generally composed of a microswitch or LED (light-emitting diode) electronic eye located at the paper feeding port of the paper shredder. The paper shredder is started as soon as the microswitch or electronic eye has detected the feeding of the paper to be shredded. Such a conventional sensing device as described above is capable of sensing the feeding of paper as soon as the front edge of the paper has entered the paper feeding port, thereby triggering the shredding action of the paper shredder. On the other hand, the conventional sensing device ceases to function as soon as the rear edge of the paper has passed the sensing device, thereby resulting in an immediate termination of the shredding action of the paper shredder. As a result, the rear end of the paper remains intact. In order to overcome such an operational deficiency as described above, the conventional paper shredder is provided with a delay circuit capable of cooperating with the microswitch or LED electronic eye in such a way that the operation of the cutter of the paper shredder is prolonged for 2-3 seconds so as to ensure that the paper is shredded in its entirety. However, the addition of the delay circuit results in an increase in the cost of the paper shredder.

3F, No. 29, Lane 80, Sec. 1, DWU HWU S. Road


A network device includes a network interface, a host interface and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to connect to a host including a processor. The processing circuitry is configured to receive from the processor, via the host interface, a notification specifying an operation for execution by the network device, the operation including (i) multiple tasks that are executable by the network device, and (ii) execution dependencies among the tasks in response to the notification, the processing circuitry is configured to determine a schedule for executing the tasks, the schedule complying with the execution dependencies, and to execute the operation by executing the tasks of the operation is accordance with the schedule.

Operation of computers in advanced computing environments such as High-Performance Computing (HPC), Artificial intelligence (AI) and Machine Learning (ML) often involves fast execution of multi-task operations such as collective operations. A commonly used Application Programming Interface (API) for initiating collective operations in HPC environment is specified by the Message-Passing Interface (MPI) forum in "MPI: A Message-Passing Interface Standard," version 2.2, Sep. 4, 2009. Version 1.1 of the MPI standard was introduced in June, 1995.
Handling collective operations in HPC and other environments is known in the art. For example, U.S. Pat. No. 8,811,417 describes a Network Interface (NI) that includes a host interface, which is configured to receive from a host processor of a node one or more cross-channel work requests that are derived from an operation to be executed by the node. The NI includes a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the cross-channel work requests via the host interface, and to execute the cross-channel work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.

Offloading execution of a multi-task parameter-dependent operation to a network device


A computer is programmed to receive data concerning a current location of a vehicle, a plurality of gas prices at a plurality of gas stations, and a plurality of locations, one location for each of the plurality of gas stations. The computer is programmed to determine a first gas station of the plurality of gas stations based on the current location of the vehicle, the plurality of gas prices, and the plurality of locations such that driving the vehicle from the current location to the first gas station and then to a final destination requires a first cost of gas, which is less than or equal to the cost of gas of driving the vehicle from the current location to any other gas station and then to the final destination. The data concerning the current location of the vehicle may be received from a global positioning system.

When an individual wants to purchase gasoline or gas for their car, they want to get the best price for the gas. However, often the cheapest gas stations are located at a great distance from where the individual's vehicle is located. Currently there are insufficient techniques for determining the most cost effective gas station to buy gas from.

Dynamic location based cost minimization


An article is coated with a multi-layer coating having a bronze color. In a preferred embodiment, the coating comprises a nickel or polymer basecoat layer, and a color and protective stack layer comprised of layers of carbon-rich refractory metal or refractory metal alloy carbonitride alternating with layers of nitrogen-rich refractory metal or refractory metal alloy carbonitride. In another embodiment, the alternating layers of the color stack layer may comprise layers of carbon-rich refractory metal carbides or carbon-rich refractory metal alloy carbides alternating with layers of nitrogen-rich refractory metal nitrides or nitrogen-rich refractory metal alloy nitrides.

It is currently the practice with various brass articles such as faucets, faucet escutcheons, door knobs, door handles, door escutcheons and the like to first buff and polish the surface of the article to a high gloss and to then apply a protective organic coating, such as one comprised of acrylics, urethanes, epoxies and the like, onto this polished surface. This system has the drawback that the buffing and polishing operation, particularly if the article is of a complex shape, is labor intensive. Also, the known organic coatings are not always as durable as desired, and are susceptible to attack by acids. It would, therefore, be quite advantageous if brass articles, or indeed other articles, either plastic, ceramic, or metallic, could be provided with coating which provided the article with a decorative appearance as well as providing wear resistance, abrasion resistance and corrosion resistance. It is known in the art that a multi-layered coating can be applied to an article which provides a decorative appearance as well as providing wear resistance, abrasion resistance and corrosion resistance. This multi-layer coating includes a decorative and protective color layer of a refractory metal nitride such as a zirconium nitride or a titanium nitride. This color layer, when it is zirconium nitride, provides a brass color, and when it is titanium nitride provides a gold color.
U.S. Pat. Nos. 5,922,478; 6,033,790 and 5,654,108, inter alia, describe a coating which provides an article with a decorative color, such as polished brass, provides wear resistance, abrasion resistance and corrosion resistance. It would be very advantageous if a coating could be provided which provided substantially the same properties as the coatings containing zirconium nitride or titanium nitride but instead of being brass colored or gold colored was bronze, particularly antique bronze, colored. The present invention provides such a coating.


A technique for managing address translation storage buffers (TSBs) supports multiple pools of different TSB sizes and dynamically assigns a process to its own TSB of the proper size as the needs of the process change. A process is assigned a small TSB and the system migrates the process to a larger TSB if needed. One method includes the steps of identifying sizes of TSBs to support, allocating a TSB pool in memory with these sizes, selecting an appropriately sized TSB for a process, and migrating that process to a larger size should the process require more memory. A second method allocates a TSB pool by determining an appropriate size for the TSB pool, determining sizes of TSBs to support, allocating memory for the pool and initializing status block for each size of TSB. A third method selects an appropriate TSB for a process by selecting a smallest supported size of a TSB from the pool. A fourth method migrates a process to a larger size by determining whether the current TSB is of an inappropriate size, selecting a larger TSB size, invalidating the previous TSB, and selecting a TSB of the new size from the TSB pool. Variations on these methods require that the memory spaces shared by the TSBs of different sizes are coexistent, require that the TSBs be stored in virtual space or that entries in the translation look-aside buffer (TLB) be reserved for a separate user TSB and kernel (system) TSB.

Within a computer system, the power and speed of computing is often limited by the actual physical memory (such as random access memory) that a central processing unit (CPU) can address. Generally speaking, a CPU can address many orders of magnitude more memory locations than actually exist in RAM. Thus, the virtual address space of a CPU is usually much greater than the actual memory space of a computer system. To remedy this deficiency, it is well known to use a virtual storage (often called virtual memory) technique for utilizing the full virtual address space of the CPU.
Virtual storage is the notion of storage space that may be regarded as addressable main storage by the user of a computer system in which virtual addresses are mapped into real addresses in physical memory. The size of virtual storage is limited by the addressing scheme of the computer system (such as of the CPU) and by the amount of auxiliary storage available and not by the actual number of real storage locations. Simply put, virtual addresses generated by a CPU may actually refer to storage locations outside of the internal physical memory of the computer, such as on a hard disk.
FIG. 1 illustrates symbolically a virtual address translation technique 10 within a computer system. Process address space 12 is a range of virtual addresses assigned to a particular process running on a CPU while physical address space 14 is the range of actual physical memory (such as RAM) available within the computer system. In the example shown, all addresses generated by a CPU for the process are virtual addresses and need to be translated into a physical address before a data element at that address can be accessed. Process address space 12 ranges from a virtual address of 0 to a virtual address of 2.sup.N-1. Physical address space 14 ranges from a physical address of 0 up to 2.sup.M-1, where the range of virtual addresses is typically much greater than the range of physical addresses. In a computer system where a CPU has 64-bit addressing capability, N=64, while the value of M may only be M=24.
In this example, the virtual address space of the process includes a section of code 16, data 18 and a stack 20. A page 22 of code 16 is mapped to a page 24 in the physical address space. Also, page 26 of data 18 is mapped to a page 28 of the physical address space. Thus, a page in the virtual address space is mapped to any page within the physical address space and a translation mechanism is needed to provide such mapping.
An increasing number of architectures provide such virtual storage support through software-managed translation look-aside buffers (TLBs). This trend is mainly due to the advent of 64-bit address space which requires huge amounts of physical memory to hold the address translation page tables. A TLB is a small hardware cache of the most recent virtual to physical address translations in the system and is managed by the operating system. During a TLB miss (i.e., when a mapping is not found in the TLB), the hardware traps into the kernel which loads a new virtual to physical translation. This dynamic approach is very flexible but depends on a high cache hit ratio and on a fast TLB-miss trap handling.
FIG. 2 illustrates in detail an example 50 of an entry in such a TLB. Shown is a TLB 52 within a CPU 54 that has an entry 56. TLB 52 may have any number of entries, although 64 entries are common. Also, there may be more than one TLB per CPU, for example, one TLB for instructions and one TLB for data. Entry 56, a translation table entry (TTE), provides a mapping from a virtual address to a physical address and includes a tag portion 58 and a data portion 60. The tag portion includes a process identifier 62 used to identify the process and a virtual address 64. The data portion includes the physical address 66 to which the virtual address is mapped and associated attributes 68. Attributes include useful parameters such as "protection", "supervisor/user state""modified", "valid", etc. A valid bit 70 is used to indicate if the entry is valid. Thus, by accessing the TLB hardware cache, A CPU is able to quickly translate a virtual address into a physical address.
However, a TLB is not able to hold all of the virtual addresses available to a CPU; thus, frequently the CPU cannot find a particular virtual address for a particular process in the TLB. This situation is called a "TLB miss". Typically, a TLB miss is handled in two ways. One technique uses hardware trap handling in order to map a virtual address when a TLB miss occurs. In hardware trap handling, the hardware uses tables in physical memory in order to look up the physical address for the given virtual address, termed a "page table walk". A number of nested segment tables and page tables are used to determine the physical address. Although this technique can be fast for 32-bit machines, it is generally not viable for 64-bit machines. With a 64-bit address space, the tables in hardware needed to implement this technique are extremely long and would take up far too much memory in the computer. Even if smaller tables are used, at least six levels of nesting of the tables may be necessary, resulting in a time-consuming look-up process. Thus, although hardware trap handling is useful for 32-bit machines, for machines with a larger address space (such as 64-bit machines) this technique is not extremely useful.
Another technique for dealing with a TLB miss is to let the operating system deal with the miss through software trap handling. Software trap handling may be implemented in many ways depending upon the system. Generally, it is desirable on a TLB miss to limit the number of memory accesses to one reference. One technique for such software trap handling uses a "translation storage buffer" (TSB) to support the TLB and is useful on larger address space machines such as on 64-bit machines. A translation storage buffer is useful on UltraSPARC work stations manufactured by Sun Microsystems, Inc. of Mountain View, California, running a Solaris version 2.6 operating system. A more detailed explanation of a translation storage buffer (TSB) may be found in the above-referenced patent application.
Such a TSB cache is backed by a table of all valid address mappings in the system. The TSB is a contiguous buffer in memory that is usually organized as a direct-mapped cache. The operating system uses the TSB for fast TLB-miss trap handling. The TLB miss trap handler searches the TSB for the missing address translation. If the search operation generates a hit, the address mapping is added to the TLB.
FIG. 3 illustrates symbolically one embodiment of a software trap handling technique 80. Shown is a translation look-aside buffer (TLB) 52, a translation storage buffer (TSB) 82 and a hash table 84. On a TLB miss, the operating system would next check TSB 82 to locate an address mapping. TSB 82 is an operating system data structure that caches the most recent address translations. The operating system uses the TSB for fast TLB-miss trap handling. On a TLB miss, the TLB miss trap handler searches TSB 82 for the missing address translation. If the search operation generates a hit, the address mapping is added to TLB 52. If an address mapping is not found in TSB 82, the operating system then checks hash table 84 which is a table of all valid address mappings in the system. Once the correct mapping is found, it is inserted in the TLB and into the TSB so that it may be found when needed next. Hash table 84 need not be a hash table, but may be any suitable data structure in memory. Thus, a TSB is a cache of recent address translations useful when a TLB miss occurs.
FIG. 4 shows in detail a TSB entry 90. As in the translation table entry (TTE) of FIG. 2, TSB entry 90 includes a process identifier 92, a virtual address 94, a physical address 96 and attributes 98. Also included is a valid bit 100 to indicate if the entry is valid.
Although a TSB is used in 64-bit machines (and is possible in 32-bit machines), there are disadvantages associated with the ways in which a TSB is used. Some systems use one global TSB for all CPUs available within a computer system. Thus, on a TLB miss for any of the CPUs within the computer system, only one TSB is used as a cache for recently used address translations. Use of one global TSB has certain drawbacks. For one, a global TSB may not have the capacity to adequately serve all processors within a computer system. That is, it may be difficult to make the global TSB large enough in memory to efficiently serve all of the processors. This decision is somewhat implementation dependent. A TSB might be given more memory at the expense of memory for users. Even with a large global TSB, context invalidation can be very costly in terms of time because the complete TSB must be walked in order to determine that an address translation is not present.
Also, with all processes on all CPUs using one TSB for caching translations, there is the problem of thrashing. Thrashing happens when different processes generate the same index into the TSB and "take one another out" in the global TSB, even though there are free slots in the TSB. Thrashing is a common problem where many processes vie for the use of one TSB. In particular, if an XOR function is used to generate an offset from a process identifier and a virtual address, then thrashing is likely to occur because the XOR function is not particularly suited for good distribution. Also, many systems are limited to a process identifier of 13 bits, which further limits the distribution of addresses in the TSB and thus leads to thrashing.
A further disadvantage of having only one global TSB is that this TSB is fixed in size, whereas each process has different characteristics and needs. In other words, a simple process such as a shell or mail program may only require a very small TSB, whereas a large database application may require an extremely large TSB to be able to map to many more addresses. The global TSB, being of only one size, is inflexible and leads to inefficiency in address translation for these different types of processes. Inefficiency also results during a TSB flush operation when the complete TSB must be walked to invalidate entries for a process no longer in use.
Aside from the global TSB approach, other systems assign a single TSB to each CPU within a multi-processor computer system. The TSB capacity problem is alleviated because many more TSBs are available for use. However, this "TSB per CPU" approach has other disadvantages. Thrashing is reduced between processes on different CPUs, but processes on the same CPU will still encounter thrashing on the TSB to which that CPU is assigned. Thus, thrashing is reduced but not eliminated. Furthermore, as in the global TSB technique, each of these TSBs is of a fixed size and is not tailorable to the needs of a particular process.
Another drawback of this technique is excessive memory usage since each CPU is allocated a private TSB. For larger systems, often the worst case must be assumed for each TSB per CPU, resulting in large amounts of space being assigned to each TSB. If a CPU is unused, or if only a small portion of the TSB is used, then space is wasted.
Also, because there is only one TSB per CPU, there may be duplicate translations for a kernel variable in different TSBs. For example, if a first CPU has a TLB miss for a kernel variable A, it places a translation in its TSB. However, if a second CPU also has a TLB miss for the same kernel variable A, it will place a duplicate translation for that kernel variable in its own TSB, resulting in duplication of effort. Another disadvantage of this technique is that a process migrating from one CPU to another must continuously repopulate its new TSB with its address translations, resulting in more inefficiency. This is known as a cold cache syndrome.
Another problem with each of the above approaches is the cost of TSB context invalidation due to context invalidation. This cost is critical in multi-user environments where a large number of small processes are created and destroyed. Especially with a large global TSB, it can be very time consuming to search the complete TSB to invalidate one context. Likewise with the TSB per CPU approach, each TSB may have to be searched to invalidate a context. Also, another drawback common to both of the above techniques is that there is no separate TSB for system uses. The global TSB, or each per processor TSB must be used for both user and system processes.
In addition, the embodiments described above store a TSB in physical memory. For example, a global TSB may be of a size that it can be stored in the nucleus of the kernel. In the TSB per processor embodiment, each TSB is typically of a larger size and is not stored in the kernel but rather outside of the kernel in physical memory. A greater shortage of physical memory within the computer system results from these techniques.
Therefore, a TSB implementation technique is desirable for large address space computer systems that would minimize or eliminate TSB thrashing between different processes and would reduce the cost of TSB context invalidation.

Flexible translation storage buffers for virtual address translation


The present invention relates to a method and system for receiving data by using the SMS and the wireless Internet. The method comprises the steps of receiving a short message from said service provider, wherein the short message comprises at least a service identifier and site information, determining whether or not there is an application protocol in the site information and executing an IP channel connecting program in correspondence with the application protocol, when the application protocol is in the site information, wherein the data receiving system receives data in correspondence with the application protocol from the service provider by executing the IP channel connecting program.

Recently, a Short Message Service, SMS, has been broadly used between mobile communication users. Also, a wireless Internet has been used more and more.
The SMS facilitates that a sender sends a short message by using mobile communication service to a recipient, then the recipient can receives the short message.
The SMS may be implemented by two ways. The one way is that a sender connects a web site using Internet and transmits a short message to a recipient using mobile communication terminal. The other way is that a sender using mobile communication terminal sends a short message to a recipient using mobile communication terminal.
To receive the short message, a separate terminal is needed. Also, the terminal may receives the short message in the middle of conversation. If a mobile communication terminal may not receive the short messages because of being turned off the power supply of the terminal, the short messages may be stored in a Short Message Service Center, SMSC. After that time, if the power supply is turned on, a message for indicating the arrival of the short messages is displayed on the display device. The terminal may receive the short messages stored in the SMSC according to a predetermined way. Also, recently, a sender, a user of one communication service company, may send short messages to a recipient, a user of another communication service company. Because a short message made of maximum 224 characters of the English may be send by using the SMS technology, the SMS technology has been used for providing weather information, stock information, transacting e-business, and other fields.
With the SMS methods, data of large size (for example, moving pictures) may not be transmitted, because the maximum size of data for transmitting is 224 characters of the English.
By using the wireless Internet technology, data provided by server may be transmitted to a user terminal via an Interworking Function, IWF, and a base station. A user may confirm the received data by handling a user terminal. Otherwise, data transmitted from the user terminal may be transmitted to the server via the IWF and the base station. The IWF has a modem and PPP server. Accordingly, users may receive or transmit data using only mobile communication terminal.
The WAP gateway converts data in HTTP protocol pattern into wireless data. If the function of the WAP gateway is embarked in the user terminal, separate WAP gateway may not be needed. Namely, a mobile communication terminal embarking the ME (Mobile Explorer) developed by MS may execute the function of the WAP gateway.
However, if users wish to use the data service by using the wireless Internet, they should connect the communication channel by handling their terminals and request the data service. Also, the service provider may not provide the data service for the users arbitrary, before the communication channel is connected by the users.

Method for receiving data using SMS and wireless internet and system thereof


Described is a carrier having a biomolecular interaction incorporated therein. The carrier is described as comprising a silica based glass and in an embodiment is a sol-gel derived glass. Also described are methods of incorporating biomolecular interaction within a carrier of the invention. Various types of biomolecular interaction are discussed as well as applications of carriers containing one or more biomolecular interactions.

Cells organize and regulate their growth, metabolism, differentiation and survival based, in large part, on external cues or signals such as hormones, growth factors, or molecules presented by neighbouring cells or the external environment. Interactions of proteins with ligands such as other proteins, phospholipids and nucleic acids mediate the internal responses to these external signals. Proteins that regulate intracellular function are generally, but not always, composed of modular domains that regulate protein—protein, protein-phospholipid, and protein-nucleic acid interactions.
A protein modular domain is a sequence of about 50 to 100 amino acids characterized by an ability to fold into the appropriate three-dimensional structure, and to retain its intermolecular binding properties, even in the absence of additional linked polypeptide sequences. A large number of protein modules have been identified. For example, protein modules have been identified that are involved with (i) cellular functions that control cell growth, or induce cell death or inflammation; (ii) the development of the cytoskeleton; (iii) the intracellular anti-microbial machinery of the cell; and (iv) transcriptional assembly.
With the increasing discovery of new protein—protein interactions there is a need for assays to analyze the interactions and identify modulators of the interactions. However, interacting protein domains are inherently difficult to assay. For example, the identification of inhibitors of an interaction may require a thermodynamically unfavorable situation wherein a weakly binding compound must disrupt and then binds to the interface between two tightly bound protein monomers. Therefore, there is a need for effective methods for assaying biomolecular interactions and for identifying substances that modulate the interactions.

Incorporation and applications of biomolecular interactions within a carrier


A PLL is provided for reproducing a standard clock having a constant Jitter band from a random time information. This PLL is composed of a receiving counter 4-1 for counting the standard clock received from the transmitting side; a subtractor 4-3 for comparing between the count value of the receiving counter 4-1 which is read out each time when the receiving counter receives the count value from the transmitting counter; a differential time calculator for calculating a difference between the present count value and the preceding count value of the receiving counter; a first attenuator 4-5 for attenuating the output of the subtractor; a second attenuator 4-6 for further attenuating the output of the first attenuator; an integrator 4-7 for integrating the output of the second attenuator based on the differential time calculated by the differential time calculator; an adder 4-8 for adding the outputs of the adder and the integrator; a converter 4-9 for converting the result of the adder into a voltage signal; and a voltage control oscillator 4-10 for outputting a signal to the receiving counter based on the input of the voltage signal converted by the converter.

1. Field of the Invention
The present invention relates to a phase locked loop (hereinafter, called PLL), and particularly relates to a digital PLL for reproducing the standard clock at a receiving side in a transfer system of the standard clock used for image coding for systems larger than current TV systems such as MPEG 2 (Motion Picture Experts Group 2).
2. Background Art
According to the specification of MPEG of the International Organization for Standardization (ISO), wherein the digital transfer systems of the dynamic image are under investigation, a transmitting side transmits a numerical information corresponding to a count of a transmitting counter by reading the count at random time intervals, while, a PLL at the receiving side reproduces a standard clock synchronized with that of the transmitting side based on numerical information obtained as a difference by comparing between the numerical information at the transmitting side and the count of the standard clock obtained by counting at the receiving side. A digital signal processing-type PLL is known as a circuit for reproducing the standard clock from the second numerical information.
Experimental and simulation results including of a first order-, a second order- and third order- all digital type PLLs are reported in a paper entitled xe2x80x9cResponse of an All Digital Phase-Locked Loopxe2x80x9d by Joseph Garodnick et al. in xe2x80x98IEEE transactions on Communication, vol. COM-22, No. 6, June 1974xe2x80x99.
The operation of this digital signal processing-type DPLL (Digital PLL) will be described hereinafter referring to a block diagram shown in FIG. 7.
An input of a receiving FM wave including noise is turned into X(t) as a wave with a restricted band by passing a band-pass filter BPF having a band width B, and after sampling, X(t) is subsequently turned into a digital signal Xk after conversion into binary codes by an A/D converter. The digital signal Xk generates a phase error signal Ek by inputting the signal with an output Wk of VCO (Voltage Controlled Oscillator) into a multiplier which corresponds to a phase comparator. The phase error signal Ek is turned into a control signal Yk by passing it through a digital filter and determining the output Wk+1 of the new VCO. While, after the control signal Yk is converted into a step-wise signal by a D/A converter as the output of the loop, the control signal is taken out as an analog signal Y(t) by LPF (Low Pass Filter). There are various types of digital filters such as a linear pass type-, a linear plus integral pass type-, and a linear plus integral plus double integral pass type-filters, and these filters are called first order-, second order-, and third order- DPLLs.
In the conventional digital signal processing type PLL, a problem arises that, since the transmitting clock information is processed assuming that the information is sampled at a fixed cycle, jitter suppression characteristics of the system become unstable when PLL is driven by information sampled at random time intervals, which results in deteriorating the transmission quality.
That is, in the digital signal processing type-DPLL, calculation is performed using a fixed differential time, since essential elements such as the primary low pass filter and the integrator are formed by a delay element having a fixed delay time of Ts second. However, when sampling intervals w are random, since scattering of the arrival time of numerical information causes fluctuation of the delay time each time and fluctuation of the time constant of the delay element, the jitter suppression characteristic of the system becomes unstable.
Therefore, it is an object of the present invention to provide a PLL capable of reproducing the standard clock which is fixed in a stable jitter band from the random time information.
The present invention is directed from a point that an equation 1, which represents the time integral,
y=∫f(t)dtxe2x80x83xe2x80x83(1)
can be replaced with an equation 2.
y=xcexa3f(i) xcex94txe2x80x83xe2x80x83(2)
That is, the delay line of the present invention is capable of operating in response to random time information by using xcex94t obtained from a differential time between the present count T(i) and the preceding count T(i-1) as an operator for each constituting elements.
The perfect second order PLL according to the present invention comprises
a receiving counter, which has the same structure with that of a counter at the transmitting side, for counting the received standard clock;
a memory for storing the output of the receiving counter;
a subtractor, which reads the counted value of the counter at the receiving side each time the counted value of the transmitting side is transmitted to the receiving side, for comparing between the counted value transmitted and the counted value of the counter at the receiving side;
a differential time calculator for calculating a differential time between the present counted value and the preceding counted value of the receiving counter at the receiving side;
a first attenuator for attenuating the output gain of the subtractor;
a second attenuator for attenuating the output of the first attenuator;
an integrator for integrating the output of the second attenuator based on the differential time calculated by the differential time calculator;
an adder for adding the output of the first attenuator to the output of the integrator;
a converter for converting the result of the adder into a voltage signal;
a voltage oscillator for converting and receiving said voltage signal of the output of the converter, and converting into a control signal for outputting into the receiving counter.
FIG. 2 shows a third order PLL according to the present invention having a primary low pass filter which receives the output of the subtractor of the second order PLL and the output of the differential time calculator and inputs its output to the first attenuator.
Operations and actions of the present device will be described hereinafter for a case of the primary low pass filter.
FIG. 4 shows a structure of the primary low pass filter, FIG. 5 shows its extended view in the Z plane, and FIG. 6 shows a frequency response characteristic of this circuit.
As shown in FIG. 4, the primary low pass filter can be constructed by an RC circuit. The frequency transfer characteristic Y(jxcfx89) is expressed by,
Y(jxcfx89)=1/(jxcfx89RC+1)xe2x80x83xe2x80x83(3)
that is, on the S plane, the equation in turned into,
Y(S)=1/(S/A+1)xe2x80x83xe2x80x83(4)
where, A is a gain of this system, which is a reciprocal of the time constant 1/RC.
When this transfer characteristics is extended on the Z plane, S is expressed as,
S=(1xe2x88x92Zxe2x88x921)/xcex94txe2x80x83xe2x80x83(5)
Here, Z1 represents a delay element, and the delay is generated expressed by, xcex94t=T(i)xe2x88x92T(ixe2x88x921), and a datum received at the time of T(ixe2x88x921) is output in T(i).
When the equation (5) is substituted into the equation (4), the following equation is obtained.
Y(Z)=axc2x7b/(1xe2x88x92bxc2x7Zxe2x88x921)xe2x80x83xe2x80x83(6)
where, a=Axc2x7xcex94t, b=1/(1+Axc2x7xcex94t).
The frequency response characteristic extended on the Z plane shown in FIG. 6 is obtained by setting the maximum sampling intervals as 0.1 sec. The frequency response characteristic in a frequency range less than 10 Hz obtained when xcex94t is set at 0.01 sec is coincides with the characteristic shown by the equation (3).
It was confirmed that a uniform characteristic is obtained in a frequency range less than 4 Hz, even if xcex94t fluctuates.
It is to be understood that, although a peak is observed at a frequency of 5 Hz and at xcex94t=0.1 sec, it does not cause any problem because the significant frequency range is less than a half of the sampling frequency as decided by the sampling theory.

PLL for reproducing standard clock from random time information


An oral care implement may include a tufted insert and a base configured to define a cavity for housing an active insert. The active insert may comprise an active agent. The head of the oral care implement may be configured so that the active insert can be in fluid communication with a membrane or an aperture.

People exhibit many forms of poor oral health including tooth decay, periodontal diseases and bad breath (halitosis). Tooth decay and periodontal disease are typically caused by harmful bacteria within the mouth. When the harmful bacteria mixes with proteins present in saliva, a film of plaque is formed on the teeth and soft tissue. If the plaque is not removed, it can attack the teeth and create cavities. Additionally, the plaque will attack the soft tissue within the mouth and cause gum disease, the leading cause of tooth loss in adults. As a result, decreasing the amount of harmful bacteria in the mouth has long been the target of persons working in the oral health care field.
The most common way of minimizing the harmful bacteria within the mouth is brushing with a dentifrice that delivers at least one oral care agent into the mouth. Orally introduced liquids, including oral rinses, are also utilized to provide additional oral care beyond that achieved while brushing. Mouthwashes may also be used to deliver breath freshening agents within the mouth in an attempt to eliminate bad breath.
Unfortunately, individuals do not always have the time for adequate oral care. For example, a busy person may not have the time or patience to brush thoroughly, floss and/or use an oral rinse. Alternatively, certain people may consider anything more than brushing their teeth to be unnecessary. For either reason, these people may leave a significant amount of harmful bacteria within their mouths after completing their oral care routines, which can begin to attack the teeth and gums.
Hence, there is a need for a toothbrush that delivers an agent during brushing to improve oral health.

Oral care implement housing an oral care agent