An n− type diffusion region surrounds a high side well region and is electrically isolated from a low side region. In the n− diffusion region formed are a first p type diffusion region and the second p type diffusion region separated with each other. The first p type diffusion region composes a double RESURF structure in an nch MOSFET in the level shift-up circuit, and in a high voltage junction terminating structure. The second p type diffusion region composes a double RESURF structure of a pch MOSFET of a level shift-down circuit. The impurity concentration of the n− type diffusion region is in the range of 1.3×1012/cm2 to 2.8×1012/cm2. The impurity concentration of the first p type diffusion region and the impurity concentration of the second p type diffusion region are in the range of 1.1×1012/cm2 to 1.4×1012/cm2.

1. Field of the Invention
Embodiments of the present invention relate to a semiconductor device.
2. Background
Traditionally, inverters for industrial application have been using transformers and photo-couplers to perform electrically isolated signal transmission in the gate driving of switching elements such as insulated gate bipolar transistors (IGBTs) that compose a power conversion bridge circuit. Recently, however, the transformers and photo-couplers are replaced for cost reduction in low capacity applications, in particular, by high voltage integrate circuits (HVICs) that do not perform electrical insulation. U.S. Patent Application Publication No. 2006/0220168, M. Yoshino et al., "A new 1200 V HVIC with a novel high voltage Pch-MOS", Proceedings of the 22nd International Symposium on Power Semiconductor Devices & ICs, Hiroshima, 2010, pp. 93-96, ("Yoshino et al. '2010") and M. Yoshino et al., "A novel high voltage new Pch-MOS with a new drain drift structure for 1200 V HVICs", Proceedings of the 25th International Symposium on Power Semiconductor Devices & ICs, Kanazawa, 2013, pp. 77-80, ("Yoshino et al. '2013"), for example, disclose such HVICs. The following describes the construction of a conventional HVIC.
FIG. 15 is a plan view showing the overall construction of a conventional HVIC. FIG. 16 is a circuit diagram showing the circuit construction of the HVIC depicted in FIG. 15. The following describes an example of HVIC 100 connected to a bridge circuit 120 of a power converter and driving the first IGBT 121 at the high side of the first and second IGBTs 121 and 122 composing one phase of the bridge circuit 120 of a power converter. The conventional HVIC 100 shown in FIG. 15 and FIG. 16 includes, on a single semiconductor chip, a high side gate driving circuit 101, and abnormality detecting circuit 102, an input/control circuit 103, a level shift-up circuit 104, a level shift-down circuit 107, and a high voltage junction terminating (HVJT) structure 111.
The high side gate driving circuit 101 and the abnormality detecting circuit 102 are disposed in the high side well region 112 and is operated with a reference potential of the emitter potential VS of the first IGBT 121 at the high side of the bridge circuit 120 of a power converter, a power supply potential of VB, and a power supply voltage of VCC′. The high side well region 112 is a high voltage region having a floating potential electrically isolated from the low side region 113 by the high voltage junction terminating structure 111. The abnormality detecting circuit 102 transmits an abnormality signal to the input/control circuit 103. The VB potential is a sum of a power supply voltage VCC′ and the emitter potential VS of the first IGBT 121 at the high side of the bridge circuit 120 of the power converter: VB=VS+VCC′.
The input/control circuit 103 is located in the low side region 113 and operates with a reference potential of GND potential. The input/control circuit 103 is operated with a power supply potential VCC supplied from the VCC terminal and controls the output HO of the high side gate driving circuit 101 according to a control signal HIN from an external microcontroller, for example, and an abnormality detection signal from the abnormality detecting circuit 102. The level shift-up circuit 104 is composed of two level shift circuits for a setting signal and for a resetting signal. Each of the two level shift circuits is composed of an n channel metal oxide semiconductor field effect transistor (nch MOSFET) 105 with a high breakdown voltage and a level shift resistor 106.
The nch MOSFET 105 of the level shift-up circuit 104 is disposed in the high voltage junction terminating structure 111, and the level shift resistor 106 is disposed in the high side well region 112. The level shift-up circuit 104 converts the setting signal and resetting signal with the reference potential of the ground potential fed from the input/control circuit 103 into signals with a reference potential of the VB potential, and delivers the converted signals to a latching circuit 110 at the next stage. The set signal is given to turn ON the high side gate driving circuit 101 for delivering a gate signal HO to the first IGBT 121 at the high side of the bridge circuit 120 of the power converter. The reset signal is given to turn OFF the high side gate driving circuit 101.
The output terminal Q of the latching circuit 110 is connected to the gate terminal of a p channel MOSFET (pch MOSFET) for charging the gate of the first IGBT 121 at the high side of the bridge circuit 120 of the power converter and to the gate terminal of an nch MOSFET for discharging the gate of the first IGBT 121. The level shift-down circuit 107 is composed of a high voltage pch MOSFET 108 and a level shift resistor 109. The pch MOSFET 108 of the level shift-down circuit 107 is disposed in the high voltage junction terminating structure 111 and the level shift resistor 109 is disposed in the low side region 113. The level shift-down circuit 107 transforms an abnormality detection signal with a reference potential of VB potential delivered from the abnormality detecting circuit 102 into a signal with a reference potential of the ground potential, and transmits the signal into the input/control circuit 103. FIG. 16 also indicates a bootstrap diode 124 and a bootstrap capacitor 125.
A planar construction of the high side well region 112 and the surroundings thereof of the conventional HVIC 100 is described below. FIG. 17 is a plan view showing in detail the planar construction around the high side well region of the HVIC of FIG. 15. FIG. 17 shows only one nch MOSFET 105 of the level shift-up circuit 104 to clearly show the planar construction of the conventional HVIC 100. As shown in FIG. 17, the high side well region 112 is composed of an n type diffusion region 14 and a low concentration n− type diffusion region 13 surrounding the n type diffusion region 14. The n− type diffusion region 13 and the n type diffusion region 14 are connected to the VB potential. The n− type diffusion region 13 is surrounded by the n− type diffusion region 1.
Between the n− type diffusion region 13 and the n− type diffusion region 1, a p− diffusion region 12, which is an isolating region, is provided. The n− type diffusion region 1 is surrounded by a p+ type diffusion region 11 at a GND potential, which is a p+ type GND region. In the n type diffusion region 14 arranged are a high side gate driving circuit 101, the abnormality detecting circuit 102, and the components of the level shift-up circuit 104 including the level shift resistor 106 but excluding the nch MOSFET 105. In the n− type diffusion region 1 arranged are the high voltage junction terminating structure 111, the nch MOSFET 105 of the level shift-up circuit 104, and the pch MOSFET 108 of the level shift-down circuit 107.
The following describes the sectional construction of the nch MOSFET 105, the pch MOSFET 108, and the high voltage junction terminating structure 111 of the conventional HVIC 100. FIG. 18 is a sectional view showing the sectional construction along the line AA-AA′ indicated in FIG. 17; FIG. 19 is a sectional view showing the sectional construction along the line BB-BB′ indicated in FIG. 17; and FIG. 20 is a sectional view showing the sectional construction along the line CC-CC′ indicated in FIG. 17. FIG. 18 depicts the sectional construction of the nch MOSFET 105; FIG. 19 depicts the sectional construction of the pch MOSFET 108; and FIG. 20 depicts the sectional construction of the high voltage junction terminating structure 111.
Commonly in the sectional constructions of FIGS. 18, 19 and 20 shown are the n− type diffusion region 1, and n− type diffusion region 13 and the n type diffusion region 14 composing the high side well region 112 selectively formed in the front surface region of the p type semiconductor substrate 10. The n− type diffusion region 13 is disposed in the outer peripheral side than the n type diffusion region 14, and the n− type diffusion region 1 is disposed in the outer peripheral side than the high side well region 112. A p− type diffusion region 15 is provided in the outer peripheral side of the substrate on the front surface layer of the substrate. The p− type diffusion region 15 penetrates in the depth direction through the n− type diffusion region 1 reaching a p type region in the back surface side of the substrate. In the p− type diffusion region 15, a p+ type GND region 11 is selectively provided.
As shown in FIG. 18, the nch MOSFET 105 of the level shift-up circuit 104 is provided with a RESURF structure with the n− type diffusion region 1 and the p type semiconductor substrate 10, the RESURF structure being a single RESURF structure. The n− type diffusion region 1 also functions as a drift region. The impurity concentration of the n− type diffusion region 1 is about 1.0×1012/cm2. In the n− type diffusion region 1 around the nch MOSFET 105, an isolation region 12 is provide between the n− type diffusion region 1 and the n− type diffusion region 13 in the deeper depth than the n− type diffusion region 1 from the front surface of the substrate. The isolation region 12 isolates the n− type diffusion region 1 from the n− type diffusion region 13.
M. Imam et al., "Design and Optimization of Double-RESURF High-Voltage Lateral Devices for a Manufacturable Process", IEEE Transactions on Electron Devices, vol. 50, no. 7, July 2003, pp, 1697-1701, ("Imam et al.") for example, discloses that the optimum impurity concentration of an n− type diffusion region 1 is at most 1.4×1012/cm2 to obtain a desired breakdown voltage for a single RESURF structure.
As shown in FIG. 19, the pch MOSFET 108 of the level shift-down circuit 107 has a double RESURF structure with a p type diffusion region 2, the n− type diffusion region 1, and the p type semiconductor substrate 10. In the n− type diffusion region 1 around the pch MOSFET 108, the isolation region 12 is not provided between the n− type diffusion region 1 and the n− type diffusion region 13, and the n− type diffusion region 1 is in contact with the n−type diffusion region 13. The p type diffusion region 2 is formed in the front surface layer of the substrate with a depth shallower than the n− type diffusion region 1. The p type diffusion region 2 not only composes a double-RESURF structure, but also functions as a p type drift region. The impurity concentration of the p type diffusion region 2 is in the range of 5.0×1011/cm2 to 1.0×1012/cm2.
As shown in FIG. 20, the high voltage junction terminating structure 111 has, like the nch MOSFET 105, a single RESURF structure with the n− type diffusion region 1 and the p type semiconductor substrate 10. In the place of the high voltage junction terminating structure 111, the isolation region 12 is provided between the n− type diffusion region 1 and the n− type diffusion region 13, and the n− type diffusion region 1 is isolated from the n− type diffusion region 13 by the isolation region 12.
In FIG. 18, the symbols 3, 4, 5, 7, 8, and 9 represent the components composing a structure of MOS gate structure, which is an insulated gate structure comprising a metal-oxide film-semiconductor gate, of the nch MOSFET 105. The symbol 16 in FIG. 18 indicates a contact, which is an electrical contact region, between a VB electrode 39 and the n type diffusion region 14. The symbols 24, 25, 27, 28, and 29 (in FIG. 19) represent the components composing the MOS gate structure of the pch MOSFET 108. The symbols 31, 32 and 33 (in FIGS. 18, 19, and 20) represent local oxidation of silicon film (LOCOS film), interlayer dielectric film, and a resistive field plate, which is a resistor functioning as a field plate, respectively. The symbols 34 and 35 (in FIG. 18) represent a source electrode and a drain electrode of the nch MOSFET 105, respectively. The symbols 36 and 37 (in FIG. 19) represent a source electrode and a drain electrode of the pch MOSFET 108. The symbols 38 (in FIG. 19) and 40 (in FIG. 18) represent a GND electrode and a field plate, respectively.
Now, operation of the conventional HVIC 100 will be described below. A control signal from a microcontroller, for example, given to the input/control circuit 103 is transmitted to the high side gate driving circuit 101 to drive the first IGBT 121 at the high side, for example, connected to the conventional HVIC 100, of the first IGBT 121 and the second IGBT 122 composing one phase of the bridge circuit 120 of a power converter. When the abnormality detecting circuit 102 detects any abnormality such as over-current or over-heating, the abnormality detecting circuit 102 transmits an abnormality signal to the input/control circuit 103, and the first IGBT 121 at the high side is turned OFF and the abnormality is notified to the microcontroller.
As described earlier, the high side gate driving circuit 101 is operated on a reference potential of the emitter potential VS of the first IGBT 121 at the high side of the bridge-connected circuit, wherein the potential VS is the potential at the node 123 between the first IGBT 121 and the second IGBT 122 at the low side. The reference potential of the high side gate driving circuit 101 rises to several hundred volts at the maximum above the reference potential, which is the ground potential, of the input/control circuit 103. However, the high voltage junction terminating structure 111 holds a breakdown voltage between the high side gate driving circuit 101 and the input/control circuit 103.
Japanese Patent No. 3952967 discloses a HVIC of this type. This HVIC has a three layer structure comprising a first region of a first conductivity type, a second region of a second conductivity type formed selectively in the surface layer of the first principal surface of the first region, and a third region of the first conductivity type formed selectively in the surface layer of the second region. The net doping amount of the second region is in the range of 1×1011/cm2 to 4×1012/cm2 so that the depletion layer extending to both sides of a first pn junction between the first region and the second region and the depletion layer extending to both sides of a second pn junction between the second region and the third region are united in the second region, when both the first pn junction and the second pn junction are reversely biased. The net doping amount of the third region is in the range of 1×1011/cm2 to 2×1012/cm2 so that the depletion layer extending to both sides of the second pn junction reaches the surface of the third region. The HVIC further includes, inside an area surrounded by the third region, a second conductivity type region electrically connected to the second region, a first conductivity type region selectively formed in the surface layer of the second conductivity type region, a first conductivity type channel MIS transistor formed in the surface layer of the second conductivity type region, and a second conductivity type channel MIS transistor formed in the surface layer of the first conductivity type region.
Japanese Patent No. 3214818 discloses another HVIC. This HVIC includes: a semiconductor material layer of a first conductivity type disposed on a semiconductor substrate and having an upper surface subjected to doping treatment, a base region of a second conductivity type formed in the surface region of the semiconductor material layer to a predetermined depth and having substantially a semicircular shape, a source region of the first conductivity type formed in the base region and forming a surface channel region between the source region and the semiconductor material layer, a source electrode in contact with the source region and electrically connected to a low voltage reference control circuit, a gate insulating layer disposed so as to be in contact with the source region and a part of the upper surface of the surface channel region, a conductive gate layer disposed in the gate insulating layer, a drain region formed in the upper surface region of the semiconductor material layer at a position laterally apart from the base region, a drain electrode formed on the drain region and in contact with a part of the upper surface of the semiconductor material layer, a contact electrode in contact with another part of the upper surface of the semiconductor material layer and electrically connected to a floating high voltage circuit, in which a part of the semiconductor material layer at the position between the contact electrode and the drain electrode forms a conductive region, and a resistance element disposed between the drain electrode and the contact electrode and arranged electrically in parallel to the conductive region of the semiconductor material layer. The base region with a substantially semicircular shape forms a peripheral ring part of the floating high voltage circuit, and a level shift circuit is provided in the peripheral ring part.
Japanese Unexamined Patent Application Publication No. H09-055498 discloses still another HVIC. The HVIC includes: a first region of a p type semiconductor substrate, an n type second region selectively formed in the surface layer of the first region, a p type third region selectively formed in the surface layer of the second region, an n type fifth region selectively formed in the surface layer of the second region, a p type sixth region selectively formed in the surface layer of the third region, a pch MOSFET formed in the surface layer of the second region, an nch MOSFET formed in the surface layer of the third region, and a high voltage junction terminating structure provided surrounding the first region.
However, the conventional HVIC 100 described above referring to FIG. 15 and FIG. 16 has the following problems. As described earlier, the conventional HVIC 100 employs a single RESURF structure in the nch MOSFET 105 and in the high voltage junction terminating structure 111 composed of the n− type diffusion layer 1 and the p type semiconductor substrate 10, whereas the pch MOSFET 108 employs a double RESURF structure composed of the p type diffusion region 2, the n− type diffusion region 1, and the p type semiconductor substrate 10. As a result, the optimum condition for the n− type diffusion region 1 differs for the pch MOSFET 108, and for the nch MOSFET 105 and the high voltage junction terminating structure 111.
More specifically, as described in Imam et al., the optimum impurity concentration of the n− type diffusion region 1 to obtain a desired breakdown voltage is at most 1.4×1012/cm2 for a single RESURF structure. An impurity concentration higher than this value cannot ensure sufficient breakdown voltage. For the double RESURF structure, the optimum impurity concentration of the n− type diffusion region 1 to ensure the breakdown voltage between the p type diffusion region 2 and the n− type diffusion region 1 is at most 2.8×1012/cm2. In order to ensure a desired breakdown voltage, an impurity concentration of the p type diffusion region is at most 1.4×1012/m2 and at the same time it is necessary that the difference between the impurity concentrations in the p type diffusion region 2 and in the n− type diffusion region 1 is at most 1.4×1012/cm2. These conditions for the impurity concentration of the p type diffusion region 2 is necessary conditions to obtain a desired breakdown voltage and not a sufficient condition. To obtain a desired breakdown voltage, optimization is needed to the impurity concentration of the p type diffusion region 2 while satisfying the above-mentioned necessary conditions. The optimum impurity concentration of the p type diffusion region 2 depends on the impurity concentration of the n− type diffusion region 1; a low impurity concentration for the n− type diffusion region 1 leads to lower optimum impurity concentration of the p type diffusion region 2.
A lower impurity concentration of the n− type diffusion region 1 tends to lower the optimum impurity concentration of the p type diffusion region 2 because the amount of positive space charges in the depletion layer has to be balanced with the amount of negative space charges. Therefore, a low impurity concentration of the n− type diffusion region 1 means a small amount of positive space charges, which are donors, in the n− type diffusion region 1, reducing the negative space charges, which are acceptors, allowed in the depletion layer of the p type diffusion region 2. When the impurity concentration in the p type diffusion region 2 is higher than the impurity concentration of the n− type diffusion region 1, deficiency of the positive space charges causes incomplete depletion of the p type diffusion region 2, resulting in insufficient breakdown voltage.
Negative space charges in a depletion layer exist not only in the depletion layer extending from pn junction between the p type diffusion region 2 and the n− diffusion region 1 into the p type diffusion region 2, but also exist in an approximately same amount in the depletion layer extending from the pn junction between the p type semiconductor substrate and the n− type diffusion region 1 into the p type semiconductor substrate. Consequently, in order to make the p type diffusion region 2 thoroughly depleted, the amount of the positive space charges in the n− type diffusion region 1 has to be about twice the amount of the negative space charges in the p type diffusion region 2. Therefore, the optimum impurity concentration in the p type diffusion region 2 for ensuring a sufficient breakdown voltage is about half the impurity concentration in the n− type diffusion region 1.
For this reason, a design condition to ensure a sufficient breakdown voltage in the nch MOSFET 105 and the high voltage junction terminating structure 111 with a single RESURF structure, a single RESURF condition, is that an impurity concentration Nd per unit area of the n− diffusion region 1 (hereinafter referred to simply as an impurity concentration of the n− diffusion region 1) is at most 1.4×1012/cm2, or the inequality Nd≦1.4×1012/cm2 holds. A double RESURF condition for the pch MOSFET 108 with a double RESURF structure to ensure a sufficient breakdown voltage is to satisfy the following four conditions.
The first condition is that the impurity concentration Nd of the n− type diffusion region 1 is about twice the impurity concentration Na of the p type diffusion region 2, or Nd≈2×Na. The second condition is that the impurity concentration Na of the p type diffusion region 2 is at most 1.4×1012/cm2 (Na≦1.4×1012/cm2). The third condition is that the impurity concentration Nd of the n− type diffusion region 1 is at most 2.8×1012/cm2 (Nd≦2.8×1012/cm2). The fourth condition is that the difference between the impurity concentration Nd of the n− type diffusion region 1 and the impurity concentration Na of the p type diffusion region 2 is at most 1.4×1012/cm2 (Nd−Na≦1.4×1012/cm2).
As a consequence, in a conventional HVIC 100, the condition for ensure a sufficient breakdown voltage is to satisfy both the single RESURF condition and the double RESURF condition. More specifically, both the single RESURF condition and the double RESURF condition are satisfied when the following two conditions are satisfied: firstly, the impurity concentration Nd of the n− type diffusion region 1 is at most 1.4×1012/cm2 (Nd≦1.4×1012/cm2); secondly, the impurity concentration Na of the p type diffusion region 2 is at most 7.0×10/cm2 (Na≦7.0×1011/cm2).
In order for the nch MOSFET 105 and the high voltage junction terminating structure 111 with a single RESURF structure to have a sufficient breakdown voltage, the impurity concentration Nd of the n− type diffusion region 1 needs to be at most 1.4×1012/cm2. The impurity concentration Na of the p type diffusion region 2 is necessarily at most 7.0×1011/cm2. When the impurity concentration Na of the p type diffusion region 2 is at a value approximately 7.0×1011/cm2, the pch MOSFET 108 cannot have a sufficient current carrying capacity because of the problems of a high drift resistance in the p type diffusion region 2 and the pinch-off of the p type diffusion region 2.
On the other hand, if the impurity concentration Na of the p type diffusion region 2 is raised in order for the pch MOSFET 108 with a double RESURF structure to exhibit sufficiently high current carrying capacity, the pch MOSFET 108 cannot have a sufficiently high breakdown voltage. In short, the conventional HVIC 100 is hardly provide optimum condition for both the current carrying capacity and breakdown voltage of the pch MOSFET 108. When the impurity concentration Nd of the n− type diffusion region 1 is a low value of about 1.0×1012/cm2, at the pn junction between the n− type diffusion region 1 and the p type diffusion region 2, an electric field is generated in the direction from the p type diffusion region 2 toward the p type semiconductor substrate 10, creating a leakage current to the p type semiconductor substrate 10. Thus, a breakdown voltage is hardly ensured between the p type diffusion region 2 and the p type semiconductor substrate 10.
As described later, in order to ensure a breakdown voltage between the p type diffusion region 2 and the p type semiconductor substrate 10, the impurity concentration Nd of the n− type diffusion region 1 in the pch MOSFET 108 should be at least 1.3×1012/cm2. Because a p type diffusion region 2 is formed on the surface of the n− type diffusion region 1 of the pch MOSFET 108, the impurity concentration of the n− type diffusion region 1 of the pch MOSFET, when formed by ion implantation homogeneous over the surface as usual, becomes lower than those of the n− diffusion regions 1 of the nch MOSFET 105 and the high voltage junction terminating structure 111. As commonly employed, when a diffusion depth of the p type diffusion region 2 is in the range of 1 μm to 2 μm, and the diffusion depth of the n− type diffusion region 1 is in the range of 10 μm to 30 μm, the impurity concentration of the n− type diffusion region 1 of the pch MOSFET 108 is lower by more than 10% than the impurity concentration of the nch MOSFET 105 and the n− type diffusion region 1 of the high voltage junction terminating structure 111.
As a consequence, even when the impurity concentration of the n− type diffusion region 1 of the nch MOSFET 105 and the impurity concentration of the n− type diffusion reign 1 of the high voltage junction terminating structure 111 are set at the upper limit value of 1.4×1012/cm2, the impurity concentration of the n− type diffusion region 1 of the pch MOSFET 108 becomes lower than 1.3×1012/cm2. Therefore, in order to adjust the impurity concentrations of the n− type diffusion regions 1 of the pch MOSFET 108, the nch MOSFET 105, and the high voltage junction terminating structure 111 to be a value of at least 1.3×1012/cm2 and at most 1.4×1012/cm2, which is required by the double RESURF condition, the ion implantation processes are carried out separately for the n− type diffusion region 1 for the pch MOSFET 108, and for the nch MOSFET 105 and the high voltage junction terminating structure 111. This causes increased process cost.
Yoshino et al. '2010 discloses a method of increasing the impurity concentration of the p type diffusion region 2 keeping a sufficient breakdown voltage to ensure a high current carrying capacity of the pch MOSFET 108 while maintaining the high breakdown voltage. This is achieved by a p type diffusion region 2 in a configuration of stripes for easy depletion. This method of the Yoshino et al. '2010, however, decreases the area of the drift region of p type diffusion region 2. Accordingly, in order to ensure a required current carrying capacity, the channel width of the pch MOSFET 108 needs to be sufficiently large, wherein the channel width is a width, in the direction perpendicular to the direction from a p+ type drain region 27 to the source region, of the channel, or a p type inversion layer generated in the n− diffusion region 1 at the place between a source region of a p type diffusion region 24 and a drift region of the p type diffusion region 2 in an ON state. The enlarged channel width of the pch MOSFET 108 causes a large parasitic capacitance of the pch MOSFET 108, which increases the displacement current associated with dV/dt surge voltage, which may cause malfunctioning of the HVIC.
Yoshino et al. '2013 discloses a method for ensuring a high breakdown voltage between the p type diffusion region 2 and the p type semiconductor substrate 10 in a structure having the p type diffusion region 2 of a stripe shape. However, Yoshino et al. '2013 fails to disclose a method for ensuring a high breakdown voltage between the p type diffusion region 2 and the p type semiconductor substrate 10 in a structure having the p type diffusion region 2 of a conventional structure without a stripe shape.

Field effect transistor and a device element formed on the same substrate


Provided is a wake disturbing apparatus and method for reducing drag, which can considerably reduce drag caused by a sharp decrease in the pressure behind an object with a blunt trailing edge, such as a vehicle, while the object is traveling at high speed. The wake disturbing apparatus includes a plurality of disrupters, which are arranged at regular intervals along the trailing edge of the object to protrude to a predetermined height so that the vortical strength of the wake occurring around the rear part of the object can be reduced and the pressure at the base surface, which has been decreased due to the wake, can be recovered. Accordingly, it is possible to considerably reduce drag on a vehicle by simply attaching a wake disturbing apparatus to the vehicle without modifying the structure of the vehicle or using additional energy. Thus, it is possible to reduce power consumption of the vehicle and thus maximize the energy consumption efficiency.

This application claims the priority of Korean Patent Application No. 2003-48436, filed on Jul. 15, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a wake disturbing apparatus and method for reducing drag, which can considerably reduce drag caused by a significant decrease in the pressure behind an object with a blunt trailing edge, such as a vehicle, while the object is traveling at high speed.
2. Description of the Related Art
In general, large vehicles, such as a heavy vehicle and a bus consume about 60% of their energy through aerodynamic drag. For example, in a case where a heavy vehicle travels 100 kilometers an hour, air resistance is accountable for 60% of its total energy consumption.
Such aerodynamic drag often occurs due to pressure at a rear part of an object (hereinafter, this part is referred to as 'base surface') while the object is traveling at high speed. The drag on the object can be reduced by decreasing the strength of vortical motion around the base surface and thus recovering pressure there, which has been decreased due to the strong vortical motion of the wake.
There have been many attempts to increase pressure at the base surface, but most of them cannot be realized and commercialized because they require the shape of the object to be significantly changed into, for example, a streamlined one, or they need much more energy than they can save by reducing the aerodynamic drag.

Wake disturbing apparatus and method for reducing drag


A golf towel transport and retrieval apparatus may comprise a receptacle operable to accept at least a portion of a golf club head and one or more attachment points operable to attach to a towel.

The present invention generally relates to golf accessories, and more particularly, to a golf towel transport and retrieval system that may make the process of cleaning golf balls during the course of a golf game easier and more convenient.
Currently, during the course of a golf game, a golf ball that has been played onto the putting green area of a golf course usually has its position on the putting green marked before the golf ball is lifted from the putting green surface.
The lifting of golf balls played onto the putting green helps to provide an unobstructed putting line for other golfers while also providing an opportunity to clean the golf ball of any dirt or refuse that may have accumulated on the surface of the golf ball during the course of play. By cleaning their golf ball of any accumulated dirt or refuse, a golfer may prevent the dirt or refuse from unpredictably affecting the path of their golf ball when it is putted on the putting green.
While professional golfers usually have a caddy that will clean their golf ball for them, amateur golfers are usually forced to clean their own golf ball. However, because carrying, using, and retrieving a towel used for cleaning a golf ball may be inconvenient, many amateur golfers may decide to forgo the opportunity to clean their golf ball, thus putting themselves at a disadvantage by leaving dirt or refuse on their golf ball.
As can be seen, there is a need for an apparatus and/or a method to more quickly and easily clean their golf ball during the course of a golf game.


The pure isomers L-buthionine-S-sulfoximine and L-buthionine-R-sulfoximine are provided. The L-S-isomer has utility, for example, in causing the depletion of glutathione, a major protectant molecule in tumors and certain parasites. The L-R-isomer has utility as a compound decreasing further uptake and thus effect of the L-S-isomer and for causing glutathione depletion specific to the kidney. The isolation of pure isomers from L-buthionine-SR-sulfoximine enables treatment at lower dosages without cross effects.. The pure L-buthionine-S-sulfoximine isomer is obtained from L-buthionine-SR-sulfoximine by recrystallization preferably by forming a solution of L-buthionine-SR-sulfoximine in water at a concentration of 0.8 M and cooling to form crystals enriched in the L-R-isomer and a filtrate enriched in L-S-isomer, drying the filtrate to obtain a solid, dissolving the solid in ethanol, adding trifluoroacetic acid to form acid salt and provide solvent, then adding hexane to cause crystal formation, then converting the crystals to the free zwitterion using ion exchange resin.. Both isomers can be separated concurrently by reverse phase chromotography in Cu.sup.++ /D-proline buffers.

Glutathione (gamma-L-glutamyl-L-cysteinylglycine) is synthesized by the sequential action of the enzymes gamma-glutamylcysteine synthetase and glutathione synthetase. L-Buthionine-SR-sulfoximine (L-(S-n-butyl)homocysteine-SR-sulfoximine is a potent and specific inhibitor of gamma-glutamylcysteine synthetase. Glutathione synthesis is decreased in tissues and cells treated in vitro or in vivo with the inhibitor and such cells and tissues become glutathione depleted. Tumors in mice treated with the inhibitor become glutathione depleted and more susceptible to the cytotoxic effects of ionizing radiation and various chemotherapeutic agents. (Bump, E.A., et al, International Journal Radiation Oncology, Biology and Physics, Vol. 8, p. 439-442, 1982 and Ozols, R.F., et al, Biochemical Pharmacology, Vol. 36, No. 1, pp. 147-153, 1987). Moreover, mice infected with Trypanosoma b. brucei have been shown to have extended survival and in some cases to be cured by treatment with DL-buthionine-SR-sulfoximine. (Arrick, B.A., et al, J. Exp. Med, Vol. 153, 720-725, March 1981).
A problem encountered in utilizing either DL-buthionine-SR-sulfoximine or L-buthionine-SR-sulfoximine is that very large dosages are often required and such dosages become osmotically burdensome to the treated subject. It has also been reported that L-buthionine-SR-sulfoximine has a deleterious effect on cystine transport (see Brodie, A.E., et al, Toxicology and Applied Pharmacology 77, 381-387, 1985) and on gamma-glutamylamino acid transport (see Anderson, M.E. and Meister, A., Proc. Natl. Acad. Sci., Vol. 80, pp. 707-711, 1983).
Since it has been shown that L-methionine-S-sulfoximine is the only diastereomer of DL-methionine-SR-sulfoximine that inhibits gamma-glutamylcysteine synthetase (Richman, Paul G., et al, The Journal of Biological Chemistry 248, No. 19, 6684-6690, 1973), it has been suspected that L-buthionine-S-sulfoximine is the only diastereomer of DL-buthionine-SR-sulfoximine that inhibits gamma-glutamylcysteine synthetase. If this were true, then the high dosage and osmotic burden associated with the use of the currently available isomer mixtures could be reduced if the pure L-S-isomer were available. Furthermore, the aforementioned deleterious effect on cystine and gamma-glutamylamino acid transport could be reduced if the pure L-S-isomer were available.

L-buthionine-S-sulfoximine and methods of making


The present invention provides processes for preparing Palonosetron salts, especially, the hydrochloride salt and intermediates used to prepare Palonosetron salts.

Palonosetron HCl, 1H-Benz[de]isoquinolin-1-one, 2-(3S)-1-azabicyclo[2.2.2]oct-3-yl-2,3,3aS,4,5,6-hexahydro-, monohydrochloride, of the following formula:
is a selective 5HT3-antagonist (prevention of chemotherapy-induced nausea and vomiting). It is marketed as a solution under the name Aloxi®. by Helsinn.
Palonosetron HCl and its cyclic amide precursor (referred to as Cp9532) are described in U.S. Pat. No. 5,202,333. Also disclosed is the preparation of Palonosetron HCl by reacting 5,6,7,8-tetrahydronaphthalene-1-carboxylic acid (referred to as Cp20774) with the diamine (referred to as Cp20771) providing the related amide (referred to as Cp9533), which is purified via it's hydrochloride salt (referred to as Cp9563). Then, Cp 9533 reacts with BuLi to provide the cyclic amide (referred to as Cp9532), which is then converted to Palonosetron by hydrogenation process. The process is illustrated by the following scheme:

The hydrogenation step is done in the presence of a mixture of acids, providing a mixture of Palonosetron salts, which are converted to the base, and then to Palonosetron HCl.
EP patent. No 430190 describes a process similar to the one disclosed in U.S. Pat. No. 5,202,333.
Another similar process is described in J. Med Chem. 1993, 36, however, in this journal, the hydrogenation is performed on the hydrochloride salt of Cp9532. This hydrogenation is performed in the presence of acids, such as acetic acid and perchloric acid, providing a mixture of Palonosetron salts, which is transformed to Palonosetron free base is and then converted to Palonosetron HCl, providing it in moderate yields.
The hydrogenation step for converting the cyclic amide (referred to as Cp9532) to Palonosetron HCl is described in Organic process Research & development, 1997, 1, 117; wherein the cyclic amide or its salt analogue is used for the reaction. The use of the salt and high amounts of catalyst are described herein, leading to a ratio of about 1:1 of the below depicted isomers. Also reported is the use of the free base form of the amide leading to a better ratio of isomers, but also to Palonosetron contaminated with the starting material, a cyclic amide, an impurity difficult to purify from.
According to the processes described in the above patents and journal articles, Palonosetron HCl is obtained as a mixture of R and S isomers at carbon No. 3. Typically, in the mixture of R and S isomers prepared according to these processes the R and S isomers are present in such mixture in a 1:2.1 to 1:3.3 ratio (see Table 3 of OPRD 1997, 1, 117-120) or 43:57 ratio (when obtained by hydrogenating as hydrochloride) and a 30:70 ratio (when hydrogenating as base) (see J Med Chem, 1993, 36, 2645-2657).
However, only the 3aS isomer is reported to possess a higher affinity for 5-HT (see Current Opinion in Investigational Drugs 2002 Vol. 3 No 10 page 1502-1507).
Hence, providing a process for producing Palonosetron salt in high yields, high purity, especially from the starting cyclic amide, and with a good isomeric ratio is of benefit.

Processes for preparing palonosetron salts


A circuit wiring layout in a semiconductor memory device comprises first and second p-type MOS transistors having channels connected to each other in series, and first and second n-type MOS transistors having sources connected in parallel to a drain of the second p-type MOS transistor, the p- and n-type MOS transistors forming a decoder NOR gating portion. The first and second n-type MOS transistors having drains connected to first and second main lines, respectively, and sources connected to a section line. The first and second p-type MOS transistors having gates to which select signals for first and second accesses are applied, respectively. The first and second p-type MOS transistors share an active junction with each other in a first area. The first and second n-type MOS transistors are spaced from the first area in a direction of the section line and have independent active junctions.

1. Technical Field
The present invention relates to semiconductor memories, and more particularly, to layouts of a decoder in a volatile semiconductor memory device.
2. Discussion of Related Art
Performance trends of electronic systems, such as personal computers or communication devices, have led to high speed and high integration volatile semiconductor memories such as static random access memories (RAMs). More particularly, memory chip manufacturers have developed layout and fabrication techniques for memory cells as critical dimensions have decreased and as functional circuits have been implemented. As process techniques have been developed for reduced critical dimensions, techniques of laying out circuit wirings for peripheral circuits adjacent to a cell area, e.g., circuits in a functional circuit area called a cell core area, have become important in achieving higher integration circuits. A core logic, e.g., a section row decoder, functioning as an interface circuit needed to operate a unit memory cell is an example of a circuit laid out in the functional circuit area.
Within such devices (e.g., a section row decoder), to achieve high speed, read/write operations are performed in parallel with each other in one clock period or cycle. In the case of such semiconductor memory devices, circuits laid out in the functional circuit area become more complex, increasing a layout area. In addition, crosstalk caused by power and signal lines increases.
FIG. 1 is a timing diagram illustrating a data access operation in a typical high speed semiconductor memory device, and more particularly, a timing of a read pulse RD_WL and a write pulse WR_WL simultaneously applied to a word line in one clock period (Tc). A period T1 indicates a time period in which the read pulse is applied to the word line, and a period T2 indicates a read recovery time. Further, a period T3 indicates a time period in which the write pulse is applied to the word line and a period T4 indicates a write recovery time.
FIG. 2 is a diagram illustrating a configuration of a memory mat of a device to which the timing of FIG. 1 is applicable. Referring to FIG. 2, the memory mat, constituting a memory cell array, includes a plurality of blocks. Each block is divided into two memory blocks 100 and 110 by a section row decoder 200. Two main read and write word lines MWL_READ and MWL_WRITE of a main row decoder are connected to the section row decoder 200 in each block. The section row decoder 200 is connected to memory cells via four section word lines at a left side and four section word lines at a right side. Two pair of section word lines SWL_W and two pair of section word lines SWL_X are in the same logic state within one block. The memory mat further includes a main word line decoder (MWL DEC).
When a design rule of 80 or less nanometers is applied, and the cell pitch of the SRAM cell is reduced, it can become difficult to lay out a circuit of a section row decoder to match the reduced cell pitch.
Therefore, a need exists for a decoder having a reduced layout area.

Circuit wiring layout in semiconductor memory device


A computer implemented method and system for providing a Fast Fourier Transform (FFT) capability to a fixed point processor architecture is disclosed. In a first aspect the computer implemented method and system comprises providing an instruction set within the fixed point architecture. The instruction set includes a plurality of instructions to calculate at least one set of add operations within a FFT butterfly. The plurality of instructions are controlled by a mode register, wherein a plurality of vector register files and a scratch state memory provide input data to at the at least one set of add operations.

Fast Fourier Transform (FFT) algorithms require moving data in non sequential manner from arrays and to arrays. In addition the operations also form long data dependent chains. As a result using vector operations in FFT algorithms incurs a high cost in underlying hardware implementation.
Fixed point operations for such algorithms have a lower cost in hardware, but reduce the expected precision of the output. Hence, what is desired are systems and methods that address the above identified issues when implementing an FFT algorithm. The present invention addresses such a need.

Instruction set to enable efficient implementation of fixed point fast fourier transform (FFT) algorithms


In an image scanning system which can scan an image in a plurality of scanning modes, and has a memory for storing a correction data file which has correction data for each of the plurality of scan modes, correction data corresponding to a scan mode of a given image scan operation is read out from the memory upon scanning an image, and an image scan is executed using the readout correction data. If correction data corresponding to the scan mode of that image scan operation is not stored in the memory, correction data corresponding to the scan mode is generated, and is stored in the memory.

In a conventional image scanning apparatus, when the output level of an image sensor has varied due to a change in utilization environment of the apparatus or aging, the tone and color reproducibility of a scanned image becomes unstable and deteriorates. To solve this problem, an image scanning apparatus which can realize stable and high tone and color reproducibility even when the output level of the image sensor has varied due to a change in utilization environment of the apparatus or aging has been proposed (e.g., Japanese Patent Application Laid-Open No. 11-275310).
In the image scanning apparatus described in Japanese Patent Application Laid-Open No. 11-275310, upon scanning a document, a reference white background is scanned for each color light source prior to the beginning of the document scan, the output signal from the image sensor upon scanning the reference white background is converted into digital image data by an A/D converter, and it is checked if the maximum value of that image data falls within a predetermined range. If the maximum value of the image data falls outside the predetermined range, light amount adjustment of the corresponding light source is redone. More specifically, even when the output level of the image sensor has varied due to a change in utilization environment of the apparatus or aging, since the aforementioned process is executed occasionally upon scanning a document image, an image scan with stable and high tone and color reproducibility is realized.
On the other hand, as the image scanning apparatus has higher resolution, a buffer memory for an image process requires a large-capacity memory element. It is advantageous for power savings and a cost reduction to use a DRAM. However, since the access speed of the DRAM is lower than an SRAM, it may bottleneck the scan time. Such low access speed may sacrifice the scan time when a low-resolution scan is made using a high-resolution image sensing element.
To solve this problem a method of executing an image process for assuring an access time to the DRAM after image data is converted into the number of pixels corresponding to the scan resolution has been proposed. In this method, the drive speed of the image sensing element is changed for each scan mode, and a low-resolution scan can be done within a short period of time.
However, in the aforementioned method, since the drive speed of the image sensing element changes depending on the scan mode, fixed pattern noise caused by distortion of an analog signal and the dark current of the image sensing element changes. For this reason, to strictly execute shading correction, shading data must be acquired for each scan mode, and shading correction must be done based on that data.
In case of an image scanning apparatus using a high-resolution (e.g., 1200DPI) image sensing element, scan modes for resolutions of, e.g., 75DPI, 150DPI, 300DPI, 600DPI, and 1200DPI should be prepared by hardware in both color and gray modes. For this purpose, calibration data and shading data for each scan mode must be prepared. However, since the number of types of scan modes is large, several minutes to about 10 minutes may be required to collectively acquire these data in the first scan.
On the other hand, calibration data and shading data may be acquired for each scan. However, a longer time is required for each scan as the resolution increases.


A method for detecting a time synchronization ability of the real-time measuring device based on a time variable is provided. On a premise that the real-time measuring device correctly receives time service signals, the method aims at detecting time synchronization signal application ability of the real-time measuring device, and involves a purely resistive loop comprising a value transferring device and a time controllable switch. The method, via a time synchronization performance thereof, relatively completely reflects the time synchronization signal application ability of the device within a value transfer requirement. The method is a development upon power station time synchronization time service signals and transmission accuracy detection and an improvement of power station time synchronization detection procedures. The method facilitates improving real-time analysis and monitoring abilities of a power station and a power grid to a primary device and a primary system.

1. Field of Invention
The present invention relates to a power device detection method, and more particularly to a method for detecting a time synchronization ability of a real-time measuring device based on a timing variable, wherein the method detects a time synchronization signal application ability of the real-time measuring device through a measuring function of an electric real-time measuring device of a power station, on a basis of a manner of controlling breaking values of alternating signals and switch value signals at a designated time.
2. Description of Related Arts
In recent years, the improvement of the electronic equipment manufacture technology, the popularization and application of the satellite time service technology, and the establishment and perfection of the time synchronization technological standard in the power industry, all support the automation technology development of the regional power grid and the transformer substation, maintain the operation safety of the power grid, improve the real-time analyzing, judging and processing abilities about the power grid operation, and facilitate the effective implement of the unattended operational mode of the transformer substation is facilitated.
The physical time synchronization of the power station including the transformer substation and the switch field of the power plant, refers to the synchronization of functions of each Intelligent Electronic Device (IED) within the power station in a narrow sense; and refers to the synchronization of the functions of the related IEDs of each power station within a region in a broad sense. The inconsistency in the time synchronization of the power station IEDs causes the incorrect time sequence of the non-local/local real-time records and the illogical fault analysis which frequently exist in the power system, and affects the abilities of the power grid which include the real-time sample and analysis, the real-time manipulation and control, the precise fault judgment and the timely accident solution.
The electric secondary IEDs for real-time measuring and analyzing faults in the power station, such as the fault recorder and the Phasor Measurement Unit (PMU), mostly have the functions of real-time measuring the alternating quantity input and the switch value input; the time accuracy of the real-time records is usually required to reach the time synchronization level at milliseconds or at microseconds.
Based on the structure of the power station time synchronization system, according to the application site and the detection situations, the correctness of the IEDs time synchronization is mainly controlled by the three links including the time service device within the power station, the transmission of the synchronization time service signal and the time-seeking application of the IEDs which is the application correctness of the IEDs to the synchronization signals. Because the current technological standard has basically satisfied the normal application and detection of the former two links, apparently, detecting the time-seeking application of the IEDs becomes the key factor, also the spot where the on-site time synchronization problems frequently occur and the technological difficulty.
Most of the conventional on-site engineering applications aimed at detecting the IED time synchronization ability, adopt the qualitative validation manner of mutual verification according to the logical correlations among the device functions. The ultimate purpose of the power station time synchronization is to accomplish the IED function time synchronization of the power primary devices; in other words, the time section of the measurement and control of the primary devices is supposed to be determined, and real-time analyzing and monitoring the primary devices and the primary system by the power station and the power grid is supposed to be supported through the IED time synchronization. Thus the time synchronization ability of the IEDs is confirmed by the source-traceable time quantitative detection method through each function of the IEDs, based on the engineering technological principle of the source validation.
The Chinese patent 200820067196.6, controllable time scale signal source, and the Chinese patent 200810047989.6, method for detecting time information of output signals of satellite synchronization time service device, disclosed the conventional time controllable switch. Based on the mature application of the time controllable switch, combined with the alternating electricity principle of the purely resistive loop, a method for detecting the time synchronization ability of the real-time measuring device based on a time variable is provided.

Method for detecting time synchronization ability of real-time measuring device based on time variable

STATE GRID HUBEI ELECTRIC POWER RESEARCH INSTITUTE


An all weather inlet/exhaust structure (32) for an outdoor furnace (10,12,14) includes a generally rectangular upper compartment (40) having an imperforate upper wall (42) and horizontally louvered, vertical side walls (44) along with an imperforate bottom wall (46) with a generally central opening (48) therein. A lower compartment (56) in the form of an inverted truncated pyramid with its upper wall being defined by the lower wall (46) of the upper compartment is provided. The lower compartment has horizontally louvered, sloped, inwardly directed side walls (58) terminating in an open bottom (60) of smaller size than the first compartment lower wall (46). A generally rectangular inlet air duct (66) depends from the lower edges of the lower compartment side walls (58) and an exhaust duct (26) is disposed within the inlet air duct (66) and extends upwardly through the lower compartment (56) to the generally central opening (48) and the bottom wall (46) of the upper compartment (40).

Increasingly, the HVAC industry has resorted to locating heating, ventilating and air conditioning equipment on the exteriors of the structures which the systems are intended to service. For example, it is now commonplace, particularly in commercial installations, to mount HVAC equipment on the roof of a structure or on a pad adjacent to the structure.
The benefits of this practice are several. Perhaps the most prominent one is the fact that with exterior location of HVAC equipment, valuable interior floor space within a building which would normally be used to house the HVAC equipment is freed for other usages. Furthermore, because developers tend to conserve the interior space devoted to HVAC equipment, oftentimes internally mounted HVAC equipment is located in cramped quarters, making it difficult to service. This problem is overcome by mounting the HVAC equipment on the exterior of the structure to be serviced by such equipment, making access to it for servicing a much simpler job.
One difficultly encountered in mounting HVAC equipment on the exterior of a structure that it is to service resides in the possible ingestion into the system of foreign substances found in the ambient. For example, ingestion of rainwater may result in corrosion problems in the equipment. In some types of operations, ingestion of rainwater may also cause operational difficulty in operating the HVAC system.
In HVAC equipment such as furnaces which burn a combustible fuel, another difficulty presents itself. Furnaces typically have two ports to their surroundings. One port serves as an inlet for combustion air while the other port serves as an outlet for the products of combustion resulting from the fuel consumed by the furnace. Not untypically, such ports are located in spaced relation to one another to prevent products of combustion from being drawn into the inlet for the combustion air which, by reason of their composition, could reduce the oxygen content of the inlet combustion air stream and thereby affect the combustion process. At the same time, when the combustion air inlet and the exhaust outlet are located in substantially spaced relationship, difficulties associated with a difference in pressure at the two ports may deleteriously affect the combustion process. For example, exteriorly mounted units are exposed to the wind. Wind currents are not necessarily uniform at two spaced locations, particularly in urban areas where the presence of buildings or other structures may cause swirling winds to occur.
As a result, if the wind causes the pressure at the exhaust outlet to be greater than that at the combustion air inlet, there will be back flow of combustion gas toward the combustion chamber of the furnace. This may cause choking of the combustion process within the furnace which, in turn, can result in unconsumed hydrocarbon fuel ultimately being discharged to the ambient. Similarly, if the wind causes the pressure at the combustion air inlet to exceed that at the exhaust outlet, the resulting rush of air through the combustion chamber may cause partial or entire extinguishing of the flame within the combustion chamber. This, also, results in the discharge of unconsumed fuel to the ambient. Either occurrence will also affect the efficiency of the furnace and thereby interfere with the ability of the equipment to perform its intended, function within the HVAC system.
The present invention is directed to overcoming one or more of the above problems.

Inlet/exhaust structure for an outdoor furnace


A first terminal electrode has a first electrode portion disposed on a first face and connected to a first internal electrode, and a second electrode portion disposed on a third face and connected to the first electrode portion. A second terminal electrode has a first electrode portion disposed on a second face and connected to a second internal electrode, and a second electrode portion disposed on the third face and connected to the first electrode portion. Each of the second electrode portions of the first and second terminal electrodes, when viewed along a second direction perpendicular to the third face, is arranged with a gap in a third direction perpendicular to the second directions so as to sandwich at least a portion of an end in the first direction of an element body region sandwiched between the first internal electrode and the second internal electrode, at an end in the first direction of the second electrode portion.

1. Field of the Invention
The present invention relates to a multilayer capacitor.
2. Related Background Art
A known multilayer capacitor is one having a capacitor element body with a dielectric property having first and second faces facing each other, and a third face extending in a first direction in which the first and second faces face each other, so as to connect the first and second faces; a first internal electrode with an end exposed in the first face and a second internal electrode with an end exposed in the second face, the first and second internal electrodes being arranged in the capacitor element body so as to face each other in a second direction perpendicular to the first direction and to the third face, while sandwiching at least a portion of the capacitor element body; a first terminal electrode connected to the first internal electrode; and a second terminal electrode connected to the second internal electrode (e.g., cf. Japanese Patent Application Laid-open No. 2004-253425). In the multilayer capacitor described in the Laid-open No. 2004-253425, the first terminal electrode has a first electrode portion disposed on the first face and connected to the exposed portion of the first internal electrode in the first face, and a second electrode portion disposed on the third face and connected to the first electrode portion. The second terminal electrode has a first electrode portion disposed on the second face and connected to the exposed portion of the second internal electrode in the second face, and a second electrode portion disposed on the third face and connected to the first electrode portion.


A shutter device makes it possible to restrict bounding of a shutter blade using a shock-absorbing member when movement of the shutter blade is completed. In addition, the shutter device makes it possible to reduce production of dust that is produced when the shock-absorbing member and the shutter blade collide with each other. Examples of dust are wear powder and flake.

1. Field of the Invention
The present invention relates to a structure of a shutter device, and, more particularly, to a mechanism for preventing a shutter blade from bounding.
2. Description of the Related Art
In a related focal-plane shutter device, a shock-absorbing member for restricting bounding of a shutter blade is provided near a movement completion position of the shutter blade. When the shutter blade collides with the shock-absorbing member in a plane that is perpendicular to a movement direction of the shutter blade when the movement of the shutter blade is completed, shock generated by suddenly stopping the shutter blade is absorbed by the shock absorbing member, so that the bounding of the shutter blade occurring when the shutter blade is stopped can be restricted. Rubber is frequently used for the shock-absorbing member.
When the collision between the shutter blade and the rubber is repeated, scraping of the rubber is eventually started by the collision of the shutter blade, thereby producing wear powder. Unlike a film camera whose film can be replaced, in a digital camera, an image pickup element is accommodated in the camera body at all times. Therefore, when the wear powder adheres to the image pickup element, the wear powder may appear in an image.
To restrict the production of wear powder, Japanese Patent Laid-Open No. 09-005831 proposes a structure in which a surface of a shock-absorbing member that comes into contact with a shutter blade is covered with a material that is harder than the shock-absorbing member.
According to this structure, since the hardness of the surface of the shock-absorbing member that comes into contact with the shutter blade is made high due to the coating layer, wear powder is not produced often. In addition, shock that is produced when the shutter blade and the coating layer collide with each other can be absorbed by the rubber existing below the coating layer.
However, even if a shock-absorbing member whose rubber surface is provided with a coating layer using a material that is harder than rubber is used, the production of wear powder cannot be prevented from occurring. This is caused by the difference between the amount of deformation of the coating layer and the amount of deformation of the rubber when the shutter blade and the shock-absorbing member collide with each other.
The amount of deformation of the coating layer is less than the amount of deformation of the rubber when the shutter blade and the shock-absorbing blade collide with each other. This difference between the deformation amounts causes a force that tries to separate the coating layer and the rubber from each other to act upon the surface where the coating layer and the rubber are joined. Therefore, when the number of collisions between the shutter blade and the shock-absorbing member increases, the coating layer and the rubber are eventually peeled off from each other, thereby causing a flake of the peeled coating layer to adhere to the image pickup element.

Shutter device and image pickup apparatus


A liquid droplet measurement method and a liquid droplet measurement device with which the luminance contrast can be improved without making changes in, for example, the numerical aperture of a lens when the quantity of reflected light from the surface of the measurement target liquid droplet alone cannot provide a sufficient luminance contrast. A method and an apparatus for manufacturing a device are also provided. The liquid droplet measurement device includes: a measurement table having a surface with a recess and for holding a translucent sample substrate; an imaging section that applies light onto the sample substrate having formed thereon a liquid droplet, and measures quantities of reflected light from the sample substrate and the liquid droplet; and a measurement control unit that determines a volume or a surface shape of the liquid droplet using luminance information of the reflected light quantities measured by the imaging section.

A known example of a panel manufacturing method produces color filters of liquid crystal displays and devices such as organic EL displays. The panel manufacturing method ejects a functional material-containing fluid through a plurality of nozzles in the form of a liquid droplet using an inkjet method and forms a film of functional material on a print target.
Here, it is important to control and make the ejection amount of a liquid droplet constant by obtaining the correspondence between the settings of a control unit that controls the ejection amount of the liquid droplet, and the amount of the liquid droplet actually ejected. This is because unevenly ejected amounts of the liquid droplet cause thickness variation in the functional material, which leads to defective devices. For example, such thickness variation is perceived as an uneven color or uneven luminance in color filters and organic EL displays.
A method is known that checks the amount of the ink actually ejected through a nozzle. In this method, ink is ejected and applied to a substrate, and the volume or surface shape of a liquid droplet is found by calculating a slope at different locations on the ink droplet surface from brightness changes optically observed at these locations (JP-A-2015-125125).
In the method that calculates the volume or surface shape from the luminance information of a liquid droplet, the quantity of reflected light from the surface of the measurement target liquid droplet represents an important factor that determines the measurement accuracy.
However, the slope difference between the center and circumference portion of a liquid droplet becomes smaller as the measurement target liquid droplet becomes flatter. In this case, a sufficient contrast may not be obtained in the quantity of the reflected light at the liquid droplet surface. It may be possible to obtain contrast by making the numerical aperture (hereafter "NA") of the imaging lens smaller. However, with a smaller NA, the luminance obtained does not reflect the shape at the circumference portion of the liquid droplet, where the slope is large. That is, the surface reflection cannot provide a sufficient luminance contrast reflective of the slope when the measurement target liquid droplet has a flat shape.

Liquid droplet measurement method and liquid droplet measurement device, and method and apparatus for manufacturing device

PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.


Provided are methods for treating or preventing vasculopathy comprising administering to a subject in need thereof , ac composition comprising a mesenchymal stem cell (MSC), or a part of a culture medium that has been in contact with the MSC and comprises one or more components of the MSC, or an exosome derived from the MSC. Pharmaceutical compositions suitable for such treatment is also provided.

The present application relates to mesenchymal stem cells with anti-inflammatory properties, method of making such mesenchymal stem cells, materials obtained from such mesenchymal stem cells, the use of mesenchymal stem cells and materials obtained from mesenchymal stem cells in treatment of vasculopathy. Vasculopathy includes, but is not limited to, pulmonary arterial hypertension (PAH), other types of pulmonary hypertension, peripheral vascular disease (PVD), critical limb ischemia (CLI), coronary artery disease, and diabetic vasculopathy.
Pulmonary hypertension is a rare, progressive, and life-threatening disease affecting the pulmonary vasculature. Specifically, pulmonary hypertension results in increased pressure in the pulmonary vasculature, which can lead to heart failure among other outcomes. Currently, pulmonary hypertension is classified into the following groups under the World Health Organisation (WHO) clinical classification system (Dana Point 2008):
Group 1: Pulmonary arterial hypertension (PAH);
Group 1′: Pulmonary veno-occlusive disease (PVOD) and/or pulmonary capillary haemangiomatosis (PCH);
Group 2: Pulmonary hypertension due to left heart diseases;
Group 3: Pulmonary hypertension due to lung diseases and/or hypoxemia;
Group 4: Chronic thromboembolic pulmonary hypertension (CTEPH); and
Group 5: PH with unclear multifactorial mechanisms.
Pulmonary arterial hypertension is a specific type of pulmonary hypertension and, untreated, leads to death on average within 2.8 to 5 years after being diagnosed (Keily et al. (2013) BMJ 346:f2028). An increasing constriction of the pulmonary circulation leads to increased stress on the right heart, which may develop into right heart failure. By definition, the mean pulmonary arterial pressure (mPAP) in a case of chronic pulmonary hypertension is>25 mmHg at rest or>30 mmHg during exertion (normal value<20 mmHg). The pathophysiology of pulmonary arterial hypertension is characterized by vasoconstriction and remodeling of the pulmonary vessels. In chronic PAH there is neomuscularization of initially unmuscularized pulmonary vessels, and the vascular muscles of the already muscularized vessels increase in circumference. This resulting increase in pulmonary arterial pressures results in progressive stress on the right heart, which leads to a reduced output from the right heart and eventually ends in right heart failure (M. Humbert et al., J Am. Coll. Cardiol. 2004, 43, 13S-24S). PAH is a rare disorder, with a prevalence of 1-2 per million. The average age of the patients has been estimated to be 36 years, and only 10% of the patients were over 60 years of age. Distinctly more women than men are affected (G. E. D'Alonzo et al., Ann. Intern. Med. 1991, 115, 343-349).
Standard therapies available on the market (e.g., prostacyclin analogues, endothelin receptor antagonists, phosphodiesterase inhibitors) are able to improve the quality of life and the exercise tolerance of patients. These medicaments can result in serious side effects and/or must be delivered using complicated types of administration. Patients are frequently on combination therapy, either at the outset or after a deterioration in condition following monotherapy. Despite the advances in treatment, there is no cure for PAH.
Thus, a need exists to develop improved therapeutic compositions and methods for treating vasculopathy, including PAH.

Enhancement of MSC immunomodulatory properties by treprostinil


A Co--Pt based magnetic alloy which has been sputtered with an oxide or nitride of a primary constituent of the magnetic layer, e.g., CoO below about 10 at. %, provides improved coercivity, squareness, and reduced noise as compared to magnetic alloys with oxygen introduced by other methods. The alloy is vacuum deposited, for example, by sputtering, and the oxide or nitride may be introduced from the sputtering target from which the magnetic layer materials come or from a separate sputtering target. Examples of such oxides and nitrides include CoO, Co.sub.2 0.sub.3, Co.sub.3 O.sub.4, CrO.sub.2, Cr.sub.2 O.sub.3, TiO.sub.2, Ta.sub.2 O.sub.5, Al.sub.2 O.sub.3, WO, CoN, Co.sub.2 N, TiN, TaN, CrN, NiN, etc.

Recording performance for magnetic disks is commonly determined by three basic characteristics--PW50, overwrite, and noise. PW50 is the pulse width of the bits expressed in either time or distance, defined as the width of the pulse at half-maximum. A narrower (and more well-defined) pulse allows for higher recording density. A wide PW50 means that the bits are crowded together, resulting in each adjoining bits interfering with one another. This interference is termed inter-symbol interference. Excessive inter-symbol interference limits the packing density of bits in a given area, and hence limits the recording capacity of the magnetic media.
Means of reducing PW50 include reducing the magnetic remnant-layer thickness product ("Mrt") or reducing the thickness ("t") for a given alloy of the magnetic layer of the media (the media being comprised of a substrate, and one or more layers, including a magnetic layer, formed on the substrate). Another means of reducing PW50 is to increase hysteresis loop squareness ("S", including coercivity squareness, "S*", and remnant coercivity squareness, "S*rem"), and narrow the switching field distribution, as described by William and Comstock in "An Analytical Model of the Write Process in Digital Magnetic Recording," A.I.P. Conf. Proc. Mag. Materials, 5, p. 738 (1971). Yet another means for reducing the PW50 is to increase the coercivity ("Hc") of the media.
Overwrite ("OW") is a measure of the ability of the media to accommodate overwriting existing data. That is, OW is a measure of what remains of a first signal after a second signal (for example of a different frequency) has been written over it on the media. OW is poor when a significant amount of the first signal remains. OW is generally affected by the coercivity, the thickness, and the hysteresis loop squareness of the magnetic layer. For example, a high Hc can result in a recording head having difficulty saturating (i.e., writing data to) the magnetic layer, resulting in poor overwrite.
Noise performance of a magnetic layer can be defined in terms of read jitter and write jitter. Read jitter is primarily determined by the amount of signal available from a bit, and the electronic noise in the channel. A higher Mrt or thicker magnetic layer for a given alloy will typically provide reduced read jitter. Unlike read jitter, write jitter is determined by the intrinsic noise of the magnetic layer. Intrinsic media noise has been theoretically modeled by Zhu et al. in "Micromagnetic Studies of Thin Metallic Films", J. Appl. Phys., vol. 63, no. 8, p. 3248 (1988), which is incorporated by reference herein. Chen et al. describe the source of intrinsic media noise in "Physical Origin of Limits in the Performance of Thin-Film Longitudinal Recording Media," IEEE Trans. Mag., vol. 24, no. 6, p. 2700 (1988), which is also incorporated by reference herein. The primary source of intrinsic noise in thin film media is from interparticle exchange interaction. In general, the higher the exchange interaction, the greater the noise.
The noise from interparticle exchange interaction can be reduced by isolating the individual particles. This may be accomplished by spacing the grains apart from one another, or by interposing a non-magnetic material or insulator at the grain boundaries as described by Chen et al. in the aforementioned "Physical Origin of Limits in the Performance of Thin-Film Longitudinal Recording Media." The amount of separation need be only a few angstroms for there to be a significant reduction in interparticle exchange interaction. A reduction in interparticle exchange interaction has also been tied to an increase in Hc by Chen et al. and by Zhu et al. in the aforementioned references.
There is another interparticle interaction, called magnetostatic interaction, which acts over a much greater distance between particles as compared to the exchange interaction. Reducing the magnetostatic interaction does reduce intrinsic media noise slightly. However, the effects of magnetostatic interaction actually improve hysteresis loop squareness and narrow the switching field distribution, and hence improve PW50 and OW. Therefore, magnetostatic interaction is generally tolerated.
In peak-detection type recording channels, noise, together with inter-symbol interference, contributes to the uncertainty in the location of the individual bits, which cause the data to be read with some displacement in timing from that which is expected. This displacement is referred to as bit shift. Bit shift must be minimized for a given timing window of a bit in order to assure accuracy in reading that bit.
In order to obtain the best performance from the magnetic media, each of the above criteria--PW50, overwrite, and noise--must be optimized. This is a formidable task, as each of these performance criteria are inter-related. For example, obtaining a narrower PW50 by increasing the Hc will adversely affect overwrite, since increasing Hc degrades overwrite. A thinner media having a lower Mrt yields a narrower PW50, however the read jitter increases because the media signal is reduced. Increasing the squareness of the hysteresis loop contributes to narrower PW50, but generally increasing squareness increases noise. Thus, the amount that PW50 may be narrowed is limited by the increase in noise.
Providing a mechanism for separating or isolating the grains to break the exchange coupling can effectively reduce the intrinsic media noise and increase coercivity. Noise is improved by eliminating the interparticle exchange interaction. A slight further reduction of noise is possible by reducing magnetostatic interaction, but this reduces the hysteresis loop squareness and increases the switching field distribution, which degrades PW50 and overwrite.
In order to obtain the optimum media performance, the Mrt must be reduced for better overwrite and PW50, but still retain sufficient signal to maintain acceptable read jitter. This is principally accomplished by reducing the magnetic layer thickness (thereby reducing the space loss between the recording head pole tip and the magnetic layer), and using an alloy having a higher saturation magnetization ("Ms").
Therefore, an optimal thin film magnetic recording media for high density recording applications, i.e., that can support high bit densities, provides low noise without sacrificing the switching field distribution and squareness. Recording density can then be increased since bit jitter is reduced. In order to achieve optimal performance, the individual grains of the magnetic layer of the media must be isolated to eliminate the exchange interaction, and grains must be uniform and have a tight distribution of sizes to minimize intrinsic media noise while maintaining high coercivity and squareness.
One type of magnetic media which has allowed optimizing certain of the above performance criteria is based on alloys of cobalt (Co) and platinum (Pt). CoPt is typically alloyed with nickel (Ni), chromium (Cr), etc. Attributes of CoPt alloys have been described by Murdock et al. in "Roadmap to 10 Gb/in.sup.2 Media: Challenges", IEEE Trans. Mag., 1992, page 3078, by Opfer et al. in "Thin Film Memory Disk Development", Hewlett-Packard Journal (Nov. 1985), and by Aboaf et al., in "Magnetic Properties and Structure of Co--Pt Thin Film", IEEE Trans. Mag., page 1514 (1983), each incorporated herein by reference. Increasing storage capacity demands and performance requirements have motivated a search for ways to improve Co--Pt based alloys.
In order to control coercivity, it is known to sputter deposit the magnetic layer in the presence of gaseous oxygen or nitrogen, for example as taught by Yamashita et al. in U.S. Pat. No. 4,988,578, which is incorporated herein by reference. Also, in order to decrease the media noise, it is known to introduce oxygen into the magnetic layer in a concentration of 5 to 30 at. %, as taught by Howard et al. in U.S. Pat. No. 5,066,552, incorporated by reference herein. As with the teachings of Yamashita et al., Howard et al. teaches the formation of the magnetic layer of the disk by vacuum sputtering in an argon ambient into which oxygen has been introduced. According to these references, either oxygen or nitrogen is introduced into the magnetic layer from the ambient.
Shimizu et al. in "CoPtCr Composite Magnetic Thin Films", IEEE Trans. Mag., vol. 28, No. 5, page 3102 (1992), which is incorporated herein by reference, disclose co-sputtering an oxide of an impurity and the CoPtCr magnetic alloy. Specifically, the media noise, in-plane coercivity, and S* were noted to improve with an introduction of approximately 10% by volume ("vol. %") SiO.sub.2. This result is presumably obtained because the immiscibility of the oxide causes it to segregate at the magnetic grain boundaries, thereby reducing the intergranular exchange interaction (coupling) between the magnetic grains.
A variation on the approach of Shimizu et al. is disclosed by Howard in U.S. Pat. No. 5,062,938, which is incorporated herein by reference, in which an impurity such as yttrium (Y), silicon (Si), hafnium (Hf), germanium (Ge), tin (Sn) or zirconium (Zr) is co-sputtered with the cobalt-based magnetic alloy material. Thereafter, the sputtered layer containing the impurity is oxidized when annealed separately in the presence of oxygen. It is believed that the impurity elements will segregate at the grain boundaries, and when oxidized, break the exchange coupling between the grains.
There are a number of disadvantages to the introduction of impurities as taught by these references. First, the addition of an impurity material (e.g., 10% by volume SiO.sub.2 by Shimizu et al. and 12 atomic percent Y by Howard) results in an excessive decrease in Ms. Therefore, the thickness of the magnetic layer must be increased to maintain Mrt. This is undesirable because an increase in layer thickness is generally accompanied by an increase in space loss between the head and the media which results in broad PW50 and poor overwrite. Second, the sputtering process is made more complex and more costly by the requirement that additional materials be sputtered. The additional step of oxidizing a sputtered layer also adds to the complexity and cost of the sputtering process. Third, introduction of oxygen or nitrogen from a gas in the sputtering environment is a difficult process to control precisely, and variations in oxygen or nitrogen concentrations from disk to disk through sputtering is not uncommon. This is particularly true for individual-disk sputtering systems such as those manufactured by Intervac Corp. and others.
Therefore, there is at present a need in the art for a method of reducing media noise without jeopardizing other media performance characteristics such as high coercivity, high degree of squareness, high SNR, high overwrite, and low PW50.

Method of sputtering selected oxides and nitrides for forming magnetic media


A limp, porous membrane (18) is formed from a flexible sheet material (20). The membrane is used with a fluidized hopper outlet (10) containing a pulverant, particulate lading which is fluidized and unloaded via the outlet. A valve installed in the outlet, when open, extends substantially through the outlet and allows fluidized lading to be unloaded through the outlet. The outlet has a frame (12) for securing the outlet to the hopper, an outlet opening (14) in which the valve is positioned, and intersecting outlet walls (16) extending between the frame and the opening. An outer margin (54) of the membrane is secured to the frame. An inner margin (18) of the membrane, which defines an opening for the lading, is attached to a boot (36). The boot is secured to the top of an outlet pan (P), adjacent the outlet opening, by a retainer ring (50). The ring locks the boot in place so the opening in membrane is secured adjacent to the outlet opening for the lading to flow into the outlet through the valve.

This invention relates to a limp, porous membrane of a sheet or cloth material and, more particularly, to a cloth material used as a membrane for a fluidized outlet in a covered hopper railway car.
It is known to use a cloth material in an outlet assembly for a covered hopper railway car. See, for example, U.S. Pat. No. 4,846,377 which is assigned to the same assignee as the present invention. However, while cloth membranes are advantageous, their usefulness has heretofore been limited. For example, the cloth membrane structure disclosed in this earlier patent shows installation of the membrane between the bottom of an outlet pan (7 in the patent drawings) and an outlet manifold (19 in the drawings). Such an assembly works well for certain types of outlets. Where, however, an outlet valve such a butterfly valve is positioned in the outlet, the installation shown in the '377 patent is not feasible. Nonetheless, it is still important to use a cloth membrane installation with such outlets so the advantages enumerated in the '377 patent can still be realized.

Cloth fluidizing membrane for hopper car outlet


A protection circuit module (PCM) integrated cap assembly includes a cap plate including an electrically conductive material and defining a through hole passing from a first surface of the cap plate to a second surface of the cap plate, a wiring unit including an electrically conductive material and a circuit pattern, and facing the first surface of the cap plate, wherein a first edge of the wiring unit is electrically coupled to the cap plate, and wherein a second edge of the wiring unit extends through the through hole of the cap plate a first insulating unit in a space of the circuit pattern a second insulating unit between the second edge of the wiring unit and a portion of the cap plate defining the through hole, and at least one electrical component coupled to the circuit pattern.

1. Field
One or more embodiments of the present invention relate to secondary batteries.
2. Description of the Related Art
A secondary battery, or rechargeable battery, is both chargeable and dischargeable, and is distinguished from a primary battery, which is incapable of being recharged. The secondary battery is widely used in electronic fields related to mobile phones, smart phones, tablet personal computers (PCs), digital cameras, electric vehicles, electric bicycles, and uninterruptible power systems (UPSs).
Secondary batteries may be divided into a can-type secondary battery, which may be cylindrically shaped or angularly shaped, and a pouch-type secondary battery, which has flexibility according to the shape of a case in which the secondary battery is accommodated.
In the case of the angularly shaped (e.g., angled shape) secondary battery disclosed in Korean Patent Publication No. 2011-0016394 (Feb. 17, 2011), a cap assembly is combined with a cell, and a protection circuit module (PCM) integrated cap assembly is combined with the cap assembly. Because the PCM integrated cap assembly should be mechanically and electrically coupled to the cap assembly, a welding process or a bolting process is applied to the connection between the PCM integrated cap assembly and the cap assembly. To weld the PCM integrated cap assembly to the cap assembly, special equipment may be used, and also, in the case of the bolting process, additional parts, such as bolts, and additional work are needed. Accordingly, from a perspective of workability and costs, the welding process and the bolting process are inefficient.

Protection circuit module integrated cap assembly, and method of manufacturing cap assembly and secondary battery


An apparatus for retaining a workpiece and a method of fabricating same. The apparatus contains an electrostatic chuck having a workpiece support surface. The workpiece support surface has protruded regions and non-protruded regions, where a total surface area of the protruded regions is less than a total surface area of the non-protruded regions. The apparatus contains a pedestal having a surface that supports a flex circuit. The topography of the chuck is formed by either machining the surface of the pedestal prior to adhering and conforming the flex circuit to the surface or sculpting the surface of an electrode within the flex circuit.

1. Field of the Invention
The invention relates generally to electrostatic chucks for holding a workpiece and, more specifically, to an improved topographical structure of a support surface of an electrostatic chuck to improve heat transfer gas distribution along the bottom surface of the workpiece.
2. Description of the Background Art
Electrostatic chucks are used for holding a workpiece in various applications ranging from holding a sheet of paper in a computer graphics plotter to holding a semiconductor wafer within a semiconductor wafer process chamber. Although electrostatic chucks vary in design, they all are based on the principal of applying a voltage to one or more electrodes in the chuck so as to induce opposite polarity charges in the workpiece and electrodes, respectively. The electrostatic attractive force between the opposite charges pulls the workpiece against the chuck, thereby retaining the workpiece.
In semiconductor wafer processing equipment, electrostatic chucks are used for clamping wafers to a pedestal during processing. The pedestal may form both a cathode and a heat sink. Electrostatic chucks find use in etching, chemical vapor deposition (CVD), and physical vapor deposition (PVD) applications. More specifically, the electrostatic chuck has a flex circuit covering a support surface of the pedestal. The flex circuit is comprised of a top layer of dielectric material covering a conductive electrode. Below the electrode is a bottom layer of dielectric material. The top and bottom dielectric layers encapsulate the conductive electrode.
In a "unipolar" electrostatic chuck, voltage is applied to the conductive electrode relative to some internal chamber ground reference. Electrostatic force is established between the wafer being clamped and the electrostatic chuck. When the voltage is applied, the wafer is referred back to the same ground reference as the voltage source by a conductive connection to the wafer. Alternatively, a plasma generated proximate the wafer can reference the wafer to ground, although some voltage drop occurs across plasma sheaths that form at both the wafer being clamped and the reference electrode.
The materials and processes used to process a wafer are extremely temperature sensitive. Should these materials be exposed to excessive temperature fluctuations due to poor heat transfer from the wafer during processing, performance of the wafer processing system may be compromised resulting in wafer damage. To optimally transfer heat between the wafer and chuck, a very large electrostatic force is used in an attempt to cause the greatest amount of wafer surface to physically contact the support surface. However, due to surface roughness of both the wafer and the chuck, small interstitial spaces remain between the chuck and wafer that interfere with optimal heat transfer.
To achieve further cooling of the wafer during processing, an inert gas such as Helium is pumped into the interstitial spaces formed between the wafer and the support surface of the chuck. This gas acts as a thermal transfer medium from the wafer to the chuck that has better heat transfer characteristics than the vacuum it replaces. To further enhance the cooling process, the chuck is typically water-cooled via conduits within the pedestal. This cooling technique is known as backside gas cooling.
Since the distribution of Helium to the interstitial spaces is osmotic and the interstitial spaces may not be interconnected, some spaces do not receive any Helium. This condition can lead to a non-uniform temperature profile across the wafer during processing and result in wafer damage. Since effective and uniform heat conduction away from the wafer is an important aspect of the manufacturing process, establishing a uniform Helium layer within the wafer to chuck interface should contribute to uniform heat transfer from the wafer. As such, backside gas cooling art developed based on this premise.
However, the physical limitations of existing technology used to electrostatically clamp large diameter (e.g., 200 mm or more) wafers do not provide the necessary conditions for a uniform distribution of Helium in all of the interstitial spaces beneath the wafer. Existing pedestal topographies limit the effectiveness of the heat transfer process because they have a generally flat top support surface and the wafers have a generally flat bottom surface. Ideally, these flat surfaces would have no defects or deviations so that 100% of the bottom surface of the wafer would contact the top support surface of the pedestal to allow for maximum heat transfer from the wafer to the pedestal. Topographical anomalies create a condition where not all of the wafer is in contact with this support surface. As such, the aforementioned interstitial spaces could form and distribution of the heat transfer gas becomes uneven and uniformity of wafer temperature is compromised. Consequently, during processing, the temperature non-uniformity may result in non-uniform processing and wafer damage.
Therefore, there is a need in the art for an improved topographical structure of an electrostatic chuck that improves temperature uniformity across the wafer without adding considerably to manufacturing costs.

Topographical structure of an electrostatic chuck and method of fabricating same


A display device (100) is provided with: a display panel (110); a light guide member (150) provided in a frame shape at a periphery of the display panel (110) on the viewing side, the light guide member (150) guiding the light that performs image display on the display panel (110) to outside of the display panel (110); and a transparent sheet-shaped covering member (140) laminated on the surface of the display panel (110) on the viewing side, with a portion of the covering member (140) provided in-between the light guide member (150) and the display panel (110). The light guide member (150) is bonded to the surface of the covering member (140) by an adhesive agent (151).

The development of big-screen displays for use with digital signage and the like has been robust recently. In particular, attention has been focused on multi-display systems, where a plurality of narrow-frame displays are combined together to form a big screen.
When combining a plurality of displays to form this big screen, it is preferable for the seams of the displays to be hard to see. Therefore, there have been attempts to make these seams harder to see by arranging a frame-shaped light-guiding member such as a lens at the periphery of each display (Patent Document 1, for example).

Display device, multi-display system and method for manufacturing display device