To provide a TFT that can operate at a high speed by forming a crystalline semiconductor film while controlling the position and the size of a crystal grain in the film to use the crystalline semiconductor film for a channel forming region of the TFT. Instead of a metal or a highly heat conductive insulating film, only a conventional insulating film is used as a base film to introduce a temperature gradient. A level difference of the base insulating film is provided in a desired location to generate the temperature distribution in the semiconductor film in accordance with the arrangement of the level difference. The starting point and the direction of lateral growth are controlled utilizing the temperature distribution.

1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor film that is formed on a substrate having an insulating surface and that has a crystal structure, and to a method of manufacturing a semiconductor device using this semiconductor film as an active layer. More specifically, the present invention relates to a semiconductor device using a crystalline semiconductor film as an active layer and to an electronic apparatus using the semiconductor device as a display unit.
2. Description of the Related Art
In recent years, some have sought advantage in forming a channel forming region from a single crystal, which has less defects, with regard to improvement in mobility of low temperature polycrystalline silicon and to drop in Ioff. A related technology has thus been developed which includes forming an amorphous semiconductor film on a light transmissive substrate with an insulating surface, and crystallizing the film by laser annealing, thermal annealing, etc., to use the obtained crystalline semiconductor film as an active layer of a thin film transistor (hereinafter referred to as TFT).
Laser annealing is known as a crystallizing technology capable of imparting high energy only to an amorphous semiconductor film to crystallize the film. In particular, an excimer laser emitting shortwave light of 400 nm wavelength or less is a representative laser that has been used since early stages of development of laser annealing echnology. In addition to the excimer laser annealing, a technique using YAG laser which is a solid state laser has been developed lately. In the laser annealing mentioned above, a laser beam is processed by an optical system so as to take a spot-like shape or a linear shape on an irradiation surface, and the irradiation surface on a substrate is scanned with the processed laser light (irradiation position of laser light is moved relative to the irradiation surface). For instance, excimer laser annealing using linear laser light is capable of annealing the entire irradiation surface with laser by merely scanning in one direction that is perpendicular to the longitudinal direction of the surface. The excimer laser annealing using linear laser light is thus superior in productivity and is becoming the mainstream in techniques of manufacturing liquid crystal display devices using TFTs. This laser annealing technique has realized a monolithic type liquid crystal display device in which TFTs constituting a pixel portion (pixel TFT) and TFTs constituting driver circuits provided in the periphery of the pixel portion are formed on one glass substrate.
However, the crystalline semiconductor film formed by laser annealing is an accumulation of plural crystal grains, and the crystal grains are positioned at random in the film and the size thereof is irregular. In the TFT fabricated on the glass substrate, the crystalline semiconductor film is divided and formed into an island-like pattern with the intention of partitioning elements. It is therefore impossible to form the TFT with the position and the size of crystal grains specified. The interface of the crystal grains (crystal grain boundary) has a recombination center and a trapping center caused by the amorphous structure, crystal defects, etc., which are factors in degrading the current transportation characteristic of carriers. The potential level in the crystal grain boundary also affects this characteristic.
The crystallinity of a semiconductor film in a channel forming region has a great influence on a TFT characteristic. However, it is almost impossible to form the channel forming region from a single crystal semiconductor film while removing the adverse influence of the crystal grain boundary.
Attempts at growing the crystal grains larger have been made in order to solve this problem. For instance, a method of laser annealing has been reported in "High-Mobility Poly-Si Thin-Film Transistors Fabricated by a Novel Excimer Laser Crystallization Method", K. Shimizu, O. Sugiwara and M. Matsumura, IEEE Transactions on Electron Devices, vol. 40, No. 1, p.p. 112–117, 1993. According to the method, a three-layer film consisting of Si, SiO2, and Si is formed on the substrate and both sides of the device, i.e., the three-layer film side and the substrate side, are irradiated with excimer laser light. The article states that the method is capable of enlarging the size of the crystal grains by laser light irradiation with a certain energy intensity.
The method proposed by K. Shimizu et al., is characterized in that a thermal characteristic of a base material of an amorphous silicon film is changed locally to control the heat flow to the substrate and to introduce a temperature gradient. In order to introduce the temperature gradient, a three-layer structure consisting of a high melting point metal layer, a silicon oxide layer, and a semiconductor film is formed on a glass substrate. Structurally speaking, to fabricate a top gate type TFT with this semiconductor layer as an active layer is not impossible. However, the silicon oxide film provided between the semiconductor film and the high melting point metal film generates parasitic capacitance and increases power consumption, making it difficult to obtain a TFT operating at a high speed.
Other methods such as a method that uses lasers having a phase difference and the step irradiation method, also have a problem and require a complicated laser apparatus. In addition, when applied to crystallization of driving elements of a liquid crystal panel having a driver circuit incorporated therein, the methods may not always be successful in enabling all part of the channel forming region to have a large grain, nor in crystallizing them into a single crystal, for the elements are usually arranged irregularly, not with regular intervals.
There is another method that is a combination of the dual beam method and the three-layer island structure. (The dual beam method is a method in which an amorphous semiconductor film is crystallized by irradiating each side of a substrate with a laser, or by irradiating one side of a substrate with a laser and then irradiating the other side of the substrate with the laser transmitted through the substrate and reflected by a mirror or the like.) When applied to crystallization of driving elements of a liquid crystal panel having a driver circuit incorporated therein, the combination method is capable of crystallizing a designated site into a single crystal, but is not good at growing a crystal grain to as large a grain size as 5 μm or more. Therefore the method is not suitable for manufacturing a thin film transistor whose channel width is wide. The method also generates a parasitic capacitance between a metal and Si, causing signal delay. Furthermore, the method has a problem of peeling because the temperature sometimes reaches high at a time of irradiation depending on the metal material used.
A method in which a base film is formed from a highly heat conductive insulating film has an advantage in that a parasitic capacitance is not generated between the metal and Si. However, the method requires a development of a highly heat conductive insulating film that is stable.

Semiconductor device and a method of manufacturing the same

Semiconductor Energy Laboratory Co., Ltd.


An image forming apparatus includes a drawer unit configured to be drawn out from a body of the image forming apparatus. The drawer unit includes a carriage path for carrying a recording medium, a lock unit configured to lock the drawer unit in the body, a driving unit configured to drive the lock unit, the driving unit including at least a driving source, and a drawer unit cover configured to cover at least the drawer unit. The drawer unit cover is a part of an outer cover of the body arranged on a side in a drawing direction of the drawer unit. The drawer unit cover is attached to the drawer unit so that the drawer unit cover is removed from the drawer unit in a state where the drawer unit is attached to the body.

1. Field of the Invention
The present invention relates to an image forming apparatus, such as a printer, a facsimile, and a copier.
2. Description of the Related Art
In general, in an image forming apparatus in which an electrostatic photographic process is utilized, a sheet of paper as a recording medium contained in a sheet feeding unit is carried to an image forming unit through a sheet feeding carriage path, and a toner image formed by the image forming unit is transferred. The sheet of paper on which the toner image is transferred is carried to a fixing apparatus, and the toner image on the sheet of paper is fixed. The sheet of paper with the fixed toner image is carried to a sheet discharge tray through a sheet discharge path, or carried to a reversing carriage path. The sheet of paper carried to the reversing carriage path is reversed, and carried to the image forming unit again, thereby the toner image on the back surface of the sheet of paper is transferred.
Japanese Patent No. 4484210 discloses an image forming apparatus which includes a drawer unit. The drawer unit contains the above-described sheet feeding carriage path, the above-described fixing apparatus, the above-described reversing carriage path, and the above-described sheet discharge path. The drawer unit can be drawn out from the image forming apparatus body. When a jam occurs in the carriage path contained in the above-described drawer unit, the drawer unit is drawn out from the apparatus body, thereby easily removing the sheet of paper therefrom.
In the image forming apparatus disclosed in Japanese Patent No. 4484210, when drawing out the drawer unit from the apparatus body, it is drawn out in accordance with the following procedure. First, the front cover is opened to expose the drawer unit. Next, the lock is released by operating a lock lever locking the drawer unit in the apparatus body, to draw out the drawer unit. Accordingly, in the image forming apparatus disclosed in Japanese Patent No. 4484210, it is necessary that the front cover is opened and the lock lever is operated, to draw out the drawer unit. Thus, many operations are required for drawing out the drawer unit, resulting in a problem of decreasing the work efficiency.
The applicant of the present invention has worked the following image forming apparatus under development. That is, it is an image forming apparatus in which a front cover as an outer cover is fixed to a drawer unit, and in which the drawer unit locked in the apparatus body is automatically unlocked using a motor as a driving source.
In the image forming apparatus under development, if a jam occurs in a carriage path of the drawer unit, the drawer unit is automatically unlocked by driving a motor provided in the drawer unit. When a user removes a sheet of paper in the carriage path of the drawer unit, the front cover is drawn out toward the front, thereby drawing out the drawer unit. Accordingly, in the image forming apparatus under development, when the user draws out the drawer unit, only an operation for drawing out the front cover is necessary. Thus, as compared to the image forming apparatus disclosed in Japanese Patent No. 4484210, an easier operation is necessary for drawing out the drawer unit. This results in enhancing the work efficiency for a jam process.
However, in the image forming apparatus under development, the drawer unit is not possibly drawn out from the apparatus body, if the motor unlocking the drawer unit is damaged. As a result, the drawer unit is not possibly exposed, causing another problem that it is very difficult to replace the damaged motor.
Therefore, there is a need to provide an image forming apparatus, in which a drawer unit can be drawn out with an easy operation, and a damaged driving source can easily be replaced even if the drawer unit is not possibly drawn out due to the damaged driving source.

Image forming apparatus having drawer unit


A battery includes a pair of an anode electric power generating source element and a cathode electric power generating source element for generating an electric power, and a container receiving therein the electric power generating source elements. The container includes a breakable portion which is breakable such that a gas from at least a part of the electric power generating source elements is allowed to flow out of the container therethrough when a pressure in the container increases excessively. The battery further includes a variable throttle for the gas which is elastically deformable by the pressure in the container such that the gas is allowed to flow out of the container.

The present invention relates to a battery including a gas discharge mechanism for releasing an excessively increased inner pressure, particularly preferable for an alkaline battery.
In an alkaline battery disclosed by JP-A-59-98452, a breakable portion of a sealing member is broken by an excessively increased inner pressure of the battery so that a gas generated in an inside of the battery by an erroneous use of the battery is discharged from the sealing member to an outside of the battery through a gas discharge port formed on an anode end plate, and the excessively increased inner pressure is released.

Matsushita Electric Industrial Co., Ltd.


A wireless transceiver circuit with an impedance matching network within an integrated circuit is disclosed. In some embodiments, the impedance matching network utilizes an inductor, having two portions, disposed on two different metal layers of the integrated circuit. The first end of the first portion of the inductor is in communication with an antenna. The second end of the second portion is in communication with a low noise amplifier for receiving signals and a power amplifier for transmitting RF signals. The second end of the first portion is connected to the first end of the second portion using a via. In another embodiment, the two portions are disposed on the same metal layer, wherein one portion is disposed within the other with a gap separating the two portions. These configurations require less space than using two separate inductors and also have a low coupling coefficient.

Wireless devices typically utilize a wireless transceiver to send and receive wireless data over a wireless network. The wireless transceiver includes circuitry needed to transmit and receive wireless signals.
To transmit data, the transceiver modulates the desired signal with a carrier frequency and amplifies the resulting signal using a power amplifier. This power amplifier is in communication with an antenna. The transceiver may include various components, such as oscillators, filters, mixers and amplifiers, in order to transmit data.
To receive data, the transceiver amplifies the received signal, and demodulates the amplified signal to obtain the wireless signal. The transceiver may include a low noise amplifier (LNA), demodulator, filters and other components, in order to receive the data.
When a single antenna is used, the power amplifier in the transmit portion of the transceiver and the LNA in the receive portion of the transceiver may both be in communication with the antenna.
Impedance matching between the power amplifier and the antenna helps maximize the power delivered to the antenna. This may be achieved by transforming the impedance of the antenna to the required impedance at the output of the power amplifier to achieve the required output power. Similarly, impedance matching between the antenna and the LNA help maximize the power delivered to the LNA. This may be achieved by matching the impedance of the antenna to the input impedance of the LNA.
Since the impedance required at the output of the power amplifier and the input impedance of the LNA may differ, separate impedance matching networks may be used to achieve maximum power efficiency.
FIG. 1 shows one such prior art configuration that may be disposed within a wireless device 10. The antenna 20 is connected to the wireless transceiver circuit 30, which may be disposed within an integrated circuit. The integrated circuit may include a first pad 35 which is used to connect the input of the LNA 31 with components located outside the integrated circuit. A first impedance matching network 50 in in communication with the first pad 35. The first impedance matching network 50 may be used to match the impedance of the antenna, represented as ZANT to the input impedance of the LNA 31.
Additionally, a second pad 36 may be used to connect the output of the power amplifier 32 with components located outside the integrated circuit. A second impedance matching network 60 is in communication with the second pad 36. The second impedance matching network 60 may be used to transform the impedance of the antenna, represented as ZANT, to the required impedance at the output of the power amplifier 32.
In operation, the wireless transceiver circuit 30 is either in transmit mode or in receive mode. When in receive mode, switch S1 in switching network 40 is closed, while switch S2 is open. When in transmit mode, the switch S2 is closed while switch S1 is open.
For energy-efficient transceivers, the first impedance matching network 50 may be a step-up matching network working as a passive voltage amplifier in front of the LNA 31 to minimize the required transconductance (gm) of the LNA 31, thereby achieving a low noise figure (NF). Reducing gm of the LNA 31 implies that the LNA 31 needs less DC current, reducing the power consumption of the receiver (RX). In some embodiments, the first impedance matching network 50 may be implemented as a series inductor to resonate with the input capacitance of the LNA 31.
The design of the second impedance matching network 60 may depend on the maximum output power of the PA. For example, the second impedance matching network 60 may be a pi-network of C-L2-C to transform the antenna impedance to the desired resistance at the output of power amplifier 32 (RPA). The maximum output power of the power amplifier 32 is determined by its supply (VddpA) and RPA. For a class D power amplifier, the maximum output power is calculated as:
      P       m        a        x       ≈         2         π     2                      V           d            d            P            A          2             R           P            A
Utilizing external impedance matching circuits allows higher quality factor inductors to minimize the insertion loss of the matching network. However, these external components increase the amount of space needed and also increase cost.
FIG. 2 shows a prior art configuration that incorporates the impedance matching network within the integrated circuit. In this embodiment, the LNA 131, the power amplifier 132 and the impedance matching network are all disposed within the wireless transceiver circuit 130, which is disposed within integrated circuit. The LNA 131 and the power amplifier 132 are connected to a shared node. A pad 135 is used to allow connection of the antenna 120 to the on-chip impedance matching network. Thus, the impedance matching network is disposed between the pad 135 and the shared node.
In certain embodiments, the impedance matching network is configured as two step-up L-networks, each comprising a capacitor and an inductor. Thus, one L-network comprises series inductor L3 and shunt capacitor C1, and the second L-network comprises series inductor L4 and shunt capacitor C2.
Because the impedance of the impedance matching network is different for transmission and reception, at least one of the components must be variable. In the configuration shown in FIG. 2, the shunt capacitors, C1 and C2 are both tunable. For example, these capacitors may be in communication with a control circuit 170 that is capable of adjusting the values of C1 and C2.
Thus, in receive mode, the control circuit 170 manipulates the shunt capacitors so that the antenna impedance (ZANT) matches the input resistance of the LNA 131. In transmit mode, the control circuit 170 manipulates the shunt capacitors so that the antenna impedance (ZANT) matches the output resistance of the power amplifier 132.
In certain embodiments, the input resistance of the LNA 131 may be 300Ω or more. In certain embodiments, in receive mode, where LNA 131 is enabled and the power amplifier 132 is disabled, C1 is set to minimum capacitance to maximize voltage gain before the LNA 131, so as to minimize the noise figure of the LNA 131. If C1 is set to a minimum value, it may be ignored such that the L3+L4 and C2 form a single L-network to step-up ZANT to RLNA.
The resistance of the receive mode, which is the maximum resistance, may be defined as:Rmax=Re(ZANT)*(1+Qmax2), where
          Q         m          a          x          =                         ω       0            ⋆             (                        L         3                +                 L         4                      )                +           Im            (             Z               A                N                T                   )                  Re          (           Z             A              N              T                )           , where Qmax is the quality factor of the matching network in receive mode setting.
Thus, for a center frequency of about 2.45 GHz, a desired maximum resistance of 300Ω, and an antenna impedance of 50Ω, Ωmax is roughly 2.23 and L3+L4 is in the range of 7-8 nH.
Further, the capacitance of C2 in this configuration is defined as:
      C       2    ,              m          a          x           =         Q         m          a          x                   ω     0        ⋆         R           m            a            x
Thus, C2,max is in the range of 500 fF.
The impedance matching network may achieve its minimum resistance during transmit mode. It is preferable to see real resistance RPA at the output of the power amplifier 132 to achieve maximum efficiency for the power amplifier 132. Assuming VddPA as 1.2 V and Pmax of 3 dBm (extra 2 dB to compensate the insertion loss of the matching network and 1 dB for non-ideal operation of class D power amplifier), RPA should be 145Ω approximately. L3, L4 and C1 values will determine RPA value. As described above, L3+L4 is defined by receive mode; therefore C1 and L3 are used to determine RPA.
For minimum insertion loss, the matching network may be designed using two step-up L-networks. This circuit may be evaluated in series, looking first at the first stage L-network, closest to the antenna. In this case, L3 and C1,opt form an L-network transforming ZANT to an intermediate real shunt resistance R3,opt. R3,opt can be calculated as:R3,opt=Re(ZANT)*(1+Q32), where
      Q   3    =                    ω      0          ⋆           L      3             +         Im          (           Z             A              N              T                )              Re        (         Z           A            N            T             )      The optimal value for C1 can be calculated as:
      C       1    ,    opt       =              Q     3                   ω      0          ⋆           R             3       ,       opt                     =                         ω       0                         L       3                +           Im            (             Z               A                N                T                   )                        ω      0          ⋆           [                              (                   Re                    (                     Z                       A                        N                        T                               )                  )                2              +                        (                                          ω            0                                             L            3                               +                     Im                      (                       Z                         A                          N                          T                                  )                            )                2                   ]               Similarly, the second stage L-network may be evaluated as follows:R4,opt=R3,opt*(1+Q42), where
      Q   4    =              ω     0        ⋆         L     4              R         3     ,     opt          The optimal value for C2 can be calculated as:
      C       2    ,    opt       =              Q     4                   ω      0          ⋆           R             4       ,       opt                     =                         ω       0                         L       4                             ω       0            ⋆             [                        R                   3          ,          opt                  2                +                           (                                 ω            0                                             L            4                               )                  2                      ]                   =               L      4                       R               3        ,        opt              2            +                     (                           ω          0                                     L          4                         )              2                     Thus, the input impedance can be given by:
          R         P          A          =            R           4      ,      opt             =                      R               3        ,        opt                   ⋆             (               1        +                 Q         4         2                      )                =                  R               3        ,        opt                   +                              (                              ω           0                                         L           4                            )                2                      R                 3         ,         opt                                     ,
As described above, the sum of L3 and L4 is given by the maximum input impedance in receive mode. The individual values for L3 and L4 may be determined based on the desired output impedance in transmit mode. By using the previous equations, R3,opt can be deduced from Re(ZANT), Rmax and R4,opt:
                            R               3        ,        opt                          Re              (               Z                 A                  N                  T                      )                -     1          +                  R             3       ,       opt                      Re            (             Z               A                N                T                   )             ⋆                              R                 4         ,         opt                              R                 3         ,         opt                           -      1                =                    R             m              a              x                      Re            (             Z               A                N                T                   )             -    1      which can be solved numerically.
When the circuit of FIG. 2 is designed in an integrated circuit, the resulting layout may be as shown in FIG. 3. L3 is shown on the left and may be an octagonal coil disposed on an upper metal layer of the integrated circuit. In this embodiment, L3 has an inductance of 2.6 nH and 3.5 turns. L3 may have an inner diameter of at least 80 μm and an outer diameter of 120 μm. This configuration is based on the following parameters: a center frequency of 2.45 GHz, RANT of 50Ω), RPA of 145Ω, and RLNA of 300Ω. L4 is shown on the right and may also be an octagonal coil disposed on an upper metal layer of the integrated circuit. In this embodiment, L4 has and inductance of 4.7 nH and 4.5 turns. L4 may also have an inner diameter of at least 80 μm and may have an outer diameter of 135 μm. This configuration is based on the parameters described above. Of course, other dimensions are also possible. A metal trace 180 may be used to connect L3 and L4. If L3 and L4 are both disposed on the higher metal layer, the metal trace 180 that connects them may be on the lower metal layer. Vias 181, 182 may be used to connect the metal trace 180 to the two inductors. C1 is also in communication with this metal trace 180. C2 may be disposed near the LNA and power amplifier. A second metal trace 185 may be used to connect L4 to the LNA and power amplifier. Note that the use of two inductors requires a large amount of space within the integrated circuit.
FIG. 4 shows an enhancement to the design shown in FIG. 2. The wireless device 200 comprises a wireless transceiver circuit 230 having a LNA 231 and a power amplifier 232. As described above, a pad 235 is used to connect the wireless transceiver circuit 230 to the external antenna 220. A control circuit 270 may be used to manipulate C2 and C3.
In this figure, a single inductor L5 having the total inductance of the two inductors, L3 and L4, is used. A first shunt capacitor, C3 is connected to one of the coils in L5, as shown in FIG. 5. C3 may be referred to as a center tap capacitor. By utilizing a single inductor, L5, the space required for the impedance matching network may be reduced. As shown in FIG. 5, the inductor L5 may be a plurality of octagonal coils disposed on an upper metal layer of the integrated circuit. In this embodiment, L5 has an inductance of 7.3 nH and 7.5 turns. L5 may have an inner diameter of at least 80 μm and an outer diameter of 155 μm. C3 may be connected to L5 using a via 190 located on a lower metal layer. C2 may be disposed near the LNA and power amplifier. A metal trace 195, disposed on the lower metal layer may be used to connect L5 to C2, the LNA and the power amplifier. Note that the use of a single inductor requires about 50% less space than the configuration shown in FIGS. 2-3 due to wasted area in the space between the two inductors.
However, the quality factor of this design is reduced as compared to the configuration shown in FIGS. 2-3. Specifically, FIG. 6A shows the configuration of the single inductor L5 and center tap capacitor C3. FIG. 6B shows an equivalent representation of this circuit, where the inductor L5 is divided into two portions L5a and L5b L5a is defined as that part of the inductor L5 between the pad and the node that connects to C3. L5b is defined as that part of the indictor L5 between the node that connects to C3 and the node that connects to C2. Note that there is mutual inductance between L5a and L5b due to the proximity of L5a to L5b. This mutual inductance (M) can be modeled as an additional inductance on L5a and L5b. This mutual inductance also appears as a negative inductance (−M) on the shunt path.
It can be seen that the shunt path in FIG. 6C that includes −M and C3 is equivalent to the shunt path in FIG. 2 that includes C1. Thus,
          1         s     ⋆           C      1               =                  -      M          ⋆     s        +         1           s      ⋆             C       3                      ,         or                                       C     3          =            C     1             1     -                  ω       0       2                         C       1                  M
At very small values of C1, the denominator of the above equation is approximately 1, so C3 very nearly equals C1. However, at larger values of C1, this is not true. Assume a coupling coefficient between L5a and L5b of 0.56. This results in a mutual inductance of M=1.22 nH. For a value of C1 of 0.634 pF, C3 would be 0.776 pF, an increase of 22% in the required range of C3 as compared to C1. This translates to a decrease in quality factor of C3 of 22% to achieve the same minimum capacitance as C1 in the topology of FIG. 2.
Thus, it would be advantageous if there were an impedance matching network that did not require the space consumed by the configuration shown in FIG. 3, but had a quality factor that was higher than the configuration shown in FIG. 5. Further, it would be beneficial if this new impedance matching network could be readily incorporated into an integrated circuit design.

Low loss impedance matching circuit network having an inductor with a low coupling coefficient


An image forming apparatus includes a device main body, a detachable unit that is detachable and attachable to the device main body, a sheet guide that guides a pathway of sheet, and a guide position part that regulates a position of the sheet guide. The guide position part is disposed in the device main body, the sheet guide is disposed movably with respect to the detachable unit, and when the detachable unit is mounted on the device main body, a position of the sheet guide is regulated by abutting the guide position part.

Conventionally, there are image forming apparatuses having a detachable unit (or detach-attach able unit) able to be able to attach and detach with respect to a device main body (for example, refer to JP2011-59578 and JP2007-101728).
However, in conventional image forming apparatuses, the sheet guide to guide the sheet to the detachable unit is disposed in the device main body. Therefore, in the conventional devices, the detachable unit and the sheet guide are respectively independently positioned. As a result, the conventional devices have a problem that the position accuracy sometimes decreases and it disturbs the sheet carrying.
The present invention is to solve the problem described above. The main purpose for this invention is to provide an image forming apparatus, wherein the detachable unit is installed in the device main body so that a sheet guide is positioned at the predetermined position at the same time.


A computer implemented process compares signals communicated between a known position and a plurality of base stations in a cellular telephone system to determine the level of interference with a signal on a channel expected to serve the known position, and determines a value indicating a probability of interference with a signal on a channel expected to serve the known position.

1. Field of the Invention
This invention relates to cellular telephone systems and, more particularly, to processes for designing and improving the performance of cellular telephone systems.
2. History of the Prior Art
Presently available commercial mobile communication systems typically include a plurality of fixed base stations (cells) each of which transmits signals to and receives signals from mobile units within its communication area. Each base station is assigned a plurality of channels over which it can communicate with mobile units. A mobile unit within range of the base station communicates with the external world through the base station using these channels. Typically, the channels used by a base station are separated from one another sufficiently that signals on any channel do not interfere with signals on another channel used by that base station. To accomplish this, an operator typically allots to a base station a group of channels which are each widely separated from the next. So long as a mobile unit is within the area in which the signal from a base station is strong enough and is communicating with only that base station, there is no interference with the communication.
In order to allow mobile units to transmit and receive telephone communications as the units travel over a wide geographic area, each cell is normally physically positioned so that its area of coverage is adjacent to and overlaps the areas of coverage of a number of other cells. When a mobile unit moves from an area covered by one base station to that covered by another, communication with the mobile unit is transferred (handed off) from one base station to another in an area where the coverage from different cells overlaps. Because of this overlapping coverage, the channels allotted to the cells are carefully selected so that adjoining cells do not transmit or receive on the same channels. The channels used by adjoining base stations are also theoretically separated from the channels of each adjoining base station sufficiently that signals from any base station do not interfere with signals from another adjoining base station. This separation is typically accomplished by assigning a group of widely separated non-interfering channels to some central cell and then assigning other groups of widely separated non-interfering channels to the cells surrounding that central cell using a pattern which does not reuse the same channels for the cells surrounding the central cell. The pattern of channel assignments continues similarly in the other cells adjoining the first group of cells. The pattern is often called a channel reuse pattern.
So long as a mobile unit is within the area in which the signal from a base station is strong enough and is communicating with only that base station, there is no interference with the communications. However, when a mobile unit moves from an area covered by one base station to that covered by another base station, the communication must be transferred from one base station to the other in an area. This requires cell coverage to overlap. Because of this overlapping coverage, the channels allotted to the cells are carefully selected so that adjoining cells do not transmit or receive on the same channels.
There are a number of different types of mobile communications systems. Channels are defined in different manners in each of the different systems. In the most prevalent American Mobile Phone System (AMPS) system, channels are defined by frequency. A frequency band of 25 MHz providing approximately four hundred different adjoining FM frequency channels is allotted by the federal government to each cellular operator. In a typical AMPS system, each channel uses a fixed FM frequency band width of 30 KHz. for downlink transmission from a base station to a mobile unit and another feed FM frequency band width of 30 KHz. for uplink transmission from a mobile unit to a cell. Typically, the frequencies assigned to the downlink transmissions for an entire cellular system immediately adjoin one another and are widely separated from the frequencies assigned to the uplink transmissions which also immediately adjoin one another. In this specification, even though widely separated, the pair of frequencies used for both downlink and uplink transmission are generally intended when reference is made to an AMPS channel unless the context indicates otherwise.
Since channels are defined by frequency in an AMPS system, the channels used by any single base station are separated from one another in frequency sufficiently to eliminate interference between those channels. An operator typically allots a base station a set of channels with frequencies which are each separated from the next by some large number (e.g., twenty-one) channels carrying intermediate frequencies. Thus, in a system with twenty-one channel separation, one base station might use channels 1, 22, 43, 64, 85, and so on up to a total of between five and one hundred individual channels.
When a mobile unit moves from an area covered by one base station to that covered by another base station in an AMPS system, the communication must be transferred from one base station to the other in an area in which cell coverage overlaps. Because of this overlapping coverage, the channels allotted to the cells are carefully selected so that adjoining cells do not transmit or receive on the same frequencies. This is typically accomplished by assigning channels to a central cell which are widely separated in frequency in the manner described above, and then assigning channels to the cells surrounding that central cell using a pattern which increases each channel number by one for each sequential cell surrounding the central cell. Thus, if cells are arranged in a honeycomb pattern in which six cells surround a central cell using the above-described channels, a first cell adjacent to the central cell may have channels 2, 23, 44, 65, 86, and so on while a second cell adjoining the central cell may have channels 3, 24, 45, 66, 87, and so on. The pattern of channel assignments continues similarly in the other cells adjoining the central cell.
In some AMPS systems, especially those with cells in urban areas carrying heavy traffic, each cell may be further divided into two or three sectors each of which may include channels having the above-described frequency allotment of channels. The antennas of each sector are typically arranged to provide 180 or 120 degree coverage. When cells are discussed herein, sectors are normally meant as well unless the context indicates otherwise.
Another type of mobile system called Code Division Multiple Access (CDMA) uses digital signals to transmit data. All of the base stations of a CDMA system use the same xe2x80x9cspread spectrumxe2x80x9d frequency band of 1.25 megacycles to transmit the digital signals. The transmissions are combined with redundant channel coding information to allow error correction. The encoded signals are then multiplied by one of sixty-four Walsh codes which establish individual channels and increase the bandwidth to 1.25 megacycles. Because of the redundancy of the encoded signals, a receiver may decode a signal from the plethora of coded channels carrying data on the broad frequency band. Since the Walsh codes establish a number of individual channels and the pseudonoise code assigned to each base station differs from those of other surrounding base stations, adjacent and remote cells may reuse the same frequency bands.
In another common type of mobile system called Time Division Multiple Access (TDMA), frequencies are assigned to the entire system in groups much like they are assigned in an AMPS system. However, within any frequency, each base station sends and receives in bursts during some number of different intervals or time slots. These time intervals within frequency bands then effectively constitute the individual channels. By assuring that the group of frequencies assigned to any individual base station differ from one another and from the frequencies assigned to base stations surrounding each individual base station, a channel reuse pattern is established which allows substantially greater use of the frequency spectrum because of the time division process.
In theory, these forms of cell arrangement and channel assignments allows channel reuse patterns to be repeated at distances separated sufficiently to negate interference between mobile units on the same and adjacent channels.
Unfortunately, interference does occur for a number reasons. Antenna patterns, power levels, scattering, and wave diffraction differ from cell to cell. Buildings, various other structures, hills, mountains, foliage, and other physical objects cause signal strength to vary over the region covered by a cell. Consequently, the boundaries at which the signal strength of a channel falls below a level sufficient to support communications with a mobile unit vary widely within a cell and from cell to cell. For this reason, cells adjacent one another do not, in fact, typically form the precise geometric boundaries suggested above. Since cell boundaries must overlap to provide complete coverage of an area and allow handoff and because the boundaries of cells are imprecisely defined, signals will often interfere with one another even though they are generated by cells which are at distances theoretically sufficient to eliminate interference. This is especially true when a sectored cell pattern is used because the cells are much closer to one another than in a simple cell pattern.
A first signal on a channel from a remote cell interferes with a second (usually) stronger signal carrying a mobile transmission on the same channel within the coverage area of a cell when the drop in strength of the first signal from the second signal is less than some threshold level (typically measured in decibels). A signal from another cell on a channel at a frequency adjacent the frequency of a channel carrying a mobile transmission interferes when the drop in strength of the interfering signal from the serving signal is less than some second threshold level. The values are determined by the particular type of mobile system involved. For example, in an AMPS system, a signal on the same channel (co-channel) from a remote base station interferes with a desired carrier signal if the interference level is not 18 dB lower than the desired carrier; and a signal on an adjacent channel from another base station interferes with a desired carrier signal if the interference level is not 6 dB lower than the desired carrier. For a CDMA system, an interfering signal must be more than 14 dB stronger than the carrier to obscure a carrier signal because the codes establishing the channels establish heavily redundant signals from which patterns may be extracted even though the interfering signal is stronger.
In order to determine whether interference exists, a mobile system operator typically relies on customer complaints. When customers register a sufficient number of complaints regarding communication at particular points in a system, an operator will usually conduct a relatively expensive field test of the suspected portion of the system to measure carrier signals and interference received. During the test, the portion of the system in which the tests are conducted is essentially disabled. Because of the expense and inconvenience, the tests are typically limited only to the suspected area. Because such tests are limited to determining the interference at those points at which a system operator expects to find interference, the efficacy of these tests is very suspect.
The tests provide data from which the points at which channels from different cells actually interfere with one another may be determined. If the level of interference is sufficiently large, the operator may change the channel group assigned to the particular area. That is, the frequency group assigned to a cell (or cells) may be changed in its entirety to another frequency group in which channels which would interfere with channels carried by other cells do not exist. It is also possible to eliminate some interference by changing cell characteristics (such as antenna tilt or power used in particular cells) without changing the channels used. Once channels have been assigned to cells which provide acceptable coverage and detected interference has been eliminated, the system is fixed and operated until other complaints arise.
A major problem with the process is that it does not provide a complete understanding of interference which actually exists in a system since typically only those positions at which extensive interference has been reported are tested for actual interference. The process does not take into consideration all of the possible signals which might be propagating into the affected area to interfere with the carrier nor does it take into consideration the effects which a change in channel assignments may have in other areas of the system. Often (and possibly usually) this method of curing interference merely exports the interference to another portion of the system where it is only discovered when a sufficient number of complaints arise to warrant a field test of the newly isolated area of interference.
Moreover, this method of placing cells, assigning frequencics, and eliminating interference is quite slow and labor intensive. Testing a medium sized system may require as much as 400 man hours. The process greatly increases the costs of creating and maintaining mobile systems without guaranteeing that interference will be eliminated. Because of the emerging nature of the market for cellular telephones, system changes which cause interference such as traffic growth are taking place constantly and at an accelerating rate. Complicating the general problem of interference in an existing system is the fact that cellular system operators are presently installing new CDMA and TDMA systems because they allow a greater number of mobile units to utilize a system and because these digital system provides a better quality of service when they are functioning properly. Often the installation of these new systems is taking place where AMPS cellular systems already exist and will continue to exist. In general, with these systems, some of the frequencies used in the AMPS systems are removed; and a CDMA base station is positioned in place of a sector at a base station.
It is desirable to provide a process by which the quality of service provided by a cellular system (and portions thereof) may be determined in terms of fixed verifiable quantities so that changes may be made to enhance the quality of service with an expectation that the changes will have the desired result in actually improving the quality of service provided by the system.
The present invention is realized by a computer implemented process which compares signals communicated between a known position and a plurality of base stations in a cellular telephone system to determine the level of interference with a signal on a channel expected to serve the known position, and determines a value indicating a probability of interference with a signal on a channel expected to serve the known position.
In one embodiment, changes in the system to improve the interference value are implemented only if the interference value is above a certain level.
These and other features of the invention will be better understood by reference to the detailed description which follows taken together with the drawings in which like elements are referred to by like designations throughout the several views.

Method of evaluation of the effect of channel reassignment and/or parameter changes on interference throughout a cellular system


A D flip-flop with a reduced power product or reduced clock line capacitance is disclosed. The flip-flop includes a half-static slave stage or a master stage with clock gating by the input and output. The half-static slave stage an output inverter and a feedback element consisting of a single switching transistor having a gate connected to the output of the flip-flop and the input of the inverter as its load. The clock gating circuit, which may comprise an XNOR gate, reduces the frequency of switching events by permitting clock pulses to pass into the master or slave stage only when the input and output of the flip-flop are at the same logical state.

Flip-flops are indispensable in digital logic design. The flip-flop itself can also be regarded as a one-bit memory circuit. There are several kinds of flip-flops. In particular, a D flip-flop accepts an input and generates an output with the same value of the accepted input when it is triggered by a clock signal. Power consumption has been one of the greatest concerns for all designers when designing a flip-flop, since it is widely in use and contributes a significant portion of the total power consumption in digital circuits. In practice, the performance of a D flip-flop is commonly measured in terms of power delay product, which is the product of the average power consumption and the propagation delay measured from the triggering point of the clock signal to the occurrence of the output signal corresponding to the input signal right before the triggering edge of the clock.
FIG. 1 shows a conventional master-slave D flip-flop 100. Each of the master stage 110 and slave stage 120 has a pass gate and a memory element. The pass gate is a transmission gate driven by a clock signal. In a conventional D flip-flop, the external clock signal typically does not drive the transmission gate directly, because that will increase the capacitance of the external clock line, which is undesirable in large circuits, as large clock line capacitance will cause clock skew problem. Instead, the external clock CLK is buffered by inverting the external clock signal CLK twice with inverters Inv1.1 and Inv1.2. The memory element in each stage is formed by a feedback loop of two inverters (Inv 1.3 and Inv1.4 in the master stage, and Inv1.5 and Inv1.6 in the slave stage) and is controlled by another pass gate (pass gate 1.2 in the master stage, and pass gate 1.4 in the slave stage). When the pass gate is turned on, the feedback path is completed and the two inverters form a latch, which can serve as memory. When the clock signal CLK is low, the pass gate 1.2 will break the loop of the master memory, while the input signal D will pass through pass gate 1.1 and complete the memory write action onto the master memory at the same time. The signal written into the master memory equals to the signal D right at the moment of the rising edge of the CLK signal. When the CLK signal is high, the two stages are connected together by the pass gate 1.3. At the same time, the pass gate 1.4 will break the loop of the slave memory. As a result, the signal that has been written into the master memory will pass through the pass gate 1.3 and complete the memory-write action onto the slave memory. When the CLK signal is low again, the slave stage is isolated from the master stage and the signal is passed to the slave stage and is stored in its latch formed by Inv1.5 and Inv1.6. Such D flip-flop is known as rising edge triggered master slave D flip-flop. D flip-flop with other triggering type can be constructed similarly in the hands of the skilled engineers.
The reduction of the power consumption of the conventional master slave D flip-flop has been extensively investigated in the literature. An effective way to reduce the power consumption is to use dynamic circuit to construct the master flip-flop and simplify the static circuit of the slave flip-flop 200 as shown in FIG. 2. The master stage 210 in FIG. 2 replaces the pass gate 1.1 in FIG. 1 by a switching transistor M2.1, which is controlled by a complemented CLK signal. The feedback inverter Inv1.4 of the memory element is eliminated. In this case, the storage function is performed by the dynamic memory element constructed by the parasitic capacitor of the output of Inv2.3. The pass gate 1.2 is replaced by transistor M2.2, which is used to turn on and off the inverter Inv2.3 to complete the memory write action. Comparing to the conventional master stage as shown in FIG. 1, the one in FIG. 2 has fewer device count and smaller clock load, thus consumes less power. The slave stage 250 is similar to the conventional one, but the two transmission gates pass gate 1.3 and pass gate 1.4 in FIG. 1 are reduced from two transistors to one with switching transistor M2.3 so that the device count is further reduced and the two phase clock is not required as contrast to that in FIG. 1. However, using switching transistor may reduce output voltage across the transistor. In the other words, it would require additional power to pull the output voltage back to VDD, where VDD is the supply voltage of the D flip-flop, which is the logic 1 voltage representation in digital logic. Otherwise the circuit will be operated with reduced noise margin. To remedy the problem, inverter Inv2.3 is added to the master stage. When D is at logic 1, node x1 has a voltage of VDD-VT, where VT is the threshold voltage of the transistor M2.1. To compensate for the reduced voltage at node x1, the transistor sizes of inverter Inv2.3 is adjusted such that its noise margin is wide enough to accommodate the voltage drop at node x1. In this case, the switching transistor M2.3 of the slave stage does not suffer from the voltage drop problem and can maintain a strong driving capability to push a large output latch. At the latch of the slave stage, a weak feedback inverter Inv2.5 is used so that switching transistor M2.3 can write a different signal into the latch by using a small power.


A method for low power clock tree synthesis using buffer insertion, removal and resizing for high-speed VLSI design is proposed. A developed tool can be embedded in the existing clock tree synthesis design flow to ensure satisfying both specifying database constrains and clock skew constrains. For a given clock tree netlist, location information of buffers, parameters of wires and buffers' timing and power library are all included. Buffer delay and wire delay of the given clock tree netlist are calculated first. Then, a feasible solution is solved if an input netlist is not feasible for given constrains. Finally, a modified low power clock tree netlist, which satisfies timing specifications, is obtained using the proposed method.

1. Field of the Invention
The present invention relates to a clock tree synthesis and, more particularly, to a clock tree synthesis for low power consumption and low clock skew.
2. Description of Related Art
In the modem high speed VLSI design era, clock design plays a crucial role in determining chip performance and facilitating timing and design convergence. Clock routing is important in the layout design of a synchronous digital system as it influences correctness, area, speed and power dissipation of the synthesized system [reference 1 and 2]. Drastically increased requirements for high performance and high speed VLSI circuits have posed challenges to the design of high speed clock networks, where minimization of clock delay and clock skew has been a critical problem. So some circuit designers' inclination is toward developing techniques to minimize the power dissipation, the clock delay (latency) and the clock skew as well as developed, understood design and verification flows.
Buffer operations are widely used in designing clock distributed networks [reference 3]. Buffers can decouple capacitance to reduce equivalent loading of each wire, so rise time and wire delay could be reduced. Also, when the signal's transfer time is faster, it can reduce power consumption. Several methodologies are adopted in the power consumption and the clock skew minimization. The previous research inserts the buffers and constructs a H-tree to reach the optimization solution in both circuit area and the power consumption aspects [reference 4]. The balanced buffer insertion scheme attempts to partition the clock tree into several subtrees such that every subtree has equal path length and all source-to-sink paths have an equal number of levels. Clock gating is another well-known technique in reducing the dynamic power dissipation of a digital circuit [reference 5 and 6]. It saves power by shutting off the sequential elements and part of the clock network during an idle state.
The design of the clock distribution network also determines the clock skew. The clock skew directly affects chip performance in a close to one-to-one ratio, since it has to be counted as a cycletime penalty. The clock trees need to be incrementally adjusted accordingly with minimum changes to ensure an acceptable clock skew. The buffer insertion usually deals with the clock skew minimization problem [reference 7]. Other research using the buffer insertion method minimizes both the power consumption and the clock skew criterion [reference 4].

Clock tree synthesis for low power consumption and low clock skew


An endplay adjustment system and method is shown having a slider body that has a thrust surface that lies in a plane that is generally perpendicular to an axis of an armature and that can be driven toward the armature by a plunger body. After the plunger body is driven into a plunger-receiving area of the housing, an angled surface of the plunger engages a mating surface of a slider body which forces the thrust surface into an end of an armature of an electric motor. The plunger body may then be secured, adhered to or welded to the housing and/or the slider body to lock the slider body and plunger into place, thereby reducing or eliminating endplay associated with the armature shaft.

1. Field of the Invention
This invention concerns an endplay adjustment system and method for reducing or eliminating endplay associated with an armature of electric motor.
2. Description of the Related Art
FIG. 11 illustrates a prior art endplay adjustment system 100 used in an electric motor (not shown) having an armature (not shown) that drives a driven gear. The system 100 has a plunger 102 that is attached to a slider body 104 having an angled face 105 with attachment fingers 106. The plunger 102 comprises a plurality of interlocking ribs 108 that cooperate and lock against ribs 110 that are situated on the slider body walls 104a and 104b in order to lock the plunger 102 to the slider body 104.
The angled face 105 engages an end of the armature (not shown) when the system 100 is inserted in the motor. Due to angled face 105 of the slider body 104, there are large variations of stall torque between thrusting between the armature and the motor case side. This is caused by the angled face 105 side loading the armature shaft. This also increases friction in one thrust direction and a change in the worm angle in relation to a gear due to the flexure of the armature shaft. The stall torque variation is an undesirable trait for a bi-directional motor.
The angled face 105 also creates a high bending stress on the armature shaft of the electric motor when the motor stalls and the shaft thrusts against the angled face 105. This high stress requires that higher strength be used and stress-reducing features be added to the shaft geometry which impacts the cost of the armature shaft.
Moreover, the interlocking ribs 108 and 110 allow for an adjustment precision of approximately 0.15 mm and this is difficult to improve because it would require making the interlocking ribs 108 and 110 smaller. The interlocking ribs 108 and 110 must be made of a "soft" or flexible polymer to permit the interlocking ribs 108 and 110 to flex.
It has been found that the level of motor noise "growl" has been shown to correlate to an amount of axial force that is applied to the armature shaft as a result of the endplay adjustment process. The level of motor "clunk" noise correlates to the amount of gap that is allowed between the armature shaft and the endplay device. Due to the variation in friction between the plunger, slider body and gear housing walls, controlling the resulting axial force, while ensuring that there is no gap between the shaft and endplay device, is has been difficult. To ensure a maximum endplay gap is taken up, high forces are required to exert on the plunger top 112 downward (as viewed in FIG. 11) in order to engage the locking ribs 108 and 110.
One prior art design utilized a plunger 102 that was attached to the slider body 104 by the two attachment fingers (one of which is shown and labeled as 106 in FIG. 11). At times, the plunger 102 became tilted, relative to the slider body 104, the plunger will not engage the slider body 104 properly, thereby delaying or preventing the installation of the endplay adjustment system into the motor housing.
What is needed therefore is an endplay adjustment system and method which overcomes one or more of the problems associated with the prior art.


A convenient method of obtaining useful highly esterified alkoxylated polyol fat substitutes from readily available triglycerides such as fats and oils is provided.

A wide variety of substances have been proposed for use as fat substitutes in food compositions. The chemical structures of such substances are selected such that they are more resistant to breakdown by the metabolic processes of the human digestive system which normally occur upon ingestion of conventional triglyceride lipids. Because of their increased resistance to digestion and absorption, the number of calories per gram available from the fat substitutes is considerably reduced as compared to common vegetable oils, animal fats, and other lipids. The use of such substances thus enables the preparation of reduced calorie food compositions useful in the control of body weight.
U.S. Pat. No. 4,861,613 describes one class of particularly useful fat substitutes wherein-a polyol such as glycerin is alkoxylated with an epoxide such as propylene oxide and then esterified with any of a number of fatty acids or fatty acid equivalents to form an esterified alkoxylated polyol. Generally speaking, it is desirable to accomplish nearly complete esterification (i.e., to react at least 90% of the hydroxyl groups of the alkoxylated polyol intermediate with fatty acid). These substances have the physical and organoleptic properties of conventional triglyceride lipids, yet are significantly lower in available (absorbed) calories than edible oils owing to their pronounced resistance towards pancreatic lipase enzymatic hydrolysis. The thermal and oxidative stability of the esterified alkoxylated polyols renders them especially suitable for use in the preparation of reduced calorie food compositions requiring exposure to high temperatures.
The methods developed to date for the preparation of esterified alkoxylated polyol fat substitutes of this type have largely required multi-step procedures when a naturally occurring triglyceride is to be utilized as the source of the long chain acyl groups incorporated into the esterified alkoxylated polyol. The triglyceride is first hydrolytically split into glycerin (which may be employed as the polyol component) and a mixture of fatty acids. The fatty acids (after separation from the glycerin) may be used directly without further modification as described in U.S. Pat. No. 4,983,329. Alternatively, the fatty acids prior to use in an esterification reaction with an alkoxylated polyol may be converted into C.sub.1 -C.sub.4 alkyl esters (as described in U.S. Pat. Ser. No. 5,175,232) or fatty acid halides (as described in U.S. Pat. No. 4,861,613). The alkoxylated polyol must first be prepared by reacting an epoxide with a polyol such as glycerin, sugar alcohol, glycoside, monosaccharide, disaccharide or other organic compound having two or more hydroxy groups. While such multi-step procedures work well and afford esterified alkoxylated polyols suitable for use as fat substitutes, the number of steps involved, including both synthetic and purification steps, renders these substances considerably more costly than the triglycerides on which they are based. Since the esterified alkoxylated polyol is intended to entirely or substantially replace conventional high caloric triglycerides in food compositions and since certain types of food compositions will normally contain high levels of fat or oil, it is apparent there exists a great need for improved processes whereby the manufacturing cost of esterified alkoxylated polyols may be substantially reduced.
Although the direct esterification method as described hereinabove and in U.S. Pat. No. 4,983,329 has the advantage of utilizing free fatty acids, thus avoiding the necessity of first preparing alkyl ester or halide derivatives prior to the alkoxylated polyol esterification step, it is not an ideal method. In particular, direct esterification normally is optimally carried out under conditions such that the water generated by the reaction of fatty acid and alkoxylated polyol is continuously removed from the reaction mixture by means such as distillation (which may be under vacuum) or sparging with an inert gas such as nitrogen. Substantially complete esterification is difficult to achieve unless the water is so removed since esterification is an equilibrium reaction. Under typical reaction conditions, the free fatty acids which are present will have a tendency to steam distill together with the water and consequently be removed from the reaction zone. This adversely affects the rate of the desired esterification reaction, not only because the fatty acid is a required reactant but also because such esterifications are preferably conducted in the absence of any metallic catalysts (due to difficulties in removing such catalysts, many of which are highly toxic, after completion of esterification) using an excess of fatty acid to self-catalyze the esterification. If fatty acid is being continually lost from the reaction zone due to overhead losses, fresh fatty acid must be added to maintain the desired rate of reaction. The need to use make-up quantities of fatty acid and to recycle, recover, or otherwise dispose of the fatty acid lost overhead increases the overall cost of such a process. Another problem is that the presence of large quantities of free fatty acid during the entire time necessary to convert an alkoxylated polyol containing no acyl groups initially to a completely esterified product provides an opportunity for the fatty acids to dimerize, polymerize, oxidize, or otherwise degrade. These undesired side-reactions of the fatty acid may result in the formation of acidic or unpleasant-tasting or smelling impurities which are difficult to remove by standard edible oil refining techniques such as deodorization, hydrogenation, or bleaching. The development of synthetic procedures which would alleviate the aforesaid difficulties would therefore be a highly desirable improvement in the fat substitute art.

Process for the preparation of highly esterified alkoxylated polyol compositions


The invention concerns a device in an piston cylinder aggregate including a valve element (8) which comprises a valve body (9) for choking the flow in a fluid channel (6) in co-operation with a valve opening (7), wherein the device is arranged in a bore (11) in an end wall (1) of the piston cylinder aggregate and wherein the valve element (8) is provided with a setting means (10) to allow adjustment from the outside of the end wall. The invention is distinguished by. that the valve body (8) is provided with a screw thread along its axial extension, PA1 that the valve opening (7) is debauching in a portion (12) of said bore which at least partly is provided with a screw thread corresponding to the one on the valve body, PA1 that the setting means (10) is extending outside the end wall surface, and PA1 that a ring shaped sealing means (14) is arranged in said hole (11) in direct proximity to the outside of the end wall (1) and having its outside surface substantially in level with the surrounding surface of the end wall, said sealing ring exerting a sealing cooperation with the setting means (10).

This invention concerns a device in a piston cylinder aggregate including a valve element which comprises a valve body for choking the flow in a fluid channel in cooperation with a valve opening. It also concerns a piston cylinder aggregate including at least one such device.
Such devices are previously known, for example from U.S. Pat. No. 2,719,510, wherein the valve element includes a setting means with a conical valve and a co-operating seat. The setting means is disposed radially in the cylinder end wall and because of its substantial axial extension it demands great constructional height and thus large dimensions of the end wall. In many applications the described setting means further leads to an essential problem related to accumulation of dirt in the irregular surfaces.
In another previously known solution the setting means, in general according to U.S. Pat. No. 2,719,510, is applied at an angle with respect to the outside surface of the cylinder end wall so as to be disposed non-radially in the cylinder end wall. Also this solution, however, result in non desired dirt collecting irregularities because a deep pocket is formed at the outer end of the setting means.
Irregularities and pockets of this kind are considered to be problematic in applications where there are rigorous demands for cleanliness, e.g. in the food industry. In such applications dirt collecting irregularities lead to a serious hygienic problem.


Embodiments of the present application provide a method and apparatus for displaying objects. In the method, data segments of to-be-stored data are stored in storage objects. A storage object is a minimum unit for data storage. The difference between the number of data segments stored in a storage object and that of another storage object is no more than a first preset threshold. Data segments are equally stored, to the greatest extent, into storage objects. The case that data having segments lost due to failure of a storage object cannot be restored is avoided.

Redundant Arrays of Independent Disks (RAID) is a technology in which multiple disks are combined into a single disk of massive storage and data is divided to be stored in the disks.
Data in RAID is typically protected through erasure coding (EC). An erasure coding strategy may be represented by n=k+m, wherein, k is the number of original segments, m is the number of redundant segments, and n is a total number of data segments. Specifically, to-be-stored data can be divided into k original segments, and based on the original segments, redundant segments are obtained by expansion and encoding. The k original segments and m redundant segments are stored respectively in disks. As such, in an event of data loss due to the failure of some of the disks, lost data segments can be restored based on remaining original segments and redundant segments.
In the above solution, typically, data segments (original segments and redundant segments) are randomly stored in disks. A case may occur that a plurality of data segments stored in one disk are all lost upon a failure of the disk. Data is unable to be restored in this case.

Data storage, distribution, reconstruction and recovery methods and devices, and data processing system

HANGZHOU HIKVISION DIGITAL TECHNOLOGY CO., LTD.


A snap frame assembly for engagably supporting a one or double sided planar display panel, comprising an elongated extruded carrier frame having an elongated housing with a central opening therein, an elongated extruded front plate slidably mounted on an elongated rigid member extending from the housing, and an elongated pivotable member flexibly attached to the housing by an elongated commonly extruded hinge. The front plate has an upper channel member which rotatively pivots on an arm extending from the housing and has a lower channel member which pivots together with a curved housing plate which comprises a portion of the housing of the carrier frame.

1. Field of the Invention
This invention relates to extruded component assembly for biasably holding a panel display such as a poster gripping assembly against a wall or from an overhead suspension arrangement.
2. Prior Art
Poster gripping assemblies have been known in the field, for a number of years. One such instance is shown in U.S. Pat. No. 4,519,152 to Seely et. al. which shows a tamper proof poster display arrangement. This display arrangement has an outer cover portion with certain defined angles which make it difficult to open the cover from its base. An "opener tool" is required for that. The cover and the base portions are independently extruded and have a hinge relationship which requires a difficult "slide together" assembly. U.S. Pat. No. 4,937,959 to Palmer et. al. discloses a gripper extrusion arrangement wherein a front cover portion and a rear panel portion are separately extruded and mated together in another complicated hinge assembly. Inadvertent sliding between the front cover portion and the rear panel portion is prevented by a rather complicated discontinuity formed in the front panel which mates with a slot or the like in the rear panel. This requires further operations and unnecessary manufacturing costs. U.S. Pat. No. 5,307,575 to Ivansson et. al. shows a frame corner assembly wherein adjacent sides of a frame are held together with a rather complicated bracket arrangement. The cover portions and rear panel portions are individually extruded and are snapped together. Alignment of the ends of these multiple component arrangements lead to inaccurate end mis-aligned corner sections. U.S. Pat. No. 5,732,496 to Tanaka shows a sign frame with corner arrangements for attaching sides of that frame together. Mitered alignment of the corners is avoided by a corner insert which is somewhat more expensive to manufacture and adds a further step in that procedure.
It is an object of the present invention, to provide a frame display poster gripping assembly which overcomes the disadvantages of the prior art.
It is a further object of the present invention to provide a poster gripping assembly which may be utilized in a poster-holding configuration by itself or in a frame construction of rectilinear configuration for one or two sided displays.
It is a further object of the present invention to provide a poster gripping assembly which simplifies the manufacturing operation over the prior art.
It is another object of the present invention to provide a poster gripping apparatus with a unique multi-curved biasing arrangement which may be readily assembled and/or re-configured with a front plate to permit adjustment of its bias.
It is yet still a further object of the present invention to provide a poster gripping assembly which may be assembled into a rectilinear frame construction with accuracy and simplicity while minimizing the likelihood of defects as may be associated with the prior art.

This patent is subject to a terminal disclaimer.


The invention provides a process for operating a system for water vapor reforming of methanol in which, in a mixture preparation step, a water vapor/methanol mixture is prepared from water and methanol and is introduced into a reforming reactor. According to the invention, the mixing ratio of the water vapor/methanol mixture is adjusted as a function of the load condition and/or load changes of the system so that a CO-concentration is obtained in the reformate which remains constant over the whole load range.

The invention relates to a process and apparatus for operating a system for water vapor reforming of methanol.
For operating such systems, it is known to vary the amount of the processed water vapor/methanol mixture which is introduced into the reforming reactor as a function of the load condition and the load change of the system. In German Patent Documents DE 1 949 184 and DE 21 57 722 C2 (in which methane is used instead of methanol), for example, a jet pump is provided for this purpose, and the vapor flow is adjusted as a function of the loading condition of the system. Thus, during a load change, the methane inflow also changes corresponding to the jet pump characteristics.
U.S. Pat. No. 5,401,589 discloses a process for operating a fuel cell system in a motor vehicle by means of a reformer system which is connected in front of the fuel cells and uses water vapor reforming of methanol for the purpose of obtaining the hydrogen required for the fuel cells. In order to be able to react to load changes faster than by merely changing the amount of the water vapor/methanol mixture introduced into the reforming reactor, a buffer battery and an oxygen reservoir are provided. In the case of an increased load requirement, additional oxygen is taken from the oxygen reservoir for introduction into the fuel cell system. It is also known from this as well as other documents that, when the water vapor concentration in the water vapor/methanol gas mixture is too low, during its reforming an increased CO-concentration occurs in the reformate. This is undesirable, particularly when the reformate is used as a fuel in so-called PEM fuel cells because these are poisoned by carbon monoxide. Normally, the water vapor/methanol mixing ratio is therefore maintained within a range of between one and ten.
During the operation of systems for the water vapor reforming of methanol, it is observed that in the case of a load change (that is, a change of the quantity of water vapor/methanol mixture introduced into the reforming reactor), a change of the water vapor/methanol mixture ratio occurs, due to a momentary change of the evaporation conditions in the system. This, in turn, leads to fluctuations in the CO-concentration of the reformate, which can cause undesirably high CO-concentrations at times, which must be removed in a purification process which follows.
The object of the invention is to provide a process of the initially mentioned type which avoids an occurrence of undesirable CO-concentrations in the reformate, during dynamic load changes as well as in static operation.
This and other objects and advantages are achieved by the process according to the invention, in which the water vapor/methanol mixing ratio of the water vapor/methanol mixture prepared in the mixture preparation step and introduced into the reforming reactor, is adjusted as a function of the time variation of the load condition, so that a CO-concentration is obtained in the reformate which is constant over the whole load range. As required, such adjustment of the water vapor/methanol mixing ratio can take place by a pure control, without an absolute requirement of feedback regulation. Keeping the CO-concentration constant in the reformate prevents undesirable CO peak values and permits a simple design of a gas purification step optionally connected behind the reforming reactor, which removes undesirable carbon monoxide. The process therefore advantageously adapts the method of operation to the loading of the system, avoiding increased CO-concentrations in the reformate.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.

Process for operating a system for the water vapor reforming of methanol


An interbody fusion device for fusion of vertebrae, and methods thereof. The device includes a first piece made of titanium having upper and lower surfaces configured to engage the endplates of two opposing vertebrae. The upper and lower surfaces include a plurality of barbed teeth configured to engage an endplate. The first piece includes an inner void area configured to receive a second piece. The second piece is configured to engage the first piece to slide over inner surfaces of the first piece become seated and mated in the first piece. The first and second pieces mate to form an assembled interbody fusion device that fits between two vertebrae.

This disclosure relates to the field of spinal fusion. In particular, this disclosure is drawn to spinal fusion devices and associated methods.
The spine can be considered to be a series of movable segments made up of vertebrae and discs. Due to trauma, disease, and/or aging, the spine may be subject to degeneration. This degeneration may destabilize the spine and cause pain and/or nerve damage. Medical procedures are often required to either ease back pain, repair damage, or to prevent further damage.
One procedure that is often used to treat back pain or spinal damage is spinal fusion. Spinal fusion is a surgical technique used to fuse two or more adjacent vertebrae. Supplemental bone tissue is typically used in conjunction with the patient's natural osteoblastic processes in a spinal fusion procedure. Spinal fusion is used primarily to eliminate back pain caused by the motion of the damaged vertebrae by immobilizing adjacent vertebrae. Conditions for which spinal fusion might be done include degenerative disc disease, treatment of a spinal tumor, a vertebral fracture, scoliosis, degeneration of the disc, spondylolisthesis, or any other condition that causes instability of the spine.


The subject apparatus and method measures the Total Average Power Loss and isolates the different power loss components of Total Average Loss such as Ton Loss and Toff loss at switching devices such as, MOSFETs, BJTs and IGBTs that may be used in a switching power supply. It provides separation of the components of Total Average Loss as Turn Ton Loss, Turn Toff Loss and allows derivation of conduction loss. It also has the capability to measure Total Average Loss and Switching Loss, while amplitude, duty cycle and frequency of the switching signal is varying in a switching power supply.

Total average power loss is the significant component in the overall power loss of a switching power supply and is estimated at 35% to 40%. The Total average power loss has an adverse impact on the performance of the switching power supply, by reducing efficiency and reliability, and by causing an increase in the size of the needed heat sink.
In order to know the exact impact, it is important to measure and characterize the total average power loss, switching loss at the switching device. Unfortunately, there are no currently available test tools in market to measure total average power loss or to measure switching loss in time varying signals.
Total average and switching loss at a switching device is currently analyzed by two methods: Thermal, and Manual. The Thermal technique has following limitations and difficulties. The design engineer needs stimuli to excite the switching device with proper voltage and current. It is time consuming, prone to human error, and the design engineer cannot isolate power loss components such as Ton loss, Toff loss, and conduction loss.
The second method uses a Digital Storage Oscilloscope (DSO) and a Manual measurement technique. This measurement technique has following limitations and difficulties. It, too, is time consuming. It, too cannot separately measure Ton time loss or Toff time loss. Moreover, it is not possible to make measurements when the duty cycle and frequency of switching cycle are varying.
Because of this complexity in measurement, most of the time, designers over-design the Switch Mode Power Supply (SMPS) resulting in lower efficiency and higher cost.
What is needed is an automated method of measuring Total average power loss, and switching loss using a digital storage oscilloscope. This technique of measurement can be applied to switching power supplies that are used in the Computer, Communication, Automotive, and Electronic Ballast industries, thereby overcoming the above-described limitations of thermal and manual computation.

Identification of average total loss and switching loss in duty cycle and/or frequency variation signals acquired across a switching device using a DSO


A heat dissipation apparatus (10) includes a heat spreader (30), and first and second resilient plates (40, 50) provided at two opposite sides of the heat spreader. The first resilient plate includes a mounting arm (41) and two fixing arms (42) extending from two opposite ends of the mounting arm, respectively. The mounting arm defines a first mounting hole (43) therein, and each of the fixing arms defines a first fixing hole (44) therein. The second resilient plate defines a second mounting hole (53) and two second fixing holes (54) therein. The first resilient plate is fixed on the heat spreader via the first fixing holes. The second resilient plate is fixed on the heat spreader via the second fixing holes. The heat spreader is fixed on a circuit board via the first and the second mounting holes.

1. Technical Field
The present invention generally relates to heat dissipation apparatuses, and particularly to a heat dissipation apparatus for dissipating heat generated by electronic components.
2. Description of Related Art
It is well known that heat is generated by electronic components such as integrated circuit chips during operation thereof. If the heat is not efficiently removed, these electronic components may suffer damage. Thus, heat dissipation apparatuses are often used to cool the electronic components.
A typical heat dissipation apparatus includes a heat spreader, a heat sink and a heat pipe thermally connecting with the heat spreader and the heat sink. The heat spreader is in contact with an electronic component, such as CPU and so on, which is disposed on a circuit board. The heat spreader includes four sleeves respectively formed at four corners thereof. Each of the sleeves receives a screw therein. During assembly, the spreader is fixed on the circuit board via the four screws, for contacting intimately with the electronic component.
However, fixing the heat spreader on the circuit board with so many screws complicates an assembly process and increases a production cost of the heat dissipation apparatus. As well, four holes respectively aligning with the four screws are required to be defined in the circuit board, which causes an inconvenience for layout of circuitry on the circuit board. On the other hand, points of application of force on the heat spreader will be reduced if fewer screws are employed. Thus, the heat spreader can not contact intimately with the electronic component.
What is needed, therefore, is a heat dissipation apparatus which overcomes the described limitations.


A method of machining cylindrical gears with internal or external gearing on a machine with a tool wherein a gear is positioned on a machine, the gear having an axis of rotation (D). The gear is then evaluated to establish a gear guiding axis (F) and the position of the gear guiding axis (F) relative to the axis of rotation (D) is determined. The gear is machined by displacing the tool in the direction of the gear guiding axis (F).

An essential prerequisite for satisfactory running of a gear in a gearbox is that the gearing must be produced centrally with its guiding axis, the subsequent axis of rotation in the gearbox, so that the gearing axis and the guiding axis of the gear practically coincide. To do so, the work piece (i.e. gear) to be machined must be aligned on the machining equipment in such a way that the guiding axis of the gear and the axis of rotation of the machine coincide within a given tolerance, because according to the state of the art, the gearing is produced about the axis of rotation of the machine. Thus, as long as the toothed work piece is meshed on the machine, the gearing axis of the work piece and the axis of rotation of the machine coincide.
The alignment process is time consuming, especially with large heavy gears, which may weigh several tons. In an attempt to displace a heavy work piece in a certain direction on the machine, it often moves in another direction, e.g., because of unequal friction over the contact surface. Despite great attempts, there is still no satisfactory method of rapid and reliable alignment of heavy cylindrical gears on the gear cutting machine.
This situation has led to the object of providing a method that will make it possible to ensure with little effort that the gearing axis of a gear practically coincides with the guiding axis of the wheel.

Method of machining essentially cylindrical gear wheels with internal or external gearing


A structured query language (SQL) relational database management system (SQL RDBMS) may integrate a biometric subsystem to process and manage biometric data separately from the demographic data stored in normalized SQL tables of the SQL RDBMS. The SQL RDBMS may be operatively connected to the biometric subsystem by means of SQL extensions. The SQL RDBMS may execute queries with demographic and/or biometric constraints, wherein the demographic data is retrieved directly from normalized SQL tables on the RDBMS, while the biometric data is retrieved in the form of scores or probabilities from the biometric subsystem. The SQL RDBMS may return a query result set containing demographic data associated with corresponding biometric data, allowing the authentication of biometric clients.

1. Field of Invention
The present disclosure is related to biometric authentication, and more specifically, to a relational database management system that may perform biometric authentication.
2. Description of Related Art
The need to establish personal identity occurs, for most individuals, many times a day. For example, a person may have to establish identity in order to gain access to physical spaces, computers, bank accounts, personal records, restricted areas, reservations, and the like. Identity is typically established by something we have (e.g., a key, driver license, bank card, credit card, etc.), something we know (e.g., computer password, PIN number, etc.), or some unique and measurable biological feature (e.g., our face recognized by a bank teller or security guard, etc.). The most secure means of identity is a biological (or behavioral) feature that can be objectively and automatically measured and is resistant to impersonation, theft, or other fraud. The use of biometrics, which are measurements derived from human biological features, to identify individuals is a rapidly emerging science.
Biometrics is a generic term for characteristics that can be used to distinguish one individual from another, particularly through the use of digital equipment. An example of a biometric is a fingerprint. Trained analysts have long been able to match fingerprints in order to identify individuals. More recently, computer systems have been developed to match fingerprints automatically. Examples of biometrics used to identify or authenticate the identity of individuals include 2D face, 3D face, hand geometry, single fingerprint, ten finger live scan, iris, palm, full hand, signature, ear, finger vein, retina, DNA and voice. Other biometric may include characteristic gaits, lip movements and the like. New biometric are being developed or discovered continually.
It is common to employ a relational database management systems (RDBMS) to manage biometric data. Such relational database management systems are not designed specifically for the processing of biometric data and may often impose resource-intensive processes, thereby utilizing a high number of computing resources (e.g., power, processor storage, memory, and/or network capacity). The resource utilization may incur a significant delay in performing the biometric analysis and matching requests.
In justice and law enforcement, biometrics technology may be applicable for analyzing crime scenes and suspects. Biometric databases for law enforcement applications may contain thousands or millions of records and the identification of a criminal or suspect may need to be determined in a fast and accurate way before they may cause harm to someone. Thus, there exists the need for an effective database architecture model for managing biometric data in a RDBMS.
U.S. Pat. No. 7,689,005 issued to Wang et al. discloses a method and system for constructing a database management system for managing biometric data. The disclosed system in Wang receives data from another database or from and enrollment process, encodes the data with an encoding plug-in, and stores the encoded data in a biometric data storage. The data may be enhanced before being stored. Incoming target data likewise is encoded using an encoding plug-in and may be pre-processed, and is sent to a matching algorithm that is either built-in or a plug-in algorithm.
U.S. Pat. No. 7,949,156 issued to Willis et al. discloses a method for analyzing a dataset comprising biographic data and biometric data. In one step, a biographic record is read that is normally meant for unique description of an individual. A biometric associated with the biographic record is also read. The biometric is correlated with a plurality of biometrics associated with other biographic records. The uniqueness of the biometric is assessed with respect to the plurality of biometrics, for example, to find duplicate biographic records with biometric matching.
However, the prior art falls short because it does not convert biometric data into a biometric template that can be compared to a plurality of stored biometric templates to see if there is a match and does not process biometric data separately from demographic data allowing a faster and more accurate execution of queries including both demographic and biometric constraints.

Systems and methods for biometric data management using relational database management systems (RDBMS)