Compounds of formula (I), wherein R.sub.1 is (a), (b), (c) or (d); n is 0, 1 or 2; A, B, C and D are each independently nitrogen or carbon; R.sub.2, R.sub.3, R.sub.4 and R.sub.5 are each independently hydrogen, C.sub.1 to C.sub.6 alkyl, aryl, C.sub.1 to C.sub.3 alkyl-aryl, halogen (e.g. fluorine, chlorine, bromine or iodine), cyano, nitro, --(CH.sub.2).sub.m NR.sub.14 R.sub.15, --(CH.sub.2).sub.m OR.sub.9, --SR.sub.9, --SO.sub.2 NR.sub.14 R.sub.15, --(CH.sub.2).sub.m NR.sub.14 SO.sub.2 R.sub.15 --(CH.sub.2).sub.m NR.sub.14 CO.sub.2 R.sub.9, --(CH.sub.2).sub.m NR.sub.14 COR.sub.9, --(CH.sub.2).sub.m NR.sub.14 CONHR.sub.9, --CONR.sub.14 R.sub.15, or --CO.sub.2 R.sub.9 ; R.sub.2 and R.sub.3, R.sub.3 and R.sub.4, or R.sub.4 and R.sub.5 may be taken together to form a five- to seven-membered alkyl ring, a six-membered aryl ring, a five- to seven-membered heteroalkyl ring having 1 heteroatom of N, O, or S, or a five- to six-membered heteroaryl ring having H 1 or 2 heteroatoms of N, O, or S and the pharmaceutically acceptable salts thereof. These compounds are useful in treating migraine and other disorders. These compounds are useful psychotherapeutics and are potent serotonin (5-HT.sub.1) agonists and benzodiazepine agonists and antagonists and may be used in the treatment of depression, anxiety, eating disorders, obesity, drug abuse, cluster headache, migraine, pain and chronic paroxysmal hemicrania and headache associated with vascular disorders, and other disorders arising from deficient serotonergic neurotransmission. The compounds can also be used as centrally acting antihypertensives and vosodilators. ##STR1##

The present invention relates to Indole derivatives, intermediates for their preparation, pharmaceutical compositions containing therm, and to their medicinal use. The active compounds of the present invention are useful in treating migraine and other disorders.
U.S. Pat. Nos. 4,839,377 and 4,855,314 and European Patent Application Publication Number 313397 refer to 5-substituted 3-aminoalkyl indoles. The compounds are said to be useful for the treatment of migraine.
British Patent Application 040279 refers to 3-aminoalkyl-1H-indole-5-thioamides and carboxamides. The compounds are said to be useful in treating hypertension, Raymond's disease and migraine.
European Patent Application Publication Number 303506 refers to 3-poly:hydropyridyl-5-substituted-1 H-indoles. The compounds are said to have 5-HT.sub.1 receptor agonist and vasoconstrictor activity and to be useful in treating migraine.
European Patent Application Publication Number 354777 refers to N-piperidinyl:indolyl:ethyl-alkane sulfonamide derivatives. The compounds are said to have 5-HT.sub.1 receptor agonist and vasoconstrictor activity and to be useful in treating cephalic pain.
European Patent Application Publication Number 438230 refers to indole-substituted five-membered heteroaromatic compounds. The compounds are said to have 5-HT.sub.1 -like receptor agonist activity and to be useful in the treatment of migraine and other disorders for which a selective agonist of these receptors is indicated.
European Patent Application Publication Number 313397 refers to 5-heterocyclic indole derivatives. The compounds are said to have exceptional propertes for the treatment and prophylaxis of migraine, cluster headache, and headache associated with vascular disorders. These compound are also said to have exceptional "5-HT.sub.1 -like" receptor agonism.
International Patent Application WO 91/18897 refers to 5-heterocyclic indole derivatives. The compounds are said to have exceptional properties for the treatment and prophylaxis of migraine, cluster headache, and headache associated with vascular disorders. These compound are also said to have exceptional "5-HT.sub.1 -like" receptor agonism. European Patent Application Publication Number 457701 refers to aryloxy amine rivatives as having high affinity for 5HT.sub.1D serotonin receptors. These compounds are said to be useful for treating diseases related to serotonin receptor dysfunction, for example, migraine.
European Patent Application Publication Number 497512 A2 refers to a class of imidazole, triazole, and tetrazole derivatives which are selective agonists for 5-HT.sub.1-like receptors. These compounds are said to be useful for treating migraine and associated disorders.
"New Trends in Benzodiazepine Research" in Drugs of Today, Vol. 24, 649-663 (1987) discusses the use of benzodiazepine receptor ligands in the treatment of anxiety and other disorders.
European Patent Application EP-499527-A1 refers to novel .beta.-carboline derivatives with affinity for benzodiazepine receptors as useful in the treatment of degenerative central nervous system disorders, e.g. Alzheimer's disease.


The invention relates in particular to a method for adjusting the loading (19) of a particulate filter (9) and to an assembly designed to carry out the method, wherein the exhaust gas aftertreatment unit (8) comprises at least two SCR systems (11, 12) and a particulate filter (9), a first operating material amount being introduced in a metered manner before the first SCR system (11), and a second operating material amount being introduced in a metered manner before the second SCR system (12), the operating material being convertible into a reducing agent. The state of loading of the particulate filter (9) is determined using a model, and, if the determined state of loading is below a previously defined loading range (16), the first operating material amount is adjusted in such a way that the amount of reducing agent is greater than or equal to the amount of reducing agent necessary for nitrogen oxide reduction in accordance with the reaction stoichiometry in the first SCR system (11), and/or, if the determined state of loading is above a previously defined loading range (16), the first operating material amount is adjusted in such a way that the amount of reducing agent is less than the amount of reducing agent necessary for nitrogen oxide reduction in accordance with the reaction stoichiometry in the first SCR system (11).

The invention relates to a method according to the preambles of the independent claims. In particular, the invention relates to a method for adjusting and/or regulating the loading of a particulate filter and an arrangement designed for this purpose.
Different methods for regulating the loading of a particulate filter are known from the prior art. For example, methods are known in which the loading of the particulate filter is determined via the differential pressure. A disadvantage of such methods is, on the one hand, that in order to determine the loading a pressure sensor must be provided before the particulate filter and a pressure sensor after the particulate filter. Furthermore, in heavy vehicles, so-called heavy-duty vehicles, the state of loading of the particulate filter cannot be detected with sufficient accuracy via the differential pressure.
The object of the invention is to overcome the disadvantages of the prior art. In particular, it is the object of the invention to create a method for adjusting and/or regulating the loading of a particulate filter with which the loading of the particulate filter can be adjusted, easily, accurately and cost-effectively, in such a way that on the one hand the particulate filter exhibits a sufficiently high filtration efficiency and that on the other hand the flow resistance of the particulate filter is sufficiently low. The invention is thus based, inter alia, on the object of creating simple, accurate and cost-effective method for adjusting the loading of a particulate filter. In particular, a method is to be created which only uses the sensors of a conventional exhaust gas aftertreatment system.

Method for adjusting the loading of a particulate filter


The present disclosure provides a method for backing up a link state advertisement (LSA) for use in a distributed device comprising a main control board and an interface board. The main control board comprises a primary board and a standby board. The method comprises: receiving by the standby board LSA related information sent by the primary board; and generating by the standby board an LSA according to the LSA related information.

Open Shortest Path First (OSPF) is a link-state based interior gateway protocol developed by the Internet Engineering Task Force (IETF) organization. At present, OSPF Version 2 (RFC 2328) is used for IPv4 protocol. OSPFv3 is developed on the basis of OSPF, in order to support IPv6.
OSPFv3 protocol divides an autonomous system into different areas. The term "area" refers to that routers are divided logically into different groups, with each group being identified by an area ID. For example, a network system is divided into five areas Area 0 through Area 4, wherein one of the areas (such as Area 0) is connected to all the other areas Area 1 through Area 4 and is called the backbone area. The link state information of OSPFv3 diffuses only within the range of an area. Each area has an independent link state information library, and an independent Shortest Path First (SPF) calculation is performed within each area.
Link State Advertisement (LSA) is the main source for OSPFv3 protocol calculating and maintaining the routing information. RFC5340 defines several types of LSAs including Router-LSA , Network-LSA, Inter-Area-Prefix-LSA, Inter-Area-Router-LSA, AS-External-LSA, Link-LSA and Intra-Area-Prefix-LSA.
Intra-Area-Prefix-LSA: OSPFv3 moves the IP prefix directly reachable to the present machine which was notified by the stub link of the Router-LSA and the IP network segment of the broadcast network which was notified by the Network-LSA in OSPF to this type of LSA. This LSA propagates within an area, and is used for notifying in an area the IP prefix that is directly reachable within the area. Because this LSA can be generated according to a stub link, or generated according to a network LSA, so this LSA further functions as a reference type: being 2001 in case reference is made to a router LSA, and being 2002 in case reference is made to a network LSA.

Method for backing up link state advertisement


A method for deploying a service in a communication network by performing the steps of: invoking a service deployment engine by a request for the service, retrieval of deployment templates, retrieval of service deployment policies, determination of a current configuration of at least one network element involved in providing the service, and selection of a deployment template from the retrieved deployment templates based on the service deployment policies and configuration. Further, a method for configuring a network element via a network element controller through the intermediary of a network element proxy.

Telecommunication networks such as the internet are an increasingly important source of information and electronic communication for users of computers in homes and businesses. A major problem associated with the internet, however, is the difficulty faced by typical computer users in connecting their computers or local area networks to the internet. For example, a computer user desiring to connect to the internet must make many critical decisions, such as which communication medium to use, which internet service provider to subscribe to, how to secure the network interface and which network services to utilize.
Likewise business managers in charge of local or wide area networks must also address questions related to the type and configuration of computer networks which are to be connected to the internet, and other such external networks. Installing an external network connection typically requires an understanding of many different communication protocols, network services, connection media and computer network practices.
This complexity is further increased by the increasing numbers of types of network elements, functionalities, protocols and services etc.
U.S. Pat. No. 6,230,194 discloses a system for upgrading the software contents of a network interface device connecting a client computer system to an external network. The network interface device is configured for the client system by automated procedures and protocols initiated from a remote server. Software programs within the network interface device provide transparent communication between the client computer system and services available on the external network. Similar software programs and a configuration database within the network interface device provide transparent communication between the client computer system and the remote server.
U.S. Pat. No. 6,237,031 discloses a system for dynamically controlling a network proxy. Network proxies are configured to have free access to both internal LAN resources and external resources, and can safely pass data back and forth across a firewall. Users may then be given safe, though indirect, access to web resources by configuring the user's web browser to reference the network proxy instead of external target servers. When the web browser is used to retrieve information from outside the firewall it sends a request to the network proxy, which then completes the request and returns the result to the requester.
U.S. Pat. No. 6,222,843 discloses a method for providing services in a telecommunication network. The method relies on an open services architecture incorporating an adaptive grooming router providing an interconnected backbone network function for connectivity between a plurality of multimedia access routers and a narrow band network, wherein the multimedia access routers provide each a hub point.
U.S. Pat. No. 6,229,810 shows a network server platform for a local loop network service architecture. The network service platform aims to address the problem that DSL modem technology is not standardized. In order to ensure compatibility the type of DSL modem provided by a local telephone company must also be provided to the end user in the customer premises equipment. Additionally, since the network is not completely controlled by the inter-exchange companies, it is difficult for the inter-exchange companies to provide data at committed delivery rates.
Therefore, it is a common problem of the prior art to manage the configuration of network elements for the purposes of deploying services over a communication network both from the perspective of the end user and for the service provider.

Method for deploying a service and a method for configuring a network element in a communication network


A setup method for a corona charger device used in an electrophotographic recording apparatus. The setup method includes operating the corona charger device in a calibration mode so that charge of a first polarity is output by the device and deposited upon a photoconductive recording member. The level of charge deposited upon the member is sensed and a position of the charger device relative to the member is adjusted so that the level of charge deposited upon the member is at a target level. The charge of the first polarity output for setup is opposite to that of charge output during the production run.

Electrophotographic printers and copiers commonly use composite photoconductors as the means to create latent electrostatic images. Composite photoconductors have a photosensitive layer (charge generation layer or CGL) and a charge transport layer (CTL). The CGL is able to generate a hole/electron pair and can transport charges of both polarities. The CTL layer is normally designed such that it will only transport one charge species (only negative or only positive charge carriers) to provide stability. Due to the fact that the CTL can transport only one species of charge carrier, a composite design results in a photoconductor that is meant to be useful for creating latent images when the surface is charged in the intended polarity. If the photoconductor is charged in the opposite polarity and then exposed to light, charges may become trapped in the photoconductor structure. These trapped charges result in poor performance or permanent damage of the photoconductor.
It is common in electrophotographic systems to have functions that require the surface of the photoconductor to be charged in the polarity opposite to that with which they are designed to be used. One such function is the corona charger that conditions the photoconductor prior to the photoconductor cleaning apparatus. The charger must charge the photoconductor and the residual toner left on the photoconductive member after image transfer to a level to facilitate removal of the residual toner. Another example of a function that requires the use of a charger of the opposite polarity is the transfer charger in a Discharge Area Development (DAD) device. DAD electrophotographic printers make use of toners that charge in the same polarity in which the photoconductive member is light sensitive. A charger of opposite polarity is required in the transfer function to cause the toned image to migrate to the receiver member.
To simplify the description of this invention, we will assume that the composite photoconductor in use is designed with a hole transport CTL. In this case, the film is designed to be charged negatively. A corona charger operating in the positive mode with such a photoconductor would benefit from use of this invention. The discussion could be applied to a positive charging photoconductor by changing all the references to negative charging to positive charging and visa versa.
Corona chargers in electrophotographic devices need to be spaced accurately from the photoconductive member to assure that uniform charge is applied to the photoconductor surface. It is common to have an adjustment feature designed into the corona charger to facilitate setting up a precise spacing between the charger and the surface of the photoconductive member. The uniformity of the charge laid down on the photoconductive member is measured by the use of an electrostatic voltmeter. The spacing of the corona charger to the photoconductive member is varied until a uniform charge is obtained. To assure consistent charging of the photoconductive member, it is required that the charge is erased after being measured by the electrostatic voltmeter. The use of erasure assures that a consistent charge level is on the photoconductive member as it enters the corona charger that is being set up.
The setup of a corona charger which charges the photoconductor in the negative polarity is straight forward. The photoconductor is charged by the corona charger to be adjusted, measured by an electrostatic voltmeter, and then erased by an exposure device to return the film to a stable level. Setup of chargers in an electrophotographic system which charges the photoconductive member in the positive polarity is more difficult. This is due to the fact that if the photoconductor is charged in the positive polarity the charge cannot be erased by an exposure device.
In systems that require the setup of a charger that operates in the positive polarity, use of an additional charging device which charges the photoconductive member to the negative polarity is commonly used. Normally the primary charger is used to accomplish this function. This charger reverses the charge level on the photoconductive member, allowing the photoconductor to be erased with an exposure device without damaging the photoconductor from trapped charge in the photoconductive layer or layers. This provides a stable input voltage for the positive charger being adjusted for uniformity.
The use of this method has some drawbacks. This method requires that either:
1. The electrostatic voltmeter probe be placed between the charger being setup and the charger that returns the photoconductive member to the negative polarity. This is often inconvenient and results in the need to facilitate multiple positions to locate the electrostatic voltmeter probe depending on the charger being setup, or PA1 2. An algorithm be provided that cycles the negative charger, that returns the photoconductive member to the negative polarity, off and on precisely. The readings for the positive charger being set up in the positive polarity are taken for one revolution, then the photoconductive member is charged to the negative polarity by the negative charger and erased. The cycle can then begin again.

Method of setting position of a corona charger


A security circuit for an IEEE Standard 1149.1 compliant PLD that is controlled by a security bit or bits programmed when the PLD is incorporated into a final product. The security circuit includes a switch connected directly or indirectly into the Boundary-Scan Register (BSR) chain of the PLD. The security bit applies a control signal to the switch such that test data signals generated during INTEST procedures are either passed through the switch, or blocked by the switch. For example, when the Boundary-Scan architecture of the PLD is set for INTEST procedures when the security bit is set in a first programmed state, the logic gate passes test data from an input terminal to an output terminal. Conversely, when the security bit is set in a second programmed state, the logic gate masks the test data values received at the input terminal (i.e., the shifted test data is blocked).

The present invention relates to IEEE Standard 1149.1 compliant ICs, and more particularly to IEEE Standard 1149.1 compliant PLDs.
Programmable Logic Devices (PLDs) are Integrated Circuits (ICs) that are user configurable and capable of implementing digital logic operations. There are several types of PLDs, including Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs). CPLDs typically include several function blocks that are based on the well-known programmable logic array (PLA) architecture, and include a central interconnect matrix to transmit signals between the function blocks. Signals are transmitted into and out of the interconnect matrix through input/output blocks (IOBs). The input/output function of the IOBs, the logic performed by the function blocks and the signal paths implemented by the interconnect matrix are all controlled by configuration data stored in configuration memory of the CPLD. FPGAs include configurable logic blocks (CLBs) arranged in rows and columns, IOBs surrounding the CLBs, and programmable interconnect lines that extend between the rows and columns of CLBs. Each CLB includes look-up tables and other configurable circuitry that is programmable to implement a portion of a larger logic function. Similar to CPLDs, the CLBs, IOBs and interconnect lines of FPGAs are controlled by configuration data stored in a configuration memory of the FPGA.
PLDs have become popular for implementing various logic functions in electronic systems that, in the recent past, were typically implemented by smaller ( less than 100,000 gates) application specific integrated circuits (ASICs). Such functions include glue logic, state machines, data bus logic, digital signal processors and protocol functions. Early PLDs often provided insufficient capacity to implement these functions, so the significant investment of time and money to design, layout and fabricate an ASIC for these functions was justified. However, recent advances in semiconductor and PLD technologies have produced PLDs with the necessary speed and capacity to implement these functions in most applications. Because PLDs are relatively inexpensive and can be programmed in as little as a few hours, the expense associated with the design, layout and fabrication of ASICs has become harder to justify. Further, the reprogrammability of many PLDs makes them even more attractive than ASICs because it is possible to update (reconfigure) PLDs, whereas ASICs must be replaced. As such, there is a trend toward the use of PLDs in place of ASICS in electronic systems.
As the capacity and performance of PLDs continues to increase, so too does the complexity of the configuration data used to configure the PLDs. In many instances, the configuration data is developed and modified over a long period of time, and represents a significant investment to the company that develops the configuration data. To protect the proprietary interests of such companies, a security function is provided on most PLDs that prevents a would-be pirate from simply downloading the configuration data from the PLD, thereby preventing the would-be pirate from replicating or reproducing the circuit design implemented on the PLD. This security function is typically implemented as a programmable bit that is set during PLD configuration.
IEEE Standard 1149.1 defines circuitry that allows test instructions and associated test data to be fed into a compliant IC and, subsequently, allows the results of execution of such instructions to be read out of the compliant IC. All information (i.e., instructions, test data, and test results) is communicated in a serial format via a four pin serial interface (referred to as the Test Access Port, or TAP) that drives a 16-state controller (state machine) formed in each compliant IC device. The four pins control transitions of the state machine that facilitates loading of instructions and data into the compliant IC device to accomplish pre-defined tasks. As set forth in greater detail below, one such task is a special instruction named INTEST. The INTEST instruction allows static (slow-speed) testing of the on-chip system logic, with each test pattern and response being shifted through a series of Boundary-Scan registers located, for example, at the I/O pins of IEEE Standard 1149.1 compliant PLDs.
A problem presented by IEEE Standard 1149.1 compliant PLDs is that the INTEST instruction can be used by potential pirates to thwart the security function of a PLD in order to replicate or reproduce the circuit design implemented on the PLD. This problem is set forth is additional detail below by first describing IEEE Standard 1149.1 circuitry found on compliant PLDs, and then illustrating by example how the INTEST instruction can be used to determine the configuration data stored on the PLD.
Originally, IEEE Standard 1149.1 was developed to test the interconnections and IC device placement on PCBs through connection pins of the PCBs (i.e., without the need for a mechanical probe). Since its establishment, IEEE Standard 1149.1 has been extended to include device self-tests, diagnostics, and functional tests such as the INTEST instruction.
FIG. 1 shows a simplified electronic system provided for the purpose of explaining the basic concepts of Boundary-Scan Test procedures. The simplified electronic system is formed on a PCB 100 and includes a first PLD 110 and a second PLD 120.
PCB 100 includes normal operation copper traces formed on a board of insulating material that provide signal paths between a PCB connector 101 and PLDs 110 and 120, and between PLDs 110 and 120. These normal operation copper traces are used, for example, to transmit configuration signals to PLDs 110 and 120, and to carry data signals during device operation. In addition to the normal operation copper traces, PCB 100 includes special purpose copper traces for transmitting signals associated with IEEE Standard 1149.1. These special purpose copper traces include a first trace 102 for transmitting test data-in (TDI) signals, a second trace 103 for transmitting test data-out (TDO) signals, a third trace 104 for transmitting test clock (TCK) signals, and a fourth trace 105 for transmitting test mode select (TMS) signals. Data (TDI/TDO) signals are typically transmitted serially through each compliant device of a system. That is, TDI signals are transmitted on first trace 102 to first PLD 110, and pass through first PLD 110 along a line 144(1). TDO signals are transmitted from PLD 110 and received as TDI signals by second PLD 120 along a linking trace 106, and pass through second PLD 120 along a line 144(2). Finally, TDO signals are transmitted from PLD 120 to PCB connector 101 on second trace 103. In contrast to the data signals, each compliant device receives the TCK and TMS signals in a parallel manner.
Each PLD of an electronic system includes IOBs that configure the device terminals (pins) for transmitting signals to or from the PLDs programmable core logic circuitry. As shown in FIG. 1, first PLD 110 includes I/O terminals 112 that transmit/receive signals via lines 114 through respective IOBs 116 to/from programmable core logic circuit 118. Similarly, second PLD 120 includes I/O terminals 122 that transmit/receive signals via lines 124 through IOBs 126 to/from core logic circuit 128.
Unlike ASICs, the functions performed by both core logic circuit 118 and IOBs 116 of PLD 110 are determined by configuration data loaded after fabrication. That is, function or functions to be performed by the programmable interconnect and logic circuitry associated with a PLD is determined after fabrication. Similarly, the determination of which I/O pins will be used for input operations, and which I/O pins will be used for output operations is made after fabrication. As described in additional detail below, this flexible pin usage requires each IOB 116 to include programmable circuitry capable of performing both input and output operations.
In addition to core logic and input/output circuitry, each IC device that complies with IEEE Standard 1149.1 includes dedicated pins and hardware elements (referred to herein as Boundary-Scan architecture). Referring to FIG. 1, first PLD 110 includes four pins 142(1) through 142(4) that are respectively connected to trace 102 (TDI), trace 105 (TMS), trace 104 (TCK) and trace 106 (TDO). Similarly, second PLD 120 includes four pins 142(5) through 142(8) that are respectively connected to trace 106 (TDI), trace 104 (TCK), trace 105 (TMS) and trace 103 (TDO). The Boundary-Scan architecture of each PLD 110 and 120 includes control circuitry (TEST CONTROL CIRCUIT) and one or more data registers (not shown) that are, for example, incorporated into IOBs 116 and 126. The data and control circuitry of the Boundary-Scan architecture provided on each compliant device utilize the signals received on the four dedicated pins.
FIG. 2 is a detailed block diagram showing an example of the basic hardware elements associated with the Boundary-Scan architecture of an IEEE Standard 1149.1 compliant PLD. The basic hardware elements include a test access port (TAP) 210, a TAP controller 220, an instruction register (IR) 230, an instruction decode circuit 235, a test data register circuit 240, an output multiplexer (MUX) 250, an output flip-flop 260 and a tri-state buffer 270. These hardware elements are well known to those of ordinary skill in the art of designing IEEE Standard 1149.1 compliant ICs. Therefore, only basic hardware elements that are utilized to perform the INTEST instruction will be described herein.
TAP 210 provides access to the test support functions build into an IEEE Standard 1149.1 compliant PLD. TAP 210 includes three input connections for receiving the test clock input (TCK) signal, the test mode select (TMS) signal, and the test data input (TDI) signal. The TCK signal allows the Boundary-Scan architecture to operate synchronously and independently of the built-in system clock provided on the PLD. The TMS signal is used to control the state of TAP controller 220, as discussed below. The TDI signal is used for serial transmission of data or instruction bits, depending upon the state of TAP controller 220. TAP 210 may also include an optional fourth input terminal for receiving a test reset input signal for asynchronous resetting of TAP controller 220. In addition to the above-mentioned input connections, TAP 210 includes an output connection through which the TDO signals are transmitted. Depending upon the state of TAP controller 220, the TDO signal is used to serially shift either instruction register or data register contents out of the PLD.
FIG. 3 is a state diagram for explaining the operation of TAP controller 220 (shown in FIG. 2). The basic function of TAP controller 220 is to generate clock and control signals required for the correct sequence of operations of instruction register 230, test data register circuit 240, output MUX 250, output flip-flop 260 and tri-state buffer 270. Specifically, TAP controller 220 control signals that facilitate loading of instructions into instruction register 230, shifting TDI data into and TDO data out of the data registers in test data register circuit 240, and performing test actions such as capture, shift and update test data. These signals are provided in accordance with the state of TAP controller 220. All state transitions (indicated as arrows in FIG. 3) within TAP controller 220 occur in accordance with the serially received TMS values (shown next to each arrow).
FIG. 4 is a simplified schematic diagram showing an IOB 116 that includes a portion of the Boundary-Scan architecture formed along line 144(1) of first PLD 110 (see FIG. 1). IOB 116 includes an input buffer IB, a tri-state buffer TS and Boundary-Scan Register (BSR) cells 243(1) through 243(3). IOB 116 is configured by an output enable (OE) signal (which is transmitted through BSR cell 243(3)) either to receive input data signals applied to an I/O pin 112, or to transmit output data signals to I/O pin 112. When the OE signal is in a first state (e.g., low), IOB 116 is configured for receiving input signals from I/O pin 112 (i.e., tri-state buffer TS is set in a tri-state mode). In the input mode, input buffer IB transmits DATA IN signals applied to I/O pin 112 through BSR cell 243(1) and on a SYSTEM INPUT line to, for example, the PLD core logic circuit. Conversely, when the OE signal is in a second state (e.g., high), IOB 116 is configured for transmitting output signals to I/O pin 112. In the output mode, output signals transmitted on a SYSTEM OUTPUT line from, for example, the PLD core logic circuit are applied to I/O pin 112 through BSR cell 243(2) and tri-state buffer TS.
BSR cells 243(1) through 243(3) are linked in the manner described below to form a BSR chain along which test data bits are shifted to implement, for example, INTEST procedures. Each BSR cell 243(1) through 243(3) respectively includes an input multiplexer (MUX) 410(1) through 410(3), a shift register flip-flop 420(1) through 420(3), a parallel latch 430(1) through 430(3) and an output MUX 440(1) through 440(3). Each input MUX 410(1) through 410(3) is controlled by a SHIFT/LOAD-DR control signal to either load SYSTEM DATA or shift TDI data from a previous BSR cell of the BSR chain. The selected data is transmitted to shift register flip-flops 420(1) through 420(3) that store the received data in response to a CLOCK DR control signal generated by the TAP controller. Shift register flip-flops 420(1) through 420(3) transmit the stored data either to a next of the BSR cell (or to TDO if transmitted from the last BSR cell) and to parallel latches 430(1) through 430(3), respectively. Parallel latches 430(1) through 430(3) store the data from shift register flip-flops 420(1) through 420(3) in response to an UPDATE-DR control signal from the TAP controller, and transmit this data to output MUXes 440(1) through 440(3), respectively. Output MUXes 440(1) through 440(3) are controlled by a MODE TEST/NORM control signal from the instruction register to either transmit SYSTEM data (during normal operation) or the contents of parallel latches 430(1) through 430(3) (e.g., during INTEST procedures). The signals from output MUXes 440(1) through 440(3) are either transmitted to the core logic (when BSR cell 243 is associated with an input pin) or to the output pin of the PLD.
During INTEST procedures, test data signals are serially transmitted through BSR cells 243(1) through 243(3) in response to the SHIFT-DR and CLOCK-DR signals generated by the TAP controller. Specifically, BSR cell 243(1) receives a TDI signal from a previous BSR cell (not shown) of the BSR on line segment 144(A). This TDI signal is shifted through multiplexer 410(1) and shift register flip-flop 420(1) and transmitted to BSR cell 243(2). Subsequently, BSR cell 243(2) shifts this TDI signal through multiplexer 410(2) and shift register flip-flop 420(2), and transmits it to BSR cell 243(3). Finally, BSR cell 243(3) shifts the TDI signal through multiplexer 410(3) and shift register flip-flop 420(3), and transmits it on line segment 144(B) to a subsequent IOB associated with the BSR.
A problem associated with conventional IEEE Standard 1149.1 compliant PLDs supporting INTEST instructions arises because the Boundary-Scan architecture can be utilized to deduce the functionality of logic resident on the IC by shifting test data values into the BSR cells of IC on the BSR chain, and then analyzing the logic output generated in response to the entered values. By systematically entering all possible combinations of test data values into the BSR cells, the INTEST instruction provides an unintended path for the replication of the IC logic design that works around any device security feature. This problem is illustrated with reference to FIGS. 5(A) through 5(D).
FIGS. 5(A) through 5(D) are simplified schematic diagrams showing a conventional IEEE Standard 1149.1 compliant PLD 500 in which portions of programmable core logic circuit 518 are utilized to implement a two-input AND gate. PLD 500 includes three IOBs 116(1), 116(2) and 116(3), each including three BSR cells that are serially connected to form a BSR chain along line 505. IOBs 116(1), 116(2) and 116(3) are assigned to the input and output signals of the two-input AND gate implemented in core logic circuit 518. In particular, IOBs 116-1 and 116-2 are assigned to transmit input signals from their associated pins to the AND gate, and IOB 116-3 is assigned to transmit the output signal from the AND gate to its associated pin.
Referring to FIG. 5(A), at the beginning of the INTEST procedure, a series of test data values (1,0,0,0,0,1,1,0,0) are shifted into PLD 500 via the TDO terminal and BSR chain 505 from a test data source 510. The data shifting process is implemented by maintaining the TAP controller in SHIFT-DR state 305 (see FIG. 3) for the amount of time required to shift-in the test data values. Note that the test data values previously stored in IOBs 116(1), 116(2) and 116(3) (indicated with X) are simultaneously shifted along BSR chain 505 to test data source 510.
FIG. 5(B) illustrates the location of test data signals in IOBs 116(1), 116(2) and 116(3) after the shifting process is completed. In particular, a logic xe2x80x9c1xe2x80x9d is stored in BSR cells 243(11), 243(21) and 243(33), and a logic xe2x80x9c0xe2x80x9d is stored in the remaining BSR cells. At this point of the INTEST procedure, the TAP controller is moved into UPDATE-DR state 309 (see FIG. 3), thereby causing the test data values to be shifted from the shift register flip-flops 420(X) to the parallel latches 430(X) (see FIG. 4).
FIG. 5(C) illustrates the process of applying the test values in accordance with the internal logic of PLD 500. To perform this process, the TAP controller is moved to RUN-TEST/IDLE state 302, at which point the system clock of PLD 500 pulses to cause operation of core logic 518. As indicated by the arrows, the logic xe2x80x9c1xe2x80x9d values transmitted from BSR cells 243(11) and 243(21) are applied to the logic implemented in core logic 518, which generates an output value (i.e., logic xe2x80x9c1xe2x80x9d value) that is subsequently captured by BSR cell 243(32) when the TAP controller moved to CAPTURE-DR state 304 (see FIG. 3). Note that this logic xe2x80x9c1xe2x80x9d value overwrites any previously stored value.
Referring to FIG. 5(D), at the end of the INTEST procedure, a dummy series of test data values (X,X,X,X,X,X,X,X,X) are shifted into PLD 500 via the TDO terminal and BSR chain 505 from a test data source 510. The data shifting process is implemented by returning the TAP controller to SHIFT-DR state 305 (see FIG. 3). Note that the test data values stored in IOBs 116(1), 116(2) and 116(3) are simultaneously shifted along BSR chain 505 to test data source 510.
The test data values generated in FIG. 5(D) are then analyzed to determine the logic performed by PLD 500. By systematically transmitting sets of test data values and comparing the results, the logic implemented in core logic 518 can be replicated, thereby circumventing the IC logic design that works around any security feature provided on PLD 500.
What is needed is a Boundary-Scan architecture that includes a security device for selectively preventing INTEST operations after a IEEE Standard 1149.1 compliant PLD is configured, thereby preventing would-be pirates from replicating configuration data stored on the PLD.
The present invention is directed to a Boundary-Scan architecture for an IEEE Standard 1149.1 compliant IC that prevents would-be pirates from replicating the logic of the IC using INTEST or other Boundary-Scan instructions by blocking data that is shifted along the Boundary-Scan chain.
In accordance with the present invention, an IEEE Standard 1149.1 compliant IC includes a Boundary-Scan architecture having a security circuit including a switch controlled by a security bit that is selectively enabled or disabled by the IC programmer. In one embodiment, the switch includes a logic gate having a first input terminal and an output terminal connected directly to the Boundary-Scan Register (BSR) chain. The security bit applies a control signal to a second input terminal of the logic gate. When the security bit is in a first programmed state, the logic gate passes test data from the first input terminal to the output terminal that is shifted along the BSR chain to permit normal Boundary-Scan (e.g., INTEST) procedures. Conversely, when the security bit is in a second programmed state, the logic gate generates a predetermined data value onto the BSR chain despite the test data values received at the first input terminal (i.e., the shifted test data is blocked). Blocking the passage of shifted data prevents would-be pirates from using the INTEST operations to replicate the logic of the IC, or the logic function implemented by a PLD.
In another embodiment, the security circuit is located in a signal path connected between the I/O pin and the core logic circuit of a host PLD. During operation, the security circuit is selectively controlled to block test data values from being driven into or captured from the core logic circuit via an associated Boundary-Scan register (BSR cell). When the security bit of the security circuit is disabled, the security circuit passes the test data values being driven into or captured from the core logic circuit. In contrast, when the security bit of the security circuit is enabled, a high INTEST signal causes the security device to generate a low (logic xe2x80x9c0xe2x80x9d) output signal. This low output signal is captured by the associated BSR cell, and the transmitted along the BSR chain during a subsequent data shift operation. Consequently, instead of including test data indicating the configuration of the core logic circuit, the resulting data stream is entirely made up of low (logic xe2x80x9c0xe2x80x9d) output signals. Therefore, it is not possible for a would-be pirate to determine the logic implemented in core logic utilizing the INTEST instruction.

Intest security circuit for boundary-scan architecture


A spherical roller bearing having an axially extending center axis with an outer ring, an inner ring arranged concentrically with the outer ring, a guide ring arranged concentrically with the inner ring and the outer ring, wherein the guide ring has a tapering radial cross-section, one set of cambered rollers on either side of the guide ring and a cage structure arranged to retain the two sets of cambered rollers. The guide ring having two circumferential guide ring sections, an inner guide ring section proximal to the inner ring and an outer guide ring section distal to the inner ring. At least one through-opening extends between two lateral surfaces of the guide ring. The at least one through-opening is arranged in the inner guide ring section and the cambered rollers of each set are distanced from the inner guide ring section and in contact with the outer guide ring section.

Spherical roller bearings are designed to accommodate heavy radial and axial loads. Structurally, they typically have an outer ring, an inner ring and, between these, there are two rows of oppositely arranged rolling elements that are separated by and interacting with a guide ring, also called centering ring or spacer, so as to optimally distribute the load.
Various tribological components of spherical roller bearings, including the aforementioned, are usually exposed to substantial heat generation and friction, and, eventually, wear. In order to alleviate consequences of this exposure, various coolants and lubricants are applied. In certain applications, such as gear boxes, a single substance, typically suitable oil, is used both for cooling and lubrication. Oil is splashed or flushed through the application and subsequently cooled, either internally or in an external heat exchanger. In this context and as is known in the art, spherical roller bearings are on a general level very compactly designed in order to maximize the number of rolling elements used. Hence, achieving that the coolant/lubricant is sufficiently spread throughout the bearing is associated with considerable difficulties. In addition, the guide ring acts as a barrier between the two rows of rolling elements and prevents fluid passage across the guide ring.
DE102012219512 discloses a spherical roller bearing with a perforated guide ring extending between the rotatable outer ring and the fixed inner ring. DE102012219512 presents a bearing for use in so called vibrating screen applications. Vibrating screens are vibrating sieving devices that separate solids from crushed material in technology fields such as mineral processing, mining and quarry.
Cross-section of the guide ring has the shape of a trapezoid. A plurality of transit channels is arranged in the guide ring. The transit channels prevent inadvertent accumulation of oil in the bearing and reduce back-pressure on both sides of the guide ring. As it may be seen, the portion of the guide ring having the transit channels provides the contact surface for the rolling element.
On a general level, interior of the spherical roller bearing is a rather extreme environment. For instance, the guide ring must withstand elevated pressures due to its contact with an end of the rolling element. On this background and for maximal structural stability, components of the roller bearing are typically made in wear-resistant materials and without dents, cavities and/or perforations.
Accordingly, it is desirable that the portion of the guide ring brought in contact with the rolling elements is devoid of structural weakenings, such as the transit channels disclosed in DE102012219512. Otherwise, this structural weakening must be compensated, by way of example by adding more material and/or by using more advanced materials.
An objective of the present invention is therefore to provide a spherical roller bearing not ridden with drawbacks that are associated with spherical roller bearings belonging to the prior art. A further objective is to provide an improved spherical roller with the components manufactured using standard production processes. Here, improvement of the properties of the production process, e.g. achieving material savings, is a further objective of the present invention.


Handling ability can be improved and operational defect at a time of integral formation with a rubber like elastic seal lip can be prevented by effecting a chamfering working to an edge portion of a conical washer like resin ring. In a method in which a conical washer like resin ring 40 is formed by conically cutting away an end surface 51 of a cylindrically formed resin material 50 with a predetermined thickness and the resin ring is utilized as a seal lip 3 by assembling the inner diameter end portion or outer diameter end portion with a device body, it is characterized in that a sharply projecting edge portion 47 on the side utilizing as the seal lip of the conical washer like resin ring 40 is subjected to chamfering working 45, 46. It is characterized in that the resin ring 40 is assembled with the device body having a rubber like elastic seal lip 2.

In a conventional sealing device with a resin seal lip (such as shown in FIG. 9), a washer-shaped resin ring 100 is formed, the outer diameter side of the resin ring 100 is assembled with a device body 101, and the inner end of the resin ring 100 is contacted in a sealing manner to an objective member, thus forming a resin seal lip 102.
The resin ring 100 is formed by cutting a cylindrical resin material 103 so as to have a conical washer-like shape so that the resin seal lip 102 is preliminarily provided with an inclination so as to facilitate formation thereof.
However, in the described prior art, when the a cylindrical resin material 103 is cut away in a conical shape, a thin edge portion 104 having a sharp angle .beta. smaller than 90.degree. is formed at an end portion of the resin ring 100. Since this thin edge portion 104 is easily deformable, it is difficult to handle the same.
In the case of a compound type sealing device, as shown in FIG. 9(c), having a seal lip 105 formed of a rubber like elastic material and a resin seal lip 102, when the rubber like elastic seal lip 105 is molded, the resin ring 100 is inserted and the assembling of the resin ring 100 and the molding thereof are carried out at the same time as shown in FIG. 10(a). At the completion of the molding and the opening of the mold, the resin ring 100 separates from the rubber like elastic seal lip 105 due to its elastic restoring force and falls down to an inner diameter side so as to have an interference.
However, the rubber base material 106 fluidized at the molding formation time extends around so as to bite the edge portion 104, so that, when the edge portion 104 has a sharp end, a go-round portion 107 engages the edge portion 104 of the resin ring 100 and the resin seal lip 105 sharply turns to the inner diameter side (see FIG. 10(b)).
Further, in a case where the resin seal lip 105 returns, when a shaft is inserted, the front end of the resin seal lip 102 is interferred with by the rubber like elastic seal lip 105. The rubber like elastic seal lip 105 widens and acts in a direction reducing the interference, so that the reliance of the rubber like elastic seal lip 105 is lowered (see FIG. 10(c)).
The present invention was conceived to solve the above problems of the prior art and aims to provide a sealing device and a method of munufacturing the same capable of improving a handling ability thereof and preventing an operational defect at a time of the integral molding with the rubber like elastic seal lip by effecting a chamfering working to the edge portion of a resin ring so as to provide a conical washer shape.

Sealing device and sealing device manufacturing method


From an input video signal, a pixel value of a pixel of notice noted at a certain time t and a proximal pixel group adjacent two-dimensionally around the pixel of notice are sampled, and maximum and minimum values from the proximal pixel value group are selected as candidate pixel values. By performing a specific operation between the pixel value of the pixel of notice and the candidate pixel value group, a judgment is made as to whether a pulse noise is contained in the pixel of notice. On the basis of the judgement, a pixel value is selected from among the pixel value of the pixel of notice and the candidate pixel values and delivered.

1. Field of the Invention
The present invention relates to a circuit for removing pulse noise components superposed on a video signal delivered from a solid-state image pickup device having pixel defects.
2. Description of the Prior Art
In image pickup devices such as video cameras, solid-state pickup devices are often used in the optoelectric conversion unit. When the output signal of the solid-state image pickup device is displayed by a monitor device and the video signal is observed, pixel defects known as white spots or black spots are sometimes observed in the picture. Such pixel defects are very obvious even if they are small in size, and pickup devices having pixel defects cannot be used as a commercial product, so that the production yield is lowered. Also, pixel defects can occur even after shipping of products. These problems are peculiar to the solid-state image pickup device, and present serious obstacles to their use.
Hitherto, as the means for solving the above problems, in a first example, as shown in U.S. Pat. No. 4,473,845, onset positions of pixel defects are stored in a PROM or the like, and the pixel defects are corrected by using the preceding and succeeding pixels on the scanning line at a timing when the output of the solid-state image pickup device corresponds to the stored position in the PROM.
In this first prior art example, the PROM is required as the means for storing the position of pixel defects. However, since the position of the pixel defects occurring in the solid-state pickup device varies from device to device, it is necessary to investigate the pixel defect position in each device and prepare a corresponding PROM, which requires too much labor. Further, this method is useless for pixel defects occurring after shipping of products.
As a second example, as disclosed in the Japanese Laid-open Patent Application Sho. 61-261974, pixel defects are detected by comparison of a pixel of notice with adjacent pixels positioned in the scanning line direction or in the direction vertical to the scanning line direction with respect to the pixel of notice, and the signal value of the pixel of notice is replaced by the value of one preceding pixel or the mean value of the preceding and succeeding pixels, so that the detected pixel defect is corrected.
In the second prior art example, when detecting pixel defects, attention is paid only to the scanning line direction or the direction vertical to the scanning line direction. However, since no comparison is made with respect to pixels in oblique directions, fine line segments in oblique directions to the scanning line are detected as pixel defects, and all line segments in oblique directions may be removed. Also, when correcting pixel defects, the pixel value is replaced by one preceding pixel or the mean value of preceding and succeeding pixels, but if there is a pixel defect on a fine line segment extending in the direction vertical to the scanning line direction, the line segment may be cut off as a result of correction.

Pixel defect removing circuit for solid-state image pickup device

Matsushita Electric Industrial Co., Ltd.


Power management for a computer system and device is accomplished by implementing two separate power modes in a serially-connected device, and selecting from the two power modes depending on the state of a receiver in the device. A signal detector within the receiver is connected to a serial interface port of the device to detect the presence of an input signal. A power controller selects a first power mode for the device when the signal detector detects the input signal and a second power mode for the device when the input signal is not detected by the signal detector.

In modern computer systems, an input/output (I/O) subsystem enables communication between a central processor and one or more peripheral devices, such as a disk drive, modem, graphics card, keyboard, mouse, sound card or print driver. The I/O subsystem is typically implemented according to a standard I/O specification, such as the parallel bus implementation described in the Peripheral Components Interconnect (PCI) Local Bus Specification, Rev. 2.3, dated Mar. 29, 2002.
In the future, to increase performance and scalability, the parallel bus implementation will likely be replaced by a serial interface implementation, such as the one described in PCI Express Base Specification, Rev. 1.0a, dated Apr. 15, 2003 (hereinafter "PCI Express"). Serial I/O subsystems are composed of serial point-to-point unidirectional or bi-directional packet-switched links between devices (or components) in the computer system.
Although the data rates achievable with serial I/O interfaces are much higher than that achievable with traditional I/O parallel buses, the power required to drive such serial I/O interfaces is significantly higher than that for a parallel bus. In all computer systems, and especially in battery-driven portable computer systems, such as laptop computers, personal digital assistants, wireless or cellular telephones and other such devices, power management is an important factor in determining whether to replace the parallel bus with serial I/O interfaces.
It is therefore desirable to provide for efficient power management in computer systems and devices utilizing serial link connections.

Device and computer system for power management using serial link connections


A non-volatile memory device and related method of driving data are disclosed. The non-volatile memory device includes an array of multi level cells and a monitoring memory cell. The method of driving including performing a preliminary read operation with respect to a monitoring memory cell using a first read voltage, determining whether data initially stored in the monitoring memory cell is identical with data read from the monitoring memory cell during the preliminary read operation, and setting a main read voltage to a level different from the level of the first read voltage when the data initially stored in the monitoring memory cell is not identical with the data read from the monitoring memory cell in relation to the first read voltage.

1. Field of the Invention
The present invention relates to non-volatile memory devices and methods of driving same. More particularly, the invention relates to a non-volatile memory device that varies the level of a read voltage in response to variations in the distribution of a threshold voltage of a memory cell, as well as related methods of driving the non-volatile memory device.
2. Description of the Related Art
With the development of mobile consumer electronics and a variety of related applications, the demand for flash memory, one common form of non-volatile memory, is increasing. Flash memory is an electrically erasable and programmable non-volatile memory device that is able to retain stored data even when power is interrupted. A given quantity of data may be stored in flash memory using less power than that required to the same quantity of data in other conventional storage media, such as magnetic disc memory (i.e., hard disk drives or HDDs). Flash memory is also able to access stored data faster than HDD based memory systems.
Conventional flash memory is classified into NOR type and NAND type according to logical connection between the constituent memory cells and bit lines. NOR flash memory is formed by connecting at least two cell transistors to each bitline in parallel, and stores data using a channel hot electron method and erases data using a Fowler-Nordheim (F-N) tunneling method. NAND flash memory is formed by serially connecting at least two cell transistors to each bitline, and stores and erases data using an F-N tunneling method. In general, NOR flash memory is less capable of being densely integrated and consumes relatively more current, but also provides a relatively higher operating speed. On the other hand, NAND flash memory may be very densely integrated and consumes relatively less cell current than NOR flash memory.
Various multi level cell (MLC) architectures and related operating methods have been proposed to increase the overall data storage capacity of flash memory. Use of MLC allows a single memory cell to be programmed according to defined threshold voltages such the memory cell is able to store at least two bits of data. In contrast, flash memory using single level memory cells (SLC) store only one bit per memory cell.
FIG. 1A is a graph showing an exemplary threshold voltage distribution for a SLC. Since the SLC stores only one bit of data, the defined threshold voltages need only indicate two data states, [0] and [1]. In order to read the data value stored by memory cell of a SLC type flash memory, a single read voltage may be applied to a wordline associated with the memory cell. The read voltage has a value somewhere between the two threshold voltage distributions and is sufficient to discriminate the stored data value.
FIG. 1B is a graph showing an exemplary threshold voltage distribution for a MLC. More particularly, FIG. 1B illustrates a case where two bits of data are stored in a single memory cell. Since the MLC stores two-bit data, the defined threshold voltages must indicate four data states, [00], [01], [10], and [11]. It follows that in order to read data from a memory cell in a MLC type flash memory, three read voltages are needed.
In a SLC type flash memory, each memory cell may be programmed into one of two states using threshold voltage distributions that ensure a large discrimination (or read) margin between data states. In contrast, the read margins between respective data states for memory cells in a MLC type flash memory are greatly reduced. That is, respective adjacent threshold voltage distributions indicating the different data states are relatively close together.
Generally speaking, the threshold voltage of a flash memory cell varies in accordance with the quantity of electrical charge (i.e., electrons) stored on its floating gate. Unfortunately, electrons stored on a floating gate tend to dissipate or "leak" over time. In extreme cases, charge leakage may actual alter the threshold voltage of a programmed memory cell, thereby changing the stored data value. Due to the reduced read margins noted above, MLC memory systems are particularly susceptible to problems associated with charge leakage. The ability of a particular memory cell to retain charge over time is referred to as its retention characteristic. The retention characteristic of a memory cell is a reliability index of sorts.
FIG. 2 is a graph showing possible changes to the exemplary threshold voltage distributions of FIG. 1B as a result of charge leakage. As stored electrons dissipate from a floating gate with the passage of time, the threshold voltage distributions tend to shift or broaden. At some point, such shifting or broadening of the threshold voltage distributions substantially increase the likelihood of an erroneous data discrimination. For example, if a fixed read voltage, Vread[1], intended to distinguish the data values [10] and [01] is applied to the MLC of FIG. 2, the lower end of the broadened threshold voltage distribution for data [01] may fall below the read voltage Vread[1] due to charge leakage. Memory cells characterized by shifted or broadened threshold voltages are more likely to result in erroneous data interpretations. In conventional flash memory, a fixed read voltage is routinely used to discriminate stored data values even when the distribution of one or more threshold voltages for the memory cell is changed due to charge leakage. This approach is likely to result in errant data reads.

Non-volatile memory device having monitoring memory cell and related method of driving using variable read voltage


A single- or multiple-component composition, which forms upon mixing with water a (meth)acrylic hydrogel and which composition including at least one water soluble at room temperature liquid (meth)acrylic compound supported on a solid carrier and/or an aqueous solution of at least one at room temperature solid or liquid (meth)acrylic compound, a free-radical initiator, and optionally a catalyst for the initiator. A method produces a hydrogel. An acrylic injection material. A method seals cracks, voids, flaws and cavities in building structures.

Swellable polymer materials such as acrylic based hydrogels are commonly used in construction industry as injection materials or sealants. Hydrogels are produced by polymerizing and cross-linking water-soluble monomer and/or prepolymer compounds in water based solutions or by contacting superabsorbent polymers with water. The polymerization mixture typically comprises, in addition to monomer or prepolymer compounds, an initiator for the polymerization reaction and optionally a catalyst. The monomer and prepolymer compounds must be water-soluble in order to achieve the hydrogel upon polymerization. Monomer and prepolymer compounds which are not water-soluble cause separation of the water from the formed polymer material.
The ingredients for producing hydrogels are usually stored and delivered in a form of two-, three- or four-component compositions or kits due to the reactiveness of the ingredients. In a two-component composition, for instance, one of the components contains the monomer/prepolymer compounds and optionally the catalyst, and the other component contains the initiator. In a three-component composition, the monomer/prepolymer compounds, the initiator, and the catalyst are each provided as a separate component.
One of the disadvantages of the above mentioned multi-component compositions is the excess time needed for mixing several components and the risk that at the time of use the proportions of polymerizable material, initiator and catalyst are not measured correctly resulting in deterioration of the physical properties of the hydrogel.

Single - or multiple component composition for producing a hydrogel


A process of co-extrusion of a thin electrode sheet with a thin electrolyte polymer sheet directly onto a current collector sheet for a lithium polymer battery. The process includes the steps of:                (a) mixing a polymer with active electrode material, lithium salt and electronic conductive material in a first mixing chamber to form an electrode slurry;        (b) mixing a polymer with a lithium salt in a second mixing chamber to form an electrolyte slurry;        (c) feeding the electrode slurry through a first flow channel and the electrolyte slurry through a second flow channel;        (d) extruding the electrode slurry in the form of a thin electrode sheet through a first die opening connected to the first flow channel, the electrode slurry being extruded directly onto a current collector sheet; and        (e) concurrently extruding the electrolyte slurry in the form of a thin electrolyte sheet through a second die opening adjacent to the first die opening and connected to the second flow channel, the thin electrolyte sheet being extruded directly onto the thin electrode sheet.

Rechargeable batteries manufactured from laminates of solid polymer electrolytes and sheet-like anodes and cathodes display many advantages over conventional liquid electrolyte batteries. These advantages include lower overall battery weight, high power density, high specific energy, longer service life, as well as being environmentally friendly since the danger of spilling toxic liquid into the environment is eliminated.
Solid lithium polymer battery components include positive electrodes, negative electrodes and an insulating material capable of permitting ionic conductivity, such as a solid electrolyte consisting of a polymer and a lithium salt sandwiched between the positive and negative electrodes. The anodes or negative electrodes are usually made of light-weight metals foils, such as alkali metals and alloys, typically lithium metal, lithium oxide, lithium-aluminum alloys and the like. The composite cathodes or positive electrodes are usually formed of a mixture of active material such as transitional metal oxide, an electrically conductive filler, usually carbon particles, and an ionically conductive polymer electrolyte material, the mixture being set on a current collector, which is usually a thin sheet of aluminum. Since solid polymer electrolytes are less conductive than liquid polymer electrolytes, solid or dry electrochemical cells must be prepared from very thin films (total thickness of approximately 50 to 250 microns) to compensate the lower conductivity with high film contact surfaces and to provide electrochemical cells with high power density.
Composite cathode thin films are usually obtained by solvent coating onto a current collector or by melt extrusion. Similarly, the polymer electrolyte separator layer is typically produced by solvent coating or by melt extrusion.
Solid lithium polymer electrochemical cells are typically manufactured by separately preparing the positive electrode, the electrolyte separator and the negative electrode. The positive electrode is initially coated onto a metallic foil (for example aluminum) or onto a metallized plastic film, which serves as a current collector. The polymer electrolyte is coated onto a plastic substrate, such as a film of polypropylene. The positive electrode is thereafter laminated onto one face of the electrolyte, then the plastic substrate is removed from the second face of the electrolyte and the lithium negative electrode is applied thereon. This manufacturing process which is reasonably efficient for research and development and small scale production of lithium polymer electrochemical cells is inadequate for large scale production. U.S. Pat. No. 5,536,278 to Armand et al. disclosed one such method of assembling the various components of a solid lithium polymer electrochemical cells.
U.S. Pat. No. 5,100,746 to Gauthier disclosed a method of laminating simultaneously a plurality of layers of components of an electrochemical cell that is adapted to speed up the manufacturing process, wherein double-layer solid polymer electrolyte/composite positive electrode sub-assemblies are subsequently associated with the other constituent layers of the electrochemical cell. However, the double-layer solid polymer electrolyte/composite positive electrode sub-assemblies are previously produced by successive lamination of positive electrodes and solid polymer electrolytes.
In order to improve the efficiency of the production process for large scale manufacturing of lithium polymer batteries, there is a need for a faster yet reliable method and apparatus for the production of multiple-layer solid polymer electrolyte/composite positive electrode sub-assemblies for thin film solid lithium polymer electrochemical cells.

Co-extrusion manufacturing process of thin film electrochemical cell for lithium polymer batteries and apparatus therefor


In a spray gun for spraying paint and similar media, there is provided a gun housing and a reservoir tank removably attached to the gun housing for holding the medium to be sprayed. The reservoir tank is configured as a commercially available storage container, for example in the form of a paint can, and is directly attached via an adapter to a projection connected to the gun housing. Thus, commercially available storage containers, differing considerably in their dimensions, can be directly fitted onto the gun housing in a short time and by a reliable method. Viscosity settings and transferring of media to be processed from one container to another are therefore not necessary, and the medium can be matched to the particular working implement and application.

1. Field of the Invention
The present invention relates to a spray gun for spraying paints and similar viscous media that can be propelled pneumatically or electrically, comprising a gun housing for accommodating the propulsion mechanism, the components of the spray gun that effect mixture and/or metering, a handle projecting from the gun housing and a reservoir tank removably attached to the gun housing for holding the medium to be processed, with the possibility of introducing the medium from the reservoir tank into the gun housing of the spray gun via a feed duct that, in a preferred embodiment, is provided with a riser pipe.
2. Description of the Prior Art
Spray guns of this type have been described in numerous different configurations and have also proven their effectiveness in practice. In order to enable a medium to be processed with these spray guns, it is necessary to remove the reservoir tank from the gun housing and to fill it accordingly. This procedure is time-consuming, and also the paint or other medium can easily be spilled. Furthermore, it is often essential to carry out extensive cleaning work when changing the medium to be processed, and this also takes time. However, the principal disadvantage of these spray guns is that the viscosity of the medium put into the reservoir tank has to be adapted to the particular design configurations of the spraying device by means of which the medium is to be sprayed. This requires expert knowledge and skill. Frequently, it is not possible to achieve an optimum working method with spray guns of prior art.


A pipe coupling for coupling together two lengths of pipe comprising first and second collars or flanges secured to the ends of the lengths of pipe and having joining surfaces thereon which abut one another on securing the lengths of pipe together,radially aligned grooves are formed in the joining surfaces for receiving a seal which includes a rigid first seal component and a flexible second seal component bonded to the first seal component,the seal extending partially into both grooves to seal between the joining surfaces of the collars.

A known pipe coupling comprises a clamp arrangement incorporating a clamp which embraces adjacent ends of adjacent pipe lengths. The clamp is tightened onto a seal so that the coupling can withstand the maximum pressure the pipeline is designed to carry.
The clamp arrangement may hold the pipe lengths together by friction in low pressure situations, or may co-operate with a groove or shoulder formed at each end of each pipe length in higher pressure situations.
Such clamp arrangements may be fixed into position by bolting or over centre clamping.
A problem with known clamp arrangements is that it is difficult to ensure accurate alignment of the internal bores of adjacent pipe lengths, primarily due to the resilience of the seal which can allow adjacent pipe lengths to move radially relative to one another, such as may occur as the clamp is being tightened onto the pipe lengths.
A known method of overcoming this problem is to design the pipe lengths to have one male end and one female end. Joins between adjacent pipe lengths are then made between the male end of one pipe length and the female end of another pipe length. This allows adjacent pip ee located accurately relative to one another and leads to alignment of the bores of adjacent pipe lengths.
A disadvantage with this known system, however, is that the pipe lengths can only be fitted into the pipeline in one direction.
It has been proposed, in U.S. Pat. No. 3,836,159, to provide a sealing ring reacting between the ends of adjacent pipe lengths and comprising a resilient, deformable plastics component sandwiched between inner and outer retainer rings of metal such as steel which are resiliently deformable in a direction radially of the pipe lenths.
In such an arrangement, the pressure in the pipeline reacts primarily on the metal components of the seal.


A method is provided for switching over a gas turbine burner operation from liquid fuel to gas fuel and vice-versa, with the burner comprising nozzles for feeding a premixed gas fuel, nozzles for injecting a pilot gas fuel and nozzles for injecting a liquid fuel. According to the method, while the liquid fuel and the premix gas fuel are regulated to switch over from liquid fuel to gas fuel operation or vice-versa, the pilot gas fuel is controlled at a substantially constant flow rate.

With reference to FIG. 1, conical premix burners 1 are known to comprise two (or also more than two) substantially conical walls 2 that define a conical swirl chamber 3.
The conical walls 2 define slots 5 for air entrance and are also provided with nozzles 6 for premix gas fuel injection into the swirl chamber 3 (premix meaning that this burner has a premix operation).
In addition, the burner 1 has a lance 7 having nozzles 8 for pilot gas fuel injection and further nozzles 9 for liquid fuel injection (typically located at the tip of the lance 7).
The walls 2 are connected through a front panel 10 to a combustion chamber 11. In FIG. 1 nozzles 8 are shown at the side of the lance 7, nevertheless in different examples the nozzles 8 for pilot gas fuel can be located at the tip of the lance 7 or at the front panel 10.
Typically pilot gas fuel generates a diffusion flame and the premix gas fuel generates a premix flame, nevertheless in different examples the pilot gas fuel may also generate a flame being a hybrid between diffusion and premix flame.
Two different operations (either with liquid or gas fuel) are possible for this kind of burner.
GAS FUEL OPERATION—During gas fuel operation, the nozzles 6 inject premix gas fuel and the nozzles 8 inject pilot gas fuel; the nozzles 9 do not inject any liquid fuel.
Therefore, compressed air enters through the slots 5 into the swirl chamber 3 and gas fuel is supplied via nozzles 6 and 8; in the swirl chamber 3 air and gas fuel mix forming a mixture that is combusted in the combustion chamber 11 (reference 13 indicates the flame).
LIQUID FUEL OPERATION—During liquid fuel operation, the nozzles 9 inject liquid fuel, whereas the nozzles 6 and 8 do not inject any fuel.
Also in this case compressed air enters through the slots 5 into the swirl chamber 3 and liquid fuel is supplied via nozzles 9; in the swirl chamber 3 air and liquid fuel mix forming a mixture that is combusted in the combustion chamber 11 (reference 13 indicates the flame).
SWITCH OVER—In order to switch from gas fuel operation to liquid fuel operation, traditionally the gas fuel flow rate injected into the swirl chamber 3 via nozzles 6 (premix gas nozzles) and 8 (pilot gas nozzles) is decreased together (i.e. both the premix gas fuel flow rate and pilot gas fuel flow rate are decreased at the same time) and, in addition, the liquid fuel flow rate is increased.
Decrease of gas fuel flow rate and increase of liquid fuel flow rate are carried out with substantially linear functions, from the initial flow rates (100% gas fuel and 0% liquid fuel) to the final flow rate (0% gas fuel and 100% liquid fuel).
Switching over from liquid fuel to gas fuel operation is carried out in the same way, i.e. liquid fuel flow rate is decreased from 100% to 0%, while both premix gas fuel and pilot gas fuel are increased at the same time from 0% to 100%.
Even if largely used, in some cases this switch over method proved to cause unstable gas turbine operation.
In other words, while premix gas fuel and pilot gas fuel decrease and liquid fuel increases, or liquid fuel decreases and premix gas fuel and pilot gas fuel increase the flame stability can be influenced such that large pressure pulsations are generated.
Pressure pulsation are known to be very detrimental for the gas turbine lifetime because they stress not only the burners and combustion chambers wherein they are generated, but also other components such as flue gas discharge systems.
WO2009/068425 discloses a gas turbine able to operate with a gas fuel and a liquid fuel and, in addition, also provided with a pilot gas fuel and a pilot liquid fuel. This documents does not give any suggestion on how a switch over from liquid to gas fuel and vice versa can be carried out.

Method for switching over a gas turbine burner operation from liquid to gas fuel and vice-versa


A cap has a circumferential band with flap pieces formed at the lower end of a cylindrical skirt portion via a weakened portion, and a feature resides in a circumferential curled portion that is formed at the lower end of the circumferential band. When the cap is opened, the flap pieces effectively prevents the circumferential band from entirely escaping.

1. Field of the Invention
The present invention relates to a pilfer-proof synthetic resin cap.
2. Description of the Prior Art
A pilfer-proof synthetic resin cap has heretofore been known to have a top panel, a cylindrical skirt portion hung from the peripheral edge of the top panel, a circumferential band provided at the lower end of the cylindrical skirt portion via a weakened line, and flap pieces provided maintaining a predetermined distance on the inner surface of the circumferential band portion to engage with a jaw portion formed at the mouth of a container, and has been widely put into practical use.
With this cap, the circumferential band portion is secured by the flap pieces to the mouth of the container. When the cap is opened, therefore, the weakened line is broken and the circumferential band portion only remains at the mouth of the container to exhibit a pilfer-proof function.
In the above cap, however, the flap pieces are not strong enough to fully engage the jaw portion formed at the mouth of the container and, besides, the weakened line is frequently not broken even when the cap is open; i.e., the cap is often entirely removed together with the circumferential band.
Furthermore, some gap is formed between the lower end of the circumferential band and the mouth of the container, and mischief is often done using this gap.
Japanese Laid-Open Patent Publication No. 296666/1990 discloses a cap having an upwardly directed flexible tab formed on the circumferential band portion and interference beads formed at the lower end of the circumferential band to inwardly protrude.
In the cap of the above prior art, an increased engaging force is obtained between the circumferential band and the jaw portion formed at the mouth of the container due to the flexible tab and the interference beads that work in cooperation together. Therefore, the cap that is opened is effectively prevented from being entirely removed, and the gap formed between the lower end of the circumferential band and the mouth of the container is filled with the interference beads. According to the above prior art, however, the cap is molded very difficulty since it has two kinds of protrusions, i.e., flexible tab and interference beads on the inside of the circumferential band. That is, the caps of this type are usually produced by such molding means as injection molding using a suitable metal mold. In the case of the above cap, however, is very difficult to remove the, metal mold after the molding operation because of the shape of the circumferential band portion. In fact, the above prior art does not at all describe concerning the molding means.

by Eiko Doi and Kenichi Doi Legal Representatives


An apparatus, method, and system for coupling a host computer to a peripheral device over an extended distance. In one example, a first hub is provided for coupling with the host computer, the first hub configured as a compound device including a hub function and an embedded function, the first hub configured such that the embedded function is a virtual hub thereby providing an additional amount of time for signal transmissions by the first hub. A communications link is provided for coupling the first hub with the peripheral device, the characteristics of the communications link being based in part on the additional amount of time made available by the configuration of the first hub. In this manner, in one example, the length of the communications link may be extended beyond a standard USB cable length to consume the additional amount of time provided by the hub configuration, and transmissions may be made between the host computer and the peripheral device over the communications link in a manner that is within the USB timing specifications.

The universal serial bus (USB) provides a low cost solution for attaching peripheral devices to a host, such as a host computer or host server. Devices that are attached to a USB bus are automatically detected and software automatically configures the devices for immediate use, typically without user intervention. The USB devices/peripherals may include devices such as printers, scanners, keyboards, a mouse, digital cameras, digital video cameras, data acquisition devices, modems, speakers, telephones or video phones, storage devices such as ZIP drives, or other peripherals.
A USB specification entitled "Universal Serial Bus Revision 2.0 Specification" available at www.usb.org, the disclosure of which is hereby incorporated by reference in its entirety, dictates that a USB bus can support 127 devices. Typically, a USB bus may include a host connected by a USB cable to a peripheral/device. By convention, data transmitted in the direction of the peripheral device is said to be in the "downstream" direction, while data transmitted in the direction of the host is said to be in the "upstream" direction.
A USB bus can be extended with a hub which can support and drive additional devices. The total number of devices (hubs and peripherals) that can be supported by a single USB host is 127. A number of hubs may be interconnected in a tiered star topology, where each hub acts as the center of a star to which peripherals are attached for a particular tier level. Due to timing constraints, the maximum number of tiers allowed in a USB bus is seven (including the root tier which has the host).
A hub is a repeater and has a hub controller, an upstream port, and a plurality of downstream ports to which one or more peripherals can be attached. A hub broadcasts data to downstream ports and can also transmit data from a downstream port upstream towards the host. The hub controller, which may include a microcontroller or other programmable logic, controls the hub under operations of software. The hub controller communicates with the host computer, and monitors peripherals or other devices attached to the hub. For instance, a hub controller may report to the host computer connection status regarding the peripheral devices coupled with downstream ports of the hub.
Many USB devices have their own built in cable, socket, or connectors. Per the USB specification, "A" and "B" connectors are utilized, where "A" connectors are for making connections "upstream" towards the computer, while "B" connectors are for making connections "downstream" and connect to individual devices or other hubs. The USB specification effectively places a limit of 5 meters (about 16.5 feet) on the length of a USB cable by regulating the propagation delay from a peripheral to the host computer.
As recognized by the present inventor, it would be beneficial to provide a connection between USB peripherals and a host computer of a distance greater than 5 meters. For instance, various industrial or laboratory applications of computer systems often require that the keyboard, mouse, or disk drive of a host computer be remote. Furthermore, there may be other instances a user wishes to connect a USB device to a USB host at a distance greater that 5 meters.
While a system of five interconnected hubs could be provided in order to increase the distance between the peripheral and the host to 25 meters (approximately 82.5 feet), such a system would be disadvantageous because at least two of the five hubs would be required to have their own power source, which may not always be available in the particular environment where the 25 meters of cable and hubs are to be used (for example, in a conduits or trunking embedded in walls, ceilings, or floors). One example of such a system is illustrated in FIG. 1, wherein a host 10 is coupled with a USB device/peripheral 12 through two 5 meter cables 14 and a hub 16. Further, many applications require that a USB system be provided such that an additional hub can be connected to the USB bus, which would require that four hubs be connected at 5 meters each, totaling 20 meters or 66 feet.
Accordingly, as recognized by the present inventor, what is needed is a system, method, and apparatus for connecting USB devices/peripherals at extended distances from a host computer, while preferably not violating any propagation times set forth by the USB standards.
It is against this background that various embodiments of the present invention were developed.

System, method, and apparatus for connecting USB peripherals at extended distances from a host computer


A word line boost circuit includes a first pump circuit, a first transistor, a voltage detection circuit and a second pump circuit. The first pump circuit provides a gate boosted signal according to an address transfer detection (ATD) signal. The first transistor has a control terminal for receiving the gate boosted signal and a second terminal coupled to a target word line. The voltage detection circuit is for detecting a voltage level of the gate boosted signal and accordingly outputting a detection signal. The second pump circuit is for outputting a boost signal to a first terminal of the first transistor according to a voltage level of the detection signal. The boost signal boosts the target word line via the turned-on first transistor.

1. Field of the Invention
The invention relates in general to a word line boost circuit and method, and more particularly to a word line boost circuit and method capable of improving a reading speed.
2. Description of the Related Art
Referring to FIG. 1, a circuit diagram of a conventional word line boost circuit is shown. A word line boost circuit 100 includes a first pump circuit 110, a first transistor M1, a second transistor M2, a zener diode 120, a first switch Q1, and a second pump circuit 130. The first pump circuit 110 receives an address transfer detection (ATD) signal and outputs a gate boosted signal AVXVF. The first pump circuit 110 substantially includes three stages of sub-pump circuits for sequentially increasing a voltage level of the gate boosted signal AVXVF. The first transistor M1 has a control terminal for receiving the gate boosted signal AVXVF and a second terminal coupled to a target word line TWL.
The second transistor M2 has a first terminal coupled to the control terminal of the first transistor M1. A control terminal of the second transistor M2 is coupled to the first terminal of the second transistor M2. The zener diode 120 has a first end coupled to a second terminal of the second transistor M2. The first switch Q1 has a control terminal for receiving the ATD signal ATD, a first terminal coupled to a second end of the zener transistor 120, and a second terminal for receiving a ground voltage GND. The second pump circuit 130 receives a trigger signal ATDBOOST and accordingly outputs a boost signal AVXBST to boost the target word line TWL.
The word line boost circuit 100 achieves the purpose of boosting the target word line TWL by timing control. Referring to FIG. 2, a timing diagram of the word line boost circuit 100 is shown. In the word line boost circuit 100, when the voltage level of the gate boosted signal AVXVF is equal to a predetermined voltage, due to the component characteristic of the zener diode 120, the voltage level of the gate boosted signal AVXVF can be stably maintained to the predetermined voltage. The predetermined voltage is a sum of a threshold voltage of the second transistor M2 and a voltage drop across the zener diode 120. Therefore, the time (t2-t1) for the voltage level of the ATD signal ATD to be kept at a high level H should be long enough such that the voltage level of the gate boosted signal AVXVF can be successfully lifted up to the predetermined voltage by the first pump circuit 110.
After the time t2, that is, after the voltage level of the gate boosted signal AVXVF has been the predetermined voltage, the voltage level of the trigger signal ATDBOOST is transferred to the high level H and the second pump circuit 130 is triggered to lift up the boost signal AVXBST to boost the target word line TWL. However, the conventional word line boost circuit 100 can increase the voltage level of the trigger signal ATDBOOST to the high level H only after the time t2, which wastes much time.


Adjusting a gloss for a print image by adjusting the cooling of the print image. Further, a toner for a printing press adjusting gloss by adjusting cooling includes 1% to 30% aliphatic hydrocarbons, aliphatic acids, aliphatic alcohols or their salts, or olefinic hydrocarbons.

In industrial printing technology, the requirements relating to the quality of the print image are growing. An important quality characteristic of a print is its gloss. The gloss arises if light falling on the surface of a print is reflected in a more or less directed manner, into the eye of the observer. To distinguish between surfaces with matt, medium, and high gloss, it is usually sufficient to measure the directed reflection with a reflectometer. Besides the use of certain inks and toner to attain a certain gloss, the prior art also proposes changing the speed and temperature of fusing rollers. Here, the speed and the temperature at which the fusing of the toner of the print image on print material is performed, and the attachment or union of the toner with the print material, are varied. A disadvantage of this process is that the speed of the print material in the printing press changes with the speed of the fusing rollers applied to it. This significantly complicates the control of the printing press and its construction.


An apparatus and system for loading items onto a rack is described. The rack loading apparatus is includes a stuffer/clipper for making sausages, a belt conveyor for receiving a sausage from the stuffer/clipper and conveying the sausage to a rotary conveyor, the rotary conveyor comprising a plurality of stages and having a loading side for receiving a sausage and an unloading side for discharging a sausage, a rack comprising a frame supporting a plurality of trays, a positioner to align the rack with the unloading side, a controller to cause the rotary conveyor to align a one of the plurality of stages on the loading side with the belt conveyor to receive a sausage from the stuffer/clipper and to rotate the rotary conveyor to align the one of the plurality of stages on the unloading side with a one of the plurality of trays, and a load pusher to discharge the sausage off the one of the plurality of stages and onto the one of the plurality of trays, the pusher comprising a plurality of tabs extending on a rotatable arm. In another embodiment, a rack loading apparatus for loading other manufactured items is described.

This invention relates generally to the field of loading material onto racks. Specifically, this invention relates to loading sausages, whole-muscle meats such as hams, or other items onto racks for further processing, such as smoking or cooking. The invention will be described as used for sausages, but can be used for any items that are loaded onto a rack.
Sausages are made by filling a casing with a pasty product in a tubular shape. The pasty product is usually a mixture of minced meat and seasonings, but can also be completely or partially made of vegetarian products. The pasty product is conveyed to a filler which pumps the pasty product through a product horn and into a casing. The casing, sometimes made of an edible material such as collagen, can be made in a tubular shape or can be formed into tubes from flat sheets. As the pasty product fills the tubular casing at the end of the product horn, the sausage forms and pushes the tubular casing off the product horn. (Often, the tubular casing is itself wrapped in netting, during the same process.) When the sausage gets to the appropriate length, separators of a double clipper, such as iris gates, clamp the extruded product, apply two clips, and sever in between the two clips. One clip becomes the end of the completed sausage and the other clip becomes the beginning of the next sausage. (A stuffer can be a separate apparatus from the clipper, or both can be pati of the same machine.) The sausage is then processed by smoking, cooking, steaming, or other finishing operation. The netting is usually left on the sausage during the finishing operation and may or may not be removed prior to sale to the consumer.
Illustrative processes and devices for making sausages are described in U.S. Pat. No. 5,024,041 to Urban, Process for Filling Tubular Casings and United States Published Patent Application No. 2005/0087075 A1 to Mysker, Apparatus and Method to Net Food Products in Shirred Tubular Casing, the disclosures of both of which are incorporated herein by reference.
As the sausages are produced by, for example, an apparatus as described in the '041 patent or the '075 publication, they are extruded onto a table or onto a conveyor belt. Workers are employed to lift the sausages off the table and place the sausages. on a tray of a rack. A rack is a framed device, with numerous trays attached to the frame. Racks are usually about six feet in height, to be able to fit into a standard smokehouse, but can vary between different sausage manufacturer's facilities. Racks are usually on wheels and are pushed on a floor from the sausage-making machine to the smokehouse. Some racks are suspended from overhead rails. Once a worker has filled up every tray of a rack with newly-made sausages, the rack is moved into a smokehouse for finishing.
Problems arise in this method of manufacture of sausages. Sausages are raw when initially made and not particularly stiff at that time. Accordingly, it is difficult for a worker to keep a sausage completely straight, as a worker who supports a, for example, three-foot-long sausage with two hands will often find the sausage bending or sagging in the middle. Bending and sagging create unsightly blemishes in the collagen casing, displeasing to consumers. Additionally, the manual nature of the operation means some percentage of sausages will be dropped and therefore ruined. The manual nature of the operation also requires quite a bit of stooping and stretching by a worker, as the lowest tray of a rack is just inches off the floor and the highest level is often six feet off the floor.
Automated methods of accomplishing loading of sausages onto a rack are complicated by the orientation of the various parts of a sausage-making system. The discharge of a stuffer/clipper is conventionally about three-feet off the floor and is fixed in height. The trays of a rack range from the lowest rack, just inches off the floor, to the highest rack, often six feet off the floor. Accordingly, sausages extruded from the stuffer/clipper have to be lowered, lifted, or moved horizontally, depending on what tray is being filled. Additionally, even within a single sausage-making facility, the sizes and types of racks vary.
Accordingly, a need exists for an automated apparatus and method to load freshly-made sausages directly onto a rack than can be then moved for further processing. A need also exists for an automated rack loader that can be universally used with different sizes and shapes of racks. The present invention meets these needs.