A subset of quality metrics as input to a disk drive failure prediction algorithm (DFPA) may be selected using a genetic algorithm. The DFPA is executed for an initially selected generation of subset quality metrics using quality metric values stored in a reference data base. At least one DFPA setting is adjusted and the DFPA executed again for the selected subset. After training the DFPA, the best DFPA setting is saved for the selected subset. A fitness score is generated for the selected subset, representing an accuracy of the DFPA relative to failure indicators stored in the reference data base. At least one genetic operator is applied in response to the fitness scores to generate a new generation of subsets. The process is repeated until a best subset of quality metrics and corresponding DFPA setting are found.

1. Field of the Invention
The present invention relates to disk drives for computer systems. More particularly, the present invention relates to using a genetic algorithm to select a subset of quality metrics as input to a disk drive failure prediction algorithm.
2. Description of the Prior Art
Disk drive failure prediction is used primarily to detect marginal disk drives that are progressing toward catastrophic failure while in-the-field so that a warning can be issued to backup the disk drive and/or return the disk drive to the manufacture for repair. Another suggested application for drive failure prediction is to screen out marginal disk drives from the manufacturing line to avoid the expensive (time consuming) final testing stage. The performance of the drive failure prediction algorithm depends on the ability to correctly identifying marginal disk drives while minimizing the number of good disk drives falsely detected as marginal disk drives (false alarms). In the case of field failures minimizing false alarms reduces the cost associated with returning a good disk drive to the manufacture for repairs, and in the case of manufacturing failures minimizing false alarms improves yield.
A well known drive failure prediction system for detecting marginal disk drives while in-the-field is the Self Monitoring and Reporting Technology (SMART). The SMART system implemented internal to each disk drive monitors a number of quality metrics (e.g., head fly height, retries, servo errors, etc.) indicative of impending failure. If any one of the quality metrics exceeds a predetermined threshold (OR operation), a failure warning is issued. However, issuing a failure warning if any one of the quality metrics exceeds a threshold provides sub-optimal prediction performance since it does not take into account the correlations of the quality metrics. For example, if the head fly-height falls below a predetermined threshold indicating a potential failure but the other quality metrics do not confirm the failure, a false failure warning may be issued and the disk drive returned unnecessarily to the manufacture for repairs.
Various prior art references have suggested ways for improving drive failure prediction by combining the quality metrics into a composite score that provides a better indication of impending failure. For example, an article by G. F. Hughes, J. F. Murray, K. Kreutz-Delgado, and C. Elkan entitled "Improved Disk Drive Failure Warnings", IEEE Transactions on Reliability, September 2002, suggests to evaluate each quality metric statistically using a rank sum test, and to combine the rank sums generated for each quality metric into a composite score representing an overall quality of the disk drive. U.S. Pat. No. 5,737,519 suggests to evaluate the quality metrics using a pattern recognition system together with a fuzzy inferencing system in order to detect patterns of quality metrics that are indicative of failure as opposed to evaluating each quality metric independently. U.S. Pat. No. 6,574,754 suggests evaluate the quality metrics using a neural network to generate a composite score and to adapt the neural network using data obtained from field experience.
Although the above references suggest different techniques for improving the drive failure prediction algorithm by evaluating the quality metrics in context rather than independently, the references do not adequately address the need to first identify the quality metrics that are the best indicators of impending failure. For example, the SMART ATA specification generates up to 30 different quality metrics but only a small subset of these quality metrics may be good failure predictors, and the subset of good failure predictors may change with each new generation of disk drives. Identifying the subset of quality metrics that are indicative of impending failure improves the performance and simplifies the implementation of the drive failure prediction algorithm.
There is, therefore, a need for a reliable method of identify a subset of quality metrics for input into a drive failure prediction algorithm.

Using a genetic algorithm to select a subset of quality metrics as input to a disk drive failure prediction algorithm


A gas turbine engine having a turbine rotor assembly with a free standing sideplate assembly is disclosed. Various construction details are developed which provide a sideplate assembly which is not radially or axially supported by the web or rim of the adjacent disk. In one particular embodiment, a rotor assembly includes a rotor disk, having a rim, a web, and a bore, and a sideplate assembly, having a web and a bore. The web of the sideplate is radially supported by the bore of the sideplate and includes a disk seal and an aperture. The disk seal is engaged with the rotor disk and has an axially directed seal force provided by an axially interfering fit between the sideplate and rotor disk. The aperture provides fluid communication between a source of cooling fluid and the rotor disk.

A typical gas turbine engine has an annular axially extending flow path for conducting working fluid sequentially through a compressor section, a combustion section, and a turbine section. The compressor section includes a plurality of rotating blades which add energy to the working fluid. The working fluid exits the compressor section and enters the combustion section. Fuel is mixed with the compressed working fluid and the mixture is combusted to thereby add more energy to the working fluid. The resulting products of combustion are then expanded through the turbine section. The turbine section includes a plurality of rotating blades which extract energy from the expanding fluid. A portion of this extracted energy is transferred back to the compressor section via a rotor shaft interconnecting the compressor section and turbine section. The remainder of the energy extracted may be used for other functions.
The rotor assembly of the gas turbine engine includes a rotating disk to which the rotor blades are attached. In addition to the rotor blades, the disk may provide support for other rotating structure such as seal runners and sideplates. The size and weight of the disk is dependant upon the loads required to be supported by the disk. The rotational forces inherent to the rotating disk magnify the loads many times. The size and weight of the rotor assembly directly affects the output of the gas turbine engine, with additional weight or inertia lowering the operating efficiency of the gas turbine engine.
Much research and development has gone into reducing the loads on turbine disks to thereby minimize the size of the turbine disk. Turbine structural components have been designed to be lighter by using higher strength and lower density materials. In addition, the rotor assembly and associated components have been configured to reduce the size at the turbine disks.
Sideplate assemblies have also been a source of research and development. A typical sideplate assembly performs several functions. An example is disclosed in U.S. Pat. No. 4,701,105, issued to Cantor et al and entitled "Anti-Rotation Feature for a Turbine Rotor Faceplate". First, the sideplate shields the disk from direct contact with hot working fluid. Second, the sideplate provides passages for a flow of cooling fluid along the forward face of the disk and into the rotor blade. The sideplate functions to protect the disk directly, and the rotor blade indirectly, from the adverse effects of heat transferred from the hot working fluid. The sideplate assembly, however, adds to the loading of the disk and therefore requires the disk to be larger to support the sideplate assembly.
The above art notwithstanding, scientists and engineers under the direction of Applicants' Assignee are working to develop lightweight turbine rotor assemblies to maximize the operating efficiency of gas turbine engines.

Free standing turbine disk sideplate assembly


In the process of the present invention, xylylenediamine and/or cyanobenzylamine is produced by a catalytic liquid-phase hydrogenation of a phthalonitrile compound. The liquid-phase hydrogenation is performed by controlling the concentration of a benzamide compound to a specific level or lower. In a preferred embodiment, the concentration of a benzoic acid compound is further controlled to a specific level or lower. By the process, xylylenediamine and/or cyanobenzylamine is produced at high yields and the catalyst life is prolonged.

1. Field of the Invention
The present invention relates to a process for producing a xylylenediamine and/or a cyanobenzylamine by hydrogenation of a phthalonitrile compound (dicyanobenzene compound). The xylylenediamine is useful as a raw material for polyamide resins, curing agents, etc., as well as an intermediate material for isocyanate resins, etc. The cyanobenzylamine is useful as a raw material and an intermediate material for medicines, agricultural chemicals, polymer additives and other organic compounds.
2. Description of the Prior Art
It is well known in the art to produce the xylylenediamine by hydrogenating the phthalonitrile compound in a liquid phase in the presence of a catalyst.
For example, Japanese Patent Publication No. 38-8719 discloses a batch-wise hydrogenation of the phthalonitrile compound in an autoclave. The proposed hydrogenation is conducted in an alcoholic solvent in the presence of a very small amount of a caustic alkali agent as well as Raney nickel or Raney cobalt to produce the corresponding diamine. Japanese Patent Application Laid-Open No. 54-41804 discloses another batch-wise hydrogenation of the phthalonitrile compound in an autoclave. The proposed hydrogenation is conducted in a mixed solvent of a lower alcohol and a cyclic hydrocarbon in the presence of a hydroxide or an alcoholate of alkali metal or alkali earth metal, and a Raney nickel or Raney cobalt-containing catalyst to produce the corresponding diamine. Japanese Patent Application Laid-Open No. 6-121929 discloses a batch-wise hydrogenation of isophthalonitrile in an autoclave. The proposed hydrogenation is conducted in a mixed solvent of methanol and ammonia in the presence of a Rh/Co-containing catalyst to produce the corresponding diamine. Japanese Patent Publication No. 53-20969 discloses a catalytic reduction of the phthalonitrile compound with hydrogen in a liquid phase in the presence of a Ni/Cu/Mo-containing catalyst, for example, by a fixed bed continuous hydrogenation. "PROCESS HANDBOOK (1978)" edited by Japan Petroleum Society discloses an industrial process for the production of xylylenediamine in which a raw nitrile is introduced into a hydrogenation reactor together with a solvent and a catalyst to subject the nitrile to hydrogenation reaction under a slurried condition. Japanese Patent Application Laid-Open No. 2002-105035 discloses a process for producing xylylenediamine in which the phthalonitrile compound obtained by ammoxidation of xylene is absorbed into an organic solvent by contacting, and liquid ammonia is added to the resultant solution to hydrogenate the phthalonitrile compound without separating the phthalonitrile compound.
The production of cyanobenzylamine by hydrogenating the phthalonitrile compound in a liquid phase in the presence of a catalyst is disclosed in Japanese Patent Application Laid-Open Nos. 49-85041, 6-507909, 9-40630 and 10-204048, etc.
The phthalonitrile compound used as a starting material for xylylenediamine or cyanobenzylamine is produced by various methods such as the ammoxidation of an alkylated benzene such as xylene, the reaction between a dichlorobenzene and hydrogen cyanide, and the reaction between a phthalic acid compound and ammonia. Of these methods, the ammoxidation of the alkylated benzene is industrially preferred. The ammoxidation of xylene is performed by known methods in the presence of known catalysts as disclosed in Japanese Patent Publication No. 49-45860, Japanese Patent Application Laid-open Nos. 49-13141, 63-190646, 5-170724, 1-275551 and 9-71561, etc.

Process for production of xylylenediamine and/or cyanobenzylamine


It is an object to obtain a self-synchronization type block processing apparatus which does not need to optimize a clock path to be distributed to each block in a clock phase management at an upper level, and can suppress an increase in a circuit scale and can minimize an increase in a design period by circuit tuning. A local block control circuit comprises an end detecting section for receiving a plurality of complete signals, a transfer control section for generating a stop signal having a negative logic to determine whether or not a system clock is supplied to a processing block upon receipt of an end signal output from the end detecting section, the system clock and a handshaking control signal, and a logical AND gate for generating an in-block clock based on the stop signal having the negative logic which is output from the transfer control section and the system clock.

1. Field of the Invention
The present invention relates to a data processing system, and more particularly to a data processing system for dividing an inner part into a plurality of processing blocks and controlling the processing blocks self-synchronously.
2. Description of the Background Art
A data processing system basically carries out control synchronously with a single system clock. In an apparatus for dividing the data processing system into a plurality of processing blocks to execute a whole processing, it is necessary to control a clock skew to have a specific reference value or less for a clock to be a synchronizing signal in the processing blocks and between the processing blocks.
In recent years, a physical control area has been enlarged with an increase in an operation speed and a scale of a system so that the reference value for the clock skew has been decreased. Thus, a situation has become increasingly tense and the clock skew having the reference value or less has been hard to implement.
Therefore, various methods for implementing the clock skew having the reference value or less have been described in Brian Curran et al., ISSCC 2001 Proceeding 15.5 "A1.1 GHz First 64 b Generation Z900 Microprocessor" p. 238-239, 454 (which will be hereinafter referred to as Document 1), Hidehiro TAKATA et al., IEICE on Electronics "Physical Design Methodology for On-Chip 64-Mb DRAM MPEG-2 Encoding with a Multimedia Processor) VOL. E85-C No. 2 February 2002 p. 368-374 (which will be hereinafter referred to as Document 2), Kouichi Yamaguchi et al., ISSCC 2001 Proceeding 25.4 "2.5 GHz 4-phase Clock Generator with Scalable and No Feedback Loop Architecture" p. 398-399, 326-327 (which will be hereinafter referred to as Document 3), and Thucydides Xanthopoulos et al., ISSCC 2001 Proceeding 25.6 "The Design and Analysis of the Clock Distribution Network for a 1.2 GHz Alpha Microprocessor" p. 402-403, 330-331 (which will be hereinafter referred to as Document 4).
More specifically, the Document 1 has described a method of employing a tree structure having an equal-length wiring for a clock line to be supplied to each processing block and carrying out a management for causing delay values sent from a clock generating source to each processing block to be equal to each other.
Moreover, the Document 2 has described a method of hierarchically carrying out a management based on a clock management on a block level in which a clock management area is restricted to a local area and a clock management between these blocks and adjusting a delay value by a delay adjusting circuit provided in a clock generating source in the clock management between the blocks.
The Documents 3 and 4 have described a method using a DLL (Delay Locked Loop) circuit for adjusting a clock phase between blocks in a method of hierarchically carrying out a clock management on a block level between blocks.
In these methods, the clock management is carried out in a two-stage hierarchy including an in-block (lower level) management and an interblock (an upper level) management in which an area is restricted, and "a tree structure having an equal-length wiring", "a delay value adjustment to be carried out by a delay adjusting circuit", "a clock phase adjustment to be carried out by a DLL" and the like are given to a clock management having an upper level which is harder to perform.
In the case in which supply of a clock or a power is to be stopped in order to reduce power consumption for a specific processing block, moreover, a control signal to satisfy supply stop conditions for the clock or the power is generated and the supply of the clock or the power is turned ON/OFF in response to the control signal.
As described above, in the apparatus for controlling a system synchronously with a single clock, a method of hierarchically managing a clock skew at a lower level on a block unit and an upper level between blocks has conventionally been used for a method of setting a clock skew to have a predetermined reference value or less.
While a management of a phase difference in a clock at a lower level can be implemented comparatively easily by reducing an area, a management of a phase difference in a clock at an upper level is harder to perform because an area to be managed covers a wide range. For this reason, there have been employed the techniques such as "a tree structure having an equal-length wiring", "a delay value adjustment to be carried out by a delay adjusting circuit", "a clock phase adjustment to be carried out by a DLL" and the like.
These techniques are to optimize a clock path to be distributed to each block and a great deal of labor is required for a design, a verification and an analysis.
Referring to "a delay value adjustment to be carried out by a delay adjusting circuit" and "a clock phase adjustment to be carried out by a DLL", furthermore, a delay adjusting circuit, a DLL and the like are required. Consequently, scales of the circuits are increased, and furthermore, these circuits are to be tuned up. Thus, a design period is increased.
In the case in which the supply of the clock or the power is to be stopped in order to reduce the power consumption for a specific processing block, moreover, it is necessary to generate a control signal to satisfy the supply stop conditions of the clock or the power.

Data processing system with block control circuits using self-synchronization handshaking and local clock/power control based on detected completion within subblocks


A bushing base plate comprised of a bushing base raw plate containing a circular or irregular aperture having inner surfaces and inner diameters; and a hollow tube having outer surfaces and out diameters which is inserted into the aperture and bonded thereto by thermal diffusion. Prior to insertion of the tube in the aperture, the outer diameters are greater than the inner diameters, thereby producing a pressing force between the outer surfaces of the tube and the inner surfaces of the aperture.

This invention relates to a bushing base plate having a box filled with melted glass or a nozzle aperture of a bushing employed for preparing glass fibers or continuous glass filaments.
Several plates are currently employed as a bushing base plate. Generally, the bush base plate is prepared by conducting a perforation treatment of a bashing base raw plate and inserting a hollow tube processed in advance to the shape of a pipe into the aperture of the raw plate and bonded by means of welding. Another bushing base plate which is prepared by compressing raw material having a plate thickness thicker than that of a final product by means of rolling or pressing to extrude a projection, and thereafter conducting a perforation treatment to the extruded projection by means of pressing is also employed.
A glass fiber of thin denier and an effective production thereof by making many holes in a certain area with smaller pitches are demanded and a bushing base plate satisfying these requirements is highly requested.
When conventionally welding is conducted by making an aperture through the bushing base raw plate and inserting the hollow tube processed in advance to the shape of a pipe into the aperture of the raw plate, the bushing base raw plate 1 and the hollow tube 3 having a flow-out aperture 2 are as shown in FIG. 1 are welded at the base end of the hollow tube 3 by means of razor or plasma or resistive welding.
In this case, the hollow tube 3 in the shape of a pipe is finished so as to have a thin wall due to the spinning conditions of glass fibers. When the hollow tube is welded to the position perforated through the bushing base raw plate 1, the welding is performed at the base end 3a of the hollow tube 3 that is the flow-in side of the glass as shown in FIG. 1.
Since the wall thickness of the hollow tube 3 is thinner than the thickness of the bushing base raw plate 1, the size of the flow-out aperture is small and the pitch between two adjacent flow-out apertures is small so that the whole thickness of the bushing base raw plate 1 is difficult to be welded, only an upper portion of the raw plate 1 is welded as shown in FIG. 1. Because of this partial welding, the flow-out aperture is difficult to be processed to the shape which fits the flow conditions of glass or the spinning conditions.
When the thus manufactured bushing case plate 4 is employed successively for a long period of time at a high temperature, a creep strain is produced in the bushing base plate 4 receiving a pressure P of glass to be entirely deformed so as to have a swelling as shown in FIG. 2.
FIG. 3 is an enlarged view showing the above fitting portion of the hollow tube 3. Due to the creep deformation of the bushing base raw plate 1, a space is formed between the raw plate 1 and the hollow tube 3 to produce a crack at the above welded portion so that a drawback of enabling the glass fiber spinning because of the leakage of glass liquid. In the worst case, the hollow tube 3 may fall off.
This drawback is critical because even when only one of the flow-out apertures is cracked or falls off, an expensive Pt alloy bushing can be no longer employed so as to stop the production or the bushing with the defect may largely influence the quality and the cost of the glass fibers. It is a problem to be solved how to provide a bushing in which cracking and the falling off are difficult to occur.
A new process of preparing a bushing is proposed in Japanese laid open gazette No. 4-241105 or the like. This contemplates to perform the bonding employed Pt waxy material to the Pt alloy base plate. When a small amount of an element is added to Pt in case of a Pt--Au alloy or a reinforced alloy, that is, when the material possesses a melting point which is the same as or smaller than that of Pt as waxy material, it is supposed to be difficult to melt the Pt by employing Pt as the waxy material.

Bushing base plate and process of preparing same

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The invention relates to a substantially pure polypeptide functioning as an ASIC1a channel blocker. Also provided is a nucleic acid molecule coding such polypeptide, pharmaceutical composition containing such polypeptide and a method of manufacturing an ASIC1a channel blocker.

Proton-gated Na+-permeable channels are the simplest form of ligand-gated channels. They are present in many neuronal cell types throughout the central nervous system, suggesting an important function of these channels in signal transduction associated with local pH variations during normal neuronal activity. These channels might also play an important role in pathological situations such as brain ischemia or epilepsy which produce significant extracellular acidification. They are also present in nociceptive neurons and are thought to be responsible for the sensation of pain that accompanies tissue acidosis in muscle and cardiac ischemia, corneal injury, and in inflammation and local infection.
It is only very recently that the first proton-gated channel, ASIC (for Acid Sensitive Ion Channel) was cloned (Waldmann, R., Champigny, G., Bassilana, F., Heurteaux, C. and Lazdunski, M. "A Proton-Gated Cation Channel Involved in Acid-Sensing", Nature, 386, 173–177, 1997.) The ASICs belong to a superfamily which includes amiloride-sensitive epithelial Na+ channels (ENaCs), the FMRFamide-gated Na+ channel (FaNaC) and the nematode degenerins (DEGs), which probably correspond to mechano-sensitive Na+-permeable channels. Several ASIC subunits have now been described: ASIC1a (Waldmann, R., above) and ASIC1b (Chen, C. C., England, S., Akopian, A. N. and Wood, J. N., "a Sensory Neuron-Specific, Proton-Gated Ion Channel", Proc. Natl. Acad. Sci. USA, 95, 10240–10245, 1998), ASIC2a (Price, M. P., Snyder, P. M. and Welsh, M. J., "Cloning and Expression of a Novel Human Brain Na+ Channel", J. Biol. Chem., 271, 7879–7882, 1996) and ASIC2b (Lingueglia, E., de Weille, J. R., Bassilana, F., Heurteaux, C., Sakai, H., Waldmann, R. and Lazdunski, M., "a Modulatory Subunit of Acid Sensing Ion Channels in Brain and Dorsal Root Ganglion Cells", J. Biol. Chem., 272, 29778–29783, 1997), ASIC3 (Waldmann, R., Bassilana, F., de Weille, J., Champigny, G., Heurteaux, C. and Lazdunski, M., "Molecular Cloning of a Non-Inactivating Proton-Gated Na+ Channel Specific for Sensory Neurons", J. Biol. Chem., 272, 20975–209758, 1997). The different subunits produce channels with different kinetics, external pH sensitivities and tissue distribution. They can form functional homomultimers as well as heteromultimers.
ASIC1a and ASIC1b both mediate rapidly inactivating currents following rapid and modest acidification of the external pH. However, while ASIC1a is present in both brain and afferent sensory neurons, its splice variant ASIC1b, is found only in sensory neurons. ASIC2a forms an active H+-gated channel and is abundant in the brain, but essentially absent in sensory neurons while its splice variant ASIC2b is present in both brain and sensory neurons and is inactive as an homomultimer. ASIC2b can form functional heteromultimers with other ASIC subunits and particularly ASIC3. ASIC3 is found exclusively in small sensory neurons which act as nociceptors. Its expression in various heteromultimeric systems generates a biphasic current with a fast inactivating phase followed by a sustained component. The association of ASIC2b with ASIC3 forms an heteromultimer with properties (time course and ionic selectivity) similar to those of a native sustained H+-sensitive channel which is present in dorsal root ganglion cells and appears to play a particularly important role in pain sensation.
Venoms from snakes, scorpions, sea anemones, marine snails and spiders are rich sources of peptide toxins which have proven of great value in the functional exploration of voltage-sensitive and ligand-gated ion channels (Hucho, F. (1995), "Toxins as tools in neurochemistry", Ang. Chem. Int. Ed. Eng., 34, 39–50). Nevertheless, there is a continuing need to find new materials which affect these channels.

Polypeptide inhibiting a proton-gated Na+ channel, a nucleic acid coding for such polypeptide and a method of manufacturing an ASIC1a channel blocker

Centre National de la Recherche Scientifique - CNRS


Disclosed is a titanium-containing ceramic paint, including 100 parts by weight of silica sol, 50 to 100 parts by weight of organic silane, 0.3 to 1 parts by weight of a catalyst, 5 to 20 parts by weight of titanium powder, and 1 to 5 parts by weight of a silicone oil. The organic silane can be methyltrimethoxy silane and/or methyltriethoxy silane. The catalyst can be formic acid, acetic acid, hydrochloric acid, citric acid, methyl formate, ethyl acetoacetate, maleic anhydride, or combinations thereof. The titanium-containing ceramic paint may further include 30 to 50 parts by weight of filler, such as silica, alumina, zirconium dioxide, silicon carbide, aluminum nitride, boron nitride, kaolin, talcum powder, mica powder, silicate of aluminum or zirconium, barium sulfate, metal fiber, stainless powder, or combinations thereof. The titanium-containing ceramic paint may further include 30 to 40 parts by weight of a color powder.

1. Technique Field
The disclosure relates to a ceramic paint and a coating utilizing the same, and in particular, relates to a titanium-containing ceramic paint and a protective coating.
2. Description of the Related Art
Ceramic paints are novel aqueous inorganic paints, which are primarily composed of a nano inorganic compound dispersed in water. A ceramic paint is usually coated and then cured with a low temperature to form a coating film. Similar to the characteristics of ceramic, the coating film has several advantages such as high temperature resistance, high hardness, non-smoke flame retardation, super climate resistance, and being environmentally friendly, non-toxic, colorful, and easy to coat on a substrate.
In recent years, ceramic paints have been applied to cooking tools due to its safety. The conventional coating agent for non-stick cooking tools is polytetrafluoroethylene (PTFE). Although PTFE has an excellent non-stick property for a long period, the PTFE film is too soft to resist abrasion under high temperatures, as it tends to soften. Compared to conventional PTFE, ceramic paint has advantages such as being environmental friendly, difficulty to peel, and difficulty to decompose at high temperatures. In CN 101190851A, a non-stick purple sand ceramic paint for cooking tools is disclosed. The paint can be applied to form a dense ceramic on a surface of metal or alloy, thereby enhancing the surface hardness and abrasion resistance of the cooking tools. In addition, the dense ceramic has an excellent non-stick property. In CN 102653660A, a ceramic paint with an abrasion resistance for non-stick cooking tools is disclosed, wherein the ceramic paint is primarily composed of silica sol, alumina sol, zirconia sol, and organic silane. The metal oxide sol and polysiloxane are reacted through condensation polymerization, thereby enhancing the adhesive strength of the coating film. However, the coating film is formed by complex steps, and the ceramic paint has many components.
Accordingly, a ceramic paint with better properties (especially the abrasion resistance) for cooking tools is called-for.

Titanium-containing ceramic paint and protective coating


A drum separator for separating brine shrimp eggs from a slurry containing an agglomeration of adult brine shrimp, brine shrimp eggs and debris includes a fluid source to maintain a slurry. The fluid source may be an internal spray jet disposed to spray against the slurry inside the drum for breaking up the agglomeration of adult brine shrimp, brine shrimp eggs and debris so that the brine shrimp eggs may pass through openings formed in the drum. An external spray jet is disposed to spray against the exterior surface of the drum for cleaning the adult brine shrimp and debris out of the openings in the drum. The internal spray jet is preferably an elongated pipe having a plurality of openings and is disposed inside the rotating drum. The external spray jet is preferably an elongated pipe with a plurality of openings and is disposed along the exterior of the rotating drum.

1. Field of the Invention
The present invention relates to an apparatus and method for separating brine shrimp eggs (artemia cysts) from a slurry containing an agglomeration of adult brine shrimp (artemia), artemia cysts, and debris. More particularly, the present invention relates to introducing the slurry into a rotating drum having openings to allow the cysts to pass through, providing a liquid source to maintain the slurry, and disposing a spray nozzle to spray against the outside surface of the drum to clean the adult brine shrimp and debris from the openings.
2. Prior Art
Brine shrimp of the genus Artemia, and specifically of the species Atremia salina, are primitive crustaceans which normally inhabit bodies of water having a high saline content, such as the Great Salt Lake in Utah. Brine shrimp serve as a source of food for many fish. Brine shrimp have been harvested for many years and are used as fish food on a commercial basis. Brine shrimp eggs are contained within protective spherical cysts or shells of hemoglobin. Brine shrimp eggs are remarkable in that they can be dried and stored and then hatched years later by returning them to salt water. The eggs may be nurtured to shrimp which are used as food in shrimp farms and the like producing food for human consumption. The ability to stockpile dried brine shrimp eggs for future hatching has made commercial harvesting of the eggs a profitable venture.
Brine shrimp and their eggs agglomerate in floating colonies at the surface of the water. Typically, the eggs occupy the top one quarter inch of water. The eggs are extremely small; approximately seven million brine shrimp eggs are contained in a single ounce. Adult brine shrimp are a thousand times larger than the egg.
The eggs are harvested by collecting the eggs left along the beaches or by off-shore harvesters. Due to the small size of the eggs, they are very difficult to harvest. In addition, because of the nature of the adult brine shrimp to agglomerate, the eggs are harvested along with adult brine shrimp and other debris.
Attempts have been made to screen the slurry of shrimp, eggs and debris in order to separate the eggs from the debris and adult brine shrimp. This is difficult because the adult brine shrimp agglomerate, trapping the eggs. In addition, the debris and adult shrimp tend to clog the openings in the screen, preventing eggs from passing through the screen.
Typical prior art devices and methods for screening the eggs comprise a horizontal screen which is vibrated. The brine shrimp and the debris clog the openings of the screen requiring the process to be stopped in order to clean the screens. Thus, these devices and methods require that the separation process be done in batches which is slow and inefficient. A more continuous device and method which configures the screen as a conveyor belt has been attempted with limited success.
Therefore it would be advantageous to develop an apparatus and method for separating brine shrimp eggs from a slurry containing an agglomeration of adult brine shrimp, eggs and other debris.


A floor mat system and clip for use therewith can be installed to any floor and includes a floor mat formed from a series of first and second criscrossed ribs which form rectangular-shaped openings therebetween, and clip having a rectangular-shape base and four outwardly extending raised projections. Certain of the second ribs have an enlarged bottom which forms a latching shoulder on each side thereof. The projections of the clip have a generally triangular-shaped end which snap-fits with the latching shoulder of the certain second ribs and which aligns with certain of the openings of the floor mat. A pair of holes are formed in the clip which align with other of the openings of the floor mat when attached thereto.

Technical Field
Generally, the invention relates to a floor mat system and clip for use therewith. Particularly, the invention relates to a floor mat system which includes a clip which mounts on the floor and engages the floor mat to retain the floor mat on the floor. Specifically, the invention relates to a floor mat formed with a latching shoulder, and a clip which is secured to the floor and which is formed with a plurality of latching projections which engage the latching shoulder to retain the floor mat adjacent the floor.


An integrated circuit includes an UTBOX insulating layer under and plumb with first and second electronic components, and corresponding ground planes and oppositely-doped wells made plumb with them. The wells contact with corresponding ground planes. A pair of oppositely doped bias electrodes, suitable for connecting corresponding bias voltages, contacts respective wells and ground planes. A third electrode contacts the first well. A first trench isolates one bias electrode from the third electrode and extends through the layer and into the first well. A second trench isolates the first bias electrode from one component. This trench has an extent that falls short of reaching an interface between the first ground plane and the first well.

SOI technology consists in separating a slender silicon layer (a few nanometers) on a silicon substrate by a relatively thick layer of insulant (a few tens of nanometers as a general rule).
Integrated circuits produced by SOI technology exhibit a certain number of advantages. Such circuits generally exhibit lower electrical consumption for equivalent performance. Such circuits also induce lower parasitic capacitances, which make it possible to improve switching speed. Moreover, the phenomenon of parasitic triggering ("latchup") encountered by MOS transistors in Bulk technology can be avoided. Such circuits therefore turn out to be particularly suitable for applications of SoC or MEMS type. It is also noted that SOI integrated circuits are less sensitive to the effects of ionizing radiations and thus turn out to be more reliable in applications where such radiations may induce operational problems, in particular in space applications. SOI integrated circuits can in particular comprise random-access memories of SRAM type or logic gates.
The reduction in the static consumption of logic gates while increasing their toggling speed forms the subject of much research. In the course of development, certain integrated circuits integrate at one and the same time logic gates with low consumption and logic gates with high toggling speed. To generate these two types of logic gates on one and the same integrated circuit, the threshold voltage of certain transistors of the logic gates with fast access is lowered, and the threshold voltage of other transistors of the logic gates with low consumption is increased. In bulk technology, the modulation of the threshold voltage level of transistors of the same type is performed by differentiating the doping level of their channel. However, in FDSOI (for "Fully Depleted Silicon On Insulator") technology, the doping of the channel is almost zero (1015 cm−3). Thus, the doping level of the channel of the transistors therefore cannot exhibit any significant variations, thus preventing the threshold voltages from being differentiated in this way. A solution proposed in certain studies in order to produce transistors of the same type with distinct threshold voltages is to integrate different gate materials for these transistors. However, the practical production of an integrated circuit such as this turns out to be technically tricky and economically prohibitive.
In order to have distinct threshold voltages for different transistors in FDSOI technology, it is also known to use a biased ground plane disposed between a thin insulating oxide layer and the silicon substrate. By altering the doping of the ground planes and their bias, it is possible to define a range of threshold voltages for the different transistors. It will thus be possible to have transistors with low threshold voltage termed LVT (typically 400 mV), transistors with high threshold voltage termed HVT (typically 550 mV) and transistors with medium threshold voltage termed SVT (typically 450 mV). To allow the operation of the different transistors, it is necessary to electrically insulate them from one another. Consequently, the transistors are generally surrounded by isolation trenches (designated by the acronym STI for "Shallow Trench Isolation"), which extend as far as the wells.
In a known manner, integrated circuits such as these also include devices for protection against accidental electrostatic discharges (ESD) that might impair these transistors.
The document "Multi-VT UTBB FDSOI Device Architectures for Low-Power CMOS Circuit", published by IEEE Transactions on Electron Devices, IEEE Service Center on pages 2473-2482, in volume 58, No. 8 of 1 Aug. 2011, describes an integrated circuit furnished with first and second FDSOI transistors disposed on a buried insulating layer of UTBOX type. First and second ground planes are disposed plumb with the first and second transistors respectively, under the buried insulating layer. First and second wells exhibit opposite types of doping and are disposed respectively under the first and second ground planes, plumb with them. Different bias voltages bias the first and second wells.
There exists a need for devices for protection against electrostatic discharges affecting integration density only marginally, making it possible to ensure local protection of the integrated circuit, and if possible ensuring protection whatever the polarity of the discharge.

ON-SOI integrated circuit comprising a thyristor (SCR) for protection against electrostatic discharges

COMMISSARIAT Á L'ÉNERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES


A finger-moistening device for fingerprint recognizing apparatus includes: a container filled with a non-volatile oil or liquid in the container, a powder-metallurgy made roller rotatably mounted and capillarily impregnated in the container to form an oil-impregnated roller, and an upper cover covering the container and having an opening for protruding a peripheral portion of the roller outwardly from the cover and the container for spreading a thin layer of oil or liquid onto the finger of a person to be detected to increase the cohesion between the finger and a prism surface of the fingerprint recognizing apparatus for obtaining a clear fingerprint image for a qualified fingerprint recognition.

For recognizing a fingerprint of a person's finger by an optical fingerprint imaging system, the finger is placed on a prism surface whereby the incident light will be absorbed by the ridge of the finger on the finger receiving surface, while the incident light will be internally reflected from the finger receiving surface underneath a valley of the finger, thereby forming fingerprint images having dark areas of the reflection image corresponding to the ridges and having the light areas corresponding to the valleys of the fingerprint.
However, a dry finger has a poor cohesion to the finger receiving surface of the fingerprint recognizing system, the incident light from an illuminator may not be completely absorbed by the ridges of the dry finger and will be partially internally reflected from the finger receiving surface, thereby causing a vague image of the fingerprint and deteriorating the fingerprint identification.
A conventional method to overcome the above-mentioned defect has been tried by moistening the finger with water or alcohol in order to have a closer contact of the finger on the prism surface for making a clear fingerprint image.
Still, the moistening with water or alcohol on the finger has the following drawbacks:
1. The water or alcohol has a good fluidity and is easily volatile to make the contacting areas unclear between the finger and the prism surface. For instance, the water or alcohol may flow from a ridge to a valley to influence the total internal reflection at the valley when touching the finger on the prism surface, thereby deteriorating the image quality of the fingerprint recognition. PA1 2. Even though the water may be soaked in a cotton pad, the water quantity as moistened on the finger from the pad can not be well controlled. Too much water may still contaminate the prism surface and may influence the imaging precision during fingerprint recognition. PA1 3. The wet finger when moistened with water or alcohol may cause dislike feeling for the person to be detected. Meanwhile, the water or alcohol pad should be always maintained or replaced with fresh one for hygienic purpose, causing inconvenience for the maintenance of the fingerprint imaging device.
The present inventor has found the drawbacks of the conventional fingerprint recognition systems and invented the present finger-moistening means for fingerprint recognizing apparatus.

Finger-moistening means for fingerprint recognizing apparatus


The invention relates to photosensitive semiconductor devices and, more particularly, to linear arrays having several parallel rows of photoconductive points and operating in the integration and charge carry mode. In particular, the object of the invention is to reduce a smearing effect.. The device of the invention comprises a photosensitive surface (SP) divided into photosensitive surface elements (SI1 to SMn) placed in rows (L1 to Ln) and in columns (C1 to CM). Each column forms a shift register that ends in a storage space (CS1 to CSM) of a readout register (RL) formed by a shift register of the charge transfer type: readout register (RL) being on same semiconductor substrate (10) as photosensitive surface (SP) the device includes.. According to a feature of the invention, the device an intermediate zone (ZI) protected from light used to make a separation distance (DS) between photosensitive surface (SP) and readout register (RL).

1. Field of the Invention
This invention relates to photosensitive semiconductor devices consisting of at lesat one row of photodetecting points, a row coupled to a readout register of the charge-transfer type. The invention is applicable particularly to linear arrays made of several parallel rows of photodetecting points operating in the integration and charge carry mode (abbreviated "IRC"), and it relates to means of significantly reducing the smearing effect.
2. Description of Background
FIG. 1 diagrammatically shows the conventional architecture of a photosensitive array BP of the type formed by several rows L1, L2, . . . , Ln with photosensitive surface elements S1n, S2n, . . . , SMn. The rows of photosensitive surface elements are parallel and these photosensitive surfaces are arranged so that they form rows L1 to Ln and columns C1 to CM perpendicular to the rows.
According to a conventional arrangement, a readout register RL (formed by a shift register operating by charge transfer) is located beside one of the ends of columns C1 to CM formed by the photosensitive surface elements belonging to first row L1. Each of these photosensitive surface elements S1 to SM of first row L1 is connected, by a gate Pl to PM, to a storage space, CS1 to CSM respectively, of readout register RL. In a conventional way, readout register RL operates, for example, in the two-phase mode, with two transfer control inputs ET1, ET2, to which there are applied control signals SC1, SC2 having phases suitable for transferring, to an output SO of the register, electrical charges that have been discharged in the latter. Output SO is connected to a readout circuit CL, conventional in the art, notably comprising an amplifier A that supplies a succession of signals (not shown) in the form of voltage, for example, each having an amplitude corresponding to the quantity of charges discharged in a space CS1 to CSM.
Each of rows L1 to Ln comprises a control input EC1 to ECn to which there are applied transfer control signals called row signals SL1 to SLn; these row signals are used to transfer, in the direction of columns C1 to CM, i.e., from rows to rows, the charges stored at the photosensitive surface elements forming these rows L1 to Ln, until these charges are discharged in storage spaces CS1 to CSM of readout register RL.
The "IRC" type of operating mode is well known in the art. It is used notably in the case of a relative linear movement between an image and photosensitive array BP. In FIG. 1, an arrow designated 3 symbolizes the shifting of the image (not represented) relative to array BP. Operation in IRC mode consists in shifting rows L1 to Ln or, more precisely, in transferring the charges accumulated at a given row L1 to Ln to a following row, synchronized with the shifting of the image and in the same direction. In this configuration, when the photosensitive surfaces of a given row are illuminated, row Ln for example, the photosensitive surfaces of this row accumulate charges during a period called integration time Ti that corresponds to the time it takes one row to analyze some of the image compared to this row of photosensitive surfaces. Then, with the relative shifting of the image and of the photosensitive array, this same row for analyzing some of the image (not shown) arrives at the level of the following row of photosensitive surfaces, i.e., row Ln-1: the charges stored in this row Ln-1 having been transferred in advance to the following row, in the direction of transfer shown by an arrow 5, row Ln-1 then finds itself emptied of all charge and row signal Sln controls the transfer of charges that were stored in row Ln and that are then transferred into adjacent row Ln-1, and then the integration period begins for the photosensitive elements of this row Ln-1. Thus it is for each photosensitive surface element of this row Ln-1; each of these photosensitive surface elements produces charges that are added to charges already stored by the illumination at the same point of a same row of the image. Also, continuing in this way up to first row L1 near the readout register, the information projected by the image is integrated n times longer.
The usefulness of a photosensitive sensor operating in the IRC mode consists in the considerable improvement of the signal-to-noise ratio, this ratio being a determining factor for detection. Indeed, if only the dominant noise and the photon noise are considered, the signal is multiplied by n while the noise is multiplied by .sqroot.n. The signal-to-noise ratio is thus increased by the factor .sqroot.n.
As a reminder, on the one hand that, the shift register, which forms the readout register RL, and controlled gates P1 to PM placed between the readout register and photosensitive array BP, are formed on the same semiconductor substrate as photosensitive array BP and, on the other hand, readout register RL and controlled gates P1 to PM are masked by a filter that is opaque to light (visible or near-visible), while the photosensitive elements are exposed to this light to produce more numerous negative charges (electrons) the more intense the illumination. The opaque filter is shown in FIG. 1 by slanted lines designated 14. Array BP thus comprises a photosensitive surface SP divided into photosensitive surface elements S1.sub.1 to SM.sub.n forming rows L1 to Ln and columns C1 to CM: row L1 is made of photosensitive surface elements S1.sub.1, S2.sub.1, S3.sub.1 . . . , SM.sub.1 ; row L2 is made of photosensitive surface elements S1.sub.2, S2.sub.2, S3.sub.2, . . . SM.sub.2, and so on; column C1 is made of surface elements S1.sub.1, S1.sub.2, S1.sub.3, . . . S1.sub.n ; column C2 is made of surface elements S1.sub.2, S2.sub.2, S2.sub.3, . . . , S2.sub.n and the same for the other columns. In the nonlimiting case shown in FIG. 1 by way of example, each photosensitive surface element S comprises, in a known way, two electrodes electrically connected to one another, one of which has a threshold voltage different from the other to direct the charge transfer in the direction of arrow 5, thus forming a pair of electrodes made of a transfer electrode ET followed by a storage electrode ES (in the direction of columns C1 to CM), with storage electrode ES beside readout register RL. Thus each column C1 to CM comprises a succession of photosensitive surface elements, each having a storage electrode and a transfer electrode so that each of the columns forms a shift register for charge transfer. If first column C1 is considered, for example following a direction opposite to that shown by arrow 5, starting at first row L1 there is found: a first storage electrode ES1 followed by a first transfer electrode ET1 in first surface element S11; then, at second row L2, a second storage electrode ES2 is found, followed by a second transfer electrode ET2; then a third storage electrode ES3 followed by a third transfer electrode ET3; and so on until last row Ln, where a storage electrode ESn followed by a transfer electrode ETn is found.
The unit operates cyclically with, for each cycle, a control for readout register RL, a control that causes, in the latter, a gradual transfer, toward the readout circuit, of data or charges that were stored in the various columns and that have been discharged in corresponding spaces of readout register RL, this is performed by gate circuits P1 to PM to which there were applied, for this purpose, authorizing pulses SA, authorizing the passage of the charges.
The transfer of charges for each column C1 to CM, from row Ln up to row L1, is obtained using row signal pulses SL1 to SLn. These row signals follow one another with phase deviations that depend on the operation of photosensitive array BP, this operation being able to be conventional, either the two-phase, three-phase, or four-phase type, or, moreover, these pulses can follow one another with a phase such that time .DELTA.T, which separates two successive pulses applied to two adjacent rows, corresponds to the ratio of cycle time TC to number of rows n (.DELTA.T=TC/n); this last type of operation is known by the English expression "ripple clock."
FIG. 2 is a timing diagram showing the phase relation among signals to be applied to a photosensitive array operating in the IRC mode, with eight "ripple clock" phases, i.e., an array comprising eight rows of photosensitive surface elements.
Rows a to h of FIG. 2 show, respectively, row signals SL1 to SL8 made of negative voltage pulses intended to be applied respectively to rows L1 to L8.
Moment t1 marks the start of row signal SL1 applied to first row L1, and moment t2 marks the end of this signal. We mention that first row L1, to which this signal SL1 is applied, is the row closest to readout register RL, and that moment t2 marks the end of the transfer of charges stored at storage electrodes ES1 of this row; these charges being transferred in the corresponding spaces of the readout register. We note that the beginning is thus first row L1 being emptied of its charges, thus leaving it ready to receive charges coming from second row L2.
Signal SL2 applied to second row L2 starts at a moment t3, which follows moment t2 by a time .DELTA.t; the end of pulse SL2 is found at a moment t4 and marks the end of the transfer of charges stored at second row L2, these charges being transferred at the storage electrodes of first row L1; second row L2 thus being freed in its turn.
A similar operation is found for pulses SL3 to SL8, applied respectively to rows L3 to L8 and beginning, respectively, at moments t7, t9, t11, t13, t15; and ending at moments t8, t10, t12, t14, t16.
At a moment t17, found after moment t16, a second pulse SL1' starts that is applied again to first row L1 to discharge the charges contained in the latter in corresponding spaces of the readout register; this pulse SL1' ends at an instant t18.
The time interval between moment t2 and moment t18 corresponds to an integration time Ti of first row L1. It can be thought that a cycle time Tc is between moment t2 and moment t18, which marks the end of second pulse SL1' applied to first row L1.
FIG. 3 shows a column C1 to CM in a diagrammatic, cutaway view, first column C1, for example, and shows the potential profiles at the electrodes of this column, these potential profiles being produced by applying row signals SL to these electrodes; as is customary concerning charge transfer devices, the positive potentials increase toward the bottom.
In the example described, first column C1 comprises 8 pairs of electrodes, ES1 to ES8 and ET1 to ET8, i.e., it belongs to an array comprising 8 rows L1 to L8.
Each pair of electrodes symbolizes a row L1 to L8 and comprises a storage electrode and a transfer electrode, the two electrodes of the same pair being connected together and controlled by the same row signal. Thus there is found successively, starting from the right of the figure in a direction opposite to charge transfer direction 5: an electrode ECs1 that controls first space CS1 of shift register RL; then an electrode EP that represents the controlled gates located between photosensitive array BP and readout register RL; then photosensitive zone or surface SP of column C1 begins, i.e., first storage electrodes ES 1 is followed by first transfer electrode ET1, these two electrodes being connected and intended to receive row signal SL1. Then there is found a second pair of electrodes made of the second storage electrode followed by the second transfer electrode, and so on up to the eighth pair of electrodes formed by an eighth storage electrode Es8 followed by en eighth transfer electrode Et8. These electrodes are carried in a conventional way by a semiconductor substrate 10, by an electrically isolating layer 11 that isolates the electrodes from one another and from substrate 10. Semiconductor substrate 10 can be of silicon, for example, of the P-doped type, but it can comprise, under isolating layer 11, a layer 12 with N-type doping, intended to form, in a conventional way, a buried channel promoting charge transfer.
As we indicated above, the zones corresponding to readout register RL and to the gates authorizing the passage of charges toward the readout register are masked by an optical filter 14, made of aluminum for example, which prevents any illumination of these zones, while photosensitive surfae SP remains exposed to light. This is illustrated in FIG. 3, in which optical filter 14, opaque to light, extends above a zone ZPL protected from light, i.e., above passage electrode P1 and above first space CS1 of readout register RL; the photons are symbolized by wavy arrows 16 that can penetrate up to the substrate to produce charges there; storage and transfer electrodes ES1 to ES8 and ET1 to ET8 being made, for example, of highly doped silicon, they are transparent to light, isolating layer 11 being also transparent to light.
It should be noted that transfer electrodes ET1 to ET 8 produce, in a conventional way, a threshold voltage higher than the storage electrodes to define an isolating wall between rows to orient the direction of the charge transfer as shown by arrow 5, i.e., in the direction starting from storage electrode ES8 toward first storage electrode ES1 and toward shift register EL. This threshold difference can be obtained in a conventional way, for example, by a difference in the doping of the semiconductor material in zones marked N-, which are located at transfer electrodes ET1 to ET8; these zones N- having the same type of conductivity as buried channel 12 with N-type doping, but less doped than the latter.
FIG. 3a is to be read with FIG. 3 and it illustrates the potential profile that exists at transfer and storage electrodes ET1 to ET8 and ES1 to ES8, just before moment t1 mentioned in FIG. 2, i.e., in the absence of row signal; this moment t1 marks the start of the pulse of row signal SL1 applied to first row L1 and subsequently applied to first transfer and storage electrodes ET1, ES1.
Thus, just before moment t1, the potential applied to all the electrodes is a resting potential which, for example, is positive with respect to a reference potential to which substrate is brought. The voltage threshold mentioned above, which transfer electrodes ET1 to ET 8 produce, creates, at these electrodes, a potential VP1 that is more negative than a potential VP2 that is created at storage electrodes ES1 to ES8. As a result, at each storage electrode ES1 to ES8, there is created a potential well PU1 to PU8 whose bottom corresponds to positive potential VP2, and these potential wells are separated by potential barriers B1 to B7 produced, respectively, at transfer electrodes ET1 to ET8; barriers B1 to B7 make it possible to separate the charges (symbolized in the figure by hatch marks) stored at storage electrodes ES1 to ES8 in corresponding potential wells PU1 to PU8. It can be noted that, in charge transfer direction 5, each potential well PU8 to PU1 contains more charges than the preceding potential well; so that just before moment t1, potential well PU1, located at storage electrode ES1, contains all the charges that were successively integrated for the same point of the image during the shifting of the latter.
FIG. 3b illustrates the transfer, in space CS1 of readout register RL, of charges that were contained in first potential well PU1, this charge transfer being completed at moment t2, at which the pulse of row signal SL1 ends: it can be seen that, with the application of row signal SL1, made by a pulse of negative voltage, the potentials at the first transfer electrode and the first storage electrode become more negative and pass respectively to values VP5, VP6, with value VP5 more negative than value VP6, so that potential barrier B1 is maintained and prevents the charges that were contained in first potential well PU1 from returning to second potential well PU2. In contrast, following a pulse of positive voltage applied to gate electrodes EP, the resting potential at the latter becomes more negative and of a value, for example VP7, which it had before moment t1 when it formed a potential barrier BPP, it passes to a more positive value, for example VP1, so that it does not form an obstacle to discharging, in space CS1 of the readout register, of the charges that were originally contained at first storage electrode ES1, i.e., in first potential well PU1.
FIG. 3c shows the potential profile between moment t2 and moment t3, represented in FIG. 2; it can be seen that potential well PU1 at first storage electrode ES1 has been emptied of its charges, and consequently it is ready to receive the charges stored in preceding potential well PU2, located at second storage electrode ES2.
FIG. 3d illustrates the transfer, into first potential well PU1, of charges that, before moment t3, were contained in second potential well PU2: between moment t3 and t4 (represented in FIG. 2), signal SL2, made of a pulse of negative voltage, is applied to second transfer and storage electrodes ET2, ES2 and the potentials at these electrodes pass to more negative values, respectively from VP2 to VP5 and from VP1 to VP6, as in the case of the preceding example. The result is that at moment t4 (shown in FIG. 2), the charges that were originally contained in second potential well PU2 are again stored in first potential well PU1.
FIG. 3e shows that, at moment t4 (illustrated in FIG. 2), second potential well PU2 is empty, and it is able, as a result, to receive the charges contained in the potential well preceding it, i.e., third potential well PU3 formed at third storage electrode ES3.
FIG. 3f illustrates the variations of potential produced at third transfer and storage electrodes ET3, ES3 by applying the pulse of negative voltage, of which row signal SL3 is made, applied to these third electrodes and which leads to transferring, in second potential well PU2, the charges that were contained in third potential well PU3; this is according to the same type of operation as in the preceding examples.
These operations are repeated in a similar manner (not shown) successively to transfer the charges contained in potential wells PU4, PU5, PU6, PU7 and PU8. The subsequent discharge, in space CS1 of readout register RL, of the charges contained in first potential well PU1 is performed, in a way similar to that shown in FIG. 3b, between moments t17 and t18 (shown in FIG. 2) at which a new row signal SL1' is again applied to first row L1, i.e., to first transfer and storage electrodes ET1, ES1. It should be noted that, between these two successive transfer operations in the spaces of register RL of the charges that were stored in first potential well PU1, the readout register was activated so as to advance gradually, toward readout circuit CL (shown in FIG. 1), all the charges that were stored in spaces CS1 to CSM.
This operation and this configuration of a photosensitive device operating in the integration and charge carry mode are conventional in the art. But this configuration produces a major drawback that consists in an especially significant smearing effect that can affect the entire image.

Optical sensor exhibiting a reduced smearing effect

Thomson Composants Militaires et Spatiaux


An integrated circuit including a resistive memory cell and a method of manufacturing the integrated circuit are described. The integrated circuit comprises a plurality of resistive memory cells and a plurality of voltage supply contacts, wherein at least four resistive memory cells are in signal connection with one voltage supply contact.

Resistive memories make use of a memory element that can change its electrical resistance through suitable programming. Accordingly, the memory element comprises a resistive storage medium that exhibits at least two different states having different electrical resistance. One of theses states may be a high resistive state and the other may be a low resistive state. The resistive storage medium may be switched between theses states through suitable programming.
In resistive memory cells, such as conductive bridge RAM (CBRAM) memory cells, also referred to as programmable metallization cells (PMC) as well as phase change RAM (PCRAM) memory cells, or magnetic RAM (MRAM) cells, for example, the logical information may be written into a memory cell by changing the resistance of the cell. Storage of the information may be achieved by maintaining the resistance of the cell. For evaluating the content of a memory cell the resistance value of the cell may be evaluated by applying a voltage or a current to the cell, for example.

Integrated circuit with resistive memory cells and method for manufacturing same


Assessing performance impact of a power upgrade of one or more wind turbines of a wind farm that includes a group of target wind turbines and a group of reference wind turbines. For each of the target wind turbines, a transfer function is generated, establishing a relationship between the locally measured wind speed at the target wind turbine and locally measured wind speeds at each of the reference wind turbines. A power upgrade is performed on each of the target wind turbines, and subsequently power performance data is obtained for the reference wind turbines and the target wind turbines, within one or more wind speed intervals. For the target wind turbines, the wind speed intervals are based on estimated wind speeds, based on locally measured wind speeds at the reference wind turbines and the transfer functions.

Wind turbines are normally provided with a rotor in the form of a rotatable hub carrying a set of wind turbine blades. The wind acts on the wind turbine blades, thereby causing the hub to rotate. The rotational movements of the hub are transferred to a generator, either via a gear arrangement or directly, in the case that the wind turbine is of a so-called direct drive type. In the generator, electrical energy is generated, which may be supplied to a power grid.
In order to improve the performance of existing wind turbines, one or more power upgrades may be performed on the wind turbine. The power upgrade(s) may, e.g., be in the form of hardware upgrade(s) and/or in the form of software upgrade(s). Hardware upgrades could, e.g., include replacement of the wind turbine blades, alterations of the aerodynamic profiles of the wind turbine blades, e.g. in the form of vortex generators, slats, auxiliary profiles, etc., replacement or alterations of other components of the wind turbine, etc. Software upgrades could, e.g., include upgrades of the control software of the wind turbine, etc.
Following a power upgrade of a wind turbine, it is desirable to be able to assess whether or not the performed power upgrade has resulted in an improved performance of the wind turbine, as well as to what extent the performance has been improved. However, a power upgrade may influence locally measured wind speeds, e.g. due to a change in the wind flow downstream relative to the rotor, where an anemometer or the like is often arranged. Furthermore, other conditions may change from a time period prior to the power upgrade to a time period after the power upgrade, e.g. wind conditions, weather conditions, temperature, humidity, etc. Therefore, a direct comparison of the performance of the wind turbine before the power upgrade is performed and after the power upgrade is performed, will often not provide reliable information regarding the impact on the performance of the wind turbine, due to the power upgrade.
WO 2015/077337 A1 discloses a method for assessing the performance impact of wind turbine upgrades. The method comprises determining a baseline power curve for a wind turbine prior to the wind turbine being upgraded and determining a baseline wind speed transfer function for the wind turbine prior to the wind turbine being upgraded, the wind speed transfer function relating a reference wind speed to a local wind speed for the wind turbine. The method may also include determining an upgraded wind speed transfer function for the wind turbine after the wind turbine is upgraded, and determining a corrected local wind speed for the wind turbine based on the baseline and upgraded wind speed transfer functions. An upgraded power curve for the wind turbine may be determined based on the corrected local wind speed.

Method for assessing performance impact of a power upgrade


Embodiments of the present invention provide a switch cell and manufacturing method thereof, a display substrate, and a display device and the manufacturing method thereof, the driving power required by the switch cell can be reduced. The switch cell for converting a 2D image to be displayed by a display substrate into a 3D image comprises: a switch substrate; and at least one metal electrode provided on the switch substrate, wherein the position of the metal electrode is configured to be correspond to at least a portion of one corresponding black matrix of at least one black matrix provided on a display substrate.

1. Field of the Invention
Embodiments of the present invention relate to the technical field of display, and especially to a switch cell for converting a two dimensional (2D) image into a three dimensional (3D) image and manufacturing method thereof, a display panel, and a display device.
2. Description of the Related Art
Liquid crystal 3D display substrate technology is used to realize 3D display by providing a switch cell on a conventional 2D image display substrate. For the structure of the liquid crystal 3D display substrate, electrodes in the switch cell is constructed by transparent materials, such as Indium Tin Oxide (ITO), in order to avoid shielding pixels. However, the resistivity of the electrodes made from the transparent ITO is very high, such that the impedance of the entire display panel is very high, and the driving power required by the display panel is increased. This defect is especially serious when producing large sized display panel.

Switch cell and manufacturing method thereof, display panel, and display device


A method and system are disclosed for enabling design of a product such as a colored plastic having a visual effect caused by an additive. In one embodiment, a user such as a designer at a first computing unit is able to interact with a second computing unit operable to provide a generally accurate representation of the product having the visual effect. Desirably, the user inputs information relating to the additive such as a flake material or a diffuser material and the system provides a representation displayable on a display or monitor of the first computing unit of the product having the visual effect based on the information relating to the additive. The design of the product having the visual effect is advantageously stored on the second computing unit and accessible by at least one second user such as a marketer or manufacturer for review of the design. Further, the users can order plaques of the designed product having the visual effect so that a comparison of the product having the visual effect to actual samples of the product can be made before a production order is placed.

The present invention generally relates to product design, and more particularly, to a method and system for enabling design of products having a visual effect.
Colored plastics having a visual effect have recently gained widespread use by manufacturers in producing various products. For example, additives such as small reflective flakes of metal or glass are added to plastics to create a speckled appearance, and additives such as small threads or mineral particles are added to plastics to create a stone-like appearance. In addition, additives such as small particles which are mismatched in refractive index with respect to the base plastic resin result in the plastic being translucent wherein objects cannot be clearly seen through the plastic. A large number of plastics having different visual effects can be produced by combining such additives in various concentrations.
Currently, customers can choose from a limited number of manufacturer developed colored plastics having visual effects. If a customer desires a colored plastic having a customized visual effect, it then becomes a trial and error approach of trying different concentrations and combinations of a base material, coloring ingredients, and additives until the desired colored plastic having the visual effect is achieved. Often, the customer must travel to the plastic manufacturer or a color development laboratory to work with lab technicians to develop the colored plastic having the visual effect. This trial and error design approach is time consuming and costly.
There is a need for a more efficient way for enabling customers to design products having a visual effect such as a colored plastic having a visual effect.

Method, system, and program product for enabling design of products having a visual effect


A secondary battery includes a cathode, an anode, and a nonaqueous electrolytic solution. The nonaqueous electrolytic solution includes a compound represented by M+[(Z1Y1)(Z2Y2)N]− (where M is a metal element, each of Z1 and Z2 is one of groups such as as a fluorine group, and each of Y1 and Y2 is one of groups such as a sulfonyl group), a compound such as a compound represented by R1-CN (where R1 is a monovalent hydrocarbon group), and a compound such as a compound represented by R22-(CN)n (where R22 is an n-valent hydrocarbon group, and n is an integer of 2 or more). A content of the compound represented by [(Z1Y1)(Z2Y2)N]− in the nonaqueous electrolytic solution is within a range of 2.5 mol/dm3 to 6 mol/dm3 both inclusive.

Various electronic apparatuses such as mobile phones and personal digital assistants (PDAs) have been widely used, and it has been demanded to further reduce size and weight of the electronic apparatuses and to achieve their longer lives. Accordingly, batteries, in particular, small and light-weight secondary batteries that have ability to achieve high energy density have been developed as power sources for the electronic apparatuses.
Applications of the secondary battery are not limited to the electronic apparatuses described above, and it has been also considered to apply the secondary battery to various other applications. Examples of such other applications may include: a battery pack attachably and detachably mounted on, for example, an electronic apparatus; an electric vehicle such as an electric automobile; an electric power storage system such as a home electric power server; and an electric power tool such as an electric drill.
There have been proposed secondary batteries that utilize various charge and discharge principles in order to obtain battery capacity. In particular, attention has been paid to a secondary battery that utilizes insertion and extraction of an electrode reactant or a secondary battery that utilizes precipitation and dissolution of an electrode reactant, which makes it possible to achieve higher energy density than other batteries such as a lead-acid battery and a nickel-cadmium battery.
The secondary battery includes a cathode, an anode, and a nonaqueous electrolytic solution. The nonaqueous electrolytic solution contains a nonaqueous solvent and an electrolyte salt. The composition of the nonaqueous electrolytic solution exerts a large influence on battery characteristics. Accordingly, various studies have been conducted on the composition of the nonaqueous electrolytic solution.
More specifically, in order to achieve superior charge storage characteristics in a high temperature environment, a lithium salt such as lithium bis(fluorosulfonyl)imide is used as the electrolyte salt, and an organic solvent such as fluorinated cyclic carbonate ester is used as the nonaqueous solvent (for example, refer to Patent Literatures 1 to 6). In addition, for example, acetonitrile may be used as the nonaqueous solvent (for example, refer to Non-Patent Literature 1).

Secondary battery-use electrolytic solution, secondary battery, battery pack, electric vehicle, electric power storage system, electric power tool, and electronic apparatus


In a method of transforming light, an optical film for performing the method and a display device having the optical film, an optical film includes an anisotropic film, an isotropic film, a λ/4 phase difference film and a λ/2 phase difference film. The anisotropic film having a first refractive index with respect to a first ray and a second refractive index with respect to a second ray. A refractive index of the isotropic film is substantially identical to the first refractive index. The λ/4 phase difference film delays wavelengths of the first and second rays by about λ/4. The λ/2 phase difference film delays the wavelength of the second ray by about λ/2.

1. Field of the Invention
The present invention relates to a display device. More particularly, the present invention relates to a method of transforming a light beam capable of improving a light transparency, an optical film for performing the method and a display device having the optical film.
2. Description of the Related Art
Liquid crystal display devices are generally classified as a transmission type liquid crystal display (LCD) device, a reflective type LCD device, or a reflective and transmissive type LCD device. The transmission type LCD device uses a rear light to display an image. The reflective type LCD device uses a front light to display an image. The reflective and transmissive type LCD device uses both the rear light and the front light to display an image.
Both the reflective type LCD device and the reflective and transmissive type LCD device include a polarizing film/color filter/reflection plate structure and the reflectivity of both devices is approximately 6% to 8%, which is substantially lower than the reflectivity of the transmission type LCD device. Thus, the reflective type LCD device and the reflective and transmissive type LCD are not sufficient as a portable small size liquid crystal display panel. Light transmittances of the polarizing film and the color filter are approximately 43% and approximately 30%, respectively, therefore, light transmittance of the reflective type LCD device or the reflective and transmissive type LCD is low.

Method of transforming a light beam, optical film for performing the method, and display device having the optical film


An advanced jig for manufacturing a firearm lower receiver can include an adapter, a guide plate, a front support, a buffer support, a buffer mounting screw and at least one carriage with at least one locating pin. A guide plate can be in a location above the fire control cavity of a lower receiver and can be mounted to the carriage(s) in conjunction with a rotary power tool adapter. The jig can be a universal fitment. The jig can include a bearing to support a rotary tool and can be constructed and arranged to provide for use of at least one guiding feature to facilitate in the guidance of the rotary tool without placing the rotary tool in direct contact with any of a plurality of guidance features for firearm lower receiver manufacturing. A removable locating pin can be situated in a location along the front takedown pin hole of a firearm receiver that is for firearm lower receiver manufacturing.

A market exists for incompletely/partially manufactured firearm lower receivers. A firearm lower receiver is unregulated until a minimum level of manufacturing is completed. This level is typically known as "80%". Firearm lower receivers completed to this level are typically referred to as "80%" lower receiver. These firearm lower receivers must then be completed by the end user to be operable. In a typical configuration the unfinished lower receiver is molded, cast, billet and/or forged and is partially machined, with certain aspects of the inner slot (in which the trigger mechanism resides) remaining uncut. The finishing task cuts this remaining slow with appropriate dimensions and accuracy.
The completion of these lower receivers can be time consuming and quality results may be difficult to achieve with prior art. In accordance with the prior art, the technique for finishing the receiver can employ complex and ineffective systems to adapt the jig assembly to various types of lower receivers. Additionally, the prior art technique can involve the use of an inadequately supported rotating tool which can produce poor results and excessive breakage.
It would be desirable to provide a device and method that can make finishing a lower receiver easier to do with high quality results and reduced breakage.

Advanced jig for manufacturing of firearm lower receiver


Provided are a PUCCH resource configuration method, transmission method, device and system. The method includes: allocating dedicated PRBs for UEs configured to transmit uplink control information using an enhanced PUCCH, which step comprising: taking the UEs configured to transmit the uplink control information using the enhanced PUCCH as a first type of UEs, and taking UEs other than the first type of UEs as a second type of UEs; and reserving a designated number of PRBs according to the number of UEs in the first type of UEs, wherein the designated number of PRBs are located between SR/semi-static ACK/NACK resources of the second type of UEs and dynamic ACK/NACK resources of the second type of UEs, and taking the designated number of PRBs as dedicated PRBs for the first type of UEs; and allocating orthogonal resources for UEs located in different cells among the first type of UEs based on the dedicated PRBs. The disclosure solves the problem of great interference between PUCCH from different cells and ensuring the receiving quality of the PUCCH.

In LTE-A, in order to improve the cell average spectrum utilization efficiency and the cell edge spectrum utilization efficiency, Coordinated Multi Point Transmission/Reception (CoMP) technology is employed. CoMP technology is classified into DL CoMP (downlink CoMP) and UL CoMP (uplink CoMP), both of which can improve the average spectrum efficiency of a cell and the quality of service of a cell edge user to a great extent. CoMP is divided into the following four scenarios:
scenario 1: a homogeneous network with intra-site CoMP;
scenario 2: a homogeneous network with high transmit power (Tx) RRHs (Remote radio head);
scenario 3: a heterogeneous network with low power RRHs within the macro cell coverage, wherein the RRHs and the macro cell have different cell IDs;
scenario 4: a heterogeneous network with low power RRHs within the macro cell coverage, wherein the RRHs and the macro cell have the same virtual cell IDs.
In LTE R8/R9/R10 protocol versions, the formats of the PUCCH channel can be divided into three categories, seven types of formats totally. The first type contains three formats, i.e., format1, format1a and format1b, the second type also contains three formats, i.e., format2, format2a and format2b, and the third type contains one format, i.e., format3. The first type of PUCCH is used for transmitting scheduling request (SR) and acknowledgement (ACK)/negative acknowledgement (NACK) signalling. The second type of PUCCH is mainly used for transmitting channel state information (CSI). Currently, the third type of PUCCH is mainly used for feeding back the ACK/NACK signalling of a plurality of cells in the case that the UE is configured with a plurality of serving cells under the carrier aggregation scenario. As shown in FIG. 1, it is a schematic diagram showing the resource allocation of a PUCCH on one slot. In FIG. 1, the mixed resource block (RB) represents that both the format1/1a/1b and the format2/2a/2b exist in this RB at the same time, and there is at most one mixed RB in one slot; the parameter N(2)RB represents the number of physical resource blocks (PRBs) occupied by format2/2a/2b, and this parameter is configured by the upper layer.
For the first type of PUCCHs, the available resource n_r is represented by three sub-resources, which are respectively: (n_cs, n_oc, n_PRB), wherein n_cs represents the resource sequence number of cyclic shift (CS), n_oc represents the resource sequence number of orthogonal code (OC), and n_PRB represents the resource sequence number of PRB. These three sub-resources are in a one-to-one correspondence with the resource index n(1,p)PUCCH. For the second type of PUCCHs, the available resource n_r is represented by two sub-resources, which are respectively: (n_cs, n_PRB). The available resources of the second type of PUCCHs are in a one-to-one correspondence with the resource index n(2,p)PUCCH. For the third type of PUCCHs, the available resource n_r is represented by two sub-resources, which are respectively: (n_oc, n_PRB). The available resources of the third type of PUCCHs are in a one-to-one correspondence with the resource index n(3,p)PUCCH.
The resource index n(1)PUCCH of format 1 in the first type of PUCCHs is configured by the upper layer. The value of the resource index n(1)PUCCH of PUCCH format 1a/1b on subframe n can be obtained by two methods, which will be described as follows by taking the case where the UE is configured with one serving cell in a frequency division duplex (FDD) system as an example.
If the physical downlink shared channel (PDSCH) on subframe n-4 of the main serving cell does not detect the corresponding physical downlink control channel (PDCCH), then the above-mentioned n(1,p)PUCCH will be obtained according to upper-layer configuration and Table 1, and such kind of ACK/NACK is referred to as semi-static ACK/NACK (which can also be referred to as semi-static A/N) herein.
If the PDSCH on subframe n-4 of the main serving cell detects a corresponding PDCCH, or this PDCCH is used for indicating downlink semi-static scheduling (SPS) release, then the above-mentioned n(1,p)PUCCH will be obtained according to the following manner n(1,p=p0)PUCCH=nCCE+N(1)PUCCH, where nCCE represents the index of the first control channel element (CCE) of the PDCCH, N(1)PUCCH is a parameter configured by the upper layer and represents the number of resource indexes reserved for SRs and semi-static ACK/NACK (which can also be referred to as SR as well as semi-static A/N). FIG. 2 is a schematic diagram showing the resource index configuration of a PUCCH. For the channel resources of the second antenna port, n(1,p)PUCCH will be obtained in the following manner: n(1,p=p1)PUCCH=nCCE+1+N(1)PUCCH, and such kind of ACK/NACK is referred to as dynamic ACK/NACK (which can also be referred to as dynamic A/N).
TABLE 1TPC domainnPUCCH(1, p)'00'The first PUCCH resource valueconfigured by the upper layer'01'The second PUCCH resource valueconfigured by the upper layer'10'The third PUCCH resource valueconfigured by the upper layer'11'The fourth PUCCH resource valueconfigured by the upper layer
In this table, the transmission power control (TPC) domain is on a corresponding PDCCH.
n(2,p)PUCCH is configured by the upper layer. The resource index n(3,p)PUCCH of the third type of PUCCHs is obtained according to upper-layer configuration and Table 2.
TABLE 2TPC domainnPUCCH(3, p)'00'The first PUCCH resource valueconfigured by the upper layer'01'The second PUCCH resource valueconfigured by the upper layer'10'The third PUCCH resource valueconfigured by the upper layer'11'The fourth PUCCH resource valueconfigured by the upper layer
Then, after the available resource is obtained according to the resource index and the parameter configured by the upper layer, a channelization process will be performed, wherein the channelization processes of different formats of PUCCHs are different, which will be described simply hereinafter respectively.
The channelization process of format1/1a/1b is as follows: a data bit is modulated, then multiplied with CS and expanded to 12 subcarriers, then multiplied with OC code to realize time domain expansion, and then is subjected to code channel scrambling, and the obtained symbol will be mapped to a corresponding PRB.
The channelization process of format2/2a/2b is as follows: a data bit is scrambled first, then modulated, then multiplied with CS, and the obtained symbol will be mapped to a corresponding PRB.
The channelization process of format 3 is as follows: a data bit is scrambled first, then modulated, then multiplied with OC code and phase rotated, then cyclic shifted at a cell-specific symbol level, and discrete Fourier transformed (DFT) and then mapped to a corresponding PRB.
In LTE R8/R9/R10 protocol versions, a user equipment (UE) corresponds to one PUCCH channel. For a PUCCH channel, different UEs in a cell are multiplexed in a code division multiplexing (CDM) or frequency division multiplexing (FDM) manner, wherein the UEs are allocated to different PRBs in the FDM manner, and the UEs adopt different cyclic shift sequences (CSs) or different orthogonal codes (OCs) in the CDM manner. Here, different cyclic shift sequences refer to different cyclic shifts corresponding to the same root sequence. The root sequence is a computer-generated constant amplitude zero auto-correlation (CG-CAZAC) sequence with a length of 12, different cyclic shifts of the same root sequence are orthogonal to each other, and different root sequences are not orthogonal to each other. The root sequence is in a one-to-one correspondence with the cell ID. Therefore, the PUCCHs within the same cell are orthogonal to each other, and the PUCCHs from different cells with different cell IDs are not orthogonal to each other.
In LTE R10 protocol version, in order to reduce inter-cell interference, inter-cell interference randomization is performed for all PUCCH formats by using cyclic shift at a cell-specific symbol level.
Therefore, in LTE R8/R9/R10 protocol versions, when cell IDs are different, the PUCCHs among cells are not orthogonal. In CoMP scenario 3, the cell IDs of the macro cell and the RRH are different, while the UE of the macro cell and the UE of the RRH may send the PUCCH over the same time frequency resource, and in this case, the PUCCHs of the two UEs are not orthogonal. When the UE of the macro cell is at the edge of the RRH coverage and the power of the sent PUCCH is relatively large, if the power of this PUCCH reaching the RRH is comparable to the PUCCH power sent by the RRH UE or greater than the PUCCH power of the RRH UE, the PUCCH sent by the RRH UE will be interfered seriously, which renders the quality of the PUCCH signal received by the RRH to be very poor. In the case of joint reception of uplink (UL) CoMP, a plurality of nodes jointly receive the PUCCH sent by the same UE, if the target PUCCH comes from a neighbour cell, the PUCCH from the current cell will interfere with the target PUCCH since this target PUCCH is not orthogonal to the PUCCH in the current cell, which renders the receiving quality of the target PUCCH to be very poor and seriously affects the CoMP gain.
Aiming at the problem of great interference between PUCCHs from different cells in the related art, no effective solution has been presented currently.


A data processing system that includes several ongoing processes that provide input words to a buffer of an independently executing processor, a buffer manager that controls the process access to the buffer and controls the words input by the processes to the buffer that includes an apparatus for regulating the number of words from an executing first process for loading into the buffer, an apparatus for loading the number of words, an apparatus for loading a synchronization word when a second process is to be executed and an apparatus for halting the loading of the first process words and providing for loading of the second process words when the synchronization word is accessed by the independently executing processor.

In data processing systems, the management of buffer queues is required in many areas. For instance, commands stored for an independently executing processing system will be temporarily stored in buffer queues. Therefore, the supplier of the commands need not provide the commands synchronized with the execution of commands by the independent processing device. However, it must be ensured that the buffer storing these commands temporarily does not overflow or, in a system optimally providing commands, that the buffer queue does not become empty. Traditionally, two techniques have been used to manage buffers. One technique requires that the sender of commands to the buffer query the status of the buffer. In a data processing system where the buffer is tightly coupled to the remainder of the system, this may not be a problem. However, if the buffer is located on a communications bus, the querying of status includes a bus overhead. A second technique is to fill the buffer and wait for the buffer to empty before it is filled again.
One example of an embodiment using the full buffer technique is contained in a paper entitled "Virtual Graphics" by Voorhies, Kirk and Lathrop, published in Computer Graphics, Vol. 22, No. 4, August, 1988. This reference illustrates a first-in/first-out (FIFO) buffer that provides interrupts when the buffer is nearly full by providing an interrupt each time a command is presented to the buffer. This forces the process providing these commands to wait until the buffer is only half full. While this process does regulate the number of commands placed into the buffer, it also generates an excessive number of interrupts.
It is the object of the present invention to provide a buffer manager that minimizes the number of interrupts required while optimally providing entries to the buffer.

First-in/first-out buffer queue management for multiple processes

International Business Machines Corporation


The present invention provides a semiconductor memory device with reduced soft error rate (SER) and a method for fabricating such a device. The semiconductor memory device includes a plurality of implants of impurity ions that provide for a reduced number of minority carriers having less mobility. A fabrication process for the semiconductor memory includes a “non-retrograde” implant of impurity ions that is effective to suppress the mobility and lifetime of minority carriers in the devices, and a “retrograde” implant of impurity ions that is effective to substantially increase the doping concentration at the well bottom to slow down or eliminate additional minority carriers.

Soft error rate (SER) measures how often, when a memory device is accessed, incorrect data is provided due to external radiation, such as alpha particles or cosmic rays, which can penetrate and upset the operation of the memory device. SER is becoming a more stringent problem as device geometries continue to be reduced, making the devices more susceptible to such phenomena. This issue is even worse for SRAM devices since the storage node capacitance is much smaller for SRAM devices as compared with DRAM devices, which have a relatively large storage capacitor in each bit. Due to their fast operation, SRAM devices still prevail in many high speed applications such as networking, communications, and the like.
Several ways have been proposed to deal with SER issues. Generally, these can be categorized into two groups: (i) adding a capacitor to the storage node to enlarge the critical charge (Qcrit) of the device and make it harder to flip the state of the device; and (ii) reducing the storage node's collecting efficiency of minority carriers, so that flipping the state of the device becomes more difficult. While some of these prior art strategies are successful in reducing the SER numbers, they typically require extra masks and process steps that can reduce overall yield. This makes these strategies expensive to implement. Additionally, some of these strategies are of limited effect in reducing the SER numbers, and are inadequate for advanced technologies.
For these reasons, it would be desirable to provide a new and improved semiconductor memory device having reduced susceptibility to SER and a method for fabricating such a device.

Semiconductor memory device with reduced soft error rate (SER) and method for fabricating same