To make it possible to lower the luminance of an LCD to a level suitable for a dark place, either first image data based on which a predetermined image is displayed or second image data based on which the same image is displayed with lower luminance than the predetermined image based on the first image data is transferred to an LCD via a selecting means.

The present invention relates to an ultrasonic imaging system and a display device. More particularly, the present invention is concerned with an ultrasonic imaging system including a main display device that displays ultrasonic images and an auxiliary display device that displays information that helps a user operate the ultrasonic imaging system, and a display device to be used in combination with the ultrasonic imaging system.
For ultrasonic imaging, echoes of ultrasonic waves transmitted to the interior of an object are used to produce tomographic images that are displayed as B-mode images. Moreover, Doppler shifts occurring in the echoes of the ultrasonic waves are utilized to produce dynamic images of a blood flow or the like that are displayed as color Doppler images.
An ultrasonic imaging system includes an operator console, with which a user can freely operate the ultrasonic imaging system. The operator control includes a graphic display so as to cope with diverse requirements for the operation.
The operator console including the graphic display switches screens so as to change the features of the operator console. Operation is performed with utilization of graphical user interfaces implemented in the screens.
A liquid crystal display is adopted as the graphic display. A transmissive LCD that radiates light, which is emitted from behind, forwards through a liquid crystal matrix so as to display images is adopted from among various types of LCDs.
The transmissive LCD exhibits high luminance so as to offer excellent visibility even in a bright room or the like. The screen of the LCD tends to be too bright for ultrasonic imaging systems that are often used in dark environments.
Therefore, for example, when images being produced are displayed on a cathode-ray tube (CRT) display for observation, the screen of the LCD that is much brighter than the display screen of the CRT dazzles a user.
The luminance of the LCD can be somewhat lowered by adjusting illumination light emitted from behind. However, there is a limit in reduction of illumination light due to the properties of a light source, and even if the amount of illumination light is decreased to the lowest limit, the LCD may still be too bright
An object of the present invention is to realize an ultrasonic imaging system in which the luminance of an LCD in an operator console can be lowered to a level suitable for a dark place, and a display device in which the luminance of an LCD can be lowered to a level suitable for a dark place.
(1) According to one aspect of the present invention for accomplishing the foregoing object, there is provided an ultrasonic imaging system including imaging means for transmitting ultrasonic waves and producing images according to the received echoes of the ultrasonic waves; main display means for displaying the images; and auxiliary display means for displaying information that helps a user operate the imaging system, wherein the auxiliary display means includes an LCD for radiating light, which is emitted from behind, forwards through a liquid crystal matrix whose transmittance can be controlled at each pixel location, and thus displaying images; first memory means in which first image data based on which a predetermined image is displayed on the LCD is stored, second memory means in which second image data based on which the same image as the predetermined image is displayed on the LCD with lower luminance than the predetermined image based on the first image data is stored; and image data providing means for providing the LCD with either the first image data or the second image data that is selected.
(2) According to another aspect of the present invention for accomplishing the foregoing object, there is provided a display device including an LCD for radiating light, which is emitted from behind, forwards through a liquid crystal matrix whose transmittance can be controlled at each pixel location, and thus displaying images; first memory means in which first image data based on which a predetermined image is displayed on the LCD is stored; second memory means in which second image data based on which the same image as the predetermined image is displayed on the LCD with lower luminance than the predetermined image based on the first image data is stored; and image data providing means for providing the LCD with either the first image data or the second image data that is selected.
According to the aspects (1) and (2) of the present invention, the LCD is selectively provided with either of the first image data based on which the predetermined image is displayed, or the second image data based on which the same image is displayed with lower luminance than the predetermined image based on the first image data. The luminance of the LCD on which the same image is displayed can be changed between two levels.
(3) According to another aspect of the present invention for accomplishing the aforesaid object, there is provided an ultrasonic imaging system including imaging means for transmitting ultrasonic waves and producing images according to the received echoes of the ultrasonic waves; main display means for displaying the images; and auxiliary display means for displaying information that helps a user operate the imaging system, wherein the auxiliary display means includes an LCD for radiating light, which is emitted from behind, forwards through a liquid crystal matrix that permits control of the hue of each pixel, and thus displaying images; first memory means in which first image data based on which a predetermined image is displayed on the LCD is stored; second memory means in which second image data based on which the same image as the predetermined image is displayed on the LCD at darker hue than the predetermined image based on the first image data is stored; and image data providing means for providing the LCD with either the first image data or the second image data that is selected.
(4) According to another aspect of the present invention for accomplishing the aforesaid object, there is provided a display device including an LCD for radiating light, which is emitted from behind, forwards through a liquid crystal matrix that permits control of the hue of each pixel, and thus displaying images; first memory means in which first image data based on which a predetermined image is displayed on the LCD is stored; second memory means in which second image data based on which the same image as the predetermined image is displayed on the LCD at darker hue than the predetermined image based on the first image data is stored; and image data providing means for providing the LCD with either the first image data or the second image data that is selected.
According to the aspects (3) and (4) of the present invention, the LCD is selectively provided with either the first image data based on which the predetermined image is displayed, or the second image data based on which the same image is displayed at darker hue than the predetermined image based on the first image data. Consequently, the brightness of the same image to be displayed can be changed between two levels.
(5) According to another aspect of the present invention for accomplishing the aforesaid object, there is provided an ultrasonic imaging system including imaging means for transmitting ultrasonic waves and producing images according to the received echoes of the ultrasonic waves; main display means for displaying the images; and auxiliary display means for displaying information that helps a user operate the imaging system, wherein the auxiliary display means includes an LCD for radiating light, which is emitted from behind, forwards through a liquid crystal matrix that permits control of the hue of each pixel, and thus displaying images; first memory means in which first image data based on which a predetermined image is displayed on the LCD is stored; second memory means in which second image data based on which the same image as the predetermined image is displayed on the LCD at darker hue than the predetermined image based on the first image data is stored; third memory means in which third image data based on which the same image as the predetermined image is displayed on the LCD in a darker achromatic color than the image based on the second image data is stored; and image data providing means for providing the LCD with any of the first image data, the second image data, and the third image data which is selected.
(6) According to another aspect of the present invention for accomplishing the aforesaid object, there is provided a display device including an LCD for radiating light, which is emitted from behind, forwards through a liquid crystal matrix that permits control of the hue of each pixel, and thus displaying images; first memory means in which first image data based on which a predetermined image is displayed on the LCD is stored; second memory means in which second image data based on which the same image as the predetermined image is displayed on the LCD at darker hue than the predetermined image based on the first image data is stored; third memory means in which third image data based on which the same image as the predetermined image is displayed on the LCD in a darker achromatic color than the image based on the second image data is stored; and image data providing means for providing the LCD with any of the first image data, the second image data, and the third image data which is selected.
According to the aspects (5) and (6) of the present invention, the LCD is selectively provided with any of the first image data based on which the predetermined image is displayed, second image data based on which the as the image as the predetermined image is displayed at darker hue than the predetermined image based on the first image data, and third image data based on which the same image as the predetermined image is displayed in a darker achromatic color than the image based on the second image data. The luminance of the LCD on which the same image is displayed can be changed among three levels.
(7) According to another aspect of the present invention for accomplishing the aforesaid object, there is provided an ultrasonic imaging system including imaging means for transmitting ultrasonic waves and producing images according to the received echoes of the ultrasonic waves; main display means for displaying the images; and auxiliary display means, wherein the auxiliary display means includes an LCD for radiating light, which is emitted from behind, forwards through a liquid crystal matrix that permits control of the lightness and hue of each pixel, and thus displaying images; fist memory means in which first image data based on which a predetermined image is displayed on the LCD is stored; second memory means in which second image data based on which the same image as the predetermined image is displayed on the LCD at lower lightness and darker hue than the predetermined image based on the first image data is stored; and image data providing means for providing the LCD with either the first image data or the second image data that is selected.
(8) According to another aspect of the present invention for accomplishing the aforesaid object, there is provided a display device including an LCD for radiating light, which is emitted from behind, forwards through a liquid crystal matrix that permits control of the lightness and hue of each pixel, and thus displaying images; first memory means in which first image data based on which a predetermined image is displayed on the LCD is stored; second memory means in which second image data based on which the same image as the predetermined image is displayed on the LCD at lower lightness and darker hue than the predetermined image based on the first image data is stored; and image data providing means for providing the LCD with either the first image data or the second image data that is selected.
According to the aspects (7) and (8) of the present invention, the LCD is selectively provided with either the first image data based on which the predetermined image is displayed, or the second image data based on which the same image is displayed at lower lightness and darker hue than the predetermined image based on the first image data. Consequently, the luminance of the LCD on which the same image is displayed can be changed between two levels.
(9) According to another aspect of the present invention for accomplishing the aforesaid object, there is provided an ultrasonic imaging system consisting of imaging means for transmitting ultrasonic waves and producing images according to the received echoes of the ultrasonic waves; main display means for displaying the images; and auxiliary display means, wherein the auxiliary display means includes an LCD for radiating light, which is emitted from behind, forwards through a liquid crystal matrix that permits control of the lightness and hue of each pixel, and thus displaying images; fi memory means in which first image data based on which a predetermined image is displayed on the LCD is stored; second memory means in which second image data based on which the same image as the predetermined image is displayed on the LCD at lower lightness and darker hue than the predetermined image based on the first image data is stored; third memory means in which third image data based on which the same image as the predetermined image is displayed on the LCD in a darker achromatic color than the image based on the second image data is stored; and image data providing means for providing the LCD with any of the first image data, the second image data, and the third image data which is selected.
(10) According to another aspect of the present invention for accomplishing the aforesaid object, there is provided a display device consisting mainly of an LCD for radiating light, which is emitted from behind, forwards through a liquid crystal matrix that permits control of the lightness and hue of each pixel, and thus displaying images; first memory means in which first image data based on which a predetermined image is displayed on the LCD is stored; second memory means in which second image data based on which the same image as the predetermined image is displayed on the LCD at lower lightness and darker hue than the predetermined image based on the first image data is stored; third memory means in which third image data based on which the same image as the predetermined image is displayed on the LCD in a darker achromatic color than the image based on the second image data is stored; and image data providing means for providing the LCD with any of the first image data, the second image data, and the third image data which is selected.
According to the aspects (9) and (10) of the present invention, the LCD is selectively provided with any of the first image data based on which the predetermined image is displayed, second image data based on which the same image as the predetermined image is displayed at lower lightness and darker hue than the predetermined image based on the first image data, and third image data based on which the same image is displayed in a darker achromatic color than the image based on the second image data. Consequently, the luminance of the LCD on which the same image is displayed can be changed among three levels.
According to the foregoing aspects of the present invention, preferably, a user selects image data to be provided for the LCD, and thus changes the luminance of the display screen of the LCD according to the user""s intention.
According to the foregoing aspects of the present invention, preferably, an amount of light to be emitted to the LCD from behind is varied in order to thus adjust an amount of illumination light and eventually control the luminance of the display screen of the LCD.
As described above, according to the present invention, an ultrasonic imaging system capable of lower the luminance of an LCD included in an operator console to a level suitable for a dark place is realized. Also realized is a display device capable of lowing the luminance of an LCD thereof to a level suitable for a dark place.
Further objects and advantages of the present invention will be apparent from the following description of the preferred embodiments of the invention as illustrated in the accompanying drawings.

Ultrasonic imaging system and display device

GE Medical Systems Global Technology Company, LLC


A substrate region of an n-channel MOS transistor is supplied with a bias voltage (VNBL) lower than a ground voltage (Vss) in a standby cycle, and with a bias voltage (VNBH) higher than the ground voltage in an active cycle. The difference between an internal power supply voltage (intVcc) and the bias voltage (VNBL) is at the level of a driving voltage (VPP) transmitted to a selected word line, while the arithmetic mean of the bias voltages (VNBL, VNBH) is substantially at the level of the ground voltage. A back gate voltage can be generated by a MOS transistor having gate insulating film breakdown voltage of the same degree as that of a memory cell transistor. Reliability of the gate insulating film of the MOS transistor of a back gate voltage generation circuit is improved, and the back gate voltage is readily generated on-chip.

1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly, it relates to a structure for implementing a high-speed operation and low power consumption in a semiconductor integrated circuit device including MOS transistors (insulated gate field effect transistors) as its components.
2. Description of the Background Art
Following densification of a semiconductor integrated circuit device such as logic and a memory circuit, elements are refined and it is necessary to reduce the power supply voltage in order to insure the breakdown voltage of these elements. If the semiconductor integrated circuit device is composed of MOS transistors, however, the driving speed for signal lines varies with the gate potentials of these MOS transistors (a so-called square characteristics of a drain current), and hence the operating speed of the circuit is reduced. In order to avoid such reduction of the operating speed, the absolute value of the threshold voltage Vth of each MOS transistor must be reduced. A value Vgs-Vth is increased to increase the drain current, where Vgs represents the gate-to-source voltage. Due to the reduction of the absolute value of the threshold voltage Vth, the MOS. transistor enters a conducting state at a fast timing for supplying the drain current, and high-speed charging/discharging of the signal line is implemented.
In general, the relation between the power supply voltage Vcc and the threshold voltage Vth with priority to the operating speed is expressed as follows, as shown in Advanced Electronics Series I-9, "VLSI Memory" by Itoh, Baifukan Shuppan, published on Nov. 5, 1994, p. 352, for example: EQU Vth=.alpha..multidot.Vcc
where .alpha. represents a constant which takes a value of 0.1 to 0.2. Assuming that the power supply voltage Vcc is 1 V, for example, the threshold voltage Vth is 0.1 to 0.2 V.
With priority to power consumption in a standby state, on the other hand, a subthreshold current must be taken into consideration. This subthreshold current is defined by a gate-to-source voltage in such a state that a constant drain current I0 starts to flow through a MOS transistor having a certain channel width (W0). This subthreshold current flows even if the gate-to-source voltage Vgs is 0 V. According to Kuroda et al., the subthreshold current as well as standby power are increased when the threshold voltage is reduced to no more than about 0.4 V (refer to Nikkei Microdevices, March 1995, p. 58).
FIG. 27 schematically illustrates changes of threshold voltages Vth of n-channel MOS transistors with respect to a potential difference VBS between a back gate (substrate regions) and a source. Referring to FIG. 27, curves T1 and T2 show threshold voltages Vth of n-channel MOS transistors, which are at the levels of 0.1 V and 0.28 V when the back gate-to-source potential differences VBS are 0 V respectively. Referring to FIG. 27, the axis of ordinates measures the threshold voltages VTh, and the axis of abscissas measures the back gate-to-source potential differences VBS. Each of these curves T1 and T2 is obtained in accordance with the following equation (1), on the assumption that a substrate effect constant K described later is 0.4: EQU Vth=VTH0+.vertline.K.vertline.(2.multidot..PHI.F-VBS.vertline.).sup.1/2 -(.vertline.2.multidot..phi.F.vertline.).sup.1/2 ! (1)
where VBS represents the back gate potential (back gate-to-source voltage) with reference to the source potential, K represents the substrate effect constant, .PHI.F represents the substrate surface potential, and VTH0 represents the threshold voltage obtained when the back gate-to-source potential difference VBS is 0 V.
As clearly understood from the characteristic curve T1 shown in FIG. 27, the threshold voltage Vth is increased when the back gate potential with reference to the source potential, i.e., the back gate-to-source voltage VBS is increased in the negative direction in the n-channel MOS transistor. For example, it is assumed that an n-channel MOS transistor having a threshold voltage Vth0 when the back gate-to-source voltage VBS is 0 V is formed by controlling the amount of implanted ions into the gate region of the n-channel MOS transistor (characteristic curve T1). In order to increase the threshold voltage Vth of this n-channel MOS transistor to 0.4 V, the back gate-to-source voltage VBS must be reduced to -1.71 V, from this characteristic curve T1. In other words, the threshold voltage of the n-channel MOS transistor can be changed by controlling the back gate-to-source voltage VBS.
FIG. 28 schematically illustrates the relations between gate potentials Vgs of n-channel MOS transistors with reference to source potentials and drain currents Ids. Referring to FIG. 27, the axis of abscissas measures the gate potentials (hereinafter referred to as gate voltages) with reference to the source potentials, and the axis of ordinates measures the drain currents in logarithmic scale. Characteristic curves TS1 and TS2 show drain currents flowing when the back gate-to-source voltages VBS are 0 V and -1.71 V respectively. Referring to the characteristic curves TS1 and TS2 shown in FIG. 28, substantially linear regions are called subthreshold regions.
Comparing the characteristic curves TS1 and TS2 with each other, it is clearly understood that the subthreshold current (drain current) flowing when the back gate-to-source voltage VBS is 0 V is larger than that flowing when the back gate-to-source voltage VBS is -1.71 V. When the back gate-to-source voltage VBS is 0 V, even when the gate voltage Vgs is low, a relatively large current flows due to reduction of the threshold voltage by 0.3 V. If an n-channel MOS transistor with the characteristic curves TS1 and TS2 in an active period, i.e., in a circuit operation and in a standby cycle respectively is employed, implemented is an n-channel MOS transistor operating at a high speed with a subthreshold current sufficiently suppressed in a standby state.
FIG. 29 illustrates an exemplary structure of a conventional back gate voltage switching circuit for an n-channel MOS transistor. Referring to FIG. 29, the back gate voltage switching circuit includes an invertor 5 operating with a power supply voltage Vcc on a power supply line 1 and a ground voltage Vss on a ground line 2 as operating power supply voltages, for inverting an activation signal SNB supplied on an input signal line 3 and outputting the inverted signal onto an output signal line 4, a level conversion circuit 10 converting the voltage level of the signal supplied from the invertor 5 onto the output signal line 4 to the level of the power supply voltage Vcc or a negative voltage VNBL, and a back gate driving circuit 15 outputting either the ground voltage Vss or the negative voltage VNBL in accordance with an output signal of the level conversion circuit 10.
A back gate voltage VNB from the back gate driving circuit 15 is supplied to a back gate (substrate region) of an n-channel MOS transistor Q included in an internal circuit 18 through an output signal line 16. The activation signal SNB indicates activation/inactivation of the internal circuit 18, and the internal circuit 18 operates when the activation signal SNB is at a high level, while remaining in an inactive state and holding a standby state when the signal SNB is at a low level.
The level conversion circuit 10 includes a p-channel MOS transistor 10a which conducts in response to the signal on the output signal line 4 for transmitting the power supply voltage Vcc on the power supply line 1 to an internal node 11a, a p-channel MOS transistor 10b which conducts in response to the activation signal SNB for transmitting the power supply voltage Vcc on the power supply line 1 to an internal node 11b, an n-channel MOS transistor 10c which conducts in response to the signal potential on the internal node 11b for transmitting a low-level back gate voltage VNBL on a back gate voltage supply line 14 to the internal node 11a, and an n-channel MOS transistor 10d which conducts in response to the signal potential on the internal node 11a for transmitting the low-level back gate voltage VNBL to the internal node 11b.
The back gate driving circuit 15 includes an n-channel MOS transistor 15a which conducts in response to the signal potential on the internal node 11a for transmitting the voltage Vss on a high-level back gate voltage supply line 17 to the output signal line 16, and an n-channel MOS transistor 15b which conducts in response to the signal potential on the internal node 11b for transmitting the low-level back gate voltage VNBL to the output signal line 16. The high-level back gate voltage supply line 17, which transmits a high-level back gate voltage, i.e., the ground voltage Vss, is equivalent to a ground line. The ground voltage Vss is 0 V, and the low-level back gate voltage VNBL is -1.71 V, for example. The term"back gate voltage" indicates a voltage measured with reference to the ground voltage. The operation of the back gate voltage switching circuit shown in FIG. 29 is now briefly described.
When the internal circuit 18 is in an inactive and standby state, the activation signal SNB is at a low level, and the signal outputted from the invertor 5 to the output signal line 4 goes high to the level of the power supply voltage Vcc. In this state, the p-channel MOS transistors 10a and 10b enter non-conducting and conducting states respectively, and the internal node 11b is charged by the p-channel MOS transistor 10b. In accordance with the potential increase of the internal node 11b, the n-channel MOS transistor 10c conducts to reduce the potential of the internal node 11a to the level of the negative back gate voltage VNBL. Following the potential reduction of the internal node 11a, the n-channel MOS transistor 10d enters a non-conducting state. Thus, the internal node 11b is charged to the level of the power supply voltage Vcc by the p-channel MOS transistor 10b, while the internal node 11a is discharged to the level of the negative back gate voltage VNBL.
The level of the negative back gate voltage VNBL is lower than the ground voltage Vss, and the n-channel MOS transistor 15a enters a non-conducting state, while the n-channel MOS transistor 15b receiving the power supply voltage Vcc at its gate conducts to transmit the low-level negative back gate voltage VNBL to the back gate of the n-channel MOS transistor Q included in the internal circuit 18 as the back gate voltage VNB. In the standby state of the internal circuit 18, therefore, the threshold voltage of the n-channel MOS transistor Q is increased to suppress a subthreshold current.
When the internal circuit 18 operates in an active cycle, on the other hand, the activation signal SNB goes high and the signal outputted from the invertor 5 onto the output signal line 4 is brought to the level of the ground voltage Vss. Thus, the p-channel MOS transistors 10a and 10b enter conducting and non-conducting states respectively. In this state, the n-channel MOS transistors 10c and 10d enter non-conducting and conducting states respectively contrarily to the aforementioned standby cycle, and the voltages of the internal nodes 11a and 11b are brought to the levels of the power supply voltage Vcc and the negative back gate voltage VNBL respectively. Therefore, the n-channel MOS transistors 15b and 15a enter non-conducting and conducting states, and the ground voltage Vss is supplied as the back gate voltage VNB. Thus, the threshold voltage of the n-channel MOS transistor Q of the internal circuit 18 is reduced so that the n-channel MOS transistor Q performs a switching operation at a high speed.
Also as to a back gate voltage for a p-channel MOS transistor included in the internal circuit 18, a similar effect can be attained by replacing the back gate voltage VNB for the n-channel MOS transistor Q with a voltage at the level of the power supply voltage Vcc or a higher level. As to the relation between the threshold voltage and the back gate-to-source voltage of the p-channel MOS transistor, the sign of the back gate-to-source voltage VBS may be inverted in each characteristic curve shown in FIG. 27, while subthreshold current characteristics of the p-channel MOS transistor can be obtained by inverting the sign of each gate voltage vgs shown in FIG. 28.
As hereinabove described, a high-speed operation in an active cycle and low power consumption in a standby cycle can be implemented by switching the back gate voltage for each MOS transistor depending on the operating cycle. However, the level conversion circuit 10, which is employed for switching the back gate voltage, changes the level of the signal changing between the power supply voltage Vcc and the ground voltage Vss to the level of the power supply voltage Vcc or the negative back gate voltage VNBL. In this case, the power supply voltage Vcc is applied to the gate of the n-channel MOS transistor 15b included in the back gate driving circuit 15 in the standby cycle of the internal circuit 18 with the activation signal SNB at a low level. Assuming that the power supply voltage is 1.0 V, the gate-to-source voltage of the n-channel MOS transistor 15n is Vcc-VNBL=1.0-(-1.71)=2.71 V, and it follows that a large voltage of 2.71 times the gate-to-source voltage (1.0 V) of an n-channel MOS transistor included in the invertor 5 is applied, for example.
Also in the level conversion circuit 10, the voltage of 2.71 V is applied between the gate and the drain of each of the non-conductive p-channel MOS transistors 10a and 10b while a voltage of 2.71 V is similarly applied between the gate and the source of each of conductive the n-channel MOS transistors 10c and 10d. Consequently, large electric fields are applied across respective insulating films of gate electrode parts of these MOS transistors, to disadvantageously reduce the reliability of the insulating films.
FIG. 30 illustrates another exemplary conventional back gate voltage switching circuit, which is shown in Nikkei Microdevices, March 1995, p. 59, for example. The back gate voltage switching circuit shown in FIG. 30 applies a back gate voltage VNB to a back gate of an n-channel MOS transistor.
Referring to FIG. 30, the back gate voltage switching circuit includes a p-channel MOS transistor 22 which is connected between a power supply line 20 transmitting a power supply voltage Vcc and an internal node 21 for receiving an activation signal /CE at its gate, a p-channel MOS transistor 24 which is connected between the internal node 21 and an internal node 23 and has a gate connected to a ground line 25 transmitting a ground voltage Vss, diodes 26a and 26b serially connected between the internal node 23 and an internal node 24, and an n-channel MOS transistor 28 which is connected between the internal node 24 and a back gate voltage transmission line 27 transmitting a low-level back gate voltage VNBL and has a gate connected to the ground line 25. The back gates of the MOS transistors 22 and 24 are connected to the power supply line 20, while that of the MOS transistor 28 is connected to the low-level back gate voltage transmission line 27.
The back gate voltage switching circuit further includes a p-channel MOS transistor 29a and an n-channel MOS transistor 29b forming an invertor which operates with the ground voltage Vss on the ground line 25 and the low-level back gate voltage VNBL on the low-level back gate voltage transmission line 27 as operating power supply voltages for inverting a signal on the internal node 24, and a p-channel MOS transistor 31a and an n-channel MOS transistor 31b forming an invertor for inverting an output signal transmitted from the invertor (the MOS transistors 29a and 29b) onto an internal node 30 and outputting a back gate voltage VNB onto a signal line 32. Back gates of the p-channel MOS transistors 29a and 31a are connected to the power supply line 20, and those of the n-channel MOS transistors 29b and 31b are connected to the low-level back gate voltage transmission line 27. The operation is now briefly described.
The MOS transistors 24 and 28 receive the ground voltage Vss at the gates thereof, and operate as resistive elements. The power supply voltage Vcc is equalized in absolute value with the low-level back gate voltage VNBL. The power supply voltage Vcc is 2.0 V, for example, and the low-level back gate voltage VNBL is -2.0 V.
When the activation signal /CE is at a high level and an internal circuit is an inactive and standby state, the MOS transistor 22 is in a non-conducting state and the node 24 is held at the level of the low-level back gate voltage VNBL by the MOS transistor 28. In response to this, the MOS transistors 29a and 29b enter conducting and non-conducting states respectively, and the voltage on the internal node 30 is brought to the level of the ground potential Vss. In response to the ground voltage Vss on the internal node 30, the MOS transistors 31a and 31b enter non-conducting and conducting states respectively, and the back gate voltage VNB from the signal line 32 is brought to the level of the low-level back gate voltage VNBL. Thus, the back gate voltage of the n-channel MOS transistor included in the internal circuit is brought to the level of the low-level back gate voltage VNBL, and its threshold voltage is increased.
When the activation signal /CE is at a low level and the internal circuit operates in an active cycle, on the other hand, the MOS transistor 22 conducts to transmit the power supply voltage Vcc to the node 23. Due to level shifting by the diodes 26a and 26b, the voltage of the node 24 exceeds the level of the ground voltage Vss, the MOS transistors 29a and 29b enter non-conducting and conducting states respectively, and the voltage on the internal node 30 is brought to the level of the low-level back gate voltage VNBL. In response to this, the MOS transistors 31b and 31a enter non-conducting and conducting states respectively, and the back gate voltage VNB on the signal line 32 is brought to the level of the ground voltage Vss. Thus, the n-channel MOS transistor of the internal circuit has the threshold voltage decreased, to attain a high-speed operation.
In the back gate voltage switching circuit shown in FIG. 30, a level shift circuit employing the diodes 26a and 26b prevents application of a voltage of the sum of the power supply voltage Vcc and the absolute value of the low-level back gate voltage VNBL between the gate and the source of each MOS transistor, thereby ensuring the reliability of the element.
In the structure shown in FIG. 30, however, a current path from the power supply line 20 to the low-level back gate voltage transmission line 27 is formed when the activation signal /CE goes low, and a current flows from the power supply line 20 to the line 27 in an active cycle. Thus, the level of the low-level back gate voltage VNBL is increased, and in order to absorb this voltage increase, the low-level back gate voltage VNBL is required to be supplied from the exterior. In case of generating the low-level back gate voltage VNBL on chip, it is necessary to absorb the current flowing through the current path formed by the MOS transistors 22 and 24, the diodes 26a and 26b and the transistor 28 and hold the back gate voltage VNBL at a constant voltage level. Thus, it is necessary to employ a back gate voltage generation circuit having high current drivability, with a large occupying area. When such a back gate voltage generation circuit having high drivability is employed, current consumption of the circuit is increased and an unnecessary current is consumed. Thus, the structure of the back gate voltage switching circuit shown in FIG. 30 is unsuitable for employment in an on-chip back gate voltage generation circuit.
FIG. 31 illustrates the structure of still another exemplary back gate voltage switching circuit, which is described in Japanese Patent Laying-Open No. 6-21443 (1994), for example. The back gate voltage switching circuit shown in FIG. 31 includes a switching circuit 35 selecting one of a positive voltage Vb and a ground voltage Vss in accordance with a standby detection signal SD. The voltage selected by the switching circuit 35 is supplied to a back gate of an n-channel MOS transistor 40a which is a component included in an internal circuit 40.
When the standby detection signal SD indicates that the internal circuit 40 is in the standby state, the switching circuit 35 selects the ground voltage Vss and supplies the same to the back gate of the MOS transistor 40a. When the standby detection signal SD indicates an active cycle of the internal circuit 40, on the other hand, the switching circuit 35 selects the positive voltage Vb and supplies the same to the back gate of the MOS transistor 40a.
In the structure shown in FIG. 31, a back gate voltage is formed by the positive back gate voltage Vb or the ground voltage Vss, and no large voltage is generated in back gate switching (the difference between a power supply voltage Vcc and the back gate voltage Vb is smaller than the power supply voltage Vcc). When a threshold voltage Vth of the MOS transistor 40a is changed by switching the back gate voltage between the positive voltage Vb and the ground voltage Vss through the switching circuit 35 shown in FIG. 31, however, the following problems arise:
Consider that the threshold voltage Vth of the MOS transistor 40a is brought to 0.1 V when a back gate-to-source voltage VBS is at the level of the positive voltage Vb and brought to 0.4 V when the back gate-to-source voltage VBS is 0 V. As shown in FIG. 32, the value of the voltage Vb, which cannot exceed a built-in voltage (diffusion potential) of 1.0 V of a P-N junction, is smaller than 1.0 V. In order to satisfy the threshold voltage conditions required in case of employing this voltage Vb, therefore, it is necessary to implement a characteristic curve T3 having a considerably steep gradient. In this case, a substrate effect constant K must be increased, from the previous equation (1). This substrate effect constant K is generally expressed as follows: ##EQU1## where tox represents the thickness of a gate insulating film, .epsilon.ox represents the dielectric constant of the gate insulating film, .epsilon.si represents the dielectric constant of a silicon film, NB represents the impurity concentration of a substrate, and q represents a unit electric charge quantity. In order to increase the substrate effect constant K, therefore, the impurity concentration of a substrate region must be increased. Thus, a depletion layer is narrowed, a gate capacitance is increased in response to this, and high-speed operation can not be performed. When the width of the depletion layer is reduced, electric field intensity across this P-N junction, which is inversely proportional to the depletion layer width, is increased, the break-down voltage of the P-N junction is reduced, and the reliability of the element is deteriorated.
When the impurity concentration of the substrate region is increased, further, a diffusion current is generated in proportion to the difference between the impurity concentration of the substrate region and that in a source/drain impurity region of the MOS transistor, and a reverse current (current flowing when a reverse-biased voltage is applied across the P-N junction) is increased in response, to disadvantageously destroy data stored in a memory cell when this MOS transistor is a memory cell transistor, for example. In addition, a leakage current is increased by this reverse current, to disadvantageously increase current consumption.
In case of setting the threshold voltage Vth in accordance with the characteristic curve T3 as shown in FIG. 32, the threshold voltage Vth is remarkably changed by a slight change of the back gate-to-source voltage VBS, and it is difficult to precisely establish a prescribed threshold voltage. When the back gate-to-source voltage VBS is applied in accordance with the characteristic curve T1, on the other hand, the characteristic curve T1 is so gradually changed that the threshold voltage Vth is changed at a rate sufficiently smaller than that of the characteristic curve T3 even if the back gate-to-source voltage VBS is slightly changed. Thus, a prescribed threshold voltage Vth can be stably established.

Semiconductor integrated circuit device operating at high speed with low current consumption


Provided are a pixel circuit and a drive method thereof, a display panel and a display device. The pixel circuit includes: a drive transistor, a storage capacitor, a data writing module, a threshold compensation module, and an organic light emitting element. The data writing module is electrically connected to a gate of the drive transistor and a first plate of the storage capacitor, and is configured to write a data signal to the gate of the drive transistor and the first plate of the storage capacitor at a data writing phase. The threshold compensation module is electrically connected to a second plate of the storage capacitor, and is configured to adjust a potential of the second plate of the storage capacitor to a first potential at the data writing phase, and adjust the potential of the second plate of the storage capacitor to a second potential.

The Organic Light Emitting Diode (OLED) display has the advantages of self-lamination, low drive voltage, high luminous efficiency, short response time, flexible display, etc., and is a display with the most potential development at present.
An OLED element of the OLED display is a current-driven element, and a corresponding pixel drive circuit needs to be provided to supply a drive current to the OLED element so that the OLED element can emit light. The pixel drive circuit of the OLED display generally includes a drive transistor, a switching transistor, and a storage capacitor, wherein the drive transistor is capable of generating the drive current to drive the OLED element according to a voltage of a gate thereof. However, due to the drive process and device aging, a threshold voltage of the drive transistor in the pixel drive circuit may drift, which causes display non-uniformity.

Pixel circuit and drive method thereof, display panel, and display device

Wuhan Tianma Micro-Electronics Co., Ltd.


Embodiments of the present invention provide methods, systems, apparatuses, and computer program products for determining delivery or pick-up windows. In one embodiment a method is provided comprising determining whether sufficient historical information/data to determine an estimated pick-up/delivery time is received for each weekday when deliveries are made and in response to determining that the sufficient historical information/data is available for a first weekday, determining an estimated pick-up/delivery time for the first serviceable point and for the first weekday based on the sufficient historical information/data for the first serviceable point and for the first weekday. Similarly, in response to determining that the sufficient historical information/data is not available for a second weekday, determining an estimated pick-up/delivery time for the first serviceable point and for the second weekday based on the first historical information/data.

Carriers often handle millions of pick-ups and deliveries on daily basis. Carriers typically arrange delivery of items or mail between a consignor/shipper and a consignee/recipient. The carrier is typically responsible for delivering items in a timely manner. As part of their services, carriers may provide customers (consignors/shippers and/or consignees/recipients) with an estimated window for picking up or delivering one or more items. Customers may rely on the estimated window for organizing various personal and business aspects. For example, merchant customers may rely on the estimated window to prepare equipment or personnel staffing based on the expected inventory at a particular time. Similarly, for items that require a recipient signature, customers may rely on the estimated delivery window to ensure that a person is present at a delivery location at a time of delivery. Accordingly, there is a dire need in the market for ways to provide highly accurate estimated windows for pick-ups and/or deliveries. Although the estimated windows are described in the transportation and logistics context, embodiments described herein have wide applicability outside of this context.

Determining estimated pick-up/delivery windows using clustering


A sense amplifier circuit for use in a semiconductor memory device has complemented logic states at opposite sides of the latch circuit in the sense amplifier circuit determinate all the time in operation. The sense amplifier circuit takes advantage of a current mirror circuit for ascending or descending a voltage level at the gate of a transistor by charge accumulation or charge dissipation, which turns on or off the transistor so as to control the logic states at opposite sides of the latch circuit in the sense amplifier circuit.

1. Field of the Invention
The present invention relates in general to a sense amplifier circuit, and more particularly, to a sense amplifier circuit having current mirror architecture for semiconductor memory devices.
2. Description of the Prior Art
Since semiconductor memory devices (for example, flash memory, DRAM and SRAM, etc) have always been one of the most important components for electronic appliances, the performance of memory devices is highly demanded and is improving uninterruptedly.
Please refer to FIG. 1, which is a circuit diagram schematically showing the structure of a prior art sense amplifier circuit 100. The sense amplifier circuit 100 comprises a first current sensing unit 110, a second current sensing unit 130, and a latch circuit 150. The first current sensing unit 110 comprises NMOS transistors 111, 113 and 115, a PMOS transistor 117, and a first non-volatile memory unit 119. The second current sensing unit 130 comprises NMOS transistors 131, 133 and 135, a PMOS transistor 137, and a second non-volatile memory unit 139. The first non-volatile memory unit 119 comprises a PMOS transistor 123 and a first non-volatile memory device 121. The second non-volatile memory unit 139 comprises a PMOS transistor 143 and a second non-volatile memory device 141. The first and second non-volatile memory devices 121 and 141 are embedded memory cells, which can be floating-gate (FG) PMOS embedded memory cells.
The first and second current sensing units 110 and 130 are both coupled between a high bias supply Vdd and a low bias supply Vss. The latch circuit 150 comprises two inverters 151 and 153 coupled in series, with the output of one inverter electrically connected back to the input of the other inverter. The latch function of the pair of cross-coupled inverters 151 and 153 is a well-known prior art and, for the sake of brevity, further discussion is omitted.
The NMOS transistors 111 and 131 are turned on or off in response to a control signal RE. The NMOS transistors 113 and 133 together with the PMOS transistors 117 and 137 are turned on or off in response to a control signal ZRE. The PMOS transistors 123 and 143 are turned on or off in response to a control signal SG. The control signal ZRE is defined to be the complement of the control signal RE.
While performing a read operation, two consecutive steps, assumed to be a first step and a second step, corresponding to different control situations are required to complete the read operation. For explanation, the first non-volatile memory device 121 is assumed to be a programmed memory device and the second non-volatile memory device 141 is assumed to be an erased memory device. During the first step, the control signals RE and SG are activated and the control signal ZRE is deactivated. The term "activated" describes one signal state that assumes a high logic level, and the term "deactivated" describes the other signal state that assumes a low logic level. Accordingly, during the first step, the PMOS transistors 123 and 143 are turned off by the control signal SG, the NMOS transistors 111 and 131 are turned on by the control signal RE, the PMOS transistors 117 and 137 are turned on by the control signal ZRE and the NMOS transistors 113 and 133 are turned off by the control signal ZRE. Based on the situation in the first step, the voltage levels at nodes N1 and N2 are both pulled down to the low voltage level Vss, and the voltage levels at nodes N3 and N4 are both pulled up to the high voltage level Vdd.
During the second step, the control signals RE and SG are deactivated and the control signal ZRE is activated. Accordingly, during the second step, the PMOS transistors 123 and 143 are turned on by the control signal SG, the NMOS transistors 111 and 131 are turned off by the control signal RE, the PMOS transistors 117 and 137 are turned off by the control signal ZRE and the NMOS transistors 113 and 133 are turned on by the control signal ZRE. Based on the situation in the second step, a first current I1 is generated through the first non-volatile memory unit 119, and a second current I2 is generated through the second non-volatile memory unit 139. Therefore, the voltage level at node N1 is boosting owing to the charge accumulation resulting from the first current I1 forwarded to the node N1, and the voltage level at node N2 is boosting owing to the charge accumulation resulting from the second current I2 forwarded to the node N2.
When the first current I1 is higher than the second current I2, the charge-accumulating rate at node N1 is also higher than that at node N2, which means that the voltage level at node N1 is boosting faster than that at node N2. Accordingly, the voltage level at node N1 is able to achieve a threshold voltage for turning on the NMOS transistor 115 precedent to that for turning on the NMOS transistor 135, which results in pulling down the voltage level at node N3 to the low voltage level Vss and the inverter 151 in turn will output a high voltage level Vdd at node N4. On the contrary, when the second current I2 is higher than the first current I1, the voltage level at node N4 is pulled down to the low voltage level Vss and the inverter 153 will output a high voltage level Vdd at node N3.
The prior art sense amplifier circuit 100 is featured by that the latch circuit 150 is latched by turning on an NMOS transistor through accumulating charge for overcoming the threshold voltage. As a result, the current difference between the first current I1 and the second current I2 is not necessary to be significant and high noise-immunity can be achieved. However, during the first step, the voltage levels at nodes N3 and N4 are both pulled up to the high voltage level Vdd. Furthermore, during the second step, the voltage levels at nodes N3 and N4 are both floated before the latch circuit 150 is latched, which means that the voltage levels at nodes N3 and N4 are both indeterminate before finishing the latch operation. That is to say, if the voltage levels at N3 and N4 are required to be always complemented to each other and be determinate before finishing the latch operation, the aforementioned prior art sense amplifier circuit cannot meet the requirements.

Sense amplifier circuit having current mirror architecture


The present invention provides a vector containing a DNA construct containing a first promoter that is a nitrilase gene promoter, a multicloning site and a nitrilase transcription regulatory protein gene (particularly preferably a structural gene is ligated into a multicloning site and a second promoter is placed at the upstream of the nitrilase transcription regulatory protein gene), and the like. The present invention affords a high expression system capable of expressing a large amount of useful proteins by actinomycete host represented by actinomycete belonging to the genus Streptomyces and the like beneficially used for the production of useful proteins.

The genus Streptomyces has been widely employed for industrial use as antibiotics-producing bacteria and has become an extremely important bacterial group for applied microbiology of today. In view of the significance of the production of useful substances by the genus Streptomyces, development of an inducible large-scale expression system capable of controlling the expression in actinomycete is desired. The present inventors have already obtained an inducible expression system for a protein (nitrilase) derived from Rhodococcus rhodochrous J1 (FERM BP-1478), which is one species of the actinomycete (JP-A-9-28380, and Proceedings of the National Academy of Sciences USA, October 1996, No. 93, pp. 10572-10577). This expression system expresses nitrilase (enzyme decomposing nitrile into acid and ammonia) in a large amount of not less than 35% of the total soluble protein in a cell-free extract, when isovaleronitrile is added to a medium as an inducer. In other words, an inducible promoter with an extremely potent transcription activity is involved in this expression system.
However, this finding concerns only a part of the actinomycete: Rhodococcus rhodochrous J1 strain, and there is no report or even a suggestion to date if a similar expression system can be utilized for actinomycetes belonging to other genera, particularly the genus Streptomyces, whose importance has been pointed out for the above-mentioned reasons.


The production of semiconductor devices manufactured through a plurality of manufacturing sites is unitarily managed and an appropriate production plan is instructed. A computer projects a production plan of an entire company based on various information. The production plan is provided to each manufacturing site as a production instruction and provided to each business person or customer as a storing reply or an order accepting period reply. If the projected production plan (possible production volume) does not coincide with a production plan (necessary production volume), parameters obtained by correcting production allocation, production capability, lead time, yield and the like are re-input from a parameter input terminal. Based on the corrected parameters, the computer re-projects the production plan and projects an optimum production plan.

In manufacturing a semiconductor device, there are a pre-process for forming semiconductor elements and wiring patterns and the like on a semiconductor wafer, and a post-process for dicing the semiconductor wafer into semiconductor chips, packaging and assembling them into a finished product. To perform processings of the pre-process and the post-process, it is known that a plurality of manufacturing processes and manufacturing sites (manufacturing factories) are prepared and that the manufacturing processes are divided among the factories.

This patent is subject to a terminal disclaimer.


The present invention relates to a booster circuit which uses multiple pump circuits to provide high voltages. The pump circuits are provided with an input voltage Vcc and are generally each made up of a diode and a capacitor. A node driving circuit provides driving signals to driving nodes and thereby to the pump circuits. The driving nodes are connected by a charge transfer switch which is selectively activated so as to allow charge that would otherwise be lost to ground to be conserved for inclusion in the final high-output voltage.

The present invention relates to a booster circuit used for a flash memory or the like.
Generally, to write/erase data in/from a flash memory, channel hot electrons or a tunnel current is used. For this purpose, a high voltage is required because a high electric field must be applied to the gate. Conventionally, a terminal for supplying a high external voltage is arranged independently of the power supply terminal. In recent years, however, a single power supply is used to simplify the external power supply circuit. The power supply voltage to be supplied is conventionally often 5 V, though it is lowering to 2 or 3 V to reduce the power consumption or increase the operation speed. The memory chip incorporates a booster circuit for generating a voltage higher than the externally supplied power supply voltage, and recently, the boosting ratio need be higher than the conventional one.
FIG. 16 shows a booster circuit disclosed in Japanese Patent Laid-Open No. 9-8229 (to be referred to as prior art 1 hereinafter). This booster circuit comprises diodes D1 to D5, capacitors CP1 to CP4, a capacitive load CL, and driving circuits DV1 and DV2.
Referring to FIG. 16, a circuit constituted by, e.g., the diode D2 and the capacitor CP2 is called a pump circuit PC. The booster circuit shown in FIG. 16 has four pump circuits PC. Nodes between the diodes D1 to D4 and the one-terminal sides of the capacitors CP1 to CP4 are represented by N1 to N4, respectively; a node between the diode D5 and the load capacitor CL, NL; and nodes between the capacitors CP1 and CP2 and the output terminals of the driving circuits DV1 and DV2, N181 and N182, respectively.
Connection in the booster circuit shown in FIG. 16 will be described next. The anode side of the diode D1 is connected to the power supply, and the cathode side is connected to the capacitor CP1 through the node N1 to form the first pump circuit. The anode side of the diode D2 is connected to the node N1, and the cathode side is connected to the capacitor CP2 through the node N2 to constitute the second pump circuit. In a similar manner, a plurality of pump circuits, i.e., the third and fourth pump circuits respectively constituted by the diodes D3 and D4 and the capacitors CP3 and CP4 are connected in series.
The other terminal of each of the odd-numbered capacitors CP1 and CP3 counted from the first pump circuit is connected to the driving node N181. The other terminal of each of the even-numbered capacitors CP2 and CP4 counted from the first pump circuit is connected to the driving node N182.
A two-phase clock signal .phi.181 and a clock .phi.182 as the inverted signal of the clock .phi.181, which have timings as shown in FIGS. 17A and 17B, are supplied to the outputs, i.e., the driving nodes N181 and N182 of the driving circuits DV1 and DV2, respectively. The driving nodes N181 and N182 for the capacitors CP1 and CP3 and the capacitors CP2 and CP4 are alternately driven in opposite phases, thereby outputting a high voltage from an output terminal Voz. In the arrangement shown in FIG. 16, a voltage five times higher than a power supply voltage Vcc is obtained. Note that the capacitor CP is called a pump capacitance.
The operation of this circuit will be described next in more detail with reference to FIGS. 16, 17A, and 17B.
For the descriptive convenience, assume that the circuit is constituted by two pump circuits, the load capacitor CL is connected to the node N3, the power supply voltage Vcc is 4 V, the capacitors CP1 and CP2 have the same capacitance value as that of the load capacitor CL, the threshold value of the diodes D1 to D3 is 0 V, and low and high levels of the clocks .phi.181 and .phi.182 are 0 V and 4 V, respectively.
In the initial state at time T180, the driving nodes N181 and N182 are at 0 V, and the nodes N1, N2, and NL are at 4 V because the power supply voltage Vcc is supplied through the diodes D1 to D3. As a result, the output voltage Voz is also 4 V.
At time T181, the clock .phi.181 rises to set the driving node N181 at 4 V. The voltage at the node N1 temporarily changes from 4 V to 8 V and immediately stabilizes at 5.3 V because charges flow to the nodes N2 and NL through the diodes D2 and D3. This is because charges accumulated in the capacitor CP1 are distributed to the capacitor CP2 and the load capacitor CL.
The clock .phi.182 does not change, and the driving node N182 also maintains 0 V.
At time T182, the clock .phi.181 falls to set the driving node N181 at 0 V. Charges stored on the N181 side of the capacitor CP1, which correspond to 4 V, are removed through the driving circuit DV1.
Simultaneously, the voltage on the node N1 side of the capacitor CP1 lowers from 5.3 V to 1.3 V and then rises to 4 V because of supply of the power supply voltage Vcc through the diode D1. Letting C (F) be the electrostatic capacitance of the capacitor CP1, the loss charge amount due to this discharge is given by C.times.Vcc (coulomb).
On the other hand, the clock .phi.182 rises to set the driving node N182 at 4 V. The voltage on the node N2 side of the capacitor CP2 temporarily becomes 9.3 V because 4 V is added to 5.3 V. However, since the diode D3 is turned on to transfer charges to the load capacitor CL, the node N2 side stabilizes at 7.3 V, and the output voltage Voz also becomes 7.3 V.
At time T183, the clock .phi.181 rises again to repeat the same operation as at time T181.
On the other hand, when the clock .phi.182 falls, the driving node N182 is set at 0 V, and charges stored on the driving node N182 side of the capacitor CP2 are removed through the driving circuit DV2. Letting C (F) be the electrostatic capacitance of the capacitor CP2, the loss charge amount due to this discharge is given by C.times.Vcc (coulomb).
This boost operation is repeated, and the output terminal Voz finally converges to 12 V. Since discharge is performed twice in one period, the loss charge amount for one period is C.times.Vcc.times.2 (coulomb). Since Vcc is 4 V, the loss charge amount is 8C (coulomb).
In prior art 1, letting Z be the number of pump circuits, the boost voltage is generally given by (Z+1).times.Vcc, and the loss charge amount is given by Z.times.C.times.Vcc (coulomb). Therefore, the loss charge amount per unit boost ratio is represented by {Z/(Z+1)}.times.C.times.Vcc (coulomb).
FIG. 18 shows another conventional booster circuit (to be referred to as second prior art hereinafter) disclosed in "1996 Symposium on VLSI Circuits Digest of Technical Papers", pp. 110-111. FIG. 18 shows the circuit in mode 2. This booster circuit is of a full-wave rectification type and aims at increasing the current amount to be output from the booster circuit and reducing the power consumption by recycling some removed charges.
The booster circuit of prior art 2 comprises PMOS transistors M1 and M4, NMOS transistors M2, M3, M5, M6, M7, and M8, drivers DV201 and DV202 for inverting an input signal and outputting the inverted signal, diodes D201 and D202, and capacitors C201 to C204. Nodes between the transistors M1 and M2, between the transistors M2 and M3, between the transistors M5 and M7, and between the transistors M6 and M8 are represented by N201, N202, N203 and N205, respectively.
The connection relationship in the circuit of prior art 2 shown in FIG. 18 will be described.
A clock .phi.201 is connected to the gate of the transistor M2 and to the gate of the transistor M4 through the driver DV202. A clock .phi.202 is connected to the gate of the transistor M3 and to the gate of the transistor M1 through the driver DV201.
The source of the transistor M1 is connected to a power supply Vcc while the drain is connected to the drains of the transistors M2 and M4 and the capacitor C201 at the node N201. The source of the transistor M3 is connected to ground GND while the drain is connected to the sources of the transistors M2 and M4 and the capacitor C202 at the node N202.
Each of the nodes N203 and N204, i.e., the other terminal of each of the capacitors C201 and C202, is connected to the source of the corresponding one of the transistors M5 and M6 and the drain of the corresponding one of the transistors M7 and M8. The drains of the transistors M5 and M6 and the anodes of the diodes D201 and D202 are connected to the power supply Vcc. The cathode of the diode D201 is connected to the gates of the transistors M5 and M8 and the capacitor C203. The cathode of the diode D202 is connected to the gates of the transistors M6 and M7 and the capacitor C204. The other terminal of each of the capacitors C203 and C204 is connected to the corresponding one of clocks .phi.203 and .phi.204. The sources of the transistors M7 and M8 are connected to a load capacitor CL at a node NL.
The operation of prior art 2 will be described next with reference to the timing charts of FIGS. 19A to 19H.
For the descriptive convenience, in FIGS. 19A to 19H, assume that the power supply voltage Vcc is 4 V, and the capacitors C201 and C202 have the same capacitance value C (F) as that of the load capacitor CL. In addition, the threshold value of the transistors M1 to M8 is 0 V, and low and high levels of the clocks .phi.201 to .phi.204 are 0 V and 4 V, respectively.
The clocks .phi.201 to .phi.204 have the same frequency. The clock signals .phi.201 and .phi.202 have a phase difference corresponding to 1/2 the period, and so do the clock signals .phi.203 and .phi.204. The clock signals .phi.203 and .phi.204 go high when a predetermined time has elapsed after the clock signals .phi.201 and .phi.202 change to high level, respectively, and then simultaneously go low.
At transient time T200, assume that the node N201 is at 4 V (Vcc), the node N202 is at 0 V (GND), the node N203 is at about 5 V (Vpp), and the node N204 at 4 V (Vcc).
At time T201, since the clock signal .phi.201 goes high while the clock signal .phi.202 is at low level, the outputs from the driver DV201 and DV202 are at high and low levels, respectively. At this time, the transistors M1 and M3 are turned off, and the transistors M2 and M4 are turned on. Consequently, charges corresponding to 4 V which are stored on the node N201 side of the capacitor C201 move, through the transistors M2 and M4, to the node N202 side of the capacitor C202 which is being discharged to 0 V, so both the nodes N201 and N202 are set at 2 V (1/2.times.Vcc). On the other hand, charges corresponding to 5 V (Vpp) which are stored on the node N203 side of the capacitor C201 decrease by 2 V to 3 V (Vpp-1/2.times.Vcc). Charges corresponding to 2 V are added to the node N204 side of the capacitor C202 which is being charged to 4 V, so the node N204 is set at 6 V (3/2.times.Vcc).
At time T202, the clock signal .phi.203 goes high while the clock signal .phi.201 is at high level and the clock signal .phi.202 is at low level. The transistors M5 and M8 are turned on. As a result, the charges corresponding to 6 V (3/2.times.Vcc), which are stored on the node N204 side of the capacitor C202, are distributed to the load capacitor CL through the transistor M8, and the voltage converges to 5.5 V (Vpp). The node N203 side of the capacitor C201, which is being discharged to 3 V (Vpp-1/2.times.Vcc), is charged to 4 V, i.e., the power supply voltage Vcc through the transistor M5.
After this, the clocks .phi.201 and .phi.203 go low, and the transistors M2, M4, M5, and M8 are turned off. The voltage at each node is kept unchanged.
At time T203, the clock signal .phi.202 goes high, and the outputs from the drivers DV201 and DV202 are set at low and high levels, respectively. At this time, the transistors M1 and M3 are turned on, and the transistors M2 and M4 are turned off. The node N201 side of the capacitor C201 is charged to the power supply voltage Vcc of 4 V through the transistor M1. The node N202 side of the capacitor C202, which is being charged to 2 V, is set at GND, i.e., 0 V through the transistor M3.
On the node N203 side of the capacitor C201, which is being charged to 4 V, charges corresponding to 2 V are added to set the node N203 at 6 V (3/2.times.Vcc). On the node N204 side of the capacitor C202, which is being discharged to 5.5 V (Vpp), charges corresponding to 2 V are removed to set the node N204 at 3.5 V (Vpp-1/2.times.Vcc).
At time T204, the clock .phi.204 goes high while the clocks .phi.201 and .phi.202 are set at low and high levels, respectively, so the transistors M6 and M7 are turned on. As a result, charges corresponding to 6 V (3/2.times.Vcc), which are stored on the node N203 side of the capacitor C201, move to the load capacitor CL through the transistor M7 and the node NL, so the voltage converges to 5.75 V (Vpp). The node N204 side of the capacitor C202, which is being discharged to 3.5 V, is charged to the power supply voltage of 4 V through the transistor M6.
After this, the clocks .phi.202 and .phi.204 go low, and the transistors M1, M3, M6, and M7 are turned off. The voltage at each node is held.
By repeating this operation, the load capacitor CL is gradually charged to a higher voltage, and the output voltage Vpp finally converges to 6 V.
In the booster circuit of prior art 2, charges corresponding to the power supply voltage Vcc, which are stored in the capacitor C201, are distributed to the capacitor C202 through the transistors M2 and M4, and charges corresponding to 1/2.times.Vcc are stored in the capacitor C202. These charges are removed to the ground GND in response to the next clock. In this case, the loss charge amount for one period is C.times.Vcc/2 (coulomb). When Vcc is 4 V, the loss charge amount is 2C (coulomb). The loss charge amount per unit boost ratio is given by 1/3.times.C.times.Vcc (coulomb).
In the above-described booster circuit of prior art 1, the charge/discharge amount of the capacitor CP by switching is large, and charges corresponding to C.times.Vcc (coulomb) are lost per capacitor CP in one clock period. When four capacitors are arranged as in prior art 1, the loss becomes C.times.Vcc.times.4 (coulomb). This loss increases as the boost ratio of the booster circuit becomes high. Therefore, the power consumption of the circuit undesirably increases.
In the booster circuit of prior art 2, the pump circuit is connected to allow a bidirectional operation such that the boost operation is performed twice in one clock period, thereby increasing the current capacitance. In addition, since the transistors M2 and M4 are arranged, charges stored in the capacitor C201 are not grounded but used to charge the capacitor C202, and then the capacitor C202 is discharged. With this arrangement, the loss charge amount can be reduced, and consequently, the power consumption of the booster circuit can be decreased.
In the booster circuit of prior art 2, however, the voltage at the driving nodes N201 and N202 changes only by Vcc/2. Charges corresponding to only Vcc/2 can contribute to the boost operation, so no high voltage can be obtained. Therefore, the booster circuit of prior art 2 cannot be used for a write/erase in/from a flash memory because the voltage is too low, although it can be used as a write voltage for a memory cell of a DRAM.
In addition, the node N201 of the capacitor C201 must be switched between 0 V and 4 V by the transistors M1 and M2. The node N203 must be driven by the transistors M5 and M8 with a gate voltage of 2.times.Vcc, i.e., 8 V by using the capacitor C203 and the diode D201 to decrease the ON resistance of the transistors M5 and M8, and be switched at a voltage higher than the power supply voltage. In this circuit arrangement, the number of devices increases, resulting in a complex circuit arrangement.
Furthermore, prior art 2 does not disclose an arrangement for realizing a boost ratio of 3 or more. As one arrangement for realizing a boost ratio of 3 or more, a plurality of booster circuits of prior art 2 are prepared, and the output from an output terminal OUT of a preceding stage is supplied to the power supply terminal Vcc of the next stage. However, since the voltage becomes high toward the last stage, the breakdown voltage of a transistor M or diode D to be used must be increased. This increases the size of each device, although the number of devices per stage is large to already result in a large chip size.


A high efficiency method of processing images to provide perceptual high-contrast output. Pixel intensities are calculated by a weighted combination of a fixed number of static bounding rectangle sizes. This is more performant than incrementally growing the bounding rectangle size and performing expensive analysis on resultant histograms. To mitigate image artifacts and noise, blurring and down-sampling are applied to the image prior to processing.

Electronic magnification devices use a combination of optical and digital magnification to allow access to video information for low vision individuals. Digital magnification of real-world images and video blurs the edges of the content. Further, any objects that have low contrast with the background are difficult to see. This effect becomes worse with magnification. Image processing, specifically contrast and edge detection are possible but often require intensive processing not available on mobile devices.

High efficiency dynamic contrast processing


An oscillating-foil type underwater propulsor with a joint provided in the invention, the propulsor including a streamline foil having a foil surface being parallel to a water surface and a span length of at least twice as long as an average chord length of the streamline foil, and a heaving mechanism undergoing heaving motion perpendicular to a propulsion direction of the propulsor and having a transmission section, wherein the transmission section is pivotally connected to the streamline foil to form a joint, the joint being provided at the middle of the span length and having a rotation center located within a circular area, which has a radius of one third of the average chord length and is centered at the point one third of the average chord length ahead of the lifting center of the streamline foil.

1. Field of the Invention
The invention relates generally to an underwater propulsor, in particular to an oscillating-foil type underwater propulsor with a joint. The underwater propulsor of the invention mimics the tail movement of fast moving cetaceans or tunas and provides an oscillating foil and a joint for achieving better propulsion efficiency.
2. Description of Related Art
Regarding conventional underwater propulsors, there are a variety of applications such as flippers for diving or snorkeling, paddles for canoeing or Chinese dragon boats, and propellers of container ships or ocean liners. As an auxiliary equipment to facilitate propulsion, the flippers have long been important in the history of human underwater activities. Such a flipper has an appearance resembling the webbed toes of a frog, but it actually functions like a tail fin of slow moving fish. For a flat structure such as the flipper, the flat structure can easily cause early flow separation and stall when used as a propulsor in a fluid medium because it does not have a thicker foil thickness and a larger curvature radius of the leading edge of a high performance streamline foil, making it an inferior device for providing lift and taking load. Besides, the flipper also is a soft or non-rigid structure, which is prone to deformation and unable to take or transmit a larger thrust. Therefore, the flipper produces a very limited thrust in practical use.
The main propulsion method used in ships today is by the use of propellers. The marine main engine transfers the kinetic power through a shaft to the propeller, the blades of which then rotate to push the water backwards to generate a forward thrust, so that the ship is propelled. During the rotation of the fins, however, water surrounding the fins travels in a circumferential direction, which is almost helpless in facilitating the propulsion of the ship and becomes energy loss. For a conventional screw propeller, this problem has been a major barrier to further significant improvement of propulsion efficiency.
Furthermore, the screw propeller has another disadvantage, which is low maneuverability. When the mechanical power of the marine main engine is transferred to the propeller through the shaft fixed to the hull of the ship, the direction of the thrust produced by the propeller may not be controlled due to the fixed-positioned shaft. Therefore, the propeller by itself can only produce forward and backward thrusts but not side thrusts. A rudder is usually provided to change the direction of the water passing through the propeller to produce the side thrust needed. However, the rudder is only functional when the ship is going forward or backward, and that the side thrust is only a small fraction of the total thrust produced by the propeller, thus the ship can not be flexibly handled to move in the desired direction. To enhance the ship's maneuverability, a podded propulsor has been invented and developed for various applications in recent years. The podded propulsor resembles a small-scale submarine and has an advantage of being capable of rotating 360 degrees to overcome the steering problem. However, the propulsion method of the podded propulsor is the same as that of the propeller in that both types of propulsors use rotating blades and thus cause rotational kinetic energy loss. The propulsion method therefore has to be improved in order to enhance propulsion efficiency.
To solve the problems above, the invention provides a general-use underwater propulsor for various purposes.

Oscillating-foil type underwater propulsor with a joint


A configuration method of measurement reporting, a measurement reporting method and device are provided. The configuration method of measurement reporting applied to a base station includes: configuring, according to current state information of a terminal, information of a corresponding measurement configuration for the terminal, wherein the information of the measurement configuration configured for measurement reporting of the terminal.

In a Long Term Evolution (LTE) system, a base station transmits information of a measurement configuration to a User Equipment (UE) via a Radio Resource Control (RRC) signaling, and the terminal performs measurement (intra-frequency measurement, inter-frequency measurement, or inter-system measurement) according to content of the information of the measurement configuration, and then triggers reporting of a measurement result to a UE according to a configured measurement reporting event, or reports a measurement result to a base station periodically.
Regardless of a current state of the UE (whether the UE is movable or not, a current moving state of the UE, a state of a network to which the UE currently belongs, and a state of a channel which the UE is currently using), a configuration, configured by the base station, of measurement reporting of the terminal is unchanged. There is no difference in the configuration for the UE in different states, which is detrimental to saving power for some stationary terminals or some terminals having low-moving speeds.

Configuration method and device of measurement reporting, measurement reporting method and device


A docking station has a housing with an open top compartment formed therein for storing a security key in a locked condition when not in use at a checkout station for opening media security containers. A slide member is moveable by a three position key operated tumbler between locked and unlocked positions across the storage compartment opening. A cam is slidably engageable with the slide member and is moveable by the tumbler for moving the slide member between the locked and unlocked positions. An alarm deactivation switch is actuated by the cam when the tumbler is rotated by the tumbler key to a third position past the locked position. The alarm communicates with a sense loop extending through a flexible expandable cord attaching the key to the housing. An LED provides a visual indication that the alarm is activated.

1. Technical Field
The invention relates to a device for temporarily storing a security key in a locked condition at a checkout counter of a retail establishment when not in use for opening security protected packages. More particularly, the invention relates to such a storage device which has a key actuated tumbler for locking a security key which is attached to the device in a storage compartment when not in use and under proper supervision.
2. Background Information
Due to the increase in shoplifting, because of the manner in which articles of merchandise are displayed in large retail establishments, various types of packages have been devised in which the articles of merchandise are stored, yet displayed in the retail establishment to reduce shoplifting. Most of these security packages contain an EAS tag or other type of theft deterrent device which must be removed or deactivated at the checkout counter to prevent a shoplifter from leaving the store without first paying for the item of merchandise. These security tags actuate an alarm usually located at the exit of the store, if not removed or deactivated at the checkout counter.
Many of these security packages require a specific type of key, either a specially designed mechanical key which moves various locking tabs within the package, or magnetic keys which move magnetically attractable locking members in the security package, enabling the item of merchandise to be removed from the package and given to a customer after purchase.
It has been found that the security key also is susceptible to theft either by an unauthorized employee or even a customer, and then used either at that retail establishment or at another retail store at a later time to open and/or deactivate certain security packages, enabling the items of merchandise to be stolen from the retail establishment. Thus, many of these security keys are tethered by a cable or other type of coiled cord at the checkout station to reduce theft of the key. Although this has proved successful to some extent, it is desirable that even a greater theft deterrent be provided for the security key, especially when the checkout clerk, and/or the supervisor is not at or adjacent the checkout station.
Therefore, the need exists for a device for storing the security key in a secured locked position when not in active use or when left in an unsupervised manner at the checkout station.


An electrostatic-image developer which comprises: (i) a toner comprising: (a) toner particles containing carbon black in an amount of from 6 to 8% by weight based on the weight of the toner particles and having a volume-average particle diameter of from 3 to 9 .mu.m; and (b) an external additive; and (ii) a resin-coated carrier having a volume resistivity of from 10.sup.7 to 10.sup.11 .OMEGA..multidot.cm in an electric field of 10.sup.3.8 V/cm and an average particle diameter of from 30 to 60 .mu.m. Also disclosed are a process for forming a black image and a process for forming a full-color image each using the electrostatic-image developer.

In electrophotography, known processes for converting an electrostatic latent image formed on a photoconductive photoreceptor or the like into a visible image with a toner include, for example, magnetic brush development, cascade development and powder cloud development. Toners for use in these development processes are generally mixtures of a thermoplastic resin and a colorant. The toner image formed on a photoconductive photoreceptor or the like by the above or other development processes is transferred to a support such as paper and fixed thereto by pressing and/or heating. With the recent increasing requirement to provide higher image quality in copies, various improvements have been tried to make in both copiers and developers. In particular, a technique frequently used for improving image quality is to employ a toner having a reduced average particle diameter. The use of a toner having a reduced average particle diameter is an effective means for improving image quality. However, this technique is disadvantageous in that triboelectric charging amount is enhanced, resulting in difficulties in obtaining a desired color density, and that the amount of charges which the toner can have per particle decreases, resulting in blurring. Various limitations are hence imposed on the use thereof.
Employed for improving the developing ability are, e.g., a technique of using a carrier having a reduced diameter so as to have an enlarged chargeable surface area and/or a reduced electrical resistance or a technique for development in which toner particles are flown by means of an AC electric field. These techniques are effective in enabling toners having a high-triboelectric charging amount and a small diameter to have a highly improved developing ability and to satisfactorily ensure a maximum color density in solid parts of from 1.5 to 1.9. With respect to the line density in images having a width of from 150 to 500 .mu.m, the above described conventional techniques are capable of ensuring a line density of 1.0 or higher to enable line or character images made up of such thin lines to be clearly recognizable.
However, the conventional techniques described above have the following problems. In the reproduction of lines or characters (6 to 8 points) having a line width of 100 .mu.m, which reproduction is recently required to attain further higher image quality in terms of line density and character image density, the reproduced line or character images have a image density of 1.0 or lower and are hence light and unclear. Even when it is attempted to form black toner particles in two or more layers so as to form a thin line having a high image density, the resulting black toner particles are only formed in almost a single layer. This is because the electrostatic latent images on the photoreceptor which correspond to the thin lines have a smaller charge amount unlike solid parts.
If the content of carbon black as a colorant is increased in order to obtain a high density, use of the resulting black toner for development in an AC electric field poses a problem that blurring is caused by charge injection due to combinations of the black toner containing a large proportion of carbon black and having a low electrical resistance with a carrier having a low electrical resistance, resulting in image defects.
Furthermore, if an electrostatic latent image corresponding to thin lines or small characters (6 to 8 points) having a line width of 100 .mu.m is formed on a photoreceptor in such a manner that the resulting image has a line width larger than 100 .mu.m in order to heighten only the image density of these lines and characters, there are problems, for example, that the resulting images are deformed although a heightened image density is obtained. In this method, repeated copying operations result in an increase in the line widths of both the thin lines and the characters.

Electrostatic-image developer and image forming process


A question document is divided into predetermined areas, and it is judged whether each divided area is important, to thereby extract an important area. A reply example candidate likelihood value is calculated for each important area, the likelihood value indicating the degree representative of whether each reply example candidate corresponds to a question content. By using the reply example candidate likelihood value, important areas having similar meanings are combined to extract final important parts. A reply example candidate is selected for each important part from reply example candidates prepared beforehand. A reply example candidate reliability degree representative of certainty of each reply example candidate and a reply composition degree indicating whether it is necessary to compose a new reply are calculated, and by using these values, question documents are distributed to different operator terminals.

1. Field of the Invention
The present invention relates to an automatic answering method and apparatus for supporting a question reply process of replying to a question document of a text format.
2. Description of the Related Art
With recent widespread of computerization, questions to companies or the like are often made by form inputs at home pages or e-mails. If every question is to be answered manually on the company side, many operators are required and the cost increases. A novice operator can not answer some questions or it takes a long time for the novice operator to answer a question. In order to solve this problem, a question-answering system has been introduced recently. With this system, a question document is input and its content is analyzed to select a reply example candidate from reply examples and question-reply examples prepared for each question content and to present the selected reply example candidate.
Most of such question-answering systems assume, however, that one document contains only one consultation content. Therefore, if a plurality of question contents are written in one document, the systems cannot analyze each question content, resulting in a low reply precision.
Another technique is disclosed in JP-A-2002-132661. This technique discloses means for dividing one document containing a plurality of question contents, into each question content. The divided question content is analyzed to select a reply example candidate. A reply precision representative of a likelihood or degree of each reply example candidate for the question content is calculated. If the reply precision has a predetermined value or higher, an answer is formed from the reply example candidate, whereas if the reply precision is lower than the predetermined value, an instruction is given to compose a new answer.
The conventional technique disclosed in JP-A-2002-132661 describes that the means for dividing a document into each question content performs a division process by using "number", "alphabet", ".", an indent, a conjunction such as "or", and the like. However, if a document is divided into each question content by using "number", an indent and the like as a separator, there occurs the problem that one question content is divided into a plurality of sentences. Conversely, there arises the problem that if the range of a question content is broad, example candidates for a plurality of question contents cannot be selected.
According to conventional techniques, since a question document is divided basing upon only the information about the contents of the question document, the divided range may not be covered by each reply example candidate. Namely, it is necessary to divide a question document so as to be covered by a prepared reply example candidate, and not to divide it by referring only to the question document content.
Since a question document divided basing upon conventional techniques may be a document irrelevant to the question document content, the reply example candidate generation process is adversely affected so that the reply example candidate generation precision lowers. It also takes a time for a reply composition operator to find a proper document to be read.
According to conventional techniques, a reply precision representative of the likelihood value of a reply example candidate is calculated, and if the reply precision is a predetermined value or higher, a reply is generated from the reply example candidate to automatically answer (automatically return) the question. If the reply precision is lower than the predetermined value, an instruction is given to compose a new answer. However, if there are a large number of types of replies or if a similar question requires a different answer, the reply precision lowers so that the number of samples exceeding a predetermined threshold reduces. Therefore, the number of samples capable of being used for the automatic reply reduces, and the number of cases requiring to generate new answers increases. There arises the problem of a low operator work efficiency or an automatic reply using an erroneous reply example candidate.

Question-answering method and question-answering apparatus


A conveyor assembly is described and which includes a reciprocally moveable and elongated conveyor bed; a drive assembly which imparts reciprocal motion to the elongated conveyor bed; and a controller for selectively energizing the drive assembly and which is operable to move a product deposited on the conveyor bed along a selectively adjustable path of travel.

Various vibratory conveyors of assorted designs have been employed in diverse industry segments through the years. Such vibratory conveyors have been used on a wide range of applications including mining, and more recently in various food handling applications. Vibratory conveyors, and more specifically, excited frame conveyors have been utilized for decades. Such vibratory conveyors have been employed to handle fragile food products such as potato chips, french fries and other coated food products in a manner which prevents damage to the product, or further prevents seasonings, and the like from becoming dislodged from the product as the product is moved between processing stations.
Excited frame conveyor designs have evolved through the years. Generally speaking, however, excited frame conveyors have included a longitudinally extending conveyor bed which has been used to transport product along a linear path of travel between adjacent work stations. In some applications, mechanical gates have been incorporated into the conveying beds of such exciting frame conveyors in order to allow a portion of a product stream to be diverted from the conveyor bed for various downstream purposes. While the mechanical gate assemblies employed on the aforementioned conveyors have operated with various degrees of success, shortcomings have long been recognized with such arrangements. Chief among the problems associated with such mechanical gates is the propensity for these assemblies to collect or otherwise be coated with various food products, and other debris, that might be introduced or mixed with the product stream. Besides the obvious problems associated with debris, and other food coating interfering with the mechanical operation of such gates, that is, the debris, often has a tendency to slow the operation of such gate assemblies, this debris also presents a sanitation problem. Additionally it is often difficult to clean such mechanical devices if the excited frame conveyor has been utilized to transmit a product that has constituent elements that might strongly adhere to the various surfaces of the mechanical gate arrangement. Of course difficulties in cleaning such devices inevitably leads to delays in converting various product lines so that they may be utilized with alternative food products as might be the case in a modern packaging plant.
A conveyor assembly which addresses these and other shortcomings in the prior art teachings and practices is the subject matter of the present application.


A process is described to produce ultra thin biaxially stretched film made of thermoplastic where at least two film webs are superimposed and stretched together in both the longitudinal and transverse directions. The film webs are subjected to a heat treatment before the first draw step. After stretching, the film webs are separated again from each other.

1) Field of the Invention
The present invention relates to a process for producing biaxially stretched film made of thermoplastics, with a thickness of less than 2 .mu.m, where at least two films are superimposed and stretched together in the longitudinal and transverse directions.
2) Prior Art
Ultra thin films with a thickness less than 3 .mu.m, particularly less than 1 .mu.m are required on ever larger scales for the production of capacitors in microelectronics. In practice, the production of these films presents extraordinary difficulties. In literature, different processes are described aiming mainly to produce first the thin film together with or on a base film, peel off the base film, and then roll up the thin film.
German Auslegeschrift DE-A-17 04 764 (equivalent to Canadian Patent 887,168) describes how two single films can be caused to adhere to one another through pressure and/or heat. Due to unavoidable slight variations in thickness of the single films, creases are formed repeatedly, whereby the creases are further ingrained during the laminating process, which means that such films are useless for their intended purpose.
German Auslegeschrift DE-A-24 31 385 (equivalent to U.S. Pat. Nos. 4,017,227 and 4,076,785) describes a device where two cast sheets are produced next to each other and joined before stretching in the transverse direction. In this method, however, the supporting function of the base layer is missing and breaking of the thin film is frequently observed.
European Patent Application EP-A-0 153 081 (equivalent to U.S. Pat. Nos. 4,708,905 and 4,756,064) relates to stretching coextruded composite films, where the individual layers are made of different polymers, and to delaminating the film composite, after stretching. But with this process, the flow velocity of the different plastics cannot be coordinated exactly. Regulating a uniform thickness profile across the film width also creates great problems since allocating the thickness distribution of the total composite film and the top layer is difficult; moreover, adjustment of the thickness profiles of the individual layers is subject to constant fluctuations at coextrusion.
It is also known that at the time the melt is drawn from the extruder, the molten plastic already has a certain measurable molecular preorientation which is dependent upon technical conditions, like die position, die width, take-off speed, chemical composition of the plastic, and its degree of polymerization. The level of the molecular preorientation and its uniformity, are of considerable importance for the further stretching and for the physical properties of the final film, such as mechanical properties like tear resistance and dimensional stability or the thickness profile and is of particularly crucial importance when producing extremely thin films.