A dual temperature refrigerated display case including a low temperature refrigerated display case defining a low temperature product display area and including a low temperature air curtain configured to flow across an access opening of the low temperature case. The dual temperature refrigerated display case also includes a medium temperature refrigerated display case disposed above the low temperature case. The medium temperature case defines a medium temperature product display area and includes a medium temperature air curtain configured to flow across an access opening of the medium temperature case. The dual temperature refrigerated display case includes a duct disposed between the medium temperature refrigerated display case and the low temperature refrigerated display case. The duct receives spillover air from the medium temperature air curtain and redirects the spillover air away from the low temperature air curtain.

The present invention relates to a dual temperature refrigerated display case including a medium temperature open display case on top and a low temperature freezer open merchandizer on the bottom.
Dual temperature refrigerated display cases of this type have generally included separate air circulation systems providing cooled air to the display area of the medium temperature case on top and to the display area of the low temperature case on the bottom to maintain the products within each respective product display area at its desired temperature. The medium temperature case includes a fan and a medium temperature coil disposed in the base of the medium temperature case below the product display area. The fan draws air into an inlet at the front of the medium temperature case and then moves this air through the medium temperature coil. After passing through the coil, the air moves upwardly through a rear passageway behind the product display area, forwardly through an upper passageway above the product display area in the canopy, and downwardly out of a discharge outlet generating an air curtain across the front access opening of the product display area. Most of the air that defines the medium temperature air curtain is returned through the inlet to recirculate through the coil.
The low temperature case includes a fan and a low temperature coil disposed in the base of the low temperature case below the product display area. The fan draws air into an inlet at the front of the low temperature case and then moves this air through the low temperature coil. After passing through the coil, the air moves upwardly through a rear passageway behind the product display area, forwardly through an upper passageway above the product display area, and out of a discharge outlet at an angle generating an air curtain across an access opening of the product display area. Most of the air that defines the low temperature air curtain is returned through the inlet to recirculate through the coil.
Although stacking two different temperature cases in this manner provides advantages to marketing of product in a retail setting, it has provided challenges to maintaining case performance. For example, spillover air from the medium temperature air curtain (i.e., air which does not return to the medium temperature coil through the inlet) can dump into the low temperature case below thereby disrupting the low temperature air curtain allowing the intrusion of relatively humid, higher temperature air into the low temperature case causing potential issues in temperature performance within the low temperature case and frost formation on the low temperature coil. In the past, frost formation has been addressed through the addition of heaters on the low temperature coil. However, heaters, like other such energy producing components, add to the energy production of the case thereby decreasing case efficiency.


An object is to provide a heat source system capable of realizing energy saving. In a heat source system including: a chilled-water main control heat pump (1) having a lower-stage evaporator (9) that cools chilled water and a lower-stage condenser (7) that dissipates heat into cooling water, and outputting the chilled water cooled in the lower-stage evaporator (9) to an external load; and a hot-water main control heat pump (51) having a higher-stage evaporator (59) to which heat is provided by medium-temperature water that has been heated with the exhaust heat from the lower-stage condenser (7) and a higher-stage condenser (57) that heats high-temperature water, and outputting the high-temperature water heated in the higher-stage condenser (57) to an external load; a lower temperature limit of the cooling water is set on the basis of a set temperature of the high-temperature water.

A heat source system for enabling the supply of chilled water of a constant temperature is provided in a factory equipped with a semiconductor fabrication facility or the like (for example, a clean room). As the heat source system, there is one equipped with a plurality of centrifugal chillers, as shown in PTL 1, for example.
In factories equipped with semiconductor fabrication facilities, high-temperature water of approximately 60 to 70° C. that is used as cleaning water in the semiconductor fabrication facility and medium-temperature water of approximately 32 to 45° C. for heating are required in addition to the chilled water.
Conventionally known heat source systems that supply such high-temperature water and medium-temperature water include, as shown in FIG. 7, those in which a boiler 129 is combined with a centrifugal chiller 101.
As shown in FIG. 7, the centrifugal chiller 101 is driven by an electric motor 103 and is equipped with a centrifugal compressor 105 that compresses refrigerant, a condenser 107 that condenses the refrigerant compressed by the centrifugal compressor 105, an expansion valve (not shown) that expands the refrigerant condensed by the condenser 107, and an evaporator 109 that evaporates the refrigerant expanded by the expansion valve.
The evaporator 109 is connected to chilled water piping 110, through which the chilled water flows, and the chilled water is cooled by the latent heat of evaporation of the refrigerant that is evaporated in the evaporator 109. The chilled water piping 110 is provided with a chilled water pump 112, and the chilled water is supplied in a circulating manner by this chilled water pump 112 between the evaporator 109 and external loads (not shown) that use the chilled water, such as the semiconductor fabrication facilities.
The condenser 107 is connected to cooling water piping 114, through which cooling water flows, and the latent heat of condensation of the refrigerant condensed in the condenser 107 is dissipated to the cooling water. The cooling water piping 114 is provided with a cooling water pump 116, and the cooling water is supplied in a circulating manner between a cooling tower 118 and the condenser 107 by this cooling water pump 116. The cooling tower 118 is of the type in which the cooling water is cooled by being sprinkled into the outside air by a sprinkler 120 and is equipped with a fan 119 for cooling the sprinkled cooling water.
The cooling water piping 114 located between the condenser 107 and the cooling tower 118 is provided with a medium-temperature-water heat exchanger 121. This medium-temperature-water heat exchanger 121 is provided with medium-temperature-water piping 125 that guides the hot water supplied from a medium-temperature-water pump 123. The medium-temperature water that has passed through the medium-temperature-water piping 125 and that has received heat from the cooling water in the medium-temperature-water heat exchanger 121 is guided to medium-temperature-water supply piping 127, and is used as the heat source for heating.
In order to supply high-temperature water, in addition to the centrifugal chiller 101, the boiler 129 is provided. The boiler 129 is provided with high-temperature-water piping 132 that guides feed water supplied from a boiler water supply pump 130. The feed water circulating in the high-temperature-water piping 132 is heated in the boiler 129 and is guided to high-temperature-water supply piping 134 as high-temperature water of approximately 60 to 70° C. The high-temperature water supplied by the high-temperature-water supply piping 134 is used as a heat source of high-temperature cleaning water for the semiconductor facilities. The reference numeral 136 is back-up piping that connects the high-temperature-water piping 132 and the medium-temperature-water supply piping 127, and that is used for supplying the high-temperature water as a back-up for the medium-temperature water.
FIG. 8 shows a heat source system in which a heat-recovery machine is employed for the condenser 107 in FIG. 7. Specifically, in FIG. 8, the heat source system is configured such that the medium-temperature-water piping 125 is connected to the condenser 107, and heating is conducted by a medium-temperature-water heat exchanger (not shown) in the condenser 107, thereby obtaining heat from the condenser 107. Therefore, in the heat source system shown in FIG. 8, the medium-temperature-water heat exchanger 121 shown in FIG. 7 is omitted. Because the other configurations are the same as in the heat source system shown in FIG. 7, the same reference numerals are assigned and descriptions thereof are omitted.

Heat source system and control method thereof


The subject of the invention is a connection device for a flex circuit (12), comprising a support (16), means (18) for positioning flex circuit (12) relative to said support (16) and conformation means (20) for flex circuit (12), characterized in that conformation means (20) has at least one bent spring strip (24) comprising at least one bend (26) positioned between flex circuit (12) and a surface (28) so as to increase the elastic effect of said strip (24).

Document U.S. Pat. No. 3,082,398 describes such a device positioned at the end of each flex circuit, both devices being held level with one another, assuring a direct contact between the flex circuits.
According to this arrangement, each device comprises a head that can receive the flex circuit, the circuit being bent to cover both surfaces of the head and being immobilized relative to transverse translation between the lateral edges of the head.
An elastic element, in the form of an elastic strip, positioned between the head and the flex circuit, is provided to reinforce the contact pressure between the two flex circuits.
For this purpose, a U-shaped piece of sheet metal is fitted onto the end of the head and comprises cut-outs that delimit elastic strips which work by flexing in the zone interposed between the head and the flex circuits. According to this embodiment, only one arm of the U is positioned between the support and the flex circuit.
In order to assure their support, the two devices are plugged into a retaining element, the flex circuits being pressed flat against one another by means of the elastic strips.
This arrangement is not completely satisfactory since it only procures a mediocre electrical contact between the two flex circuits, and this contact deteriorates over time.
Moreover, this arrangement does not assure an optimal positioning between the two flex circuits, since these circuits are simply immobilized between the lateral edges of the heads, with the result that the electrical components of both flex circuits cannot be positioned level with to one another.


A log message classifier employs machine learning for identifying a corresponding parser for interpreting the incoming log message and for retraining a classification logic model processing the incoming log messages. Voluminous log messages generate a large amount of data, typically in a text form. Data fields are parseable from the message by a parser that knows a format of the message. The classification logic is trained by a set of messages having a known format for defining groups of messages recognizable by a corresponding parser. The classification logic is defined by a random forest that outputs a corresponding group and confidence value for each incoming message. Groups may be split to define new groups based on a recurring matching tail (latter portion) of the incoming messages. A trend of decreased confidence scores triggers a periodic retraining of the random forest, and may also generate an alert to operators.

An information system typically generates log files indicative of various system functions and operations. Log files facilitate troubleshooting and remediation when problems occur, and can provide a path of performed operations. Modern information systems handling many transactions or information requests can generate substantial volumes of log file entries. Often, log files need not be consulted unless an anomaly or problem is discovered. However, it is often beneficial to maintain the log files for regulatory, legal or business practices. The result can be a substantial quantity of sparsely used data.

High volume message classification and distribution


A pressure sensing cable in one embodiment includes an optical fiber having a first core and a second core. The first core extends along a length of the cable, and is sized and configured to provide propagation of light along the first core along the length of the cable. The first core has a first mode index corresponding to the speed of light propagation along the first core. The second core extends along the length, is spaced a distance from the first core, and is sized and configured to provide propagation of light along the second core along the length of the cable. The second core has a second mode index corresponding to the speed of light propagation along the second core. The second mode index is different from the first mode index, wherein light propagates along the second core at a different speed than along the first core.

Various devices have been developed for measuring environmental conditions of a given location, such as temperature or pressure. However, numerous locations present challenges to many of these devices. For example, many devices may not be appropriate for use in higher temperature environments, such as geothermal wells, oil wells, or the like.
Certain conventional down-hole sensing techniques (e.g., for oil, gas, or geothermal applications) use distributed strain, temperature, and/or acoustic sensing. Pressure sensing along the length of a cable (or along the depth of a well or hole) may be performed using separately packaged sensors that are spliced along a length of a cable. For example, hydrostatic pressure may be transduced into longitudinal strain along an axis of the sensor, with the longitudinal strain used in determining pressure. However, the process of packaging and splicing sensors along a cable places practical limits on the numbers of pressure sensors along the length of the cable, and accordingly limits the numbers of locations for which pressure may be determined. The splicing of sensors into the cable and/or the use of transduced axial strain increases the cost, complexity, and/or instrumentation of distributed pressure sensing. Conventional approaches may also provide reduced resolution and/or present additional or alternative drawbacks. For example, certain conventional approaches may provide information for limited, discrete locations of a remote environment.
Temperature, strain, and/or acoustics may be measured along the length of an optical fiber by means of Raman, Brillouin, or Rayleigh scattering measurements, with distance resolution down to about one meter along the length of the cable possible. However, distributed pressure measurements (e.g., continuous or nearly continuous measurement of pressure along a length of a cable) may not be able to be made in the same manner.

Systems and methods for distributed pressure sensing


A gearbox with an actuating device for automated shifting and selection of transmission ratios includes a gearbox operating element that is driven by an actuator. The actuator has a drive source with an output element. A swivel movement of the output element causes the gearbox operating element to shift into or out of a transmission ratio or to select one of the shift slots of a shift-gate pattern and to simultaneously apply a force to an energy-storing device. The energy-storing device acts on an intermediate element which acts on the gearbox operating element. At least one retaining element limits the actuation of the intermediate element to a predetermined position.

The invention relates to a gearbox with an operating device for automatic shifting and selection of a gear ratio, the gearbox having a gearbox operating element which is arranged to adjust the gear ratio and can be activated by means of an operating actor.
Such gearboxes are known, for example, from published German patent application Serial No. 196 37 001 in which a hydraulic drive is used for each activation of the shift and for each selection process. The use of two drives to control the shift and selection process is complex in construction and assembly with regard to the drive.


Antiproliferative compounds having a structure represented by formula (II), where n, R1, R2, R3, R4, and R5 are as defined herein, can be used to treat tumors, optionally when conjugated to a ligand such as an antibody:

This invention relates to compounds structurally related to the tubulysins, conjugates thereof with a ligand, methods for making and using such compounds and conjugates, and compositions comprising such compounds and conjugates.
The tubulysins are cytotoxins originally isolated from cultures of the myxobacteria Archangium gephyra or Angiococcus disciformis, with each organism producing a different mixture of tubulysins (Sasse et al. 2000; Reichenbach et al. 1998). Their crystal structure and biosynthetic pathway have been elucidated (Steinmetz et al. 2004) and their biosynthesis genes have been sequenced (Hoefle et al. 2006b). Pretubulysin, a biosynthetic precursor of the tubulysins, also has been shown to possess significant activity in its own right (Ullrich et al. 2009). (Full citations for the documents cited herein by first author or inventor and year are listed at the end of this specification.)
The tubulysins belong to a group of naturally occurring antimitotic polypeptides and depsipeptides that includes the phomopsins, the dolastatins, and the cryptophycins (Hamel 2002). Antimitotic agents other than polypeptides or depsipeptides also exist, for example paclitaxel, the maytansines, and the epothilones. During mitosis, a cell's microtubules reorganize to form the mitotic spindle, a process requiring the rapid assembly and disassembly of the microtubule constituent proteins α- and β-tubulin. Antimitotic agents block this process and prevent a cell from undergoing mitosis, although at the molecular level the exact blockage mechanism may differ from one agent to another. The tubulysins prevent the assembly of the tubulins into microtubules, causing the affected cells to accumulate in the G2/M phase and undergo apoptosis (Khalil et al. 2006). Conversely, paclitaxel effects the same end result by binding to microtubules and preventing their disassembly.
The tubulysins have a tetrapeptidyl scaffold constructed from one proteinogenic and three non-proteinogenic amino acid subunits: N-methylpipecolinic acid (Mep), isoleucine (Ile), tubuvaline (Tuv), and either tubuphenylalanine (Tup, RA equals H in formula (I) below) or tubutyrosine (Tut, RA equals OH). About a dozen naturally occurring tubulysins (named A, B, etc.) are known, the sites of structural variation among them being at residues RA, RB and RC as shown in Formula (I) and Table 1:

TABLE 1Naturally Occurring TubulysinsTubulysinRARBRCAOHOC(═O)MeCH2OC(═O)i-BuBOHOC(═O)MeCH2OC(═O)n-PrCOHOC(═O)MeCH2OC(═O)EtDHOC(═O)MeCH2OC(═O)i-BuEHOC(═O)MeCH2OC(═O)n-PrFHOC(═O)MeCH2OC(═O)EtGOHOC(═O)MeCH2OC(═O)CH═CH2HHOC(═O)MeCH2OC(═O)MeIOHOC(═O)MeCH2OC(═O)MeUHOC(═O)MeHVHOHHZOHOHHPretubulysinHHMe
Kaur et al. 2006 studied the antiproliferative properties of tubulysin A and found that it was more potent than other antimitotic agents such as paclitaxel and vinblastine and was active in xenograft assays against a variety of cancer cell lines. Further, tubulysin A induced apoptosis in cancer cells but not normal cells and showed significant potential antiangiogenic properties in in vitro assays. The antimitotic properties of other tubulysins have also been evaluated and generally have been found to compare favorably against those of non-tubulysin antimitotic agents (see, e.g., Balasubramanian et al. 2009; Steinmetz et al. 2004; Wipf et al. 2004). For these reasons, there is considerable interest in the tubulysins as anti-cancer agents (see, e.g., Domling et al. 2005c; Hamel 2002).
Numerous publications describe efforts directed at the synthesis of tubulysins, including: Balasubramanian et al. 2009; Domling et al. 2006; Hoefle et al. 2003; Neri et al. 2006; Peltier et al. 2006; Sani et al. 2007; Sasse et al. 2007; Shankar et al. 2009; Shibue et al. 2009; and Wipf et al. 2004. Other publications describe structure-activity relationship (SAR) studies, via the preparation and evaluation of tubulysin analogs or derivatives: Balasubramanian et al. 2008 and 2009; Domling 2006; Domling et al. 2005a; Ellman et al. 2009; Hoefle et al. 2001 & 2006a; Patterson et al. 2007 & 2008; Richter 2008; Vlahov et al. 2009; Wang et al. 2007; and Wipf et al. 2007 and 2010. The SAR studies mainly explored structural variations in the Mep ring, residues RB and RC of the Tuv subunit, and the aromatic ring or aliphatic carbon chain of the Tup/Tut subunit.
Domling et al. 2005 disclose conjugates of tubulysins with a partner molecule generically described as a polymer or a biomolecule, but with actual examples limited to polyethylene glycol (PEG) as the partner molecule. Other documents disclosing conjugates of tubulysins are Boyd et al. 2008 and 2010; Vlahov et al. 2008a, 2008b and 2010; Leamon et al. 2008 and 2009; Reddy et al. 2009; and Low et al. 2009. Leung et al. 2002 disclose polyanionic polypeptides that can be conjugated to drugs (including tubulysins) to improve their bioactivity and water solubility.
Davis et al. 2008 and Schluep et al. 2009 disclose cyclodextrin based formulations in which tubulysins are covalently attached to a cyclodextrin via a hydrazide-disulfide linker moiety bonded to the Tup/Tut carboxyl group.

This patent is subject to a terminal disclaimer.

Antiproliferative compounds, conjugates thereof, methods therefor, and uses thereof


The new variety ‘Georgia Sunset’ is provided. The new variety ‘Georgia Sunset’ generally has bright two-tone flowers, a large flower size, and persistent flowering throughout the growing season. The new variety ‘Georgia Sunset’ has brighter yellow flowers and a longer blooming period than similar cultivars of Gaillardia plants currently on the market. The new variety ‘Georgia Sunset’ flowers for at least four months during the growing season.

The present invention relates to the discovery of a new and distinct cultivar of Gaillardia plant botanically known as a Gaillardia×grandiflora and herein referred to as 'Georgia Sunset', as herein described and illustrated.
The new Gaillardia plant variety 'Georgia Sunset' was selected in Watkinsville, Ga. in 2007. The new variety 'Georgia Sunset' generally has bright two-tone flowers, a large flower size, and persistent flowering throughout the growing season.
Pedigree and history: The new Gaillardia plant variety 'Georgia Sunset' was one of many seedlings selected in summer 2007 in Watkinsville, Ga. and originated from open pollination of Gaillardia plants in the University of Georgia Trial Gardens in Athens, Ga. The maternal plant is likely the Gaillardia plant 'Arizona Sun' (unpatented). Seeds from the open-pollinated Gaillardia plants were collected in fall 2006 and grown out in containers and in the field at Watkinsville, Ga. The resulting seedlings, of which the new variety 'Georgia Sunset' was one, were selected in summer 2007. The new Gaillardia plant variety 'Georgia Sunset' has been evaluated and tested in Watkinsville, Ga. and Athens, Ga. since 2007.
The new Gaillardia plant variety 'Georgia Sunset' has been shown to maintain its distinguishing characteristics through successive asexual propagations by, for example, rooted stem cuttings. Plants from stem cuttings have been directly planted in the ground.

University of Georgia Research Foundation, Inc.


An organic EL display panel having display pixels with an improved aperture ratio. A display pixel includes a control electrode line coupled to control electrodes of first and second transistors and a main electrode of a fourth transistor, and a power electrode line provided substantially in parallel with a data line and coupled to a main electrode of the first transistor. Channels of the first and second transistors are formed substantially in parallel with a scan line. A node of the control electrode line for coupling the control electrodes of the first and second transistors is arranged in a direction substantially perpendicular to that of the scan line, and a portion of the control electrode line extended to the main electrode of the fourth transistor is formed substantially in parallel with the power electrode line in a substantially vertical direction, and forms a capacitor together with the power electrode line.

(a) Field of the Invention
The present invention relates to a video display. More specifically, the present invention relates to an organic electroluminescent (EL) display panel.
(b) Description of the Related Art
In general, an organic EL display electrically excites a phosphorous organic compound to emit light. A light emitting pixel includes an anode (ITO), an organic thin film, and a cathode layer (metal). The organic thin film has a multi-layer structure including an EML (emitting layer), an ETL (electron transport layer), and an HTL (hole transport layer) for maintaining balance between electrons and holes and improving emitting efficiencies. The organic thin film further includes an EIL (electron injecting layer) and an HIL (hole injecting layer).
The organic emitting cells are arranged in an nxm matrix format to configure an organic EL display panel which displays video data by voltage or current-driving.
FIG. 1 shows a brief diagram of a general organic EL display.
As shown, the organic EL display includes an organic EL display panel 10, a scan driver 20, and a data driver 30.
The organic EL display panel 10 includes a plurality of data lines D1 to Dm extending in a column direction and arranged in a row direction, a plurality of scan lines S1 to Sn extending in the row direction and arranged in the column direction, and a plurality of pixel circuits 11. The data lines D1 to Dm transmit data voltages for displaying video signals to the pixel circuits 11, and the scan lines S1 to Sn transmit select voltages for selecting the pixel circuits 11 to the pixel circuits 11. The pixel circuits 11 are formed at pixel areas, each of which is defined by two neighboring data lines and two neighboring scan lines.
The scan driver 20 sequentially applies the select signals to the scan lines S1 to Sn, and the data driver 30 applies the data voltages for displaying the video signals to the data lines D1 to Dm.
Methods for driving the organic emitting cells through the pixel circuits 11 include a passive matrix method, and an active matrix method which uses thin-film transistors (TFTs). The passive matrix method forms anodes and cathodes to cross each other, selects lines, and drives the organic emitting cells, and the active matrix method uses the TFTs to select lines, stores data in capacitors of the pixels, and drives the organic emitting cells.
U.S. Patent Publication No. 2002/0118150 discloses a pixel circuit with four transistors for the organic EL display based on the active matrix method.
A driving transistor transmits the current which corresponds to a voltage between a gate and a source to an organic EL element (OLED). A capacitor is connected between the gate and the source of the driving transistor. A compensation transistor for compensating for a threshold voltage of the driving transistor is diode-connected, and its gate is coupled to the gate of the driving transistor. A switching transistor which has a gate coupled to a current scan line and a source coupled to a data line applies the data voltage to a source of the compensation transistor in response to the select signal of the current scan line. A pre-charge transistor which has a gate coupled to a previous scan line applies a pre-charge voltage to the gate of the driving transistor in response to the select signal of the previous scan line.
In order to make the threshold voltages at the driving transistor and the compensation transistor substantially the same in the above-described pixel circuit, the driving transistor and the compensation transistor are arranged in parallel with the data lines. The pre-charge transistor is arranged to be coupled to a previous scan line.
However, the above-mentioned arrangement has a problem of reducing the aperture ratio of display pixels since the area of gate lines for coupling a drain of the pre-charge transistor, the gate of the driving transistor, and the gate of the compensation transistor is increased.

Organic electroluminescent display panel


A container for thermal conditioning of a fluid under pressure, use of the container for thermally conditioning a fluid under pressure, a chemical reactor including the container and a polymerization process using the reactor, and a method of producing the container and the reactor. The container is bounded over at least part of its surface facing the outside by at least one external plate and facing the inside by at least one internal plate, the external plate being thicker than the internal plate, the external plate and the internal plate being joined together in places to define a space between joints for circulation of a heat-transfer fluid and the container including a mechanism to adjust the pressure of the heat-transfer fluid to that of the fluid under pressure.

1. Field of the Invention
This application is a 371 of PCT/EP05/053027, filed Jun. 28, 2005, and claims priority to French Patent Application No. 04.07158, filed Jun. 29, 2004.
The subject of the invention is a container for the thermal conditioning of a fluid under pressure, its use, a chemical reactor, a polymerization process using it and a method of manufacturing the container and the reactor.
2. Description of Related Art
When it is necessary to carry out heat exchange in a container intended to contain a fluid under pressure, one is generally confronted with the problem of controlling the heat exchange (thermal conditioning of the fluid), namely to remove the heat generated or to supply the heat needed. In particular in exothermic or endothermic reactions, one is faced with the problem of removing the heat generated by the reaction or alternatively supplying the heat needed for it.
Many containers intended to contain fluids under pressure have already been described, in particular those in which a double-walled jacket in which the heat-transfer fluid for controlling the heat exchange circulates, is fixed to the outer face of the outer wall of the container. In this particular case, the heat flux must pass through the thickness of the wall, which results in low heat exchange coefficients for heat exchange between the fluid under pressure and the heat-transfer fluid, leading in the particular case of a polymerization reaction to an increase in the polymerization time and a loss of efficiency of the plant.
Other containers intended to contain fluids under pressure in which the double-walled jacket is fixed to the inner face of the outer wall of the container have also been described.
Thus, document EP 0 012 410 B1 describes a container for carrying out exothermic and endothermic reactions, in particular the polymerization of vinyl chloride by controlling the heat exchange by means of a heat-transfer fluid circulating in a double-walled jacket fixed to the inner face of the outer wall of the apparatus. The double-walled jacket is produced by welding, to the internal face of the wall of the container, a semi-tubular coil consisting of half-tubes in the form of semicircular tubes so that they form a winding with touching turns. This type of container is characterized by a better heat exchange coefficient than those exhibited by the prior containers with a double-walled jacket fixed to the outer wall of the container, but it is still low. It is also complicated to produce, resulting in very high construction costs. Finally, because the half-tubes form, between them, on the inside of the container a very sharp angle (a discontinuity), this type of container has a major drawback, as the container shown diagrammatically in Patent Application FR 2746488 also has, in particular when it is used for a polymerization, especially for the polymerization of vinyl chloride, namely the fact that the polymer formed is disadvantageously deposited in the regions between the half-tubes on the inside of the container. This means that the polymerization cycle has to be interrupted more often in order to clean the reactor. The productivity of such a process is greatly affected thereby.

Thermal conditioning container and method of manufacturing it


A visual display and helmet assembly is configured to function in the presence of a harsh environment, e.g., high wind, vibration and shock and strong ambient light. The visual display preferably includes a transmissive liquid-crystal display to reduce the display's size and to enhance the intensity of a virtual image. In addition, the display is preferably reconfigurable so that different display indicia can be programmed as desired. To reduce probability of injury to a user, the visual display is carried on the exterior of the helmet with its center of mass positioned substantially on the midsagittal plane of the user. In addition, a mount permits the visual display to detach from the helmet when it is subjected to forces above a predetermined threshold. The mount is also permits yielding movement between the visual display and the helmet to enhance viewing of the image.

1. Field of the Invention
The present invention relates generally to visual displays and more particularly to headgear-mounted displays.
2. Description of the Related Art
A variety of visual-display systems have been proposed for presenting an information display to a system user while that user is concentrating on a visual scene which is critical to the user's immediate task, e.g., driving a high-speed motor vehicle, piloting an aircraft or operating a mobile, motion-picture camera. These systems are generally positioned on the user's head and are often integrated into a headgear which is associated with the user's task, e.g., eyeglasses or a helmet. The systems are typically referred to as head-up displays (HUD) because they facilitate concentration on a visual scene that is generally in front of the user.
Visual-display systems have included a variety of image generators. For example. U.S. Pat. No. 3,833,300 combines an image generator in the form of a cathode-ray tube with a helmet visor which is configured in the shape of a parabola. An optical fiber conducts the image of the cathode-ray tube to the focal point of the parabola. From the focal point, the image is directed at the visor. The visor preferably carries a reflective coating to enhance a reflection of the image to the wearer of the helmet.
A parabolically-shaped, helmet visor is also described in U.S. Pat. No. Re. 28,847. An image generator is positioned at the focal point of the parabola and directed at the visor surface. A coating is applied to the visor surface to cause it to be a combining surface, i.e., it is partially reflective and partially transparent. In another embodiment, the visor is altered to place the parabolic focal point within the forehead of the wearer of the helmet and a mirror is added to reflect the image from the image generator to the visor. The mirror is positioned so that a virtual image appears to be located at the focal point.
Another exemplary use of a cathode-ray tube as an image generator is found in U.S. Pat. No. 4,761,056. From a cathode-ray tube, an image is reflected from a first parabolic mirror and then directed along an optical path which is defined by a pair of fold mirrors. The optical path intersects a second parabolic mirror which is in the field of view of the system's user. In one embodiment the first and second parabolic mirrors are segments of a helmet visor. The parabolic mirrors are preferably formed by partially reflective coatings on the visor.
U.S. Pat. No. 5,189,512 describes yet another exemplary display system in which a cathode-ray tube functions as an image generator. An image, which is formed by the cathode-ray tube, is directed along an optical path with a pair of fully-silvered mirrors. Positioned between the mirrors is a double convex lens. The second mirror is placed in front of one eye (the "display eye") of a user of the system. The spacing between the lens and the cathode-ray tube is adjusted to position a virtual image at a distance, e.g., 3 meters, sufficient to avoid the need for extensive refocusing when attention is diverted away from the user's immediate task. Preferably, an occlusion device in the form of an opaque element is positioned in front of the user's other eye (the "non-display eye"). This element is arranged in a shape which approximates the shape of the perceived image in the display eye. The occlusion device is intended to prevent "binocular rivalry" in which the brain's perception areas become confused by conflicting visual information.
Other visual-display systems have employed liquid-crystal displays as a display generator. In U.S. Pat. No. 4,181,405, each visual element, e.g., an alpha-numeric symbol, of an information display is generated by a reflective liquid-crystal display. A helmet visor is configured with a plurality of convex lenses and each liquid-crystal display is separated from a different lens by a space that is generally equal to or less than the focal length of the respective lens.
Another exemplary system is described in U.S. Pat. No. 4,869,575, which positions a reflective liquid-crystal display in association with a body of optically-clear material. The body has a prism portion and a collimating lens portion. In one embodiment, the prism portion forms a planar surface and a pair of reflecting surfaces and the lens portion forms a spherical convex lens. The liquid-crystal display is positioned against the planar surface and the body is mounted to the frame of a pair of eyeglasses with the lens positioned proximate to one glass of the eyeglasses. In operation, the lens receives the image from the reflecting surfaces and forms a virtual image at optical infinity. To view the virtual image, a user looks slightly above the normal sight line through the eyeglasses.
In still another exemplary system, U.S. Pat. No. 5,162,828 mounts a transmissive liquid-crystal display in various headgears, e.g., ski goggles, scuba dive masks and sunglasses. The liquid-crystal display is illuminated by ambient light that reaches the display through a diffusing filter. Alternatively, the ambient light is replaced by light from an incandescent source which is reflected from a parabolic mirror. In one embodiment, a partially-reflective mirror is positioned above or to the side of the user. A lens is placed between the liquid-crystal display and the mirror to provide an apparent optical distance which is selected to correspond to the visual distance that is associated with the immediate task of the wearer.
Although these exemplary display systems may adequately present an information display to a system user when the user's immediate task is performed in a benign environment (e.g., a motion-picture studio), they generally are not suitable for tasks (e.g., operating a racing vehicle) that are performed in the presence of harsh conditions (e.g., high wind, vibration and shock and strong ambient light). Under these conditions, a display system attached to an eyeglass frame (see U.S. Pat. No. 5,162,828) would not survive. A display system arranged within a helmet (see U.S. Pat. No. Re. 28,847) can become a lethal object to the system user and one whose center of mass is located at one side of a user's head (see U.S. Pat. No. 4,761,056) can induce dangerous twisting forces on the head. Such harsh conditions demand a system which can present an image that is visible in the presence of strong ambient light and which is configured to protect a user of the system from injury.


Method and arrangement in base station (110) for estimating the amount of data to be received from a terminal (120). The base station (110) and the terminal (120) are comprised within a wireless communication system (110). The terminal (120) comprises a buffer arranged to buffer frames comprising data. The method comprises determining (401) a service requested by the terminal (120), estimating (403) the arrival time of data to be received from the terminal (120), based on the determined service, and setting (404) a buffer estimate, comprising an estimation of the amount of data to be received, based on an estimated frame size for the determined service.

In the 3rd Generation Partnership Project (3GPP), work is ongoing on specifications of the UMTS Terrestrial Radio Access Network (UTRAN) evolution (E-UTRA) as part of the Long Term Evolution (LTE) effort.
In LTE, scheduling is modelled in the Medium Access Control (MAC) layer and resides in the eNodeB (eNB). The scheduler assigns radio resources, also called Resource Blocks (RB), for the downlink (assignments) as well as for the uplink (grants) using the Physical Downlink Control CHannel (PDCCH).
The radio uplink is the transmission path from a terminal, which may also by referred to as a User Equipment (UE), to a base station, or an eNodeB. A downlink is the inverse of an uplink, i.e. the transmission path from the eNodeB to the terminal.
For uplink scheduling, the eNodeB needs information about the current state of the buffers in the terminal, i.e. if and how much data the terminal has in its priority queues. This information is sent from the terminal to the eNodeB either as a 1-bit Scheduling Request (SR) or by a Buffer Status Report (BSR). The Scheduling Requests are transmitted on a control channel such as e.g. Physical Uplink Control CHannel (PUCCH) or Radio Access CHannel (RACH) while the BSR are transmitted on the data channel such as e.g. Physical Uplink Shared CHannel (PUSCH), mostly together with user data.
Precise and up-to-date scheduling information allows more accurate scheduling decisions, and can help to optimize the use and management of radio resources and to improve capacity. However, the accuracy of the information provided by the terminal is limited by the granularity of the buffer status reports, by the frequency of the Scheduling Request and buffer status report transmissions and by the delay between the reception of the Scheduling Request or buffer status report and the scheduling decision.
For delay sensitive services with periodical packet arrival, such as Voice over Internet Protocol (VoIP), the likelihood that the buffer status information is outdated when it is used is high. It is likely that additional data has arrived since the buffer status report was transmitted. It is also likely that the buffer will be emptied frequently and therefore the only available information will be a one bit Scheduling Request.
With incorrect uplink information, the scheduler will provide either a too large grant, which then results in the terminal transmitting padding and may reduce system capacity, or a too small grant, which may lead to Radio Link Control (RLC) segmentation and increase transmission delay.
Uplink buffer status reports are needed in order for the base station to know the amount of data waiting for transmission in the terminal. In E-UTRAN uplink buffer status reports refer to the data that is buffered for a Logical Channel Group (LCG) in the terminal. Four LCGs and two formats are used for reporting in uplink:
A short Buffer Status Report format, which contains the buffer size of one LCG and a long Buffer Status Report format, which contains the buffer sizes of all four LCGs.
Uplink buffer status reports are transmitted using MAC signalling.
According to the previously known solution in LTE, a framework for buffer status reporting is specified. Buffer status reporting is used by the terminal to report to the eNodeB the amount of data stored in its buffers for transmission. The eNodeB uses these reports to allocate resources to the terminal, and to prioritize resource allocation between different terminals.
The terminal triggers a regular Buffer Status Report and Scheduling Request when uplink data becomes available for transmission and if this data belongs to a radio bearer, i.e. logical channel, group with higher priority than those for which data already existed in the buffer or if the terminal buffers were empty just before this new data became available for transmission.
In case the transport block size is larger than the amount of data available for transmission at the time of assembly of the MAC Protocol Data Unit (PDU) for transmission, one Buffer Status Report can also be including, also referred to as a padding Buffer Status Report. In case the terminal has data for more than one logical channel but a Buffer Status Report format that can only contain information about one logical channel, a truncated format is also available as padding Buffer Status Report.
Another type of Buffer Status Report, the Periodic Buffer Status Report, provides a timer-based trigger per terminal to handle reporting for continuous flows.
FIG. 1 shows a simplified example of what might happen when a scheduling principle adopted for best-effort data services is applied to VoIP, resulting in unnecessary delay and many grant transmissions. The scheduling request triggers a small grant that only allows a Buffer Status Report and a small amount of data. While waiting for the grant, another packet arrives. So first two grants are spent to transmit one single packet and a packet that could have been transmitted with the second grant has to wait for another grant.
The current buffer status reporting framework has several shortcomings, such as e.g. the Buffer status information is likely to be outdated when used in scheduling decisions. Also, buffer status information is likely to be based on only a 1-bit Scheduling Request when used in scheduling decisions. Further, a solution to determine buffer status in a more efficient way would be most useful.

Method and arrangement in a wireless communication system


A continuous process with increased production throughput of a high dropping point lithium complex grease composition comprising the steps of heating a mixture of a C12 to C24 hydroxy fatty acid or a C12 to C24 hydroxy fatty acid ester, an aqueous solution of lithium base and at least one base oil at an elevated temperature; removal of volatiles (i.e., water and methanol, etc.) in a dehydration zone; and transferring the mixture to a recycle line wherein additives, a borated additive and at least one base oil are added to afford a formulated grease composition.

Lithium soaps are the most common thickeners used in the formulation of lubricating greases. Lithium soaps used for grease making are classified into two types: simple soap and complex soap. The main performance difference between the two is the greater thermal stability of the lithium complex greases as seen in the dropping point (ASTM D566 or D2265). Both types contain the lithium salt of a fatty acid. Lithium complex soaps contain an additional lithium salt, or "complexing agent", most commonly a dilithium salt of a low molecular weight dibasic organic acid or dibasic ester.
Lithium greases can be manufactured by continuous process in a heated tube reactor (U.S. Pat. Nos. 4,297,227; 3,475,335; and 4,444,669). The process is most convenient and problem-free for simple lithium soap thickened greases. However, lithium complex greases having much higher thickener concentrations resulted in increased difficulties during continuous production. These difficulties include wide fluctuations in flow rates, cessation of flow and resultant downtime, and greatly reduced unit production capacity.

Continuous lithium complex grease manufacturing process with a borated additive


A carrier body for electrical or electronic component elements or circuits, the carrier body being electrically nonconductive or virtually nonconductive. In order to simplify the carrier body while at the same time providing extremely improved heat dissipation, the invention process that the carrier body is provided integrally with heat-dissipating or heat-supplying cooling elements.

According to the prior art, planar structures are constructed for dissipating heat from modules of power electronics, which structures dissipate the heat diffusing from a heat source (active or passive electrical components) via numerous interlayers (solders, conductive pastes, adhesive compounds, metallizations) into an electrically nonconductive, uniformly shaped, simple geometric body (disc, rectangular substrate). Although the geometry of the individual components is simple, the entire layer construction is complicated and requires consecutive application of a very wide variety of processes which are susceptible to faults, such as adhesive bonding, pressing, screwing and also, to a limited extent, soldering. Each interface of this stacked construction represents a barrier for heat transfer and reduces either the reliability and/or the life of the module (oxidation, breakdown, ageing) or limits its performance.
Organic and ceramic circuit carriers (carrier bodies) having low or insufficient thermal conductivity need to be attached in a permanently interlocking manner to a metallic cooling body by additional measures, such as electrically insulating interlayers. As the thermal loads increase, some of the heat sources need to be removed from the printed circuit board and mounted, in the conventional sense, on a metallic cooling body and electrically connected to the circuit carrier.
The construction comprising a plurality of different materials is complex and a compromise in terms of long-term reliability. An increase in the power density is only possible to a small extent.
The thermal conductivity can only be used to a certain extent since a planar-parallel construction is involved.
A direct combination of an electrically conductive cooling body and a heat source is likewise not possible.
In order to simplify the carrier body whilst at the same time providing extremely improved heat dissipation, the invention proposes that the carrier body is provided integrally with heat-dissipating or heat-supplying cooling elements.


The invention comprises systems, methods and computer-readable media for providing multiple-resource management of a cluster environment. The method embodiment of the invention is illustrative and comprises, at a cluster scheduler, defining a resource management interface, identifying a location of a plurality of services within the cluster environment, determining a set of services available from each of the plurality of resource managers, selecting a group of services available from the plurality of resource managers, contacting the group of services to obtain full information associated with the computer environment and integrating the obtained full information into a single cohesive world-view of compute resources and workload requests.

1. Field of the Invention
The present invention relates to managing resources in a compute environment and more specifically to a system and method of querying and controlling resources in a compute environment such as a multi-cluster environment.
2. Introduction
Grid computing may be defined as coordinated resource sharing and problem solving in dynamic, multi-institutional collaborations. Many computing projects require much more computational power and resources than a single computer may provide. Networked computers with peripheral resources such as printers, scanners, I/O devices, storage disks, scientific devices and instruments, etc. may need to be coordinated and utilized to complete a task.
Grid/cluster resource management generally describes the process of identifying requirements, matching resources to applications, allocating those resources, and scheduling and monitoring grid resources over time in order to run grid applications as efficiently as possible. Each job submitted for processing will utilize a different set of resources and thus is typically unique. In addition to the challenge of allocating resources for a particular job, grid administrators also have difficulty obtaining a clear understanding of the resources available, the current status of the grid and available resources, and real-time competing needs of various users. General background information on clusters and grids may be found in several publications. See, e.g., Grid Resource Management, State of the Art and Future Trends, Jarek Nabrzyski, Jennifer M. Schopf, and Jan Weglarz, Kluwer Academic Publishers, 2004; and Beowulf Cluster Computing with Linux, edited by William Gropp, Ewing Lusk, and Thomas Sterling, Massachusetts Institute of Technology, 2003.
It is generally understood herein that the terms grid and cluster are interchangeable in that there is no specific definition of either. The definition of a grid is very flexible and may mean a number of different configurations of computers. The introduction here is meant to be general given the variety of configurations that are possible. In general, a grid will comprise a plurality of clusters as is shown in FIG. 1. Several general challenges exist when attempting to maximize resources in a grid. First, there are typically multiple layers of grid and cluster schedulers. A grid 100 generally comprises a group of clusters 110, 112 or a group of networked computers. A grid scheduler 102 communicates with a plurality of cluster schedulers 104A, 104B and 104C. Each of these cluster schedulers communicates with a plurality of resource managers 106A, 106E and 106C. Each resource manager communicates with a series of compute resources shown as nodes 108A, 108B, 108C within cluster 110 and 108D, 108E, 108F in cluster 112.
There are various vendors of resource managers 106A, 106B, 106C that require differing means of communication to and from the resource manager. For example, one resource manager vendor may have software that only communicates with certain types of compute resources, such as MicroSoft or Linux operating systems, hard drives using certain protocols and so forth. This can cause challenges when a cluster includes a variety of cluster resource managers in order to communicate with these differing products.
Other challenges of the model shown in FIG. 1 exist as well. Local schedulers (which may refer to either the cluster schedulers 104 or the resource managers 106) are closer to the specific resources 108 and may not allow grid schedulers 102 direct access to the resources. Examples of compute resources include data storage devices such as hard drives and computer processors. The grid level scheduler 102 typically does not own or control the actual resources. Therefore, jobs are submitted from the high level grid-scheduler 102 to a local set of resources with no more permissions that then user would have. This reduces efficiencies.
Another issue that reduces efficiency is the heterogeneous nature of the shared resources. Without dedicated access to a resource, the grid level scheduler 102 is challenged with the high degree of variance and unpredictability in the capacity of the resources available for use. Most resources are shared among users and projects and each project varies from the other.
Furthermore, the performance goals for projects differ. Grid resources are used to improve performance of an application but the resource owners and users have different performance goals: from optimizing the performance for a single application to getting the best system throughput or minimizing response time. Local policies may also play a role in performance.
A bottleneck in the middleware component of the cluster or grid environment is the difficulty in communication and managing the diverse compute resources. If the clusters 110 and 112 include a group of compute resources that have diverse communication protocols and requirements across different resource managers 106A, 106B, 106C, then a cluster manager or company establishing or provisioning a cluster may need to purchase or license multiple resource managers to communication and assign jobs to all the compute resources.
FIG. 2 illustrates the prior art in more detail. Typically the cluster scheduler 104A communicates with only one resource manager server 106A. The resource manager server 106A retrieves data from a number of resource manager clients 120A, 120B, 120C that are located on each of the compute hosts 122A, 122B, 122C within a respective cluster node 108A, 108B, 108C. The clients 120A, 120B, 120C obtain information regarding the state of the node 108A, 108B, 108C, the load on the node, the configuration of the node, and similar properties.
This model is acceptable for simple clusters but it has a number of problems. A primary problem in this scenario is that the cluster scheduler's view of the compute resources is bound by the resource manager server 106A and it is not able to obtain any information that is not contained within the resource manager 106A. The cluster scheduler 104A is not able to take any action that is not within the scope of the communication and control capabilities of the resource manager 106A. For an end user or a customer site, they are bound to select a single resource manager and are unable to pick and choose one resource manager combined with the features of another. The standard resource manager 106A is designed on a locked-in model and purchasers must simply find the best resource manager with the combination of features and purchase it or look to purchasing and incorporating multiple and diverse resource managers to meet all their needs.
What is needed in the art is a way of allowing a scheduler to contact multiple sources of information and multiple sources of control so that an end user site can pick and choose which groupings of services to utilize from multiple sources. What is further needed in the art is an improved method and system for managing the disparate compute resources at a single location within the context of a cluster environment where there are a variety of cluster resource managers and a variety of compute resources.

System and method for providing multi-resource management support in a compute environment


A Combinatorial Optical Processor and method for the architecture of optical systems utilizes one or more optical modules, each module including a number of individually addressable optical elements. The optical elements are arranged and addressed in a combinatorial-arithmetic fashion such that a set of optical filter functions are defined, and can be performed, by the optical modules. The number of optical filter functions may be an exponential function of the number of addressable optical elements. Additionally, each of the optical filter functions may be addressed at random and a plurality of such functions may be addressed simultaneously. Apparatus, such as imaging systems, may employ the Combinatorial Optical Processor in order to include without limitation the features of being solid-state, projection of images into free space and random addressability of the filter functions of the system. Combinatorial optical processing principles may be implemented as a method of optical digital to analog conversion. A free-space randomly-addressable interactive three-dimensional display system based on the Combinatorial Optical Processor is also described.

In U.S. Pat. No. 5,148,310, "Rotating flat screen fully addressable volume display system," an angular multiplanar volumetric display system was described that solved a number of the problems related to the generation of three-dimensional (3-D) images. That invention, like others in its class, was based in part on the projection of scanned images onto a moving, and in this case, rotating, display screen. The benefits of multiplanar techniques over other methods for achieving 3-D imaging, include a wide field of view and observation without requiring the use of special viewing glasses.
Despite the benefits mentioned above, many problems still exist in the generation of practical 3-D displays. The first problem is that of making the entire system solid-state, i.e., having no moving parts.
Another problem is that the displayed images should exist in free space, i.e., wherein the display region is generally not enclosed or occupied by a substrate material.
Yet another problem is that an observer should be able to control the display system with the use of a physical pointer. Ideally, observers could control the display by merely reaching into the display region and "touching" desired 3-D image with their hand or finger.
A further problem is that the display should be widely scalable in parameters such as size, resolution, gray-scale and color. Fifth, the display should be simple to produce, compact and have relatively low cost.
Another problem is that any portion of the display region should be randomly addressable without dependence on a faster scan rate.
Still a further problem is that the refresh rate of the display should be scalable, beyond the 20–60 Hz requirement of human persistence of vision, to the range of kHz or faster for increased resolution and additional applications, i.e., such as machine vision, data storage, optical computing and optical networking, etc.
Above, several well-known problems that relate to the engineering of 3-D displays have been described; in fact, these problems are a subset of the broad challenges sweeping throughout many applications of optics in general.


The present invention relates to a via structure having an open stub and a printed circuit board having the same. In accordance with an embodiment of the present invention, a via structure having an open stub including: a signal transmission via passing through an insulating layer; upper and lower via pads for connecting first and second transmission lines, which are respectively formed on and under the insulating layer, and the signal transmission via; and at least one open stub connected to an outer periphery of each via pad to have a shunt capacitance with each ground pattern formed on and under the insulating layer is provided. Further, a printed circuit board with a via having an open stub is provided.

1. Field of the Invention
The present invention relates to a via structure having an open stub and a printed circuit board having the same, and more particularly, to a via structure having an open stub that has an open stub connected to a via pad, and a printed circuit board having the same.
2. Description of the Related Art
As the transmission rate of mobile devices such as PCs, mobile phones, and tablet PCs and the data rate increase, the amount of data transmitted through a circuit board and the usable frequency are also increasing.
Conventional signal transmission via in a substrate and circuit board have a structure in which a via passing through an insulating layer is connected between a first transmission line for receiving a signal and a second transmission line for outputting a signal through a via pad.
The longer the line and the higher the frequency, the greater the transmission loss value of a signal transmission channel of the circuit board having the conventional via and via pad, and return loss characteristics are also deteriorated due to specific impedance discontinuity occurring in the via and so on.
The characteristics of the conventional signal transmission channel will be described with reference to FIGS. 7 and 8.
FIG. 7 is a view showing a signal transmission channel equivalent circuit in the conventional via structure and circuit board, and FIG. 8 is a graph showing signal transmission channel characteristics in the conventional via structure and circuit board in accordance with FIG. 7.
FIG. 7 is a channel equivalent circuit of the conventional via pad structure, and a resistor R1 and L1 between transmission lines represent equivalent resistance and inductance of the via. In the via having the conventional via pad, since a capacitance between a top via pad without an open stub and a ground plane and a capacitance between the top via pad and an inner layer upper via pad are negligibly low, they can be omitted from the equivalent circuit, and a capacitance between a bottom via pad and the ground plane and a capacitance between an inner layer lower via pad and the bottom via pad are the same. In the signal transmission channel having the conventional via pad, as shown in FIG. 8, as the frequency increases, the loss increases and the return loss characteristics are deteriorated.

Via structure having open stub and printed circuit board having the same


Provided are a blue-light-emitting iridium complex, an iridium complex monomer, a phosphorescent polymer, and an organic electroluminescent device using same. The blue-light-emitting iridium complex contains a ligand having a low electron density structure, such as triazole or tetrazole. The iridium complex monomer containing a ligand having a polymerizable vinyl group produces a blue phosphorescent polymer through the polymerization with carbazole derivatives. The organic electroluminescent device comprises a first electrode, a second electrode, and a light-emitting layer interposed between the first electrode and the second electrode, wherein the light-emitting layer contains the above-described iridium complex or polymer containing the iridium complex.

An electroluminescent device does not require a backlight, has a fast response speed, and also has excellent brightness and viewing angle characteristics as it is a self-light-emitting device. In particular, an organic electroluminescent device may be manufactured in the form of a thin film with a bendable structure. Moreover, the formation of patterns and the mass production by thin film manufacturing techniques are easy, and the driving voltage is low. Furthermore, the organic electroluminescent device can theoretically emit light of all colors in a visible light region. Thus, great efforts to develop light-emitting materials used in the organic electroluminescent devices have continued. However, since blue-light-emitting materials should have a wide band gap, it is difficult to synthesize and drive the blue-light-emitting materials compared to green and red-light-emitting materials. Therefore, in order to implement the organic electroluminescent device as a natural-color flat-panel display, it is necessary to continuously develop blue-light-emitting materials with improved efficiency, color, and stability.

Blue-light-emitting iridium complex, iridium complex monomer, phosphorus polymer, and organic electroluminescence device using same

GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY


A laminate preform is disclosed, having a top side and a back side extending between respective edge portions, the laminate preform comprising a plurality of layers of fiber tows extending in a length direction of the laminate pre-form, the fiber tows being at least partly fixed by resin. The laminate pre-form is in between a first and a second prepreg or semi-preg layer including fibers extending in an oblique direction with respect to the length direction, and at least one distribution channel is provided at the back side extending in the length direction. Also disclosed is a method for manufacturing such a laminate pre-form.

Composite structures, such as wind turbine blades, usually comprise a plurality of layers of sheets made of fibres embedded in a resin. These semi-finished component can be called pre-forms.
Traditionally, such preforms have been produced by cutting layers of sheets from an endless sheet material of fibres in a resin, and stacking them in layers on each other to form a composite structure. The composite structure is then consolidated by removal of any air trapped between the layers of the structure, usually by applying a vacuum. During this consolidation procedure, additional resin may be introduced to, or infused in, the structure to fill any voids therein to strengthen the structure.
Air trapped in the pre-form may decrease the strength of the finished pre-form, and is therefore unwanted.
WO 2009/077582 discloses a method for preparing a pre-form comprising several layers of fibre tows being fixed by a resin. In order to remove trapped air from the pre-form, an encapsulation step is suggested, allowing air removal from the enclosure to draw out the trapped air. To facilitate removal of trapped air, the layers of resin may be distributed in a non-continuous manner.
WO2004/078442 discloses a method for fabricating a pre-consolidated pre-form comprising a resin and a plurality of layers of oriented fibers arranged in fibre tows.
A pre-form is a composite material comprising fibres and an uncured or only partly cured resin. The fibres are preferably provided in layers of oriented fibres like for example individual fibres, fibre tows, fibre tow-pregs or prepregs.
By pre-consolidation is herein meant a process, whereby gas inside a pre-form is removed and a low porosity pre-form is produced. Pre-consolidation involves redistribution of a resin and optionally a redistribution of fibres. Furthermore, pre-consolidation may involve a limited curing of the resin. Pre-consolidation is particularly useful as it produces a dense pre-form (hereinafter named a pre-consolidated pre-form). Pre-consolidated pre-forms and composites prepared from pre-consolidated pre-forms will be appreciated amongst others due to good reproducibility, low porosity, high homogeneity, high strength, ability to plastically shaping of the pre-consolidated pre-form, ability to be connected to other pre-forms and/or other structures, suitability for automation and long shelf life without premature curing.
The present invention provides an improved technique of facilitating the removal of trapped air in a pre-consolidating process. The present invention provides an improved technique for reducing the occurrence of intra-layer voids during the formation of a pre-consolidated prepreg. With intra-layer voids is here intended voids that may appear inside a prepreg structure.

Laminate pre-form for a wind turbine blade


A process for the formation of a device edge morphological structure for protecting and sealing peripherally an electronic circuit integrated in a major surface of a substrate of semiconductor material includes formation above an intermediate process structure of a dielectric multilayer comprising a layer of amorphous planarizing material. The process also includes the partial removal of the dielectric multilayer so as to create at least one peripheral termination of the multilayer in the device edge morphological structure. Removal of the dielectric multilayer requires that the peripheral termination thereof be located in a zone of the intermediate process structure relatively higher than the level of the major surface, if compared with adjacent zones of the intermediate structure itself at least internally toward the circuit and in so far as to the device edge morphological structure.

As is well known, electronic devices, in particular those integrated monolithically, if not carefully protected and sealed can be critically affected by the environmental conditions in which they are placed during assembly and/or during their lifetimes. In particular, the presence of humidity and other contaminating agents can result in the entry of undesired materials into the electrically active part of the device. This generally reduces the reliability of the device and can even irreversibly compromise its operation.
It is therefore crucial, especially for certain applications, to make the best possible provision for protection and sealing of the electrical circuit which is part of the device. For this purpose it is necessary to ensure perfect sealing also at the edge of the device.
For the meaning of edge of a device it should be remembered that a plurality of identical monolithically integrated circuits are formed simultaneously on a single wafer of semiconductor material, commonly monocrystalline silicon, in adjacent prepared areas. The individual devices are spaced and separated by unoccupied cross strips in which the surface of the silicon is left exposed. These strips are typically mutually orthogonal and are known as "scribe lines" and the wafer will be cut through them mechanically to separate the individual devices (the so-called "dicing" process) The edge of a device is thus the peripheral region thereof bordering on the associated scribe line.
After formation of the circuit electrical structures, i.e., of the electrical components, such as, for example, transistors or memory cells and their interconnections, the device is insulated and sealed. Layers of dielectric materials act as electrical and thermal insulators of the conducting interconnection layers and protect the underlying structures of the integrated circuit from mechanical stress such as impacts or from contaminants (impurities, moisture) by creating a barrier against those harmful substances coming from the environment.
The so-called final passivation includes a relatively thick layer completely covering the device to protect it. However, at the edge of the device the presence of the final passivation alone is not sufficient to ensure its sealing. Other measures are necessary. For this purpose primarily the most peripheral structures of the device are typically left inactive, i.e., disconnected electrically from the device terminals.
More specifically, for protection of the device at the edges there is formed a structure arranged peripherally which also permits sealing of the device. This is a device edge morphological structure and reference will be made thereto in the following description. It includes a closed ring completely surrounding the device along its entire periphery. This structure is known to those skilled in the art as Chip Outline Band (COB) i.e., a band surrounding the device.
The device edge morphological structure is formed simultaneously with the electrical structures of the integrated circuit. The more internal part of the COB, i.e., the part nearest the device, does indeed normally include structures which appear morphologically identical to the electrically active ones of the device. However, they do not have any electrical function since they are electrically insulated, but only act as termination for the device end. The COB structure is consequently different in different devices depending on the process used and the device design.
In any case the more external part of the COB, which terminates in the scribe line adjacent to and is contiguous with the preceding part, is designed so as to completely seal the device from the external environment. For this purpose there is applied the simple principle in accordance with which, to permit better sealing, each overlying layer must be terminated more externally than the one immediately below. The layers are disposed to virtually cover and enclose the previous layer. This way the edge descends gradually downward while going near the associated scribe line, such as to enclose the integrated circuit in subsequent shells, several times. An example of a device edge morphological structure of known type is shown in FIG. 1. Specifically there is represented in cross-section, not to scale, a peripheral portion of a single device. By way of example this is in particular a CMOS device, such as typically a memory circuit.
It is necessary to remember that in the more complex integrated circuits it is becoming ever more pressing to limit the area occupied by reducing the size of the components, and, thus, of the device to thereby increase the total number of devices which can be integrated on a single wafer. Accordingly, two or more interconnection levels are provided. It is in this framework that the present description is placed. The device to which reference is made by way of example in the figure comprises two interconnection levels.
In FIG. 1 the visible portion of the device edge morphological structure is indicated as a whole by reference number 1. Further to the right of the figure is seen a scribe line which is shown only partially and indicated by reference number 2, while to the left the device edge morphological structure 1 joins the active part of the device, i.e., the actual circuit (not shown in the figure). It should be remembered that the device edge morphological structure is shown in its most peripheral portion--in some cases another portion thereof comprising other electrically inactive structures could be present at the device periphery.
In FIG. 1 for greater clarity the COB is divided approximately and ideally in two regions as set forth above: a region indicated by reference number 3 placed more internally with respect to the circuit and comprising structures defining a sort of extension with continuity of the device circuit structures, and a region 4 which is more external or peripheral and has a device sealing function. The device is formed in a major surface 5 of a substrate 6 of monocrystalline silicon. The process calls for simultaneous formation of the circuit and its edge structure.
Once the structure of the electric circuit components (not shown in the figure) have been completed, a so-called "intermediate" dielectric layer acting as their insulation is formed above. In FIG. 1 can be seen the portion, indicated by reference number 7, of this layer which is included in the device edge morphological structure 1. Conventionally the intermediate dielectric comprises a Boron Phosphorus Silicon Glass (BPSG) layer, i.e., silicon oxide doped with boron and phosphorous. In the intermediate dielectric there are opened appropriate holes to the surface 5 of the substrate to allow contact therewith by overlying conducting levels.
A first interconnection level, i.e. a metallization layer, typically aluminum, more briefly known as "METAL 1", is overlaid on the intermediate dielectric 7. The first metallization layer, indicated by reference number 8, has portions in direct contact with the surface 5 through the above mentioned holes, denominated contacts, formed in the intermediate dielectric and not shown in the figure.
The metallization layer 8 is then patterned so as to have the appearance of metallic strips. As shown in FIG. 1, in this embodiment the METAL 1 in region 4 has a peripheral termination in contact with the surface 5 of the substrate 6. This peripheral termination is more external than the peripheral termination of the intermediate dielectric 7.
Over the first interconnection level 8 is formed a multilayer of dielectric material to insulate it from a subsequent second overlying metallization layer or briefly "METAL 2" indicated by reference number 9. In the description given below reference is made to this multilayer as to an intermetallization dielectric multilayer or intermetallization dielectric because it is placed between two metallization layers. The intermetallization dielectric is indicated as a whole by reference number 10 and also acts as a planarizer of the surface before formation of the second metallization layer 9 to ensure a deposition and a definition thereof without drawbacks.
As shown in FIG. 2 indeed, after formation of the METAL 1 layer, the resulting intermediate process structure displays zones with different heights. The intermediate process structure for this exemplified process is indicated as a whole by reference number 11 in the figure. It comprises the intermediate dielectric layer 7 and the first interconnection layer 8 already patterned. It can be observed from the figure that the free surface of the structure 11 displays considerable differences in height with a sort of stepped profile. This is true in general and to a different degree even in other process steps and typically is true for the intermediate structures created after deposition of each interconnection level.
As shown in FIG. 1, to planarize the surface of the structure 11, the overlying intermetallization dielectric 10 includes a layer of Spin-on Glass (SOG) which as known is commonly used for planarization in various steps of the formation of the integrated circuits. This is an amorphous material which is deposited in the fluid state, as a solution, by means of a "spinning" process, i.e., being sprayed over the entire surface of the wafer where it is deposited in such a manner as to fill the deepest zones and smooth the irregularities of the underlying structure. After hardening by evaporation of the solvent, a following anisotropic etching of the SOG leaves its top surface virtually planar, although a slight meniscus is formed because of the surface tension of the material. The etching is stopped when the relatively higher zones of the underlying structure are completely exposed.
It should be remembered, however, that the SOG, since it is a highly contaminating material because of its origin, must be enclosed between insulating layers so as not to come into contact with the active structures of the circuit. Specifically, as shown in FIG. 1, the intermetallization dielectric 10 hence includes a first layer comprising a silicon oxide, typically TEOS (tetraethylorthosilicate) indicated by 12, a layer of SOG 13 and a second layer of TEOS 14. The TEOS is chosen preferably because it has good chemical and physical characteristics and is a material which does not introduce contamination.
In accordance with the prior art process the first TEOS layer 12 is arranged conformal with the intermediate process structure 11 (FIG. 2) and accordingly displays a profile which is still not planar. Formation of SOG in accordance with what above mentioned so as to fill only the deepest portions, permits planarization of the surface. In this manner, after the conformal deposition of the second TEOS layer 14 there is obtained a virtually planar surface for deposition of the second interconnection level 9.
Following its formation, holes are opened in the intermetallization dielectric 10 by means of masking, these holes permitting formation of the so-called VIAs for contact between METAL 2 and METAL 1. As may be seen in the figure, in region 4 of the device edge morphological structure 1 the intermetallization dielectric 10 is terminated outside the termination of the first conducting layer 8, in accordance with the principle set forth above to ensure good sealing of the device. In accordance with a prior art technique, formation of the peripheral termination of the intermetallization dielectric multilayer takes place simultaneously with formation of the openings of the VIAs in the intermetallization dielectric 10, i.e., by using an opening in the same mask.
FIG. 1 shows a single VIA 15 in the region 3 of the edge morphological structure 1. The intermetallization dielectric 10 is, therefore, discontinuous since it is separated in two portions, one, indicated by reference number 10', being included in the region 3 and the other, shown by reference number 10", extending into both regions 3 and 4 of the morphological structure 1.
On this subject it should be remembered that formation both of the contacts, which allow connection between a metallic interconnection and the substrate or circuit components, and of the VIAs between conducting layers of different levels is very critical in very large scale integration manufacturing processes because of the extremely small cross-sectional dimensions which they must have and of the relatively great thickness of the dielectric layer through which the holes must be made. Under these conditions during sputtering deposition of the metallization layer which will form the contact the cover of the vertical walls of the "holes" becomes unsatisfactory and the metal deposited can display unacceptable thinning. On the other hand, it is not possible to reduce the thickness of the dielectric layer, and, hence, the depth of the contact proportionately to the cross-sectional dimensions. An approach commonly used includes using, for the metallization portion which is to be inside the holes, a metallic material, typically tungsten, titanium and/or titanium nitride, which can be deposited by chemical vapor phase deposition to allow easy filling of the hole.
In this direction there was developed a technique according to which the holes are first filled with tungsten plugs. The aluminum layer is then deposited so as to form the conducting layer. Techniques of this type are described, e.g., in the articles, "Selective CVD of tungsten and its applications to MOS VLSI" by Takahiko Moriya and Hitoshi Itoh, VLSI Research Center, Toshiba Co., presented at the Workshop 1985 of the Material Research Society; "A study of tungsten etchback for contact and VIA fill applications" by Jen-Jiang Lee and Dennis C. Hartman, presented at the IEEE VLSI Multilevel Interconnection Conference (VMIC), 1987.
More specifically, in accordance with a process to which specific reference is made in the following embodiments of the present invention, for the formation of the contacts and the VIAs in the holes there is first deposited a pre-adhesion or barrier layer. Typically the barrier layer comprises a first layer of titanium (Ti) on which is deposited a second layer of titanium nitride (TiN)(altogether Ti/TiN) for a total thickness varying between 50 nm and 90 nm. On the barrier layer a tungsten layer is then deposited by the CVD technique. A subsequent etching leaves the tungsten only in the holes in the form of plugs. This technique is described for example in European patent application no. 0543254 assigned to the assignee of the present invention. An improvement of this technique is described in European patent EP 0571691 also assigned to the present assignee
In FIG. 1 the barrier layer Ti/TiN is indicated by reference number 16 and the tungsten plug by reference number 17. It is noted that, since the process calls for the peripheral termination of the intermetallization dielectric 10 to be obtained by means of a mask for formation of the VIAs, a tungsten residue is also present in the zone of the above mentioned termination. As may be seen in the figure, since an anisotropic etching is used, after partial removal of the tungsten for formation of the plugs a so-called tungsten bead, indicated by reference number 18, with an underlying very thin barrier layer (not shown), remains beside the above mentioned termination.
Like the first interconnection level 8, the second level 9 also terminates by contacting the surface 5 of the substrate more peripherally than the termination of the intermetallization dielectric multilayer. A relatively thick final passivation layer, indicated by reference number 19, completes formation of the device by providing protection of the circuit elements and the interconnection levels.
To allow separation of the devices provided on the same wafer the final passivation layer is then etched in the scribe line region, i.e., in region 2, until reaching the substrate surface 5. The scribe line has been formed at this stage. FIG. 1 shows the device as it appears at the termination of this step.
The process for formation of the device edge morphological structure 1 just described concomitantly with the electrical circuit formation process and illustrated in FIGS. 1 and 2 displays, however, some drawbacks which appear evident from an analysis of the obtained structure 1. It should be noted in fact that normally the SOG, in accordance with the conventional planarization process with three layers diagramed above, is completely enclosed between dielectric material layers. This is visible even in FIG. 1 in the region 3 of the device edge morphological structure, i.e., as concerns the intermetallization dielectric portion 10 placed more internally, to the left of the VIA 15.
However, as shown in FIG. 1, in accordance with the process for the formation of the device edge morphological structure in accordance with the prior art in the more external portion of the intermetallization dielectric multilayer 10 placed to the right of the VIA 15 and extending between the two regions 3 and 4, the SOG is not completely incorporated. Indeed, the intermetallization dielectric 10 in region 4 of the morphological structure 1 declines slowly in the direction of the device edge towards the surface 5 of the silicon until it reaches it. At the same time the SOG layer which as mentioned above forms a slight meniscus, is slowly thinned. The terminal etching of the intermetallization dielectric multilayer 10 immediately outside the termination of the first interconnection level 8 is performed in a zone where the thickness of the SOG layer 13 is not yet sufficiently reduced. Cutting of the multilayer 10 in accordance with the process described is performed far enough from the edge of the device so as to still permit formation further peripherally of the termination of the second interconnection level 9 in contact with the substrate. Accordingly the SOG terminal portion is not insulated from the second metallization layer 9, but instead is in contact with the tungsten bead 18.
The presence of SOG exposed to the next metallization layer 9 can give rise to a defects. In a certain percentage of devices there may in fact occur delayering of the overlying metallization level. As known to those skilled in the art, each SOG layer, if it has not been perfectly cured, shrinks before formation of the next metallization layer. The behavior of this material is due to a natural phenomenon known as outgassing. The problems of defects connected therewith when the outgassing occur at the interface with a metallization layer, as in our case, are illustrated for example in the article of C. Chiang, N. V. Lam, J. K. Chu, N. Cox, D. Fraser, J. Bozarth, B. Mumford, entitled "Defects study on spin on glass planarization technology", Proceedings Conference VMIC, 1987; and in the article of M. Kobayakawa, A. Arimatsu, F. Yokoyama, N. Hirashita, T. Ajioka, entitled "A study of outgassing from spin-on-glass films used for planarizing", Proceedings Conference VMIC, 1991. As analyzed in these articles the outgassing also leads to formation of structural defects in the metallic layers in direct contact with the SOG.
In addition, in the process just described and illustrated the presence of the tungsten bead in contact with the SOG enormously worsens the problem. As shown in FIG. 1 the SOG layer 13 when shrinking inwardly, before formation of the barrier layer Ti/TiN 16, leaves an empty space indicated by reference number 20 between the more external edges of the two dielectric layers 12 and 14. The side surface of the termination of the intermetallization dielectric 10, obtained after cutting of the dielectric and which must be covered by the second interconnection level, because of the SOG shrinkage, is accordingly irregular and with a negative slope.
This induces a stress in the barrier layer 16. To this is added the fact that the thickness of the barrier layer 16 is much reduced as described above and is deposited by an anisotropic technique, and, therefore, on such a negative step it is thinned, i.e., it does not have uniform thickness, and can even be missing at some points. For these reasons delayering of the barrier may occur, i.e., partial lifting thereof along the contact with the termination of the intermetallization dielectric.
The tungsten layer formed at this point is deposited both outside and inside the lifted edges of the barrier layer 16. It should be remembered that, during a common process for forming tungsten, tungsten fluoride is typically used as a source. This highly corrosive gas is able to penetrate any holes present in the barrier layer. Also the tungsten has high stress. The tungsten etching necessary for formation of the plugs thus generates a highly defective structure with holes. The following metallization layer 9 can accordingly be delayered, differently from how it appears in the ideal case shown in FIG. 1.
The device can be damaged in case of marked delayering in which there can be generated on the surface of the wafer residues of delaminated layers which cause short circuiting of active metallizations. The seriousness of the problem is on the other hand due to the fact that such a defective structure in the device edge morphological structure, which as such is not electrically active, may not immediately damage the functionality of the device. That is, the device in which this delayering phenomenon occurred at the terminal part of the METAL 2 would be functioning and would not fail upon testing. However, once operating it would become clearly unreliable in a more or less short time because it is not correctly sealed.
The problem described is accentuated in the devices located near the wafer edge, in which the barrier layer is thinned because it forms a meniscus upon deposition. A known attempt to solve this problem was given recently and is illustrated in FIG. 3. In this figure there is shown the same portion of the device edge morphological structure, here indicated by reference number 1', as in the preceding figure. The same reference numbers are kept for the same or equivalent structures and parts.
The approach includes modifying the etching masks of the VIAs, virtually avoiding opening a contact VIA in the intermetallization dielectric, whether in the more external region 4 of the device edge morphological structure or along the adjacent scribe line, for generating the peripheral termination of the layer. This means not etching the intermetallization dielectric in this zone as shown clearly in the figure. This avoids etching the SOG.
The layer of intermetallization dielectric 10 is accordingly as one might say extended to reach the region of the scribe line 2. It is etched away only during the following step of formation of the scribe line. This way the SOG layer 13 in the cutting region, i.e., the edge of the device in this case, is considerably thinned
Differently from the case illustrated in the previous figure, the peripheral termination of the second interconnection level 9 is not in contact with the substrate as shown in FIG. 3. Anyway the second metallization layer 9 is removed in the zone adjacent to the scribe line 2 so that it is always isolated from the outside by means of the final passivation layer 19. The process just described accordingly allows obviating the problem of delayering of the METAL 2 at the bead, which is drastically eliminated. But this approach displays some drawbacks.
Although the intermetallization dielectric layer 10 is greatly extended and at the scribe line level where it is cut the SOG layer 13 is very thin, it is still necessary to point out that the latter is not completely absent. A small portion of SOG remains in contact with the outside. Since the SOG is hygroscopic because of its porosity there is the risk of moisture penetrating into the device with a resulting reliability problem.
Another problem is due to the structure obtained by means of this process. As may be readily seen, the dielectric layer on the scribe line before its etching is considerably increased with respect to the previous case shown in FIG. 1. Indeed, beyond the final passivation layer, on the scribe line there is also present the intermetallization dielectric 10. The total thickness, which can reach even 3 micron (.mu.m), can be excessive in the following terms. Primarily, excessive thickness extends the total time needed for completely etching the scribe line and makes necessary an overetching to completely clean the scribe line. Thus the entire process is delayed. This also implies greater complexity in controlling the process flow.
In addition, at the end of the etching it may happen that the scribe line is not well cleaned. There may remain residue of the oxide making up the lower layer to be etched, i.e., in this case the first dielectric layer of the intermetallization dielectric, in the most critical etching zones. These zones are typically those at the edges of the scribe line, and, in particular, at the feet of the opening which must be formed, i.e., where the etching arrives with more difficulty if the step is very steep. Other critical zones are those in which the corridor to be etched is very narrow, and, therefore, where the height-to-width ratio is very high. This happens, for example, in corridors at the sides of testing structures present in the center of the scribe line and which are not to be removed in this etching step. The presence of these oxide residues mainly near the scribe line crossings can generate mechanical damage to the contiguous devices during the dicing process. From this point there is a relatively high probability that crossing fracture lines will depart towards the adjacent devices. The devices involved are clearly not well sealed.
The problem illustrated accordingly seems almost insoluble. Indeed, good sealing is prevented for any device in which SOG is to be used as the planarization layer, because of the presence of at least one subsequent metallization level. The same problem arises both in the framework of a intermetallization dielectric for a device having at least two interconnection levels, and in the case not specifically described in which the SOG is already used in the intermediate dielectric for devices having a single metallization level and in which inside the intermediate dielectric there are to be formed contacts for the first metallization level.
It should be noted that although the drawbacks described are discussed for the case exemplified in FIGS. 1-3, they can appear every time a dielectric having similar characteristics, such as an amorphous planarizing material highly contaminating especially for the metallization layers and capable of generating defects, is used for the planarization instead of SOG. In addition these drawbacks are very devastating when the contacts and the VIAs are created by means of the described plug technique.

Process for forming a morphological edge structure to seal integrated electronic devices, and corresponding device