Programming a NVM memory cell such as an NROM cell by using hot hole injection (HHI), followed by channel hot electron (CHE) injection. CHE injection increases the threshold voltage (Vt) of bits of memory cells that were disturbed (unnecessarily programmed) in HHI programming step. Page Write may be performed using a combination of only HHI, followed by CHE without any Erase.

Demand for non-volatile memory (NVM) devices, including embedded NVM in other microelectronics and IC devices, has grown rapidly in recent years due to the expansion of digital computing and processing beyond desktop computer systems to include a broader array of consumer electronic, communications, automotive and industrial products. These products include mobile phones, still and video digital cameras, personal digital assistants (PDAs), portable computers, portable digital music players, digital video recorders, set-top boxes, communication routers and switches, digital televisions and other electronic systems. Each of these products typically requires one or more non-volatile memory device(s) to store data, such as the product's operating system and may also require data storage capabilities. The flash memory market, which in 2004 was the largest segment of the non-volatile semiconductor memory market, has traditionally been divided into four segments: code flash, data flash, embedded flash and serial flash.
Historically, the most widely-used technology for non-volatile semiconductor memory devices is floating gate technology, which was developed in the late 1960s and has been the prevalent technology for non-volatile semiconductor memory devices since then. A floating gate device is a variation of a standard metal oxide semiconductor (MOS) field effect transistor (FET) in that it has an additional electrically isolated "floating gate," made of a conductive material. A floating gate device stores information by holding electrical charge within the floating gate. Adding or removing charge from the floating gate changes the threshold voltage (Vt) of the cell thereby defining whether the memory cell is in a programmed or erased state—representing a binary "1" or a binary "0" (memory cell states which may also be referred to herein as logic "1" and logic "0"), respectively or, conversely, binary or logic "0" and binary or logic "1", respectively (the definition of the erase and program states as binary or logic "1" and binary or logic "0" being somewhat arbitrary, and generally at a designer's/manufacturer's discretion).
NROM technology effectively doubles the storage capacity of each memory cell by enabling the storage of two physically distinct and independent charges, each representing one bit of information, within a single memory cell. This significantly reduces the amount of silicon wafer required for each non-volatile memory device, resulting in a significant cost reduction to semiconductor manufacturers. Further advances in NROM and related ONO technology increase storage capacity to more than two bits (binary digits) per cell by better control and/or characterization of trapped charge.
Non-volatile memory devices based on NROM or other ONO (such as SONOS) technology contain a trapping nitride layer which stores a charge, instead of a floating gate suspended above the cell. The nitride layer is usually surrounded by two insulating silicon dioxide layers (oxide). Where applicable, descriptions involving NROM are intended specifically to include related oxide-nitride technologies, including SONOS (Silicon-Oxide-Nitride-Oxide-Silicon), MNOS (Metal-Nitride-Oxide-Silicon), MONOS (Metal-Oxide-Nitride-Oxide-Silicon) and the like used for NVM devices. Further description of NROM and related technologies may be found at "Non Volatile Memory Technology", 2005 published by Saifun Semiconductor and materials presented at and through http://siliconnexus.com, "Design Considerations in Scaled SONOS Nonvolatile Memory Devices" found at: http://klabs.org/richcontent/MemoryContent/nvmt_symp/nvmts—2000/presentations/bu_white_sonos_lehigh_univ.pdf, "SONOS Nonvolatile Semiconductor Memories for Space and Military Applications" found at: http://klabs.org/richcontent/MemoryContent/nvmt_symp/nvmts—2000/papers/adams_d.pdf, "Philips Research-Technologies-Embedded Nonvolatile Memories" found at: http://research.philips.com/technologies/ics/nvmemories/index.html, and "Semiconductor Memory: Non-Volatile Memory (NVM)" found at: http://ece.nus.edu.sg/stfpage/elezhucx/mvweb/NVM.pdf, all of which are incorporated by reference herein in their entirety.
Commonly-owned patents disclose structure and operation of NROM and related ONO memory cells. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,768,192 and 6,011,725, 6,649,972 and 6,552,387.
Commonly-owned patents disclose architectural aspects of an NROM and related ONO array, (some of which have application to other types of NVM array) such as segmentation of the array to handle disruption in its operation, and symmetric architecture and non-symmetric architecture for specific products, as well as the use of NROM and other NVM array(s) related to a virtual ground array. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,963,465, 6,285,574 and 6,633,496.
Commonly-owned patents also disclose additional aspects at the architecture level, including peripheral circuits that may be used to control an NROM array or the like. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,233,180, and 6,448,750.
Commonly-owned patents also disclose several methods of operation of NROM and similar arrays, such as algorithms related to programming, erasing, and/or reading such arrays. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,215,148, 6,292,394 and 6,477,084.
Commonly-owned patents also disclose manufacturing processes, such as the process of forming a thin nitride layer that traps hot electrons as they are injected into the nitride layer. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,966,603, 6,030,871, 6,133,095 and 6,583,007.
Commonly-owned patents also disclose algorithms and methods of operation for each segment or technological application, such as: fast programming methodologies in all flash memory segments, with particular focus on the data flash segment, smart programming algorithms in the code flash and EEPROM segments, and a single device containing a combination of data flash, code flash and/or EEPROM. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,954,393 and 6,967,896.
The Field Effect Transistor
The transistor is a solid state semiconductor device which can be used for amplification, switching, voltage stabilization, signal modulation and many other functions. Generally, a transistor has three terminals, and a voltage applied to a specific one of the terminals controls current flowing between the other two terminals.
The terminals of a field effect transistor (FET) are commonly named source, gate and drain. In the FET a small amount of voltage is applied to the gate in order to control current flowing between the source and drain. In FETs the main current appears in a narrow conducting channel formed near (usually primarily under) the gate. This channel connects electrons from the source terminal to the drain terminal. The channel conductivity can be altered by varying the voltage applied to the gate terminal, enlarging or constricting the channel and thereby controlling the current flowing between the source and the drain.
FIG. 1 illustrates a FET 100 comprising a p-type substrate, and two spaced-apart n-type diffusion areas—one of which will serve as the "source", the other of which will serve as the "drain" of the transistor. The space between the two diffusion areas is the "channel". A thin dielectric layer is disposed over the substrate in the neighborhood of the channel, and a "gate" structure is disposed over the dielectric layer atop the channel. (The dielectric under the gate is also commonly referred to as "gate oxide" or "gate dielectric".) Electrical connections (not shown) may be made to the source, the drain, and the gate. The substrate may be grounded.
Generally, when there is no voltage on the gate, there is no electrical conduction (connection) between the source and the drain. As voltage (of the correct polarity) is applied to the gate, there is a "field effect" in the channel between the source and the drain, and current can flow between the source and the drain, and can be controlled by the voltage applied to the gate. In this manner, a small signal (gate voltage) can control a relatively large signal (current flow between the source and the drain).
The Floating Gate Transistor
A floating gate transistor is generally a transistor structure, broadly based on the FET, as described hereinabove. As illustrated in FIG. 2, the floating gate transistor 200 has a source and a drain, but rather than having only one gate, it has two gates which are called control gate (CG) and floating gate (FG). It is this arrangement of control gate and floating gate which enables the floating gate transistor to function as a memory cell, as described hereinbelow.
The floating gate is disposed over tunnel oxide (comparable to the gate oxide of the FET). The floating gate is a conductor, the tunnel oxide is an insulator (dielectric material). Another layer of oxide (interpoly oxide, also a dielectric material) separates the floating gate from the control gate.
Since the floating gate is a conductor, and is surrounded by dielectric material, it can store a charge. Electrons can move around freely within the conductive material of the floating gate (which comports with the basic definition of a "conductor").
Since the floating gate can store a charge, it can exert a field effect on the channel region between the source and the drain, in a manner similar to how a normal FET works, as described hereinabove. Mechanisms for storing charges on the floating gate structure, as well as removing charges from the floating gate are described hereinbelow.
Generally, if a charge is stored on the floating gate, this represents a binary "1". If no charge is stored on the floating gate, this represents a binary "0". (These designations are arbitrary, and can be reversed so that the charged state represents binary "0" and the discharged state represents binary "1".) That represents the programming "half" of how a floating gate memory cell operates. The other half is how to determine whether there is a charge stored on the floating gate—in other words, to "read" the memory cell. Generally, this is done by applying appropriate voltages to the source, drain and gate terminals, and determining how conductive the channel is. Some modes of operation for a floating gate memory cell are described hereinbelow.
Normally, the floating gate non-volatile memory (NVM) cell has only a single "charge-storing area"—namely, the conductive floating gate (FG) structure, and can therefore only store a single bit of information (binary "1" or binary "0"). More recently, using a technology referred to as "multi-level cell" (MLC), two or more bits can be stored in and read from the floating gate cell. MLC operation of memory cells is discussed in greater detail hereinbelow.
A Two-Bit (Dual Bit) Memory Cell
Another type of memory cell, called a "nitride, read only memory" (NROM) cell, has a charge-storage structure which is different from that of the floating gate memory cell and which permits charges to be stored in two separate charge-storage areas. Generally, the two separate charge storage areas are located within a non-conductive layer disposed between the gate and the underlying substrate, such as a layer of nitride formed in an oxide-nitride-oxide (ONO) stack underneath the gate. The non-conductive layer acts as a charge-trapping medium. Generally, electrical charges will stay where they are put in the charge-trapping medium, rather than being free to move around as in the example of the conductive floating gate of the floating gate memory cell. A first bit of binary information (binary "1" or binary "0") can be stored in a first portion (such as the left-hand side) of the charge-trapping medium, and a second bit of binary information (binary "1" or binary "0") can be stored in a second portion (such as the right-hand side) of the charge-trapping medium. An alternative viewpoint is that different charge concentrations can be considered for each bit of storage. Using MLC technology, as discussed in greater detail hereinbelow, at least two bits can be stored in and read from each of the two portions of the charge-trapping medium (for a total of 4 bits), similarly 3 bits or more than 4 bits may be identified.
FIG. 3 illustrates a basic NROM memory cell, which may be viewed as an FET with an "ONO" structure inserted between the gate and the substrate. (One might say that the ONO structure is "substituted" for the gate oxide of the FET.)
The ONO structure is a stack (or "sandwich") of lower oxide 322, a charge-trapping material such as nitride 324, and an upper oxide 326. The ONO structure may have an overall thickness of approximately 10-25 nm, such as 18 nm, as follows:
the bottom oxide layer 322 may be from 3 to 6 nm, for example 4 nm thick;
the middle nitride layer 324 may be from 3 to 8 nm, for example 4 nm thick; and
the top oxide layer 326 may be from 5 to 15 nm, for example 10 nm thick.
The NROM memory cell has two spaced apart diffusions 314 and 316 (which can function as source and drain, as discussed hereinbelow), and a channel region 320 defined in the substrate between the two diffusion regions 314 and 316.
The charge-trapping material 324 is non-conductive, and therefore, although electrical charges can be stored in the charge-trapping material, they are not free to move around, they will generally stay where they are stored. Nitride is a suitable charge-trapping material. Charge trapping materials other than nitride may also be suitable for use as the charge-trapping medium. One such material is silicon dioxide with buried polysilicon islands. A layer (324) of silicon dioxide with polysilicon islands would be sandwiched between the two layers of oxide (322) and (326). Alternatively, the charge-trapping layer 324 may be constructed by implanting an impurity, such as arsenic, into a layer of silicon dioxide deposited on top of the bottom oxide 322.
The memory cell 300 is generally capable of storing two bits of data, a right bit in an area of the nitride layer 324 represented by the dashed circle 323 and a left bit in an area of the nitride layer 324 represented by the dashed circle 321. (MLC operation of the NROM, for storing a total of 4 bits of data is discussed hereinbelow.)
Each of the storage areas 321, 323 in the charge-trapping material 324 can exert a field effect on the channel region 320 between the source and the drain, in a manner similar to how a normal FET works, as described hereinabove (FIG. 2). some mechanisms for storing in the storage areas of the charge-trapping material, as well as removing charges from the storage areas of the charge-trapping material are described hereinbelow.
Generally, if a charge is stored in a given storage area of the charge-trapping material, this represents a binary "1", and if no charge is stored in a given storage area of the charge-trapping material, this represents a binary "0". (Again, these designations are arbitrary, and can be reversed to that the charged state represents binary "0" and the discharged state represents binary "1".) That represents the programming "half" of how an NROM memory cell operates. The other half is how to determine whether there is a charge stored in a given storage area of the charge-trapping material—in other words, to "read" the memory cell. Generally, this is done by applying appropriate voltages to the diffusion regions (functioning as source and drain) and gate terminals, and determining how conductive the channel is. Some modes of operation for an NROM memory cell are described hereinbelow.
Generally, one feature of NROM cells is that rather than performing "symmetrical" programming and reading, NROM cells are beneficially programmed and read "asymmetrically", which means that programming and reading occur in opposite directions. The arrows labeled in FIG. 3 are arranged to illustrate this point. Programming may be performed in what is termed the "forward" direction and reading may be performed in what is termed the "opposite" or "reverse" direction. Some programming and reading modes of operation for memory cells are described hereinbelow.
Memory Cell Modes of Operation and Injection Mechanisms
A memory cell's state may be defined and determined by what is called its threshold voltage (Vt) which determines a threshold level for the gate voltage required to establish the "channel" between the source and the drain—in other words, for the memory cell to begin to conduct current. A memory cell's threshold voltage level is directly related to the amount of charge (the number of electrons) stored in the charge storage region (floating gate, or ONO layer) of the cell—generally, more electrons stored means a higher threshold voltage Vt. Typically, for a given structure of a memory cell, the gate voltage that provides 1 pA (picoAmpere) of channel current is termed the threshold voltage (Vt).
The structure and general operation of two types of memory cells—floating gate and NROM—have been described hereinabove, with reference to FIG. 2 (floating gate) and FIG. 3 (NROM). Fundamentally, these two types of memory cells have in common with one another that they both operate very generally as a field effect transistor (FET)—namely, having two spaced-apart diffusion regions (functioning as source and drain) and a gate (for controlling the flow of electrons (current) through the channel region between the two diffusion areas, with the modification that they both have a charge storage structures under the gate.
The floating gate (FG) memory cell has a conductive layer between the gate and the channel region and, since the floating gate is a conductor, electrical charges stored in the floating gate are free to move around within the floating gate.
The NROM memory cell has a non-conductive layer (such as nitride) which can store charge in distinct areas and, since the non-conductive layer is not a conductor, the charges stored in the non-conductive layer are not free to move around, but rather tend to stay more-or less where they have been stored in a charge-storage region of the non-conductive layer, typically in a first region near one of the two diffusion regions, and in a second region adjacent the other of the two diffusion regions. These two diffusion regions are typically referred to as "left" and "right", and the corresponding two charge-storage regions in the non-conductive layer are typically similarly referred to as "left" and "right".
The concept of storing charges in the charge-storage structures (floating gate of a floating gate memory cell, or non-conductive layer of an NROM memory cell) has been discussed. The charges can also be removed from the charge-storage structure. Generally, the process of moving of charges into or out of the charge-storage structure is referred to as "injection", and there are a number of known injection mechanisms.
In a general sense, "electrons" are (or behave as) negative charges and "holes" are (or behave as) positive charges. As we have heard many times in many contexts, "opposites attract". For example, the north pole of a magnet attracts the south pole of another magnet, and is repelled by the north pole of another magnet. Generally, the same principle applies with electrical charges. An electron (negative charge) will be attracted by a positive electrical charge (or voltage) and will be repelled by a negative electrical charge (or voltage), and a hole (positive charge) will be attracted by a negative electrical charge (or voltage) and will be repelled by a positive electrical charge (or voltage).
The charge-storage structures of both the floating gate (FIG. 2) or NROM (FIG. 3) memory cells are separated from the channel region between the two diffusion regions by an insulating material, typically silicon dioxide (see tunnel oxide, FIG. 2; See lower oxide 322, FIG. 3). Therefore, in a general sense, the purpose of an injection mechanism is to move charges (electrons or holes) across the insulating material separating the channel region from the charge-storage structure of the memory cell.
The broad purpose of semiconductor memory is to store ("program") data—many binary "1"s and "0"s—and allow access to ("read") the stored data. And the broad purpose of a single memory cell is to store individual bits of the data. Single-level (SLC) floating gate memory cells can store one bit of data. Single-level (SLC) NROM memory cells can store two bits of data. Multi-level (MLC) floating gate memory cells can store two bits of data. Multi-level (MLC) NROM memory cells can store four bits of data. MLC operation of memory cells is discussed in greater detail hereinbelow.
Data is stored in and retrieved from memory cells in what is termed "modes of operation". Generally, there are four modes of operation: "erase", "program", "write" and "read". The first three modes (erase, program, write) relate to storing data. And, for purposes of this discussion, the write mode typically is simply a combination of erase and program. The read mode refers to accessing stored data.
The principle modes of operation discussed in this disclosure are program and erase. Both floating gate and NROM will be discussed.
Generally, to store a charge in the floating gate of a floating gate memory cell, the control gate's voltage may be raised with the source and drain grounded (or with the drain at a raised voltage), so that electrons tunnel through the tunnel oxide from the channel region to the floating gate, by a process known as CHE (channel hot electron) injection. To remove the charge (electrons) from the floating gate, the source's voltage may be raised with the gate grounded (or at a negative potential), and the electrons tunnel from the floating gate back to the substrate, by a process known as F-N (Fowler-Nordheim) tunneling (also abbreviated "FNT").
FIG. 2A illustrates a technique for programming a floating gate memory cell, using channel hot electron (CHE) injection to put charges (inject electrons) into the floating gate. The floating gate memory cell generally comprises a channel region between a source region and a drain region, and a floating gate disposed between the channel region and the control gate (compare FIG. 2). This figure illustrates various voltages which may be applied to the source (Vs), to the gate (Vg) and to the drain (Vd), from external sources and/or connections (not shown). Generally, there is no "connection" to the floating gate.
Generally, in order implement CHE injection of electrons into the floating gate, the source is grounded, the drain is set to zero or to a positive voltage (which will "attract" electrons from the source, laterally across the channel region), and the gate is also set to a positive voltage (which will "attract" electrons vertically through the tunnel oxide, into the floating gate). As electrons flow through the channel from source to drain, some of the electrons will make their way through the tunnel oxide and become stored on the floating gate. This injection of electrons into the floating gate increases the threshold voltage of the memory cell. The shift (increase) in threshold voltage can be on the order of 3 or more volts. The threshold voltage (Vt) of the memory cell can later be measured, or "read".
FIG. 2B illustrates a technique for erasing a floating gate memory cell, using a mechanism which is called "Fowler-Nordheim Tunneling", abbreviated as "F-N tunneling", or "FN tunneling", or simply "FNT".
Generally, whereas CHE injection was used (described hereinabove), in programming, to inject electrons into the floating gate, F-N tunneling (FNT) is used, in the erase operation, to remove electrons from the floating gate.
Generally, in order implement F-N tunneling of removing electrons from the floating gate, both the source and the drain are set to a positive voltage (to "attract" electrons through the tunnel oxide from the floating gate into the substrate), and the gate is set to a negative voltage (to "repel" electrons through the tunnel oxide from the floating gate into the substrate). This removal of electrons from the floating gate decreases the "threshold voltage" of the memory cell.
Generally, during programming, the threshold voltages of individual memory cells or (in the case of NROM) two charge-storage regions of a single memory cell) are individually manipulated to represent the data desired to be stored. In contrast thereto, generally, during erase, it is normally acceptable to simply decrease the threshold voltages of a great many memory cells, all at once, such as all of the memory cells in a sector or block of a memory array.
Typically, to inhibit erase of selected memory cells, an "inhibit" signal, such as a positive voltage (which will not "repel" the electrons) may be applied to the gates of the selected memory cells. In a common array architecture, the gates of several memory cells are typically all connected to a common word line (of many such word lines) in the array. Array architecture is discussed in greater detail hereinbelow.
Regarding "reading" the contents of a memory cell, no "injection mechanism" is used. The conventional technique of reading conductive floating gate memory cells is to apply appropriate "read voltages" to the gate and drain and to ground the source. This is similar to the method of programming with the difference being that lower level voltages are applied during reading than during programming.
Since the floating gate is conductive, the trapped charge is distributed evenly throughout the entire floating conductor. In a programmed device, the threshold is therefore high for the entire channel and the process of reading becomes symmetrical.
It makes no difference whether voltage is applied to the drain and the source is grounded or vice versa.
The following table presents exemplary conditions for programming, erasing and reading a floating gate memory cell.
TABLE 1Exemplary Floating Gate ConditionsVsVgVdVbtimeErase (FN)>=0−8-10v>=06-8 v100msProgram (CHE)gnd8-10v4-5 v??1μsRead0 v5v 1 v
FIGS. 3A and 3B illustrate a technique for programming an NROM memory cell, using channel hot electron (CHE) injection to inject electrons into the charge storage areas 321 and 323. As shown in FIG. 3A, the NROM memory cell comprises a channel region between two spaced-apart diffusion regions (left and right), and an ONO stack (322, 324, 326) between the channel region and the gate (328). (Compare FIG. 3.)
Generally, NROM memory cells may be programmed similarly to floating gate memory cells, using a channel hot electron (CHE) injection mechanism. Voltages are applied to the gate and drain creating vertical and lateral electrical fields which accelerate electrons from the source along the length of the channel. As the electrons move along the channel some of them gain sufficient energy to jump over the potential barrier of the bottom silicon dioxide layer 322 (of the ONO layer) and become trapped in the silicon nitride (charge trapping) layer 324 (of the ONO layer).
The NROM cell can store charges in two separate portions 321 and 323 of the charge-trapping layer 324. For purposes of this portion of the discussion, the left region 321 stores a left bit, and the right region 323 stores a right bit. Depending on which bit is desired to be programmed, the left and right diffusion regions 314 and 316 can act as source and drain, or as drain and source. The gate always functions as the gate.
FIG. 3A illustrates CHE programming of the right bit. In this example, electron trapping occurs in a region near the diffusion region 316 acting as a drain, as indicated by the dashed circle 323. Electrons are trapped in the portion 323 of nitride layer 324 near but above and self-aligned with the drain region 316 because the electric fields are the strongest there. Thus, the electrons have a maximum probability of being sufficiently energized to jump the potential barrier of the oxide layer 322 and become trapped in the nitride layer 324 near the drain 316.
FIG. 3B illustrates CHE programming of the left bit. For the left bit, the situation is reversed from programming of the right bit. In simple terms, the left diffusion area 314 functions as the drain and the right diffusion area 316 functions as the source, and electrons are sufficiently energized to jump the potential barrier of the oxide layer 322 and become trapped in the nitride layer 324 near the drain 314.
Generally, NROM memory cells may be erased using a technique called hot hole injection (HHI), or tunnel enhanced hot hole (TEHH) injection. For example, to erase an NROM memory cell, the source voltage can be set to a positive voltage such as +5 v, the gate voltage can be set to a negative voltage such as −7 v, and the drain voltage may be set to a positive voltage such as +2 volts (less than the source voltage) or may be left floating or disconnected.
Using HHI, holes (the "counterpart" of electrons) can be selectively inserted into the left portion 321 of the nitride layer 324 and into the right portion 323 of the nitride layer 324, in a controlled manner. Generally, holes which are injected cancel out electrons which are trapped (stored) in the left and right portions of nitride layer on a one-to-one basis (one hole "cancels out" one electron).
FIG. 3C illustrates erasing the right bit. In this example, hole injection occurs in a region near the diffusion region 316 acting as a drain, as indicated by the dashed circle 323. Holes are injected in the portion 323 of nitride layer 324 near but above and self-aligned with the drain region 316 because the electric fields are the strongest there. Thus, the holes have a maximum probability of being sufficiently energized to jump the potential barrier of the oxide layer 322 and become injected into the nitride layer 324 near the drain 316.
FIG. 3D illustrates HHI erasing of the left bit. For the left bit, the situation is reversed from erasing of the right bit. In simple terms, the left diffusion area 314 functions as the drain and the right diffusion area 316 functions as the source, and holes are sufficiently energized to jump the potential barrier of the oxide layer 322 and become injected into in the nitride layer 324 near the drain 314.
Reading an NROM memory cell may involve applying voltages to the terminals of the memory cell comparable to those used to read a floating gate memory cell, but reading may be performed in a direction opposite to that of programming. Generally, rather than performing "symmetrical" programming and reading (as is the case with the floating gate memory cell, described hereinabove), the NROM memory cell is usually programmed and read "asymmetrically", meaning that programming and reading occur in opposite directions. This is illustrated by the arrows in FIG. 3. Programming is performed in what is termed the forward direction and reading is performed in what is termed the opposite or reverse direction. For example, generally, to program the right storage area 323, electrons flow from left (source) to right (drain). To read the right storage area 323 (in other words, to read the right "bit"), voltages are applied to cause electrons to flow from right to left, in the opposite or reverse direction. For example, generally, to program the left storage area 321, electrons flow from right (source) to left (drain). To read the left storage area 321 (in other words, to read the left "bit"), voltages are applied to cause electrons to flow from left to right, in the opposite or reverse direction. See, for example, commonly-owned U.S. Pat. No. 6,768,165.
The following table presents exemplary conditions for programming, erasing and reading an NROM memory cell.
TABLE 2Exemplary NROM Gate ConditionsVsVgVdVbtimeProgram (CHE)+5 v8-10v0 v1 μsErase (HHI)  5 v−7v2 v??Read05v1.3 v  "Vs" refers to the left diffusion area, and "Vd" refers to the right diffusion area, for the operations of programming, erasing and reading the right side bit of an NROM memory cell.
The operations of program and erase are typically performed using pulses, each pulse partially moving (nudging) the memory cell towards the desired Vt, followed by verify (a quick read, to see if the desired Vt has been reached), until the desired Vt has been attained. Typically, conditions are established so that only a few (for example, 3-5) pulses are required to program or erase each cell.
Exemplary operating modes for memory cells, using the mechanism of CHE injection for programming a memory cell, and the mechanisms of FNT and HHI for erasing a memory cell have been described, hereinabove. Other and additional mechanisms are known for performing the modes of operation.
Other Erase and Program Operations for NROM
The article "A Single-Sided PHINES SONOS Memory Featuring High-Speed and Low-Power Applications", IEEE Electron Device Letters, Vol. 27, No. 2, February 2006, incorporated in its entirety by reference herein, discloses erase and program operations for a memory cell having ONO thicknesses of 5 nm (bottom oxide), 7 nm (nitride) and 9 nm (top oxide), and being operated as a one-bit/cell device used in a virtual ground array. As noted in the article, CHE programming has low programming efficiency and causes high power consumption.
First the memory cell is erased to a high Vt level by a negative FN electron tunneling operation wherein, a high negative voltage is applied to the gate of the memory cell in a single terminal (1-terminal) operation (the source and drain voltages are left at 0 volts), and electrons tunnel into the nitride charge storage area. See FIG. 3E.
The erase conditions set forth in the article are Vs=0 v; Vg=−20 v; Vd=0 v; Vb=0 v. See Table 3, below. An upward Vt shift of approximately 3 volts (from 0 to 3 volts) can be achieved in approximately 1 millisecond (1 ms).
The negative FNT erase operation being a single terminal operation, the entire charge storage area of the memory cell is populated with electrons. This is shown in FIG. 3E by the nitride layer being filled with electrons (represented as dashes in circles). And, when multiple memory cells are tied to a common word line, all of the memory cells tied to that word line will be erased. Erase is generally a "bulk", indiscriminate operation, intended to bring a plurality of memory cells to a predefined state (either logic "1" or logic "0"), at once.
Then, for programming the cell, band-to-band hot-holes (HHs) are injected to both the left side and the right side to decrease the cell Vt, and a programming speed as fast as 20 μs can be achieved. See FIGS. 3F, 3G.
Hot Hole Injection (HHI) is a two-terminal operation, so only one side can be done at a time. In FIG. 3F, holes (represented as plus signs in circles) fill the left side of the nitride layer, "canceling out" a like number of electrons. In FIG. 3G, holes (represented as plus signs in circles) fill the right side of the nitride layer, "canceling out" a like number of electrons. (In the diagrams of FIGS. 3F and 3G, the electrons are illustrated as being in the top oxide layer not because they are there—they aren't—but rather because they simply do not fit in the illustration within the nitride layer—where they are. The electrons are in the nitride layer, as shown in FIG. 3E.)
The program conditions set forth in the article are Vs=0 v; Vg=−10 v; Vd=0 v; Vb=0 v. See Table 3, below. A downward Vt shift of approximately 3 volts (from 0 to −3 volts) can be achieved in approximately 20 microseconds (20 μs).
Since the device channel stays off during both programming and erase operation, the power consumption is very low. The article claims to achieve a high programming throughput of 10 MB/s with low power (program current<10 nA/cell).
However, it should be realized that the memory cell is being used as a one-bit/cell device, rather than as a two-bits/cell device, as in NROM. (The article appears to claim that two-bits/cell can be achieved by MLC operation).
TABLE 3Exemplary NROM Gate ConditionsVsVgVdVbtimeErase (FNT)0 v−20 v0 v0 v1msProgram (HHI)5 v−10 v5 v0 v20μs
The erase and program operations may typically be performed using a few cycles of pulses followed by verify (read).
There are, of course, many nuances to each of the operations of memory cells discussed hereinabove. For example, repeated erasing of a memory cell can result in lowering the threshold voltage beyond zero, becoming negative, a condition known as "over-erase". And, particularly with regard to programming NROM memory cells in an array of many NROM cells, programming one bit of a given cell may disturb the state of a neighboring cell. These issues, as they may become relevant and pertinent, are discussed hereinbelow.
For example, U.S. Patent Publication No. US2005/0078527, incorporated in its entirety by reference herein, discloses a method of over-erase protection in a NROM device by performing a F-N tunneling program to provide additional electrons to the nitride charge-trapping layer (of a NROM device having an ONO layer) to increase the threshold voltage before a CHE program cycle or before a HHI erase cycle. The FNT step may be applied to individual NROM devices, or to a plurality of NROM devices.
Programming is typically performed in increments, with pulses of voltage—after each pulse, a verify operation occurs in which the threshold voltage level of the cell is measured (read). The general idea is to "nudge" the threshold voltage to the desired level, rather than over-shooting (over programming) or under-shooting (under programming) the desired level. With appropriate control mechanisms, only a few pulses (nudges) are required. A similar concept of cycles of pulse followed by verify until a desired Vt has been attained may sometimes be used during the erase operation, to avoid under-erase or over-erase. See, for example, commonly-owned U.S. Pat. Nos. 6,292,394; 6,396,741; 6,490,204; 6,552,387; 6,636,440; and 6,643,181.
Multi-Level Cell (MLC) Operation of Memory Cells
Mention has been made, hereinabove, of single level cell (SLC) and multi-level cell (MLC) operation, and it shall be described only briefly in this disclosure.
Theoretically, in order to determine the programmed state of a memory cell, only one voltage threshold is needed—either the threshold voltage (Vt) of the cell is below the threshold, or over the threshold (Vth). However, this simplistic approach can lead to ambiguities and false readings. This is in part due to the fact that the charges (such as electrons) cannot be stored (in the floating gate, or in the NROM storage region) with absolute precision, and is in part due to the fact that sometimes electrons disappear from the storage region.
Therefore, in practice, to store one bit of data, two voltage levels are needed. If the sensed threshold voltage is below the lower of the two voltage levels, that is classified as a "0", and if the sensed threshold voltage is above the higher of the two voltage levels, that is classified as a "1".
Memory cell technology has been developed wherein memory cells can hold two or more bits of data, instead of just one each, in the storage region. The trick is to take advantage of the analog nature of the charge stored in the memory cell and allow it to charge to several different voltage levels. Each voltage range to which the floating gate can charge can then be assigned its own digital code. This is generally referred to as "Multi-Level Cell (MLC)" technology.
Injection Mechanisms, Generally
A number of "injection mechanisms" have been described hereinabove, in the context of modes of operating memory cells, such as CHE, FNT, HHI.
Generally, an injection mechanism includes any mechanism that causes electrons to be inserted into the storage area (floating gate) of a floating gate memory cell, or into the left or right storage area (in the ONO layer) of an NROM memory cell, such as CHE and FNT.
Generally, the more electrons you can insert into the storage area, the higher the threshold voltage of the memory cell will be. For a single level cell (SLC), a threshold voltage Vt above a predefined level Vth may be designated to represent either a logic "1" or a logic "0", and a threshold voltage Vt below the predefined level Vth may be designated to represent either a logic "0" or a logic "1".
Generally, an injection mechanism also includes any mechanism that causes electrons to be removed (extracted) from the storage area (floating gate or ONO region) of a memory cell. Generally, the threshold voltage of the memory cell can be lowered by removing previously-inserted electrons from the storage area.
Another way to lower the threshold voltage of the memory cell is to "cancel out" the electrical charge effect of previously-inserted electrons in the storage area, and this may be accomplished by inserting holes into the storage area, such as with HHI. Generally, one hole will "cancel out" one electron.
These injection mechanisms are generally well known. Although the mechanisms may largely be dominated by the various voltages applied to the source (Vs), gate (Vg) and drain (Vd) of the memory cell, as well as to the substrate (Vb), factors such as materials used in various elements of the memory cell, as well as geometry and dimensions of the elements of the memory cell can also significantly affect the injection mechanism.
Memory Array Architecture, Generally
Memory arrays are well known, and comprise a plurality (many, including many millions) of memory cells organized (including physically arranged) in rows (usually represented in drawings as going across the page, horizontally, from left-to-right) and columns (usually represented in drawings as going up and down the page, from top-to-bottom).
As discussed hereinabove, each memory cell comprises a first diffusion (functioning as source or drain), a second diffusion (functioning as drain or source) and a gate, each of which has to receive voltage in order for the cell to be operated, as discussed hereinabove. Generally, the first diffusions (usually designated "source") of a plurality of memory cells are connected to a first bit line which may be designated "BL(n)", and second diffusions (usually designated "drain") of the plurality of memory cells are connected to a second bit line which may be designated "BL(n+1)". Typically, the gates of a plurality of memory cells are connected to common word lines (WL).
FIG. 4 illustrates an array of NROM memory cells (labeled "a" through "i") connected to a number of word lines (WL) and bit lines (BL). For example, the memory cell "e" has its gate connected to WL(n), its source (left hand diffusion) is connected to BL(n), and its drain (right hand diffusion) is connected to BL(n+1). The nine memory cells illustrated in FIG. 4 are exemplary of many millions of memory cells that may be resident on a single chip.
Notice, for example that the gates of the memory cells "e" and "f" (to the right of "e") are both connected to the same word line WL(n). (The gate of the memory cell "d" to the left of "e" is also connected to the same word line WL(n).) Notice also that the right hand terminal (diffusion) of memory cell "e" is connected to the same bit line BL(n+1) as the left-hand terminal (diffusion) of the neighboring memory cell "f". In this example, the memory cells "e" and "f" have two of their three terminals connected together.
This means that if you want to perform an operation (such as program, erase or read) on one cell something, there could be an effect on a neighboring cell, since two of the three terminals of adjacent memory cells are connected together (gate connected to gate, and one of left/right diffusions connected to one of right/left diffusions for the neighboring cell.)
Generally, as discussed in greater detail hereinbelow, it may be relevant whether a given operation (such as program, erase or read) is performed as a "I-terminal" operation (such as FNT erase to high Vt, discussed hereinabove), as a "2-terminal" operation (for example, applying a non-zero voltage to the gate and to one of the source or drain diffusions) or as a "3-terminal" operation (for example, applying a non-zero voltage to the gate and to both of the source or drain diffusions).
Generally, when programming or erasing a cell, one or more of the neighboring cells may be affected by the programming/erasing operation, causing thereto a possible change in their threshold voltage. This unwanted change in threshold voltage of unselected cells is known as a "disturb". A similar effect (disturb) may occurs during a read operation. However, due to the relative weakness of the applied voltage levels, the effect during read is significantly smaller.
The situation of neighboring memory cells sharing the same connection—the gates of neighboring memory cells being connected to the same word line, the source (for example, right hand diffusion) of one cell being connected to the drain (for example left hand diffusion) of the neighboring cell—is even more dramatically evident in what is called "virtual ground architecture" wherein two neighboring cells actually share the same diffusion. In virtual ground array architectures, the drain of one memory cell may actually be the same diffusion which is acting as the source for its neighboring cell. Examples of virtual ground array architecture may be found in U.S. Pat. Nos. 5,650,959; 6,130,452; and 6,175,519, incorporated in their entirety by reference herein.
A memory array may also include isolation zones (not shown). Isolation zones segregate one group of memory cells from a neighboring group of memory cells, for example isolation zones can divide the array into slices of just one column or a plurality of columns. Examples of arrays having isolation zones may be found in commonly-owned U.S. Pat. No. 7,043,672, incorporated in its entirety by reference herein, and in coinmonly-owned U.S. Pat. No. 6,975,536.
A more complete description of NROM and similar ONO cells and devices, as well as processes for their development may be found at "Non Volatile Memory Technology", 2005 published by Saifun Semiconductor and materials presented at and through http://siliconnexus.com, both incorporated by reference herein in their entirety.

Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection


The present invention relates to a method for processing the noni plant into powder. The method for processing the noni plant into powder, includes the steps of picking the noni fruit from the tree, placing picked noni fruit in a room, washing and cleaning the noni plant, mashing the noni fruit, placing the pulp onto liner, rotating trays for five hours, rotating trays for another five hours, rotating trays for another 14 hours, and crushing and grinding dried wafers.

1. Field of the Invention
The present invention relates to the Noni plant (Morinda Citrifolia).
More particularly, the present invention relates to the Noni plant (Morinda Citrifolia) as a pharmaceutical product.
2. Description of the Prior Art
Numerous innovations for plant usage have been provided in the prior art that are adapted to be used. Even though these innovations may be suitable for the specific individual purposes to which they address, they would not be suitable for the purposes of the present invention.
For example, U.S. Pat. No. 4,666,606 to Heinicke teaches a method for eliminating grease, sewage odor and hydrogen sulfide from restaurant grease traps and municipal sewage systems using xeronine. Xeronine works by stimulating the metabolism of the resident anaerobic and aerobic bacteria.
U.S. Pat. No. 4,409,144 to Heinicke teaches that many commercial enzyme preparations which are used in pharmacology and industry and which are labeled and sold as proteases, pepidases, amylases or lysozymes actually owe their efficacy to chance contamination with the precursor system which produces Xeronine. Since the amount of the Xeronine precursor system varies between different batches of product may by the same manufacturer, the effectiveness of such products is unreliable. It is now proposed that either pure xeronine or a reliably standardized system or "kit" which releases xeronine be produced and used in place of these improperly described products.

Noni (Morinda Citrifolia) as a pharmaceutical product


Mine neutralization provides for radio control of a small boat having associated therewith: a projection mounted onto the boat and pointing forward; a primary magnet; a housing holding the primary magnet and joined at the front end of the projection; a fluid-dynamically shaped explosive device detachably attached underneath the boat; at least one secondary magnet affixed to the explosive device; and, a rope or cable tautly connected at its upper end to the primary magnet and at its lower end to the explosive device. The boat journeys near a floating mine to bring about magnetic interaction between the primary magnet and the mine. The primary magnet magnetically attaches to the mine, and a pulling force is exerted on the explosive device. The explosive device detaches from the boat, moves toward the mine, and magnetically attaches (via at least one secondary magnet) to the mine.

The present invention relates to mines, more particularly to mine neutralization involving delivery of a mine-neutralizing payload, such as an explosive, to a location in the vicinity of a mine.
Mines are explosive devices that pose great threats to troops and ships. Most mines are "independent" in that, once placed, they do not require human maintenance or operation. Generally, there are two categories of mines, based on their situation, viz., "land mines" and "sea mines" (also known as "naval mines"). "Minefields" are areas where mines have been placed. Some mines are difficult to detect (e.g., concealed underground or underwater). A typical sea mine includes an explosive charge that is set to fire in response to the presence of a marine vehicle (e.g., a ship or submersible) in contact therewith or in proximity thereto. A sea mine may be designed to be triggered by direct contact and/or by indirect influence. "Floating" mines are buoyant sea mines that are partially visible above water.
Mine countermeasures (MCM) frequently involve detonation of a mine through the influence of an explosion or an artificially generated ship-like signature. For instance, a conventional strategy for sea mine neutralization provides for diver delivery of a high explosive to the mine; this is an extremely hazardous task. A better approach to mine neutralization is one that does not put people at significant risk.

Remote control mine neutralization delivery system

The United States of America as Represented by the Secretary of the Navy


An assembling device (a production system) includes robots that produce a piping component from a plurality of types of parts, and a display that accepts an input of lot information of at least one of the plurality of parts used in producing operations by the first to third robots and that outputs unsuitable condition information when an unsuitable condition in any of the parts is detected, the unsuitable condition information identifying a lot of the any of the parts in which the unsuitable condition is detected.

1. Field of the Present Invention
The embodiments disclosed herein relates to a production system and an article producing method.
2. Description of the Related Art
Hitherto, a production system (parts assembling method) including a double arm robot (producing device) that produces a predetermined finished product from a plurality of parts has been available (refer to, for example, Japanese Unexamined Patent Application Publication No. 2006-35346 (Patent Document 1)).
Patent Document 1 discloses a parts assembling method (production system) including a double arm robot that holds and assembles parts. In the parts assembling method, the parts that are supplied by a part supplying device are taken out by the double arm robot, and the taken out parts (such as a valve) are inserted into a valve body having a valve hole.
However, in the parts assembling method (production system) in the aforementioned Patent Document 1, even if an unsuitable condition (such as a scratch) exists in a part that is supplied by the part supplying device, the unsuitable part may be assembled by the double arm robot. In general, it is desirable that parts included in a lot that is the same as that of the unsuitable part not be used in the assembly operation. However, in the parts assembling method in the aforementioned Patent Document 1, even parts included in a lot that is the same as that of the unsuitable part are assembled by the double arm robot. In particular, in fields in which, for example, medical parts, chemical parts, or electronic parts are to be precisely supplied, control is strictly performed so that such a problem does not occur.

Production system and article producing method


A method of decoding a primary codeword and a set of secondary codewords stored in a non-volatile memory (NVM), which includes reading, from the NVM, the primary codeword and all the secondary codewords and storing them in a second memory. The primary codeword is then read from the second memory and decoded, utilizing a soft-decision decoder, based on a log-likelihood ratio (LLR) vector. When the decoding of the primary codeword is unsuccessful: each secondary codeword of the set of secondary codewords is read from the second memory and decoded, utilizing a hard-decision decoder, to identify and correct errored data bits in the each secondary codeword and to determine a location of each errored data bit in the primary codeword. An adjusted LLR vector is generated by adjusting the LLR for each primary codeword data bit based on the determined locations of the errored data bits in the primary codeword.

Non-Volatile Memory (NVM), such as NAND flash memory, is a very popular storage medium because it allows data to be stored for some length of time. The ability to store data has enabled the information age and prompt, reliable, access to this data is one of the reasons why solid-state drives (SSDs) have become so popular in recent years. Also, Solid-state drives (SSDs) that are built using NAND flash memory are becoming more and more common as their prices decrease.
NAND flash memory, however, is not particularity reliable as a storage medium because NAND flash memory often suffers from errors. Historically, NAND flash memory suffers from two classes of errors: (1) small scale errors; and (2) large scale errors. Small scale errors add Raw Bit Error Rate (RBER) to the data stored on a storage medium. Large Scale errors comprise gross defects causing large sections of the data to be in error or erased.
For NAND flash memory, a well-known large-scale (or gross) defect is a "die-kill". A "die-kill" occurs when an entire die of the NAND flash memory becomes inoperable. All data on that die, which can be as much as 128 Gb, may be lost. A common cause of a die-kill is a charge pump failure in the circuitry of the NAND flash memory. The probability of "die kill" error is estimated to be a few parts per million (PPM).
Because NVMs are never error free, to ensure data that is stored on the NVM is reliably protected, a NVM controller must implement a robust error correcting code (EEC) method. As errors can be small scale and/or large scale, it is advantageous to utilize a combination of ECC methods to protect against both small scale and large scale errors.
Improvements ECCs for NVMs are therefore desirable.

Method and system for decoding encoded data stored in a non-volatile memory


The present invention is directed to golf equipment packages using a coating that gives a color traveling effect. The color traveling coating can be applied to golf equipments such as golf balls, golf gloves and golf clubs, and to golf equipment display. In addition, because the coating reflects ultraviolet light, it can be coated on golf balls and golf clubs to prevent discoloration under ultraviolet light.

Unique, attractive golf balls, golf equipment, golf packaging and counter displays attract potential buyers. Attractive golf balls and equipment, and unique-looking packaging for golf balls and equipment convey high quality and make the merchandise more attractive.
U.S. Pat. No. 4,991,851 to Melesio discusses using a solid layer of light-reflective glass beads to coat a golf ball so that it can be used at night. When illuminated by a light source, it can be readily located and can be used at night.
U.S. Pat. No. 5,875,891 to Snell relates to packaging for golf balls that prevents moisture absorption during storage. This reference discloses a package that includes a sealing member, which is a moisture barrier forming an airtight seal around the golf balls.
U.S. Pat. No.6,044,970 to Shinoda discloses a golf ball package having a holographic display. The hologram sheet comprises a plastic film covering a reflective surface that consists of evaporated metal film with fine irregularities. Depending on the viewing angle, the hologram sheet becomes iridescently colored. In addition, there are also formed, within the irregularly reflective area, both a first regularly reflecting area which reflects incident light from a predetermined angle for displaying an external view of the golf ball, and a second regularly reflecting area which regularly reflects incident light from a different angle for displaying the internal structure of the golf ball. However, this reference requires the use of metal as reflective surfaces to display holographic images.
There remains a need for other methods to make golf balls, golf equipment, and golf packaging to look unique, more attractive and desirable.

Golf products and packaging for golf products with color traveling coating


In a computer system having a plurality of software components, a security system for controlling interactions between the software components, the security system including at least one constraint associated with the interaction; and at least one attribute associated with the software components. The attributes and interaction parameters are bound to the constraint. The security system reaches a verdict permitting or forbidding the interaction, by resolving the constraint, based on value of the attribute and values of the parameters. The security system uses constraints and attributes specified during different life stages of each software component, where constraints are incrementally added during each subsequent life stage.

1. Field of the Invention
The present invention relates to computer security systems for ensuring secure interaction between various software components.
2. Description of the Related Art
EP1631032 describes a method and system for control of computer resources based on various parameters and access policies. This reference describes how parameters for accessing a certain resource (such as a software component) are formed.
U.S. Pat. No. 6,978,381 describes a system and method for processing of secure data. In this reference, a list that includes various access levels, profile lists and user lists is formed. The access to the data is then implemented based on the lists.
U.S. Patent Publication No. 2005/0251508 describes a system and method for file access that uses a list of file parameters. The access to the files is implemented is based on the parameters list.
U.S. Patent Publication No. 2003/0055991 describes a system and method for accessing an object. This reference describes how the data regarding the object, the access commands, the data regarding the actions, etc. are formed. The mechanism for determining whether access to the object should be permitted utilizes a first set of commands for access control, where the object has specified parameters that correspond to the object context. A second set of commands controls access such that the parameters of the access are hierarchically broader than the parameters of the context.
U.S. Patent Publication No. 2005/0262362 describes access control to an object based on parameters relating to its name, parameters relating to resources, and parameters relating to the object itself.
One of the difficulties in a modern approach of software development and in ensuring security for interaction between software components is the fact that the component itself has to be designed with security in mind. In other words, security aspects must be built into the component itself, and, generally, cannot easily be added or changed later. This adds a considerable burden on the developer, and also increases the likelihood of bugs and errors in the software, which virus writers and hackers can exploit down the line. On the other hand security requirements for distribution, deployment, selling, licensing, configuration, administration, using, etc. are highly dependent on a particular use case. These types of different requirements are very difficult to implement and even to enumerate in advance, which makes it virtually impossible for software component users to enforce their own security strategy, if it does not correspondent to the security model implemented in the software component.
An example of such a built-in security system can be found, for example, in modern file systems, such as the NTFS file system, the mail services, phone services, such as those available in Microsoft Windows™, and so forth. For example, in the case of the NTFS file system, the Microsoft Windows™ operating system checks whether whichever software components is trying to access a file actually has permission to access that file. In this case, the security is built into the file system and the APIs that support it.
On the other hand, earlier systems, such as FAT32 and FAT16, do not have a built in security, and adding a level of security to these file systems is virtually impossible. Even those conventional systems that have security built into them do not have the option of changing the parameters of the security system based on the life stage of the particular software component.
Accordingly, there is a need in the art for a system and method that addresses secure interaction between software entities, in a manner that removes much of the burden relating to the security of the interaction from the developer of the software component itself.

This patent is subject to a terminal disclaimer.

Constraint-based and attribute-based security system for controlling software component interaction


A hose with a protector comprises: a tubular-shaped hose body 10; a tubular-shaped protector 20 which is coaxially provided in the state in which it covers the outer peripheral surface of the hose body 10; a tubular-shaped engager 30 which bonds the hose body 10 and the protector 20 integrally at both edge portions thereof and which forms an inserting opening into which a nipple is inserted and bonded. By producing the hose body out of resin and producing the protector out of rubber, the present hose with a protector can obtain heat resistance and anti flame resistance which are suitable for a filler hose and which are necessary at the time of vehicle fire and also the present hose with a protector is good in sealing property with the mating pipe and good in connecting function.

1. Field of the Invention
The present invention relates to a hose with a protector having high resistance to harm such as heat and flame from the outer peripheral surface side. The hose with a protector according to the present invention is optimum for transferring gasoline, lamp oil and chemical drug.
2. Description of the Related Art
As the conventional hose with a protector, the hose comprising a tubular-shaped protector which coaxially covers the outer periphery side of a hose body transferring liquid has been known. This type of conventional hose with a protector is described in Japanese Unexamined Utility Model Publication Nos. 174192/1987, 18488/1981, 188087/1986 and 46194/1990 (Kokai). In these publications, various inventions have been made so as to form the space between the hose body and the tubular-shaped protector which covers the hose body. Furthermore, concerning the joint of a hose with a protector, the invention utilizing a splicing fitting is described in Japanese Utility Model Publication No. 34548/1991 (Kokoku).


A transparent crystalline electrically-conductive thin film of the present invention comprises an indium tin oxide as a main component, wherein the indium tin oxide contains 9% by weight or less of tin oxide based on the total amount of indium oxide and tin oxide, wherein the transparent crystalline electrically-conductive thin film contains 0.45 atomic % or less of nitrogen. The transparent crystalline electrically-conductive thin film of the present invention has a high resistance value and good reliability in a high-temperature, high-humidity environment.

Indium tin oxide (ITO) thin films are conventionally used as transparent electrically-conductive thin films, because of their excellent transparency. Among transparent electrically-conductive thin films for the above applications, for example, those for use in touch panels and the like are desired to have high resistance values, in view of position detection accuracy or power consumption. Transparent electrically-conductive thin films for the above applications are also desired to have satisfactory reliability in high-temperature, high-humidity environments (the smaller the rate of resistance value change, the higher the reliability). After formed, transparent electrically-conductive thin films may also be crystallized so as to have improved reliability.
However, conventional transparent electrically-conductive thin films using indium tin oxide thin films have low resistance values and insufficient reliability. The reliability can be improved by increasing a thickness of the transparent electrically-conductive thin film. However, such an increase in thickness can result in a reduction in transparency or resistance value and thus is not preferred. The reliability of the transparent electrically-conductive thin film can also be improved by increasing a content of tin oxide in the indium tin oxide thin film. However, too high tin oxide content can make the time for crystallization very long and thus is not preferred.
To solve the problems, it is proposed that an indium tin oxide thin film is doped with nitrogen (see Patent literature 1). Patent literature 1 discloses that in the nitrogen-containing transparent electrically-conductive thin film, a nitrogen content of 0.25% by weight or more based on the amount of indium tin oxide can be effective in improving the resistance value or reliability of the transparent electrically-conductive thin film. However, the transparent electrically-conductive thin film disclosed in Patent Literature 1 is amorphous, and crystallization thereof for a further improvement in the reliability requires a very long time.
Patent literature 1: Japanese Patent Application Laid-Open No. 04-308612

Transparent crystalline electrically-conductive thin film, method of production thereof, transparent electrically-conductive film, and touch panel


A handwriting instrument with a stamp carrier (40) with stamp pad (41) introduced from the side into the stock (10). The stamp carrier is releasably connected to a lid (20). The lid (20) is a segment of the stock (10). For this writing instrument a flexible standard refill (50) is provided, with which the aide of a guide bar (53) and further stock elements is bent and held against the inner wall of the stock (10) in such a manner, that it's central area is eccentrically displaced for providing greater space for the stamp carrier (40).

1. Field of the Invention
The invention concerns a handwriting instrument combined with a stamp, in which either a stamp with stamp pad or a self-impregnated stamp is integrated in the stock or, as the case may be, casing or housing, of the handwriting instrument and can be pivoted or extracted therefrom for carrying out the stamping process.
2. Related Art of the Invention
This type of handwriting instrument, generally referred to as a so-called "stamp pen", is well known for example from DE GM 77 15 261, DE GM 81 30 431, DE GM 84 18 819.
Since the stamp pad and/or the stamp requires space and the dimensions of the handwriting instrument naturally are limited, in the past only short writing cartridges or ink reservoir tubes, hereafter referred to simply as refills, with a comparatively small ink or paste reservoir, were employed.
EP 0 433 572 B1 discloses a handwriting instrument with an incorporated stamp, in which a high capacity writing cartridge, that is, a cartridge with large storage volume, is provided. In this writing instrument the stamp carrier, which can be folded out for stamping, is provided with an inked stamp on the rear end of the stock, whereby a relatively long writing instrument results.
The present inventive device is concerned with a task of providing an ergonomic writing instrument combined with a stamp, in which a conventional refill can be employed and of which the stock length does not substantially exceed the refill length.
For solving this task the invention begins with the known writing instrument, in which the stamp pad is provided with a stamp lying there—against in the longitudinal direction of the stock and a handle is used to remove the stamp carrier with stamp from a laterally or sideways open recess of the stock.
Such a handwriting instrument is basically known from DE 29 38 931 A1.
However in this writing instrument only a disadvantageously relatively short refill, here a writing tip with ink cartridge, can be employed, so that it is not suited for use with relatively longer refills, in particular ball point type refills.

Rigoni Vermoegensverwaltung GmbH & Co. KG