In a DRAM of separated I/O type, column selecting lines for reading data and column selecting lines for writing data are provided independently from each other. An addition circuit is provided corresponding to each memory cell array block for precharging, when that memory cell array is not selected, a read line pair corresponding that memory cell array block to the same potential Vb1 as that of the bit lines equalized by an equalizer circuit. Both in data reading and writing operations, current does not flow between any equalizer circuit and the write data line pair provided corresponding to each unselected memory cell array block in spite of the fact that a transistor for write selection is not provided in each bit line pair.

1. Field of the Invention
The invention relates, in general, to a semiconductor memory device and an operation method of the same, and particularly to a semiconductor memory device having data lines which are provided independently from each other for reading and writing data, respectively, and an operation method of the same.
2. Description of the Prior Art
DRAMs (Dynamic Random Access Memories) have such features that memory capacities can be easily increased, as compared with SRAMs (Static Random Access Memories), but they require a relatively long time for reading and writing data.
Reduction of the access time of DRAMs has been attempted from various aspects. In one aspect, it relies on improvement of components and elements of the DRAM such as advance of performance of transistors in the DRAM and reduction of a signal delay time of interconnections in the DRAM, which are achieved by the advance of the process technology of the semiconductor integrated circuit device. In another aspect, it relies on improvement of circuit constructions of the DRAM achieved by the design technology of the semiconductor integrated circuit device.
The reduction of the access time of the DRAM has been mainly realized from the former aspect. In recent years, however, remarkable reduction of the access time of the DRAM has been attempted from the latter aspect.
The latter attempt is based on a following view. A major cause of preventing the reduction of the access time in the conventional DRAM is that "in a data reading operation, it is impossible to operate a sense amplifier immediately after activation of a word line connected to memory cells from which the data is to be read". This attempt will be described below in detail with reference to FIGS. 7-11.
FIG. 7 is a circuit diagram showing a construction of a major portion of the conventional DRAM to which the above attempt is not applied.
With reference to FIG. 7, a memory cell array block MA includes memory cells MC which are disposed in a row direction and a column direction to form a matrix, word lines WL which are provided correspondingly to rows of the memory cells, respectively, and bit line pairs BL, /BL which are provided correspondingly to columns of the memory cells, respectively.
Each memory cell MC is formed of an N-channel MOS transistor 100 having its gate connected to corresponding word line WL, and a capacitor 200. Transistor 100 and capacitor 200 are mutually connected in series between one of the two bit lines BL and /BL forming the corresponding bit line pair and a cell plate supplying a low potential Vsg.
In the data writing operation and data reading operation, a potential (nearly equal to power supply potential Vcc) at a high level is supplied to one of word lines WL. In all memory cells MC connected to this one word line WL, transistors 100 are turned on, and thus capacitors 200 are electrically connected to corresponding bit lines BL or /BL, respectively.
A sense amplifier SA and a bit line equalizer circuit EQ are connected between two bit lines BL and /BL forming each bit line pair.
Each sense amplifier SA includes two P-channel MOS transistors 300 and 310 connected between two signal lines 360 and 370, and two N-channel MOS transistors 320 and 330 connected between two signal lines 360 and 370. Between signal lines 360 and 370, transistors 300 and 320 are connected in series and also transistors 310 and 330 are connected in series. A connecting point of transistors 300 and 320 is connected to one (BL) of the two bit lines forming the corresponding bit line pair and is also connected to gates of transistors 310 and 330. Similarly, a connecting point of transistors 310 and 330 is connected to the other bit line /BL and gates of transistors 300 and 320.
Accordingly, each sense amplifier SA is activated while signal lines 360 and 370 are receiving supply potential Vcc and ground potential Vss corresponding to the low level, respectively. The activated sense amplifier SA operates as a differential amplifier, which amplifies a potential difference between corresponding two bit lines BL and /BL, and also operates as a temporary memory circuit, which latches the potentials of corresponding two bit lines BL and /BL at the connecting point of transistors 300 and 320 and the connecting point of transistors 310 and 330, respectively.
Each bit line equalizer circuit EQ includes N-channel MOS transistors 400 and 410 which are connected in series between two bit lines BL and /BL forming the corresponding bit line pair. An equalization control signal .phi.EQ is commonly applied to gates of transistors 400 and 410 in all equalizer circuits EQ. In each equalizer circuit EQ, an intermediate potential Vb1 (=Vcc/2) between supply potential Vcc and ground potential Vss is applied to the connecting point of transistors 400 and 410.
In the data writing and reading operations, equalization signal .phi.EQ is at the low level. Thereby, transistors 400 and 410 are turned off in each equalizer circuit EQ, so that intermediate potential Vb1 is not applied to any bit pair BL and /BL. When neither data reading operation nor data writing operation is to be carried out, equalization signal .phi.EQ is at the high level. Thereby, transistors 400 and 410 are turned on in each equalizer circuit EQ, so that each bit lines BL and bit line /BL paired therewith are set equally at the intermediate potential Vb1.
Sense amplifier activation signals .phi.pSA and .phi.nSA are applied to signal lines 360 and 370, respectively. By setting sense amplifier activation signals .phi.pSA and .phi.nSA to have supply potential Vcc and ground potential Vss, respectively, all sense amplifiers SA are activated.
Each bit line BL and bit line /BL paired therewith are connected through N-channel MOS transistors 500 and 510 to data lines /IO and IO, respectively. Transistor 500 connected to bit line BL and transistor 510 connected to bit line /BL paired with bit line BL have gates connected to a common column selecting line CSL. Thus, one column selecting line CSL is provided correspondingly to each bit line pair.
In the data writing and reading operations, the potential at the high level is applied to only one of the column selecting lines CSL. Thereby, both transistors 500 and 510 connected to this one column selecting line CSL are turned on, so that only one bit line pair BL and /BL corresponding to this one column selecting line CSL is electrically connected to data line pair IO and /IO.
Now, a general circuit operation for writing the data will be described below.
In the data writing operation, mutually complementary potentials are externally applied, as write data, to data line pair IO and /IO.
The potentials of data lines IO and /IO are transmitted to transistors 500 and 510 through bit lines corresponding to the one column selecting line to which the potential at the high level is applied (hereinafter referred to as selected bit lines).
The potentials of selected bit lines BL and /BL are latched at nodes N1 and N2 in corresponding sense amplifier SA, respectively.
In memory cell array block MA, if memory cell MC connected to one word line to which the potential at the high level is applied (hereinafter referred to as selected word line) is connected to bit line BL, charging or discharging, which depends on the potential latched in node N1, is caused in capacitor 200 in one memory cell MC connected commonly to selected bit line BL and selected word line WL (hereinafter referred to as selected memory cell).
Meanwhile, if memory cell MC connected to selected word line WL is connected to bit line /BL (one selected bit line), charging or discharging, which depends on the potential latched in node N2, is caused in capacitor 200 in one memory cell MC connected commonly to another selected bit line /BL and the selected word line WL.
Therefore, charging and discharging of capacitor 200 in selected memory cell MC are caused if the write data, i.e., the potential applied to data line IO (if this memory cell is connected to bit line BL) or data line /IO (if this memory cell is connected to bit line /BL) is at the high level and the low level, respectively. The state in which capacitor 200 has been charged and the state in which capacitor 200 has not been charged correspond to data "1" and data "0", respectively.
In this manner, the write data supplied to data line pair IO and /IO is written only in selected one memory cell MC.
In the data reading operation, the data is transmitted from memory cell array MA to data line pair IO and /IO. General circuit operation for reading the data will be described below with reference to FIGS. 7 and 8.
FIG. 8 is a timing chart showing variation of the potentials in some signal lines and some control signals in FIG. 7 in the data reading operation.
When after the fall of bit line equalization signal .phi.EQ (FIG. 8(a)), the potential of one of the word lines WL rises, as shown in FIG. 8(b), to a potential (Vcc+.alpha.) which is slightly higher than the power supply potential Vcc, depending on the stored data in each memory cell MC connected to this word line WL, the potential of bit line BL or /BL connected to this memory cell MC changes.
In a memory cell MC, when transistor 100 is turned on in such conditions that capacitor 200 has been charged, the connecting point between capacitor 200 and transistor 100 has the potential at the high level and bit line BL or /BL connected to this memory cell MC has intermediate potential Vb1, the charge is supplied to this bit line from capacitor 200, so that the potential of this bit line rises from the intermediate potential Vb1. Meanwhile, in a memory cell MC, when transistor 100 is turned on in such conditions that capacitor 200 has not been charged, the connecting point between capacitor 200 and transistor 100 has the potential at the low level and bit line BL or /BL connected to this memory cell MC has the intermediate potential Vb1, the charges flow from the bit line to capacitor 200, so that the potential of this bit line lowers from the intermediate potential Vb1. Since the capacitor 200 has a very small capacity, the potential of the bit line rises and lowers only to a very small extent in the above cases.
In response to the rise of potential of one word line WL, therefore, the potential of each bit line BL (if the memory cell MC connected to this word line WL is connected to bit line BL) or each bit line /BL (if the memory cell MC connected to this word line WL is connected to bit line /BL) slightly rises or lowers from intermediate potential Vb1, as shown in FIG. 8(c), depending on the stored data in one memory cell connected to the selected word line among a plurality of memory cells connected to this bit line. Thereby, a small potential difference is generated between two bit lines BL and /BL forming each bit line pair. Each sense amplifier SA is employed for amplifying the small potential difference between the corresponding bit lines BL and /BL to a value corresponding to the difference between ground potential Vss and supply potential Vcc.
Each sense amplifier SA is activated with a considerable delay after the rise of potential of any word line WL. For this purpose, sense amplifier activation signals .phi.nSA and .phi.nSA are set to the supply potential Vcc and ground potential Vss with a considerable delay after the rise of potential of any word line WL, as shown in FIGS. 8(e) and 8(d). Each sense amplifier SA is inactivated when both sense amplifier activation signals .phi.pSA and .phi.nSA are set to the intermediate potential Vb1.
Owing to the activation of each sense amplifier SA at the above timing, sense amplifier SA starts to sense and amplify the potential difference between the corresponding bit lines, when the potential difference between two bit lines BL and /BL forming corresponding bit line pair increases to some extent.
As a result, the potential of bit line BL or /BL having the slightly raised potential is raised to supply potential Vcc, as indicated by solid line (1) in FIG. 8(c), in response to the rise of sense amplifier activation signal .phi.pSA (i.e., fall of sense amplifier activation signal .phi.nSA). Meanwhile, the potential of the bit line /BL or BL paired with the above bit line is lowered to ground potential Vss, as indicated by dashed line(3), in response to the rise of sense amplifier activation signal .phi.pSA (i.e., fall of sense amplifier activation signal .phi.nSA).
Conversely, the potential of bit line BL or /BL having the slightly lowered potential is lowered to ground potential Vss, as indicated by solid line (2) in FIG. 8(c), in response to the fall of sense amplifier activation signal .phi.nSA (i.e., rise of sense amplifier activation signal .phi.pSA). Meanwhile, the potential of bit line /BL or BL paired with the above bit line is raised to supply potential Vcc from intermediate potential Vb1, as indicated by dashed line (4), in response to the fall of sense amplifier activation signal .phi.nSA (i.e., rise of sense amplifier activation signal .phi.pSA).
In this manner, each bit line pair BL and /BL have the potentials at the complementary logical levels which depend on the stored data in corresponding one among a plurality of memory cells MC connected to selected word line WL.
However, only the potentials appearing on the selected bit line pair are transmitted to data line pair IO and /IO through transistors 500 and 510. For this purpose, the potential of only one of column selecting lines CSL is raised to supply potential Vcc, as shown in FIG. 8(f), after the activation of sense amplifier SA, and thus transistors 500 and 510 provided between corresponding bit line pair BL and /BL and data line pair IO and /IO are turned on.
In this manner, the complementary potentials which correspond to the stored data in one memory cell MC connected commonly to selected word line WL and selected bit line BL or /BL are transmitted to data line pair IO and /IO. The potentials transmitted to data line pair IO and /IO are externally supplied therefrom as the read data.
In the above data reading operation, the charges move between capacitor 200 in the selected memory cell MC and bit line BL or /BL connected to the selected memory cell, which causes rising or lowering of potential of node N1 or N2 in sense amplifier SA connected to this bit line. This rising or lowering to the sufficient extent requires a time of about 10 ns. Thus, it requires a considerable time until the potential difference corresponding to the stored data in selected memory cell MC is sufficiently generated between inputs N1 and N2 of sense amplifier SA connected to selected bit line pair.
Sense amplifier SA operates to sense the potential difference between its inputs N1 and N2, i.e., potential difference between corresponding bit lines BL and /BL. If this potential difference is small, the sense amplifier SA may malfunction to raise the potential of the bit line which should be lowered to ground potential Vss or to lower the potential of the bit line which should be raised to supply potential Vcc. Therefore, if sense amplifier SA is activated immediately after the rising of potential of one of word lines WL, sense amplifier SA connected to the selected bit line pair starts to operate, before the sufficient potential difference is generated between selected bit lines BL and /BL in accordance with the stored data in selected memory cell MC. Thus, sense amplifier SA may malfunction to incorrectly determine the stored data in selected memory cell MC.
In order to prevent the incorrect determination of sense amplifier SA, sense amplifier SA is activated when a certain time elapses after the rise of potential of one word line WL, i.e., when the potential difference caused by the stored data in the selected memory cell MC between selected bit lines BL and /BL increases to some extent. A waiting time is required after the rise of potential of one word line WL and before the activation of sense amplifier SA. In order to reliably prevent the malfunction of sense amplifier SA, this waiting time is set slightly longer than a time which is required after the rise of potential of one word line WL and before the potential difference between the selected bit lines BL and /BL reaches the maximum value corresponding to the capacity of the capacitor 200 in selected memory cell MC.
Therefore, even if the potential difference corresponding to the stored data in selected memory cell MC is generated between selected bit lines BL and /BL before sense amplifier SA is activated, the time is not reduced, which is after the selection of one word line WL and before the complementary potentials corresponding to the stored data in selected memory cell MC appear in data line pair IO and /IO. Consequently, it is impossible to increase the speed of the data reading operation in the conventional DRAM.
There has been proposed a DRAM, of which data reading operation does not require a time margin between the start of operation of the sense amplifier for determining the stored data in the selected memory cell and the rise of potential of one word line, e.g., by Y. Nakagome et al, "Symposium on VLSI Circuits, Dig of Tech. Papers", pp 17-18, 1990, and M. Taguchi et al, "1991 IEEE International Solid-State Circuits Conference", pp 112-113.
FIG. 9 is a circuit diagram showing a construction of a major part of such DRAM.
A DRAM shown in FIG. 9 is different from the conventional DRAM shown in FIG. 7 in that a data line pair WDB and /WDB for receiving the write data is provided independently from a data line pair RDB and /RDB for receiving the read data and that a sense amplifier RSA for amplifying the potential difference between the selected bit lines BL and /BL in the data reading operation is provided independently from sense amplifiers WSA for latching the complementary potentials corresponding to the write data in the data writing operation.
Further, read data input circuits RD are provided correspondingly to respective bit line pairs for transmitting the variation of potentials of the bit line pairs BL and /BL to read sense amplifier RSA. Also, transistors 600 and 610 for write selection are provided correspondingly to each bit line pair for interrupting flow of unnecessary current between each bit line pair BL and /BL and write data line pair WDB and /WDB.
Now, circuit operations of this DRAM for writing and reading the data will be described below with reference to FIG. 10.
FIG. 10 is a timing chart showing variation of potentials appearing on some signal lines in the circuitry in FIG. 9 in the data writing operation and data reading operation.
First, the circuit operation for reading the data will be described below.
In the data reading operation, write data line pair WDB and /WDB receives the complementary potentials, as the write data.
Write data line WDB is connected through transistors 500 and 600 to bit line BL, and write data line /WDB is connected through transistors 510 and 610 to bit line /BL paired with bit line BL. Write selection transistors 600 and 610 have gates to which a write selection signal .phi.WS is commonly applied. In the operation for writing the data in memory cell array block MA, write selection signal .phi.WS is raised to supply potential Vcc as shown in FIG. 10(h), so that all the write selection transistors 600 and 610 are turned on. Therefore, in response to the rise of potential of one column selecting line CSL, the potentials of write data lines WDB and /WDB are transmitted to selected bit lines BL and /BL, respectively.
A circuit which forms write sense amplifier WSA and has the same construction as sense amplifier SA in FIG. 7 is disposed between two bit lines BL and /BL forming each bit line pair. Therefore, the potentials transmitted to selected bit lines BL and /BL are latched at nodes N1 and N2 in corresponding write sense amplifier WSA, respectively.
If the memory cell MC connected to selected word line WL is connected to bit line BL, the data is written in selected memory cell MC in accordance with the potential latched at node N1. If the memory cell MC connected to selected word line WL is connected to bit line /BL, the data is written in selected memory cell MC in accordance with the potential latched at node N2.
As described above, this DRAM performs the data writing operation in a manner similar to the conventional circuit operation.
The circuit operation for reading the data will be described below.
In all the memory cell array blocks, write selection signal .phi.WS is at the ground potential Vss, as shown in FIG. 10(h). Thus, all write selection transistors 600 and 610 are turned off to electrically isolate bit lines BL and /BL and write data lines WDB and /WDB from each other. Therefore, when the potential (FIG. 10(b)) of one of word lines WL rises after the fall of bit line equalization signal .phi.EQ (FIG. 10(a)), the potential of each bit line BL or /BL slightly rises or lowers from the potential Vb1 in response, which it has held, on the principle similar to that of the prior art, as shown in FIG. 10(c).
Meanwhile, the potential of one column selecting line CSL is raised, as shown in FIG. 10(f), at the substantially same timing as the rise of potential of one word line WL. In this DRAM, each column selecting line CSL is connected not only to the gates of bit line selection transistors 500 and 510 but also to corresponding read data input circuit RD.
Each read data input circuit RD includes N-channel MOS transistors 700 and 710 having gates respectively connected to corresponding bit lines BL and /BL and N-channel MOS transistors 720 and 730 each having a gate connected to corresponding column selecting line CSL.
Transistors 700 and 720 are connected in series between the ground GND and read data line RDB. Transistors 710 and 730 are connected in series between the ground GND and read data line /RDB.
Accordingly, at the time that the difference potential corresponding to the stored data in selected memory cell MC starts to generate between selected bit lines BL and /BL, transistors 700 and 710 of which gates are connected to these bit lines, respectively, have already been electrically connected to read data line pair RDB and /RDB.
Read sense amplifier RSA includes P-channel MOS transistors 740 and 760 connected in series between read data line RDB and power supply Vcc, and a P-channel MOS transistor 750. Transistor 750 is connected between read data line /RDB and transistor 760. Transistors 740 and 750 have gates commonly connected to read data line RDB. Thus, read sense amplifier RSA operates to amplify the potential difference between read data lines RDB and /RDB while read sense amplifier activation signal .phi.RSA applied to the gate of transistor 760 is at the low level. Meanwhile, the elements 740, 750, 760, 700, 710, 720 and 730 serve as a current mirror.
Read sense amplifier activation signal .phi.RSA falls to the low level, as shown in FIG. 10(g), at substantially the same timing as the rise of potential of one word line WL. Therefore, when the potential difference corresponding to the stored data in selected memory cell MC starts to be generated between selected bit lines BL and /BL, read sense amplifier RSA is already activated, and is electrically connected to transistors 700 and 710 connected to selected bit lines BL and /BL.
Therefore, upon generation of the potential difference between the selected bit lines BL and /BL, the difference of the voltages applied to the transistors 700 and 710 causes difference of the currents taken out from the transistors 700 and 710, in read data input circuit RD connected to these bit lines. On the other hand, since transistors 740 and 750 have respective gates connected together, a big potential difference appears between read data lines RDB and /RDB due to the difference between a current flowing through the transistors 700 and 720 and a current flowing through the transistors 710 and 730.
If the bit line BL has a higher potential as compared with the bit line /BL, the potential on the read data line /RDB swings to a low level while the potential on the read data line RDB swings to a high level, since the transistor 700 has a larger current driving capability than the transistor 710.
Conversely, if the line BL has a lower potential as compared with the line /BL, the potential on the line RDB swings to a low level while the potential on the line /RDB swings to a high level, since the transistor 710 has a larger current driving capability than the transistor 700.
As described in the foregoing, a current mirror amplifier comprising a read sense amplifier RSA and a read data input circuit RD is responsive to a very small potential difference appearing in bit line pair immediately after rising of the potential on a word line, to amplify the potential difference and provide a big potential difference to the read data lines RDB and /RDB.
Also in the data reading operation, write sense amplifier WSA is activated at the same timing as the sense amplifier SA in FIG. 7. Thus, sense amplifier activation signals .phi.pSA and .phi.nSA go to supply potential Vcc and the ground potential Vss (see FIGS. 10(d) and 10(e)) with a considerable delay after the rise of one word line WL. Thereby, write sense amplifier WSA operates when the potential difference corresponding to stored data in selected memory cell MC sufficiently generates between selected bit lines BL and /BL.
When the sense amplifier WSA starts to operate, the potential difference between selected bit lines BL and /BL increases, so that transistor 700 or 710 in read data input circuit RD connected to bit lines BL and /BL goes to more strongly turned-on state, which increases the current flowing from read data line RDB or /RDB. Consequently, read sense amplifier RSA operates more accurately. The sense amplifier WSA is activated in order to rewrite the data of a memory cell.
In the DRAM, as described above, the variation of potentials appeared on selected bit lines BL and /BL is transmitted through the gates of transistors 700 and 710 to read sense amplifier RSA. Therefore, even if read sense amplifier RSA malfunctions due to the small potential difference between selected bit lines BL and /BL and thus the potentials of read data lines RDB and /RDB start to change contrary to the stored data in selected memory cell MC, the potentials of selected bit lines BL and /BL are not affected by incorrect variation of the potentials of the read data lines RDB and /RDB. Thus, the data read from selected memory cell MC to selected bit lines BL and /BL is not broken.
By virtue of the operation of write sense amplifier WSA, the potentials of selected bit lines BL and /BL reliably attain to the values corresponding to the stored data in selected memory cell MC. When potential difference between the selected bit lines BL and /BL is sufficiently increased owing to the operation of write sense amplifier WSA, the operation is accurately performed to set the potentials of write data lines RDB and /RDB at values corresponding to the potential difference between selected bit lines BL and /BL.
Therefore, the potentials of read data lines RDB and /RDB reliably attain to the values corresponding to the stored data in selected memory cell MC, even if the time of start of the operation of read sense amplifier RSA is not delayed from the time of rise of potential of word line WL.
Conversely, if sense amplifier SA in FIG. 7 malfunctions in the data reading operation, the potentials themselves of selected bit lines BL and /BL do not reflect the stored data in selected memory cell MC, so that incorrect data ultimately appears on data lines IO and /IO. In addition, the data in the memory cell which should be rewritten correctly is damaged, which is a big problem.
In the data reading and writing operations, bit line selection transistors 500 and 510 which are provided correspondingly to selected bit lines BL and /BL, respectively, are turned on. Therefore, selected bit lines BL and /BL would be electrically connected by corresponding bit line selection transistors 500 and 510 to write data lines WDB and /WDB, respectively, if write selection transistors 600 and 610 do not exist. Meanwhile, write data lines WDB and /WDB are fixed at supply potential Vcc or the ground potential Vss in the operations other than that for writing the data in corresponding memory cell array block MA.
Generally, the DRAM includes a plurality of memory cell array blocks MA, and a plurality of write data line pairs WDB and /WDB are provided correspondingly to them.
FIG. 11 is a schematic block diagram showing a whole construction of a DRAM in which write data line pairs WDB and /WDB are provided independently from read data line pairs RDB and /RDB.
With reference to FIG. 11, when a plurality of memory cell array blocks MA are disposed in a column direction, for each memory cell array block MA, there are provided write data line pair WDB and /WDB and write sense amplifier WSA connected to bit line pairs BL and /BL in the memory cell array block as well as one read data line pair RDB and /RDB, read data input circuit RD connected to bit line pairs BL and /BL in memory cell array block and one read sense amplifier RSA.
Column selecting lines CSL are provided commonly to memory cell array blocks MA. Thus, memory cell array blocks MA include the same number of columns of memory cells. Gates of transistors 500 and 510 as well as transistors 720 and 730, which are connected to bit line pair corresponding to the same column, are commonly connected to the same column selecting line CSL.
In the data writing and reading operations, column decoder CD selectively applies the potential at the high level to one of column selecting lines CSL. Therefore, in the data reading and writing operations, the potential at the high level is applied to one of the column selecting lines CSL in each memory cell array block MA.
Word lines WL, however, are provided independently in respective memory cell array blocks MA. In the data reading and writing operations, row decoder RDE supplies a potential (Vcc+.alpha.) slightly higher than supply potential Vcc to one of the word lines WL in any one of the memory cell arrays MA. Therefore, both the potentials of one column selecting line CSL and one word line WL go to the high level only in one memory cell array block MA. Consequently, the data is written in and read from selected memory cells MC only in this one memory cell array block MA.
Each write data line pair WDB and /WDB is electrically connected to a common write data line pair GWDB and /GWDB only while corresponding memory cell array MA is selected. In the data writing operation, the write data, i.e., the potentials at the complementary logical levels are supplied to common write data line pair GWDB and /GWDB. These complementary potentials are applied through corresponding write data line pair WDB and /WDB only to one of the bit line pairs BL and /BL in selected memory cell array block MA, i.e., memory cell array block MA including word line WL to which the high potential is applied from row decoder RDE. More specifically, bit line pair BL and /BL to which the complementary potentials are actually applied is the bit line pair connected to one column selecting line CSL to which the potential at the high level is applied from column decoder CD.
As described above, since the memory cell array is divided into memory cell array blocks MA in the practical construction, the potential of one column selecting line CSL has the high level in not only selected memory cell array block but also each of unselected memory cell array blocks in both the data reading operation and data writing operation.
Therefore, in FIG. 9, even when memory array block MA is not selected transistors 500 and 510 connected to one of bit line pairs BL and /BL in unselected memory cell array block MA are turned on. When memory cell array block MA is not selected, write data lines WDB and /WDB which are provided correspondingly to unselected memory cell array block MA are fixed at supply potential Vcc or the ground potential Vss.
Meanwhile, each bit line pair BL and /BL in unselected memory cell array block MA is equalized by bit line equalizer circuit EQ connected thereto to an intermediate potential Vb1. Therefore, if write selection transistors 600 and 610 were not provided, current flows from a power supply feeding the intermediate potential Vb1 to the equalizer circuit EQ (hereinafter referred to as a bit line precharge power supply: not shown) to write data line WDB through the selected bit line BL and transistors 400 and 500 connected to this bit line, and current flows between bit line precharge power supply and the other write data line /WDB through the other selected bit line /BL and transistors 410 and 510 connected thereto, in each of the non-selected blocks.
As described above, if bit line selection transistors 600 and 610 were not provided, useless current would flow between the bit line precharge power supply and the power supply for supplying supply potential Vcc or the ground potential Vss to write data line pair WDB and /WDB, in each unselected block, resulting in increase of power consumption. Bit line selection transistors 600 and 610 are provided for preventing the above problem.
In the data reading and writing operations, all write selection transistors 600 and 610 which are provided correspondingly to the unselected blocks receive write selection signal .phi.WS at the low level to be turned off, so that current paths between bit lines BL and /BL and write data line pairs WDB and /WDB are interrupted in these unselected blocks, respectively. In each unselected block, therefore, the current does not flow between write data line pair WDB and /WDB and bit line precharge power supply through bit line pair BL and /BL corresponding to one column selecting line CSL to which the potential at the high level is applied.
As described above, the DRAM of a so-called separated I/O type, which is independently provided with read data line pairs and write data line pairs, requires read data input circuits RD and two write selection transistors 600 and 610 which are provided correspondingly to the respective bit line pairs. Each read data input circuit RD is formed of four transistors 700, 710, 720 and 730, as shown in FIG. 9.
Therefore, the DRAM of separated I/O type has a construction identical with the construction in which six transistors are additionally provided correspondingly to each bit line pair in a DRAM of so-called common I/O type in which read data lines and write data line pairs are common to each other (see FIG. 7).
The DRAM of separated I/O type requires a signal line for supplying selection signal .phi.WS for controlling the write selection transistors to the gates of write selection transistors 600 and 610.
Therefore, the DRAM of separated I/O type in the prior art has a large number of components, elements and signal lines, so that it occupies larger chip area than that the DRAM of common I/O type.
In order to avoid the above problem, the write selection transistors may be eliminated. In this case, however, the current flows between the bit line precharge power supply and power supply for applying Vss or Vcc through write data line pairs WDB and /WDB in the unselected blocks, on the principle described above.
Thus, it is difficult to suppress both the increase of the occupied chip area and increase of the power consumption in the conventional DRAM in which the access time in the data reading operation is reduced.

Semiconductor memory device divided into blocks and operable to read and write data through different data lines and operation method of the same


A cross-domain data transfer technique is disclosed in which page remapping operations are eliminated in situations where physical memory addresses can be passed across domains. By passing physical memory addresses across domains instead of virtual memory addresses, the page remapping operations necessarily associated with passing virtual memory addresses across domains can be avoided in many cases. With the receipt of data across domains, page remapping operations are able to be deferred until the data is received in a domain that needs to touch the data. In certain cases, the transfer of data can be completed without ever having to map in the data to the receiving domain's address space. With the transmission of data across domains, where possible the pages are borrowed in their physical form. The invention can be embodied in many ways, including system, apparatus or method forms.

1. Field of the Invention
The present invention relates to data transfer across domains, and more particularly, to data transfer across a number of different protection domains using page remapping.
2. Description of the Related Art
Operating systems that utilize different protection domains require a data transfer scheme to transfer data from one domain (sender or source) to another domain (receiver or sink). The operating system is responsible for not only the transfer of the data from one domain to another but also insuring that the protection or security information is updated so that processes running in a certain domain will not interfere with processes running in other domains.
Through use of multiprogramming, modern computer systems are able to execute several processes at essentially the same time. With multiprogramming, the computer (e.g., CPU) and the memory are time shared amongst the several users (i.e., processes), thereby giving the illusion that all users have their own machine. Computers which use multiprogramming usually also provide for a sharing of code and data between processes. Such sharing allows communication between the processes and can reduce the number of copies of identical information being stored.
Despite the ability to share code and data between processes, often times data must be transferred from one domain to another domain. Simply copying the data from the sender domain to the receiver domain is unacceptable because it is so inefficient and burdensome to the computer and the memory that they become a bottleneck. As networks become faster, this bottleneck worsens because when data is copied, every word passes through the computer and the memory.
Prior attempts to minimize data transfer overhead associated with the transfer of data between different protection domains in an operating system have typically used virtual memory remapping techniques. Virtual memory remapping techniques give the appearance of data transfer by remapping data pages from the sender domain to the receiver domain. See, e.g., S.-Y. Tzou and D. P. Anderson, "The Performance of Message-passing using Restricted Virtual Memory Remapping," Software-Practice and Experience, Vol. 21, March 1991. Here, instead of copying the data across domains, virtual memory remapping techniques are used to update page table entries in a memory-management unit (MMU).
However, in reality, simulating the data transfer by conventional virtual memory remapping techniques requires a lot more work than simply updating page table entries within the MMU. Typically, the operating system has to manage buffers at the source and destination, update virtual mappings at several levels, and perform translation-look-aside buffer (TLB) consistency actions. As a result, the total work involved with remapping can be expensive.
Recently, proposals have been made which attempt to cut down the number of page remapping operations required for data transfer across different domains. See, e.g., Peter Druschel and Larry L. Peterson, "Fbufs: A High-Bandwidth Cross-Domain Transfer Function," Proceedings of the Fourteenth ACM Symposium on Operating Systems Principals, December 1993. However, these recent proposals are unsatisfactory because they require deviation from existing UNIX networking I/O interface, require special hardware support and/or compromise data protection or security.
Thus, there is a need for a cross-domain data transfer technique which does not require extensive page remapping operations, yet maintains data protection and security and works with existing network interfaces without the need for special hardware support.

Cross-domain data transfer using deferred page remapping


According to one embodiment of the invention, a method for controlling flow of data cells within a digital subscriber line access multiplexer is provided. The method includes providing a flow control package for a cell delineation module of the digital subscriber line access multiplexer. The method also includes receiving, at the flow control package, at least one signal indicating that one or more buffers within the digital subscriber line access multiplexer have reached a predetermined data storage capacity. The method also includes directing, from the flow control package, at least one device that is operable to transmit the data to the one or more buffers to halt transmission of the data to the one or more buffers in response to receiving the signal.

Digital subscriber line (DSL) technology provides faster data service over existing twisted pair wiring. Implementation of DSL technology requires a communications server that may operate as an interface between the individual DSL subscribers and the Internet Protocol (IP) network.
Advances in communications technology provide methods for making DSL servers that are less expensive and more powerful. For example, data multiplexing may be implemented within the communications server to reduce the number of components on associated circuit boards. Reducing the number of components reduces the cost of manufacturing the server and frees circuit board space. The circuit board space made available may be used to add more capabilities to the communications server. However, data multiplexing may also adversely affect the ability to control data flow within the communications server. This lack of flow control may cause data overflow at buffers associated with the communications server.

Method and system for controlling flow of multiplexed data


A linkage coupling a drum foot pedal rotor to a drum beater apparatus comprising in combination an elongated link, a first universal joint coupling the rotor to the link, and a second universal joint coupling the link to the apparatus, at least one of the universal joints coupling first and second components relatively rotatable about a transverse axis, two transversely spaced bearings carried by the first component, each bearing including annular inner and outer races and bearing balls located between the races, there being members tightly coupling the inner races to the second component at transversely spaced locations, whereas the inner races are offset transversely relative to the outer races to thereby clamp the balls transversely between the races, and immobilizing means joining the outer races to the first component, and/or the members to the second component.

This invention relates generally to rotary drives between drum foot pedal rotors and drum beaters, and more particularly concerns elimination of play between mechanical coupling elements located between such rotors and drum beaters.
The use of foot pedals remote from drum beaters introduces associated play between such coupling elements, resulting in loss of precise timing of drum beating in response to operation of foot pedals. Such play can occur when one or more universal joints is in the drive train of elements between the drum foot pedal and the drum beaters. There is need for coupling that removes any such unwanted play, to enhance precise timing of drum beating during musical performances.


A computer user interface is provided which allows a user to adjust the size of icons based upon a user's preference or based upon a characteristic of the objects that the icons represent. When the icon sizing is performed according to a user preference, a relative sizing scheme or an arbitrary icon sizing scheme can be employed to variably size icons. Providing the ability to size icons in such a manner allows users to represent a user's categorization of object importance, for example.

1. Field of the Invention
The present invention is directed to icons and similar types of graphical objects that are employed in a graphical user interface for computers. More specifically, the present invention is directed to a graphical user interface which displays variable size icons based on various user preferences and/or object characteristics.
2. Description of the Related Art
The rapid advance of computer technology has enabled computer programmers to greatly enhance the sophistication of their software programs. Yet, an increase in sophistication often brings an increase in application complexity. Such complexity often serves to confuse and frustrate computer users as they attempt to learn the operation of a new computer application, especially when the software manuals are large and burdensome to use.
The computer industry has attempted to address the above drawback by designing application programs with user-friendly display interfaces. Generally, the user-friendly paradigm aims to present information in the simplest and most intuitive fashion possible. This may be achieved by organizing information using a series of hierarchical menus or windows. Also, user-friendliness is promoted by including graphical metaphors in the user interface instead of nondescriptive command-line prompts. For example, images of file folders are used to identify containers for storage of information, and graphical depictions of trash containers are employed to assist in the disposal (e.g., deletion) of information.
Conventional graphical user interfaces make extensive use of icons within a computer display system. Graphical icons used on display screens in computer systems can represent physical objects in the system, such as storage media and servers, as well as electronic files that pertain to documents and computer applications selected by a user. The icons present a simple graphical metaphor to users that provide a basic description and/or function of the content of the object represented by the icon. Besides providing access to computer applications and documents, icons can be manually manipulated by a user to perform tasks easily. For example, an icon representing a text document can be selected by a mouse that is manipulated by a user, and be either placed onto another icon representing a word processing application or placed onto an icon of a printer which represents a printing application. Once placed on the printer icon or word processor icon, the document is printed or opened by the word processor, respectively.
Users have been permitted to personalize the graphical user interface, by enabling the user to both create and modify graphical icons for a variety of purposes. For example, facial features such as hair color, skin color and hair style of an icon image representing a human face can be edited. Many different icons can be employed within a computer system to graphically represent the presence of different applications and documents. Many of these icons are only changed slightly with respect to their appearance. An icon image can also change depending upon the status of the document or how the document is currently being employed with the computer system. For example, an object may have one icon image when it is not being used, and another slightly different icon that represents the same object when the object is being accessed or used.
An icon may give the user a basic idea of the functions that are performed by a program represented by the icon or the contents of documents represented by the icon. However, there has been no manner to describe the relative importance of programs or documents represented by icons. While individual labels (i.e., the ability to color icons) can be applied to icons to help classify icons, such categorization still does not provide an intuitive indication of the relative importance of the files or program represented by icons, since the user must remember which color is associated with which category.
To provide some flexibility to the user, the size of all icons in a system can be manually altered. However, currently there are essentially two nominal sizes for icons, typically denoted as small and large. For instance, in the Macintosh Operating System developed by Apple Computer, Inc., a small icon has a 16-by-16 pixel area representation and large icon has a 32-by-32 pixel area representation. A user can alter all icons of a display system from one size to another size based upon his or her preference. For example, if a user wishes to have small icons represented on a display system, he or she can employ a display option to have all icons displayed with 16-by-16 pixel icon sizes. Alternatively, if a user desires, the size of all icons in a display system can be increased to the larger pixel area. A user can change the size of the icons if, for example, hindered eyesight requires larger icons. However, such difference in size does not indicate the relative importance of the files or program represented by the icon, since the change in icon size is performed universally for all icons in a container, such as a folder or window. Accordingly, in order to present a more informative and personalized user interface, a manner of describing to a user relative importance of an icon in relation to other icons in a system is desirable.

Graphical user interface for computers having variable size icons


In an actuation circuit for a stepping motor, one switching element and its associated coil are connected at one connecting point, while the other switching element and its associated coil are connected at another connecting point. A pair of switching circuits and a pair of rectifying circuits are provided between two connecting points. When one of switching elements is changed from an ON condition to an OFF condition, the voltage difference between two connecting points allows the current to flow in a designated direction through the switching circuit and the rectifying circuit combined, thereby releasing the energy stored in the coils.

1. Field of the Invention
This invention relates to an inductance L load actuating apparatus that actuates an inductance L load of a stepping motor or the like.
2. Related Art
A conventionally known apparatus, as this kind of apparatus, is for example disclosed in the Japanese Utility Model No. HEI 7-33598, published in 1995. The stepping motor apparatus, disclosed in this prior art, reference will be explained in greater detail hereinafter.
FIG. 22 shows an actuation circuit for a bipolar winding 2-phase stepping motor. A direct-current power source unit 1, generating a voltage Vcc, is connected to each of first coil 2a to fourth coil 2d. These first coil 2a to fourth coil 2d are connected to first to fourth switching elements (MOS transistors) 3a to 3d, respectively.
A first current-detection resistance 4a is connected between a common connecting point of switching elements 3a, 3c and the ground. A diode 5a is connected in parallel to the first current-detection resistor 4a for forming a current path for discharging energy stored in the coil. In the same manner, a second current-detection resistance 4b is connected between a common connecting point of switching elements 3b, 3d and the ground. A diode 5b is connected in parallel to the second current-detection resistor 4b.
Responding to exciting current signals supplied through output lines 7a and 7b of an exciting signal generation circuit 7, first and second control circuits 6a and 6b, respectively control the switching elements 3a to 3d in accordance with a predetermined exciting method (e.g. 2-phase exciting method). More specifically, control circuit 6a compares the current detection signal obtained from a detection line 8 connected to the first current-detection resistance 4a with a reference voltage V1 produced from a reference voltage generation circuit 10, and executes the intermittent control (i.e. chopping control) for the associated switching elements 3a and 3c. Similarly, control circuit 6b compares the current detection signal obtained from a detection line 9 connected to the second current-detection resistance 4b with a reference voltage V2 produced from the reference voltage generation circuit 10, and executes the intermittent control (i.e. chopping control) for the associated switching elements 3b and 3d. Through the above-described chopping control, a stepping motor is actuated by a constant current.
FIG. 23 shows waveforms of various portions of the above-described actuation circuit obtained when the stepping motor is actuated by the two-phase exciting method. Waveforms (A) and (B) represent exciting signals, while waveforms (C) through (F) represent gate signals of switching elements 3a through 3d, respectively. When the exciting signal shown by the waveform (A) is in HIGH level, switching element 3a is subjected to the chopping control. When the exciting signal shown by the waveform (B) is in HIGH level, switching element 3b is subjected to the chopping control. Furthermore, when the exciting signal shown by the waveform (A) is in LOW level, switching element 3c is subjected to the chopping control. When the exciting signal shown by the waveform (B) is in LOW level, switching element 3d is subjected to the chopping control.
Control circuits 6a and 6b have the same arrangement. FIG. 24 shows the detailed arrangement of control circuit 6a. Operation of control circuit 6a, during an exciting period for generating a signal to activate coil 2c, will be explained with reference to the timing chart of FIG. 25.
When switching element 3c is in an ON condition, the voltage applied between both ends of current-detection resistance 4a, i.e. current-detection voltage Vr, becomes a positive voltage in proportion to the current flowing through this resistance 4a during its ON period. On the other hand, when switching element 3c in an OFF condition, current-detection voltage Vr is equalized to the forward voltage drop of diode 5a. Accordingly, as shown by the waveform (A) of FIG. 25, current-detection voltage Vr varies in response to ON and OFF of switching element 3c.
A comparator 61 compares the current-detection voltage Vr with the reference voltage V1. When the current-detection voltage Vr reaches to the reference voltage V1, the output of comparator 61 is turned to LOW level. Thus, a capacitor 62 is discharged. When the current-detection voltage Vr is smaller than the reference voltage V1, the output of comparator 61 is in HIGH level. Thus, capacitor 62 is charged. The terminal voltage V.sub.62 of capacitor 62, hence, varies as indicated by the waveform (B) of FIG. 25. This voltage V.sub.62 is compared with a predetermined reference voltage V.sub.0 at a comparator 63, and is converted into a pulse signal V.sub.63 as shown by the waveform of FIG. 25. This pulse signal V.sub.63 is level-inverted through a NOT circuit 64.
In an exciting period of coil 2c, the signal produced from exciting signal generation circuit 7 is in LOW level and the output of NOT circuit 66 is in HIGH level. Hence, the pulse signal is supplied to switching element 3c through AND circuit 65. A voltage V.sub.GS, having the waveform (D) of FIG. 25, is applied between the gate and the source of switching element 3c.
Accordingly, as shown by waveforms (A) through (D), when the switching element 3c is turned on at the time t1 and the current-detection voltage Vr has reached the reference voltage V1, the output of AND circuit 65 is turned to LOW level and the switching element 3c is turned off. Thereafter, capacitor 62 is charged. When the terminal voltage V.sub.62 reaches the reference voltage V.sub.0 at the time t2, the output of AND circuit 65 is turned to HIGH level and switching element 3c is turned on. By repeating this operation, switching element 3c is subjected to the chopping control.
During the ON period (t2 to t3) of switching element 3c, current Ic shown by the waveform (E) of FIG. 25 flows through a circuit consisting of power source unit 1, coil 2c, switching element 3c, current-detection circuit 4a and the ground. During the OFF period (t1 to t2) of switching element 3c, energy stored by the excitement of coil 2c is discharged through coil 2a which is electromagnetically coupled with this coil 2c. In other words, current Ia flows through a circuit consisting of coil 2a, power source unit 1, bypass diode 5a and a built-in diode of switching element 3a. When the flowing direction of current Ia is defined by the arrow shown in FIG. 24, current Ia has the waveform (F) shown in FIG. 25. The composite current I of current Ic and current Ia is shown by the waveform (G) of FIG. 25.
The above-described operation is performed in the exciting period of any other coils 2a, 2b and 2d, in the same manner as in the exciting period of coil 2c.
As described above, current Ic flows in response to turning-on operation of switching element 3c. In this case, a voltage Vc (refer to the waveform (H) of FIG. 25) at a connecting point C between switching element 3c and coil 2c is a low-level voltage equivalent to the sum of an ON-voltage of switching element 3c and current-detection voltage Vr. A voltage Va (refer to the waveform (I) of FIG. 25) at a connecting point A between switching element 3a and coil 2a becomes a high-level voltage induced in proportion to the gradient of current Ic due to mutual induction between activated coil 2c and coil 2a.
When switching element 3c is turned to the OFF condition, the voltage Vc is increased to the high-voltage level by the energy stored based on the excitement of coil 2c. At the same time, in the coil 2a paired with coil 2c, a negative voltage is caused with a voltage drop equivalent to voltage Va by the energy stored in coil 2c. As a result, switching element 3a, having being set in the cutoff condition, is turned on with inverse bias, thereby supplying exciting current to coil 2a.
Accordingly, when switching element 3c is turned off, energy stored in coil 2c is discharged only through the coil 2a which is paired with coil 2a.
With the above-described operation, according to the above-described conventional system, voltage Vc at the connecting point C is increased up to a very high-voltage level in response to the transition of switching element 3c from ON to OFF. For this high voltage, it is necessary to increase the withstand voltage of switching elements 3a through 3d. Furthermore, emissive noise may be caused by the high-voltage surge.


An array substrate, a liquid crystal display and a control method thereof are disclosed. The array substrate includes scanning lines, data lines, pixel units, and common lines. Each common line is disposed along a row of pixel units. The array substrate also includes a common voltage supply line, and dual-channel selection switches each having an output terminal connected to a set of common lines, two input terminals connected to a common voltage high level supply line and a common voltage low level supply line respectively to selectively apply a high level or a low level to the common lines, thereby avoiding delay of the common voltage Vcom and the Vcom drift during a display mode and improving the display effect for an image.

Liquid Crystal Display (LCD) devices are widely used in flat-panel displays. A conventional LCD device is a Thin Film Transistor Liquid Crystal Display (simply referred to as TFT-LCD). A Thin Film Transistor (TFT) includes an amorphous-Silicon Thin Film Transistor (a-Si TFT) and a Poly-Silicon Thin Film Transistor (Poly-Si TFT). Furthermore, the Poly-Silicon Thin Film Transistors includes Low Temperature Poly-silicon (referred to as LTPS) TFT-LCDs and High Temperature Poly-silicon (referred to as HTPS) TFT-LCDs. Specifically, the TFT-LCDs in the prior art are referred to as the a-Si TFT-LCDs. The circuit diagram of the internal structure of a TFT-LCD is shown in FIG. 1, and the structure will be described as follows.
Multiple scanning lines 51 to Sm parallel to each other and multiple data lines D1 to Dn parallel to each other are disposed on the array substrate of the TFT-LCD. The scanning lines are arranged to intersect with the data lines and pixel units 110 are disposed at the intersections of the scanning lines and the data lines to form a pixel unit array. The pixel unit 110 includes a transistor 112 of which the gate is connected to a corresponding scanning line, the source of the transistor 112 is connected to a corresponding data line and the drain of the transistor 112 is coupled to a common voltage Vcom via a pixel element 114. Specifically, a storage capacitor 116 connected across the pixel element 114 to stabilize the voltage across the pixel element 114.
When an image is displayed by the TFT-LCD, a scanning signal is transmitted to the scanning lines to turn on a transistor connected to each of the scanning lines. Then, a data signal is sequentially applied to the pixel units 110, and the storage capacitor 116 will be charged upon the data signal is transmitted from the source to the drain of transistor 112. Meanwhile, the common voltage Vcom is applied to the other end of the pixel element 114, since Vcom is different from the voltage of the drain of the transistor, the voltage difference is formed between the two ends of the pixel element 114, and thus the pixel element 114 is lit up.
On the array substrate of the TFT-LCD, the common voltage is applied to the whole substrate, therefore, when one pixel unit is driven, the common voltage is applied to the whole substrate simultaneously. That is, the load driven by the common voltage Vcom may be all the pixel units on the array substrate, so that the common voltage Vcom may not have sufficient drive capability.
In order to solve the problem, the solution according to the prior art is shown in FIG. 2. One common line is disposed for each row of pixel units, and a common voltage is applied to the pixel units via the common line. The common line is connected to a corresponding scanning line via a transistor 21. Here, the gate of the transistor 21 is connected to the corresponding scanning line, and the drain of the transistor 21 is connected to the common line, and the sources of all the transistors 21 on the array substrate are connected to a terminal from which the common voltage is supplied.
During display of an image, transistors within a row of pixel units and the transistor 21 connected to the corresponding common line are turned on simultaneously by a scanning signal, thus the common voltage is applied to the pixel units row by row, the load for the common voltage is reduced and the drive capability of Vcom is improved.
However, adopting this design will affect the quality of display due to the extremely short charging time of the pixel located away from a common voltage signal input terminal which is caused by the RC delay. Since a common electrode line has the common voltage only when the row of scanning line is turned on, the common electrode line is in a floating state at other times and can be affected by disturbance, and thus the quality of display will be deteriorated.

Array substrate with multiple common lines, liquid crystal display and control method thereof

SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD.


Systems and methods are provided to implement a state map to control operations of a complementary metal-oxide-semiconductor (CMOS) sensor. The state map can be a table comprising one or more locations. Each of the locations can comprise a destination state to define the operations of the sensor and an exit criterion to advance to a next location in the state map. For example, an operation sequence can be implemented using the state map to instruct the CMOS sensor to perform a specific set of operations. Further, a data value to represent the destination state and/or a variable input can be stored in a writable address of a register. Thus, a simplified architecture can be provided to implement CMOS sensor operation states, for instance, to improve interactions between real time and non-real time signals and to increase functionality of the CMOS sensor.

Recent developments in semiconductor technology include the complementary metal-oxide-semiconductor (CMOS). CMOS is a technology employed in constructing integrated circuits, producing semiconductor devices having a wide variety of uses in electronic components. These uses can include, for instance, microprocessors, microcontrollers, static random access memory, and other digital logic circuits. Analog uses include data integrators, and integrated transceivers employed in electronic communication, as well as for image sensors.
One particular type of image sensor leveraging CMOS technology is the CMOS image sensor. A CMOS image sensor can be incorporated into a System-on-Chip (SoC). As such, the SoC can integrate various components (e.g., analog, digital, . . . ) associated with imaging into a common integrated circuit. For instance, the SoC can include a microprocessor, microcontroller, or digital signal processor (DSP) core, memory, analog interfaces (e.g., analog to digital converters, digital to analog converters), and so forth.
Visible imaging systems utilizing CMOS imaging sensors can reduce manufacturing costs for such systems, reduce power consumption of an electronic device, and reduce electronic noise, while improving optical resolution. For instance, cameras can use CMOS imaging System-on-Chip (iSoC) sensors that efficiently marry low-noise image detection and signal processing with multiple supporting blocks that can provide timing control, clock drivers, reference voltages, analog to digital conversion, digital to analog conversion and key signal processing elements. High-performance video cameras can thereby be assembled using a single CMOS integrated circuit supported by few components including a lens and a battery, for instance. Accordingly, by leveraging iSoC sensors, camera size can be decreased and battery life can be increased. The iSoC sensor has also facilitated the advent of more advanced optical recording devices, including dual-use cameras that can alternately produce high-resolution still images or high definition (HD) video.
An image sensor converts an optical image into an electronic signal. This electronic signal can then be processed and reproduced, for instance on a display screen. Typically, the image sensor comprises an array of many active pixels; each active pixel comprising a CMOS photodetector (e.g., photogate, photoconductor, photodiode, . . . ) controlled by circuits of digitally controlled transistors. The CMOS photodetector can absorb electromagnetic radiation in or around the visible spectrum (or more typically a subset of the visible spectrum—such as blue wavelengths, red wavelengths, green wavelengths, etc.), and output an electronic signal proportionate to the electromagnetic energy absorbed.
Electronic imaging devices, such as digital cameras and particularly video recorders, capture and display many optical images per second (e.g., 30 per second, 60 per second, 70 per second, 120 per second, . . . ), equal to the optical frame rate of the imaging device. Capturing a single image in a single frame time involves multiple operations at the CMOS pixel array and readout circuit. One mechanism for image capture is referred to as a rolling shutter. As an example, rolling shutter operations can include capture and convert (e.g., capture light information and convert to electrical information), readout, and reset operations. Some frames can be constructed so that the capture and convert operation, and the reset operation are performed in a single reset cycle, for instance, with reset of a prior frame occurring at a beginning of the reset operation, and capture and convert of a current frame occurring at the end of the reset operation. Thus, alternating reset and readout cycles can clear the CMOS photodetector array, capture a new image, and output the captured image for processing.
Conventional images sensors communicate with external components on the iSoC to control the image sensor operations (e.g., readout operations, reset operations, etc.). Common external components on the iSoC include a processor, serial peripheral interface (SPI), and a field programmable gate array (FPGA) to maintain the image sensor operations. Since timing in the image sensor is often very specific, the FPGA communicates with the image sensor using real time signals. The processor and SPI communicate with the image sensor using non-real time signals. However, the non-real time signals do not allow precise control of timing. For example, the image sensor may need to read out data five clock cycles after the rising edge of a synchronization signal. If the data is not read out five clock cycles after the rising edge of a synchronization signal, the image sensor operations can be hindered. Since real time signals and non-real time signals are used to communicate to the image sensor, fine control of timing is often very difficult. As a result, complicated interactions between the non-real time signals and the real time signals are used to control the image sensor operations. Consequently, conventional image sensors do not allow versatile implementation for multiple applications and/or complex image sensor operations.

Sensor state map for managing operational states of an image sensor


A chemical process apparatus component comprising a high purity, corrosion resistant composite including a continuous carbon fiber reinforced carbon matrix having a level of total metal impurity below about 10 ppm, preferably below about 5 ppm. Most preferably, the composite has a level of metal impurity below the detection limit of inductively coupled plasma spectroscopy for the metals Ag, Al, Ba, Be, Ca, Cd, Co, Cr, Cu, K, Mg, Mn, Mo, Na, Ni, P, Pb, Sr and Zn. A process utilizing at least one of the above components for use in a chemical process apparatus, wherein said component is in contact with at least one of i) a high purity material, such as for processing, and ii) a corrosive process media.

The chemical process industry uses a variety of reactors for the production of various chemicals. In many instances the media in which the chemical reactions occur is highly corrosive to conventional metals. In these reactions, high temperatures are often employed in conjunction with aggressive chemical reagents such as acids or alkalis.
As an example, processing or reclaiming precious metals by extraction of the metals from various sources, using methods involving dissolution in aqua regia, is well known. The precious metal group includes silver, gold and platinum. These metals are used in a variety of high performance applications where their outstanding corrosion resistance and catalytic behavior prove useful.
Despite the history of the use of aqua regia and the effort expended in reclaiming the precious metals, severe problems are still encountered due to the difficulty in manipulating and containing this highly corrosive acid, which comprises a 3:1 or 4:1 mixture of hydrochloric and nitric acids, and which will dissolve most metals rapidly. Conventional equipment capable of handling this acid is usually made from ceramics or glass. Problems associated with poor durability and poor shock resistance frequently occur, posing severe safety hazards, and in some cases leading to significant financial losses.
Chemical reactors usually contain various plates, baffles, stirrers, trays, tubes and the like, which are usually made from steel or other metals. In certain chemical reactions, these parts have to be replaced on a frequent basis due to the high level of corrosion that takes place. Replacement of these parts means lengthy reactor downtime with serious economic consequences.
In some chemical reactor applications, graphite has found use due to its corrosion resistance. However, its widespread use is limited by its poor structural properties and overall limited durability.
There is, therefore, a need to develop chemical reactor parts that exhibit superior corrosion resistance compared to conventionally used materials such as steels, and improved structural and lifetime properties compared to graphite. Such materials must exhibit thermal and chemical stability, corrosion resistance, and must not transfer impurities to the products of the reaction, for example, to food additives, catalysts, pharmaceutical compounds and the like.
There is also a need to develop a robust, structural material that is inert to attack by aqua regia. Such a material must be capable of being fabricated into a variety of components. In addition, such a material must be highly pure so that contamination of the high value precious metals is minimized.
High temperature composite materials, in which a ceramic or carbon matrix is reinforced with a continuous fiber, find use in a variety of applications. One common application for composite materials is in aircraft brakes. In this use, the friction, or braking, material is made from a carbon matrix reinforced with carbon fibers (carbon/carbon or C/C). Such materials have high mechanical strength and are capable of operating at extreme temperatures, up to 3000.degree. C. (in a non-oxidizing atmosphere). Composites in which both the reinforcing fiber and the matrix are ceramic find use in specialty applications such as aircraft engine parts where both strength at high temperature and low weight are needed.
Carbon/carbon based composites offer outstanding chemical resistance. This coupled with their lightweight and structural performance makes them ideal candidates for chemical processing equipment. An added advantage is that, according to the present invention, such materials can be produced at extremely high levels of purity, thus minimizing the risks of product contamination.
It is therefore an object of the present invention to provide components for use in chemical process reactors that are superior in mechanical and thermal properties to conventional graphite components.
It is a further object of the present invention to provide components for use in chemical process reactors that are superior in purity characteristics to conventional graphite components and to conventional carbon/carbon materials.
It is a further object of the present invention to provide components for use in chemical process reactors that are superior to conventional metals in corrosion resistance.
It is a further object of the present invention to provide a process for processing or reclaiming precious metals by dissolution in aqua regia, using processing components that are resistant to corrosion by aqua regia.

Chemical process employing corrosion resistant composites


A compact for storing a plurality of cosmetics includes a tray for storing cosmetics in a first and a second side; a base having a pair of hinge pins received by the tray, the tray pivoting in the hinge from a first position making the first side accessible to a user to a second position making the second side accessible to the user.

Compacts are containers that permit a user to carry cosmetics from one location to another without spillage of the cosmetics or affecting the quality of the cosmetics. Typically, these cosmetics are made of highly compressed powder or hot poured anhydrous contained in small palettes called pans and are specialized to be foundation, blush, lip stick, eye shadow, face powder, or the like. A user applies the cosmetic to their body via a small brush or like applicator.
The pans themselves are suitably sized, such as 1 inch length by ¾ inch width by ⅛ inch height, to provide the user a predetermined amount of cosmetic. Given the practical limitations of a compact to maintain its portability, the size of the compact limits the number of pans that may be provided in the compact. Thus, compacts generally only provide three or four cosmetic pans.
Understandably, users would like to have a greater choice in available cosmetics by providing additional cosmetic pans. While reducing the size of each pan and providing more pans is an option for manufacturers, users prefer that the traditional pan size is maintained and that more pans are provided in a compact of the same size.
Thus, a need exists for providing additional storage of cosmetic pans in a compact in the same limited space. A need exists for such storage to be readily accessible by the user.


Rotary lithographic printing members are prepared from a non-porous zirconia ceramic that is an alloy of ZrO.sub.2 and a second oxide chosen from MgO, CaO, Y.sub.2 O.sub.3, Sc.sub.2 O.sub.3, a rare earth oxide or a combination of any of these. These printing members can be rotary printing cylinders having a zirconia alloy ceramic printing surface. Such cylinders can be composed of zirconia alloy ceramic throughout, or have a ceramic sleeve or shell mounted around a non-ceramic core. In use, the surface of the zirconia alloy ceramic printing member is imagewise exposed to infrared radiation which transforms it from a hydrophilic to an oleophilic state or from an oleophilic to a hydrophilic state, thereby creating a lithographic printing surface which is hydrophilic in non-image areas and is oleophilic and thus capable of accepting printing ink in image areas. These printing members are directly laser-imageable as well as image erasable.

The art of lithographic printing is based upon the immiscibility of oil and water, wherein the oily material or ink is preferentially retained by the image area and the water or fountain solution is preferentially retained by the non-image area. When a suitably prepared surface is moistened with water and an ink is then applied, the background or non-image area retains the water and repels the ink while the image area accepts the ink and repels the water. The ink on the image area is then transferred to the surface of a material upon which the image is to be reproduced, such as paper, cloth and the like. Commonly the ink is transferred to an intermediate material called the blanket, which in turn transfers the ink to the surface of the material upon which the image is to be reproduced.
Aluminum has been used for many years as a support for lithographic printing plates. In order to prepare the aluminum for such use, it is typical to subject it to both a graining process and a subsequent anodizing process. The graining process serves to improve the adhesion of the subsequently applied radiation-sensitive coating and to enhance the water-receptive characteristics of the background areas of the printing plate. The graining affects both the performance and the durability of the printing plate, and the quality of the graining is a critical factor determining the overall quality of the printing plate. A fine, uniform grain that is free of pits is essential to provide the highest quality performance.
Both mechanical and electrolytic graining processes are well known and widely used in the manufacture of lithographic printing plates. Optimum results are usually achieved through the use of electrolytic graining, which is also referred to in the art as electrochemical graining or electrochemical roughening, and there have been a great many different processes of electrolytic graining proposed for use in lithographic printing plate manufacturing. Processes of electrolytic graining are described, for example, in U.S. Pat. No. 3,755,116, U.S. Pat. No. 3,887,447, U.S. Pat. No. 3,935,080, U.S. Pat. No. 4,087,341, U.S. Pat. No. 4,201,836, U.S. Pat. No. 4,272,342, U.S. Pat. No. 4,294,672, U.S. Pat. No. 4,301,229, U.S. Pat. No. 4,396,468, U.S. Pat. No. 4,427,500, U.S. Pat. No. 4,468,295, U.S. Pat. No. 4,476,006, U.S. Pat. No. 4,482,434, U.S. Pat. No. 4,545,875, U.S. Pat. No. 4,545,875, U.S. Pat. No. 4,548,683, U.S. Pat. No. 4,564,429, U.S. Pat. No. 4,581,996, U.S. Pat. No. 4,618,405, U.S. Pat. No. 4,735,696, U.S. Pat. No. 4,897,168 and U.S. Pat. No. 4,919,774.
In the manufacture of lithographic printing plates, the graining process is typically followed by an anodizing process, utilizing an acid such as sulfuric or phosphoric acid, and the anodizing process is typically followed by a process which renders the surface hydrophilic such as a process of thermal silication or electrosilication. The anodization step serves to provide an anodic oxide layer and is preferably controlled to create a layer of at least 0.3 g/m.sup.2. Processes for anodizing aluminum to form an anodic oxide coating and then hydrophilizing the anodized surface by techniques such as silication are very well known in the art, and need not be further described herein.
Included among the many patents relating to processes for anodization of lithographic printing plates are U.S. Pat. No. 2,594,289, U.S. Pat. No. 2,703,781, U.S. Pat. No. 3,227,639, U.S. Pat. No. 3,511,661, U.S. Pat. No. 3,804,731, U.S. Pat. No. 3,915,811, U.S. Pat. No. 3,988,217, U.S. Pat. No. 4,022,670, U.S. Pat. No. 4,115,211, U.S. Pat. No. 4,229,266 and U.S. Pat. No. 4,647,346. Illustrative of the many materials useful in forming hydrophilic barrier layers are polyvinyl phosphonic acid, polyacrylic acid, polyacrylamide, silicates, zirconates and titanates. Included among the many patents relating to hydrophilic barrier layers utilized in lithographic printing plates are U.S. Pat. No. 2,714,066, U.S. Pat. No. 3,181,461, U.S. Pat. No. 3,220,832, U.S. Pat. No. 3,265,504, U.S. Pat. No. 3,276,868, U.S. Pat. No. 3,549,365, U.S. Pat. No. 4,090,880, U.S. Pat. No. 4,153,461, U.S. Pat. No. 4,376,914, U.S. Pat. No. 4,383,987, U.S. Pat. No. 4,399,021, U.S. Pat. No. 4,427,765, U.S. Pat. No. 4,427,766, U.S. Pat. No. 4,448,647, U.S. Pat. No. 4,452,674, U.S. Pat. No. 4,458,005, U.S. Pat. No. 4,492,616, U.S. Pat. No. 4,578,156, U.S. Pat. No. 4,689,272, U.S. Pat. No. 4,935,332 and EP-A 0 190 643.
The result of subjecting aluminum to an anodization process is to form an oxide layer which is porous. Pore size can vary widely, depending on the conditions used in the anodization process, but is typically in the range of from about 0.1 to about 10 .mu.m. The use of a hydrophilic barrier layer is optional but preferred. Whether or not a barrier layer is employed, the aluminum support is characterized by having a porous wear-resistant hydrophilic surface which specifically adapts it for use in lithographic printing, particularly in situations where long press runs are required.
A wide variety of radiation-sensitive materials suitable for forming images for use in the lithographic printing process are known. Any radiation-sensitive layer is suitable which, after exposure and any necessary developing and/or fixing, provides an area in imagewise distribution which can be used for printing.
Useful negative-working compositions include those containing diazo resins, photocrosslinkable polymers and photopolymerizable compositions. Useful positive-working compositions include aromatic diazooxide compounds such as benzoquinone diazides and naphthoquinone diazides.
Lithographic printing plates of the type described hereinabove are usually developed with a developing solution after being imagewise exposed. The developing solution, which is used to remove the non-image areas of the imaging layer and thereby reveal the underlying porous hydrophilic support, is typically an aqueous alkaline solution and frequently includes a substantial amount of organic solvent. The need to use and dispose of substantial quantities of alkaline developing solution has long been a matter of considerable concern in the printing art.
Efforts have been made for many years to manufacture a printing plate which does not require development with an alkaline developing solution. Examples of the many patents and published patent applications relating to such prior efforts include: U.S. Pat. No. 3,506,779 (Brown et al), U.S. Pat. No. 3,549,733 (Caddell), U.S. Pat. No. 3,574,657 (Burnett), U.S. Pat. No. 3,793,033 (Mukherjee), U.S. Pat. No. 3,832,948 (Barker), U.S. Pat. No. 3,945,318 (Landsman), U.S. Pat. No. 3,962,513 (Eames), U.S. Pat. No. 3,964,389 (Peterson), U.S. Pat. No. 4,034,183 (Uhlig), U.S. Pat. No. 4,054,094 (Caddell et al), U.S. Pat. No. 4,081,572 (Pacansky), U.S. Pat. No. 4,334,006 (Kitajima et al), U.S. Pat. No. 4,693,958 (Schwartz et al), U.S. Pat. No. 4,731,317 (Fromson et al), U.S. Pat. No. 5,238,778 (Hirai et al), U.S. Pat. No. 5,353,705 (Lewis et al), U.S. Pat. No. 5,385,092 (Lewis et al), U.S. Pat. No. 5,395,729 (Reardon et al), EP-A-0 001 068, EP-A-0 573 091.
Lithographic printing plates designed to eliminate the need for a developing solution which have been proposed heretofore have suffered from one or more disadvantages which have limited their usefulness. For example, they have lacked a sufficient degree of discrimination between oleophilic image areas and hydrophilic non-image areas with the result that image quality on printing is poor, or they have had oleophilic image areas which are not sufficiently durable to permit long printing runs, or they have had hydrophilic non-image areas that are easily scratched and worn, or they have been unduly complex and costly by virtue of the need to coat multiple layers on the support.
The lithographic printing plates described hereinabove are printing plates which are employed in a process which employs both a printing ink and an aqueous fountain solution. Also well known in the lithographic printing art are so-called "waterless" printing plates which do not require the use of a fountain solution. Such plates have a lithographic printing surface comprised of oleophilic (ink-accepting) image areas and oleophobic (ink-repellent) background areas. They are typically comprised of a support, such as aluminum, a photosensitive layer which overlies the support, and an oleophilic silicone rubber layer which overlies the photosensitive layer, and are subjected to the steps of imagewise exposure (usually in the infrared region) followed by development to form the lithographic printing surface.
It is also known to use various non-planar surfaces for lithographic printing. For example, instead of mounting a flat plate around a printing press cylinder, the cylinder itself can be made of a suitable material for printing. Alternatively, a printing "sleeve" having a printing surface can be fitted around a metal core. Printing cylinders and sleeves having a porous ceramic printing surface are described, for example in U.S. Pat. No. 5,293,817 (Nussel et al). These porous ceramic materials provide an interconnected network that carries dampening fluid from the inside of the cylinder to the printing surface.
U.S. Pat. No. 5,317,970 (Nussel et al), U.S. Pat. No. 5,454,318 (Hirt et al), U.S. Pat. No. 5,555,809 (Hirt et al) and EP-A-0 693 371 (Nussel et al), all disclose various ceramic printing cylinders and sleeves for wet lithography, whereby an oleophilic material is imagewise deposited on the printing members to provide ink accepting image areas.
While such materials have advantages in certain instances, there is a need for printing cylinders and/or sleeves that have high density mechanical strength (that is, they have greater fracture toughness) and do not require the use of deposited oleophilic materials as in the art in the preceding paragraph. Moreover, there is a need for greater image quality than is achievable with porous ceramic surfaces.

Zirconia alloy cylinders and sleeves for imaging and lithographic printing methods


Pump apparatus having a wear end and a pump end is provided with means for preventing fluid being pumped from entering the wear end. An internal pump is positioned between the wear end and the pump end of sealless pumps to direct small quantities of fluid from the wear end to the pump end at a pressure which prevents fluid in the pump end to pass into the wear end.

This invention relates to a pumping apparatus having a wear end and a pump end having an internal pumping means to prevent fluid in the pump end from entering the wear end. More particularly, this invention relates to a sealless pumping apparatus having a pump end and a wear end wherein a rotor portion of the wear end is sealed from the environment around the wear end and wherein an internal pumping means is provided to prevent fluid in the pump end from entering the wear end.
Pumps generally include a pump end where incoming liquid is pressurized for subsequent recovery through an outlet and a wear end where the parts subject to wear such as bearings, shaft, thrust washers, driven magnet or the like are located. Pumps of all types, including centrifugal, gear or screw pumps rely on a seal or a magnetic drive or a canned motor design in order to minimize leakage from the pump. The relatively simple designs of the sealed pumps have a seal which will wear and, therefore, eventually leak.
In canned motor design pumps and magnetic drive pumps, the rotor portion of the pump is separated and sealed from the stator portion of the pump or the drive magnet portion, respectively by means of a seal known as a can, lining or shell. The can prevents fluid in the rotor portion from contacting the environment. Since a rotating shaft does not rotate through the can, there is no need to provide a seal between the can and environment. The can portion of the pump is formed of a metallic composition to render it resistant to a variety of liquids being pumped, particularly hydrocarbon compositions and corrosive liquids. However, the type of liquids that can be pumped also is limited such as acidic compositions which degrade the can metallic composition, slurries, the solid portion of which rapidly deteriorate the wear end and hot liquid composition which also deteriorate the wear end. In the case of slurries, it has been proposed to utilize a screen or a filter between the pump end and the wear end to eliminate contact between the solid portion of the slurry and the wear end. The use of filter screens is undesirable since they become rapidly plugged thereby depleting the wear end of needed heat exchange and lubricating liquid. In addition, in magnetic drive pumps, the use of metallic cans creates eddy current losses which consume energy and which produce undesirable heat that must be removed from the wear end. In addition, since presently available canned motor pumps and magnetic drive pumps rely upon the liquid being pumped to effect lubrication and heat removal in the wear end, they cannot be run dry accidently without destroying the pump. With either of the magnetic drive or canned motor sealless pump designs, the units do not have seals but they do have internal bearings and thrust washers and shafts which depend on the fluid being pumped for lubrication. Accordingly, these parts will wear over time as well. In the event that the liquid being pumped is non-lubricating, abrasive or crystalline or very hot or cold, the bearings, washers and shafts can be damaged quickly and render the pumps either too expensive or impractical to repair.
U.S. Pat. No. 4,290,611 discloses a pumping seal utilizing a plate having spiral grooves as a pump. U.S. Pat. No. 5,090,712 discloses a pumping seal having an alternative discontinuous grooved surface.
Some designs provide clean pressurized liquid to the wear end and allow it to flow through a bushing into the pump end. Said designs require a flow as low as 0.6 gallon per minute which makes the design impractical and said flows will increase as the throttle bushing wears. Further, the use of a throttle bushing does not prevent liquid from entering the wear end when the pump is idle and therefore aggravates wear in the wear end resulting in limited durability. By contrast, this invention permits flows of as low as 0.4 gallons per day and seals the wear end from the pump end when the pump is idle.
Accordingly, it would be desirable to provide a pump which prevents the fluid being pumped from entering a wear end of a pump. This will allow the use of the pump in slurries, low viscosity or thin liquids, high temperatures, afford "run dry" protection and greatly extend the life of the wear end. It would also be desirable to provide a magnetic drive pump which can utilize a nonmetallic can in order to avoid eddy current loss but removes the negative aspects of the nonmetallic can being the only seal to the environment.