A method is for monitoring interaction between a person and his companion and pet. The method can be realized via a data transfer network, a monitoring arrangement used in the method, a server and a computer program to be used in the monitoring arrangements, which are included in the monitoring arrangement. With the method and monitoring arrangement, an interactive event between the companion and person and/or pet can be visualized on a data processing device for a selected time period. The data processing device can be situated in a different location than the persons and pet being monitored. In the method, the latest 3D location measuring data and physiological measuring data of the pet, companion and person are compared to long-term average data. The physiological measuring data is received from wireless monitoring devices carried by the pet, companion and person.

The elderly portion of the population grows quickly in industrialised countries. An elderly person often lives in a place, where relatives or friends do not have time to visit sufficiently often in order to evaluate the health and functional ability of the person. In such a case the worry of the relatives and friends for how the person they are close to manages in their daily routines can be great.
In order to eliminate such a situation, various computerised solutions have been developed, by using which the daily activities of a person or several persons can be monitored on a rough level. The apartment, which a person uses, can for example be equipped with various door or room sensors, which indicate the use of the door or the movement of the person inside the room. Thus the person's movement can be discovered over a certain time period. If no signals regarding the person's movement are received from the sensors either at a certain time or at certain time intervals, the arrangement provides an alarm, which is relayed through a data network. Examples of such monitoring systems are shown in the patents JP 2007299121 and CN 101324662.
Solutions are also known, wherein the person has a device for example on his or her wrist, which device monitors vital functions or which can be used to send an alarm to an external person in situations, where the person feels that his or her ability has weakened. The alarm can be sent for example via radio, telephone or the internet.
Owning and caring for pets also continuously becomes more common. Caring for pets is an element, which counterbalances the daily hustle for a busy human. The presence of a pet has also been shown to be beneficial for a human's mental welfare and even to lower the blood pressure. Doing things with a pet maintains both the physical and mental fitness of a person.
Various pet monitoring and controlling means functioning via data networks are known. Especially the emergence and development of the internet as a central communication channel has made the development of various pet monitoring and controlling systems easier. With such monitoring and controlling means the behaviour of a pet can be monitored in real-time either via video image or an audio dispatch also when outside the home. From the video images and/or the sounds of the pet one can deduce in what kind of activity state the pet is at that exact moment.
The movement and recreation of the pet can also be monitored in real-time via a data network. The locationing of the pet in the home can be implemented for example with video surveillance, RFID identifier readers, GPS, infrared sensors, acoustic locationing methods, ultrasound locationing, radio locationing or calculation of the location based on acceleration measurement.
At least part of the monitoring of the daily activities of the pet can be given over to a suitably programmed home computer. In such a system a computer in the home simulates the owner during at least a part of the day. One such arrangement is depicted in application publication US 2006/0011144. The depicted arrangement comprises real-time positioning of a pet (dog) with various methods, control of the food and drink dispensers, monitoring of the activity state of the dog with an acceleration sensor (in its place or moving), monitoring of the body temperature of the dog, monitoring of the barking of the dog, creating various scent, sound and picture animations depicting the owner and showing them to the dog. If an activity model, which differs from the normal, can be observed in the activity of the dog at a certain time, the computer sends an alarm regarding the matter to the dog owner. The solution shown in the reference publication can thus give an alarm, if the activity of the dog momentarily differs sufficiently from activity models stored in the memory of the computer.
The arrangement shown in reference publication US 2006/0011144 cannot make conclusions in situations, where the activity of a dog surprisingly changes, even if the activity stays within normal limits, but the movement of the dog still changes either temporarily or little by little to differ completely from the normal movement. For example the dog moves as much as before, but the movement area has changed from the usual. One possibility of the movement of the pet changing in the described manner is a sudden change in the functional ability of a person in the apartment, such as for example a sudden illness.

Method and arrangement for evaluating activity and functional ability based on interaction and physiological signals


A transparent conductive layer is made of a graphene transparent conductive material and is in the form of a thin film having a thickness of 0.36 nm-10 nm, transmittance of visible light being 80-97%, and surface resistance being 30-500Ω/□. A CF substrate includes the graphene transparent conductive layer to replace and ITO transparent conductive layer in order to obtain an electrode or a static electricity draining layer having high transmittance and excellent flexibility and, when used in a liquid crystal display panel, helps improve the transmittance of the liquid crystal panel and reduce the use of backlighting. Also provided is a manufacturing method of the CF substrate having the graphene transparent conductive layer, which uses a CVD process to form graphene on a growth substrate to be subsequently transferred to a CF substrate body.

1. Field of the Invention
The present invention relates to the field of liquid crystal displaying, and in particular to a graphene transparent conductive layer and a CF (Color Filter) substrate having the conductive transparent layer and a manufacturing method thereof.
2. The Related Arts
Heretofore, a commonly used transparent conductive material is a metal oxide mixed transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), and aluminum-doped zinc oxide (AZO), among which the most commonly used one is the ITO transparent conductive material that has a light transmittance as high as 90%. However, element indium is a rare and expensive metal and the manufacture of ITO film requires high degree of vacuum and a relatively high temperature. The ITO film so obtained is brittle, making it difficult to make a flexible electrode. These limit further development of the ITO transparent conductive material.
Recently, researches revealed that graphene is novel carbon based material having a two-dimensional honeycomb structure formed by a single layer of densely packed carbon atoms. Graphene is the thinnest but hardest nanometer material that is currently known and is almost perfectly clear, absorbing 2.3% of light and having an electric resistivity of around 10−6Ω·cm, which is lower than that of copper or silver, making it a material of lowest electric resistivity that is currently known, and can be manufactured by various processes, such as chemical vapor deposition (CVD), micro-machine exfoliation, and epitaxial growth. Since graphene has an electrical conductivity that matches ITO and has a light transmittance as high as 97% and also since graphene has mechanical strength and flexibility both superior to the ITO transparent conductive material, graphene can be used completely in place of ITO in making a transparent conductive electrode or conductive layer. Further, graphene made with a CVD process is of low manufacture cost, requiring no high temperature and high pressure, and the technique for transferring graphene so manufactured to a substrate to serve as a transparent electrode or a transparent conductive layer is getting mature. Compared to the ITO transparent conductive materials, graphene has a wider and more prosperous future in flexible displaying.
It is thus desired to provide a graphene transparent conductive layer having various parameters that are all suitable to replace the ITO transparent conductive layer for use in an CF substrate of a liquid crystal display in order to acquire an electrode of a graphene transparent conductive layer having high transmittance and excellent flexibility to accordingly improve the transmittance of a CF substrate of a liquid crystal display panel that uses graphene transparent conductive material and reduce the use of backlighting.

Transparent conductive layer and CF substrate having same and manufacturing method thereof

Shenzhen China Star Optoelectronics Technology Co., Ltd


Devices, methods, and kits for detecting at least two analytes present within a small volume single fluid sample obtained from patient for the creation of a multiplexed panel of the various analytes present within the single fluid sample are disclosed.

Numerous devices and methods exist for detecting analytes that may be present in a fluid sample. However, the currently employed devices and methods require the use of multiple fluid samples and/or aliquots of a single fluid sample for the detection of analytes present in such sample(s). Such devices and methods require a large volume of the fluid sample, the collection of multiple fluid samples from a patient in order to achieve analyte detection, and/or result in fluid sample loss/reduction due to multiple aliquots being taken from the fluid sample for analyte detection. Accordingly, a need exists for new and improved devices and methods of high sensitivity that allow a small volume of a single fluid sample obtained from a patient to be re-used in order to detect at least two analytes present in the single fluid sample. Such devices and methods thereby allow for the creation of a multiplexed panel associated with the various analytes present in the single fluid sample. It is to such devices and methods, as well as kits related thereto, that the presently disclosed and claimed inventive concept(s) is directed.

Devices, methods, and kits for multiplexing a fluid sample via fluid sample reuse


An agricultural harvesting machine, such as a forage harvester comprises a set of feedrolls (20, 21, 26, 27) for feeding harvested crop material to a rotating cutterhead (36). The feedrolls are driven by a hydraulic drive means comprising a hydrostatic pump (123) coupled to the engine (70) of the harvesting machine, a hydrostatic motor (80) coupled to said feeder means (20, 21, 26, 27) and hydraulic circuitry (142, 143, 152) interconnecting the pump and the motor. The circuitry comprises a feeder arrest valve (165) which is operable to interrupt the oil flow from said hydrostatic motor (80), thereby arresting said feedrolls (20, 21, 26, 27). The hydrostatic motor (80) is provided with a flushing valve (156) for diverting part of the oil flow in said circuitry through said motor for lubricating and cooling the latter. The arrest valve (165) is provided in said circuitry (142, 143, 152) between the hydrostatic motor (80) and the flushing valve (156). This arrangement allows for an immediate and efficacious arresting of the feedrolls upon detection of a foreign object in the harvested crop.

It is well known in the art to provide agricultural harvesting machines, such as forage harvesters, with an apparatus for detecting foreign material in the stream of crop material which is being fed to a crop processing unit, such as a rotating cutterhead co-operating with a stationary shear bar. Such detector apparatus may be a metal detector of the type described in EP-B-0,102,665. The signal generated by this detector is fed to feeder arrest means, which provoke an immediate stop of the means feeding the crop material to the cutterhead. Thus is prevented that stray metal objects, which were picked up from the field, reach the cutterhead and cause serious damage to the knives and the shear bar. The arrest system also prevent that smaller metal particles are comminuted by the cutterhead and mixed with the crop which is fed to the cattle.
Typical mechanical arrest means as disclosed by U.S. Pat. No. 5,921,071 and U.S. Pat. No. 4,296,591 comprise a ratchet wheel which is mounted to the drive line of the feedrolls of the feeder means and a pawl which is positioned to engage this ratchet upon detection of metal. The movement of the pawl is controlled by a solenoid which is operated by the foreign material detector. Actuation of the pawl has to be combined with the simultaneous deactivation of a clutch in the drive line of the feedrolls to prevent damage to the engine or components of the drive line.
The use of such clutch is not required when the feeder means are driven by a hydrostatic motor as described in EP-A-0,848,902. The hydraulic circuitry then may be equipped with an arrest valve which is operable to cut the oil flow to or from the motor upon detection of a foreign object as suggested by FR-A-2,173,352. Such systems may work satisfactorily when used on the former low capacity forage harvesters. However, it has been experienced that serious problems as to reaction. speed and life time emerged when such systems are applied to the present-day high capacity harvesters in which the rotating feedrolls have a greater kinetic energy. Especially the low reaction time is critical as the foreign object may have the time to reach the cutterhead.
It therefore is an object of the present invention to provide a drive and arrest system for the feeder means which, on the one hand, does not require a clutch which has to be disengaged upon detection of a foreign object, and, on the other hand, is sufficiently powerful and fast to halt the crop flow before the foreign object reaches the crop processing means, even on larger harvesters.


A duplexer package comprises two surface acoustic wave filter chips having different band center frequencies and a phase matching circuit for matching the phases of the two SAW filter chips, the filter chips and the phase matching circuit being accommodated in one unit, wherein the phase matching circuit is formed in a layer providing a cavity for the filter chips, the layer defining the cavity being located above a face for mounting the surface acoustic wave filter chips. According to the present invention, the height of the duplexer package can be lowered.

1. Field of the Invention
The present invention relates to duplexer packages and more particularly, to duplexer packages using surface-acoustic-wave (SAW) band-pass filters.
2. Description of Related Art
In recent years, down-sized versions of mobile communication apparatuses typified by handy phones have been rapidly developed and, therefore, the parts for use therein have been desired to have a smaller size and higher performance. In mobile communication apparatuses, duplexers are used to separate or generate signals.
While most of the duplexers comprise band-pass filters using dielectrics, band-rejection fillers or a combination of these filters, duplexers using SAW filters are now under research and development for further down-sizing and higher performance.
The duplexer separates two surface acoustic waves having different pass bands to prevent the interference between the two surface acoustic waves. A duplexer comprising two SAW band-pass filter chips should be designed so as to prevent or reduce the interference of the filter characteristics of the two SAW band-pass filter chips with each other. To this end, the two SAW band-pass filter chips are each provided with a phase matching circuit, or at least one of the two SAW band-pass filter chips is provided with a phase matching circuit.
The phase-matching circuit may be placed in a multilayer ceramic package together with the filter chips to form a small duplexer package of about 2.4 mm in height.
In usual, the two filter chips included in the duplexer have different center band-pass frequencies (e.g., 836 MHz and 881 MHz). The filter chips characteristically show a small attenuation in the respective pass bands, and a large attenuation in the respective rejection bands so that the level of a signal becomes low.
It is also necessary to prevent the deterioration of the filter characteristics of the two filter chips when used in the duplexer. For this purpose, ideally, the impedance of each of the filter chips is infinity and the reflection coefficient thereof is about 1 in the pass band of the other filter chip.
For attaining the above characteristics, the phase matching circuit is connected to the filter chip. The phase matching circuit is generally formed of a strip-line, a condenser (C) or a inductance (L), the latter two being discrete devices.
In the phase matching circuit formed of the strip-line, the resistance increases proportionally to the length of the strip line. the increase in resistance may cause a signal transmission loss and increase in stray capacitance in a distribution constant.
The increase in the stray capacitance influences the phase circuit constant and the like to change the characteristics. Such influence is known to become greater specially as a higher frequency is used and as the material for packaging the duplexer is higher in dielectric constant.
To avoid this influence, a material having a low dielectric constant (e.g., alumina ceramic or glass ceramic) is used for the package and a conductor having a low resistance (e.g., tungsten) is used for the phase matching circuit.
When the discrete chip L or C is used, the constant of the phase matching circuit is not influenced much. However, due to the accuracy of the chip, delicate adjustment in phase matching is difficult. Further, since the size of the chip is large, the duplexer becomes of considerable height.
An example of a conventional duplexer comprising two SAW filter chips of band-pass type will hereinafter be described.
FIG. 12 is a block diagram illustrating the circuit construction of a conventional duplexer formed in a package. Referring to FIG. 12, the reference alphanumerics F1 and F2 denote SAW filter chips. Phase matching circuit P1 and P2 are inserted to prevent the interference of the filter characteristics of the filter chips.
Terminals T1 and T1' are common signal terminals, terminals S1 and S1g and terminals S2 and S2g are input/output terminals for separated signals. One of each of the above pairs of terminals (e.g., T1', S1g, and S2g) is connected to ground (GND).
Usually, the SAW filters F1 and F2 and the phase matching circuits P1 and P2 are accommodated in a multilayer ceramic package.
FIGS. 13 to 17 are schematic sectional views and perspective views showing the construction of conventional duplexer packages. Referring to FIG. 13, externally connecting terminal section 101 is located in the lowermost layer of the package, which corresponds to the terminals T1, S1 and S2 in FIG. 12.
A phase matching circuit 100 made of tungsten or the like is buried in an insulating layer 103.
In the duplexer shown in FIG. 13, the phase matching circuit 100 is inserted only between the filter F1 and the terminal T1.
One end of the phase matching circuit 100 is connected to the common signal terminals T1 in the lowermost layer via a through-hole and the other end is connected to the filters F1 and F2 via a through-hole. The filters F1 and F2 are disposed on a die-attach layer 102 serving as a face for mounting the filter chips, and are connected to a bonding terminal layer 104 via a wire 107.
The bonding terminal layer 104 is located on the surface of a layer 105 defining a cavity (hereafter referred to as a cavity layer), the surface being at the same height as the top surface of the filters, and is connected to the signal terminals S1 and S2 in the lowermost layer via an end portion of the package. The die-attach layer 102 is provided with a ground (GND) pattern, and the filters F1 and F2 are disposed on the GND pattern. On the uppermost layer, a cap 106 is disposed as a hermetic seal.
Referring to FIG. 14 showing a perspective view of the duplexer package shown in FIG. 13, the phase matching circuit 100 is formed in a layer 7. Via through-holes, an end of the phase matching circuit 100 is connected to the terminal S1' in the cavity layer 105 and the other end is connected to the terminal S2' and the terminal T1 which is located in the lowermost layer. The surface of a layer 5 is the die-attach layer, on which the filter chips F1 and F2 is disposed.
A ground (GND) layer is formed on the surface of a layer 9 and connected to GNDs in a layer 2 and a layer 6 via a through-hole and an end portion of the package.
The size of the conventional duplexer package as shown in FIGS. 13 and 14 is about 7.5 (length).times.8.5 (width).times.2.4 (height) mm.
FIG. 15 is a perspective view illustrating a conventional duplexer package wherein the phase matching circuits 100 are inserted both on a layer 7 and on a layer 8 between the filters F1, F2 and the common signal terminal T1.
Difference from the conventional duplexer package as shown in FIG. 14 lies in that the layer 8 on which the phase matching circuit 100 is formed is added. Due to the addition of the layer 8, this duplexer package is about 0.35 mm higher than that shown in FIG. 14 (2.4 mm).
FIGS. 16 and 17 show a conventional duplexer package of upside-down construction with respect to the construction shown in FIG. 13, in which the phase matching circuit 100 is formed above the die-attach layer. Compared with the duplexer package shown in FIG. 13, the insulating layer 103 can be omitted in this construction, and therefore the size of the duplexer package is about 8.5 (length).times.9.5 (width).times.1.6 (height) mm.
However, the phase matching circuit 100 disposed on the top, as it is, is ready to be affected by external radiant noise.
Accordingly, if a signal line such as GND lies close to the phase matching circuit 100, the characteristic impedance of the phase matching circuit changes and the device characteristics deteriorate. Therefore a certain space is necessary.
Conventionally, the duplexer package having the construction as shown in FIG. 16 is employed with a space of 0.6 mm or more provided above the phase matching circuit 100. After all, this duplexer package occupies the height of 2.2 mm or more in use.
As previously mentioned, the down-sizing of the parts is highly demanded for small-sized communication apparatuses, and especially there is much more need for "the lowering the part height."
The duplexer package of multilayer construction with the buried pattern of the phase matching circuit as shown in FIG. 13 can reduce the adverse effect of the filters on each other's characteristics, but it is difficult to further down-size the duplexer package or lower the height thereof because a considerable number of layers are necessary.
Also, in the construction shown in FIG. 16, since a space of a certain height is required above the duplexer package, there is a limit to the lowering of the height. Further there is a strong possibility that the filter characteristics are adversely affected by external noise.


Video processing apparatus in which input images of an input video sequence are processed according to user adjustable video effects parameters to generate output images of an output video sequence comprises: rendering means for rendering images of the output video sequence according to a priority order of:

1. Field of the Invention
This invention relates to image processing and rendering.
2. Description of the Prior Art
In image processing systems such as video special effects systems, once a particular effect has been selected and all the parameters defined, a xe2x80x9crenderingxe2x80x9d operation has to take place.
Rendering is the process of generating an output image, a series of images forming an output video sequence, or an intermediate data type such as a motion vector or position value, according to the processing operation which has been set up. For example, a lighting effect might involve the user selecting a source and a destination position for a computer-generated spotlight to be applied to a video sequence. Once these positions have been defined, the next task is to render each image in the output sequence by applying the defined lighting effect to determine the colour and luminance of each pixel of each output image.
With current processing systems, rendering can be very time consuming, typically taking between a few seconds and many hours (depending on the sequence length) to render each image of a video sequence. To avoid inconvenient delays to a user, it is considered desirable not to initiate a rendering process whenever a processing parameter is changed by a user, but instead to wait until the user is happy with all the parameters that have been changed. However, this does not give the user a direct response when he changes a processing parameter.
This invention provides video processing apparatus in which input images of an input video sequence are processed according to user adjustable video effects parameters to generate output images of an output video sequence, the apparatus comprising:
rendering means for rendering images of the output video sequence according to a priority order of:
(i) an image or images currently displayed for view by a user;
(ii) first and last images of the output video sequence; and
(iii) remaining images of the output video sequence.
The invention addresses the problems described above by providing a rendering operation which renders images or data values of an output video sequence according to a priority order, so that those images which are generally required most quickly by the user are rendered first. This can alleviate the subjective delay involved in a rendering operation. This can alleviate subjective delays and also supports the use of multiple views of different stages of a rendering operation.
It is preferred that the user should be able to continue to operate the apparatus during a rendering operation, thus alleviating part of the problem with previous apparatus (where a lengthy rendering operation could make the apparatus temporarily unusable). It is therefore preferred that the rendering means is operable as a background process within the apparatus.
In particular, this may lead to the user changing a parameter being used by a current (background) rendering operation, so it is preferred that the apparatus comprises means for detecting a parameter change by a user which makes a current rendering operation invalid; and means, responsive to such a detected parameter change, for aborting a current rendering operation by the rendering means and for restarting operation of the rendering means. This prevents a waste of processing resources in rendering using out-dated processing parameters.
Preferably the apparatus comprises user-operable sequence selection means for selecting a subset of the input video sequence to be rendered to form the output video sequence. In this way the user can define a range of interest, with only those images in the range of interest being rendered. Particularly during a development of the effects parameters to be used, this can save rendering time.
The invention also provides a video processing method in which input images of an input video sequence are processed according to user adjustable video effects parameters to generate output images of an output video sequence, the method comprising the step of:
rendering images of the output video sequence according to a priority order of:
(i) an image or images currently displayed for view by a user;
(ii) first and last images of the output video sequence; and
(iii) remaining images of the output video sequence.


In a semiconductor storage device, a gate insulating film and a gate electrode are laid on a first conductivity type semiconductor substrate, and charge holding portions are formed on both sides of the gate electrode. Second conductivity type first and second diffusion layer regions are formed in regions of the semiconductor substrate corresponding to the charge holding portions. The charge holding portions are each structured so as to change, in accordance with an electric charge amount held in the charge holding portions, a current amount flowing from one of the second conductivity type diffusion layer regions to the other of the diffusion layer regions through a channel region when voltage is applied to the gate electrode. Part of each charge holding portion is present below an interface of the gate insulating film and the channel region.

Conventionally, there has been a nonvolatile memory capable of storing two bits by one field-effect transistor (e.g., see JP-2001-512290 A, published Aug. 21, 2001). The structure of this nonvolatile memory and the principle of its write (program) operation will be described hereinbelow.
As shown in FIG. 25, this memory is composed of a gate electrode 909 formed on a P type well region 901 through a gate insulating film, and a first N type diffusion layer region 902 and a second N type diffusion layer region 903 formed at the surface of the P type well region 901. The gate insulating film is composed of a so-called ONO (Oxide Nitride Oxide) film in which a silicon nitride film 906 is interposed between silicon oxide films 904 and 905. In the silicon nitride film 906, there are formed memory holding portions 907, 908 in the vicinity of the edge portions of the first and second N type diffusion layer regions 902, 903. An electric charge amount in each of these memory holding portions 907, 908 is read as a drain current of the transistor so that two-bit information is stored in one transistor.
Next description will be given of a write operation method in this nonvolatile memory. The term "write (or program)" is used herein to refer to the action of injecting electrons into the memory holding portion 907, 908. In JP-2001-512290 A, there has been disclosed a method for injecting electrons into a right memory holding portion 908 by applying 5.5V to the second diffusion layer region 903 and 10V to the gate electrode 909. This makes it possible to write to a specific one of the two memory holding portions. There has been also disclosed a method for erasing and reading from a specific side. By combining these methods, two-bit operation is enabled.
In the above-stated nonvolatile memory, in order to provide the gate insulating film with the function of operating the transistor as well as the function as a memory film for storing electric charges, the gate insulating film is formed into three-layer structure with use of the ONO film. This makes it difficult to manufacture thinner gate insulating films. Also, in the above nonvolatile memory, as the channel length is shortened, the two memory holding portions 907, 908 in one transistor interfere with each other, which makes two-bit operation difficult. This obstructs further miniaturization of the devices.

Semiconductor storage device having a function to convert changes of an electric charge amount to a current amount


A method of forming a film on a substrate by plasma CVD, comprising the steps of: providing a discharge tube in a vacuum chamber; providing a partition wall around the discharge tube; evacuating space between the discharge tube and the partition wall to vacuum; providing the substrate at a position confronting the discharge tube; and effecting plasma discharge in the discharge tube.

The present invention relates to a plasma CVD (chemical vapor deposition) film forming method of forming a plasma-polymerized film and a diamondlike carbon film acting as a protective film for a metallic thin film type magnetic recording medium, an insulating film for semiconductor and liquid crystal, an amorphous silicon film acting as a photoelectric conversion element, a superconducting thin film, etc., which not only minimizes film forming defects but greatly increases the adhesive strength of the films themselves.
For forming a thin film by plasma CVD, a method is known in which the interior of a vacuum chamber is occupied by discharge space. However, this known method has a serious problem for industrial in that defects are produced on the thin film itself due to contamination of not only a base on which the thin film is formed, but also an inner face of a wall of the vacuum chamber. In order to solve this problem, a countermeasure in which a discharge tube is provided in the vacuum chamber is disclosed in, for example, Japanese Patent Publication No. 63-26195 (1988) or Japanese Patent Laid-Open Publication No. 63-118074 (1988). Furthermore, another countermeasure in which an ultra-low temperature panel is provided in the vacuum chamber is proposed in, for example, Japanese Patent Laid-Open Publication No. 4-248125 (1992). By employing these countermeasures, contamination of the interior of the vacuum chamber is substantially eliminated.
However, in the prior art methods referred to above, inconveniences are encountered, owing to the influence of unreacted gas leaking from the discharge tube, in that the adhesive strength of the formed thin film, relative to the base, is weak, and the reliability of the protective film or the insulating film, for example its durability, corrosion resistance, etc., are poor. Meanwhile, defects resulting from slight abnormal discharges due to sudden pressure change between the discharge tube and the interior of the vacuum chamber are produced on the film itself.
More concretely, in case the magnetic recording medium is a tape, its corrosion resistance drops and its dropout increases. Meanwhile, when the magnetic recording medium is a magnetic disk, its CSS (contact-start-and-stop) characteristics are not sufficient. Furthermore, when the magnetic recording medium is a photoelectric conversion element, such problems arise that its conversion efficiency drops with time and reliability of the insulating film for semiconductor or liquid crystal drops.

Matsushita Electric Industrial Co., Ltd.


A high-pressure phase boron nitride-based high-hardness high-strength sintered body for cutting tools represented by a milling tool and an end mill etc., which is improved in wear resistance and chipping resistance, is obtained. The high-pressure phase boron nitride-based sintered body according to the present invention comprises a plurality of grains (1) of high-pressure phase boron nitride and a binder phase (2, 3), and the content of the aforementioned grains (1) is at least 20.0 volume % and not more than 99.7 volume %. The aforementioned binder phase (2, 3) includes a first binder phase (2) enclosing the aforementioned grains (1) and a second binder phase (3) other than that. The first binder phase (2) consists of the form of at least either a nitride of at least one of Ti, TiAl, Zr and Hf or a solid solution thereof. The aforementioned second binder phase (3) includes a grain growth suppressive binder phase (4) between a plurality of the aforementioned grains (1) enclosed with the aforementioned first binder phase (2).

High-pressure phase boron nitride represented by cubic boron nitride (hereinafter referred to as cBN) is the next high-hardness material to diamond, and its reactivity with a ferrous material is low as compared with diamond, and hence cBN-based sintered bodies are used for various cutting tools.
Further, a material which is of high hardness and high strength is earnestly desired not only in a cutting application but also in various applications such as a wear-resistant part provided on a sliding part and a shock-resistant part employed for a defensive wall, for example. In a conventional high-pressure phase boron nitride-based sintered body, however, there has been a problem in compatibility of hardness and strength, and no sufficient performance has been attained.
At this point, cBN is a typical non-sinterable material ranking with diamond, and is a high-pressure stable phase. Therefore, extreme sintering conditions of 2000.degree. C. and at least 8 GPa are required, in order to sinter cBN grains. Therefore, cBN grains cannot be bonded to each other under industrial sintering conditions of 1450.degree. C. and not more than 4.5 GPa. Therefore, it is necessary to sinter cBN powder and binder powder after mixing, in order to prepare a cBN-based sintered body under industrial sintering conditions. Powder of Al, Ti Al, Ti Al.sub.3, TiN or TiC is employed as this binder powder. And, cBN-based sintered bodies industrially produced by employing a binder (hereinafter referred to as an Al-based binder) consisting of an Al metal or an intermetallic compound of at least one of Al elements can be roughly classified into the following two types:
It is disclosed in Japanese Patent Laying-Open Gazette No. 55-126581 that a cBN-based sintered body (A) consisting of at least 80 weight % of cBN and a binder phase is obtained by performing sintering while employing cBN grains and Al as starting materials. This is because metallic Al or an intermetallic compound of Al such as Ti Al.sub.3 causes fused Al in a high-temperature state in sintering and promotes formation of neck growth between the cBN grains. At this point, neck growth indicates such a state that the cBN grains are fused or bonded and a continuous mosaic or an alternate material is generated. A cBN-based sintered body having a cBN content of 85 to 90 volume % is worked into a product in practice. The transverse rupture strength of this cBN-based sintered body is about 80 to 100 kgf/mm.sup.2 under a condition of a 4 mm span with a test piece of 6 mm in length, 3 mm in width and 0.4 to 0.45 mm in thickness.
On the other hand, a cBN-based sintered body (B) consisting of about 50 to 80 volume % of cBN and a binder phase is obtained by performing sintering while employing cBN grains, an Al-based binder and a nitride or a carbide of an element of the group 4a, 5a or 6a of the periodic table represented by TiN and TiC and the like or a solid solution thereof (hereinafter referred to as a transition metal nitride or the like) as starting materials. This is because metallic Al or an intermetallic compound of Al such as TiAl.sub.3 causes fused Al in a high-temperature state in sintering, forms reaction products between the cBN grains and grains of the transition metal nitride or the like and between the grains of the transition metal nitride or the like, and forms strong binding. A cBN-based sintered body having a cBN content of about 50 to 80 volume % is worked into a product in practice, as a high-strength cutting tool employed for an intermittent cutting application or the like. The transverse rupture strength of this cBN-based sintered body is about 90 to 110 kgf/mm.sup.2 under a condition of a 4 mm span with a test piece for measurement of 6 mm in length, 3 mm in width and 0.4 to 0.45 mm in thickness.
The theoretical strength of the cBN grains is about 70 GPa when estimated from the Young's modulus. Further, the theoretical strength of the grains of the transition metal nitride or the like is about 20 to 50 GPa. In reality, however, the aforementioned cBN-based sintered body (A) is lower in transverse rupture strength than the aforementioned cBN-based sintered body (B), although the content of the cBN grains having high theoretical strength is high. Namely, the aforementioned cBN-based sintered body (B) is of higher strength than the aforementioned cBN-based sintered body (A) having neck growth between the cBN grains as the main of the bonding form of the constituent grains. Thus, it is understood that the bond strength between the cBN grains and the grains of the transition metal nitride or the like and between the grains of the transition metal nitride or the like is stronger than the bond strength by the neck growth between the cBN grains.
However, the aforementioned cBN-based sintered body (B) is prepared by mixing and charging the Al-based binder, the cBN powder and the transition metal nitride or the like and thereafter sintering the same, as hereinabove described. The Al-based binder has a function of neck-growing the cBN grains, as hereinabove described. In the conventional mixing state, therefore, a region where the cBN grains are in contact with each other through the Al-based binder and a region where the cBN grains are directly in contact with each other and the Al-based binder exists in the vicinity thereof have been present to no small extent. Therefore, a region where the aforementioned cBN grains cause neck growth has been generated in sintering. Consequently, holding power for the cBN grains weakens due to the occurrence of the neck growth also in the aforementioned cBN-based sintered body (B), and there has been such a problem that sufficient wear resistance and chipping resistance have not been exhibited when compared with an ideal cBN-based sintered body.
There are Japanese Patent Laying-Open Gazette No. 58-58247, Japanese Patent Laying-Open Gazette No. 58-60678, Japanese Patent Laying-Open Gazette No. 5-186844 and Japanese Patent Laying-Open Gazette No. 58-61253 as those proposed in order to solve such a problem.
In Japanese Patent Laying-Open Gazette No. 58-58247, there is disclosed a high-toughness boron nitride-based sintered body for cutting and wear-resistant tools comprising cBN or wurtzite boron nitride (hereinafter referred to as wBN) and a binder phase. The aforementioned binder phase consists of a boride and a carbide of at least one of Ti, Hf, Zr and Mo. At least either the aforementioned cBN or wBN is enclosed with the aforementioned boride which is 0.1 to 2 .mu.m in mean thickness.
In Japanese Patent Laying-Open Gazette No. 58-60678, there is disclosed a high-toughness boron nitride-based sintered body for cutting and wear-resistant tools comprising at least either cBN or wBN and a binder phase consisting of a nitride and a carbide of at least one of Ti, Hf and Si. At least either the aforementioned cBN or wBN is enclosed with the aforementioned boride whose mean thickness is 0.1 to 2 .mu.m.
In Japanese Patent Laying-Open Gazette No. 5-186844, further, there is disclosed a sintered body containing high-density phase boron nitride, comprising at least either cBN or wBN and a binder phase consisting of a carbide, a nitride, an oxide or a boride of a metal of the group 4a, 5a or 6a of the periodic table, Al, Si, Fe, Ni or Co, an oxide or a nitride of a rare earth metal or a solid solution thereof, or Fe, Ni and Go. The aforementioned sintered body is obtained by sintering a composite hard phase prepared by coating at least either cBN or wBN with at least one of a nitride and a boride of Ti, Hf, Zr, Mo, Al or Si and a solid solution of these having a mean thickness of 0.5 to 90 nm.
In Japanese Patent Laying-Open Gazette No. 58-61253, further, there is disclosed a high-toughness material boron nitride-based sintered body for cutting and wear-resistant tools, which is of a composition containing at least either cBN or wBN and one or two of Al and an oxide and a nitride of Al. The aforementioned sintered body has such a structure that Al or one or two of Al and an oxide and a nitride of Al whose mean layer thickness is 0.1 to 1 .mu.m encloses at least either the aforementioned cBN or wBN.
In the high-pressure phase boron nitride-based sintered bodies described in the aforementioned Japanese Patent Laying-Open Gazette No. 58-58247, Japanese Patent Laying-Open Gazette No. 58-60678 and Japanese Patent Laying-Open Gazette No. 5-186844 high-pressure phase boron nitride grains of at least either cBN or wBN are coated with binders and sintered. Thus, the cBN grains in the sintered bodies aggregate thereby reducing regions being unsintered and improving wear resistance and chipping resistance.
Further, the sintered body described in Japanese Patent Laying-Open No. 58-61253 is such a one that Al enclosing at least either cBN or wBN counter-diffuses with and is strongly bonded to high-pressure phase boron nitride such as cBN and the oxide and the nitride of Al, thereby improving toughness of the aforementioned sintered body.
Grain growth of the binder phase has been a serious problem in the aforementioned generally proposed high-pressure phase boron nitride-based sintered bodies employing high-pressure phase boron nitride coated with the binders, not to mention the conventional high-pressure phase boron nitride-based sintered body. Namely, even if a high-pressure phase boron nitride-based sintered body having such a structure that high-pressure phase boron nitride grains homogeneously disperse in the aforementioned binder phase is prepared, there has been such a problem that the continuous binder phase causes conversion to coarse grains by grain-growing during sintering and chipping resistance lowers.
In the sintered bodies described in the aforementioned Japanese Patent Laying-Open Gazette No. 58-58247, Japanese Patent Laying-Open Gazette No. 58-60678 and Japanese Patent Laying-Open Gazette No. 5-186844, the binders containing elements such as Al, Ti and Hf coat the high-pressure phase boron nitride grains as at least one selected from nitrides, borides and solid solutions thereof. The aforementioned binders coat the high-pressure phase boron nitride grains as thermally and chemically stable ceramic, and hence bond strength formed between the high-pressure phase boron nitride grains and the grains of the transition metal nitride or the like and between the grains of the transition metal nitride or the like is weak as compared with the Al-based binder causing fused Al in a high-temperature state in sintering. Thus, these have been unsatisfactory in wear resistance and chipping resistance, following harshening of cutting conditions following recent requirement for efficiency increase-high-speeding.
In the sintered body described in the aforementioned Japanese Patent Laying-Open Gazette No. 58-61253, on the other hand, most part of Al remains as metallic Al in an unreacted state after sintering, and hence it has not been practical in such an application that the cutting temperature readily reaches a level exceeding 1000.degree. C. in case of cutting hardened steel or cast iron or the like, since metallic Al is fused.
Further, the wBN grains employed in the aforementioned proposed sintered body are synthesized by an impact compression method, while cBN grains are synthesized by a static compression method. Both of wBN and cBN are high-pressure phase boron nitride, and various physical properties such as hardness, chemical stability and reactivity with the Al-based binder in the grains themselves are substantially equivalent. However, they remarkably differ from each other in existence forms of the grains thereof respectively. Namely, while the cBN grains mainly consist of single crystals, wBN is polycrystalline grains consisting of secondary grains in which primary grains having grain sizes of several 10 nm to several 100 nm are sintered by energy in impact compression. The grain sizes of these secondary grains of wBN reach about several .mu.m.
Even if wBN is coated with the binder, therefore, it comes to that strong bonding through the grains of the transition metal nitride or the like is formed only between primary grains of wBN located on surfaces of the secondary grains of wBN and primary grains of wBN located on surfaces of other cBN grains or other secondary grains of wBN. Consequently, the primary grains of wBN are bonded to each other not through the binder in the interior of the secondary grains of wBN, and it could not be said that the same has sufficient wear resistance and chipping resistance.
The present invention has been proposed in order to solve the aforementioned problems, and aims at providing a high-pressure phase boron nitride-based high-hardness high-strength sintered body for cutting tools represented by a milling tool and an end mill and the like, which is improved in wear resistance and chipping resistance.

High-pressure phase boron nitride base sinter


An electrophotographic photoconductor includes an undercoat layer and a photosensitive layer sequentially provided on a conductive substrate. The undercoat layer is mainly composed of a resin and contains a metal oxide. The resin is provided by mixing and polymerizing raw materials of aromatic dicarboxylic acid in a range of 0.1 to 10 mol %, two or more types of dicarboxylic acid other than the aromatic dicarboxylic acid, two or more types of diamine, and at least one type of cyclic amide compound. The resin exhibits an acid value and a base value each of at most 6.0 KOH mg/g. Advantageously, generation of secondary aggregates in the undercoat layer, which result in image defects such as black spots and fogging on a white field, is suppressed.

1. Field of the Invention
The present invention relates to an electrophotographic photoconductor (hereinafter also simply referred to as "photoconductor"), in particular, to an electrophotographic photoconductor that is used in copiers, facsimile machines, printers, or the like electrophotographic apparatuses.
2. Description of the Related Art
Image formation using an electrophotographic system is diversely applied to copiers, printers, plotters and digital imaging complex machines combining functions of these machines in the office, and recently also to small-sized printers and facsimile machines for personal use. Many types of photoconductors for these electrophotographic apparatuses have been developed since the invention by C. F. Carlson, see U.S. Pat. No. 2,297,691. Photoconductors today generally use organic material.
There is a type of organic photoconductor using organic material which is a functionally separated photoconductor and which consists of an undercoat layer, a charge generation layer, a charge transport layer, and a protective layer that are laminated on a conductive substrate. The conductive substrate is made of aluminum or the like. The undercoat layer can be an anodic oxide film or a resin film. The charge generation layer contains an organic pigment exhibiting the photoconductive property such as phthalocyanines or azo pigments. The charge transport layer contains a molecule having a partial structure that involves hopping conduction of charges, such as a molecule of amine or hydrazone that bonds with conjugated π electrons. Another type of known photoconductor, a single layer type photoconductor, comprises a photosensitive layer exhibiting both charge generating and charge transporting functions and a protective layer that are laminated on an undercoat layer.
Each layer is normally formed, because of mass-production, by dipping and coating a conductive substrate in a coating liquid prepared by dissolving or dispersing a pigment, a charge generation agent, to exhibit a charge generation or light scattering function, and a charge transport agent to exhibit a charge transport function.
In a so-called reverse development process that is primarily employed in recent electrophotographic apparatuses, an exposure light source uses a semiconductor laser or a light emitting diode with an oscillation wave length ranging from 450 nm to 780 nm; digital signals of a picture or characters are transformed into optical signals; the light is irradiated on an electrified photoconductor to form a latent electrostatic image on the photoconductor surface; and the latent image in turn is made visible by toner.
Among charge generation agents, phthalocyanines have been extensively studied as a material for a photosensitive layer because the phthalocyanines have a larger light absorbing capability in the oscillation wavelength region of semiconductor lasers than other charge generation agents and thus exhibit excellent charge generation ability. Known photoconductors use a variety of phthalocyanines having a central atom of copper, aluminum, indium, vanadium, or titanium.
There are two methods for electrifying a photoconductor: a non-contact electrification method by means of corona discharge from a scorotron in which the electrifying member is not in contact with the photoconductor, and a contact electrification method by means of a roller of conductive rubber or a brush of conductive fibers in which the electrifying member is in contact with the photoconductor. The contact electrification method has advantages, compared with the non-contact electrification method, including less generation of ozone because of a shorter discharge distance in the air, lower supply voltage, maintenance-free by virtue of no deposition of contamination on the electrifying member due to discharge, and a homogeneous electrification potential on the photoconductor. These advantages can achieve an electrophotographic device that is compact, low in price, and low in environmental pollution. Therefore, the contact electrification method is the mainstream method in medium to small-sized devices.
In a reverse development process, dark potential corresponds to a white field on an image, and bright potential corresponds to a black field. If the surface of the conductive substrate has structural defects such as significant irregularities or defects involving in inhomogeneity of material such as precipitation of impurities, these defects emerge as image defects such as black spots or fogging in the white field. These image defects can be considered to occur through local drop of the electrified potential at the location of the defects on the conductive substrate at which charge injection takes place into the photosensitive layer from the substrate due to the defects on the substrate. This tendency is particularly significant in electrophotographic devices employing both the reverse development system and the contact electrification system because of direct contact between the photoconductor and the electrifying member.
To address this problem in electrophotographic devices employing contact electrification system, an undercoat layer is generally provided between the conductive substrate and the photosensitive layer. The undercoat layer is composed of, for example, an anodic oxide film of aluminum, a boehmite film, or a resin film of poly(vinyl alcohol), casein, poly(vinyl pyrrolidone), poly(acrylic acid), gelatin, polyurethane, or polyamide. The resin film can contain particles of metal oxide such as titanium oxide or zinc oxide for the purpose of suppressing excessive reflection of exposure light from the substrate and avoiding a poor image due to interference fringes, and for appropriately adjusting the resistivity of the undercoat layer. The anodic oxide film, in particular, is known to give excellent stability of electrical potential under an environment of high temperature and high humidity, as disclosed in Japanese Unexamined Patent Publication No. H5-34964. A copolymerized nylon film is also widely used for an undercoat layer because it can provide a uniform thickness by means of dip coating and exhibits desirable mass-production and low price. International Patent Publication No. WO 85/00437 discloses a photoconductor for rear surface exposure using caprolactam as a component monomer for copolymerized nylon resin.
An undercoat layer currently in use has the problem that the electric properties change remarkably in the environment of operation, especially in an environment of high temperature and high humidity, and the electric resistivity changes due to moisture absorption in the undercoat layer causing fogging in the image. To cope with this problem, Japanese Unexamined Patent Publication No. S63-298251, for example, discloses use of an intermediate layer including a resin layer containing titanium oxide for the purpose of suppressing the environmental dependence. This document, however, only discloses an embodiment using a nylon resin having a special structure. Japanese Unexamined Patent Publication No. 2003-287914, discloses use of an intermediate layer including a polyamide resin of special structure to improve resistance to moisture. The document, however, fails to disclose an aromatic ring in the dicarboxylic structure in the component monomer and does not mention an effect from adding a monomer of aromatic dicarboxylic acid.
There is a further cause of image defects including black dots and fogging in a white field, that is, aggregation of metal oxide used in the undercoat layer. The aggregate, when it exists in the coating liquid, is also included in the film in the process of application and becomes a passageway for charges causing microscopic leak of charges towards the surface of the photosensitive layer. Thus, poor images result similar to image faults due to defects on the substrate.
Of the aggregates, coarse primary particles can be removed rather readily from coating liquid by a process of filtration, for example, while secondary particles, being formed by a relatively weak force of aggregation, cannot be removed. Therefore, it is important to avoid the formation of secondary particles by finding a composition that inhibits generation of such particles, by improving dispersion capability of the metal oxide, and by establishing an interaction with the resin to maintain a stable dispersion.

Fuji Electric Device Technology Co., Ltd.


A recording unit recording the plurality of time-series parallax images outputted from the plurality of imaging units on a recording medium when the moving image is photographed, reading out the first and second information from the storage unit, and recording the first information and the second information read out from the storage unit on the recording medium in association with the plurality of parallax images.

PTL 1 discloses a stereoscopic imaging device provided with a first lens barrel having a CCD for acquiring photographing information for the right eye, a second lens barrel having a CCD for acquiring photographing information for the left eye, a camera detection circuit detecting the respective focal lengths of the first lens barrel and the second lens barrel, a ROM composed of an EEPROM or the like preliminarily storing the amounts of deviation of the centers of the respective optical axes of the first lens barrel and the second lens barrel in the respective focal lengths, and a CPU controlling an image cutout area in at least either one of the pair of right and left CCDs in the respective focal lengths based on an output from the ROM.
PTL 2 discloses an image processor where an approximation formula for coordinate correction based on a lens center is set with respect to a lens property of a stereo camera, and based on this approximation formula, projected coordinates of a target image captured by the camera are corrected.
On the other hand, PTL 3 discloses an image processor where high-definition imaging is performed using a plurality of imaging devices, respective imaging outputs of the imaging devices are converted into a digital image, thereafter the digital image is divided into a plurality of image areas by an image splitting circuit, and the respective image areas are subjected to image processing in parallel, so that high-speed image processing can be performed at a high moving image rate even in the case of a high-definition image.

Stereoscopic imaging device, image reproducing device, and editing software


A highly reliable solid-state image pickup device with one- or two-dimensionally arranged connecting portions, capable of avoiding corrosion of wirings resulting from chipping of the substrates and eliminating image defect, is achieved by arranging plural substrates, each bearing a plurality of image taking elements, in a planar manner on a supporting substrate and filling the connecting portions of thus arranged substrates with an organic or inorganic material, of which content in chlorine or in each of sodium and potassium does not exceed 200 ppm.

1. Field of the Invention
The present invention relates to a one-dimensional or two-dimensional solid-state image pickup device, adapted for use in a facsimile apparatus, a digital copying machine or an X-ray image taking apparatus.
2. Related Background Art
In the image reading system of the facsimile apparatus, the digital copying machine or the X-ray image taking apparatus, there has generally been employed a system consisting of a combination of a reduction optical system and a CCD sensor. Also in recent years, owing to the development of photoelectric converting semiconductor materials represented by hydrogenated amorphous silicon (hereinafter represented as a-Si), there has been proposed a contact sensor containing the photoelectric converting elements or such elements and a signal processing unit on a large-sized substrate and adapted to read the information from a source with a real-size optical system, and such contact sensor is being commercialized particularly in the one-dimensional sensor. In particular, since a-Si can be utilized not only as the photoelectric converting material but also as the semiconductor material for a thin film field effect transistor (hereinafter represented as TFT), it allows to simultaneously form a photoelectric converting semiconductor layer and a semiconductor layer of the TFT on a same substrate, thereby simplifying the structure.
However the increase in the size of the substrate may result in a lowered production yield with respect to the number of processed substrates, because the satisfactory or defective product can only be judged after the final stage of the manufacturing process. Also there is required a large investment in the manufacturing equipment since exclusive process and manufacturing line, including the film formation and the photoresist process, have to be newly established corresponding to the substrate size. Based on such viewpoint, the realization of economically acceptable product poses a difficult aspect. In particular, an improvement in the manufacturing yield has to be considered sufficiently in case of the solid-state image pickup device of a large image reading area, since such device cannot be obtained, unlike the line sensors, in a large number from a single substrate.
For this reason, attention is being attracted, for the purpose of improving the manufacturing yield, to a method of obtaining a large-sized device by arranging a plurality of small-sized substrates. FIGS. 1A and 1B show an example of the solid-state image pickup device forming by arranging a plurality (2.times.2=4 units in the illustrated example) of small-sized substrates. In these drawings there are shown circuit boards 2001, flexible circuit boards 2002, lead electrodes 2010 formed on the sensor substrates, and sealant 2011.
The sealant 2011 is applied at the junction of the lead electrodes 2010 and the flexible circuit boards 2002, for the purpose of preventing corrosion of the lead electrodes 2010, and is generally composed of silicone resin. There are also shown sensor substrates 2003-2006 bearing thereon sensor elements 2007 (represented by sensor areas), a base member 2008 for supporting the sensor substrates 2003-2006, and an adhesive material 2009 for fixing the sensor substrates 2003-2006 to the base member 2008. The sensor substrates 2003-2006 are fixed to the base member 2008, with such alignment that the pitch of the pixels is matched two-dimensionally.
FIG. 2 shows an example of the process for preparing the solid-state image pickup device formed by arranging a plurality of small-sized substrates as shown in FIGS. 1A and 1B. In a step (2101), four sensor substrates 2110-2113 prepared by a thin-film semiconductor process are sliced into a desired size by a rotary diamond blade 2114.
Then, in a step (2102), the circuit board 2001 is connected, by suitable jointing means 2115 and through the flexible circuit board 2002, to the lead electrode portion 2010 of the sensor substrate 2110-2113 prepared in the predetermined size. In a next step (2103), the sealant 2011 is coated by a dispenser 2116 so as to cover the junction portion of the lead electrode portion 2010 and the flexible circuit board 2002.
Then, in a step (2104), the sensor substrates after sealing are mutually so aligned that the pitch of the pixels matches two-dimensionally, and the substrates are placed on and fixed to the base member 2008 coated with the adhesive material 2009 in advance. (In FIG. 2, the sensor elements 2007 are omitted from the illustration.)
In case the above-mentioned solid-state image pickup device is used as an X-ray image pickup device, there is adopted a configuration in which the X-ray is converted by a fluorescent plate into a sensitive wavelength range of the sensor, such as visible light, and such converted light is read by the sensor. FIGS. 3A and 3B show an example of the X-ray image pickup device, wherein shown are circuit boards 2001; flexible circuit boards 2002; lead electrode portions 2010 provided on sensor substrates 2110-2113; and a sealant 2011.
The sealant 2011 is applied at the junction of the lead electrode portion 2010 and the flexible circuit board 2002, for the purpose of preventing corrosion of the lead electrodes 2010, and is generally composed of silicone resin. There are also shown sensor substrates 2003-2006 bearing thereon sensor elements 2007, a base member 2008 for supporting the sensor substrates 2003-2006, and an adhesive material 2009 for fixing the sensor substrates 2003-2006 to the base member 2008. The sensor substrates 2003-2006 are fixed to the base member 2008, with such alignment that the pitch of the pixels is matched two-dimensionally. There are further shown a fluorescent plate 2201 for converting the X-ray into the visible light, and an adhesive material for adhering the fluorescent plate 2201 to the sensor substrates 2003-2006. In FIG. 3A, the fluorescent plate 2201 is partially cut off at the lower right corner for the purpose of showing the structure thereunder. The fluorescent plate 2201 may be provided over the entire area corresponding to the area of the photoelectric converting elements 2007.
FIG. 4 shows an example of the process for preparing the X-ray image pickup device shown in FIGS. 3A and 3B. In a step (2301), sensor substrates 2110-2113 prepared by a thin-film semiconductor process are sliced into a desired size by a rotary diamond blade 2114. Then, in a step (2302), the circuit boards 2001 are connected, by suitable jointing means 2115 and through the flexible circuit boards 2002, to the lead electrode portions 2010 of the sensor substrate 2110-2113 prepared in the predetermined size.
In a next step (2303), the sealant is coated by a dispenser 2116 so as to cover the junction portion of the flexible circuit board 2002 connected onto the lead electrode portion 2010. Then, in a step (2304), the sensor substrates 2110-2113 after sealing are mutually so aligned that the pitch of the pixels matches two-dimensionally, and the substrates are placed on and fixed to the base member 2008 coated with the adhesive material in advance. Then the fluorescent plate 2201, coated with the adhesive material 2202 over the entire area for example by spraying, is placed on the sensor substrates 2110-2113. Then, in a step (2305), adhesion is achieved by a constant pressure applied by a roller 2203. In FIG. 4, the photoelectric converting elements (sensor elements) 2007 are omitted from the illustration.
In such solid-state image pickup device formed by arranging plural small-sized substrates, the image pickup device of pseudo single substrate is formed by matching the pitch of the pixels in two-dimensional directions. Consequently it is possible, when the small-sized substrate is completed, to inspect the electrical characteristics thereof, thereby judging each substrate satisfactory or defective, and to improve the yield at the next assembling step. On the other hand, it is necessary to pay attention, in the cutting process in the step (2101) or (2301) shown in FIG. 2 or FIG. 4, not only to the dimension precision and the positional error resulting from the burrs generated at the cutting, but also to the destruction of the elements resulting from the chipping at the cut portion and the corrosion.
FIG. 5 shows a connecting portion between the two neighboring substrates in a schematic plan view, wherein shown are sensor pixel portions 2401; thin film transistor portions 2402; gate lines 2403; and signal lines 2405. The interval of the gate lines or the signal lines corresponds to the pitch a of the pixels. In order to connect the neighboring substrates while matching the pitch of the pixels as shown in FIG. 5, the distance .beta. from the end 2406-1 or 2406-2 of each substrate to the gate line 2403-1 or 2403-2 has to satisfy a relation .beta.<.alpha./2. In recent years, because of the requirement for a finer image and the advancement in the semiconductor technology, the pixel pitch of the solid-state image pickup device is in the order of several tens of microns to several hundreds of microns. With such miniaturization of the pixels, the distance .beta. from the end of the substrate to the gate line becomes shorter so that the size of chipping at the substrate end detrimentally affect the structure of the device.
FIG. 6 shows an example of a chipping at the connecting portion of the two neighboring substrates (upper part being a schematic plan view while lower part being a schematic magnified cross-sectional view), wherein shown are a chipped portion 2501; an insulating film (silicon nitride film) 2502; a protective film (polyimide film) 2503; and a transparent insulating substrate 2505. The insulating film 2502 and the protective film 2503 are normally so formed as to cover sensor pixel portions 2401, thin film transistor portions 2402, gate lines 2403 and signal lines 2405 to prevent intrusion of moisture and impurity ions such as of sodium, potassium and chlorine, thereby protecting the metal wirings from corrosion. However, if the substrate is chipped as illustrated to a position close to the gate line, the moisture and the impurity ions intrude at the interface of the insulating film 2502 and the transparent insulating substrate 2505, thereby inducing corrosion of the wirings and eventually leading to the breakdown thereof. This causes the lack of a line in the image, thus significantly deteriorating the image quality.
At the process of producing the X-ray image pickup device, in a state that the flexible circuit board is connected onto the lead electrode portion of the sensor substrate, a sealing material is painted by a dispenser to cover the junction portion. Then, the four sensor substrates after sealing are mutually so aligned that the pitch of the pixels matches in the two-dimensional directions, and are placed on and fixed to the base member on which the adhesive material is painted previously. And then, a fluorescent plate painted with the adhesive material over the entire area thereof for example by spraying is placed on the sensor substrates. And, pressing thereon at a constant pressure by a roller, the fluorescent plate is bonded to the base plate. In this operation, the excessive adhesive material is leaked out from the ends of the fluorescent plate, thereby further covering the lead electrode portions already covered with the sealant. As a result, the lead electrode portions are twice sealed.
The lead electrode portion or the surface thereof is covered with an Al film, or formed with Al or an Al alloy, and is therefore not protected against the moisture or the impurity ions such as sodium, potassium or chlorine. For this reason, the lead electrode portion is sealed, in a similar manner as explained above, by organic resin with low impurity ions, such as silicone resin or epoxy resin. Such resin is initially liquid and is solidified by a chemical reaction induced by the addition of heat, moisture, ultraviolet light or a hardening agent, and is provided with a considerable adhering power. Also between the sensor substrates and the fluorescent plate there is employed an adhesive material, which is required:
1. to be optically transparent; PA1 2. to have satisfactory adhesion to and to be hardly peelable from the substrates; PA1 3. to be of a low viscosity in order not to include bubbl es between the substrates; and PA1 4. to be hardenable at the room temperature, in consideration of peeling of the substrates by the difference in the thermal expansion coefficients.
These requirements apply also to the sealing resin for the lead electrode portions, so that a same material may be employed for both purposes.


Disclosed is a method for saving electricity consumed by a computer. The method includes the steps of defining a plurality of items of service so that a user can select one of the items of service, identifying at least one device, driver and application corresponding to the selected item of service and providing a simplified process for actuating the device, driver and application corresponding to the selected item of service.

1. Field of Invention
The present invention relates to a computer and, more particularly, to a method for saving electricity consumed by a computer.
2. Related Prior Art
Traditionally, a computer cannot immediately provide any service to a user after it is turned on. Only after the loading of an operating system is completed can the computer provide service such as TV, radio, games, internet browsing, web phone, emails, music and movies. One problem is that a lot time elapses before the loading of the operating system is completed. Another problem is that a lot of electricity is consumed during the executing of the operating system.
There have been techniques based on changes in software and/or hardware to enable a computer, when turned on or before the loading of an operating system, to provide a single item of service. The single item of service may be music or movies. However, each of these techniques cannot cause the computer to provide a plurality of items of service.
Disclosed in Patent Application Publication US20040006690 is a computer that executes a first operating system or a second operating system. As required, the second operating system executes an application selected from a DVD application, a TV application, a digital device application, a remote control application, a voice-recording application and an audio application. This technique discloses the provision of several applications, but fails to mention how to enable a user to choose from the applications. Moreover, during the executing of the second operating system, the devices of the computer irrelevant to a chosen application also consume electricity, and this is a waste.
Therefore, the present invention is intended to obviate or at least alleviate the problems encountered in prior art.

Computer and method for saving electricity consumed thereby


Methods and systems are provided for improved protection of radio frequency identification tag memory by using two or more “brownout-safe” pointer registers (instead of a single pointer register) that are logically concatenated to form a complete address for the boundary between a locked portion and an unlocked portion of the tag memory. A first pointer is a coarse pointer identifying a block of memory containing the boundary. A second pointer is a fine pointer identifying a specific location within the identified coarse block of memory. The coarse pointer may be a gray-coded or linear pointer. Similarly, the fine pointer may be a gray-coded or linear pointer.

Radio frequency identification (RFID) tags, especially passive tags, can suffer momentary power loss during write operations resulting in incomplete execution of the write. If the loss of power occurs during a write of new identification or other data, the problem can be detected and corrected by rewriting the data at a later time. However, if instead the loss of power occurs during an update to a stored memory pointer, the pointer can be corrupted and may point to a random address. The corruption problem is particularly severe if the pointer is used to indicate one or more regions of locked (read and/or write) or permanently-locked memory. The term "locked" is typically used to indicated read or write permission, temporarily or for the life of the tag (known as "permalocking").
An expected typical mode of operation on tag user memory is for an interrogator to write a new data item to the lowest available unlocked memory address and then to lock the region of memory containing the new data. In typical applications, a single address pointer is utilized to indicate the current boundary between locked and unlocked memory. Such traditional pointers are sometimes call "log" pointers, because they achieve a range of "n" addresses using only log2(n) bits (e.g., an 8 bit pointer handles up to 256 addresses). A limitation of the use of traditional "log" points is that an arbitrary number of bits may change when an address changes. A "brownout" that prevents completion of the pointer update could result, for example, in un-locking memory that had previously been protected against accidental or malicious rewrites. This traditional approach is commonly used. For example, the ISO/IEC 15962:2004 standard describes the use of an increment-only pointer for the ISO/IEC 18000-3 Mode 2, for the 13.54 mHz RFID air interface.
Two techniques have been proposed to mitigate the problems potentially cause by "brownouts" or similar situations. One technique uses a non-traditional Gray-Coded address pointer. The advantage of incrementing addresses using a Gray code is that only one bit changes every time the pointer is incremented. Thus, changing an address by repeatedly incrementing it by one value will guarantee that the result, after a brownout, is either correct, or at worst, one less than the correct value. For additional details of the Gray-code technique, see U.S. patent application Ser. No. 11/835,201, entitled "Protecting Critical Pointer Value Updates To Non-Volatile Memory Under Marginal Write Conditions," which is incorporated herein by reference in its entirety.
A disadvantage of the Gray-code technique, compared to the traditional log pointer approach, is that to change the address by "n" locations, "n" separate successive write cycles are required. This approach, when large address changes are involved, may be slow, reducing processing throughput. Additionally, the approach may increase the probability that the tag will lose power before the full update is completed and may shorten the life of the tag which has a maximum guaranteed number of write cycles.
A second technique uses a "bitmap" instead of a standard address pointer to indicate which "blocks" of memory are permanently locked. For example, each '1' bit in the bitmap indicates a locked block. This approach is sometimes referred to as a "linear" pointer. Because the individual bits each control a separate block, no logical dependencies exist between the bits. Therefore, changing protection on one block changes only one bit, with no effect on the other bits. Moreover, in a "permalocking" application of the memory pointers, new blocks are allowed to "protected," but previously-protected blocks are by definition not allowed to become "unprotected." Therefore, the tag is only allowed to set bits to '1' within the bitmap, never to '0.' Thus, a "brownout" may result in incomplete protection, but will not result in lost protection.
A disadvantage to this approach is that it forces a tag vendor, as user memory size increases, to choose between a very large "bitmap" and a smaller "bitmap" where each bit represents a larger block of addresses. Choosing a large block size incurs the penalty that, as each new data item is written (then locked), a significant portion of the last bytes of each last-written block will be wasted.
A log-linear hybrid approach uses a linear pointer to protect blocks of memory coupled to a log pointer for each block to provide fine-grained protection within each block. Because the secondary pointers are traditional "log" pointers, they are also susceptible to the "brownouts" described above.
What is therefore needed is a method and system to ensure that previously locked data is not accidentally unlocked due to power loss.
What is further needed are methods and systems to minimize wasted nonvolatile memory when multiple items are written then locked over time.
The present invention will now be described with reference to the accompanying drawings. In the drawings, like reference numbers can indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number may identify the drawing in which the reference number first appears.

Concatenated pointers for radio frequency identification tags


An adder circuit in parallel with a zero flag generation circuit. In a preferred embodiment, an arithmetic logic unit (ALU) circuit in a microprocessor based computer system includes an adder circuit preferably adapted to receive first and second operands. The preferred adder circuit is further adapted to produce a result equal to the sum of the first and second operands. The ALU circuit further includes a zero flag generation circuit. The zero flag generation circuit is adapted to receive the first and second operands in parallel with the adder circuit and to produce a zero flag signal in response to the operands. The zero flag signal is indicative of whether the sum of the operands is equal to zero. In one embodiment, the zero flag generation circuit includes N half adders in parallel wherein each adder receives a bit from the first operand and a corresponding bit from the second operand. Each half adder produces a sum bit and a carry bit in response to the inputs. Preferably, the zero flag generation circuit further includes N-1 Exclusive OR (EXOR) gates. Each of the N-1 EXOR gates receives one bit of the N sum bits and a corresponding bit of the N carry bits as inputs. The N-1 outputs from the EXOR gates, together with an inverted least significant sum bit, are routed to a logic circuit. The logic circuit functions as an AND gate, producing an output signal indicative of whether each input signal is equal to 1.

1. Field of the Invention
This invention relates to the field of microprocessors and more specifically to an improved method and circuit for generating condition codes in an arithmetic logic unit of a microprocessor.
2. Description of the Relevant Art
Microprocessors determine the speed and power of personal computers, and a growing number of more powerful machines, by handling most of the data processing in the machine. Microprocessors typically include at least three functional groups: the input output unit (I/O unit), the control unit, and the arithmetic-logic unit (ALU). The I/O unit interfaces between external circuitry and the ALU and the control unit. I/O units frequently include signal buffers for increasing the current capacity of a signal before the signal is sent to external components. The control unit controls the operation of the microprocessor by fetching instructions from the I/O unit and translating the instructions into a form that can be understood by the ALU. In addition, the control unit keeps track of which step of the program is being executed. The ALU handles the mathematical computations and logical operations that are performed by the microprocessor. The ALU executes the decoded instructions received from the control unit to modify data contained in registers within the microprocessor.
The computing power of a microprocessor can be increased by increasing the clock speed. Higher clock speeds, however, place design constraints on the circuit boards and interconnect circuits that interact with the microprocessor. Alternatively, increased computing power can be accomplished by maximizing the number of instructions that can be executed at a given speed and by minimizing the number of cycles during which the microprocessor is in a wait state. A wait state refers to a microprocessor cycle during which the microprocessor executes no instructions. Wait states can be required, for example, when the microprocessor must wait for data from an external device.
One source of undesired delay or wait states involves the generation of condition codes by the ALU. In a typical microprocessor, the ALU generates one or more condition codes each time it performs a mathematical or logical operation upon a set of operands. The condition codes indicate characteristics or attributes of the result produced by the mathematical or logical operation executed by the ALU. Condition codes are used to control branching, to monitor the accuracy of data, and to control a variety of other functions. One widely known example of a condition code is referred to as the zero flag. The zero flag is a special-purpose one bit register that is set when a mathematical or logical operation executed by the ALU produces a result equal to zero.
Many mathematical operations performed by the ALU proceed from the least significant bits of the operands to the most bits. For example, a typical ADD operation executed by a ripple-carry adder will add the least significant bit of a first operand to the least significant bit of a second operand to produce a least significant bit of result and a first carry bit. The first carry bit will then be added to the next most significant bit of the first operand and the next most significant bit of the second operand to produce an intermediate result bit and an intermediate carry bit. This sequence continues until, eventually, the most significant bits of the operands have been added together with the carry bit from the preceding sequence to produce the most significant bit of the result (and a carry out bit).
Reference to FIG. 1 will help clarify this example. In FIG. 1, a first operand 12 is added to a second operand 14 to produce the result 16 with a ripple-carry adder. First operand 12, second operand 14, and result 16 include n bits. Result 16 is produced by adding a least significant bit 12a of first operand 12 to a least significant bit 14a of second operand 14 to produce a least significant bit 16a of result 16 and a first carry bit 18. Next, first carry bit 18, intermediate significant bit 12b of first operand 12, and intermediate significant bit 14b of second operand 14 are added to produce intermediate significant result bit 16b and second carry bit 20. This procedure is repeated until finally, n.sup.th -1 carry bit 24 is added to most significant bit 12n of first operand 12 and most significant bit 14n of second operand 14 to produce most significant bit 16n of result 16. As will be appreciated, least significant bit 16a of result 16 is generated prior to intermediate significant result bit 16b which, in turn is generated prior to most significant result bit 16n. Stated similarly, a finite but measurable period of time elapses between generation of least significant result bit 16a and most significant result bit 16n.
FIG. 2 shows a block diagram of an ALU execution unit 26 and an ALU condition code generation circuit 28. Execution unit 26 receives first operand 12 and second operand 14 together with instruction and control signals routed to the execution unit 26 over control bus 25. In response to the control signals and instruction signals contained on bus 25, execution unit 26 performs operations on first operand 12 and second operand 14 to produce result 16 as an output. The operations that execution unit 26 may perform on first operand 12 and second operand 14 include numerous instructions, such as the simple add instruction shown in FIG. 1. These operations frequently operate upon low order bit "a" of the respective operands 12 and 14 before the instruction operates on high order bit "n". As will be appreciated by those skilled in the art, the delay time between the generation of least significant result bit 16a and most significant result bit 16n in a conventional ripple-carry adder increases as the number of bits within first operand 12 and second operand 14 increases.
To address the delay time associated with ripple-carry adders, execution unit 26 can be designed with a fast adder circuit, such as a carry lookahead adder (CLA). The CLA reduces the delay time required to produce result 16 by reducing the number of logic levels needed to generate the most significant carry bit. Whereas the ripple-carry adder requires approximately 2N levels of logic to generate result 16, a practical CLA requires only approximately log.sub.2 N logic levels where N is the number of bits. A description of ripple-carry adders and CLAs can be found in J. Hennessy & D. Patterson, Computer Architecture a Quantitative Approach, pp. A-2 to A-3 and A-31 to A-39 (Morgan Kaufmann 1990) hereinafter "Hennessy"!.
Regardless of the time required for execution unit 26 to produce result 16, conventional microprocessor-based systems do not begin to generate condition codes, including the zero flag, until result 16 has been calculated. Referring again to FIG. 2, condition code generation circuit 28 receives result 16 from execution unit 26 and produces a plurality of condition codes in response thereto. As stated previously, condition codes indicate characteristics of the result 16 after execution of the instruction by execution unit 26. The condition codes produced by execution unit 28 shown in FIG. 2 include those commonly found in x86 type microprocessors. These flags include the parity flag (PF), the zero flag (ZF), the carry flag (CF), the auxiliary carry flag (AF), the sign flag (SF), and the overflow flag (OF). The zero flag is generally set after each mathematical or logical operation whenever result 16 is equal to zero. The zero flag is frequently used to control the branching of computer programs. If, for example, it is desired to branch to a particular location or subroutine when first operand 12 is equal to second operand 14, the condition can be detected by subtracting first operand 12 from second operand 14 and checking the zero flag. If first operand 12 is equal to second operand 14, result 16 will be equal to zero and the zero flag will be set. Conditional branching based upon the value of the zero flag is well known in the art of microprocessor programming.
The generation of the zero flag is within the critical speed path of the program execution. Execution of subsequent program instructions is often dependent upon and, therefore, must await the determination of the zero flag. When program execution must wait for generation circuit 28 to generate a zero flag before subsequent execution can occur, the time required to generate the condition codes has a direct impact on the system performance. It would therefore be desirable to reduce or eliminate the delay between the generation of result 16 and the generation of the zero flag.

Method and circuit for fast generation of zero flag condition code in a microprocessor-based computer


A bicycle advertising rack which is selectively attached to an existing parking meter, and which may be suitably used for locking up a bicycle in areas such as business areas having few or no bicycle racks or other objects to which the bicycle may be effectively secured. The bicycle advertising rack comprises a U-shaped tube having an upper arm and a lower arm; each having an end having a cylindrical collar affixed thereunto. The post of the parking meter extends concentrically through each of the collars, and forms a closed loop therewith, through which a chain or a U-shaped lock may be extended while “locking” a bicycle to the parking meter. The bicycle advertising rack has two flat plates for selectively displaying an advertisement thereupon.

1. Field of the Invention
The invention generally relates to a bicycle rack to which an existing bicycle may be locked, and in particular relates to a bicycle rack which is selectively attached to an existing parking meter, and which has flat plates for selectively displaying an advertisement thereupon.
2. Description of the Related Art
Hundreds of thousands of bicycles are stolen every year from outdoor locations. To minimize the possibility of theft, many bicycle owners secure their bicycles to a stationary object such as a bicycle rack with a chain and lock or with a U-shaped lock. However, certain areas, such as business areas, have few or no bicycle racks or other objects to which a bicycle may be effectively secured. Moreover, many such areas would benefit from the provision of an effective advertising display system for informing persons in the area of various retail outlets in the area, or for general advertisement purposes. Accordingly, there is a need for a bicycle rack which is selectively attached to an existing parking meter, and which has flat plates for selectively displaying an advertisement thereupon.
A variety of bicycle racks have been devised for enabling a user to selectively lock an existing bicycle thereunto, for preventing a would-be thief from absconding with the bicycle. While the existing bicycle racks may be suitable for the particular purpose employed, or for general use, they would not be as suitable for the purposes of the present invention as disclosed hereafter.


The present invention provides a method for preparing a carbon nanotube material. In the present invention, a mixture of polyolefin and modified montmorillonite is used as the carbon source. Under the action of a catalyst, a carbon nanotube is synthesized in air. The present invention can address the problem of “white pollution” caused by waste plastics, such as waste polyolefin polymers.

It is well known that from the microscopic view a carbon nanotube is formed in the following way: multiple carbon atoms each link with three adjacent carbon atoms to form hexagonal ring nuclei among the carbon atoms. By spreading and bending a plane constituted by cellular, repeated hexagonal nuclei, a circular cylinder is formed. The carbon nanotube is characterized in that its diameter is generally in the range from several angstroms to scores of nanometers while its length/diameter ratio is in the range from several tens to several thousands. Because of their excellent physical and mechanical properties and excellent electric conductive property, carbon nanotubes have been widely used. In recent years, research results concerning the modification of polymers by carbon nanotube have been reported. Carbon nanotubes used in this application do not need to be perfect in structure but should be produced in large quantity. Therefore this will demand a synthesizing technology that can produce carbon nanotubes in large quantity at low cost.
Carbon nanotubes were generally manufactured by electrical arc method, laser evaporation method, electrochemical gas phase deposition method, catalyst synthesis method and plasma synthesis method. In these methods, carbon sources used were those of small organic hydrocarbon molecules such as methane, acetylene, ethylene, carbon monoxide and etc. Organic polymers were scarcely used as the carbon source for manufacture of the carbon nanotubes. In addition, in the manufacturing process, an inert gas was used for protection purpose and the facilities used were relatively complex.

Method of preparation for carbon nanotube material

Changchun Institute of Applied Chemistry Chinese Academy of Science