The invention discloses a processing method for process changing time-series database table structure, wherein comprising following steps: an application side generates a data table containing a table name ID, a schema version, and a column ID; when a data column is increased, the application side modifies a schema of the data table, increases the schema version, assigns a new column ID number to a newly increased column incrementally, and assigns a default value to the newly increased column; according to a data insertion request of the application side, a data node receives data of a schema version carrying a data table from the application side and writes the received data, wherein writing the received data comprises: storing the schema version of the data table carried by data from the application side by the data node, and writing the received data, and writing the received data; when the data node receives new data from the application side, comparing the schema version of the data table carried by the new data with a stored schema version of the same data table; and the data node writes data according to the comparison result. According to the method, the operation of changing the structure of a table can be completed instantly, the historical data does not need to be changed, new and old table structure definitions can be used in parallel, and the flexibility can be improved.

One data sampler often collects multiple parameters at the same time point, and the number of parameters may change with the update of a software or firmware. In order to cope with the change, one existing mode is to store each collected parameter as one independent time series, which is very flexible, but each series needs to save its own timestamp, so that the storage space is wasted and the calculation operation between different collected parameters is inconvenient. Another mode is to adopt a traditional relational database, where each parameter is one column and multiple parameters are multiple columns, having the advantage that multiple columns share one timestamp. But the disadvantage is obvious in that adding a new parameter requires adding a new column. For tables with a large number of recorded entries, this would be an extremely inefficient operation because all existing data needs to be updated.

Processing method for changing time-series database table structure


A socket engageable with a drive assembly is disclosed, the socket having two segments pivotably connected with each having an engageable periphery for rotation of the socket by the drive assembly and together defining a center bore for engaging a work piece, the segments being self locking when the work piece is engaged. The drive assembly has a selectively accessible slot for receiving and holding the socket in the operative position, a mating drive gear for the rotation of the socket and a guide for assuring lateral and rotational stability of the socket.

In the manufacture and maintenance of aircraft, heavy equipment, machinery and appliances it is often necessary to remove and install hoses, lines and pipes that are attached to fittings by a threaded fastener (for example, a flare nut, B nut, or the like). Moreover, such equipment and machinery may often utilize a plurality of conduits that are placed close together, in confined or otherwise hard to access spaces, or at awkward angles.
These threaded fasteners, therefore, must often be rotated with open end wrenches and various types of pliers, risking damage to the fastener and providing only a slow manual manipulation of the fastener and little or no means for limiting the torque delivered to the fastener. Removal and installation of threaded fasteners on the various forms of conduit may thus be slow and tedious.
Several types of wrenches to rotate such fasteners in such a way as to make the process faster and cause less damage to the fastener have been heretofore suggested and/or utilized. U.S. Pat. Nos. 2,712,256, 2,712,257, and 2,758,493 disclose open ratchet wrenches which can turn a hex fastener encircling a line. U.S. Pat. Nos. 3,564,955, 3,668,949, 4,914,987, and 4,374,479 disclose gear driven tools for rotating fasteners or appliances that hold such fasteners.
These tools, however, suffer from many of the same problems as open end wrenches (such as the ratchet wrenches described above), in that when a plurality of hoses, lines or pipes are clustered together or are close to accessories of the equipment being worked on it is very difficult to find enough room to manipulate the tool in such a way as to engage and operate the tool. In addition, many such tools are unduly complex and/or are configured in such a way that they can slip off the fastener and cause damage to the fastener, the tool and/or the user.
Of those tools described above utilizing geared peripheries, some have utilized a single divided collet as a holder for nut rotating accessories thus practically negating use for flare nuts on continuous lengths of conduit (i.e., such tools, while providing a collet that can be split and opened to grip accessories, have not provided accessories that can be split and opened to encircle the length of conduit), and have not provided for their use with an assortment of interchangeable sockets for different applications. Often, complex closing and locking procedures are required which limit the applications and/or complicate usage of such tools.


A method of using special designed wiring level mask(s) to determine product transistor and circuit performance in a chip during the early portion of the product evaluation cycle saves weeks of time that would have been taken by the passage of the wafer through the fab. The method also saves cost during production by identifying wafers for rework at an early stage.

The field of the invention is that of integrated circuits, in particular fabricating circuits with design changes.
In the course of developing an integrated circuit, the designers make use of extensive computer models that predict the electrical performance of a circuit that has been synthesized, e.g. in a computer program that accepts as input the logic requirements of a system and generates a schematic that performs the functions specified.
Such programs are very sophisticated, but not infallible.
During the logic technology qualification cycle, one of the major hurdles needed to overcome is performance limitations that prevent the system specification from being realized. This becomes more critical with advanced technology.
Numerous process changes and model to hardware correlation are needed to assess the performance specification for the technology. The performance assessment is often made on final product chips with four to six levels of metal. The turn-around-time of this trial and error method to achieve final product performance data is significantly long due to extensive BEOL (Back End Of Line) wiring levels used in the product chip. As we incorporate more device types and move towards System On a Chip (SOC) early readout and correlation of product performance becomes critical. The parametric data does not always match the product performance.
Product chip data at final test are currently correlated back to the inline parametric data taken during the passage of the wafer through the fab. Parametric data is monitored to provide look ahead and indicate whether the hardware heading to product wafer test is healthy and to predict final chip yield. Parametric monitoring has been performed in this way for multiple generations of integrated circuits, providing standard checks on electrical parameters including the transistor characteristics.
However, the reference macro designs on which the parametric data is obtained cannot accommodate all the numerous design/process variables that reflect all transistors in the actual product chip environment. Often, the inevitable differences between the parametric transistor design vs. product transistor design can result in conflicting data. For example, it often happens that the parametric transistor results measured inline meet the design manual specification and yet the product chip performance results do not meet the specification set for the chip.
As performance requirements increase, the margin for error or manufacturing tolerance is reduced, so that a deviation in the performance of an individual device may be magnified by the circuit within which the devices is located. The result may be that the circuit does not meet its specification, even though the device does.
Due to the complex process of fabricating transistors in various environments, it is possible to have different physical shapes for transistors in different environments. It becomes increasingly difficult to maintain transistor shapes constant across the chip with each scaling technology generation. Systematic technology process solutions (across chip solutions) can only resolve this issue to a certain degree.
In particular, across chip line width variation may produce transistors with different amounts of drive in different parts of the chip. This may affect the time when a following device is turned on or off and thus change the circuit timing from its specification. In some cases, there may be logic errors when a signal arrives late or early.
In addition to the foregoing problems that do not depend on the time to pass through the fab significantly, there are other issues that explicitly deal with the time between identification of a problem and implementation of a solution. Often, a performance limiting feature is only identified on fully finished wafers.
In order to identify such problems, the chips often need to be delayered down to a lower level where a FIB (focused ion beam) probe technique is used to evaluate the actual transistor behavior in the questionable circuit. These standard techniques simply consume too many resources and have very long turn-around-time.
For example, the transit time of a wafer through a fab takes several months which the exact turn-around-around time varies depending on specific chip design for Back-End-of-Line build and fab loading, so that it takes a significant amount of time for a test batch of wafers to emerge from the fab so that they can be tested more rigorously than is possible for the in-process testing. Once a problem is identified (and a possible solution found) it then takes a period of months for wafers embodying the solution to make their way through the fab so that tests can be run to confirm that the proposed solution does or does not work.
There are several current methods for assessing performance of the product
1. Actual product performance at speed—This approach needs a final test, and possibly a packaged module. Further, if a problem is seen it can be difficult to correlate the problem with particular devices.
2. The use of test modes (in the testing program) to evaluate parts of the circuit—This approach needs both a final test and also additional circuits on the chip (Silicon area=cost) and design effort.
3. Test points within the design—This approach provides direct access to devices, but also needs access to the first metal (in order to locate the test points) and the design functions require significant bench work and design effort.
4. Chip delayer and Focus Ion Beam (FIB) cutting+wiring of devices within the chip—This approach also needs for the final level to be completed. In addition, we need to know which device is causing a problem. Further, since this is a labor-intensive process, there will be only a small sample size, so that the particular components examined may not be the immediate cause of the problem (even if they contribute to the problem in a large statistical sample). This approach often fails to identify a problem that can be fixed when there is an inconclusive test output.
5. Correlation of parametric data to product performance —This approach also needs test data from the completed chip. It is also not always successful in correlating the circuit problem with the parametric data.

Using a partial metal level mask for early test results

International Business Machines Corporation


A method of fabricating a thinned, reinforced semiconductor wafer is disclosed. Particularly, a semiconductor wafer may be provided and a plurality of separate semiconductor dice may be formed upon a surface thereof. At least one region of the semiconductor wafer may be thinned and at least one reinforcement structure for reinforcing the semiconductor wafer may be formed. A semiconductor wafer is disclosed comprising at least one thinned region and at least one reinforcement structure having a first portion and a second portion extending from respective thinned surfaces of the at least one thinned region. A method of designing a semiconductor wafer is disclosed wherein at least one region thereof is selected for thinning. Remaining unthinned regions of the semiconductor wafer may be selected for forming at least one reinforcement structure. At least one semiconductor die location may be selected within the at least one thinned region.

1. Field of the Invention
The present invention relates to semiconductor wafer structures and methods for fabricating same. Particularly, the present invention relates to a thinned semiconductor wafer structure including at least one structure providing reinforcement therefor.
2. Background of Related Art
Semiconductor wafer thinning techniques have been developed in response to an ever-increasing demand for smaller-sized, higher-performance semiconductor devices. For example, operation of semiconductor devices may generate relatively large amounts of heat. Accordingly, heat must be removed from a semiconductor device to avoid failure or performance degradation thereof due to excessive temperatures or a deleterious thermal environment.
One way to enhance heat transfer away from a semiconductor device and mitigate deleterious thermal effects is by thinning the semiconductor wafer on which the device is fabricated. Other reasons for thinning a semiconductor device may include dimensional packaging constraints (such as for, by way of example only, use in cell phones, personal digital assistants (PDAs) notebook computers and the like), optimization of transmission line characteristics, and reduction of the length of via holes extending transversely through the thickness of the device. Semiconductor devices may be thinned while the devices are in a wafer form or structure (i.e., prior to dicing). However, one undesirable consequence of thinning a semiconductor wafer is increased fragility thereof due to the inherently brittle nature of semiconductor materials. In turn, increased fragility of a semiconductor wafer may undesirably influence handling during the thinning operation, thereafter, or both.
Furthermore, due to the relatively high cost of semiconductor handling equipment, and correspondingly high investment therein, it will almost always be preferred to utilize, at least for a period of time, existing semiconductor handling equipment for handling thinned semiconductor wafers. Of course, such semiconductor handling equipment will have likely been designed for full thickness semiconductor wafers and, therefore, may not perform optimally or even suitably for handling thinned semiconductor wafers.
One conventional approach for addressing the fragility of a thinned semiconductor water is to mount a semiconductor wafer to a support layer or other support structure prior to thinning, wherein the support structure, alone or in combination with the semiconductor wafer structure itself, provides structural support for handling of the semiconductor wafer, as well as protection of a semiconductor wafer surface. Also, the support structure in combination with the thinned semiconductor wafer may be configured to exhibit dimensions substantially similar to a conventional, unthinned semiconductor wafer, which may facilitate handling thereof by conventional semiconductor wafer handling equipment.
For example, a conventional support structure may be affixed to a semiconductor wafer by first coating a major surface of the wafer with an adhesive material and bonding the support structure to the semiconductor wafer, thus forming a supported semiconductor wafer. In addition to providing structural support for the semiconductor wafer, the support structure may also facilitate handling of the semiconductor wafer. U.S. Pat. No. 3,475,867 to Walsh, entitled "Processing of Semiconductor Wafers," and U.S. Pat. No. 3,492,763 to Walsh, entitled "Method and Apparatus for Mounting Semiconductor Slices," each describes conventional methods and support structures of the type described above, respectively.
A semiconductor wafer, once supported by a conventional support structure may be thinned by either mechanically grinding or chemically etching an exposed surface thereof, typically the back side. However, the use of adhesive material may be undesirable as increasing the potential for introducing contaminants into the process area. In addition, the processing temperatures, which the supported, bonded wafer encounters, must remain below the melting temperature of the adhesive material. Other considerations may include warping or bowing of a semiconductor wafer due to difference between the coefficients of thermal expansion or stress states of the wafer and the support structure and dicing of the semiconductor wafer.
Another conventional example of methods and apparatus for supporting a semiconductor wafer during or after thinning is U.S. Pat. No. 4,853,286 to Narimatsu et al. and entitled "Wafer Processing Film," which patent discloses providing a wafer processing film comprising a base film having a Shore D hardness of 40 or less and an adhesive layer disposed on one surface of the base film for supporting wafers such as silicon and similar wafers during grinding thereof.
Further, U.S. Pat. No. 5,476,566 to Cavasin, entitled "Method for Thinning a Semiconductor Wafer" discloses a laminated semiconductor wafer structure for providing mechanical support to a wafer during and after thinning. According to such a configuration, a semiconductor wafer is affixed to a UV-transparent support substrate with a double-sided adhesive tape, the tape having dissimilar adhesives on its two sides. Subsequent to thinning, the support substrate and the tape are removed from the wafer by exposing the laminated structure to UV radiation.
Also, U.S. Pat. No. 5,508,206 to Glenn et al., entitled "Method of Fabrication of Thin Semiconductor Device" discloses thin semiconductor devices, such as thin solar cells, and a method of fabricating same. First, material layers for forming the solar cell are formed over substantially a surface of a wafer or substrate. Then, a microblasting procedure is employed to thin the opposite surface of the semiconductor wafer or substrate, wherein fine abrasive particles are used to etch away wafer material through a mask. Thick areas remain at the perimeter of the semiconductor device or solar cell, in regions of the semiconductor device or solar cell behind the front interconnect attachment pads, and at corresponding rear interconnect attachment areas. In addition, there are thick areas in a pattern that comprise interconnected beams that support the thin wafer areas.
Accordingly, it would be advantageous to provide a semiconductor wafer structure for supporting a relatively thin semiconductor wafer and methods for forming same. Further, it would be advantageous for the methods to employ processing acts of reduced complexity and time requirements and which may be compatible with existing automated wafer handling systems.

Wafer reinforcement structure and methods of fabrication


An indexable cutting insert for metal machining comprises an upper rake surface, a bottom surface and side surfaces that extend between the upper and bottom surfaces. Cutting edges are formed at the transitions between the side surfaces and the upper surface. Disposed along the cutting edges on the upper surface are elongated primary lands. Disposed inside of the lands is a chip-breaking depression. A raised land area to be ground is situated in the chip-breaker, so that the total grinding area of the upper surface becomes about as large as the total grinding area of the bottom surface. The insert can thus be ground by upper and lower grinding wheels which rotate simultaneously in opposite directions.

The present invention relates to a cutting insert which is ground to form a sharp edge. The cutting insert is primarily intended for milling, although also cutting inserts for turning and drilling lie within the framework of the invention.
Cutting inserts such as indexable inserts are made by form-pressing and sintering of a cutting material-forming powder, usually cemented carbide. The cutting insert comprises (a) an upper surface or chip surface, (b) a bottom surface substantially parallel with the upper surface (these two surfaces constitute the main surfaces) and abuttable against a cooperating bottom support surface in an insert seat, and (c) side or relief surfaces extending between these upper and bottom surfaces. At least one of the side or relief surfaces is abuttable against a cooperating side support surface in the insert seat. The side surfaces may be perpendicular to said upper and bottom surfaces, but usually they are somewhat obliquely positioned, i.e., oriented at an acute angle to the upper surface, and at an obtuse angle to the bottom surface. A transition between the upper surface and a side surface is shaped as a cutting edge.
In production of primarily indexable cutting inserts of cemented carbide, a direct pressing method is being employed to an increasing extent, according to which method a cemented carbide forming powder first is shaped into the desired form in a pressing tool, and thereafter it is given the final strength by being sintered in an oven. The pressing operation as such has been refined and is today so rational that it brings about good possibilities of forming the cutting edge and the appurtenant chip shaping surfaces and possible reinforcing faces with great accuracy.
For some types of machining, e.g., some forms of face milling and corner milling, the requirements of shape and dimensional accuracy of the inserts have been raised during the last years. Primarily geometries with sintered-in positive cutting edges require a very high dimensional accuracy in order to guarantee a satisfactory result at small tooth feeds. These requirements of dimensional accuracy, and in some cases also on sharp cutting edges, have hitherto been achieved by so-called contour grinding or peripheral grinding, wherein the surface(s) that adjoins the individual cutting edge is after-ground following the usual grinding and cooling. This contour grinding is made on the relief side of the cutting insert, i.e., on the side surfaces. As an example of such a grinding, U.S. Pat. No. 5,078,550 is referred to. However, thereby the working measure or the IC measure are altered. Further, when the cutting insert has sintered-in chip breakers, the after-grinding may result in the primary land of the cutting insert becoming unacceptably narrow and fragile. Moreover, the bottom surface of the cutting inserts have been ground a substantially perfect plane, in order to guarantee a safe and stable support in the insert seat.
However, in order to not excessively alter the working measure of the cutting insert and at the same time obtain a sharp cutting edge, it would be desirable to be able to grind the cutting edge with the appurtenant primary land from above, i.e., on the upper or chip surface of the cutting insert. However, in conventional grinding machines this has not been feasible due to the fact that very little material of the upper surface is to be ground, i.e., only the cutting edge line or a primary land immediately adjacent the cutting edge line. Because of the small extent or area of the cutting edge line or primary land (often <0.2 mm), the speed of the grinding plate has to be lowered and then undesired chippings are obtained. Furthermore, it is extremely difficult to control the grinding capacity when there is not enough material that exerts a resistance against the grinding operation, whereby the precision of the ground face becomes poor.
Thus, a primary object of the present invention is to provide a cutting insert that may be ground with a substantially unaltered chip cutting geometry on the rake side as well as on the relief side by a conventional grinding mechanism.
A second object of the invention is to be capable of producing sharp cutting edges without altering the chip cutting geometry.
Still another object of the present invention is to rationalize the grinding of the cutting inserts as much as possible.

Cutting insert adapted to be ground on upper and lower surfaces thereof


The invention relates to a disc discriminating method and an optical disc information reproducing apparatus wherein DVD-RAM which is DVD-RAM1 or DVD-RAM2 and DVDRW which is DVD-RW or DVD+RW which cannot be respectively determined based upon distance from the surface of a disc to the recording face, the number of recording faces and the reflectance can be discriminated. In case an optical disc is DVD-RAM or DVDRW, the amplitude of a push-pull tracking error signal is measured by a microcomputer in a state in which servo control is executed based upon a focus error signal. Determination is performed based upon the amplitude of the push-pull tracking error signal, when the amplitude of the push-pull tracking error signal is larger than a predetermined value, the optical disc is judged as DVD-RAM and when the amplitude is smaller than the predetermined value, the optical disc is judged as DVDRW.

The present invention relates to technique for reproducing or recording data from/to an optical disc.
For a medium for recording information, a magnetic tape and a disc can be given.
For the magnetic tape, a magnetic tape on which analog signals are serially recorded for a long time such as one used in VTR is well-known.
In the meantime, for the disc, an optical disc on which digital information is recorded can be given, it is used for an external storage of a computer and an apparatus for recording or reproducing an aural signal or a picture signal to/from an optical disc has been manufactured. As information can be recorded or reproduced to/from an optical disc at random, compared with a magnetic tape on which information is serially recorded, the optical disc has a merit that access to information is promptly enabled.
The above-mentioned optical disc has various types such as a compact disc (CD) and a digital video disc (a digital versatile disc) (DVD), for CD, a compact disc read only memory (CD-ROM), a compact disc-recordable (CD-R) and CD-rewritable (CD-RW) are known and for DVD, there are single-layer DVD-read only memory (DVD-ROM), dual-layer DVD-ROM, DVD-recordable (DVD-R), DVD-random access memory version 1.0 (DVD-RAM1), DVD-RAM2, DVD-RW and DVD+ReWritable (DVD+RW) (a rewritable DVD standard settled by Sony Corporation, Philips Electronics, Hewlett Packard, Mitsubishi Chemical Industries, Ltd., Ricoh Co., Ltd. and Yamaha Motor Co., Ltd. and called Phase-Change ReWritable).
As some of these plural types of optical discs are different in a method of recording and reproducing information, each optical disc is required to be switched. Therefore, the type of an optical disc to/from which information is to be recorded or reproduced is required to be discriminated.
For reference examples of discriminating an optical disc, Japanese unexamined publication No. H11-306650, No. H10-334574, No. H9-44982 and No. H8-249801 can be given.

This patent is subject to a terminal disclaimer.

Disc discriminating method and information reproducing apparatus using thereof


Embodiments of the invention provide a magnetic disk drive that allows members to be mounted onto a base simply and accurately. In one embodiment, a magnetic disk drive comprises: a base; a disk assembly including at least one magnetic disk and mounted rotatably on the base; and an actuator assembly including at least one actuator having a magnetic head and mounted swingably on the base. The base is formed with a guide. The guide functions to guide, when a member to be disposed on the base is to be mounted, the member from a corresponding initial placement position of the member on the base to a target position, at which the member is to be disposed. Further, the guide includes a positioning portion, against which the member abuts at the corresponding target position.

The present invention relates generally to a magnetic disk drive and, more specifically, to a base mounted with members forming the magnetic disk drive.
A magnetic disk drive, such as a hard disk drive, is formed by including a variety of members, such as a magnetic disk, a magnetic head, and the like. Many of these members forming the magnetic disk drive are mounted on a base that serves as a housing of the magnetic disk drive.
Conventionally, assembly robots, for example, have been used for mounting these members on the base. The assembly robot accurately transports each of the different members to a specified location and places the member correctly therein. See, e.g., Patent Document 1 (Japanese Patent Laid-open No. 08-329655).

Hitachi Global Storage Technologies Netherlands B.V.


An industrial expert system for use in designing a plant system or device thereof and in fault detection, includes a knowledge base having a rules-section for describing deductive inference rules. Also included is an expression-section for describing a calculation formula of equality with either a right side or left side being a simple term having a value and the other side being polynomial including known functions. Also included is an attributes-section for declaring the nature and value of each of the attributes cited in calculation and inference and for declaring parameters for controlling communication between a process of deductive inference and a calculation process according to calculation formulas. A deductive inference engine performs deductive inferencing on the basis of the rules, calculation formulae and the attributes stored in the knowledge base. This system uses a simple construction to efficiently perform detection of fault logic by using specific formula or calculation of parameters representing features of a fault which are to be performed during an inference.

Inference engines of conventional expert systems utilize a frame and production rules. The term "frame" as used herein means a mechanism for chaining a kind of data base defining mutual relations between attributes concerning facts or observations, etc., or describing definitions, etc., of values of such attributes; "production rules" means a mechanism for chaining deductive inferences.
Deductive inference is performed by citing a list of knowledge for inference "if A, then B", that is, rules.
Rules can be described as follows:
a) If "hot", then "possibly fever".
b) If "temperature>38.degree. C.", then "possibly fever".
In rule a) the truth or falsehood of a conclusion is decided according to truth or falsehood of establishment of phenomenon in a conditional portion. In rule b) truth or falsehood of a conclusion is decided according to whether a value of phenomenon cited in the conditional portion exceeds a certain fixed threshold value.
Inference is performed by tracing, syllogistically, in other words in a chain, rules in a knowledge base listing rules. In this case, a rule is described SO that a final conclusion of a given problem is obtained at the end of inference chain.
In some cases, such as in design planning or fault detection for a plant, all processes up to a final conclusion may not necessarily be expressed by rules or frames.
Thus, for design and planning, an index is calculated representing an amount of some merit or some risk for a condition which is to be cited in a following inference. This is frequently done by citing some simple evaluation formulae in a chain depending upon the content of the intermediate conclusion.
In fault detection applications in order to check the possibility of a fault postulated as an intermediate supposition obtained from observation or investigation, specific formulae are frequently used in a chain together with data. Such data include observation/investigation data and specification/design data which is used to confirm whether or not a fault satisfies a formula describing it phenomenally, or which is used to calculate parameters representing a feature of the fault.
However, it is difficult for a conventional inference engine to realize a process in which the execution of a deductive inference chain is interrupted and a calculation is performed by citing specific formula in a chain. In order to accommodate this, processing must temporarily exit from an inference engine described by a language such as LISP, etc., and an operation process mechanism described by a language such as FORTRAN, etc., (i.e., a language different from that of the inference language). This leads to an increase in the processing time and a complicated mechanism, resulting in a system whose utility is low.
One feature of an expert system is causing knowledge in a knowledge base which is an object of inference to be realized. Knowledge represented by a calculation formula cannot be actualized like a program of an existing language such as FORTRAN, even by an expert system capable of calculating in some way. This is because a conventional knowledge base calculation formula does not adequately express an engineer's knowledge. Even if a conventional knowledge base actualizes inference knowledge, the fact that the calculation formulas have both actual meanings and also meanings based on technical evaluation, is ignored.
Though calculation formulas include the relevant technical content, there is a limit on the accuracy of mathematical expression of the technical content due to the accuracy of modelling. Accuracy of mathematical expression determines the accuracy of a calculation result according to the formula currently involved as well as the accuracy of the constants and variables used therein.
Though every formula has an accuracy of mathematical expression dependent upon the problem to be handled. Conventional expert systems have no function for describing this accuracy and for evaluating the accuracy of the calculation results using such a description.
Considering the technical meaning of mathematical formula and the description of knowledge expressed by the formula, units of constants and variables used in the formula must be attached as knowledge, since values of constants and variables (attribute values) themselves differ with different units. However, this is not actualized in a conventional systems.
For such constants and variables, an expert in a technical field has "typical values" as his knowledge. This is actualized in the conventional system as default values. Moreover, there is an "existing range" of such constants and variables that is the expert's knowledge in the field. The expert has as his knowledge an "existing range" from which, when a value outside this range is obtained, he can decide the value as being an "erroneous measurement" or "erroneous calculation".
However, the conventional system does not do this. That is, a conventional calculation system including an expert system is not capable of expressing the background technical knowledge of such calculation formula, knowledge of accuracy of mathematical expression in the formula and knowledge such as the "unit" of a constant and a variable and "existing ranges of value" inherent to the formula.
This lead to problems including a lack of capability of knowledge expression in the knowledge base, a lack of ability of the expert system to function with the knowledge base and a limited expansion range of adaptation and actual application.
An object of the present invention is to provide an industrial expert system capable of performing, a calculation of an index according to an evaluation formula during rule-based inferencing of plant design and planning, detection of the existence of a fault according to a specific formula during rule-based inferencing of fault detection and calculation of parameters representing features of a fault.
Other objects of the present invention are to improve the description capability of a knowledge base, to facilitate obtaining knowledge and to improve adaptation, adaptation range and the inferencing capability of the expert system. This is accomplished by making a description form of listed calculation formula the calculation formulas describing portions of a knowledge base, which is calculated by a calculation mechanism according to the present invention. This approach is as close to "storage form of expert" or "description form on technical material expert usually uses" as possible, in the same sense that a rule description is made as close to expert knowledge as possible.
A further object of the present invention is to further improve the description capability of the knowledge base by providing expressions of knowledge of expression accuracy of mathematical formula and knowledge of "unit" of constants and variables and "existing range of values", to further improve the capability of expert system.
According to the present invention, these objects are achieved by an industrial expert system for use in designing a plant and in detecting faults therein. The expert system having a knowledge base including a rules-section describing rules of deductive inference, an expressions-section having values corresponding to calculation results of a simple term corresponding to either a right side or left side of equation and describing the other side as a polynomial including a known function. The system also has an attributes-section declaring various natures and values of attributes used in inferencing and calculations and declaring control parameters passing between a deductive inference process and calculation process according to calculation formulae, and a deductive inference engine for performing deductive inference on the basis of the rules stored in the knowledge base, calculation formula and attributes.
According to the expert system constructed in this manner, deductive inference is performed by the deductive inference engine on the basis of the rules stored in the knowledge base, the calculation formula and the attributes. Therefore, the detection of faulty logic by means of specific formula and the calculation of parameters representing the fault during inferencing, and can be processed.
The expressions-section takes the form of a list of calculation formula with formula numbers. The calculation formulas take the form of equality and either the left side or right side thereof is a result of calculation in the form of a simple term. The other side describes an operation formula for obtaining the result. The operation formula is a general polynomial and may include operational symbols such as addition, subtraction, multiplication, division, exponential, parenthesis and known functions such as sine and cosine, etc. Therefore, the description of an operational formula takes a general form which can be described even by a person who has no knowledge of a computer.
For simplicity of description, the calculation result is placed on the right side of a formula and an operational term is placed on the left side .


A network device includes packet processing circuitry and queue management circuitry. The packet processing circuitry is configured to transmit and receive packets to and from a network. The queue management circuitry is configured to store, in a memory, a queue for queuing data relating to processing of the packets, the queue including a primary buffer and an overflow buffer, to choose between a normal mode and an overflow mode based on a defined condition, to queue the data only in the primary buffer when operating in the normal mode, and, when operating in the overflow mode, to queue the data in a concatenation of the primary buffer and the overflow buffer.

Computer systems often use queues for communication between processes. The queues may be implemented as circular memory buffers.
U.S. Pat. No. 5,873,089 describes a data handling system in which a circular queue formed in a paged memory is used to buffer the transfer of data items between a producer entity and a consumer entity. The producer entity maintains a tail pointer into the queue to indicate the storage location next to be written to; similarly, the consumer entity maintains a head pointer to indicate the storage location next to be read. Since the head and tail pointers may point to different memory pages and these may not have been assigned in a contiguous block to the circular queue, the derivation of queue status information using the head and tail pointers is complex. To simplify this task, the producer and consumer entities maintain producer and consumer indexes for the next write and read positions based on a logical view of the queue as a circular continuum of storage locations.
PCT International Publication WO 1998/036534 describes a split-queue architecture and method of queuing entries to a three part queue. The first part of the queue is a write side in which entries to the queue are received. The second part of the queue is a read side from which entries exit the queue after flowing through the queue. Entries normally flow from the write side to the read side. An overflow area, located off-chip in an external memory, forms part of the queue on an as needed basis to store entries from the write side when the read side no longer has capacity to accept more entries from the write side. When the read side regains capacity to accept more entries, the overflow area transfers its entries to the read side.


Hybrid Super Threshold (SupVt) circuits are CMOS circuits that can function in two different operation modes: a normal operation mode and a SupVt power saving mode. At normal operation mode, a hybrid SupVt circuit operates in the same ways as typical CMOS circuits. At SupVt mode, the standby leakage current of the circuit is reduced significantly, while the circuit still can function at high speed. Typically, most parts of a hybrid SupVt circuit stay in power saving mode. A circuit block is switched into normal operation mode when it needs to operate at full speed. The resulting circuits are capable of supporting ultra-low power operations without sacrificing performance.

The present invention relates to low power electrical circuits, and more particularly to low power short channel Metal-Oxide-Semiconductor (MOS) circuits.
Complementary Metal-Oxide-Semiconductor (CMOS) is a technology for constructing Integrated Circuits (ICs). CMOS technologies are used in microprocessors, microcontrollers, Static Random Access Memory (SRAM), Application Specific Integrated Circuits (ASIC), and wide varieties of electrical circuits. The word "complementary" refer to the fact that the typical design style with CMOS uses complementary pairs of p-channel and n-channel metal-oxide-semiconductor Field Effect Transistors (FETs). Since one transistor of the pair is always off, the series combination draws significant power only momentarily during switching between on and off states. Consequently, CMOS devices do not waste as much power as other forms of logic, such as Transistor-Transistor Logic (TTL) or N-channel Metal-Oxide-Semiconductor (NMOS) logic, that normally have significant standby leakage current even when not changing state. By definition, "standby leakage current" is the current flowing through the power supply of a circuit when the circuit is not changing state. The standby leakage currents of CMOS circuits are typically much lower than that of other types of circuits. It was primarily for this reason that CMOS became the most used technology to be implemented in integrated circuits.
As IC technologies advanced, the channel lengths of MOS transistors have been reduced. Currently, transistors with channel length as short as 22 nanometers (nm) have been manufactured. The standby leakage currents of CMOS circuits increase rapidly with decreasing channel lengths of CMOS transistors. For CMOS circuits using transistors with channel lengths longer than 200 nm, the standby leakage currents of the CMOS circuits are typically negligible. On the other hand, short channel CMOS circuits can waste significant power even when the circuit is not changing state. Consequently, it is often necessary to provide power saving methods to reduce standby leakage currents for short channel CMOS circuits.
Currently, most of power saving methods are controlled by logic circuits called power management units. A prior art Power Management Unit (PMU) monitors the activities of circuit blocks, and turns off the power supply of a circuit block that is not in use in order to save power. FIG. 1(a) is a flowchart showing typical operations of a prior art PMU, and FIG. 2(a) is a timing diagram showing the power supply voltages of a circuit block controlled by a prior art PMU. At normal operation conditions, the substrate terminals and the source terminals of the p-channel transistor that are connected to the power source are connected to a power line at voltage Vdd, and the n-channel substrate terminals and the source terminals of n-channel transistors that are connected to power source are connected to a ground line at voltage Vss; the power supply voltage (Vpower) is equal to (Vdd−Vss) and it is typically set at a standard voltage (Vstd). Each generation of CMOS technology is optimized for a particular standard voltage. For examples, the standard voltage for 180 nm technology is typically 1.8 volts, Vstd is typically 1.2 volts for 130 nm technology, Vstd is typically 1.0 volt for 90 nm technologies, and so on. The prior art PMU monitors the activities of the whole circuit to determine whether a particular circuit block needs to work or not. If the circuit block needs to work, it stays in full power, which means that Vpower applied on the circuit block stays at Vstd. If a circuit block is no longer needed to work, the PMU can shut down the circuit block to save power. For example, the PMU found that starting from time T1 in FIG. 2(a), a circuit block is no longer needed. Typically, a prior art PMU cannot turn off the power immediately at time T1. When the power supply of a circuit block is turned off, the data stored in the volatile memory devices inside the circuit block can be lost. When the power is turned back on, the circuit may not return to previous state because the contents in memory devices can be different after power up. Examples of volatile memory devices include Static Random Access Memory (SRAM), Content Addressable Memory (CAM), registers, latches, flip-flops, and so on. It is typically necessary to store the contents of volatile memory devices before shutting down the power. As shown in FIG. 1(a), when the PMU determines to shut down a circuit block to save power, it typically needs to store data in memory devices into nonvolatile memory before turning off the power of the circuit block to save power. As shown in FIG. 2(a), the circuit block is not in use since time T1, but the PMU need to maintain in full power on the circuit block until time T3. The storage time (T3−T1) is used to store contents in memory devices into nonvolatile memory devices such as hard discs. This procedure can be time consuming, and it can burn a lot of power. After time T3, the PMU can shut down the power, and Vpower gradually approaches zero, as shown in FIG. 2(a). During this period of time, the PMU continues to monitor the activities of the whole circuit to determine whether the circuit in power saving mode is needed or not. If the circuit block is not needed, it can stay in power saving mode, as shown in FIG. 1(a). If the circuit block is needed, the PMU restarts the circuit block by turning on its power at time T2, as shown in FIG. 2(a). However, the circuit block is not ready to function until the data are restored back to the memory devices in the circuit block at time T4, as shown in FIG. 2(a). This recovery time (T4−T2) can be long, and the circuit block can consume a lot of power during recovery. After time T4, the circuit block is ready to restart normal operations, as illustrated in FIG. 2(a).
The operation of prior art PMUs can be very complex, especially when a circuit block comprises many memory devices. The procedures to shut down and restore a circuit block can be time consuming, and the processes can consume a lot of power. The PMU itself also can consume significant power. It is therefore highly desirable to develop power saving modes that support fast recovery time.
In U.S. Pat. No. 7,782,655 and in U.S. Pat. No. 8,164,969, Shau disclosed "Hybrid Subthreshold (SubVt) Circuits" that solved many problems of prior art power management units. FIG. 1(b) is a flowchart showing typical operations of a prior art Hybrid SubVt circuit. FIG. 2(b) is a timing diagram showing the voltages applied on a circuit block controlled by a prior art Hybrid SubVt controller, where NVps is the power connection to the source terminals of p-channel MOS transistors that are connected to power source, NVpb is the electrical connection to the substrate terminals of p-channel MOS transistors, NVns is the ground connection to the source terminals of n-channel MOS transistors that are connected to power source, and NVnb is the electrical connection to the substrate terminals of n-channel MOS transistors. At normal operation, Hybrid SubVt circuits operates in the same condition as typical CMOS circuits, where NVpb is connected to NVps at power supply voltage Vdd, NVnb is connected to NVns at ground voltage Vss, and the power supply voltage (Vpower) equals standard voltage (Vstd), as shown in the timing diagram in FIG. 2(b). A Hybrid SubVt controller monitors the activities of the whole circuit to determine whether a particular circuit block needs to work or not. If the circuit block needs to work, then it stays in full power, which means that Vpower of the circuit block stays at Vstd. If a circuit block is no longer needed to work, the circuit can be placed into subthreshold power saving mode, as shown in FIG. 1(b). At subthreshold power saving mode, the power supply voltage (Vpower) is reduced to a level that is lower than the threshold voltages (Vt) of the MOS transistors in the circuit block. Under SubVt mode, the standby leakage current of the circuit can be reduced by 99% or more relative to the standby leakage current of the same electrical circuit under normal operation mode, while all the memory devices still can hold their data. It is therefore possible to get into SubVt power saving mode immediately without the need to store the data in memory devices into nonvolatile memory devices. For example, the controller found that starting from time T1 in FIG. 2(a) the circuit block is no longer needed. Right after T1, the circuit can get into SubVt power saving mode, where NVpb is pulled up to a voltage Vpb that is higher than Vdd, NVnb is pulled down to a voltage Vns that is lower than Vss, the voltage on NVps is allowed to drop no lower than a voltage Vpt, and the voltage on Vns is allowed to rise no higher than a voltage Vnt, as shown in FIG. 2(b). The voltage difference (Vpt−Vnt) is controlled to be lower than Vt, so that the circuit block is under SubVt mode. During this period of time, the controller continues to monitor the activities of the whole circuit to determine whether the circuit in power saving mode is needed or not. If the circuit block is not needed, it can stay in SubVt mode, as shown in FIG. 1(b). If the circuit block is needed, the controller restarts the circuit block by going back to normal operation mode at time T2, as shown in FIG. 2(b). Since there is no need to restore data from nonvolatile memory devices, the circuit block can go back to normal operation mode instantly after time T2, as shown in FIG. 2(b).
Shau's hybrid SubVt circuits significantly reduced the wastes in power during storage time and recovery time. However, hybrid SubVt mode is applicable typically when the circuit block does not need to do any work. It is highly desirable to develop a power saving mode that is applicable on circuit blocks that need to do work.

Low power high performance electrical circuits


A static random access memory comprises a memory cell array, a plurality of bit lines provided in correspondence to said plurality of memory cell columns, a first decoder for selecting a memory cell column, a second decoder for selecting a memory cell groups included in the selected memory cell column, and a third decoder supplied for selecting a memory cell included in the selected memory cell group. Each memory cell comprises a flip-flop circuit that is formed of thin film transistors. Each memory cell group includes a predetermined number of the memory cells, a sub-bit line extending over the memory cells included in the memory cell group, a first selection circuit connected to the sub-bit line and further to the bit line that corresponds to the selected memory cell group and a second selection circuit connected to the sub-bit line and the bit line that corresponds to the selected memory cell group. The first selection circuit is activated in response to an output signal of the second decoder for causing a voltage change in the bit line in response to a voltage level on the sub-bit line, and comprises bulk transistors having diffusion regions formed in a semiconductor substrate. The second selection circuit comprises a thin film transistor that is turned on in response to a second output signal of the second decoder for connecting the bit line and said sub-bit line electrically.

The present invention generally relates to semiconductor devices, and more particularly to a static random access memory that uses a thin film transistor (TFT) for improved integration density.
The static random access memory (SRAM) is a random access memory that stores information by the latching operation of a flip-flop circuit. The device does not require periodical refreshing contrary to the dynamic random access memory (DRAM), and is suitable for a memory that is required to have a high speed access. For example, the SRAM is used extensively for the cache memory of computers. On the other hand, SRAMs have a problem in the integration density, as they use a flip-flop circuit that includes a number of transistors, for the memory cells.
FIG. 1 shows the circuit diagram of a typical SRAM that uses transistors 2, 3, 9 and 10 that form a flip-flop circuit 8. There, the transistors 2 and 3 are formed of an n-channel MOS transistor while the transistors 9 and 10 are formed of a p-channel MOS transistor. Further, transfer gate transistors 6 and 7 are provided in correspondence to complementary bit lines BL and /BL as usual, wherein the transistors 6 and 7 are activated by a word enable signal on a word line WL.
In the construction of FIG. 1, it should be noted that all the transistors 2, 3, 6, 7, 9 and 10 are formed of so-called bulk transistors that have a channel region as well as source and drain regions formed in a single crystal substrate of a semiconductor material such as silicon. In other words, the are disposed on a planar surface of the substrate with an isolation region formed between the transistors. Typically, the isolation region has a size of a few microns. Thus, the SRAM of FIG. 1 has suffered from a problem of low integration density as compared with the DRAMs.
In order to improve the integration density of conventional SRAMs, a construction as shown in FIG. 2 is proposed. There, p-channel MOS transistors 4 and 5 that form a flip-flop circuit 1 together with the n-channel MOS transistors 2 and 3, are replaced by polysilicon resistors 4 and 5 that are provided at a level above the transistors 2 and 3. This prior art device, however, has a problem of increased power consumption as the current flows continuously through the flip-flop circuit 8.
FIG. 3 shows a circuit diagram of another prior art SRAM that uses a flip-flop circuit 11, wherein the resistors 4 and 5 of the circuit of FIG. 2 are replaced by p-channel thin film transistors (TFT) 12 and 13. The p-channel TFT is a transistor that has a channel region comprised of a polysilicon strip. There, the polysilicon strip is doped to the p-type in correspondence to the source and drain regions except for a channel region that is formed as an undoped region located between the source and drain regions. Further, a gate electrode is provided above the channel region with an intervening insulation layer. It will be noted that such a TFT, formed on a polysilicon strip, does not need the substrate and can be provided easily into a multi-level configuration. Thereby, one can increase the integration density of the SRAM significantly.
FIG. 4 shows a circuit diagram that improves the integration density of the circuit of FIG. 3 further.
Referring to FIG. 4, it will be noted that the SRAM uses a flip-flop circuit 14 that in turn includes n-channel TFTs 15 and 16 in place of the transistors 2 and 3 of the flip-flop circuit 11 of FIG. 3. The n-channel TFT uses a polysilicon strip for the channel region similarly to the p-channel TFT except that the polysilicon strip is doped to the n-type in correspondence to the source and drain regions. Further, the transfer gate transistors 6 and 7 are also replaced by n-channel TFTs 17 and 18, respectively. By constructing the flip-flop circuit 14 as well as the transfer gate transistors 17 and 19 entirely from the TFT, one can increase the integration density further.
On the other hand, the device of FIG. 4 has a drawback, associated with the characteristic of the currently available TFT, in that it takes a relatively long time for changing the voltage level of the bit lines BL and /BL when reading or writing data. It should be noted that the bit lines BL and /BL have a relatively large parasitic capacitance. On the other hand, currently available TFTs can provide only a limited turn-on current as compared with the bulk transistors used in the conventional SRAMs. In a typical example, a TFT transistor shows the turn-on current of about 10 .mu.A, while a typical bulk MOS transistor shows the turn-on current of 1-2 mA. Obviously, this reduced turn-on current is caused by the scattering of carriers at the grain boundary of polysilicon. Thereby, the time needed for discharging the parasitic capacitance of the bit lines becomes inevitably longer, and the operational speed of the SRAM is slowed down as a result.

Static random access memory that uses thin film transistors in flip-flop circuits for improved integration density


An electronic gaming system conducts a reel-based electronic wagering game, in which jackpot upgrade symbols are added to one or more reel strips based on the occurrence of one or more reel upgrade symbols in the wagering game. In the exemplary embodiment, jackpot upgrade symbols are added to a third reel strip based on the occurrence of one or more reel upgrade symbols on a first reel strip, and to a fifth reel strip based on the occurrence of one or more reel upgrade symbols on the third reel strip. In addition, jackpot upgrade symbols are added to the first and third reel strips to replace the one or more reel upgrade symbols occurring thereon.

Electronic gaming machines (EGMs), or gaming devices, provide a variety of wagering games such as, for example, and without limitation, slot games, video poker games, video blackjack games, roulette games, video bingo games, keno games, and other types of games that are frequently offered at casinos and other locations. Play on EGMs typically involves a player establishing a credit balance by inserting or otherwise submitting money and placing a monetary wager (deducted from the credit balance) on one or more outcomes of an instance, or play, of a primary game, sometimes referred to as a base game. In many games, a player may qualify for secondary games or bonus rounds by attaining a certain winning combination or other triggering event in the base game. Secondary games provide an opportunity to win additional game instances, credits, awards, jackpots, progressives, etc. Awards form any winning outcomes are typically added back to the credit balance and can be provided to the player upon completion of a gaming session or when the player wants to "cash out."
Slot games are often displayed to the player in the form of various symbols arranged in a row-by-column grid, or "matrix." Specific matching combinations of symbols along predetermined paths, or paylines, drawn through the matrix indicate the outcome of the game. The display typically highlights winning combinations and outcomes for ready identification by the player. Matching combinations and their corresponding awards are usually shown in a "pay-table" that is available to the player for reference. Often, the player may vary his/her wager to included differing numbers of paylines and/or the amount bet on each line. By varying the wager, the player may sometimes alter the frequency or number of winning combinations, the frequency or number of secondary games, and/or the amount awarded.
Typical games use a random number generator (RNG) to randomly determine the outcome of each game. The game is designed to return a certain percentage of the amount wagered back to the player, referred to as return to player (RTP), over the course of many plays or instances of the game. The RTP and randomness of the RNG are fundamental to ensuring the fairness of the games and are therefore highly regulated. The RNG may be used to randomly determine the outcome of a game and symbols may then be selected that correspond to that outcome. Alternatively, the RNG may be used to randomly select the symbols whose resulting combinations determine the outcome. Notably, some games may include an element of skill on the part of the player and are therefore not entirely random.

Electronic wagering game in which jackpot upgrade symbols are added to one or more reel strips

Aristocrat Technologies Australia Pty Limited


A method and system are disclosed in an electronic payment network, for associating a payment card of a cardholder with a personal computing device of the cardholder, then authenticating the payment card in electronic transactions processed in the network. The card and a device activation code are input to the cardholder device by the cardholder, then communicated sent to a remote server for obtaining a card token. The server generates a device token and an authorisation token, stores the generated tokens together with the card token, and sends the card and device tokens to the cardholder device for storage. Whenever a transaction is processed in the network, the payment card is authenticated by inputting authenticating data to the cardholder device for generating an authorisation token, which is sent to the server with the stored card and device tokens, for a matching operation against the card, device and authorisation tokens at the server.

Technical developments are ongoing in the electronic payments industry to implement payment form factors that increase protection against various forms of fraud. In this context, the three main card schemes Europay, Mastercard and Visa ('EMV') created the original EMV technical standard for payment cards, which is now managed by EMVCo and aspects of which are based upon ISO/IEC 7816 for contact cards and ISO/IEC 14443 for contactless cards.
Payment cards complying to the EMV standard are variously known as smart cards, chip cards and IC cards and store data on integrated circuits rather than magnetically on a stripe. EMV cards were originally contact cards insertable into readers interfacing a point of sale ('PoS') terminal or automated teller machine ('ATM') with the card chip, and are increasingly being replaced with contactless cards that can be read by a PoS or ATM over a short distance using radio-frequency identification ('RFID') technology.
EMV cards provide substantial protection for card-present transactions, i.e. those transaction conducted between a cardholder and a merchant at a till or the like and wherein the card is physically interfaced with a PoS, but there remains a need to minimise unauthorised use of cardholder account data and to reduce fraud opportunities for card-not-present transactions, typically those conducted over the phone or the Internet, and emerging transaction environments which combine elements of card-present and card-not-present transactions, such as contactless transactions at a retail location.
A recent development path that shows promise for solving the above issue is payment tokenisation systems. In most of these systems, a payment token is implemented as a surrogate replacing the number uniquely identifying a payment card within electronic payment networks, which is known as the Primary Account Number (PAN) of the card. Accordingly, it is known to use payment tokens in Cardholder Verification Methods (CVMs), including signature, online and offline PIN, and outside CVMs. For example, if an online PIN is used with a payment token, in accordance to ISO 9564-1 PIN Block Format 0 or Format 3, the PIN block would include the payment token in lieu of the card's PAN. In this context, token service providers are responsible for ensuring that the issuer of the payment card receives the PIN block with the PAN or payment token, as appropriate, for validation.
In these systems, a process must be followed to ensure that the payment token is replacing a PAN which is legitimately being used by the token requestor. This process is known as Identification and Verification (ID&V) and is performed each time a payment token is requested. Different types of ID&V may be performed, resulting in corresponding levels of token assurance, wherein no or minimal ID&V performed would result in a low assurance payment token, but a high level of ID&V would result in a high assurance payment token.
Higher levels of ID&V rely on multifactor authentication techniques, typically 2 factors currently and, in that context, the three domain ('3D') Secure authentication protocol first deployed by Visa under the name 'Verified by Visa' and since adopted by other Card Schemes such as MasterCard and its MasterCard SecureCode, can be used as one of the two factors. A fundamental requirement of the 3-D Secure protocol is the enrolment of a payment card in the service prior to the successful completion of an authenticated transaction. This can be implemented as a stand-alone process or integrated with an online retail event, and its purpose is both to validate the identity of the cardholder prior to use of the payment card and to assign a means of authentication to that card. The cardholder is presented with a user interface, typically a succession of at least two secure browser pages, before the enrolment process is complete and a transaction can be completed. However, the card industry reports that as many as 52 percent of users opt out of 3-D Secure participation when first presented by the user interface, and an additional 18 percent close the activation window altogether. Each cardholder opting out of 3-D Secure when prompted to enroll, is an example of a cardholder being inconvenienced by the enrolment-based system, eventually leading to dissatisfaction and abandonment of purchases by legitimate consumers.
Accordingly, there is a clear requirement for improving multifactor authentication of a payment card during the distributed processing of an electronic transaction.


A photographic camera comprises a chamber for receiving a cartridge containing a filmstrip, a film exposing gate, and movable blocking means for sealing a film passage to the exposing gate which must be moved out of the way to permit a filmstrip from a cartridge in the chamber to be advanced to the exposing gate. The blocking means is positioned inside the chamber over a film egress opening to the film passage to be moved to uncover the film egress opening by a cartridge during insertion of the cartridge into the chamber.

1. Field of the Invention
The invention relates generally to the field of photography, and in particular to a photographic camera with an interior dust seal.
2. Description of the Prior Art
U.S. Pat. No. 5,142,316, issued Aug. 25, 1992, discloses a photographic camera comprising a loading chamber for receiving a 35 mm cartridge containing a filmstrip, a film exposing gate, and movable light-blocking means for normally sealing a narrow film passage connecting the chamber and the exposing gate but which can be moved out of the way to permit the leading end of a filmstrip from a cartridge in the chamber to be advanced to the exposing gate. The light-blocking means is a pair of elastic members positioned within the narrow film passage in urged contact with each other to be pushed aside by the leading end of the filmstrip when the filmstrip is advanced from the cartridge.
3. Problem to be Solved by the Invention
In U.S. Pat. No. 4,870,437, it is taught that the leading end of a filmstrip advanced from a cartridge in the chamber is the preferred element for opening the light-blocking means to permit film access to the film exposing gate. A problem may occur, however, in that the filmstrip may not have sufficient longitudinal rigidity to force the leading end to push aside the elastic members. Consequently, a film jam can result.

Photographic camera with interior dust seal


A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type and a second region of the second conductivity type in the substrate, spaced apart from the first region, thereby defining a channel region therebetween. A plurality of floating gates are spaced apart from one another and each is insulated from the channel region. A plurality of control gates are spaced apart from one another, with each control gate insulated from the channel region. Each of the control gate is between a pair of floating gates and is capacitively coupled to the pair of floating gates. A plurality of select gates are spaced apart from one another, with each select gate insulated from the channel region. Each select gate is between a pair of floating gates.

Non-volatile memory integrated circuit chips are well known in the art. See for example U.S. Pat. Nos. 5,029,130 and 6,151,248. One form of a non-volatile memory integrated circuit chip is a "NAND" flash memory device in which a string of serially connected non-volatile memory cells are grouped in a NAND flash memory structure.
Referring to FIG. 1A there is shown a cross-sectional view of a prior art split gate NAND flash memory structure 10. (See "Split-Gate NAND Flash Memory At 120 nm Technology Node Featuring Fast Programming and Erase" by C. Y. Shu et al, 2004 symposium on VLSI Technology Digest of Technical Papers, p. 78–79). The NAND flash memory structure 10 is formed on a semiconductor substrate 12 of a first conductivity type. The NAND flash memory structure 10 has a first region 14 of a second conductivity type and a second region 16 of the second conductivity type in the substrate 12. The first region 14 and the second region 16 are spaced apart from one another to define a continuous channel region between the first region 14 and the second region 16. A plurality of floating gates (18A . . . 18N) are spaced apart from one another with each floating gate 18 positioned over a separate portion of the channel region and separated and insulated therefrom. The structure 10 further has a select gate 20 associated with each floating gate 18. The select gate 20 is positioned over another portion of the channel region, and is immediately adjacent to the associated floating gate 18 and is insulated therefrom. Finally, the structure 10 has a plurality of control gates 22 with each control gate 22 associated with a floating gate 18 and forming a stacked gate configuration with the associated floating gate 18.
Typically, the NAND gate structure 10 is formed in a column direction with the select gate 20 and the control gate 22 connecting the respective select gates and control gates in a row direction. A plan view of an array of such NAND structures 10 is shown in FIG. 1B.
The problem with the NAND structure 10 of the prior art is that it requires two row lines for each cell: one for the select gate 20 and one for the control gate 22. With two lines for each cell and where for non-volatile memory cells the lines must carry high voltages, there would be too many high voltage control lines required for the pitch of each cell. In addition, the NAND structure 10 is uni-directional in operation.
Memory arrays in which the adjacent rows/columns are electrically connected at ends of the array are well known. See, e.g. U.S. Pat. No. 6,825,084 (FIG. 2). Finally, control gates that are substantially T shaped positioned between a pair of floating gates and having a portion over a channel region, and capacitively coupled to the pair of floating gates is also well known in the art. See e.g. U.S. Pat. No. 6,151,248.
Accordingly, there is a need to reduce the line count per cell to thereby improve the pitch of the nonvolatile memory device.

Bidirectional split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing


A tape cassette winding apparatus that can accept either an audio compact cassette (ACC) or a digital compact cassette (DCC) that has a revolving drive arrangement for rotating the hub or reel of the cassette to load tape into the cassette. The winding apparatus has first and second winding shafts constructed to fit into an ACC hub or DCC hub. A moving assembly selectively moves the correct winding shaft into position to engage either an ACC hub or DCC hub. The revolving drive rotates the cassette hub to load tape into the cassette when the correct winding shaft has been selected and engaged in the cassette hub. A lid opening assembly is provided to open and close the hub protective lid on DCC's.

Heretofore, in order to mass produce cassettes having magnetic tape wound therein, for example, audio analog compact cassettes (hereinafter referred to as the "ACC"), there has been a method that can directly wind the magnetic tape into the cassette having a leader tape applied in advance, and another method in which the magnetic tape and the leader tape are wound on the hub or reel before it is put into the cassette.
A tape winding apparatus for mass production of cassettes in the former method was disclosed in, for example, Japanese Patent Application Laid Open Sho 51-89404. In this method, the cassette is held in place, and the leader tape is drawn out of the cassette and cut in half. One end of the cut leader tape is stuck to one end of the supplied magnetic tape. In turn, a winding shaft is fitted in with the hub of the cassette. The winding shaft is rotate to wind the magnetic tape onto the hub. When a predetermined length of magnetic tape is wound, the winding shaft is stopped from rotating. The magnetic tape is cut. The cut end of the magnetic tape is stuck to the other cut end of the leader tape. The magnetic tape and leader tape stuck together left out of the cassette is wound into the cassette by the winding shaft before the completed cassette is discharged. The process described above is repeated to produce numbers of cassettes.
There has been proposed a digital compact cassette (hereinafter referred to as the "DCC") along with recent development of the digital electronics technology. It is made in a shape similar to the ACC. However, the hub of the DCC is made to have the winding shaft inserted only in a single side direction, while that of the ACC can have the winding shaft inserted in any of the both directions. Also, the winding shaft for the ACC is shaped at its end for ease of insertion into the hub, but cannot be put into the hub of the DCC. The reason is that while for the ACC the winding shaft can be put through the cassette body from its thin end to a thick fitting portion, but for the DCC it cannot be put through to reach the fitting position. Further, for the DCC, holes for insertion of the winding shaft are closed by a sliding lid to protect the magnetic tape wound in the DCC. To revolve the hub in the DCC, the lid provided on one side has to be opened before the winding shaft is fitted in the hub. Further more, the magnetic tape is to be wound on one of the hubs in the cassette, but the ACC and the DCC are different in hub size to wind magnetic tape. For these reasons, conventional winding apparatus used for production of an ACC could not wind tape a DCC irrespective of their similar shapes.
In view of the foregoing, one object of the present invention is to provide a winding apparatus capable of producing either an ACC or a DCC in a single unit.
Another object of the present invention is to provide an improved winding assembly for production of both an ACC or DCC using of the conventional ACC winding apparatus.

Cassette adaptable tape widning apparatus and assembly


A neural network is trained to identify one or more features of an image. The neural network is trained using a small number of original images, from which a plurality of additional images are derived. The additional images generated by rotating and decoding embeddings of the image in a latent space generated by an autoencoder. The images generated by the rotation and decoding exhibit changes to a feature that is in proportion to the amount of rotation.

Few-shot learning is a training technique for neural networks which may be useful when it is difficult to obtain a sufficient quantity of training samples. Few-shot learning has been applied to classification problems in which a neural network is trained to categorize objects. However, few-shot learning has not typically been applied to solve regression problems. One such problem relates to estimating, from an input image comprising a representation of a person, a direction of the person's gaze.


A product and process for imparting decorative appliques to the sidewalls of tires during the curing operation are presented. In one embodiment, a spool of applique composite material is maintained for feeding into a tire mold or onto a transfer device, thereby defining a ring for vulcanization to a tire. The applique consists of a laminate received upon a carrier, the laminate having a first barrier layer and a congruent second decorative layer. The laminate is received by a tire sidewall between two grooves which serve to isolate the decorative layer from the tire itself. In another embodiment a laminate of white and barrier rubber stock is formed and then configured into a cylinder. A plurality of bands are cut from the cylinder then transferred to a fixture by reorienting the bands to conform to the angle of the sidewall of the tire at the point with which the band is to be adhered. The band is then transferred to a tire curing press which subsequently receives a green tire, with the band and tire being simultaneously cured, achieving a bond of the band to the tire by vulcanization.

The manufacture of tires is significantly complicated by the imparting of decorative bands into a tire sidewall to form a "white sidewall" tire. Presently, this is accomplished by fabrications using the extrusion and calendering of a number of black and white components which are subsequently combined into a decorative sidewall preassembly. All of the tire components, including the tire sidewall preassembly, are then applied in sequence to the tire building drum to form the green or uncured tire. Following the tire curing operation, the decorative sidewall side of the tire is carefully ground and buffed to expose the decorative sidewall area which was previously protected by a cover strip. These complex steps detrimentally effect the efficiency of the tire manufacturing process. Further, many interfaces produced in construction of the decorative sidewall tire effect the structural integrity of the tire and its durability and performance on the road.
It is generally known in the tire industry that the tire carcasses used for forming a blackwall tire are different from those employed in manufacturing tires having decorative features or "white sidewalls" thereon. Further, modern tires are designed with increasingly thinner sidewalls, such that the decorative portion of the sidewall is becoming an increasingly significant part of the tire sidewall structure itself. Since the decorative portion is typically less than optimum as a structural element, it is becoming increasingly difficult to manufacture modern tires having sidewalls with decorative features thereon. Previously known tires with decorative sidewalls have been characterized by a plurality of boundaries defining the different layers of the decorative structure, each boundary presenting an area for the development of a potential defect.
To obviate the shortcomings of the prior art, it has been proposed to replace the previously known sidewall decorative features with appliques of polymeric paint applied to stock blackwall tires after the curing operation on the tire. Such structures and techniques are taught in U.S. Pat. Nos. 4,767,481, 4,684,420, 4,699,193, and 4,684,431, all assigned to Bridgestone/Firestone, Inc. The appliques of these patents are quite thin, on the order of 0.003 inch and, accordingly, susceptible to damage by scrapping, scuffing, and the like. While the appliques are designed to be scuff resistant, and the tire receiving such appliques is configured to protect the same from scuffing, the inherent thin nature of the appliques gives rise to concern over damage resulting from use.
In the past, some attempts have been made to manufacture elastomeric appliques for use in the manufacture of whitewall tires. However, such prior techniques have proven to be time consuming and costly. Previously, single rings of an elastomeric material have been extruded upon a carrier for placement in a tire mold and for transfer by vulcanization to the tire during the curing operation. However, these prior attempts have not demonstrated an ability to be cost effective and reliable. Accordingly, there is a need for an automated method of producing whitewall appliques for vulcanization to a tire during the curing operation.

Apparatus for manufacturing tires with white sidewall appliques


Terminals and switching methods are provided. The terminal includes: a first component (11) connected to a second component (13) via a connection unit (12), the second component (13) being connected to the connection unit (12), and the first (11) and second (13) components being in a first relative position relationship when the connection unit (12) is in the first connection state, or in a second relative position relationship when the connection unit (12) is in the second connection state; a detection unit (14) configured to detect a relative position relationship between the first (11) and second (13) components, and generate a first detection result upon detection of the first relative position relationship, or a second detection result upon detection of the second relative position relationship; and a switching unit (15) connected to the detection unit (14) and configured to switch the terminal to a first operation state based on the first detection result, or to a second operation state based on the second detection result. The terminal includes a first operating system and a second operating system. The first operation state is an operation state in which the first operating system is primarily used, and the second operation state is an operation state in which the second operating system is primarily used.

Recently, with the rapid development of mobile internet, portable devices such as tablet computers are more suitable for the concept of mobile internet. The market of tablet computers expands explosively. Tablet computers are advantageous in portability and capability of providing better audiovisual experiences. However, conventional operating systems for tablet computers are very limited. The operating systems for traditional computers are typically used, which are designed for mouse and keyboard based operations and cannot take advantages of touch operations and thus cannot meet consumer's requirements.


The invention relates to a hydraulic steering facility for mobile systems, with a steering circuit for a steering facility and a working circuit for a working hydraulic system, whereby the steering circuit and the working hydraulic system are connected to a supply pump via a shared flow dividing valve and the flow dividing valve is connected to a load signal connection of the steering device. It is provided that the steering facility has an adjustable input choke that is connected via an inflow connection of the steering facility to the flow dividing valve, between the load signal connection and downstream of the input choke, a parallel circuit consisting of a choke and an adjustable second load signal choke is arranged, and the load signal connection is further connected via an adjustable first load signal choke to a return flow connection of the steering facility.

Hydraulic steering facilities are used in mobile systems that consist of a steering circuit and a working circuit, and which are both supplied by a shared pump, whereby the steering circuit takes priority.
Such systems mainly consist of a shared supply pump and a shared flow dividing valve and a steering facility and steering cylinder on the one hand, and a working circuit on the other. The flow dividing valve is spring loaded and obtains its control signal as a so-called load signal from the hydraulic steering facility. After this load signal, the flow dividing valve regulates its flow cross-sections in such a manner that the steering circuit is supplied as a priority and according to requirements, and the working circuit is supplied with excess pressure oil. It is known that the load signal can be provided statically or dynamically. Due to the high reactivity of a dynamic load signal, this type of provision is increasingly being used in practice.
Thus, for example, a generic steering facility with a dynamic load signal is known from EP 0 096 963 A2. This steering facility has a load signal path that branches off from the main flow line before the steering facility, leading towards the spring loaded side of the flow dividing valve on the one hand and, on the other, towards a separate connection of the steering facility, opens out again within the steering facility after the first adjustable choke into the main flow line, and at the same time leads to the return flow. In the portion of the load signal path that leads to the return flow, there is an adjustment choke that behaves inversely proportional to the first adjustable choke. This steering facility has the disadvantage that in order to maintain a priority, needs-oriented supply of the steering aggregate, including at high steering speeds, and thus with high flow quantities, a regulating spring with a relatively high spring rigidity is required. However, in the neutral position, i.e. when the steering facility is not actuated, it is constantly necessary to work against this strong regulating spring in order to supply the working circuit. This leads to high energy and performance losses of the hydraulic system.
DE 44 10 693 recommends a solution for improving the energy balance of the generic hydraulic systems. With the needs-oriented increase in pressure difference, which only takes effect during steering, the use of a weaker compression spring is possible. For this purpose, a choke and an adjustable load signal choke are switched in series in a secondary line.

Hydraulic steering facility with load signal


A drive system for a vehicle includes first and second electrical machines, a transmission, and an electrical energy supply. The transmission includes first and second gear sets, a connecting shaft coupled to the first gear set, a driveshaft configured to transport power from the electrical machines to a tractive element of the vehicle, and a clutch. The first gear set is coupled to the first electrical machine. The second gear set is coupled to the second electrical machine. Carriers of the first and second gear sets are coupled. The clutch selectively rotationally couples the carriers to the driveshaft when engaged. The drive system operates in an electric only configuration whereby the electrical energy supply provides electrical energy to at least one of the electrical machines to drive at least one of the connecting shaft and the driveshaft without a mechanical energy input to the transmission from an engine.

Traditional vehicle transmissions use gears and gear trains to provide speed and torque conversions from a rotating power source (e.g., an engine, a motor, etc.) to another device (e.g., a drive shaft, wheels of a vehicle, etc.). Transmissions include multiple gear ratios selectively coupled to the rotating power source with a mechanism that may also selectively couple an output to the various gear ratios.

Multi-mode electromechanical variable transmission


A system and method for providing real-time imaging for use in wide area space based surveillance utilizing an Optical Tera-bps Satellite (OPTSAT) network, including a plurality of OPTSATs, wherein an object is imaged with at least one surveillance aperture operatively linked to at least one of the plurality of OPTSATs is disclosed herein. The optical image data obtained the at least one surveillance aperture is processed in a one image processor, and displayed in a terminal capable of wirelessly transceiving information with the plurality of OPTSATs.

1. Field of the Invention
The present invention relates generally to a system and method for real-time imaging for use in wide area space based surveillance, and more particularly to a system and method for optically streaming satellite images utilizing an Optical Tera-bps Satellite (OPTSAT) Network.
2. Description of the Related Art
As remote sensing, more specifically, imaging observation satellites, increases in use and importance, a need to download large volumes of imagery data for processing by one or many users will also increase. For example, some applications for a representative imaging system featuring a multi-wavelength, satellite based, all-weather sensor constellation include: military applications, i.e., surveillance and defense systems; NASA applications for planetary exploration; Government applications for natural resource management, exploration, and conservation; disaster recovery surveillance; border surveillance for homeland defense; and commercial applications including food production status and news coverage from overhead.
Additionally, an imagery generation rate, especially for low-to-medium earth orbit satellite constellations, can be substantial. For example, an imaging satellite with a nominal 1 meter by 1 meter resolution, 16 bit digitalization, and coverage of a 2000 km wide swath with 4 wavelengths can generate about 0.6 Tera-bps (Tbps) of data (0.6×1012). With this data generation rate a constellation of, for example, 50 such satellites in a single orbiting plane generates 30 Tbps of image data. For 4 orbital planes, about 120 Tbps of data would be generated. If more wavelengths are used for each observation and with special extreme resolution modes, e.g., for identification of objects, the total generated data rate could approach 1 Peta-bps (1015 bps). Such extreme data rates could essentially provide nearly continuous coverage to a nominal 1 m by 1 m resolution over the more populated regions of the world or a planet being explored. However, conventionally, the down-linking and processing of such extreme data rates would be a major challenge.
In a related application entitled "Satellite-Based Mobile Communication System", filed in the United States Patent and Trademark Office on Dec. 12, 2002, and assigned Ser. No. 10/317,456, the contents of which are hereby incorporated by reference, an OPTSAT Network is disclosed, which addresses these technical challenges. In the OPTSAT Network, a first terminal transmits a data and/or voice information signal to a multiple beam scanning array transceiver located in the at least one satellite. The multiple beam scanning array receives the signal at either a micro-mirror bank or an optical switch bank. The satellite routes the signal to a second terminal through the multiple beam scanning array, utilizing a micro-mirror bank or an optical switch bank. The multiple beam scanning array is capable of handling pluralities of transmit and receive signals at any point in time, and capable of capacities of up to at least tera bits per second transfer rates.
Therefore, with a rise in the need for national security as well as an overall increase in satellite imaging, a need exists for a system and method for optically streaming satellite image signal data utilizing Optical Tera-bps Satellite (OPTSAT) technology.

System and method for real-time image control and processing for use in wide area space based surveillance


A telecine can be adapted to write video signals onto film. The film gate and flying spot scanner are enclosed in a light-tight shield and a four-segment (R, G, B, and clear) color filter wheel is interposed in the optical path between the scanner and the imaging optics. The CRT grid is modulated sequentially by R, G, and B components of the video signals which are preprocessed for shading and color errors. The film may be scanned a number of times under the modulation of each component, and displaced in both X and Y directions to increase resolution. In a preferred embodiment, the scan is displaced by 1/4-pixel for each of four scans to increase horizontal resolution and, for each horizontal displacement, four scans are performed, spaced 1/4-line apart, to increase vertical resolution. Thus, each frame is scanned 16 times per color component, and 48 times in all.

Telecine machines have been known for many years and are widely used in studios for converting cinematographic film into video signals suitable for broadcasting.
One type of telecine is the `flying spot` telecine in which the film is read by a raster on a cathode ray tube by scanning the film.
There is a general need for equipment which can convert film images into video signals for editing or the addition of special effects and then transfer the video signals back to cinematographic film.

Electronic film editing with system having telecine mode and film writing mode