An empirical diffraction based overlay (eDBO) measurement of an overlay error is produced using diffraction signals from a plurality of diffraction based alignment pads from an alignment target. The linearity of the overlay error is tested using the same diffraction signals or a different set of diffraction signals from diffraction based alignment pads. Wavelengths that do not have a linear response to overlay error may be excluded from the measurement error.

Semiconductor processing for forming integrated circuits requires a series of processing steps. These processing steps include the deposition and patterning of material layers such as insulating layers, polysilicon layers, and metal layers. The material layers are typically patterned using a photoresist layer that is patterned over the material layer using a photomask or reticle. Typically, the photomask has alignment targets or keys that are aligned to fiduciary marks formed in the previous layer on the substrate. However, as the size of integrated circuit features continues to decrease, it becomes increasingly difficult to measure the overlay accuracy of one masking level with respect to the previous level. This overlay metrology problem becomes particularly difficult at submicrometer feature sizes where overlay alignment tolerances are reduced to provide reliable semiconductor devices. One type of overlay measurement is known as diffraction based overlay metrology.

Diffraction based overlay linearity testing


The present invention provides a silver alloy for use in a reflection film in an optical recording medium, comprising silver as a main component, and at least one metal element as a first additive element having lower melting point than that of silver. Preferable first additive elements in the present invention are aluminum, indium, tin, bismuth, gallium, zinc, strontium, calcium and germanium. Further, second additive elements in the present invention are preferable if they contain at least one of elements comprising platinum, gold, rhodium, iridium, ruthenium, palladium, lead, copper, manganese, silicon, nickel, chrome, cobalt, yttrium, iron, scandium, zirconium, titanium, niobium, molybdenum, tantalum, tungsten, hafnium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, thulium, ytterbiumm, magnesium, and boron.

Silver is said to be the most preferable material for a reflection film being used in an optical recording medium, display or the like. The reason is that silver, in addition to a high reflectivity, is less expensive than gold which also has a high reflectivity. Especially, in the field of optical recording media, application of materials having higher reflectivity has been demanded as the field makes the transition to recordable and rewritable media such as CD-R/RW and DVD-R/RW/RAM. This is ascribable to a cause that organic dye materials have been widely used as a constituent material for a recording layer in recordable and rewritable media, and organic dye materials lead to a greater attenuation of laser, so that the attenuation should be complemented by improving the reflectivity of a reflection film.
In contrast, silver is poor in corrosion resistance, thereby has a drawback that corrosion changes the color of silver into black and will deteriorate the reflectivity. One of the factors contributing a corrosion of a reflection film is that for example the film has a poor corrosion resistance to an organic dye material which is applied to a recording layer in an optical recording medium although it varies according to equipment on which the film is applied, and as a result deterioration in reflectivity can be recognized after a long-term use. A reflection film in a display is likely to be corroded due to moisture or the like in the atmosphere.
There is further an issue of deterioration in reflectivity to a reflection film comprising silver caused by heat. Although it is not known exactly how heat deteriorates a reflectivity, a phenomenon has been confirmed that when a silver thin film is heated, the thin film gets local coagulation and exposes its substrate layer. Therefore, heat resistance is also required to a reflection film used for an optical recording media, plasma display or the like because the film is subjected to heat.
In order to address the above-discussed issue of deterioration in a reflectivity of a reflection film, developments of a silver alloy for use in a reflection film have been conventionally carried out in which both corrosion resistance and heat resistance are increased while a reflectivity is insured. Many of the reflection films have silver as a main component and are added by one or two or more various additive elements. For instance, it is disclosed 0.5-4.9 atm % of palladium has been added to silver. These silver alloys are said to have a good corrosion resistance, can maintain reflectivity under an environment of service, thereby being suitable as a reflection film. Refer to Patent Document 1 for details of the earlier technology. Patent Document 1: Japanese Patent Application Laid-open No. 2000-109943 With respect to the above-discussed silver alloys, some tentative improvements are recognized in terms of corrosion resistance and heat resistance. However, there is no guarantee that these silver alloys do not deteriorate at all under an environment of service. There is also no guarantee against deterioration in reflectivity, and so that materials capable of maintaining a higher level of reflectivity have been demanded.
In the field of optical recorders, red semiconductor laser (wavelength of 650 nm) is currently applied as a light source for recording, however practical use of blue laser (wavelength of 405 nm) has been in sight recently. Application of blue laser can insure a five- or six-fold storage capacity compared to the present optical recorders, so that it is considered blue laser-applied optical recorders will become mainstream in the next-generation ones. In this regard, the present inventors have confirmed the reflectivity of a reflection film will fluctuate in accordance with the wavelength of laser to be irradiated, and especially have confirmed irradiation of laser having a short-wavelength will cause deterioration in reflectivity irrespective of presence or absence of corrosion and the deterioration in reflectivity due to corrosion will be more substantial in degree than in a case of irradiation of laser having a long-wavelength. Thus, in order to manufacture recording media capable of addressing the future development of light sources for recording, it is desired a development of materials having a higher reflectivity with respect to irradiation of laser of short-wavelength band and further capable of maintaining reflectivity within a practical scope of use.
The present invention has been made against the above background, and relates to a silver alloy composing a reflection film in an optical recording medium or the like. It is an objective of the invention to provide a material capable of serving with the reflectivity kept not deteriorated due to a long-term use. Furthermore, the present invention provides a material having a higher reflectivity with respect to laser beams of short-wavelength.


A double-walled nested plant pot assembly having a base pot and an insert pot, the latter removably inserted into the base pot. The base pot has a bottom and tapering sides, an open top, a drain hole in the bottom, and legs on the bottom for elevating the base pot above a surface. Clearance holes are provided for plumbing to be disposed under the base pot bottom. A pipe fitting is disposed in the drain hole for connection with a drain line. Stand offs are formed in the base pot for supporting the insert pot. The shape of the insert pot conforms to the base pot with slightly smaller dimensions and includes a basin portion with a plurality of drain slots. When placed on the stand offs, the spaces between the basin portion, the insert bottom, and the interior sides and bottom of the base pot provide a volume through which water may drain from the insert pot into the base pot and through the base pot drain.

1. Field of the Invention
The present invention relates generally to agricultural and horticultural plant pots, and more particularly to plant pots employed in hydroponic plant growing systems, and still more particularly to a two-part separable double-walled nested hydroponic plant pot having an outside pot with a water inlet/outlet and basin drain in fluid communication with a subsoil irrigation/fertilization system.
2. Background Discussion
It is well-known to grow plants using hydrocultural growing techniques—"hydroponics." The systems and apparatus employed in hydroponics obviate the need for soils, conserve on water use, restrict chemical or other pollutants into the environment, facilitate harvesting, and ultimately result in superior plant specimens. It is also well known to use either sub-irrigation or top irrigation systems to water hydroponically grown plants, and to use either static or continuous flow irrigation for either type, as well as ebb-and-flow or flood-and-drain irrigation. The instant invention falls broadly into the top irrigation flood-and-drain type irrigation system, using a improved set of nested pots.

Double-walled nested plant pot assembly for hydroponic irrigation system


In a method of manufacturing CMOS transistors, a well that is of a second conductivity type is formed in a semiconductor substrate of a first conductivity type and is surrounded by a high concentration buried layer of the first conductivity type which completely extends around and below the well, and which also constitutes wells of the first conductivity type. The high-concentration buried layer is formed by a self-aligned process, and the potential of the buried layer can be easily fixed from the top of the semiconductor substrate so that a high degree of resistance is obtained to CMOS latch-up.

The importance of CMOS technology in the VLSI field has grown, as a result of requirements for a high noise margin and low power consumption. However as miniaturization has increased, serious problems have arisen with regard to preventing stray thyristor operation which causes the CMOS latch-up phenomenon to occur between mutually adjacent portions of an n-channel MOSFET and p-channel MOSFET, and with regard to maintaining a sufficient level of withstanding voltage between mutually adjacent elements.
Various forms of device configuration and manufacturing process have been proposed for overcoming these problems. These proposals include the use of a configuration containing wells, formation of a buried high concentration layer, and formation of a self-aligned channel stop at the edge of a well region.
Summaries of these various structures and methods will be given successively in the following, together with respective problems that have arisen with these.
Firstly, a method which uses an epitaxial structure over a high dopant concentration substrate will be described, referring to FIG. 17. This structure has been proposed by Yuan Taur et al, in the I.E.E.E. Transactions on Electron. Devices, Vol. ED-32, No. 2, February 1985 pp. 203-209.
In FIG. 17 numeral 51 denotes an n-type well, 52 is a high dopant concentration substrate (p.sup.+), 53 denotes a low dopant concentration epitaxial layer (p), 56 denotes an insulating isolation layer, 60 denotes a channel stop (p.sup.+). The region PA in the left half of the diagram is a p-channel transistor region, and region NPA in the right half of the diagram is an n-channel transistor region.
With this structure, a thin epitaxial layer 53 having a thickness of 4.5 .mu.m is formed upon the high concentration (at least 10.sup.19 cm.sup.-3) substrate 52, and then a 2.5 .mu.m layer of photoresist is selectively formed. Using the photoresist layer as a mask, high-energy implantation of phosphorus at 700 KeV is performed, and then short-term annealing for 4 hours at 1050.degree. C. is executed. As a result, a retrograde n-well 51 is formed, having a peak value of concentration in a deep portion of the well. Due to the formation of this n-type well 51 by high-energy implantation, and low-temperature short-term annealing, diffusion of boron (i.e. the substrate dopant) from the high concentration substrate 52 is prevented, and it becomes possible to form the n-type well 51 in the thin epitaxial layer 53, to thereby enhance the CMOS latch-up prevention capability.
Normally with such a semiconductor device structure, the high concentration substrate (p.sup.+) 52 is connected to ground potential (Vss) while the n-type well 51 is set to the power supply potential (V.sub.DD) due to the n.sup.+ layer 54 (provided for fixing the potential of the well) that is disposed closely adjacent to the source region 55s of the p-channel transistor.
A stray vertical pnp transistor arises with this structure, where p, n and p thereof are respectively the drain region 55d of the p-channel transistor, the n-type well 51, and the low dopant concentration epitaxial layer (p) 53 together with the high concentration substrate (p.sup.+) 52. If for example latch-up trigger current flows (as holes h injected from the drain region 55d) to pass through the virtual base region (i.e. the n-type well 51) and enters the low dopant concentration epitaxial layer 53, then this current will be immediately absorbed by the high concentration substrate (p.sup.+) 52 which is securely held at a fixed potential at its rear face. This serves to prevent any localized increase in potential of the low dopant concentration epitaxial layer 53. A stray lateral npn transistor also arises, having the low dopant concentration epitaxial layer 53 as its virtual base. The n, p and n of this stray lateral npn transistor are respectively the drain region 54d of the n-channel transistor, the low dopant concentration substrate (p) 53, and the n-well 51. However due to the device structure, this stray transistor cannot be set in the ON state. Thus with this configuration, a sufficient degree of suppression of the stray vertical pnp transistor operation is achieved, to thereby suppress latch-up.
However as described hereinafter, a stray lateral pnp transistor is formed below the insulating isolation layer 56, (where the p, n and p of this transistor are respectively the drain region 55d of the p-channel transistor, the well 51, and the low dopant concentration epitaxial layer (p) 53), and this in conjunction with the stray lateral npn transistor (where n is the drain region 54d of the n-channel transistor, p is the low dopant concentration substrate (p) 53, and n is the n-type well 51) forms a stray PNPN thyristor. As the structure is increasingly miniaturized, the width of the insulating isolation layer 56 becomes so small that satisfactory performance cannot be achieved, due to the presence of this stray PNPN thyristor.
For that reason, to suppress CMOS latch-up with this technology, it is necessary to limit the minimum spacing between the n-channel transistor and p-channel transistor to approximately 4 .mu.m. If the spacing is further reduced, then the epitaxial layer 53 must be made even more thin. However it is necessary to suppress the diffusion of boron (i.e. the substrate dopant) from the high concentration substrate 52 to an absolute minimum. This is very difficult to achieve. The problem of reducing the spacing width of the insulating isolation layer 56 is closely related to the method of forming the n-type well 51, and the configuration and method of forming the channel stop 60 which is disposed immediately below the insulating isolation layer. The basic features of forming the n-well 51 and the channel stop 60 will be described referring to FIG. 18.
Firstly, an oxide film 82 and a nitride film 81 are formed on the surface of the low dopant concentration epitaxial layer 53, which has been grown upon a high concentration substrate (p.sup.+) 52. A photoresist pattern 83 is then selectively formed on the result, and ion implantation of the n-type well 51 is executed through this pattern. An insulating film 84 is then formed over the entire surface (FIG. 18(a)).
Next, lift-off processing is executed such that the insulating film 84 is left only upon the region of the n-well 51. Further patterning processing is then executed to form a photoresist pattern that corresponds to the insulating isolation layer 56. The channel stop 60 is then formed by implantation (FIG. 18(b). It is important to note that the channel stop 60 is formed by means of the insulating film 84 such as to substantially coincide in position with the edge of the n-type well 51. That is to say, with this process, the channel stop 60 is formed at the edge of that n-type well in a substantially self-aligned manner.
Using the photoresist pattern 85, etching of the insulating film 84 and the nitride film 81 is executed, and a nitride film pattern is formed corresponding to the insulating isolation layer 56 (FIG. 18(c)). Next, the insulating isolation layer 56 is formed by the usual LOCOS thermal oxidation process (FIG. 18(d).
A very important question with regard to this process is that at the point in time at which ion implantation is executed of the channel stop 60 (which generally has a higher concentration than the n-type well 51), the region of the n-type well 51 has been compensated by migration in the lateral direction. In addition, as a reult of the thermal oxidation processing of the portion 161 (shown in FIG. 18(d)) of the channel stop 60, large-scale diffusion occurs within the n-type well 51, due to the effect of oxidation-enhanced diffusion. Due to this diffusion, part of the n-type well dopant ions are compensated in a localized region, whereby reduction of the width of the virtual base region (n-well 51) of the stray lateral pnp transistor occurs ((where the P, N and P of this transistor are respectively the drain region 55d of the p-channel transistor, the n-well 51, and the low dopant concentration epitaxial layer (p) 53). The h.sub.FE of this stray pnp transistor is thereby increased, and that transistor therefore responds very sensitively to injection of a trigger current from the drain region 55d of the p-channel transistor. This is a serious defect, which results from reduction of the size of the insulating isolation layer 56, i.e. which is caused by an increased degree of miniaturization.
Another proposal has been made by K. W. Terril et al, (I.E.E.E. 1984 I.E.D.M) Technical Digest pp. 406-409, which is shown in FIG. 19. In FIG. 19, numeral 61 denotes an n-well, 62 is a high concentration buried layer (p.sup.+), and 63 denotes a low dopant concentration substrate (p).
With this structure, after the n-well 61 has been formed, the high concentration buried layer (p.sup.+) 62 is formed uniformly at a location which is deeper than the n-well 61. In the same way as for the epitaxial structure described above, a stray pnp transistor arises (where p is the drain region 65d of the p-channel transistor, n is the n-well 61, and p is the low dopant concentration substrate (p) 63 and the high concentration buried layer (p.sup.+) 62). If a latch-up trigger current flows from the drain region 65d for example, due to the injection of holes h, the structure has the objective of suppressing any localized increase in potential which might result from this current passing through the virtual base region (i.e. the n-well 61) into the low dopant concentration substrate 63.
However this structure differs from the epitaxial structure example in that the potential of the high concentration buried layer (p.sup.+) 62 is floating, and hence such a trigger current cannot be absorbed with sufficient effectiveness, as is achieved with the epitaxial structure.
In addition, both with the structure using the epitaxial layer and the structure in which a high concentration region is formed by implantation, similar problems occur. That is to say, of the holes that pass into the low dopant concentration substrate through the n-well (having been injected from the source or the drain region of the p-channel transistor), most will be absorbed by the high concentration region. However those holes which flow in the lateral direction will not be absorbed sufficiently, and this will result in the potential of a specific region of the low dopant concentration substrate being increased. Hence, a trigger current will flow through that portion, which will turn on the stray PNPN thyristor, and hence will result in the latch-up phenomenon occurring. This is a very serious problem, that results from a reduction in the spacing between the borders of the n.sup.+ and p.sup.+ layers of the regions that constitute the complementary transistor pair, and presents an obstacle to increased levels of integration of CMOS complementary semiconductor devices.
In addition, in the case of the epitaxial structure, the cost of an epitaxial wafer is high, and it is difficult to attain increased productivity by achieving stable manufacture of large-diameter wafers having a thin epitaxial layer. Furthermore it is necessary to make the thickness of the epitaxial region (i.e. the low dopant concentration region) as small as possible, in order to assure effective absorption of holes. However a problem arises that a very shallow low dopant concentration region cannot be achieved, due to out-diffusion (i.e. diffusion of substrate dopant ions) from the high concentration region during growth of the epitaxial layer. On the other hand with the method in which a high concentration region is formed by implantation, although the manufacturing cost is not excessive, it is not possible to achieve a sufficient degree of effectiveness of suppression of the CMOS latch-up phenomenon, since it is not possible to fixedly determine the potential of the high concentration buried layer (p.sup.+) at its rear face or by a diffusion layer formed on the upper face of the semiconductor substrate. In order to increase the dopant concentration of the high concentration buried layer (p.sup.+), to achieve sufficient absorption of the trigger current, it is necessary to use high-energy high-dose implantation (1.0.times.10.sup.14 cm.sup.-2 or higher). However the problem then arises that point defects are produced within the substrate.
Thus, with both the epitaxial structure and the structure having a high concentration buried layer formed by high-energy high-dose implantation, satisfactory characteristics cannot be achieved.
Another example of the use of a well and of a channel stop below the insulating isolation layer in a miniaturized device will be described referring to the manufacturing process cross-sectional views of FIG. 20. This has been proposed by R. A. Martin, (I.E.E.E. 1984 I.E.D.M) Technical Digest pp. 403-406.
With this manufacturing process, a channel stop is formed directly below an insulating isolation layer, between mutually adjacent portions of the n-channel and p-channel transistors. The objective of the proposal is to achieve simplification of the manufacturing process and a more miniaturized structure.
In FIG. 20(a), firstly a p-type dopant is implanted to a high concentration, to form an n-channel stop 75, in a portion of a region which will constitute an insulating isolation layer. Next, an insulating isolation layer 76 is formed by the usual LOCOS thermal oxidation processing, and then a pattern of photoresist 80 is formed over a part of the insulating isolation layer 76. At this time, the n-type channel stop has been diffused into the interior of the substrate as a result of the aforementioned thermal oxidation (FIG. 20(b)).
Next, in FIG. 20(c), high-energy n-type implantation is then executed through the photoresist pattern 80, to produce a comparatively high concentration n.sup.+ region as an n-well 71, together with a high concentration n.sup.+ region that is disposed immediately below a portion of the insulating isolation layer 76 and constitutes a part of the n-well 71. Thus, a p-type channel stop is formed in a single step.
Using the normal manufacturing process, a gate oxide film 78, gate electrode 77, and source and drain regions 73s, 73d and 74s, 74d and aluminum connecting lead 79n are then formed, to obtain a complementary semiconductor device as shown in FIG. 20(d).
Thus with this manufacturing process, the p-type channel stop is formed by a compensation method through implantation of n.sup.+ ions, executed in a condition in which p.sup.+ diffusion to form an n-type channel stop has already occurred. In this way, oxide-enhanced diffusion of the type shown in FIG. 18 will not cause diffusion into the n-well from the channel stop 75. However it is extremely difficult to set the dopant concentration for the channel stop at the n-type well 75 side, to achieve correct compensation. That is to say, the concentration is established by implantation processing, and the p.sup.+ channel stop 75 is also affected by oxide-enhanced diffusion resulting from the LOCOS processing. It is necessary to control the n.sup.+ implantation precisely, and in addition to accurately control the concentration distribution in the depth direction, such as to obtain both of the requisite concentrations for the p.sup.+ channel stop 75. If there is even a small amount of inaccuracy, then the shape of the boundary portion 176 shown in the drawings will not be accurately determined, so that the threshold voltage Vt at the n-well 71 side of the insulating isolation layer 76 will be lowered, and hence the channel stop function will not be achieved. Furthermore, this method of manufacture raises particular problems with regard to the n-type channel stop 75, which is not compensated. That is to say, due to the work function of the connecting leads (formed of n.sup. + polysilicon or Al) which are formed on the insulating isolation layer 76, the threshold voltage of the stray n-channel MOSFET can easily become lower than the threshold voltage of the stray p-channel MOSFET. In order to increase the threshold voltage of the stray n-channel MOSFET it is necessary that the n-type channel stop 75 have a high dopant concentration. However due to the fact that the p-type channel stop is formed by compensation, the concentration of the n-type channel stop 75 will only be a fraction of that of the p-type channel stop. Thus it is difficult to set the level of concentration of the n-type channel stop 75 to a sufficiently high value. For these reasons, the width of the insulating isolation layer cannot, be reduced by very much.
Furthermore, due to the fact that the n.sup.+ implantation forms the n-well 71 at the same time as the channel stop is formed, in order to simplify the processing, a CMOS structure providing optimum suppression of latch-up cannot be achieved, since the optimum implantation conditions for forming the channel stop and the optimum implantation conditions for forming the n-well 71 do not coincide. Thus this method is not suitable for obtaining increased miniaturization.
As described above, the prior art proposals can be broadly divided into two types, i.e. a structure and method of manufacture in which a high concentration layer is used for suppression of the stray vertical transistor effect, and a structure and method of manufacture in which a channel stop is provided below the insulating isolation layer, for suppressing the stray lateral transistor effect.

Method of manufacture for semiconductor device by forming deep and shallow regions

Matsushita Electric Industrial, Co., Ltd.


A hinge structure with an electrical connector is connected to a first body of an electronic device through a support frame. A pivot portion of the hinge structure is connected to a second body of the electronic device and includes a rotating shaft connected to the support frame, such that the first body is capable of rotating relative to the second body. The electrical connector is a power input connector disposed on the support frame, such that a power line is inserted in the power input connector to electrically connect to the electronic device.

1. Field of the Invention
The present invention relates to a hinge structure, and more particularly to a hinge structure with an electrical connector applied to an electronic device.
2. Related Art
With the progress of electronic technology, various portable electronic devices such as notebook computers, electronic dictionaries, and clamshell phones have become indispensable in people's work and daily life. Such an electronic product generally includes a display and a main body, and a hinge structure pivoted to the display and the main body serves as a rotating axle center between the display and the main body, such that the display and the main body are connected and rotate relative to each other through the hinge structure.
Currently, in order to make the portable electronic devices to be easily carried along and prevent the devices from being interrupted in operation due to power loss, most portable electronic devices employ the power supply mode of setting a power connector within the main body of each device and configuring a power jack exposed out of the surface of the main body for connecting to the power line.
However, recently, as the power connector (DC-in) of the portable electronic device is disposed within the main body, the power jack exposed out of the surface of the main body is located on two sides or at the back of the main body of the electronic device. Taking the notebook computer for example, when a user intends to insert the power plug into the power connector, the position of the power jack has to be found first so as to insert the power line in the notebook computer. Besides, the only way for the user to figure out whether the power line is successfully plugged or pulled is from the window of the operating system of the computer.

Hinge structure with electrical connector


A process for the coating of substrates comprising insertion of a substrate into a process oven, dehydration of the substrate, withdrawal of a metered amount of one or more chemicals from one or more chemical reservoirs, vaporizing the withdrawn chemicals in one or more vapor chambers, and transfer of the vaporized chemicals into a process oven, thereby reacting with the substrate. An apparatus for the coating of substrates comprising a process oven, a metered chemical withdrawal subsystem, and a vaporization subsystem.

1. Field of the Invention
This invention relates to the coating of substrates, and in particular to an apparatus and process for the efficient coating of substrates using chemical vapor reaction.
2. Description of the Related Art
The application of coatings onto substrates and other workpieces is required as a process step in many industrial fields. An example of such a process is the coating of a silicon wafer with a layer of Hexamethyldisalizane (HMDS). This coating process is used to promote the adhesion of organic layers such as photoresist to the inorganic silicon wafer. The HMDS molecule has the ability to adhere to the silicon wafer and also to be adhered to by an organic additional layer. For example, silicon wafers would be baked for 30 minutes in a 150 C oven for 30 minutes to dehydrate them. The silicon wafers would then be sprayed with HMDS. The excess HMDS would then be spun off of the silicon wafer. A typical process of this type would result in a HMDS monolayer on the surface of the silicon wafer.
A problem encountered with the above mentioned process was that if the silicon wafer was not sufficiently dry prior to the application of HMDS, then residual moisture would interfere with the reaction of the HMDS to the silicon wafer. This would result in variations in the HMDS layer reaction and then could lead to voids in the subsequently applied next layer. Another problem with a process of this type is that HMDS would rapidly deteriorate when exposed to air and moisture, and thus such a process required a large amount of HMDS to provide a small amount of reaction.
Because of the problems relating to variations in the HMDS monolayer, processes for the coating of substrates with HMDS evolved. Later processes more thoroughly dehydrated the silicon wafer substrate prior to the application of HMDS, and limited the HMDS from much, if any, exposure to air and moisture. An example of such a process would be as follows. Silicon wafers would be placed in a vacuum chamber and cycled back and forth between vacuum and preheated hot dry nitrogen in order to dehydrate the silicon wafer. For example, the silicon wafer would be exposed to a vacuum of 10 Torr for 2 minutes. At this pressure water boils at about 11 C. The vacuum chamber would then be flooded with preheated nitrogen at 150 C. This part of the process would heat the surface of the silicon wafer so that the high temperature of the wafer would assist in the dehydration process as vacuum was once again applied. After 3 complete cycles, a vacuum of 1 Torr would be applied to complete the dehydration process.
The next step in such a process is to open a valve between the vacuum chamber and a canister of HMDS. At room temperature the HMDS boils at approximately 14 Torr and thus the chamber is flooded with 14 Torr of HMDS vapor. In this process the HMDS is not exposed to air or moisture and the silicon wafer is significantly dryer prior to being coated.
Some coating processes based on the above mentioned type of process require a higher pressure. The HMDS is preheated to create a higher vapor pressure. Typical figures are preheating of the HMDS to 100 C to produce up to 400 Torr pressure or HMDS vapor while limiting the pressure in the process oven at 300 Torr to avoid condensation of the HMDS.
Processes involving the preheating of the deposition chemicals have the drawback that if the deposition chemicals degrade with exposure to heat then the bulk preheating of these chemicals may result in the loss of the unused residual chemical. These chemicals are often very expensive. Also, many of these chemicals are hazardous materials. The less of these chemicals actually being used in the process at any time reduces the potential risk for processing facilities.
The coating of substrates for biotech applications may require sufficiently dehydrated substrates and insertion into the process chamber of one or more deposition chemicals which have been preheated and/or vaporized prior to insertion. Some coatings for biotech applications are quite expensive. Some coatings are difficult to vaporize and vaporization requires a combination of low pressure and high temperature. Without reduced pressure, the temperature required for vaporization may be too high to retain stability of the chemical to be vaporized. Biotech applications may require silane deposition onto glass and/or other substrates as a bridge to organic molecules. Among the silanes used are amino silanes, epoxy silanes, and mercapto silanes. These silanes are used in the adhesion layer between glass substrates and oligonucleotides. Oligonucleotides are a short DNA monomer. Substrates are coated with a monolayer of silane as a bridge between the inorganic substrate and the organic oligonucleotide. A silane coated substrate with an oligonucleotide layer is now a standard tool used in biotech test regimens. One area where this oligonucleotide layer is used is in the formation of DNA microarrays. A uniform and consistent silane layer leads to a more uniform and consistent top surface of the oligonucleotide layer, which in turn leads to more useful test results.
What is called for is a process and apparatus which withdraws deposition chemicals from a bulk storage container and then preheats and/or vaporizes this portion separately prior to delivery into the process chamber, allowing for the introduction of deposition chemicals at high temperatures and/or vapor pressures into a process chamber, without requiring preheating of bulk amounts of the deposition chemicals.
Substrates coated with such a process have more consistent monolayers with better bonds to the substrate, allowing for a more consistent oligonucleotide layer. This consistent substrate, used in DNA microarray tests, leads to more accurate test results

Apparatus for the efficient coating of substrates


The present invention blocks and/or attenuates the upstream travel of acoustic disturbances or sound waves from a flight vehicle or components of a flight vehicle traveling at subsonic speed using a local injection of a high molecular weight gas. Additional benefit may also be obtained by lowering the temperature of the gas. Preferably, the invention has a means of distributing the high molecular weight gas from the nose, wing, component, or other structure of the flight vehicle into the upstream or surrounding air flow. Two techniques for distribution are direct gas injection and sublimation of the high molecular weight solid material from the vehicle surface. The high molecular weight and low temperature of the gas significantly decreases the local speed of sound such that a localized region of supersonic flow and possibly shock waves are formed, preventing the upstream travel of sound waves from the flight vehicle.

1. Field of the Invention
The present invention relates generally modifying the local speed of sound characteristics of a gas or fluid flow, more particularly to modifying these characteristics using the distribution of a high molecular weight and/or low temperature gas into to the flow, and most particularly to attenuating the acoustic disturbance and/or noise associated with aircraft by modifying the local speed of sound characteristics using high molecular weight and/or low temperature gas upstream of the aircraft.
2. Description of the Related Art
Reduction of noise generated by jet engines has become an important aspect of aircraft design. Sound waves from aircraft traveling at subsonic speed propagate in all directions relative to the aircraft. The reduction of noise generated by aircraft has obvious benefits, including reducing noise pollution and, thereby, reducing safety risks to persons in the vicinity of aircraft. Also, sound waves have a tendency to contribute to wear and fatigue of aircraft components.
Many technical solutions have been employed in order to reduce noise generated by aircraft. These include using physical barriers attached to aircraft in order to provide a physical shield to block or attenuate sound waves and injecting gases directly into the jet engine exhaust in order to suppress noise. These solutions provide some reduction to noise levels, but normally result in some reduction in aircraft efficiency or performance. In addition, all of these solutions relate to decreasing sound waves only "downstream" from the aircraft, but do not address sound waves emanating "upstream" from the aircraft.
Therefore, it is desired to provide a relatively low-cost apparatus and method to attenuate or block aircraft noise emanating in any direction from an aircraft, without affecting aircraft performance.

Method for creating an aeronautic sound shield having gas distributors arranged on the engines, wings, and nose of an aircraft

The United States of America as represented by the Administrator of the National Aeronautics and Space Administration


Systems and techniques that facilitate electronic generation of three-dimensional quantum circuit diagrams are provided. In various embodiments, a system can comprise a data component that can access qubit topology data characterizing a quantum computing device. In various aspects, the system can further comprise a rendering component that can render a three-dimensional quantum circuit diagram based on the qubit topology data. In various instances, the qubit topology data can indicate which qubits of the quantum computing device are coupled together. In various cases, the rendering component can render the three-dimensional quantum circuit diagram by generating a two-dimensional qubit configuration model of the quantum computing device based on which qubits of the quantum computing device are coupled together, by extruding one or more qubit lines three-dimensionally outward from the two-dimensional qubit configuration model, and by rendering one or more quantum gates on the one or more qubit lines.

The subject disclosure relates to quantum circuit diagrams, and more specifically to electronic generation of three-dimensional quantum circuit diagrams.
A quantum computing device can utilize one or more qubits to perform quantum information processing. Quantum information processing is accomplished by executing one or more quantum circuits on the one or more qubits of the quantum computing device. A quantum circuit is a string of quantum gates that can be executed in series and/or in parallel to transform the states of the one or more qubits of the quantum computing device. A quantum circuit can be visually illustrated by a quantum circuit diagram.
Conventionally, a quantum circuit diagram depicts a column on a left side of the quantum circuit diagram that lists the one or more qubits that comprise the quantum computing device. Moreover, the quantum circuit diagram depicts a qubit line extending rightward from each qubit in the column of qubits. Furthermore, the quantum circuit diagram depicts representations of quantum gates along the qubit lines, where execution is performed from left to right. Thus, the quantum circuit diagram allows a viewer (e.g., an operator, a scientist, an engineer, an analyst) to visually see which quantum gates are applied to which qubits of the quantum computing device in which execution order. In other words, the quantum circuit diagram visually represents quantum software that is executable on the quantum computing device.
A technical problem that plagues such a conventional quantum circuit diagram is that such a conventional quantum circuit diagram is wholly disconnected from the physical configuration of the quantum computing device. In other words, such a conventional quantum circuit diagram does not in any way visually represent and/or otherwise convey information about the underlying qubit topology of the quantum computing device (e.g., does not indicate how the one or more qubits of the quantum computing device are coupled together). This is problematic because the underlying qubit topology of the quantum computing device can limit how quantum circuits are executed on the quantum computing device. For instance, two qubits cannot be entangled via a CNOT gate unless they are coupled together, but a conventional quantum circuit diagram does not convey which qubits are coupled together and which are not. Thus, although such a conventional quantum circuit diagram may indicate which quantum gates are applied to which qubits in which execution order, such a conventional quantum circuit diagram lacks information about the underlying qubit topology of the quantum computing device, which deprives viewers of a deeper level of understanding of the quantum computing device.
Systems and/or techniques that can ameliorate one or more of these technical problems can be desirable.

Electronic generation of three-dimensional quantum circuit diagrams

INTERNATIONAL BUSINESS MACHINES CORPORATION


Aqueous processes for the preparation of a new beta quinacridone modification possessing a magenta color having C.I.E. color space values in masstone of L=33-36, A=34-40 and B=8-15 starting with the crude pigment and comprising several milling and alternative deaggregation and recrystallization steps, the latter being facilitated at elevated temperatures aided by the presence of base and minor amounts of crystal growth auxiliaries, and the beta quinacridone modification having the indicated C.I.E. color space values.

Quinacridone, also referred to as 5,12-dihydroquino[2,3-b]acridine-7,14-dione, of the following formula ##STR1## is known to exist in three polymorphic modifications. The alpha (U.S. Pat. No. 2,844,484) and gamma (U.S. Pat. Nos. 2,844,581 and 2,969,366) forms are bluish-red pigments, while the beta form (U.S. Pat. No. 2,844,485) is a violet pigment.
A second, distinct beta quinacridone polytype designated .beta..sub.I was identified and described in U.S. Pat. No. 4,857,646. The new form differs from the known beta form by a modified X-ray diffraction pattern and a significant color shift from violet to magenta. The new form also offers a variety of new color styling opportunities, particularly for automotive and industrial finishes. The pigment additionally shows excellent hiding power, purity of shade, fastness to light and weathering, resistance to high temperatures and solvent and softener resistance.
Several methods were identified for preparing the new pigment and for preparing it in the desired relatively low specific surface area form. The new pigment could be prepared either by controlled particle size reduction/ripening of a crude pigment or by overmilling of a crude and then growing the pigment particles to the desired size and surface area. It was also noted that both particle size reduction and growth by crystallization could be achieved in a single operation.
Applicable disclosed procedures can be summarized as follows:
(1) Milling of alpha quinacridone, preferably of small particle size, in the presence of alcohol and base.
(2) Milling of crude or large particle size .beta..sub.II quinacridone (surface area of 3-8 m.sup.2 /g) in the presence of alcohol and base and appropriate milling media.
(3) Conducting the second procedure in two steps with premilling of the crude beta quinacridone following by ripening or particle size growth in a subsequent alcohol-base milling step.
(4) Particle ripening of a finished, particle size reduced beta quinacridone (a) by milling in the presence of alcohol and base, or (b) refluxing in basified alcohol.
Further experimentation with the new beta polytype revealed that it could exhibit a greater breadth of color within the magenta class. Thus, in terms of C.I.E. coordinates with L, A, B color space units, the modified form disclosed in U.S. Pat. No. 4,857,646 exhibited masstone L (lightness)=35.2 units, A (chroma)=38.0 units, B (hue)=10.9 units when incorporated into a high solids enamel paint system. It has now been determined that each of the L, A, B coordinates can be defined in terms of a range of values.

Aqueous process for preparation of modified beta quinacridone


An acoustic separation device for reagent manipulation a standing acoustic including a wave generating device and pairs of perforated pseudo walls comprising a longitudinal standing bulk acoustic wave (LSBAW) channel. The LSBAW channel provides local pressure field amplification to overcome drag forces arising from reagent flow. Further, method for manipulating a reagent under continuous flow conditions microcarrier particles locally confined in an acoustic separation device comprising an inlet and an outlet, a fluid routing layer coupled to a channel, a plurality of loading wells configured to hold a plurality of substances required for a desired synthesis, and a controller configured to distribute the plurality of substances held by the loading wells in a desired sequence. The device for antibody manipulation further comprises an ultrasound actuator, and a channel wherein the channel is separated from the ultrasound actuator.

Automation of lab-scale chemical synthesis has become a driving force behind many routine, yet error-prone, reaction and synthetic procedures. These procedures include reactions involving polypeptides, RNA, DNA, proteins, carbohydrates, and other macromolecules. In many of these synthetic procedures, miniaturization and integration of unit operations enables several functions to be performed automatically in single or interconnected modules, which provide precise environmental control for each step. There is therefore a need to eliminate manual, error-prone operations in the synthesis of antibody conjugates (ACs) and to improve the quality and throughput of produced ACs through automation and integration of all synthetic steps.
For example, antibodies attached to biologically active drugs or imaging tracers present a significant source of next-generation oncolytic therapies and diagnostics with the potential to improve clinical outcomes for a diverse population of cancer patients. Other methods involving post-translational modification of antibodies include modification of the amino acids or the carbohydrates in antibodies, humanization of antibodies, dimerization or oligomerization of antibodies, and cross-linking of antibodies with other antibodies, antibody fragments, or other biologics. The growth in clinical trials, FDA-approved products, and antibody conjugate-related publications involving antibody-tracer conjugates (ATCs) and antibody-drug conjugates (ADCs), evidences the extent and promise of this research area. In this context, production and validation of new antibody conjugates (ACs) are integral to a variety of fundamental and preclinical studies. Traditional manual synthesis of ACs is labor-intensive, requires large reagent volumes, and suffers from inconsistency and poor reproducibility that can yield unacceptable proportions of false positives and false negatives in imaging studies. These deficiencies have motivated pursuit of alternative approaches to manual AC preparation including process miniaturization and automation.
Described herein is an acoustic separation device including a microfluidic device architecture that locally augments the pressure field for separation and enrichment of targeted microparticles in a longitudinal acoustic trap. Pairs of pillar arrays comprise "pseudo walls" that are oriented perpendicular to the inflow direction. Though sample flow is unimpeded, pillar arrays support half-wave resonances that correspond to the array gap width. Positive acoustic contrast particles of supracritical diameter focus to nodal locations of the acoustic field and are held against drag from the bulk fluid motion. Thus, the longitudinal standing bulk acoustic wave (LSBAW) device achieves size-selective and material-specific separation and enrichment of microparticles from a continuous sample flow. Finite element analysis models are used to predict eigenfrequencies of LSBAW architectures with two pillar geometries, slanted and lamellar. Corresponding pressure fields are used to identify longitudinal resonances that are suitable for microparticle enrichment. Optimal operating conditions exhibit maxima in the ratio of acoustic energy density in the LSBAW trap to that in inlet and outlet regions of the microchannel. Separation and isolation of 20 μm polystyrene and ˜10 μm antibody-decorated glass beads within both pillar geometries is demonstrated. The results also establish several practical attributes of our approach. The LSBAW device is inherently scalable and enables continuous enrichment at a prescribed location. These features benefit separations applications while also allowing concurrent observation and analysis of trap contents. The acoustic separation device is well-suited to a range of applications, from ex vivo cancer assays and diagnostics (e.g., ELISA) to imaging (antibody-tracer conjugates) and interventions (antibody-drug conjugates).

Synthesis, post-modification and separation of biologics using acoustically confined substrates


A magnetic resonance method and system for generation of an optimized MR image of an examination subject operate as follows. A pulse sequence including a series of at least two RF pulses is radiated into the examination subject to generate at least one optimized signal, wherein the second and possibly every additional RF pulse is radiated before the effect of the first or a preceding RF pulse on the spin system in the examination subject has decayed. The radiated RF pulses are generated by parallel transmission coils. At least the signal resulting after the last radiated RF pulse of the pulse sequence is acquired. The pulse sequence is repeated with modified spatial coding until signals have been generated and acquired in a desired positional space. The optimized MR image per pulse sequence is calculated from at least one of the acquired signals.

1. Field of the Invention
The present invention concerns a method to generate an optimized MR image of an examination subject, a corresponding electronically readable data storage medium, and a corresponding magnetic resonance apparatus.
2. Description of the Prior Art
Magnetic resonance (MR) imaging is a known modality with which images of the inside of an examination subject can be generated. Expressed in simple terms, for this purpose the examination subject is positioned in a strong, static, homogeneous basic magnetic field B0 (field strengths from 0.2 to 7 Tesla or more) in a magnetic resonance apparatus so that nuclear spins in the subject orient along the basic magnetic field. For spatial coding of the measurement data, rapidly switched gradient fields are superimposed on the basic magnetic field. To trigger nuclear magnetic resonances, radio-frequency excitation pulses (RF pulses) are radiated into the examination subject by at least one transmission coil. The triggered nuclear magnetic resonances (signals) are measured by reception coils, and MR images, for example, are reconstructed on the basis of the measured signals. The magnetic flux density of these RF pulses is typically designated with B1. The pulse-shaped radio-frequency field is therefore generally also called a B1 field for short. The nuclear spins of the atoms in the examination subject are excited by these radio-frequency pulses such that they are deflected (flipped) out of their steady state parallel to be basic magnetic field B0 by an amount known as an "excitation flip angle" (also called a "flip angle" in the following for short). The nuclear spins then precess around the direction of the basic magnetic field B0. The magnetic resonance signals that are thereby generated are acquired by radio-frequency reception antennas. The acquired measurement data are digitized and stored as complex numerical values—raw data—in a k-space matrix. By means of a multidimensional Fourier transformation, an associated MR image can be reconstructed from the k-space matrix populated by such values. In addition to anatomical images, spectroscopic data, movement (flow) data or temperature data of an examined or treated area can be determined using suitable magnetic resonance techniques.
The measured signals thus depend on the radiated RF pulses. In addition to a homogeneous basic magnetic field and precisely linear gradient magnetic fields for spatial coding, typical methods to reconstruct image data sets from magnetic resonance signals also require a homogeneous RF field distribution (B1 field distribution) in the examination volume. However, the B1 field distribution in the examination volume typically is non-uniform in real MR systems, which leads to image inhomogeneities (image artifacts in the MR images reconstructed from the signals, and therefore to a poorer ability to recognize the desired details in the imaged examination subject. Particularly in whole-body imaging or acquisitions of the torso (breast, abdomen, pelvis) at basic magnetic fields of 3 Tesla or more, artificial shadows occur in the image due to an inhomogeneous RF field distribution. Due to the resulting poor image quality, this has prevented more extensive use of such examinations in the clinical field. The interfering image artifacts intensify and multiply with an increase of the field strengths that are used.
Artifacts and inconsistencies in MR imaging or spectroscopy due to inhomogeneous B1 fields have long been known. In conventional MR imaging with a transmission channel, it is not possible to directly affect the homogeneity of B1 fields. Therefore, conventional methods have the goal of exciting signals over a defined range of B1 variations, which signals are independent of the B1 field strength. One example of such a procedure is the use of composite RF pulses or adiabatic RF pulses. However, these have only limited applicability with regard to achievable flip angle and phase response in use with slice selection, as well as with regard to pulse times and SAR intensity (SAR: "specific absorption rate"). They are therefore typically used only for magnetization preparation and moreover have found no broad application in typical MR imaging sequences. Such magnetization preparations can in turn reduce the sensitivity of a subsequent imaging sequence, but they naturally lengthen the required transmission time of the complete pulse sequence.
A further known procedure attempts to achieve a spatial modulation of the generated transversal magnetization by simultaneous action of RF and gradient pulses on the spin system. The achievable homogeneity of these spatially selective, two-dimensional (2D) or three-dimensional (3D) pulses is unlimited in principle. 2D and 3D modulations, however, lead to very long pulse times and an inefficient use of the RF pulses since the average flip angle per radiated power is reduced. Most notably, the length of the required pulse sequences has previously prevented an establishment of this method in MR imaging.
Using the parallel transmission technique—thus using multiple transmission/reception coils—it is possible directly influence the spatial distribution of the B1 field. The individual RF fields thereby emanating in parallel from spatially separated individual transmission coils are vectorially superimposed in order to form the actual B1 field. The generated B1 field can be spatially modulated by adjusting the phases and amplitudes of the individual transmission channels (transmission coils). This method is known as "RF shimming". The achievable homogeneity is limited by the hardware, i.e. the number of available parallel transmission channels, for example. The pulse times for the spatially selective 2D and 3D pulses that are described above can also be shortened with the parallel transmission technique. However, the achievable pulse times are still longer than could be used to replace the previously typical slice-selective or non-selective pulses in the prevalent imaging sequences. Furthermore, it is unclear how robustly (i.e. with regard to B0 field variations, chemical shifts, movements of the examination subject and/or relaxation times), and with what SAR efficiency, these complex pulses can be used for in vivo imaging.
DE 103 38 074 B4 (corresponding to United States Patent Application Publication No. 2005/0083054) describes a method to compensate for contrast inhomogeneities in magnetic resonance images that are caused by spatial distributions of a transmitted radio-frequency field, in which method multiple individual images of a defined region are initially acquired with different radio-frequency pulse sequences which lead to different flip angles, and then on the basis of the various individual images a common contrast-homogenized image for the appertaining region is generated so that, within the contrast-homogenized image, intensity fluctuations caused by a distribution of the flip angle are at least smaller per region than in the individual images.

Magnetic resonance method and system to generate an optimized MR image of an examination subject


The lateral overflow drain for charge coupled devices includes: a semiconductor region 70 of a first conductivity type having a trench 92; a drain region 24 of a second conductivity type below the trench 92; a gate 20 in the trench 92 overlying and separated from a portion of the semiconductor region 70; and a virtual gate 30 of the first conductivity type in the semiconductor region 70 adjacent the trench 92.

Without limiting the scope of the invention, its background is described in connection with antiblooming structures for charge coupled device image sensors, as an example. Antiblooming action is important for operation of CCD sensor imaging scenes whose range of illumination intensities greatly exceeds the dynamic range of the sensor. With strong antiblooming action, the optical system can be adjusted for optimum performance at low light levels, and the high overloads associated with the bright portions of the scene can be absorbed by the antiblooming. Two major forms of antiblooming exist in the prior art. One uses charge recombination at the semiconductor-insulator interface to remove excess charge while the other forms a barrier and drain structure next to or underneath the pixel that removes any charge in excess of full well. Disadvantages of the charge recombination antiblooming include: large size; limited charge removal rate which is particularly a problem for short duration light pulses; constant clocking which causes large power consumption; and large interface state density which creates problems for dark current generation which is increased by high interface state density. A disadvantage of the prior art barrier and drain structures is that the size of the structures are not readily reduced due to the two dimensional effects of the potential profile and due to the necessary tolerances which are present in the mask alignment process.

Trench lateral overflow drain antiblooming structure for virtual phase charge coupled devices with virtual gate element


An apparatus includes a blocking N-channel MOS (LDMOS) transistor that prevents current flow when the supply connection is reversed. When connected properly, the body diode conducts to provide a start-up function. A bias generator is employed to enable the low drop-out voltage function, allowing the output voltage to be very close to supply.

1. Field of the Invention
This invention relates generally to voltage regulators, and more particularly to a methodology that employs reverse current blocking via a lateral double-diffused MOS (LDMOS) device to block the current flow when the supply connection is reversed.
2. Description of the Prior Art
Junction isolated IC processes must be protected against reverse supply connection. In many instances, this is done within the system, where an external component is placed to perform this function. In small, highly integrated systems however, it is desired or required to eliminate the external blocking component. Known solutions consist of PMOS or bipolar PNP transistor protection. Such solutions, in certain applications such as pre-regulators, are not area efficient.
In view of the foregoing, it would be both beneficial and advantageous to provide a reverse current blocking technique and that does not employ PMOS, bipolar PNP, or external circuit current blocking devices to block the current flow when the supply connection is reversed.

Pre-regulator with reverse current blocking


Video processing in general and image processing in particular is a very complex process. This is more so when the analysis is required to extract information from the images for providing of the same directly or indirectly to the users. This additional complexity is due to the direct competition with users who are used to analyzing of the images both syntactically and semantically. One of the ways to contain the complexity of image analysis is to exploit the domain semantics during image processing. A system and method to help in semantics based image processing involves the identification of one or more domain relevant semantic hierarchies and using of the same during image processing.

Video analysis of, say, a movie typically involves analyzing of a sequence of images contained in the video. The analysis is performed different points of view such as analysis for image/video compression, analysis for image/video annotation, or analysis for spam detection. As can be observed, one kind of video/image analysis is for machine processing while the other kind of video/image analysis is for providing information directly or indirectly to users. Note that video/image compression falls into the first kind while the video/image annotation is of second kind. For example, video/image annotations help in supporting semantics based end user queries on videos and relevance based ad targeting while watching the videos. For a successful annotation of an image, it is necessary to undertake the semantic analysis of the image: the image is analyzed to identify the prominent objects in the image so as provide that annotation based on these recognized objects. Note that both object recognition and identification of prominent objects are a complex and error prone processes there by leading to the not-so-very accurate image annotation. One approach to contain this complexity and enhance the accuracy of image annotation is to exploit the domain semantics during image processing.

System and method for hierarchical image processing


A semiconductor device having amplifying circuits provided near corresponding bonding pads receiving external signals, and positioned between the bonding pads and internal circuits to which such external signals are to be applied. The device includes a control signal generating circuit for the amplifying circuits which is not provided in conventional semiconductor devices. In response to external control signals, the control signal generating circuit generates internal control signals for controlling electric paths between a power supply and ground in the amplifying circuits. During the standby period of the semiconductor device, the paths between the power supply and ground are cut regardless of the potential of the corresponding bonding pads, preventing flow of a through current.

1. Field of the Invention
The present invention relates to a semiconductor device and, more specifically, to a semiconductor device in which capacitance at an input path of an external signal is decreased.
2. Description of the Background Art
A semiconductor device including an electronic circuitry formed of a number of elements includes bonding pads for exchange of signals between the electronic circuitry and the outside. FIG. 10 shows an example of a bonding pad arrangement in the semiconductor device. Referring to FIG. 10, the semiconductor device includes a semiconductor substrate 100 on the surface of which an electronic circuit 110 and bonding pads 120 are formed. Electronic circuit 110 is provided at the central portion of the semiconductor substrate 100, and bonding pads 120 are provided near the outer side of the semiconductor substrate 100. Each of the bonding pads 120 is connected to electronic circuit 110 by means of interconnection layer 130 formed on the surface of the semiconductor substrate 100. Semiconductor substrate 100 is adhered on a lead frame 220 having external pins 210 allowing exchange of signals with the outside. One external pin 210 is provided for each bonding pad 120. Each of the bonding pad 120 is formed by deposited metal, and is connected to the corresponding external pin 210 by means of a thin metal wire 300.
In this manner, in a semiconductor device, bonding pads are interposed between external pins and an internal circuitry, providing electrical contact therebetween. Since the external pin and the bonding pad are subjected to wire bonding and the length of the wire which can be taken out at one time is limited, the distance between the bonding pad and the external pin should be as short as possible. Therefore, the bonding pads are provided near the outer side of the semiconductor substrate.
A DRAM (Dynamic Random Access Memory) is one of such semiconductor devices requiring such bonding pads. FIG. 11 is a schematic block diagram showing functionally the whole structure of the DRAM. Referring to FIG. 11, a DRAM chip 1 includes a memory cell array MCA including memory cells (not shown) arranged in a matrix of a plurality of rows and a plurality of columns; an address buffer AB, a row decoder RD and a column decoder CD for selecting a memory cell to which or from which data is to be written or read out of the memory cells in memory cell array MCA; a data input circuit DI for taking from the outside a data signal to be written in the selected memory cell; a sense amplifier SA for amplifying a data signal read from the selected memory cell; and a data output circuit DO for externally outputting the data signal amplified by the sense amplifier SA as a read data signal Dout. Further, DRAM chip 1 includes a control signal generating circuit CG for generating, based on external control signals such as a low-active row address strobe signal RAS, a column address strobe signal CAS and a write enable signal WE, internal control signals for controlling these functional portions. In the following description, low-active signals are represented with / attached to the reference characters.
In the memory cell array MCA, memory cells arranged in the same row are all connected to the same word line (not shown), and the memory cells arranged in the same column are all connected to the same bit line (not shown).
Address buffer AB externally receives n+1 bits of address signals. The respective bits of signals A0, A1, . . . , An constituting the address signal are applied in parallel to address buffer AB. Address buffer AB buffers these signals A0 to An and apply these signals to row decoder RD and column decoder CD. Row decoder RD decodes the address signal from address buffer AB and selects any of the rows of memory cells included in memory cell array MCA, and activates the word line connected to the selected row of the memory cells. Column decoder CD decodes the address signal from address buffer AB and selects any of the columns of memory cells included in memory cell array MCA, as well as the bit line and the sense amplifier SA connected thereto.
In data writing, a data signal Din is externally applied to data input circuit DI. Data input circuit DI applies the data signal Din only to the sense amplifier SA and the bit line which are connected to the column of memory cells selected by column decoder CD. Therefore, the external data is written only in the memory cell which is connected to this bit line and to the word line activated by row decoder RD.
In data reading, only the data stored in memory cells connected to the word line which has been activated by row decoder RD appear as electric signals on corresponding bit lines, and amplified by the sense amplifier SA. Out of the amplified stored data signals, only that signal appearing on the bit line which is connected to the column of memory cells selected by column decoder CD is applied to data output circuit DO. Data output circuit DO outputs externally the data signal from sense amplifier SA as a read data signal Dout.
Since DRAM chip 1 includes the above described internal circuitry, it includes, as external terminals, a plurality of bonding pads for receiving externally the control signals such as row address strobe signal, column address strobe signal and write enable signal; n+1 bonding pads for receiving externally the n+1 bits of address signals; a bonding pad for externally receiving the data to be written to the memory cell array MCA; a bonding pad for receiving data read from memory cell array MCA through data output circuit DO; and two bonding pads for receiving externally the voltage for operating the internal circuitry. One of the aforementioned two bonding pads receives general ground potential Vss, and the other receives the general power supply potential Vcc.
FIG. 12 shows an actual arrangement of the bonding pads and main internal circuitry on a DRAM chip such as described above. Referring to FIG. 12, the DRAM chip 1 includes two memory cell arrays 2 having two sub arrays divided in the direction of rows. More specifically, one of these two memory cell arrays is divided into sub arrays MCA1 and MCA2, while the other one is divided into sub arrays MCA3 and MCA4. Sense amplifiers SA1 and SA2 are provided corresponding to sub arrays MCA1 and MCA2, respectively. Similarly, sense amplifiers SA3 and SA4 are provided corresponding to sub arrays MCA3 and MCA4, respectively. A column decoder CD1 and a row decoder RD1 are both provided common to sub arrays MCA1 and MCA2. Similarly, a column decoder CD2 and a row decoder RD2 are both provided common to sub arrays MCA3 and MCA4. On chip 1, the memory cell array divided into sub arrays MCA1 and MCA2 and a circuitry portion provided correspondingly, and the memory cell array divided into sub arrays MCA3 and MCA4 and a circuitry portion provided correspondingly are arranged on the right and left sides, respectively, as different blocks. An address buffer AB is arranged at the center of chip 1. Bonding pads 2 are arranged along the longitudinal direction near the outer side of chip 1. Each of the bonding pads 2 is connected to any of the functional portion constituting the internal circuitry by means of an interconnection layer formed on chip 1, corresponding to the signal which the bonding pad receives. For example, a bonding pad receiving an address signal is connected to address buffer AB.
Address buffer AB receiving n+1 bits of address signals generally includes a buffer AB0 for buffering the least significant bit signal A0, a buffer AB1 for buffering the second least significant bit signal A1, . . . , and a buffer ABn for buffering the most significant bit signal An. On chip 1, a bonding pad receiving signal A0, a bonding pad receiving signal A1, . . . , a bonding pad receiving signal An are connected to buffers AB0, AB1, . . . , ABn, respectively by means of separate interconnection layers. FIG. 12 shows, as a representative, interconnection layer 20 which connects a buffer ABi with a bonding pad 200 receiving a signal Ai (i=0, 1, 2, . . . , n) out of the n+1 signals constituting the address signal.
Recently, the internal circuitry of a semiconductor device realizing complicated functions such as a DRAM has come to be formed of larger number of elements. Since the degree of integration of the semiconductor device is increased, the size of the chip of the semiconductor device is also increased. The larger the chip size becomes, the longer the interconnection layer becomes for connecting the bonding pad with the internal elements. Therefore, a capacitance (stray capacitance) generated between the interconnection layer and the semiconductor substrate on which the interconnection layer is formed becomes larger. For this reason, driving capability of a circuit externally supplying signals to the bonding pad must be improved. In a semiconductor memory, for example, as the number of memory cells included in the memory cell array increases, the number of bits of the address signals is increased. Therefore, the number of bonding pads to be provided on the semiconductor memory chip to receive the address signals is also increased. Consequently, some of the bonding pads receiving the address signals are provided apart from the internal circuitry to which these pads are to be connected. In a DRAM, for example, bonding pad 200 receiving one address signal Ai is provided near the end portion in the longitudinal direction of chip 1, that is, considerably apart from buffer ABi to which the pad is to be connected. Therefore, the length of interconnection layer 20 connecting bonding pad 200 and buffer ABi is about one half of the longer side of chip 1. The length of the longer side of a 4M bit DRAM chip is about 14 mm, for example, and therefore the length of interconnection layer 20 in that case is about 7 mm. In this example, the interconnection layer 20 has a stray capacitance of about 1.2 pF. Each of the bonding pads 2 is connected to an external pin constituting a lead frame (not shown). A total capacitance of each of the external pins (hereinafter referred to as address signal pins) connected to the bonding pads receiving the address signals, the bonding pads connected thereto and of the metal wires connecting the address signal pins and the bonding pads, is, in general, about 3.5 pF. Namely, the capacitance existing between the external circuitry (not shown) generating the address signal Ai and buffer ABi is about 4.7 pF (=3.5 pF+1.2 pF). More specifically, the aforementioned external circuitry must have at least a driving capability enough to quickly charge/discharge a capacitor having the capacitance of 4.7 pF.
In actual practice, a plurality of such semiconductor memories are used combined to realize writing and reading of a large amount of information. In such a case, the plurality of semiconductor memories are mounted on one memory board formed of an insulating material, and address signals are supplied from a common external circuitry. When 100 4M bit DRAMs are mounted on one memory board, the external circuitry generating an address signal Ai must have a driving capability enough to quickly charge the total capacitance of 350 pF (3.5 pF.times.100) of a total of 100 address signal pins provided corresponding to the address signal Ai out of external pins of 100 DRAM chips, 100 metal wires respectively connected to 100 address signal pins and 100 bonding pads 200, as well as the total capacitance of 120 pF (=1.2 pF.times.100) of 100 interconnection layers 20 connecting these 100 bonding pads 200 to the buffers ABi of the corresponding chips.
In order to solve such a problem, the stray capacitance of the interconnection layer connecting the bonding pad with the internal circuitry must be made smaller. In a DRAM, for example, the driving capability of the external circuitry generating signals which are to be externally supplied to external pins is enough to quickly charge/discharge the capacitance of about 5 pF or less conventionally. Therefore, in order to avoid the increase of the driving capability required for the external circuitry providing signals to the DRAM accompanying the increase of storage capacity of the DRAM, the total capacitance posed between the respective external pins of the DRAM and the internal circuitry connected thereto (including the capacitance of the external pins themselves) must be about 5 pF or less even in a DRAM having large storage capacity. Further, the aforementioned total capacitance should preferably be 4 pF or less in consideration of variation during manufacturing of the lead frames. Therefore, the stray capacitance of the interconnection layer connecting an address buffer and a bonding pad receiving the address signal out of the bonding pads of the DRAM must be 0.5 pF (=4 pF-3.5 pF) or less, regardless of the storage capacity of the DRAM. However, in case of a 4M bit DRAM, the stray capacitance of the interconnection layer 20 connecting the buffer ABi with a bonding pad 200 shown in FIG. 12 is as large as about 1.2 pF, as described above.
Japanese Utility Model Laying Open No. 63-40896 shows a method of decreasing stray capacitance of the interconnection layer connecting the bonding pad to the internal circuitry. According to this Utility Model Laying Open 63-40896, an amplifying circuit is newly provided between the bonding pad and the internal circuitry to be connected to the pad. On a semiconductor substrate, the amplifying circuit is provided very close to the bonding pad, and the amplifying circuit amplifies the signal externally applied to the bonding pad, and applies the amplified signal to the internal circuitry. FIG. 13 shows electrical path between the bonding pad and the internal circuitry to be connected thereto in the semiconductor device disclosed in Japanese Utility Model Laying-Open No. 63-40896. FIG. 13 shows each of the interconnection layers connecting internal circuits in the form of an equivalent circuitry including resistance elements having resistance values corresponding to the length thereof, and capacitances (stray capacitances) generated between the interconnection layers and the semiconductor chip substrate.
Referring to FIG. 13, amplifying circuits 23 and 24 are newly provided corresponding to bonding pads 21 and 22 receiving address signals Aj1 and Aj2, respectively. Amplifying circuit 23 is provided near bonding pad 21, and amplifying circuit 24 is provided near bonding pad 22. Further, a switch 27 is newly provided at a succeeding stage of amplifying circuits 23 and 24. An output signal of switch 27 is applied to address buffer 29. Output signals from amplifying circuits 23 and 24 are applied to switch 27. Switch 27 switches and outputs the output signal from amplifying circuit 23 or the output signal from amplifying circuit 24. Therefore, address signal Aj1 or address signal Aj2 is switched and applied to address buffer 29. Consequently, two signals Aj1 and Aj2 constituting the address signals are respectively buffered and a complementary signal pair a,/a by means of a single buffer 29.
Bonding pad 21 and amplifying circuit 23, bonding pad 22 and amplifying circuit 24, amplifying circuit 23 and switch 27, amplifying circuit 24 and switch 27, and switch 27 and address buffer 29 are connected to each other by interconnection layers formed on semiconductor chip 1. However, since amplifiers 23 and 24 are provided close to bonding pads 21 and 22, respectively, interconnection layer 30 connecting bonding pad 21 and amplifying circuit 23 and interconnection layer 31 connecting bonding pad 22 and amplifying circuit 24 are very short. Therefore, stray capacitances of interconnection layers 30 and 31 are so small that they can be neglected. If bonding pads 21 and 22 are positioned very much apart from address buffer 29, interconnection layer 25 connecting amplifying circuit 23 and switch 27, interconnection layer 26 connecting amplifying circuit 24 and switch 27, and interconnection layer 28 connecting switch 27 and address buffer 29 are long. Therefore, stray capacitances and resistances of these interconnection layers 25, 26 and 28 are considerably larger than the stray capacitances and resistances of interconnection layers 30 and 31. However, the interconnection layers 25, 26 and 28 are driven by amplifying circuits 23 and 24. Therefore, attenuation of signals in the interconnection layer 25 because of larger stray capacitance of the interconnection layer 25, attenuation of signals in the interconnection layer 26 because of larger stray capacitance of interconnection layer 26 and attenuation of signals in interconnection layer 28 because of larger stray capacitance of interconnection layer 28 are no problem. More specifically, the driving capability of the external circuitry generating address signals Aj1 and Aj2 may be set corresponding to the stray capacitances of interconnection layers 30 and 31. Even if the driving capability of the external circuit is not very much improved, speed and accuracy signal transmission to internal circuitry is assured.
FIG. 14 shows a circuitry disclosed in Japanese Utility Model Laying Open No. 63-40896 as a specific example of the amplifying circuits 23 and 24 shown in FIG. 13. Referring to FIG. 14, each of the amplifying circuits 23 and 24 includes, for example, inverters INV1, INV2 and INV3 connected in series.
Inverter INV1 includes a P channel MOS transistor Q2 and an N channel MOS transistor Q3 receiving at their gates an address signal Aj from a corresponding bonding pad and a P channel MOS transistor Q1 having its gate grounded. Transistors Q1, Q2 and Q3 are connected in series between a power supply Vcc and the ground GND. Since transistor Q1 is always conductive, transistors Q2 and Q3 serve as an inverter for inverting address signal Aj. More specifically, if the potential of address signal Aj is lower than the threshold voltage of transistor Q2 and the threshold voltage of transistor Q3, only the transistor Q2 is rendered conductive, whereby the potential of the power supply Vcc is applied to the node between transistors Q2 and Q3. Conversely, if the potential of address signal Aj is higher than the threshold voltage of transistor Q2 and than the threshold voltage of transistor Q3, only the transistor Q3 is rendered conductive, whereby the potentials of transistors Q2 and Q3 are lowered to the ground potential. The threshold voltage of transistor Q2 is set to be higher than the potential of the address signal Aj corresponding to the logic value of " 0", and the threshold voltage of transistor Q3 is set to be lower than the potential of address signal Aj corresponding to the logic value of "1". Therefore, the node between transistors Q2 and Q3 is supplied with a current from power supply Vcc in response to the address signal Aj having the logic value 0, and the current at this node is drawn to the ground GND in response to the address signal Aj having the logic value 1. Consequently, the amplitude of the output potential from inverter INV1 is about the output voltage of external power supply. Inverter INV2 includes a P channel MOS transistor Q4 and an N channel MOS transistor Q5 connected in series between power supply Vcc and the ground GND. Similarly, inverter INV3 includes a P channel MOS transistor Q6 and an N channel MOS transistor Q7 connected in series between the power supply Vcc and the ground GND. An output potential from inverter INV1 is applied to the gates of transistors Q4 and Q5, and an output potential from inverter INV2 is applied to the gates of transistors Q6 and Q7. Therefore, at the node between transistors Q4 and Q5, a logic level inverse to the output logic level from inverter INV1 appears, and at the node between transistors Q6 and Q7, a potential having the inverse logic level to the output logic level of inverter INV2 appears. Therefore, the address signal Aj with its logic level inverted is output from the amplifying circuit.
Differential voltage (hereinafter referred to as amplitude of address signal Aj) between the potential of the address signal Aj having the logic value of 0 and the potential of the address signal Aj having the logic value of 1 is smaller than the output voltage of the aforementioned external power supply, the amplitude of the address signal after inversion by inverter INV1 is larger than the address signal Aj before inversion; the amplitude of the address signal further inverted by inverter by INV2 is larger than the address signal before inversion by inverter INV2; and the amplitude of the address signal further inverted by inverter INV3 is larger than that of the address signal before inversion by inverter INV3. Namely, the address signal Aj has its logic level successively inverted by inverters INV1, INV2 and INV3, and its amplitude widened to about the output voltage of the aforementioned external power supply by means of these three inverters. Consequently, the output signal Ajr from the amplifying circuit is an amplified signal of the original address signal Aj.
As described above, in one conventional method of reducing driving capability of the external circuitry supplying signals to the bonding pads by reducing stray capacitances of interconnection layers connecting the bonding pads with internal circuitry in a semiconductor device, an amplifying circuit electrically connected to a bonding pad and to the internal circuitry to which the bonding pad is to be connected inherently is provided near the bonding pad. However, the amplifying circuit is adapted to operate only in response to the signal externally applied to the corresponding bonding pad. Consequently, the following problem arises.
Referring to FIG. 14, to the amplifying circuit, only the address signal Aj externally applied to the corresponding bonding pad is input. Therefore, the potential of the output signal Ajr of the amplifying circuit is determined by the states of transistors Q2 and Q3 (that is, dependent on whether they are on or off). Assume that the amplifying circuit shown in FIG. 14 is applied to a DRAM chip.
FIGS. 15(a)-15(c) are timing charts showing timings of switching external control signals and the address signal in the DRAM. Referring to FIGS. 14 and 15(a)-15(c), in the DRAM, the row address strobe signal /RAS (FIG. 5 (a)) falls to the low level at time t2 earlier than time t3 at which the column address strobe signal /CAS falls to the low level corresponding to the logic value of 0 during data writing and data reading. Thereafter, the row address strobe signal /RAS rises to the high level corresponding to the logic value 1 at time t5, at the same timing as the column address strobe signal /CAS. Data writing and data reading are carried out during the period in which the row address strobe signal /RAS is at the low level. More specifically, in data writing, the row decoder RD, column decoder CD and the data input circuit DI are enabled only during the period in which the row address strobe signal RAS is at the low level. In data reading, the row /decoder RD, the column decoder CD and data output circuit DO are enabled during the period in which the row address strobe signal /RAS is at the low level (see FIG. 11). The row decoder RD is enabled in response to the fall of the row address strobe signal RAS to the low level, while the column decoder CD is enabled in response to the fall of the column address strobe signal /CAS to the low level. Therefore, in the period when the row address strobe signal /RAS is at the low level, the row address signal and the column address signal corresponding to the memory cell to which or from which data is to be written or read must be surely applied to the row decoder RD and the column decoder CD while the row address strobe signal /RAS is at the low level. For this purpose, the row address signal, that is, the signal indicating the column in which the memory cell to which or from which data is to be written or read is arranged, and the column address signal, that is, the signal indicating the column in which the memory cell to which or from which data is to be written or data is to be read is positioned, must be externally applied little earlier than the enablement of the row decoder RD and the column decoder CD. Generally, the row address signal and the column address signal are applied to the same bonding pad.
Accordingly, as shown in FIG. 15 (c), in the DRAM, the row address signal R1 and the column address signal C1 indicating the position of said memory cell are applied at time t1 earlier than the time t2 of the fall of the row address strobe signal /RAS and at a time earlier than the time t3 of the fall of the column address strobe signal /CAS, respectively. As the row address signal R1 and the column address signal C1 are successively applied in the period when the row address strobe signal /RAS is at the low level, data is written to or data is read from the memory cell corresponding to the crossing of the row indicated by the row address signal R1 and the column indicated by the column address signal C1. The row address signal R1 and the column address signal C1 are both latched in the corresponding internal circuit, therefore they should be kept supplied externally for a time period necessary for them to be latched in the corresponding internal circuitry. Therefore, after the time t4 by which time the row address signal R1 and the column address signal C1 have been latched in the corresponding internal circuitry, signal potentials of any bits corresponding to the address signals may have arbitrary values. Therefore, from time t4 to the time t6 little earlier than the time t7 at which the row address strobe signal /RAS falls next, the potential of the bonding pads receiving the address signals may have any value, or it may be unstable. In the following, the period in which the row address strobe signal /RAS is at the low level is called an operational period of the DRAM, while the period in which the row address strobe signal is at the high level is called a standby period of the DRAM.
In any operational period, the column address strobe signal /CAS falls after the fall of the row address strobe signal /RAS. Therefore, at the start of the next operational period (time t7 to t10) following the first operational period (time t1 to time t5) of FIGS. 15(a)-15(c), the row address signal R2 and the column address signal C2 are applied in this order, indicating the position of an arbitrary memory cell. More specifically, the row address signal R2 is applied from time t6 little earlier than the time t7 at which the row address strobe signal /RAS falls, and the column address signal C2 is applied a little earlier than t8 at which the column address strobe signal /CAS falls. After the time t9 by which time the row address signal R2 and the column address signal C2 have been already latched in the corresponding internal circuitry, the potentials of any bonding pads receiving the address signals may have any values.
Generally, an input signal to the DRAM is applied with the TTL level. In other words, the potential not lower than 2.4 V is input as a signal having the logic value of "1" and a potential not higher than 0.8 V is input as a signal having the logic value of "0", to the internal circuitry of the DRAM. Since the DRAM is a MOS-IC formed of MOS transistors, the internal circuitry of the DRAM recognizes the power supply potential and the ground potential 0 V as signals having the logic values of 1 and 0, respectively. Generally, the power supply potential of a MOS-IC such as a DRAM is 5 V. Therefore, the threshold voltage of the inverter in the DRAM is set at about 2.5 V, that is, middle of the power supply potential 5 V and the ground potential 0 V. Referring to FIG. 14, transistors Q2, Q4 and Q6 are designed such that they are completely turned off when the gate potential rises to about 5 V, and that they are completely turned on when the gate potential lowers to about 0 V. Conversely, transistors Q3, Q5 and Q7 are designed such that they are completely turned on when the gate potential rises to about 5 V, and they are completely turned off when the gate potential lowers to about 0 V. If the gate potential is near 2.5 V, the transistors Q1 to Q7 are at the state corresponding to the boundary between the on and off states. More specifically, the conduction resistance of each of the transistors Q1, Q2, Q4 and Q6 gradually becomes smaller as the gate potential thereof lowers from the middle potential between the power supply potential and the ground potential, while conduction resistance of each of the transistors Q3, Q5 and Q7 gradually lowers as the gate potential thereof increases from the middle potential between the power supply potential and the ground potential.
Therefore, each of the inverters INV1, INV2 and INV3 outputs a potential lower than the intermediate potential when the input potential is higher than the intermediate potential between power supply potential and the ground potential, and it outputs a potential higher than the intermediate potential when the input potential is lower than the intermediate potential. Therefore, if the potential of the address signal Aj is at a potential corresponding to the logic value 1 of the TTL level (=2.4 V), not only transistor Q1 but also transistors Q2 and Q3 are turned ON, in inverter INV1. Thus, a through current flows from power supply Vcc to the ground GND through transistors Q1, Q2, and Q3. Consequently, potential at the node between transistors Q2 and Q3 is determined dependent on the ratio of conduction resistances of the transistors Q1 and Q2 and conduction resistance of transistor Q3, and hence it becomes lower than the intermediate potential between the power supply potential and the ground potential. Accordingly, the output potential from inverter INV2 becomes higher than the intermediate potential between the power supply potential and the ground potential, and thus the output potential from inverter INV3 becomes lower than the intermediate potential. Namely, a logic value inverse to the logic value represented by the address signal Aj is output from inverter INV3. Conversely, if the address signal Aj is at a potential corresponding to logic value 0 at the TTL level (=0.8 V), transistors Q2 and Q3 are respectively set to approximately complete ON and complete OFF as compared with the case when the address signal Aj is at a potential corresponding to the logic value 1 of the TTL level, the output potential of inverter INV1 attains about the supply potential 5 V. Thus the output potential from inverter INV2 becomes the ground potential, and the output potential of inverter INV3 becomes the power supply potential. Namely, in this case also, a logic value which is inverse to the logic value represented by the address signal Aj is output from inverter INV3.
In this manner the amplifying circuit shown in FIG. 14 inverts and amplifies the input external signal having the TTL level to the MOS level and outputs the same. However, in the period from time t4 to t6 in FIG. 15, that is, the period in which the potential of the address signal Aj may have any value, there is a problem that a through current continuously flows in inverter INV1. More specifically, in such a period, generally, the potential of each bit constituting the address signal is fixed to a potential corresponding to the logic value 1 or 0 of the TLL level, and therefore transistors Q1 and Q2 in inverter INV1 are not completely turned off. Especially when any of the n+1 signal potentials constituting the address signal is fixed at a potential corresponding to the logic value 1 of the TTL level, conduction resistances of transistors Q1 and Q2 both become sufficiently small in inverter INV1 in the first stage of the amplifying circuit provided corresponding to that signal. Consequently, a through current of considerable magnitude continuously flows during the standby period in the inverter INV1. This leads to larger power consumption of the DRAM.

Semiconductor device having no through current flow in standby period