Disclosed is a semiconductor device, including: stack structures including interlayer insulating patterns and conductive line patterns, which are alternately stacked, and separated by a first slit; string pillars passing through the stack structures; and dummy holes passing through top portions of the stack structures to be spaced apart from bottom surface of the stack structures and disposed between the string pillars.

1. Field
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a three-dimensional memory device and a method of manufacturing the same.
2. Discussion of Related Art
A semiconductor device includes a memory device capable of storing data. Recently, a three-dimensional (3D) memory device has been suggested for high integration of the semiconductor device.
The 3D memory device includes memory cells three-dimensionally arranged on a substrate. The memory cells may be serially connected to each other and coupled to a single memory string through a channel layer.
In a conventional method of forming the 3D memory device, sacrificial insulating layers are replaced with gate material layers. The process of replacing the sacrificial insulating layers with the gate material layers may cause various process defects, thereby degrading reliability of the 3D memory device.

Semiconductor device and method of manufacturing the same


A graphical display icon on the front of a data storage unit provides status information on disk drives within the unit. The icon has a shape identical to that of the unit and includes a number of bicolor LED's which each correspond to a similarly situated disk drive located in the unit. The color emitted by the LED's communicate information on the status of the corresponding disk drive within the unit.

1. Field of the Invention
The present invention relates to the use of disk drives in computer systems, and more particularly to a graphical display icon which is used to communicate information on the location and activity or error status of disk drives in the system.
2. Description of the Related Art
Computer systems are becoming increasingly large and complex and hence require increasing amounts of data storage capability. Computer systems are also being called upon to perform increasingly difficult tasks which require large amounts of data storage. This is particularly true of computer systems that serve as file servers in local area networks (LAN's). Additionally, computer systems are being called upon to perform critical tasks which require a high degree of data integrity and reliability. Therefore, a major area of growth in the computer industry has been to provide larger and more reliability data storage capabilities for computer systems.
Computer systems that require large amounts of data storage may include several drive bays or drive chambers comprising a plurality of disk drives. A common problem that may occur among disk drives is overheating of a drive, which may cause failure of the drive and loss of data. In addition, many different types of error conditions generally occur which may cause a particular disk drive to fail. In current computer systems, an operator generally must read a diagnostic file prepared by the operating system to determine if a particular logical volume has failed or has encountered an error condition. The operator must then correlate the logical volume with the physical disk drive and then determine the physical location of the drive to effect problem resolution. This multiple correlation is difficult and time consuming and can be almost impossible if the proper records cannot be found. Therefore, it is desirable to have an apparatus which informs an operator of the status of each of the disk drives in the system so that the operator is immediately notified of a failed disk drive or a disk drive which has encountered an error condition.


An electric motor apparatus and method of controlling the same are provided. The electric motor apparatus includes a stator and a rotor rotationally mounted coaxially with the stator; an intermediate screen having a magnetic material and rotationally mounted between the stator and the rotor to provide magnetic screening between the rotor and the stator; and control circuitry to control power supplied to windings on the rotor and the stator in dependence upon a desired output rotational speed.

There are several different ways of configuring electric motors each of which has its own associated advantages and disadvantages. Many of these configurations provide very efficient operations. However, this high efficiency is generally restricted to a particular optimum operating frequency of the motor and when the motor moves away from this operating frequency the efficiency may drop dramatically. In order to address this problem, motors of the prior art have been operated in conjunction with gearing systems, such that they can drive axles at different speeds, while still operating close to their own optimum rotation frequency. The provision of gears adds cost to the system and can themselves reduce efficiency.
One known type of motor is the universal motor which is schematically shown in FIG. 1 and has a rotor component and stator component that both have winding arrangements. Such a universal motor can be operated with either DC or AC power and generally provides a compact and high powered motor. To some extent, a universal motor can be viewed as combining the advantages of both induction motors and permanent magnet motors. However, the difficulties associated with coupling the required waveforms to the rotor winding arrangements have significant drawbacks. This problem is addressed in U.S. Pat. No. 8,450,954.
Although such a universal motor may provide a compact and high powered motor, the efficiency of such a motor still reduces dramatically away from an optimum operating frequency and thus, such a motor is generally operated in conjunction with some gearing mechanism.

Electronically controlled universal motor


A pattern transfer method includes first through third steps. In the first step, a desired pattern is transferred onto a resin layer formed on a substrate, a release layer being disposed between the substrate and the resin layer. In the second step, which is executed after the first step, the pattern having been transferred onto the resin layer is transferred to the substrate and the release layer is partially exposed. In the third step, which is executed after the second step, the release layer present between the substrate and the resin layer is dissolved and is thus removed from the substrate.

1. Field of the Invention
The present invention relates to a pattern transfer method.
2. Description of the Related Art
Nano-imprinting, a type of microprocessing technology that has been attracting a great deal of interest in recent years, is a technology whereby an indentation/projection (relief) pattern is transferred onto a substrate by using a mold having a fine relief pattern formed thereupon (see nonpatent reference literature: Spectroscopic Research vol 51, #4 (2002)). FIGS. 10A-10H illustrate a nano-imprinting method that may be adopted for pattern transfer. A substrate 110 having formed thereupon a resist film 120 is first prepared (see FIG. 10A).
Next, a mold 140 with a relief pattern formed thereupon is prepared and the surface of the mold 140 with the relief pattern is pressed against the resist film 120, thereby deforming the resist film 120 (see FIG. 10B). The mold 140 having been pressed against the resist film 120 is then separated from the resist film 120 (see FIG. 10C). The relief pattern at the mold is transferred onto the resist film 120 as a result.
Then, the residual resist 125 present over the area having been compressed by the mold 140 is removed through dry etching, thereby exposing the surface of the substrate 110 over the area (see FIG. 10D). Subsequently, a metal film 130 constituted of Ni or the like is vapor-deposited onto the substrate 110 (see FIG. 10E)). The resist film 120 is next removed by using an organic solvent (see FIG. 10F). Thus, only the metal film 130 having been directly deposited onto the substrate 110 remains on the substrate 110.
Using the remaining metal film 130 as a mask pattern, the surface of the substrate 110 is etched to a predetermined depth through an optimal etching method (see FIG. 10G). The metal film 130 is then removed from the etched substrate and, as a result, the substrate 110 with the relief pattern at the mold 140 transferred thereon is obtained (see FIG. 10H).
When transferring a pattern through nano-imprinting by using a resist as described above, the pattern cannot be sustained if it is transferred before pre-baking the resist. If the resist is to be pre-baked during the transfer, the mold needs to be formed by using a material that will withstand the baking process, which is bound to impose limitations on the choice of the material. Thermal deformation, which will prevent high-precision pattern transfer, is another problem that needs to be considered. Pattern transfer after the pre-baking process, on the other hand, is problematic in that the resist will have become hardened through the pre-baking process and thus the pattern cannot be transferred readily.
As an alternative to the resist, a resin may be used. The use of resin facilitates transfer of a curved pattern, e.g., a lens, which cannot be transferred with ease using a resist. However, it is difficult to reliably remove the resin following the etching process, leading to a problem of residual resin left on the substrate 110. The resin may be removed through, for instance, oxygen plasma ashing but it is still difficult to remove the resin reliably.


A system includes a database of image data associated with a vehicle; and control logic configured to cause a user device to capture one or more images and compare data associated with the one or more images with the image data to determine if a user is present in a vehicle and disable a text messaging function at least in part responsive to the determination using the image data.

1. Field of the Invention
The present invention relates to the use of and management of resources for mobile users.
2. Description of the Related Art
Financial services cards, such as debit, credit, and ATM cards, are ubiquitous. Fraud prevention is an increasingly difficult task.
Mobile devices, particularly smart phones and tablets, are seeing phenomenal growth. It is expected by industry analysts that the percentage of consumers who own smart phones soon will outstrip the ownership of the old-fashioned "feature phones." Tablets are increasingly being used for many information tasks by mobile users since their size is decreasing and they are becoming less cumbersome to use in a mobile setting.
Consumers carry mobile devices with them at all times and everywhere. It is a rare consumer who leaves his house without carrying one or more mobile device on his person. Consequently, consumers always have a mobile device handy and often use them in all kinds of situations and environments. Some of these situations may be dangerous to the consumers and/or the general public.
Recently, there have been a flurry of reports in the media highlighting the danger of drivers of automobiles text messaging while driving. Indeed, many fatal accidents have been reported in the press and several legislative bodies have outlawed such use of mobile devices. Drivers of trains and buses have also been charged with such acts of carelessness that have resulted in harm to the general public. The situation is not limited to text messaging but to many other kinds of services available on mobile devices such as games, phone calls, internet browsing, etc. The situation is also not limited to drivers of automobiles but also to operators of buses, public transportation systems, etc.
It is therefore of great public interest to find a general solution that can allow a service provider to detect when a driver or an operator of a transport device is engaged in activity that can potentially lead to a distracted state. Many methods and systems have been proposed to restrict consumers from text messaging while driving.
Certain proposed methods and systems require that the driver's telecommunication signal be jammed within the confines of the automobile. This is clearly unacceptable since it will also render the passenger mobile devices to become inoperative.
Certain other proposed methods rely on detecting when a mobile device (being carried on the person of a consumer) is in motion and rendering it incapable of text messaging (or other services). Again, this would be unacceptable if the device does not belong to the driver of the automobile.
It is therefore imperative to detect when the driver or operator of a car or any transport device is actually engaged in driving the car or transport device. Once such detection has been made, only the device in question should be isolated for any action that the policy of the service provider dictates

System and method for controlling mobile services using sensor information


A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control PET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control PETS and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control PET and the second sync PET via a second clip, respectively.

The present application claims the benefit of and priority to a pending provisional patent application entitled "Dual Phase Power Converter Package and Integration," Ser. No. 61/616,949 filed on Mar. 28, 2012. The disclosure in that pending provisional application is hereby incorporated fully by reference into the present application.
As electronic devices decrease in size, internal electrical circuit packages are, likewise, required to decrease in size as well as offer increased current density and current capacity. In addition, many electronic devices require multiple internal power supply voltages. However, conventional power supply designs, such as conventional buck converters, typically include a half-bridge circuit controlled by a dedicated control IC. Thus, multiple internal power supplies typically require multiple half-bridge circuits, each controlled by a respective control IC. However, conventional power supply packages including a single half-bridge circuit and a dedicated control IC require a physical layout considerably larger than either the half-bridge circuit or dedicated control IC alone. Consequently, utilizing multiple conventional power supply packages can be very space-inefficient, while also having undesirably low current and power densities as well as requiring a larger physical layout within the electronic device.

Dual power converter package using external driver IC


A method for transverse flux induction heating using a heating machine including an iron core, that essentially has a U-shape with an opening facing downwards. The legs lie in contact with downwards facing displaceable core jaws. These are so arranged that they are displaceable towards and from each other by means of pneumatic pistons. The object that is to be heated is placed between the core jaws. The core jaws are at the displacement guided by means of U-shaped rails and rolls or linear bearings. The displacement serves among other things to free the object that is to be heated or has been heated for transport into and out from the machine. When the right position has been reached the displacement is stopped and the two core jaws are locked by a pressurized bellow pressing the core jaws upwards against the legs of the U-shaped core. In this way a locking and a securing of as good contact as possible is obtained between the moveable core jaws and the U-shaped core so that the field is hindered as little as possible. Monitoring of heat parameters is done using one or more cameras.

The present invention relates generally to the field of inductive heating and in particular transverse flux induction heating. The object of the invention is to provide a more efficient and precise method of controlling the heating of an object.
One source of difficulties with inductive heating is that the properties and structure of the heating machinery will inevitably change with time. The powerful magnetic fields in the core will magnetize the different parts. Because the field is alternating the parts will possibly vibrate relative to each other. Over time, this means mechanical wear on the core. The ends of the core close to the object being heated become frayed causing changes in the field at and through the object. The part of the core close to the object being heated also becomes hot. This contributes to changes in the core and thus the magnetic field distribution. If the objects that are to be heated differ, for instance extrusion tools with different aluminum profiles, this also changes the heating circumstances.
For instance, when heating extrusion tools made of metals and alloys, in particular aluminum, an increased precision in controlling the heating is desired. These tools, before their use, must be heated in order to allow the aluminum to be pressed through the tool. Otherwise the aluminum xe2x80x9cfreezes solidxe2x80x9d and the tool might break. Conventionally, the tools are heated for many hours or days in an oven before the extrusion tool is mounted in the extruding machine. In the beginning of the extrusion process, neither the quality nor the quantity that is obtained for the extruded profiles is acceptable and one must wait a while before good quality and full production speed can be achieved. This occurs when the surface of the tool that is in contact with the aluminum has arrived at essentially the same temperature as the heated aluminum. Also, if a tool is inserted too cold, the risk that it breaks is great, because heat tensions may arise and the pressure from the press is very large.
In view of these problems, it is the object of the present invention to provide a method of inductive heating for an object and the monitoring of the heating, thereby dealing with the aforementioned issues.
In accordance with this invention, the problems with wear on the heating machinery are dealt with by monitoring the heating and adjusting it, if needed. The heating parameters may be altered by: changing the core topography at the surface facing the object to be heated; or by altering the relative positions of the core and the object to be heated; or combinations thereof so for instance a non-uniform heating can be counteracted. Also, the current fed to the magnetizing coils can be adjusted.
Additionally, the invention undertakes the heating of an extrusion tool before its mounting in the press by means of induction whereby the local temperature distribution may become very close to what exists during the continuous extruding process.
It also diminishes the time before the quality of the extrusion profile is acceptable and limits the loss due to rejection at the beginning of the process. Therefore, frequent changes of the tools are possible, if desired, with only small storage requirements. Overall, this method is a good use of expensive extruding presses.
Moreover, the tools are not overheated by this process. This is a great benefit because in some cases, the peripheral parts do not have to be heated to the same temperature as the rest of the object. In other situations, the inner working surface of the tools does not need to be heated to its full working temperature until shortly before it is put to use. Uniform heating would occur if an oven was used, but this does not necessarily occur with this invention. This is advantageous because at the working temperature the air could easily corrode the tools.
The heat monitoring is accomplished by means of a heat camera. For example, this method can be used to find the proper profile for heating of an extrusion tool. First, an extrusion tool that was just used is lifted into the heating device and the heat camera(s) register(s) the heat picture. This picture is then stored. Next time that tool needs to be used, it is heated as close as possible to the previous heat picture or the proper heat picture is extrapolated for when the tool is functioning properly.
Also, another application is crimp fittings (railroad wheels on axles, for instance). The controllable heating in accordance with the invention may find use in the hardening of cogwheels, cog, etc. because it minimizes use of effort and time, and reduces the strain and temperature influence on treated objects due to non-uniform heating. Similarly, for ball bearing races, the heating can be controlled to achieve a uniform heating.
In accordance with this invention, the control of the heat generation may, for instance, be achieved by the use of specific adaptors between the object that is to be heated and the magnetic core, thereby closing the magnetic field in the heating device. Alternatively, the adaptation method used can be varied with time. This can be done, for instance, by switching the adaptation means. By varying the times of the different adaptation means, it is possible to gain good control of the heating process.
In particular, the core or core jaw may include an elongated part that corresponds to an opening or channel in the core or core jaw. This channel is displaceable and extendable for the insertion into depressions of a heated object or can be slid through this if the opening in the heated object is large. For instance circular objects, such as ball bearing races, may be uniformly heated in this way, because the circular objects function as a secondary winding in a transformer. Because the current heating of the object is the same all the way around, the heating will be uniform. Even several races may be heated simultaneously by being fed or replaced one at a time in the heating location. By this method, the heating time may be multiplied by the number of races that are heated simultaneously. This can increase the feed speed. By monitoring only the races that have been there the longest and that are to be removed at the next feed interruption, the time or field strength can be controlled to give precisely the right temperature or heating conditions. Also, a high production rate is possible without sacrificing the time that the heated object has to remain heated in order to obtain the intended molecular reorganization before, for instance, cooling at hardening.
A further degree of freedom in the heating is obtained by varying the strength and frequency of the magnetic field. A lower frequency results in a deeper heating while a higher frequency results in a more superficial heating.
It is also possible to use magnetic shielding to reduce heating of specific parts or objects by screening or shortcircuiting of the field.
Further advantages and characteristics of the invention are apparent from the patent claims and the following description of an embodiment described with reference to the drawings.

Method for inductive heating and monitoring


A system and method for monitoring real-time operational data of a robotic manipulator. The system includes a robotic manipulator, a robotic manipulator controller, an electronic processor, a memory, and an output device. The memory includes a robotic manipulator profile, the robotic manipulator profile including a history of robotic manipulator operational data. The robotic manipulator controller is configured to generate a data packet based on signals relating to various operations of the robotic manipulator, and transmit the packet to the electronic processor. The electronic processor is configured to process the data contained in the data packet, update the robotic manipulator profile based on the processed data, and generate an alert that is output to the output device based on the updated robotic manipulator profile.

Robotic manipulators are used in manufacturing to move and position parts or tools within a work envelope. Robotic manipulators, such as six-axis robotic arms, are equipped with a plurality of actuators controlled by a controller. The controller is configured to provide commands to the actuators by interpreting movement instructions given by a user or a program. When controlled by the controller, the actuators can move one or more links of the robotic manipulator by producing a rotational force at one or more joints that connect the links.
Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.
The apparatus and method components have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments of the present invention so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein.

Monitoring real-time data of a robotic manipulator


A spin MOSFET includes: a first ferromagnetic layer provided on an upper face of a semiconductor substrate, and having a fixed magnetization direction perpendicular to a film plane; a semiconductor layer provided on an upper face of the first ferromagnetic layer, including a lower face opposed to the upper face of the first ferromagnetic layer, an upper face opposed to the lower face, and side faces different from the lower face and the upper face; a second ferromagnetic layer provided on the upper face of the semiconductor layer, and having a variable magnetization direction perpendicular to a film plane; a first tunnel barrier provided on an upper face of the second ferromagnetic layer; a third ferromagnetic layer provided on an upper face of the first tunnel barrier; a gate insulating film provided on the side faces of the semiconductor layer; and a gate electrode provided on the side faces of the semiconductor layer with the gate insulating film being interposed therebetween.

1. Field of the Invention
The present invention relates to a spin MOSFET and a reconfigurable logic circuit.
2. Related Art
In recent years, MRAM (Magnetic Random Access Memory) with a MTJ (Magnetic Tunnel Junction) having a tunnel barrier layer interposed between two vertical magnetization films has been drawing attention, for its lower spin injection current density and excellent thermal stability. In this specification, a "vertical magnetization film" is a ferromagnetic film that has a magnetization direction (a magnetization easy-axis direction) substantially perpendicular to its upper face.
Meanwhile, intensive research and development are being made with respect to devices having novel functions such as spin MOSFETs. One of those devices is a spin MOSFET having source/drain regions made of a magnetic material. A spin MOSFET is characteristically capable of controlling its output properties simply by reversing the direction of the spin moment of the magnetic material of the source/drain regions. By taking advantage of this feature, it is possible to form a spin MOSFET having a reconfigurable function and an amplifying function, or a reconfigurable logic circuit (see APL84 (2004) 2307, for example).
As a spin torque transfer switching method, a write method involving spin injection has been suggested. A spin torque transfer switching can be seen by spin-injecting spin-polarized current. Also, to apply spin injection writing to spin MOSFETs, a structure having a MTJ in one of the magnetic bodies forming the source/drain regions has been suggested (see JP-A 2008-66596 (KOKAI)). With the use of the structure disclosed in JP-A 2008-66596 (KOKAI), the following effects can be achieved:
1) Two outputs can be used for reading; and
2) A spin torque transfer switching can be utilized, since a MTJ (a ferromagnetic stacked film) is provided.
Also, the use of vertical magnetization films in the MTJ in the source/drain region in a spin MOSFET has been suggested by the inventor, and has been filed for a patent by the applicant (Japanese Patent Application No. 2008-191146). In this spin MOSFET, source/drain regions are provided at a distance from each other in a semiconductor substrate, and a gate electrode is formed on a semiconductor region to be the channel region between the source region and the drain region. A ferromagnetic stacked film having a vertical magnetization film is provided on each of the source/drain regions, and at least one of the ferromagnetic stacked films on the source/drain regions has a MTJ structure (hereinafter also referred to as a lateral structure). With this structure, the spin-injection write current density can be lowered, the areas of the source/drain portions can be reduced, and thermal stability can be advantageously secured in a spin MOSFET.
In a case where vertical magnetization films are used in the MTJ of the source or drain region, however, a leakage magnetic field generated from the fixed magnetization layer of the MTJ affects the magnetic recording layer, and shift adjustment cannot be performed, as will be described below. Such a leakage magnetic field also affects adjacent spin MOSFETs. In such a spin MOSFET having a lateral structure including vertical magnetization films, spin relaxation in the semiconductor region to be the channel region is accelerated due to the leakage magnetic field. This problem was not recognized in the past, and was recognized first by the inventor.
As described above, in a spin MOSFET using vertical magnetization films in the ferromagnetic material of the MTJ in the source/drain region, the spin-injection write current density becomes lower, and excellent thermal stability and the likes can be achieved. However, a spin MOSFET having a lateral structure has the following problems: difficult field shift adjustment, influence of a leakage magnetic field on adjacent transistors, and accelerated spin relaxation in the semiconductor region to be the channel region due to the leakage magnetic field.

Spin MOSFET and reconfigurable logic circuit


A semiconductor device includes a first voltage generator which outputs a first signal to a first node, a second voltage generator which outputs a second signal to a second node, a capacitor coupled between the first and second nodes; and a current supply circuit coupled to said second node. While the first voltage generator outputs the first signal to set the first node to a first voltage potential, the second voltage generator is activated to output the second signal to set the second node to a second voltage potential. At that time, the capacitor influences to the second node, based on a coupling capacitance thereof and the current supplying circuit supplies a current to suppress the influence.

1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device having an internal voltage generating circuit.
2. Description of Related Art
In some cases, a semiconductor integrated circuit device uses a plurality of internal voltages different from an external power supply voltage (hereinafter referred to as VCC) for ensuring the reliability, reducing power consumptions, ensuring operations, and so on. These internal voltages include a variety of types, such as a positive internal voltage lower than VCC, a positive internal voltage higher than VCC and a negative internal voltage lower than an external ground voltage (hereinafter referred to as GND). These internal voltages are generated by their corresponding internal voltage generating circuits, and driven into a predetermined voltage with the charge of parasitic and stabled capacitances formed within a semiconductor substrate. Furthermore, it is necessary to complete a setup operation at the time of setup such as power-on of the semiconductor integrated circuit device so that these internal voltages reach a predetermined electric potential within a time period defined by specifications.
For the semiconductor integrated circuit device, for example a DRAM which is one type of semiconductor storage device, a memory cell comprises one cell transistor and one cell capacitor. An internal voltage VBB for a back gate bias (hereinafter referred to as VBB), which is a negative voltage, is applied to a back gate region of the cell transistor. An internal voltage VPLT for a cell plate (hereinafter referred to as VPLT) is applied to an opposite electrode of the cell capacitor. Furthermore, an internal voltage VBL for precharge of a bit line pair (hereinafter referred to as VBL), an internal voltage VPP for setting of a word line (hereinafter referred to as VPP), which is higher in electric potential than VCC, as a selection voltage for a word line, and an internal voltage VNN for reset of a word line (hereinafter referred to as VNN), which is at a negative electric potential, as a non-selection voltage for a word line are used.
Internal voltages used in a memory core region on which memory cells are formed, for example VBB, VPLT, VBL, VPP, VNN are driven into a predetermined voltage by charging a parasitic capacitance between impurity diffusion regions within the memory core region. Furthermore, these internal voltages are mutually capacitive-coupled through the parasitic capacitance.
In order to generate a positive internal voltage higher than VCC and a negative internal voltage lower than GND as described above, the internal voltage is generally driven into a predetermined electric potential using a charge pump circuit comprising a capacitive element. There are various kinds of factors that determine the current drive capacity of the charge pump, but one of the major factors is the area of the capacitive element. The current drive capacity of the charge pump circuit is proportional to the area of the capacitive element. Therefore, for increasing the current drive capacity of the charge pump circuit, the area of the capacitive element included in the charge pump circuit may be increased. However, high integration is hindered because the block area of the charge pump circuit increases. Thus, it is necessary to make a design to decrease the current drive capacity of the charge pump circuit so that the circuit area becomes as small as possible while ensuring a necessary and sufficient capacity in consideration of loads on the charge pump circuit at the time of power-on setup operation, standby operation and active operation.
Incidentally, as the process has become precise and the capacity of memories has been increased in recent years, a parasitic capacitance to be charged within a memory core has increased, and accordingly, it has become necessary to increase the current drive capacity of the internal voltage generating circuit. For example, VBB is generated only by biasing the back gate region of the cell transistor to a negative voltage at the time of standby operation and active operation, and the VBB generating circuit may have a moderate current drive capacity capable of absorbing voltage variations by a leak current. However, at the time of power-on setup operation, a parasitic capacitance to be charged increases, and therefore a high current drive capacity corresponding to the parasitic capacitance is required.
When a design is made to increase the current drive capacity of the VBB generating circuit in accordance with the power-on setup operation, it is necessary to increase the capacitive element of the charge pump circuit, and the area of the circuit becomes so large that high integration is hindered. Conversely, when a design is made to decrease the current drive capacity of the VBB generating circuit in accordance with the standby operation, it may be impossible to complete the power-on setup operation so that a predetermined electric potential is reached within a time period defined by specifications. In this connection, explanations are presented here for VBB, but the same applies for internal voltages other than VBB.
Thus, a semiconductor integrated circuit device is known which drives (overdrive) VPLT and the like to be higher than an originally required electric potential at the time of power-on setup and then reduces, by a coupling capacitance, VBB connected to VPLT by the coupling capacitance at the time of drop in voltage after the overdrive (see, for example, Patent Documents 1 and 2). According to such a semiconductor integrated circuit device, a capacity of driving the internal voltage into a negative voltage at the time of power-on setup operation can be reinforced without increasing the drive capacity of the internal voltage generating circuit for VBB. Therefore, the drive capacity at the time of power-on setup can be reinforced without increasing the circuit scale of the VBB generating circuit itself, thus allowing the power-on setup of VBB in a short time.
[Patent Document 1] Japanese Patent Laid-Open No. 2004-334583 (FIG. 2)
[Patent Document 2] Japanese Patent Laid-Open No. 2005-353186 (FIGS. 4 and 15)
Incidentally, when a negative internal voltage and another negative internal voltage are mutually coupled by a parasitic capacitance, e.g. VBB and VNN are mutually coupled by a parasitic capacitance, Patent Document 2 discloses two types of methods for driving these internal voltages. FIG. 5 is a time chart showing a change in voltage waveform of each part of a semiconductor integrated circuit device according to a first method (corresponding to FIG. 15 of Patent Document 2). In FIG. 5, VPLT, VBB and VNN are fixed to GND until time T1. At time T1, VPLT is increased toward an electric potential V4 higher than a normal predetermined electric potential V5 (overdrive operation).
When VPLT reaches the electric potential V4 at time T2, the overdrive operation is stopped. In the overdrive operation at time T1 to T2, VBB and VNN are fixed to GND (clamp state).
At time T2 when VPLT reaches the electric potential V4, the clamp of VBB and VNN to GND is cancelled to reduce VPLT to the normal predetermined electric potential V5 (voltage drop state). VBB decreases from GND toward a negative voltage by capacitive coupling, since it is coupled through the coupling capacitance of VPLT and VBB. After time T2, VBB ultimately reaches a predetermined negative electric potential V7 due to depressing by the drive capacity of the VBB generating circuit itself and the coupling capacitance with VPLT (at time T3). After time T3, VBB is driven so as to be kept at the predetermined negative electric potential V7.
Furthermore, at time T2, a coupling capacitance exists between VNN and VBB, and therefore following a reduction in VBB, the electric potential of VNN decreases by capacitive coupling. VNN operates so that it reaches the negative electric potential V7 as in the case of VBB at time T3, and the electric potential of VNN after time T3 is kept at the negative electric potential V7 as in the case of VBB.
According to the first method, if it is desired to make VNN and VBB different, it is necessary to increase an output drive capacity in a VNN generating circuit for canceling charges supplied by the coupling capacitance to drive the voltages into further desired voltages. Thus, it is necessary to increase a circuit scale related to the VNN generating circuit.
FIG. 6 is a time chart showing a change in voltage waveform of each part of a semiconductor integrated circuit device according to a second method (corresponding to FIG. 4 of Patent Document 2). In FIG. 6, the explanations of the process until time T2 are omitted because it is same as that in FIG. 5. At time T2 when VPLT reaches the electric potential V4, the clamp of VBB to GND is cancelled to reduce VPLT to the normal predetermined electric potential V5 (voltage drop state). VBB decreases from GND toward a negative voltage by capacitive coupling, since it is coupled through the coupling capacitance of VPLT and VBB. After time T2, the electric potential of VBB ultimately reaches the predetermined negative electric potential V7 due to depressing by the drive capacity of the VBB generating circuit itself and the coupling capacitance with VPLT (at time T3). After time T3, VBB is driven so as to be kept at the predetermined negative electric potential V7.
Furthermore, VNN is clamped to GND until time T3, and the clamp of VNN to CND is cancelled at time T3. After time T3, VNN ultimately reaches a predetermined negative electric potential V6 due to the drive capacity of the VNN generating circuit itself (at time T4). After time T4, VNN is driven so as to be kept at the predetermined negative electric potential V6.
According to the second method, there is the concern that time for completion of the setup is prolonged to time T4, thus making it difficult for VNN to reach a predetermined negative electric potential within a time period defined by specifications.
As described above, in the related art, there is the concern that an output voltage cannot be set to a desired voltage within a predetermined time period without increasing the circuit scale of the voltage generating circuit. In this connection, explanations have been presented for VBB and VNN in the above description, but the same applies for combinations of internal voltages other than VBB and VNN.

Semiconductor integrated circuit device having internal voltage generating circuit


An iron base amorphous alloy strip having a sheet thickness of from 50 to 150 .mu.m and a sheet width of at least 20 mm. The strip is produced by a single-roll cooling process and has a fracture strain of 0.01 or more.

1. Field of the Invention
The present invention relates to amorphous alloy strips having a large thickness and a method for producing the same, more particularly to amorphous alloy strips having a large thickness produced by quenching and solidifying molten metal or alloy on a movable cooling substrate and a method for the same.
2. Description of the Related Art
It is well known to use a melt spin process to continuously produce amorphous strips from molten metal or alloy. In the melt spin process, molten metal is deposited onto a cooling substrate, e.g., the surface of annular chill roll, through a nozzle or nozzles. The molten metal is quenched and solidified by the cooling substrate, resulting in a continuous metal strip or wire.
In the melt spin process, the cooling rate is so high that, if the composition is suitably selected, an amorphous metal or alloy having substantially the same structure as the molten metal can be obtained. An amorphous metal or alloy has unique properties valuable for practical applications.
There are, however, some difficulties in obtaining wide strips. Important factors in the production of an amorphous metal or alloy are the shape of the nozzle, the relative arrangement of the nozzle and cooling substrate, the ejecting pressure of the molten metal through the nozzle, and the moving rate of the cooling substrate. To increase the width of the strip, one must meet severe conditions for each of the above.
A continuous casting method for a metallic amorphous strip and an apparatus for producing a wide strip are disclosed in Japanese Unexamined Patent Publication (Kokai) No. 53-53525. The method includes the steps of directing a slotted nozzle having a rectangular opening to a cooling substrate (roll or belt) with a gap of from about 0.03 to about 1 mm therebetween, advancing the cooling substrate at a speed to provide a peripheral velocity of from about 100 to about 2000 meters per minute, and ejecting molten metal to the chill surface of the cooling substrate through the slotted nozzle. The molten metal is quenched in contact with the chill surface at a rapid quenching rate and solidifies into a continuous amorphous metal strip. In this method, there is no limit on the width of the amorphous metal strip, in principle.
Restrictions on the cooling rate also make it difficult to obtain a thick strip. The problem of thickness of increasing the thickness of the strip has not been solved up until now. This limit on the thickness of the strip applies not only to amorphous metal requiring severe cooling conditions, but also to crystalline metal not requiring the same. The principal method adoptable to try to form a metal strip having a large thickness in the conventional continuous molten metal quenching process is to increase the advancing length of the puddle formed on the cooling substrate with respect to the advancing speed of the cooling substrate. In actual production of an amorphous metal strip, any one of the following means or combinations thereof may be considered to achieve this increase: The means are
1. To enlarge the width of the nozzle opening
2. To increase the forcing pressure
3. To increase the gap between the nozzle and the chill surface
4. To decrease the advancing speed of the cooling substrate
The present inventors experiments to produce an amorphous metal strip having a large thickness by using the above four means, but could not obtain good results. They found that there is a limit on thickness due to the type of metal or alloy and the material of the cooling substrate and that an unreasonable increase in thickness leads to an undesired shape and deterioration of the strip. Excessive molten metal, specifically, adheres to the nozzle and solidifies thereon. The solidified metal, which contacts the advancing chill surface, leads to nozzle breakage. Also, when a thick strip is produced by the above four means, the free surface of the metal strip is exposed to the atmosphere for a longer time, resulting in an undesired appearance, such as a rough surface, furrows, and coloring. Generation of such phenomena, in the case of an amorphous alloy, means also that crystal is formed on the surface layer, even if the crystal cannot be detected by X-ray diffraction. This reduces the ductility, the magnetic properties such as coercive force and core loss , and other properties of the amorphous alloy.
IEEE Trans., May 18 (1982) page 1385, discloses that if the strip thickness at which the coercive force begins to increase is defined as the critical strip thickness at which crystallization commences, the greatest critical strip thickness shown by an Fe-Si-B system alloy is 42 .mu.m of Fe.sub.76 -B.sub.10 -Si.sub.10. According to investigations by the present inventors, with Fe.sub.80.5 Si.sub.6.5 B.sub.12 C.sub.1 of a width of 25 mm, the critical strip thickness is 32 .mu.m. Further U.S. Pat. No. 4,331,739 discloses F.sub.40 Ni.sub.40 P.sub.14 B.sub.6 of a width of 5 cm, a thickness of 0.05 mm (50 .mu.m), and isotropic tensile properties.
Recently, an Fe base alloy strip having a width of 25.4 mm and a thickness of 82 .mu.m was reported (Journal of Applied Physics vol. 5, No. 6 (1984) P. 1787). According to the report, however, this alloy strip, of Fe.sub.80 B.sub.14.5 Si.sub.3.5 C.sub.2 showed the existence of 5% or less crystals under an X-ray diffraction test. As a consequence, the alloy strip as cast shows considerable brittleness. The fracture strain by bending stress of an 82 .mu.m thick Fe.sub.80 B.sub.14.5 Si.sub.3.5 C.sub.2 alloy is 0.006. The fracture strain .epsilon..sub.f is usually represented by the equation .epsilon..sub.f =t/(2r-t), wherein t is the strip thickness and r is the bending radius.
The more amorphous the alloy, the greater the fracture strain. A substantially amorphous alloy has a crystallization ratio of 1% or less as cast. The crystallization ratio is defined as follows: EQU Fc=(I-Io)/Ic
wherein I is the diffraction intensity on a specified crystal face for example (110) face of a sample of a strip as cast, Io is the diffraction intensity on the same crystal face of a standard amorphous sample, and Ic is the diffraction intensity on the same crystal face upon complete crystallization.

Amorphous alloy strip having a large thickness


A transducer array and method for medical imaging which produces an ultrasound beam upon excitation, the transducer array including a plurality of transducer elements, each of said transducer elements having a first surface facing a region of examination when the transducer is in use and a second surface opposite of the first surface wherein the second surface faces away from the region of examination when the transducer is in use, said second surface is concave in an elevation direction, and a focusing lens disposed on the first surface of each element.

Ultrasound machines are often used for observing organs in the human body. Typically, these machines contain transducer arrays for converting electrical signals into pressure waves. Generally, the transducer array is in the form of a hand-held probe which may be adjusted in position to direct the ultrasound beam to a region of interest. Transducer arrays may have, for example, 128 transducer elements for generating an ultrasound beam. An electrode is formed on a top and bottom surface of each transducer element and each transducer element is individually excited to generate pressure waves as is well known. The pressure waves generated by the transducer elements are directed toward a region of examination, and more particularly, an object to be observed, such as the heart of a patient being examined. Each time the pressure wave confronts tissue having different acoustic characteristics, a wave is reflected backwards to the transducer. The array of transducer elements converts the reflected pressure waves into corresponding electrical signals. An example of a phased array acoustic imaging system is described in U.S. Pat. No. 4,550,607 which is incorporated herein by reference. That patent illustrates circuitry for combining the incoming signals received by the transducer array to produce a focused image on a display screen.
Broadband transducers are transducers capable of operating at a wide range of frequencies without a loss in sensitivity. As a result of the increased bandwidth provided by broadband transducers, the resolution along the range direction may improve, thereby resulting in better image quality. One possible application for a broadband transducer is contrast or tissue harmonic imaging. In contrast harmonic imaging, contrast agents, such as micro-balloons of protein spheres, are injected into a body to illustrate how much of a certain tissue, such as the heart, is active. These micro-balloons are typically one to five micrometers in diameter and, once injected into the body, may be observed via ultrasound imaging to determine the degree of blood perfusion in the tissue being examined. B. Schrope et al. "Simulated Capillary Blood Flow Measurement Using a Nonlinear Ultrasonic Contrast Agent." Ultrasonic Imaging, Vol. 14 at 134-58 (1992), which is incorporated herein by reference, disclose that an observer may clearly see the contrast agent at the second operating harmonic. That is, at the fundamental frequency, the heart and muscles tissue is clearly visible via ultrasound techniques. However, at the second harmonic, the observer is capable of clearly viewing the contrast agent itself. In addition, it may be desirable to provide an ultrasonic system that is responsive to reflected harmonic signals even when a contrast agent is not injected into a body because tissue itself produces a non-linear response.
Because contrast and tissue harmonic imaging requires that the transducer be capable of operating at a broad range of frequencies (i.e., at both the fundamental and second harmonic), existing transducers typically cannot function at such a broad range. For example, a transducer having a center frequency of 5 Megahertz and having a 70% ratio bandwidth to center frequency has a bandwidth of 3.25 Megahertz to 6.75 Megahertz. If the fundamental frequency is 3.5 Megahertz, then the second harmonic is 7.0 Megahertz. Thus, a transducer having a center frequency of 5 Megahertz would not be able to adequately operate at both the fundamental frequency and second harmonic frequency.
U.S. Pat. Nos. 5,415,175 ("the U.S. Pat. No. '175") and 5,438,998 ("the U.S. Pat. No. '998"), assigned to the present assignee and specifically incorporated herein by reference, disclose a mechanically focused transducer array in which the surface of each transducer element that faces a region of examination when the transducer is in use, is preferably concave in shape and each transducer elements has a non-uniform thickness measured in the range direction. Preferably at least one acoustic matching layer is disposed over each transducer element and the acoustic matching layer also has a non-uniform thickness and a concave surface facing the region of examination. The combination of the curved transducer element and acoustic matching layer provides focusing in the elevation direction. Typically a non-refractive protective layer such as polyurethane is placed on a front surface of the transducer array. Because each transducer element has a non-uniform thickness, by controlling the excitation frequency, an operator can control which section of the transducer element generates the ultrasound beam. At higher excitation frequencies, the beam is primarily generated from the center of the transducer element and at lower excitation frequencies, the beam is primarily generated from the full aperture of the transducer element.
U.S. Pat. No. 4,4788,085 discloses an ultrasound transducer that has a plurality of transducer elements that are non-uniform in thickness. In one embodiment shown in FIGS. 8A-D of this patent, each transducer element has a front surface that faces a region of examination when the transducer is in use that is planar and a back surface, opposite of the front surface, that is concave and each transducer element has a non-uniform thickness measured in the range direction. A single matching layer 32 is disposed over the transducer element 31 and an acoustic lens 33 is disposed on the matching layer. Sasaki does not provide details regarding the acoustic lens material, however, the lens has a convex/concave shape and is probably lossy. In addition to having a transducer which is capable of operating at a broad range of frequencies, two-dimensional transducer arrays are also desirable to increase the resolution of the images produced. An example of a two-dimensional transducer array is illustrated in U.S. Pat. No. 3,833,825 to Haan issued Sep. 3, 1974 and is incorporate herein by reference. Two-dimensional arrays allow for increased control of the excitation of ultrasound beams along the elevation axis, which is otherwise absent from conventional single-dimensional arrays. However, two-dimensional arrays are also difficult to fabricate because they typically require that each element be cut into several segments along the elevation axis, connecting leads for exciting each of the respective segments. A two-dimensional array having 128 elements in the azimuthal axis, for example, would require at least 256 segments, two segments in the elevation direction, as well as interconnecting leads for the segments. In addition, they require rather complicated software in order to excite each of the several segments at appropriate times during the ultrasound scan because there would be at least double the amount of segments which would have to be individually excited as compared with a one-dimensional array.
It is thus desirable to provide a transducer array that employs a low loss acoustic lens and a plurality of sharply focused acoustic matching layers. It is also desirable to provide a transducer array that provide 1.5 or 2 dimensional imaging without the system complexity or channels required of typical 1.5 and 2 dimensional arrays.

Limited diffraction broadband phased array transducer with frequency controlled two dimensional aperture capability


A miniaturized diffractive imaging spectrometer (DIS) has a footprint less than 2×1 mm2, is about 2.5 mm tall (excluding an image detector, which in some embodiments may be a CCD matrix), and covers the entire visible spectral range from 400 nm to 700 nm with resolution of approximately from 2 nm to 4 nm across the field. The DIS is able to function with multiple input waveguide channels, and is flexible in its various possible configurations, as it can be designed to achieve better resolution or higher number of channels or wider spectral range or smaller size.

1. Field of the Invention
This invention relates generally to spectral devices for applications such as lab-on-a-chip for biological and chemical analysis, and more particularly, to a Diffractive Imaging Spectrometer ("DIS") in the form of a highly compact device, which takes multiple optical input signals from input channel waveguides, and produces a spectrally resolved image, covering a wide spectral range with high resolution.
2. Description of the Related Art
Small scale spectral devices are required for applications, such as lab-on-a-chip, for biological and chemical analysis. The integration of microfluidics, microelectronics, and integrated optics on a single chip or wafer is essential for the practical implementation of a micro total analysis system (μTAS), for example. Reduced overall size and weight are also essential factors for experimental research tools used in space and aircraft-based laboratories.
For biological or chemical applications, fluorescence and absorption spectroscopy are the main types of optical measurements required for μTAS applications. Unfortunately, small footprint spectrometers have low resolution. To date, various schemes have been proposed for producing high-resolution optical spectrometers. However, these devices still have unacceptably large footprints, typically on the order of about several square centimeters. Microspectrometers that would be acceptable for μTAS applications must have footprints that are two orders of magnitude smaller, while still covering a wide spectral range of several hundred nanometers and having a resolution on the order of single nanometers. Moreover, the development of a practical μTAS requires a device that has the ability for parallel processing of multiple optical inputs. There is not presently available, a microspectrometer having the aforesaid features.
There is therefore a need for an analytical spectral device that is highly compact and low in weight. It is important that the reduction in size and weight not affect adversely limit the ability of the device to receive input from multiple sources, or to limit its resolution.
It is, therefore, an object of this invention to provide a highly compact DIS.
It is another object of this invention to provide a DIS that can receive multiple optical input signals from input channel waveguides.
It is also an object of this invention to provide a DIS that can cover a wide spectral range with high resolution.
It is a further object of this invention to provide a DIS that can easily be optimized for a particular application.


The object of this invention is to provide a phase stabilization device for stimulated brillouin scattering-phase conjugate mirrors and a light amplification apparatus using the phase stabilization device. A light amplification apparatus of the present invention includes a polarizer (70) for polarizing light beams reflected from a plurality of stimulated brillouin scattering-phase conjugate mirrors and causing the light beams to interfere with each other. A detector (80) acquires an interfering beam resulting from interference of the polarizer (70), and outputs the interfering beam. A phase controller (90) controls phase using the interfering beam acquired by the detector. Therefore, the apparatus of the present invention can stably lock the phase for a long period of time, and can be used in various industries and for scientific research in cases where a high repetition rate and high power are required.

Generally, since a stimulated brillouin scattering-phase conjugate mirror reflects a phase conjugate wave, it can compensate for distortion of a laser beam occurring during a laser amplification procedure. Therefore, a stimulated brillouin scattering-phase conjugate mirror can be very easily applied to a beam combination high power laser. Examples of a beam splitting amplification system using stimulated brillouin scattering-phase conjugate mirrors are described with reference to FIGS. 1 and 2.
FIG. 1 is a diagram showing a conventional wavefront-dividing amplification system using stimulated brillouin scattering-phase conjugate mirrors.
Referring to FIG. 1, light 505 emitted from a laser oscillator 500 is amplified and formed into more light beams while passing through a first light amplification stage 510, a second light amplification stage 540, and a third light amplification stage 570. That is, the light 505 is reflected from a Polarizing Beam Splitter (hereinafter referred to as a 'PBS'), is incident on a first beam blocker 520, and is reflected from a Stimulated Brillouin Scattering-Phase Conjugate Mirror (SBS-PCM). The reflected light passes through the PBS again and is incident on a first light amplifier 530. Thereafter, light incident on the first light amplifier 530 is amplified while passing through the first light amplifier 530. The amplified light is reflected from the SBS-PCM and is incident on the PBS. The PBS reflects the incident light and outputs the reflected light to an optical expander 535. The optical expander 535 expands the incident light and outputs the expanded light to the second light amplification stage 540. The second light amplification stage 540 is provided with a second beam blocker 550, which has the same structure as the first beam blocker 520 of the first light amplification stage 510, and which performs the same function. However, the second light amplification stage 540 further includes a wavefront-dividing beam splitter 562 disposed upstream of a second light amplifier 560. The second light amplifier 560 is formed in a 2×2 array. In this case, the wavefront-dividing beam splitter 562 is used to individually transmit light beams to components constituting the 2×2 array of the second light amplifier 560. That is, before light is incident on the second light amplifier 560, the wavefront of the light is divided by the wavefront-dividing beam splitter 562, and divided light beams are amplified by respective amplifiers arranged along optical axes thereof. The amplified light beams are reflected from an SBS-PCM, and are combined and incident on the PBS. The PBS reflects the incident light and outputs the reflected light to a beam expander 565. The beam expander 565 expands the incident light and outputs the expanded light to the third light amplification stage 570. In the third light amplification stage 570, a third light amplifier 590 is formed in a 4×4 array, and a third beam blocker 580 is formed in a 2×2 array. In this case, wavefront-dividing beam splitters 582 and 592 are used to transmit light to respective arrays.
When such a light amplification system is constructed, a desired number of amplification stages are successively connected to each other, thus not only freely increasing output energy without causing damage to the optical system, but also maintaining a repetition rate at a uniform level. That is, when energy density is increased due to continuous amplification, the optical system and laser gain media may be damaged if energy density is not decreased. Therefore, the expansion of laser light is required, but the size of the laser gain media must also be increased. This results in a decrease in the cooling rate of the laser gain media, and thus it is actually impossible to generate laser light having a high repetition rate. Therefore, the beam combination amplification apparatus of FIG. 1, which employs a method of increasing the size of laser light, but maintaining the size of gain media unchanged, has been used.
FIG. 2 is a diagram showing a conventional amplitude-dividing amplification system using stimulated brillouin scattering-phase conjugate mirrors.
Referring to FIG. 2, the amplitude-dividing amplification system is constructed to include a laser oscillator 100 for generating laser light, a Beam Expander (BE) 101 for expanding the laser light, a PBS 102 for reflecting the expanded light, a first amplification stage 200 for amplifying the reflected light, a BE 103 for expanding the light amplified by the first amplification stage 200, a second amplification stage 300 for amplifying the light amplified by the first amplification stage 200 again, and a BE 104 for expanding the light amplified by the second amplification stage 300, and is constructed to allow the light amplified by the second amplification stage 300 to be output to a third amplification stage (not shown).
In the first amplification stage 200, devices for light amplification, that is, a quarter-wave plate 201, a PBS 202, a BE 203, a Faraday Rotator (FR) 204, an amplifier 205, an FR 206, and a Phase Locker (PL) 207, are arranged along an optical path. Further, in the second amplification stage 300, devices for light amplification, that is, a PBS 301, a quarter-wave plate 302, a PBS 303, a 45-degree rotator 304, a PBS 305, a BE 306, an FR 307, an amplifier 308, an FR 309, and a PL 310, are arranged along an optical path.
The light, which is output from the laser oscillator 100 and is S-polarized, is expanded by the BE 101 and is reflected from the PBS 102, and the reflected light is incident on the first amplification stage 200. The light incident on the first amplification stage 200 is converted into circularly polarized light while passing through the quarter-wave plate 201. The circularly polarized light is amplitude-divided by the PBS 202, and thus part of the circularly polarized light (P-polarized light) is reflected from the PBS 202 and the remaining part thereof (S-polarized light) passes through the PBS 202. P-polarized laser light and S-polarized laser light are individually amplified while passing through an optical path formed by the BE 203, the FR 204, the amplifier 205, the FR 206, and the PL 207, and then pass through or reflect from the PBS 202 in the same polarization states. The laser light beams are combined before the quarter-wave plate 201, and are circularly polarized, like that of the light before it was amplitude-divided. Thereafter, the circularly polarized light passes through the quarter-wave plate 201 and is converted into P-polarized laser light. Further, the laser light amplified in this way passes through the PBS 102 and is expanded through the BE 103.
Then, the light expanded by the BE 103 is incident on the second amplification stage 300. The second amplification stage 300 is operated to amplitude-divide the incident light into four light beams, combine the amplified light beams with each other, and output the combined light to a subsequent third amplification stage (not shown). The PBS 301 of the second amplification stage 300 outputs incident light to the quarter-wave plate 302. The PBS 303 amplitude-divides the light output from the quarter-wave plate 302, passes P-polarized laser light therethrough, reflects S-polarized laser light, and individually outputs the passed laser light and reflected laser light to the 45-degree rotator 304. In this case, in order to amplitude-divide a single laser light beam into two beams, a single 45-degree rotator 304 is connected to a combination of two PBSs 305, and thus a 2×2 array structure is formed. When the P-polarized and S-polarized light beams pass through the 45-degree rotator 304, the polarization of each beam is rotated by 45 degrees. Thereafter, each of the polarized beams is amplitude-divided into two beams by the subsequent optical device, that is, the PBS 305. A subsequent process is omitted because the same functions are performed on the same construction as that of the above-described first amplification stage 200. When the beams pass through and return to the 45-degree rotator 304, polarization is rotated by 45 degrees and then by −45 degrees, and thus there is no variation in polarization. Therefore, since amplitude division using the 45-degree rotator and the PBS can be infinitely performed, infinite energy amplification is possible if an additional amplification stage is provided after the second amplification stage 300.
The beam splitter used in the beam combination light amplification apparatus of FIG. 1 employs a wavefront dividing method, which is shown in FIG. 3a.
As shown in FIG. 3a, a wavefront-dividing beam splitter splits incident light a into two output beams b. That is, the wavefront dividing method divides laser light into two small laser beams.
Meanwhile, the beam splitter may use the amplitude dividing method of FIG. 2 in addition to the wavefront dividing method. This method is shown in FIG. 3b.
Referring to FIG. 3b, the amplitude-dividing beam splitter splits incident light a into two output beams b so that one output beam passes through the beam splitter and the other output beam is reflected from the beam splitter. That is, in the amplitude dividing method, two beams have only divided energy without changing the sizes thereof. Compared to the amplitude dividing method, the wavefront dividing method applied to the conventional light amplification apparatus cannot have a laser light shape identical to that of a main oscillator, so that there is difficulty in that the section of the gain medium of an amplifier must be processed in the shape of laser light. The reason for this is that, when the section of the gain medium is different from the shape of incident light, amplification efficiency may decrease. Further, the spatial distribution of laser light includes high spatial frequencies, and thus phase conjugation may be broken when reflection occurs through an SBS-PCM. Further, in the case where the phases of two beams are different from each other in areas where two beams intersect when the light beams are combined after being amplified, intensity spikes occur, thus deteriorating the spatial distribution of light.
However, since stimulated brillouin scattering is caused by random noise, a reflected beam has a random phase. Therefore, the combined laser beams have spatially different phase distributions. In the case of FIG. 1 (wavefront division), spike occurs at the boundary, and in the case of FIG. 2 (amplitude division), energy loss occurs. Therefore, in order to apply an SBS-PCM to a beam combination laser system, the phases of respective reflected beams are locked, and the phase difference between the phases must be zero.
Conventional methods of controlling the phases of the reflected beams of the SBS-PCM are described below.
FIG. 4 is a configuration diagram showing a conventional phase locking method based on a focus-overlapping method using an SBS-PCM.
Referring to FIG. 4, this method is implemented to focus a plurality of beams onto the scattering medium of a single SBS-PCM while overlapping the focuses of the beams with each other. That is, traveling beams are caused to pass through a condensing lens, and thus a plurality of beams is focused on the SBS-PCM while overlapping each other.
FIG. 5 is a configuration diagram showing a conventional phase locking method based on the back-seeding of a Stokes wave using a stimulated brillouin scattering-phase conjugate mirror.
Referring to FIG. 5, the term "Stokes wave" means a laser beam having the same frequency as the reflected wave, which is reflected by stimulated brillouin scattering. This method is implemented to allow a back-seeding laser beam to pass through a focus, thus amplifying the back-seeding laser beam. That is, an incident seeding beam is incident on the SBS-PCM after passing through an optical path formed by optical devices, and is reflected from the SBS-PCM, so that a back-seeding laser beam is generated and amplified.
FIG. 6 is a configuration diagram showing a conventional first method of locking the phases of laser beams using stimulated brillouin scattering and self-beam feedback, and FIG. 7 is a diagram showing a conventional second method of locking the phases of laser beams using stimulated brillouin scattering and self-beam feedback. That is, FIGS. 6 and 7 illustrate self-phase control methods of allowing incident laser beams to pass through SBS-PCM and to feed the laser beams back to stimulated brillouin scattering media using concave mirrors and Piezoelectric Transducers (PZT), thus controlling acoustic noise. In particular, the self-phase control methods are advantageous in that they can control the phases of stokes beams regardless of the number of beams.
However, in the beam combination laser system, short-term or long-term phase drift, occurring due to variation in density caused by the thermal effect of media on an optical path or the heterogeneity of density caused by convection current, and variation in optical path length caused by vibration and thermal expansion of optical devices, may be a problem, in addition to the random phases of stimulated brillouin scattering itself. However, in the conventional phase locking methods, since such a problem is not considered when the phase of a Stokes wave is controlled, the phase cannot be efficiently controlled.
Therefore, in order to sufficiently lock the phase of the reflected beam of the SBS-PCM, a new phase stabilization method is required in addition to the conventional phase control methods.

Phase stabilization device for stimulated brillouin scattering phase conjugate mirrors and light amplification apparatus using the same

Korea Advanced Institute of Science and Technology


An address control system for a RAM, comprising a synchronous counter for receiving input data according to a clock signal and providing n-bit row column address, and an n-bit column address a first buffer for receiving the n-bit row address from the synchronous counter and generating the n-bit row address, a first tri-state inverter for outputting data stored in a ROM according to a write enable signal a second tri-state inverter for outputting reference data according to the write enable signal, an adder for adding the n-bit column address from the synchronous counter and output address signals from the first inverter, and a second buffer for receiving output signals from the adder generating a column address delayed from the n-bit column address.

The present invention relates to an address control system for a Random Access Memory (RAM) in a digital audio system, and more particularly to an address control system in a digital audio system capable of performing a pre-set function in order to efficiently use the RAM.
In a surround audio or sound field reproduction system, in general, since every sound emitted through a speaker is echoed with small or large time lags, causing time lagged sound to be heard, it is necessary for the system to employ a time delay processor to provide the central handling of the surround type. A much longer delayed time lag may be considered as a reproduction of large and wide echo circumstances but it becomes difficult to control the delayed time lag.

Address control system for a RAM in a digital audio set


Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A collector is formed in a semiconductor substrate, an intrinsic base is formed on the semiconductor substrate, and an extrinsic base is formed on the intrinsic base. An airgap is located vertically between the extrinsic base and the collector. A contact surface is located adjacent to the airgap. The contact surface is coupled with the collector. A spacer is located laterally between the airgap and the subcollector contact surface.

The invention relates generally to semiconductor device fabrication and, in particular, to heterojunction bipolar transistors, as well as fabrication methods and design structures for a heterojunction bipolar transistor.
Bipolar junction transistors are three-terminal electronic devices that include three semiconductor regions defining an emitter, an intrinsic base, and a collector. Heterojunction bipolar transistors are a variant of bipolar junction transistors in which at least two of the semiconductor regions are comprised of different materials. An NPN heterojunction bipolar transistor includes two regions of n-type semiconductor material constituting the emitter and collector, and a region of p-type semiconductor material sandwiched between the two regions of n-type semiconductor material to constitute the intrinsic base. A PNP heterojunction bipolar transistor includes two regions of p-type semiconductor material constituting the emitter and collector, and a region of n-type semiconductor material sandwiched between the two regions of p-type semiconductor material to constitute the base. The differing conductivity types of the emitter, base, and collector define a pair of p-n junctions, namely a collector-base junction and an emitter-base junction, across which the conductivity type changes. A voltage applied across the emitter-base junction controls the movement of charge carriers that produces charge flow between the collector and emitter.
Heterojunction bipolar transistors may be found, among other end uses, in high-frequency and high-power applications. In particular, heterojunction bipolar transistors may be used in radiofrequency integrated circuits, which are found in wireless communications systems, power amplifiers in cellular telephones, and other varieties of high-speed end uses. To take advantage of the positive characteristics of both transistor types, heterojunction bipolar transistors and CMOS field effect transistors may be combined in a single chip to form a BiCMOS integrated circuit.
Improved device structures, fabrication methods, and design structures are needed for enhancing the performance of heterojunction bipolar transistors.

Heterojunction bipolar transistors with an airgap between the extrinsic base and collector

International Business Machines Corporation


If a consumer instruction specifies a 64 bit source register comprised of results provided by two 32 bit producer instructions, the number of dependencies that must be tracked per source register can be decreased by transforming one or more of the 32 bit producer instructions so that rather than simply storing its result in a 32 bit destination register, the transformed instruction stores its result into a 64 bit logical register along with another 32 bit value held in another 32 bit register.

1. Field of the Invention
This invention relates generally to storing results of processor instructions into registers, and more particularly to storing instruction results in such a way that the number of dependencies per register is decreased.
2. Description of the Related Art
Computer programs are generally designed to be executed in a particular order. For example, a program that implements the Pythagorean theorem (A2+B2=C2) might instruct a computer to first determine the value of A2 and store the result in a first register, then to determine the value of B2 and store that result in a second register. Finally, the program would instruct the processor to add the contents of the first and second register to arrive at the value of C2. As is apparent from this example, the value of C2 cannot be determined until the values of both A2 and B2 are known.
Many modern processors, however, are capable of executing multiple instructions simultaneously (parallel processing), in a different order than specified by the computer program (out of order execution), or even of executing certain instructions based on a "guess" (predictive branching). Processors using some or all of these techniques may be able to execute a given set of instructions much quicker than processors executing instructions sequentially in the order specified by a program. In cases like the example above, however, even the most modern processors cannot add the values of A2 and B2 until those two values are known.
When a processor cannot perform a particular instruction, for example calculating the value of C2, until results of previous instructions, for example calculating A2 and B2, are known, the instruction that must wait is said to be dependent on the instructions that must be completed earlier. To deal with these dependencies, various hardware and software dependency tracking techniques have been developed.
Normally, results produced by instructions are temporarily stored in registers (called destination registers) before being sent for longer term storage in main memory. Likewise, values consumed by instructions are read from registers (called source registers). Note that the same register may be used as a destination register by one instruction, and as a source register by another instruction. Thus, in the example above, a first register may be used as a destination register by the instruction calculating the value of A2, and as one of two source registers by the instruction calculating the value of C2.
An additional layer of complexity is added when a processor implementation has to handle aliasing, which involves storing the results of a lesser width (e.g. 32 bit) instruction into a greater width (e.g. 64 bit) register. Aliasing can be particularly useful in some modern processors designed to provide backwards compatibility with older processors. For example, a backwards compatible processor designed to execute 64 bit (or even 128 bit) code, may still be capable of running 32 bit code written for older processors. Because 32 bit code usually produces 32 bit results even when being executed by a 64 bit processor, the 64 bit processor may employ aliasing techniques that allow it to store different 32 bit results onto different portions of a single 64 bit register.
Often, processors that employ out of order processing and/or aliasing techniques use a reorder buffer, or some similar method of storing interim values. Referring to FIG. 1, a prior art method of using a reorder buffer is discussed. Reorder buffer (ROB) 110 and architectural register file (ARF) 120 are both sets of registers. A software program only sees the registers in the ARF 120, so if an instruction specifies 64 bit register d0 or 32 bit registers f1 or f0, the software is only aware of physical registers 122, 123, or 124, respectively. The 64 bit X register 112, 64 bit Y register 116, and 32 bit registers 113, 114, 117, and 118 in ROB 110 are used by hardware to store interim values produced by instructions executed out of order, results of a predictive branch, partial results, and other "non-finalized" results that are not guaranteed correct.
Once results are finalized, the results are "committed to the architectural state" by moving them from ROB 110 to ARF 120. Assume, for example, that a first load instruction LDF0 specifies 32 bit destination register f0 as a destination register and a second load instruction LDF1 specifies 32 bit destination register f1. Assume further that the instructions are being executed out of order, i.e. LDF1 is executed before LDF0. The software expects the result of LDF0 to be stored in register 124 of ARF 120, and the result of LDF1 to be stored in register 123 of ARF 120. Since the instructions are being executed out of order, however, the hardware temporarily stores the result of LDF0 in 32 bit register 113, which occupies half of 64 bit X register 112, and the result of LDF1 in 32 bit register 118. Note that the temporary results of LDF0 and LDF1 are designated (f0) and (f1) respectively. Once the processor knows that the temporary values (f0) and (f1) are final, those values are moved to registers 124 and 123, respectively, and an instruction specifying 64 bit register d0 as a source is free to operate on register d0.
While the method just described ensures that the third instruction, which specifies 64 bit local register d0 as a source register, gets a finalized value, the method is less than perfect. For example, the third instruction must wait for both f1 and f0 to commit to the architectural state, which can reduce processor efficiency. As an alternative to waiting for both 32 bit values to commit to the architectural state, the processor must be designed to track up to two dependencies for a single source register d0, which is expensive in silicon area and power In effect, traditional processors require a tradeoff between a lower performance alternative (e.g. waiting until producers commit) and a higher performance, but higher cost alternative, (e.g. tracking multiple dependencies per register).

Storing results of producer instructions to facilitate consumer instruction dependency tracking


The apparatus and method according to the invention includes an objective (8) which is capable of operating basically in two different measuring modes. In a first interference mode, a measuring object (9) is interference—optically measured. In a second imaging operating mode on a detector array (12) designed like a camera, an optical image is generated, which is supplied to an image processing routine. The switching over between the two operating modes occurs by switching the illumination devices which are associated with different locations of the beam path of the apparatus—when viewed from the camera, one in front of a beam divider and the other behind the beam divider, which couples a reference light path to the beam path.

The invention concerns an apparatus and a method for an optical measurement of an object to be measured. The apparatus and the method are particularly suitable for measuring tasks in the microsystem technology.
For measuring areas of height structures also on stepped objects optically with highest precision, the vertically scanning white-light interferometry (WLI) is particularly suitable. Common interferometric arrangements for this purpose are the Michelson interferometer, the Linnik-interferometer and the Mirau interferometer. In the WLI, a white light source, typically a halogen lamp is used for illumination. During the measurement the optical travel distance difference between the measuring beam path and the reference beam path is continuously increased or reduced while at a distance of less than 100 nm (nanometers) interference images of the object are recorded generally by a pixel sensor with areal resolution (for example a CCD- or CMOS array). The optical travel distance change can be generated by a movement of the object being measured in the direction of the interferometer, a movement of the interferometer in the direction toward the object or away therefrom, a movement of the interference objective or a reference mirror. This procedure is called vertical scanning A. The intensity curve for each camera pixel, the so-called correlogram which depends on the optical travel length difference is then submitted to further signal evaluation.
In the WLI signal evaluation a distinction is made between a coherence peak evaluation which provides for a relatively coarse estimation of the height location of a measuring point with deviations of at times, more than 100 nm, and the phase evaluation, which provides for measurement errors in the nano or sub-nano range. The height measurement range can be several millimeters.
Lateral geometric features of objects to be measured can be determined via a digital evaluation of pixel images, for example, using an edge detection algorithm. In connection with microscopic objects, measuring microscopes are consequently equipped with suitable cameras in order to record such pixel images and subsequently evaluate them digitally. An advantage of this procedure resides in the high measuring speed which, with a corresponding synchronization between the image establishment and the excitation of the measuring object, permits also examinations of the dynamic behavior of the respective measuring objects to be performed. However, all microscopic procedures are, with regard to the achievable lateral resolution, subject to the limitations set by the diffraction-limited mapping. With the use of visible light, this results generally in lateral resolutions of about 0.5 μm (micrometer).
If the evaluation of lateral structures based on the digitized light-microscopic imaging is to be performed with one of the above-mentioned interferometer arrangements, the interference effects necessarily occurring in connection with the interference microscopy because of the additional image contrasts caused thereby are troublesome.
Therefore, WO 2005/108915 A1 proposed a measuring arrangement which can operate with the same objective in an interferometric as well as in an imaging operating mode. To this end, two light sources are provided which emit light of different spectral composition. In this reference light path a filter is arranged which permits only light of the one spectral composition to pass but not light of the other composition.
With this principle the use of different types of light is provided in the different modes of operation.
It is the object of the present invention to improve this situation.

Apparatus and method for a combined interferometric and image based geometric determination, particularly in the microsystem technology


Disclosed is a Ni—Cr-based brazing alloy including, on the basis of mass %: 15%<Cr<30%; 3%<P<12%; 0%≤Si<8%; 0.01%<C<0.06%; 0%≤Ti+Zr<0.1%; 0.01%<V<0.1%; 0%≤Al<0.01%; 0.005%<O<0.025%; 0.001%<N<0.050%; 0%≤Nb<0.1%; and the balance being Ni and incidental impurities. Inequality (1): 0.2≤0.24V %/C %≤1.0 is satisfied if the alloy contains no Nb, and Inequality (2): 0.2≤(0.24V %+0.13Nb %)/C %≤1.0 is satisfied if the alloy contains Nb. Also disclosed is an inexpensive Ni—Cr-based brazing alloy containing a trace amount of V for use in the production of stainless steel heat exchangers and other steel articles. The alloy has a low liquidus temperature and high corrosion resistance, and achieves high brazing strength.

Stainless steels have been conventionally brazed with Ni-based brazing alloys, especially JIS BNi-2 alloy (Ni—Cr—Fe—B—Si alloy), BNi-5 alloy (Ni—Cr—Si alloy), and BNi-7 alloy (Ni—Cr—P alloy), in many cases due to their high corrosion resistance and oxidation resistance. These three Ni-based brazing alloys each have different advantages and disadvantages, and are selected depending on applications. For example, the BNi-2 alloy has a relatively low liquidus temperature of about 1000° C. but its corrosion resistance is not necessarily sufficient. The BNi-5 alloy has high corrosion resistance, but has a liquidus temperature of about 1140° C., that is, requires a high brazing temperature. The BNi-7 alloy has a very low liquidus temperature of about 900° C. and relatively high corrosion resistance, but requires expensive raw materials. Thus, no Ni-based brazing alloy establishes compatibility between low liquidus temperature, high corrosion resistance, and low material costs, and there have been strong demands for a novel brazing alloy.
Proposed solutions to these issues are Ni-based brazing alloys with a low liquidus temperature and high brazing strength. Such Ni-based brazing alloys contain Cr for high corrosion resistance and P for a low liquidus temperature. For example, JP2015-51459A (Patent Document 1) discloses an inexpensive Cu-containing Ni—Cr—Fe-based brazing alloy that has a low melting temperature and high corrosion resistance and strength, for use in the production of stainless steel heat exchangers and other steel articles. WO 2009/128174 (Patent Document 2) discloses an inexpensive thermal- and corrosion-resistant Fe-based brazing alloy that has high resistance to corrosion in sulfuric acid and nitric acid and high brazing strength and are suitable for brazing of substrate parts of various stainless steels, especially ferrite stainless steels, at practical temperatures (1120° C. or lower) with good wettability on the substrate parts without coarsening the structure of the substrate.
JP2013-208650A (Patent Document 3) discloses a highly alloyed iron-based brazing filler material, a brazing method, and a product brazed with the highly alloyed iron-based brazing filler material. JP2012-183574A (Patent Document 4) discloses a nickel-based brazing alloy suitable for braze-assembling automobile exhaust system parts made of corrosion-resistant steels (for example, exhaust gas heat exchangers of exhaust gas recirculation (EGR) systems), which requires high corrosion resistance. WO 2013/077113 (Patent Document 5) discloses a brazing alloy for bonding members made of various stainless steels of general heat exchangers and other heat exchangers in EGR coolers and exhaust heat recovery systems, for example.

Ni—Cr based alloy brazing material containing trace amount of V