The timing recovery apparatus and the diversity communication apparatus using the same realizes a high-speed timing phase pull-in characteristic and a low-jitter characteristic at the time of power-on sequence, recovery from line disconnection and the like. The apparatuses also prevent the bit error rate characteristic and synchronization characteristic from being deteriorated by signal delay time difference. A received PSK signal is X-times oversampled. From received phase data sequences Y.sub.i obtained by the X-times oversampling, a data sequence including j symbol frequency components not affected by carrier frequency deviation is extracted by signal processing including simple adding and subtracting operations. The data sequence including j symbol frequency components is synthesized to provide two data sequences including symbol frequency components having a good S/N ratio with .pi./4 phase difference in radian and not affected by carrier frequency deviation. Further, a data sequence including two symbol frequency components is used for timing regeneration.

1. Field of the Invention
The present invention relates to a timing recovery apparatus and a diversity communication apparatus using the timing recovery apparatus and, more particularly, the present invention is applicable to a demodulator for use in a digital wireless communication apparatus based on PSK (Phase Shift Keying).
2. Description of Prior Art
A timing recovery apparatus for a demodulator of a digital wireless communication apparatus based on PSK is disclosed on JP-A 6/252965. The disclosed timing recovery apparatus uses a phase detecting section for initial pull-in that detects a clock phase by using a preamble pattern and a phase detecting section for steady state based on zero cross detecting that detects lead or lag of a clock phase. Various schemes for conventional diversity communication apparatuses are described in "Basics of Mobile Communication," Chapter 7, edited by Institute of Electronics, Information and Communication Engineers of Japan, published by Corona Publishing, for example.
FIG. 50 shows a conventional diversity receiving apparatus including the above-mentioned timing recovery apparatus. For simplicity of description, let the number of branches K of the diversity of this diversity receiving apparatus be 2. In the figure, reference numerals 1A and 1B indicate antennas, 2A and 2B indicate detecting sections, 3A and 3B indicate sampling sections, 4 indicates a diversity section, 5 indicates a timing recovery section, 6 indicates a Nyquist point extracting section, 7a indicates a Nyquist point data output terminal, 7b indicates a burst gate input terminal, 7c indicates a frame synchronization signal input terminal. In the timing recovery section 5, reference numeral 10 indicates phase detecting section for initial pull-in (hereinafter, it is called as an initial pull-in phase detecting section), 11 indicates a phase detecting section for steady state (hereinafter, it is called as a steady state phase detecting section), 12 indicates a filtering section for initial pull-in (hereinafter, it is called as an initial pull-in filtering section), 13 indicates a filtering section for steady state (hereinafter, it is called as a steady state filtering section), 14 indicates a phase control selecting section, and 15 indicates a phase controlling section.
FIG. 51 shows a constitution of the initial pull-in phase detecting section 10, in which reference numerals 16 and 17 indicate registers, 18 indicates a subtractor, 10a indicates a received phase data input terminal, 10b indicates a regenerated double frequency clock input terminal, and 10c indicates a differential data output terminal. FIG. 52 shows a constitution of the initial pull-in filtering section 12, in which reference numeral 20 indicates a serial-parallel converter, 21 indicates an integrator, 22 indicates integration controlling section, 23 indicates a ROM, 24 indicates a register, 12a indicates a differential data input terminal, 12b indicates a regenerated 1/2 frequency clock input terminal, 12c indicates a regenerated clock input terminal, 12d indicates a burst gate input terminal, 12e indicates a timing phase difference data output terminal, and 12f indicates a timing phase difference data calculation complete signal output terminal. In the integrator 21, reference numerals 26A and 26B indicates multiplier, 27A and 27B indicate adders, 28A and 28B indicate registers, 29A and 29B indicate dividers. In the integration controlling section 22, reference numeral 30 indicates an AND gate, 31 indicates an inverter, 32 indicates an up counter, and 33 indicates a comparator.
FIG. 53 shows a constitution of the steady state phase detecting section 11, in which reference numeral 11a indicates a received phase data input terminal, 34 indicates a polar-coordinate converter, 35A and 35B indicate zero-cross detectors, 36 indicates a zero-cross signal synthesizing section, 11b indicates a LEAD signal output terminal, and 11c indicates CROSS signal output terminal. FIG. 54 shows a constitution of the zero-cross detectors 35A and 35B, in which reference numeral 35a indicates a data input terminal, 35b indicates a regenerated clock input terminal, 37A, 37B, 37C and 37D indicate registers, 38 indicates an inverter, 39A and 39B indicate exclusive OR gates, 35c indicates an LEAD signal output terminal, and 35d indicates a QCROSS signal output terminal.
FIG. 55 shows a constitution of the steady state filtering section 13, in which a reference numeral 13a indicates frame synchronization signal input terminal, 13b indicates a phase control complete signal input terminal, 13c indicates a LEAD signal input terminal, 13d indicates a CROSS signal input terminal, 13e indicates a burst gate input terminal, 13f indicates a regenerated clock input terminal, 40 indicates a selector, 41 indicates a 1-bit shifter, 42 indicates an UP/DOWN counter, 43A and 43B indicate comparators, 44 indicates an OR gate, 13g indicates an UP signal output terminal, and 13h indicates a DOWN signal output terminal.
FIG. 56 shows a constitution of the phase control selecting section 14, in which reference numeral 14a indicates a timing phase difference data calculation complete signal input terminal, 14b indicates an UP signal input terminal, 14c indicates a DOWN signal input terminal, 14d indicates a timing phase difference data input terminal, 45 indicates an UP/DOWN data generating section, 46 indicates a gate circuit, and 14e indicates a phase control data output terminal. FIG. 57 indicates a constitution of the phase controlling section 15, in which reference numeral 15a indicates a phase control data input terminal, 15b indicates a regenerated 2.sup.m times (for example 32 times) frequency clock input terminal, 47A and 47B indicate comparators, 48 indicates an AND gate, 49 indicates an m-bit up counter, 50 indicates a 1/2 divider, 51A and 51B indicate inverters, 15c indicates a regenerated 1/2-times frequency clock output terminal, 15d indicates a regenerated clock output terminal, 15e indicates a regenerated double frequency clock output terminal, 15f indicates a regenerated 16-times frequency clock output terminal, and 15g indicates a phase control complete signal output terminal.
The operations of the above-mentioned conventional diversity receiving apparatus will be described. First, the operations of the diversity receiving apparatus in its entirety will be described. In this example, for reduction in size and power consumption, the demodulator of the receiving apparatus for digital mobile communication operates by using only phase information, discarding amplitude information. That is, the demodulator operates by using only a baseband receive phase signal obtained by detecting the carrier signal that passed the limiter. Also, in this example, delay detecting based on .pi./4 shift QPSK (Quadrature PSK) is used for demodulation. In the conventional diversity receiving apparatus, two antennas 1A and 1B receive a PSK signal. Two detecting sections 2A and 2B detect the received signal to output an analog baseband receive phase signal and a receive signal power. The detecting sections 2A and 2B are each composed of a limiter, a bandpass filtering section, mixer, and other analog devices.
The sampling sections 3A and 3B each oversample each analog baseband receive phase signal at a double frequency double of a symbol frequency to output quantized baseband receive phase data. Here, it is assumed that the phase resolution of the baseband receive phase data be 5 bits. The diversity section 4 delay-detects the baseband phase signals outputted from the sampling sections 3A and 3B. An automatic frequency controlling section in the diversity section 4 removes a carrier frequency deviation from each baseband phase signal. Then, the diversity section 4 performs signal synthesis such as selective synthesis, equivalent gain synthesis or maximum ratio synthesis described in the above-mentioned document "Basics of Mobile Communication" by using the received signal power and the two pieces of delay-detected baseband receive phase data outputted from the detecting sections 2A and 2B to output the synthesized baseband receive phase data to the timing recovery section 5 and the Nyquist point extracting section 6.
The timing recovery section 5 outputs a regenerated double frequency clock to be used by the sampling sections 3A and 3B. The timing recovery section 5 controls the clock phase such that the double regenerated clock samples Nyquist points of the baseband receive phase data every two samples. Consequently, the Nyquist point of the baseband receive phase data after delay detection also appears, every two samples, in the baseband receive phase data after synthesis outputted from the diversity section 4. The Nyquist point extracting section 6 extracts the Nyquist point coming from the baseband receive phase data from the synthesized baseband receive phase data outputted from the diversity section 4. Further, the extracting section polar-coordinate converts the extracted phase data to output in-phase Nyquist point data and orthogonal Nyquist point data.
The following describes the above-mentioned operations with reference to the timing chart of FIG. 58. The curves of (A) and (C) of FIG. 58 indicate the baseband receive phase data detected by the detecting sections 2A and 2B. The baseband receive phase data are the data obtained by performing .pi./4 shift QPSK on the data pattern in which "00" and "10" repeat by the mapping shown in FIG. 59. For simplicity of description, no carrier frequency deviation is given to the baseband receive phase data. When the data pattern in which "00" and "01" repeat is modulated by .pi./4 shift QPSK, the phase fluctuates from 0 to .pi./4 or from .pi./4 to 0 at a symbol interval. However, the baseband receive phase data indicating this phase jitter is distorted by the influence of noise or phasing as indicated by the curves of (A) and (C) of FIG. 58. A tiny circle in the figure shows a Nyquist point, of which phase originally indicates 0 and .pi./4. However, by the influence of noise and phasing, the phase at Nyquist point takes a different value at a position at which the received signal power outputted from the detecting sections 2A and 2B drops. The received signal power outputted from the detecting sections 2A and 2B are shown in (B) and (D) of FIG. 58.
The sampling sections 3A and 3B sample the baseband receive phase data (A) and (C) respectively by the regenerated double frequency clock outputted from the timing recovery section 5 shown in (F) of FIG. 58. The sampled data are indicated by vertical lines in (A) and (C) of FIG. 58. The diversity section 4 delay-detects the sampled baseband receive phase data shown in (A) and (C) of FIG. 58. If not affected by noise or phasing, the delay-detected Nyquist point phase data show .pi./4 and -.pi./4 alternately. Then, the diversity section 4 performs signal synthesis by selective synthesis, equivalent gain synthesis or maximum ratio synthesis by using two pieces of delay-detected baseband receive phase data and the received signal power (B) and (D), outputting the delay-detected baseband receive phase data after synthesis indicated by vertical lines in (E) of FIG. 58.
The timing recovery section 5 uses the synthesized delay-detected baseband receive phase data (E) to control the clock phases of the regenerated double frequency clock (F) of FIG. 28 and the regenerated clock (G) such that the rise position of each of these clocks comes to a Nyquist point. In the example of FIG. 58, the phase difference between the rise of the Nyquist point and the regenerated clock is .pi./2 initially, but as time goes by, this phase difference converges to zero gradually. The Nyquist point extracting section 6 extracts the delay-detected base band receive phase data (E) at the rise of the regenerated clock (G) as Nyquist point data to output the same as in-phase and orthogonal Nyquist point data shown in (H) and (I) of FIG. 58. Consequently, in the first half of the timing chart, the Nyquist point extracting section 6 outputs the data that are deviated from the Nyquist point by .pi./2 as the Nyquist point data; in the last half of the timing chart, the extracting section 6 can output the inherent Nyquist point data by the clock phase control performed by the timing recovery section 5.
The operation of the timing recovery section 5 will be described. The present diversity apparatus receives burst data as shown in FIG. 60. The timing recovery section 5 uses a data pattern that repeats "01" and "10" called a preamble pattern in the head of the burst data to calculate a timing phase difference and, at the same time, performs the clock phase initial pull-in controlling. The calculation of the timing phase difference is performed by the initial pull-in phase detecting section 10 and the initial pull-in filtering section 12. After the clock phase initial pull-in controlling, the timing recovery section 5 performs a timing phase following operation by using a random pattern (including a unique word pattern for frame synchronization) shown in FIG. 60. The timing phase following operation is performed by the steady state phase detecting section 11 and the steady state filtering section 13.
First, the clock phase initial pull-in control operation will be described. The initial pull-in phase detecting section 10 uses the synthesized delay-detected baseband receive phase data outputted from the diversity section 4 to output differential data that provides a phase detection signal. The initial pull-in filtering section 12 integrates the differential data. The initial pull-in filtering section 12 outputs the timing phase difference data indicating the phase difference between Nyquist point and regenerated clock and the timing phase difference data calculation complete signal indicating the completion of the timing phase difference data calculation. The initial pull-in phase detecting section 10 and the initial pull-in filtering section 12 calculate the timing phase difference by using the preamble pattern. It should be noted that the timing phase difference cannot be calculated from a random pattern in which data changes irregularly.
The operations of the initial pull-in phase detecting section 10 and the initial pull-in filtering section 12 will be described with reference to the timing chart of FIG. 61. In the baseband receive phase data having the preamble pattern entered from the input terminal 10a of the initial pull-in phase detecting section 10, the Nyquist points indicated by a tiny circle take values of 3.pi./4 and -.pi./4 alternately unless unless affected by noise or the like as shown in (A) of FIG. 61. The registers 16 and 17 that operate on the regenerated double frequency clock entered from the input terminal 10b perform re-timing on the baseband receive phase data to delay the same by one symbol as shown in (B) of FIG. 61. The subtractor 18 subtracts the baseband receive phase data delayed by one symbol from the baseband receive phase data to generate differential data as shown in (C) of FIG. 61 and output the same from the output terminal 10c. Therefore, the differential data at the Nyquist points indicate the .pi. and -.pi. values alternately. It is assumed here that the phase difference between Nyquist point and regenerated clock be 7.pi./4 as shown in (E) of FIG. 61. In this case, the vertical line in (C) of FIG. 61 provides the data sampled by the regenerated double frequency clock.
The differential data entered from the input terminal 12a are serial-parallel converted by the serial-parallel converter 20 into data of two sequences in which even-number data and odd-number data are separated from each other. The multipliers 26A and 26B the data of two sequences by 1 when the regenerated 1/2 frequency clock coming from the input terminal 12b is logic "1" or -1 when the same is logic "0" shown in (F) of FIG. 61. Then, the data of two sequences are converted to data indicated by vertical dotted lines shown in (C) of FIG. 61. As shown in (C) of FIG. 61, let the even-number data sequence after multiplication be G.sub.i (i=1, 2, 3, . . . ) and the odd-number data sequence after multiplication be H.sub.i (i=1, 2, 3, . . . ) as shown in (C) of FIG. 61. The two data sequence G.sub.i and H.sub.i are accumulated by J times (J.gtoreq.2) by two accumulators composed of adders 27A and 27B and registers 28A and 28B respectively.
The clock to operate the two accumulators by J times is realized by performing a logical product operation by the AND gate 30 between the regenerated clock and the gate signal that indicates logic "1" during J symbol period at input of the preamble pattern. The comparator 33 indicates logic "0" when the output of the up counter 32 is less than J. The up counter 32 starts counting at the rise of the burst gate signal entered from the input terminal 12d in the timing shown in FIG. 60. The gate signal is generated by inverting the output of the comparator 33 that compares the output of the up counter 32 with J.
The two data sequence G.sub.i and H.sub.i accumulated by J times are divided by J in the dividers 29A and 29B respectively. Therefore, mean value GA of G.sub.1 through G.sub.J and mean value HA of H.sub.1 through H.sub.J are obtained. The GA and HA are entered in ROM 23, from which the timing phase difference is outputted based on the input-output relationship shown in FIG. 62. As described above, the output of the comparator 33 rises from logic "0" to "1" when the output of the up counter 32 exceeds J. The timing phase difference can be obtained at this point of time, the output of the comparator 33 is outputted from the output terminal 12f as the timing phase difference data calculation complete signal. In addition, the output of the ROM 23 is latched in the register 24 by the output of the comparator 33. The latched data are outputted from the output terminal 12e as the timing phase difference data.
The following describes the timing phase following operation to be performed by the steady state phase detecting section 11 and the steady state filtering section 13 after the clock phase initial pull-in control. Following the initial pull-in control, the steady state phase detecting section 11 and the steady state filtering section 13 perform phase control. The steady state phase detecting section 11 uses the synthesized delay-detected baseband receive phase data outputted from the diversity section 4 and generates a LEAD signal that indicates whether the current timing phase is advancing or lagging and a CROSS signal that indicates that the LEAD signal is valid. In what follows, the operation of the steady state phase detecting section 11 will be described. The delay-detected baseband receive phase data coming from the input terminal 11a is converted by the polar-coordinate converter into IDATA that indicates an in-phase component and QDATA that indicates an orthogonal component. The IDATA and the QDATA are entered in the zero-cross detectors 35A and 35B respectively.
The registers 37A and 37B in the zero-cross detector 35A of FIG. 54 sample the IDATA entered from the input terminal 35a at the rising and falling of the regenerated clock. Here, let sample data of the IDATA at the falling edge of the regenerated clock obtained by the inverter 38 and the register 37A be Z.sub.n (n=1, 2, 3, . . . ), sample data of the IDATA at the rising edge obtained by the register 37B be N.sub.n (n=1, 2, 3, . . . ), and sample data of the IDATA at the rising edge delayed by one symbol obtained by the register 37C be N.sub.(n-1) (n=1, 2, 3, . . . ), then the zero cross of the data occurs when the following relation is established as shown in FIGS. 63(A) and 63(B): EQU N.sub.n .times.N.sub.(n-1) <0 (1)
In this case, if EQU N.sub.n .times.Z.sub.n >0 (2)
indicating that the clock phase is advancing before the Nyquist point as shown in FIG. 63(A). EQU If N.sub.n .times.Z.sub.n <0 (3)
indicating that the clock phase is lagging behind the Nyquist point as shown in FIG. 63(B).
In the above-mentioned example, DPLL (Digital Phase Locked Loop) is used for clock phase control. Sample data is used as one-bit decision data. The exclusive OR gate performs an exclusive OR operation between the data N.sub.n and the data N.sub.(n-1) which is one symbol before the data N.sub.n to output a signal that indicates the detection of data zero cross. When the zero cross is detected, an ICROSS signal of logic "1" is outputted from the output terminal 35d. The ILEAD signal that indicates the lead or lag of the clock phase is obtained by performing an exclusive OR operation between the data Z.sub.n (n=1, 2, 3, . . . ) re-timed at the rising of the regenerated clock by the register 37C and N.sub.n (n=1, 2, 3, . . . ) outputted from the register 37B. Namely, the output of the exclusive OR gate 39A indicates the ILEAD signal. If the clock phase is advancing, the ILEAD signal of logic "0" is outputted from the output terminal 35c; if the clock phase is lagging, the ILEAD signal of logic "1" is outputted from the output terminal 35c.
The operation of the zero-cross detector 35B with QDATA inputted is generally the same as that of the zero-cross detector 35A. The zero-cross detector 35B outputs the QCROSS signal that indicates whether QDATA zero cross occurred or not and the QLEAD signal that indicates whether the clock phase is advancing or lagging. The zero-cross signal synthesizing section 36 generates the LEAD signal and the CROSS signal from the ILEAD, ICROSS, QLEAD, and QCROSS signals to output the LEAD signal from the output terminal 11b and the CROSS signal from the output terminal 11c. The LEAD signal and the CROSS signal are outputted according to the condition of FIG. 64. The LEAD signal is obtained by a logical OR operation between the ILEAD signal and the QLEAD signal. The CROSS signal is also basically obtained by a logical OR operation between the ICROSS signal and the QCROSS signal; however, if the ICROSS signal and the QCROSS signal are both logic "1's" and the ILEAD signal and the QLEAD signal have different values, then the CROSS signal is set to logic "0".
The steady state filtering section 13 of FIG. 55 averages the LEAD signal coming from the input terminal 13c if the CROSS signal coming from the input terminal 13d is logic "1". Then, if the filtering section 13 determines that the timing phase is lagging, the filtering section 13 outputs an UP signal that leads the timing phase from the output terminal 13g; if the filtering section 13 determines that the timing phase is advancing, the filtering section 13 outputs a DOWN signal that delays the timing phase from the output terminal 13h. The averaging is implemented by the UP/DOWN counter 42. The UP/DOWN counter 42 operates in the period of the regenerated clock entered from the input terminal 13f. The UP/DOWN counter 42 is enabled when the burst gate signal of FIG. 60 is entered as logic "1" from the input terminal 13e and the CROSS signal that indicates the detection of zero cross is logic "1".
FIG. 65 shows the timing chart of the operation of the steady state filtering section 13. The UP/DOWN counter is initially set to a value Nx. Then, the UP/DOWN counter down-counts if the LEAD signal indicates a phase lead or up-counts if the LEAD signal indicates a phase lag. The output of the UP/DOWN counter 42 is compared with 2Nx in the comparator 43A and with 0 in the comparator 43B. Detecting a match, these comparators each output logic "1" each. Value 2Nx is generated by one-bit shifting Nx by the bit shifter 41. When the counter value reaches 2Nx as shown in (a) of FIG. 65, the UP signal of logic "1" is outputted from the comparator 43A to the output terminal 13g. When the count value reaches 0 as shown in (b) of FIG. 65, the DOWN signal of logic "1" is outputted from the comparator 43B to the output terminal 13h.
The signal of logic "1" coming from the comparator 43A or 43B is also a load signal to the UP/DOWN counter 42. Therefore, when the signal of logic "1" is outputted from the comparator 43A or 43B, Nx is set again to the UP/DOWN counter. The first loading of Nx is performed by the phase control complete signal entered from the phase controlling section 15 to the input terminal 13b, this signal indicating that the timing phase control has been completed. The filtering section for steady state 13 uses the frame synchronization signal entered from the input terminal 13a to determine whether the current point is in phase pull-in state or steady state. In the phase pull-in state, high-speed pull-in is required, so that, in the phase pull-in state, the selecting section (SEL) 40 sets Nx to a relatively small value N.sub.1 and, in the steady state, a low jitter is required, so that the selecting section sets Nx to a relatively large value N.sub.2.
The phase control selecting section 14 shown in FIG. 56 outputs the phase control data that indicates a controlled quantity from the output terminal 14e. In this example, the resolution of the phase control is 1/32 symbol. Therefore, the timing phase data of 0 to 2.pi. and the phase control data of 0 to 2.pi. outputted from the initial pull-in phase filtering section 12 are both represented in 0 to 31. The phase control by the UP signal and the DOWN signal is performed at every 1/32 symbol. The UP signal entered from the input terminal 14b and the DOWN signal entered from the input terminal 14c are entered in the UP/DOWN data generating section 45.
The UP/DOWN data generating section 45 outputs "15" when the UP signal is logic "1", outputs "17" when the DOWN signal is logic "1", and outputs "16" otherwise. The gate circuit 46 holds the phase control data to "16" until the calculation of the timing phase data by the initial phase pull-in operation is completed. When the timing phase data is entered from the input terminal 14d upon completion of the calculation of the timing phase data, the gate circuit 46 converts the timing phase data "0 to 15, 16 to 31" to "16 to 31, 0 to 15" to output the result as the phase control data. After completion of the timing phase data calculation, the gate circuit 46 outputs the data outputted from the UP/DOWN data generating section 45 as the phase control data. The completion of the timing phase data calculation can be known by the timing phase data calculation complete signal entered from the input terminal 14a.
In the phase controlling section 15 of FIG. 57, the UP/DOWN counter 49 up-counts by a fixed clock that is 32 times the symbol frequency entered from the input terminal 15b . The UP counter 49 outputs a count value in 5 bits, the most significant bit being outputted from the output terminal 15d as the regenerated clock. The counter outputs of the remaining 4 bits except for the most significant bit are inverted by the inverter 51A through 51B to be a regenerated double frequency clock through regenerated 16-times frequency clock. These clocks are outputted from the output terminals 15e through 15f respectively. The 1/2 divider divides the regenerated clock by 2 to generate a regenerated 1/2 frequency clock, which is outputted from the output terminal 15c.
The 5-bit output value of the UP counter 49 is compared with "16" in the comparator 47A. The comparator 47A outputs logic "1" if the counter output value matches "16". The output of the comparator 47A is used as a load signal to the UP counter 49. When the load signal is logic "1", the UP counter 49 loads the phase control data entered from the input terminal 15a . If the phase control data takes the value of "16" that indicates that the phase control data is in the uncontrolled state, "16" is loaded when the count value of the UP counter 49 is "16", so that the count value does not become discontinuous. Consequently, the phase change of the regenerated clock does not occur.
If the clock phase is advancing, the phase control data becomes "17" by the DOWN signal. Therefore, as shown in FIG. 66(A), when the count value of the UP counter 49 reaches "16", "17" is loaded in the UP counter 49. As a result, the clock phase is delayed. If the clock phase is lagging, the phase control data becomes "17" by the UP signal. Therefore, as shown in FIG. 66(B), the count value of the UP counter 49 reaches "16" "15" is loaded in the UP counter. As a result, the clock phase is led.
At the time of initial phase pull-in, the phase control data take a value 0 to 31, so that, when the count value of the UP counter reaches "16", a value 0 to 31 is loaded. As a result, clock phase pull-in is realized. FIG. 67 shows an example in which clock phase pull-in is performed when the initial phase difference is 3.pi./2. By the initial pull-in detecting section 10 and the initial pull-in filtering section 12, the phase difference 3.beta./2 is outputted as timing phase difference data "24". The timing phase difference data "24" is converted to phase control data "8". Then, when the count value of the UP counter 49 reaches "16", "8" is loaded.
When the phase control has been completed, the phase control complete signal for instructing the setting of the value of the UP/DOWN counter 42 to Nx is outputted from the output terminal 15g. The comparator 47B compares the phase control data with "16". If a match found, the comparator 47B outputs logic "1". The AND gate 48 performs a logical AND operation between the output of the comparator 47B and the load signal. The output of the AND gate becomes the phase control complete signal. Thus, the timing phase synchronization by the timing recovery section 5 is performed.
The conventional timing recovery section 5 calculates the timing phase difference by using 10 to 20 symbols of the preamble data located in the head of burst data to perform initial phase control. The time required for the initial phase control is a time from starting the signal entry to the calculation of the timing phase difference. After the initial phase control, the timing recovery section 5 performs a phase following operation by using a random pattern. Therefore, the initial phase control cannot be performed if the position of the preamble pattern is not known when a portable radio terminal is powered on in which the timing when burst data come has not yet been established, or at the time of recovery from such line disconnection as blockage, for example. In this case, the phase detecting section for steady state 11 and the filtering section for steady state 13 which use a random pattern perform timing phase pull-in. However, the phase pull-in using the random pattern performed by the steady state phase detecting section 11 and the steady state filtering section 13 is performed based on the lead or lag of the timing phase. Consequently, even if a noiseless transmission path is assumed and Nx in the steady state filtering section 13 is set to "2", it takes as long a time as equivalent to about 100 symbols until completion of the timing phase pull-in.
In the conventional diversity receiving apparatus, the outputs of the detecting sections 2A and 2B are sampled by the sampling sections 3A and 3B, the results being synthesized by the diversity section 4. Because the detecting sections 2A and 2B are implemented by analog devices, a difference occurs between the signal delay time in the detecting section 2A and that in the detecting section 2B. Depending on analog devices used, a delay time difference of about .pi./2 in terms of phase may occur. If there is a delay time difference between the two detecting sections 2A and 2B, selective synthesis, equivalent gain synthesis or maximum ratio synthesis is performed in the diversity section 4 with the Nyquist point positions of the two signals offset from each other. If equivalent gain synthesis or maximum ratio synthesis is performed on the two signals in a phase relationship in which the Nyquist point positions are largely offset, the synthesized signals are distorted, deteriorating bit error rate characteristic and synchronization characteristic. As for selective synthesis performed in the similar condition, the Nyquist point positions are offset at signal switching, thereby temporarily causing a timing phase difference, resulting in deteriorated bit error rate characteristic and synchronization characteristic.

Timing recovery apparatus and a diversity communication apparatus using the same


One example antenna apparatus includes S groups of antenna bays, S groups of phase-shift feeding networks, and S beamforming networks. An ith group of antenna bays include Ni bays, an ith group of phase-shift feeding networks include Ni phase-shift feeding networks, and the Ni bays are connected to the Ni phase-shift feeding networks. In a first state, an ith beamforming network is configured to form ni beams corresponding to the Ni bays, where Ni first ports corresponding to the beamforming network are connected to the Ni phase-shift feeding networks, ni second ports corresponding to the beamforming network are connected to ni antenna ports, and ni is less than Ni. In a second state, an ith beamforming network is configured to form Ni beams corresponding to the Ni bays, where Ni first ports corresponding to the beamforming network are connected to the Ni phase-shift feeding networks, and Ni second ports corresponding to the beamforming network are connected to Ni antenna ports.

A smart antenna is also referred to as an adaptive array antenna, including three parts: an antenna, array, a beamforming network, and a beamforming algorithm. The smart antenna adjusts a weighted amplitude and phase of each array element signal by using an algorithm that meets a criterion, to adjust a shape of a directivity pattern of the antenna array to strengthen a required signal and suppress an interference signal. A smart antenna technology is applicable to a CDMA system that uses time division duplex (TDD), and can suppress multi-user interference and increase a system capacity to a relatively large extent.
In the prior art, in a scenario of capacity expansion for a TDD smart antenna, a three-dimensional multi-beam antenna technology or a massive MIMO (MM) technology is usually used. In the three-dimensional multi-beam antenna technology, an antenna directivity pattern of a three-sector coverage network of a wireless cellular system is divided into a plurality of parts, including several parts in a horizontal dimension and several parts in a vertical dimension. The MM is an advanced form developed from a multi-antenna technology, and is a key technology of a 4.5G network. A quantity of radio frequency channels and a quantity of antennas are significantly increased at an MM site, and the antenna and a radio frequency unit are integrated into an active antenna unit (AAU). Compared with the traditional multi-antenna technology, the MM can significantly improve performance of a single-user link and a multi-user space division multiplexing capability by using a massive antenna array to jointly receive, demodulate, or send a signal, thereby significantly improving quality and a transmission rate of a system link. In addition, in the MM system, a degree of freedom in the vertical dimension is increased, and shapes of beams in the horizontal dimension and in the vertical dimension can be flexibly adjusted. Therefore, a three-dimensional coverage capability of a base station is significantly improved.
The two technologies have respective advantages and disadvantages in terms of costs, performance, and technology maturity, and are used in different scenarios. For example, the three-dimensional multi-beam technology is applicable to a small-packet service scenario in which users are evenly distributed, and the MM may be applicable to a large-packet service scenario. However, the MM has a large quantity of channels and high costs, and has a low performance gain in the small-packet service. How to implement smooth evolution while both features are supported has become a concern of operators.

Antenna apparatus and beam state switching method


A method is used in recovering from metadata inconsistencies in storage systems. A metadata inconsistency is detected in a portion of a file system. The file system is managed by upper-layer component. The portion of the file system is recovered. Lower-layer component recovers the portion of the file system. The portion of the file system is validated. The upper-layer component validates the portion of the file system.

Technical Field
This application relates to recovering from metadata inconsistencies in storage systems.
Description of Related Art
Computer systems may include different resources used by one or more host processors. Resources and host processors in a computer system may be interconnected by one or more communication connections. These resources may include, for example, data storage devices such as those included in the data storage systems manufactured by EMC Corporation. These data storage systems may be coupled to one or more servers or host processors and provide storage services to each host processor. Multiple data storage systems from one or more different vendors may be connected and may provide common data storage for one or more host processors in a computer system.
A host processor may perform a variety of data processing tasks and operations using the data storage system. For example, a host processor may perform basic system I/O operations in connection with data requests, such as data read and write operations.
Host processor systems may store and retrieve data using a storage device containing a plurality of host interface units, disk drives, and disk interface units. The host systems access the storage device through a plurality of channels provided therewith. Host systems provide data and access control information through the channels to the storage device and the storage device provides data to the host systems also through the channels. The host systems do not address the disk drives of the storage device directly, but rather, access what appears to the host systems as a plurality of logical disk units. The logical disk units may or may not correspond to the actual disk drives. Allowing multiple host systems to access the single storage device unit allows the host systems to share data in the device. In order to facilitate sharing of the data on the device, additional software on the data storage systems may also be used.
Such a data storage system typically includes processing circuitry and a set of disk drives (disk drives are also referred to herein as simply "disks" or "drives"). In general, the processing circuitry performs load and store operations on the set of disk drives on behalf of the host devices. In certain data storage systems, the disk drives of the data storage system are distributed among one or more separate disk drive enclosures (disk drive enclosures are also referred to herein as "disk arrays" or "storage arrays") and processing circuitry serves as a front-end to the disk drive enclosures. The processing circuitry presents the disk drive enclosures to the host device as a single, logical storage location and allows the host device to access the disk drives such that the individual disk drives and disk drive enclosures are transparent to the host device.
Disk arrays are typically used to provide storage space for one or more computer file systems, databases, applications, and the like. For this and other reasons, it is common for disk arrays to be structured into logical partitions of storage space, called logical units (also referred to herein as LUs or LUNs). For example, at LUN creation time, storage system may allocate storage space of various storage devices in a disk array to be presented as a logical volume for use by an external host device. This allows a disk array to appear as a collection of separate file systems, network drives, and/or volumes.
Disk arrays may also include groups of physical disks that are logically bound together to represent contiguous data storage space for applications. For example, disk arrays may be divided into redundant array of inexpensive disks (RAID) groups, which are disk arrays created by logically binding individual physical disks together to form the RAID groups. RAID groups represent a logically contiguous address space distributed across a set of physical disks. Each physical disk is subdivided into pieces used to spread the address space of the RAID group across the group (along with parity information if applicable to the RAID level). The physically contiguous pieces of the physical disks that are joined together to create the logically contiguous address space of the RAID group are called stripes. Stripes may form blocks and blocks may be allocated to create logical representations of storage space for use by applications within a data storage system.
As described above, applications access and store data incrementally by use of logical storage array partitions, known as logical units (LUNs). LUNs are made up of collections of storage blocks of a RAID array and are exported from the RAID array for use at the application level.
Existing data storage systems may utilize different techniques in connection with managing data availability in data storage systems, for example, in the event of a data storage device failure. There are a number of different RAID (Redundant Array of Independent or Inexpensive Disks) levels and techniques that may be used in connection with providing a combination of fault tolerance and/or improved performance for data storage devices. Different RAID levels (e.g., RAID-1, RAID-5, RAID-6, and the like) may provide varying degrees of fault tolerance. Further, RAID parity schemes may be utilized to provide error detection during the transfer and retrieval of data across a storage system.
Large storage arrays today manage many disks that are not identical. Storage arrays use different types of disks, i.e., disks with different RAID (Redundant Array of Independent or Inexpensive Disks) levels, performance and cost characteristics.
Generally, a RAID system is an array of multiple disk drives which appears as a single drive to a data storage system. A goal of a RAID system is to spread, or stripe, a piece of data uniformly across disks (typically in units called chunks), so that a large request can be served by multiple disks in parallel. For example, RAID-5 techniques can be used in connection with a data storage system to protect from a single device failure.
In a particular RAID-5 context, for example, which comprises a storage array of five disk modules, each disk has a plurality of "N" data storage sectors, corresponding sectors in each of the five disks being usually referred to as a "stripe" of sectors. With respect to any stripe, 80% of the sector regions in the stripe (i.e., in a 5 disk array effectively 4 out of 5 sectors) is used for user data and 20% thereof (i.e., effectively 1 out of 5 sectors) is used for redundant, or parity, data. The use of such redundancy allows for the reconstruction of user data in the event of a failure of a user data sector in the stripe.
When a user data disk module fails, the redundant or parity entry that is available in the parity sector of a stripe and the data in the non-failed user data sectors of the stripe can be used to permit the user data that was in the sector of the failed disk to be effectively reconstructed so that the system can remain operative using such reconstructed data even when the user data of that sector of the failed disk cannot be accessed. The system is then said to be operating in a "degraded" mode since extra processing operations and, accordingly, extra time is required to reconstruct the data in the failed disk sector when access thereto is required.
Certain kinds of failures, however, can occur in which the storage array is left in an incoherent or effectively unusable state, e.g., a situation can occur in which there is power failure, i.e., power to a storage processor fails or the storage processor itself fails due to a hardware or software defect, or power to the disk drives themselves fails.
In data storage systems where high-availability is a necessity, system administrators are constantly faced with the challenges of preserving data integrity and ensuring availability of critical system components. One critical system component in any computer processing system is its file system. File systems include software programs and data structures that define the use of underlying data storage devices. File systems are responsible for organizing disk storage into files and directories and keeping track of which part of disk storage belong to which file and which are not being used.
The accuracy and consistency of a file system is necessary to relate applications and data used by those applications. However, there may exist the potential for data corruption in any computer system and therefore measures are taken to periodically ensure that the file system is consistent and accurate. In a data storage system, hundreds of files may be created, modified, and deleted on a regular basis. Each time a file is modified, the data storage system performs a series of file system updates. These updates, when written to disk storage reliably, yield a consistent file system. However, a file system can develop inconsistencies in several ways. Problems may result from an unclean shutdown, if a system is shut down improperly, or when a mounted file system is taken offline improperly. Inconsistencies can also result from defective hardware or hardware failures. Additionally, inconsistencies can also result from software errors or user errors.
Additionally, the need for high performance, high capacity information technology systems are driven by several factors. In many industries, critical information technology applications require outstanding levels of service. At the same time, the world is experiencing an information explosion as more and more users demand timely access to a huge and steadily growing mass of data including high quality multimedia content. The users also demand that information technology solutions protect data and perform under harsh conditions with minimal data loss and minimum data unavailability. Computing systems of all types are not only accommodating more data but are also becoming more and more interconnected, raising the amounts of data exchanged at a geometric rate.
To address this demand, modern data storage systems ("storage systems") are put to a variety of commercial uses. For example, they are coupled with host systems to store data for purposes of product development, and large storage systems are used by financial institutions to store critical data in large databases. For many uses to which such storage systems are put, it is highly important that they be highly reliable and highly efficient so that critical data is not lost or unavailable.

Recovering from metadata inconsistencies in storage systems


In one embodiment, the method includes forming a conductive via structure in a base layer. The base layer has a first surface and a second surface, and the second surface is opposite the first surface. The method further includes removing the second surface of the base layer to expose the conductive via structure such that the conductive via structure protrudes from the second surface, and forming a first lower insulating layer over the second surface such that an end surface of the conductive via structure remains exposed by the first lower insulating layer.

Embodiments of the inventive concepts relate generally to a semiconductor device and/or methods of fabrication, and more particularly, to semiconductor devices having through electrodes or conductive via structure and/or to methods of fabricating the same.
A process of fabricating a semiconductor device with a through electrode or a through silicon via (TSV) may include protruding the through electrode outward from a bottom surface of a substrate, depositing a conventional chemical vapor deposition (CVD) layer on the bottom surface of the substrate, and then exposing the through electrode using a chemical-mechanical polishing process. The conventional CVD layer may have a poor step coverage property. For example, the conventional CVD layer may be formed to be thicker on the through electrode than on other portions. As a result, a lower insulating layer may be folded and the through electrode may be formed to have a high variation in protruding length thereof. Theses may lead to warpage or breakage of the through electrode in a subsequent planarization process, and thus a production yield may decrease.

Semiconductor devices having conductive via structures and methods for fabricating the same


A process is described for shifting a gear change transmission which has no synchronizing members. A defined rotational speed difference is adjusted at the gear clutches in the range of the synchronous rotational speed. Thereby engaging flanks of the clutch halves which are always situated opposite to one another in the same rotating direction come in contact during the shifting.

This application claims the priority of German application 197 17 042.0, filed Apr. 23, 1997, the disclosure of which is expressly incorporated by reference herein.
The present invention relates to a process for shifting a gear change transmission having no synchronizing members, and more particularly, to a process for shifting a gear change transmission having no synchronizing member from an old gear into a new gear without the interruption of the drive connection between the gear change transmission and an internal-combustion engine used as the driving engine and using form-locking gear clutches for coupling a respective gearwheel to its transmission shaft. In a process step triggered by a shifting signal, first the engine torque is reduced and then the gear clutch of the old gear is disengaged, and, in a further process step, when the old gear is disengaged, the rotational engine speed is changed in the direction of the synchronous rotational speed pertaining to the new gear, and, in a further process step, the rotational engine speed--if it is within the range of the synchronous rotational speed--is maintained at a significant value for a defined time period and, in this time period, the gear clutch of the new gear is engaged.
DE 35 07 565 C2 describes a device which operates for establishing the synchronous running of a position change transmission having no shifting clutch members and no synchronizing members for a vehicle, such as a motor vehicle, equipped with an internal-combustion engine as the driving engine. The device is equipped with at least one system for influencing the torque output of the internal-combustion engine, a transmission control unit and means for determining the synchronous point of the position change transmission. During gear shifting, the rotational speed of the internal-combustion engine is changed after the disengagement of the old gear to the rotational speed corresponding to the new gear and, when the synchronous point is reached, the new transmission gear is engaged.
In order to avoid the engagement of the preselected gear from taking place before the synchronous point of the transmission members to be coupled has already clearly been exceeded because the entire arrangement and particularly the mechanical devices for the gear shifting generally are subject to inertia, and in order to thus permit a comfortable, no-jolt engaging of a new transmission gear without the aid of special mechanical synchronizing members, the known device uses a method of operation such that, when the synchronous point is achieved, the torque influencing device can abruptly be acted upon for adjusting such a low torque of the internal-combustion engine that the rotational speed of the internal-combustion engine remains constant or changes only slightly.
An object of the present invention is to keep the shifting forces for engaging the form-locking gear clutches required as low as possible. According to the present invention, this object has been advantageously achieved by providing a process wherein in the process step triggered by the shifting signal, the engine torque is first raised in the coasting operation, and in that the significant value of the engine rotational speed is assigned to a defined rotational speed difference at the gear clutches such that the respective drive-side clutch half, during all shifts, either always has the higher or always has the lower rotational speed with respect to the rotational speed of the output-side clutch half.
During each gear change in the process of the present invention, only one and the same of the two engaging flanks of a clutch tooth of a clutch half of the participating gear clutch can come in contact with an engaging flank of the other clutch half which is adjacent in the circumferential direction. Thereby, a symmetrical chamfering angle or chamfering angles on the two engaging flanks of a clutch tooth is or are no longer required. Such a chamfering angle always results in an axial force component which limits the shifting comfort.
Therefore, in the process according to the present invention, the use of gear clutches, in which one engaging flank of a clutch tooth is situated completely in a plane containing the clutch axis, has been found advantageous.
In the process according to the invention, the synchronous rotational speed can be adjusted such that a residual differential rotational speed remains, specifically such that the rotational speed of the engine-side transmission elements (gear wheel) is higher than the rotational speed of the output-side transmission elements (clutch sleeve). Advantageously, these differential rotational speeds are between 10 min.sup.-1 and 40 min.sup.-1.
In the process of the invention, the shifting of the respective gear wheel clutch always takes place such that the same engaging flanks of the clutch teeth strike against one another, irrespective of whether it is an upshift or a downshift.
Thus the engaging flanks of the respective clutch tooth can be configured such that one engaging flank has no chamfering angle, and the other engaging flank is provided with a chamfering angle. Thereby, the clutch teeth of the two clutch halves always strike against one another with the straight engaging flanks and, as a result, only circumferential forces are generated which reduce the remaining differential rotational speed. No axial forces are generated which would counteract the shifting force. The chamfering angle of the second engaging flank permits an axial engaging of the clutch teeth when sweeping over the differential angle between two opposite clutch teeth.
The present invention also relates to a testing step for initiating or terminating a process step under defined conditions.

Process for shifting a gear change transmission without synchronizing members


A tool display assembly includes a card having a dove-tailed flange formed to a lower edge thereof, at least one connecting member having a dove-tailed groove defined in a top thereof sa as to receive the dove-tailed flange therein and a lower end having four walls extending downwardly therefrom so as to form a rectangular portion to be received in a socket. An aperture is defined through a top of the lower end of the connecting member. A hook member has a hook formed on a top thereof and a stop bar extending transversely from a lower end thereof such that the hook extends through the socket and the rectangular portion and is engaged with the aperture.

1. Field of the Invention
The present invention relates to a tool display assembly and, more particularly, to a tool display assembly having at least one connecting member to connect a tool, such as a socket, to a display card with a hook member securely combining the socket and the connecting member so as to prevent the socket from being stolen.
2. Brief Description of the Prior Art
FIG. 4 shows a conventional socket display assembly which includes a metal plate 60 having a longitudinal protrusion 601 extending centrally from an upper surface thereof and at least one U-shaped member 62 which has two distal ends each having a groove 63 defined in an inner side thereof so as to slidably receive two sides of the metal plate 60 therein. A lower portion 64 of the U-shaped member 62 is used to be force-fitted into an engaging hole 72 of a socket 70. It is to be noted that the lower portion 64 is flexible so that it can be narrowed slightly and force-fitted into the engaging hole 72. After the lower portion 64 is inserted into the socket 70, it applies an outward force against an inner periphery defining the engaging hole 12 such that the socket 70 is connected to the U-shaped member 62.
An inherent problem to be overcome is that the socket 70 could b directly pulled from the U-shaped member 62 or the metal plate 60 intentionally or unintentionally. In addition, when sliding the U-shaped members 62 to the metal plate 60, fingers of assemblers could be hurt by the sharp and thin sides of the metal plate 60.
The present invention intends to provide an improved tool display assembly which is easily operated and effectively prevents the tools on the display assembly from being stolen so as to mitigate and/or obviate the above-mentioned problems.

No. 22, West 4th Alley, Lin 20, Hsi Ping Li, Hua Hsia Lane


A water releasing composition in the form of an emulsion and process for using the composition are provided. The composition includes an aqueous phase and an oil phase. The aqueous phase includes at least one water-soluble active ingredient at a concentration by weight of from about 0.1% to about 20%, based upon weight of the composition. The oil phase includes dimethicone at a concentration by weight of about 1% to about 25%, and an emulsifying crosslinked siloxane elastomer at a concentration by weight of about 0.1% to about 20%, both based upon weight of the composition. The composition has a phase ratio of the aqueous phase to the oil phase of about 3.0 to about 12.0. The composition converts from an emulsion to a plurality of droplets upon application of shear.

The incorporation of water-soluble active ingredients into emulsion-type compositions has posed various stability challenges. This has been especially true when the desire was to incorporate larger amounts of said ingredients into compositions. Examples of lack of stability include discoloration of the formula and/or precipitation of the ingredients out of the composition. It is therefore an object of the present invention to provide a composition capable of stably carrying water-soluble active ingredients, which is also tactilely pleasing to consumers upon application.

This patent is subject to a terminal disclaimer.

Carrier system for water-soluble active ingredients


To insure that no air bubbles are included in a pump of an anti-locking system, the pump is placed into the master brake conduit, thereby causing it to be scavenged by manual brake operation. Once a brake pressure of about 5 bar is attained, a switch-over valve (28) is switched-over, causing the master brake conduit in the pressure build-up direction to be blocked. Additionally pressure fluid is supplied to the secondary conduit (26) and a pressure opening valve (27). The pressure decrease is effected through the direct conduit (13). In the event of a brake slip control, the pump takes in pressure fluid from the reservoir (25) through the suction valve (22).

A brake system of the type with which the present invention is concerned is described in German Patent application No. P 40 00 837.1 and copending U.S. patent application Ser. No. 07/638,927, filed on Jan. 9, 1991. The pump is located in the brake conduit connecting the master cylinder and wheel cylinder and separated from the master cylinder upon commencement of a slip control operation. The separation is performed by an electromagnetically actuated separating valve.
If the separating valve were not activated, this would result in the master brake cylinder being evacuated during a control operation. Switching of the separating valve hence, is thus absolutely necessary prior to a control operation. Accordingly, it is readily apparent that the switch-over operation of the separating valve must be monitored.
It is, therefore an object of the invention to provide an improved brake system of this type in which the need for an electromagnetically actuated separating valve is eliminated while insuring a reliably operating system.


A mattress assembly including a bottom mattress section and a top, transfer mattress section is provided. The transfer mattress section includes lateral flaps which are coupled to the sides of the bottom mattress section by hook and loop type fasteners. Pull straps are secured to the flaps for moving the transfer mattress section, and a patient thereon, with respect to the bottom mattress section once the fasteners have been disengaged. The interface of the top and bottom mattress sections is low friction to facilitate sliding the top mattress section with respect to the bottom mattress section.

1. Field of the Invention.
The field of the invention relates to patient transfer assemblies for transferring patients from hospital beds, stretchers or the like to other supports.
2. Brief Description of the Prior Art.
The difficulty of moving a patient from one support, such as a stretcher, to another is well recognized. Various systems have accordingly been designed for transferring patients without actually first lifting them.
One such system is disclosed in U.S. Pat. No. 4,970,738. This system includes a semi-rigid transfer apron and a mattress attached to the transfer apron. Low friction belts are attached to the transfer apron and to an endless belt. A crank is employed to rotate the endless belts, causing the transfer apron to be translated laterally across a rigid support.
U.S. Pat. No. 4,796,313 and U.S. Pat. No. 4,819,283 disclose transfer mechanisms including transfer sheets wound upon rollers. The patient is transported longitudinally as opposed to laterally.
U.S. Pat. No. 5,329,655 discloses a method for turning or transferring a patient which includes the use of a bed sheet having a bottom surface characterized by low frictional drag and a top surface having higher frictional drag. The sheet is ordinarily tucked under a mattress to maintain it in place.
U.S. Pat. No. 3,829,914 discloses a sheet including a slippery bottom surface and handles. The sheet is used for positioning a patient upon a mattress.
WO 94/2002 discloses a sheet including gripping strips for shifting a patient from one bed to another. The sheet is positioned on a mat conveyor to effect transfer.


A rotatable hoisting device includes a hanging unit with a hook, and a rotary shaft which is connected to the hanging unit. The rotary shaft is driven by a power drive unit for rotating and adjusting the hanging unit, thereby rotating a form hung on the hook to a desired angular position before it is positioned.

1. Field of the Invention
This invention relates to a hoisting device for a crane, more particularly to a hoisting device with a hanging unit which is rotatable and adjustable to a desired angular position.
2. Description of the Related Art
In the conventional way of transporting an article to a desired location with the use of a crane, cables on the crane are fastened to a hoisting device. The hoisting device has a hook hung therefrom, and the hook holds together the top ends of four hanging chains. The bottom ends of the hanging chains extend away from each other and are fastened to the corners of the article. In construction sites, it is frequent to hoist a modular form assembly into a building or from floor to floor with the use of a crane and then position the same at a location where concrete will be formed. When the form assembly is hung on the hoisting device, it would normally rotate. In order to place the form assembly in a proper position, the position of the form assembly must be manually controlled and adjusted by operators when the form assembly is unloaded from the hook of the hoisting device. However, because of its bulky volume and heavy weight, handling of the form assembly is difficult to be conducted by operators.

Rotatable hoisting device for position adjustment

Nan-Shing Tsun, Kui-Jen Hsiang, Tainan Hsien


A water impervious, elastomeric coating is applied to the outer surface of a foundation wall and across the joint between the lower end of the wall and the footing. Protection board is bonded to the elastomeric coating and serves to prevent damage to the coating during backfilling of the foundation wall. The protection board is composed of an impact resistant, extruded, thermoplastic material and has inner and outer faces connected together by a series of parallel spaced ribs which define vertical channels that extend the height of the board. A plurality of spaced isolated holes are formed in the outer face of the board and communicate with the channels. The board not only protects the elastomeric coating from damage, but the inner face provides an additional waterproofing membrane, and the holes and channels facilitate movement of water to the drain tile and relieve hydrostatic pressure on the wall.

Waterproofing coatings are frequently applied to the outer surface of concrete foundation walls to prevent water penetration through the wall. By definition, a "waterproofing" coating is one that will prevent the passage of water when the water present in the soil is under hydrostatic pressure. In contrast, a "damp-proofing" coating is one which is not intended to be impermeable when the water in the soil is under pressure. An extremely effective waterproofing coating is that described in U.S. Pat. No. 5,352,531. The coating of that patent is a highly adhesive, elastomeric type which is asphalt free and when cured is of nonhazardous and nontoxic. The coating, preferably applied to the foundation wall by spraying, provides an elastic, highly adhesive, water impervious membrane that firmly adheres to the foundation wall to prevent penetration of water through the wall even when the wall is subjected to substantial hydrostatic pressure, up to about 90 pounds per square foot, or more.
After application of the elastomeric coating to the foundation wall, the wall is backfilled normally through use of mechanical handling equipment, such as a bulldozer. It has been found that during backfilling, solid material such as coarse rocks and stones, scrap lumber, sheet metal, and other materials may be forced against the wall and may rupture the elastomeric coating, with the result that the water impermeable characteristics of the coating may be destroyed. Because of this, it is recommended to apply protection board over the elastomeric coating. The protection board is applied to the tacky coating and will firmly bond to the coating. The protection board as used in the past, is not in itself a waterproofing membrane. A common type of protection board as used in the past, is polystyrene foam board The polystyrene foam board aids in protecting the elastomeric coating and has some insulating value. However, the polystyrene foam is somewhat brittle and can be fractured by backfilling. Further, the polystyrene foam is not waterproof and over time will absorb water so that the protection board, in itself does not constitute a waterproofing membrane.
U.S. Pat. No. 5,511,346 describes a foundation wall construction utilizing a thermoplastic foam insulation and drainage board. In accordance with that patent, the outer surface of the foam insulation board is provided with a series of parallel flow channels each channel having a narrow inlet at the outer surface of the board and a wider portion in the interior of the board. The patent states that the channels aid in providing water drainage downward to the drain tile at the footing. However, with the construction as shown in U.S. Pat. No. 5,511,346, the channels cannot be placed too closely together without destroying the physical integrity of the foam board. If the channels are located too closely together, the thin area between channels is susceptible to damage and breakage during backfilling.


A drive unit for driving an electric motor includes two motor drive circuits disposed in parallel and each consisting of a bridge circuit of switching devices each incorporating a reverse blocking diode, a power switch provided between a power supply and each of the bridge circuits, and a function switch provided between the electric motor and each of the bridge circuits. In case of failure of one bridge circuit, the other bridge circuit is used to replace the failed bridge circuit, thereby continuing controlled operation of the electric motor. While these switches which are associated with one of the bridge circuits are closed, the switches associated with the other bridge circuit are kept open. This arrangement prevents the current from flowing from the power supply into the failed bridge circuit. The failed bridge circuit does not allow the electric motor to act as a generator even when any of the switching devices causes an ON fault.

1. Field of the Invention
The present invention relates generally to a drive unit for driving an electric motor by computer control based on information from various sensing devices, and more particularly to a motor drive unit for use with an electric power steering apparatus or a four-wheel steering system installed in a motor vehicle.
2. Description of the Related Art
An electric power steering apparatus installed in a motor vehicle includes a steering torque sensor for detecting a steering torque produced during steering operation by the driver. The steering torque sensor generates a torque signal corresponding to the detected steering torque, which is used in combination with a signal from another sensing device to generate a motor drive signal, such as PWM (pulse-width modulation) signal, for controllably driving an electric motor via a drive unit in such a way that an appropriate steering assist torque is supplied from the electric motor to the steering system, thereby lightening the manual steering effort of the driver.
One example of known motor drive unit includes a bridge circuit (H-type bridge circuit) composed of two pairs of switching elements or devices, such as junction field-effect transistors "JFETs" or metal-oxide-semiconductor field-effect transistors "MOSFET", each incorporating one diode connected in parallel with the associated switching device to block current flow in the opposite direction from that of the associated switching device (the diode being thereinafter referred to as "reverse blocking diode"). The switching devices in each pair are connected in series and two pairs of such series connected switching devices are connected in parallel. A power supply is connected to a junction between the two parallel connected switching device pairs, and the electric motor is connected between respective junctions between the series connected switching devices.
The motor drive unit of the electric power steering apparatus, as against a control unit for an automotive engine, does not employ a duplex system in which each of two distinct units becomes available to recover over a failure of the other unit. Accordingly, a failure occurring in the motor drive unit may result in malfunctioning of the entire system of the electric power steering apparatus. In the case where the failure is the so-called "Off fault" of any of the switching devices (at which the faulty switching device is fixed in the OFF state), no power is supplied from the power supply to the electric motor. In case of the failure being the so-called "ON fault" of any of the switching devices at which the faulty switching device is fixed in the ON state, power from the power supply is continuously supplied to the electric motor. In either case, accurate drive control of the electric motor is difficult to achieve.
The foregoing problems may be overcome by an improved motor drive unit in which a duplex system is incorporated. There still exist a problem however that when each of two distinct drive units is operating to controllably drive the electric motor while the other drive unit assumes a standby status, current may flow from the power supply to the other drive unit, deteriorating the accuracy of drive control of the electric motor. Additionally, when an ON fault occurs in one of the switching devices of the other drive unit, operation of one drive unit causes the other drive unit to form a closed circuit which allows the electric motor to act as a generator, making it difficult to achieve accurate drive control of the electric motor.


An oil drainage catch pan (A) having an open top (10) for receiving used engine oil drained therein has a reservoir (B) on one end of the pan with a discharge spout (C) and a container (D) connected by a coupling (E) to the spout. After collecting the used oil in the catch pan, the catch pan is tilted causing the used oil to flow to the reservoir and drain through the spout into the container for containment and transport to a suitable location.

This invention relates to an apparatus and method for draining used engine oil from vehicles and the like wherein a catch pan and a container are utilized for receiving and containing used oil for transport to a suitable location for disposal in an environmentally desirable fashion.
Used vehicle engine oil is a common source of contamination of soil and water, and its proper disposal is high on the list of environmental projects. Attempts to dispose of engine oil in a suitable fashion have been many and varied and have included the use of disposable containers which may be in the form of plastic bags. Drainage apparatus employing plastic bags is illustrated in U.S. Pat. No. 4,022,257 wherein the bag is received through an opening in the side of a collection funnel and the top of the bag is passed over the top of the funnel so as to avoid contamination of the funnel while containing the oil discharged from the vehicle into the funnel. Such an apparatus has the disadvantage of being difficult to manipulate when draining used engine oil during an oil change by one changing his own oil. The following U.S. Pat. Nos. further illustrate the state of the art: 4,025,048; 4,033,432; 4,269,237; 4,592,448; and 4,756,349.

Vehicle oil drainage apparatus and method


There is provided an antenna arrangement for a radio transceiver device for simultaneous use of two polarization directions. The antenna arrangement comprises at least two baseband chains. The antenna arrangement further comprises a first set of antenna elements of a first polarization direction, and a second set of antenna elements of a second polarization direction. The antenna arrangement comprises an analog distribution network operatively connecting the at least two baseband chains to both sets of antenna elements. All of the baseband chains are operatively connected to each respective antenna element of the first set and to each respective antenna element of the second set via the analog distribution network.

In communications networks, there may be a challenge to obtain good performance and capacity for a given communications protocol, its parameters and the physical environment in which the communications network is deployed.
For example, for future generations of mobile communications systems frequency bands at many different carrier frequencies could be needed. For example, low such frequency bands could be needed to achieve sufficient network coverage for terminal devices and higher frequency bands (e.g. at millimeter wavelengths (mmW), i.e. near and above 30 GHz) could be needed to reach required network capacity. In general terms, at high frequencies the propagation properties of the radio channel are more challenging and beamforming both at the network node at the network side and at the terminal devices at the user side might be required to reach a sufficient link budget.
The terminal devices and/or the transmission and reception point (TRP) of the network node could implement beamforming by means of analog beamforming, digital beamforming, or hybrid beamforming. Each implementation has its advantages and disadvantages. A digital beamforming implementation is the most flexible implementation of the three but also the costliest due to the large number of required radio chains and baseband chains. An analog beamforming implementation is the least flexible but cheaper to manufacture due to a reduced number of radio chains and baseband chains compared to the digital beamforming implementation. A hybrid beamforming implementation is a compromise between the analog and the digital beamforming implementations. As the skilled person understands, depending on cost and performance requirements of different terminal devices, different implementations will be needed.
For terminal devices the incoming signals might arrive from all different directions. Hence it is beneficial to have an antenna implementation at the terminal devices which has the possibility to generate omni-directional-like coverage in addition to the high gain narrow beams.
However, for antenna arrays with single polarized antenna elements (and implementing analog beamforming) it could be challenging to generate beams with a large variety in beamwidths. Hence, antenna arrays with dual-polarized elements are preferred such that dual-polarized beamforming as disclosed in WO2011/050866 A1 and WO2016141961 A1 can be used to generate beams with basically any beamwidths, ranging from the beamwidth of a single antenna element to the beamwidth of the entire antenna array.
One issue with using dual-polarized beamforming, where both polarization ports are used to create a port, for an antenna array implementing analog beamforming is that the resulting beam will only have one distinct polarization in each direction, which means that polarization mismatch can occur between the transmitter and receiver, which can deteriorate the link significantly.
FIG. 1 schematically illustrates an antenna arrangement 100 having two baseband chains 110a, 111b. Each baseband chain 110a, 110b is operatively connected to antenna elements 130a, 130b of an antenna array 120, where one of the baseband chains is operatively connected to all antenna elements of a first polarization, and the other of the baseband chains is operatively connected to all antenna elements of a second polarization.
Even though the antenna arrangement 100 has one baseband chain per polarization, only one signal for one polarization can be transmitted/received in each direction at a given time. It is envisioned that the number of baseband chains might possibly be reduced whilst at the same time applying dual-polarized beamforming for an antenna array implementing analog beamforming, where a single baseband chain is connected to all antenna elements of both polarizations of the antenna array. In this way dual-polarized beamforming can be applied whilst only using a single baseband chain. Such an antenna arrangement might be cheaper to manufacture compared to the antenna arrangement illustrated in FIG. 1. But if two orthogonal polarizations are desired simultaneously with the envisioned antenna arrangement, two such antenna arrangements have to be stacked next to each other, which adds implementation space.

Antenna arrangement for two polarizations


A puzzle book having a front cover, a back cover, a plurality of pages disposed between the front and back covers, and a puzzle disposed on the exterior side of the front cover. The puzzle is composed of a plurality of interlocking puzzle pieces which are disposed in a cavity formed in the exterior side of the front cover. Each of the puzzle pieces has a portion of a printed image formed thereon and a plurality of interlocking portions. The cavity in which the puzzle pieces are disposed may have a shape defined by an internal perimeter of a border area, and the border area may have a plurality of interlocking portions which mate with the interlocking portions of the puzzle pieces to help hold the puzzle pieces within the cavity when the front cover of the puzzle book is opened. The puzzle book may also be provided with a single sheet of transparent material which covers at least a portion of the puzzle and which is removable from the front cover. The transparent material may be a sleeve or band shrink-wrapped around the front cover or a rectangular sheet adhered to the front cover.

The invention is directed to a book which incorporates a puzzle therein.
U.S. Pat. No. 5,213,507 to Ozrovitz discloses a child's story and picture book having a front cover, a back cover, and a plurality of pages pivotally disposed between the front and back covers. At least one of the pages includes text on one or more sides and a puzzle on the other side. The puzzle has a plurality of interlocking puzzle pieces.
The Ozrovitz puzzle pieces may be provided with a transparent material, such as plastic, disposed over and attached to an overlay material. The transparent material on the puzzle pieces allows an erasable material, such as paraffin wax, to be used by a child to color the puzzle pieces. Ozrovitz indicates that the erasable material should preferably cover only the puzzle pieces.


An optical head using a semiconductor laser array as a light source comprises a semiconductor laser array in which a plurality of semiconductor lasers are linearly arrayed, a collimator lens, an objective lens and a beam shaping prism system. The beam shaping prism system is arranged between the collimator lens and the objective lens to convert a beam width of a beam emerged from the collimator lens. The junction surfaces of the semiconductor lasers are parallel with an array direction. A plane defined by incident and emerging beams on and from the beam shaping prism system is parallel with or overlapping the array direction of the semiconductor lasers.

The present invention relates to an optical head using a semiconductor laser (to be referred to as an LD hereinafter) as a light source and, more particularly, to an optical head using an LD array in which a plurality of LDs are linearly arrayed as a light source.
Conventionally, many proposals have been made about a method of optically recording/reproducing data on/from a data recording medium using an optical head having an LD array as a light source. For example, Japanese Patent Publication Nos. 57-60697, 58-56164, 59-9976, 59-18772, and 61-20057 are known.
FIG. 1 shows a structure of an optical head shown in an embodiment of Japanese Patent Publication No. 61-20057. A description will be made along the propagation of a light beam. Divergent light beams emitted from an LD array 102 having a plurality of light-emitting points 101.sub.1, 101.sub.2, and 101.sub.3 are collimated by a collimator lens 103. These light beams pass through polarizing beam splitter 104 and a .lambda./4 (quarter wavelength plate 105, and then form small spots 108.sub.1, 108.sub.2, and 108.sub.3 on a recording surface 109 of a recording medium 107 by an objective lens 106. The light beams reflected by the recording surface 109 pass through the objective lens 106 and the .lambda./4 plate 105. Since the light beams reciprocate through the .lambda./4 plate 105, they are reflected by the polarizing beam splitter 104, and then are converged on a light-receiving element 111 by a focusing lens 110.
Various applications of functions and roles of the plurality of small spots 108 on the recording surface 109 can be proposed. For example, assume that the recording medium 107 is moved in a direction of an arrow A in FIG. 1 relative to an optical head. The small spot 108.sub.2 is used for recording data, and the small spot 108.sub.3 is used for auto focus control and auto tracking control and for reproducing recorded data. The small spot 108.sub.1 is used for preheating a recording region or for detecting a defect or dust on the surface of the recording medium 107. These functions are realized by arranging light-receiving portions corresponding in number to the small spots 108 on the light-receiving element 111 and detecting a variation in light amount of each light beam. In the above description, the function of each small spot 108 is merely an example, and other applications may be adopted.
However, there are the following drawbacks upon employment of an optical head using an LD array as a light source having the structure shown in FIG. 1. In general, auto focus control and auto tracking control techniques are necessary for accurately recording or reproducing data on/from a predetermined position on the recording surface 109 of the recording medium 107. For this purpose, the objective lens 106 is moved to be perpendicular to or parallel to the recording surface 109 of the recording medium 107. Therefore, the objective lens 106 is required to be lightweight and compact. In consideration of this requirement, a double-aspherical single lens having a focal length fo of about 4 to 5 mm has been developed for an objective lens. In order to increase a recording density, each small spot 108 on the recording surface 109 is required to have a spot size of about 1.5 .mu.m. For this purpose, the objective lens 106 must have a feature of a very bright lens, i.e., have a numerical aperture (NA) of about 0.5. When the objective lens 106 of such specifications is designed, it is important to correct spherical aberration, an coma, and an astigmatism. However, in the optical head shown in FIG. 1, light components on and outside the optical axis, i.e., a plurality of small spots 108.sub.1 to 108.sub.3 must be satisfactorily focused on an identical plane, i.e., the recording surface 109. Therefore, correction of curvature of field must be taken into account in addition to the aberrations.
Optical components used in an optical head are designed to have a target R.M.S. value (Root Mean Square) of 0.07.lambda. or less of a total wavefront aberration of the optical components between the light source and the recording surface according the Strehl definition (.lambda. is the wavelength of an LD).
In the above specifications, a field angle of the objective lens 106 which can satisfy the above definition is about 0.5.degree.. Therefore, if the focal length fo of the objective lens 106 is 4.5 mm, an interval l between adjacent small spots 108.sub.1 and 108.sub.2 on the recording surface has an upper limit of about 40 .mu.m.
The interval l is preferably as large as possible as long as focusing performance is not impaired. The reason for this is as follows. For example, as described above, when auto focus control and auto tracking control are performed using the small spot 108.sub.3, if there is a considerably large amount of dust on the surface of the recording medium 107, it is impossible to perform accurate control using the spot 108.sub.3. In an extreme case, an erroneous recording operation may be performed by the spot 108.sub.2 at a position other than desired. In order to prevent such an erroneous operation, a change in light amount of the spot 108.sub.1 is detected to detect the presence of dust or the like in advance. An auto focus mechanism and an auto tracking mechanism (neither are shown) are fixed in position for a predetermined period of time, and are restarted later. Therefore, a given processing time is required after dust or the like is detected by the spot 108.sub.1 until the fixing operation of the mechanisms is started. For this reason, the interval l is preferably at large as possible.
Points to be noted about an interval p between the adjacent light-emitting points 101 in the LD array 102 will now be pointed out. As a form of the LD array 102, a hybrid type in which a plurality of independent LDs are linearly arrayed and fixed in a single package and a monolithic type in which a plurality of light-emitting points 101 capable of being independently driven are formed by an identical semiconductor substrate are known. In the former type, the interval p between a plurality of light-emitting points 101 is preferably large in view of an array packaging technique. In the latter type, a problem of thermal crosstalk, i.e., a problem that a signal for driving the light-emitting point 101.sub.1 leaks to influence the adjacent light-emitting point 101.sub.2, is posed. In order to avoid this problem, the interval l between adjacent light-emitting points is set to be at least 100 .mu.m or more, and is preferably set to be 150 .mu.m or more.
To summarize the above preferred requirements, a focal length fc of a preferred collimator lens 103 is determined. That is, EQU fc=p.multidot.fo/l (1)
fo=4.5 mm, l=40 .mu.m, and p=150 .mu.m are substituted in this equation to yield fc=16.875 mm.
However, when the collimator lens 103 having such a long focal length is used, the dimensions of the entire optical head are increased, and its weight becomes heavy. Therefore, such a structure disturbs a high-speed access operation of the entire optical head.
In the arrangement of the optical head shown in FIG. 1, a near-field shape of the light-emitting point 101 is directly projected onto the recording surface 109, and the small spot 108 has an elliptical or oval shape, and is not preferable for a requirement of high recording density.
FIG. 2 is a block diagram of an optical recording/reproducing apparatus described in an embodiment of Japanese Patent Laid-Open (Kokai) No. 61-206925. The apparatus shown in FIG. 2 is constituted by a semiconductor laser array 201, a collimator lens 202, an expanding prism 203, a polarization prism 204, a .lambda./4 plate 205, a converging lens 206, a disk 207, lenses 208 and 209 for converging a beam from the polarization prism 204, and a photosensor 210.
However, Japanese Patent Laid-Open (Kokai) No. 61-206925 merely describes that the semiconductor laser array and the expanding prism are used, and has no description about a detailed arrangement condition of the semiconductor laser array and the prisms for shaping a beam.

Optical head using semiconductor laser array as light source


A single elongated light source fixture is disclosed. The fixture, comprising a hyperbolic reflector combined with a single elongated light source such as a fluorescent tube, provides adequate levels of illumination while substantially saving energy usage compared to existing light fixtures.

This invention relates to reflectors, specifically, to reflectors in the cross-sectional shape of conic sections for fluorescent light fixtures. Other patents have taught how to use reflectors on light fixtures which have a cross-sectional shape generally hyperbolic, generally elliptic, or generally parabolic. For example, U.S. Pat. No. 4,089,047 uses reflectors with elliptical cross-sections with the feature of one set of focuses of the ellipses being coincident and with the other focuses located at the ceiling level. These incandescent light fixtures use only reflected light with the embodiment designed such that all direct light coming from the light source is blocked. This patent would restrict the fixture to something small in diameter in order to meet the requirement of having one set of focuses coincident. Having all direct light blocked seriously limits the efficiency and usefulness of the lamp. A hyperbolic reflection surface is added to the lamp in another embodiment which is described, however, no diagram of the configuration is provided and the juxtaposition of the light source and the focus of the hyperbola is not taught.
U.S. Pat. No. 4,683,526 claims a desk lamp with a reflector in the shape of a parabola formed from a series of triangular facets. This patent claims a method to approximately construct at reasonable cost, a curved reflection surface to improve the light delivery from the lamp.
Although there are a number of fluorescent light fixtures on the market, few seem to utilize the direct light and reflected light coming from the light source to full advantage. Reflection surfaces are painted milky white which has a medium reflectance. Some reflectors are being made on special order to retrofit existing light fixtures, reduce the number of fluorescent tubes, and thus improve the light efficiency and energy utilization. These retrofit reflectors are fabricated by bending them into rectangular facets thus approximating a parabola in cross-sectional shape. A highly reflective material, such as Silverlux by 3M Company, applied to the surface of a thin aluminum sheet, is being used on these reflectors.
Generally, fluorescent light fixtures which are designed to provide illumination for an area should:
a. Uniformly illuminate the area. PA1 b. Minimize the formation of shadows. PA1 c. Provide light agreeable for human activity. PA1 d. Minimize the use of energy while providing an adequate level of illumination.
Accordingly, there is a need for new, optimized, light fixtures which will provide uniform light patterns coupled with an adequate level of illumination, and providing substantial energy savings. They must be suitable for use in new building construction or retrofit to existing structures, for illumination of art works or advertising signs, and for use in homes, stores, and offices.

Reflectors for fluorescent light fixtures