A semiconductor memory device having a sense amplifier, comprises an n-type sense amplifier formed of an nMOS transistor with a source connected to a bit line and a gate connected to an inverted bit line, and an nMOS transistor with a source connected to the inverted bit line and a gate connected to the bit line. In activating the n-type sense amplifier, the voltage of a control signal line is set to a voltage Vss2 lower than a ground voltage Vss. In restoring data in a capacitor of a memory cell, the voltage of the control signal line is set to the ground voltage Vss. With this setting, the sense amplifier can operate at an ultra-low voltage and can ensure a satisfactory operation margin.

The present invention relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device having a dynamic memory cell with a bit line sense amplifier which steadily operates even at a low voltage.
This application is based on Japanese Patent Application No. 9-149159, filed Jun. 6, 1997, the content of which is incorporated herein by reference.
Along with the advance in manufacturing techniques relating to a semiconductor device, the scales of elements used in semiconductor memory devices are being decreased. Accordingly, with a conventional power supply voltage Vcc, the field density at each portion of the element is too high, and the reliability of the device is degraded. To suppress the degradation of the reliability, the operation power supply voltage Vcc is decreased. For example, the power supply voltage is 5V in a 1-Mbit DRAM, but 3.3V in most 16-Mbit DRAMs mass-produced at present.
The decrease in power supply voltage Vcc yields a secondary advantage, i.e., reduction in power consumption. Therefore, the technique of decreasing the power supply voltage Vcc is important in the fields of semiconductor memory devices and semiconductor integrated circuit devices.
Recently, portable data processing devices such as a PDA (Personal Digital Assistants) are rapidly spread because of small sizes, high performance, and advanced functions. Particularly in recent years, along with the advance in functions, semiconductor memories such as a DRAM are also incorporated in the internal systems of portable data processing devices.
To realize smaller-size, higher-performance portable data processing devices with more advanced functions, the operation voltage of the semiconductor memory is further decreased. That is, the power supply voltage is decreased from 3.3V to 1 to 1.5V. As a result, the portable data processing device can be further decreased in power consumption and can operate with a battery.
In addition, ultra-low-power-supply-voltage operation semiconductor memories which operate at a power supply voltage Vcc of 1V or less are also developed. Such a semiconductor memory is useful in not only portable data processing devices but also other electronic devices.
As the power supply voltage Vcc decreases to a low or ultra low voltage, it becomes difficult to meet demands for a bit line sense amplifier, i.e., to detect and amplify a small data signal from a memory cell.
A typical bit line sense amplifier will be described below.
FIG. 18 is a circuit diagram of a typical bit line sense amplifier used in a conventional DRAM. FIG. 19 is an operation waveform chart of the sense amplifier.
The circuit arrangement will be explained.
As shown in FIG. 18, a bit line BL connected to a dynamic memory cell MC1 and an inverted bit line /BL ("/" means "inverted" hereinafter) connected to another memory cell MC2 are arranged. The bit line BL and the inverted bit line /BL are paired (to be referred to as a pair of bit lines hereinafter).
The memory cell MC1 comprises a transfer gate transistor TR1 and a memory capacitor C1. The transfer gate transistor TR1 has a current path and a gate electrode connected to a word line WL1. One end of the current path is connected to the bit line BL. Two electrodes of the memory capacitor C1 are connected to the other end of current path of the transfer gate transistor TR1 and a plate electrode, respectively. The electrical charge of memory data is stored at a contact node of the TR1 and C1 (a storage node). The plate electrode receives a plate voltage VPL. Similarly, the memory cell MC2 comprises a transfer gate transistor TR2 and a memory capacitor C2. The transfer gate transistor TR2 has a current path and a gate electrode connected to a word line WL2. One end of the current path is connected to the inverted bit line /BL. Two electrodes of the memory capacitor C2 are connected to the other end of current path of the transfer gate transistor TR1 and a plate electrode, respectively. The electrical charge of memory data is stored at a contact node of the TR2 and C2 (a storage node). The plate electrode receives the plate voltage VPL.
The pair of bit lines are connected to a bit line pair equalizer 10, an n-type sense amplifier 11, and a p-type sense amplifier 12.
The bit line pair equalizer 10 comprises an n-channel MOSFET (to be referred to as an nMOS transistor hereinafter) N3 with a current path series-connected between the bit line BL and the inverted bit line /BL, an nMOS transistor N4 which has one current path end connected to the bit line BL and receives, at the other end, an intermediate voltage Vcc/2 between a high voltage Vcc and a low voltage Vss (for example, ground voltage), and an nMOS transistor N5 which has one current path end connected to the inverted bit line /BL and receives the intermediate voltage at the other end. The gates of the NMOS transistors N3 to N5 receive a precharge signal PRC.
The n-type sense amplifier 11 comprises an nMOS transistor N1 with one current path end connected to the bit line BL and a gate connected to the inverted bit line /BL, and an nMOS transistor N2 with one current path end connected to the inverted bit line /BL and a gate connected to the bit line BL. The other end of the current path of each of the nMOS transistors N1 and N2 is connected to a activating node SAN.
The activating node of the n-type sense amplifier 11 SAN is connected to the intermediate voltage Vcc/2 via a switch SW1N and the low voltage Vss via a switch SW2N.
The p-type sense amplifier 12 comprises a p-channel MOSFET (to be referred to as a PMOS transistor hereinafter) P1 with one current path end connected to the bit line BL and a gate connected to the inverted bit line /BL, and a pMOS transistor P2 with one current path end connected to the inverted bit line /BL and a gate connected to the bit line BL. The other end of the current path of each of the pMOS transistors P1 and P2 is connected to a activating node SAP.
The activating node of the p-type sense amplifier 12 SAP is connected to the intermediate voltage Vcc/2 via a switch SW1P and the high voltage Vcc via a switch SW2P.
The operation will be explained.
As shown in FIG. 19, the word line WL1 is at the low voltage Vss during the standby period (precharge period). The switches SW1N and SW1P are ON, and the switches SW2N and SW2P are OFF. With this setting, the activating nodes SAN and SAP are at the intermediate voltage Vcc/2. The precharge signal PRC is at the high voltage Vcc. The voltages of the pair of bit lines BL and /BL are equalized to the intermediate voltage Vcc/2.
After the precharge period, the read/write period (active period) starts. When the precharge period shifts to the read/write period, the precharge signal PRC first changes to the low voltage Vss. The switches SW1N and SW1P are turned off, and the activating nodes SAN and SAP are disconnected from the intermediate voltage Vcc/2. If the word line WL1 of all word lines is selected, its voltage rises to an active voltage of the word line VWLH higher than the high voltage Vcc. Data corresponding to the storage charge amount is previously written and stored in the storage node electrode SN1 of the memory cell MC1. During a read period, the voltage of the word line WL1 rises to the voltage VWLH to turn on the transfer gate transistor TR1 of the memory cell MC1, and the electrical charge written in the storage node electrode SN1 is transmitted to the bit line BL. As a result, the voltage of the bit line BL slightly changes. When data "1" is written in the storage node electrode SN1, the voltage of the bit line BL rises by +.DELTA.V; when data "0" is written in the storage node electrode SN1, the voltage of the bit line BL falls by -.DELTA.V. FIG. 19 exemplifies the case wherein the voltage rises by +.DELTA.V. The voltage .DELTA.V and a memory capacitor CS/bit line capacitor CB have a relationship of .DELTA.V=(CS/CB).times.(Vcc/2).
After the data of the memory cell is transferred to the bit line, the switches SW2N and SW2P are turned on. Then, the activating node SAN is connected to the low voltage Vss, and the activating node SAP is connected to the high voltage Vcc. The sense amplifiers 11 and 12 are activated. The voltage of the bit line BL further rises from (Vcc/2)+.DELTA.V to the high voltage Vcc, whereas the voltage of the inverted bit line /BL falls from Vcc/2 to the low voltage Vss, thereby amplifying the potential difference between the pair of bit lines. The amplified potential difference between the pair of bit lines is transmitted as readout data to a data line (not shown). In addition, the potential difference between the pair of bit lines is latched by the sense amplifiers 11 and 12 while they are activated. Using the latched voltage Vcc of the bit line BL as data to be restored in the memory cell MC1, data "1" is restored in the memory cell MC1.
The principle of voltage amplification by the sense amplifier will be described with reference to the n-type sense amplifier 11 (nMOS transistors N1 and N2 and activating node SAN) shown in FIG. 18 for the sake of simplicity.
FIGS. 20A and 20B are views for explaining the principle of voltage amplification. FIG. 20A is a view showing a state before the sense amplifier is activated, and FIG. 20B is a view showing a state during activation of the sense amplifier.
As shown in FIG. 20A, before the n-type sense amplifier 11 is activated, the bit line BL is at a voltage of (Vcc/2)+.DELTA.V, the inverted bit line /BL is at the voltage Vcc/2, and the activating node SAN is at the potential Vcc/2.
Thereafter, as shown in FIG. 20B, the voltage of the activating node SAN decreases to Vss, and the n-type sense amplifier 11 is activated. After the voltage of the activating node SAN decreases to Vss, the voltage (corresponding to the amount of charges) of the bit line BL tends to be decreased to the low voltage Vss as BL is discharged toward Vss via the nMOS transistor N1. Similarly, the voltage (corresponding to the amount of charges) of the inverted bit line /BL tends to be decreased to the low voltage Vss as /BL is discharged toward Vss via the nMOS transistor N2. As for the nMOS transistor N2, a source S2 is at the voltage Vss, and a gate G2 is at the voltage of (Vcc/2) +.DELTA.V. As for the nMOS transistor N1, a source S1 is at the voltage Vss, and a gate G1 is at the voltage Vcc/2. In other words, a potential difference VGS between the gate and source of the nMOS transistor N2 is larger than that of the nMOS transistor N1. In this state, the nMOS transistor N2 has a higher current activating ability than that of the nMOS transistor N1. Therefore, the voltage (corresponding to the amount of charges) of the inverted bit line /BL is decreased to the low voltage Vss as /BL is discharged toward Vss via the NMOS transistor N2 prior to the voltage (corresponding to the amount of charges) of the bit line BL. The decrease in voltage of the inverted bit line /BL decreases the voltage of the gate G1 of the NMOS transistor N1. The current activating ability of the nMOS transistor N1 starts lowering. As the current activating ability of the NMOS transistor N1 lowers, the difference in current activating ability between the nMOS transistor N2 and the nMOS transistor N1 is increased more and more. As a result, the voltage of the inverted bit line /BL comes close to the low voltage Vss quickly than that of the bit line BL.
Also in the p-type sense amplifier 12, the voltage of the bit line BL comes close to the high voltage Vcc faster than that of the inverted bit line /BL in accordance with an operation principle symmetrical to that of the n-type sense amplifier 11.
When the voltage of the bit line BL reaches Vcc, and that of the inverted bit line /BL reaches Vss, charging of the bit line BL from the activating node SAP and discharging of the inverted bit line /BL to the activating node SAN stop.
The principle of voltage amplification by the sense amplifier has been described above.
In the typical sense amplifier, if the power supply voltage Vcc decreases to, e.g., 1 to 1.5V, the voltage VGS (=(Vcc/2)-Vss) across the gate and source of each of the nMOS transistors N1 and N2 decreases, resulting in lower current activating abilities of the nMOS transistors N1 and N2 than the conventional case. This delays the voltage amplification operation of the sense amplifier.
If the power supply voltage Vcc further decreases to 1V or less, the nMOS transistors N1 and N2 may not operate satisfactorily because the threshold voltages of the nMOS transistors N1 and N2 become higher than the voltage VGS across the gate and source. In this state, even if the voltage of the activating node SAN is connected to Vss, only a voltage VDS across the source and drain of each of the nMOS transistors N1 and N2 changes to (Vcc/2)+.DELTA.V or Vcc/2, so the inverted bit line /BL cannot be effectively discharged to the activating node SAN. Therefore, the voltage amplification speed of the sense amplifier further decreases.
To solve this problem, the threshold voltages of the nMOS transistors N1 and N2 suffice to be set low. In general, however, they must be 0.4 to 0.5V or more because lower threshold voltages of the nMOS transistors N1 and N2 generate a subthreshold leak current between the high voltage Vcc and the low voltage Vss in the sense amplifier made up of the n-type sense amplifier 11 and the p-type sense amplifier 12, i.e., of the CMOS circuit. Moreover, a similar subthreshold leak current is generated in a peripheral circuit using an nMOS transistor formed in the same manufacturing process as the nMOS transistors N1 and N2. As is well known, the subthreshold leak current increases the power consumption.
A sense amplifier for solving the problem caused by an ultra-low power supply voltage Vcc is reported in M. Nakamura et al. "A 29 ns 64 Mb DRAM with Hierarchical Array Architecture", ISSCC 95. In the sense amplifier reported in this reference, the activating node SAP is temporarily connected to a voltage Vcc2 higher than the memory cell data "1", i.e., the high voltage Vcc to increase the voltage VGS across the gate and source of each of the pMOS transistors P1 and P2 of a p-type sense amplifier at the start of activating the sense amplifier.
The principle of voltage amplification by this sense amplifier will be briefly described in correspondence with the sense amplifier shown in FIGS. 18 and 19.
FIG. 21 is a circuit diagram of a conventional bit line sense amplifier of a DRAM and its peripheral circuit. FIG. 22 is an operation waveform chart of the sense amplifier. The same reference numerals as in FIGS. 18 and 19 denote the same parts in FIGS. 21 and 22, and only a difference will be explained.
As shown in FIG. 21, the circuit is different from that shown in FIG. 18 in that the activating node SAP is connected via a switch SW3P to the voltage Vcc2 higher than the high voltage Vcc.
The operation will be explained below.
As shown in FIG. 22, the word line WL1 is at the low voltage Vss during the precharge period. The switches SW1N and SW1P are ON, and the switches SW2N, SW2P, and SW3P are OFF. With this setting, the activating nodes SAN and SAP are at the intermediate voltage Vcc/2.
After the precharge period, the read/write period (active period) starts. When the precharge period shifts to the read/write period, the precharge signal PRC first changes to the low voltage Vss. The switches SW1N and SW1P are turned off, and the activating nodes SAN and SAP are disconnected from the intermediate voltage Vcc/2. After that, the word line WL1 is selected, and its voltage increases to an active voltage of the word line VWLH higher than the high voltage Vcc. Data written in the storage node electrode SN1 is transferred to the bit line BL, and the voltage of the bit line BL slightly changes within the range of .+-..DELTA.V. FIG. 22 exemplifies the case wherein the voltage rises by +.DELTA.V. Upon the slight change in voltage of the bit line BL, the switch SW3P is turned on to connect the activating node SAP to the sufficiently high voltage Vcc2. At this time, the difference between the voltage Vcc/2 of the inverted bit line /BL and the voltage Vcc2 of the activating node SAP becomes more than the voltage Vcc/2. The potential difference VGS=Vcc2-(Vcc/2) between the gate and source of the PMOS transistor P1 becomes more than the threshold voltage of the PMOS transistor P1, and the p-type sense amplifier 12 starts satisfactorily amplifying the voltage. The p-type sense amplifier 12 starts charging the bit line BL to the sufficiently high voltage Vcc2 via the pMOS transistor P1 prior to the inverted bit line /BL in accordance with the principle of voltage amplification described above. Accordingly, the voltage of the bit line BL rises. By the raised voltage of the bit line BL, the potential difference between the gate and source of the nMOS transistor N2 exceeds the threshold voltage of the nMOS transistor N2. Then, the n-type sense amplifier 11 starts satisfactorily amplifying the voltage. The n-type sense amplifier 11 discharges the inverted bit line /BL to the low voltage Vss via the nMOS transistor N2 prior to the bit line BL in accordance with the principle of voltage amplification described above. After the potential difference between the pair of bit lines is satisfactorily amplified in this manner, the switch SW3P is turned off, and the switch SW2P is turned on, thereby decreasing the voltage Vcc2 of the bit line BL to the high voltage Vcc. Using the latched high voltage Vcc of the bit line BL as data to be restored in the memory cell MC1, data "1" is restored in the memory cell MC1.
In this sense amplifier, at the start of activating the sense amplifier, the activating node SAP is increased to the sufficiently high voltage Vcc2 to drive the p-type sense amplifier 12 first and to raise the voltage of the bit line BL. Using the raised voltage of the bit line BL, the n-type sense amplifier 11 is activated.
By this method, the potential difference between the pair of bit lines can be amplified by the sense amplifier even when the power supply voltage Vcc is decreased to twice or less the threshold voltage of the nMOS transistors N1 and N2.
However, in the bit line sense amplifier with an ultra-low operation voltage which can be used in a semiconductor memory wherein the p-type sense amplifier is first operated, the following technical difficulty is found: the operation margin is smaller than that of a typical sense amplifier not having three power sources for p-type sense amplifier such as shown in FIG. 21.
By the conventional semiconductor manufacturing technique, the threshold voltage in the whole chip or whole wafer varies more in the pMOS transistor whose threshold is difficult to control to be an uniform value than in the nMOS transistor.
In the sense amplifier (FIG. 21) which operates at an ultra-low voltage, the p-type sense amplifier 12 is operated prior to the n-type sense amplifier 11 in order to raise the bit line voltage. In other words, the pMOS transistor whose threshold voltage varies over a wide range performs the initial operation of voltage amplification.
During operation of the sense amplifier, the sense amplifier may erroneously operate if two, paired transistors are different in threshold voltage owing to manufacturing conditions. More specifically, as described above, according to the operation principle of the sense amplifier, the charges of the memory cell are transferred to the bit lines to amplify a small potential difference between the pair of bit lines by the difference between two activating abilities with gate electrodes connected to the bit lines. If the threshold voltage varies to be higher than the slight signal voltage, the signal cannot be accurately amplified, decreasing the operation margin. Therefore, to ensure the operation margin, the signal voltage must be sufficiently set higher than variations in threshold voltage of the transistor caused during the manufacture.
In a conventional sense amplifier which can operate at an ultra-low voltage and performs the initial operation of voltage amplification by a pMOS sense amplifier whose threshold voltage varies over a wide range, a signal voltage in the bit line must be set lower in order to ensure the same operation margin with respect to variations in power supply voltage or the use environment such as the temperature as in a sense amplifier which performs the initial operation of voltage amplification by an nMOS sense amplifier. For example, the lowest power supply voltage is set higher, or the capacitance of the cell capacitor is set larger. A high power supply voltage however contradicts the object of decreasing the operation voltage. To increase the capacitance of the cell capacitor, the semiconductor manufacturing process must be improved.


A piezoelectric acoustic transducer that can be reliably and easily connected with an external conductor without detracting from the vibration characteristics of the piezoelectric acoustic transducing element is provided. A first case member is provided with an acoustic hole continuous with an internal space. A piezoelectric acoustic transducing element is constituted by mounting a piezoelectric element on one surface of a diaphragm and is housed inside the case partitioning the internal space into two portions. Ends of terminal members are connected to the piezoelectric element inside the case, their middle portions are held between the first case member and the second case member and the portions that are beyond the middle portions are led out to the outside of the case to constitute spring pieces, which are folded upward and back over the one surface of the second case member.

1. Field of the Invention
The present invention relates to a piezoelectric acoustic transducer that may be employed in a buzzer, a telephone or the like.
2. Discussion of Background
When electrically connecting a piezoelectric acoustic transducer and an external conductor, a lead wire covered with an insulator is employed under normal circumstances, with one end of the lead wire soldered onto a piezoelectric acoustic transducing element included in the piezoelectric acoustic transducer and the other end led out to the outside of the piezoelectric acoustic transducer and soldered onto the external conductor. Such technology is disclosed in Japanese Examined Utility Model Publication No. 38558/1990, Japanese Unexamined Utility Model Publication No. 38399/1994, Japanese Unexamined Utility Model Publication No. 13900/1989, Japanese Unexamined Patent Publication No. 13800/1986, U.S. Pat. No. 4,006,371, U.S. Pat. No. 3,700,938 and the like.
As a means for dispensing with the complicated and time consuming process of soldering, Japanese Examined Utility Model Publication No. 45917/1990, Japanese Unexamined Patent Publication No. 199298/1985, U.S. Pat. No. 4,965,483 and the like disclose a technology in which a spring terminal member is employed that is electrically connected to a piezoelectric acoustic transducing element by its spring pressure, with a spring terminal led out to the outside of the piezoelectric acoustic transducer to be electrically connected to an external conductor.
However, when a spring terminal is to be employed, the following requirements must be satisfied. First, in the electrical connection between the spring terminal and the external conductor, a high degree of reliability must be assured for the connecting portion, i.e., the force with which they press against each other at the contact point portion must be great. Second, in the electrical connection with the piezoelectric acoustic transducing element, the spring terminal must not inhibit the vibration of the diaphragm, i.e., the force with which it is held against the piezoelectric acoustic transducing element at the contact point portion must not be greater than necessary.
Since these two requirements conflict with each other, it is difficult to satisfy them both and none of the prior art publications mentioned above discloses a means for satisfying these requirements.


Apparatus and methods provide a player of a massively multiplayer online role playing game (MMORPG) to participate in at least one aspect of the MMORPG while using a wireless device. The wireless device executes a mobile MMORPG client, which interfaces with the game server(s) of the MMORPG via a mobile MMORPG server. A location based gaming mode for use with the wireless device is disclosed.

Personal computers and computer-like devices, such as gaming consoles, are capable of hosting games which allow individuals and/or groups of individuals to explore and interact with a virtual environment. Examples of gaming consoles include Sony's PLAYSTATION® series of consoles and Microsoft's XBOX® series of consoles. The virtual environments presented in these games are highly detailed and typically present a gamer with a fantasy, science fiction, historical, or futuristic milieu.
Computer gaming began as a single player experience. Subsequently, multiplayer games were created allowing more than one player to play the same game at the same time, either cooperatively to achieve a common goal, as a competition against one another, or a mixture of both. Aspects of the game where players compete with or against computer controlled entities are generally known as player versus environment (hereinafter "PvE"), while aspects of the game where players compete against other players are generally known as player versus player (hereinafter "PvP"). Initially, multiplayer games were designed for multiple players to play on a single computer or computer-like device. However, as networking technology became more common, multiplayer games were designed to be played by different players each playing on their own computer or computer-like device.
As computer and computer-like devices become more powerful, and as network connectivity (including connectivity to the Internet) became more prevalent, the complexity of computer games and the number of simultaneous players increased. One genre of computer games is designed for play by a large number of simultaneous players. Such games are typically known as massively multiplayer online role playing games, or MMORPGs. These games are also sometimes known as massively multiplayer online games, or MMOs. For consistency, this document will use only the term MMORPG. Examples of MMORPGs include, for example, ULTIMA ONLINE®, EVERQUEST®, STAR WAR GALAXIES®, SHADOWBANE®, CITY OF VILLANS®, CITY OF HEROS®, FINAL FANTASY XI®, WORLD WAR II ONLINE®, EVE ONLINE®, EVERQUEST II®, WORLD OF WARCRAFT®, and DUNGEONS AND DRAGON ONLINE®.
A MMORPG permits a large number of people to share a virtual experience together by allowing the individual players to interact with each other in small and large groups. Players create alternate personas in the form of player characters. Players generally have the ability to customize their player characters' appearance, physical, and mental attributes. For example, a player can customize his character by selecting gender, facial appearance, body type, hair color/styles, skin tone, and clothing. Additionally, a character can be associated with additional attributes consistent with the theme of the MMORPG. For example, within a fantasy themed MMORPG, a player typically can choose to play a character selected from any of several races and classes. Examples of available races may include, humans, wood elves, high elves, dwarves, gnomes, dark elves, trolls, and ogres. Examples of classes may include clerics, druids, shamans, rangers, paladins, shadow knights, warriors, monks, rogues, bards, enchanters, magicians, necromancers, and wizards. Each of these choices may affect the appearance and capabilities of the player character.
By controlling their actions, players can cause their player characters to interact with other player characters and computer generated non-player characters in a computer generated virtual (or game) world. These actions may affect the status of the players characters and/or the environment of the game world, and thus further affect the appearance and/or capabilities of the player characters. Most MMORPGs permit multiple avenues for advancement of player characters. These may include defeating enemies in combat, performing quests (quests are discussed in greater detail in relationship to FIG. 6, below), exploration, or engaging in artisan activities. In many MMORPGs, successfully completing an activity which provides for advancement is rewarded by an award of experience points. Player characters may be organized into a series of increasingly powerful levels, with each increasing experience level requiring an increased accumulation of experience points. Higher level characters may fight with greater skill, tolerate a greater degree of damage before being defeated, have a wider range of abilities, or be capable of casting more powerful spells.
Further, while many MMORPGs permit player characters to advance by engaging in solo activities within the game world, the core of many MMORPGs is social interaction between the various players. Accordingly, MMORPGs generally permit player characters to form groups and for those groups to work together at a common goal. In order to facilitate group formation, many MMORPGs may include in-game features to facilitate group formation. For example, player characters can be visibly flagged by their players as "looking for a group" (hereinafter "LFG"). Alternatively, the game world may provide predetermined locations for player characters who are looking for a group to gather.
FIG. 1 illustrates a system 100 for playing a MMORPG. Players 110a each install computer programs known as the game client 120a, 120b on their respective computers 130a or computer-like devices 130b. These devices 130a, 130b connect, via a network 140, which may be the Internet, to a game system 150. While there are various business models for recouping the costs of developing a MMORPG and operating the game system 150, players 110a are typically charged a fixed amount to purchase the game client software 120a, 120b and then pay a monthly fee for access to the game system.
The game system 150 includes at least one game server 151 for maintaining the state of the game world. Except for scheduled downtime to perform upgrades and administrative tasks, the server 151 is generally operated continuously, resulting in a game world which is persistent. Further, in order to avoid overcrowding of the virtual world, most MMORPGs support multiple shards (also known as instances) of the virtual world. Each shard generally shares a same basic design, but are generally populated by different sets of player characters. Thus, while each shard begins with a common set of initial states, the difference in actions taken by the player characters of each shard will cause each shard to have its own unique state. Alternatively, some shards may be operated using alternate rules of play, and thus may start with a different state than the common state. For example, in a game where most shards are operated in a predominately PvE mode, some shards may be operated to permit a greater range of PvP activities.
Typically, each shard is supported by its own hardware. For example, each shard may be supported by its own game server 151. Generally, administrative mechanism are built into the game system 150 to support moving characters between shards, thereby permitting expanding the number of game servers 151 when the MMORPG is increasing in number of players and contracting the number of game servers 151 when the MMORPG is decreasing in number of players.
The game system 150 may include other servers aside from one or more game servers 151. For example, most MMORPGs utilize at least one authentication server 152 for authenticating player log-ins to the game system 150. Most MMORPGs provide chat and/or message board services to its players. Such services may be provided by one or more messaging servers 153. Preferably, messaging servers 153 provide the chat and message board services via a web based interface. Further, most MMORPGs bill players a subscription fee for accessing the server. Billing services may be provided by one or more billing servers 154. Preferably, the billing servers 154 also provide a web based interface for players to enter and edit their contact and billing information.
Also shown in FIG. 1 is a game master 111. The operation of any MMORPG generally requires a number of game masters. Each game master 111 is a customer service agent for the entity which runs the game system 150. Their role in the MMORPG may be to address customer issues. Such issues may include a character which is stuck in the virtual world due to a bug in the MMORPG, arbitrating a dispute between multiple players 110a, or managing special events, such as holiday related events.
As previously noted, the game system 150 maintains the game world in a persistent state. Thus, a player can reasonably expect that even when the player is logged-out of the MMORPG, other players are playing the MMORPG and thus, changing the state of the virtual world. Typically, a player can log-out of the MMORPG under certain predetermined conditions (e.g., the player's character is not engaged in combat, or the player's character is located in a safe location within the virtual world). When the player logs-out of the MMORPG, the state of the player's character is saved by the server and then the player's character is removed (i.e., vanishes from the perspective of other characters) from the virtual world. Conversely, when the player logs-in to the MMORPG, the state of the player's character is restored and the player's character is inserted (i.e., appears from the perspective of other characters) into the game world at the same location as when the player logged out of the MMORPG. In FIG. 1, players 110a represent players which are logged-in to the MMORPG, and therefore have characters which appear in the virtual world, while players 110b represent players which have logged-out the MMORPG, and therefore do not have characters which appear in the virtual world.
Many of the players 110b who are logged-off the MMORPG would like to be able to further participate in the affairs of the virtual world supported by the MMORPG. Such players 110b may not have access to a computer 130a or computer-like devices 130b to run the regular game client 120a, 120b. Although such players 110b may have mobile devices, generally, it is impractical to run a version of the standard game client 120a, 120b on the mobile device. This partially due to the enormous amount of data processed by the client 120a, 120b present the virtual world. For example, the game client for the WORLD OF WARCRAFT® requires four gigabytes of memory. Accordingly, there is a need and desire for methods and apparatus to permit a player of the MMORPG to have increased interactions with the MMORPG.

System and method for managing virtual worlds mapped to real locations in a mobile-enabled massively multiplayer online role playing game (MMORPG)


An extract-transform-load (ETL) platform fetches consistent datasets in a batch for a given period of time and provides the ability to rollback that batch. The batch may be fetched for an interval of time, and the ETL platform may fetch new or changed data from different cloud/on-premise applications. It will store this data in the cloud or on-premise to build data history. As the ETL platform fetches new data, the system will not overwrite existing data, but rather will create new versions so that change history is preserved. For any reason, if businesses would like to rollback data, they could rollback to any previous batch.

Businesses must process large amounts of data to make strategic decisions and be successful. The data is often provided in formats such as reports. To build a meaningful report, businesses are relying on multi-tenanted software as a service (SAAS) analytic companies. Building and providing meaningful analytics typically require a large amount of resources and have a high cost.
In order to reduce cost, more and more businesses are adapting to cloud based SAAS application models. For example, businesses may store sales data in "Salesforce" applications, accounting data in "NetSuite" applications, and billing data in "Zuora" applications. It is important to have detailed information about a company's performance and positions. Unfortunately, analytic applications do not consolidate data from different SAAS applications and provide a single view. Analytic applications also do not provide data consistency within data collection of different data types. What is needed is an improved analytics system that improves upon the analytic systems of the prior art.

Data consistency and rollback for cloud analytics


A signage display apparatus 6 is provided for use on a kiosk or automated teller machine 8 for displaying information concerning a service offered by the provider of the drive-through or teller machine services. The apparatus includes a base 18, a pair of opposed, upstanding panels 20 that are sealed together along the side edges thereof, and an elongated hood 22 received over top edges of the panels. A gasket 32 is sandwiched between the hood and the top edges of the panels to seal them against the passage of moisture between the top edges of the panels. The base 18 is secured to the kiosk or teller machine 8 within the line of sight of users such that the apparatus displays information concerning a service offered by the service provider to anyone making a transaction. In addition, the method of the disclosure includes the additional steps of permitting the user to make a request for additional information concerning the service about which information is displayed, and providing the additional information to the user, either through the kiosk or automated teller machine, or as a follow-up to the user's request.

The present invention relates generally to a signage display apparatus for use on a kiosk, an automated teller machine, or the like, and to a method of displaying and disseminating information in conjunction with such machines.
The use of drive-through kiosks by banks is becoming increasingly popular, accounting for a greater and greater percentage of the total business transactions performed by such institutions. Typically, several kiosks are constructed side-by-side next to a banking facility manned by one or more tellers so that customers can drive up to one of the kiosks and conduct a transaction. Each kiosk is typically provided with a microphone and speaker to enable the customer and teller to communicate with one another, as well as a pneumatic transfer assembly for allowing documents and money to be transferred to and from the kiosk by the teller.
A conventional automated teller machine includes a display screen or the like, a card reader input device, a printer, and at least one additional input device such as a keyboard, microphone, bar code reader or the like. Banks are common owners of automated teller machines, and use the machines to permit customers to access their accounts and conduct banking business at times convenient to the customer, and without requiring them to park their cars and walk into the bank to a teller window.
Typically, when a customer wants to use an automated teller machine at a bank, he or she first inserts a data-bearing card into the card reader input device of the machine, and enters a personal identification number or PIN into the keypad. Thereafter, the customer is empowered to input requests for any of the various services offered through the machine, such as making a deposit or withdrawal, or checking his or her account balance. Depending upon which request is made, a series of options are presented to the customer, and responses are made by inputting information into the keypad or microphone of the machine until the service is completed, whereupon the customer's card is returned.
Although it is common for banks to display information about their various services on signage or the like inside the lobby of the bank, no such vehicle is used to provide similar information to customers who use the drive-through or automated machines without entering the bank itself. For example, information concerning car loan or mortgage rates, or information concerning other various financial products is typically advertised on such signage, and brochures and other literature are made available at the teller windows for anyone requesting such additional information.
In light of the absence of a vehicle for presenting similar information to users of drive-through and automated teller machines, it would be advantageous to provide an apparatus and method for displaying such information and for disseminating such additional information to customers who express an interest in these advertised services.

Method and apparatus for displaying information


A dynamic pulse width modulation (PWM) amplifier comprising an input terminal, a dynamic PWM controller, a power stage, a low pass filter, and an output terminal. The input terminal receives an input signal. The dynamic PWM controller transforms the N-bit input signal sampled by a sampling frequency to a 1-bit PWM signal. The power stage receives and outputs the 1-bit PWM signal. The low pass filter receives and outputs the 1-bit PWM signal. The 1-bit PWM signal is used to drive the power stage and the low pass filter. The output terminal outputs the 1-bit PWM signal. The dynamic PWM amplifier is characterized in the dynamic PWM amplifier uses a register array to store the input signal processed immediately in each frame, regroups the input signal, and outputs the regroup signal, so that the 1-bit PWM signal is changed according to the input signal.

1. Field of the Invention
The present invention relates to a dynamic pulse width modulation (PWM) amplifier, and in particular relates to a dynamic PWM controller.
2. Description of the Related Art
Generally, power amplifiers are divided into four classes: A, B, AB, and C. A class-A amplifier has an output transistor, the operating point of which is in the center of the linear region. The current obtained by the class-A amplifier from a voltage source is constant and does not vary with the level of an input signal. Because the amplitude of an output signal is changed continuously when the class-A amplifier is used to amplify an audio frequency, the class-A amplifier has low efficiency of not more than 25% in practice. Amplification by the class-A amplifier can be performed by a signal-transistor or a pull-push circuit. The class-A amplifier has no crossover distortion and no switching distortion, and the harmonic mainly comprises an even harmonic. The tone quality is thick at a low pitch, smooth at a median, and clear at a high pitch. The class-A amplifier is not popularly used to amplify power due to the large power consumption, low efficiency, easy heating, and greater heat dissipation requirement. Moreover, components within the class-A amplifier have low reliability and short life when they operate with in high current and high temperature over a long period of time, and the class-A amplifier has high cost. Thus, class-A amplifiers are no longer produced. A simple class-A amplifier has only one active component, such as a transistor. Because a bias voltage current is applied to the transistor, it is not completely turned on or off. The non-turned on/off region is referred to as a linear region. An amplifier which operates in the linear region has low distortion, but low efficiency.
A class-B amplifier has a bias voltage circuit, so that pull-push transistors within the class-B amplifier have low current when there is no any driving signal. When a driving signal is provided, the current of one of the two transistors is increased and the other is turned off in the first half period. In the second half period, the operations of the two transistors are exchanged. Because the two transistors operate alternately, a pull-push circuit is required to completely amplify the wave form of signals. The class-B amplifier has high efficiency with efficiency of 78% being the highest in theory. The class-B amplifier, however, has large distortion. The class-B amplifier comprises two transistors which pull and push each other, one outputs current and the other receives current. When a sine wave which is symmetrical with respect to the zero point is to be amplified, one of the transistors is used to amplify the upper half portion of the sine wave, and the other is used to amplify the lower half portion thereof. The two transistors operate alternately to accomplish the amplification operations. The class-B amplifier thus has higher efficiency than a class-A amplifier. However, some undesired problems of the class-B amplifier occu in a non-linear region wherein the sine wave only passes through the zero point. In the non-linear region, one of the two transistors is only just turned on, and the other is only just turned off. Since the transistors require a short transition period to turn on, singles are distorted in the non-linear region.
A class-AB amplifier serves as a class-A amplifier when the level of its driving signal is lower, and it transfers to serve as a class-B amplifier when the level of its driving signal becomes higher. The efficiency of the class-AB amplifier is higher than the class-A amplifier when a small signal serves as an input signal. In the class-AB amplifier, the efficiency is increased as the output power increases. Although there is more distortion in the class-AB amplifier than in the class-A amplifier, the class-AB amplifier is still used, wherein a class-AB of high bias current is popularly used to reduce the distortion of a low level signal. In the configuration of the class-AB amplifier, the class-AB amplifier is composed of a class-A amplifier and a class-B amplifier. The configuration is similar to class-B amplifier, and a circuit which provides small bias current to each transistor is further applied in the class-AB amplifier, so that each transistor is not completely turned off. The class-AB amplifier with high bias current has large power consumption as the class-A amplifier, but it has lesser distortion than class-A amplifier. The class-AB amplifier requires two transistors as the class-B amplifier. The performance of the class-AB amplifier is thus better.
A class-C amplifier has an active component which is turned on in a duration of a small portion of an input signal. The class-C amplifier thus requires a tuned circuit to return the other portions of the input signal by the flywheel effect of the tuned circuit. The class-C amplifier has great distortion, the power of the collector of the class-C amplifier is, however, the greatest. The class-C amplifier is thus used in frequency multiplication circuits or stages of power amplifying. In practice, the oscillation frequency of the class-C amplifier is usually limited by a quartz oscillator with a single output frequency. To raise output frequency, a frequency multiplier is applied to vary the shifting value of the oscillation frequency or FM signal frequency in an integer multiple. The frequency multiplier outputs signal frequency to a non-linear circuit and then obtains required the high-order harmonic from the distorted output wave using a high-multiple resonance frequency set by a resonance circuit. In general, class-C amplifiers with the characteristic of non-linear and resonance circuits operate in coordination to serve as frequency multiplication circuits.

Dynamic pulse width modulation amplifiers


A method for transmitting variable length packets based on FEC coding. Data packets are successively and contiguously stored in a two-dimensional storage device. FEC coding is performed to generate parity packets. The parity packets are stored in the two-dimensional storage device. The data packets, offsets representing positions of the data packets in the two-dimensional storage device, types of packets, and the parity packets are then transmitted.

(a) Field of the Invention
The present invention relates to a method for transmitting and receiving variable length packets on the basis of the FEC coding. More specifically, the present invention relates to a method for transmitting and receiving variable length packets on the basis of the FEC coding for generating parity packets of the variable length packets without padding to recover lost packets, and enabling a transmitter to immediately transmit data packets.
(b) Description of the Related Art
Digital communication systems use the ARQ (automatic repeat request) method or the FEC (forward error correction) method so that a receiver may control packet losses generated at a channel during data transmission.
The ARQ method includes a stage for analyzing whether received data blocks have errors or are lost, and a stage for requesting retransmission of blocks that have errors or are lost. The ARQ method is not suitable for a system that has many errors and is strict with delay.
The FEC method transmits data with additional data so that the receiver may detect errors and recover data without retransmission of the error data. The FEC method includes the Hamming code, the BCH code, and the RS (Reed Solomon) code. In particular, the RS code allows per-byte error detection and correction.
In the IETF document "An RTP Payload Format for Generic Forward Error Correction" (IETF(Internet Engineering Task Force) RFC(Request For Comment Document) 2733, December 1999) proposed by J. Rosenberg et al., exclusive-or calculation is used.
A single parity packet for each set of packets is transmitted in a separate stream. When a packet is lost from the corresponding set, it can be restored by a receiver. In order to be compatible with a host that does not support the FEC method, the parity packet has a predetermined RTP (Real-time Transport Protocol) payload type value. The host that does not know the RTP payload type value ignores a received parity packet and executes the original process according to a previous IETF document of "RTP: A Transport Protocol for Real-Time Application" (IETF RFC 1889, January 1996) by H. Schulzrine.
Also, according to "An Improved UDP Protocol for Video Transmission Over Internet-to Wireless Networks" (IEEE Tr. On Multimedia, pp. 356-365, September 2001) by H. Zheng, and "An Adaptive Redundancy Control Method for Erasure-Code Based Real-Time Data Transmission Over the Internet" (IEEE Tr. On Multimedia, pp. 366-374, September 2001) shortened RS codes are used for restoring erased packets. When k data packets are transmitted together with (n-k) parity packets, even if (n-k) packets are lost to the maximum, they may be restored by the receiver. Serial numbers of the lost packets can be detected by the receiver using an RTP protocol. (The term erasure is defined to be loss or an error at a known position.) The above-noted method has more packet loss protection than RFC 2733 since more than one packet may be restored by using the method. The method for restoring at least one packet proposed by Wagner is currently under the process of standardization by the IETF ("draft-ietf-avt-uxp-02.txt: An RTP payload format for erasure-resilient transmission of progressive multimedia streams," March 2002).
The above methods are applied on the assumption that the length of the packets is fixed. The length of the packets of compressed audio is fixed, and the length of the packets of compressed video is variable in most cases as shown in FIG. 10.
Accordingly, when the length of packets to be transmitted is variable and much delay is not allowed in the like manner of recent Internet video services, it is required to use the FEC method and modify it to be suitable for streams of variable length packets.
Because the conventional FEC coding methods are based on the same length packets, the methods have a weak point that a padding process is required to obtain the same length packets as shown in FIG. 6. Also, since the length of the parity packets would be the same as the longest length of the packets in an associated packet group, a bandwidth is wasted. And since a transmitter does not transmit input packets until the associated packet group including the first packet through the sixth packet is input so as to detect the packet of the longest length, delay is problematically generated.

Method for transmitting and receiving variable length packets based on forward error correction (FEC) coding

Electronics and Telecommunications Research Institute


Provided is an LED element which achieves high light extraction efficiency even at low operating voltages and which can be produced using a simple process. The LED element has a first semiconductor layer made of a p-type nitride semiconductor, a light-emitting layer made of a nitride semiconductor formed on the upper layer of the first semiconductor layer, a second semiconductor layer made of an n-type nitride semiconductor formed on the upper layer of the light-emitting layer, and a transparent electrode formed on the whole surface of the second semiconductor layer. The second semiconductor layer in at least a region that is in contact with the transparent electrode is made of AlnGa1-nN (0<n<1) and has an n-type impurity concentration larger than 1×1019/cm3.

Conventionally, in an LED made of a nitride semiconductor, GaN is mainly used. In this case, from the viewpoint of lattice matching, a GaN film having few defects is formed on a sapphire substrate by epitaxial growth, so as to form an LED element made of a nitride semiconductor. Here, the sapphire substrate is an insulating material, so that, for the purpose of supplying electric power to a GaN-based LED, the n-layer is exposed by cutting a part of the p-layer to form an electrode for power supply on each of the p-layer and the n-layer. The LED having a structure such that the electrodes for power supply are arranged in the same direction is referred to as a lateral-type structure, and such a technique is disclosed, for example, in the following Patent Document 1.
On the other hand, for the purpose of improving the light emission efficiency and achieving more efficient light extraction of the LED element, development of an LED having the so-called longitudinal-type structure in which the p-layer and the n-layer are arranged on the front and back surfaces to provide power supply is advanced. In producing an LED having this longitudinal-type structure, the n-layer and the p-layer are arranged on the sapphire substrate sequentially from below and, after a support substrate made of silicon (Si) or copper tungsten (CuW) is bonded to the p-layer side, the sapphire substrate is removed. In this case, the element surface will be the n-layer side, and the voltage supply is carried out by disposing a power supply terminal on this n-layer and connecting a wire, which is a power supply line, to this power supply terminal.
In the longitudinal-type structure, when a voltage is applied between an electrode on the p-layer side (hereafter referred to as "p-side electrode") and a bonding electrode formed on the n-layer (hereafter referred to as "n-side electrode"), a current flows from the p-side electrode to the n-side electrode via the LED layer including the light-emitting layer. By the flow of the current in the light-emitting layer, a region of the light-emitting layer emits light.
Here, the p-side electrode and the n-side electrode are arranged in a positional relationship of opposing each other in a vertical direction. For this reason, when a voltage is applied between the two electrodes, a current path in the vertical direction of travelling almost by the shortest distance from the p-side electrode towards the n-side electrode is formed. In this case, almost all of the current flows in a part of the light-emitting layer located vertically under the n-side electrode, and little current flows in other parts of the light-emitting layer, thereby causing a problem in that the light-emitting region is restricted to lower the light emission efficiency.
In view of such a problem, the following Patent Document 2 discloses a construction in which the n-side electrodes are disposed in a network configuration. By disposing the n-side electrodes in a network configuration, the current flowing in the light-emitting layer can be widened in a horizontal direction while ensuring the light extraction region.
Also, when the resistance value between the LED layer and the n-side electrode is high, another problem is caused such that the voltage needed for allowing the current needed for light emission to flow is high. For this reason, in order to extract light of a high light quantity with a low operating voltage, it is important that the resistance value between the LED layer and the n-side electrode is reduced as much as possible. In view of such a problem, the following Patent Document 3 discloses an LED element in which the n-layer in the LED layer is formed by sequential lamination of a high-concentration layer and a low-concentration layer.

LED element, and production method therefor


A distributor and a fuel cell module including the distributor are disclosed. The distributor is for supplying a fuel or oxidant from a supply tube to a plurality of distribution portions. The distributor includes a buffer portion and a guide portion. The buffer portion has a center for receiving the fuel or oxidant from the supply tube, and a buffer surface extending away from the center. The guide portion defines a first space with a periphery of the buffer portion. The guide portion is radially connected to the plurality of distribution portions about a center axis of the distributor.

1. Field
The following description relates to a distributor and a fuel cell module having the same.
2. Description of Related Art
A fuel cell may be classified into several types depending on the type of electrolyte used. Because of the variety of output ranges and usages among the different fuel cell types, the appropriate fuel cell may be selected based on its intended purpose.
Among the different fuel cell types, the solid oxide fuel cell functions well as a distributed power generator in both a commercial and a residential setting. In a solid oxide fuel cell, control of the electrolyte position is easy. In addition, the position of the electrolyte is fixed and thus, there is little or no risk of electrolyte depletion. Further, the strong anti-corrosiveness of the electrolyte provides for a long lifetime of the material.
The voltage or capacity of a single unit cell in the fuel cell is typically not high enough for the actual usage needed. Accordingly, a fuel cell stack having a specific voltage and a specific capacity is designed by connecting a plurality of unit cell in series or in parallel to implement the necessary real life voltage or capacity.
Further, a fuel cell module is used to connect a plurality of fuel cell stacks in a high-capacity configuration. The design of an efficient distributor capable of using space efficiently while uniformly distributing fuel or oxidant to each stack becomes an important issue in terms of efficiency of the entire fuel cell system.

Distributor and fuel cell module having the same


The invention relates to a multilayer printed circuit board structure comprising a stack of plurality of electrically insulating and/or electroconductive layers and at least one passive or active electrical component arranged inside the stack of layers, the component extending laterally only in part of the surface extension of the stack of layers. The invention also relates to a passive or active electrical component mounted on the stack, to an associated wiring, and to a corresponding production method. According to the invention, the insert is embedded between two electrically insulating liquid resin layers or prepreg layers extending over the entire surface and covering the insert on both sides, the insert being surrounded by a resin material that is liquefied by compression or lamination of the structure. The invention structure can be used in printed circuit board technology.

Multilayer printed circuit board structures comprising a layer stack made from a number of layers that are electrically insulating and/or provided with conductor track structures and at least one passive or active electrical component in the interior of the layer stack have recently gained more and more in significance for integrating passive electrical components such as capacitors and resistors, and/or active electrical components such as semiconductor chips, in the interior of a printed circuit board of the so-called multilayer type. The multilayer structure comprises a layer stack made from a number of electrically insulating or dielectric layers lying one above another, for example made from a prepreg resin material, with interposed electrical conductor structure planes that include suitable substrates with applied conductor track structures. The layer stack is completed, for example, by lamination or pressing with the use of dielectric prepreg layers, at least some of the layers laid one above another being provided on one or both sides with an electrically conducting layer that is structured into a desired electrical conductor pattern before the layers are laid one above another to form the layer stack. To this end, use is frequently made of an epoxy resin as substrate material with a copper cladding for so-called inner plies, that is to say layers located in the interior of the layer stack and provided with conductor track structures. In order to structure the so-called outer plies, that is to say the external layers provided with conductor track structures, a copper foil is mostly laid onto a dielectric prepreg layer and is firmly connected to the prepreg layer by the pressing operation.
In order to integrate an active and/or passive electrical component into a printed circuit board in such a way, it is known to fix such a component in a region free of conductor tracks on an electrically insulating base layer provided with conductor tracks, before one or more further layers are then applied to complete the layer stack, and the overall structure is laminated together and pressed. It is customary in this case for there to adjoin the base layer carrying the component a next dielectric layer that is of full-area design or is provided in the region of the electrical component with a window or cutout region. In the present context, a window is understood as an opening completely penetrating the relevant layer, whereas a cutout is understood as a recess formed on one side only in the relevant layer at a depth smaller than the layer thickness. Terminal contact pads of the electrical component are contact-connected to conductor structures on the base layer, or to conductor structures in other planes of the layer stack with the aid of vias, which are also to be understood for the sake of simplicity in the present context as blind hole contacts that end on the contact pads. Alternatively, the electrical component is fixed on the base layer in an electrical contacting region thereof and electrically connected directly to conductor structures there. Multilayer printed circuit board structures of these various types are described, for example, in laid-open patent application DE 196 27 543 A1, patent EP 1 230 680 B1 and the journal article W. Bauer and S. Purger, Integration aktiver und passiver Bauelemente in die Leiterplatte—Alles inklusive—[Integration of active and passive components in the printed circuit board—including all—], EPP November 2003, page 48.
German laid-open patent application DE 31 25 518 A1 describes a thin wiring arrangement for connecting electrical components to an external circuit that comprises a substrate for holding the electrical component, a first insulating layer, arranged on the substrate and made from an organic material, a wiring that is constructed on the first insulating layer and is connected to the electrical component, a second insulating layer, arranged on the first insulating layer and made from an organic material, and terminals, arranged on the first insulating layer, which lie exposed in the second insulating layer and are connected to the wiring. The substrate used is a metallic or ceramic substrate having a cutout in which the electrical component is held. The wiring constructed on the first insulating layer makes contact with terminals provided on the top side of the electrical component. In an embodiment described with reference to U.S. Pat. No. 3,763,404, the wiring for the component is formed on a top side of a flexible wiring substrate that is provided with a window region for making contact with the electrical component arranged underneath the level of the wiring substrate, that is to say terminal structures of the wiring are guided through the window region to the top-side terminal pads of the component. This contacting of the component is simultaneously used for mechanical preassembly of the component on the wiring, that is to say wiring substrate, wiring and component are, for example, prefabricated by means of a continuous tape band process.
Patent DE 690 31 350 T2 discloses an electronic multilayer package having a multilayer ceramic substrate that consists of a multiplicity of insulating and signal/reference voltage layers lying one above another, and which includes on its top side one or more cutouts for holding one or more semiconductor chips arranged next to one another. The chip(s) located in the respective cutout is/are seated there on a binder layer that is formed on the bottom of the cutout and, for example, is formed from a eutectic gold alloy or an epoxy or polyimide material. In the case of a number of chips that are to be placed in a cutout, these form part of a chip structure that is introduced into the cutout and additionally includes above the chips intermediate and innerchip wiring planes that consist of multiple line/metal interconnections and insulating plies interposed therebetween. A multilayer thin film structure made from a multiplicity of insulating layers and metallization layers is applied to the substrate top side provided with the chip(s) introduced, the metallization layers being electrically connected by vias to top-side terminal pads of the respective chip or to the intermediate and innerchip wiring planes of the chip structure.
U.S. Pat. No. 5,401,688 discloses a multilayer printed circuit board structure comprising a layer stack made from a number of layers provided with conductor track structures and in which at least one semiconductor chip is embedded between two of these layers. In the lamination process of the multiply multilayer printed circuit board structure, electrical contact is made between bump terminal pads of the chip and conductor structures of the neighboring layer that are aligned therewith.

Multilayer printed circuit board structure comprising an integrated electrical component, and production method therefor


Methods and devices for “shaping” a slope of the phase component of OFDM data symbols in order to decrease an accumulation of phase error are provided. By way of example, a method includes receiving an incoming data signal via a processor of a transmitter. The method further includes computing one or more roots of a first function representing a phase component of the data signal, computing a second function representing the phase component based on the one or more roots, deriving a periodicity of the phase component based on the second function, and deriving a value of a slope of the phase component based at least in part on the periodicity of the phase component to reduce or eliminate an error of the phase component.

The present disclosure relates generally to polar transmitters, and more particularly, to polar transmitters included within electronic devices.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Transmitters and receivers are commonly included in various electronic devices, and particularly, portable electronic devices such as, for example, phones (e.g., mobile and cellular phones, cordless phones, personal assistance devices), computers (e.g., laptops, tablet computers), internet connectivity routers (e.g., Wi-Fi routers or modems), radios, televisions, or any of various other stationary or handheld devices. One type of transmitter, known as a wireless transmitter, may be used to generate a wireless signal to be transmitted by way of an antenna coupled to the transmitter. Specifically, the wireless transmitter is generally used to wirelessly communicate data over a network channel or other medium (e.g., air) to one or more receiving devices.
The wireless transmitters may generally include subcomponents such as, for example, an oscillator, a modulator, one or more filters, and a power amplifier. Furthermore certain data modulation techniques that may be implemented by wireless transmitters may include a modulation of in-phase (I)/quadrature (Q) time samples of a signal into amplitude and phase signals. However, because certain wireless transmitters may also utilize phase information to modulate the frequency of one or more oscillators included within the wireless transmitters, the output signal, and, by extension, the information to be transmitted may become distorted. It may be useful to provide more advanced and improved wireless transmitters.

Devices and methods for orthogonal frequency division multiplexing signal phase shaping


The disclosure relates to a packaging machine comprising a liftable and lowerable tool, wherein a first lift drive, implemented as a spindle drive with a spindle and a spindle nut, and a second lift drive are provided for moving the tool in a vertical direction. The disclosure is characterized in that, by means of the second lift drive, a tool guide is movable in a vertical direction, and that, at a raised position of the tool guide, the tool can be put down on the tool guide by means of the spindle drive.

Such a packaging machine is described e.g., in DE 10 2008 032 306 A1. More specifically, this packaging machine is a tray sealer for use in comparatively small shops or catering establishments, in which trays have to be closed occasionally and individually. In order to allow a more flexible use of such packaging machines, DE 10 2008 032 306 A1 already discloses a possibility of changing the sealing and cutting tools. To this end, a spindle drive used for vertically moving the tool is moved so far that the spindle is brought out of engagement with the spindle nut. The whole tool assembly can now be tilted forwards until it strikes against a stop. When a cover panel of the packaging machine is opened, the whole tool assembly can be removed and replaced by another tool assembly.
This conventional packaging machine is disadvantageous insofar as a certain amount of skill on the part of the operator is still necessary for carrying out the exchange of tools as smoothly as possible.

Packaging machine with a liftable and lowerable tool

MULTIVAC SEPP HAGGENMUELLER GMBH & CO. KG


In one embodiment, a method comprises a wireless detector in a lighting element detecting a movable object within a prescribed detection zone of the wireless detector; and the lighting element sending a message identifying detection of the movable object to a remote gateway, allowing the remote gateway to locate the movable object.

This section describes approaches that could be employed, but are not necessarily approaches that have been previously conceived or employed. Hence, unless explicitly specified otherwise, any approaches described in this section are not prior art to the claims in this application, and any approaches described in this section are not admitted to be prior art by inclusion in this section.
Location of network-enabled devices has been limited generally by the ability to provide overlapping coverage areas by multiple transceivers within a prescribed geographical region while minimizing interference between the transceivers. Hence, the location of a network-enabled device is determined by its connection with a corresponding one of the wireless transceivers, for example a cellphone tower, a wireless mobile router, or an identified wireless access point.

Network-enabled light fixture for locating movable object


Disclosed herein is a variable length packet switching system. The variable length packet switching system includes at least two switching means, a plurality of multiplexing units and a plurality of demultiplexing units. The switching means switch ATM cells or variable length packet data in parallel. The multiplexing means are arranged upstream of the switching means for multiplexing data inputted from a line card to the switching means in packet units and dividing a packet into packets of a number corresponding to the number of the switching means. The demultiplexing means are arranged downstream of the switching means for combining packets inputted after being switched in parallel by the at least two switching means and outputting the combined packet converted into a format adequate to the line card.

1. Field of the Invention
The present invention relates generally to a variable length packet switching system having a plurality of ports, and more particularly to a variable length packet switching system, in which a plurality of chips for dividing data into units of a predetermined length including overheads are employed in parallel to perform switching, and multiplexing/demultiplexing, buffering and format conversion are carried out by the port upstream/downstream of the chips, thereby allowing high-speed switching to be performed in a non-blocking manner without the intervention of software, and enabling the expansion of its capacity by the accommodation of various signals.
2. Description of the Prior Art
In a conventional packet switching system, a switch chip such as the MASCON developed by the Electronics and Telecommunications Research Institute (ETRI) has sixteen 8-bit input/output ports. In order to switch the sixteen 16-bit ports using the MASCON chip, two MASCON chips are arranged in parallel and 16-bit input/output data are switched by the two MASCON while being divided into upper and lower 8-bit data. Such a conventional switching system is provided with a 16-bit backplane, there is a disadvantage that the number of signals is increased. The current technology can provide a 10 Gbps switching system that is operated at 50 MHz and switches 16 ports with 16 bits. Additionally, in accordance with the technology, a 32-bit backplane is provided and 4 MASCON chips are used for each byte, so a switching system can be operated at 50 MHz while doubling the port speed of a switching board, e.g., up to 1.25 Gbps. However, the conventional switching system cannot perform switching for more than 32 ports. Additionally, there is a problem that the conventional switching system can be used only for ATM cells.


A sense amplifier having a sampling circuit to sample the amplifier input signal; a reference node storing a reference signal corresponding to the input signal; and a timing circuit activating the sampling circuit for a predetermined interval, and admitting the reference signal to the reference node. The sense amplifier also can include a pump capacitor substantially maintaining a value of the reference signal; and a gain circuit coupled with the reference node and disposed to adaptively adjust gain of an output signal produced by the sense amplifier. The sense amplifier can be a single-ended sense amplifier.

1. Field of the Invention
The present invention relates to memory devices, in particular, semiconductor memory devices, and most particularly, scalable, power-efficient semiconductor memory devices.
2. Background of the Art
Memory structures have become integral parts of modern VLSI systems, including digital signal processing systems. Although it typically is desirable to incorporate as many memory cells as possible into a given area, memory cell density is usually constrained by other design factors such as layout efficiency, performance, power requirements, and noise sensitivity.
In view of the trends toward compact, high-performance, high-bandwidth integrated computer networks, portable computing, and mobile communications, the aforementioned constraints can impose severe limitations upon memory structure designs, which traditional memory system and subcomponent implementations may fail to obviate.
One type of basic storage element is the static random access memory (SRAM), which can retain its memory state without the need for refreshing as long as power is applied to the cell. In an SRAM device, the memory state II usually stored as a voltage differential within a bistable functional element, such as an inverter loop. A SRAM cell is more complex than a counterpart dynamic RAM (DRAM) cell, requiring a greater number of constituent elements, preferably transistors. Accordingly, SRAM devices commonly consume more power and dissipate more heat than a DRAM of comparable memory density, thus efficient; lower-power SRAM device designs are particularly suitable for VLSI systems having need for high-density SRAM components, providing those memory components observe the often strict overall design constraints of the particular VLSI system. Furthermore, the SRAM subsystems of many VLSI systems frequently are integrated relative to particular design implementations, with specific adaptions of the SRAM subsystem limiting, or even precluding, the scalability of the SRAM subsystem design. As a result SRAM memory subsystem designs, even those considered to be xe2x80x9cscalablexe2x80x9d, often fail to meet design limitations once these memory subsystem designs are scaled-up for use in a VLSI system with need for a greater memory cell population and/or density.
There is a need for an efficient, scalable, high-performance, low-power memory structure that allows a system designer to create a SRAM memory subsystem that satisfies strict constraints for device area, power, performance, noise sensitivity, and the like.
The present invention satisfies the above needs by providing a sense amplifier having a sampling circuit to sample the amplifier input signal; a reference node storing a reference signal corresponding to the input signal; and a timing circuit activating the sampling circuit for a predetermined interval, and admitting the reference signal to the reference node. The sense amplifier also can include a pump capacitor substantially maintaining a value of the reference signal; and a gain circuit coupled with the reference node and disposed to adaptively adjust gain of an output signal produced by the sense amplifier. The sense amplifier can be a single-ended sense amplifier.

Single-ended sense amplifier with sample-and-hold reference


A drug delivery apparatus and method for delivering a drug locally to internal body tissue. The invention contemplates positioning a drug delivery device in a body passageway or within body tissue and then selectively introducing a selected drug so that it is transported across a drug transport wall of the device for direct contact with the passageway wall or body tissue. A further aspect of the present invention involves treating a dilated vessel in the area of a stenotic lesion with a fixative or other drug to render the vessel biologically inert and to form a biological stent or prevent restenosis using specifically selected drugs. A still further aspect of the present invention involves treating a tumor or local or regional tissue mass with antitumor sensitizing agents, biological modifiers, antibiotics or other types of drugs by delivery of the drug to the tumor or tissue area directly or through the passageway wall.

1. Field of the Invention
The present invention relates generally to a drug delivery apparatus and method, and more particularly, to an apparatus and method for selectively and locally delivering a drug to internal body tissue. More specific applications of the present invention relate to an apparatus and method for limiting restenosis of natural or an artificially dilated blood vessel and localized treatment of tumors or other tissue.
2. Description of the Prior Art
Many techniques currently exist for delivering drugs or other medicaments to body tissue. These include, among possible others, oral administration, injection directly into body tissue such as through an intramuscular injection or the like, topical or transcutaneous administration where the drug is passively absorbed, or caused to pass, into or across the skin or other surface tissue and intravenous administration which involves introducing a selected drug directly into the blood stream.
Except for topical or transcutaneous administration, the above drug delivery systems tend to be systemic. In other words, administration of the drug is delivered throughout the body by the blood stream. Although transcutaneous drug delivery systems tend to be localized delivery systems in that the drug is delivered locally to a selected area, such drug delivery systems are also, by definition, limited to application of a drug externally through the patient's skin or other surface tissue. Thus, the above described drug delivery systems are generally not appropriate for the localized treatment of internal body tissue.
Although many medical situations are satisfactorily treated by the general systemic administration of a drug, there are a great many treatments which could be facilitated and/or improved by the ability to deliver or administer a drug locally to a selected portion of internal body tissue, without appreciably affecting the surrounding tissue.
One example is the ability to treat the dilated vessel in percutaneous transluminal coronary angioplasty (PTCA), and thus limit or prevent restenosis. In PTCA, catheters are inserted into the cardiovascular system under local anesthesia and an expandable balloon portion is then inflated to compress the atherosclerosis and dilate the lumen of the artery. Despite the general success of such PTCA procedures, high restenosis rates (reported to be as high as 47%) continue to be a major problem. Various techniques have been tried to treat stenosed vessels including the use of lasers, application of heat and the use of intravascular stents. However, many of these are still under investigation with mixed results, while others have generally not been successful. The ability to administer a drug locally to the dilated portion of the artery in PTCA procedures, without significantly affecting other tissues, would greatly enhance the ability to address the restenosis problem.
A second example of specific application for a local drug delivery system for delivering a drug to an internal body tissue is in the treatment of cancerous tumors or the like. In the treatment of such tumors, an objective is to administer the cancer drug so that it localizes, as much as possible, in the tumor itself. Such drugs are commonly administered systemically through the blood stream. Various means are then utilized for causing the drug to localize in the cancer tumor. Nevertheless, significant portions of the drug still circulate through the blood stream, thereby affecting noncancerous tissue, producing undesirable side effects, and limiting the dosages of the drug which can be safely administered.
Accordingly, there is a need in the art for a method and apparatus for delivering a drug selectively and locally to internal body tissue, without significantly affecting other tissue. There is a further need for such a system and method for the localized treatment of internal body tissues to limit restenosis following PTCA, to treat cancerous tumors or the like, or to treat various other medical situations.


An enhanced IP telephone taking advantage of the many call-related functions provided by existing PBX systems. The enhanced IP telephone includes a thin computer telephony integration (CTI) client transmitting to a CTI server a command associated with a particular call-related function provided by a PBX unit. The CTI server translates the command to a PBX command, and transmits the PBX command to the PBX unit for providing the particular call-related function to the enhanced IP telephone. Instead of the thin CTI client, the enhanced IP telephone may include an enhanced IP signaling protocol stack for accessing the PBX functionality using its signaling protocol. A CTI translator translates the enhanced signaling command to a CTI command for transmitting to the CTI server.

Internet protocol (IP) telephones used for Internet telephony via signaling protocols such as H.323 or Session Initiation Protocol (SIP), already exist in the prior art. Although these signaling protocols may make some provisions for additional functionality, such as multiparty conferencing with other SIP and H.323 devices, they do not take advantage of the powerful existing functionality already found within most private branch exchange (PBX) systems. PBX systems provide such functionality as automatic call distribution, messaging, voice mail, conferencing, call hold, dial-by-name, and the like. Existing Internet telephony signaling protocols do not include specific provisions for accessing such PBX functionality. Specifically, signaling protocols such as H.323 and SIP have been designed to work without the use of a PBX.
The existence of Computer Telephony Integration (CTI) technology does not aid in providing PBX functionality to IP phones. Generally speaking, CTI is a technology through which computers add intelligence to telephone networks. CTI is typically applied to a personal computer (PC) with an associated standard telephone to access the functionality of a PBX. A CTI client resident within the PC typically exploits functionality residing within the PC, such as ActiveX, OLE, dlls, and the like, to access the PBX functionality. For example, a call may be initiated by clicking a name in a contact management PC program instead of dialing the number on the telephone.
FIG. 1 is a schematic block diagram of a traditional CTI system conventional in the art. The system includes a CTI-enabled desktop 10 including a PC and a traditional telephone set 14. A software application 18 resident in the PC 12 is used to access a functionality provided by a PBX 20 via a CTI client 16 also resident in the PC. The CTI client transmits commands to a CTI server 22 via an internet protocol (IP) network 24 associated with the accessed functionality. The CTI server 22 receives the CTI commands from the PC 12, translates them to PBX commands; and transmits the PBX commands to the PBX for invoking an action on the PBX 20. Communication ensues with the telephone set 14 via the PBX 20 over a telephone network 26: Existing CTI architectures, however, are not applicable to IP telephones.
One approach in allowing IP phones to utilize the existing PBX functionality is PBX redesign. PBX redesign exposes the internal features of the PBX to vendor-specific IP phones, allowing IP phones to interact directly with the PBX without intermediate servers. Unfortunately, PBX redesign and vendor-specific IP phones have the following limitations. First, with PBX redesign, an enterprise may be generally forced to only use the vendor-specific IP phone with the vendor-specific PBX. As such, customer choice may be eliminated, severely impacting an enterprise migration plan. For example, an enterprise may have multiple types of PBXs and may wish to decouple the choice of the IP phone from the types of existing or future PBX systems.
Second, with PBX redesign, many of the vendor-specific IP phones may be able to make/place calls to/from the PBX itself, but not from other standardized IP phones and IP voice gateways. Third, for the vendor to make changes to the internal. PBX system, the PBX system may have to be modified to expose the functionality to IP clients. This may require substantial development effort on the part of the vendor and may further require each enterprise to install the modified PBX system.
Consequently, what is needed is a solution that exposes the PBX functionality that is typically associated with custom vendor digital sets or CTI-based PC desktop applications to IP phone clients. Specifically, a solution is needed that enhances IP phone clients with powerful functionality already resident within many existing PBX systems.

This patent is subject to a terminal disclaimer.


A pliers has specifically configured elongate jaws of about rectilinear construction with multiple position adjustability to variously operatively engage a plurality of slack adjustment services of diverse commercial air brakes to check the slack.

1. Field of the Invention
This invention relates to tools for checking the slack on an automotive air brake. This invention more particularly relates to tools for checking the slack in air brake automotive slack adjusters.
2. Discussion of the Background and Prior Art
A typical foundation air brake used on each wheel, or wheel-pair, of large vehicles such as trucks and buses includes an air chamber rigidly mounted on a non-rotating portion of an axle structure near one of the wheels. A piston within the chamber is moved in one direction by compressed air controlled by a valve operated by the driver of the vehicle to apply the brakes by means of a push rod attached to the piston and connected by a clevis to a lever, called a slack adjuster, mounted on one end of a cam shaft. This movement of the lever transmits torque through the camshaft to rotate an S-shaped cam, or S-cam, rigidly mounted on the other end of the shaft. The S-cam transmits the force through cam-follower rollers supported at the ends of brake shoes to force the brake shoes apart and the brake pads mounted on them against the brake drum to brake the vehicle.
The brake shoes are set to move a certain minimum distance before the pads touch the drums, and this distance constitutes slack in the movement of the slack adjuster lever. As the brake drum and the pads wear, the lever has to move farther to apply the brakes, which increases the range of slack movement. This freedom of motion must be limited so that it does not exceed a certain maximum amount, and for that reason the lever includes means for adjusting its angular setting on the camshaft relative to the orientation of the S-cam. The slack adjuster is not directly affixed to the camshaft but is rotatably mounted on a worm gear that has internal spines mounted on spines on the end of the camshaft to prevent the gear from rotating relative to the shaft. The lever can rotate on the worm gear only to a limited extent within a range determined by the engagement of gear teeth on the outer surface of the gear with a worm mounted in a fixed location within the slack adjuster lever. The worm is rotatable about its own axis, which is perpendicular to the axis of the cam shaft, and it has a polygonal head, which is usually hexagonal but is square on some slack adjusters, and is somewhat accessible from outside the slack adjuster to permit the worm to be rotated on its axis by a socket wrench. Excess slack is taken up by rotating the head to adjust the angle of the lever to the proper position to cause the S-cam to begin to apply pressure to the roller followers after the outer end of the push rod extending from the air chamber has moved only a short distance, typically between ½″ and ¾″ from the position it occupies when the piston is not under pressure from compressed air.
Other slack adjusters are referred to as self-adjusting or automatic because they have sensors that detect the amount of slack and are connected to actuating means in the slack adjusting lever to rotate the worm to take up excess slack. However, even the automatic slack adjusters have provision for some manual check.
The slack in each brake of a vehicle so equipped needs to be checked regularly to be sure that the brake shoes apply balanced pressure on the drums so that they can bring the vehicle to a halt without causing it to swerve or skid as it stops. In organizations that operate fleets of vehicles having air brakes, mechanics are required to inspect the brakes on a regular schedule, but in addition, the drivers are also supposed to check the slack adjusters at the beginning of each day's trip.
Recent state and federal regulations, such as the Department of Transportation's 1198 edict, mandate that all truck drivers must be able to measure the slack in the air brakes of the vehicles they own, operate or drive. Thus the air brakes must be checked daily, and certainly before each trip, to determine if the slack of each air brake assembly is within or exceeds the safe working maximum limits.
In the field relating to air brake slack check tools, it is generally known to provide a tool having fixedly spaced engagement members, which members are positioned for engagement of different but a limited number of slack check surfaces. One such tool is disclosure is U.S. Des. 296,750, granted Jul. 19, 1988 to Hamatani (the "Hamatani tool"). The Hamatani tool required two hands to be operable, one hand engages the handle and the other hand adjusts and sets the position using a wing nut. The Hamatani tool relies on the wing nut to hold the set position when the tool was in use. A present widely used tool, quite similar to the Hamatani tool construction, is the Brake Slack Check OTC 5052 tool, commercially available from OTC a division of SPX Corporation, Owatonna, Minn. (the "OTC tool"). The OTC tool provides a four position construction. The OTC tool, like the Hamatani tool, requires two hands to be operable, and provides a limited range of operable positions. The OTC tool also generally requires a two-person operation; a first person operates the tool while a second person in the cab applies force to the brake to permit the first person to use the tool to check the clearance or slack.
The air brake slack check the art desires a tool, which readily provides sufficient gripping and leverage forces for a broad range of slack adjuster surfaces of diverse models of trucks and buses, and yet is practical in design and construction. The air brake slack check art further desires a tool, as aforesaid, which eliminates the number of hands and operators, and yet provides the necessary slack check leverage. The present invention provides a solution to the foregoing slack check art requirements and needs.
In the field related to pliers, it is generally known to provide pliers that are adjustable. Adjustable pliers are disclosed in U.S. Pat. No. 6,892,609, granted May 17, 2005 to Kuo, U.S. Pat. No. 4,603,607 granted Aug. 5, 1986 to Schaffner et al, U.S. Pat. No. 5,134,908, granted Aug. 4, 1992 to Fisher, and U.S. Pat. No. 4,890,519 granted Jul. 2, 1990 to Le Duc.