A pin plug is a connector which is inserted into a jack etc. In the pin plug, a cylindrical sleeve portion and an insulator body for fixing the sleeve portion and a metal center pin are integrally formed with rigid resin to form an insulator. Moreover, a flexible metal contact piece is attached to an opening portion formed at a part of the sleeve portion, and a non-rigid resin cover engages the outside of the insulator and the contact piece. When the thus constructed pin plug is inserted into a jack, a good electric contact state can be obtained between the pin plug and jack owing to the resiliency of the contact piece and the cover, and the pin plug can be inserted into or extracted from the jack with ease.

1. Field of the Invention
The present invention relates to a pin plug which is a connecting apparatus to be connected to a jack, etc., for connecting electric components to each other.
2. Description of the Related Art
There were pin plugs of this kind such as disclosed in the following literatures;
Literature 1: Japanese Utility Model Publication No. 63-25668
Literature 2: Electronic Industries Association of Japan Specification "RC-6703A pin connector for electronic components" (1988-7) published by Electronic Industries Association of Japan (Inc.) Technical Department.
FIG. 1 is a longitudinal cross-sectional view of a conventional pin plug described in the literature 1 set forth above and FIG. 2 is an enlarged cross-sectional view thereof cut along II--II line.
The pin plug 10 is inserted into or extracted from, for example, a jack 20. The jack 20 comprises a cylindrical metal sleeve 21 and a female electric contact 22 which is fixed in the metal sleeve 21 by way of an insulator.
The pin plug 10 comprises a cylindrical metal sleeve 11 which is inserted outside the sleeve 21 of the jack 20, a metal center pin 12 which is arranged along the axis of the sleeve 11 and contacts the female electric contact 22 of the jack 20, an insulator 13 which electrically insulates the sleeve 11 from the center pin 12 and fix them to each other and a synthetic resin cover 14 which engages the outside of the sleeve 11.
The sleeve 11 includes a cylindrical head portion 11a and a cord clamping portion 11b extended therefrom, both of which are, for example, made of a sheet of metal plate. The cylindrical head portion 11a is formed of a sheet of metal plate machined into a cylindrical shape having a slit 11c therein. The cord clamping portion 11b of the sleeve 11 fixedly clamps a cord 30, and the second conductor of the cord 30 (e.g., a cable sheath) 32 is fixed to the cord clamping portion 11b by spot welding etc. A center pin 12 is arranged along the axis of the cylindrical head portion 11a. The center pin 12 is connected to a first conductor of the cord 30 (e.g., a cable core) 31 at the rear half portion thereof by spot welding etc., and the rear half portion of the center pin 12 and the sleeve 11 are fixed to each other by a resin insulator 13 so as to form a cylindrical form having the same diameter as that of the head portion 11a. A cover 14 engages the outside of the insulator 13 and the sleeve 11.
The assembling of the pin plug of this kind and the connection thereof to the cord 30 are performed as follows.
The center pin 12 is inserted into the head portion 11a of the sleeve 11 along the axis thereof and the cylindrical insulator 13 having the same diameter as that of the head portion 11a and fixing the rear half of the center pin 12 therein is formed between the head portion 11a and the cord clamping portion 11b by way of resin insert. Then the cord 30 piercing the cover 14 is clamped by the cord clamping portion 11b of the sleeve 11, the cable sheath 32 of the cord 30 is connected to the cord clamping portion 11b by spot welding etc., and the cable conductor 31 of the cord 30 is connected to the center pin 12 at the rear side surface thereof by spot welding etc.
Thereafter the cover 14 is forced to be put on the sleeve 11 from the rear side thereof toward the head portion 11a so as to cover the same. In this way the assembling of the pin plug and the connection of the cord 30 thereto are completed.
When the tip end of the center pin 12 of the thus assembled pin plug 10 is inserted into the female contact 22 of the jack 20, the sleeve 11 of the pin plug 10 engages the outside of the sleeve 21 of the jack 20, so that the center pin 12 of the pin plug 10 is electrically coupled to the female contact 22 of the jack 20 and the sleeve 11 of the pin plug 10 is electrically coupled to the sleeve 21 of the jack 20.
The conventional pin plug, however, had the following drawbacks.
In the conventional pin plug 10, the sleeve 11 is made of, for example, a sheet of metal plate by press molding, etc. for manufacturing simplification, cost reduction, etc. and has a cylindrically formed head portion 11a. Since the cylindrical head portion 11a is made of a sheet of metal plate, it has a slit 11c, which makes the head portion 11a displaceable and elastic in the radial direction thereof. The elasticity of the head portion 11a of the sleeve 11, however, is poor due to its construction.
The diameter of the head portion 11a of the sleeve 11 is determined by a technical standard as described in the literature 2, etc., set forth above, with a strict allowable error of, e.g., .PHI. 8.3.+-.0.1 (mm). As a result, when the diameter of the head portion 11a of the sleeve 11 is too large due to a manufacturing variation, there occurs a defective electrical contact between the sleeve 21 of the jack 20 and itself. On the contrary, when it is too small, it can hardly be inserted into or extracted from the sleeve 21 of the jack 20. At that time, if the head portion 11a having a small diameter is forced to be set outside the sleeve 21 of the jack 20, there is a likelihood of defective electric contact between the sleeve 21 and itself since the sleeve 21 enlarges the slit 11c so that the head portion 11a is deformed to be elliptical in cross section and the contacting area between the head portion 11a and the sleeve 21 is lessened.
Moreover, there were drawbacks such as the poor corrosion resistance of the metal head portion 11a of the sleeve 11, and furthermore, the difficulty of coloring for color code identification of pin plugs.
It is the first object of the present invention to provide a pin plug which comprises a sleeve and an insulator integrally formed with a rigid resin and has a two-partitioned structure, so as to increase accuracy in the diameter of the cylindrical sleeve portion at manufacturing and be easily assembled without any specific tool.
It is the second object of the present invention to provide a pin plug comprising a flexible metal contact piece at the opening formed at a portion of the circumference of the cylindrical sleeve thereof and a non-rigid resin cover which presses the contact piece toward the axis of the insulator so as to enable the pin plug to be smoothly inserted into the sleeve etc. of the jack and extracted therefrom, and furthermore, to obtain a good electric contact between the sleeve of the jack and itself by the elasticity of the cover and the contact piece.
It is the third object of the present invention to provide a pin plug which is improved in corrosion resistance and easy coloring so as to be identified by a color code at the sleeve thereof with ease.
It is the fourth object of the present invention to provide a pin plug which can be manufactured more easily by integrally forming the insulator having a cylindrical sleeve portion by rigid resin molding so as to fix the metal contact piece and the center pin therein.
In order to achieve the above objects, the pin plug according to the present invention comprises a cylindrical sleeve to which a first conductor of a cord having the first and a second conductors therein is connected, a center pin disposed along the axis of the sleeve, one end of which projects from the sleeve and the other end of which is connected to the second conductor of the cord, an insulator for electrically insulating the sleeve from the center pin and for fixing them each other, and a non-rigid resin cover which engages the outside of the sleeve.
The sleeve and the insulator set forth above are integrally formed with rigid resin into a two-partitioned component, the sleeve includes an opening at a part of the circumference of the cylindrical sleeve portion thereof, and a flexible metal contact piece connected to the first conductor of the cord is attached to the opening so as to be radially displaceable.
The objects of the present invention set forth above, other objects and new characteristic thereof will be more completely understood by reading the following detailed description with reference to attached drawings. The drawings, however, is exclusively for explanation and does not limit the scope of the present invention thereto.


The invention relates to a mobile structure which is intended for various different uses and purposes and which is of the type that comprises a flat floor chassis with wheels, towing means such that it can be towed by a vehicle and floor support means. The invention is characterized in that the structure comprises: an upper structural shell consisting of two outer frames and at least one intermediate frame, which are connected at the top by lateral and central longitudinal joists, and crossbars forming a plurality of upper cavities which are covered either by laminar sections or skylight elements; and a plurality of independent panels forming the walls of the structure, which are disposed around the structural shell and which can take the form of solid panels or panels comprising a window, a door or an air-conditioning system. The panels are disposed peripherally around the structural shell such that adjacent panels are joined as well as being connected at the bottom to peripheral assembly means belonging to the floor of th chassis and fixed in place using coupling means. The panels are made from frames comprising a pair of hollow lateral posts which are equipped with a plurality of longitudinal grooves on the inner face thereof (racks) and which are connected by a plurality of crossbars and external, internal and lateral cover sheets. The aforementioned racks are designed to receive hooks, supports or brackets or similar furnishings and interior fittings.

Before the present invention, a type of trailer mobile structure was well-known, which comprise a chassis with axles and wheels, four sheet walls—two lateral, one in the front, one on the back, and a horizontal roof, joined by a variety of means in vertical posts of the support structure, and are best known as trailers, and generally these trailers resemble hollow cellars that are typified on the inside by ordinary furniture, which are placed inside the trailer in a random way, generally without being fixed to the trailer.
Such furniture inevitably needs lower supports such as legs, multiple means of attaching such as screwing, brackets, etc. and in case air conditioning is desired, it is necessary to cut the existing wall to install it in the hole created by the cut, the same occurs in case that is intended to install additional doors or windows.
Such mobile stations, cottages or trailers, are delivered as "big boxes" that do not have with any means for adding to the basic adaptations, which reduces the versatility of the inner space, besides in the case of wiring for electric energy, voice and/or data, the wires will remain visible to the occupants of the trailers.
Because of all the previously problems, it was necessary to create a new multifunctional mobile rolling trailer that primarily solves the inconveniences described and further that could offer large significant advantages from it's structural, functional and versatility aspects and further for its design and configuration of accessories and interior equipment perspective.


A chip embedded package method is provided by an embodiment of the present invention. The method comprises: etching metallic sinks on the thicker metal layer of each organic substrate; part of metallic sinks is used for packaging at least one chip, and other metallic sinks are used for via-holes; mounting the at least one chip into a metallic sink of each organic substrate via adhesive; flipping one organic substrate on another to form a combination; drilling blind-holes on both sides of the combination of the two organic substrates to pass through the adhesive; drilling via-holes to get through the combination of the two organic substrates, wherein the via-holes locates beyond the metallic sinks with chips; filling the blind-holes and via-holes with conductive medium through an electroplating process.

With continuous development of information technology, mobile phones and other various electronic products become thinner and lighter. Mobile phones and computers have more and more functions while the size of which become smaller and smaller. Therefore, the requirement of the integration level of chips and devices becomes higher and higher. Along with the development of large-scale integration circuit, the integration level has reached an unprecedented level as the line width is approaching 22 nm. Meantime, more improvement of related technology and devices is also required. Since further reduction of line width becomes more and more difficult, the development of related technology process and devices therefore slows down.
In this case, 3D high density packaging technology has attracted widely attention, by which, no longer one chip but several chips can be packaged in one device. In addition, the chips are stacked into a 3D high-density assembled micro-chip rather than being arranged in the same layer. Hence, the 3D chip stacking greatly reduces the size of the device. Furthermore, the chip stacking process is also constantly developed. From FLIP CHIP technology to TSV (Through Silicon Via) through-hole interconnection technology, electronic devices become smaller and smaller. Package process is improved by technologies from the traditional bonding, chipping and plastic package to current essential processes such as RDL (Redistribution Layer), Flip Chip, wafer bonding, TSV and so on. Consequently, package structures with smaller sizes and higher chip density emerges continually.
By using the prior chip embedding technology, mass-production cannot be achieved efficiently due to the unreliability of heat dissipation. Especially for high-power devices, the application of chip embedded package is restricted by the heat dissipation management.

Chip embedded package method and structure

National Center For Advanced Packaging Co., Ltd.


A thermal imaging camera with a repositionable focal plane array (FPA) is disclosed. An active portion of the FPA is used by the camera to generate a thermal image. The FPA may be positioned such that a defect in the FPA is located in an unused and inactive portion of the FPA.

Thermal imaging cameras are used in a variety of situations. For example, thermal imaging cameras are often used during maintenance inspections to thermally inspect equipment. Example equipment may include rotating machinery, electrical panels, or rows of circuit breakers, among other types of equipment. Thermal inspections can detect equipment hot spots such as overheating machinery or electrical components, helping to ensure timely repair or replacement of the overheating equipment before a more significant problem develops.
Thermal imaging cameras include sensors for detecting infrared energy in a scene being viewed by the camera. An example of such a sensor is a focal plane array (FPA) which generates an electrical signal in response to infrared energy received through the camera lens. The FPA includes sensor elements, such as bolometers or photon detectors, and each such sensor element may be referred to as a sensor pixel. The electrical resistance or voltage of the sensor pixels changes in response to infrared energy and can therefore be used to generate a thermal image.
The focal plane array includes a plurality of sensor pixels arranged side by side, often in vertical columns and horizontal rows. However, one or more sensor pixels may be inoperable or may become damaged during production of the FPA and prior to placement in the thermal imaging camera. In some cases, such as when only a single pixel is inoperable, the processor of the camera can compensate for the inoperable pixel by mathematical analysis of the data from the surrounding pixels to estimate the thermal energy reading that would be obtained by the inoperable sensor pixel if it were functioning normally, and use that estimate in producing the thermal image. However, in other cases, such as when multiple pixels which are adjacent to each other are inoperable, such an estimate of the thermal energy reading is less effective, resulting in a defect which may be perceptible and/or objectionable to a manufacturer or end user. In such cases, the manufacturer may choose to discard the FPA.
In some cases, if the defect is located on the periphery of the FPA, the thermal imaging camera may use only the central portion of the FPA for gathering thermal energy readings. In this way, the FPA can still be used, though a reduced number of sensor pixels would be used to create the thermal image. However, such adjustments are not possible if the defect is located too close to the center of the FPA. In addition, portions of the periphery of the FPA which are fully functional, or which include pixels for which mathematical compensation is acceptable, remain unused and are therefore wasted in such a scenario.

Thermal imaging camera with repositionable active portions of focal plane array


An insertion system with a self-expanding braided stent (11) for implantation in a blood vessel has an outer sleeve (12) with a distal end (14) and a proximal end. An inner sleeve (16) arranged in the outer sleeve (12) is displaceable relative to the latter and protrudes, with a handling section, from the proximal end of the outer sleeve (12). Moreover, at the distal end (15), there is a tip (18) which is securely connected to a stent support (24) on which the braided stent (11) is arranged in its loaded state. The stent support (24) is arranged to be displaceable relative to the inner sleeve (16).

1. Field of the Invention
The present invention relates to a delivery system having a self-expanding braided stent intended for implantation into a blood vessel, with an outer sleeve, which has a distal end and a proximal end and in which an inner sleeve is arranged that is displaceable relative to the outer sleeve and protrudes, with a handling portion, from the proximal end of the outer sleeve, and with a tip, which is arranged at the distal end and is securely connected to a stent support on which the braided stent is arranged in its loaded state.
2. Related Prior Art
A delivery system of this kind is known commercially to the applicant of the present invention.
A stent is understood as a radially expandable endoprosthesis, which is a typical intravascular implant that is implanted via a lumen and is radially enlarged expanded after it has been introduced percutaneously. Stents are used, for example, to strengthen blood vessels and, in the vascular system, to prevent restenosis after angioplasty. In addition, they are also implanted in arteries for the treatment of aneurysms.
Such stents can be self-expanding or can be expanded by a radial force applied from the inside, for example when they are fitted on a balloon.
A very wide variety of stents are used depending on the type of application. The present invention is concerned with the application of what are called braided stents, such as are known, for example, from DE 197 50 97 A1 or DE 103 35 649 A1.
A braided stent is a metal stent that is produced by what is called a plain weaving technique. It is composed of a hollow body, which can stretch in the longitudinal direction and whose jacket is a braid made up of a multiplicity of filament-like elements which, in the expanded state of the braided stent, intersect a plane, perpendicular to the longitudinal direction, at a braid angle. A braided stent undergoes a considerable change in length when stretched, this change in length being all the greater the greater the original diameter and the smaller the original braid angle.
For implantation, a braided stent of this type is stored in an elongate configuration in what is called a delivery system or applicator, the latter being introduced percutaneously into the body at a suitable location, for example the femoral artery, and being guided through a lumen as far as the vessel where the stent is to be released. The delivery system and the stent are often provided with X-ray markers with which the positioning and the release of the stent can be monitored in situ.
In stents that experience no change or only a very slight change in length when released, the position of the implantable stent can be verified in this way without any difficulty, for which reason there are also many different delivery systems available for stents of this type that only expand radially.
In braided stents, however, a problem that arises is that they are very much shortened when released. At a braid angle of 40°, for example, the ratio between the stent length in the loaded state in the delivery system and the stent length in the expanded state, in other words the free state, is 1.5:1, for example. If the braid angle α is smaller, this ratio increases still further, and, at a braid angle of α=10°, the ratio can even be 4:1 to 6:1. It should be noted here that the shortening in length is of course also dependent on the diameter of the stent in the loaded state and on the diameter of the stent in the released state.
Braided stents are therefore extremely extensible and, in their elongated state, they as it were store mass which, upon contraction of the stents, ensures a compact and stiff functional area, as is explained in detail in aforementioned DE 103 35 649 A1.
Braided stents, in which this shortening has to be taken into account, have hitherto been releasable in the blood vessel only with a low level of positioning accuracy. However, the positioning of a stent at the desired location in the blood vessel is a critical factor that determines the effect of the stents and the success of the medical intervention. The area in the blood vessel where the stent is to be expanded is usually accessible to the physician only with difficulty.
For example, the stent has to be positioned in the area of an organ or, in the case of the carotid artery, in the region of the cerebral arteries, where in some cases only a relatively short stent has to be put in place. However, because of the considerable shortening that takes place upon release of a braided stent, conventional systems require a substantial length of release, as is the case, for example, in the system available on the market.
In the known delivery system, the braided stent in the loaded state, that is to say in the extremely elongated form, lies proximally from the tip and rests on the stent support, which is connected securely to the inner sleeve. The stent is pressed radially inward by the outer sleeve and is held in its elongated form.
To deploy the braided stent, the inner sleeve is held secure, and with it the stent support and the tip connected to the latter, and it must not be moved during the release. The outer sleeve is then pulled back carefully from the tip, such that the stent is released gradually. As the stent comes free, it contracts in the direction of the outer sleeve and thus moves away from the tip, which remains fixed in position relative to the vessel by the inner sleeve. As the outer sleeve is pulled back, the gradually released and radially expanding stent, contracting in the longitudinal direction, follows the outer sleeve until a portion of the braided stent has been released which is such that the latter bears securely against the inner wall of the vessel.
All of this means, however, that the tip of the delivery system has to be displaced distally far beyond the intended site of release of the braided stent in order to permit a correct placement. In the known delivery system, this amounts to several centimeters, which leads to a length of release that cannot be tolerated, especially in the case of small braid angles. Particularly in cases where a relatively short stent has to be placed in proximity to an organ or to the cerebral arteries, there is a danger that the further advanced tip will cause damage to the organ or the cerebral artery.
A further disadvantage of the known delivery system is seen in the fact that the position of the braided stent in the vessel can be influenced only with difficulty by manipulation of the outer sleeve. If the operating surgeon has pushed the delivery system in too far or not far enough, he can no longer influence the final position of the braided stent in the known delivery system. If he finds that the braided stent is released too far above or below the planned site of deployment, he has to pull the braided stent in again, which, in the known delivery system, can only be done in emergency situations, and not more than twice. To "reload" the braided stent into the delivery system, the outer sleeve is now held secure, while the inner sleeve is carefully pulled back. In the known delivery system, however, this reloading is only possible as long as not more than 50% of the braided stent has been released.
In the known delivery system, therefore, one disadvantage is that braided stents in particular with small braid angles cannot be positioned close enough to organs or cerebral arteries, etc., while a further disadvantage is that exact positioning is extremely difficult.

Delivery system having a self-expanding braided stent


A semiconductor memory cell comprising a first transistor for readout, a second transistor for switching, and having a first region, a second region formed in a surface region of the first region, a third region formed in a surface region of the second region, a fourth region formed in a surface region of the first region and spaced from the second region, a fifth region formed in a surface region of the fourth region, and a gate region, wherein when the semiconductor memory cell is cut with a first imaginary perpendicular plane which is perpendicular to the extending direction of the gate region and passes through the center of the gate region, the second region and the fourth region in the vicinity of the gate region are nearly symmetrical with respect to a second imaginary perpendicular plane which is in parallel with the extending direction of the gate region and passes through the center of the gate region.

The present invention relates to a semiconductor memory cell having at least two transistors merged into one unit or at least two transistors and a diode merged into one unit. Otherwise, the present invention relates to a semiconductor memory cell having two transistors and a junction-field-effect transistor merged into one unit or at least two transistors, a junction-field-effect transistor and a diode merged into one unit.
As a high-density semiconductor memory cell, conventionally, there is used a dynamic semiconductor memory cell that is called a single-transistor semiconductor memory cell including one transistor and one capacitor as shown in FIG. 67A. In the above semiconductor memory cell, an electric charge stored in the capacitor is required to be large enough to generate a sufficiently large voltage change on a bit line. However, with a decrease in the planar dimensions of the semiconductor memory cell, the capacitor formed in a parallel planar shape decreases in size, which causes the following new problem. When information stored as an electric charge in the capacitor of the semiconductor memory cell is read out, the read-out information is buried in a noise. Or, since the stray capacitance of the bit line in the semiconductor memory cell increases from generation to generation, only a small voltage change is generated on the bit line. As means for solving the above problems, there has been proposed a dynamic semiconductor memory cell having a trench capacitor cell structure as shown in FIG. 67B or a stacked capacitor cell structure. Since, however, the fabrication-related technology has its own limits on the depth of the trench (or groove) or the height of the stack, the capacitance of the capacitor is also limited. For this reason, dynamic semiconductor memory cells having the above structures are said to encounter the above limits unless expensive new materials are introduced for the capacitor as far as the dimensions thereof beyond the deep sub-micron rule (low sub-micron rule) are concerned.
In the planar dimensions smaller than those of the deep sub-micron rule (low sub-micron rule), the transistor constituting the semiconductor memory cell also has problems of deterioration of the drain breakdown voltage and a punchthrough from a drain region to a source region. There is therefore a large risk that current leakage takes place even if the voltage applied to the semiconductor memory cell is still within a predetermined range. When a semiconductor memory cell is made smaller in size, therefore, it is difficult to normally operate the semiconductor memory cell having a conventional transistor structure.
For overcoming the above limit problems of the capacitor, the present Applicant has proposed a semiconductor memory cell comprising two transistors or two transistors physically merged into one unit, as is disclosed in Japanese Patent Application No. 246264/1993 (JP-A-7-99251) corresponding to U.S. Pat. No. 5,428,238. The following explanation is made by referring to Japanese Patent Application No. 246264/1993 (JP-A-7-99251). The semiconductor memory cell shown in FIGS. 15(A) and 15(B) of the above Japanese Patent Application comprises a first semi-conductive region SC1 of a first conductivity type formed in a surface region of a semiconductor substrate or formed on an insulating substrate, a first conductive region SC2 formed in a surface region of the first semi-conductive region SC1 so as to form a rectifier junction together with the first semi-conductive region SC1, a second semi-conductive region SC3 of a second conductivity type formed in a surface region of the first semi-conductive region SC1 and spaced from the first conductive region SC2, a second conductive region SC4 formed in a surface region of the second semi-conductive region SC3 so as to form a rectifier junction together with the second semi-conductive region SC3, and a conductive gate G formed on a barrier layer so as to bridge the first semi-conductive region SC1 and the second conductive region SC4 and so as to bridge the first conductive region SC2 and the second semi-conductive region SC3, the conductive gate G being connected to a first memory-cell-selecting line, the first conductive region SC2 being connected to a write-in information setting line, and the second conductive region SC4 being connected to a second memory-cell-selecting line.
The first semi-conductive region SC1 (functioning as a channel forming region Ch2), the first conductive region SC2 and the second semi-conductive region SC3 (functioning as source/drain regions) and the conductive gate G constitute a switching transistor TR2. On the other hand, the second semi-conductive region SC3 (functioning as a channel forming region Ch1), the first semi-conductive region SC1 and the second conductive region SC4 (functioning as source/drain regions) and the conductive gate G constitute an information storing transistor TR1.
When information is written in the above semiconductor memory cell, the switching transistor TR2 is brought into an ON-state. As a result, the information is stored in the channel forming region Ch1 of the information storing transistor TR1 as a potential or as an electric charge. When the information is read out, the threshold voltage of the information storing transistor TR1 seen from the conductive gate G varies, depending upon the potential or the electric charge stored in the channel forming region Ch1 of the information storing transistor TR1. Therefore, when the information is read out, the storage state of the information storing transistor TR1 can be judged from the magnitude of a channel current (including a zero magnitude) by applying a properly selected potential to the conductive gate G. The information is read out by detecting the operation state of the information storing transistor TR1.
That is, when information is read out, the information storing transistor TR1 is brought into an ON-state or an OFF-state, depending upon the information stored therein. Since the second conductive region SC4 is connected to the second line, a current which is large or small depending upon the stored information (xe2x80x9c0 xe2x80x9d or xe2x80x9c1xe2x80x9d) flows in the information storing transistor TR1. In this way, the information stored in the semiconductor memory cell can be read out through the information storing transistor TR1.
Further, the present Applicant in Japanese Patent Application No. 251646/1997 (JP-A-10-154757) has proposed a semiconductor memory cell comprising three transistors such as a transistor TR1 for readout, a transistor TR2 for switching and a junction type transistor TR3 for current control.
In the semiconductor memory cells disclosed in the above Laid-open publications, however, the layout and structure of the regions are asymmetric with regard to a conductive gate, so that there is involved a problem that it is constantly required to advert to the direction of the conductive gate during designing and production of the semiconductor memory cells.
It is a first object of the present invention to provide a semiconductor memory cell, or a semiconductor memory cell for a logic, which permits a high freedom during designing or production thereof, which attains stabilized performances of a transistor, which requires no large capacitor unlike any conventional DRAM, which secures reliable writing and readout of information and which permits minimizing of dimensions, and further to a semiconductor memory cell in which at least two transistors, or at least two transistors and a diode are merged into one unit.
It is a second object of the present invention to provide a semiconductor memory cell, or a semiconductor memory cell for a logic, which permits a high freedom during designing or production thereof, which attains stabilized performances of a transistor, which requires no large capacitor unlike any conventional DRAM, which secures reliable writing and readout of information and which permits minimizing of dimensions, and further to a semiconductor memory cell in which at least two transistors and a junction-field-effect transistor, or at least two transistors, a junction-field-effect transistor and a diode are merged into one unit.
According to a first aspect of the present invention for achieving the above first object, there is provided a semiconductor memory cell comprising;
(1) a first transistor for readout, having source/drain regions, a channel forming region and a gate region and having a first conductivity type, and
(2) a second transistor for switching, having source/drain regions, a channel forming region and a gate region and having a second conductivity type,
the semiconductor memory cell having;
(a) a semi-conductive first region having a second conductivity type,
(b) a semi-conductive second region which is formed in a surface region of the first region and has a first conductivity type,
(c) a third region which is formed in a surface region of the second region and is in contact with the second region so as to form a rectifier junction together with the second region,
(d) a semi-conductive fourth region which is formed in a surface region of the first region and spaced from the second region and which has the first conductivity type,
(e) a fifth region which is formed in a surface region of the fourth region and is in contact together with the fourth region so as to form a rectifier junction together with the fourth region, and
(f) a gate region which is formed on an insulation layer so as to bridge the first region and the third region and so as to bridge the second region and the fourth region, and is shared by the first and second transistors,
wherein:
(A-1) one source/drain region of the first transistor is formed of a surface region of the second region,
(A-2) the other source/drain region of the first transistor is formed of a surface region of the fourth region,
(A-3) the channel forming region of the first transistor is formed of a surface region of the first region which surface region is interposed between said surface region of the second region and said surface region of the fourth region,
(B-1) one source/drain region of the second transistor is formed of said surface region of the first region which surface region forms the channel forming region of the first transistor,
(B-2) the other source/drain region of the second transistor is formed of the third region,
(B-3) the channel forming region of the second transistor is formed of said surface region of the second region which surface region forms the one source/drain region of the first transistor,
(C) the gate region is connected to a first line for memory cell selection,
(D) the third region is connected to a write-in information setting line,
(E) the fourth region is connected to a second line, and
(F) the fifth region is connected to the first region,
and further wherein:
when the semiconductor memory cell is cut with a first imaginary perpendicular plane which is perpendicular to the extending direction of the gate region and passes through the center of the gate region, the second region and the fourth region in the vicinity of the gate region are nearly symmetrical with respect to a second imaginary perpendicular plane which is in parallel with the extending direction of the gate region and passes through the center of the gate region.
In the present invention, the term xe2x80x9cimaginary perpendicular planexe2x80x9d refers to an imaginary plane perpendicular to the surface of the first region. Further, the term xe2x80x9cnearly symmetricalxe2x80x9d is used for including a concept that cases where xe2x80x9csymmetryxe2x80x9d varies depending upon methods of forming each region are included in cases where two regions are symmetrical. The term xe2x80x9cnearly symmetricalxe2x80x9d is also used in this sense hereinafter.
According to a second aspect of the present invention for achieving the above first object, there is provided a semiconductor memory cell comprising;
(1) a first transistor for readout, having source/drain regions, a channel forming region and a gate region and having a first conductivity type,
(2) a second transistor for switching, having source/drain regions, a channel forming region and a gate region and having a second conductivity type, and
(3) a third transistor for current control, having source/drain regions, a channel forming region and a gate region and having the second conductivity type,
the semiconductor memory cell having;
(a) a semi-conductive first region having a second conductivity type,
(b) a semi-conductive second region which is formed in a surface region of the first region and has a first conductivity type,
(c) a third region which is formed in a surface region of the second region and is in contact with the second region so as to form a rectifier junction together with the second region,
(d) a semi-conductive fourth region which is formed in a surface region of the first region and spaced from the second region and which has the first conductivity type,
(e) a fifth region which is formed in a surface region of the fourth region and is in contact together with the fourth region so as to form a rectifier junction together with the fourth region, and
(f) a gate region which is formed on an insulation layer so as to bridge the first region and the third region, so as to bridge the second region and the fourth region and so as to bridge the first region and fifth region, and is shared by the first, second and third transistors,
wherein:
(A-1) one source/drain region of the first transistor is formed of a surface region of the second region,
(A-2) the other source/drain region of the first transistor is formed of a surface region of the fourth region,
(A-3) the channel forming region of the first transistor is formed of a surface region of the first region which surface region is interposed between said surface region of the second region and said surface region of the fourth region,
(B-1) one source/drain region of the second transistor is formed of said surface region of the first region which surface region forms the channel forming region of the first transistor,
(B-2) the other source/drain region of the second transistor is formed of the third region,
(B-3) the channel forming region of the second transistor is formed of said surface region of the second region which surface region forms the one source/drain region of the first transistor,
(C-1) one source/drain region of the third transistor is formed of said surface region of the first region,
(C-2) the other source/drain region of the third transistor is formed of the fifth region,
(C-3) the channel forming region of the third transistor is formed of said surface region of the fourth region,
(D) the gate region is connected to a first line for memory cell selection,
(E) the third region is connected to a write-in information setting line, and
(F) the fourth region is connected to a second line,
and further wherein:
when the semiconductor memory cell is cut with a first imaginary perpendicular plane which is perpendicular to the extending direction of the gate region and passes through the center of the gate region, the second region and the fourth region in the vicinity of the gate region are nearly symmetrical with respect to a second imaginary perpendicular plane which is in parallel with the extending direction of the gate region and passes through the center of the gate region.
Further, in the semiconductor memory cell according to the first or second aspect of the present invention, preferably, the third region and the fifth region in the vicinity of the gate region are nearly symmetrical with respect of the above second imaginary perpendicular plane when the semiconductor memory cell is cut with the above first imaginary perpendicular plane.
In the semiconductor memory cell according to the first or second aspect of the present invention, it is preferred to employ a constitution in which the second region is connected to a third line, the second line is used as a bit line and a predetermined potential is applied to the third line, or a constitution in which the second region is connected to a third line, the third line is used as a bit line and a predetermined potential is applied to the second line.
Alternatively, in the semiconductor memory cell according to the first or second aspect of the present invention, for simplification of a wiring structure, it is preferred to employ a constitution in which a diode is formed of the second region and the third region, and the second region is connected to the write-in information setting line through the third region. In this case, it is preferred to employ a constitution in which the second line is used as a bit line or a constitution in which the write-in information setting line is used as a bit line as well and a predetermined potential is applied to the second line.
According to a third aspect of the present invention for achieving the above second object, there is provided a semiconductor memory cell comprising;
(1) a first transistor for readout, having source/drain regions, a channel forming region and a gate region and having a first conductivity type,
(2) a second transistor for switching, having source/drain regions, a channel forming region and a gate region and having a second conductivity type, and
(3) a junction-field-effect transistor for current control, having source/drain regions, a channel region and gate portions,
the semiconductor memory cell having;
(a) a semi-conductive first region having a second conductivity type,
(b) a semi-conductive second region which is formed in a surface region of the first region and has a first conductivity type,
(c) a third region which is formed in a surface region of the second region and is in contact with the second region so as to form a rectifier junction together with the second region,
(d) a semi-conductive fourth region which is formed in a surface region of the first region and spaced from the second region and which has the first conductivity type,
(e) a fifth region which is formed in a surface region of the fourth region and is in contact with the fourth region so as to form a rectifier junction together with the fourth region, and
(f) a gate region which is formed on an insulation layer so as to bridge the first region and the third region and so as to bridge the second region and the fourth region and is shared by the first and second transistors,
wherein:
(A-1) one source/drain region of the first transistor is formed of a surface region of the second region,
(A-2) the other source/drain region of the first transistor is formed of a surface region of the fourth region,
(A-3) the channel forming region of the first transistor is formed of a surface region of the first region which surface region is interposed between said surface region of the second region and said surface region of the fourth region,
(B-1) one source/drain region of the second transistor is formed of said surface region of the first region which surface region forms the channel forming region of the first transistor,
(B-2) the other source/drain region of the second transistor is formed of the third region,
(B-3) the channel forming region of the second transistor is formed of said surface region of the second region which surface region forms the one source/drain region of the first transistor,
(C-1) the gate portions of the junction-field-effect transistor are formed of the fifth region and a portion of the first region which portion is opposed to the fifth region,
(C-2) the channel region of the junction-field-effect transistor is formed of a portion of the fourth region which portion is interposed between the fifth region and said portion of the first region,
(C-3) one source/drain region of the junction-field-effect transistor is formed of said surface region of the fourth region which surface region extends from one end of the channel region of the junction-field-effect transistor and forms the other source/drain region of the first transistor,
(C-4) the other source/drain region of the junction-field-effect transistor is formed of a portion of the fourth region which portion extends from the other end of the channel region of the junction-field-effect transistor,
(D) the gate region is connected to a first line for memory cell selection,
(E) the third region is connected to a write-in information setting line,
(F) the fourth region is connected to a second line, and
(G) the fifth region is connected to a third line,
and further wherein:
when the semiconductor memory cell is cut with a first imaginary perpendicular plane which is perpendicular to the extending direction of the gate region and passes through the center of the gate region, the second region and the fourth region in the vicinity of the gate region is nearly symmetrical with respect to a second imaginary perpendicular plane which is in parallel with the extending direction of the gate region and passes through the center of the gate region.
In the semiconductor memory cell according to the third aspect of the present invention, there may be employed a constitution in which the fifth region is connected to the write-in information setting line in place of being connected to the third line, or a constitution in which the fifth region is connected to the first region in place of being connected to the third line.
In the semiconductor memory cell according to the third aspect of the present invention, there may be employed a constitution in which the semiconductor memory cell further comprises a second junction-field-effect transistor for current control, having source/drain regions, a channel region and gate portions,
the gate portions of the second junction-field-effect transistor are formed of the third region and a portion of the first region which portion is opposed to the third region,
the channel region of the second junction-field-effect transistor is formed of a portion of the second region which portion is interposed between the third region and said portion of the first region,
one source/drain region of the second junction-field-effect transistor is formed of said surface region of the second region which surface region extends from one end of the channel region of the second junction-field-effect transistor and forms the one source/drain region of the first transistor, and
the other source/drain region of the second junction-field-effect transistor is formed of a portion of the second region which portion extends from the other end of the channel region of the second junction-field-effect transistor.
In the above case, there may be employed a constitution in which the fifth region is connected to the first region in place of being connected to the third line.
A semiconductor memory cell according to the fourth aspect of the present invention for achieving the above second object further has a third transistor for current control, and in this point, it differs from the semiconductor memory cell according to the third aspect of the present invention. That is, the semiconductor memory cell according to the fourth aspect of the present invention comprises;
(1) a first transistor for readout, having source/drain regions, a channel forming region and a gate region and having a first conductivity type,
(2) a second transistor for switching, having source/drain regions, a channel forming region and a gate region and having a second conductivity type,
(3) a third transistor for current control, having source/drain regions, a channel forming region and a gate region and having the second conductivity type, and
(4) a junction-field-effect transistor for current control, having source/drain regions, a channel region and gate portions,
the semiconductor memory cell having;
(a) a semi-conductive first region having a second conductivity type,
(b) a semi-conductive second region which is formed in a surface region of the first region and has a first conductivity type,
(c) a third region which is formed in a surface region of the second region and is in contact with the second region so as to form a rectifier junction together with the second region,
(d) a semi-conductive fourth region which is formed in a surface region of the first region and spaced from the second region and which has the first conductivity type,
(e) a fifth region which is formed in a surface region of the fourth region and is in contact with the fourth region so as to form a rectifier junction together with the fourth region, and
(f) a gate region which is formed on an insulation layer so as to bridge the first region and the third region, so as to bridge the second region and the fourth region and so as to bridge the first region and the fifth region and is shared by the first, second and third transistors,
wherein:
(A-1) one source/drain region of the first transistor is formed of a surface region of the second region,
(A-2) the other source/drain region of the first transistor is formed of a surface region of the fourth region,
(A-3) the channel forming region of the first transistor is formed of a surface region of the first region which surface region is interposed between said surface region of the second region and said surface region of the fourth region,
(B-1) one source/drain region of the second transistor is formed of said surface region of the first region which surface region forms the channel forming region of the first transistor,
(B-2) the other source/drain region of the second transistor is formed of the third region,
(B-3) the channel forming region of the second transistor is formed of said surface region of the second region which surface region forms the one source/drain region of the first transistor,
(C-1) one source/drain region of the third transistor is formed of said surface region of the first region,
(C-2) the other source/drain region of the third transistor is formed of the fifth region,
(C-3) the channel forming region of the third transistor is formed of said surface region of the fourth region,
(D-1) the gate portions of the junction-field-effect transistor are formed of the fifth region and a portion of the first region which portion is opposed to the fifth region,
(D-2) the channel region of the junction-field-effect transistor is formed of a portion of the fourth region which portion is interposed between the fifth region and said portion of the first region,
(D-3) one source/drain region of the junction-field-effect transistor is formed of said surface region of the fourth region which surface region extends from one end of the channel region of the junction-field-effect transistor, forms the other source/drain region of the first transistor and forms the channel forming region of the third transistor,
(D-4) the other source/drain region of the junction-field-effect transistor is formed of a portion of the fourth region which portion extends from the other end of the channel region of the junction-field-effect transistor,
(E) the gate region is connected to a first line for memory cell selection,
(F) the third region is connected to a write-in information setting line, and
(G) the fourth region is connected to a second line, and
and further wherein:
when the semiconductor memory cell is cut with a first imaginary perpendicular plane which is perpendicular to the extending direction-of the gate region and passes through the center of the gate region, the second region and the fourth region in the vicinity of the gate region is nearly symmetrical with respect to a second imaginary perpendicular plane which is in parallel with the extending direction of the gate region and passes through the center of the gate region.
In the semiconductor memory cell according to the fourth aspect of the present invention, there may be employed a constitution in which the semiconductor memory cell further comprises a second junction-field-effect transistor for current control, having source/drain regions, a channel region and gate portions,
the gate portions of the second junction-field-effect transistor are formed of the third region and a portion of the first region which portion is opposed to the third region,
the channel region of the second junction-field-effect transistor is formed of a portion of the second region which portion is interposed between the third region and said portion of the first region,
one source/drain region of the second junction-field-effect transistor is formed of said surface region of the second region which surface region extends from one end of the channel region of the second junction-field-effect transistor and forms the one source/drain region of the first transistor, and
the other source/drain region of the second junction-field-effect transistor is formed of a portion of the second region which portion extends from the other end of the channel region of the second junction-field-effect transistor.
A semiconductor memory cell according to a fifth aspect of the present invention for achieving the above second object differs from the semiconductor memory cell according to the third aspect of the present invention in a position where the junction-field-effect transistor is formed. That is, the semiconductor memory cell according to the fifth aspect of the present invention comprises;
(1) a first transistor for readout, having source/drain regions, a channel forming region and a gate region and having a first conductivity type,
(2) a second transistor for switching, having source/drain regions, a channel forming region and a gate region and having a second conductivity type, and
(3) a junction-field-effect transistor for current control, having source/drain regions, a channel region and gate portions,
the semiconductor memory cell having;
(a) a semi-conductive first region having a second conductivity type,
(b) a semi-conductive second region which is formed in a surface region of the first region and has a first conductivity type,
(c) a third region which is formed in a surface region of the second region and is in contact with the second region so as to form a rectifier junction together with the second region,
(d) a semi-conductive fourth region which is formed in a surface region of the first region and spaced from the second region and which has the first conductivity type,
(e) a fifth region which is formed in a surface region of the fourth region and is in contact with the fourth region so as to form a rectifier junction together with the fourth region, and
(f) a gate region which is formed on an insulation layer so as to bridge the first region and the third region and so as to bridge the second region and the fourth region and is shared by the first and second transistors,
wherein:
(A-1) one source/drain region of the first transistor is formed of a surface region of the second region,
(A-2) the other source/drain region of the first transistor is formed of a surface region of the fourth region,
(A-3) the channel forming region of the first transistor is formed of a surface region of the first region which surface region is interposed between said surface region of the second region and said surface region of the fourth region,
(B-1) one source/drain region of the second transistor is formed of said surface region of the first region which surface region forms the channel forming region of the first transistor,
(B-2) the other source/drain region of the second transistor is formed of the third region,
(B-3) the channel forming region of the second transistor is formed of said surface region of the second region which surface region forms the one source/drain region of the first transistor,
(C-1) the gate portions of the junction-field-effect transistor are formed of the third region and a portion of the first region which portion is opposed to the third region,
(C-2) the channel region of the junction-field-effect transistor is formed of a portion of the second region which portion is interposed between the third region and said portion of the first region,
(C-3) one source/drain region of the junction-field-effect transistor is formed of said surface region of the second region which surface region extends from one end of the channel region of the junction-field-effect transistor and forms the one source/drain region of the first transistor,
(C-4) the other source/drain region of the junction-field-effect transistor is formed of a portion of the second region which portion extends from the other end of the channel region of the junction-field-effect transistor,
(D) the gate region is connected to a first line for memory cell selection,
(E) the third region is connected to a write-in information setting line,
(F) the fourth region is connected to a second line, and
(G) the fifth region is connected to the first region,
and further wherein:
when the semiconductor memory cell is cut with a first imaginary perpendicular plane which is perpendicular to the extending direction of the gate region and passes through the center of the gate region, the second region and the fourth region in the vicinity of the gate region are symmetrical with respect to a second imaginary perpendicular plane which is in parallel with the extending direction of the gate region and passes through the center of the gate region.
Differing from the semiconductor according to the third aspect of the present invention, the fifth region does not take part in the constitution of the junction-field-effect transistor. Since, however, the fifth region and the first region are connected to each other, a region where information is to be stored can be increased, and the length of time period for which the semiconductor memory cell stores information can be increased.
The junction-field-effect transistor (JFET) or the second junction-field-effect transistor in the semiconductor memory cell according to each of the third to fifth aspects of the present invention can be formed by
(i) optimizing the distance between the opposing gate portions of each junction-field-effect transistor (thickness of the channel region), and
(ii) optimizing the impurity concentration of the opposing gate portions of each junction-field-effect transistor and the impurity concentration of the channel region of each junction-field-effect transistor.
When the distance between the gate portions (thickness of the channel region) and the impurity concentration of each of the gate portions and the channel region are not optimized, a depletion layer does not broaden, and no ON-OFF operation of each junction-field-effect transistor can be obtained. The above optimization is required to be attained by computer simulation or experiments.
Further, in the semiconductor memory cell according to the third, fourth or fifth aspect of the present invention, preferably, when semiconductor memory cell is cut with the above first imaginary perpendicular plane, the third region and the fifth region in the vicinity of the gate region are nearly symmetrical with respect to the above second imaginary perpendicular plane.
In the semiconductor memory cell according to the third aspect of the present invention, it is preferred to employ a constitution in which the second region is connected to a fourth line, the second line is used as a bit line and a predetermined potential is applied to the fourth line, or a constitution in which the second region is connected to a fourth line, the fourth line is used as a bit line and a predetermined potential is applied to the second line.
In the semiconductor memory cell according to the fourth or fifth aspect of the present invention, it is preferred to employ a constitution in which the second region is connected to a third line, the second line is used as a bit line and the a predetermined potential is applied to the third line, or a constitution in which the second region is connected to a third line, the third line is used as a bit line and a predetermined potential is applied to the second line.
Alternatively, in the semiconductor memory cell according to the third, fourth or fifth aspect of the present invention including various variants, for simplification of a wiring structure, it is preferred to employ a constitution in which a diode is formed of the second region and the third region, and the second region is connected to the write-in information setting line through the third region. In this case, it is preferred to employ a constitution in which the second line is used as a bit line, or a constitution in which the write-in information setting line is used as a bit line as well and a predetermined potential is applied to the second line.
When the third region is formed of a semi-conductive region having an opposite conductivity type to the second region, the diode is a pn junction diode, and the pn junction diode can be formed by adjusting impurity concentrations of these regions forming the pn junction diode to proper values. When potentials in the regions forming the pn junction diode are set improperly, or when designing of the relationship of the impurity concentrations in these regions is improper, carriers injected from the above pn junction diode may latch up the semiconductor memory cell.
For avoiding the above failure, it is preferred to employ a constitution in which a diode-constituting region is formed in a surface region of the second region to be in contact with the second region so as to form a rectifier junction together with the second region, a majority carrier diode is formed of the diode-constituting region and the second region, and the second region is connected to the write-in information setting line through the diode-constituting region. The diode-constituting region is preferably made from a material which forms a Schottky junction or an ISO type hetero-junction in which such a diode operates on the basis of majority carriers in the second region and majority carriers are not injected even when a forward-direction bias is applied to the junction portion. That is, the rectifier junction is preferably a majority carrier junction such as a Schottky junction or an ISO type hetero-junction. The term xe2x80x9cISO type hetero-junctionxe2x80x9d refers to a hetero-junction formed between two semi-conductive regions which have an identical conductivity type but are different in kind. Particulars of the ISO type hetero-junction are described in xe2x80x9cPhysics of Semiconductor Devicesxe2x80x9d, S. M. Sze, 2nd Edition, page 122 (issued by John Wiley and Sons). In the above Schottky junction or ISO type hetero-junction, the forward-direction voltage is lower than the forward-direction voltage in a pn junction. The majority carrier diode having the above properties can avoid the latch-up phenomenon. The Schottky junction can be formed when the diode-constituting region is made of a metal such as aluminum, molybdenum or titanium or silicide such as TiSi2 or WSi2. The ISO type hetero-junction can be formed when the diode-constituting region is made of a semi-conductive material which differs from a material constituting the second region and which has the same conductivity type as the conductivity type of the second region. The diode-constituting region may be made of the same material as a material (for example, titanium silicide or TiN for use as a barrier layer or a glue layer) used for constituting the write-in information setting line. That is, there can be employed a structure in which the diode-constituting region is formed in a surface region of the second region and the so-formed diode-constituting region is used as part of the write-in information setting line. The above structure in which xe2x80x9cthe diode-constituting region is used as part of the write-in information setting linexe2x80x9d also includes a state where the diode-constituting region is made of a compound formed by a reaction between a wiring material and silicon of a silicon semiconductor substrate.
In the semiconductor memory cell according to the second aspect of the present invention, preferably, an impurity-containing layer having the second conductivity type is formed in a surface region of the fourth region forming the channel forming region of the third transistor. In this case, when information is retained, and when the potential of the first line is set at 0 volt, the third transistor is brought into an ON-state, and the fifth region and the first region are brought into a conduction sate. Preferably, the impurity content of the impurity-containing layer is adjusted such that the third transistor is brought into an OFF-state by a potential which is applied to the first line when information is read out.
The semiconductor memory cell of the present invention may be formed in a surface region of a semiconductor substrate, on an insulating layer formed on a semiconductor substrate, in a well structure formed in a semiconductor substrate or on an insulator. For coping with a soft-error caused by a particle or neutron, preferably, the semiconductor memory cell is formed in a well structure or on an insulator (insulating layer), or it has a so-called SOI structure or a TFT structure. The insulator or insulating layer may be formed not only on a semiconductor substrate, but also on a glass substrate or a quartz substrate.
In the semiconductor memory cell of the present invention, it is preferred to form a high-impurity-concentration layer having a first conductivity type below the first region, since, in this case, the potential or charge stored in the channel forming region of the first transistor can be increased.
The channel forming region can be made from silicon, GaAs or the like according to a conventional method. The gate region of the first transistor or the second transistor can be made from a metal, an impurity-containing silicon, an impurity-containing amorphous silicon, an impurity-containing polysilicon, silicide, or GaAs containing a high concentration of an impurity, according to a conventional method. The insulation layer can be made from SiO2, Si3N4, Al2O3 or GaAlAs according to a conventional method. Each region can be made from an impurity-containing silicon, an impurity-containing amorphous silicon, an impurity-containing polysilicon, silicide, silicon-germanium (Sixe2x80x94Ge) or GaAs containing a high concentration of an impurity according to a conventional method depending upon required properties and structure thereof.
In the semiconductor memory cell of the present invention, the third region may be made from silicide, a metal or a metal compound depending upon required properties. However, the third region is preferably made from a semiconductor. Further, the fifth region may be made from a semiconductor, or it may be made from silicide, a metal or a metal compound.
In the present invention, when the semiconductor memory cell is cut with the first imaginary perpendicular plane, the second and fourth regions in the vicinity of the gate region are symmetrical with respect to the second imaginary perpendicular plane, and in some constitutions, further, the third and fifth regions in the vicinity of the gate region are symmetrical with respect to the second imaginary perpendicular plane. Therefore, the freedom during designing or production of the semiconductor memory cell can be increased.
In the semiconductor memory cell of the present invention, further, the gate region is common to the first transistor and the second transistor and is connected to the first line for memory cell selection, so that one line is sufficient for the first line for memory cell selection, which serves to decrease a chip area. Further, since the first transistor for readout and the second transistor for switching are merged into one unit, so that a cell area can be decreased and that a leak current can be decreased.
In the semiconductor memory cell of the present invention, the ON-OFF state of the first transistor and the second transistor can be controlled by selecting a proper potential in the first line for memory cell selection. That is, when information is written in, the potential of the first line for memory cell section is set at a level at which the second transistor is sufficiently turned on. Therefore, the second transistor is brought into conduction, and a charge is stored in a capacitor formed between the channel forming region and one source/drain region of the second transistor depending upon a potential of the write-in information setting line. As a result, information is stored in the channel forming region of the first transistor in the form of a potential difference between the channel forming region of the second transistor and the channel forming region of the first transistor, or a charge. When the information is read out, the potential of the source/drain region of the first transistor comes to be a readout potential, and in the first transistor, the potential or charge (information) stored in the channel forming region is converted to a potential difference between the channel forming region and the other source/drain region or a charge, and the threshold value of the first transistor, seen from the gate region, changes depending upon the above charge (information). When information is read out, a properly selected potential is applied to the gate region, whereby the ON-OFF operation of the first transistor can be controlled. The operation state of the first transistor is detected, whereby the information can be read out.
Further, a diode obviates the third line which is to be connected to one source/drain region (second region) of the first transistor. In the above semiconductor memory cell of the present invention, when the potentials are improperly set in the regions constituting the diode, or when the impurity concentration relationship of these regions is designed improperly, a latch-up phenomenon may take place during writing of information if the voltage applied to the write-in information setting line is not at a low level (for example, smaller than, or equal to, 0.4 volt when the junction is a pn junction) at which no large forward-direction current flows in the junction portion of the third region and the second region. For avoiding the latch-up phenomenon, there is provided a method as is already explained, in which a diode-constituting region is formed in a surface region of the second region, and the diode-constituting region is made of a silicide, a metal or a metal compound, to form a Schottky junction or an ISO type hetero-junction as a junction of the diode-constituting region and the second region, so that majority carriers mainly constitute a forward-direction current.
In the semiconductor memory cell according to any one of the third to fifth aspects of the present invention, further, the junction-field-effect transistor is provided in addition to the first transistor of a first conductivity type and the second transistor of a second conductivity type. The ON-OFF operation of the junction-field-effect transistor is controlled when the information is read out, so that a margin of a current which flows between the source/drain regions of the first transistor can be remarkably broadened. As a result, there is almost no limitation to be imposed on the number of the semiconductor memory cells that can be connected, for example, to the second line. Further, when the third transistor for current control is provided, the ON-OFF operation is controlled during reading of information, so that a margin of a current which flows between the source/drain regions of the first transistor can be more reliably remarkably broadened. As a result, the number of the semiconductor memory cells that can be connected, for example, to the second line is limited to a far less degree.
The semiconductor memory cell of the present invention retains information in the form of a potential, a potential difference or a charge, while it is attenuated by a lead current such as junction leak and a refreshing operation is required. The semiconductor memory cell therefore operates like DRAM.


In a coordinate measuring machine or any other kind of machine having at least one translational movement axis, correction values are determined by moving the mobile head of the machine along a defined path of movement. First and second position data are recorded by means of first and second position measuring devices. The first position data originate from position measuring devices of the machine. The second position data result from a reference measurement. The correction values are determined as a function of the first and second position data. A defined number of correction values is determined for each section of the path of movement, with the defined number varying in the sections as a function of the error profile defined by the correction values.

The present invention relates to a method for determining correction values for correcting positional measurement errors in a machine having at least one translational movement axis, such as, in particular in a coordinate measuring machine. The invention further relates to a coordinate measuring machine having a memory for storing correction values which have been determined in accordance with such a method.
Coordinate measuring machines are typically used to measure the shape of a measurement object with high accuracy. For example, coordinate measuring machines are used to check the shape of workpieces for quality control. A coordinate measuring machine has a displacement mechanism which enables a probe to move inside a measurement volume. The probe is brought into a defined position relative to the measurement object, and subsequently the spatial coordinates of the measuring points are determined from the position of the probe in the measurement value.
The probe often carries a stylus designed for contacting the selected measuring point on the measurement object in order to initiate the determination of the spatial coordinates. As an alternative, however, there are also heads which sense the measurement object without making contact, for example by means of optical means. The present invention is independent of the type of probing. It relates to all coordinate measuring machines and, moreover, to any other machines, where a head is moved via a displacement mechanism along at least one translational axis of movement. Thus, the invention can, for example, also be applied in the case of machine tools, EDM machines or robots. The head is then, for example, a tool holding fixture.
For sake of simplicity, however, the invention is illustrated below for the preferred application of a coordinate measuring machine, since here the requirements placed on the measuring accuracy for the sensing of position are particularly high.
The current spatial position of the head is determined by means of what is called material measures (or material representations) in the case of known coordinate measuring machines. Said material measures are often glass bars on which a scale is applied. Position data for the position of the head are read off at the material measures by means of a suitable sensor system.
However, it is known that the accuracy in the determination of the spatial position of the head is limited. In other words, each measurement is affected by measurement errors. The measurement errors have various causes. These include the limited accuracy with which material measures can be produced. This holds true, in particular, in the case of large coordinate measuring machines in which the material measures must be assembled from a number of parts. However, even in the case of relatively small coordinate measuring machines small manufacturing tolerances in the material measures are already enough to affect the measuring accuracy of the machine. It can happen that only a few of a plurality of "equal" material measures are suitable for the desired accuracy of a coordinate measuring machine. Sometimes, defects in the material measures come to light only after they have been installed in the coordinate measuring machine, and this is particularly disadvantageous since the "poor" material measures must subsequently be exchanged. The production costs of a coordinate measuring machine therefore depend strongly on the quality and the costs of the material measures.
It is known to compile correction value tables (or error tables) and make them available in a memory of the coordinate measuring machine in order to reduce the inevitably remaining measurement errors. For this purpose, the head of the coordinate measuring machine is moved along defined path of movements. The positions of the head are recorded both with the position measuring devices of the coordinate measuring machine itself, and with second position measuring devices. It is usually laser interferometers and what is called inclination scales which serve as second position measuring devices in this sense. The position data of these second position measuring devices are adopted as "true" position data, and correction values are determined from the comparison with the first position data of the coordinate measuring machine. These correction values are taken into account in the measurements. Such a method is described, for example, in DE 1 638 032 A1.
The accuracy of this error correction depends, inter alia, on how "finely meshed" the network of the correction values is. The greater the spacings at which correction values are determined, the more likely it is for position-specific errors (so-called short-period errors) not to be detected and, consequently, not to be corrected. Consequently, a "finely meshed" network of correction values is desirable for a high accuracy.
However, the determination of many correction values is time consuming, particularly for large coordinate measuring machines, such as are used, for example, in order to measure entire motor vehicle bodies. Moreover, large correction value tables require a great deal of memory space in the control and evaluation unit of the coordinate measuring machine. Both factors contribute to high production costs.
On the other hand, it is just large coordinate measuring machines having assembled material measures which are particularly susceptible to position-specific errors, in particular at the joints of the multipartite scales. There is a range of proposals for avoiding or at least reducing such errors.
An overview of the prior art is given by DE 197 24 732 A1, which describes a modular scale in which the joints of the assembled scale are positioned such that they lie as distant as possible from the joints of an associated carrier element. Thus, an attempt is made here to improve the quality of assembled scales.
DE 101 62 849 A1 proposes that a scale which is shorter than the measuring volume is moved relative to the position of a number of sensors spaced apart from one another, one of the sensors respectively being selected for the measuring. The disadvantage of this proposal is a need for a plurality of sensors, which is expensive. DE 196 21 015 C2 also proposes to increase the accuracy in the region of joints of an assembled scale by making use of a number of sensors. Moreover, it is known to identify the joints of scales by specific code fields (DE 38 18 044 A1), or to provide setting screws by means of which the spacing of the scale parts in the region of a joint can be adjusted (DE 27 27 769 C2). The additional outlay increases the production costs of the coordinate measuring machine in all cases.

Method for determining correction values for correcting positional measurement errors in a machine having at least one translational axis of movement

Carl Zeiss Industrielle Messtechnik GmbH


A wound dressing includes an hydrophilic foam layer which is coated with a liquid-permeabe adhesive layer on one side. The dressing includes an absorbent layer disposed on the foam layer on the side opposite to the adhesive coating, wherein absorbent layer is able to drain the foam layer through the action of capillary forces, and wherein the dressing further includes elements that ensure effective contact between the absorbent layer and the foam layer.

The present invention relates to a wound dressing that includes an hydrophilic foam layer that is covered on one side with a liquid permeable adhesive layer.
Weeping wounds or sores are typically treated with wound dressings that include a pad which absorbs surplus fluid exuding from the wound. The fluid, or semifluid, absorbed by the pad spreads laterally in the dressing and may reach the skin which lies around the edges of the wound and which then comes into contact with the fluid. This fluid contact is potentially harmful to the skin, as it may result in maceration of the skin or damage the skin in some other way. This is a highly common complication in the treatment chronic wounds and sores.
Another problem is that the change of dressings will often have a deleterious affect on the healing process.
An object of the present invention is to provide a wound dressing with which the risk of skin maceration is reduced and with which that part of the wound pad that lies proximal to the wound is kept free from fluid until the pad becomes saturated. Another object of the invention is to provide a two-layer dressing that includes a drainable first layer of hydrophilic foam that lies nearest the wound. This layer can be left on the wound, or sore, over a long period of time whereas a second layer that functions to drain the first layer can be changed at regular intervals.
These objects are achieved with a wound dressing which comprises an hydrophilic foam layer that is coated with a layer of liquid-permeable adhesive on one side, wherein the dressing is characterized by an absorbent layer disposed on the foam layer on the opposite side of the adhesive coating and which has the ability to drain the foam layer by capillary action; and in that the dressing includes means for ensuring that good contact is obtained between the absorbent layer and the foam layer. The capillary forces in the layer of absorbent material act to empty the foam layer of fluid, therewith essentially eliminating the risk of skin maceration. This enables the foam layer to remain on the wound bed for a longer period of time without needing to be chanced.
In one preferred embodiment of the invention, the hydrophilic foam layer has a maximum thickness of 2 mm and a mean cell size of 300-500 xcexcm. The adhesive coating is comprised of a soft, sticky, hydrophobic elastomer.
The invention also relates to a wound dressing intended for co-action with an absorbent body, wherein the dressing is characterized by an hydrophilic foam layer which has on one side an adhesive coating that extends over the whole of its surface without blocking or clogging the pores of said layer, wherein said layer has a thickness of at most 2 mm and a mean cell size of 300-500 xcexcm.