In one embodiment, a sliced tunnel is signaled between a head-end node and a tail-end node. One or more fork nodes along the sliced tunnel are configured to furcate the sliced tunnel into a plurality of child tunnels of the sliced tunnel. Also, one or more merge nodes along the sliced tunnel are configured to merge a plurality of child tunnels of the sliced tunnel that intersect at the merge node.

Path computation for tunnels of a computer network, e.g., label switched paths (LSPs), typically results in tunnels that traverse a single path, whether that path is a point-to-point (P2P) path, point-to-multipoint (P2 MP) path, etc. For example, tunnels in many Multi-Protocol Label Switching (MPLS) Traffic Engineering (TE) networks (e.g., MPLS TE-LSPs) are computed using a constrained shortest path first (CSPF) algorithm. As those skilled in the art will understand, CSPF offers high flexibility and scalability, and is well-equipped to handle frequent topology changes, dynamic traffic demands, and resource availability changes. According to CSPF (for example), when a tunnel is built to satisfy a bandwidth constraint of "X", the tunnel only follows a single path between a head-end node and one or more tail-end node of tunnels (e.g., the shortest path).
In the event the bandwidth constraint X is greater than the available bandwidth of links between the head and tail-end nodes, then no single path is available for the tunnel (i.e., the bandwidth constraint cannot be satisfied). Currently, if a tunnel requires a bandwidth greater than what is available along a single path between the head and tail-end nodes, the only way to satisfy the constraint is to establish multiple tunnels between the head and tail-end nodes whose reserved bandwidths are each smaller than X and when combined total X (or greater than X). Similarly, if there are multiple parallel links/circuits available between a pair of nodes along a tunnel's path, the tunnel may only utilize one of them. In order to utilize the multiple parallel links, multiple corresponding tunnels must be created from a head-end node where each follows the same path but over a different parallel link.
In either situation above, the respective head-end node of the multiple tunnels is thus required to load balance traffic between the multiple tunnels. Also, in many instances, these multiple tunnels share various links between the head and tail-end nodes (e.g., where those shared links have available bandwidth greater than X), resulting in an increased number of tunnels on those shared links. For example, as mentioned above, if two intermediate nodes along a path have ten parallel links between them, each having one tenth of the bandwidth X, a head-end node would need to establish ten tunnels along the entire path in order to utilize those ten parallel links. As such, each other link/node along the path may be required to maintain those ten tunnels. These multiple tunnels may be a burden to the head-end node and intermediate nodes to maintain, and generally do not scale well (particularly for long paths requiring many tunnels).
Note, also, that one or more of these issues apply to backup tunnels, such as those offering bandwidth protection where it is difficult to compute a single backup tunnel that supports the entire amount of protected bandwidth. In particular, multiple backup tunnels at a point of local repair (PLR) for a protected tunnel are generally difficult to maintain, as will be understood by those skilled in the art (e.g., selection of a single backup tunnel requiring packing algorithms, etc.). Also, even if a particular path could satisfy the bandwidth constraint of a backup tunnel it may be more desirable to spread the backup load amongst several paths if possible.


A computer system and method for providing user feedback when creating, modifying, or editing electronic documents. An insertion point icon is placed in a document at a position for insertion and/or deletion of text, graphics, data, etc. Upon receiving a user input indicating movement, the insertion point icon is divided into two icons, one stationary at the position, and one moving with user input. When movement is complete, space contained between the icons may be deleted or inserted. The system may be used to shift handwritten text to subsequent lines on an electronic document containing handwritten text, and may be used to bring two groups of text together, deleting space in between. A connection line may be displayed between the icons to provide feedback regarding the action to be taken.

The use of computers and/or computing systems to generate textual documents has become an established practice in today's Computer Age. Through the use of a computer, such as a personal computer, and a keyboard (e.g., one having the "QWERTY" key configuration), it is now possible for users to type and create documents of many different types and formats.
Various word-processing programs also provide a certain amount of visual feedback, through a user interface, to provide the user with visual cues as to the effects of the user's actions. For example, in generating an electronic document using the "MICROSOFT® WORD" program, which is a word-processing product offered by Microsoft Corp., many visual cues are provided. One such visual cue is a flashing cursor that appears at a point in the document. The flashing cursor, represented by a vertical line, is the point at which text will appear if the user were to begin typing on the keyboard. In this regard, the location of the cursor may be referred to as the insertion point. The cursor is also the point from which text may be deleted upon pressing an "Insert" or "Delete" key on the keyboard, and may also serve as a first point in highlighting a portion of the document.
However, the use of such a cursor for various editing actions requires the user to study and learn multiple functions and commands, thus complicating the user's interaction with the system. To illustrate, FIG. 3A shows a screen of text from a prior art word processing program. In the FIG. 3A screen, several lines of text 301 may have been generated by the user, for example, by typing the letters on a keyboard. If the user should desire to insert additional space, or text, at a point 302 within the lines of text 301, the user generally is required to position the cursor 303 at the insertion point, and then add spaces or text (by hitting the space bar or keys on a keyboard) to perform the insertion. Carriage returns may also be inserted by pressing the "Enter" or "Return" key on a conventional keyboard. However, with each press of a key (e.g., spacebar), the entire portion of the lines of text 301 beyond the cursor 303 shifts as a result of the addition. If the user wishes to insert 20 spaces, the text might shift 20 times for the spaces. This shifting is disorienting to the user, and complicates the user's interaction with the displayed document.
A similar problem is encountered if the user wishes to "close up" space between two groups of text. To illustrate, FIG. 3B shows another screen of text from a typical word processing program, in which two groups of text 304a, 304b are separated by space 305. If the user wishes to "close up" this space 305 by bringing the two groups of text together, the user typically must either: 1) highlight and delete the spaces and/or carriage returns between the groups of text; or 2) position the cursor at some point within the space 305, and begin pressing "Delete" or "Backspace" keys to delete the various components of space 305 (which may include spaces, tabs, carriage returns, etc.). These operations, however, also complicate the user's computer experience. In option 1, the user must learn how to properly select the entire space area 305, and then learn how to delete or cut the selected space area 305 from the document. An inadvertent selection of more, or less, than space 305 might result in an accidental deletion of some or all of the groups of text 304a, 304b, requiring the user to backtrack and attempt the deletion again. Option 2 involves the deletion of individual spaces, tabs, carriage returns, etc., one at a time. This one-at-a-time deletion may be disorienting to the user as text group 304b may be shifted once for each deletion. On slower machines, the repeated deletions may be affected faster than they are displayed, resulting in over deletions. On faster machines, the rate at which pages scroll is faster than the user's ability to respond, further frustrating the user.
FIGS. 3C-F illustrate another prior art attempt at easing the user's interaction with the displayed document. In the Microsoft® Inkwriter® product, a user could generate multiple lines 330 of text, which could be handwritten using a stylus, and interact with the displayed document using a pointing device (such as the stylus, mouse, etc.). The user could also place a cursor 332 at an insertion point. The cursor 332 would initially have the appearance of an "I-beam," as shown in FIG. 3C. As the user moved a pointer, such as a mouse or stylus pointer 334, over the cursor 332, also known as "hovering" over the cursor 332, a new hover symbol 336 would appear below the cursor 332, as shown in FIG. 3D. If the user were to subsequently "click and drag" the mouse cursor by, for example, pressing a mouse button and moving the mouse, the hover symbol 336 would be replaced by an expanding arrow 338. This "click and drag" may also be performed using a stylus. As the user "dragged" the cursor 332, the expanding arrow 338 would then dynamically indicate the vertical position of the mouse pointer 334, as shown in FIG. 3E, while maintaining the same horizontal position. Upon completing the drag, the text following the cursor 332 is moved to begin as a new line at the final vertical position of the mouse pointer 334.
The Inkwriter® hover symbol 336 and expanding arrow 338 provide some feedback to the user, but this feedback is limited. For example, no additional feedback is provided if the user drags the cursor 332 within the same line (e.g., to the left or right). Additionally, the amount of vertical feedback is limited to a vertical indication only. In the FIG. 3E screen, the expanding arrow 338 does not indicate the horizontal positioning of the pointer 334, resulting in some confusion on the part of the user as to what will happen when the dragging ceases. The operation of the Inkwriter® cursor is also confusing when the user wishes to delete space in a document. In deleting space or text, the Inkwriter® cursor 332 behaves as described above with respect to FIGS. 3C-E, resulting in a feedback display as shown in FIG. 3G. In the FIG. 3G screen, the expanding arrow 338 similarly provides limited feedback regarding exactly what text, if any, will be deleted when the dragging is completed.
The user's computer experience is complicated by these forms of editing feedback, which is undesirable from a computer-usability standpoint. Consequently, there is a need for a more intuitive and user-friendly form of feedback when editing documents with a computer. This need is further heightened in any computer system that attempts to simplify a user's computer experience.

This patent is subject to a terminal disclaimer.


An integrated human and computer interactive data mining method receives an input database. A learning, modeling, and analysis method uses the database to create an initial knowledge model. A query of the initial knowledge model is performed using a query request. The initial knowledge model is processed to create a knowledge presentation output for visualization. It further comprises a feedback and update request step that updates the initial knowledge model.

During the last decade, there is an explosive growth in the capabilities to both generate and collect data. Advances in data collection, widespread use of bar codes for most commercial products, and the computerization of many business and government transactions have flooded us with information. In calendar year 2000, it is estimated that about 1 Exabyte (=1 million Terabyte) of data was generated and the trend is accelerating. The data collected could be a source of valuable information. However, finding valuable information and synthesizing useful knowledge hidden in them is a non-trivial task. Without adequate means to explore the large amount of data, the data becomes useless and the databases become data "dumps".
There is an urgent need for new techniques and tools that can intelligently and automatically assist a user in transforming data into useful knowledge. The emerging field of data mining and knowledge discovery in databases (KDD) creates significant research and product interests. Data mining can be defined as "The nontrivial extraction of implicit, previously unknown, and potentially useful information from data". Statistics, databases, machine learning, artificial intelligence and visualization techniques are applied in an attempt to discover and present knowledge in a form which is easily comprehensible to a human. Data mining related researches span classification and clustering, trend and deviation analysis, dependency modeling, integrated discovery systems, next generation database systems, visualization, and application case studies. Many tools and services are commercially available such as Decisionsite from Spotfire (Spotfire, http://www.spotfire.com/products/decision.asp), Insightful Miner from Insightful (Insightful, http://www.insightful.com/products/product.asp?PID=26), Clementine from SPSS(SPSS, http://www.spss.com/spssbi/clementine/index.htm), VisuaLinks from Visual Analytics (Visual Analytics, Inc. www.visualanalytics.com), Enterprise Miner from SAS (SAS Institute Inc. www.sas.com). However, there is only limited success in the adoption of the data mining technologies and tools for practical applications.
The prior art approach falls into two extremes. In one extreme, it relies heavily on a human's ability to search the database, understand detailed meaning of feature attributes and ability to comprehend statistics and learning methods. We call this approach the human dominated method. A visual data mining method (Keim Daniel, "Information Visualization and Visual data Mining", IEEE Trans. on Visualization and Computer Graphics, Vol. 7, No 1, January–March 2002) was developed that uses special visualization techniques to facilitate users direct involvement in the data mining process. Visual data mining techniques prioritize and display relations between data fields to harness the enormous human visual information processing capacity in order to rapidly traverse large information spaces and facilitate comprehension with reduced anxiety. However, it falls short of empowering users to harness vast data for efficient discovery of novel and important information. For noisy and inhomogeneous data sets it becomes ineffective because it cannot help the human separate strong data from weak data or exhibit the effects of strong or weak decisions. Unfortunately, some of the most important opportunities for data mining (i.e. geology, natural resource exploration, biomedical drug discovery, experimental physics) are characterized by weak and noisy data. This results in inconsistent data mining performance and it is difficult to create highly novel concepts and knowledge. This approach is also extremely inefficient when the database being explored is large.
The other extreme of the prior art approach heavily relies on a computer to automatically generate rules and discover knowledge from data (Ian H. Witten, Eibe Frank "Data Mining: Practical Machine Learning Tools and Techniques with Java Implementations", Morgan Kaufmann, October 1999.) We call this approach the computer dominated method. The automatic method relieves a human of the responsibility for deciding on the significance and relationships between the data. Unfortunately, the methods are very limited and rely on assumptions, which are often not valid in practical applications. When a mismatch exists between the assumptions and application situations, the automatically generated knowledge could be worse than useless since the knowledge indicated is not valid and may mislead the human. As application demand and data complexity are increasing, a general-purpose fully automatic data mining/knowledge discovery technology is not in sight. The path to success is the integration of human direction with computer inputs from automatic learning results. Existing software that allows users to effectively create data models and reach conclusions with measurable confidence are created only through arduous icon based programming tasks, and the data models are difficult to modify and understand. This interaction is reluctant, slow, costly and manual. Furthermore, most of the automatic learning methods do not support incremental update. So human feedback is not easily incorporated to refine the automatically generated knowledge. This invention bridges the gaps between the human dominated method and the computer dominated method. It lays the foundation for next generation integrated intelligent human/computer interactive data mining.
The effectiveness of human data mining could be greatly improved if the visualization of data could be effectively ranked and clustered according to the strength of the data and the strength of decision processes. Furthermore, counter examples could be shown through a contrasting approach that facilitates human discovery of subtle differences. The hierarchic structure of the regulation tree of this invention naturally maps to information granularity. This is an ideal representation that supports multi-level abstraction data mining process: overview, zoom and filter, details-on-demand.

Dynamic learning and knowledge representation for data mining

Abstract: A multiple level integrated human and computer interactive data mining method facilitates overview interactive data mining and dynamic learning and knowledge representation by using the initial knowledge model and the database to create and update a presentable knowledge model. It facilitates zoom and filter interactive data mining and dynamic learning and knowledge representation by using the presentable knowledge model and the database to create and update the presentable knowledge model. It further facilitates details-on-demand interactive data mining and dynamic learning and knowledge representation by using the presentable knowledge model and the database to create and update the presentable knowledge model.

Abstract: The integrated human and computer interactive data mining method allows rule viewing by a parallel coordinate visualization technique that maps a multiple dimensional space onto two display dimensions with data items presented as polygonal lines.


A gate antenna device has a plurality of loop antennas which supplies power and transmission data to an IC-integrated medium through electromagnetic induction and acquires reception data in the form of a fluctuation of a load from the IC-integrated medium. The plurality of loop antennas include a power-fed loop antenna to which a signal current is supplied and a non-power-fed loop antenna to which no signal current is supplied. The gate antenna device expands the distance and range of communication with an IC-integrated medium and improves the accuracy of communication while suppressing power consumption and leakage electric fields.

It is an object of the present invention to provide a gate type antenna device which is preferably used in an IC-integrated media reader or reader/writer for supplying power and transmission data to an IC-integrated medium, e.g., a non-contact IC card and acquiring reception data in the form of load fluctuations from the non-contact IC card.
For purposes such as authentication and sorting of destinations of baggage, it is becoming common to use IC-integrated media having ID codes such as IC cards and IC tags and IC-integrated media readers and IC-integrated media readers/writers for authenticating ID codes of such IC-integrated media. When an IC-integrated medium enters a communication range of an antenna of an IC-integrated media reader, an electromagnetic wave from the antenna generates an induction voltage at an antenna of the IC-integrated medium, and the voltage is rectified into power and transmission data which are then supplied to the IC. In the IC-integrated medium to which the power has been thus supplied, according to data read from a memory incorporated therein, a switch is turned on/off according to 1s and 0s in the data by, for example, a modulation circuit which is formed by a load resistance and a switch and which is connected to the antenna. The switching on/off results in a fluctuation of a load applied to the antenna of the IC-integrated medium, and the load fluctuation is transmitted to the antenna of the IC-integrated media reader or reader/writer as a signal. The transmitted signal is demodulated by the IC-integrated media reader or reader/writer to allow execution of authentication of the ID code (for example, see JP-A-1-126785 and JP-A-2000-163523).
In this connection, there is demand for capability of authenticating ID codes of IC-integrated media, for example, by passing baggage or commodities to which the IC-integrated media are attached through a baggage gate at an airport or an entrance or exit of a store. The capability of authenticating ID codes of IC-integrated media is also desired for purposes like checking of the inventory of a commodity which is placed in a commodity showcase and to which an IC-integrated medium is attached. Under the circumstance, it is desired to use an antenna having stable characteristics to prevent erroneous reading and writing. For this reason, antennas which are fed with very high power and which radiate strong electromagnetic waves are used to allow data to be transmitted and received to and from IC-integrated media with high reliability.
In the related art in which a gate antenna device having a plurality of antennas is supplied with power at all of the antennas as disclosed in Japanese Patent Laid-Open No. JP-A-2003-258545, a problem has arisen in that power consumption increases and in that correction of phase shifts of a reception signal on the different antennas is required especially in communicating with a radio communication medium for mutual data communication.
However, the strength of a leakage electric field from induction-type read/write communication facility is limited to a distance of 10 meters by the Radio Law, and the use of an antenna that supplies high power in the excess of the limit is restricted. For this reason, a limit has been placed on efforts toward increases in power fed to an antenna for reliable communication with an IC-integrated medium. The term "IC-integrated media" implies not only IC media such as IC tags, IC cards, ID tags, and ID cards but also various other media which allow radio communication on a non-contact basis.
An increase in the level of power fed to an antenna results in a reduction of a communication range, which has led to a problem that communication with an IC-integrated medium becomes unsatisfactory.
A multiplicity of antennas may be provided in order to expand the range of communication with an IC-integrated medium. When a multiplicity of antennas is provided, however, a problem arises in that there will be a corresponding increase in power consumption, and this is disadvantageous for construction of a system for which low power consumption is desired. 1. Field of the Invention

Matsushita Electric Industrial Co., Ltd.


An ATM network carries several categories of services, each having its own traffic characteristics and performance requirements. The ABR (available bit rate) service category is the only existing one suited for high-reliability data communications, such as file transfer, LAN emulation, etc. The invention relates to the control of ABR traffic flow in an ATM network, to quickly utilize the bandwidth left unused by higher priority service categories while minimizing ABR cell loss, and maintaining fairness among ABR connections. On each ABR connection, the source end system periodically sends RM (resource management) cells to the corresponding destination end system which loops them back to the source. The ATM network may instruct the ABR sources of the exact rates it can support by modifying a certain field in the RM cells. The invention relates to techniques of deriving the proper explicit cell rate for each ABR connection which can grow to a fair level even under special conditions.

ATM is a high speed connection oriented packet switching technique where information is organized into fixed length packets, called cells. In general terms, an ATM network is a collection of end systems interconnected through one or more ATM switches. On a connection, generally, an end-system both sends data to the other end systems on the network involved in the connection, and receives data from other end systems on the network involved in the connection. When an end system is a sender of data, it is referred to as a source; it is referred to as a destination when it is a receiver of data. Typically an end system acts as both source and destination.
The following documents are referred to as prior art;
[1] "ATM Forum Traffic Management Specification, Version 4.0" (Draft), S. S. Sathaye, ATM Forum/95-0013R9, December 1995. PA1 [2] "Enhanced PRCA (Proportional Rate-Control Algorithm)", L. Roberts, ATM Forum/94-0735R1, August 1994. PA1 [3] "NIST ER Switch Mechanism (An Example)," N. Golmie et al., ATM Forum/95-0695, June 1995. PA1 [4] "Intelligent Congestion Control for ABR Service in ATM Networks," K.-Y. Siu and H.-Y. Tzeng, Computer Communication Review, Vol. 24, No. 4, pp. 81-106, October 1995. PA1 [5] "Example Switch Algorithm for Section 5.4 of TM spec," A. Barnhart, ATM Forum/95-0195, February 1995. PA1 [6] "A Sample Switch Algorithm," R. Jain et al, ATM Forum/95-0178R1, February 1995. PA1 [7] "ERICA+: Extensions to the ERICA Switch Algorithm," R. Jain et al, ATM Forum/95-1346, October 1995. PA1 [8] "The Rate-Based Flow Control Framework for the Available Bit Rate ATM Service," F. Bonomi and K. Fendick, IEEE Network, Vol. 9, No. 2, pp. 25-39, March/April 1995. PA1 [9] Applicant's pending application Serial No. 08/634,488 filed on Apr. 18, 1996, "Flow Control of ABR Traffic in ATM Networks", now U.S. Pat. No. 5,754,530 issued on May 19, 1998. PA1 First, CCR represents the maximum rate that the VC can use (i.e. ACR) at the time the RM cell was transmitted by the source. However, it is expected that an ABR VC may not use all of its ACR, and thus ACR will be larger than the actual rate of the VC. Therefore, CCR does not necessarily reflect the actual rate of the VC, even just before the RM cell is transmitted (by the source). PA1 Second, when the RM cell is received by an intermediate switch and its CCR field is read by the switch, the CCR field will be too old to even reflect the current value of ACR back at the source, not to mention its current actual rate. PA1 Third, a bad (but perhaps smart) source may insert the wrong ACR value in its CCR field, hoping to acquire more rate by doing so. If this happens with any of the known ABR switch mechanisms, the network may suffer (in terms of buffer overflows, etc.) and major fairness problems may arise.
According to [1] above, five service categories, differing in traffic characteristics and/or service guarantees, are defined for ATM networks. They are: (1) CBR (constant bit rate); (2) rt-VBR (real-time variable bit rate); (3) nrt-VBR (non-real-time variable bit rate); (4) UBR (unspecified bit rate); and (5) ABR (available bit rate).
ABR is the most recent among the above service categories. ABR is intended mainly for non-real-time data applications with varying and/or unknown bandwidth requirements and which cannot be easily characterized in terms of a peak cell rate, a sustainable cell rate, and a maximum burst size. Furthermore, it is the only one among the above service categories that is inherently closed loop. Example types of applications for ABR are any UBR application for which the user wants a more reliable service, critical data transfer (e.g. defence information), super computer applications and data communications applications requiring better delay behavior, such as remote procedure call, distributed file service (e.g. NFS), or computer process swap/paging [1].
The source of an ABR VC (virtual connection) periodically creates and sends special control cells called RM (resource management) cells which travel through the same path as data cells of the VC all the way to the destination of that VC. The destination then loops these cells back to the source through the same path. When an RM cell is traveling from the source to the destination, it is referred to as a forward RM cell; when it is traveling from the destination to the source, it is referred to as a backward RM cell. FIG. 1 shows an RM cell with all of its fields. FIG. 2 shows those fields which have bearings on the present invention. As seen in FIG. 2, some of these fields are intended for information-sharing only and are thus read-only fields and others are read/write fields which may be modified by intermediate switches and/or the destination.
The source adjusts its ACR (allowed cell rate) based on the feedback carried by returning RM cells. ACR represents the rate the source is using to control its cell transmission for VC. The value of a particular forward RM cell is inserted in that cell's CCR field at the time of its transmission. It is expected that end systems which comply with the source and destination reference behaviors as recommended by the above-cited ATM Forum Specification [1], will experience a low cell loss ratio and obtain a fair share of the available bandwidth. According to one definition, a fair share for a VC will be a function of its MCR (minimum cell rate) that is negotiated during connection setup, as well as the MCRs of the other VCs sharing with it one or more links.
Five different fairness criteria are described in Section I.3 of [1]. The first criterion (called "Max-Min") only applies to the case where all ABR VCs are unweighted (or equally weighted) and with zero MCRs; both restrictions are unrealistic. The third criterion (called "Maximum of MCR or Max-Min share") does not place any direct restriction on MCRs but it requires long iteration time to converge to the equilibrium point. The fourth criterion (called "Allocation proportional to MCR") can not be used if there are ABR VCs with zero MCRs.
The above leaves only two useful fairness criteria for ABR, namely the second and the fifth. The second criterion (called "MCR plus equal share") requires that each active ABR VC get its contracted MCR plus an equal share of the available elastic bandwidth (the latter is obtained after subtracting the MCRs of all active ABR VCs from the available bandwidth). With the fifth criterion (called "Weighted allocation"), the bandwidth allocation for an ABR VC, say VC[vc.sub.-- no], is proportional to its pre-determined weight, w[vc.sub.-- no]. The weight of a given ABR VC may or may not be related to its MCR.
In addition to the PTI (payload type identifier) field which distinguishes between RM and data cells, and the VCI/VPI (virtual connection identifier/virtual path identifier) fields which identify the connection of a cell, important fields of an RM cell in the context of this invention are the following (see FIG. 2).
DIR (direction) bit:
When the source creates an RM cell, it sets DIR=0 indicating that this is a forward RM cell. Before the destination loops back an RM cell, it changes DIR to 1 indicating that this is now a backward RM cell. The DIR bit may not be altered by intermediate switches.
CCR (current cell rate) field:
This is a read-only field that contains the value of ACR at the transmission time of this RM cell.
MCR (minimum cell rate) field:
This is a read-only field that contains the contracted MCR. MCR is a minimum guaranteed rate. The source's rate need never be less than MCR.
ER (explicit rate) field:
This is a read/write field. Before the source transmits an RM cell, it should set this field to the desired rate (typically, the peak cell rate of the connection). An intermediate switch along the connection's path may reduce the value of the ER field in RM cells passing through it to whatever value it can support. However, an intermediate switch may never increase the value of the ER field in an RM cell passing through it.
While ATM Forum specification [1] cited above specifies a reference behavior for an ABR end system (e.g. in terms of the generation and handling of RM cells, adjusting ACR, etc.), the ABR switch behavior is largely unspecified and is left as implementation specific. In particular, the method by which a switch monitors its traffic and updates the ER fields of ABR RM cells passing through it is left as implementation specific.
To understand the objectives of an ABR switch mechanism, it is important to first understand the role of ABR within an ATM network (from a network point of view). In general, it is assumed that ABR will have access to the excess bandwidth left unused by "higher" priority traffic classes, namely, VBR and CBR. The handling of CBR bandwidth is straightforward, since CBR consumes a fixed amount of link bandwidth. However, VBR traffic is bursty by definition which causes the amount of bandwidth available to ABR to fluctuate.
Thus, the function of an ABR switch mechanism is to provide each ABR VC with the "right" rate allocation (inserted in the ER field of ABR RM cells passing through it) with the following two (somewhat conflicting) goals in mind: rapid stabilization to high link utilization and small queue sizes at intermediate switches. Furthermore, the bandwidth available to ABR should be shared in a fair manner among contending ABR VCs. What makes the latter objective non-trivial to achieve is the existence of heterogeneous MCRs and weights (i.e. different ABR VCs may have different MCRs and different weights). For example, assume that two ABR VCs, A and B, share a 100 Mbps link where MCR for VC A is 60 Mbps and MCR for VC B is 0 Mbps. Furthermore, assume that the weight of VC A is 1 while that of VC B is 3. Then a straightforward division of the bandwidth would result in VC A getting 50 Mbps, which is even less than its guaranteed minimum of 60 Mbps. However, the fair share for VC A is 60+(100-60)*(1/4)=70 Mbps and the fair share for VC B is 0+(100-60)*(3/4)=30 Mbps. This example demonstrates how the only two useful ABR fairness criteria of [1] which are #2 (called "MCR plus equal share") and #5 (called "Weighted allocation") can be combined. In this case, each ABR VC gets its MCR plus a weighted share of the available elastic bandwidth.
It should be noted that this invention intentionally ignores the binary mode of operation for ABR, where switches experiencing congestion set a congestion flag in the headers of data cells and/or set special bits in the RM cells. This is because it is well-known that the explicit rate (ER) mode operation for ABR (where switches know what rates they can support and convey these rates to the ABR sources involved) has far superior performance compared to that of the binary mode [8].
None of these existing ABR switch mechanisms takes into account the MCR values of the contending ABR VCs in their ER calculations (not to mention any possible VC weights). They all make the assumption that all ABR VCs have the same MCR, and thus there is no need to take MCR into account. Clearly, in a real network, different ABR VCs may have different MCRs (and different weights) and as such any good ABR switch algorithm should take MCR (and VC weight) explicitly into account. Furthermore, while modifying some of the existing algorithms to account for MCR may be possible, this is not necessarily true for all of them. In particular, modifying ERICA [6] to account for MCR does not seem to be an easy task.
In addition to the above problem of not taking MCR into account, existing ABR switch mechanisms also suffer from what is known as the "CCR-reliance" problem. This can be explained as follows. All existing ABR switch mechanisms read the CCR fields of RM cells passing through them and use these fields in the calculations of the ERs. An implicit assumption that the existing mechanisms make is that the CCR field read from an RM cell on a given VC represents the actual rate of the VC at the moment of reading the field. This is not true for the following reasons:
To avoid the CCR-reliance problems, per ABR VC rate measurements have to be performed. However, this has been avoided in existing ABR switch mechanisms because it was thought that this (i.e. measuring rates per ABR VC) is too complex to implement and may require scanning of ABR VCs to update their measured arrival rates.
EPRCA [2] was the first ER switch mechanism to be proposed. In EPRCA, two congestion states are defined: congested when the queue size exceeds some threshold, and very congested when the queue size exceeds a larger threshold. EPRCA maintains a running weighted exponential average, called MACR, of the CCR fields of all ABR VCs (MACR=MACR*15/16+CCR*1/16). This is done by first intercepting any forward RM cell passing through the link under consideration and reading its CCR field. The newly read CCR is allowed to trigger an update to the MACR average only if the link is congested (as defined above) and CCR<MACR, or if the link is not congested (as defined above) and CCR>MACR*7/8. When a backward RM cell is received and the link is very congested, then ER=min(ER in cell, MACR*1/4). Otherwise, if the link is just congested and CCR>MACR*7/8, then ER=min(ER in cell, MACR*15/16).
It has been shown by many ATM Forum contributions that EPRCA suffers from the following problems: oscillations, link under-utilization, unfairness, and parameter sensitivity. These problems are in part due to the way EPRCA defines congestion (i.e. queue threshold crossing). The problems are expected to become even worse with the introduction of VBR into the network, since EPRCA takes VBR traffic into account indirectly through the queue length measurements.
ERICA [6] and [7], uses a different approach in coming up with the right ER for each ABR VC, and operates with a target link rate in mind. ERICA uses a count based measurement interval: for every N cells received (it is unclear whether this count includes ABR cells only, or all cells), the following link variables are updated:
______________________________________ Nactive = the number of ABR VCs seen in this interval VBR.sub.-- Input.sub.-- Rate = number of VBR cells received/interval duration ABR.sub.-- Capacity = target rate-VBR.sub.-- Input.sub.-- Rate Load.sub.-- Factor = ABR.sub.-- Input.sub.-- Rate/ABR.sub.-- Capacity Fair.sub.-- Share = ABR.sub.-- Capacity/Nactive ______________________________________
Also, the flag Connection.sub.-- Seen is reset for all ABR VCs (this requires scanning for all ABR VC at the end of each measurement interval). The CCR fields are read from forward RM cells and stored, and are then used to update the ER fields of backward RM cells according to the following equations.
______________________________________ ERS = max(Fair.sub.-- Share, CCR/Load.sub.-- Factor) ER = min(ER in cell, ERS) ______________________________________
Furthermore, multiple backward RM cells on the same ABR VCs which are seen during the same measurement interval are given the same ER value; this is done in order to avoid oscillations. This adds two more variables per ABR VC: a flag to indicate that a backward RM cell has been seen on the VC in this measurement interval, and the rate that was last given to each ABR VC. The flag (together with the above-mentioned Connection.sub.-- Seen flag) must be reset for all ABR VCs at the end of each measurement interval.
No independent evaluation of ERICA has been published. However, the present inventors have conducted extensive simulation studies of ERICA under various network scenarios and found that ERICA (at least in its published form) suffers from several serious problems. They include:
Scalability:
Ignoring VBR traffic for now, ERICA is extremely sensitive to the choice of the measurement interval length. If the recommended 30-cell length (for OC-3 links) is used, that means that a maximum of only 30 ABR VCs can be declared as active in any given measurement interval. This would cause the first term in ERICA's main equation (i.e., Fair.sub.-- Share=ABR.sub.-- Capacity/Nactive) to be excessively large, causing problems for the switch since this Fair.sub.-- Share will be provided to all non idle ABR VCs whether they have contributed to Nactive or not. On the other hand, if the length of the measurement interval is chosen to be large enough (say, 10 times the number of VCs which are set up to pass through the link under consideration), then so much activity may be lost and ERICA would be too slow to react to both congestion and under-utilization problems. If the length of the measurement interval is chosen somewhere in between, severe oscillation would occur. Another aspect of scalability concerns the requirement in ERICA to scan all ABR VCs at the end of each measurement interval in order to reset two per VC flags.
Fairness:
It can be shown that, even with MCR=0 (and equal weights) for all ABR VCs, ERICA may not necessarily achieve the max-min fairness criterion in certain network scenarios. For example, it is assumed that the measurement interval length is chosen in such a way that the above-mentioned problems are avoided (it is not certain that this is possible). It is further assumed that a large number of ABR VCs exist on a link where all of them (except, say, for one VC) are rate limited. In this case, the ACRs of the rate limited VCs will be determined through the first term in ERICA's main equation (i.e. Fair.sub.-- Share=ABR.sub.-- Capacity/Nactive). On the other hand, the ACR of the only greedy VC will be determined through the second term in ERICA's main equation (i.e. CCR/Load.sub.-- Factor). Now, if one of the initially rate limited VCs decides that it wants to become greedy and uses all of the bandwidth that it is given, it may not be able to share the link fairly with the VC that initially started as greedy. This happens because the network locks into the wrong set of rate allocations.
On a given ABR VC, the source sends data cells to the destination through one or more intermediate ATM switches. Furthermore, in accordance with the ATM Traffic Management Specification [1] referred to above, the source periodically creates and sends forward RM cells. The aggregate traffic sent by the source is dynamically shaped to ACR (allowed cell rate), which is controlled by the network. The forward RM cells travel through the same path as that of the data cells on the same VC. These forward RM cells are characterized by having their DIR bit set to 0 (see FIG. 2) and carry information about the source that can be useful to the network. In particular, the source inserts its current ACR in the CCR (current cell rate) field of the forward RM cell. Also, it inserts its contracted MCR (minimum cell rate) in the MCR field. Furthermore, it indicates its desired rate through the ER (explicit rate) field; typically, the ER field will be initially set to PCR (peak cell rate) of the connection.
When the destination receives a forward RM cell, it changes the DIR bit to 1 indicating that the cell is now a backward RM cell, reduces the ER field to whatever value it can support, and finally loops the RM cell back to the source. The backward RM cells travel through the same path as that of the data and forward RM cells on the same VC, but in the reverse direction.
In accordance with the ATM Forum Traffic Management Specification [1], intermediate switches have the option of intercepting forward and/or backward RM cells to reduce their ER fields to whatever values they can support as long as fairness is maintained. Thus, when an RM cell finally returns to its originating source, its ER field would reflect the maximum possible rate on the most congested link along the connection's path. The source then adjusts its ACR using:
______________________________________ ACRnew = min(ER in returning RM cell, ACRcurrent + RIF*PCR) ______________________________________
where RIF (rate increase factor) is a parameter that is determined during connection set-up. The source always ensures that the resulting ACR is never below MCR or above PCR. It can be seen that when RIF=1, ACR is totally controlled by the ER values in returning RM cells.
In [9] above, a schematic diagram of ABR flow control algorithm as applied to a single output-buffered ATM switch is described in detail. FIG. 3 is a schematic illustration of a single output-buffered ATM switch where an embodiment of the invention is implemented. It should be noted that the invention itself applies to any ATM switch architecture and is not restricted to output-buffered switches only. The invention typically resides at each queuing point of an ATM switch. Referring to FIG. 3, a switch fabric 40 connects a pair of ports 42, each having a queue 44 at its egress. The data cell flow and RM cell flows associated with one direction of an ABR VC are shown in differing solid lines with an arrow.
In summary, the flow control comprises four processes, namely, a traffic monitoring process, a measurement interval process, a forward RM cell process, and backward RM cell process.
The traffic monitoring process is concerned with monitoring the traffic (ABR and otherwise) being received and dequeued, and updating various cell counts. These cell counts are used by other processes.
In the measurement interval process, the output rate available to ABR is determined and a load factor is updated. This involves steps to determine the ABR input rate, the ABR output rate, and the input and/or output rates of other traffic classes. One aspect of this flow control is that it takes into account riot only ABR input rate, but also ABR output rate. This indirectly takes into consideration the ABR cells already in the queue, especially in situations where ABR cells accumulate in the queue because of, e.g., VBR traffic. Another aspect of the flow control is that, when determining the rate available to ABR, it takes into account both the input and output rates of VBR as well as previous samples of the rate available to ABR.
In the forward RM cell process, forward RM cells are intercepted and their CCR fields are read. The read CCRs are used to update certain link and VC variables. In particular, a moving average of the CCRs seen on each VC is maintained. Furthermore, a moving average of the CCRs seen on all VCs (but without their MCR components) is also maintained; this link variable is called the mean elastic rate. Also, a moving average of the weights of all seen ABR VCs is maintained. Thus, one aspect of the flow control is the averaging of the CCRs seen on a VC. By doing so, certain oscillation problems are avoided without resorting to approaches which require scanning of all ABR VCs at the end of each measurement interval. Another aspect of the flow control is the subtraction of MCR from CCR before triggering an update to the link-wide average of CCRs (i.e. the mean elastic rate). This achieves an MCR-based fairness. A third aspect is the averaging of the weights of seen ABR VCs.
In the backward RM cell process, backward RM cells are intercepted to update their ER fields. One aspect of the flow control is its main equation of calculating the ER for a VC. That equation utilizes the VC's MCR, the VC's weight, the moving average of CCRs seen on this VC, the link's mean elastic rate, and the link's load factor. Another aspect of the flow control is the differentiation between two link states when calculating the ER for a given VC: excessively overloaded (when the load factor is less than some threshold), and otherwise. This differentiation is found to be extremely important to prevent the network from being locked into the wrong set of rate allocations and to allow newly active ABR VCs to acquire their fair share of the bandwidth. Through yet another aspect of the flow control, the rate allocation may be further adjusted based on how much total rate (on all ABR VCs) is allowed as compared to the output rate actually available to ABR; this is controlled through a maximum overbooking factor.
As seen in the above description, this earlier flow control mechanism described in the applicant's U.S. Pat. No. 5,734,530 measures and utilizes rates, both aggregate and per-connection. In summary, according to the described flow control mechanism, the main equation for updating the ER field for ABR connection [vc.sub.-- no] is: ##EQU1## MER is a running exponential weighted moving average of the elastic rates (elastic rate=non-guaranteed rate=actual input rate-MCR) seen on all connections. It is updated with every forward RM cell received. IR[vc.sub.-- no] is the actual input rate measured on the virtual connection VC[vc.sub.-- no]. UF is an underload factor for the link. It is also mentioned that MER does not represent the "real" average of the rates of "active" connections. Rather, it is biased towards larger connections and this bias is believed to improve fairness and helps preventing the network from being locked into the wrong set of rate allocations, which may result in connections which may initially be rate-limited, being not able to acquire their fair share of the bandwidth when they become more active.

Flow control mechanism of ABR traffic in ATM networks


An exposure apparatus comprises an optical system support supporting a projection optical system, a stage surface plate, first stage and second stages, a first interferometer configured to measure stage position in a first area, a second interferometer configured to measure stage position in a second area, a third interferometer which is interposed between the first interferometer and the second interferometer, a gap sensor configured to measure a gap between the optical system support and the stage surface plate, and a control unit configured to pass, in the swapping, the measurement result obtained by one of the first interferometer and the second interferometer to the other one of the first interferometer and the second interferometer using the measurement result obtained by the third interferometer, and to correct the passed measurement result based on the measurement result obtained by the gap sensor.

1. Field of the Invention
The present invention relates to an exposure apparatus used in a semiconductor manufacturing process and, more particularly, to a projection exposure apparatus which projects and transfers an exposure pattern formed on an original plate onto a substrate.
2. Description of the Related Art
Conventionally, an exposure apparatus used in a semiconductor manufacturing process comprises a stage device having a coarse moving stage which rapidly accelerates/decelerates with a high acceleration/deceleration, and a fine moving stage which accurately aligns a substrate. To save the alignment waiting time and to improve the throughput, such an exposure apparatus parallelly executes alignment measurement and exposure by swapping the positions of two stages between an alignment measurement area and an exposure area. This processing is called a swap.
JP2005-353969A discloses a technique of interposing intermediary interferometers between a plurality of interferometers which measure the positions of coarse moving stages. The intermediary interferometer passes the measurement result obtained by one interferometer to the other interferometer before and after a swap, thereby improving the alignment accuracy of a stage device in an exposure station.
Unfortunately, JP2005-353969A does not describe how to measure the distance between an optical system support and a stage surface plate. Even when the stage surface plate deforms or its position changes before and after a swap operation, it is impossible to detect any misalignments of stages due to such factors. As a consequence, the alignment accuracy of the stage device deteriorates after the swap operation, so alignment or the like must be repeatedly performed. This results in prolongation of the processing time per wafer.

Exposure apparatus, method of controlling the same, and manufacturing method


An apparatus for applying a tape onto a cartridge includes a frame and a rotatable tape roll support mounted on the frame. A pivoting tape applying arm is mounted on the frame and a pair of nip rollers are mounted on the lower end of the tape applying arm. The nip rollers allow linered tape movement only in the direction away from the tape roll. Tape unwinds from the tape roll only in response to movement of the tape applying arm after tape has been applied and before the next application. The tape travels from the tape roll, through the nip rollers and along the tape applying arm before a pin mounted on the applying arm strips the tape from its liner. A paddle then tacks the tape onto the cartridge and a buff roller presses the tape against the cartridge to insure adhesion. A cutter fixed on the frame cuts the applied tape and includes an electrically heated wire mounted in a sleeve with a ceramic backup component.

Apparatus for automatically applying tape to a surface are well known. A product to be taped is moved in a path, either manually or automatically, and intersects the path of the tape to be applied The tape is taken from a tape source such as a roll and is moved to its application position typically by a series of arms and rollers. The arms may be dancer arms which accumulate tape or other pivoting arms which reduce the inertia on the tape roll to reduce the tension on the tape being applied U.S. Pat. No. 4,789,418 to Rayl is representative of tape applicating machines in which one way rollers prevent reverse tape movement and a stationary or movable knife is used to cut applied tape.
Dewyer, U.S. Pat. No. 2,543,004 discloses an apparatus which applies adhesive transfer tape onto an object using a series of rollers, one of which is activated by a brake to control advance of tape. Unwinding of the tape is controlled by a motor which also combines with a dancer arm to regulate the unwind tension of the tape. The tape is held in position for application by a vacuum wheel and a blade-type cutter severs the tape. This vacuum-using apparatus is very complex and expensive.
Shipping and other containers are commonly sealed by applying L-shaped clips of adhesive tape over a corner of the container. Various devices for applying L clips to containers include automatic applicators which operate in conjunction with a conveyer for applying L clips to a container as the container moves past the applicator. Typical L clip applicators, such as the one disclosed in Locke et al., U.S. Pat. No. 2,515,130, include an applicator arm for applying tape to a container conveyed past the applicator arm, a blade for cutting the adhesive tape into segments, and a buffer assembly for pressing the segments into contact with the container. The Locke tape dispenser applies tape around the corners of boxes. This apparatus is not suitable for applying fragile linered tape.
An applicator for automatically applying two L clips in line is disclosed in copending U.S. patent application Ser. No. 307,681 filed on Feb.6, 1989 by Ramacier and assigned to the assignee of the present invention. In the Ramacier application an actuator selectively increases the tension on the tape during cutting and decreases the tension at other times. However, this apparatus is not designed for use with fragile linered tape.
Luhman et al., U.S. Pat. No. 4,781,782 discloses an applicator for applying a tape to a stationary surface using a dancer roll. The tape is a linered pressure sensitive adhesive and the liner is stripped from the adhesive to be wound on a take-up reel before the tape is applied. A knife is used to cut the tape. However, this applicator is also not designed for use with fragile linered tape, can not apply L clips, and is relatively complex.
No known, simple, inexpensive apparatus can take a fragile linered tape which includes a tearable film adhered to a support sheet and a removable liner adhered to the tape for storing the tape, strip off the liner, and apply the linerless tape onto a product without stretching or otherwise damaging the tape during application. Moreover, fragile linered tape can not be pulled taut or cut with a conventional blade-type knife as the tension and shear forces would damage or destroy the tape. Scissors and crush cut type cutters are expensive to manufacture and use oil or other detackifying agents which contaminate the tape. Hot wire cutters may be used to sever the tape from a tape roll. Known hot wire cutting tools, such as the wire cutter disclosed in U.S. Pat. No. 4,427,144 to Macgrory et al., use high tensions and low temperatures which result in relatively long cutting times These long cutting times frequently yield improper cutting of the web and sometimes are insufficient to cut the web at all at the higher operating speeds that are compatible with the process speeds common in the industry. Operating at high temperatures would distort the wire and likely impair the ability of the wire to cut.

Apparatus for applying an L clip tape to a cartridge

Minnesota Mining and Manufacturing Company


Control apparatus for an electric vehicle is described, the control apparatus comprising input means operable to generate a first signal indicative of a component of a desired motion of the vehicle and a second signal independently indicative of said component; an electric motor arranged to drive a wheel of the vehicle; a controller arranged to control the motor according to said first signal; and means for generating a signal indicative of a voltage across windings of the motor, the controller further including: means for calculating a quantity indicative of a nominal expected voltage across said windings according to said second signal; means for comparing said voltage with said expected voltage; and means for generating an error signal in response to said voltage and expected voltage differing by more than a predetermined amount. A corresponding method of controlling an electric vehicle is also described.

The present invention relates to control apparatus for electric vehicles, and in particular to error or fault detection in control apparatus arranged to drive the vehicle.
Electric vehicles are well-known and an example 200 is shown in FIG. 1. The electric vehicle 200 comprises input means 1 which is operable by a user or driver to indicate a desired motion of the vehicle. In the case of electric wheelchairs, the input means is typically a joystick to facilitate control. The joystick generates an X signal indicative of the component of a joystick deflection along a nominal X axis and a Y signal indicative of the component of the deflection along a nominal Y axis. Usually the Y axis is aligned with the forward-reverse axis of the vehicle and movement of the joystick in the X direction corresponds to left-right movement. Thus, the Y signal is indicative of a desired forward-reverse motion of the vehicle and the X signal is indicative of a desired turning motion of the vehicle. The X and Y signals generated by the joystick are usually analogue signals and are transmitted to a controller 3 where they are converted into digital signals XD and YD by an analogue to digital converter (ADC) 31. The digital signals are processed by a microprocessor or microchip 32 which outputs a control signal 91 used to control the speed of a motor 2 arranged to drive a wheel 10 of the vehicle. In FIG. 1, only one motor 2 and one wheel 10 are shown. Typically however, the vehicle will comprise two driven wheels and two corresponding driving motors. Turning motion is achieved by driving the wheels at different respective angular velocities and forward-reverse motion is achieved by driving the two wheels at a common angular velocity.
In general, the control signal 91 is a function of (i.e. it is determined by or calculated from) both the X and Y inputs.
The control signal 91 is used to control circuitry 33 which regulates the supply of power from a battery 4 to the motor 2. The circuitry 33 outputs a further control signal 92, which is a voltage signal applied to the motor.
A problem with the arrangement shown in FIG. 1 is that a fault in the input means, controller hardware or software may affect the motor control signal 92 and may result in the wheel being driven at an inappropriate speed, i.e. the user may lose control. Clearly this is undesirable and may be dangerous.
So-called dual decode joysticks are known which, in addition to generating X and Y signals, also produce nominal inverse outputs Xi and Yi. X and Xi are independently indicative of the X position of the joystick, and similarly Y and Yi are independently indicative of its Y position. Thus, for a given joystick deflection, a dual decode joystick produces two independent signals indicative of the X component of that deflection, and two independent signals indicative of the Y component of the deflection. The xe2x80x9cnormalxe2x80x9d and xe2x80x9cinversexe2x80x9d signals are usually generated in physically separate output circuits. Thus, malfunctions or faults with the joystick hardware can be detected by comparing X with Xi and Y with Yi.
Electric vehicles employing dual decode joysticks are known, and an example is shown in FIG. 2. Normal and inverse X and Y signals are transmitted to the controller 3 where they are converted into corresponding digital signals by the ADC 31. The digital signals then pass to a processor 32. Three nominal processing operations are performed, represented schematically by regions 321, 322 and 323 in the figure. In the first processing operation 322 the normal and inverse X signals XD and XDi are compared. If the signals differ by more than a predetermined value (an error threshold) then an error signal is generated. Similarly in the second processing operation 323 the normal and inverse Y signals are compared and an error signal may be generated. It will be apparent that the apparatus may be designed to respond to an error signal (fault indication) in a number of different ways. For example, the vehicle may be brought to a rest by interrupting the power supply from the battery, by applying a brake, by appropriate control of the circuitry 33, or by other means. the controller may also provide an indication to the user or a service engineer that a joystick fault has developed.
Alternatively, if the normal and inverse signals are within the predetermined range or threshold then the normal X and Y signals are passed to the third processing operation 321 by which the control signal 91 is generated.
Although the use of a dual decode joystick represents an improvement on previous arrangements, there are still problems associated with the control apparatus of FIG. 2. In particular, only faults in the joystick and ADC hardware will be detected. Faults associated with the controller hardware and software still, in general, remain undetected and may result in the incorrect control signal being applied to the motor.
It is therefore desirable to address the problems associated with the prior art.
According to a first aspect of the present invention there is provided control apparatus for an electric vehicle, the apparatus comprising:
input means operable to generate a first signal indicative of a component of a desired motion of the vehicle and a second signal independently indicative of said component;
an electric motor arranged to drive a wheel of the vehicle;
a controller arranged to control the motor according to said first signal; and
means for generating a signal indicative of a voltage across windings of the motor,
the controller further including:
means for calculating a quantity indicative of a nominal expected voltage across said windings according to said second signal;
means for comparing said voltage with said expected voltage; and
means for generating an error signal in response to said voltage and expected voltage differing by more than a predetermined amount.
The means for generating a signal indicative of a voltage across windings of the motor may comprise a voltage dividing circuit and/or a filter circuit and the signal may be proportional to an average voltage developed across the windings. The controller may include a microprocessor which may calculate the expected average voltage (or a quantity proportional to it) from the second signal and, for example, from a preprogrammed quantity indicative of the supply voltage from a battery.
Advantageously, the error or fault signal may be generated in response to any error or fault resulting in a sufficiently large difference between the actual and expected (predicted) voltages developed or seen across the motor windings. Thus, this aspect of the present invention provides an error check on all of the control apparatus, including the input means (eg. a joystick), the controller circuitry and any software, and the motor windings themselves.
As such, it represents a considerable improvement in error detection and safety over the prior art. Errors or faults not affecting the voltage developed across the motor windings are, by definition, less serious from a control/safety point of view.
The input means may be further operable to generate third and fourth signals independently indicative of another component of a desired motion of the vehicle, the controller may be arranged to control the motor (ie its speed and direction of rotation) according to the first and third signals, and the calculating means may calculate the quantity indicative of the expected voltage according to the second and fourth signals.
The motor may be brushless and comprise three phase windings.
According to a second aspect of the present invention there is provided, control apparatus for an electric vehicle the apparatus comprising:
input means operable to generate a first signal indicative of a component of a desired motion of the vehicle and a second signal independently indicative of said component;
an electric motor arranged to drive a wheel of the vehicle; and
a controller responsive to said first signal to control the motor, the controller including
means for generating a control signal to control the motor according to said first signal,
means for calculating a nominal expected value of a parameter of said control signal according to said second signal,
means for comparing said expected value with an actual value of said parameter, and
means for generating a signal indicative of an error in response to said expected and actual values differing by more than a predetermined amount.
The control signal may, for example be a PWM voltage signal used to control switching elements in chopper circuit a PWM voltage signal output from a chopper circuit, or an output voltage from a commutation circuit.
The control signal may be applied directly to a terminal or across terminals (i.e. across windings) of the motor.
The input means may be a joystick and the first and second signals may be indicative of a component of a deflection of the joystick in either the nominal X or nominal Y direction. Advantageously, the second signal may nominally (i.e. provided that the joystick is functioning correctly) be the inverse of the first signal.
Thus, the control signal which is used to determine the speed at which the motor is driven is determined or set according to the first signal, and not the second signal. In contrast to prior art arrangements, rather than comparing the first and second signals (or their digital equivalents) directly, the second input is used to calculate an expected value of a parameter of the control signal, for example its magnitude, its time averaged value or, in the case of the control signal being a pulse with modulated signal, its mark-space ratio or duty cycle. The controller will typically comprise a microprocessor or (microchip) appropriately programmed to allow calculation of the expected value.
The means for comparing the expected and actual values may, for example, compare them directly, or add or subtract them and compare the resultant sum with a predetermined value (amount).
Advantageously, an error signal may be generated in response to a fault, error, or malfunction in the input means hardware, the hardware and software for generating the control signal, and the hardware and software for calculating the expected value. Thus, the control apparatus of the present invention provides more thorough and comprehensive error detection than previous arrangements, and accordingly provides a significant improvement in safety.
Preferably the control signal may be a control voltage applied to one of the motor terminals, or across motor terminals (i.e. a voltage applied across motor windings). Comparing the motor control voltage with an expected value therefore provides an error check on all of the hardware and software up to the motor terminals i.e. all of the hardware and software, from the joystick down, used to control the speed at which the motor is driven. Any fault affecting the motor control voltage should be detected. Of course, any fault not affecting the motor control voltage may not be detected, but by definition, such a fault is not as serious from a control and safety point of view.
According to a third aspect of the present invention there is provided control apparatus for an electric vehicle, the apparatus comprising:
input means operable to generate a first signal indicative of a component of a desired motion of the vehicle and a second signal independently indicative of said component;
an electric motor arranged to drive a wheel of the vehicle; and
a controller responsive to said first signal to control the motor, the controller including
means for generating a control signal to control the motor according to said first signal,
means for generating a signal dependent on said control signal,
means for calculating a nominal expected value of a parameter of the dependent signal according to said second signal,
means for comparing said expected value with an actual value of said parameter, and means for generating a signal indicative of an error in response to said expected and actual values differing by more than a predetermined amount.
For example, the control signal may be a PWM (pulse-width modulated) signal input to a chopper circuit to control the operation of its switching elements. The output of the chopper circuit, itself a PWM voltage, may be applied across terminals of the motor and the dependent signal may be generated using a voltage divider and filter connected across the terminals. Thus, the dependent signal is dependent on the control signal but is also indicative of the actual voltage appearing across the motor windings. By comparing a parameter of the dependent signal with its expected value, faults can be detected not just in the controller hardware and software but in the motor windings also.
Thus, rather than comparing the control signal or a parameter of it with an expected value, in this third aspect a signal is generated or derived that is dependent on the control signal, and then a parameter of the dependent signal is compared with an expected value. The dependent signal may be generated from the control signal or from an actual motor voltage by smoothing, filtering, or time averaging, and the means for generating the dependent signal may include a voltage divider. Again, advantageously this second aspect enables an error or fault check to be made on the hardware and software (including the input means) used to generate and determine the control signal and hence ultimately the voltage applied to the motor.
The input means may be further operable to generate third and fourth signals independently indicative of another component of a desired motion of the vehicle, and the means for generating the controlled signal may generate the control signal according to the first and third signals, and the calculating means may calculate the nominal expected value using the second and fourth signals. The input means may be a dual decode joystick.
In embodiments of the above described aspects of the present invention, the calculation of the nominal expected value may be performed by a microprocessor or microchip already present in the controller and used to generate the control signal. Thus, the improved error or fault detection may be provided without the need for additional hardware compared with prior art arrangements. The calculation of the expected value, comparison with the actual value, and generation of the error signal may be conveniently achieved by making use of previously redundant processing power.
According to a fourth aspect of the present invention there is provided control apparatus for an electric vehicle, the apparatus comprising:
input means operable to generate a first signal indicative of a component of a desired motion of the vehicle and a second signal independently indicative of said component;
an electric motor arranged to drive a wheel of the vehicle; and
a controller responsive to said first and second signals to control the motor, the controller including
means for generating a control signal for controlling the motor according to said first signal,
means for generating a further signal according to said second signal, the further signal being nominally equivalent to or a nominal inverse of said control signal,
means for comparing a parameter of said control signal with a corresponding parameter of said further signal, and
means for generating a signal indicative of an error in response to said parameters differing by more than a predetermined amount.
The control signal and further signal may be generated by separate hardware, or conveniently may both be generated by common hardware present in the controller and necessary for the control of the motor. The control signal may be a pulse with modulated signal generated by a microprocessor according to the first input signal, and the further signal may be an xe2x80x9cinversexe2x80x9d pulse-width-modulated signal generated from the second input signal. The means for comparing may conveniently compare the duty cycle of the control signal with the duty cycle of the further signal. In the art, xe2x80x9cduty cyclexe2x80x9d is used to denote the fraction or percentage of unit time interval at which the pulse-width-modulated voltage is in the xe2x80x9chighxe2x80x9d state, i.e, the duty cycle is related to the mark-space ratio and may be written as duty cycle=mark/(mark+space).
Again, the input means may be further operable to generate third and fourth signals indicative of another component of a desired motion of the vehicle, the control signal may be generated from the first and third signals, and the further signal may be generated from the second and fourth signals.
In embodiments of the above described aspects of the present invention, the control signal may be a pulse-width-modulated voltage signal, and may be an output signal from a chopper circuit. Chopper circuits are well-known and produce a PWM output signal from a constant supply voltage (in the case of electric vehicles, typically from a battery) by appropriate control of switching devices or elements. Alternatively, the control signal may be a PWM signal input to a chopper circuit to control its switching elements.
The motor may comprise brushes and may be controlled by a PWM voltage applied directly across its terminals (i.e. across its windings) or alternatively the motor may be brushless in which case the controller includes commutation circuitry. The control signal may be a voltage signal output from the commutation circuitry.
The control signal may be a voltage signal applied directly to a terminal of the motor, or may be a differential voltage signal applied across terminals of the motor.
The control apparatus may comprise means for measuring or determining the average voltage appearing across the motor terminals. This average voltage will be dependent on the control signal, and may be compared with an expected average voltage calculated by the calculating means.
The motor may be brushless and comprise first, second and third windings, a first end of each winding being connected to a first common point, and a second end of each winding being connected to a respective one of three motor terminals, each motor terminal being connected to a respective output of commutation circuitry included in the controller, each second end being further connected via a respective resistor to a second common point, the second common point being connected to a reference voltage, typically earth, by means of a further resistor and capacitor connected in parallel. The voltage at the second common point is thus indicative of an average voltage across the motor windings, and may be compared with a calculated expected value.
The means for generating a control signal may be further operable to generate a plurality of control signals, and the means for calculating may be further operable to calculate a corresponding plurality of nominal expected values. Each expected value may be compared with a corresponding actual value and an error signal may be generated accordingly.
In other embodiments a plurality of dependent signals may be generated, each corresponding to a respective one of said plurality of control signals, and again each nominal expected value may be compared with a corresponding actual value to determine whether or not to generate an error signal.
In further embodiments a plurality of control signals may be compared with a plurality of corresponding further signals and error signals may be generated accordingly.
Thus, it is possible to compare actual values, or parameters of control signals (or signals derived from control signals) with expected values at a number of points in the control apparatus architecture. This provides the advantage that in addition to simply indicating that a fault or error has occurred, the control apparatus can provide an indication of the location or source of that fault.
In general, between the inputs and outputs of the controller there will be a hierarchy of dependent control signals, and fault diagnosis may be performed at various points in this hierarchy. For example, one level of control signal may be the PWM signal input to a chopper controller to control the operation of its switching elements and a dependent control signal will be the PWM output signal from the chopper.
The control apparatus may further comprise:
means for slowing the vehicle in response to an error signal. This slowing may be achieved, for example, by interrupting the power supply from a battery, by appropriate control of chopper circuitry or commutation circuitry, by applying a brake, or by other suitable means.
According to a fifth aspect of the present invention there is provided a method of controlling an electric vehicle, the method comprising the steps of:
generating a first signal indicative of a component of a desired motion of the vehicle;
generating a second signal indicative of said component;
controlling a motor according to said first signal, the motor being arranged to drive a wheel of the vehicle;
generating a signal indicative of an actual voltage appearing across windings of the motor;
calculating an expected value for the voltage appearing across said windings using the second signal;
comparing the expected voltage with the actual voltage; and
generating an error signal in response to the expected and actual voltages differing by more than a predetermined amount.

Apparatus and a method for controlling an electric vehicle


An AC plasma panel display includes front and back panels that respectively support a first parallel electrode pattern and a second orthogonally oriented, parallel electrode pattern. The electrode patterns define a display area and both patterns are covered by dielectric layers. A dischargeable gas is positioned between the dielectric layers in the known manner. Driver circuitry is coupled to both electrode patterns for creating a spatially continuous gas discharge along at least one continuous electrode of one electrode pattern and across the entire display area. The driver circuitry scans the spatially continuous gas discharge across remaining parallel electrodes of the one electrode pattern so as to scan the entire display area. A further electrode is in DC conductive communication with the gas and is positioned outside of the display area but in contact with the spatially continuous gas discharge during its scanning action. The electrode provides a capacitive structure which prevents a build-up of an excessive static charge on the dielectric layers and thereby prevents dielectric breakdown.

AC plasma display panels or gas discharge panels are well known in the art and generally comprise a pair of glass substrates respectively supporting column and row electrode patterns. The electrode patterns are coated with dielectric layers and are disposed in parallel spaced relation to define a gap therebetween. The substrates are arranged such that the electrode patterns are disposed in orthogonal relation and thereby define points of electrode intersection which, in turn, define discharge cells. A dischargeable gas is positioned in the gap between the dielectric layers and may be selectively discharged by appropriate energization of intersecting electrodes.
Such panels operate with AC voltages and provide a write voltage which exceeds the firing voltage of the gas at a given discharge "pixel cell" as defined by selected, intersecting, column and row electrodes. A discharge at a selected pixel cell can be continuously "sustained" by applying an alternating polarity sustain voltage, which by itself is insufficient to initiate a discharge. The sustain action relies upon wall charges which are generated on the dielectric layers and cooperate with the applied sustain signal to exceed the gas breakdown voltage.
Early versions of the AC plasma display panel applied both addressing and sustain signals to common electrodes (see U.S. Pat. No. 3,559,190 to Bitzer et al.). Later, improved AC plasma displays have separated the sustain and address circuitry to achieve greater flexibility in operation and lower drive circuit costs (see U.S. Pat. No. 4,772,884 to Weber et al.). In most AC plasma display structures, all electrodes within a display area of the panel structure are covered by the dielectric layer, thereby enabling wall charge accumulation and preventing arc-over which could occur if conductors were directly exposed to the ionizable gas.
DC-operated plasma display panels employ DC electrodes that are in direct contact with the gas, but employ current limiting devices in the drive circuitry to prevent excessive current flow when the gas discharges. To confine the discharge area within a DC plasma display panel, dielectric separators are positioned between the pixel cells and prevent the spread of the ionized gas. In AC plasma panels, such separators are not required.
DC electrodes have also been used in AC plasma panel structures. Engineers at the Fujitsu Corporation have developed a panel that has dielectric-covered AC electrodes on one substrate and orthogonally oriented, metal DC electrodes on the other substrate. This panel is described in a paper entitled "Improvement of Luminance and Luminous Efficiency of Surface-Discharge Color AC PDP" by Shinoda et al., Society for Information Display, International Symposium, Digest of Technical Papers, vol. 22, pages 724-727, May 6-10, 1991. In the Shinoda et al. panel, AC electrodes on the front glass plate were energized with the usual AC sustain signal and DC electrodes on the rear glass substrate were used only for addressing.
It has recently been found that AC plasma display panels exhibit a reliability problem that is manifested by an irreversible breakdown of the thick film dielectric layer over the electrode structures. The dielectric layer is the fundamental insulating layer that prevents destructive arc discharge in the panel. Referring to FIG. 1, a cross-section of a prior art AC plasma panel is shown and includes glass substrates 10 and 12 that enclose a dischargeable gas 14. Row electrodes 16 reside on the lower surface of glass substrate 10 and column electrodes 18 (only one is shown), reside on the upper surface of glass substrate 12. Electrodes 16 and 18 are each covered by dielectric layers 20 and 22 which may, in turn, be covered by a further dielectric MgO overcoat (not shown).
Dielectric layers 20 and 22 are normally designed to withstand voltages of at least 500 volts. Typically used sustain pulses are approximately 100 volts and, when added to a maximum value of 100 volts of wall potential which appear on the walls of dielectric layers 20, 22, result in a maximum potential across both dielectric layers 20 and 22 of approximately 200 volts (or 100 volts across each dielectric). Thus the 500 volt breakdown strength for each dielectric layer offers a significant safety factor under normal operation. Nevertheless, it has been found that under certain circumstances, dielectric layers 20 and 22 experience catastrophic breakdown, with a resultant arcing between electrodes 16 and 18. Once this breakdown has occurred, the panel is permanently damaged and in the neighborhood of the damaged dielectric, will not function properly. The cause of such dielectric breakdown has heretofore been thought to result from dielectric abnormalities or deficiencies. As will be apparent from the below described invention, the Applicant has found that the cause of the dielectric breakdown is entirely different than heretofore understood.
Accordingly, it is an object of this invention to provide an improved method for operating an AC plasma panel which prevents arc breakdown of dielectric layers covering panel electrodes.
It is yet another object of this invention to provide an improved AC plasma panel structure which prevents conditions from occurring within the AC plasma panel that lead to dielectric layer breakdown.

AC plasma panel with system for preventing high voltage buildup


The present invention provides a human squalene epoxidase (HSQEP) and polynucleotides which identify and encode HSQEP. The invention also provides genetically engineered expression vectors and host cells comprising the nucleic acid sequences encoding HSQEP and a method for producing HSQEP. The invention also provides for the use of HSQEP and agonists, antibodies, or antagonists specifically binding HSQEP, in the prevention and treatment of diseases associated with expression of HSQEP. Additionally, the invention provides for the use of antisense molecules to polynucleotides encoding HSQEP for the treatment of diseases associated with the expression of HSQEP. The invention also provides diagnostic assays which utilize the polynucleotide, or fragments or the complement thereof, and antibodies specifically binding HSQEP.

The de novo biosynthesis of cholesterol in the endoplasmic reticulum proceeds by a multistep process. Acetyl coenzyme A (-CoA) is condensed and converted to 3-hydroxy 3-methylgutaryl (HMG)-CoA. HMG-CoA is reduced to mevalonate by the action of HMG-CoA reductase. In consecutive enzyme-catalyzed reactions, mevalonate is converted to isopentenyl pyrophosphate (IPPP), geranyl pyrophosphate (GPP), farnesyl pyrophosphate (FPP) and squalene. Squalene is oxidized to squalene 2,3-epoxide by squalene epoxidase. Rearrangements of squalene 2,3-epoxide lead to lanosterol. Lanosterol is converted to cholesterol in the endoplasmic reticulum in another series of enzymatic reactions.
HMG-CoA reductase is considered one of the major regulatory enzymes in cholesterol biosynthesis. HMG-CoA reductase inhibitors such as lovastatin are widely used to lower plasma cholesterol levels. Since the HMG-CoA reductase-catalyzed production of mevalonate is an early step in the cholesterol biosynthetic pathway, HMG-CoA reductase inhibition depletes many other intermediates of the cholesterol biosynthetic pathway.
Many intermediates in the cholesterol biosynthetic pathway depleted by inhibition of HMG-CoA reductase have additional roles in cellular function. For instance, FPP and FPP-derived geranylgeranyl pyrophosphate (GGPP) covalently modify proteins, heme, and tRNA, and are precursors for biologically important molecules such as dolichols and ubiquinones (Grunler, J. et al. (1994) Biochim. Biophys. Acta 1212:259-277). Posttranslational protein isoprenylation promotes the anchoring of proteins to membranes and serves as a regulatory signal (Glomset, J. A. et al. (1990) Trends Biochem. Sci. 15:139-142). For example, the Rab proteins are a class of small GTP binding proteins which are involved in intracellular vesicle trafficking. Isoprenylated Rab proteins on the surface of vesicles interact with GTPase-activating proteins and specific Rab receptors on the target membrane, leading to membrane fusion. When cellular isoprenoid synthesis is blocked by lovastatin, Rab proteins that are normally localized in membranes of the endoplasmic reticulum, Golgi apparatus, and endosomes accumulate in the cytosol (Kinsella B. T. et al. (1992) J. Biol. Chem. 267:3940-3945).
Defects in protein isoprenylation caused by depletion of FPP and its metabolites may have undesirable biological consequences. The vesicular trafficking of integral membrane proteins is compromised by altered Rab isoprenylation resulting from depletion of intracellular FPP and GGPP. For instance, cystic fibrosis transmembrane conductance regulator (CFTR) function in a primary human airway epithelial cell line is compromised by lovastatin (Shen, B.-Q. et al. (1995) J Biol. Chem. 270:25102-25106). Lovastatin is proposed to disrupt the trafficking of CFTR to the apical plasma membrane by inhibiting the isoprenylation of Rab or Rab-like trafficking proteins. Protein isoprenylation is also important in the maintenance of retinal cytoarchitecture. Lovastatin produces profound dysplasic-like changes in adult rat retinas primarily in the photoreceptor layer (Pittler, S. J. et al. (1995) J. Cell Biol. 130:431-439). This retinal degeneration is traced to defects in protein isoprenylation.
Arteriosclerosis, a generic term for thickening and hardening of the arterial wall, is responsible for the majority of deaths in the United States and most westernized societies. One type of arteriosclerosis is atherosclerosis, the disorder of the larger arteries that underlies most coronary artery disease, aortic aneurysm, and arterial disease of the lower extremities and also plays a major role in cerebrovascular disease. Atherosclerosis is by far the leading cause of death in the U.S., both above and below age 65 and in both sexes.
A generally accepted theory for the pathogenesis of atherosclerosis is the reaction to injury hypothesis. According to this idea, the endothelial cells lining the intima are exposed to repeated or continuing insults to their integrity. Injury to the endothelium includes metabolic injury, such as chronic hypercholesterolemia. Reduction of hypercholesterolemia results in a decrease in the progression of atherosclerosis in humans and other primates. Drugs that act primarily by lowering low density lipoprotein (LDL) cholesterol are the current drugs of choice for high-risk patients.
It is apparent that, while inhibitors of enzymes at early steps in the cholesterol biosynthetic pathway are effective cholesterol-lowering therapeutics, such inhibitors also deplete other necessary metabolic intermediates. Inhibitors of enzymes which are further along the cholesterol biosynthetic pathway would therefore provide more desirable cholesterol-lowering therapeutics than the inhibitors of earlier pathway enzymes such as HMG-CoA reductase.
The discovery of polynucleotides encoding human squalene epoxidase, and the molecules themselves, presents opportunities to investigate the regulation and control of the later (post-FPP) cholesterol biosynthetic pathway and to elucidate mechanisms for the reduction of hypercholesterolemia in humans. Discovery of molecules related to squalene epoxidase satisfies a need in the art by providing new diagnostic or therapeutic compositions useful in the reduction of LDL cholesterol, a key risk factor in atherosclerosis and coronary heart disease.