Predetermined bits of an address signal taken into an address register are taken into a burst address counter and are changed in synchronization with a clock signal. The address bits from the burst address counter are applied to a block decoder for selecting a memory sub-array from the plurality of memory sub-arrays. A block address and the memory sub-array to be selected change at every clock cycle. An operation frequency of data read circuits provided for the respective memory sub-arrays can be made lower than a frequency of the clock signal. Memory cell data can be read out accurately even in a high-frequency operation.

1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device which operates in synchronization with a clock signal, and particularly to a structure of a data reading portion of a clock-synchronous static semiconductor memory device which can operate in a burst mode.
2. Description of the Background Art
For constructing a processing system, which can operate in a fast speed, by fulfilling a gap in operation speed between a main storage device and a microprocessor, such a structure has generally been used in recent years that a cache memory for storing data which are accessed with high frequency is generally arranged between the microprocessor and the main storage device. As such a cache memory, a synchronous burst SRAM (which will be referred to as a "BSRAM" in some cases hereinafter) which operates in synchronization with an external clock signal such as a system clock has been widely used.
FIG. 27 schematically shows a whole structure of a BSRAM in the prior art. The BSRAM shown in FIG. 27 is disclosed, e.g., in IEICE Transaction on Electronics, Vol. E80-C, No. 4, April 1997, pp. 557-565.
In FIG. 27, BSRAM includes a memory array 900 having a plurality of static memory cells arranged in rows and columns, a control circuit 902 which determines states of externally supplied control signals, i.e., an address advance signal /ADV, an address strobe signal /ADS, a write enable signal /WE and an output enable signal /OE at a rising of a clock signal CLK such as a system clock, and generates internal control signals for performing operations in accordance with a result of the determination, an address register 904 which takes in an externally supplied address signal Ade in accordance with an address strobe instructing signal received from control circuit 902, a burst address counter 906 which takes in predetermined bits of external address signal Ade taken into address register 904 and, and changes the address bits thus taken in a predetermined sequence under the control by control circuit 902, and a memory cell select circuit 908 which selects an addressed memory cell in memory array 900 in accordance with internal address signal Adi formed of remaining address signal bits from address register 904 and address bits from burst address counter 906.
Address advance signal /ADV enables the count operation of burst address counter 906. Control circuit 902 changes the count value of burst address counter 906 in synchronization with clock signal CLK when address advance signal /ADV is active (L-level). Burst address counter 906 takes in predetermined bits (column address bits) in address register 904 as a leading address, and performs the count operation in a predetermined sequence for output. Address register 904, which is controlled by control circuit 902, takes in external address signal Ade in synchronization with clock signal CLK when address strobe signal /ADS is active. Write enable signal /WE and output enable signal /OE are signals for enabling write/read of data and output of data, respectively. When signal /OE is at H-level, the BSRAM is in the data output high impedance state.
The BSRAM further includes a read/write circuit 910 which reads and writes data from and into a selected memory cell in memory array 900 under the control by control circuit 902, and an input/output register 912 which transmits data to and from read/write circuit 910 in synchronization with clock signal CLK under the control by control circuit 902. Input/output register 912 includes an input register for data writing and an output register for data output, and performs input and output of data applied thereto in synchronization with clock signal CLK. Read/write circuit 910 includes a main amplifier which is activated in the data read operation as well as a write driver which is activated in the data write operation. An operation of the BSRAM shown in FIG. 27 will be described below with reference to a timing chart of FIG. 28.
In clock cycle #1, address strobe signal /ADS is set to L-level at a rising edge of clock signal CLK. Control circuit 902 applies a strobe instructing signal to address register 904 in response to this activation of address strobe signal /ADS, i.e., to L-level thereof. Address register 904 takes in and latches externally applied address signal Ade(A) in accordance with the address strobe instructing signal from control circuit 902. The address signal taken into address register 904 is output as an internal address signal Adi in clock cycle #1. A predetermined address bit (e.g., the least significant column address signal bit) in the address signal issued from address register 904 is applied to burst address counter 906. Burst address counter 906 does not perform the counting, but operates to take in and output the address signal bit received from address register 904 when address advance signal /ADV is at H-level. In clock cycle #1, therefore, internal address signal Adi is generated in accordance with external address signal Ade.
In clock cycle #2, address strobe signal /ADS and address advance signal /ADV are set to H- and L-levels in synchronization with the rising edge of clock signal CLK, respectively. In this state, address register 904 is in the latching state, and does not take in the externally applied address signal. Meanwhile, burst address counter 906 performs the counting in synchronization with clock signal CLK under the control by control circuit 902, and changes the values of the address signal bits held therein. FIG. 28 represents by way of example an operation in which burst address counter 906 changes the count value by incrementing the count by one, starting from the taken address signal bit.
In this clock cycle #2, memory cell select circuit 908 performs the memory cell selection in accordance with address signal A applied at the rising edge of clock signal CLK and, more specifically, selects an addressed memory cell in memory array 900, and read/write circuit 910 reads data from the selected memory cell. The data read from read/write circuit 910 is latched by input/output register 912.
At next clock cycle #3, data Q(A) which is supplied from input/output register 912 at the rising of clock signal CLK is sampled as output data by a processing device such as an external processor. Inside the BSRAM, the memory selection is performed in accordance with address signal A+1 changed by burst address counter 906, and read/write circuit 910 reads the data of the selected memory cell. When the output data of read/write circuit 910 is made definite, I/O register 912 takes in the definite data. In clock cycle #3, therefore, memory cell data Q(A+1) at this address A+1 is read out, and is made definite at the rising edge of clock signal CLK in clock cycle #4.
In the BSRAM, address advance signal /ADV is set to L-level at each of clock cycles #3 and #4, and address strobe signal /ADS is held at H-level so that burst address counter 906 performs counting under the control by control circuit 902 to increment successively its address to A+2 and A+3. Thereby, the memory selection is performed in accordance with internal address signals A+2 and A+3 at clock cycles #4 and #5, respectively, and the data of the selected memory cells are output from I/O register 912 and are definite at the rising edge of clock signal CLK in clock cycles #5 and #6, respectively.
As shown in FIG. 28, data is read in synchronization with clock signal CLK, and thus the rising edge of clock signal CLK determines the timing of definition of the output data, i.e., data appearing on an output pin. Therefore, it is not necessary to account for a timing margin for definition of the output data, which allows fast reading. Since I/O register 912 is used for reading data in synchronization with clock signal CLK, two clock cycles are required after application of external address signal Ade(A) at clock cycle #1 to output of corresponding memory cell data Q(A). Even in this case, the internal address signal is internally and successively produced every clock cycle for performing the memory cell selection and the reading of memory cell data. Therefore, data can be read every clock cycle after these operations, so that fast access can be performed.
Burst address counter 906 is used and has the count value changed to change the internal address signal. Therefore, it is not necessary to change and set external address signal Ade every clock cycle. Therefore, it is not necessary to drive the address signal line outside the BSRAM every clock cycle, but the operation of internally updating internal address signal Adi is merely performed so that the internal address signal can be rapidly produced every clock cycle. An external address signal line has a large load so that it requires a large current consumption for driving thereof, and its changing speed is limited. Therefore, it is possible to provide a storage device which can achieve fast data transfer.
FIG. 29 schematically shows structures of the array and the data read/write portion in the BSRAM shown in FIG. 27. In FIG. 29, memory array 900 is divided into memory sub-arrays MA#0, MA#1, MA#2 and MA#3 each having a plurality of static memory cells arranged in rows and columns. These memory sub-arrays MA#0-MA#3, of which structures will be described later in detail, include a main word line MWL extending over memory sub-arrays MA#0-MA#3 and local word lines each arranged in only one of the memory sub-arrays and corresponding to the main word line.
Memory select circuit 908 includes a block decoder 908a which decodes a block address signal ADz included in internal address signal Adi, and generates a block select signal designating one of memory sub-arrays MA#0-MA#3, a global row decoder 908b which decodes a row address signal Adx included in internal address signal Adi, and generates a signal designating a row in memory sub-arrays MA#0-MA#3, and a column decoder 908c which is provided commonly to memory sub-arrays MA#0-MA#3 and decodes a column address signal Ady included in internal address signal Adi and generates a column select signal selecting a column in memory sub-arrays MA#0-MA#3.
The signal generated from global row decoder 908b is transmitted onto main word line MWL extending over memory sub-arrays MA#0-MA#3. Block decoder 908a decodes block address signal Adz to drive one of block select signals BS0-BS3 to the active state and thereby designates one of memory sub-arrays MA#0-MA#3. Memory sub-arrays MA#0-MA#3 are selected in accordance with block select signals BS0-BS3, and row selection is performed in the selected memory sub-array in accordance with the row select signal applied from global row decoder 908b. In the nonselected memory sub-arrays, each row is held in the nonselected state.
For memory sub-arrays MA#0-MA#3, there are provided array peripheral circuits 901a-901d, respectively, which select columns and perform writing and reading of internal data into and from selected memory cells. Each of these array peripheral circuits 901a-901d includes a column select gate for selecting a column in accordance with the column select signal from column decoder 908c, and a bit line load circuit for precharging and equalizing each bit line pair (column) in the corresponding one of memory sub-array MA#0-MA#3 to a predetermined potential.
Read/write circuit 910 includes local read/write circuits 910a-910d provided corresponding to memory sub-arrays MA#0-MA#3, respectively. Each of local read/write circuits 910a-910d is activated when the block select signal from block decoder 908a is active, to perform read/write of data to the memory cell on the column selected by the corresponding array peripheral circuit.
A main sense amplifier 910e is coupled commonly to the read circuits in local read/write circuits 910a-910d through a common data bus 911. In the data read operation, main sense amplifier 910e is activated to amplify the data read from the selected memory cell in the selected memory sub-array through the local read/write circuit.
Input/output register 912 includes an output register 912a which takes in the output signal of main sense amplifier 910e in synchronization with the clock signal (not shown), and an input register 912b which takes in the data applied in the data writing in synchronization with the clock signal (not shown), and transmits the same onto common data bus 911 in synchronization with the clock signal. An output buffer 913a buffers the data applied from output register 912a, and produces external read (output) data DQ. Input register 912b receives and stores the buffered external write data through input buffer 913b in the data writing.
The memory sub-array, array peripheral circuit and local read/write circuit form one memory block. The structure shown in FIG. 29 includes four memory blocks MB#0-MB#3, each having the same structure.
FIG. 30 shows more specifically the structure of memory block MB#0 shown in FIG. 29. In FIG. 30, memory block MB#0 includes a plurality of static memory cells MC arranged in rows and columns, a plurality of local word lines LWL00-LWL0m arranged corresponding to the rows of memory cells, respectively, and connected to the memory cells in the corresponding rows, and a plurality of bit line pairs BLP0-BLPn arranged corresponding to the columns of memory cells, respectively, and connected to memory cells MC in the corresponding columns. Local word lines LWL00-LWL0m extend in the row direction only within memory block MB#0, and are driven to the active state in accordance with the word line select signal from a local row decoder 920. Main word lines MWL0-MWL0m for transmitting the row select signal applied from global row decoder 908b are arranged corresponding to local word lines LWL00-LWL0m. Local row decoder 920 drives the local word line corresponding to the selected main word line to the selected state in accordance with block select signal BS0 and the row select signal transmitted onto the main word line from global row decoder 908b. Each of main word lines MWL0-MWLm is arranged commonly to memory blocks MB#0-MB#3 and extends over these memory blocks for transmitting the row select signal to the local row decoders included in memory blocks MB#0-MB#3.
Memory block MB#0 further includes bit line peripheral circuits BPH arranged corresponding to bit line pairs BLP0-BLPn, respectively, and a local data bus LIO0 coupled to the addressed column, i.e., selected column through bit line peripheral circuit BPH. Each bit line peripheral circuit BPH includes an I/O gate for receiving corresponding one of column select signals Y0-Yn from column decoder 908c to electrically connect the bit line pair corresponding to the selected column to local data bus LIO0, and a bit line load circuit for precharging corresponding one of bit line pairs BLP0-BLPn to a predetermined potential during standby. Column select signals Y0-Yn from column decoder 908c are commonly applied to memory blocks MB#0-MB#3.
Memory block MB#0 further includes a local sense amplifier 910aa which is activated, when a local sense amplifier activating signal LSE0 is active, to amplify and transmit the signal potential on local data bus LIO0 onto common read data lines RDL and RDLB included in common data bus 911, and a write driver 910ab which amplifies the signal potential on a write data line WDL included in common data bus 911 to transmit complementary write data onto local data bus LIO0. Local sense amplifier activating signal LSE0 is selectively activated in accordance with block select signal BS0 in data reading operation. Write driver 910ab is activated in accordance with block select signal BS0 in data writing operation, although a path for this is not shown. Memory blocks MB#1-MB#3 likewise include local sense amplifiers and write drivers, respectively. Local data buses independent from each other are likewise arranged for each of these memory blocks. Common data bus 911 is arranged commonly to memory blocks MB#0-MB#3.
Read data bus lines RDL and RDLB are coupled to the main sense amplifier shown in FIG. 29.
Read data bus lines RDL and RDLB are coupled to the main sense amplifier shown in FIG. 29.
FIG. 31 shows a relationship between external address signal Ade and internal address signal Adi. As shown in FIG. 31, external address signal Ade includes a block address signal designating a memory block, a row address signal designating a row of memory cells in the memory block, and a column address signal designating a column in the memory block. These block address signal, row address signal and column address signal are multibit address signals. The least significant two bits of the column address signal are applied to the burst address counter, and the value thereof is successively updated every clock cycle. Therefore, internal address signal Adi designates the same block address and row address as external address signal Ade and, in the first cycle, external address signal Ade and internal address signal Adi designate the same column address.
In the next clock cycle, external address signal Ade and internal address signal Adi differ in value of the column address from each other. In the burst mode of selecting successively the memory cells in accordance with the burst address counter, therefore, different columns in the same memory block and the same memory cell row are successively selected. Description will now be given on an operation of successively reading out memory cell data of 4 bits in memory block MB#0 with reference to FIG. 32.
FIG. 32 shows, by way of example, an operation of successively reading out bit line pairs BLP0-BLP3 in memory block MB#0.
In clock cycle #0, internal address signal Adi is produced in accordance with externally applied address signal Ade, and local word line LWL00 corresponding to the addressed row in memory block MB#0 is driven to the selected state. Responsively, data stored in memory cells MC00-MC0n connected to the selected local word line LWL00 are read onto corresponding bit line pairs BLP0-BLPn, respectively.
In parallel with this operation of selecting the local word line, column decoder 908c performs the column selection, and column select signal Y0 is driven to the selected state. In accordance with column select signal Y0 driven to the selected state, the column select gate, which is included in bit line peripheral circuit BPH provided corresponding to bit line pair BLP0, is turned on to electrically connect bit line pair BLP0 to local data bus LIO0, and data in memory cell MC00 is read onto local data bus line pair LIO0. At this time, block select signal BS0 has already been driven to the H-level and thus the selected state. Then, local sense amplifier activating signal LSE0 is driven to the active state in accordance with activation of block select signal BS0 and local word line LWL00, and local sense amplifier 910aa amplifies and transmits the data on local data bus line LIO0 onto read data bus lines RDL and RDLB.
Then, main sense amplifier activating signal MSE is driven to the active state, and main sense amplifier 910a shown in FIG. 29 is activated so that the data in memory cell MC00 is amplified, and the amplified data is applied to output register 912a (FIG. 29) for storage therein in synchronization with clock signal CLK. The data stored in output register 912a is output via output buffer 913a in synchronization with clock signal CLK.
When a predetermined time elapses in clock cycle #0, local word line LWL00 and column select signal Y0 are both driven to the nonselected state. Block select signal BS0 maintains the selected state.
In next clock cycle #1, the burst address counter performs counting to update the least significant two bits of the column address, and column select signal Y1 from column decoder 908c is driven to the selected state. In this burst mode, the block address and row address do not change, so that local word line LWL00 is driven to the selected state again in clock cycle #1. Block select signal BS0 maintains the selected state and thus H-level for the burst period, i.e., a period for which data is continuously read out in response to one-time external address designation. In this state, data of one of memory cells MC00-MC0n connected to local word line LWL00, more specifically, data of memory cell MC01 connected to bit line pair BLP1 is transmitted onto local data bus line LIO0 through bit line peripheral circuit BPH. Then, local sense amplifier activating signal LSE0 is driven to the active state, and local sense amplifier 910aa is activated. Then, the main sense amplifier is activated, and data of memory cell MC01 is stored in the output register and will be read out through the output buffer in the next cycle.
In subsequent clock cycles #2 and #3, column select signals Y2 and Y3 are successively driven to the selected state, and data of memory cells MC02 and MC03 is successively read out. When expiration of the burst period is designated by a combination of states of external control signals, block select signal BS0 is driven to the nonselected state.
By internally and automatically producing the address signals, the memory cell selection can be performed fast, and fast data transfer can be implemented by reading and outputting data in synchronization with clock signal CLK.
FIG. 33 schematically shows a structure of a portion which generates a timing signal for selecting a row and a column. In FIG. 33, the timing signal generating portion includes a word line activating circuit 925 which is activated in response to activation of chip select signal /CS, to activate a word line activating signal WLE having a predetermined time width in synchronization with clock signal CLK, and a column activating circuit 927 which activates a column select line activating signal CLE having a predetermined time width in accordance with word line activating signal WLE. Word line activating signal WLE generated from word line activating circuit 925 is applied to global row decoder 908b. Column select line activating signal CLE generated from column activating circuit 927 is applied to column decoder 908c. Global row decoder 908b is kept active while word line activating signal WLE is active. Likewise, column decoder 908c is kept active while column select line CLE is active. Block decoder 908a statically decodes the block address signal received from the address register (FIG. 29). The address register resets the contents stored therein each time a new address is taken in response to activation of address strobe signal /ADS. Therefore, block decoder 908a is driven to the inactive or disabled state at the time of taking in the new address.
Word line activating signal WLE determines periods of selection (activation) of word lines MWL and LWL. Column select line activating signal CLE determines the active period of column select signal Y of column decoder 908c. Thus, word line activating signal WLE determines an active period TWLON of local word line LWL00 shown in FIG. 32, and column select line activating signal CLE determines an active period TYON of each of column select signals Y0-Y3.
In the operation of reading data from the memory cell, the local word line is selected, and then data of the selected memory cell is read onto the selected bit line pair and is subsequently transferred onto the local data bus line through the bit line peripheral circuit. Thereafter, the local sense amplifier is activated. In the data write operation, the write driver drives the local data bus line pair to the potential level depending on the write data, and the write data is transmitted onto the bit line pair through the bit line peripheral circuit and is written into the memory cell.
For correctly reading and writing data from and into the memory cell, it is necessary to properly perform the transmission of data between the bit line pair and the memory cell as well as the transmission of data between the bit line pair and the local data bus line pair. Therefore, active period TWLON of the local word line and active period TYON of the column select line must be longer than certain time periods, respectively. Active periods TWLON and TYON can be reduced only to limited extents when a high frequency operation is to be performed by reducing cycle time Tc of clock signal CLK in FIG. 32. Meanwhile, these active and inactive periods TWLON, TWLOFF, TYON and TYOFF satisfy the following relationship: EQU TWLON+TWLOFF.apprxeq.Tc EQU TYON+TYOFF.apprxeq.Tc
When cycle time Tc of clock signal CLK decreases, inactive period TYOFF of column select signal Y decreases relative to active period TYON of column select signal Y because the minimum length of active period TYON is predetermined. During the inactive period of the column select signal, the local data bus lines are precharged and equalized.
FIG. 34 schematically shows a structure of a precharge/equalize portion for the local data bus lines for one memory block. In FIG. 34, the precharge/equalize portion includes an AND circuit 930 receiving column select line activating signal CLE and a block select signal BSi (BS0-BS3), and a precharge/equalize circuit 932 which is activated to precharge and equalize bus lines LIOa and LIOb of local data bus line pair LIO to power supply voltage Vcc level when the output signal of AND circuit 930 is active. The precharge/equalize circuit 932 includes p-channel MOS transistors PTa and PTb provided for local data bus lines LIOa and LIOb, respectively, and receiving on their gates the output signal of AND circuit 930.
In each nonselected memory block, block select signal BSi is at L-level, and the output signal of AND circuit 930 is at L-level. Responsively, precharge/equalize circuit 932 is activated, and local data bus lines LIOa and LIOb are precharged to power supply voltage Vcc level. In the selected memory block, block select signal BSi is at H-level and thus active, and the output signal of AND circuit 930 attains L-level in synchronization with deactivation (L-level) of column select line activating signal CLE. Responsively, precharge/equalize circuit 932 precharges and equalizes local data bus lines LIOa and LIOb to power supply voltage Vcc level.
In the selected memory block, the precharge/equalize period of local data bus lines LIOa and LIOb is equal to inactive period TYOFF of column select line Y. If cycle time Tc of clock signal CLK decreases, and inactive period TYOFF of the column select line decreases, local data bus line pair LIO cannot be precharged and equalized sufficiently. This problem will now be described below with reference to FIG. 35.
FIG. 35 schematically shows change in potential on local data bus line pair LIO. Description will first be given on the case where cycle time Tc of clock signal CLK is long. At time T1, column select signal Y is driven to the active state, and the memory cell data is read onto local data bus line pair LIO after elapsing of time ta. In this state, the local sense amplifier is activated, and the memory cell data is read out. Upon elapsing of active period TYON, column select signal Y is set to the nonselected state, and column select activating signal CLE is deactivated, so that local data bus line pair LIO is precharged and equalized. If cycle time Tc is long, precharge/equalize circuit 932 shown in FIG. 34 restores local data bus line pair LIO to initial power supply voltage Vcc level.
Now, description will be given on the case where cycle time Tc of clock signal CLK is short. At time T2, column select activating signal CLE is activated, and column select signal Y is driven to the selected state. After elapsing of active period TYON, precharge/equalize circuit 932 shown in FIG. 34 equalizes in potential local data bus line pair LIO. If cycle time Tc is short, inactive period TYOFF of column select line and the precharge/equalize period of local data bus line pair LIO are short. Therefore, the precharge/equalize operation is ended at time T3 when the potential on local data bus line pair LIO is not yet restored to the original potential level.
In such an insufficiently precharged and equalized state, a next clock cycle starts, and the data of the selected memory cell is transmitted onto local data bus line pair LIO. It is now assumed that the data read in the cycle starting from time T3 is opposite in logic to the data of the memory cell selected in the cycle starting at time T2. In this case, a sufficiently large potential difference is not yet present on local data bus line pair LIO after time period ta from time T3 when the potential on the local data bus line at a lower potential of local data bus line pair LIO was driven to a high level, and a sufficiently large potential difference will appear after a time period tb from time T3. Therefore, the timing of activating the local sense amplifier must be set at or after elapsing of time period tb after time T3, which impedes fast reading. Due to the signal transmission delay at the main sense amplifier and output register, memory cell data cannot be externally output at the rising edge of clock signal CLK, and the fast reading cannot be performed.
This problem relating to the precharging and equalizing of the data bus line pair likewise arises in common data bus 911. Main sense amplifier 910e operates at each clock cycle, to transmit the data transmitted onto this common data bus to output register 912a (see FIG. 29). If cycle time Tc of clock signal CLK is short and a high frequency operation is to be performed, read data bus lines RDL and RDLB (see FIG. 30) included in common data bus 911 cannot be precharged and equalized sufficiently, and accurate reading or fast reading of the data is impossible. In this case, it is necessary to delay the timing of activating main sense amplifier activating signal MSE shown in FIG. 32. In this case, the timing of definition of the data taken into the output register is delayed so that the read data to be output through the output buffer is not made definite in accordance with the timing of rising of clock signal CLK, and data reading cannot be performed accurately.
More specifically, as shown in FIG. 36, if local sense amplifier activating signal LSE and main sense amplifier activating signal MSE are activated in accordance with delayed timing for reliably performing the precharge/equalize of the internal data bus lines, the timing of definition of the output signal of output register 912a is delayed. Therefore, it is impossible to ensure a sufficiently long setup time (with respect to clock signal CLK) for external read data DQ supplied from output buffer 913a, which in turn buffers the output signal of output register 912a for outputting. This results in a problem that data reading cannot be performed correctly.

Synchronous semiconductor memory device operable in a burst mode


A dental implant for a patient includes an anchoring part to anchor the dental implant in the bone and an abutment that is designed for fixation of a crown or similar supraconstruction and is or can be connected to the anchoring part. The anchoring part and the abutment are manufactured on a zirconium-oxide basis. The anchoring part and the abutment have special sections corresponding to the individual dimensions of the patient's bone and/or gums, said sections comprising a roughened surface designed to promote bone fusion. The special sections are produced on the green compact before the latter is finally sintered.

The invention relates to a dental implant.
For some time dental implants have been successfully employed. In many cases the material used for them is titanium, with which secure osteogenic fusion can be achieved. However, problems with their visual appearance can be avoided only by taking very elaborate measures.
From the document DE 101 59 683 a dental implant of the kind cited above is known in which the transition between the implant, the abutment and the supraconstruction seated thereon does not present any such aesthetic problems, because the material used there is based on zirconium oxide. What is problematic here is the fact that implants "ready-made" in this way must be stored in many different variants by the dental technician or at the factory, so that after the appropriate measurements of the patient have been made, the best-fitting implant can be selected. Even so, an optimal fitting is hardly possible.

Zirconium oxide-based dental implant and method for producing said dental implant


Modified chlorinated polyolefins obtained by heating the chlorinated polyolefin with a hydrocarbon acid having at least 7 carbon atoms in the presence of a free radical initiator are disclosed. The modified chlorinated polyolefins can be formulated into aqueous dispersions and coated onto plastic substrates to improve the adhesion of subsequently applied coatings.

Plastic substrates are commonly used in automotive parts and accessories, containers, household appliances, and other commercial items. Organic coating compositions are very often applied to these substrates for decorative and protective purposes. These plastic substrates are made of a variety of thermosetting and thermoplastic materials having widely varying surface properties including surface tension, roughness, and flexibility, which make it difficult to achieve adequate adhesion of organic coatings to such materials, particularly after aging or environmental exposure of the plastic materials. It is desirable to have a coating composition which can be used to coat various plastic substrates in order to promote adhesion of subsequently applied coatings on the substrate.
Moreover, in automotive applications, it is desirable to provide a coating composition which exhibits compatibility with subsequently applied coatings, stability with respect to long-term storage, resistance to gasoline, acids, and other chemicals, resistance to humidity, and excellent appearance.

Modified chlorinated polyolefins, aqueous dispersions thereof and their use in coating compositions


A utilities connecting unit for connecting motor vans and house trailers with networks or sources of electricity, gas, water, antenna voltage and the like, is inserted into an opening in the floor of the motor van or house trailer. The connecting unit includes a rotatable and/or pivotable arm with integrated utility leads and pipelines, which can be moved between a retracted position and an extended position in such a manner, that, in the extended position, it protrudes laterally from the outline of the motor van or house trailer.

The invention relates to a utilities connection for connecting motor vans and house trailers with networks or sources of electricity, gas, water, antenna, voltage and the like, with an opening in the floor of the motor van or house trailer, into which the connecting unit is inserted.
Various solutions have been proposed for connecting motor vans or house trailers with networks supplying electricity, water, television antenna, etc. Embodiments are known, for which a connecting unit is provided in the region of the side walls of the vehicle. This position is relatively unfavorable. On the one hand, the danger exists of forming thermal bridges, since it is necessary to tamper with the insulation layer of the walls. In view of the fact that the walls of motor vans or house trailers are relatively thin, a construction, moreover, is necessary, which protrudes relatively far to the inside and/or the outside and, if it is on the outside, is exposed to the danger of damage. Embodiments have therefore also become known, for which the connecting unit is located in the floor of the vehicle. However, since in most cases the walls of a corresponding vehicle extend downward over the ground as an apron, access to the connecting units at the underside of the floor is relatively difficult. Moreover, the connecting units tend to become dirty, so that it is troublesome and unpleasant to make the connection.

Utilities connection for motor vans or house trailers


In a vertical carousel storage and retrieval unit and the like, a restricted multi-compartment tote is used in conjunction with a height control such as a plurality of blocking rail. The tote is step-shaped and extends into the full depth of the unit. The blocking rail system allows sliding doors to be moved to one or more intermediate positions between fully open and fully closed positions in order to provide restricted authorized access to each of the compartments in sequential order from the first compartment at the front of the tote to the last compartment at the rear of the tote.

The present invention relates to an improvement in the vertical stacking system described in U.S. patent application Ser. No. 08/549,167. More particularly, the present invention relates to an improved vertical carousel in which sliding doors use blocking rails or any other height control system in combination with restricted access totes. Reference is made to said U.S. patent application for a discussion of storage and retrieval equipment of this type in general and of a vertical storage system with restricted access.
One potential disadvantage of current sliding door vertical storage systems is that they do not permit utilization of the entire depth of the carrier. Moreover, access is restricted to one part at a time.
In addition, even with the improvements found in the sliding door system described in U.S. patent application Ser. No. 08/549,167, each carrier, although providing for subdivision left to right into different size compartments, requires a depth of fixed amount, e.g., about 15 inches. This requirement has been found to make difficult, at least in certain situations, the storage of smaller size parts.
An object of the present invention is to provide an improved sliding door system in which a specially configured tote, in combination with a height control system such as a blocking rail arrangement and the like permits the entire depth of the storage system to be utilized while restricting access to one part at a time.
It is another object of the present invention to provide a tote which advantageously permits the depth of the storage system to be subdivided into multiple compartments, e.g., three or more.

Vertical stacking system using controlled access method


In one embodiment, an apparatus including a phase detector unit to determine a phase difference between a reference clock signal and a feedback clock signal. The apparatus further includes a controller unit to generate a delay signal based on the phase difference. The apparatus further includes a set of voltage-controlled delay lines to generate phase outputs based on the delay signal, where the phase outputs are provided by the apparatus to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver.

The International Organization for Standardization Open Systems Interconnection (ISO/OSI) model is a layered architecture that standardizes levels of service and types of interaction for systems exchanging information through a communications network. The ISO/OSI model separates computer-to-computer communications into seven layers or levels, each building upon the standards contained in the levels below it. The highest of the seven layers deals with software interactions at the application-program level. In contrast, the lowest level is the "physical layer" (PHY), which is hardware-oriented and deals with aspects of establishing and maintaining a physical link between communicating systems. Among specifications covered on the physical layer are cabling, electrical signals, and mechanical connections.
As the development of mobile device trends toward richer functionality (e.g., improved displays, cameras, peripherals, etc.) and media/content (e.g., more robust cloud-based services), mobile computing device platforms and architectures seek to accommodate greater bandwidth in the transfer of data between components. Mobile Industry Processor Interface (MIPI) Alliance is a working group that sets standards for mobile computing devices. Smart phones, personal digital assistants, laptops, tablets, and, more generally, mobile computing devices, may be designed with one or more MIPI configuration compliant components. Each component may implement a MIPI link.

Low power oversampling with delay locked loop implementation


A speed binning test circuit for a semiconductor device may include a plurality of circuit groups arranged along a boundary of a chip circuit. Each circuit group may include a different number of unit delay circuits that may form a chain structure. The speed binning test circuit may also include a plurality of pads. Each pad may be arranged between a pair of circuit groups so that at least one output terminal of a unit delay circuit of one of the plurality of circuit groups is connected to one of the pads. The speed binning test device performs a speed binning test method in which a signal through the circuit groups is delayed, and on-chip-variations are monitored to determine a total signal delay time through the chain structure.

1. Field of the Invention
The present invention relates to a semiconductor device with a speed binning test circuit and a test method thereof.
2. Description of the Related Art
In general, semiconductor memory devices such as a Dynamic Random Access Memory (DRAM) and an Application-Specific Integrated Circuit (ASIC) are manufactured by a series of processes. These processes may include a design process, a manufacture process, a chip test process, and a packaging process, before the semiconductor memory devices enter the marketplace. One type of chip test process is referring to as a speed binning test. A speed binning test is one of a series of processes performed after the manufacture process. In high-performance semiconductor memory devices such as those described above, a significant effect of temperature variation during testing is to affect the assessed maximum speed of the device in normal use, known as "speed binning". In a speed binning test, operation speeds of chips may be measured at a wafer-level, and poor-quality chips or wafers may be sorted out based on the result of measurement.
The operation speeds of semiconductor integrated circuits such as central processing units (CPUs), which are manufactured through an ultra-fine process, rely largely on process variations. Thus, there is a need for monitoring on-chip variations at a wafer level using the speed-binning test, and then predicting the operation features of chips, prior to placing the chips in the marketplace. Accordingly, packaging costs may be reduced. Typically, product costs for packaging a device such as a high-performance CPU is expensive, and the practical utility of working dies is determined primarily by the dies' functional working at a desired speed, rather than the dies' functional working. Therefore, it is more desirable to perform the speed-binning test at the wafer level to sort out poor-quality wafers.
In a conventional speed binning test circuit, a Boundary Scan Register (BSR) installed within the chip may be used to measure turn-around time by using an inverter chain installed around the chip. The turn-around time indicates a delay time duration until an input signal is output. Turn-around time is used for estimating the operation speed of the chip after the packaging process. That is, the range of the chip operation speed may be estimated using tracking plots that are measured based on a correlation between the turn-around time from the inverter chain, and the chip operation speed. The speed-binning test described above is disclosed in U.S. patent application Ser. No. 20020,129,310A1.
A conventional speed binning test method of measuring turn-around time is based on the fact that the operation speed of chip (using the inverter chain and DC characteristics evaluated through a Test Element Group (TEG), for example) depend largely on process variations.
However, as process conditions become more minute and on-chip variations become more serious, it is difficult to accurately predict the operation speed of chip by only using the conventional inverter chain to measure the turn-around time after the packaging process. In other words, the influences of on-chip variations upon circuits at every possible location, e.g., upper, lower, left and right portions, over the chip are represented as a data value, which may be referred to as a 'total delay value', in the inverter chain. It is impossible to accurately predict the operation speed based only on the total delay time. For example, it is difficult to determine whether (i) circuits at the every possible location over the chip are affected uniformly by the on-chip variations, or (ii) only a circuit at a particular location is largely affected by the on-chip variations. Thus, it may be difficult to explain why the operation speed of a core circuit becomes slower when the turn-around time for the latter case (ii) equals turn-around time for the former case (i).
Also, in the conventional speed binning test method, influence of on-chip variations is evaluated by manually measuring operation speeds at a number of different locations in the inverter chain (which is installed around the core circuit), using test equipment. The results of these measurements are then stored in a database. However, considerable time is spent on manual evaluation of the operation speed, thus making it difficult to measure the operation speeds of all of chips on a wafer. Accordingly, in the above test method only a few wafers of a lot are selected, and the evaluation is performed on only a few chips of the selected wafers. A distribution of measurement results become wide, as process conditions become even more minute. Thus, these measurement results are not accurate enough to represent the performance of the all chips on a wafer.

Semiconductor device with speed binning test circuit and test method thereof


An arbor (20) for a tool is provided. The arbor includes a shaft (22) and a locking mechanism (24) operatively coupled to the shaft. The arbor also includes an adapter (26) removably coupled to the shaft by the locking mechanism, the adapter being selectively configurable within the shaft between at least a first operating position, where the adapter is configured to secure a first tool accessory (62, 66, or 72) to the arbor, and a second operating position, where the adapter is configured to secure a second tool accessory (62, 66, or 72) different at least in part from the first tool accessory.

A hole saw is a tool used to make cut-outs in a material, such as, for example, wood, steel, fiberglass, and plastic. The hole saw is commonly adaptable to be attached to a hand drill, either power driven or manually operated, in a manner and fashion similar to conventional drill bits and the like. Different styles or sizes of hole saws vary in their mounting configurations, such as the size of the threaded apertures used in coupling the hole saw to the hand drill. For this reason, the tool user often requires an arbor that is specific for each type and/or size of hole saw.
The need to acquire and store a specific arbor for each type or size of hole saw results in additional costs to the user and increases the complexity of using such tools. Thus, there is a need for an arbor that can accommodate different types and sizes of hole saws.


To provide a liquid droplet ejection method which can detect abnormality of a nozzle, an ejection head including a plurality of nozzles has, for the respective nozzles, a camera unit that images from the inside of a nozzle to its peripheral portion. A captured image processing unit converts the captured image into an image which can recognize at least one of a state of a meniscus inside the nozzle, the shape of a nozzle opening and states of surface films formed inside and outside the nozzle, and sends the converted image to a comparison determination unit. The comparison determination unit compares the converted image with a reference image which is previously stored in a determination condition storing unit. As a result, for an objective nozzle, the quality (nozzle abnormality) of ejection performance is determined.

1. Field of Invention
Exemplary aspects of the present invention relate to a liquid droplet ejection method, a liquid droplet ejection device, a nozzle abnormality determination method, a display device and an electronic apparatus.
2. Description of Related Art
Related art ink jet devices (liquid droplet ejection device) are widely used as ink jet printers. In such an ink jet device, an ejection head can be miniaturized and constructed with a high-density structure. Further, it is possible to land ink (liquid droplet, liquid material) at a target position with high precision. Then, such an ink jet device does not depend on a type or nature of ink to be ejected. Further, it can be applied to a printing medium, such as a film, a fabric, a glass substrate and a metallic substrate, other than paper. Moreover, it has a low noise during printing and is manufactured at low cost.

Liquid droplet ejection method, liquid droplet ejection device, nozzle abnormality determination method, display device, and electronic apparatus


The invention provides humanized anti-Siglec-8 antibodies and their use in treating and preventing eosinophil-mediated disorders and/or mast cell-mediated disorders, as well as compositions and kits comprising the humanized anti-Siglec-8 antibodies.

Siglecs (sialic acid-binding immunoglobulin-like lectins) are single-pass transmembrane cell surface proteins found predominantly on leukocytes and that are characterized by their specificity for sialic acids attached to cell-surface glycoconjugates. The Siglec family contains at least 15 members that are found in mammals (Pillai et al., Annu Rev Immunol., 2012, 30:357-392). These members include sialoadhesion (Siglec-1), CD22 (Siglec-2), CD33 (Siglec-3), myelin associated glycoprotein (Siglec-4), Siglec-5, OBBP1 (Siglec-6), AIRM1 (Siglec-7), SAF-2 (Siglec-8), and CD329 (Siglec-9). Siglec-8, a member that is expressed in humans but not in mouse, was first discovered as part of efforts to identify novel human eosinophil proteins. In addition to expression by eosinophils, it is also expressed by mast cells and basophils. Siglec-8 recognizes a sulfated glycan, i.e., 6′-sulfo-sialyl Lewis X or 6′-sulfo-sialyl-N-acetyl-S-lactosamine, and contains an intracellular immunoreceptor tyrosine-based inhibitory motif (ITIM) domain shown to inhibit mast cell function.
Along with mast cells, eosinophils can promote an inflammatory response that plays a beneficial functional role such as controlling an infection at a specific tissue site. During an inflammatory response, apoptosis of eosinophils can be inhibited through the activity of survival-promoting cytokines such as IL-3 and GM-CSF. However, an increase of activated eosinophils that are not rapidly removed by apoptosis can result in the release of eosinophil granule proteins at already inflamed sites which can damage tissue and cause inflammation to be further exacerbated. Several diseases have been shown to be linked to eosinophil activation such as Churg Strauss syndrome, rheumatoid arthritis, and allergic asthma (Wechsler et al., J Allergy Clin Immunol., 2012, 130(3):563-71). There is currently a need for therapies that can control the activity of immune cells involved in inflammation, such as the activity of eosinophils and mast cells.
Previous studies have demonstrated that eosinophils undergo apoptosis when Siglec-8 is crosslinked with specific murine antibodies raised against the extracellular portion of Siglec-8 (Nutku et al., Blood, 2003, 336:918-24). These antibodies are described in U.S. Pat. No. 8,207,305, U.S. Pat. No. 8,197,811, U.S. Pat. No. 7,871,612, and U.S. Pat. No. 7,557,191. However, there remains a need for developing humanized anti-Siglec-8 antibodies that recognize human Siglec-8 with high affinity and specificity. Discovery of such anti-Siglec-8 antibodies may allow for the development of treatment for diseases mediated by the activity of eosinophils and/or mast cells.
All references cited herein, including patent applications, patent publications, and scientific literature, are herein incorporated by reference in their entirety, as if each individual reference were specifically and individually indicated to be incorporated by reference.

Anti-Siglec-8 antibodies and methods of use thereof


A direct-current converter that includes: a first series circuit, which is connected in parallel with a smoothing capacitor and in which a first switching element and a second switching element are connected in series; a second series circuit, which is connected in parallel between main electrodes of the first switching element and in which a resonance capacitor, a resonance reactor and a primary winding of a transformer are connected in series; a half wave rectification smoothing circuit, which rectifies and smoothes a voltage of a secondary winding of the transformer; a control circuit configured to alternately turn on and off the first switching element and second switching element, based on an output voltage of the rectification smoothing circuit; and a third series circuit, which is connected in parallel with the second switching element and in which a boost reactor and a direct-current power supply are connected in series.

FIG. 12 illustrates a circuit diagram of a background direct-current converter having a boost chopper and a step-down converter of a half wave current resonance-type. In the direct-current converter shown in FIG. 12, the boost chopper has a configuration where a series circuit of a reactor L and a switching element Q3 such as MOSFET is connected to both ends of a direct-current power supply Vi, and a series circuit of a diode D3 and a capacitor Ci is connected between a drain and a source of the switching element Q3, boosts a voltage of the direct-current power supply Vi and supplies the boosted voltage to the step-down converter.
The step-down converter has a configuration where a series circuit of switching element Q1 such as MOSFET and a switching element Q2 such as MOSFET is connected to both ends of a capacitor Ci, a series circuit of a current resonance capacitor Cri, a primary winding N1 of a transformer T and a reactor Lr connected between a drain and a source of the switching element Q1, and a series circuit of a diode RC and a capacitor Co is connected to both ends of a secondary winding N2 of the transformer T and outputs a direct-current voltage, which is insulated by stepping down a voltage of the capacitor Ci, to the capacitor Co.
In the background art, even when an input voltage is largely varied, it is possible to obtain a stable output voltage by the configuration of the boost chopper and the step-down converter. Meanwhile, JP-A-2010-81736 discloses an example of the configuration of the boost chopper and the step-down converter, as the prior art technology.
Also, JP-A-11-262263 discloses that the configuration of the boost chopper, and the step-down converter is made by a half bridge converter configuration, as one converter.

Direct-current converter capable of increasing operating frequency


Multi-pass recording is executed for each of n types of super cell regions that are each defined as a region that contains pixel positions in which recording of dots is performed in various types of main scan passes of n types of main scan passes. The n types of super cell regions (i) include a boundary portion that is not parallel to either a main scanning direction or a sub-scanning direction in at least a portion of a boundary of the individual super cell regions, and (ii) are arranged such that the boundary of the n types of super cell regions appears periodically repeating along both the main scanning direction and the sub-scanning direction.

1. Technical Field
The present invention relates to a dot recording apparatus, a dot recording method and a computer program for the same.
2. Related Art
A printing apparatus that causes a plurality of recording heads, which discharge inks of different colors, to move reciprocally in relation to a recording material and performs printing by performing a main scan during the outward movement and during the return movement is known as the dot recording apparatus (for example, JP-A-6-22106). In the printing apparatus, pixel groups that are configured of m×n pixels are arranged so as not to be adjacent to one another within a region in which it is possible to print in one main scan. The recording is completed by performing the main scan multiple times using multiple interleaving patterns that are in an inter-complementary arrangement relationship.
However, in the printing apparatus of the related art described above, since the individual pixel groups have rectangular shapes, and the boundaries thereof are configured of sides that are parallel to the main scanning direction and sides that are parallel to the sub-scanning direction, a long boundary that extends in the main scanning direction and a long boundary that extends in the sub-scanning direction are formed due to the convergence of the boundaries of adjacent pixel groups. Therefore, there are problems in that banding (regions of image quality degradation) occurs easily along the long boundaries and easily becomes conspicuous. These problems are not limited to a printing apparatus, and are common problems in dot recording apparatuses that record dots on a recording medium (a dot recording medium).

Dot recording apparatus, dot recording method and computer program for the same


A dual-bit memory device includes a first charge storage region spaced apart from a second charge storage region by an isolation region. Techniques for erasing a memory can be provided in which electrons can be injected into the charge storage regions to erase the charge storage regions. Other techniques for programming a memory can be provided in which holes can be injected into at least one of the charge storage regions to program the charge storage regions.

Flash memory is a type of electronic memory media that can hold its data in the absence of operating power. Flash memory can be programmed, erased, and reprogrammed during its useful life (which may be up to one million write cycles for typical flash memory devices). Flash memory is becoming increasingly popular as a reliable, compact, and inexpensive nonvolatile memory in a number of consumer, commercial, and other applications. As electronic devices get smaller and smaller, it becomes desirable to increase the amount of data that can be stored per unit area on an integrated circuit memory cell, such as a flash memory unit.
One conventional flash memory technology is based upon a memory cell that utilizes a charge trapping dielectric cell that is capable of storing two bits of data. Non-volatile memory designers have recently designed memory circuits that utilize two charge storage regions to store charge within a single silicon nitride layer. This type of non-volatile memory device is known as a dual-bit Flash electrically erasable and programmable read-only memory (EEPROM), which is available under the trademark MIRRORBIT™ from Advanced Micro Devices, Inc., Sunnyvale, Calif. In such an arrangement, one bit can be stored using a first charge storing region on one side of the silicon nitride layer, while a second bit can be stored using a second charge storing region on the other side of the same silicon nitride layer. For example, a left bit and right bit can be stored in physically different areas of the silicon nitride layer, near left and right regions of each memory cell, respectively. In comparison to a conventional EEPROM cell, a dual-bit memory cell can store twice as much information in a memory array of equal size.
FIG. 1 is a cross-sectional view of a conventional dual-bit memory cell 50. The memory cell 50 has a dual-bit (bit1, bit2) architecture that allows twice as much storage capacity as a conventional EEPROM memory device.
The conventional memory cell 50 includes a substrate 54, a first insulator layer 62 disposed over the substrate 54, a nitride charge storage layer 64 disposed over the first insulator layer 62, a second insulator layer 66 disposed over the charge storage layer 64, and a polysilicon control gate 68 disposed over the second insulator layer 66. To produce an operable memory device, a first metal silicide contact (not shown) can be disposed on substrate 54, and the control gate 66 can be capped with a second metal silicide contact (not shown).
In one implementation, the substrate 54 is a P-type semiconductor substrate 54 having a first buried junction region 60 and a second buried junction region 61 formed within substrate 54 in self-alignment with the memory cell 50. First buried junction region 60 and second buried junction region 61 are each formed from an N+ semiconductor material. The charge storage layer 64 is capable of holding a charge. The first insulator layer 62, the charge storage layer 64, and the second insulator layer 66 can be implemented using an oxide-nitride-oxide (ONO) configuration in which a nitride charge storage layer 64 is sandwiched between two silicon dioxide insulator layers 62, 66. Alternatively, charge storage layer 64 may utilize buried polysilicon islands as a charge trapping layer.
Memory cell 50 can store two data bits: a left bit represented by the circle (bit 1); and a right bit represented by the circle (bit 2). In practice, memory cell 50 is generally symmetrical, thus first buried junction region 60 and second buried junction region 61 are interchangeable. In this regard, first buried junction region 60 may serve as the source region with respect to the right bit (bit 2), while second buried junction region 61 may serve as the drain region with respect to the right bit (bit 2). Conversely, second buried junction region 61 may serve as the source region with respect to the left bit (bit 1), while first buried junction region 60 may serve as the drain region with respect to the left bit (bit 1). A threshold voltage exists between the control gate 66 and the substrate 54 to prevent leakage during functioning of the device.
While a single dual-bit memory cell 50 is illustrated in FIG. 1, it will be appreciated that any suitable number of the dual-bit memory cells 50 could be used to form a memory array, as described below with reference to FIG. 2.
FIG. 2 is a simplified diagram of a plurality of dual-bit memory cells arranged in accordance with a conventional array architecture 200 (a practical array architecture can include thousands of dual-bit memory cells 50). Array architecture 200 includes a number of buried bit lines formed in a semiconductor substrate as mentioned above. FIG. 2 depicts three buried bit lines (reference numbers 202, 204, and 206), each being capable of functioning as a drain or a source for memory cells in array architecture 200. Array architecture 200 also includes a number of word lines that are utilized to control the gate voltage of the memory cells. FIG. 2 depicts four word lines (reference numbers 208, 210, 212, and 214) that generally form a crisscross pattern with the bit lines. Although not shown in FIG. 2, charge storage layer, such as an ONO stack, resides between the bit lines and the word lines. The dashed lines in FIG. 2 represent two of the dual-bit memory cells in array architecture 200: a first cell 216 and a second cell 218. Notably, bit line 204 is shared by first cell 216 and second cell 218. Array architecture 200 is known as a virtual ground architecture because ground potential can be applied to any selected bit line and there need not be any bit lines with a fixed ground potential.
Control logic and circuitry (not shown) for array architecture 200 governs the selection of memory cells, the application of voltage to the word lines 208, 210, 212, 214, and the application of voltage to the bit lines 202, 204, 206 during conventional flash memory operations, such as: programming; reading; erasing; and soft programming. Voltage is delivered to the bit lines 202, 204, 206 using bit line contacts (not shown). FIG. 2 depicts three conductive metal lines (reference numbers 220, 222, and 224) and three bit line contacts (reference numbers 226, 228, and 230). For a given bit line, a bit line contact is used once every 16 word lines because the resistance of the bit lines is very high.
When charging up the charge storage layer 64, one way to reduce or minimize power consumption is by using Fowler-Nordheim (FN) tunneling mechanism to inject electrons into the charge storage layer 64 and thereby erase the memory cell 50.
FIG. 3 is a cross-sectional view of the conventional dual-bit memory cell during a Fowler-Nordheim (FN) erase operation in which FN tunneling can be used to inject electrons into the nitride charge storage layer 64. The basic structure of the memory cell 50 is described above with respect to FIG. 1, and for sake of brevity will not be described again. The buried junction regions 60, 61 can either be floating or grounded. The highly positive gate 68 bias voltage (e.g., 18 volts to 20 volts) pulls electrons (Θ) from the grounded substrate 54 into the charge storage layer 64 such that the charge storage layer 64 is evenly charged with electrons (Θ). This FN tunneling operation involves a relatively small amount of current and therefore consumes relatively low power.
FIG. 4 is a cross-sectional view of the structure of the conventional dual-bit memory cell during band-to-band hot hole (BTBHH) programming operation. The basic structure of the memory cell 50 is described above with respect to FIG. 1, and for sake of brevity will not be described again. This particular bias configuration, can be used to inject hot holes (electrically positively charged) into the right hand side (bit 2) of the nitride charge storage layer 64 to neutralize electrons stored at bit 2 thereby "programming" bit 2 of the memory cell 50. The right bit (bit 2) is programmed by applying a relatively high negative voltage to gate 68 via the appropriately selected word line, floating the bit line corresponding to first buried junction region 60 (which serves as the source in this case), and applying a medium positive bias voltage to the bit line corresponding to second buried junction region 61 (which serves as the drain in this case). This injects holes into the nitride layer 64 to neutralize electrons trapped in the nitride layer 64 at bit 2. Although not shown, by switching the drain/source biasing condition, holes can be injected into bit 1. The left bit (bit 1) is programmed by applying a relatively high negative voltage to gate 68 via the appropriately selected word line, floating the bit line corresponding to second buried junction region 61 (which serves as the source in this case), and applying a medium positive bias voltage to the bit line corresponding to first buried junction region 60 (which serves as the drain in this case).
FIG. 5 is a cross-sectional view of a conventional dual-bit memory cell 50 which illustrates residual electrons (Θ) that result in the center of the charge storage layer 64 as a result of the program operation. In an ideal situation, after programming one of the bits 1, 2 of the memory cell 50, the other one of the bits 2, 1 would contain exactly one-half of the electrons that were initially established in the charge storage layer 64 during the charge up operation of FIG. 3. In other words, in an ideal situation, when bit 1 is programmed, one-half of the electrons at bit 1 would be neutralized, when bit 2 is programmed, one-half of the electrons at bit 2 would be neutralized, and if both bit 1 and 2 are programmed the entire charge storage layer 64 would be neutralized. However, as illustrated in FIG. 5, band-to-band hot hole (BTBHH) programming leaves residual electrons (Θ) in the center portion of the charge storage layer 64 since hot holes can not be injected that far and therefore residual electrons (Θ) can not be neutralized. This results in degraded device operation or performance and reliability problems. For example, the residual electrons (Θ) in the center portion of the charge storage layer 64 can interfere with transistor operation since the transistor is no longer uniform because the threshold voltage at the center of the charge storage layer 64 would be different than the threshold voltages near the ends of the charge storage layer 64.
Notwithstanding these advances, it would be desirable to provide improved techniques for erasing and/or programming a dual-bit memory cell. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.

Methods for erasing and programming memory devices


This invention relates to a method, a computer program, a computer program product and a device for reducing motion blur of images shown on non-stroboscopic display devices, in which local areas p, of an image of a video signal are displayed during respective local display times t; that are less than or equal to a image period T, comprising determining (40) an amount X; of high spatial frequency content related to a local area p, of said image of said video signal, and adjusting (41) a local display time t, in dependence on said determined amount X; of high spatial frequency content, wherein said local display time t; is decreased with increasing determined amount X; of high spatial frequency content.

Non-stroboscopic non-emissive displays, such as Liquid Crystal Displays (LCD), active-matrix LCDs (amLCD), Plasma Panel Displays (PDP), Thin Film Transistor (TFT) displays, Liquid Crystal on Silicon (LCOS) displays or Colour Sequential Displays, consist of a display panel having a row and column array of image elements (pixels) for modulating light, means for illuminating the display panel from the front or back side, and drive means for driving the pixels in accordance with an applied input video signal. Quite similar, non-stroboscopic emissive displays, such as Organic Light Emitting Diodes (O-LED) displays, Polymer Light Emitting Diodes (PLED) displays, active-matrix PLEDs (amPLED) displays or Plasma Display Panels (PDP), consist of a display panel having a row and column array of pixels (LEDs) and drive means for driving the pixels (LEDs) in accordance with an applied input video signal. However, the pixels (LEDs) emit and modulate light by themselves without requiring illumination from the front or back side.
In state-of-the-art Cathode Ray Tubes (CRTs), each pixel of a displayed image is generated as a pulse, which is very short compared to the image period T. Different to these state-of-the-art CRTs, in new flat, high quality, low cost non-stroboscopic display devices, each pixel is displayed during most of the image period. Of course, this non-stroboscopic behavior also holds for types of CRTs whose pixels, e.g. slow phosphor atoms, are active for a time not negligible to the image period. In the sequel of this description, we thus will only differentiate between stroboscopic and non-stroboscopic displays, and in case of a non-stroboscopic display, we will use the term "pixel" for both the elements of a light modulation/generation array and the activated (slow) atoms of a CRT-type display.
In case any area of the image displayed on a non-stroboscopic display contains motion, the viewer will track this motion. As each pixel is displayed substantially the whole image period, the intensity of pixels showing the motion is integrated along the motion trajectory as follows:
                                          F            out                                          (                                          x                ->                            ,              n                        )                          =                              1                          t              i                                                                    ∫              0                              t                i                                                                                F                                                  (                                                                                x                        ->                                            +                                                                        t                          T                                                                                D                          ->                                                                                ,                    n                                    )                                                                          ⅆ                t                                                                        (        1        )            with ti as display time of each image, F as input video signal, Fout as output video signal, and T as image period. The motion vector {right arrow over (D)}={right arrow over (v)}T is the product of the object velocity {right arrow over (v)} and the image period T. In case ti is constant, the integration is the same as a convolution of F({right arrow over (x)}, n) and a sample-and-hold function h(α):
                                                                                F                  out                                                                  (                                                            x                      ->                                        ,                    n                                    )                                            =                                                                            T                                      t                    i                                                                                ∫                    0                                                                  t                        i                                            T                                                                                F                                                                    (                                                                                x                              ->                                                        +                                                          α                                                                                D                                ->                                                                                ,                          n                                                )                                                                                ⅆ                      α                                                                                =                                                                            ∫                                      -                    ∞                                    ∞                                                                                F                                                                    (                                                                                x                              ->                                                        +                                                          α                                                                                D                                ->                                                                                ,                          n                                                )                                                              ·                                          h                                                                    (                        α                        )                                                                                ⅆ                    α                                                                                (        2        )            where
                              h                                (            α            )                          =                  {                                                                                T                    /                                          t                      i                                                        ,                                      0                    ≤                    α                    ≤                                                                  t                        i                                            /                      T                                                                                0                  ,                  otherwise                                                                                (        3        )            is a 1D block function, oriented along the motion vector {right arrow over (D)}. It is therefore actually a 2D function h({right arrow over (x)}), which has zero value outside the line segment {right arrow over (x)}=k{right arrow over (D)}, 0≦k≦ti/T, while the 2D integral area is normalized to 1. The 2D spatial Fourier transform (leading to a representation of h({right arrow over (x)}) in the spatial frequency domain) of Eq. (2) yields:
                                                                                F                  out                                (                                                      f                    ->                                    ,                  n                                )                            =                                                                            ∫                                      -                    ∞                                    ∞                                                                                ∫                                          -                      ∞                                        ∞                                                                                F                        out                                            (                                                                        x                          ->                                                ,                        n                                            )                                                                                ⅇ                                              (                                                                              -                            j                                                                                2                                                                                π                                                                                x                            ->                                                                                f                            ->                                                                          )                                                                                ⅆ                                              x                        ->                                                                                =                                                                            F                  (                                                            f                      ->                                        ,                    n                                    )                                ·                                  H                  (                                      f                    ->                                    )                                                                                (        4        )            with F({right arrow over (f)}, n) denoting the 2D spatial Fourier transform of the input video signal F({right arrow over (x)}, n), and H({right arrow over (f)}) denoting the 2D spatial Fourier transform of h({right arrow over (x)}):
                              H          (                      f            ->                    )                =                                            sin                                            (                                  π                                                                                D                    ->                                                                                t                        i                                                              T                                                                          f                    ->                                                  )                                                    π                                                                                D                ->                                                                                t                  i                                T                                                          f                ->                                              =                      sin                                                                                c                (                                  π                                                                                D                    ->                                                                                t                      i                                        T                                                                          f                    ->                                                  )                            .                                                          (        5        )
Apparently the effect of the motion tracking/temporal sample-and-hold characteristic is a spatial frequency low-pass filtering in the direction of the motion with a sinc-frequency response, with a cut-off-frequency being inversely proportional to the quantity
                    t        i            T                  D      ->        ,where
      t    i    Tis denoted as the duty cycle of the display. The non-stroboscopic light generation, combined with the eye tracking of the viewer trying to follow moving objects from one image to the next, thus leads to the perception of motion-dependent blur in the images. When the motion {right arrow over (D)} in the image increases, the cut-off-frequency of the spatial low pass filter and thus the degree of perceived motion blur can be kept constant by reducing the display time
      t    i          (          or                                      the                                      duty                                      cycle                                                        t          i                T              )  with the drawback of loss of brightness and increased flicker.
To reduce motion blur, loss of brightness and flicker, prior art document WO 03/101086 A2 proposes to measure the motion and the characteristics of motion in the images of the input video signal and to continuously adjust the display time ti depending on this measured motion and the characteristics of motion. In a preferred embodiment, additionally anti-motion blur filtering based on the measured motion vectors is performed, and the display time and the sort and amount of anti-motion blur filtering are jointly controlled based on the measured motion and the characteristics of motion. In a further preferred embodiment, local image characteristics that determine high spatial frequencies are considered in the filtering process and in the joint control of display time and sort and amount of anti-motion blur filtering, because these characteristics contain information on how reliable anti-motion blur filtering can be performed. To reduce loss of brightness, WO 03/101086 A2 proposes to control the light output of the display inversely proportional to the display time, and, to reduce flicker, it is targeted to keep the display time as large as possible and to suppress motion blur with anti-motion blur filtering instead of reducing the display time.
All embodiments of WO 03/101086 A2 require the estimation of both the amount and the direction of motion vectors and thus require frame memories and computationally expensive real-time motion estimation algorithms. This proposed display system is thus complex and expensive when being implemented.


A noise squelch circuit for a radio receiver (100) includes an adaptive filter (204) for shaping frequency characteristics of a demodulator out put (115) according to factors which effects squelch sensitivity. Such factors may include channel spacing of the receiver, received signal strength level, received signal deviation, and SINAD. The adaptive filter (204) comprises a switched capacitor filter, the response of which may be controlled by a control signal (212) according to one or more of such factors.

In radio frequency (RF) communication systems, an audio message is modulated onto a carrier signal to provide a communication signal which is transmitted over air by means of an RF transmitter. A radio receiver receives the communication signal and demodulates it to recover the audio message which is presented to a speaker through an audio circuit.
Generally, when the received communication signal (or carrier signal) has little or no strength, the output of the demodulator comprises substantial noise in the 10-20 KHz range which is detected and mutes the audio path to the speaker. Squelching the radio prevents undesired noise from being heard, which also decreases power consumption of the receiver because no current is drawn by the speaker.
In the radio receivers, a noise squelch circuit generally provides a squelch signal which disables the audio circuit based on the noise power at the demodulator output. The received signal strength level which unsquelches a radio is commonly referred to as squelch sensitivity of the receiver. The squelch sensitivity of the receiver varies based on the noise characteristics of the demodulator output. Usually, the squelch sensitivity of the receiver is set to different levels by varying an attenuator which sets a threshold for unsquelching the radio.
Conventionally, the noise at the demodulator output after being frequency shaped and rectified is compared to the threshold to determine whether the squelch signal should be generated or not. However, because the noise characteristics of the demodulator output are not stable and may vary under certain conditions, the conventional squelch circuits may squelch or unsquelch the radio prematurely. The noise characteristic variations may depend on such factors as the channel spacing of the receiver (e.g. 25 KHz, 12.5 KHz), the received signal strength level, signal-to-noise ratio of the received signal (i.e. SINAD), and the deviation of the received communication signal (especially in frequency modulation (FM) communication systems). The noise characteristic variations could degrade radio receiver operation unless receiver hardware is modified. Therefore, numerous receiver circuit hardware may be required for accommodating the various operating circumstances. Accordingly, it is desired to improve squelch response of the radio receiver without extensive hardware modifications.

Noise squelch circuit with adaptive noise shaping


A dosing device is proposed which is designed for dosed output of a fluid. The dosing device has a block-shaped channel body, through which a dosing channel system passes. The dosing channel system has a fluid infeed opening and a plurality of fluid output openings. The fluid output openings are formed by the channel apertures of narrowed output sections of a plurality of output channels of the dosing channel system. The entire dosing channel system, including the output channels, is formed in the block-shaped channel body. The dosing channel system is preferably structured such that the flow velocity of the fluid channelled through during operation is at least substantially the same throughout with the exception of in the output sections of the output channels.

The invention relates to a dosing device for dosed output of a fluid, comprising a block-shaped channel body, through which a dosing channel system passes, which has at least one fluid infeed opening formed in the channel body to feed the fluid to be dosed and a plurality of fluid output openings arranged in a row beside one another to output the fluid, each fluid output opening being formed by a channel aperture of a narrowed output section of an output channel of the dosing channel system, the channel cross-section of the output section of each output channel being smaller than the channel cross-section of an input section of the respective output channel directly adjoined thereto upstream in the direction of the fluid infeed opening.
A dosing device of this type is known from DE 10 2017 207 524 A1. Such a dosing device allows the dosed output of a fluid in carrier substrates, for example in so-called microtiter plates. The fluid quantities output per dosing operation are generally relatively small and often represent so-called fluid samples which are for example biological or biochemical analysis samples which have to be analysed or treated in another manner The dosing device has a dosing channel system, which extends between a fluid infeed opening and a plurality of fluid output openings, the fluid to be dosed being capable of being fed into the dosing channel system via the fluid infeed opening and of being output again in a dosed manner via the fluid output openings. The fluid output openings are formed by the apertures of individual output channels, which end with a narrowed output section, so that a very precise dosing of the fluid quantities is possible. The majority of the dosing channel system so far runs in a block-shaped channel body, which is fitted on its underside with tubular nozzle needles, which define the narrowed output sections of the output channels. The dosing needles are screwed into the channel body and sealed with the aid of fittings. The manufacture and assembly of such a dosing device is relatively complex.
A dosing device is also known from DE 10 2014 013 552 B3, which has a dosing channel system, which is formed partly in a block-shaped channel body and partly in nozzle needles fastened to the channel body.


A switching power supply apparatus wherein a main converter turns "on" and "off" a DC current applied to a primary winding of a main transformer using a main switching element and outputs a main output voltage to the secondary side after rectifying and smoothing current induced in a secondary winding; an error amplifier generates an error voltage between the main output voltage and a first reference voltage; a PWM control circuit outputs an on-off control signal for the main switching element so that the error voltage is minimized; a photo coupler receives the error voltage and provides an output to the PWM control circuit; an over-voltage protection circuit generates an over-voltage protection signal when the main output voltage exceeds a second reference voltage; an on-off circuit outputs either a high level potential or a common level potential depending on whether the power is to be turned "on" or "off"; a shut down latch circuit outputs a shut down signal when the over-voltage protection signal represents an over-voltage state; and a shut down implementation circuit holds the input voltage to the photo-coupler at a value which suppresses input to the photo-coupler when a signal from the on-off circuit specifies power off or when the shut down signal from the shut down latch circuit is effective; whereby only a single isolator is required in the apparatus.

1. Field of Invention
This invention relates to a switching power supply unit used for example with computers; and, more particularly, to improvements in such an unit that can start and stop the primary side switching element by start and stop signals generated on the secondary side, or by command from an over-voltage protection circuit for the output voltage located on the secondary side.
2. Description of the Prior Art
In conventional switching power supply units, a plurality of isolators are used to isolate the following signals: a feedback signal for output voltage stabilization; a signal from the over-voltage protection circuit; and a remote control signal that turns "on" and "off" the power using an external switch located on the secondary side. The isolators may comprise photo-couplers or transformers. For example, in Japan UM Application 1-79389 (1989), a single isolator is used to isolate the remote control signals from the over-voltage protection signals.
However, in that prior apparatus, since the isolator for isolating the feedback signal for output voltage stabilization is provided separately, more than one isolator is needed for the entire apparatus, thereby increasing the number and cost of the components. In addition, for such prior apparatus, if isolation is required between the primary side and the secondary side using a photo-coupler or a transformer, the printed wiring board is difficult to design because specified distances and clearances are required by industry safety standards.
In Japan Patent Application 4-156270 (1992), a signal isolator is used to isolate the above three types of signals. However, in that unit since the latch circuit for over-voltage protection is located on the primary side, the remote control signal is not able to release the latch and restart the power supply. In addition, the commercial power supply has to be turned "off" in order to release the latch. Thus, this prior unit cannot be used in some power supply applications.