The semiconductor device comprises on a semiconductor substrate an insulating structure formed of a plurality of insulating films; an interconnection structure buried in the insulating structure and formed of a plurality of conducting layers; and a plurality of dummy patterns formed of the same conducting layer as the conducting layers forming the interconnection structure and buried in a surface side of the respective insulating films, and the dummy patterns near the interconnection structure are connected with each other through via portions. Thus, the insulating structure near the interconnection structure are reinforced, and the generation of cracks and peelings in the interfaces between the insulating films or in the inter-layer insulating films due to mechanical stresses or thermal stresses can be prevented.

The present invention relates to a semiconductor device and a method for fabricating the same, more specifically, a semiconductor device including an inter-layer insulating film of a low dielectric constant material and a method for fabricating the semiconductor device.
In semiconductor device fabrication processes, a number of elements are formed on one semiconductor wafer, and the semiconductor wafer is cut along dicing lines into discrete LSI chips. On the side walls along the dicing lines, the interfaces of many inter-layer insulating films laid in the process of forming the elements are exposed. The interfaces are often paths for water intrusion, causing problems, such as erroneous operations and breakages, etc. of semiconductor devices, which impair their reliability. Stresses in the dicing, and stresses, etc. due to thermal expansion coefficient differences between the inter-layer insulating films and a sealing resin cause cracks in the inter-layer insulating films, and the cracks often are paths for water intrusion.
A structure bounding each LSI chip is provided inside the dicing lines along all the border, whereby the intrusion of water through the interfaces of the inter-layer insulating films and the extension of cracks in the inter-layer insulating films into the chip are prevented. Such structure is formed of layers of dummy patterns which are formed of the same layers as the interconnection layers forming the internal circuits and is often called a guard ring, a seal ring, a moisture resistant ring or others. Structures for preventing the water intrusion and cracks are described in, e.g., Japanese published unexamined patent application No. 2000-232081, Japanese published unexamined patent application No. 2000-232104, Japanese published unexamined patent application No. 2000-232105, Japanese published unexamined patent application No. 2000-277465, Japanese published unexamined patent application No. 2000-277713, Japanese published unexamined patent application No. 2001-053148, Japanese published unexamined patent application No. 2001-168093, and Japanese published unexamined patent application No. 2002-134506.
On the other hand, as semiconductor devices are larger scaled and more highly integrated, the design rules for the interconnection have been diminished as the generations have passed. Conventionally, the interconnection layers have been formed by depositing conducting materials and patterning the deposited conducting materials by lithography and dry etching, but as the generation passes, it has technical limits. As a new forming process which takes the place of the conventional interconnection layer forming process, the so-called damascene process, in which groove patterns and hole patterns are formed in inter-layer insulating films, and conducting materials are buried in the grooves and the holes, is increasingly used. The damascene process can form interconnection layers of low resistance materials, such as copper which is difficult for reactive etching, and is very effective to form low-resistance interconnection layers having micronized patterns.
As the interconnection layers are more micronized, the spacings of interconnections are smaller. Increase of the parasitic capacitance formed via the inter-layer insulating films is one factor for hindering speed-up of semiconductor devices. The use of organic insulating materials having lower dielectric constants (low-kmaterials) than the conventionally used silicon oxide film and silicon nitride film are studied. As the organic insulating materials, an organic-based polymer called "SiLK" (registered trademark) from The Dow Chemical Company, which is an organic SOG material, an organic-based polymer called "FLARE" (registered trade mark) from Honeywell Electronic Materials, etc. are known.
Low dielectric constant materials, such as the above-described organic insulating materials, etc. are largely different from the conventional materials having siloxane bonds, which are based on silicon oxide film in physical properties, such as Young's modulus, hardness and thermal expansion coefficient. Generally, to obtain low dielectric constant, structures, as of atoms or molecules, inside materials must be changed. The dielectric constant can be lowered as inter-atom distances or inter-molecule distances are larger, but increase of inter-atom distances or inter-molecule distances lead to lower bond strength. Accordingly, when a multi-level interconnection structure is formed of low dielectric constant materials, the adhesion in the interfaces with the inter-layer insulating films is lowered in comparison with the adhesion in the interfaces with the inter-layer insulating films of insulating materials based on the conventional silicon oxide film having siloxane bonds, and the mechanical strength of the inter-layer insulating films themselves is also lowered.
Accordingly, it has been found that the semiconductor device having the inter-layer insulating films formed of low dielectric constant materials have lower mechanical strength in comparison with the semiconductor device including the conventional insulating materials and has cracks and peelings due to even the mechanical stresses which have been insignificant in the fabrication process of the conventional structures.
In dual damascene process, for example, in the CMP (Chemical Mechanical Polishing) for planarizing inter-layer insulating films and filling copper interconnection layers, cracks and peelings have been often caused due to mechanical stresses applied to the interfaces between the inter-layer insulating films and inside the inter-layer insulating films.
On the guard rings, the inductors, etc., which are structures of stacked acutely bent interconnections, thermal stresses during processing and stresses from packages after mounted tend to be concentrated, often causing cracks from parts near the pattern corners to the inter-layer insulating films.
Due to wire bonding and formation of bumps, stresses are concentrated on the interconnection materials of pads, and the mechanical stresses often cause cracks in parts upper or lower of the pads.
In the fuse circuit regions of the redundant circuits, cracks are often caused due to thermal impulses of lasers when the metal fuses are cut by the lasers.
The cracks caused in the inter-layer insulating films do not impair device functions. However, the cracks are extended during use of devices, often causing serious problems in the reliability. To solve this problem, structures and fabrication methods which can effectively prevent the cracks and peelings in the semiconductor devices using low dielectric constant materials are expected.

Semiconductor device and method for fabricating the same


A method for providing charged particle beam exposure onto an object having a plurality of chip areas with a plurality of aligning marks formed in correspondence to each of said chip areas. A charged particle beam is irradiated upon an object mounted on a mobile step based upon positions of the aligning marks. Actual positions of the alignment marks are detected and compared to the design positions of the alignment marks to determine approximate relationships which are used to calculate an actual position to perform exposure.

1. Field of the Invention
The present invention relates to a method of and a system for charged particle beam exposure on semiconductor wafers, masks and so on having a coating of resist.
2. Description of the Related Art
As the elements in semiconductor integrated circuits become ever finer, the use of charged particle beam exposure systems will become common, and in such systems, electrons may be used as charged particles. With these systems, it is possible to produce very fine elements, down to 0.05 .mu.m or smaller with alignment accuracy of 0.02 .mu.m or better.
FIG. 1 shows the structure of parts of a charged particle beam exposure system in the prior art.
The object to be exposed here is a semiconductor wafer 10 that is mounted on a mobile stage 11. The wafer 10 is coated with a film of resist and a charged particle beam, in this instance, an electron beam EB, is radiated onto the film to perform exposure.
Above the wafer 10, a blanking aperture array 13 is provided over an aperture 12. As shown in FIG. 2, the blanking aperture array 13 is provided with a plurality of openings 15A to 15C formed in grid pattern in a thin substrate and is also provided with common electrodes 16A to 16C and blanking electrodes 17A to 17C which project downward and which are formed at the edges of the openings 15A to 15C respectively. The openings 15A to 15C may be, for example, squares whose sides are 25 .mu.m, and the number of these openings may be 16.times.64. An electron beam EB, which is made to run approximately parallel by an electromagnetic lens 19 and which has a nearly consistent current density, is radiated on to the blanking aperture array 13. The point of irradiation on the wafer 10 of a portion of the electron beam that has passed through one opening 15 may be, for example, an approximate square with sides of 0.08 .mu.m.
By setting the voltage between the common electrodes 16A to 16C and the blanking electrodes 17A to 17C to 0 or Vs, the electron beam that passes through the openings 15A to 15C is either radiated onto the wafer 10 after passing through the aperture 12, shown in FIG. 1, or it is blocked by the aperture 12. As a result, by setting the common electrodes 16A to 16C at 0V and also by supplying a voltage pattern that corresponds to the pattern to be exposed to all the blanking electrodes 17A to 17C from a blanking control circuit 14, a very fine pattern can be exposed onto the semiconductor wafer 10.
However, since exposure is performed by the charged particle beam scanning over the semiconductor wafer or a mask, the exposure takes longer than in photo exposure. Because of this, it is necessary to improve the throughput of the charged particle beam exposure system. Generally speaking, improving the throughput also entails a loss of exposure positional accuracy, which results in a reduction in processing accuracy. Thus, an improvement in exposure positional accuracy is required together with an improvement in throughput.
Scanning the electron beam EB on the wafer 10 is performed by the mobile stage 11, and a main deflector 20 and a sub deflector 30 that are positioned over the mobile stage 11. Normally, the main deflector 20 is an electromagnetic type and the sub deflector 30 is an electrostatic type.
The ranges of movement from the greatest to the least whereby scanning can be performed are provided by: the mobile stage 11, the main deflector 20 and the sub deflector 30, in that order. However, the order of scanning speed is the reverse, with the sub deflector 30 first, the main deflector 20 next, and the mobile stage 11 last. By taking advantage of these scanning characteristics, scanning with the electron beam EB on the wafer 10 is performed, for example, as shown in FIG. 3.
That is, the electron beam EB is scanned by the sub deflector 30 within a subfield F in direction A. Every time the scanning within one subfield F is completed, step scanning is performed by the main deflector 20 by the width of the subfield F in the direction B of the stripe ST (in the direction which runs at a right angle to the direction A). Also, with the mobile stage 11, scanning in direction C which is perpendicular to direction B is continuously performed. The length of the stripe ST may be 2 mm, with one side of the subfield F being 100 .mu.m, for instance.
(1) Reduction of throughput in an exposure system imposed by the setting time.
In FIG. 1, the main deflection data DM are converted to analog by a D/A converter 21 and then this data DM is amplified at an amplifying circuit 22 to be supplied to the main deflector 20 as a drive current I. Likewise, the sub deflection data DS is converted to analog by D/A converter 31 and then this data DS is amplified at an amplifying circuit 32 to be supplied to the sub deflector 30 as a drive voltage V.
When scanning with the electron beam EB in direction A in FIG. 3 with the sub deflector 30, the drive voltage V changes in a small step for every pulse of the electron beam EB and when swinging back from the trailing end to the leading end of a scan in direction A, the drive voltage V changes in a large step, in correspondence with the dotted lines. FIG. 4A shows the waveform of the drive voltage V when it changes in a small step and FIG. 4B shows the waveform of the drive voltage V when it changes in a large step.
Due to the frequency characteristics of the amplifying circuit 32 and the capacity of the sub deflector 30, the setting time of the drive voltage V cannot be set to 0 when the input of the amplifying circuit 32 changes in steps. During this setting time, exposure cannot be performed because the deflecting error is significant. Therefore, it is wait time and it is a cause of reduced throughput of the charged particle beam exposure system.
Since the number of changes is larger when the changes are in small steps than when they are in in large steps, in the prior art, the characteristics of the amplifying circuit 32 are adjusted in such a manner that the setting time .DELTA.t1 for the small step change is at a minimum. Because of this, if the setting time .DELTA.t1 is set at 100 ns, for example, the setting time .DELTA.t2 for the large step change is a relatively large value, i.e., 500 ns. This prevents any improvement in throughput in the charged particle beam exposure system. The aforementioned adjustment is performed by changing the electrostatic capacity of the capacitor that is included in the amplifying circuit 32, through which high frequency components pass.
On the other hand, there is a significant transient waveform included in the outputs of both of the D/A converters 21 and 31 in FIG. 1, and the their setting time also presents a cause for reduction in throughput of the exposure system.
In the D/A converters, as shown in FIG. 5A, for instance, the output ends of constant current sources 210 to 213, the input ends of which are commonly connected to a source wire VCC, are connected to the input end of a operational amplifier 218 via analog switches 214 to 217 respectively, and the resistor 219 is connected between the input end and the output end of the operational amplifier 218. The constant currents I, 2I, 4I and 8I are output from the constant current sources 210 to 213 respectively.
When simultaneously turning ON the analog switches 214 to 217, from the state in which the analog switches 214 to 217 are all OFF, because of differences in operating speed among the analog switches 214 to 217 and the like, the analog switches 214 to 217 are not turned ON perfectly simultaneously. As a result, a transient waveform (glitch waveform) as shown in FIG. 5B is included in the output of the operational amplifier 218. Because of its origin, the magnitude of this glitch waveform depends upon the values at the input of the D/A converters before and after the change.
(2) Reduction in throughput of an exposure system due to a reduction in the deflection area of an electrostatic deflector
FIG. 6A is a perspective view of an electrostatic deflector in the prior art and FIG. 6B is a cross section through the line 6B--6B in FIG. 6A.
Four pairs of electrostatic deflecting electrodes a1 to a4 and b1 to b4 that face opposite each other are formed by plating a conductive material onto the inner surface of a cylindrical member 301 which is formed in one piece by injection. A wire 302 for applying a voltage from the outside is connected to the end of each electrode. Reference number 303 indicates a portion where the plating is cut and the other corresponding portions are identical.
With the four pairs of electrodes, a consistent electrical field is formed over a wider region compared with an arrangement with only two pairs of electrodes that are positioned at a right angle to each other to cause deflection in direction X and in direction Y. In each pair of electrodes, one is set at 0V, or, potentials whose absolute values are equal to each other but whose signs are opposite are applied from a complementary output type amplifier.
FIG. 7 shows the path that is obtained when an electron beam EB is deflected in the direction indicated with the arrow A1 with a one-stage electrostatic deflector 30A within an electromagnetic lens (not shown). Since the magnetic field of the electromagnetic lens causes the electron beam EB to converge, the electron beam EB running along the z-axis is deflected as indicated with the arrow. This path turns spirally as indicated with the dotted line when viewed in the x-y plane which contains the x-axis and the y-axis, and which lies at a right angle to the z-axis, restricting the deflection area.
With a reduced sub deflection area, the number of times the main deflector is operated increases and, on the other hand, since the setting time for a deflection imparted by the main deflector is longer than for one imparted by the sub deflector, the throughput of the electron beam exposure system is reduced.
This problem becomes more pronounced when an electrostatic deflector 30 is positioned within an immersion lens 40, which is constituted with the lens portions 40A and 40B provided above and below the wafer 10. The immersion lens 40 achieves low aberration and high resolution by forming a strong magnetic field on the wafer 10 to converge the electron beam EB, making more fine processing possible.
The following methods may be employed in order to increase the sub deflection area:
(a) Increase the deflection voltage. PA1 (b) Reduce the distance between electrostatic deflecting electrodes that face opposite each other. PA1 (c) Lengthen electrostatic deflecting electrodes.
However, since an amplifier capable of high voltage output has inferior response characteristics, with method (a), the throughput of an electron beam exposure system is reduced. With method (b) or (c), the processing accuracy on the inner surface of the cylindrical member 301 is reduced and, consequently, the deflection accuracy is also reduced. As the path of the electron beam EB within the immersion lens 40 rotates spirally, only a very small increase in deflection area is achieved with method (c).
(3) Reduction in throughput of an exposure system caused by a long shift time between subfields required by an electromagnetic deflector
In order to utilize an electron beam exposure system for LSI mass production, the total of exposure time per wafer must be equal to or less than 3 minutes.
As shown in FIG. 11, for instance, electromagnetic deflectors 20A to 20D are positioned in four stages in the direction of the optical axis and their coils are connected in series with the number of turns at, for example, 80 and the inductance at approximately 50 .mu.H. Because of this, the response is low and the shift time between the subfields F in FIG. 3 is, for example, 50 .mu.sec. The number of subfields in a wafer 8" in diameter is typically 2.4.times.10.sup.6 making the total length of shift time 120 sec. This would make it impossible to utilize an electron beam exposure system for LSI mass production.
In order to solve this problem, a method has been disclosed (First Publication No. 62-277724 of Japanese Patent Application, U.S. Pat. No. 4,853,870) in which the difference V1X-V2X between the output V1X of the D/A converter 21 and the monitor output V2X of the amplifying circuit 22 in FIGS. 1 and 9 is detected, to be added to the input of the differential amplifying circuit 32.
However, while the deflection area within subfields is -50 to 50 .mu.m, a voltage capable of deflecting by approximately 100 .mu.m must be applied to the sub deflector 30 at the rise of the output V1X of the D/A converter 21 during a shift between subfields and it is necessary, therefore, to approximately double the amplification factor of the amplifying circuit 30. This reduces the SN ratio, which in turn causes a problem that the exposure positional accuracy when scanning within subfields with the sub deflector 30 is reduced.
(4) Reduction in throughput of an exposure system due to long alignment time of patterns between layers.
During the manufacturing process of a semiconductor integrated circuit, it is necessary to mode a circuit pattern with aligning several tens of layers on a semiconductor wafer. The minimum pattern size of a 256 Mbit DRAM is 0.25 .mu.m, for example, and the tolerance for layer alignment is equal to or less than 1/8 of that, i.e., 0.031 .mu.m, which means that a very high degree of alignment accuracy is required.
As shown in FIG. 10, in an electron beam exposure process, chip areas 10i, 1=1 to n are formed on the semiconductor wafer 10 and around each chip area 10i, aligning marks Ai, Bi, Ci and Di for layer alignment are formed. When exposure is performed with a stepping projection aligner, the global alignment method, in which, of n number of chip areas 10i, the positions of the aligning marks Ai for 3 chips areas 10i are detected, for instance, and based upon the relationships with the corresponding positions in design, a relational expression that expresses the relationship between the design position of a given aligning mark Ai and its actual position and the semiconductor wafer 10 is determined to be used for alignment.
However, since a high degree of alignment accuracy is required in electron beam exposure, as mentioned earlier, the di-by-di alignment method is employed, wherein the aligning marks Ai, Bi, Ci and Di for each chip area 10i are detected for alignment. For example, when 50 chip areas are formed on a semiconductor wafer 10 with a 6-inch diameter, while electron beam exposure for one layer takes 2 minutes, it takes 7 minutes to detect all the aligning marks, resulting in low throughput of electron beam exposure.
(5) Reduction in the exposure pattern accuracy due to astigmatism of an electromagnetic lens
As shown in FIG. 11, electromagnetic main deflectors 20A1 to 20A4 and an astigmatism correction coil 41, for deflecting an electron beam EB, are provided on the inside of an electromagnetic lens 40A. An electron beam EB0 diverges from the point of intersection of the optical axis 42 and the lateral cross sectional plane 43 of the electron beam EB when the deflection quantity is 0, and is converged onto the wafer 10 by the electromagnetic lens 40A as indicated with the solid line.
FIG. 12A shows a situation in which the astigmatism correction coil 41 is not operated. Because of the astigmatism of the electromagnetic lens 40A, the cross-over point CX of the X-Z cross section plane 44X and the cross-over point CY of the Y-Z cross section plane 44Y of the electron beam are offset, and the electron beam spot on the wafer becomes rectangular as indicated by the shaded area. If there is no astigmatism present, the electron beam spot 46 is square. The astigmatism correction coil 41 generates a magnetic field which expands or contracts the shape of the lateral cross sectional plane of an electron beam to correct the astigmatism.
The X-Y cross section plane 44X, the Y-Z cross section plane 44Y of the electron beam and its spot 45 on the wafer when the position PZ of the astigmatism correction coil 41 on the optical axis is set at PZ>CX, PZ=CX, CY<PZ<CX, PZ=CY and PZ<CY for the astigmatism at the Y-Z cross section 44Y in FIG. 12A are shown in FIG. 12B to 12F respectively. Reference numbers 471 to 474 indicate the directions, i.e., direction X and direction Y of the electromagnetic force applied to the electron beam EB by the magnetic field generated by the astigmatism correction coil 41. For the sake of simplification, it is assumed that the cross section of the electron beam instantaneously changes when it is at a position in direction Z of the astigmatism correction coil 41.
Since, on the optical axis 42, the electromagnetic force generated by the astigmatism correction coil 41 cancels itself to 0, in FIG. 12C there is no change in the X-Z cross section 44X of the electron beam and only the Y-Z cross section 44Y is enlarged at a position in direction Z of the astigmatism correction coil 41. Consequently, by adjusting the electric current supplied to the astigmatism correction coil 41, the electron beam spot 45 can be aligned with the electron beam spot 46 obtained when there is no astigmatism.
However, cross-over points vary depending upon the position within the electromagnetic lens 40A, i.e., depending upon the deflection position of the electron beam EB and, therefore, the astigmatism correction coil 41 cannot be position aligned with the cross-over point CX. It is the same when there is an astigmatism generated at the X-Z cross section 44X.
Actually, it is verified that the shape of the cross section of the electron beam EB distorts at the corners of the deflection area. For example, compared to the regular shape, the shape of the cross section of the electron beam becomes flattened at the upper right corner, and it becomes oblong at the lower left corner. When the cross section of the electron beam EB is a 3 .mu.m.times.3 .mu.m square, for instance, the quantity of change in the shape of the cross section is equal to or less than 0.1 .mu.m for each side. In order to meet with the requirement of more fine patterns, it is necessary to raise the accuracy of astigmatism correction to a level higher than that achieved currently.

Method of providing changed particle beam exposure in which representative aligning marks on an object are detected to calculate an actual position to perform exposure


A process for transporting a fluid in a pipe under conditions where hydrates may form. In the process, the pipe fluid contains at least one of a gaseous hydrocarbon or liquid hydrocarbon and water and the water content is less than the liquid hydrocarbon content. The process includes the steps of 1) adding a dispersive additive in a hydrocarbon solution to the fluid to be transported, so as to form an emulsion, 2) transporting the liquid and gaseous hydrocarbons in the presence of water and the hydrates, 3) separating the gas phase, the hydrocarbon liquid in excess and a liquid hydrocarbon phase comprising the hydrates and the dispersing additive, and 4) separating the liquid hydrocarbon phase comprising the hydrates and the dispersing additives. The liquid hydrocarbon phase comprising the hydrates is separated by dissociating the hydrates to form a water-in-oil emulsion, the additives being solved in the oil or liquid hydrocarbon, and breaking the water-in-oil emulsion so as to obtain an aqueous phase and a liquid hydrocarbon comprising the additives. Finally the liquid hydrocarbon phase containing at least part of the dispersing additive from step 4, is recycled to a point in the pipe.

Such hydrates may form when water is in the presence of light hydrocarbons, either in the gas phase or dissolved in a liquid phase, such as a liquid hydrocarbon, and when the temperature reached by the mixture becomes lower than the thermodynamic hydrate formation temperature, this temperature being given for a given gas composition and pressure value.
Hydrate formation can be feared notably in the petroleum and gas industry where hydrate formation conditions can be met. In fact, in order to decrease the production cost of crude oil and gas, as regards investment as well as development, one of the means considered, notably in offshore production, consists in reducing or even doing away with the processings applied to the crude oil or to the gas to be transported from the reservoir to the coast, and notably in keeping all or part of the water present in the fluid to be transported. Offshore processings are generally performed on a platform situated at the surface close to the reservoir, so that the effluent, initially hot, can be processed before the thermodynamic hydrate formation conditions are reached as a result of the cooling of the effluent circulating in a pipe in indirect contact with sea water. This procedure is particularly advantageous when offshore production is performed in a zone that is difficult of access. However, the major drawback thereof lies in the risks of hydrate formation due to the presence of water.
In fact, petroleum effluents containing a gas phase and possibly a liquid phase can consist, for example, of a natural gas, a condensate gas or an associated gas mixed with crude oil. They are generally water-saturated and they may even contain free water in some cases.
During the transportation of production effluents from an underwater natural gas or oil and gas reservoir, containing water, the sea bottom temperature can be of the order of 3.degree. or 4.degree. C. Such a temperature leads to a fall in the temperature of the effluent produced, which can bring the latter into thermodynamic conditions favourable to the formation of hydrates, that agglomerate and block production pipes.
Hydrates are inclusion compounds formed from water and light hydrocarbons such as methane, ethane, propane, iso or n-butane. Nitrogen, as well as certain acid gases present in natural gas, such as carbon dioxide or hydrogen sulfide, can also form hydrates in the presence of water.
The formation, then the agglomeration of hydrates lead to the filling and to the clogging of transmission pipes, which eventually prevents passage of oil or gas and has extremely serious consequences. In fact, these phenomena can lead to production stops and to considerable financial losses. Furthermore, restarting the facility, notably in the case of offshore production or transportation, can be long since the decomposition of the hydrates formed is very difficult to achieve.
Conditions favourable to the formation of hydrates can also be met in the same way onshore, for pipes buried near the ground surface for example when the temperature of the ambient air is quite low, notably in northern zones such as arctic zones.
In order to avoid such drawbacks, one has tried in the prior art to use products that, added to the fluid, act as inhibitors by lowering the thermodynamic hydrate formation temperature. These are notably alcohols, such as methanol, or glycols, such as mono-, di- or triethylene glycol. This solution is very costly since the amount of inhibitors to be added can reach 10 to 50% by weight of the water content and these inhibitors are difficult to recover completely.
It has also been recommended to insulate or even to heat transmission pipes by means of a suitable device, such as described in patent application WO-90/05,260, in order to prevent too fast a cooling of the fluids transported. Such devices are nevertheless expensive and complex as far as their technical realization is concerned.
Other means consist in using radiations, for example, patent HU-18,511 teaches to send an electromagnetic wave whose frequency values and modes of propagation are selected to cause the hydrates formed to melt.
In patent SU-442,287, an ultrasonic wave is used to break the hydrate crystals and to release the trapped gas.
The use of additives capable of modifying the hydrate formation mechanism has also been described, where the hydrates formed disperse in the fluid without agglomerating and without clogging the pipes rather than quickly agglomerate with each other and form very solid plugs. The applicant's patent application EP-A-323,774 can be cited in this respect, which describes the use of non-ionic amphiphile compounds selected from the polyol and carboxylic acid esters, substituted or non-substituted, and the imide function compounds. The applicant's patent application EP-A-323,775 can also be cited, which notably describes the use of compounds belonging to the fatty acid or fatty acid derivative diethanolamides family. Patent U.S. Pat. No. 4,956,593 describes the use of surface-active compounds such as organic phosphonates, phosphate esters, phosphonic acids, their salts and their esters, organic polyphosphates and their esters, as well as polyacrylates and polyacrylamides. Patent application EP-A,457,375 describes the use of anionic surface-active compounds such as alkylsulfonic acids and their alkali metal salts. Amphiphile compounds obtained by reaction of at least one succinic derivative, selected from the group consisting of the amides and the polyalkenylsuccinic anhydrides, on at least one polyethyleneglycol monoether have also been proposed to reduce the agglomeration tendency of gas hydrates in patent application EP-A-582,507.
Methods advocating the use of dispersing chemical additives for the transportation of hydrates are interesting because of the low amounts of additives necessary to disperse the hydrate crystals in the liquid hydrocarbon phase. However, the resulting economic saving is limited on the grounds of the cost of the additive, that is higher than the cost of conventional inhibitors such as methanol or the glycols.
It is therefore advantageous and beneficial to recover and to re-use the dispersing additive at least partly.

Process for recycling a dispersing additive used for the transportation of a condensate gas or of an oil with associated gas in the presence of hydrates


A computer product for controlling a color-reproduction process employing N colorants, where N is greater than 3, the computer program product comprises: a computer readable storage medium having a computer program stored thereon for performing the steps of: defining a first transformation from a N-dimensional colorant-signal space associated with the color-reproduction process to a 3-dimensional colorimetric space such that each combination of N colorant signals is mapped to a visual color that would be produced by the process in response to that combination of signals; defining a second transformation for mapping from a 3-dimensional parameter space into the N-dimensional colorant-signal space for defining a particular 3-dimensional subspace of the N dimensional colorant-signal space for ultimately restricting the permitted combinations of the N colorant signals; combining the first and second transformations for defining a third transformation for transforming data directly from the 3-dimensional parameter space to the 3-dimensional calorimetric space; finding the mathematical inverse of the third transformation for defining an inverse transformation which transforms data from the 3-dimensional calorimetric color space to the 3-dimensional parameter space.

It is well known from color-matching experiments that the human visual system, under normal conditions, is trichromatic in nature. Color information is acquired in the retina by absorption of light in three distinct types of sensor cells (the "cones") having different broad-band spectral sensitivities. The neural signals generated in the retina, therefore, can be represented mathematically as a vector in a 3-dimensional space. A number of different 3-dimensional vector spaces have been used to represent visual colors; most notable are those defined over the years by the Commission Internationale de l'Eclairage (CIE), such as CIE 1931 XYZ, CIE 1976 L*a*b* (CIELAB), and CIE 1976 L*u*v* (CIELUV). In these spaces, a point represents a color visually distinct from those represented by all other points. The CIE has established and recommended practices for measuring and computing the coordinates in these spaces corresponding to real objects and illuminants; these practices together are known as colorimetry.
A corollary of the trichromatic nature of color vision is that the satisfactory reproduction of colors requires the use of 3 independent colorants. Three degrees of freedom are required in the color-reproduction system in order to vary the color stimulus over the 3 dimensions sensed by the human retina. For instance, color television and computer monitors use an additive set of red, green, and blue (RGB) phosphors. Color photography is based on a subtractive set of cyan, magenta and yellow (CMY) dyes. A number of printers and copiers also rely on overprints of CMY colorants.
Nonetheless, many systems use more than the required 3 colorants. Any reproduction process has a limited gamut, or range, of reproducible colors. The use of additional colorants can expand the gamut. Furthermore, particular additional colorants may be used to stabilize the reproduction process for particularly important colors, such as neutrals.
Most commonly, black is added to the set of subtractive primaries. In offset printing, for example, the use of black ink increases the dynamic range of the process, by permitting the reproduction of darker neutrals. It also stabilizes the process somewhat against mis-registration of the halftone screens and batch variations in the primary inks.
Examples of such processes are:
offset lithography, in which the "four-color process" employs printing inks as colorants applied to paper, in a halftone screen pattern, by a printing press; PA1 gravure printing, which also employs printing inks applied to paper; PA1 off-press proofing systems, which employ toners as colorants to simulate the effect of an offset press; PA1 computer-driven printers, which use a variety of technologies and colorants, such as jettable inks, toners, and dyes, applied in various continuous-tone, halftone, or dithered patterns.
Most of these processes make use of three chromatic colorants. In addition they may use an achromatic, or black, colorant (abbreviated as K). Thus, the chief application of the current invention is for CMYK systems, although it is clearly generalizable to systems using additional chromatic colorants, such as red, orange, pink, green, or blue.
Since the colorant space in these CMYK systems has a higher dimension (4) than the visual color spaces (3), there is generally no unique way to reproduce a given color. Typically, in fact, there is an infinite number of possible CMYK overprints that can render the same visual color. The resulting ambiguity in determining the rendering of colors has to be resolved by imposing constraints and aims on the overprints. For offset printing, for example, these take the form of restrictions on the total area coverage (TAC) of the 4 halftone separations and preferences in the utilization of black ink; these restrictions and preferences arise mostly from practical considerations of press control, quality assurance, cost reduction, etc., rather than from the intrinsic nature of color reproduction.
The current invention is a method of imposing such constraints and aims in a flexible and useful manner.
Color separations for offset printing have traditionally been produced from photographic originals through the use of RGB separation filters. Originally, these methods involved optical exposure of photographic transparencies. More recently, electronic scanning devices (first analog and subsequently digital) have been employed to separate the red, green, and blue content of the original image and convert the information into electrical signals. Typically, these RGB signals are then converted to CMY signals, which are then used to drive the printer, the film writer, or other output device. The simplest form of this conversion is the complement function: EQU C=1-R EQU M=1-G EQU Y=1-B
(Here the signals are assumed to range over the interval 0, 1!.) This simple form is not usually satisfactory, because the physics of the CMY color-reproduction process is complex and not directly related to the spectral sensitivities of the RGB filters. An empirical color-correction matrix is usually needed to convert RGB to CMY in such a way as to preserve acceptable fidelity in the reproduced colors.
Subsequently, a K signal is generated, in order to add black to the CMY overprints. There are many ways to do this, and scanning systems provide many options that can be selected by the operator. Frequently, for instance, it is desirable to avoid using black entirely in the lighter parts of the image, but to increase its use progressively in the darker parts. In some cases, there is a preference to restrict the use of black to neutral colors (grays) and near-neutrals, while, in others, black continues to be used even for moderately saturated (but dark) colors In general, these possibilities can be implemented by making K a function of the primary signals. In particular, a common approach is to make K a function of the minimum of C, M, and Y (for instance, Gaulke and Jung, U.S. Pat. No. 4,482,917).
When black is added to an overprint, the amount of primary colorant must be reduced, in order to keep the color from darkening. Certain CMY overprints reproduce shades of gray and are, therefore, visually equivalent to certain quantities of black colorant printed alone. These neutral overprints typically require an approximately equal balance of the cyan, magenta, and yellow colorants, although the balance is not exact for most processes. These equivalent overprints can be used to compute the reduction in CMY that should accompany the addition of K in order to preserve an approximate shade of gray in a neutral overprint. If black is used in the printing of chromatic colors, somewhat different methods may be required to preserve color fidelity (Gaulke and Jung, op. cit.).
Various strategies have developed in the printing industry for using more or less black in printing various colors and adjusting the amount of primary colorant accordingly. These have been known as Under Color Removal (UCR), Grey Component Replacement (GCR), and Under Color Addition (UCA). Unfortunately, these terms have been used differently by different writers and have lost the precise meaning they may once have had. Accordingly, here these terms will be avoided, and a distinction will be made instead between the use of black on-axis (i.e., for neutrals) and off-axis (i.e., for chromatic colors). Regardless of the terminology, however, the usual approach has been to convert RGB to an initial CMY signal; K is generated on the basis of this CMY; the CMY is then readjusted, on the basis of K, in order to approximate the color that would have been printed by the initial CMY. Thus, the signal-processing chain is RGB.fwdarw.(CMY).sub.i .fwdarw.CMYK!, where the subscript "i" distinguishes the initial values.
Most of these earlier methods cannot automatically preserve color fidelity to a high degree of accuracy, because the conversion of RGB to (CMY).sub.i and the conversion of (CMY).sub.i to CMYK are not based on realistic models of the color-reproduction process. Scanning devices for the graphic arts, therefore, provide (analog or digital) controls so that a trained operator can adjust these conversions empirically to improve the results. This is a difficult procedure, requiring considerable time and skill. More recently, there have appeared a number of digital systems, based on colorimetry, that represent an improved technology. In these systems, a conversion is first made from the RGB scanner signals to a device-independent color space, such as CIELAB. This conversion, e.g., RGB.fwdarw.L*a*b*!, is based on a calorimetric characterization of the scanner. This is followed by a conversion from the device-independent space to the CMYK signals that drive the output device. This second conversion is based on a colorimetric characterization of the reproduction process (offset printing, off-press proofing, inkjet printing, dye-sublimation printing, etc.), so that the colors that are printed will be visual matches to the colors that were scanned, since they correspond to the same CIELAB coordinates.
The mathematics of this second conversion involves the inversion of a model of the process. Color patches are printed with various combinations of the CMYK control signals; calorimetric measurements and computations then yield the corresponding visual colors, represented, for instance, in CIELAB. A mathematical model can then be fitted to the colorimetric data, resulting in a representation of the CMYK.fwdarw.L*a*b*! transformation. The inverse of this transformation must then be computed in order to implement the required conversion L*a*b*.fwdarw.CMYK!. This computation is generally implemented by an iterative search technique, conducted at a regular sampling of points in CIELAB space. The results of the inversion are tabulated, and various interpolation methods can subsequently be used to compute an approximation to the inverse at arbitrary points.
The same problem that occurred in the older technology now reappears in a new form. Just as there is no unique transformation from RGB to CMYK, there is no unique inverse to CMYK.fwdarw.L*a*b*! of the form L*a*b*.fwdarw.CMYK!. In order to remove the ambiguity in the inverse, constraints must be applied.
A typical approach to this problem is disclosed in Van de Capelle et al. (U.S. Pat. No. 5,402,253), which is incorporated herein by reference. As in the older technology, the CMY signals are regarded as the independent dimensions of the colorant space; K, on the other hand, is treated as an extra dimension that must be assigned a specific value by imposing an additional constraint or relation. For instance, K could be assigned a constant value. This would obviously remove the ambiguity in the transformation and permit a unique inverse; however, it would not be of much practical use, since, if K were fixed to a constant non-zero value, it would be impossible to render white by leaving areas of an image blank. Therefore, the referenced patent teaches a more general approach in which K is made to depend on C, M, and Y, and, in particular, may depend on the minimum of C, M, and Y. This is similar to the approach used in the older technology; there is an important difference, however, in that the dependence is not on an initial (CMY).sub.i which is subsequently readjusted. Instead, the relation that is imposed is a dependence of K on the final CMY. This is possible, in the newer technology, because the relation becomes a condition imposed on the iterative search for an inverse, rather than a particular step in a processing sequence.
Another way to look at this is that the relation between K and CMY defines a particular 3-dimensional subspace of CMYK-space. This subspace is selected in such a way that each overprint in the subspace reproduces a different color; i.e., no two points in the subspace map to the same point in CIELAB space. Thus, within the subspace, the inverse is unique.
A similar approach is disclosed in Rolleston et al. (U.S. Pat. No. 5,305,119 and No. 5,528,386). These authors similarly impose a relation between K and CMY. However, their method establishes the form of this relation prior to the calorimetric characterization. The color patches that are printed and colorimetrically analyzed consist of a sampling over CMY-space with the inclusion of K in the overprints as required by the relation. The model is then defined over this 3-dimensional space, and the 4-dimensional ambiguity is avoided from the beginning. The method is less flexible than that of Van de Capelle et al., however, since each choice of the relation requires that a different set of patches be printed and analyzed. For certain applications, such as graphic arts, it is more convenient to define and fit a calorimetric model over the 4-dimensional CMYK-space; various 3-dimensional subspaces can then be selected subsequently, at will, to obtain various behaviors of K with respect to CMY.
The technology described above is deficient in its ability to handle certain practical issues and requirements. For instance, many printing processes have a limitation in the total amount of colorant that can be deposited on a substrate without smearing or running. In offset printing, this is a limit on TAC (total area coverage), which is the sum of the fractional areas covered by the halftone dots in the 4 separations; it can be computed simply as (C+M+Y+K). The TAC limit is generally less than 4.0 ("400% dot coverage") and often less than 3.0 ("300% dot coverage") in typical offset presses. These constraints are difficult to impose within the cited prior art.
Another deficiency in the art is in providing separate controls for the on-axis and off-axis usage of black colorant. The relation between K and CMY, if only a function of a single variable (the minimum of C, M, and Y), may provide a desired on-axis usage, but may then fail to provide the off-axis behavior that some printers may require.
Another deficiency has to do with alternative interpretations of "neutral". In a colorimetric sense, "neutral", or "achromatic", may be defined as "having the same chromaticity as the illuminant". Since the paper stock may impart a slight cast to the chromaticity at the white point, it may be more practical to define "neutral" as "having the same chromaticity as that of the light of the illuminant after reflection from the substrate". This may be regarded as the "true neutral", because the entire gray scale, from white to black, can then be reproduced at the same chromaticity. On the other hand, it has been common practice in offset printing to define "neutral" conventionally, in terms of certain proportions of the printing inks--typically, equal amounts of magenta and yellow, overprinted with a somewhat greater amount of cyan. These overprints, combined with various amounts of black, may not exactly reproduce a true neutral, but they are a close approximation and are preferred by many press operators for practical considerations of press control. Still another possibility, more applicable to computer-driven printers than to printing presses, is to define "neutral" in terms of equal, or balanced, amounts of the 3 primaries; this choice allows the primaries to range independently up to their maximum value, thus maximizing the gamut and dynamic range of the process, even though the darkest "balanced neutral" may have an appreciable color cast relative to the substrate chromaticity. It is difficult to accommodate these possible alternatives within the framework of the existing technology.


In an exemplary method, at least one computing device 1) stores a plurality of content instances associated with a plurality of user profiles, 2) determines, based on a predefined relevance heuristic, a relevance between a user profile and each of the other user profiles included in the plurality of user profiles, 3) prioritizes, based on the determined relevance between the user profile and each of the other user profiles, the plurality of content instances relative to one another, and 4) provides, for display, data representative of the prioritized plurality of content instances.

In computing, a file system is typically configured to translate physical locations on a disk (e.g., a hard drive) to a logical data structure in which electronic files are organized in hierarchical directories. It is not uncommon for such directories to include many hierarchical levels and vast numbers of files. Unless specific information about a particular file or its hierarchical location is known, it can be difficult to locate the electronic file within a conventional hierarchical directory. Difficulties in locating electronic files typically intensify along with an increase in the number of electronic files in a hierarchical directory.
Moreover, with traditional content storage and retrieval technologies, a user who requests content may be inundated with information that is deemed to be related to the requested content. Because of the amount of such information that is returned and/or the difficulty in looking through the information, the user may be overwhelmed by and/or find the information unhelpful.

This patent is subject to a terminal disclaimer.

Systems and methods for prioritizing content based on user profile relevance


A cue message detection synchronizer that provides an out-of-band cue message to downstream content insertion devices. The cue message detection synchronizer receives a first data stream corresponding to a network feed, receives a second data stream corresponding to a provider feed, receives at least one cue message associated with the first data stream, compares the first data stream to the second data stream to determine a data stream offset, and generates cue message comprising one or more of: (i) the determined data stream offset, and (ii) a timestamp associated with the generated cue message and modified by the determined data stream offset. In this way, a location within a synchronized provider stream can be provided to downstream content insertion devices.

Compressed image and video data is stored and transmitted in a standard format known as a compression stream. As is well-known in the art, MPEG (i.e., MPEG-1, MPEG-2, MPEG-4, H.264) compressed video and audio streams may be mapped to MPEG-2 Transport Streams as Elementary Streams (ES) packed into Packetized Elementary Transport (TS) packets. The PES packets contain a PES header which includes, among other things, a Presentation Time Stamp (PTS) and optionally a Decoding Time Stamp (DTS) (in the event the DTS is not present, the DTS is often considered to be equal to the PTS). Further, the MPEG-2 systems layer is responsible for the integration and synchronization of the elementary streams (ES): audio and video streams, as well as an unlimited number of data and control streams that can be used for various applications such as subtitles in multiple languages. This is accomplished by first packetizing the ESs thus forming the packetized elementary streams (PES). These PESs contain timestamps from a system clock for synchronization. The PESs are subsequently multiplexed to form a single output stream for transmission.
Existing methods for performing ad insertion utilize in band cue messages that are included in the broadcast video stream. The cue messages include information that identifies where in the video stream ad insertion points are located. That is, splice points are traditionally signaled in the MPEG-2 Transport Stream by means of STCE-35 cue messages. These messages contain the PTS value of the video frame that corresponds with the intended splice point. However, the process of encoding the broadcast video stream by the provider generally results in the insertion of new time stamps and the cue messages may be removed or selectively passed in the encoded output stream. As a result, the use of in band cue messages has required a high degree of cooperation from the encoded video stream provider (e.g. provider) and the party wishing to make use of the in band triggers. Accordingly, where the provider is unable or is otherwise unwilling to pass additional cue messages for reasons such as system compatibility issues with downstream devices, accurate insertion can be difficult or impossible to perform.

System and method to provide out-of-band broadcast trigger synchronization and communication to insertion devices


The present invention provides a shorting strip structure of a liquid crystal display panel and a liquid crystal display panel. The shorting strip structure includes: an even-numbered gate line and an odd-numbered gate line that are arranged parallel, a plurality of even-numbered data lines and a plurality of odd-numbered data lines that are arranged parallel, and a shorting strip that is arranged parallel to the even-numbered gate line. The even-numbered data lines are perpendicularly connected to the even-numbered gate line. The odd-numbered data lines are perpendicularly connected to the odd-numbered gate line. The shorting strip is electrically connected to ends of the plurality of even-numbered data lines that are adjacent to the even-numbered gate line. The present invention is arranged to have the shorting strip connecting the ends of the even-numbered data lines that are adjacent to the even-numbered gate line to each other to effectively spread out electrical charges and to prevent an issue of circuit burn-out caused by an excessive current that is induced at the time when the electrical charges are eventually discharged due to accumulation, so as to effectively enhance the yield rate of the liquid crystal display panel. Further, the shorting strip and the even-numbered data lines are formed simultaneously so that the manufacture process is simple and the cost is low so as to be favorable for cost control.

1. Field of the Invention
The present invention relates to the field of liquid crystal displaying, and in particular to a shorting strip structure of a liquid crystal display panel and a liquid crystal display panel.
2. The Related Arts
Liquid crystal displays have a variety of advantages, such as thin device body, low power consumption, and being free of radiation, and are thus widely used. Most of the liquid crystal displays that are currently available in the market are backlighting liquid crystal displays, which comprise an enclosure, a liquid crystal display panel arranged in the enclosure, and a backlight module that is arranged in the enclosure. The operation principle of the liquid crystal display panel is that, with liquid crystal molecules interposed between two parallel glass substrates, a drive voltage is selectively applied the two glass substrates to control the rotation of the liquid crystal molecules in order to refract out light emitting from the backlight module for generating images.
A liquid crystal display panel generally comprises: a thin-film transistor (TFT) substrate and a color filter (CF) substrate opposite to and bonded to the TFT substrate and a layer of liquid crystal interposed between the TFT substrate and the CF substrate. Referring to FIG. 1, in the known art of manufacturing of TFT substrate, an even-numbered gate line (M1—even) 100 of a gate metal layer (M1) is arranged to short the even-numbered data lines (M2—even) 500 of a source/drain metal layer (M2) through a transparent conductive layer 300. The transparent conductive layer 300 is generally an indium tin oxides (ITO) layer that is used to make a pixel electrode of a thin-film transistor. An odd-numbered gate line (M1—odd) 700 of the gate metal layer is arranged to short the odd-numbered data lines (M2—odd) 900 of the source/drain metal layer through the transparent conductive layer 300. In this arrangement, the even-numbered data lines 500 or the odd-numbered data lines 900 of the source/drain metal layer are shorted together by means of the transparent conductive layer 300; however, the transparent conductive layer 300 is often set at the fifth layer so that before that, all the lines of the even-numbered data lines 500 and the odd-numbered data lines 900 of the source/drain metal layer are independent of each other and this readily lead to accumulation of electrical charges 500, causing electro-static discharge (ESD) occurring at a weak link, especially ESD being easily generated at the sites where the even-numbered data lines 500 and the odd-numbered data lines 900 of the source/drain metal layer are respectively connected to the even-numbered gate line 100 and the odd-numbered gate line 700 of the metal layer. The peak value of an ESD may get as high as tens amperes and may have an extremely large instantaneous power, so that the energy of the electromagnetic pulses generated by ESD may be large enough to burn out the even-numbered gate line 100 and the odd-number gate line 700, leading to incapability of applying a test signal to the TFT substrate in the subsequent array test process and thus affecting the inspection and maintenance of electrical defects and reducing the yield rate of the TFT substrate.
In light of the above described shortcomings, as shown in FIG. 2, a TFT substrate is proposed for the liquid crystal displays, in which gate lines 131, odd-numbered data lines 172, even-numbered data lines 173, a transparent conductive strip 121, and a gate shorting strip 130 are formed on a transparent substrate 11. The transparent conductive strip 121 is disposed under the gate shorting strip 130. The gate lines 131 are in electrical connection with the transparent conductive strip 121, whereby through electrical charges being transferred by way of the transparent conductive strip 121, balance of electrical charge can be achieved to prevent the occurrence of gate shorting strip 130 and the gate lines 131 being burnt out by ESD thereby enhancing the yield rate of the TFT substrates of liquid crystal displays.
However, disposing the transparent conductive strip 121 under the gate shorting strip 130 would increase the steps of the manufacturing process of the TFT substrate thereby increasing the manufacture cost and becoming disadvantageous for cost control.

Shorting strip structure of liquid crystal display panel and liquid crystal display panel

Shenzhen China Star Optoelectronics Technology Co., Ltd


An apparatus (10) for keeping a down hole drilling tool vertically uses a pendulum (36). The pendulum (36) controls flow from outlets (34) of drilling fluid chambers (30), providing drilling fluid to centralizer (24) activating pistons (26) acting upon centralizer blades (24). When the outer housing (12) deviates from a vertical orientation, the pendulum (36) swings by force of gravity to assume an angularly offset pivotal position. This adjusts the hydraulic pressure in one or two of the outlets (34) for one or two of the drilling fluid chambers (30) resulting in a change in the hydraulic force acting upon one or two of the pistons (26) causing one of the centralizers (24) to change their position to urge the outer housing (12) back toward the vertical position until the pendulum (36) again assumes the concentric pivotal position and the balanced pressure equilibrium in the drilling fluid chambers (30) is restored.

It is difficult to keep well bores vertically aligned when drilling an oil or gas well. An example of an apparatus that is commercially available to keep a down hole drilling tool vertically aligned when drilling a vertical well is a system known by the Trade Mark "VertiTrak" which is marketed by Baker Hughes Incorporated. Another example of an apparatus that is commercial available to keep a down hole drilling tool vertically aligned when drilling a vertical well is a system know by the Trade Mark "Power V" which is marketed by Schumberger Incorporated.

Apparatus for keeping a down hole drilling tool vertically aligned


A ranging procedure is performed using interference cancellation using preamble messages from a plurality of objects, each of which includes a pre-defined orthogonal design coded modulation patterns. A channel for an object may be estimated using the pre-defined orthogonal design coded modulation patterns in the preamble messages received from objects to remove interference of the preamble message received from other objects. A range to an object may be determined based on a determined delay in the preamble message from that object. The range may be used to assist in determining the position of the object. The pre-defined preamble message may be transmitted by receiving a schedule for an access point in a network for a ranging procedure and periodically transmitting a pre-defined preamble message for the ranging procedure, the pre-defined preamble message includes an orthogonal design coded modulation pattern.

1. Background Field
The present invention relates generally to localization of objects and more particular, to ranging of multiple objects using channel estimation.
2. Relevant Background
Location Based Services (LBS) often use satellite based positioning systems, such as the well-known Global Positioning System. For indoor locations, however, satellite based positioning systems, are problematic due to poor signal reception as well as relatively poor resolution. For example, when a satellite based positioning system is used for localization in an indoor environment, the resolution of a few meters that may be achieved with satellite based positioning systems may result in an object being located in an incorrect room.
Typically, when tracking objects or persons in indoor environments, resolution that is superior to that achieved by satellite based positioning systems is desirable. Ranging to access points in the Gigahertz bandwidth range may be used to achieve desired resolutions in indoor environments. Ranging to access points, however, may require the temporary suspension of transmission from access points, such as WiFi™ Thus, it may be desirable to search for multiple objects simultaneously when ranging to access points to reduce amount of time of the suspension of transmission from the access points. Accordingly, it is desirable if multiple objects can communicate with the access points simultaneously. Unfortunately, interference between signals broadcasted by objects being tracked may be problematic with respect to channel estimation, which is necessary to identify which signals are associated with which object.

Method and apparatus for ranging using channel estimation with interference rejection


In a first microcomputer, a communication function is provided for outputting a data signal having a transmission period Tr that has a relation of Td<Tp/2 with a data time Td, and it sends various data processed by itself and carried on the data signal to a second microcomputer, where the received data signal is sequentially stored in a memory, and the various data are read by timing pulses for reading and processed.

In the communication system applied to the occupant protecting device for vehicles, a collision is generally detected by the acceleration sensors each provided in the main ECU and the satellite ECUs, and signals are exchanged between the two to process the result of collision determination or temporary data for the crash in the main ECU.
FIG. 1 is a schematic perspective plan view showing the positional replacement between the main ECU and satellite ECUs on a vehicle. 10 is a vehicle, 11 is the front portion, 12 is the rear portion, and 13a and 13b are the side portions. A main ECU 20 is installed in the central portion of the vehicle 10, and side satellite ECUs 30a and 30b are installed on the side portions 13a and 13b, respectively. Further, at both sides of the front portion 11, there are provided front satellite ECUs 40a and 40b, respectively. The main ECU 20 has a function of detecting a collision occurred at the front side of the vehicle to unfold air bags in front of occupants, particularly the driver and the passenger-side occupant, and a function of receiving collision information from the other satellite ECUs 30a, 30b, 40a, and 40b to unfold the air bags on the side or in front of occupants. The side satellite ECUs 30a and 30b are to detect a side-impact collision by an acceleration sensor, and has a function of determining the accuracy of the collision by its own microcomputer and sending it to the main ECU 20 through communication lines 31a and 31b. Further, the front satellite ECUs 40a and 40b are provided, because an offset collision may not be determined only by the main ECU 20, and they have a function of processing the detection status of the acceleration sensor provided in them by their own microcomputers, and sending the processed data to the main ECU 20 through communication lines 41a and 41b.
Data sent from the satellite ECUs 30a, 30b, 40a, and 40b to the main ECU 20 represent the determination result of collision and the fault diagnosis status of the acceleration sensor under normal conditions. Thus, in the conventional communication system, a trigger signal functioning as a data request command is sent from the main ECU 20 to the satellite ECUs 30a, 30b, 40a, and 40b, and the respective satellite ECUs 30a, 30b, 40a, and 40b transmit a collision determination result or a fault diagnosis result to the main ECU according to the trigger. The main ECU 20 processes and determines the transmitted result, displays a warning or unfolds an air bag.
FIG. 2 is a block diagram showing the schematic circuit configuration for implementing the conventional communication system. In this figure, the required minimum main ECU 20 and satellite ECU 30 in a pair are shown for simplicity.
In the figure, 1 is the battery of the vehicle, by which a d.c. current is supplied to the booster circuit 21 of the main ECU 20 via an ignition switch 2. 3 and 4 are squib resistances for igniting the gun powder for unfolding the air bags (not shown) for protecting the front portion and the side portion of an occupant. If a collision occurs at the front side of the vehicle, an ignition current is supplied to the squib resistance 3 from the booster circuit 21 through a mechanical acceleration switch 27, which closes when it senses an impact in the longitudinal direction of the vehicle, and a switching transistor 28 controlled by a microcomputer 23. To the other squib resistance 4, an ignition current is also supplied from the booster circuit 21 through a switching transistor 29 controlled by the microcomputer 23 upon the occurrence of a side-impact collision to the vehicle. Further, from the booster circuit 21, a d.c. voltage is supplied to fixed-voltage circuits 22 and 32 functioning as the d.c. power supplies for the microcomputers 23 and 33 and other circuits.
Now, the operation is described.
The microcomputer 23 always determines faults of a longitudinal acceleration sensor 24 in the normal condition where there is no collision, and if a fault occurs, it outputs a signal for controlling an alarm (not shown) such as a lamp. If a collision at the front side of the vehicle occurs, the microcomputer 23 determines the detection signal from the longitudinal acceleration sensor 24, which represents a collision state, and outputs a control signal to bring the switching transistor 28 into conduction. At this point, if the mechanical acceleration switch 27 is closed, an ignition current is supplied to the squib resistance 3 to unfold the air bag in front of the occupant.
Further, the microcomputer 23 exchanges signals with a communication circuit 25. Based on a clock pulse, a trigger signal (a) of FIG. 3 of a fixed period is sent from the communication circuit 25 to the side satellite ECU 30 side through a communication interface 26. As described later, a signal (b) or (c) of FIG. 3 sent from the satellite ECU 30 in response to the trigger signal is provided to the microcomputer 23 through the communication interface 26 and the communication circuit 25.
In the satellite ECU 30, the microcomputer 33 performs the normal fault diagnosis of a lateral acceleration sensor 34 and an acceleration switch 37, and determines the detection outputs of the lateral acceleration sensor 34 and the acceleration switch 37, if a collision at its lateral side of the vehicle occurs. In the fault diagnosis, the signal (b) of FIG. 3 is sent to the main ECU 20 side via a communication circuit 35 and a communication interface 36, and if the microcomputer 23 determines that an abnormal state has occurred, the alarm is operated to alert the occupant to it. Further, in the event of a side-impact collision, determination is made in the microcomputer 33 upon receipt of the detection signals of the lateral acceleration sensor 34 and the acceleration switch 37, and the signal (c) of FIG. 3 indicating a collision is sent to the microcomputer 23 through the communication system. Upon receipt of this signal, the microcomputer 23 determines whether the collision has actually occurred, and outputs a control signal to turn on the switching transistor 29 if it determines that the collision is dangerous. Whereupon, an ignition current flows through the squib resistance 4 via the switching transistor 29 to unfold the air bag for side protection.
The conventional communication system is described according to FIG. 3. A trigger signal (a) of repetitive pulses with a fixed period TO is always sent from the main ECU 20 to the satellite ECU 30 side. On the other hand, a diagnosis data provided by checking the fault status of the lateral acceleration sensor 34 and the acceleration switch 37 are outputted from the microcomputer 33, and upon the reception of a predetermined number of pulses of the trigger signal (a), a response signal (b) including the diagnosis data is sent from the communication circuit 35 to the main ECU 20 side. The response signal (b) is provided to the microcomputer 23, which determines the diagnosis data, and issues a control output to drive the alarm if there is anything wrong. Further, if a lateral collision occurs with a vehicle, the response signal is as shown by (c).
Since the conventional communication system is constructed above, the main ECU requires a transmission process for always sending the trigger signal, and a data reception process for the response signal, so the processing is complicated. Furthermore, there is a problem that the satellite ECU requires a circuit for receiving the trigger, causing an obstacle to the downsizing of the device.
This invention was accomplished to solve the above described problem, and its object is to obtain a communication system in which the communication between the main ECU and the satellite ECU is carried out by the start-stop synchronization communication provided in the microcomputer.


Methods are provided for calibrating a process for growing an epitaxial silicon-comprising film and for growing an epitaxial silicon-comprising film. One method comprises epitaxially growing a first silicon-comprising film on a first silicon substrate that has an adjacent non-crystalline-silicon structure that extends from said first silicon substrate. The step of epitaxially growing uses hydrochloric acid provided at a first hydrochloric acid flow rate for a first time period. A morphology of the first film relevant to the adjacent non-crystalline-silicon structure is analyzed and a thickness of the first film is measured. The first flow rate is adjusted to a second flow rate based on the morphology of the first film. The first time period is adjusted to a second time period based on the second flow rate and the thickness. A second silicon-comprising film on a second silicon substrate is epitaxially grown for the second time period using the second flow rate.

The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. An MOS transistor includes a gate electrode as a control electrode disposed overlying a semiconductor substrate and spaced apart source and drain regions disposed within the substrate and between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel within the substrate between the source and drain regions.
Epitaxially-grown silicon films often are used in MOS transistors to modify the performance of such transistors. For example, an epitaxially-grown silicon film can be used to increase the mobility of majority carriers through the channel of an MOS transistor by inducing stresses in the channel. The mobility of holes, the majority carrier in a P-channel MOS (PMOS) transistor can be increased by applying a compressive longitudinal stress to the channel, especially when the transistor is fabricated on a silicon wafer. It is well known that a compressive longitudinal stress can be applied to a silicon MOS transistor by embedding an epitaxially-grown material such as silicon germanium (SiGe) at the ends of the transistor channel. Similarly, the mobility of electrons, the majority carrier in an N-channel MOS (NMOS) transistor can be increased by applying a tensile longitudinal stress to the channel. Such a stress can be applied to a silicon MOS transistor by embedding a material such as epitaxially-grown silicon doped with carbon at the ends of the transistor channel. Such methods typically require the etching of trenches into the silicon substrate and the selective epitaxial deposition of silicon germanium and/or silicon carbon.
Ideally, the epitaxial growth of silicon films is conducted for a time sufficient to ensure that the film has grown to a predetermined thickness within all relevant trenches or on all relevant surfaces of all devices on a semiconductor wafer. Any undergrowth of the epitaxial silicon film can result in device-to-device variations and wafer-to-wafer variations that can reduce device yield. To ensure adequate growth of an epitaxial film across a semiconductor wafer, or from wafer to wafer, the epitaxial silicon film generally is grown for a period slightly longer than that typically required for the film to grow to a predetermined thickness. In other words, the film is slightly overgrown.
While overgrowth may be advantageous for certain purposes, it can be disadvantageous for others. If the overgrown epitaxial silicon film grows uniformly, that is, its leading edge has a relatively flat profile, and the overgrown epitaxial silicon film grows beyond surfaces of an adjacent structure, the epitaxial silicon film is said to have "popped" with respect to the adjacent structure. FIG. 1 illustrates an example of an overgrown epitaxial silicon film 20 that has popped relative to a silicon substrate 12. In this example, an MOS gate structure 10 is disposed on the silicon substrate 12 with dielectric spacers 14 that are formed about sidewalls 11 of the gate structure 10 and that extend beyond an upper surface 15 of the silicon substrate. MOS gate structure 10 comprises a gate insulator 24 on the silicon substrate 12 and a gate electrode 16 disposed on the gate insulator. Trenches 18 are etched into the silicon substrate and are filled with an epitaxially-grown silicon-comprising film 20. As evident in FIG. 1, the epitaxially-grown silicon-comprising film is uniformly overgrown such that the leading edge 17 of the epitaxial silicon-comprising film is relatively flat and the epitaxial silicon-comprising film 20 has grown along, not only side surfaces 19 of the trenches 18, but also along the side surfaces of gate insulator 24 and spacers 14. FIG. 2 illustrates another example of an overgrown epitaxial silicon-comprising film 62 that has popped relative to a shallow trench isolation (STI) structure 60 disposed on silicon substrate 12 and that extends from a surface 63 thereof. As evident in FIG. 2, the epitaxially-grown silicon-comprising film 62 is uniformly overgrown such that a leading edge 61 of the epitaxial silicon-comprising film 62 is relatively flat and the epitaxial silicon-comprising film 62 has grown along a side surface 64 of STI structure 60 and beyond the side surface. One problem with popping results because, typically following the growth of an epitaxial silicon-comprising film, the epitaxial silicon-comprising film is implanted with conductivity-type impurity ions to form source and drain regions of the MOS device. When implanting into the epitaxial layer, the energy of the implant must be adjusted to compensate for the thickness of the layer. For the "popped" case, the overgrown thickness follows the across-wafer, wafer-to-wafer, and lot-to-lot variations inherent in the epitaxy process. This can lead to significant device variability and even yield degradation.
In contrast, it is preferable that the epitaxially-grown silicon-comprising films are "pinned" to an adjacent structure. "Pinning" occurs when growth of the epitaxial silicon-comprising film along the surface of an adjacent structure terminates at the end of the surface, although growth towards the center of the epitaxial silicon-comprising film may continue. In this regard, excess epitaxial silicon growth is minimized particularly at the surface of the adjacent structure, which is most critical for controlling device characteristics, although overgrowth at the center of the film insures the overall growth of the epitaxial silicon-comprising film to a predetermined average thickness. Thus, the amount of additional epitaxial silicon-comprising film that the impurity ions must penetrate to form the source and drain regions or other doped regions is minimized. FIG. 3 illustrates an example of the overgrown epitaxial silicon-comprising film 20 of FIG. 1 that is pinned relative to the silicon substrate 12. As is evident in FIG. 3, growth of the epitaxial silicon-comprising film 20 along the side surfaces 19 of the trenches 18 terminated at an end of the side surfaces 19 while growth of the film 20 towards its center continued. Similarly, FIG. 4 illustrates the overgrown epitaxial silicon-comprising film 62 of FIG. 2 that is pinned relative to the STI structure 60. As evident in FIG. 4, growth of the epitaxial silicon-comprising film terminated at the end of the side surface 64 of STI structure 60 while growth of the film 62 towards its center continued. Thus, it is desirable to grow epitaxial silicon-comprising films that provide for overgrowth but also provide for pinning at surfaces of adjacent structures.
While it is desirable to have overgrowth and pinning that are uniform from device to device on a wafer and from wafer to wafer, such uniformity may be compromised when variations in the growth process arise due to, for example, equipment malfunction, change in environmental conditions, and the like. A change in the uniformity of overgrowth and pinning can result in implant shadowing and varied implant profiles, which in turn can result in significant differences in device characteristics from device to device, wafer to wafer, and lot to lot.
Accordingly, it is desirable to provide methods for calibrating a process for growing epitaxial silicon-comprising films that result in both overgrowth of the films and pinning of the films to adjacent structures wherein the overgrowth and pinning is uniform across a wafer. In addition, it is desirable to provide methods for growing epitaxial silicon-comprising films that result in overgrowth and pinning to adjacent structures wherein the overgrowth and pinning is uniform across a wafer. Further, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.

Methods for calibrating a process for growing an epitaxial silicon film and methods for growing an epitaxial silicon film


The method for forming a coating film includes: supplying a first liquid from a nozzle to a cylindrical substrate to thereby form the coating film of the first liquid, wherein the method includes, pressing a member including a second liquid, to form a liquid film of the second liquid on the peripheral surface, and forming the coating film of the first liquid includes: supplying the first liquid onto the liquid film of the second liquid formed on the peripheral surface of the substrate to form a bead of the first liquid between the liquid-supplying unit and the liquid film of the second liquid, and extending the bead in a circumferential direction of the substrate.

1. Field of the Invention
The present invention relates to a method for forming a coating film of a coating liquid on the peripheral surface of a cylinder/column-shaped substrate for use in charging, development, transfer, fixing, pressurizing or the like in an electrophotographic apparatus such as a copier or a printer, and a method for producing an electrophotographic fixing member.
2. Description of the Related Art
In an electrophotographic apparatus such as a copier or a printer, a member such as a cylinder/column-shaped belt or roller is used in various processes such as charging, development, transfer, fixing and pressurizing. In such a member, a functional film for exhibiting a required function is formed on a substrate depending on the application of the member. In the present specification, a cylinder-shaped substrate or a column-shaped substrate is also simply referred to as "substrate" in some cases.
Such a functional film can be formed by forming a coating film of a coating material for forming the functional film on the peripheral surface of the substrate, and drying or if necessary curing the coating film. Then, as a method for forming the coating film on the peripheral surface of the substrate, a spiral method is known (see Japanese Patent Application Laid-Open No. 2002-370065).
The spiral method is a method in which, while allowing a substrate to relatively rotate against a coating liquid-supplying unit and also allowing the coating liquid-supplying unit and the substrate to relatively move in the direction along with the rotation axis of the substrate, a coating liquid is supplied from the coating liquid-supplying unit to form a coating film on the peripheral surface of the substrate.
The spiral method can shorten the time required for coating with the coating material, and achieve the high use efficiency of the coating liquid. Therefore, a reduction in production cost can be achieved.
According to studies by the present inventors, however, the coating film formed by using the spiral method may have spiral unevenness in thickness due to the rotation period of the substrate.
The functional film of the member for use in the electrophotographic apparatus, if having an uneven thickness, may have an influence on the quality of an electrophotographic image. Therefore, the coating film formed on the substrate is required to be highly uniform in thickness.
In particular, a fixing member having a layer formed by curing an addition curing type silicone rubber composition (hereinafter, also referred to as "cured silicone rubber layer") is often used in a thermal fixing apparatus of the electrophotographic apparatus. In such a fixing member, a primer layer is formed on the peripheral surface of the substrate before formation of the cured silicone rubber layer, in order to allow the substrate and the cured silicone rubber layer to tightly adhere to each other.
Here, the primer layer may include a reactive component with an unsaturated aliphatic group (vinyl group) included in the cured silicone rubber layer to be formed thereon. In such a case, the reactive component may be transferred from the primer layer to the cured silicone rubber layer, and the reactive component and the unsaturated aliphatic group may react with each other in the cured silicone rubber layer, resulting in an increase in hardness of the cured silicone rubber layer. If the primer layer here has partial unevenness in thickness, the amount of the reactive component transferred to the cured silicone rubber layer is partially different, resulting in causing partial unevenness in hardness of the cured silicone rubber layer. Such partial unevenness in hardness of the cured silicone rubber layer can cause unevenness in melting of a toner in thermal fixing of an electrophotographic image, thereby causing unevenness in gloss in the electrophotographic image.
Therefore, the present inventors have recognized that if a coating film of a raw material for primer layer formation is formed on the substrate by using the spiral method that is advantageous in terms of costs, a new technique is required to be developed in order to cause no spiral unevenness in thickness on the coating film.
Then, the present invention is directed to providing a method for forming a coating film, which can more suppress the occurrence of unevenness in thickness of a coating film in formation of the coating film on the peripheral surface of a substrate.
Further, the present invention is directed to providing a method for producing an electrophotographic fixing member, which contributes to formation of a high-quality electrophotographic image.

Method for forming coating film and method for producing fixing member


A print medium includes a plurality of print areas and a plurality of identification markers. The plurality of print areas are set along a longitudinal direction on a printing surface. The plurality of print areas are a plurality of areas on which printing is to be performed. The plurality of identification markers are intermittently printed along the longitudinal direction on the print medium. Each of the plurality of identification markers includes a set of leading edge information and identification information and is printed in correspondence with a single print area group. The leading edge information is information for setting a leading edge position of the print area in the feed direction. The identification information is information for identifying a type of the print medium. The print area group is formed of a plurality of mutually adjacent print areas among the plurality of print areas.

The present disclosure relates to a long sheet-shaped print medium, a printer, and a medium.
A long sheet-shaped print medium and a printer that prints characters etc. on the print medium are known. For example, a label paper is known in which a plurality of labels are provisionally attached at a predetermined interval on the top surface of a belt-shaped base paper, and detection markers are printed on the rear surface on a side edge in positions corresponding to a leading edge of each of the labels. A label printer detects the leading edge position of each individual label by reading the detection marker using a photo-detector. The label printer reads a number of a plurality of lines that form the detection marker and reads intervals between the plurality of lines to distinguish a label type, and then performs printing on the label paper.