Embodiments of the invention relate to a process for fabricating a silicon-on-insulator structure comprising the following steps: providing a donor substrate and a support substrate, only one of the substrates being covered with an oxide layer; forming, in the donor substrate, a weak zone; plasma activating the oxide layer; bonding the donor substrate to the support substrate in a partial vacuum; implementing a bond-strengthening anneal at a temperature of 350° C. or less causing the donor substrate to cleave along the weak zone; and carrying out a heat treatment at a temperature above 900° C. A transition from the temperature of the bond-strengthening anneal to the temperature of the heat treatment may be achieved at a ramp rate above 10° C./s.

Silicon-on-Insulator (SOI) structures are frequently used in Complementary Metal-Oxide-Semiconductor (CMOS) applications.
Such structures comprise, from their useful surface to their bottom side: a thin silicon layer; a buried layer made of a dielectric material that is typically an oxide, such as SiO2; and a support substrate. The buried layer made of a dielectric material is often denoted by the acronym BOX for the term "Buried OXide."
The thicknesses of the thin silicon layer and the oxide layer may vary depending on the intended applications.
In particular, the thickness of the thin silicon layer is reduced to a thickness of 50 nanometers (nm) or less, even 20 nm or less, and especially to about 12 nm in order to allow what are called "FDSOI" ("Fully Depleted SOI") structures to be obtained. Such FDSOI structures have the advantage of significantly reducing operational instability and considerably improved performance relative to what are called "PDSOI" ("Partially Depleted SOI") structures in which the thickness of the thin silicon layer is about 70 to 90 nm. The improved performance may include low dynamic power, low leakage current, and/or high transistor density.
Among these structures, UTBOX (UTBOX standing for "Ultra-Thin Buried OXide") structures, having an ultrathin buried oxide layer, show great promise because the extreme thinness of this electrically insulating layer makes it possible to apply a voltage to the back side of the structure (i.e., to the side opposite the thin silicon layer) and therefore to precisely control the operation of the device.
The term "ultrathin" is understood to mean having a thickness of 50 nm or less.
The fabrication processes of structures having a buried oxide layer with a thickness of between 25 and 50 nm are, at the present time, quite well characterized and it is possible to produce such structures with a defectivity level that is compatible with subsequent component fabrication.
However, UTBOX structures with a buried oxide layer having a thickness of 25 nm or less, and particularly of 15 nm or less, can currently only be fabricated with a defectivity level that is not easily compatible with the requirements of component manufacturers.
More precisely, this defectivity is due to a bubbling or blistering effect that is observed at the bonding interface located between the thin silicon layer and the mechanical support, in the case of an SOI substrate fabricated using the SMART CUT® process.
FIG. 1 shows the variation in the defectivity as a function of the thickness of the BOX layer expressed in nanometers (nm).
The defectivity shown in this graph is the number of bubbles counted on the surface of an SOI structure immediately after the thin silicon layer has been transferred.
In the case of structures in which the BOX layer has a thickness below 15 nm (the hatched zone of the line in FIG. 1), the bubbling is so widespread that it may be impossible or impractical to count the bubbles.
FIGS. 2A to 2D illustrate the main steps of a first known process for fabricating such a structure employing the SMART CUT® process.
With reference to FIG. 2A, an oxide layer 2 is formed on the surface of a donor substrate 31 from which the thin silicon layer will be transferred.
A weak zone 32 is formed in the donor substrate 31, at a depth corresponding to the thickness of the thin layer 3 to be transferred, through the oxide layer 2, for example, by implantation of atomic species (represented by the arrows in FIG. 2B).
With reference to FIG. 2C, the donor substrate 31 (by way of the oxide layer 2) and the receiver substrate 1 are hydrophilically bonded by molecular adhesion.
This bonding step is followed by a bond-strengthening anneal intended to increase the bond strength.
Next, a supply of energy, for example, thermal energy, causes the donor substrate 31 to cleave in the weak zone 32.
In general, the bond-strengthening anneal is carried out at a low temperature (i.e., at a temperature between 200° C. and 550° C.) and the anneal allows the bonding interface to be strengthened and the cleaving of the donor substrate 31 to be initiated in the same step.
After the non-transferred part of the donor substrate 31 has been detached, a silicon-on-insulator structure (FIG. 2D) is obtained to which conventional finishing treatments (rapid thermal annealing (RTA), sacrificial oxidation, etc.) are applied, these treatments being intended to, inter alia, smooth the surface of the thin semiconductor layer 3 and repair implantation-related defects.
The one or more RTA treatments are typically carried out at a temperature above 900° C.
In the step of bonding the two substrates, water molecules present at the interface contribute to the bonding of the surfaces.
However, during the bond-strengthening anneal, water molecules diffuse through the oxide layer 2, and through a thin native-oxide layer on the surface of the receiver substrate 1, and react with the silicon of the semiconductor layer 3 and with the silicon of the receiver substrate 1. The reaction between the water molecules and the silicon may proceed as shown in the following oxidation reaction:2H2O+Si→SiO2+2H2
This reaction produces molecules of hydrogen gas, which are trapped in the buried oxide layer, the buried oxide layer thus acting as a hydrogen-gas reservoir.
However, in the case of an ultrathin oxide layer, the layer is not thick enough to store all of the hydrogen gas molecules.
The buried oxide layer therefore becomes saturated and can no longer absorb the molecules of hydrogen gas. The excess hydrogen accumulates at the bonding interface where it generates defects.
This is because, as soon as the temperature of the bonded structure exceeds about 300° C., the hydrogen gas subjects defects present at the bonding interface to pressure, forming bubbles.
This effect is described in the following articles: "A model of interface defect formation in silicon wafer bonding," S. Vincent et al., Applied Physics Letters, 94, 101914, (2009); and "Study of the formation, evolution, and dissolution of interfacial defects in silicon wafer bonding," S. Vincent et al., Journal of Applied Physics, 107, 093513, (2010).
By carrying out an anneal at a temperature of between 300° C. and 400° C., the generation of hydrogen gas is limited and thus the bubbling effect is prevented.
Thus, after the cleaving, a structure with a very low defectivity is obtained.
However, the bonding interface still needs to be adequately strengthened and the SOI substrate still needs to be finished without allowing bubbles to appear in the finishing steps.
At temperatures of 900° C. and above, hydrogen gas is soluble in silicon.
After the cleaving, the objective is therefore to increase the temperature to 900° C. (a temperature above which hydrogen outgases from the silicon) rapidly enough to set the structure and thus to prevent generation of defects at the bonding interface.
However, after a conventional RTA treatment micro-bubbles are observed to form in the structure and, although these bubbles are much smaller than those observed after the known process described with reference to FIGS. 2A to 2D, they make it impossible to use the structures for the intended applications.
This is a result of the fact that during the RTA the temperature was not increased rapidly enough to set the structure and prevent the bubbling effect.
It is therefore still necessary to develop a process that prevents bubbles from forming in the case of structures in which the BOX layers are 15 nm or less in thickness, and, in particular, 10 nm or less in thickness.
To prevent H2 from forming, document WO 2010/049496 describes a second process, the steps of which are represented in FIGS. 3A to 3E.
With reference to FIG. 3A, an oxide layer 21 is formed on the surface of the donor substrate 31.
A weak zone 32 is formed within the donor substrate 31 at a depth corresponding to the thickness of the thin layer 3 to be transferred, through the oxide layer 21, for example, by implantation of atomic species (represented by the arrows in FIG. 3B).
With reference to FIG. 3C, an oxide layer 22 is formed on the surface of the receiver substrate 1.
Next, molecular adhesion (oxide/oxide) bonding is used to bond the donor substrate 31 to the receiver substrate 1, the oxide layers 21, 22 being located at the interface and together forming the buried oxide layer 2 of the SOI substrate.
After this bonding step, the donor substrate 31 is cleaved at the weak zone 32.
This process achieves good results in terms of defectivity in so far as the H2-generating reaction is limited by the presence of the two facing buried oxide layers 21, 22 that form a barrier to water-molecule diffusion.
Specifically, these molecules cannot reach the oxide/silicon interface, the silicon oxidation reaction cannot take place, and the generation of H2 molecules is thereby prevented.
However, bonding substrates by way of their respective oxide layers 21, 22 have the drawback that the bonding interface is not completely closed. In other words, when the structure is observed with a transmission electron microscope after the finishing anneals (RTA at 1200° C. for 30 seconds), the interface between the two layers (represented by the dot-dash line 23 in FIG. 3E) may still be seen.
This incompletely closed interface may create electrical problems that could interfere with the operation of the electronic devices formed in or on the structure.

Process for fabricating a silicon-on-insulator structure


An input circuit includes an input signal transmission circuit configured to output a first transmission signal at a first output node in response to an input signal at an input node, and a Schmitt trigger inverter configured to output a second transmission signal at a second output node in response to the first transmission signal. The input signal transmission circuit includes a voltage drop element connected to the input node and configured to provide a voltage drop between the input node and a transistor having a gate to which a first supply voltage is applied. An input circuit may include an input signal transmission circuit configured to output a first transmission signal in response to an input signal and a feedback control signal, a Schmitt trigger inverter configured to output a second transmission signal in response to the first transmission signal and a second control signal, and an enable block configured to generate the feedback control signal and the second control signal in response to an enable signal.

Conventional electronic circuits may be driven using a single supply voltage having a ground voltage for reference. Even when two supply voltages are used, the supply voltages may typically be identical with each other except for their polarities, for example, ±5 volts and/or ±3.3 volts. Such supply voltages may also be employed in connection with circuits incorporating semiconductor devices.
For systems with very fast operating speeds and/or low current consumption, electronic circuits may use a greater variety of supply voltages and/or direct current (DC) bias voltages as compared to conventional circuits. An electronic circuit configured to operate using a range of supply voltages may include a tolerant input circuit that is designed to generate an input voltage having desired characteristics, such as voltage level, rise/fall time, noise level, and/or other characteristics, in response to a signal voltage applied to an input pad of the circuit.
FIG. 1 is a circuit diagram of a conventional input circuit 100 configured to operate using a range of supply voltages.
Referring to FIG. 1, the input circuit 100 includes an electrostatic discharge (ESD) protection circuit 110, an input signal transmission circuit 120, a Schmitt trigger inverter 130, and an inverter 140.
A first supply voltage VDD1 may have a lower voltage level than a voltage level of a second supply voltage VDD0 and a third supply voltage VDDP. Further, a ground voltage GND may be 0V (volts).
The ESD protection circuit 110 discharges electrostatic charge present in an input signal applied through an input pad 105. The ESD protection circuit 110 may discharge static charge through the first supply voltage VDD0 and/or the ground voltage GND. Thus, the ESD protection circuit 110 provides the input signal applied to the input pad 105 to the input node N0 with reduced electrostatic charge. The ESD protection circuit 110 may include five MOS transistors and a resistor R configured as shown in FIG. 1. Since the structure and operation of the ESD protection circuit 110 are well known, a more detailed description of the ESD protection circuit 110 may be omitted.
The Schmitt trigger inverter 130 generates the second transmission signal at the second output node N2 in response to the first transmission signal at the first output node N1.
The input signal transmission circuit 120 generates and outputs a first transmission signal at the first output node N1 using the input signal applied at the input node N0 through the ESD protection circuit 110, in response to a second transmission signal at the second output node N2 generated at an output of the Schmitt trigger inverter 130.
The inverter 140 inverts the phase of the second transmission signal at the second output node N2 and outputs it as an output signal OUT. The inverter 140 may be used as a buffer for providing the second transmission signal at the second output node N2 to, for example, a circuit that operates based on the second transmission signal.
Each of the second supply voltage VDD0 and the third supply voltage VDDP may have a voltage of 3.3V and the first supply voltage VDD1 may have a voltage of 1V.
When a voltage of zero volts is applied to the input pad 105, the voltage level of the input signal at the input node N0 output from the ESD protection circuit 110 is also zero volts. Also, an NMOS transistor M1 having a gate to which the second supply voltage VDDP of 3.3V is applied is turned on. Consequently, the voltage level of the first transmission signal at the first output node N1 will be zero volts. The Schmitt trigger inverter 130, whose operation is controlled by the voltage of the input signal at the input node N0, may cause the second transmission signal at the second output node N2 to have a voltage level of 3.3V in response to the first transmission signal at the first output node N1 having a voltage level of zero volts. An NMOS transistor M5, which has a gate connected to the second output node N2 having a voltage level of 3.3V, is turned on, and an NMOS transistor M4 having a gate to which the first supply voltage VDD0 of 3.3V is applied is also turned on. Accordingly, since the voltage applied to the gate of a PMOS transistor M2 is zero volts, the PMOS transistor M2 is also turned on.
The NMOS transistor M1 and the PMOS transistor M2, which may form a transmission gate, may be driven through the procedures described above. When a voltage of zero volts is applied at the input node N0, a PMOS transistor M3, which has a first current terminal connected to the input node N0 and a gate to which the first supply voltage VDD1 with a voltage level of 1V is applied, remains off.
When the voltage level at the input node N0 is gradually increased to about 1.6V, the voltage between the gate and the source of the PMOS transistor M3 is −0.6V. If the threshold voltage of the MOS transistor M3 is −0.6V, current will start to flow once the voltage at the input node N0 starts to go over about 1.6V.
The second transmission signal at the second output node N2 output from the Schmitt trigger inverter 130 will change from 3.3V to 0V when the first transmission signal at the first output node N1 reaches 1.9V. However, the MOS transistors M3, M4, and M5 will remain on while the voltage applied to the input pad is increased from 1.6V to 1.9V.
Accordingly, in this voltage range, undesired leakage current may flow from the PMOS transistor M3 to the ground voltage connected to a terminal of the NMOS transistor M5. This leakage current is illustrated in the graphs on the left-hand side of FIG. 6. As shown therein, in a conventional input circuit configured to operate using a range of supply voltages, when a voltage V(PAD) of the input pad 105 is increased, a leakage current I(PAD) may flow from the input pad 105 just before and/or just after the transition of the voltage V(n2) of the second transmission signal at the second output node N2 from a high level to a low level. As the operating voltage of a system using the circuit is lowered, the difference between the voltage level of a signal input/output through the input pad and the operating voltage may increase, and the threshold voltage of MOS transistors employed in the circuit may be lowered. These changes may result in an increase in the amount of a leakage current in the circuit. Increased leakage currents may result in higher power consumption and/or shorter battery life.

Input circuits configured to operate using a range of supply voltages


A compact and light flow meter having a rapid response includes a main body having a groove portion opened in the upper portion and also having connecting portions for communicating the groove portion and the exterior at both ends of the groove portion; a detachable cover body sealing the opened upper portion of the groove portion having a rectangular sectional shape in which a measured fluid is flowed; and a circuit substrate coming in close contact with the external face of the cover body. A sensor hole opened to the measuring chamber is arranged in the cover body; and a flow sensor is arranged in the circuit substrate so as to be arranged within the sensor hole and set a detecting face to face the measuring chamber.

1. Field of the Invention
The present invention relates to a flow meter.
2. Background Art
In a chip mounter, etc. for sucking an IC chip in a vacuum and holding and conveying the IC chip, it is judged whether the IC chip is appropriately sucked and held by monitoring the existence of an air flow of a vacuum flow path. When a compact and light flow meter is mounted to the head of such a chip mounter requiring a high speed operation and the existence of the air flow is monitored, high speed responsibility is more important than the accuracy of a flow rate. In patent literatures 1 and 2, the high speed responsibility is improved by devising the structure of a flow sensor.
[Patent literature 1] JP-A-6-66612
[Patent literature 2] JP-A-2003-240618
However, a fluid has inertia even when any high speed sensor is used. Accordingly, the fluid is intended to be continuously flowed within the flow meter even when the flow path is interrupted. Otherwise, the fluid is intended to stay in the same place even when the flow path is opened. Therefore, a problem exists in that a change in the flow velocity of a measured fluid within the flow meter is delayed and delay is caused in detection.


A cell reselection method by a user equipment (UE) receiving an MBMS service in a serving cell of a mobile communication system. The UE receives control data of the serving cell, including configuration information necessary for accessing MBMS control channels (MCCHs) of neighbor cells and control information necessary for accessing an MBMS data transport channel (MTCH) of the serving cell, over an MCCH of the serving cell, and stores the received control data, while the MBMS service is provided in the serving cell. If cell reselection to a target cell, which is one of the neighbor cells is determined, the UE moves to the target cell by utilizing configuration information stored for the target cell.

1. Field of the Invention
The present invention relates generally to mobility support in a mobile communication system, and in particular, to a method of cell selection in a user equipment (UE) supporting Multimedia Broadcast/Multicast Service (MBMS).
2. Description of the Related Art
Currently, as a result of the development of communication technology, services provided in a Code Division Multiple Access (CDMA) mobile communication system are developing into Multicasting/Multimedia Communication services for transmitting the existing voice service data and additional large amounts of data such as packet data and circuit data.
In a Universal Mobile Telecommunication Service (UMTS) system, which is a 3rd generation (3G) mobile communication system employing Wideband Code Division Multiple Access (WCDMA) based on Global System for Mobile communications (GSM) and General Packet Radio Services (GPRS), Broadcast/Multicast Service in which the same data stream is provided from one data source to a plurality of user equipments (UEs) is supported in order to support the Multicasting/Multimedia Communication. The Broadcast/Multicast Service can be classified into Cell Broadcast Service (CBS), which is a message-oriented service, and Multimedia Broadcast/Multicast Service (MBMS service) for supporting multimedia data including real-time images and voice, still images, and text.
FIG. 1 is a diagram schematically illustrating a network configuration for providing an MBMS service in a mobile communication system. Referring to FIG. 1, a multicast/broadcast-service center (MB-SC) 110 provides an MBMS stream, and the MS-SC 110 schedules an MBMS service stream and sends the scheduled MBMS service stream to a transit network (NW) 120. The transit network 120 is a network existing between the MB-SC 110 and a serving GPRS support node (SGSN) 130, which sends the MBMS service stream provided from the MB-SC 110 to the SGSN 130. The transit network 120 is comprised of a gateway GPRS support node (GGSN) and an external network.
The SGSN 130 receiving an MBMS service stream via the transit network 120 controls an MBMS service for the subscribers, i.e., UEs 161, 162, 163, 171, and 172, requesting the MBMS service. For example, the SGSN 130 manages MBMS service accounting data for each of the subscribers, and selectively transmits MBMS service data to an associated radio network controller (RNC) 140. In addition, the SGSN 130 generates and manages a service context for the MBMS service and sends a stream for the MBMS service to the RNC 140.
The RNC 140 transmits the MBMS service stream to Node Bs 160 and 170 controlling the cells where the UEs 161, 162, 163, 171, and 172 requesting an MBMS service are located, among the Node Bs managed by the RNC 140 itself The RNC 140 and the Node Bs 160 and 170 constitute a UMTS terrestrial radio access network (UTRAN).
A cell 1, which belongs to the Node B 160 that is requesting a particular MBMS service, includes the UE1 161, the UE2 162, and the UE3 163, and a cell 2, which belongs to the Node B 170, includes the UE4 171 and the UE5 172. Herein, the term "cell" has a meaning similar to that of the term "Node B." The RNC 140 controls radio channels set up between the Node Bs 160 and 170 and the UEs 161, 162, 163, 171, and 172 in order to provide the MBMS service. As illustrated in FIG. 1, one radio channel is established between one Node B and UEs belonging to the Node B in order to provide an MBMS service.
In such an MBMS service system, when a UE receiving an MBMS service moves from one cell, i.e., a serving cell, to another cell, i.e., a target cell, the control of the UE must be handed over from the serving cell to the target cell by a cell reselection procedure. More specifically, the UE must acquire information on the target cell in order to continuously use the same MBMS service as that used in the serving cell. The target cell information includes control information for accessing a transport channel for carrying a data stream for an MBMS service in the target cell. As a result, during cell reselection, delay occurs when acquiring information on the target cell by the UE. Further, this delay prevents the user from seamlessly receiving the MBMS service while moving between cells. Accordingly, there is a demand for cell reselection technology that enables a UE to rapidly acquire information on a target cell while moving between cells, thereby seamlessly providing an MBMS service.

Method for cell reselection in an MBMS mobile communication system


A method for impregnating porous monolith supports with catalytically active materials is disclosed. The impregnation is carried out at a temperature which substantially reduces chemisorption rates such that reactions between the monolith substrate and catalytically active materials in the catalyst solution are minimized. The process can be completed in a practical time that allows for unit selectivity of the weight ratio of catalytically active materials in the substrate to the weight ratio of catalytically active materials in the catalyst solution.

The present invention relates to a method for preparing catalysts, and in particular to a method for impregnating monolithic catalyst supports, such as honeycomb structures, which substantially reduces preferential loading and achieves unit selectivity.
Catalyst impregnation is one of the most crucial steps for preparing industrial catalysts, such as those useful in hydrotreating applications. Generally, high surface area oxide substrates or supports are loaded with one or more catalytically active materials, such as noble and/or base metals. Two widely-known impregnation techniques include pore volume impregnation (PVI), and excess solution impregnation (ESI).
PVI which is used with pellets or beads catalyst supports, involves the use of a catalyst solution of a volume equivalent to or slightly less than the total pore volume of the supports. The liquid solution penetrates and fills up the support pore volume, delivering a specific amount of metal into the pores. Following imbibation (i.e., complete filling of the pore volume with the available liquid solution) the pellet supports are dried to remove excess water, and achieve the desired metal concentration. Advantages of the PVI technique include easy determination of the catalyst volume solution required, and unit selectivities (i.e., the weight ratios of the catalytically active materials in the solution are equal to the weight ratios of the catalytically active materials in the substrate).
However, pore volume impregnation is not readily applicable to monolithic catalyst supports due to the complexity and rigidity of their shape. Simply absorbing the volume of solution equivalent to the volume of the support, generally results in very poorly distributed catalysts. Therefore, honeycomb supports are usually impregnated with a catalyst solution having a volume that exceeds the support's pore volume. This technique is known as excess solution impregnation or ESI. The honeycomb support is fully submerged in the catalyst solution over an extended period of time. The solution penetrates the pores of the support due to capillary pressure and fills up the available pore volume.
A disadvantage of the ESI technique, is the interaction that occurs between the surface of the support and the catalyst solution because the various catalytically active materials have different chemisorption rates or react at different rates and to different equilibrium levels. This leads to "preferential loading" of some metals over others, and unit selectivities cannot be achieved.
It is extremely important for any large scale impregnation process to have selectivities as close to unity as possible, in order to be commercially viable. If the selectivities are far from unity, the relative metal concentrations in the solution will differ before and after impregnation and the composition of the solution will change over time. This renders the catalyst solution unusable after a period leading to material loss and excessive cost. Further, to achieve the desired catalyst composition, the impregnation solution must be optimized independently for each process, which results in further costs and inefficient processing.
There is, thus, a need for an improved method to impregnate porous monolithic supports to reduce preferential loading and achieve unit selectivities, and provide a process that is cost-effective and efficient.


A photographic camera having a halfway film rewind mode in which a cartridge having film with part of the frames exposed and part of the frames unexposed is rewound into the film cartridge. The camera also allows the user to set a mode in which data relating to the cartridge can be entered into the memory of the camera. The memory of the camera stores the user input cartridge data together with data representative of the member of unexposed film frames remaining on the film in the cartridge.

1. Field of the Invention
This invention relates to a photographic camera for use with a new type of standardized film cassette, which is different from the "DX-code system" film cartridge, that has been recently standardized.
2. Description of Related Art
A new type of film cartridge, which is loaded in a photographic camera of the invention, has been standardized for an advanced photographic system (APS). For the purpose of providing an understanding of the new type of film cartridge, reference is made to FIGS. 12A and 12B. Generally, the film cartridge includes a generally cylindrical light-tight cartridge shell 30 in which a roll of a fresh filmstrip 34 wound on a spool 32 rotatable inside the film cartridge 30 is loaded at the manufacturer. The cartridge shell 30 has a light block door 36 which is rotated closed to prevent ambient light from entering the interior of the cartridge through a film egress/ingress slot as film is taken out of the camera or until it is placed in the camera, and which is then rotated open to allow the filmstrip 34 to move into and out of the cartridge interior through the film egress/ingress slot.
This new type of film cartridge 30 has what is called a visual exposure index (VEI). That is, the film cartridge 30 at one of its ends is provided with a data disk 38 rotating together with the spool 32. The data disk 38 has optically readable bar codes of various information concerning the filmstrip 34, such as the type of film, the speed or sensitivity of film and the number of exposures, printed on its outer surface. The film cartridge 30 at another one of its ends is formed with four cut-outs 40, 42, 44 and 46 differently shaped in the forms of circle, square, cross and semicircle, respectively. A tongue-shaped white indicator (not shown) rotatable together with the spool 32 is located on a side of the cartridge interior and is viewed through one of the respective cut-outs 40, 42, 44 and 46 from the exterior of the film cartridge 30 according to angular positions. Specifically, the white indicator viewed through the circular cut-out 40 provides an indication that the filmstrip 34 is fresh. The white indicator viewed through the square cut-out 42 provides an indication that the filmstrip 34 has been photo-processed. The white indicator viewed through the cross cut-out 44 provides an indication that the filmstrip 34 has been fully exposed but is not photo-processed. The white indicator viewed through the semicircular cut-out 46 provides an indication that the filmstrip 34 is partly exposed and partly unexposed.
The filmstrip 34 has a silver salt photosensitive layer coated on one surface 34.sub.F of the film base and a magnetic recording layer on another surface 34.sub.R of the film base. The filmstrip 34 also has magnetic tracks 52 and 54 coated along and on opposite sides of each film frame 48 on the one surface 34.sub.F of the film base and perforations 50 formed to define opposite ends of each film frame 48. Information on exposure, such as the type of exposure light, the focal length, etc., and the title of a picture are magnetically recordable on and readable from the magnetic tracks 52 and 54 at the photographer's request.
The film cartridge 34 has an optically readable bar code 56 indicating its own identification number (ID number) printed on the outer surface thereof.
When a camera of the APS type is loaded with the film cartridge 34, the camera automatically reads the optically readable data, such as the bar codes, on the data disk 38 by means of an optical reader incorporated therein. While the camera automatically opens the light block door 36, it also automatically detects an angular position of the white indicator to automatically advance the filmstrip 34 out of the film cartridge 34 until a first unexposed film frame is placed in the camera exposure frame if the filmstrip 34 is fresh or partly exposed. On the other hand, if the filmstrip 34 is fully exposed or has been photo-processed, the camera judges from the angular position that the filmstrip 34 is unavailable, and holds the filmstrip 34 in the interior of the film cartridge 30.
When the filmstrip 34 is fully exposed, while the camera rewinds the exposed filmstrip 34 into the interior of the film cartridge 30, it aligns the white indicator with the cross cut-out 44 and locks it, and closes the light lock door 36. When unloading the film cartridge 30 from the camera, the film cartridge 30 shows the white indicator through the cross cut-out 44, indicating to the photographer or persons handling the film cartridge 30 that the filmstrip 34 in the film cartridge 30 is fully exposed. When the filmstrip 34 is intentionally rewound into the interior of the film cartridge 30 after it is partly exposed, the camera aligns the white indicator with the semicircular cut-out 46 and locks it, and closes the light lock door 36. When unloading the film cartridge 30 from the camera, the film cartridge 30 shows the white indicator through the semicircular cut-out 46, indicating to the photographer or persons handling the film cartridge 30 that the filmstrip 34 in the film cartridge 30 is partly exposed.
As described above, the new type of film cartridge has various novel features, such as a magnetic information recording and reproducing feature, in addition to features of the conventional film cartridge. Further, the new type of film cartridge enables photographers not only to visibly recognize the exposed state of the filmstrip 34 preserved therein even if the filmstrip 34 is exposed, fully or partly, or has been photo-processed, but also to use different types of films by turn with a single camera of the APS type, which is hardly realizable by the conventional DX-code system film cartridges.
In cases where the new type of film cartridge is used together with a conventional camera, when the film cartridge with a partly unexposed filmstrip 34 contained therein is reloaded in the conventional camera, it is impossible to read the magnetically recorded information on the magnetic tracks of the filmstrip 34, and the features accompanying the new type of film cartridge, such as automatic positioning of a first unexposed film frame of the filmstrip 34, are not applicable.
In order for a camera for use with the new type of film cartridge to read magnetically recorded information on the magnetic tracks, it is necessary to incorporate a highly sensitive and highly precise magnetic head which is generally large in size and needs its associated parts and elements including complicated circuits and operation switches. While it may be possible to enter an ID No. of a film cartridge into the camera without using such a magnetic head, entering an ID No. of a film cartridge whenever the film is intentionally rewound halfway imposes a somewhat troublesome operation on the photographer when rewinding a film halfway for the purpose of photo-processing.
While the film cartridge containing a film with film frames partly unexposed is visually recognized to be partly exposed and partly unexposed through the VEI, it is not known how many unexposed film frames the film in the cartridge has unless the film cartridge is loaded in the camera. Loading and unloading a film cartridge in a camera so often is undesirable in view of durability.

Photographic camera having a memory for storing film cartridge data together with data representing the number of unexposed frames on the film in the cartridge


A multilayered printed circuit board is produced by (a) forming a resin layer on an inner circuit substrate and abrading it to expose the circuit conductors, (b) contacting a copper foil having a layer of insulating adhesive composed of an epoxy resin, a carboxylic acid-containing acrylic or acrylonitrile-butadiene rubber, a curing agent and accelerator with the resin layer and exposed circuit conductors, (c) removing portions necessary for connection with the copper foil and insulating adhesive exposed to the holes by etching, (d) connecting the copper foil with circuits exposed to the holes and forming a surface circuit by processing the outer layer of the copper foil, and (e) repeating steps (a) to (d) to obtained a multilayered structure.

This invention relates to a resin composition and processes for producing a multilayer printed circuit board using said resin composition.
Usual multilayer printed circuit boards are produced by piling a prepreg, which is obtained by impregnating glass cloth with an epoxy resin and semi-curing the resin, together with a copper foil on an insulating substrate having interlayer circuits thereon, laminating them into an integrated structure by pressing with heating, drilling holes for inter-laminer connection, conducting electroless plating on the inner walls of through-holes and copper foil surface, if necessary, conducting electrolytic plating so as to make circuit conductors in necessary thickness, removing selectively unnecessary copper, and forming circuit conductors.
With recent tendency of miniaturization, light weight and multi-functionality of electronic devices, an increase of the degree of integration of large scale integrated circuits (LSI) and miniaturization of chip parts proceed together with an increase of connecting pins and miniaturization of parts. Thus, in order to mount these parts, wiring in multilayer printed circuit boards becomes finer and finer. But the reduction of the width of wiring has naturally a limit technically. Today, the minimum wiring width for mass production is about 100 .mu.m. Further, the size of through-holes, which occupies a considerably large area compared with the wiring width, becomes an obstacle for improving wiring density. These through-holes are drilled mechanically in general. Since it is difficult to make the diameter of a drill smaller from the viewpoint of maintaining mechanical strength, it is difficult to make the areas of through-holes smaller.
Recently, it is reported various processes for forming through-holes without using a drill. For example, there are reported, first, hole fabrication using a laser, second, a process for forming via holes selectively, and third, a process for selectively removing only an insulating material by etching.
According to the first process of using a laser, the diameter of through-holes can be lessened, but the laser per se is expensive, and it requires a step for removing molten glass, resins, etc. after hole-fabrication, and thus not efficient.
According to the second process of selective via hole formation, a multilayer printed circuit board is produced by forming holes previously in a prepreg or a thin adhesive sheet, laminating the prepreg or the like on a circuit substrate, electrically connecting inner walls of the holes to outer conductors using an electroconducting substance, conducting circuit processing, and repeating these steps for forming multilayers. But since the resin of prepreg or the adhesive of the adhesive sheet has fluidity, when holes having a small diameter are formed, the resin or the adhesive is forced to ooze into the interior of the holes at the time of lamination, resulting in making the hole diameter smaller.
According to the third process, the problem mentioned above can be solved. For example, as disclosed in Japanese Patent Examined Publication (JP-B) No. 42-24109, an insulating adhesive is attached to a metallic foil, followed by selective removal of a part of the metallic foil, wherein the removed portion can be corroded with a suitable corrosive. Thus, small holes which can not be formed by drilling can be fabricated. Further, it is not necessary to use an expensive special device such as a laser. But according to said JP-B, a thin film of polyester is used as an insulating material and concentrated sulfuric acid is used for corrosion. But, the polyester film is not used in printed circuit boards now. Thus, the use of polyester film is not practical.
The use of an alkali-soluble resin as an insulating material in place of the polyester is disclosed in Japanese Patent Unexamined Publication (JP-A) No. 5-259649. According to said JP-A, a multilayer printed circuit board is produced by forming an insulating layer on an inner layer circuit substrate using an uncured alkali-soluble resin, laminating a copper foil thereon, forming an etching resist except for positions of holes to be formed, removing the exposed copper foil not covered with the resist by etching using a chemical etching solution, further removing the exposed alkali-soluble resin by etching using an alkaline solution to form via holes, curing the alkali-soluble resin, and metallizing the inner portion by electroless plating or the like for electrical connection. But according to the process of said JP-A, there are the following problems:
(i) Since the alkali-soluble resin is used, it is not possible to use an alkaline solution in other steps. PA1 (ii) When the alkali-soluble resin is cured, the resin is fluidized to make the hole diameter smaller. PA1 (a) an epoxy resin having a number average molecular weight of 1200 or less in an amount of 30 to 100 parts by weight, PA1 (b) a carboxylic acid-containing acrylic rubber or a carboxylic acid-containing acrylonitrile-butadiene rubber in an amount of 30 to 70 parts by weight, PA1 (c) a curing agent for the epoxy resin, and PA1 (d) a curing accelerator. PA1 (a) forming a resin layer for filling hollow portions between circuit conductors on the whole surface of an inner circuit substrate, followed by abrasion of the resin layer so as to expose the circuit conductors, PA1 (b) piling a copper foil having a layer of insulating adhesive on one side so as to contact the insulating adhesive with the resin layer and the exposed circuit conductors, followed by lamination to form an integrated structure with heating under pressure, PA1 (c) removing portions necessary for connection with the copper foil by etching, and removing the insulating adhesive exposed to holes by chemical etching, PA1 (d) connecting the copper foil with circuits exposed to the holes and forming a surface circuit by processing an outer layer of the copper foil, and PA1 (e) repeating the steps (a) to (d) depending on the number of circuit layers necessitated. PA1 (a) printing or coating a filling material for hollow portions and having fluidity at B-stage on hollow portions of a circuit substrate, PA1 (b) drying the filling material, followed by curing to B-stage, PA1 (c) piling a copper foil having a layer of insulating adhesive made from the above-mentioned resin composition which is capable of forming via holes by chemical etching on one side so as to contact the insulating adhesive with the filling material coated surface, followed by lamination to form an integrated structure, PA1 (d) removing portions necessary for connection with the copper foil by etching, and removing the insulating adhesive exposed to holes by chemical etching, PA1 (e) connecting the copper foil with circuits exposed to the holes and forming a surface circuit by processing an outer layer of the copper foil, and PA1 (f) repeating the steps (a) to (e) depending on the number of circuit layers necessitated. PA1 (a) forming via holes in a copper foil having a layer of insulating adhesive made from the above-mentioned resin composition which is capable of forming holes by chemical etching, PA1 (b) piling the copper foil having a layer of insulating adhesive with via holes on one side of an inner circuit board so as to contact the insulating adhesive with circuit conductors on the inner layer circuit board, followed by lamination to form an integrated structure with heating under pressure, PA1 (c) removing the insulating adhesive oozed into the holes by chemical etching, PA1 (d) curing with heating the insulating adhesive to form via holes or a cavity, PA1 (e) forming conductive pathes in via holes or a cavity using an electroconductive paint or metallic deposition by plating, and PA1 (f) repeating the steps (a) to (e) depending on the number of circuit layers necessitated. PA1 (a) forming via holes in a sheet of insulating adhesive made from the above-mentioned resin composition which is capable of forming holes by chemical etching, PA1 (b) piling the sheet with holes on one side of an inner circuit board so as to contact the insulating adhesive with circuit conductors on the inner layer circuit board, and piling a copper foil on the insulating adhesive with holes, followed by lamination to form an integrated structure with heating under pressure, PA1 (c) removing copper from portions in which via holes are to be made in the insulating adhesive, and removing the insulating adhesive oozed into the holes by chemical etching, PA1 (d) curing with heating the insulating adhesive to form via holes or a cavity, PA1 (e) forming conductive pathes in via holes or a cavity using an electroconductive paint or metallic deposition by plating, and PA1 (f) repeating the steps (a) to (e) depending on the number of circuit layers necessitated.

Multilayer printed circuit board with epoxy resin and carboxylated rubber as adhesive


The present invention provides an array substrate, which includes a plurality of pixel units, each pixel unit includes a thin film transistor, a pixel electrode, a common electrode and a passivation layer, the thin film transistor includes an active layer, a gate electrode, a source electrode and a drain electrode, the drain electrode and the pixel electrode are connected, the passivation layer is disposed on the active layer, the source electrode, the drain electrode and the pixel electrode, the common electrode is disposed above the pixel electrode with the passivation layer therebetween, a test electrode is disposed on the active layer and under the passivation layer, the test electrode is electrically insulated from the gate electrode, the source electrode and the drain electrode. Correspondingly, a method for fabricating and a method for testing the array substrate, and a display device including the array substrate are provided.

With the development of a display manufacturing technology, a liquid crystal display technology develops rapidly, it has replaced a traditional cathode-ray-tube display and become the mainstream of future flat panel displays. In the field of the liquid crystal display technology, Thin Film Transistor Liquid Crystal Displays (TFT-LCDs) are widely used in televisions, computers, mobile phones and other areas due to their advantages of large size, high integration, powerful functions, flexible manufacturing process and low cost. Wherein, a TFT-LCD of an Advanced Super Dimension Switch (ADS, also referred to as ADSDS) mode forms a multiple dimension electric field by an electric field generated by slit electrode edges in the same plane and an electrical field generated between slit electrode layer and plate electrode layer, in order to enable the liquid crystal molecules with all orientations between the slit electrodes in liquid crystal box and right above the electrodes to rotate, and thus the operation efficiency of the liquid crystal is improved and light transmission efficiency is increased, thereby increasing the picture quality of TFT-LCD products. Therefore, the TFT-LCD of an Advanced Super Dimension Switch mode is widely used in the liquid crystal display area.
In a TFT-LCD, a display panel is the main component thereof, and is generally formed by aligning and assembling a manufactured array substrate and a color filter substrate and then perfusing liquid crystal molecules. In an ADS mode display panel, to detect whether the TFT channel can be driven normally, a test on the TFT channel characteristics locating on the array substrate is required (generally, including tests on TFT switch current, threshold voltage and electron mobility. The specific test method is: connecting a probe of the test apparatus to a pixel electrode (the pixel electrode is located at the uppermost layer of the array substrate, and therefore the probe can be directly connected to the pixel electrode), as a drain electrode and the pixel electrode are connected, the probe of the test apparatus can be connected to the drain electrode through the pixel electrode; then inputting corresponding signals into gate lines and data lines through the probe of the test apparatus, respectively; and determining whether the TFT channel can be normally driven according to the signal obtained from the drain electrode by the test apparatus.
With the development of a TFT technology, a wide viewing angle panel capable of being visible in the sunshine, i.e., High aperture ADS (H-ADS) mode display panel, comes forth in this area. In an array substrate of an H-ADS mode display panel, as a pixel electrode is located in the middle part of the array substrate (as shown in FIG. 1, a pixel electrode 8 is located between a gate insulating layer 5 and a passivation layer 9), such that the probe of the test apparatus cannot be connected to the pixel electrode or the drain electrode (the drain electrode is also located in the middle part of the array substrate, as shown in FIG. 1, a drain electrode 7b is located between an active layer 6 and the passivation layer 9), and therefore, an existing test apparatus cannot be used to perform TFT channel characteristics test on the H-ADS mode display panel.

Array substrate, method for fabricating and testing array substrate, and display device


An adjustable web cutter which allows web samples to be cut in various lengths, width and thickness while employing a disposable cutter blade.

1. Field of the Invention
This invention relates to adjustable web cutters. Such structures of this type, generally, allow web samples to be cut in various lengths, widths and thicknesses while employing a disposable cutter blade.
2. Description of the Related Art
It is known, in a mat cutting apparatus, to employ a single edge razor blade which is mounted to cut on an angle. Exemplary of such prior art is U.S. Pat. No. 3,973,459 ('459) to C. P. Stowe, entitled "Mat Cutting Apparatus". The '459 reference employs a blade that moves while cutting a stationary piece of mat, but the blade cannot be inverted when dulled. Also, the blade cannot be set in more than one position.
It is also known, in paper cutting systems, to employ a portable cutter which uses round slitter blades. Exemplary of such prior art is the "cutoff" system, manufactured by TAPIO Technologies of Finland. While the TAPIO system uses chain tensioning that requires lubrication, it also employs round slitter blades which cut with a scissor effect. However, the slitter blades must be sharpened at a machine shop, which adds to the operating expense. While the TAPIO system is portable, it must be bolted to a work top. Also, the system uses a feed plate which must also be fixed to the work top. Finally, while the TAPIO system employs a fixed hand wheel to wind the paper, it can only cut fixed-width rolls.
Consequently, a more desirable web cutter would be one which (1) tightly winds the web sample that is cut, (2) utilizes standard, replaceable blades, which are readily accessible at any hardware store, (3) the blades are protected by a safety shield, (4) the cutter is adjustable for several core widths, (5) the cutter will support rolls with variable diameters, allowing numerous cross-directional (CD) samples to be wound on one core, (6) the cutter is free-standing, thereby allowing various support surfaces to be utilized, (7) the height of the cutter is adjustable, (8) the cutter allows for sample winding with the felt or wire-side of the web facing out, (9) the cutter employs an interchangeable handle to allow for both left-handed and right-handed operation, (10) the cutter is portable and easily assembled and (11) the cutter requires no lubrication.
It is apparent from the above that there exists a need in the art for a web cutter which is lightweight through simplicity of parts and uniqueness of structure, and which at least equals the cutting characteristics of the known cutters, but which at the same time avoids all of the previously mentioned downfalls of the known cutters.
It is a purpose of this invention to fulfill this and other needs in the art in a manner more apparent to the skilled artisan once given the following disclosure.


A probe apparatus providing an electrical connection between a device under test and a test apparatus body, comprising a device-side terminal unit including a flexible sheet and device-side connection terminals passing through the sheet and connected to the device under test; an intermediate substrate provided on the test apparatus body side of the device-side terminal unit and including device-side intermediate electrodes electrically connected to the device-side connection terminals and tester-side intermediate electrodes electrically connected to the test apparatus body; a tester-side substrate that is provided on the test apparatus body side of the intermediate substrate and includes, on the intermediate substrate side thereof, tester-side electrodes electrically connected to the test apparatus body; and a contact section provided between the intermediate substrate and the tester-side substrate and including first pins connected to the tester-side intermediate electrodes and second pins connected to the tester-side electrodes.

1. Technical Field
The present invention relates to a probe apparatus and a test apparatus.
2. Related Art
A conventional test apparatus is known that transports and secures one wafer at a time, electrically connects to a plurality of semiconductor integrated circuits formed on the wafer, and performs testing, such as shown in Patent Document 1. Patent Document 1: Japanese Patent Application Publication No. 2010-204096
However, the number of semiconductor integrated circuits formed on a single wafer and the number and density of electrodes that are to be electrically connected have been increasing. As a result, the component mounting density in probe apparatuses that are electrically connected between a test apparatus body and a wafer has increased, and this makes it difficult to realize a spacious design when arranging the electronic circuit elements.


A boiler gas flow distribution fin includes an elongated flow distribution fin protruding from a back wall of a flow distribution channel into a hot gas flow path from a boiler combustion chamber. The flow distribution fin can include a leading segment with a leading ridge, a medial segment with a medial ridge, and a trailing segment with a trailing ridge. A gap between the fin ridges and a set of convective fins in an adjacent flue passageway segment can vary from a larger gap at the leading ridge to a smaller gap at the trailing ridge, transitioning along the medial ridge. The flow distribution fin can aid in directing a hot gas flow from a combustion chamber into the flue passageway segment, resulting in a substantially balanced mass flow rate through each of a series of flue passageway sections.

Domestic boilers are used to generate hot water, which may be used to flow through a circuit to provide heating to a facility, such as a home or office building. The hot water also may be stored in a hot water tank and used for hot water needs, such as running a dishwasher, shower and other domestic hot water uses.
Fuel-burning boilers commonly include a fuel-burning combustion device, or burner, to provide a source of heat to heat liquid water or steam. The burner may supply a hot gas mixture, which can be routed through a series of flue passageways. A boiler may further include two or more flue sections designed to transfer heat by way of convection from the hot gas mixture to liquid water or steam. The flue section typically can include one or more convective flue passageways through which the hot gas mixture can flow. In some boilers, the hot gas mixture can be routed through a sequence of flue passageways, each of which can be comprised of a series of flue passageway segments in a series of flue sections.
Additionally, the hot gas mixture can be routed in different directions through the flue passageway—for example, the hot gas mixture can be routed in one direction through a first flue passageway, and then in the opposite direction through a second flue passageway that runs parallel to the first, and so on, through a sequence of multiple flue passageways in the flue sections.
Generally, the flue sections of a boiler also include water passageways that are separated from the flue passageways by a solid wall, for example, produced from cast iron. The water passageway in the individual flue sections can be interconnected in order to permit liquid water or steam in the water passageways to flow between the flue sections, as well.
Furthermore, the flue passageways can include a series of convective fins attached to or formed from the solid wall and configured to extend into the flow stream of the hot gas mixture in order to transfer heat from the hot gases to the fins, and subsequently to the liquid water or steam on the opposite side of the wall in the water passageways.
Thus, hot gases from the burner can be routed to the first flue passageway segment of the boiler, where the hot gases pass over a set of convective fins around the perimeter of the flue passageway segment in order to transfer heat to the liquid water or steam in the water passageways. Thus, the flue passageway flow path is effectively divided into discrete sections by the convective fins.
In some boiler configurations, the combustion gases can travel along a combustion chamber wall and into one or more gas flow distribution channels, from which the combustion gases may the first flue passageway segment at a right angle to the flow direction of the flow distribution channel. In some boiler configurations, it has been shown that a disproportionately high portion of the hot gas mass flow travels to a far end of the gas flow distribution channel or channels, and into a last section of the flue passageway between an uppermost pair of convective fins and a far wall of the flue passageway.
Accordingly, it is desirable to provide a method and apparatus that more evenly distributes the hot gas flow through all of the flue passageway sections.

Boiler gas flow distribution fin apparatus and method


A structure and method of forming a semiconductor material wafer comprising forming an ingot of semiconductor material. A first dielectric layer is formed on the surface of the ingot, and the surface of the first dielectric layer is larger than the surface of the ingot. A second dielectric layer is formed on the surface of the first dielectric layer, and the surface of the second dielectric layer is larger than the surface of the first dielectric layer. The semiconductor wafer structure comprises a slip core formed of a semiconductor material, a first annular portion, and a second annular portion. The slip core had a first outer peripheral. The first annular portion is adjacent to the first outer peripheral, and is formed of a first dielectric material. The first annular portion has a second outer peripheral being larger than the first outer peripheral. The second annular portion is adjacent to the second outer peripheral, and is formed of a second dielectric material. The second annular portion has a third outer peripheral being larger than the second outer peripheral. The present invention provides the first annular portion and the second annular portion to protect the wafer, thereby preventing wafer edge cracks.

1. Field of the Invention
The present invention relates to a structure and method of forming a semiconductor material wafer and, more particularly, to a structure and method of forming the wafer with sacrificial layers.
2. Description of the Prior Art
The Czochralski technique for growing single crystals is named CZ seed-pulling (1918). Silicon wafers are generally taken from crystals grown by Teal and Buehler. The CZ dislocation-free single crystal was developed by Dash.
The CZ method comprises the following steps: (1) poly charging; (2) meltdown; (3) necking and crown; (4) body growth; and (5) tail growth.
(1) poly charging and (2) meltdown—a new crucible is charged in the Graphite suspector, and the chuck polycrystalline silicon ("polysilicon") and dopant are charged to the crucible. In order to reduce the quartz crack caused by polysilicon and the suspector, the large diameter of chuck polysilicon is charged in the bottom and side of the suspector, and the dopant is charged in the central. The furnace is then closed, vacuumed, the leaking rate is checked, and heating is performed at a temperature higher than 1420° C. to completely melt and maintain for a time in order to uniformly mix the melted solution. If the chuck and granular material are used together, the granular material is slowly added from the side of the furnace before the chuck is completely melted, in order to achieve the desired total amount, and maintained for a time so as to evaporate the gas, in order to achieve the stable status of the solution temperature, the suspector temperature, and the thermal field.
(3) necking and crown through (5) tail growth—the temperature of the melted solution surface is fine-tuned by dipping the seed crystal into the solution, thereby monitoring the melting status. A monocrystalline seed with a specific shape and crystal orientation (1.7×1.7×2.5 cm )is dipped into the solution about 0.3 cm. If this dipped seed crystal is easily melted, the output power of the heater needs to be reduced. If the dendritic polysilicon is grown outwardly from the dipped seed crystal, the output power needs to be increased. Under proper temperature, the seed crystal is rotated and pulled. The dipped seed crystal is pulled to form a new monocrystalline seed with a diameter of 0.5˜0.7 cm. It is so-called "the neck". The growth rate of the neck diameter and the internal quality are controlled by skilled operators. The purpose of growing the necking is to eliminate plastic deformation defects 5 caused by machining, for example, dislocation and vacancy, or defects caused by rapidly heating the seed crystal contacted with the solution.
The grown ingot is sawed into a plurality of slip wafers, thereby forming the required structures on the wafers. Since each wafer is not easy to form, cracks are inspected by instrumentation when the wafer edge or even the main body generates a crack caused by the external factors during the subsequence processing. This usually wastes resources and increases costs.

Structure and method of forming a semiconductor material wafer

Grace Semiconductor Manufacturing Corporation


A dual spin valve (DSV) magnetoresistive (MR) sensor has a free magnetic layer disposed between first and second pinned magnetic layers. The first pinned layer has two magnetic sublayers separated from each other by an antiparallel spacer. The first magnetic sublayer closer to the free layer has a magnetic moment which is smaller than the magnetic moment of the second magnetic sublayer. The net moment of the magnetic sublayers is chosen to be equal to the magnetic moment of the second pinned layer thus creating a flux closure and substantially minimizing the effect of the demagnetizing forces. By creating a flux closure and current induced magnetic fields, the first and second pinned layers' magnetization are fixed. This is in contrast with conventional dual spin valve sensors using two antiferromagnetic layers to pin the magnetization of the pinned layers.

1. Technical Field
This invention relates in general to a direct access storage device (DASD) of the type utilizing dual spin valve magnetoresistive sensors for reading signals recorded in a magnetic medium and, more particularly, it relates to a DASD having a self-biased dual spin valve sensor.
2. Description of the Background Art
Computers often include auxiliary memory storage devices having media on which data can be written and from which data can be read for later use. A direct access storage device (disk drive) incorporating rotating magnetic disks are commonly used for storing data in magnetic form on the disk surfaces. Data is recorded on concentric, radially spaced information tracks on the disk surfaces. Magnetic heads including read sensors are then used to read data from the tracks on the disk surfaces.
In high capacity disk drives, magnetoresistive read sensors, commonly referred to as MR heads, are the prevailing read sensors because of their capability to read data from a surface of a disk at greater linear densities than thin film inductive heads. An MR sensor detects a magnetic field through the change in the resistance of its MR sensing layer (also referred to as an "MR element") as a function of the strength and direction of the magnetic flux being sensed by the MR layer.
One type of MR sensor currently under development is giant magnetoresistive (GMR) sensors manifesting the GMR effect. In the GMR sensors, the resistance of the MR sensing layer varies as a function of the spin-dependent transmission of the conduction electrons between the magnetic layers separated by a non-magnetic layer (spacer) and the accompanying spin-dependent scattering which takes place at the interface of the magnetic and non-magnetic layers and within the magnetic layers.
GMR sensors using only two layers of ferromagnetic material (e.g., NiFe or Co or NiFe/Co) separated by a layer of GMR promoting non-magnetic metallic material (e.g., copper) are generally referred to as spin valve (SV) sensors. In an SV sensor, one of the ferromagnetic layers, referred to as the pinned layer, has its magnetization typically pinned by exchange coupling with an antiferromagnetic (e.g., NiO or FeMn) layer. The pinning field generated by the antiferromagnetic (AFM) layer is usually equal or greater than 200 Oersteds (Oe) so that the magnetization direction of the pinned layer remains fixed during the application of external fields (e.g., fields from bits recorded on the disk). The magnetization of the other layer, referred to as the free layer (free magnetic layer), however, is fixed and is free to rotate in response to the field from the disk.
FIG. 1 shows a prior art SV sensor 100 comprising end regions 104 and 106 separated by a central region 102. A free layer (free MR layer) 110 is separated from a pinned layer (pinned MR layer) 120 by a non-magnetic, electrically-conducting spacer layer 115. The magnetization of the pinned layer 120 is fixed through exchange coupling with an antiferromagnetic (AFM) layer 125. Free layer 110, spacer layer 115, pinned layer 120 and the AFM layer 125 are all formed in the central region 102. Hard bias layers 130 and 135 formed in the end regions 104 and 106, respectively, provide longitudinal bias for the MR free layer 110 and the pinned layer 120. Leads 140 and 145 formed over hard bias layers 130 and 135, respectively, provide electrical connections for the flow of the sensing current I.sub.s from a current source 160 to the MR sensor 100.
The SV effect, i.e., the net change in resistance, exhibited by a typical prior art SV sensor is about 3% to 4.5%. U.S. Pat. No. 5,206,590 entitled "Magnetoresistive Sensor Based On The Spin Valve Effect", granted to Dieny et al. on Apr. 27, 1993, discloses an MR sensor operating on the basis of the spin valve effect.
Referring to FIG. 2, there is shown another type of spin valve sensor commonly referred to as dual spin valve sensor 200, comprising end regions 204 and 206 separated by a central region 202. A free layer (free MR layer) 210 is separated from two outer pinned (pinned MR layer) layers 220 (PL1) and 230 (PL2) by two SV promoting spacer layers 240 and 250, respectively. The magnetization of the first pinned layer 220 is fixed through exchange coupling with a first antiferromagnetic (AFM1) layer 225. The magnetization of the second pinned layer 230 is fixed through exchange coupling with a second antiferromagnetic (AFM) layer 235 (AFM2). Free layer 210, spacer layers 240 and 250, pinned layers 220 and 230 and the AFM layers 225 and 235 are all formed in the central region 202. Hard bias layers 260 and 270 formed in the end regions 204 and 206, respectively, longitudinally bias the MR free layer 210. Leads 280 and 290 formed over hard bias layers 260 and 270, respectively, provide electrical connections for the flow of the sensing current I.sub.s from a current source (not shown) to the MR sensor 200.
Referring to FIG. 2, the magnetization directions of PL1 and PL2 are arranged in such a way that a rotation of the free layer magnetization generates an SV signal of equal sign across the SV promoting spacers, leading to a larger SV effect in dual spin valve sensors as compared to the SV effect in the spin valve sensor of FIG. 1. For example, a dual spin valve sensor having a 70 angstrom thick free layer exhibits an SV effect of about 3.6%-5.5% in comparison to an SV effect of about 3%-4.5% for a single spin valve sensor of the same thickness free layer.
However, there are several significant problems associated with the typical dual SV sensor of FIG. 2.
First, a typical prior art dual SV sensor requires two antiferromagnetic layers (AFM1 and AFM2)with sufficiently large exchange bias fields (usually greater than 200 Oe) in order to pin PL1 and PL2. However, in practice it is difficult to have sufficiently large exchange bias fields for pinning the pinned layers because exchange bias fields magnitude changes significantly depending on whether the ferromagnetic layer is deposited on the AFM layer (PL1 220 on AFM1 225) or the AFM layer is deposited on the ferromagnetic layer (AFM2 235 on PL2 230);
second, it is known that in a conventional spin valve sensor (FIG. 1), the stray field from the pinned layer causes a nonuniform magnetization distribution in the free layer leading to approximately 30% reduction of the linear portion (also referred to as the "usable portion" or "dynamic range") of the SV effect. The added stray field from the second pinned layer in the dual spin valve sensor reduces the SV linear range by approximately 60%, largely offsetting the SV effect advantage of the dual spin valve sensor; and PA1 third, prior art dual spin valve sensors require two AFM layers made of FeMn or NiO in order to pin the magnetization of both pin layers by creating pinning fields of about 200 Oe. However, both FeMn and NiO have rather low blocking temperatures (blocking temperature is the temperature at which pinning field for a given material reaches zero Oe) which make their use as an AFM layer difficult and undesirable. Referring to FIG. 3, there is shown the change in the pinning field versus temperature for FeMn having the blocking temperature of about 150.degree. C. (line 310) and NiO having the blocking temperature of about 200.degree. C. (line 320). Considering that a typical SV sensor used in a DASD should be able to operate at a constant temperature of about 120.degree. C. at a pinning field of about 200 Oe, it can readily be seen that FeMn substantially loses it ability to pin the pinned layer at about 120.degree. C. and NiO can marginally provide adequate pinning at about 120.degree. C. It should be noted that once the pinning effect is lost, the SV sensor loses its SV effect either totally or partially rendering the SV sensor useless. FeMn is also very prone to corrosion which makes its use as an AFM layer even more problematic than NiO.
Therefore, there is a need for an invention in which pinned layers' magnetization cancel each other out and further discloses a means for pinning the magnetization of the pinned layers in a dual SV sensor without utilizing an antiferromagnetic layer, thus eliminating the dual SV sensor operation on the temperature sensitivity of the AFM layers.

International Business Machines Corporation


Power inverters include a frame and a power module. The frame has a sidewall including an opening and defining a fluid passageway. The power module is coupled to the frame over the opening and includes a substrate, die, and an encasement. The substrate includes a first side, a second side, a center, an outer periphery, and an outer edge, and the first side of the substrate comprises a first outer layer including a metal material. The die are positioned in the substrate center and are coupled to the substrate first side. The encasement is molded over the outer periphery on the substrate first side, the substrate second side, and the substrate outer edge and around the die. The encasement, coupled to the substrate, forms a seal with the metal material. The second side of the substrate is positioned to directly contact a fluid flowing through the fluid passageway.

Vehicles can utilize electric fraction motors to drive wheels. In such case, a vehicle may include a three-phase alternating current (AC) motor coupled to a power inverter. The power inverter converts direct current (DC) from a power source to alternating current that can be used by the AC motor. Typically, the power inverter includes components, such as insulated gate bipolar transistors (IGBTs) and a direct bonded copper (DBC) substrate. The IGBTs act as switches used in converting the power from DC to AC and are mounted on the DBC substrate. The DBC substrate includes integrated bus bars that may be combined with a circuit card and a signal connector to provide a power electronics package for the vehicle.
As the vehicle starts, changes cruising speeds, accelerates and/or brakes, power demands of the electric traction motor driving the vehicle may fluctuate over a relatively wide range (e.g., in a range of from about 5 kW and about 120 kW). These power demand fluctuations may cause temperature changes in the power inverters during operation. Over time, the operability of the power inverter may degrade due to the temperature changes. Specifically, because IGBTs and DBCs may be made of different materials, they may expand and/or contract at different rates and thus, may shift positions relative to each another.
To limit the expansions and contractions of the power inverter components to a selected range, the temperature changes within the power inverter may be controlled. For example, the power inverter may include a cooling system that provides fluids that are circulated through heat sinks associated with the DBC substrate. In other instances, air may be directed over the power electronics package to absorb and remove heat from the DBC.
Though the aforementioned configurations have been generally sufficient for cooling the power inverter components, they may be improved. For instance, the aforementioned configurations may be relatively heavy and may not be suitable for inclusion into vehicles having weight restrictions. In other cases, the aforementioned configurations may have a relatively large footprint and may not be useful for inclusion into small vehicles. In still other cases, the heat sink may not remove heat from the DBC substrate as efficiently as desired.
Accordingly, it is desirable to have a power inverter that has a cooling system that is more lightweight and/or smaller in size than conventional inverters. In addition, it is desirable for the power inverter to be relatively simple and inexpensive to manufacture. Moreover, it is desirable for the cooling system to be suitable for inclusion into a variety of different space configurations within different types of power inverters. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.


An optoelectronic measuring device having scanning functionality having a pulsed radiation source for generating a measuring beam from light pulses at a light pulse emission rate, an optoelectronic detector for detecting light pulses reflected from a target object, a control and analysis unit designed for measuring a distance value from a respective scanning point of the target object according to the time-of-flight principle, based on a number n>=1 of light pulses, wherein the control and analysis unit is designed to automatically set the number (n) depending on a target-object-related measured value determined by the measuring device in real time.

Optoelectronic measuring devices having scanning functionality, using which a position is determined based on optical radiation, are known in manifold forms. Examples are geodetic measuring devices such as total stations or multi-stations, for example total stations and laser scanners such as the Leica P20 or Leica Multistation 50, laser trackers, or profilers, which are used to measure and/or produce 3D coordinates of surfaces, or laser scanners for geodetic or industrial measuring purposes. 3D scanning is a very effective technology for producing millions of spatial measurement points of objects within minutes or seconds. Typical measuring tasks are the recording of objects such as gear wheels, wings, ships, or aircraft, and/or the surfaces thereof or objects such as industrial plants, house facades, or historical buildings, but also accident locations and crime scenes. For this purpose, they have to be capable of guiding the measuring beam of a distance measuring device over a surface and simultaneously acquiring direction and distance in relation to the measurement point. A so-called 3D point cloud is generated from the distance and the direction information correlated therewith for each point by means of data processing.
Such measuring devices have for this purpose at least one radiation source for generating optical measuring radiation, often laser radiation, and optical means such as lenses, prisms, mirrors, light-guiding fibers, or collimators, by means of which the generated measuring radiation can be emitted in free space onto a target to be measured, because of which these devices are also referred to as so-called free beam sensors. Optical measuring radiation is understood in this case as electromagnetic radiation, not only in the visible range of the spectrum, but rather also radiation in the ultraviolet, in the infrared, and in the terahertz range. Optoelectronic measuring devices are known which use measuring radiation having a wavelength of 405 nm, 532 nm, 635 nm, 650-690 nm, 780 nm or 765 nm, 795 nm, 808-850 nm, 905 nm, 980 nm, 1064 nm, or between 1500 and 1570 nm.
Furthermore, such a device has a beam deflection unit, by means of which the measuring radiation can be pivoted around at least one axis, usually two axes aligned perpendicularly to one another, for example, a vertical and horizontal axis. The beam deflector can be implemented in the form of a moving mirror or alternatively also by other elements suitable for the controlled angle deflection of optical radiation, for example, rotatable prisms, movable light guides, deformable optical components, etc.
The target to be measured is, for example, a point of a surface of a natural object. The irradiated target reflects measuring radiation in a diffuse or oriented manner, so that at least a part of the measuring radiation is reflected back to the measuring device. The measuring device has an optoelectronic sensor, which is designed for at least time-resolved detection of the measuring radiation, for example, an APD diode, an SPAD array, or an array of SPAD arrays. The desired measured variable, for example, a distance and direction value and/or a 2D/3D coordinate, is determined on the basis of the detected measuring radiation. Various measuring principles are available for this purpose, for example, a runtime measurement (time-of-flight, TOF), which determines the runtimes of individual laser pulses and therefrom from—with knowledge of the speed of light—the distance from the target object.
In this case, a plurality of surface points of the target object is sampled in succession by the pivoting, whereby, for example, an item of 3D information about the object as a whole can be obtained and/or a 3D image of the measuring environment is produced. The measurement is usually performed with determination of distance and angles, i.e., in spherical coordinates, which can also be transformed into Cartesian coordinates for display and further processing.
For rapid and accurate scanners, in particular a short measuring time is required with high measurement accuracy at the same time, for example, a distance accuracy in the millimeter range or less at measuring times of the individual points in the range of sub-microseconds to milliseconds. The measuring range extends in this case from a few centimeters up to several kilometers. The spatial measuring resolution is of particular significance in this case. It determines which details can still be recognized, but also the duration of the scanning procedure and the quantity of data arising in this case. Measuring projects using modern high-speed scanners produce 3D point clouds having a strength of, for example, several hundred million or several billion object points and above.
The accuracy of the measurement result and/or the quality of the determination of the respective distance values is substantially dependent on the signal-to-noise ratio (SNR). This is in turn decisively dependent on the detected radiant power. A high detected radiant power is advantageous to be able to delimit the measuring radiation unambiguously and sharply from the electronic and photonic noise and/or from the background radiation. The detected radiant power is often problematically weak when measuring targets having low reflectivity and/or small reflection coefficients, as many natural surfaces have. In this case, man-made structures such as concrete, asphalt, or metal are also to be understood as natural targets. For example, black target objects such as car tires are measurable only very inadequately or not at all using scanners of the prior art. On the other hand, specular reflecting targets such as metals or surfaces which are glossy in the respective wavelength range also result in low detected radiant powers away from the direction having the strongest reflection and therefore in poor measurement results.
On the other hand, elevated noise has a negative effect on the signal-to-noise ratio and thus on the measurement result. Elevated or high noise occurs above all during measurements outside, primarily due to solar radiation, which is incident directly or as ambient light diffusely on the receiving optical unit and then—for example, even in spite of an optical bandpass filter—on the detector of the measuring device. In particular when targeting and measuring bright surfaces, such as white house facades, the background radiation can be substantial, the shot noise level in the receiving unit rises and reduces the signal-to-noise ratio and thus the measurement accuracy.
Carrying out a runtime measurement not only on the basis of a single respective detected light pulse or sampled point, but rather using multiple successive or adjacent light pulses and employing them for the measurement is known from the prior art for increasing the detected power and/or improving the signal-to-noise ratio. I.e., multiple light pulses and the object points thus sampled are combined to form one scanning point.
However, this is generally performed fixedly by a fixed user-side specification for the entire scan, during which the user selects whether and to what extent such a combination occurs. Before a scanning procedure, the user sets a quality factor in each case at the operator interface, which establishes the typical distance noise. If a relatively high number of light pulses and thus points is combined in one scanning pass, this does enable usable measured values or scanning points to be obtained, for example, from weakly reflective targets, however a sufficiently dense scanning grid is thus generated at most at short range. In the case of more remote objects, in contrast, scanning points are then "missing" and/or only a very wide-meshed scanning grid is provided and the position resolution is too low to satisfactorily acquire the geometry of a respective object. Vice versa, more remote objects can also be scanned with sufficiently good resolution using a scan having analysis, for example, of each individual light pulse ("single shot" ), however the mentioned problem of a poor SNR arises again, for example, with stronger intensity of the background signal or poorly reflective target objects in the scanning range.

Optoelectronic measuring device having scanning functionality


A heat spreader and method for thermal management of a computer memory module by promoting natural convection cooling of the memory module. The heat spreader includes a frame surrounding a planar body adapted to be mounted to a memory module of a computer, and a grid defined in the planar body by a plurality of uniformly distributed perforations. The perforations extend through the planar body to allow natural convention between an interior space beneath the planar body and an exterior space above the planar body.

The present invention relates to thermal management equipment and methods for computer memory modules, and more particular to a heat spreader that can be assembled with a memory module to promote natural convection cooling of the module.
Memory bandwidth requirements have steadily increased as a countermeasure against data starvation of central processors of personal computers. A number of different strategies have been employed to provide better data throughput to and from the system memory pool. The three most important measures have been to increase the memory clock frequency, increase the data rate, and increase the number of physical banks to allow for more pages that can be held open.
As a rule of thumb, power consumption of any integrated circuit increases in a linear fashion with the clock frequency and, therefore, the migration to higher memory core frequencies necessarily results in higher power draw. Likewise, the increased power consumption of open memory pages is well documented. Combined, the higher operating frequency, along with the increased system memory density and higher number of ranks/open pages, have reached a stage where heat dissipation of computer memory modules becomes a limiting factor. For example, in high density DDR2 SDRAM (double-data-rate two synchronous dynamic random access memory) components, a new access latency has been introduced to add wait cycles between bank-interleaved read accesses during the four bank activation window (tFAW), without which the memory components might incur thermal runaway.
Recently, thermal management of memory modules has employed dedicated memory heat spreaders that are added to the modules and serve the purpose of thermally buffering and dissipating the heat generated by the memory IC's. Typically, heat spreaders have been designed to have a solid surface for maximum contact with the individual components. However, a major drawback of such a configuration is that the heat spreader encapsulates the modules and traps the air space between the components. This trapping of heat does not affect the short term buffering of thermal transients by the heat spreaders, but raises the overall operating temperature of the modules.
The issue of heat trapping is especially of concern in the case of registered modules where a high speed clock chip or phase lock loop (PLL) chip and registers are added, either of which consumes constant power at a rate higher than that of the average memory IC. This has led to either overheating of the PLL and heating of the memory chips by the PLL.
In view of the heat-trapping problem, dedicated memory fans have been employed to reduce the dead air space between memory modules enclosed by solid-surface heat spreaders. While effective, fans incur an additional and undesirable cost. Other proposed solutions include the use of water-cooled memory modules that are more efficient, but are also more expensive to implement than fan cooling. In view of the above, there is a need for effective but less expensive cooling solutions for memory modules.

Method and apparatus for thermal management of computer memory modules


An ultrasonic sensor includes a transceiver device for transmitting and receiving ultrasonic waves; a circuit board mounted with an electronic circuit processing ultrasonic signals transmitted and received through the transceiver device; a housing including a device storing portion storing the transceiver device, a board storing portion storing the circuit board and a communication hole for bringing the device storing portion and the board storing portion into communication with each other, the board storing portion having an opening; and an electric connection unit extending through the communication hole to electrically interconnect the transceiver device and the circuit board. A cover member is installed in the opening of the board storing portion to hermetically seal the board storing portion.

Conventionally, there is available an ultrasonic sensor that includes, as shown in FIG. 13, a hollow housing 101 having an opening on one surface thereof, a transceiver device 102 having a wave transceiving surface for transmitting and receiving ultrasonic waves, the wave transceiving surface exposed on the other surface of the housing 101, a circuit board 103 arranged within the housing 101 and mounted with an electronic circuit for processing ultrasonic waves transmitted and received through the transceiver device 102, a wiring line 104 electrically interconnecting the transceiver device 102 and the circuit board 103, a cover member 105 installed to cover the opening of the housing 101, and a terminal 106 connected at one end to the circuit board 103 by welding or other methods and at the other end to a power supply terminal (not shown).
When used in a motor vehicle, the ultrasonic sensor is installed in a portion highly susceptible to drenching and severe vibrating, e.g., a bumper or a front grill. In many conventional ultrasonic sensors, therefore, a filler material 107 (such as silicone or the like) having hydrophobicity and elasticity is filled in the housing 101 accommodating the circuit board 103 and so forth. It is a typical configuration to secure an increased waterproof property and a high vibration resistance in this manner (see, e.g., Japanese Patent Application Publication No. 2005-24351).
In the conventional example stated above, however, the weight and cost of the ultrasonic sensor is proportionately increased as the filler material 107 is filled in the housing 101. In addition, there is a possibility that, due to the existence of the filler material 107, distortions are generated in the circuit board 103 arranged within the housing 101. It is also likely that cracks are generated in the solder portions between the circuit board 103 and the electronic parts mounted on the circuit board 103. There is also the likelihood that the sensing area characteristics of the sensor are changed before and after filling the filler material 107. Other causes of generating distortions in the circuit board 103 include, e.g., an external load generated by the thermal expansion and shrinkage of the filler material 107. Examples of the change in the sensing area characteristics before and after filling the filler material 107 include the narrowing of a sensing area of the sensor. There is also a problem in that a great deal of time is required in the drying process. In this viewpoint, there remains a room for improvement.

PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.


The texture coordinates (u,v) of a point Q' are determined by: (1) determining the modified texture coordinates (u',v')=(u/z,v/z) by linear interpolation, where z is a world coordinate; (2) determining 1/z by linear interpolation; and (3) dividing (u',v') by 1/z. The division is replaced with multiplying (u',v') by the inverse of 1/z. The inverse is obtained using a lookup table (LUT). The LUT stores inverses of a few values. Linear interpolation is applied to the LUT output to increase the inverse value accuracy.

The present invention relates to computers, and more particularly to determining texture coordinates in compute graphics.
Textures are used in computer graphics to make computer-generated images appear more realistic. A texture consists of a number of texture elements ("texels"). Each texel has a value corresponding to color, intensity, or some other image parameter. Texel values are used to modify the color, intensity, or other parameters of corresponding pixels in the computer image. See, for example, M. Segal et al., "Fast Shadows and Lighting Effects Using Texture Mapping", Computer Graphics, 26, 2, July 1992, pages 249-252, incorporated herein by reference.
In the computer, texels are identified by texture coordinates. Thus, finding a proper texel for a pixel involves determining the texel's texture coordinates. It is desirable to provide small and inexpensive circuits for determining the texture coordinates.

Determining texture coordinates in computer graphics


A new approach to customer support that protects working artifacts through their entire lifecycle by provisioning, on-demand, a transient-controlled debugging environment that preferably is associated with a particular support issue (or subset of issues) when particular artifacts (e.g., files) are securely received at the service or software provider. This approach allows for complete (or substantially complete) isolation and control of the artifacts in a contained environment for so long as necessary by the provider. Preferably, the provider owns or otherwise manages the provisioned environment, which can be augmented as needed to meet the debugging requirements of the particular issue. Preferably, the provisioned environment is restricted in access to only those engineers or others with a verifiable need to know, or that have the necessary training and skill sets for the support operation required.

1. Technical Field
This disclosure relates generally to network-based support activities.
2. Background of the Related Art
In the course of providing customer support for software products (e.g., debugging, or maintaining critical infrastructure), customers must often must send artifacts to service or software providers. In situations where the infrastructure may contain regulated data, e.g., HIPAA, tight controls must exist to ensure that the information is not disseminated beyond fully-qualified and trained support engineers. The working artifacts thus must be protected in transit, while in review, and in use, until such time as it can be assured that they are destroyed. Since the Health Information Technology for Economic and Clinical Health Act (HITECH) was enacted in 2009, industry has struggled to maintain compliance. There are many industry-standard methods for the secure transit of files, but these methods only protect the working artifacts while in transit, and they provide no protection once the artifacts arrive in the service provider's environment. To address this problem, many companies opt to create virtual private networks (VPNs) to allow the service provider to work within the customer's environment, but this solution opens up that environment to potential compromise, and it does not prevent unintended disclosure or exposure to only required artifacts. The problem is further exacerbated if the customer requires that all work be done on the customer's own assets, which may not include the full suite of debugging tools often required by support engineers. As a stop-gap solution, support engineers often go on-site to the customer environment to debug issues, but this is an expensive, non-scalable solution.

Provisioning transient-controlled secure environments for viewing sensitive data

International Business Machines Corporation