A semiconductor component comprises a semiconductor body including a front side and a number of cell strips. Each of the cell strips includes a terminal zone of a first type arranged on the front side of the semiconductor body and a terminal zone of a second type arranged on the front side of the semiconductor body. A patterned first metallization layer, a patterned second metallization layer, and a patterned third metallization layer are arranged successively on the front side. A first plurality of conductive lines are formed in the first metallization layer and a second plurality of conductive lines are formed in the second metallization layer. The second plurality of conductive lines cross the first plurality of conductive lines at crossover locations. The second plurality of conductive lines are electrically conductively connected to the first plurality of conductive lines at predetermined crossover locations.

In order to be able to carry higher currents, semiconductor components of this type have a plurality of cells that are electrically connected in parallel with one another. Each of the cells comprises a terminal zone of a first type, for example, a drain terminal of a DMOS cell, and a terminal zone of a second type, for example a source terminal of a DMOS cell. Usually a plurality of such cells are in each case connected together to form cell strips.
In order that two or more of such cell strips are electrically connected in parallel, with regard to all the cell strips to be connected in parallel firstly their terminal zones of the first type must be electrically conductively connected to one another and secondly their terminal zones of the second type must be electrically conductively connected to one another.
FIG. 1 shows a section of such a semiconductor component in accordance with the prior art in a perspective view.
The semiconductor component comprises a semiconductor body 10 having two cell strips 91, 92 having a cell strip width d ("pitch"), which each have a strip-shaped terminal zone 7 of a first type and a strip-shaped terminal zone 8 of a second type. The terminal zones 7, 8 run in a first lateral direction x of the semiconductor body 10 and perpendicular to a second lateral direction y of the semiconductor body 10.
By way of example, the terminal zones 7 of the first type are formed as drain terminal zones D and the terminal zones 8 of the second type are formed as source terminal zones S. The terminal zones 7 of the first type and terminal zones 8 of the second type are arranged alternately successively and parallel to one another.
A patterned first metallization layer 1, a patterned second metallization layer 2 and a patterned third metallization layer 3 are arranged successively on the front side 19 of the semiconductor body 10 above the terminal zones 7, 8. The first and second metallization layers 1, 2 are formed from aluminum and the third metallization layer 3 is formed from copper.
The third metallization layer 3 has a first section 33 and a second section 34. All the terminal zones 7 of the first type are electrically conductively connected to the first section 33 and all the terminal zones 8 of the second type are electrically conductively connected to the second section 34 of the third metallization layer 3.
The first and second metallization layers 1, 2 are primarily required for feeding the necessary electrical drive signals to terminal zones (not illustrated in FIG. 1) for driving the cell strips 91, 92 that is to say the gate terminal zones thereof, by way of example.
Since, for this reason, the first and the second metallization layer 1, 2 cannot be dispensed with, sections of the first and the second metallization layer 1, 2 are used for producing, together with plated-through holes 41, 51, 61 which are also referred to as "vias", and also with further plated-through holes that are not discernible in this view, the electrically conductive connections between the terminal zones 7 of the first type and the first section 33 of the third metallization layer 3 and also between the terminal zones 8 of the second type and the second section 34 of the third metallization layer 3.
For this purpose, the patterned first metallization layer 1 has conductive lines 11, 12, 13, 14 spaced apart from one another and the patterned second metallization layer 2 has conductive lines 21, 22, 23, 24 spaced apart from one another. The conductive lines 11, 12, 13, 14, 21, 22, 23, 24 are formed in strip-shaped fashion and run parallel to one another and also parallel to the strip-shaped terminal zones 7, 8 of the semiconductor body 10.
Each of the terminal zones 7, 8 forms a unit with two overlaying conductive lines, of which one belongs to the first metallization layer 1 and one belongs to the second metallization layer 2, and is electrically conductively connected to these by means of plated-through holes. Arranged above the conductive lines 21, 23 of the second metallization layer 2 are plated-through holes 61 which electrically connect the conductive lines 21, 23 to the first section 33 of the third metallization layer 3.
Correspondingly, arranged above the conductive lines 22, 24 of the second metallization layer 2 are plated-through holes (not discernible in FIG. 1) which electrically connect the conductive lines 22, 24 to the second section 34 of the third metallization layer 3.
An intermetal dielectric is generally arranged between the semiconductor body 10 and the first metallization layer 1, between the first metallization layer 1 and the second metallization layer 2, between the second metallization layer 2 and the third metallization layer 3, between the conductive lines 11, 12, 13, 14 of the first metallization layer 1, between the conductive lines 21, 22, 23, 24 of the second metallization layer 2, and also between the sections 33, 34 of the third metallization layer 3; the illustration of said intermetal dielectric has been dispensed with in FIG. 1 for reasons of clarity.
FIG. 2 shows a plan view of the semiconductor component in accordance with FIG. 1. This view reveals the conductive lines 21, 22, 23 and 24 of the second metallization layer, above which the sections 33, 34 of the third metallization layer are arranged.
The positions of plated-through holes 61, 62 arranged between the second and the third metallization layer 2, 3 are indicated as dotted circles in FIG. 2.
In this case, the plated-through holes 61 connect the conductive lines 21, 23 of a second metallization layer that are connected to the drain terminal zones to the first section 33 of the third metallization layer. The plated-through holes 62 correspondingly connect the conductive lines 22, 24 of the second metallization layer that are connected to the source terminal zones to the second section 34 of the third metallization layer.
In the context of technical further development, the cell strip widths d decrease further and further whilst retaining the same current-carrying capacity, which, relative to the active chip area, leads to ever higher current densities in the component.
In such an arrangement with increasing current densities undesirably high voltages are dropped across the electrical line resistances between the terminal zones 7 and the section 33 of the third metallization layer 3 and also between the terminal zones 8 and the section 34 of the third metallization layer 3.

Semiconductor component comprising interconnected cell strips


A system for identifying the position of a tire on a vehicle based on wireless messages received from the tire includes a receiver circuit, a signal strength circuit, a memory, and a processing circuit. The receiver circuit is configured to receive the wireless messages. The signal strength circuit is configured to determine the signal strengths of the wireless messages. The memory is configured to store a predetermined frequency distribution. The processing circuit is configured to provide a frequency distribution of the wireless messages based on the signal strengths and to compare the frequency distribution to the predetermined frequency distribution to determine the position of the tire on the vehicle.

Increasing attention is being given to monitoring the pressure of tires on a vehicle while the vehicle is in motion. A typical tire pressure monitor includes a plurality of transmitter circuits coupled to each of a plurality of tires on a vehicle, each transmitter circuit including a tire pressure sensor inserted into the tire and a radio frequency transmitter. The transmitter circuits sense tire pressure and generate radio frequency signals in the form of a message, the message including a tire identification number and the sensed tire pressure. The tire pressure monitor also includes a receiver circuit coupled to the vehicle for receiving the radio frequency signals. The receiver circuit processes the signals by, for example, displaying the tire pressures of each tire, providing warnings when the tire pressures are outside predetermined parameters, etc.
One challenge in tire pressure monitoring is identifying the location of the tires on the vehicle (e.g., left front, left rear, right rear, etc.). As tires are changed or rotated, the tire locations must be updated. In order to display the proper tire pressure to the driver for each tire, the locations of the tires must be known.
According to one prior system, signals coming via various reception antennas are processed not individually but rather together, and evaluated as to signal intensity for purposes of allocation to a specific wheel. The signals are summed, and the intensity of the summed signal is determined and compared to the intensity of a summed signal constituted by temporarily switching only Nxe2x88x921 reception antennas to the input of the receiver. The disconnected reception antenna is changed cyclically. According to the teachings of this system, the antenna whose deactivation results in the greatest intensity loss in the summed signal is normally that antenna which is located closest to the transmitting wheel electronics package, and thus receives the signal with the greatest field strength.
One drawback of this system is that some signals may be received with a higher signal strength at a reception antenna which is not closest to the position of the transmitting wheel, due to multipath, interference caused by spinning tires and surrounding objects, and other disturbances. This can lead to inaccurate results, which is disadvantageous in a system where it is very important to avoid providing misleading tire pressure data to the operator. Furthermore, this system requires multiple reception antennas, and, therefore, cannot be used with a tire pressure monitoring system having only one antenna.
Accordingly, what is needed is an accurate system and method for identifying tire position that does not require manual programming. Further, what is needed is a system and method usable on tire monitoring systems having one antenna or a plurality of antennas. Further still, what is needed is a system and method for passively identifying tire position that is more accurate and reliable than prior systems. Further yet, what is needed is a system that can detect tire position universally, i.e., without the need for a specialized transmission protocol. The teachings hereinbelow extend to those embodiments which fall within the scope of the appended claims, regardless of whether they accomplish one or more of the above-mentioned needs.
According to one exemplary embodiment, a method of identifying the position of a tire on a vehicle includes receiving a plurality of wireless messages from a transmitter associated with the tire and determining the signal strengths of the received wireless messages. The method further includes providing a frequency distribution of the wireless messages based on the signal strengths and comparing the frequency distribution to a predetermined frequency distribution to determine the position of the tire on the vehicle.
According to another exemplary embodiment, a system for identifying the position of a tire on a vehicle based on wireless messages received from the tire includes a receiver circuit, a signal strength circuit, a memory, and a processing circuit. The receiver circuit is configured to receive the wireless messages. The signal strength circuit is configured to determine the signal strengths of the wireless messages. The memory is configured to store a predetermined frequency distribution. The processing circuit is configured to provide a frequency distribution of the wireless messages based on the signal strengths and to compare the frequency distribution to the predetermined frequency distribution to determine the position of the tire on the vehicle.
According to yet another exemplary embodiment, a system for determining the position of a tire on a vehicle includes a means for receiving a plurality of transmitted messages from a transmitter associated with the tire. The system further includes a means for determining the signal strength of the plurality of transmitted messages and a means for providing a pattern of the messages based on the signal strengths of the plurality of transmitted messages. The system further includes a means for determining the position of the tire on the vehicle based on the pattern of the messages and a stored pattern of signal strength values.

Using signal strength to identify tire position


There is provided an ergonomic rake which includes an elongated handle having first and second ends. A head is attached to the handle at its first end. The second end of the handle is a free end. A bend is provided in the handle so that the user of the rake may remain in a substantially upright position while raking to reduce the likelihood of a back injury. A support stand is rotatably attached to one side of the head. By using the support stand, the rake may be stood up while not in use so that the user does not need to bend over to pick up the rake, which also reduces the likelihood of a back injury.

This invention relates to rakes. More particularly, it relates to ergonomically designed rakes which help avoid back injuries.
A standard yard rake has an elongated straight handle attached to a raking head. The standard rake has been known to cause the user back injuries because the user must bend his back in order to properly use the rake. The use of a standard rake is illustrated in FIG. 1. In addition, when the rake is not in use, it often is laid flat on the ground. Thus when the user is ready to use the rake, he must bend over and pick up the rake from the ground, which also can cause back injuries.


Described herein are implantable devices, formulations and methods of making implantable devices for the release of a polypeptide from an implantable device, and methods of use thereof.

The sustained release of active agents, e.g., exenatide, is known to be of value. In particular, long-term drug delivery has been shown to be effective in obtaining constant serum levels and in improving patient compliance.
Hydrogel membranes may be used for sustained delivery of active compounds. There are several theories regarding the mechanism of solute diffusion in hydrogels. The hydrogels that have been described have some porosity due to the network structure of the crosslinked polymer chains, which allow smaller molecules to diffuse through the structure. The size of the pores varies depending upon the hydrogel chemical composition and thus its degree of hydration. The hydrogels described in the art, however, are not particularly well adapted for delivery of large macromolecules, including bioactive proteins useful for the therapeutic treatment of humans and animals.
There is a need for delivery devices that provide controlled delivery of therapeutically effective amounts of bioactive polypeptides, which can be utilized in the treatment of a variety of diseases and pathological conditions in humans and animals.

This patent is subject to a terminal disclaimer.

Implantable device for the sustained release of a polypeptide


A projection engine uses a first polarizing beam splitter (PBS) that substantially reflects light incident along a first input direction in a first polarization state and substantially transmits light incident in the first input direction in a second polarization state orthogonal to the first polarization state. The first PBS demonstrates an angularly dependent reflectivity for light in the second polarization state that is asymmetric about the first input direction. At least two imager devices are positioned to receive light reflected and transmitted by the first PBS respectively. The imager devices modulate the incident light with an image. The image light from the imagers is combined and projected.

Optical projection systems typically include a transmissive or a reflective imager, also referred to as a light valve or light valve array, which imposes an image on a light beam. Reflective light valves modulate only selected portions of the input beam to form an image, and provide important advantages over transmissive light valves. For example, reflective light valves permit controlling circuitry to be placed behind the reflective surface, and more advanced integrated circuit technology is available because the substrate materials are not limited by their opaqueness.
Many reflective liquid crystal display (LCD) imagers rotate the polarization of incident light. Thus, polarized light is either reflected by the imager with its polarization state substantially unmodified, or with a degree of polarization rotation imparted to provide a desired grey scale. Accordingly, a polarized light beam is generally used as the input beam for reflective LCD imagers. A desirable compact arrangement includes a folded light path between a polarizing beamsplitter (PBS) and the imager, wherein the illuminating beam and the projected image reflected from the imager share the same physical space between the PBS and the imager. The PBS separates the incoming light from the polarization-rotated image light. A single imager may be used for forming a monochromatic image or may also be used for forming a color image when the single imager is illuminated with light whose color is temporally varied. Multiple imagers may be used for forming a color image, where the illuminating light is split into multiple beams of different color, for example red, green and blue. An image is imposed on each of the colored beams individually by respective imagers, and the differently colored image beams are then recombined to form a full color image beam.
It is desirable to use as much light generated by the light source as possible. Where the light source generates light over a wide angle, such as an arc lamp, more light can be passed through the imager system using low f-number optics. A problem, termed "polarization cascade" and associated with a conventional PBS that relies on Brewster effects to polarize the light, places a lower limit on the f-number of the illumination optics of traditional optical imaging systems. A conventional PBS used in a projector system, sometimes referred to as a MacNeille PBS, uses a stack of inorganic dielectric films placed at Brewster's angle. Light having s-polarization is reflected, while light in the p-polarization state is transmitted through the polarizer. However, wide angle performance is difficult to achieve using these polarizers, since the Brewster angle condition for a pair of materials is strictly met at only one angle of incidence. As the angle of incidence deviates from Brewster's angle, a spectrally non-uniform leak develops. Furthermore, there are contrast disadvantages for a folded light path projector associated with the use of p- and s-polarization.
Since light in a projection system is generally projected as a cone, most of the rays of light are not perfectly incident on the polarizer at Brewster's angle, resulting in depolarization of the light beam. The amount of depolarization increases as the system f-number decreases, and is magnified in subsequent reflections from color selective films, for example as might be found in a color-separating prism. It is recognized that the problem of depolarization cascade effectively limits the f-number of the projection system, thereby limiting the light throughput efficiency.


A semiconductor device package having pre-formed and placed through vias and a process for making such a package is provided. One or more signal conduits are placed in a holder that is subsequently embedded in an encapsulated semiconductor device package. The ends of the signal conduits are exposed and the signal conduits are then used as through package vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package. Holders can be provided in a variety of geometries and materials, depending upon the nature of the application. Further, multiple holders with signal conduits can be provided in a single package to provide for more complex interconnect configuration demands in, for example, system-in-a-package applications.

1. Field
This disclosure relates generally to semiconductor device packaging, and more specifically, to providing through-package vias in an encapsulated device package by using pre-formed signal conduits, such as conductive pillars and optical waveguides.
2. Related Art
Semiconductor and other types of electronic devices are often encapsulated wholly or partly in resin to provide environmental protection and facilitate external connection to the devices. Subsequent to encapsulation, interconnect structures can be built up on one or both sides of the encapsulated devices. For packages having electrical contacts on both top and bottom surfaces (e.g., a double-sided buildup), through-vias are often made to provide contacts between bottom side and top side interconnect structures. Traditionally, through package vias are made after encapsulation using a drilling and filling/metallization process that includes steps for via drill, via fill/metallization, polish and taping, and so on. This process of post-encapsulation via formation introduces complexities to the manufacturing process that have a variety of manufacturing and reliability challenges (e.g., consistent integrity of the through via and reliable connection to the interface). Further, costs associated with materials, processes and additional tooling to generate the through vias can be high.
It is therefore desired to have a process for creation of through package vias by utilizing existing tools for manufacturing encapsulated packages. It is further desired that the mechanism for providing through vias allows for flexible configurations of vias and dies incorporated into a device package.
The use of the same reference symbols in different drawings indicates identical items unless otherwise noted. The figures are not necessarily drawn to scale.

Semiconductor device packaging having pre-encapsulation through via formation using drop-in signal conduits


An example method is provided in one example embodiment and includes receiving a handover request from a first radio network to handover a user equipment (UE) to a second radio network, wherein the handover request includes an international mobile subscriber identity (IMSI) for a user associated with the UE and a pseudo cell identifier (ID); determining a target channel configuration for the UE using the pseudo cell ID; querying a third radio network using the user IMSI to determine a location of the UE, wherein at least one access point in the third radio network is in communication with the UE; and selecting a particular target access point in the second radio network for handover of the UE based, at least in part, on the location of the UE, the target channel configuration for the UE and a location of the particular target access point.

Networking architectures have grown increasingly complex in communication environments. For example, small cells have gained notoriety due to their capabilities to connect wireless devices to a network. In general terms small cell access points can operate in a licensed spectrum to connect user equipment to the network, often using broadband connections. For a mobile operator, small cell access points can offer improvements to both coverage and capacity, which is particularly applicable to indoor networking environments where macro cells typically suffer coverage limitations. Small cell access points can also offer an alternative networking architecture to deliver the benefits of fixed-mobile convergence. However, there are significant challenges in managing access to small cell access points, particularly in the context of hand-in operations from macro cells.

System and method for hand-in disambiguation using user equipment WiFi location in a network environment


The present disclosure relates to an in vivo fluorescent or radioactive probe represented by a compound of formula I which is capable of longitudinal imaging of inducible nitric oxide synthase (iNOS) expression in living cells and living animals on a real time basis. The probe of the present disclosure can exhibit specific and high affinity binding to the iNOS enzyme with reduced enzyme inhibitory property and also enables longitudinal monitoring of iNOS expression along with its activity or NO production in a same experimental subject throughout the progression of a physiological or disease process without employing separate subjects as controls and experimental. The present disclosure further provides a rapid and inexpensive real time method for visualizing iNOS expression and its activity in living cells and living animals precisely, conveniently and reversibly along with simultaneous in vivo imaging of its catalytic product, nitric oxide (NO) in live physiological settings.

Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
Nitric-Oxide Synthase (NOS) is a mammalian enzyme responsible for producing the biologically versatile compound Nitric-Oxide (NO), which plays a critical role in various life-sustaining processes like, blood circulation, memory, neurotransmission, vision and immune response. NOS, is a bi-domain enzyme which is only active in its dimeric form and utilizes arginine (Arg) as a substrate to produce the biologically active product, NO along with citrulline. NOS exists in three different forms or isoforms in the human body namely, inducible (iNOS), neuronal (nNOS) and endothelial (eNOS) to cater to different levels of NO requirement for specific physiological functions in different tissue environments. However, overproduction of NO, specifically by its inducible form, iNOS, has been etiologically linked to several inflammatory, immunological and neuro-degenerative diseases like arthritis, inflammatory bowel syndrome (IBD), asthma, sepsis, diabetes, Parkinson and Alzheimer's disease, thus making iNOS a subject of great clinical significance and interest, especially as a signature for biological inflammation.
A number of imaging techniques including those using fluorescence have been developed in the art for tracking iNOS expression and its activity in tissues, yet severe limitations exist. For instance, Panda et al, PNAS (2005) Vol. 102: 10117-10122, discloses a fluorescein isothiocyanate (FITC)-labeled pyrimidine imidazole conjugate, which although enables static imaging of iNOS in live cells, is however unsuitable for sustained real-time imaging of the enzyme in both cells and animals largely because of its photolability and considerable iNOS inhibition potency. Further, real time monitoring of iNOS expression in live cells and animals remains a challenge because iNOS is an unstable and short-lived enzyme (half-life of around 1.8 h) and thus liable to degeneration within the biological environment quite rapidly. The present imaging techniques employing known antibody based fluorescent probes for detection or expression evaluation of iNOS are not only time consuming but also require killing of the cells or animals making real-time assessment of quantitative expression of this short-lived enzyme along with its catalytic activity or NO producing capability virtually impossible. Moreover, the existing fluorescent probes are not capable of direct, immediate, and selective iNOS detection in live cells and animals. Genetically engineered iNOS-tagged fluorescent proteins (GFP-iNOS or RFP-iNOS) have also been used to facilitate imaging of the expression of iNOS in live cells. However, such techniques require the fusion genes to be transfected (artificially introduced into the cells) and thus cannot be used to monitor in vivo expression of the enzyme, particularly in cells and animals naturally expressing the enzyme (iNOS).
Moreover, the existing imaging techniques only allow for cross-sectional monitoring of enzyme (iNOS) expression which involves different sets of animals or cells as control and experimental. As no animal or cell can be a perfect control for any physiological or disease process, such cross-sectional techniques fail to produce both accurate as well as reproducible results. Such anomalies become critical especially when the level of expression change of the enzyme is particularly low (i.e early stages of diseases or physiological processes involving iNOS).
There is thus a need in the art for a new and improved in vivo iNOS probe that uses fluorescence, radioactivity or any imageable property for imaging the enzyme and is highly selective, highly stable, exhibits high affinity for the iNOS enzyme with reduced enzyme inhibitory property as well as enables real time longitudinal monitoring of iNOS expression along with its activity in living cells and living animals both under physiological and pathological conditions.
Moreover, as iNOS has a relatively short half-life (1.8 h), the existing methods of detection or quantification of the enzyme (i.e. Western blotting or immunofluorescence) do not deliver adequate justice to accurate evaluation of the precise level of expression change of the enzyme as they are significantly time consuming (takes several hours). However, the iNOS probe described in the present disclosure can light up the true expression of the enzyme both in cells and animals within 20 mins of its application thus allowing for rapid and more accurate assessment of the expression change of the enzyme during a physiological or disease process.
The present invention satisfies the existing needs, as well as others, and generally overcomes the deficiencies found in the prior art.

In-vivo probe for real time longitudinal monitoring of inducible nitric-oxide synthase in living cells and animals


A femoral hip joint prosthesis includes a metal component having a double tapered stem and a preapplied cement mantle with an integral centralizer.

The present invention relates to a hip joint prosthesis and more particularly to a femoral component of such prosthesis. U.S. Pat. No. 5,080,680, of which I am a co-inventor, discloses a femoral stem prosthesis with a preapplied cement mantle. A continuation-in-part application of such patent, namely, application Ser. No. 07/673,367, filed Mar. 22, 1991, discloses another embodiment in which the preapplied cement mantle has a series of interstices or openings in the preapplied cement mantle.
As disclosed in the above patent and continuation-in-part application, each of such prostheses is implanted in the intramedullary canal of the femur of a patient, normally with its distal end positioned in a centralizer which assures proper positioning of such distal end in the central area of the intramedullary canal. As is well-known in the field of implanting femoral prostheses, bone cement such as polymethylmethacrylate (PMMA) is normally used to fix the femoral stem prostheses in position. With each of the femoral stem prostheses disclosed in U.S. Pat. No. 5,080,680 and application Ser. No. 07/673,367, filed Mar. 22, 1991, (both of which are incorporated herein by reference) there is a gap between the end of the preapplied cement mantle and the upper end of the centralizer. There is a possibility that, upon implantation of either of such prostheses, the new bone cement will not completely fill the gap and will leave a portion of the stem of the metal component immediately above the centralizer uncontacted by bone cement. The presence of any such uncontacted area could lead to osteolysis and eventual loosening and failure of the implanted prosthesis.


An air fan capable of increasing the amount of air fed in a radial direction thereof. An impeller which includes a plurality of blades for sucking air from one side in an axial direction of a revolving shaft of a motor and guiding sucked air mainly toward the other side in the axial direction is mounted on a rotor of the motor. A casing includes a peripheral wall arranged so as to define a cavity therein in which the motor and impeller are received. A cavity is closed at each of both ends in the axial direction with a closing wall. The peripheral wall is provided at a portion thereof in proximity to an end thereof on the one side with a lateral suction port which permits air to be suckedly introduced therethrough into the cavity in a radial direction of the revolving shaft. Also, the peripheral wall of the casing is provided at a portion thereof in proximity to an end thereof on the other side with a lateral discharge port which permits air suckedly introduced into the cavity to be discharged therethrough in the radial direction. The lateral suction port and lateral discharge port are arranged so as not to be aligned with each other in the axial direction.

This invention relates to an air fan, and more particularly to an air fan adapted to be received in a receiving housing of an electronic appliance to cool an electronic component.
Japanese Patent Application Laid-Open Publications Nos. 231940/1990 (2-231940) and 231941/1990 (2-231941) each disclose an air fan constructed so as to flow feed in a radial direction thereof perpendicular to an axial direction thereof by means of an axial fan. The air fan is generally called a radial fan in the art. An axial fan includes an impeller securely mounted on a revolving shaft of a motor. The impeller is provided with a plurality of blades and constructed so as to suck air on one of both sides defined in an axial direction of the revolving shaft of the motor and guide it toward the other side. Also, the impeller is arranged in a cylindrical cavity which is defined by a peripheral wall of a casing. The axial fan exhibits characteristics capable of increasing the amount of air fed while keeping a pressure at a reduced level. The radial fan was developed utilizing such advantageous characteristics of the axial fan. Thus, the radial fan exhibits characteristics capable of increasing the amount of air fed while being decreased in thickness or depth as compared with a cross-flow fan or a cirrocco fan and reducing noise as compared with a cirrocco fan.
The conventional radial fan described above is so constructed that the cavity in which the impeller is received is closed at one end thereof with a wall and provided with a lateral discharge port, which is formed by removing a part of a peripheral wall of the casing. The lateral discharge port is provided so as to thoroughly extend from one end of the cavity to the other end thereof, so that the blades of the impeller each are fully exposed from the lateral discharge port of the casing when it faces the port during rotation of the impeller.
The inventors made such a radial fan as described above utilizing the axial fan and conducted an experiment on the radial fan thus made. As a result, it was found that the radial fan causes the amount of air discharged from the lateral discharge port and blown against a component being cooled to be less than expected.
Also, when the conventional radial fan is received in a receiving housing of an electronic appliance decreased in thickness or depth, it causes the amount of air fed to be excessively decreased or rendered substantially zero.

Air fan for cooling electronic component


A roof ladder construction includes a roof hook assembly and a ladder to which the roof hook assembly is pivotally mountable for movement between two operative positions, a first of the operative positions being a position in which the roof hook assembly may extend over a roof ridge for engagement with a remote roof surface at a side of the roof opposite that at which the ladder is positioned and the other, second position being one in which the roof hook assembly does not engage with the remote surface of the roof.

Field of the Invention
This invention relates to arrangements for facilitating access to the roof regions of a building.
In particular the present invention is concerned with facilitating access to the roof of a building such as a residential house, an office building, or other buildings having what is known as single pitched or double pitched roof constructions.
As is well known the upper most length part of such a roof is known as the ridge.
In the case of a double pitched roof construction the roof to either side of the roof ridge extends downwardly and outwardly away from the ridge which is usually located midway between the walls of the associated building and are in line with the length of the building. In the case of a single pitched roof the ridge is usually located above the wall that is in line with the length direction of the ridge.
For the purposes of the following discussion it will be presumed that the arrangement for facilitating access to the roof is particularly intended to facilitate access to a double pitched roof.
It is convenient to note that with a view to facilitating reduction in the amount of fossil fuels used for producing electrical power it is known to produce electrical power by harnessing the energy of the sun. This power production can be direct as is possible with the use of photovoltaic cells or indirectly by concentrating solar power upon a heatable material that when heated enables production of electrical power. For example one such method involves appropriately focussing the sun's energy so that the focused energy is able to boil water which is then used to provide the desired power.
Description of the Related Art
Generally speaking in relation to buildings such as above mentioned it has been proposed to mount directly upon the roofs of such buildings electricity generating/producing units incorporating an array of photovoltaic cells. These units are generally known as solar panels and are usually mounted upon a roof at location(s) at which it would be able to receive and react to sunlight over as long as possible period during a day.
A solar panels are generally incorporates a shallow rectangular shallow tray like container within which is located a rectangular array of individual photovoltaic cells appropriately electrically interconnected to the output of the panel. A protective sheet of transparent glass/plastics covers in the cells.
As will be appreciated by reason of their extended area rectangular shape, the shallowness of the panels and the fact that they are covered in with sheet glass/plastics the panels need to be very carefully handled during fitting to a roof and whenever it is desired to carry out servicing operation upon fitted panels.


A plurality of "snoop advisory" bits are maintained by snoop management circuitry externally to the processor structure. Each snoop advisory bit corresponds to a respective "snoop advisory page" of the memory address space. Three parallel processes take place with respect to these bits. First, in response to each read access by the processor structure, if the read access is of a predetermined type (such as a cache line fill operation with intent to modify), snoop management circuitry writes a "snoop yes" value into the snoop advisory cell corresponding to the snoop advisory page which includes the address of the processor's access. Second, in response to each access by another device which shares the address space with the processor structure, a snoop request is issued to the processor structure, but only if the snoop advisory cell corresponding to the snoop advisory page which includes the address of the device's access, contains the "snoop yes" value. Otherwise, the device is allowed to perform its access directly to the memory structure without issuing a snoop request. Third, on a recurrent basis, the processor internal cache is synchronized with the memory structure and the system writes a "snoop no" value into each of the snoop advisory bits to clear them. Synchronization can involve performing a write-back on each cache line which is in a modified state, and/or invalidating each line in the cache.

1. Field of the Invention
The invention relates to cache coherency mechanisms in a multiple processor environment, and more particularly, to a mechanism for reducing the number of snoops required of a processor structure which includes a cache memory.
2. Description of Related Art
Many computer systems include at least one level of cache memory. A cache memory is a high-speed memory that is positioned between a central processing unit (CPU) and main memory in a computer system in order to improve system performance. Cache memories (or caches) store copies of portions of main memory data that are actively being used by the CPU while a program is running. Since the access time of a cache can be faster than that of main memory, the overall access time for accesses by the CPU can be reduced. Descriptions of various uses of and methods of employing caches appear in the following articles: Kaplan, "Cache-based Computer Systems," Computer, 3/73 at 30-36; Rhodes, "Caches Keep Main Memories From Slowing Down Fast CPUs," Electronic Design, Jan. 21, 1982, at 179; Strecker, "Cache Memories for PDP-11 Family Computers," in Bell, "Computer Engineering" (Digital Press), at 263-67, and Intel, "i486 Processor Hardware Reference Manual" (1990) at 6-1 through 6-11, all incorporated herein by reference.
Many microprocessor-based systems implement a "direct mapped" cache memory. In general, a direct mapped cache memory comprises a high speed data Random Access Memory (RAM) and a parallel high speed tag RAM. The RAM address of each line in the data cache is the same as the low-order portion of the main memory line address to which the entry corresponds, the high-order portion of the main memory address being stored in the tag RAM. Thus, if main memory is thought of as 2.sup.m blocks of 2.sup.n "lines" of one or more bytes each, the i'th line in the cache data RAM will be a copy of the i'th line of one of the 2.sup.m blocks in main memory. The identity of the main memory block that the line came from is stored in the i'th location in the tag RAM.
When a CPU requests data from memory, the low-order portion of the line address is supplied as an address to both the cache data and cache tag RAMs. The tag for the selected cache entry is compared with the high-order portion of the CPU's address and, if it matches, then a "cache hit" is indicated and the data from the cache data RAM is enabled onto a data bus of the system. If the tag does not match the high-order portion of the CPU's address, or the tag data is invalid, then a "cache miss" is indicated and the data is fetched from main memory. It is also placed in the cache for potential future use, overwriting the previous entry. Typically, an entire line is read from main memory and placed in the cache on a cache miss, even if only a byte is requested. On a data write from the CPU, either the cache RAM or main memory or both may be updated, it being understood that flags may be necessary to indicate to one that a write has occurred in the other.
Accordingly, in a direct mapped cache, each "line" of secondary memory can be mapped to one and only one line in the cache. In a "fully associative" cache, a particular line of secondary memory may be mapped to any of the lines in the cache; in this case, in a cacheable access, all of the tags must be compared to the address in order to determine whether a cache hit or miss has occurred. "k-way set associative" cache architectures also exist which represent a compromise between direct mapped caches and fully associative caches. In a k-way set associative cache architecture, each line of secondary memory may be mapped to any of k lines in the cache. In this case, k tags must be compared to the address during a cacheable secondary memory access in order to determine whether a cache hit or miss has occurred. Caches may also be "sector buffered" or "sub-block" type caches, in which several portions of a cache data line, each with its own valid bit, correspond to a single cache tag RAM entry.
When the CPU executes instructions that modify the contents of the cache, these modifications must also be made in the main memory or the data in main memory will become "stale." There are two primary techniques for keeping the contents of the main memory consistent with that of the cache--(1) the write-through method and (2) the write-back or copy-back method. In the write-through method, on a cache write hit, data is written to the main memory immediately after or while data is written into the cache. This enables the contents of the main memory always to be valid and consistent with that of the cache. In the write-back method, on a cache write hit, the system writes data into the cache only and sets a "dirty bit" (or enters a "modified" state) which indicates that a data word has been written into the cache but not into the main memory. On a subsequent cache read miss, which requires a cache line to be replaced (filled) with new data from memory, a cache controller checks for a dirty bit before overwriting any line of data in the cache. If the dirty bit for the cache line is set, the cache controller writes the line of data out to main memory before loading the cache with new data.
A computer system can have more than one level of cache memory for a given address space. For example, in a two-level cache system, the "level one" (L1) cache is logically adjacent to the host processor. The second level (L2) cache is logically behind the first level cache, and other memory (which in this case can be referred to as tertiary memory), typically DRAM or SDRAM, is located logically behind the second level cache. When the host processor performs an access to an address in the memory address space, the first level is cache responds if possible. If the first level cache cannot respond (for example, because of an L1 cache miss), then the second level cache responds if possible. If the second level cache also cannot respond, then the access is made to the tertiary memory. The host processor does not need to know how many levels of caching are present in the system or indeed that any caching exists at all. Similarly, the first level cache does not need to know whether a second level of caching exists prior to the tertiary memory. Thus, to the CPU, the combination of both caches and tertiary memory is considered merely as a single main memory "structure". Similarly, to the L1 cache, the combination of the L2 cache and tertiary memory is considered simply as a single main memory structure. In fact, a third level (L3) of caching could be included behind the L2 cache, and the L2 cache would still consider the combination of L3 and subsequent memory as a single main memory structure.
The PowerPC.TM. 603 microprocessor, available from IBM and Motorola, is an example of a microprocessor which has an on-chip, two-way set associative cache memory. This cache is divided into a data cache and a separate instruction cache. The data cache on a PowerPC 603 is a write-back cache. The cache is actually programmable based on the address specified to follow a write-through or a write-back policy, but special precautions must be taken externally to the chip as long as even one line is able to follow a write-back policy as further explained below. Thus, as used herein, a "write-back cache" is a cache memory, any part of which can hold data which is inconsistent with that in the external memory subsystem.
In systems having multiple devices which share a common address space, a cache coherency protocol is implemented in order to provide the same image of memory to all such devices. Such a protocol allows synchronization and cooperative use of shared resources. Otherwise, multiple copies of a memory location, some containing stale values, could exist in a system and errors could result. One popular write-back cache coherency protocol is known as the MESI (modified/exclusive/shared/invalid) protocol. The MESI protocol is described in "Intel, Pentium Processor User's Manual", Vol. 1: "Pentium Processor Databook" (1993), incorporated herein by reference, especially at pp. 3-20 through 3-21. A superset of the MESI protocol, known as MOESI, is described in Thorson, "Multiprocessor Cache Coherency", Microprocessor Report, pp. 12-15 (Jun. 20, 1990), also incorporated by reference. In the MESI protocol, each cache data line is accompanied by a pair of bits which indicate the status of the line. Specifically, if a line is in state M, then it is "modified" (has been written to since it was retrieved from main memory). An M-state line can be accessed (read or written) by the CPU without sending a cycle out on an external bus to higher levels of the memory subsystem.
If a cache line is in state E ("exclusive"), then it is not "modified" (i.e. it contains the same data as subsequent levels of the memory subsystem). In shared cache systems, state E also indicates that the cache line is available in only one of the caches. The CPU can access (read or write) an E-state line without generating a bus cycle to higher levels of the memory subsystem, but when the CPU performs a write access to an E-state line, the line then becomes "modified" (state M).
A line in state S ("shared") may exist in more than one cache. A read access by the CPU to an S-state line will not generate bus activity, but a write access to an S-state line will cause a write-through cycle to higher levels of the memory subsystem in order to permit the sharing cache to potentially invalidate its own corresponding line. The write will also update the data in the data cache line.
A line in state I is invalid. It is not available in the cache. A read access by the CPU to an I-state line will generate a "cache miss" and may cause the cache to execute a line fill (fetch the entire line into the cache from higher levels of the memory subsystem). A write access by the CPU to an I-state line will cause the cache to execute a write-through cycle to higher levels of the memory subsystem.
The PowerPC 603 implements a cache coherency protocol which is a coherent subset of the MESI protocol omitting the shared (S) state. Since data cannot be shared, the PowerPC signals all cache line fills as if they were cache write misses (reads with intent to modify), thereby flushing the corresponding copies of the data in all caches external to the PowerPC prior to the PowerPC's cache line fill operation. Following the cache line fill, the PowerPC is the exclusive owner of the data and may write to it without a bus broadcast transaction (state E).
Computer system cache memories typically cache main memory data for the CPU. If the cache uses a write-back protocol, then frequently the cache memory will contain more current data than the corresponding lines in main memory. This poses a problem for other devices which share the same address space in the memory, because these devices do not know whether the main memory version is the most current version of the data. Similarly, for both write-back and write-through caches, even if the data in the cache is not modified with respect to that in memory, the CPU must be kept informed of write accesses to memory by external devices. Otherwise, the CPU would not know whether the cached version is the most current copy of the data. Cache controllers, therefore, typically support inquire cycles (also known as snoop cycles), in which a device essentially asks the cache memory to indicate whether it has a more current copy of the data.
In PowerPC-based systems, a device issues a snoop cycle by driving the snoop address onto the CPU bus and asserting the processor's TS and GBL control signals. The processor responds by asserting its ARTRY output if the specified data line is present in the internal cache and the specified cache line is in the M (modified) state. (If the specified data line is present in the internal cache but it is unmodified (state E), then the processor merely invalidates the line in the cache. Similarly, if the specified data line is present in the internal cache but the snoop cycle is for a write access to the entire line, then the processor merely invalidates the line in the cache. In either case, ARTRY is not asserted.) Thus, ARTRY, when asserted, indicates that the internal cache contains a more current copy of the data than is in main memory. The processor then automatically conducts a write-back cycle while the external device waits. By this process, therefore, the external device will be able to access the desired line in main memory without any further concern that the processor's internal cache contains a more current copy of the data.
The time required to perform the snoop cycle, however, is significant. This is a problem not only because of the CPU bus bandwidth occupied by snoop cycles, but also because of the delays they impose on memory accesses by the external device. In systems in which the external devices are performance-critical, such as in graphics coprocessor arrangements, the need to snoop every memory access can substantially impact performance.
One technique that has been used in the past to minimize the number of snoops required by an external device, is simply to designate parts of the memory address space as being dedicated to the external device. For example, in systems having a graphics coprocessor, an area of the memory address space may be designated the frame buffer and dedicated to the coprocessor. The coprocessor never needs to snoop the CPU's cache because only the coprocessor, and not the CPU, can read or write to the frame buffer. But this solution greatly limits the flexibility of the system: it may be most desirable, for example, for the CPU to render some parts of an image while the coprocessor renders other parts of the same image. Dedicating the frame buffer to the coprocessor precludes such flexibility. Moreover, this solution avoids the question of how to minimize snoops when an external device accesses shared regions of the memory address space; dedicating an area of memory exclusively to the external device renders it no longer shared.
Another technique to minimize snoops of a processor's internal cache, has been used only on high-end systems which include a second-level (L2) cache extend to the processor. Specifically, the system enforces a rule that data cannot be cached in the processor's internal cache, unless it is also cached in the L2 cache. In such a system, the external device first snoops the L2 cache, and then snoops the processor's internal cache only if there is an L2 cache hit. The device does not need to snoop the processor's internal cache if there is an L2 cache miss. But this solution is expensive in that it requires a second-level cache external to the processor.
Accordingly, a definite need continues to exist for an alternative mechanism for reducing the number of snoop cycles required to a processor structure having an internal cache memory.

Method and apparatus for managing snoop requests using snoop advisory cells


There is provided an organic light emitting display device capable of reducing power consumption by adjusting a voltage according to an input image and deterioration of the organic light emitting display device and a method of driving the same.

1. Field of the Invention
An embodiment of the present invention relates to an organic light emitting display device and a method of driving the same, and more particularly, to an organic light emitting display device capable of reducing power consumption by adjusting a voltage according to an input image and deterioration of the organic light emitting display device and a method of driving the same.
2. Description of the Related Art
Recently, various flat panel display devices (FPD) capable of reducing weight and volume that are disadvantages of cathode ray tubes (CRT) have been developed. The FPDs include liquid crystal display devices (LCD), field emission display devices (FED), plasma display panels (PDP), and organic light emitting display devices.
Among the FPDs, the organic light emitting display devices display images using organic light emitting diodes (OLED) that generate light by re-combination of electrons and holes. The organic light emitting display device has higher response speed and is driven with lower power consumption.
The contemporary organic light emitting display device includes a data driving unit for supplying data signals to data lines, a scan driving unit for sequentially supplying scan signals to scan lines, a pixel unit having pixels arranged at every intersections between the scan lines, and a timing controller for controlling operations of the data driving unit and the scan driving unit.
The pixels charge, when the scan signal are supplied, voltage corresponding to the data signals supplied through the data lines storage capacitors included in the respective pixels and supply current corresponding to the charged voltage to organic light emitting diodes to emit light of luminance corresponding to the data signals.
In the contemporary organic light emitting display device, an optimized level of the base power voltage of a shipped product is a first voltage but a second voltage is set to the level of the base power voltage by considering deterioration of the organic light emitting display device. Thus, additional power consumption occurs as much as a difference between the first voltage and the second voltage even before the organic light emitting display device is deteriorated. The contemporary organic light emitting display device supplies a third voltage as a level of the base power voltage by considering the full white pattern regardless of supplying the fourth voltage or the fifth voltage as a level of the base power voltage in a normal case. By doing so, there occurs an additional power consumption corresponding to a difference between the third voltage and the fourth voltage or the fifth voltage.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the described technology and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.

Organic light emitting display device and method of driving the same

Samsung-ro, Giheung-Gu, Yongin-si, Gyeonggi-Do


Semiconductor devices having redundant through-die vias (TDVs) and methods of fabricating the same are described. A substrate is provided having conductive interconnect formed on an active side thereof. Through die vias (TDVs) are formed in the substrate between a backside and the active side thereof. The TDVs include signal TDVs, redundant TDVs (i.e., redundant signal TDVs), and power supply TDVs. The signal TDVs are spaced apart from the redundant TDVs to form a pattern of TDV pairs. The power supply TDVs are interspersed among the TDV pairs. The conductive interconnect includes first signal conductors electrically coupling each of the signal TDVs to a respective one of the redundant TDVs defining a respective one of the TDV pairs.

As semiconductor technology has advanced, the amount and speed of logic available on an integrated circuit (IC) has increased more rapidly than the number and performance of input/output (I/O) connections. As a result, IC die stacking techniques have received renewed interest to address the interconnection bottleneck of high-performance systems. In stacked IC applications, two or more ICs are stacked vertically, and interconnections between them are made by wire bonding at chip periphery or by forming high aspect ratio through die vias (TDVs). There are several approaches for stacking ICs. Multiple silicon device layers can be grown epitaxially or fully processed ICs can be bonded for vertical integration.

Semiconductor devices having redundant through-die vias and methods of fabricating the same


An in-plane switching mode liquid crystal display device includes a plurality of gate and data lines on a substrate that cross each other to define a pixel region, a thin film transistor at a crossing of the plurality of gate and data lines, an organic insulating layer over the substrate including the thin film transistor, and having a step difference in the pixel region, common electrodes on the organic insulating layer above the data lines, and pixel electrodes positioned between the common electrodes.

1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an In-Plane Switching (IPS) mode liquid crystal display (LCD) device and a method of manufacturing the same.
2. Discussion of the Related Art
Demands for various display devices have increased as the information society has developed. Accordingly, many efforts have been made to research and develop various types of flat display devices, such as liquid crystal display (LCD), plasma display panel (PDP), electroluminescent display (ELD), and vacuum fluorescent display (VFD). Some types of flat display devices have already been used as displays in a variety of different applications. Among the various flat display devices, liquid crystal display (LCD) devices have been most widely used due to the advantageous characteristics of thin profile, light weight, and low power consumption. LCD devices have been provided as a substitute for a Cathode Ray Tube (CRT) in many applications. In addition, mobile type LCD devices, such as a display for a notebook computer, have been developed. Further, LCD devices can be used as computer monitors, televisions or other types of equipment that display video.
Various technical developments an research in LCD technology has been ongoing. However, the picture quality is still, in some respects, lacking as compared to other features and advantages of the LCD device. In order to use LCD devices in various fields as a general display, the key to developing LCD devices depends on whether LCD devices can implement a high quality picture, such as a high resolution and high luminance large-sized screen, while still maintaining light weight, thin profile, and low power consumption.
In general, an LCD device includes an LCD panel for displaying a picture image, and a driving part for applying a driving signal to the LCD panel. The LCD panel includes first and second glass substrates bonded to each other with a predetermined gap therebetween. A liquid crystal layer is injected into the gap between the first and second glass substrates.
The first glass substrate (TFT array substrate) includes a plurality of gate and data lines, a plurality of pixel electrodes, and a plurality of thin film transistors. The plurality of gate lines are formed on the first glass substrate at fixed intervals, and the plurality of data lines are formed perpendicular to the plurality of gate lines at fixed intervals. The plurality of pixel electrodes, arranged in a matrix-type configuration, are respectively formed in pixel regions defined by the plurality of gate and data lines that cross each other. The plurality of thin film transistors are switched according to signals from the gate lines to transmit signals of the data lines to the respective pixel electrodes.
The second glass substrate (color filter substrate) includes a black matrix layer that excludes light from regions except for the pixel regions of the first substrate. The second glass substrate also includes an R/G/B color filter layer for displaying various colors. Further, a common electrode can be positioned on the second glass substrate. However, in the case of an In-Plane switching mode LCD device, the common electrode is formed on the first glass substrate.
The gap between the first and second glass substrates is maintained by spacers when the first and second substrates are bonded to each other by a seal pattern having a liquid crystal injection inlet. The liquid crystal layer is formed using a liquid crystal injection method, in which the liquid crystal injection inlet is dipped into a container having liquid crystal while a vacuum state is maintained in the gap between the first and second glass substrates. That is, the liquid crystal is injected between the first and second substrates by an osmotic action. Subsequently, the liquid crystal injection inlet is sealed with a sealant.
A LCD device is driven according to the optical anisotropy and polarizability of liquid crystal. Liquid crystal molecules can impart directional characteristics on light because liquid crystal molecules have long and thin shapes. The directional characteristics of the liquid crystal molecules can be controlled by inducing electric field across the liquid crystal in the direction of an alignment direction for the liquid crystal molecules. That is, if the alignment direction of the liquid crystal molecules is controlled by the induced electric field, the direction of polarized light can be changed by the optical anisotropy of the liquid crystal to thereby display a picture image.
Liquid crystal is classified into positive (+) type liquid crystal having positive dielectric anisotropy and negative (−) type liquid crystal having negative dielectric anisotropy according to electrical characteristics of the liquid crystal. In the positive (+) type liquid crystal, a longitudinal (major) axis of a positive (+) liquid crystal molecule is in parallel to the electric field applied to the liquid crystal. Meanwhile, in the negative (−) type liquid crystal, a longitudinal (major) axis of a negative (−) liquid crystal molecule is perpendicular to the electric field applied to the liquid crystal.
FIG. 1 is an exploded perspective view illustrating a Twisted Nematic (TN) mode LCD device. As shown in FIG. 1, the TN mode LCD device includes a lower substrate 1 and an upper substrate 2 bonded to each other with a gap therebetween, and a liquid crystal layer 3 in the gap between the lower and upper substrates 1 and 2.
The lower substrate 1 includes a plurality of gate lines 4, a plurality of data lines 5, a plurality of pixel electrodes 6, and a plurality of thin film transistors T. The plurality of gate lines 4 are formed on the lower substrate 1 in one direction at fixed intervals and the plurality of data lines 5 are formed perpendicular to the plurality of gate lines 4 at fixed intervals to thereby define a plurality of pixel regions P. A plurality of pixel electrodes 6 are respectively formed in the pixel regions P defined by the plurality of gate and data lines 4 and 5 that cross each other. A plurality of thin film transistors T are respectively formed at crossings of the gate and data lines 4 and 5. Next, the upper substrate 2 includes a black matrix layer 7 that excludes light from regions except for the pixel regions P, R/G/B color filter layers 8 for displaying various colors, and a common electrode 9.
Each of the thin film transistors T include a gate electrode, a gate insulating layer (not shown), an active layer, a source electrode, and a drain electrode. The gate electrode projects from the gate line 4. The gate insulating layer (not shown) is formed over an entire surface of the lower substrate. The active layer is formed on the gate insulating layer above the gate electrode. The source electrode projects from the data line 5, and the drain electrode is formed opposite to the source electrode. The aforementioned pixel electrode 6 is formed of transparent conductive metal having great transmittance, such as indium-tin-oxide (ITO).
In the aforementioned LCD device, liquid crystal molecules of the liquid crystal layer 3 on the pixel electrode 6 are aligned as a result of a signal applied through the thin film transistor T. Light transmittance is controlled according to alignment of liquid crystal to thereby display a picture image. The liquid crystal molecules by driven by an electric field perpendicular to the lower and upper substrates using the common electrode 9 of the upper substrate 2. This method obtains great transmittance and high aperture ratio. Also, it is possible to prevent liquid crystal cells from being damaged by static electricity since the common electrode 9 of the upper substrate 2 serves as the ground. However, in the case of driving the liquid crystal molecules with an electric field that is perpendicular to the lower and upper substrates, it is difficult to obtain a wide viewing angle.
In order to overcome the narrow viewing angle problem of a Twisted Nematic (TN) mode LCD device, an In-Plane switching (IPS) mode LCD device has been proposed. Hereinafter, a related art IPS mode LCD device will be described with reference FIG. 2, FIG. 3A, FIG. 3B, FIG. 4A, FIG. 4B, FIG. 5 and FIG. 6. FIG. 2 is a cross-sectional view schematically illustrating the related art In-Plane switching mode LCD device. In the related art IPS mode LCD device, as shown in FIG. 2, a common electrode 13 and a pixel electrode 12 are formed on the same plane of a lower substrate 10. Then, the lower substrate 10 is bonded to an upper substrate 20 with a gap therebetween. A liquid crystal 3 is positioned between the lower and upper substrates 10 and 20. The liquid crystal 3 is driven by an electric field between the common electrode 13 and the pixel electrode 12 on the lower substrate 10.
FIG. 3A and FIG. 3B respectively illustrate the alignment direction of liquid crystal when a voltage is turned off and turned on in the related art In-Plane switching mode LCD device.
FIG. 3A illustrates the related art IPS mode LCD device when the voltage is turned off in that no electric field is applied in parallel to the lower and upper substrates between the common electrode 13 or the pixel electrode 12. Accordingly, there is no change in alignment of the liquid crystal 3. For example, liquid crystal molecules are basically twisted at 45° to a horizontal direction of the pixel electrode 12 and the common electrode 13.
FIG. 3B illustrates the related art IPS mode LCD device when the voltage is turned on in that an electric field is applied in parallel to the lower and upper substrates between the common electrode 13 and the pixel electrode 12. Accordingly, alignment of the liquid crystal 3 is changed. In more detail, the alignment of liquid crystal 3 is twisted more at 45° as compared to the alignment of liquid crystal when the voltage is turned off. In this state, the horizontal direction of the common and pixel electrodes 13 and 12 is identical to the twisted direction of liquid crystal.
As mentioned above, the related art IPS mode LCD device has the common electrode 13 and the pixel electrode 12 on the same plane. The related art IPS mode LCD device has the advantageous characteristic of as wide viewing angle. For example, along a front direction of the IPS mode LCD device, a viewer can have a viewing angle of 70° in all directions (i.e., lower, upper, left, and right directions). Furthermore, the related art IPS mode LCD device has simplified fabrication process steps, and reduced color shift. However, the related art IPS mode LCD device has the problems of low light transmittance and low aperture ratio since the common electrode 13 and the pixel electrode 12 are formed on the same substrate. Further, the related art IPS mode LCD device also has the problems of high driving voltages to improve response times, and the need to maintain a uniform cell gap due to the small misalignment margin of the cell gap. That is, the IPS mode LCD device has the aforementioned advantages and disadvantages as compared to the Twisted Nematic (TN) mode LCD device, whereby a user can select the mode of the LCD device according to a purpose.
FIG. 4A and FIG. 4B are perspective views illustrating operation of the IPS mode LCD device while respectively in the states of being turned off and turned on. FIG. 4A is a state when a voltage is not supplied to the pixel electrode 12 or the common electrode 13 such that the alignment direction 16 of the liquid crystal molecules is identical to the alignment direction of an initial alignment layer (not shown). Then, as shown in FIG. 4B, when the voltage is supplied to the pixel electrode 12 and the common electrode 13, the alignment direction 16 of the liquid crystal molecules is corresponding to an electric field application direction 17.
FIG. 5 is a plane view illustrating a unit pixel of the related art IPS mode LCD device. FIG. 6 is a cross-sectional view taken along lines I-I′ and II-II′ of FIG. 5. As shown in FIG. 5 and FIG. 6, the related art IPS mode LCD device includes a transparent lower substrate 60 having a plurality of gate lines 61 and data lines 64 crossing each other to define pixel regions, and a plurality of thin film transistors T respectively where the plurality of gate lines 61 and data lines 64 cross each other. Each of the thin film transistors T includes a gate electrode 61a protruding from the gate line 61, a gate insulating layer 62 over an entire surface of the lower substrate 60 including the gate electrode 61a, an active layer on the gate insulating layer 62 above the gate electrode 61a, a source electrode 64a protruding from the data line 64, and a drain electrode positioned at a predetermined interval from the source electrode 64a. Also, a common line 61b is formed in the same layer as the gate line 61. More particularly, the common line 61b is formed in parallel to the gate line 61 within the pixel region.
A passivation layer 65 is formed over the entire surface of the lower substrate 60 including the data line 64, and a contact hole 66 is formed to expose the drain electrode 64b. The passivation layer 65 is formed of silicon nitride. Then, a common electrode 67 and a pixel electrode 68 are alternately formed on the passivation layer 65 of the pixel region in parallel. The common electrode 67 is connected to the common line 61b through the contact hole 69, and the plurality of common electrodes 67 are formed in parallel to the data line 64 within one pixel region. The pixel electrode 68 is connected to the drain electrode 64b of the thin film transistor through the contact hole 66. Both the common electrode 67 and the pixel electrode 68 are formed of transparent conductive layers.
Although not shown, an upper substrate is formed opposite to the lower substrate. The upper substrate includes color filter layers corresponding to the pixel regions of the lower substrate, and a black matrix layer for preventing light leakage on the portions except the pixel regions. At this time, the black matrix layer is formed corresponding to the portions including the gate line 61, the data line 64, the common electrode 67 adjacent to the data line 64, and the thin film transistor. Also, liquid crystal molecules positioned between the common electrode 67 and the pixel electrode 68 are aligned in the same direction as that of an electric field parallel to the substrates between the common electrode 67 and the pixel electrode 68, thereby forming one domain.
As mentioned above, the common electrode 67 and the pixel electrode 68 are formed of transparent conductive layers. Luminance is improved by using the transparent conductive layers. However, when the black matrix layer is formed on the data line 64 and the adjacent portions, it is necessary to take a margin for bonding the lower and upper substrate into consideration, thereby complicating manufacturing process steps. Also, depending on the resolution, a bonding margin can cause a decrease in luminance at the periphery of the data line 64. In other words, the black matrix layer is formed on the corresponding portion between the common electrodes 67 adjacent to the data line 64 as well as the data line 64, thereby causing a decrease of the aperture ratio and the luminance by the bonding margin.
In addition, the passivation layer is formed of silicon nitride having a thickness of approximately 0.3 μm. Such a silicon nitride thickness may result in cross-talk between the data line and the common electrode, and a deterioration of the picture quality by parasitic capacitance may also occur. Accordingly, in order to prevent cross-talk problem and problems of parasitic capacitance, an organic insulating layer having a low dielectric constant is formed over the entire surface of the lower substrate instead of a silicon nitride passivation layer. However, such an an organic insulating layer may cause the problem of decreased light transmission efficiency due to the thick organic insulating layer. That is, while the silicon nitride layer is formed having a thickness of approximately 0.3 μm, the organic insulating layer is formed having a thickness of approximately 3 μm, so that the light transmission efficiency of the pixel region is lowered to approximately 92% by approximately a 8% light transmission efficiency decrease.

In-plane switching mode liquid crystal display device and method of manufacturing the same


The invention provides universal chloroplast integration and expression vectors which are competent to stably transform and integrate genes of interest into chloroplast genome of multiple species of plants. Transformed plants and their progeny are provided. Monocotyledonous and dicotyledonous plants are transformed which have never been transformed heretofore. Plants transformed with a synthetic gene express valuable biodegradable protein-based polymers (PBPs). Transformed plants produce high value molecules. Resistance is provided to agricultural crops against the major classes of chemical herbicides. Herbicide resistance is used as a lethal selectable marker for chloroplast transformation. The transformed plants are capable of expressing in addition to the targeted trait, a desirable, secondary non-targeted trait. Insect resistance is provided to transformed plants, both against insects that are susceptible to Bt toxins and against insects that have developed resistance to Bt toxins.

Advantages of Chloroplast Transformation Over Nuclear Transformation. The attractiveness of transformation of the chloroplast genome over transformation of the nuclear genome is attributable to the serious risks resulting from the latter. One common concern is the escape of foreign genes through pollen dispersal from transgenic crop plants to their weedy relatives. It has been demonstrated that transgenic pollen will deliver foreign (transgenic) genes to other sexually-compatible plants (detected by marker gene prevalence in progeny harvested from non-transgenic plants grown in surrounding area). For Example, dispersal of pollen from a central test plot containing transgenic cotton plants to surrounding non-transgenic plants has been observed at varying distances in different directions. (Lewellyn and Fitt, 1996); (Umbeck, P. F., et al., 1991). In addition, the frequencies of marker genes in wild sunflowers averaged about 28 to 38%; in wild strawberries growing within 50 meters of a strawberry field, more than 50% of the wild plants contained marker genes from cultivated strawberries. (King, J., 1996).
The escape of foreign genes through pollen is especially a serious environmental concern, in the case of herbicide resistance genes, because of the high rates of gene flow from crops to wild relatives. The concern is that gene escape from transgenic crops to their weedy relatives will create super weeds. In rice (Oryza sativa), gene flow from cultivated varieties to wild relatives has been noted, into O. perennis (Barrett, 1983) and red rice (O. sativa; Langevin et al., 1990). In the southern US, red rice has become a major weed because herbicides that kill it also kills cultivated rice. Decreased prices are paid for cultivated rice contaminated with red rice. Some researchers have introduced the bar gene conferring resistance to glufosinate (Liberty) into cultivated rice to combat this weed (Oard et al., 1996; Sankula et al., 1996). However, due to sexual compatibility, introduction of a nuclear-expressed gene will allow transmission of that resistance trait into red rice via pollen.
Similarly, transgenic oil seed rape, genetically engineered for herbicide resistance outcrossed with a weedy relative, Brassica campestris (field mustard) and conferred herbicide resistance even in the first back-cross generation under field conditions. (Mikkelson, T. R., et al., 1996).
Maternal inheritance of introduced genes prevents gene escape through pollen. Engineering foreign genes through chloroplast genomes (which are maternally inherited for most of the crops) is a solution to this problem. Also, the target enzymes or proteins for most herbicides (e.g. amino acid/fatty acid biosynthetic pathways or photosynthesis) are compartmentalized within the chloroplast. Another important advantage of chloroplast transformation is the higher levels of foreign gene expression due to a very high copy number (5000–10,000) of chloroplast genomes in plant cells. Because the transcriptional and translational machinery of the chloroplast is prokaryotic in nature, herbicide resistant genes of bacterial origin can be expressed at extraordinarily high levels in chloroplasts.
Transformation of the Chloroplast Genome. Early investigations on chloroplast transformation focused on the development of in organello systems using intact chloroplasts capable of efficient and prolonged transcription and translation (Daniell and Rebeiz, 1982; Daniell et al., 1983) and expression of foreign genes in isolated chloroplasts (Daniell and McFadden, 1987). These experiments were done under the premise that it was possible to introduce isolated intact chloroplasts into protoplasts and regenerate transgenic plants (Carlson, 1973). The discovery of the gene gun as a transformation device opened the possibility of direct plastid transformation in plants (Daniell, 1993). Transient expression of foreign genes in plastids of dicots (Daniell et al., 1990; Ye et al., 1990), monocots (Daniell et al., 1991), prolonged foreign gene expression using autonomously replicating chloroplast expression vectors (Daniell et al., 1990) and stable integration of a selectable marker into the tobacco chloroplast genome (Svab and Maliga, 1993) were accomplished using the gene gun. Tobacco plants resistant to certain insects were obtained by integrating the cryIAc gene into the tobacco chloroplast genome (McBride et al., 1995; U.S. Pat. No. 5,451,513, incorporated herein by reference). Stable plastid transformation of higher plants has been accomplished so far only in tobacco.Prior Studies on the Chloroplast Genome. To date, stable integration of a foreign gene into the chloroplast genome of a higher plant has been reported only in tobacco. This was achieved with a vector which was specific for tobacco and which was derived from the tobacco chloroplast genome, that is, the vector contained a sequence homologous only to the tobacco chloroplast genome and which is not highly conserved in the chloroplast genomes of other plants. Such vector is unsuitable for stably transforming plant species other than tobacco. The only published report of foreign gene expression in a plant species other than tobacco is that of wheat leaves and embryos (Daniell et al., 1991), but stable integration was not accomplished. Stable integration of a foreign gene into the chloroplast genome of a monocotyledonous plant has never been reported. At least in cereals (monocots), previously developed transformation/regeneration protocols may not be amenable to plastid transformation due to inherent inefficiencies within those systems. Also, sequential/serial selections (repeated selections), deemed important for achieving homoplasmy (Daniell, 1997), may not be feasible using those regeneration systems employed. Recent development of unique corn (Rudraswamy, 1997) and rice (unpublished) transformation/regeneration protocols have the potential to exhibit substantially increased efficiencies and allow more than one round of selection during regeneration.
Maliga et al. in U.S. Pat. No. 5,451,513 and Svab et al., 1990 propose a transformation of the plastid genome of tobacco by a non-lethal selection technique which employs plastid DNA encoding a non-lethal selectable phenotype. According to Maliga et al. a non-lethal selection is absolutely essential for obtaining transplastgenic lines.
Unlike the Maliga et al. technique, the method of the invention provides a selection which is lethal to all non-transformed plants, but for tobacco. Only the transformed plants survive and continue to grow. This lethal selection takes place with virtually all antibiotics, including spectinomycin and streptomycin in a medium containing the antibiotic in a concentration of 500–1,000 μg/ml. Similar conditions were shown to be non-lethal for tobacco by Maliga et al. Moreover, unlike the technique of Maliga et al., in accordance with the invention, transformation to homoplasmy can be achieved even in the first round of selection.
In European Patent Application No. 0 251 654, Cannon et al. describe transposon-mediated chloroplast transformation of tobacco for instance, using the bacterial transposon Tn5. The vector containing the transposon is targeted at a chromosomal region known to be a "transcriptionally silent" region in order to preserve the transcriptional integrity of the native genes. Such a transcriptionally silent region is identified to be located between two known divergent promoters of chloroplast genes, e.g. the promoters for the genes for the chloroplast large subunit of ribulose bisphosphate carboxylate (RbcL, "LS RuBisCo") and for β-ATPase (atpB). These promoters transcribe the genes in opposite directions away from the silent region of the chromosome. No transcription terminator is provided in the expression vector of Cannon et al., such terminator regions are known to be absolutely essential for gene expression in plastids. Finally, no stable chloroplast transformation is shown to be accomplished by Cannon et al.
The invention described herein has several distinguishing features over Cannon et al. The invention teaches stable transformation transmittable to the progeny. The integration is not directed into a transcriptionally inactive region of the chloroplast chromosome. The invention integrates a cassette (which contains a transcription terminator as described further hereinafter) into a transcriptionally active region of the chloroplast genome. Promoters controls the expression of one or more genes. Unlike Cannon et al. no transposon is involved in the transformation of the chloroplast in accordance with the invention.
In NATO Asi Series, Daniell et al., 1994 report engineering insect resistance via chloroplast genomes showing the expression of CryIIA protein in plants to control insects. McBride et al, 1995, and U.S. Pat. No. 5,545,818 (1996), confirm report of Daniell et al and show the expression of Bacillus thuringiensis CRYIAc protein into plant plastids. The vectors reported by McBride are designed to introduce the construct only into the tobacco chloroplast genome.
The Need for a Vector to Transform a Variety of Plants. It is evident from the state of the art that an important need exists for a chloroplast integration and expression vector for transforming, preferably stably, the chloroplast genomes of many different species of plants. Such a "universal vector" would permit the transformation of the chloroplast genome of a selected target plant with a heterologous (foreign) DNA coding sequence and eliminate the need to construct vectors which each one is specifically suited to transform the chloroplast genome of the particular plant species which is to be transformed.
The problem to construct such a universal vector competent to transform different plants has to the knowledge of the inventor, not yet been solved.
Prior Art Concepts of the Intergenic Spacer Region. While the nucleotide sequence of coding regions of the genome, including the chloroplast genome, are often conserved between species, in contrast the sequences flanking functional genes, i.e. the spacer regions between coding regions typically are not conserved. The accepted dogma for lack of conservation, and thus the low degree of homology between species of spacer regions, is that the spacer regions typically do not perform essential functions. Therefore, there is little, if any, selective pressure to conserve the sequence of spacer regions between species. The sequence of the spacer regions may be altered without undesirable effects.
Stummann et al., 1988, disclose that the gene order of the ribosomal RNA operon of the chloroplast genome is the same between different species of plants, including tobacco, maize, and a liverwort, Marchantia, and that the coding sequences of this operon are highly homologous. Stummann also discloses that the interspecies homology of the operon is less than the interspecies homology of the gene coding regions. This is consistent with the lack of conservation of spacer regions; and suggests that the interspecies homology of spacer regions in the ribosomal RNA operon is relatively low.
The invention, contrary to the dogma of lack of conservation of the spacer regions, uses spacer regions that are highly conserved between different plants to construct vectors competent to transform a variety of plants.

Universal chloroplast integration and expression vectors, transformed plants and products thereof


The present invention is directed to a breastpump that can be operated to generate milk expression sequences or curves with some irregularity or randomness in the course of a session.

1. Field of the Application
The invention relates generally to breastpumps for drawing breastmilk, and particularly to a new way to operate a breastpump, such as a motorized, electrically driven breastpump, to better simulate an infant during breastfeeding.
2. Description of the Related Art
Breastpumps for use by nursing mothers are well known. They allow the nursing woman to express the breastmilk as necessary or convenient, and further provide collection of the breastmilk for later use. For some mothers, breastpumps may be a necessity, such as when the mother is away from the child (as at work), the child has suckling problems, or if the mother has problems with excessive or deficient milk production, or soreness, deformation or injury of the mammilla.
Historically, electrically driven motorized breastpumps have been made with a single type of "cycle" for a given pump. That is, the driving mechanism for generating the vacuum (negative pressure) to be applied at the breast is geared to a particular sequence, or curve, of negative pressure increase (i.e., increasing suction), and then release. This is often aimed at reproducing in some sense the suckling action of an infant, for instance. Breastpumping can cover a range of different conditions, however, such as where the mother's nipples are sore for some reason, there is a state of significant engorgement, some nipple stimulation may be particularly desired, let-down and relaxation may be of particular interest, it may be desired to increase milk production, and so on.
Some breastpumps have provided the user with the ability to vary the amount of peak vacuum being applied, as well as the speed of the pumping action (i.e., number of cycles per minute, or frequency). The basic "curve" or sequence remains fixed, however, and the user must adapt as best she can to making variations within that particular curve built into the machine, which typically has been generalized for the overall population of users. FIG. 1 shows such a prior art sequence that yields a simple smooth curve between a maximum vacuum and ambient conditions (negative pressure is along the y-axis (in millimeters of mercury) and time (in seconds) along the x-axis). Note how the cycle depicted repeats itself (here, every 1.25 seconds).
The SYMPHONY breastpump by Medela, Inc., which is the subject matter of U.S. Pat. No. 6,547,756, introduced both a breastpump that can be programmed to generate a plurality of differing milk expression sequences or curves, as well as the ability to now generate a sequence that had special inflections, or modifications, that differed from a smooth curve. In FIG. 2, which is the Superior program, note how the maximum negative pressure peak (P1) is followed by a slight pause (P2), thereby yielding a curve shape that is different from that of the standard curve of FIG. 1. Although providing a number of choices for the mother in the way of different shaped curves, each of these programs is predictable and regular, i.e., the cycle or sequence repeats itself (at least while that particular sequence is in operation, since a plurality of different sequences may be used in a session, e.g., letdown, then an expression sequence.
This type of regularity, however, is not presented by an infant when breastfeeding. During breastfeeding, an infant does not suck in a regular repeatable pattern, but rather pauses at times, and may further change the level of force applied (e.g., suction) and even the rate in rapid fashion. It is therefore the consideration of this invention to better simulate an infant during breastfeeding by providing a breastpump that can be operated to generate milk expression sequences or curves with some irregularity or randomness therein.

Breastpump with irregular milk expression sequences