An option setting device and method is provided for use on a computer mother-board for providing various user-defined settings to the motherboard. The motherboard includes a CPU, a chip set coupled to the CPU, a clock generator coupled to the chip set, a delay circuit coupled to the chip set, a first latching circuit coupled to the chip set, and a reset circuit coupled to the delay circuit. After the motherboard is power on, the CPU transfers a first setting via the chip set to the first latching circuit so as to allow the first setting to be latched in the first latching circuit, and meanwhile triggers the delay circuit to start counting time. The delay circuit outputs a trigger signal to the reset circuit after a preset time, causing the reset circuit to restart the motherboard. After the motherboard is restarted, the chip set fetches the first setting from the first latching circuit so as to be set accordingly. In the case of the motherboard further having a voltage regulator, the option setting device and method further utilizes a second latching circuit for latching a second setting from the CPU and then transferring the latched setting to the voltage regulator to cause the voltage regulator to output a voltage accordingly.

1. Field of the Invention
This invention relates to computer motherboards, and more particularly, to an option setting device and method for use on a computer motherboard to provide various settings to the computer motherboard through software means instead of jumpers, thus allowing the computer motherboard to be more easily manufactured and used.
2. Description of Related Art
IBM-compatible personal computers (PC) are the most popular computer systems around the world. Earlier IBM-compatible PCs were constructed in compliance with the PC/XT and PC/AT standards. With technologies becoming more sophisticated and diversified, however, present computer motherboards are constructed in compliance with a great variety of standards. For instance, earlier CPUs were typically 4.77 MHz (megahertz) in speed, but today's high-end CPUs run at more than 300 MHz. Moreover, earlier CPUs were driven by a system voltage of 5 V (volt), but today's CPUs are driven by a system voltage of 3 V or even lower.
For compatibility reasons, many manufactures integrate the various standards on a single motherboard and provide jumper means (referred to as an option setting device in this specification) to allow the user to select the desired options. For example, the option setting device may allow the user to choose one frequency from 133 MHz, 166 MHz, 200 MHz, and 233 MHz as the clock rate to drive the CPU. Further, the option setting device may allow the user to choose between internal and external clock rates ad for the CPU and choose one voltage from 3.3 V and 2.8 V as the system voltage to drive the CPU. Beside the CPU, the motherboard may include various other components, such as a PCI (Peripheral Component Interconnect) interface, an AGP (Accelerated Graphics Port) interface, and a memory interface, for the installation of various expansion cards on the motherboard. These interfaces may run on various different clock rates and voltages that the user is required to set before operation.
In view of the foregoing requirements, a conventional computer motherboard is typically provided with a number of jumpers to allow the user to choose between all the available options. When there are too many available options, the motherboard may include such a great number of jumpers that it would be very difficult for ordinary users to implement the settings quickly and correctly. In the event of wrong settings, the computer motherboard may be inoperable or even suffer from system crash. It is therefore highly desirable to reduce or even entirely eliminate the jumpers and instead use software means to implement the settings.
FIG. 1 is a schematic system diagram showing the use of a conventional jumper-sharing scheme on a computer motherboard to help reduce the number of jumpers. As shown, the computer motherboard utilizing the jumper sharing scheme includes a clock generator 120 and a chip set 130, both of which are designed to share the same set of jumpers--a first jumper 111, a second jumper 112, and a third jumper 113. The clock generator 120 is used to generate a system clock signal for driving the motherboard, with the clock rate being dependent on the particular combination of the logic states at the FS1, FS2, and FS3 ports that is set via the three jumpers 111, 112, 113 to either the system voltage V.sub.cc (the high-voltage logic state) or the ground (the low-voltage logic state).
Moreover, the chip set 130 can be used to set the clock rates respectively used to clock the CPU (not shown), the AGP interface (not shown), and the PCI interface (not shown), which are dependent on the particular combination of the logic states at the HA1, HA2, HA3 ports that are also set via the three jumpers 111, 112, 113 to either the system voltage V.sub.cc or the ground. The clock generator 120 and the chip set 130 can share the same set of jumpers 111, 112, 113 because the clock rates for the CPU, the AGP interface, and the PCI interface are related to the system clock rate generated by the clock generator 120.
Therefore, the jumper-sharing scheme can help reduce the number of required jumpers on the computer motherboard. Since the HA1, HA2, HA3 ports of the chip set 130 may not be set to the same logic states as the FS1, FS2, FS3 ports of the clock generator 120, an adapting circuit composed of three tri-state buffers 141, 142, 143 and two inverters 151, 152 is provided between the jumpers 111, 112, 113 and the chip set 130 to alter the logic states to the ones desired for the chip set 130.
It is to be noted that the adapting circuit shown in FIG. 1 is only an example; the actual configuration is dependent on the specifications of the integrated circuit being used as the chip set 130. Furthermore, the chip set 130 is provided with a REST port, which is connected to receive a DRST signal. The DRST signal is also used to control the tri-state buffers 141, 142, 143 in such a manner that when it is switched to a first logic state, for example a low-voltage logic state, it switches the buffers 141, 142, 143 to the conducting state, thereby allowing the transfer of the logic voltage states set by the three jumpers 111, 112, 113 respectively to the HA1, HA2, HA3 ports of the chip set 130; and when switched to a second logic state, for example a high-voltage logic state, it switches the buffers 141, 142, 143 to non-conducting state. In the latter condition, the HA1, HA2, HA3 ports of the chip set 130 can be used as output ports for address signals.
The foregoing jumper sharing scheme allows the clock generator 120 and the chip set 130 to share the same set of jumpers 111, 112, 113 to receive the user-defined settings. One drawback to this scheme, however, is that when other makes of devices with different specifications are used as the clock generator and the chip set, the adapting circuit (i.e., the buffers 141, 142, 143 and the inverters 151, 152) between the jumpers 111, 112, 113 and the chip set 130 may have to be redesigned in compliance with the new specifications of the clock generator and the chip set.
The manufacture of the motherboard would be therefore quite cost-ineffective. Moreover, if an advanced device having a software frequency programming capability is used as the clock generator 120, the scheme of using jumpers to set options would not allow such a clock generator to be fully utilized in its advanced functionality.
As a summary, the prior art of FIG. 1 has the following disadvantages in manufacture and utilization.
(1) First, the prior art is quite cost-ineffective for the suppliers to manufacture, in that when another make of clock generator and chip set are used, the adapting circuit may have to be totally redesigned so as to allow the new clock generator and the new chip set to share the same set of jumpers.
(2) Second, the scheme of using jumpers to set an advanced clock generator having a software frequency programming capability would not allow the clock generator to be fully utilized in its advanced functionality.
(3) Third, the scheme of using jumpers to provide various settings to the motherboard would be user-unfriendly to most computer users and could easily result in wrong settings.

Option setting device and method for providing various settings through software means to a computer motherboard


A nonvolatile semiconductor memory which is capable of a high degree of integration and can conduct the writing of analog data at high speed and with a high degree of accuracy.. The memory device comprises two or more semiconductor devices comprising a first MOS transistor having a first floating gate which is electrically insulated, a first electrode which is capacitively coupled with the first floating gate, a second electrode provided with the first floating gate via a tunnel junction, and a third electrode connected to the second electrode via a switch; the present invention is further provided with a fourth electrode connected commonly with the third electrodes of the semiconductor devices, a fifth electrode connected commonly with the source electrodes of the first MOS transistors, a sixth electrode which is capacitively coupled with the fourth electrode, and a seventh electrode which is connected with the fourth electrode via a switch.

1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and in particular, relates to a memory device which is capable of storing analog or many-valued data at high speed and with a high degree of accuracy.
2. Description of the Related Art
In recent years, in concert with the development in computer technology, the progress in the field of data processing technology has been truly remarkable. However, when attempts were made to realize the flexible type of data processing conducted by human beings, it was almost impossible to obtain the results of such calculations in real time using present computers. The reasons advanced for this are that the data which human beings process in the course of their daily lives are analog data, so that there is firstly an enormous amount of such data, and moreover, these data are inexact and vague. It is thus a problem in present data processing systems that the extremely redundant analog data are all converted into digital values, and rigorous digital operations are conducted one by one.
An example of this is image data. For example, if one screen is incorporated into a 500.times.500 two dimensional array, then the total number of pixels is 250,000, and when the strength of the three colors red, green, and blue for each pixel is expressed in terms of eight bits, then the amount of data in one stationary image reaches 750,000 bits. In moving images, the amount of image data increases with time. Even if a present day supercomputer is used, it is impossible to manipulate the large amount of (1)/(0) data and conduct picture recognition and understanding in real time.
On the other hand, attempts have been made to realize data processing approximating that of human beings by accepting real world data, which are analog values, in an unchanged form and conducting calculations and processing on these analog values, in order to overcome the problems described above. As a result, a number of memory devices have been invented.
As one of these devices, the present inventors have proposed, in Japanese Patent Application No. Hei 7-2944, a memory device which is capable of writing desired analog values using simple circuitry such as that shown in FIG. 9 (title of the invention: Nonvolatile semiconductor Memory, date of application: Jan. 11, 1995). First an explanation of the cell of this technology will be made.
Reference 901 indicates an NMOS transistor, while reference 902 indicates a floating gate formed from, for example, N.sup.+ polysilicon; this controls the ON and OFF state of NMOS 901. NMOS drain 903 is connected to power source line 904, while source 905 is connected to an external capacity load 906; the structure is such that the circuit operates as a source follower circuit and reads out a potential V.sub.FG of the floating gate 902 to the exterior as V.sub.OUT. Reference 907 indicates an electrode which is capacitively coupled with floating gate 902; in this example, it is grounded. The capacitive coupling coefficient thereof is represented by C.sub.1. Reference 908 indicates a charge transfer electrode; it is connected with the floating gate via a tunnel junction 909 which is an oxide film of approximately 10 nm. The capacitance of this tunnel junction 909 is represented by C.sub.2. Charge transfer electrode 908 is connected to writing high voltage application electrode 911 via a capacitance 910 (the size thereof is represented by C.sub.3). Reference 912 indicates an NMOS transistor; the ON and OFF state thereof is controlled by the output line 913 of the inverter. NMOS transistor 914 serves to connect the input 915 of a control circuit constructed using an inverter to a memory cell. The input 915 of the control circuit is capacitively coupled with input of inverter 916, and the input of inverter 916 and output 917 are connected via NMOS transistor 918. Output 917 controls the ON and OFF state of NMOS transistor 912 via a further stage inverter.
The readout principle is simple; NMOS 914 is placed in an OFF state, and the memory cell is cut off from the control circuit, and transistor 901 is then conducts a source follower operation in the state in which electrode 911 is grounded, and the contents of the floating gate are read out as an analog value.
The writing principle will next be explained. During writing, after a reference value is first inputted into input 915 of the control circuit, NMOS transistor 918 is first turned ON and is then turned OFF, and the reference value is stored in the input portion of inverter 916, which has been placed in a floating state, as a charge, and next, when the reference value is inputted into the control circuit, the control circuit outputs the power source voltage to the output line 913. This reference value represents the addition of an offset voltage to the voltage of the data which are to be written, and since the offset voltage has a value particular to each circuit, the reference value is easy to determine.
Next, NMOS 914 is placed in an ON state so that the control circuit may monitor the output of the source follower. After this, a high voltage of approximately 20 V is applied to electrode 911, a strong electric field is produced in the tunnel junction 909, and a Fowler-Nordheim current is caused to flow. The electrons are drawn from the floating gate and writing commences, and the voltage of the floating gate during this writing is inputted into the control circuit via transistor 901 during the source follower operation. When the output of the source follower has become equal to the reference value, the power source voltage is outputted to the output line of the control circuit and transistor 912, which was in an OFF state, is allowed to conduct. When this is done, electrode 908 is discharged, the strong electric field generated in tunnel junction 909 disappears, and writing is completed. At this time, the voltage of the object data is written into the floating gate.
Furthermore, a variety of circuit structures are employed as the control circuit, and only one example thereof is discussed here.
FIG. 10 is a circuit diagram showing a plurality of such cells arranged so as to form an actual memory. The circuit shown in FIG. 9 is employed in an unchanged manner as the control circuit. Of course, other circuits maybe employed in some cases.
The reason that a plurality of cells need to be arranged in this way is so that writing may be conducted in such a manner that only the cell into which writing is to be conducted is selected. References 1001, 1002, and 1003 are writing high voltage application electrodes of the cells, respectively, while references 1004, 1005, and 1006 are NMOS transistors used for reading selection. In writing selection, a high voltage is applied only to the writing voltage application electrode of the cell into which writing is to be conducted, while the electrodes of other cells are set to the ground potential, and only the reading selection transistor of the cell into which writing is conducted is placed in an ON state, so that the control circuit may monitor only the contents of the cell into which writing is to be conducted. By proceeding in this manner, it is possible to cause a tunnel current to flow only in the cell in which writing is to be conducted, and it is possible to read out the state of only that cell into which writing is conducted to the control circuit.
This memory realizes accurate writing with simple control circuitry; in addition, there is sufficient selectively in writing and reading, although there is a problem in that the degree of integration does not increase.
The reason for this is as given below.
C.sub.2 represents the capacitance formed in the tunnel oxide film and since an extremely thin oxide film is employed, although this capacitance becomes rather large, it is necessary to set C.sub.1 and C.sub.3 so as to be larger than C.sub.2. The reasons that the design must be accomplished in this manner are as follows:
(1) In order to apply a large voltage to C.sub.2, it is necessary that C.sub.2 be shown to be small in comparison with C.sub.3 and C.sub.1 ; PA1 (2) C.sub.1 must be made large in comparison with C.sub.2 and C.sub.3 in order to suppress the rise in voltage in the floating gate resulting from capacitive coupling when a high voltage is applied during writing; PA1 (3) It is necessary to set the value of C.sub.3 so as to be considerably larger than the sum of C.sub.1 and C.sub.2 in order to reduce the voltage drop across C.sub.2 resulting from the movement of charge during writing. As an example, appropriate examples are C.sub.1 :C.sub.2 : C.sub.3 =5:1: 25. At this time, the size of the tunnel oxide film is set to 1.5 .mu.m on a side and the thickness thereof is set to 10 nm, and if C.sub.1 is formed between the substrate and the first polysilicon layer, then the thickness of the oxide film between these is 50 nm, and the area is 7 .mu.m.sup.2, while 16 .mu.m.sup.2 is necessary for C.sub.3. In a structure in which this type of conventional cell is employed, a large capacitance load such as C.sub.3 is provided for each cell as shown in FIG. 10 and this is undesirable. It is clear that as a result of this capacitance alone, the size is not different from present DRAM or EEPROM, so that the degree of integration does not increase.
Furthermore, attempts have been made to omit output selection transistors such as 1004, 1005, and 1006 in order to further reduce the number of elements. At this time, when power sources 1007, 1008, and 1009 are all in operation, output line 1010 is set to the maximum value maintained by the floating gate at all times, and selectivity is lost with respect to reading and with respect to the cell which is monitored during writing. Furthermore, if only the power line of the cell which is to be operated is set to the power source voltage, and only one cell is read out, as a result of the voltage rise of voltage line 1010, the power source side of cells which are not to be read out becomes the source, and in this state, they enter an ON state, and this is undesirable. The source follower transistors of the cells which are to be read out also include these and charging is necessary, so that this leads to a decline in the read out speed.
Accordingly, stratagems are necessary to reduce the number of elements.
FIG. 11 shows a circuit in which the outputs of the cell group shown in FIG. 10 are connected one by one to source follower buffer circuits having a CMOS structure. During actual use as a memory, it is necessary that the memory data be conveyed as far as the operating portions, so that the source follower of the cells must drive comparatively long wiring. For this reason, it was necessary to connect buffer circuits such as those conventionally employed to the memory output portions, as shown by 1101, 1102, and 1103; however, the attachment of buffer circuits to each of the memory outputs further increases the number of elements required for a memory cell, and thus an increase in the degree of integration can be anticipated. Furthermore, as a result of variation in the buffer, or the thermal characteristics of the MOS threshold, there were cases in which an accurate readout could not be conducted.
The present invention was created in light of the above circumstances; it has as an object thereof to provide a nonvolatile semiconductor memory which is capable of a high degree of integration and can conduct the writing of analog data at high speed and with a high degree of accuracy.

Nonvolatile semiconductor memory device capable of storing analog or many-valued data at high speed and with a high degree of accuracy


A method from discriminating between spurious and genuine surges in a gas turbine engine is provided which includes the steps of receiving an engine speed signal over a global engine surge investigation region that includes a plurality of operating regions (e.g. speed bands) in which engine surges can occur, identifying a specific operating region in which an engine surge event occurs, incrementing a surge counter corresponding to the operating region in which the engine surge event occurred, identifying the operating regions in which no engine surge event occurred, decrementing a surge counter corresponding to each operating region in which no engine surge event occurred; enabling a surge avoidance signal when the magnitude of the surge counter for a particular operating region has reached a predetermined value; and adapting an engine acceleration schedule in the operating region corresponds to the surge avoidance signal.

1. Field of the Invention
The subject invention relates to a control system for use with aircraft gas turbine engines, and more particularly to, a method of discriminating between spurious engine surges caused by, for example, disturbances to the inlet gas stream and genuine engine surges caused by, for example, the deterioration of the core engine or the malfunction of a critical engine component.
2. Background of the Related Art
The occurrence of a surge event in a gas turbine engine is often a precursor to a stall condition. Several techniques have been developed for detecting whether a surge event has occurred. A first technique compares engine control parameters with actual engine parameters. By example, the existence of a sustained difference between the demanded rate of change of engine speed and the actual rate of change of engine speed may indicate a surge condition. Another technique uses an engine signature to detect an engine surge, and relies primarily on a measurement of combustor burner pressure. In particular, this technique relies on sensing a transient spike in combustor burner pressure.
State-of-the-art adaptive digital control systems for helicopter gas turbine engines are configured to modify or adapt the baseline engine acceleration schedules following an engine surge event in an effort to compensate for and avoid future engine surges. However, these modifications are not permanently stored in computer memory because the surge event may have been spurious rather than genuine. If the surge event was spurious, permanently modifying the acceleration schedule would result in an reduction in engine performance over the present operating period, but more importantly would unnecessarily degrade engine performance during subsequent operating periods until maintenance is performed on the engine.
Therefore, in prior art control systems, which are not capable of making distinctions between spurious and true surge events, the adaptation of the acceleration schedule is stored in volatile computer memory (RAM) and the schedule is returned to the baseline values prior to the beginning of the next operating period.
Spurious engine surges can result from the ingestion of munitions gases, rocket exhaust gases or engine exhaust gases causing a distortion in the inlet air flow to the engine. Generally, spurious surge events are not repetitive and occur randomly. Genuine engine surges, on the other hand, often result from the deterioration of the core engine or malfunction of an engine component such as an inlet guide vane or bleed valve, and require repair or removal of the engine. Moreover, genuine surge events typically repeat within specific operating ranges, such as gas generator speed.
Often, after an initial engine surge event and subsequent modification of the baseline acceleration schedules of the engine, the remainder of the flight is without incident. However, since the acceleration schedule modifications are not stored in the permanent computer memory, if the initial surge event was indeed genuine, the engine will surge again on subsequent flights, and the engine performance will remain deteriorated. Under such circumstances, the engine would be removed from service.
U.S. Pat. No. 5,726,891 to Sisson et al. discloses a method of, and a system for, detecting an occurrence of a surge in a gas turbine engine. The method illustrated in Sisson includes steps, executed during consecutively occurring time periods, of: obtaining filtered derivatives of first and second engine operating characteristics; comparing the filtered derivatives of the first and the second engine operating characteristics to first and second threshold values, respectively; and incrementing a count only if both of the filtered derivatives exceed their respective threshold values. Otherwise, a next step decrements the count if one or both of the filtered derivatives do not exceed their respective threshold values. The method further includes a step of indicating a surge condition only if the count is equal to a predetermined value that is greater than unity. In a presently preferred embodiment of this invention the engine is a turbofan engine, the first engine operating characteristic is fan speed, and the second engine operating characteristic is exhaust gas temperature.
Although the Sisson et al method attempts to reduce the number of "false alarms" generated by transient conditions, it does so by evaluating the derivatives of two operating parameters over consecutively occurring time periods. A disadvantage of the Sisson et al. surge detection method is that it does not provide a method for distinguishing a spurious surge, which is a surge nonetheless, from a genuine surge. The Sisson et al. disclosure does not recognize that most genuine surge events often repeat at distinct operating regions and most spurious surge events occur randomly throughout the operating range of the engine.
It would be beneficial therefore, to provide a method of discriminating between spurious engine surges caused by disturbances to the inlet gas stream and genuine or true engine surges caused by the deterioration of the core engine or malfunction of critical engine components. Such a method would allow surge avoidance modifications to be permanently stored in non-volatile computer memory for subsequent application. The engine would remain in service until the next scheduled maintenance stop, thereby minimizing aircraft downtime.

Goodrich Pump & Engine Control Systems, Inc.


Disclosed herein are compounds of formula I and/or a stereoisomer, stable isotopologue, and/or pharmaceutically acceptable salts thereof; and therapeutic uses of these compounds, which are inhibitors of tryptophan 2, 3-dioxygenase 2 (TDO2) and/or indoleamine 2, 3-dioxygenase 1 (IDO1), potentially useful in the treatment of diseases treatable, such as cancers.

The tryptophan catabolism plays a central role in maintaining the immunosuppressive microenvironment in various types of cancers. Depletion of tryptophan levels and formation of the metabolites in the kynurenine pathway are thought to cause suppression of T cell proliferation. Additionally, the production of metabolites in the kynurenine pathway provides a source of nicotinamide dinucleotide (NAD+) and modulates other biological effects, particularly in the immune, reproductive, and central nervous systems. Tryptophan 2,3-dioxygenase (TDO2) and indoleamine 2,3-dioxygenase (IDO1 and IDO2) are related immune regulatory enzymes that oxidize tryptophan in the first step of the kynurenine pathway leading to the formation of kynurenine. Tryptophan is an essential amino acid obtained through diet required for the biosynthesis of proteins, neurotransmitters such as serotonin, melatonin and Vitamin B3 (niacin). Although these enzymes catalyze the same reaction, differential expression and compartamentalization of TDO2 and IDO in different tissues is thought to mediate their different biological roles. IDO1 is a monomer distributed ubiquitously in extrahepatic tissues particularly in lung, small intestine and placenta. Compared to IDO1, IDO2 possesses a lower affinity for L-tryptophan and is expressed mainly in brain and placenta, also present in many other tissues, such as liver, small intestine, spleen, placenta, thymus lung, brain, kidney and colon. TDO2 is a tetramer expressed predominanity in liver and placenta.
High level of IDO1 in tumors and tumor-draining lymph nodes induces T-cell apoptosis and increases regulatory T cells, which create an environment in which tumor-specific cytotoxic T lymphocytes are no longer able to attack a patient's cancer cells, and therefore is associated with a poor prognosis in various malignancies. Inhibition of IDO1 suppresses tumour formation in animal models and several IDO1 inhibitors are currently tested in various stages of clinical development (A. B. Dounay, et al. J. Med. Chem. 2015, 58, 8762-8782).
Recent studies have showed that TDO2 is equally capable of inhibiting antitumour immune responses. TDO2 is expressed in a significant proportion of human tumors. A survey of 104 cancer cell lines indicated that 16% of the cell lines expressed IDO1 positive, 19% of the cell lines expressed TDO2 positive, and 15% of the cell lines expressed both TDO2 and IDO1 positive (L. Pilotte, et al. Proc Natl Acad Sci USA. 2012, 109, 2497-2502). In a preclinical model, TDO2 expression by tumors prevented their rejection by immunized mice, while systemic treatment of a TDO2 inhibitor restored the ability of mice to reject TDO2-expressing tumors. TDO2-derived kynurenine was found to suppress antitumour immune responses and promote tumour-cell survival and motility through activating the aryl hydrocarbon receptor (AHR) (C. A. Opitz, et al. Nature 2011, 478, 197-203). Emerging evidence indicates a tumour-promoting role of the AHR. TDO2-AHR pathway is active in human brain tumours and is associated with malignant progression and poor survival. These observations suggest that TDO2 is a promising target for cancer immunotherapy. Inhibition of TDO2 can reverse the immune suppression at the tumor site and allow the generation of an effective anticancer immune response.
Kynurenine pathway is also implicated in a variety of other diseases and disorders, including autoimmune diseases or disorders, such as rheumatoid arthritis, and immunologic tolerance and prevention of fetal rejection in utero, acquired immune deficiency syndrome (AIDS), chronic infections, dementia complex, alzheimer's disease (AD), huntington's disease, amyotrophic lateral sclerosis (ALS), schizophrenia, psychiatric disorders and depressive disorders (J. Neurosci. 2007, 27, 12884-12892; Br. J. Pharmacol. 2013, 169, 1211-27; J. Psychopharmacology 2013, 27, 878-893).
Thus IDO1 and/or TDO2 have been shown to play an important role in immunosuppression, tumor resistance and other diseases such as chronic infections, HIV-infection, AIDS, autoimmune diseases or disorders, and immunologic tolerance and prevention of fetal rejection in utero. Inhibitors of IDO1 and TDO2 that suppress tryptophan degradation are desirable. Specific or dual inhibitors of IDO1 and TDO2 can be used to activate T cells and therefore enhance T cell activation when the T cells are suppressed by pregnancy, malignancy or a virus such as HIV. Inhibition of TDO2 and/or IDO1 may also be important to treat patients with neurological or neuropsychiatric diseases or disorders.

Heterocyclic compounds, compositions comprising heterocyclic compound, and methods of use thereof


A refrigerator includes a plurality of storage compartments, a plurality of cooling units to cool the plurality of storage compartments, a temperature sensing unit to sense temperatures of the plurality of storage compartments, a drive unit to drive the plurality of cooling units, and a controller to control the drive unit to drive the cooling unit that satisfies a predetermined driving condition. If at least one cooling unit among the plurality of cooling units is being driven, the controller delays driving the other cooling unit even if the other cooling unit satisfies the driving condition. The refrigerator minimizes simultaneous driving a plurality of compressors, which may prevent generation of noise and vibration, as well as excessive power consumption, due to driving the plurality of compressors.

1. Field
The following description relates to a refrigerator using a plurality of compressors, and a control method for the same.
2. Description of the Related Art
A refrigerator is an apparatus that keeps food and beverages, for example, fresh for a long time.
A refrigerator has a plurality of storage compartments including a freezing compartment in which food is kept below a freezing temperature, and a refrigerating compartment in which food is kept at a temperature slightly above freezing. In addition, a variable temperature chamber for long time storage of fresh goods, such as vegetables and fish, for example, may be provided.
Such a refrigerator keeps a storage compartment at a predetermined target temperature via an iterative implementation of a refrigeration cycle consisting of compression, condensation, expansion, and evaporation of a refrigerant. That is, the refrigerator supplies air, cooled by an evaporator provided for each storage compartment, into each storage compartment based on a target temperature of the storage compartment, thereby keeping the storage compartment at the target temperature.
Conventional refrigerators keep a freezing compartment and a refrigerating compartment at respective target temperatures using a single evaporator and do not provide appropriate cooling environments.
In recent years, a refrigerator in which evaporators are respectively provided at a freezing compartment and a refrigerating compartment has been developed. The refrigerator includes a switching valve to control a flow path of refrigerant to be supplied to the evaporator provided at the freezing compartment or the refrigerating compartment, such that the refrigerant, condensed through a compressor and a condenser, is supplied to the evaporator provided at the freezing compartment or the refrigerating compartment according to temperatures of the freezing compartment and the refrigerating compartment.
However, the aforementioned refrigerator adopts a single compressor and a single condenser, causing difficulty in simultaneously cooling the freezing compartment and the refrigerating compartment, which differ greatly in target temperature. Moreover, due to addition of a variable temperature chamber for storage of fresh goods, such as vegetables, fish, or meat, and a considerable increase in capacities of the freezing compartment and the refrigerating compartment, insufficient compressor capacity has become a major issue.

Refrigerator and control method for the same


The present invention relates to disposable elastic thermal knee wraps having one or more thermal packs comprising a plurality of heat cells, wherein heat is applied to specific areas of the user's knee, for pain relief. More particularly, the present invention relates to disposable elastic thermal knee wraps having good conformity to user's knee which provide consistent, convenient and comfortable heat application.

A common method of treating temporary or chronic pain is by application of heat to the afflicted area. Such heat treatments are used as a means of therapy for conditions which include aches, stiffness in muscles and joints, nerve pain, rheumatism and the like.
The human knee is one of the most vulnerable joints of the human body to overstress injury. While elastic compression bandages have been used to help stabilize knee movement during injury healing, heating pads, whirlpools, hot towels, and hydrocollators have been commonly used to apply heat to the knee to relieve the pain of knee injury. These pain relieving and stabilization devices, however, typically provide either one function or the other, but not both.
In general, the beneficial therapeutic effects from the administration of heat diminish after the heat source is removed. Therefore, depending on the temperature, it is desirable to provide a sustained heat source to the afflicted area for as long as possible, i.e., for from about twenty minutes to about twelve hours, preferably from about four hours to about twelve hours, most preferably from about eight hours to about twelve hours. Depending on the length of exposure, the skin temperature needs to be maintained from about 35.degree. C. to about 55.degree. C., preferably from about 36.degree. C. to about 45.degree. C., more preferably from about 37.degree. C. to about 43.degree. C., and most preferably from about 38.degree. C. to about 42.degree. C., to achieve the desired therapeutic benefits. Many of the current heating devices which require the thermal source to be replenished, such as the devices mentioned above or those employing reusable thermal packs containing water and/or microwaveable gels, are inconvenient to use on a regular and extended basis because the heat energy may not be immediately available when needed or released in a controllable manner. That is, many of these thermal units or devices do not provide long lasting heat and also do not maintain a consistent temperature over long periods of time. Proper positioning of the thermal energy also may not be maintainable during knee flexure.
Disposable heat packs based on iron oxidation, such as those described in U.S. Pat. Nos. 4,366,804, 4,649,895, 5,046,479 and Re. 32,026, are known. However, such devices have proven not totally satisfactory because many of these devices are bulky, cannot maintain a consistent and controlled temperature, have difficulty staying in place during use, and/or have unsatisfactory physical dimensions which hinder their effectiveness. Specifically, such devices cannot be easily incorporated into wraps which comfortably and reliably conform to various body contours, and hence, deliver inconsistent, inconvenient and/or uncomfortable heat application to the body.
The present inventors have discovered disposable elastic thermal knee wraps which provide both compression and thermal energy in a controlled and sustainable manner. These wraps comprise one or more thermal packs having a unified structure, wherein each thermal pack has at least one continuous layer of a semirigid material which is sufficiently rigid in specific areas of the thermal pack, yet which softens in between such areas when heated during use, preferably comprising a coextruded film of polypropylene and EVA. The thermal pack or packs also comprise a plurality of individual heat cells, which typically comprise an exothermic composition, preferably comprising a specific iron oxidation chemistry and having specific physical dimensions and fill characteristics, spaced apart and fixedly attached across the thermal pack. Active heat cells, that is, heat cells having a temperature of from about 39.degree. C. to about 60.degree. C., preferably from about 40.degree. C. to about 48.degree. C., more preferably from about 42.degree. C. to about 47.degree. C., most preferably from about 42.degree. C. to about 45.degree. C., soften narrow portions of the continuous layer or layers of semirigid material which immediately surround the heat cells. All remaining portions of the continuous layer or layers which surround the softened portions remain more rigid. The narrow, softened portions act as hinges between each heat cell and the remaining, cooler, more rigid portions, bending preferentially more than either the heat cell or the more rigid portions. This results in thermal packs which possess sufficient rigidity to maintain structural support of the heat cells when oriented on an incline or vertically, to prevent unacceptable stretching of structures of the continuous layer or layers during processing or use, and to ensure child resistance, while still maintaining good overall drape characteristics when heated. The thermal pack or packs, when incorporated into the knee wraps of the present invention, provide uniform heat coverage by having excellent conformity with the user's knee. These wraps also comprise alignment and bunching resistance features.
It is therefore an object of the present invention to provide disposable elastic knee wraps which comprise one or more thermal packs, each having a unified structure of at least one continuous layer of semirigid material, which has different stiffness characteristics over a range of temperatures, and a plurality of individual heat cells, which provide a controlled and sustained temperature and which reach their operating temperature range relatively quickly. The heat cells are spaced apart and fixedly attached across the unified structure of the thermal pack.
It is a further object of the present invention to provide disposable thermal knee wraps having good overall drapability while maintaining sufficient rigidity to maintain structural support of the heat cells and to prevent unacceptable stretching of the continuous layer or layers during processing or use.
It is a still further object on the present invention to provide disposable elastic thermal knee wraps which provide consistent, convenient and comfortable heat application while ensuring child resistance.
These objectives and additional objectives will become readily apparent from the detailed description which follows.


A lentiviral vector system for expressing a lentiviral particle is disclosed. The lentiviral vector system includes a therapeutic vector, an envelope plasmid, and at least one helper plasmid. The lentiviral vector system can produce a lentiviral particle for inhibiting PARP expression in neuron cells of a subject afflicted with Parkinson's disease.

Parkinson's disease ("PD") is the second most common neurodegenerative disorder in the United States. Approximately 1 million Americans are afflicted with PD, with more than 60,000 new cases diagnosed each year. See, e.g., Fahn, S., 991 Ann. N.Y. Acad. Sci. 1-14 (2003). The incidence is expected to double by 2030. See, e.g., Dorsey, E. R., et al., 68(5) Neurology, 384-6 (2007). PD is a chronic progressive condition that generally appears late in life. PD is caused by the degeneration and death of dopamine producing neurons in the substantia nigra region of the basal ganglia. The deteriorated neurons and reduced dopamine result in abnormal neural activity and a chronic, progressive deterioration of motor function control. Patients with PD suffer from significant quality-of-life issues due to symptoms that include bradykinesia, rigidity, tremor, and postural instability. Additional complications due to PD include non-motor symptoms, such as dysphagia, and neuropsychiatric effects. See, e.g., Weintraub, D. et al., 14(2 Suppl) Am. J. Manag. Care, S40-8 (2008).
PD can be treated with L-DOPA or dopamine agonists, but there are significant side effects and the continuous neuronal death results in an increasing requirement for L-DOPA or dopamine agonists. Gene therapy has the potential to modify the behavior of neurons in the substantia nigra. Consequently, gene therapy has been considered as a possibility for effectively treating PD.
Initial clinical studies on PD gene therapy attempted to increase dopamine production in the substantia nigra by elevating the level of dopamine-synthesizing enzymes, particularly aromatic L-amino acid decarboxylase (AADC). Adeno-associated viral vectors (AAV) carrying the complementary DNA sequence for AADC were injected into the substantia nigra of patients afflicted with PD. In one study, delivery of AADC using adeno-associated virus (AAV) was well tolerated, but the clinical outcomes trended to only modest improvement. See, e.g., Eberling et al., 70(21) Neurology, 1989-93 (2008). After longer (e.g., 4-year) follow-up, the clinical impact was largely lost, and it was concluded that the dosing was insufficient for sustained clinical improvement
An alternate approach sought to treat PD using gene therapy to increase expression of neurturin, a neurotrophic growth factor, in the substantia nigra. Results from AAV delivery of the neurturin gene to the brains of patients afflicted with PD showed no improvement over sham controls. See, e.g., Marks Jr. et al., 9(12) Lancet Neural., 164-72 (2010).
Gene therapy trials designed to increase dopamine production or provide neurotrophic growth factors have not provided a significant, durable objective clinical response in patients with PD. See, e.g., Eberling et al., supra. Part′ of the reason why treatment for PD is complex and challenging is that disease progression is due to the accelerated death of dopaminergic neurons that eventually reduces dopamine below survivable levels.
Accordingly, current treatments for PD symptoms include drugs, ablative surgical intervention, and neural stimulation.

Viral vectors for treating Parkinson's disease

American Gene Technologies International Inc.


A diaper pail has a body with an interior container space and an access opening into the interior container space. A diaper receptacle is also in the body and has a diaper receiving opening into the receptacle. An obstruction is provided that can be moved between a receiving orientation and a dumping orientation. In one aspect, an input device I configured to signal a part of the diaper pail to automatically operate the obstruction between the dumping orientation and the receiving orientation to receive a soiled diaper into the diaper receptacle and to dump the soiled diaper from the diaper receptacle into the interior container space. In another aspect, an activated charcoal filter is in communication with at least the interior storage space and is designed to chemically eliminate odors that emanate from the soiled diapers in the interior storage space.

1. Field of the Disclosure
The present disclosure is generally directed to waste containers for diapers, and more particularly to a touch-free diaper pail that can be operated without the need for the user to touch the diaper pail.
2. Description of Related Art
The diaper changing process is common to most families with children. Caregivers face the issue of what to do with a soiled diaper. Some caregivers choose reusable cloth diapers and manually dispose of the waste. The cloth diapers are then washed and reused. However, it has become much more common to use disposable diapers. Some people choose simply to toss a soiled disposable diaper in their regular trash. However, soiled diapers emit unpleasant odors.
Diaper pails and other devices for disposing of soiled diapers are known in the art. A conventional diaper pail is typically used to temporarily store soiled diapers in the vicinity of where the diaper changing process took place, such as in a child's nursery or adjacent a changing table. Every few days, the caregiver must empty the diaper pail as it fills with dirty or soiled diapers.
Many diaper pails don't prevent odors from the soiled diapers from escaping into the environment adjacent the diaper pail. Many diaper pails are also fairly difficult to use. It can be difficult for the caregiver to place a soiled diaper in the container of the diaper pail. Some of these more difficult to use diaper pails have mechanisms that are not intuitive to the average caregiver. Some of these more difficult to use diaper pails also require at least one or even both hands to properly operate the unit in order to dispose of a soiled diaper.
Some diaper pails require the use of proprietary, custom fit bags. The proprietary bags can be quite expensive and can be difficult to install and replace in the pail. Additionally, some proprietary bags can only be purchased at select retailers and, thus, can be difficult to obtain at times for an average caregiver. Many of these types of diaper pails are wasteful in that the amount of plastic used per each soiled diaper is much larger than if one were to use a regular trash bag.
Some diaper pails known in the art do not fit particularly well in a nursery. For example, many diaper pails have a circular cylinder configuration and, thus, have a circular footprint. The circular diaper pail does not fit in many conventional storage locations within a nursery or other home environment. Thus, some diaper pails can take up unnecessary space when used.
There are diaper pails on the market that have attempted to address one or more of the above-noted issues. However, there is no diaper pail available today that addresses all of the problems and disadvantages discussed above. One such diaper pail product uses a scented tablet made out of a scented plastic in attempting to mask the odor of soiled diapers. The effect has been shown to be minimal. This product has a lid that can be opened by pressing on a foot pedal at the base of the pail. This product also uses standard trash bags. The product does not eliminate odors, must be touched by the user's foot, and has a round footprint making it difficult to place in a home environment.
A second known diaper pail product has two spring loaded arms that pinch closed the bag that holds the soiled diapers. This same product also has a compartment in the lid that can receive an air freshener, which only attempts to mask the odor of soiled diapers. This same product has a push button that the user must push to open a lid and expose the receptacle in which the soil diaper can be placed. This product also uses standard trash bags. Thus, the second known product does not eliminate soiled diaper odors, still must be touched by the user in order to open the unit, and also has a round footprint making it difficult to store the unit within the home environment.
A third known diaper pail product attempts to contain soiled diaper odors by preventing the odors from escaping the containment bag. This product uses two sets of spring loaded arms to pinch the bag closed. This third product must be operated by hand in order to dispose of soiled diapers, uses proprietary trash bags, and also has a round cylinder configuration.
A fourth known product attempts to contain soiled diaper odors by preventing the odors from escaping the containment bag. This is accomplished by twisting each soiled diaper into its own compartment within a long, thin plastic bag, which may be compared to the outer skin of sausage links. The proprietary bags are scented in order to help mask the odors of the soiled diapers. This product again must be manually operated by the user. This fourth product does not eliminate odors, must be manually operated, uses proprietary trash bags, and again has a round footprint.
A fifth known product attempts to contain soiled diaper odors by employing a mechanism that drops the diaper into a containment area without exposing the odor of the soiled diaper to the environment. The containment area is sealed in an attempt to prevent escape of the soiled diaper odors. The seals are not particularly tight, so odor can and does escape the containment area. This product has a handle that must be manipulated by the user in order to turn a hole upside down to drop a diaper into the containment area. This product does use standard trash bags. Thus, this known diaper pail must be manually operated, does not eliminate diaper odors, and also has a round footprint.
Yet another known product employs trap doors and minimal seals to attempt to prevent odors from escaping the diaper pail. This sixth known product also uses proprietary scented bags to help mask soiled diaper odors. This product employs a foot pedal in order to raise the lid exposing the diaper receptacle. This product does have a rectangular footprint rendering it a better fit within the home environment. However, this sixth known product does not eliminate diaper odors, must be touched in order to be used, and uses proprietary scented trash bags. Standard trash bags can be used with this sixth known product, but the minimal masking impact gained by using the proprietary scented bags is lost.


A dual-configuration shear bolt for coupling components of an assembly is provided. The dual-configuration shear bolt can include a body defining a chamber and a pin in the chamber. The body can include a shear portion. The pin can move between a shearing position and a non-shearing position. The pin can be retained within the shear portion by a retaining mechanism in the non-shearing position. The pin can be moved away from the shear portion to the shearing position.

Tool assemblies deployed into a well system (e.g., oil or gas wells for extracting fluids from a subterranean formation) may include multiple components or devices coupled together. For example, a tool assembly that includes multiple tools may be deployed into a wellbore, such as a whipstock assembly with a whipstock that is attached to a lead mill using a shear bolt. In some cases, one or more tools may be disconnected from the tool assembly prior to retrieving the tool assembly from the wellbore.
During deployment, large amounts of force may be applied to a tool assembly that includes a shear bolt connection between tools. Some shear bolts may be designed to shear at forces lower than the forces applied to the tool assembly during deployment. For cases in which forces applied to the tool assembly during deployment exceed the shear strength of the shear bolt, a shear bolt connection may shear and thereby prematurely decouple components of the tool assembly. Prematurely decoupling components of the tool assembly may result in costly delays or retrieval operations.


An integrated optical waveguide based surface plasmon resonance biosensor is formed by detecting amplitude and phase of electromagnetic waves utilizing interferometry and/or optical delay configurations.

1. Field of the Invention
The present invention relates to biosensors based on integrated optical waveguides, and more particularly, to surface plasmon resonance interferometric detection sensors formed by an array of planar waveguides.
2. Description of Related Art
Surface plasmon resonance (SPR) devices have shown high sensitivity in the detection of chemical and biological agents. Conventional SPR devices are based on sensing the reflectance change of mono- or polychromatic light, which undergoes total internal reflection at the hypotenuse of a prism, which is coated with a thin metal film. At certain angles of incidence for a given wavelength of light, the incident light with polarization in the plane of incidence is in resonance with the surface plasmon of the metal film. The term "surface plasmon" describes the collective longitudinal oscillation of the electrons in the metal film. The angle of incidence for the wavelength of the light at which this surface plasmon resonance occurs is very sensitive to the dielectric constant of the immediate environment of the thin metal film, which can be changed by a change in the index refraction of the surrounding material or chemical bonding of material deposited onto the metal layer.
Free space SPR interferometry techniques, such as SPR ellipsometry, optical heterodyning, and mapping the spatial intensity distribution, are cumbersome to be incorporated into compact SPR devices and exhibit high sensitivity to changes in the environment, such as temperature fluctuations. By contrast, a planar optical waveguide based SPR sensor operates similarly as a free space prism SPR device, but it offers higher sensitivity and is capable of being fabricated into multiple sensors on a single chip and can be easily integrated with fiber optical components, such as light sources and detectors.
Background information on a waveguide based SPR sensors that monitors the ratio of the transverse magnetic (TM) polarization and transverse electric (TE) polarization intensities is described in U.S. Pat. No. 5,606,633, issued Feb. 25, 1997, to Groger et al. "Chemical detector employing surface plasmon resonance excited using an optical waveguide configuration as an asymmetric waveguide coupler," including the following, "the ratio of the TM and TE polarization intensities is monitored by a polarization beam splitter. The relatively unchanged TE polarization intensity serves as an integral reference for the sensor."
The article "Surface plasmon resonance biosensor based on integrated optical waveguide" by J. Dostalek et al. (Sensors and Actuators, vol. B76, 2001, pages 8–12) describes the use of a broadband light source combined with spectral interrogation of SPR and demonstrates a detection sensitivity of 10−6 to a change in the index of refraction. Another SPR technology is based on detecting the phase-change of the light in a SPR sensor, which has been shown to significantly increase the detection sensitivity (P. Nikitin et al, "Surface plasmon resonance interferometer for biological and chemical sensing" Sensors and Actuators B., 1999, vol. 54, pp. 43–50).
Accordingly, a need exists to provide a highly sensitive surface plasmon waveguide arrayed sensor that simultaneously detects intensity and phase by planar light wave geometries. The present invention is directed to such a need.

Multiple array surface plasmon resonance biosensor


A handwriting type input display device is provided with a display device for performing a two-dimensional display, an input device which constitutes a handwriting device in combination with the display device, and is adapted to detect a handwriting input operation by a user at a coordinate position corresponding to a position on a screen of the display device, a passing point predicting device for receiving the coordinate point sequence from the input device to insert a new coordinate point sequence between neighboring coordinate points of the coordinate point sequence, and outputting a coordinate point sequence for forming a smooth handwritten curved line, and a processing device for instructing an insertion method of coordinate points to the passing point predicting device, and performing processing of displaying on the display device a curved line based on the coordinate point sequence which is obtained by the passing point predicting device.

1. Field of the Invention
The present invention relates to a user interface technique for an information processing device, and particularly to a handwriting type input display device according to a handwriting input display technique in which "operability of paper and pen" (which is defined as the same operability as performed by handwriting information on physical paper with a physical pen) is achieved by an information processing device.
2. Description of the Related Art
A handwriting type input display device to achieve "operability of paper and pen" has been hitherto utilized as a user interface for a general user because it can be easily operated by even an user who is unfamiliar with the operation of the information processing device. However, since such a conventional handwriting type input display device cannot sufficiently reproduce "the operability of paper and pen", there is a problem that the operational load imposed on the user is large and thus the operation efficiency of the user is low.
This problem will be described in detail by considering some specific prior art.
As a first prior art, there is known a handwriting type input display device such as a pen computer or a pen electronic pocketbook in which the coordinate value of a coordinate point detected by coordinate input means (corresponding to input means shown in FIGS. 1 to 3) such as a touch panel or the like is interpreted by processing means, and then a response display based on the interpretation is performed by display means such as LCD (Liquid Crystal Display) or the like.
In such a handwriting type input display device, there is a time delay from the time when a user performs his handwriting input operation until the time when a response display to the handwriting input operation is actually performed by the display means, and thus the user must carry out his handwriting input operation while considering that a curved line which does not appear at the input time (a curved line which is not displayed on the screen of the display means) will be displayed in time. This consideration would put mentally and realistically heavy operational load on the user. In addition, since the sampling interval of the coordinate input means is generally longer than the speed of the handwriting operation which is daily carried out by the user, a curved line which is handwritten by the user is actually broken in a response display step even by smoothly shifting a pen. Therefore, in order for the user to draw a curved line accurately, he must slowly shift the pen in consideration of the sampling interval, which causes the operation efficiency of the user to be reduced.
In the specification, an equipment to be held by an user to perform the handwriting input is called as "pen" (even if another name is provided to an equipment having the same function, the equipment is assumed to be covered by the concept of "pen").
As a second prior art, there is a handwriting input display device disclosed in Japanese Laid-open Patent Application No. Hei-6-289993. In order to solve the problem of the time delay of the response display in the first prior art, according to the second prior art, the coordinate value of a coordinate point which is predicted as a coordinate point to be input next is generated on the basis of the sequence of coordinate points (hereinafter referred to as a coordinate point sequence) obtained by coordinate input means, and then the response display of the coordinate point thus predicted is performed earlier by the delay time. If the position error (displacement) between the predicted coordinate point and the actually input coordinate point is large, the response display of the predicted coordinate point is deleted and the response display of the actually input coordinate point is performed again.
In the handwriting type input display device as described above, it is difficult to perform an accurate prediction on the basis of the sequence of the coordinate points which are obtained by the coordinate input means having a long sampling interval. In addition, the processing time is wasted because the response display must be carried out while repeating the deletion of predicted coordinate points which do not meet the actually input coordinate points as described above, and thus it is impossible to perform a continuous response display along a handwritten locus of a pen. This causes a user to be confused in the course of his handwriting operation, resulting in reduction of the operation efficiency.
As described above, in the above-described handwriting type input display devices, there are some problems that the operational load on the user is large and that the operation efficiency is low. That is, as described above, the first prior art has the problem that the operation load on the user is large because the response display to the handwriting input operation has a time delay, namely, time lag. The first prior art also has the problem that the operation efficiency of the user is low because the sampling interval of the coordinate input means is long. Furthermore, the second prior art has the problem that the processing time is wasted by the retrial of the response display for the deletion of a predicted coordinate point and it is impossible to perform a continuous response display along a locus of a pen, so that the operation efficiency of the user is reduced.


A heater system includes a bag forming a cavity, a fluid bladder carried within the cavity and forming a fluidly sealed chamber. The fluid bladder being configured to store electrorheological fluid within a fluidly sealed chamber. The heater system further including an electrical wire in fluid communication with the electrorheological fluid and a heater blanket carried within the cavity. The method includes altering the electrorheological fluid with a current and providing heat with a heater blanket.

1. Field of the Invention
The present application relates generally to heater blankets, more specifically, to a heater blanket having variable stiffness.
2. Description of Related Art
Heater blankets are well known in the art for providing warmth to an object. Conventional heater blankets typically include an electrical wire disposed within a thermal conductive body and when activated, the electrical energy traveling through the wire creates heat, which in turn warms the object that the heater blanket is place thereon.
In one application of use, a heater blanket is utilized in the aircraft industry during repair of a laminate structure. For example, a plurality of repair plies are stacked and placed on a damaged composite surface and thereafter cured with the heater blanket. The heat from the heater blanket causes the adhesive disposed within the plies to cure.
A common disadvantage with conventional heater blankets is the inability to retain the heater blanket in a fixed position on the plies without the use of straps and/or a vacuum bag. Further, conventional heater blankets are not always adapted to conform to the outer surface of the structure, thereby limiting use.
Although the foregoing developments in the field of heater blankets represent great strides, many shortcomings remain.
While the system and method of the present application is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular embodiment disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the process of the present application as defined by the appended claims.

Variable stiffness blanket with variable heating


The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a top metal layer on a first substrate, in which the top metal layer has a plurality of interconnect features and a first dummy feature; forming a first dielectric layer over the top metal layer; etching the first dielectric layer in a target region substantially vertically aligned to the plurality of interconnect features and the first dummy feature of the top metal layer; performing a chemical mechanical polishing (CMP) process over the first dielectric layer; and thereafter bonding the first substrate to a second substrate.

In semiconductor technology, a semiconductor substrate can be bonded to another substrate in applications such as the fabrication of a back-illuminated imaging device or a micro-electro mechanical system (MEMS). While having a second, bonded substrate can facilitate the processing of the semiconductor substrate, it can produce additional difficulties. For example, a polishing process often cannot achieve expected surface flatness when using a second, bonded substrate due to bonding quality issues such as air bubbles and delaminations.

Taiwan Semiconductor Manufacturing Company, Ltd.


The present invention relates to an anchor for floating devices and includes a body provided with a shackle linked to an anchor chain, with one set member for engaging the bed of a body of water being jointedly mounted on said body. The body includes a first portion having two longitudinal ends and a second portion extending between the ends of the first portion and being spaced away so as to surround a void space therebetween. The shackle is slidingly mounted along the second portion and the set member is assembled on the first body portion in a jointed fashion to thereby be able to switch between set positions pointing oppositely from each other.

A great number of anchor types are known such as a stock type anchor, a blade type anchor, and a flat type anchor, etc.
Many known anchor designs, in particular the blade type anchor, suffer from being hardly retrievable, i.e. they are frequently lost since one must disconnect the anchor from the boat in order to set the latter free.
By contrast, other anchors such as the flat type anchor, allow some degree of play which results In better release, but reset is difficult to achieve in case of a tidal change for instance.


An expandable well screen provides increased collapse, torsional and tensile strength. In a described embodiment, an expandable well screen includes a generally tubular base pipe and an external filtering media. The well screen is configured to have sufficient torsional and tensile strength for conveyance and positioning in a wellbore, while also having sufficient strength to prevent collapse when the screen is radially expanded.

The present invention relates generally to operations performed, and equipment utilized, in conjunction with a subterranean well and, in an embodiment described herein, more particularly provides an expandable well screen.
It is useful in some circumstances to be able to convey generally tubular equipment into a subterranean well, position the equipment within a wellbore of the well, and then outwardly expand the equipment in the wellbore. For example, a restriction in the wellbore may prevent the equipment in its expanded. configuration from passing through that part of the wellbore, but the equipment may pass through the restriction in its retracted configuration. In one application of this principle, it is known to use expandable well screens in wellbores.
An example of the potential usefulness of expandable equipment in a wellbore is where the wellbore intersects a productive, relatively unconsolidated, formation. It would be desirable in many situations to be able to utilize a well screen to filter production from the formation, while foregoing the expense of cementing casing in the wellbore and performing a gravel packing operation. Unfortunately, without any radial support the unconsolidated formation would likely collapse into the wellbore, causing additional expense and loss of revenue. Conventional nonexpandable well screens must necessarily be smaller than the wellbore in order to be conveyed therethrough, and so they are incapable of providing any radial support for an unconsolidated formation. Conventional expandable well screens are not designed for contacting and providing radial support for a formation, and so are unsuited for this purpose.
Therefore, it can be seen that it would be quite desirable to provide an expandable well screen which may be used for contacting and providing radial support for a formation intersected by a wellbore. It would also be desirable to provide an expandable well screen having enhanced torsional and tensile strength. It is accordingly an object of the present invention to provide such an expandable well screen.


In a vehicle drive control system, a control unit calculates an evaluation index indicating an approach/separation condition of a subject vehicle during a travel and stores this evaluation index together with an inter-vehicle distance with respect to each driver in a memory device. The control unit further calculates a maximum value of the stored evaluation index for each distance, and calculates a relational equation between the distance and the calculated maximum evaluation index. The control unit determines, by correcting the relational equation, a speed control start determination equation, which determines the start timing of the automatic acceleration and/or deceleration control.

As disclosed in JP 06-40270A (JP 2567548), for example, an inter-vehicle distance control system, which controls a subject vehicle to maintain an inter-vehicle distance from a preceding vehicle at a target inter-vehicle distance based on a relative speed between the subject vehicle and the preceding vehicle.
According to this inter-vehicle distance control system, the time constant of a filter for processing a relative speed signal or information (data) is set small when the vehicle speed is high and the inter-vehicle distance is short, and the time constant of the filter is set large when the vehicle speed is low and the inter-vehicle distance is long. The inter-vehicle distance control system improves the control response characteristic by the small time constant and realizes the control stability.
Since the above inter-vehicle control system controls the speed of the subject vehicle to maintain the inter-vehicle distance at the target inter-vehicle distance, the acceleration/deceleration (acceleration and/or deceleration) of the vehicle will not necessarily match acceleration/deceleration, which a driver of the subject vehicle wants.
It is therefore proposed in US 2007/0021876 A1 (JP 2007-076632 A) that a vehicle drive assisting system is configured to accelerate and decelerate a subject vehicle based on a target relative acceleration/deceleration, which is calculated as a target between the subject vehicle and a preceding vehicle, based on a target driver condition coefficient and an actual driver condition coefficient. The target driver condition coefficient is a driver condition coefficient corresponding to a desired drive operation performed by a skilled or model driver to maintain an inter-vehicle distance between the subject vehicle and the preceding vehicle.
However, according to this proposed vehicle drive assisting system, both the target deceleration and the target acceleration are calculated based on only the inter-vehicle distance and the relative speed, and hence the acceleration and the deceleration are still not so satisfactory to a driver at some instances.
It is therefore further proposed in U.S. patent application Ser. No. 12/151,998 (JP patent application No. 2007-128568) filed on May 12, 2008 that a vehicle control system is configured to control acceleration based on a correction distance condition evaluation index KdBc, which is calculated in consideration of a travel speed of a preceding vehicle. This evaluation index indicates approach/separation (approach and/or separation) of the subject vehicle relative to the preceding vehicle. In this US patent application, it is indicated that braking start points (timings) are present on one characteristic curve when the evaluation index KdBc is calculated by the following equation Eq. 1. This is based on a result of testing a vehicle by starting to brake the vehicle at the latest possible timing not to crash the preceding vehicle under a condition that the subject vehicle is approaching the preceding vehicle. This characteristic curve is approximated as the following equation Eq. 2.KdBc=10×log{|(−2×|Vr|+α×|Vb|)/(D3×5×10−8)|}  (Eq. 1)KdBc=−23.76×log D+76.96   (Eq. 2)
For many drivers, use of the approximated equation Eq. 2 as the equation for determining the timing of starting the acceleration control and the deceleration control will provide generally satisfactory and comfortable starting of acceleration and deceleration. However, the timing of starting decelerating operation varies from driver to driver. As a result, the timing of starting the acceleration and deceleration determined by the approximated equation Eq. 2 will possibly be felt too early or too late.


In a semiconductor device having a first terminal 101 (source terminal) and a second terminal 102 (drain terminal), the substrate main surface of a semiconductor chip is on the (110) face, the main contact face of an n-type region 2 and a p-type region 4 is the {111} face perpendicular to the (110) face, elongated n-type regions 2 and elongated p-type regions 4, which are arranged alternately, form a voltage holding area. The first terminal 101 is connected to the p-type regions through wiring, and the second terminal 102 is connected to the n-type regions 2. Also, the p-type region is formed to cover the bottom comers of a gate polycrystalline silicon layer 8.

In known semiconductor devices, in cases where the terminals of the main current path are used as first and second terminals to give the semiconductor devices a high withstanding-voltage, it is necessary to form a depletion layer so that the strength of an electric field generated inside of the semiconductor element, when a voltage is impressed between the first terminal and the second terminal, becomes lower than the critical strength, resulting in avalanche breakdown. To this end, it is necessary to make the specific resistance of a drift layer area high and to form the drift layer area so that the length thereof in the voltage drop direction is large, so that the depletion layer can easily spread when a voltage is applied between the first and second terminals. Therefore, there is a problem that the resistance between the first terminal and the second terminal raises rapidly as the withstanding-voltage between the first terminal and the second terminal is made higher.
Japanese Patent Prepublication No. 54661/1990 discloses a semiconductor device in which the semiconductor main body has a plurality of n-type first regions, between which a p-type second region is sandwiched. The length of these first and second regions in the direction perpendicular to their thickness is made to have a value sufficient to carry a voltage over 100V along the semiconductor main body when a free charge carrier was eliminated, and an electrically parallel current path is formed which extends through the semiconductor main body. The values of the thickness and doping density of each of the first and second regions are selected so that the space-charge per unit area of each of positive and negative alternately arranged space-charge regions formed by the first and second regions becomes lower than the critical strength, resulting in avalanche breakdown.
Further, in the above-mentioned Japanese Patent Prepublication No. 54661/1990, a semiconductor device is also disclosed in which, in order to form said first and second regions, a high resistance p-type epitaxial layer is grown on a low ohmic n-type substrate having a main surface axial direction of [110], and etching is performed until reaching the substrate by using anisotropic etching. A groove is formed having sheer side faces in the epitaxial layer, and then an n-type epitaxial layer is formed, and this n-type epitaxial layer is used as said first regions and said high resistance p-type epitaxial layer is used as said second regions. Although in the above-mentioned Japanese Patent Prepublication No. 54661/1990 there is a description indicating that anisotropic etching is applied to the (110) face, and thereby the repeated pattern of n-type and p-type regions can be formed, no planar structure suitable for low loss is discussed. Also, in the case of the semiconductor elements in the above-mentioned Japanese Patent Prepublication No. 54661/1990, since it is impossible to make the repeated pattern of the n-type and p-type regions narrow, there is the problem that it is impossible to make the electric power consumed in the semiconductor element; and, further, because of the existence of said repeated pattern, there is the problem that the inter-drain/source capacitance of a power MOS FET, for example, becomes large.
In U.S. Pat. No. 5,438,215 and U.S. Pat. No. 5,216,275, there is disclosed a planer structure suitable to provide a semiconductor device best suited to a high withstanding-voltage and low loss. However, in U.S. Pat. No. 5,438,215 and U.S. Pat. No. 5,216,275, there is no description relating to the planer structure suitable for the case where the (110) face is used as the semiconductor substrate.
Japanese Patent Prepublication No. 223896/1998 proposes a method for ion implantation into the side faces of etched silicon grooves, as a method of manufacture of a semiconductor device simultaneously achieving low loss and a high withstanding-voltage. However, although Japanese Patent Prepublication No. 54661/1998 describes an approach for making the pitch of the repeated pattern of the n-type and p-type regions narrow, this structure is in effect unsuitable for production.
German Patent No. 19730759 discloses a structure in which said p-type second regions are separated from the body diffusion layer of a MOS FET. In the technique disclosed in this German Patent No. 19730759, in order to obtain a device structure suitable for a high withstanding-voltage and a low loss, there is a need for an improvement.
The semiconductor device according to this invention comprises a voltage holding area in which, within the semiconductor chip, first regions of a first conduction type having an elongated shape and second regions of a second conduction type having a similar shape are arranged alternately and adjacently. The first regions are connected to a second terminal and the second regions are connected to a first terminal. When a voltage is applied between the first and second terminals and current flow is obstructed, positive and negative space-charge regions are alternately arranged in the voltage holding area formed by the first and second regions. In this case, the first and second conduction are the p-type or the n-type, respectively, which are opposite conduction types. Furthermore, the semiconductor device according to this invention can have one construction selected from the following descriptions A to E:
A. A device in which the substrate main surface of the semiconductor chip is positioned on the (110) face and a couple of opposed side edges of four side edges of the semiconductor chip are positioned on the {111 } face, which is perpendicular to the (110) face, and the first and second regions extend in an elongated fashion in the [110] axis direction.
B. A device in which the substrate main surface of the semiconductor chip is positioned on the (110) face, and the first and second regions extend in an elongated fashion in the [110] axis direction, with the main contact face positioned on the {111 } face perpendicular to (110) face.
C. A device in which a third regions of the first conduction type are formed at the periphery of the voltage holding area, said third regions having a higher mean impurity concentration than that of the first regions.
D. The semiconductor device is an insulated gate type semiconductor device of which channel region is separated from the second regions.
E. The semiconductor device is an insulated gate type semiconductor device of a trench gate type, which the spacing between the trench gates is shorter than the spacing between the second regions.
A method of manufacturing a semiconductor device having the construction A or B, according to this invention includes the following steps F or G:
F. A step of forming a groove in the silicon semiconductor chip with an anisotropic etching liquid by using as a mask a polygon pattern composed of four main sides intersecting at the angle of 70.5xc2x0xc2x15xc2x0 or 109.5xc2x0xc2x15xc2x0, and a step of filling the formed groove with a silicon layer.
G. A step of forming a groove in said silicon semiconductor chip with an isotropic etching liquid by using a photo mask formed along the (-11-1) face or the (-11-1) face on which a couple of opposed side edges out of four side edges of said semiconductor chip are positioned, and a step of filling the formed groove with a silicon layer.
In accordance with this invention, the voltage holding area can be formed with high precision, or it is possible to improve the voltage holding function of the voltage holding area at the time when current flow is obstructed. Therefore, it is possible to achieve a semiconductor device with a high withstanding-voltage and/or a low loss function.