Large graph data in many application domains dynamically changes with vertices and edges inserted and deleted over time. The problem of identifying and maintaining densely connected regions in the graph thus becomes a challenge. Embodiments of the invention describe a method using a k-core measure as a metric of dense connectivity over large, partitioned graph data stored in multiple computing servers in a cluster. The method describes steps to identify a k-core subgraph in parallel and to maintain a k-core subgraph when a new edge is inserted or an existing edge is deleted. The embodiments thus enable practitioners to identify and monitor large scale graph data, such as exemplified by multiple topical communities in a social network, in a scalable and efficient manner.

1. Field
The present invention relates generally to analytical techniques, and more particularly to analytical techniques for identifying a k-core subgraph in a graph and maintaining the materialized k-core subgraph over dynamic updates to the graph, usefully with data stored in a distributed cluster.
2. Description of the Related Art
Large scale graph data is widely represented in problems in scientific and engineering disciplines. For example, the problems of identifying k-core subgraphs appear in the context of finding close-knit communities in a social network, analyzing protein interactions, understanding the nucleus of Internet Autonomous Systems, and the like. In graph theory, k-core is a key metric used to identify subgraphs of high cohesion, also known as the "dense" regions of a graph. The k-core metric is defined as the maximal connected subgraph in which all vertices have degree at least k (Reference: http://en.wikipedia.org/wiki/Degeneracy_(graph_theory)#k-Cores) Equivalently, the k-core subgraph can be found by repeatedly deleting from the complete original graph all vertices of degree less than k.
Previously, Batagelj and Zaversnik (BZ) proposed a linear time algorithm to compute k-core (Reference: Vladimir Batagelj and Matjaz Zaversnik. An O(m) Algorithm for Cores Decomposition of Networks, Advances in Data Analysis and Classification, 2011. Volume 5, Number 2, 129-145). The BZ algorithm first sorts the vertices in the increasing order of degrees and starts deleting the vertices with degree less than k. At each iteration, the algorithm sorts the vertices by their degrees to keep them ordered. Due to high number of random accesses to the graph, the algorithm can run efficiently only when the entire graph can fit into main memory of a single machine.
In order to go beyond the limit of main memory, Cheng et al. proposed an external-memory algorithm, which can spill into disk when the graph is too large to fit into main memory (Reference: J. Cheng, Y. Ke, S. Chu, and M. T. Özsu, "Efficient core decomposition in massive networks," in ICDE, 2011, pp. 51-62). This proposed algorithm, however, does not consider any distributed scenario where the graph resides on a large cluster of machines.
In addition to computing k-core, another challenge is to maintain the k-core subgraph, as successive edge insertions and/or deletions occur. Li et al. addressed dynamic updates by determining a minimal region in the graph impacted by updates (Reference: R. Li and J. Yu, "Efficient core maintenance in large dynamic graphs," arXiv preprint arXiv:1207.4567, 2012). The proposed Li et al. algorithm however only works for in-memory on a single server only.

Distributed k-core view materialization and maintenance for graphs

International Business Machines Corporation


A cylindrical plug connector is provided for terminating an electrical cable which includes at least first and second inner conductors surrounded by an outer insulating jacket. A generally cylindrical dielectric housing mounts at least an outer cylindrical conductive contact and an inner conductive contact. The inner conductive contact is terminated to one of the first and second inner conductors of the cable. A terminal has a body portion in engagement with the outer cylindrical conductive contact. The terminal includes a first crimp arm projecting from the body portion for crimping termination with the other of the first and second inner conductors of the cable, and a second crimp arm projecting from the body portion for crimping onto the outer insulating jacket of the cable.

DC plug connectors are used to terminate multi-wire electrical cables, such as a 3-wire cable, with the plug connector being mateable into a cylindrical DC jack or socket. A typical DC plug connector includes a pair of outer, telescoped cylindrical contacts surrounding a center contact. The plural contacts conventionally are soldered to the three wires or conductors of the cable. Some form of strain relief means are provided between the connector and the cable. With the contacts being soldered to the conductors and the connector being additionally secured to the cable by the strain relief means, automated manufacture and/or assembly is difficult and expensive.
The present invention is directed to providing an extremely simple DC plug connector of the character described wherein all of the termination operations can be carried out by simple crimping processes.


A bicycle accessory container constructed to be supported generally under a seat of a bicycle. The container includes a pair of sidewalls that generally enclose a cavity. A severable closure is attached to the sidewalls and allows the cavity to be selectively enclosed or exposed to atmosphere. A securing member is secured to one or both of the sidewalls within the cavity and is deformable between a first orientation wherein the securing member will pass freely between adjacent seat brackets and a second orientation wherein the securing member will not pass freely through the space between the seat brackets.

The present invention relates to a bicycle accessory container and, more particularly, to an accessory container or seat pack, constructed to be suspended from beneath a seat of a bicycle.
Interest in recreational and/or competitive cycling continues to increase. The consequence of this popularity of bicycle riding has been a growing presence of bicycle operators or riders or cyclists, of all ages, on public roads or off road trails. Further, as the recreation has grown, typical bicycle excursions or trips have lengthened in extent and, concomitantly a great variety of lighter, multi-geared and faster bicycles have entered the marketplace. Increasingly, as bicycle trips are planned for longer durations and distances, riders commonly prefer to carry several accessories with them during such excursions. Some such accessories can include car keys, identification, small tools, money, sunscreen, electronic devices such as cell phones and the like, etc. Many riders wear clothing that does not include pockets or other containers for carrying such items. Even when wearing clothes with pockets, operating a bicycle with such articles disposed in a pocket can be both a nuisance and/or painful. Accordingly, many riders prefer to have an accessory carrying device that can be supported by the bicycle rather than carried on the rider. One such device is a seat pack.
A seat pack is a container constructed to be suspended or otherwise supported by the seat of bicycle. Positioning, the accessory container near the seat of the bicycle ensures that a rider can access the accessories even during operation of the bicycle. Some seat packs are constructed to be permanently secured to particular bicycle whereas others are constructed to be removably secured thereto. Those seat packs that are constructed to be removable secured to a bicycle generally include a mating structure wherein one part is permanently secured to a particular bicycle and a pack part removably engages the mating structure. Although such systems allow the pack to the removed from the bicycle relatively easily, such systems are not without their drawbacks.
Many seat packs are provided as a two part system, the pack itself and a support bracket. The bracket is mechanically fixed to a seat and the pack removable engages the bracket. Such systems generally require a bracket that is specific to a seat construction and the use of multiple mechanical connectors to secure the bracket to a respective seat. Although such systems provide a removable pack, use of the pack is limited to the bicycle having the bracket attached thereto. Alternatively, the rider must transport the tools necessary to transfer the bracket from one bicycle to another. Furthermore, loss, theft, or damage to either of the pack or the bracket renders the other part of the system virtually useless.
Another drawback of such systems is the relatively complex construction of the connection mechanism configured to allow the removable engagement of the seat pack with the underlying bracket. Commonly, a snap fit connection or otherwise movable members are provided that interact to secure the pack to the bracket. Such systems generally include deformable tabs and/or spring biased members that are constructed to cooperate with mating structures formed on the alternate member of the system. Such configurations complicate the construction of the seat pack system and are also suspect to failure. Generally, if any portion of the interface structure between the pack and the bracket becomes damaged and/or worn, the seat pack system in rendered unreliable and/or unusable.
The riding environment can also impact the life cycle of the seat pack system. Riders who venture from paved surfaces are commonly subjected to more jarring or impact forces than riders who remain on paved surfaces. These forces are translated to the bicycle and any of the accessories and/or accessory mounting systems secured thereto. An accessory containing system such as a seat pack must be constructed to withstand such operating conditions. Furthermore, the means of connecting a seat pack to the bicycle must also be able to withstand the forces associated with extended rides over rough terrain so as to avoid the seat pack from becoming unintentionally detached from the seat.
In view of the above, it will be apparent to those skilled in the art that there exists a need for an improved seat pack system that is easy to use, is engageable with a variety of bicycle seat configurations, is constructed to be quickly and efficiently used with different bicycles, is robust and simple to use, and cost effective to manufacture.


A method for managing Quality of Experience (QoE) for video streaming traffic flow on a network, the method including: collecting data associated with a plurality of video streaming traffic flows; creating a model based on the collected data; determining factors associated with a new video streaming traffic flow; analyzing the factors based on the model; determining a QoE score based on the analysis. A system for managing QoE for video streaming traffic flow on a network, the system including: a factor determination module configured to collect data associated with a plurality of video streaming traffic flows; a model module configured to create a model based on the collected data; an analysis module configured to determine factors associated with a new video streaming traffic flow and analyze the factors based on the model; and a QoE engine configured to determine a QoE score based on the analysis.

Internet Data traffic has been growing quickly in developed and developing markets. Video streaming traffic tends to dominate the overall bandwidth and volume of data consumed. As such, there is a need to accurately calculate subscriber video experience. Understanding user experience while consuming streaming video has generally been identified by network operators as critical in evolving their infrastructure to next generation technologies. Without the right methods of estimating real world user experience, network operators may struggle to maintain their credibility in an increasingly competitive landscape. This may be exacerbated by the rise of a wide variety of Over the Top (OTT) video providers (YouTube, Disney+, Netflix, Amazon Prime Video, and the like, along with regional or country specific providers) that may host different types of content, different types of encoding and may cater to different types of audience demands for experiencing video. Further, a greater variety of programming and sporting events are being telecasted live on the Internet, as well as TV shows and movies increasingly shifting from traditional screens (movie theatres and terrestrial/cable television) to the Internet. As such, there is a need to more effectively manage, measure and monitor video quality on a network.
Network operators benefit from understanding how video streaming is being provided and consumed by end users to ensure quality of experience, congestion management, advanced data services, billing and charging related services, and the like. Given that videos may be streamed over a wide variety of devices including but not limited to smartphones, laptop/desktop computers, Smart Televisions, and the like, accurately understanding the nature of user experiences coupled with possible network-related incidents and outages that may impact user experience is a challenge. With the rise of end to end encryption for a lot of Internet traffic, network providers may not have access to the actual video information like audio/video codecs, frame-rate, position, duration of video in a given traffic flow.
The task of measuring video quality becomes even more challenging for systems that do not have full access to either the client side or the server side. These systems only have access to the data "on the wire" and typically include Internet Service Providers (ISPs) or network operators (generally referred to herein as operators) that deploy wired, wireless (mobile), and satellite networks.
There is therefore a need for improved systems and methods for managing video streaming quality of service and quality of experience.
The above information is presented as background information only to assist with an understanding of the present disclosure. No determination has been made, and no assertion is made, as to whether any of the above might be applicable as prior art with regard to the present disclosure.

System and method for managing video streaming quality of experience


An operation cable has an operational structure in which an inner member inserted into a tubular outer member is pulled from a lower end side thereof. The operation cable having a double layer structure is axially connected to a double layer cable that is constructed from a stay of a headrest and a push rod inserted into the tubular stay. In particular, the stay is inserted into a support positioned on an upper portion of the seat back, a lower end of the stay and an upper end of the inner member are axially connected to each other, so that a lower end of the push rod in the tubular stay and a head portion of the outer member are positioned closer to each other. As a result, the push rod can be pushed by the head portion of the outer member when the operation cable is pulled.

Conventionally, there is a vehicle seat having a mechanism that is capable of instantaneously moving a headrest forwardly so as to support a head of a sitting person when a vehicle back-side collision happens. An operation mechanism for moving the headrest forwardly as described above is known. The operation mechanism uses an operation cable that is pulled by a seat back loading that is applied to a seat back by the sitting person when the vehicle back-side collision happens.
This operation cable, for example, has a double layer structure in which a linear inner member is inserted into a flexible tubular outer member. The operation cable is disposed so as to extend from inside of the headrest to inside of the seat back through a stay that may function as a support pillar thereof. Therefore, in a case that the headrest is constructed to be detachable with respect to the seat back, it is necessary to take various structural measures in order to dispose the operation cable. For example, the operation cable can be divided to two portions. The divided portions are respectively previously disposed in the headrest and the seat back, so that end portions thereof are connected to each other when the headrest is attached to the seat back.
Japanese Laid-Open Patent Publication No. 2003-299549 teaches a technique in which electrical cables separately disposed within a headrest and a seat back can be connected to each other during headrest attaching operation. According to this technique, one of the electrical cables is inserted into a tubular stay of the headrest. A connection terminal of the cable is retained at a lower end of the stay. Conversely, the other of the electrical cables is also inserted into a cylindrical stay-insertion support that is disposed in an upper portion of the seat back. A connection terminal of the cable is retained within the cylindrical support while maintained in a standby condition for connection. Thus, the connection terminals of both of the electrical cables can be axially integrally connected to each other when the stay is inserted into the cylindrical support.


A multiport memory device includes first and second memory cell arrays divided by a shared sense amplifier circuit, a first serial data register capable of transferring data with a row in the first memory array through a first data bus, a second serial data register capable of transferring data with a row in the second memory array through a second data bus. The multiport memory device activates both the first and second data bus for transferring data of a row in the first or second memory array both to the first and second serial data registers in the same data transfer cycle in response to a dual read transfer instructions.

1. Field of the Invention
The invention relates to a multiport semiconductor memory device having a RAM port which is accessible in a random sequence and a SAM port which is accessible only in a serial sequence, and particularly to a dual port semiconductor memory device having a RAM port including a DRAM (dynamic random access memory) having a shared sense amplifier structure.
2. Description of the Related Art
In recent years, various technical developments have been rapidly progressed in a field of image processing technology. Such developments include colored display of CRTs (cathode ray tubes) for personal computers, three dimensional display of images in CAD systems (computer aided design systems), enlargement and reduction of images, multi-window display of screens and improvement of image resolutions.
Under these circumstances, image signals are converted into digital signals for processing at a high accuracy. For storing digital image signals, video memories have been developed for various image processing applications. Among these video memories, a video RAM (random access memory) is known as a memory optimized for storing digital image data. The vide RAM has a random access port which is accessible in a random sequence and a serial access port which is accessible in a serial sequence.
FIG. 7 shows a construction of an image processing system using a video RAM. In FIG. 7, the image processing system includes a video RAM 1 for storing image data, a central processing unit (CPU) 5 which accesses video RAM 1 through a data bus 6 in a random sequence, a CRT controller 7 which reads data from a video RAM 1 in a serial sequence, and a CRT display 8 which displays the data read under the control of CRT controller 7 on a screen.
Video RAM 1 includes a dynamic random access memory 2 having dynamic memory cells arranged in rows and columns, a serial access memory 4 having a memory capacity sufficient for storing the data of memory cells in one row of dynamic random access memory 2, and a data transferring bus 3 for transferring data between dynamic random access memory 2 and serial access memory 4.
Dynamic random access memory 2 is accessed through data bus 6 by CPU 5 in a random sequence. Serial access memory 4 is controlled by CRT controller 7 to serially supply stored data in response to a serial clock signal which is externally applied thereto. Generally, a portion including dynamic random access memory 2 is called a RAM port, because it is accessed in a random sequence. A portion including serial access memory 4 is called a SAM port, because it is accessible in a serial sequence.
The memory cells in one row of dynamic random access memory 2 store the data to be displayed on one scanning line in the screen of CRT display 8. Thus, the memory cells in one row of dynamic random access memory 2 correspond to the one scanning line in CRT display 8. The data of the memory cells in one row of dynamic random access memory 2 is transmitted through data transferring bus 3 to serial access memory 4. Serial access memory 4 is responsive to externally applied serial clock signal to have the storage data serially read therefrom and displayed on the screen of CRT display 8 under the control of CRT controller 7.
While the data is being serially read from serial access memory 4, CPU 5 can access dynamic random access memory 2 through data bus 6. Therefore, even while the image data is being displayed on the screen of CRT display 8, CPU 5 can access video RAM 1 to carry out reading of the data, a processing of the read data and writing of the processed data. Therefore, in parallel with the display of the image data on the screen of CRT display 8, CPU 5 can process the image data, so that high-speed processing and displaying of the image data can be carried out.
Generally, a memory having a plurality of access ports is called a multiport memory. The video RAM shown in FIG. 7 has the two ports, i.e., RAM port accessed by CPU 5 and SAM port accessed by CRT controller 7, and thus is called a dual port memory. In the SAM port, data is read from serial access memory 4 in response to an externally applied serial clock signal. The access to the RAM port generally requires toggle of signals *RAS (row address strobe signal) and *CAS (column address strobe signal), so that the SAM port can be accessed at a higher speed than the RAM port.
The dual port RAM has the RAM port and the SAM port which can be independently accessed, so that it can achieve an image processing system which processes the image data at a higher speed than a conventional RAM having only one port, because, in the conventional RAM having only one port, CPU 5 cannot access the RAM and thus remains in a waiting state while the data is being read to the CRT display therefrom.
FIG. 8 shows a specific construction of the conventional video RAM. In FIG. 8, video RAM 1 is comprised of the RAM port including dynamic random access memory 2 (see FIG. 7) and the SAM port including serial access memory 4 (see FIG. 7).
The RAM port includes a memory cell array 9 in which dynamic memory cells are arranged in a matrix of rows and columns, an address buffer 11 which receives address signal bits A0-Aj applied to an address input terminal 10 and generates an internal address signal, a row address decoder 12 which decodes the internal row address signal supplied from address buffer 11 to select a corresponding row in memory cell array 9, a column address decoder 13 which decodes internal column address signal supplied from address buffer 11 to select a corresponding column in memory cell array 9 and connect the selected column to an I/O bus 16.
A RAM IO terminal 14 has a plurality of pin terminals, and a RAM input/output data WIO is formed of multiple bits. Memory cell array 9 is divided into blocks correspondingly to each RAM input/output data bit. Row address decoder 12 selects one row in each block of memory cell array 9, and column address decoder 13 selects one column in each block of memory cell array 9. The RAM port further includes a sense amplifier 17 for sensing and amplifying the data of the memory cells in the selected row in memory cell array 9, and I/O bus 16 for connecting the column selected by column address decoder 13 to a data input/output buffer 15. Data input/output buffer 15 produces, in the data writing operation mode, internal write data from data WIOi supplied to RAM IO terminal 14 and transmits the same to I/O bus 16. In the data reading operation, data input/output buffer 15 produces external read data WIOi from internal read data on I/O bus 16 and transmits the same to terminal 14.
The SAM port includes a serial register 18 having a memory capacity for storing the data for one row in memory cell array 9, and a serial selector 21 for sequentially connecting unit registers included in serial register 18 to a serial data input/output buffer 20. Serial data input/output buffer 20 produces, in the data writing operation, internal write data from serial data SIOi supplied to SAM IO terminal 19 and transmits the same to serial register 18. In the data reading operation, serial data input/output buffer 20 produces external data from data read from serial register 18 onto SAM IO terminal 19. Serial register 18 is divided into blocks, similarly to the block structure of memory cell array 9, which correspond to the pin terminals of SAM IO port 19, respectively.
Serial selector 21 receives an internal column address from address buffer 11 to designate a first address in serial register 18, and sequentially connects the data registers included in serial register 18 to serial data input/output buffer 20 in accordance with a serial shift clock signal SC generated by a timing generator 22.
Data transferring bus 3 is disposed between memory cell array 9 and serial register 18. Data transferring bus 3 is responsive to a transfer instructing signal supplied from timing generator 22 and bidirectionally transfers the data between memory cell array 9 and serial register 18.
Timing generator 22 is shown in FIG. 8 controlling only the data transferring operation of data transferring bus 3, but actually generates various internal control signals in accordance with externally applied control signals SC, DSF, *SE, *WB/*WE, *DT/*OE, *CAS and *RAS.
Signal *RAS provides a timing for generating an internal row address signal by address buffer 11, and activates the RAM port. Signal *RAS (row address strobe signal) is used also as a reference signal in determining the operation mode of the SAM port because it is determined in accordance with the combination of the states of the respective control signals at the falling edges of signal *RAS.
Signal *CAS is a column address strobe signal for providing a timing at which address buffer 11 generates the internal column address signal. Signal *CAS is used also as a timing signal for setting the first address to serial selector 19.
Signal *DT/*OE sets a data output mode in RAM port, and provides a timing for activating the data transferring operation of data transferring bus 3 and for transferring the data.
Signal *WB/*WE sets the RAM port at the data writing mode, and also sets a write per bit operation mode. This write per bit operation is an operation mode, in which intended pin terminals are masked against the data writing to memory cell array 9 from RAM IO terminal 14.
Signal *SE is a serial enable signal for enabling the SAM port.
Signal DSF is a signal for setting a special function of the video RAM, and indicates that the special function is to be set in the video RAM 1 when signal DSF is activated.
Signal SC is a serial clock signal, and provides a timing at which serial selector 21 connects the data register included in serial register 18 to serial data input/output buffer 21.
The access to the RAM port is carried out similarly to a conventional DRAM. Specifically, in response to signals *RAS and *CAS, row and column are selected in memory cell array 9, and the selected memory cells' data is sensed and amplified by sense amplifier 17. The read mode and write mode for the data are selectively set by signals *DT/*OE and *WB/*WE. If signal *DT/*OE is in an active state of "L", the RAM port goes to the data output mode. If signal *WB/*WE is in the active state of "L", RAM port goes to the data write mode.
Data input mode and data output mode of the SAM port is determined by the data transferring cycle which was carried out in the last cycle. When the data was transferred from the RAM port to the SAM port, i.e., from memory cell array 9 to serial register 18, the SAM port goes to the data output mode. When the data is transferred from the SAM port to the RAM port, the SAM port goes to the data input mode. Now, the read transfer cycle for transferring the data from the RAM port to the SAM port will be described below with reference to an operation waveform diagram of FIG. 9.
The read transfer cycle is designated by setting both signals *DT/*OE and DSF at "L" and setting signal *WB/*WE at "H" at the falling edge of signal *RAS. In this read transfer cycle, the RAM port entering the memory cycle by signal *RAS carries out the selection of one row in memory cell array 9 and the sense/amplification of the data of the selected memory cells, and thereafter the data of the selected memory cells are transferred through data transferring bus 3 to serial register 18 in response to the rise of signal *DT/*OE.
That is, in response to the fall of signal *RAS, address signal bits A0-Aj applied to address input terminal 10 are strobed and latched as a row address signal indicating a row address AX. Row address decoder 12 decodes the applied internal row address signal to select the row corresponding to row address AX in memory cell array 9. Then, sense amplifier 17 is activated, and the data of the memory cells connected to the selected row are amplified and latched.
When signal *CAS falls, address signal bits A0-Aj, which have been applied before this fall, are latched as the column address signal indicating a column address AY. Column address AY also indicates a position of the register to be selected first in serial register 18. Serial selector 21 latches an address AY+1. The register in serial register 18 designated by column address AY is connected to serial data input/output buffer 20.
When signal *DT/*OE rises to "H" thereafter, timing generator 22 supplies a read transfer instructing signal RT. Data transferring bus 3 responds to read transfer instructing signal RT by simultaneously transferring the data of the memory cells on one row designated by address AX in the memory cell array 9 to serial register 18. Simultaneously with this data transfer, the data of the memory cell in memory cell array 9 designated by addresses AX and AY is held in serial data input/output buffer 20 through serial register 18.
After the rise of signal *DT/*OE to "H", the data which has been held in serial data input/output buffer 20, is supplied to the SAM IO terminal 19 in response to first applied serial clock signal SC.
Serial register 18 has the internal registers sequentially selected by serial selector 21 in response to serial clock signal SC to be connected to serial data input/output buffer 20. That is, the data of the memory cell designated by addresses AX and AY is supplied from input/output buffer 20, and subsequently the data at the address AY+1 is transmitted from serial register 18 to serial data input/output buffer 20 to be latched thereat. At this time, serial selector 21 latches an address AY+2.
When the serial clock signal SC is second applied thereafter, serial data input/output buffer 20 respectively supplies the data of address AY+1 held therein to the SAM IO terminal 19, and then latches the data of address AY+2 supplied from serial register 18.
The foregoing operation is repeated, so that the data of addresses AY+2, AY+3 . . . in serial register 18 is sequentially supplied to SAM IO terminal 19 upon each application of serial clock signal SC. The address of serial selector 21 is incremented one by one in accordance with serial clock signals SC.
Now, a write transfer cycle operation for transferring the data from serial register 18 to memory cell array 9 will be described with reference to an operation waveform diagram of FIG. 10. The write transfer cycle is designated by setting signals *WB/*WE, *DT/*OE and DSF at "L" and setting serial enable signal *SE at "H, at the falling edge of signal *RAS. In response to the fall of signal *RAS, address signal bits A0-Aj are latched as a row address signal for designating a row address ax in memory cell array 9, and row address decoder 12 selects corresponding one row in memory cell array 9. Then, in response to the fall of signal *CAS, address signal bits A0-Aj are latched as the column address signal indicating column address AY. In this operation, serial register 18 has already stored the valid data applied through serial data input/output buffer 20. In response to the rise of signal *DT/*OE, timing generator 22 generates write transfer instructing signal WT for transferring the data from serial register 18 to memory cell array 9, and write transfer instructing signal WT is applied to data transferring bus 3. Data transferring bus 3, in response to write transfer instructing signal WT, transfers the data stored in serial register 18 to one row on memory cell array 9 designated by the row address ax. Column address ay which is supplied in this time is held by serial selector 21 as a start address in the next serial write operation. Thereafter, upon each application of serial clock signal SC, data supplied to SAM IO terminal 19 is sequentially written in serial register 18, using address ay as a first or start address.
As described above, the read and write of the SAM port is switched by conducting the read transfer cycle and the write transfer cycle. Signal *SE is a signal for controlling the read and write of the SAM port. When signal *SE is in the inactive state of "H", the data is not written in serial register 18. In an operation waveform diagram of FIG. 10, when signal *SE is "H" at the falling edge of signal *RAS, a pseudo write transfer cycle is carried out. In this pseudo write transfer cycle, the operation similar to the write transfer cycle is carried out, but the data stored in serial register 18 is not transferred to memory cell array 9. The pseudo write transfer cycle is conducted for switching the SAM port from the data output mode to the data input mode. Generally, serial clock signal SC is not generated during the data transfer cycle operation in which data is transferred from serial register 18 to memory cell array 9.
In a processing of the image information at a high definition and high resolution, data to be processed has a remarkably large number of bits, and thus a large memory capacity is required for the dual port RAM (video RAM). The DRAM having the shared sense amplifier structure may be used as the DRAM forming the RAM port in order to achieve the large memory capacity as well as a small chip area and a low current consumption.
FIG. 11 shows a construction of a video RAM in which the DRAM of the shared sense amplifier structure is applied to the RAM port. Referring to FIG. 11, memory cell array 9 shown in FIG. 8 is divided into two memory cell arrays 9l and 9u. Between memory cell arrays 9l and 9u, there are provided a shared sense amplifier circuit 23 and column address decoder 13 commonly used by both of the arrays 9l and 9u. Shared sense amplifier circuit 23 includes sense amplifiers, each of which is normally connected to the column lines (bit line pairs) in memory cell arrays 9l and 9u. In operation, each sense amplifier is connected only to the memory cell array containing the selected row, and is isolated from the memory cell array which does not contain the selected row. Column address decoder 13 and I/O bus 16 are similar to those shown in FIG. 8. After the sense and amplification of the selected memory cells' data by shared sense amplifier circuit 23, column address decoder 13 selects and connects the corresponding column to I/O bus 16 in accordance with the column address signal supplied from address buffer 11.
A first serial register 24l and a second serial register 24u are provided corresponding to two memory cell arrays 9l and 9u, respectively. Serial selectors 21l and 21u set the first or start addresses of first and second serial registers 24l and 24u and also control the shifting operations thereof, respectively.
A data transferring bus 26l is disposed between memory cell array 9l and first serial register 24l. A data transferring bus 26u is disposed between memory cell array 9u and second serial register 24u.
Timing generator 22 is responsive to an array designating signal Ab (e.g., a highest bit in the row address) supplied from address buffer 11 to activate one of data transferring buses 26l and 26u (when the data transfer cycle is designated). A sense amplifier drive circuit 30 is provided in order to selectively connect each sense amplifier in shared sense amplifier circuit 23 to memory cell array 9l or 9u and to control the sensing operation of the same. Sense amplifier drive circuit 30 is responsive to the timing signal (generally, the internal of signal *RAS) supplied from timing generator 22 to generate a sense amplifier activating signal .phi.S, and is also responsive to array designating signal Ab and a control signal supplied from timing generator 22 to generate connection control signals SI(l) and SI(u) for controlling the connection between each sense amplifier in shared sense amplifier circuit 23 and memory cell arrays 9l and 9u.
According to the structure in which the sense amplifiers are commonly used by memory cell arrays 9u and 9l, the number of sense amplifiers can be reduced to a half as compared with the structure in which sense amplifiers are provided independently for each of memory cell arrays 9l and 9u, so that the area required for the sense amplifiers is reduced to a half, and the current consumption in the sensing operation is also reduced to a half. In this shared sense amplifier structure, the sense amplifiers are disposed between memory cell arrays 9l and 9u, so that the length of the bit lines in memory cell arrays 9l and 9u can be short, and thus a parasitic capacitance of the bit line can be reduced. Therefore, sufficient read voltages can be generated on the bit lines, and the stable sensing operation can be carried out at a high speed.
FIG. 12 shows a construction of a main part of the video RAM shown in FIG. 11. FIG. 12 shows only a part related to one shared sense amplifier 230, i.e., a part related to one column in each of memory cell arrays 9l and 9u.
In FIG. 12, memory cell array 9l includes bit lines 28a and 28b, word line WLl and a memory cell MC connected to word line WLl and bit line 28b. Bit lines 28a and 28b form a bit line pair to which memory cells in one column are connected. Word line WLl connects thereto memory cells in one row of memory cell array 9l. Serial register 24l includes a data register 240l which is provided corresponding to bit lines 28a and 28b of memory cell array 9l. Data transferring bus 26l includes a transfer gate 260l, which is responsive to a read transfer instructing signal RT1 and a write transfer instructing signal WT1 generated from timing generator 22 to transfer the data between data register 240l, and bit lines 28a and 28b.
Memory cell array 9u includes bit lines 29a and 29b, a word line WLu and memory cell MC connected to word line WLu and bit line 29b. Bit lines 28a and 28b form a pair to which memory cells in one column of memory cell array 9u are connected. Word line WLu connects thereto memory cells in one row of memory cell array 9u. Serial register 24u includes a data register 240u which is provided for bit lines 29a and 29b. Data transferring bus 26u includes a transfer gate 260u, which is responsive to a read transfer instructing signal RT2 and a write transfer instructing signal WT2 supplied from timing generator 22 to transfer the data between data register 240u, and bit lines 29a and 29b. Data registers 240l and 240u are provided corresponding to bit line pair 28a and 28b, and to bit line pair 29a and 29b, respectively. Serial registers 24l and 24u have storage capacities sufficient for storing the data of the memory cells in one row of memory cell arrays 9l and 9u, respectively.
Shared sense amplifier circuit 23 includes shared sense amplifier 230, which senses and amplifies a potential on a pair of bit lines 28a and 28b, or on a pair of bit lines 29a and 29b in response to sense amplifier activating signal .phi.S. Generally, shared sense amplifier 230 includes cross-coupled n-channel MOS transistors (insulating gate type field effect transistors) and cross coupled p-channel MOS transistors. In FIG. 12, shared sense amplifier 230 is shown being activated in response to one control signal .phi.S.
Shared sense amplifier circuit 23 further includes a connection control gate 32 which is responsive to a connection control signal SI(1) to isolate bit lines 28a and 28b from shared sense amplifier 230, and a connection control gate 33 which is responsive to a connection control signal SI(u) to isolate bit lines 29a and 29b from shared sense amplifier 230.
In shared sense amplifier circuit 23, a column selecting gate is provided for connecting the column (i.e., bit line pair), which is selected by column selecting signal supplied from column address decoder 13, to the I/O bus. In FIG. 12, however, the column selecting gate is not shown for the convenience of clarification of the figure.
Now, the data transferring operation of the video RAM of the shared sense amplifier structure shown in FIGS. 11 and 12 will be described with reference to an operation waveform diagram of FIG. 13. The read transfer cycle and write transfer cycle are designated in a manner similar to that already described with reference to FIGS. 9 and 10. It is assumed that word line WLl in memory cell array 9l is designated in the following description.
In response to the fall of signal *RAS, address buffer 11 applies array designating signal Ab to timing generator 22 and sense amplifier drive circuit 30. Sense amplifier drive circuit 30, in response to the timing control signal supplied from timing generator 22 and array designating signal Ab, sets connection control signal SI(1) at "H" and the connection control signal SI(u) at "L, so that the memory cell array 9l including the selected word line WLl is connected to shared sense amplifier 230 while memory cell array 9u is isolated from the same shared sense amplifier 230. Thereby, bit lines 28a and 28b are connected to shared sense amplifier 230 through the gate 32, and bit lines 29a and 29b are isolated from shared sense amplifier 230 by the gate 33. After the fall of signal *RAS, row address decoder 12 selects word line WLl, so that the data of memory cell MC is transmitted to bit line 28b. When the potential difference between bit lines 28a and 28b increases to a sufficient value, sense amplifier activating signal .phi.S is generated, and shared sense amplifier 230 senses and amplifies the data on bit lines 28a and 28b. Then, data BL(l) and *BL(l) on bit lines 28a and 28b have values corresponding to the data read from memory cell MC.
In memory cell array 9u, word line WLu is in an unselected state, so that data BL(u) and *BL(u) on bit lines 29a and 29b hold a precharged intermediate potential (Vcc/2).
Then, timing generator 22 generates the transfer instructing signal. In the read transfer cycle, read transfer instructing signal RT1 is generated in response to the signal Ab. In write transfer cycle, write transfer instructing signal WTl is generated in response to the signal Ab. Transfer gate 260l transfers the data between data register 240l and bit lines 28a and 28b.
Connection control signal SI(l) has the level further increased from "H" in the selected state. This is done for transmitting the potential level of "H" amplified by shared sense amplifier 230 to bit line 28a or 28b without a signal loss at the gate 32.
When signal *RAS rises to "H" and sense amplifier activating signal .phi.S falls to "L" after the data transfer is completed, connection control signals SI(l) and SI(u) cause bit lines 28a, 28b, 29a and 29b to be mutually connected through sense and latch nodes of sense amplifier 230, to be precharged and equalized to the intermediate potential, i.e., precharged potential by precharging/equalizing means (not shown).
When word line WLu is selected, memory cell array 9u is connected to shared sense amplifier 230, and subsequently has the data transferred to and from serial register 24u through transferring bus 26u.
As described above, the RAM port of the shared sense amplifier structure accomplishes the small occupied area and low power consumption. The write and read of the data to and from serial registers 24l and 24u are performed similarly to the video RAM already described with reference to FIG. 8. In this case, one of first serial register 24l and second serial register 24u supplies and receives the data to and from serial data input/output buffer 20 in accordance with a signal DBS (data buffer select) supplied to timing generator 22 (signal path for this operation is not shown in FIG. 11).
In the video RAM of the shared sense amplifier structure described above, the data is transferred only between the memory cell array including the selected row and the associated serial register. Memory cell array 9l can transfer the data only to and from first serial register 24l through data transferring bus 26l. Memory cell array 9u can transfer the data only to and from second serial register 24u through data transferring bus 26u. However, memory cell array 9l cannot transfer the data through data transferring bus 26u to and from second serial register 24u, and memory cell array 9u cannot transfer the data through data transferring bus 26l to and from first serial register 24l. In the video RAM of this shared sense amplifier structure, serial registers 24l and 24u can transfer the data only to and from restricted rows (e.g., rows for the upper or lower half region on the screen). Meanwhile, in the video RAM shown in FIG. 8, serial register 18 can transfer the data to and from an arbitrary row in memory cell array 9. Therefore, in the video RAM of the shared sense amplifier structure shown in FIG. 11, there may be a disadvantage that image data cannot be processed at a high speed in some applications.
For example, in such a case that the same data is to be written in memory cell arrays 9l and 9u through serial registers 24l and 26u for the initial setting of arrays 9l and 9u, a following operation is required. That is; double buffer select signal DBS designating which register is employs is used to write the same data in first and second serial registers 24l and 24u, and then the data is transferred between first serial register 24l and memory cell array 9l and between second serial register 24u and memory cell array 9u. For this reason, an unnecessary time period is required in the initial setting operation for writing the same data both in first and second serial registers 24u and 24l.
For example, in the construction shown in FIG. 8, if the initial setting data is written in serial register 18, it is then required only to sequentially apply the row selecting signal from row address decoder 12 to select each row in memory cell array 9 for transferring the data. For the reason described above, as compared with the time period for writing the initial setting data through serial register 18 in FIG. 8 in memory cell array 9, the time period required for writing the initial setting data in first and second serial registers 24u and 24l becomes longer. Also, signal DBS must be used.
If the data transferring path is fixed, as is done in the video RAM of the shared sense amplifier structure shown in FIG. 11, the data cannot be exchanged between memory cell arrays 9u and 9l, and thus a high speed processing of the image data cannot be flexibly performed in some image processing applications (e.g., when the same image is to be displayed on both the upper and lower half regions of the screen).


Device for the detection and processing of optical radiations, comprising at least one quantum well having asymmetric composition, said well consisting of a stack of layers of materials having differing gaps.

1. Field of the Invention
The invention relates to a device for the detection and processing of optical radiations.
2. Discussion of the Invention
Long-wavelength optical detectors (greater than or equal to 5 micrometres) fall into two large main groups of devices:
Photoelectric effect semiconductor detectors. PA1 Photothermic detectors. PA1 The energy level E.sub.1 is the trap level and E.sub.2 the conduction band for the extrinsic photoconductors. PA1 The energy level E.sub.1 is the valence band, and E.sub.2 the conduction band for the intrinsic photoconductors, photovoltaics etc . . . PA1 (E.sub.2 -E.sub.1) is the barrier height in a Schottky detector. PA1 1. of operating readily at ambient temperature or slightly cooled, at high wavelengths (for example, more than 3 .mu.m). PA1 2. for detectors, of providing a very high impedance, even at ambient temperature, which permits a high amplification and a utilization as detector at ambient temperature. PA1 3. of all being capable of being manufactured by the technology of semiconductors and thus exhibiting a possibility of integration into a semiconductor system.
In the first case, these detectors operate only at low temperature. In fact, the principle of operation of these devices is based on the generation of free carriers by optical transition between 2 energy levels E.sub.1 and E.sub.2. Depending upon the type of application:
If an electromagnetic wave permits a transition (E.sub.2 -E.sub.1) of low energy value (110 meV, for example), the phonons at ambient temperature will be of sufficiently high energy (25 mev) and sufficiently numerous to cause this transition. In other words, the dark current is very large in such a device at ambient temperature and the detectivity of the photodetector (like its impedance) is extremely low (D*.sup..about. 10.sup.6 cm. .sqroot.Hz/W)
In the second case, that is to say in photo-thermic detectors, the increase in the temperature due to the absorption of the electromagnetic wave leads to a variation of the dielectric constant of a pyroelectric material. In contrast to the first group of devices (photoelectric effect semiconductor detectors), these detectors operate at ambient temperature. As optical transitions between associated levels are not involved, the electrical conductivity of these materials does not change, and the impedance of the capacitive structures remains very large, permitting high amplifications.

Device for the detection of optical radiations


Various embodiments of a cable clip having a clip housing configured to engage a casing to establish an operative connection with a portable device encased within the casing are disclosed.

Protective casings used to encase and protect a portable device are well known. Typically, cables used to transmit data and/or power to the portable device encased in the protective casing can easily become detached when jostled or jarred by an external impact or entanglement. As such, data and power transmission can be interrupted when the cable becomes detached from the protective casing, thereby leading to loss of power or incomplete data transmission to the portable device.
It is with these observations in mind, among others, that various aspects of the present disclosure were conceived and developed.
Corresponding reference characters indicate corresponding elements among the view of the drawings. The headings used in the figures do not limit the scope of the claims.


A five-level feed-back digital-to-analog converter (DAC) in a switched capacitor sigma-delta analog-to-digital converter has an improved switching sequence that boosts from two to five the number of quantization levels of the feed-back DAC. Switching sequences are used to obtain five equally distributed charge levels C*VREF, C*VREF/2, 0, −C*VREF/2 and −C*VREF. When summed with an input voltage, VIN, the five-level feed-back DAC produces five equally distributed output voltages of A*VIN+VREF, A*VIN+VREF/2, A*VIN+0, A*VIN−VREF/2 and A*VIN−VREF, where A is gain, VIN is the input voltage, and VREF is the reference voltage.

Analog-to-digital converters are in widespread use today in electronics for consumers, industrial applications, etc. Typically, analog-to-digital converters include circuitry for receiving an analog input signal and outputting a digital value proportional to the analog input signal. This digital output value is typically in the form of either a parallel word or a serial digital bit string. There are many types of analog-to-digital conversion schemes such as voltage-to-frequency conversion, charge redistribution, delta modulation, as well as others. Typically, each of these conversion schemes has its advantages and disadvantages. One type of analog-to-digital converter that has seen increasing use is the switched capacitor sigma-delta converter.
As many analog-to-digital converters, the switched capacitor sigma-delta converter uses a digital-to-analog converter in a feedback loop and cannot be more accurate than the digital-to-analog converter. Therefore a very accurate digital-to-analog converter is required in order to achieve an accurate analog-to digital conversion. However a high resolution is not required for the digital-to-analog converter used in the feedback loop of a sigma-delta converter: The digital-to-analog resolution can be exchanged with the over-sampling ratio at the cost of a longer conversion time.
A two-level digital-to-analog converter is inherently accurate and thus is not the limiting factor for the accuracy of a sigma-delta converter. Therefore it is the standard approach in a sigma-delta analog-to-digital converter.
However, what is needed is a reduction in quantization noise, over sampling ratio and power consumption of the sigma-delta analog-to-digital converter. Such a reduction is sometime achieved with a multi-level digital-to-analog converter but with the cost of an expensive trimming or a complicated dynamic element matching technique.

Five-level feed-back digital-to-analog converter for a switched capacitor sigma-delta analog-to-digital converter


A printed wiring board includes a core substrate including an insulative substrate, a first conductive layer formed on first surface of the insulative substrate, and a second conductive layer formed on second surface of the insulative substrate, a first buildup laminated on first surface of the core and including an interlayer insulation layer, a conductive layer formed on the insulation layer, and a via conductor penetrating through the insulation layer and connected to the conductive layer, and a second buildup laminated on second surface of the core and including an interlayer insulation layer, a conductive layer formed on the interlayer insulation layer, and a via conductor penetrating through the insulation layer and connected to the conductive layer. The insulation layer of the first buildup has thermal expansion coefficient set higher than thermal expansion coefficient of the insulation layer of the second buildup.

1. Field of the Invention
The present invention relates to a printed wiring board having a core substrate and upper and lower buildup layers.
2. Description of Background Art
Japanese Laid-Open Patent Publication No. 2011-100908 relates to a printed wiring board having through holes (penetrating holes) formed using a laser. The printed wiring board of Japanese Laid-Open Patent Publication No. 2011-100908 has through holes that become narrower from an upper surface of the core substrate toward a lower surface and through holes that become narrower from the lower surface toward the upper surface so that warping of the printed wiring board is reduced. Semiconductor devices may be manufactured by mounting IC chips on printed wiring boards. Such mounting may be conducted through a reflow process. The entire contents of this publication are incorporated herein by reference.


A computer system for providing user support in editing graph structures includes a memory, a display, and a processor cooperatively operable with the display and the memory. The processor, based on instructions stored in the memory, causes the display to present, on a user interface, a visualization of a graph structure that includes one or more connections and one or more objects. Each of one or more connections represents a connection of two or more objects. In response to an action by user that selects at least one of the one or more connections and one or more objects, the processor causes the display to present, on the user interface, in real time, a support that indicates an allowable modification to the graph structure based on a methodology to which the graph structure is assigned and the selection of the one or more connections and one or more objects.

Graph structures are widely used in the software industry to describe and support models of various types. When designing a graph structure, it is necessary to keep the graph consistent and to maintain graph integrity. That is to say, changes in the graph structure, whether by deletion or addition, must not result in a break in graph structure flow.
Designing a graph structure is necessarily based on certain methodologies and according to semantic rules.
Unfortunately, current modeling technology provides user interfaces that necessitate trial and error user actions, and consequently can be very cumbersome for the user who must maintain integrity of the graph structure. Current modeling technology does not provide a framework which sufficiently supports a user.

System and method for providing user support in designing graph structures


A method is provided for managing virtual networks wherein switching hubs, each having ports to which nodes are respectively connected and having a bridging function, are interconnected via an ATM network, and predetermined ones of the ports of the switching hubs are grouped in order to construct virtual LANs. Data from a source node is transmitted to nodes belonging to the same group as the source node. A VLAN server, which stores MAC addresses of these nodes and VLAN identifiers in association with each other, is connected to the ATM network and collectively manages all nodes by means of the MAC addresses. The switching hub makes an inquiry for a VLAN identifier, and reconstructs or modifies the VLAN in accordance with a VLAN identifier responded from the VLAN server.

1. Field of the Invention
This invention relates to a virtual network management method for managing virtual networks, for example, virtual LANs or the like, which are configured over a backbone network such as an ATM (Asynchronous Transfer Mode) network.
2. Description of the Related Art
In the case of using switching hubs as connecting devices connected to a high-speed network such as an ATM network, it is conventionally known to construct a plurality of separate LANs (virtual LANs) irrespective of physical configuration.
The configuration of a typical virtual LAN will be explained below. In the virtual LAN, a switching hub which is designed according to, for example, the standard ATM-IEEE 802.3 (hereinafter merely referred to as "switching hub") has an ATM interface for high-speed backbone. Utilizing LAN Emulation standardized by the ATM Forum, the switching hub transfers a packet structured according to the standard IEEE 802.3 (hereinafter merely referred to as "packet") to an ATM-side interface.
With LAN Emulation, it is possible to construct a plurality of different emulated LANs (hereinafter referred to as "ELANs"). Namely, according to LAN Emulation, software permits any one of switching hub ports which are designed in conformity with the standard IEEE 802.3 (hereinafter merely referred to as "ports") to be allocated to a desired ELAN. Consequently, a plurality of independent LANs (virtual LANs) can be constructed without reconfiguring physical wiring. A broadcast packet is inhibited from passing through different virtual LANs, and nodes belonging to different virtual LANs are isolated from one another and are unable to communicate directly.
In such virtual LANs, since the individual ports are allocated to different networks by means of software, there arises a difference between the physical wiring and the actual networks, making it difficult to grasp the network configuration. Also, it is unnecessary to reconfigure the hard wiring each time the networks are modified; however, when network modification is made by means of software, virtual LANs must be set manually with a thorough understanding of the hardware connections, requiring considerable time and labor for the settings.
Here let it be assumed that network wiring is installed, for example, in a building and that switching hubs are arranged on the individual floors of the building. The wiring for the switching hubs is extended above ceilings or behind walls and the individual ports are arranged in the form of sockets at predetermined locations on the floors. To each socket is connected a 10 Base-T type hub which in turn is wired to respective nodes in a group or department, followed by the setting of virtual LANs.
With such network wiring installed, there may arise a situation where the nodes of a department at a certain location on the second floor are moved to the first floor and connected to sockets of the switching hub on the first floor. In such a case, the virtual LAN setting for a conventional network system involves checking and setting the port number of the switching hub having sockets to which the nodes were newly connected. It is therefore necessary to grasp with accuracy the wiring relationship between the sockets and physical ports connected thereto.
In practice, however, it is difficult to keep a thorough understanding of the port numbers of the switching hubs in relation to the sockets connected thereto, inclusive of the wiring within the building. Especially in the case of a larger-scale network, the difficulty in the virtual LAN settings through the switching hubs increases for the above reason. If a setting error exists because of erroneous information about the port numbers, there is a possibility that a grave communication fault will occur in the network. Consequently, modification of the virtual LAN settings during operation of the network is always accompanied by great risks that can affect the LAN operation.
In view of the foregoing, there has conventionally been proposed a concept of relational LAN wherein packet protocols or network numbers are detected, and identical network protocols or identical network numbers are automatically allocated to the same virtual LAN, as described on pages 58-81 of Nikkei Communications, No. 186 (Nov. 21, 1994 issue, Japan). The relational LAN facilitates the reconstruction of virtual LANs according to identical protocols or identical network numbers as well as modification of the virtual LANs, thus making it possible to modify the virtual LANs while the network is in operation.
The concept of relational LAN involves the function of isolating networks with the same network number from one another or making different networks coexist on the same virtual LAN, the security function of excluding a network node that was added on purpose to cause a network fault, and other functions. When these functions are executed on the virtual LAN, however, calculations must be performed taking account of upper-layer frames and thus are complicated, entailing difficulty in achieving the functions. It is also necessary that all protocols such as IP (Internet Protocol) and IPX (Internet Packet eXchange) should be recognized and handled, requiring complicated operation.

Method of managing virtual networks using a virtual network identifier


A gas discharge display panel in which opaque bus electrodes are structured in a frame shape for making each display cell clear as viewed from outside of the front substrate, and the bus electrodes function as a black matrix of the display screen. Hence the integrity of the black display status is improved and the contrast is increased.

The present invention relates to a gas discharge display panel, such as a plasma display, and, more particularly, to an AC driving type gas discharge display panel having a high contrast. The invention also relates to a manufacturing method for a gas discharge display panel and to a display unit, such as a monitor, using a gas discharge display panel.
A gas discharge display panel, such as a plasma display, produces a display by its own light emission, so that the view angle is wide and the display is clearly visible. It has characteristics such that a thin panel can be produced and a large screen can be realized, and so application of a gas discharge display panel to a display unit of an information terminal device, a high-quality TV receiver, and similar display devices can be expected.
Gas discharge display panels are broadly divided into the DC driving type and the AC driving type. The AC driving type plasma display panel has a memory function by the action of a dielectric covering the electrodes and the brightness thereof is high. Recently, by application of a protective film, a life span fit for practical use has been realized and the AC driving type panel has been put to practical use as a multipurpose video monitor.
FIG. 9 shows a partial perspective view of the structure of a conventional plasma display panel. This gas discharge color display panel has a rear substrate 2 and a front substrate 1 which are arranged opposite to each other. The rear substrate 2 has a barrier rib 3a for maintaining the gap with the front substrate 1 constant, and the front substrate 1 and the rear substrate 2 are connected to each other via this barrier rib 3a. In FIG. 9, the front substrate 1 and the barrier rib 3a of the rear substrate 2 are separated from each other for ease of illustration of the structure.
The front substrate 1 has display electrodes (transparent electrodes) 61 and 71, bus electrodes 62 and 72, a dielectric layer 8, and an MgO film (protective film) 9 formed on a front glass plate 4. The rear substrate 2 has an address electrode 14, a barrier rib 3a, and a fluorescent layer 12 formed on a rear glass plate 5. The front substrate 1 and the rear substrate 2 are arranged and stuck in parallel relationships to each other so that the surfaces with electrodes face each other and a discharge space 3f is formed between the front substrate 1 and the rear substrate 2. The display electrodes 6 and 7 and the address electrode 14 are arranged on both sides of the discharge space 3f so as to cross at right angles.
Cross-sectional views of the gas discharge display panel are shown in FIGS. 10a to 10c and 22. FIG. 10a is a cross-sectional view of a part of the display panel of this embodiment as seen on a plane which is parallel with the address electrode 14 and perpendicular to the surfaces of the substrates 1 and 2. FIG. 10b is a cross-sectional view at the position 10B shown in FIG. 10a and the section thereof is on a plane which is perpendicular to the address electrode 14 and perpendicular to the surfaces of the substrates 1 and 2. FIG. 10c is a cross-sectional view at the position B shown in FIG. 10a and the section thereof is a plane which is perpendicular to the address electrode 14 and perpendicular to the surfaces of the substrates 1 and 2. In FIGS. 10a to 10c, only the sections are shown so as to make the drawings more easily understood, and the illustration of the constitution which will be seen behind each view is omitted. The cross-sectional view on the plane indicated by 22 shown in FIG. 10a is shown in FIG. 22.
As shown in FIGS. 10b and 10c, between the substrates 1 and 2, a display cell (also referred to as a discharge cell) is formed for each combination of the display electrodes 61 and 71 and the discharge space 3f is formed by both the substrates 1 and 2 and the barrier rib 3a. Inside this discharge cell, the fluorescent layer 12 is formed. The space 3f in the cell is charged with discharge gas. In this conventional display panel, as shown in FIG. 22, the barrier ribs 3a are parallel bar-shaped ribs, and the discharge spaces 3f of the cells which are continued transversely (or longitudinally) are not separated by the barrier ribs 3a. FIG. 22 is a parallel cross-sectional view of the discharge space.
When a pulse voltage is applied between the electrodes 6 and 7 of the front substrate 1 and the address electrode 14 formed on the rear substrate 2, an auxiliary discharge is generated in each cell formed by the front substrate 1, the rear substrate 2, and the barrier ribs 3a. On the surface of the protective layer 9 covering the parallel electrodes 6 and 7 formed in the front substrate 1 for each cell, a wall charge is formed using this auxiliary discharge. When a pulse voltage is applied between the electrodes 6 and 7 with the wall charge formed, a main discharge is generated. Ultraviolet light generated by this main discharge causes the fluorescent layer 12 coated inside each cell to emit light. The display of this display panel is realized by light from this fluorescent layer 12 which can be observed through the front substrate 1.
An example of the gas discharge display unit described above is set forth in Outsuka; Flat Panel Display 1994, pp. 198-201).
However, in the aforementioned publication, the display cells arranged in the extending direction of the address electrode 14 are separated only by the relative position of the display electrodes 6 and 7, and so, to prevent improper discharge between adjacent display cells, it is necessary to increase the distance between the display electrodes of adjacent display cells. The space between the display cells does not contribute to the display, but causes light blurring and color mixture by light emission of the existing fluorescent layer 12. The display electrodes 6 and 7 have the bus electrodes 62 and 72 for lowering the electrode resistance, and there exist many barrier ribs between the display cells arranged in the extending direction of the display electrodes. The bus electrodes are formed by an opaque material, so that they do not contribute to the display. The bad effect produced by the existence of the bus electrodes is increased when the electrodes are widened so that the electrode resistance is lowered. The existence of a portion around the display cells which does not contribute the display lowers the aperture ratio of the panel, so that a reduction in brightness is caused. Light emission between the display cells and the existence of the barrier ribs 11, which are not black, cause a reduction in the integrity of the black display status. In the display panel disclosed in the aforementioned publication, it is difficult to lower the brightness in the dark state and increase the brightness in the bright state, as mentioned above, and so a high contrast cannot be realized.

Gas discharge display panel and manufacturing method thereof


This invention relates to a method of encapsulating nano-dimensional structures, comprising: depositing at least one material upon a substrate such that the material includes at least one portion; and creating an oxidized layer located substantially adjacent to the deposited material such that the at least one portion of the deposited material becomes substantially encapsulated by a portion of the oxidized layer.

1. Field of the Invention
This invention relates to a method of encapsulating nano-dimensional structures, comprising: depositing at least one material upon a substrate such that the material includes at least one portion; and creating an oxidized layer located substantially adjacent to the deposited material such that the at least one portion of the deposited material becomes substantially encapsulated by a portion of the oxidized layer.
2. Description of the Related Art
Prior to the present invention, as set forth in general terms above and more specifically below, it is known, that industrial interest in materials having structural and functional features with nanoscale dimensions has been growing rapidly. Nano-structures have been fabricated by semiconductor processing techniques including patterning techniques such as photolithography, electron-beam lithography, ion-beam lithography, X-ray lithography, and the like. Other nano-structures have also been fabricated utilizing structures formed by self-ordering processes.
It is further known that such small objects require novel and specialized methods of fabrication and subsequent processing. One common task is localized encapsulation of conductors or sensing surfaces. With increasing complexity of nanostructures, it will be more and more difficult to insulate certain regions of the device, while leaving others intact or exposed to the environment. At present, the most common and direct approach to encapsulation is to mask the relevant part of the device and cover it with a protective (insulating) layer. However, this general approach is difficult to implement when coverage of the device areas adjacent to the area being insulated is undesirable because it may interfere with the device's operation. In such cases, very precise masking processes (alignment, deposition, etc.) are required, which would be difficult to achieve at the nanoscale level.
As an example, consider the edge of a 100 nm stack of 10 nm thick layers alternating between conducting and insulating layers. Such an edge would be very difficult, if not impossible, to insulate using the traditional mask and deposit approach, without depositing material on the top face of the structure, which may be undesirable. Such a situation requires a localized means of encapsulation and protection of the conductive edges of the conductive layers. Consequently, a more advantageous nanostructure encapsulation system, then, would be provided if inexpensive and accurate methods of encapsulation could be developed.
It is apparent from the above that there exists a need in the art for an encapsulation system that is inexpensive, effective, and capable of localized encapsulation of the conductors or sensing surfaces. It is a purpose of this invention to fulfill this and other needs in the art in a manner more apparent to the skilled artisan once given the following disclosure.

Encapsulation of nano-dimensional structures by oxidation

Hewlett-Packard Development Company, L.P.


A parallel computer architecture incorporates a new register file organization for parallel ALUs that provides improved performance due to reduced off-chip crossings and locally higher density. Each ALU is provided with its own, smaller register file located on the ALU chip. Data written by one ALU is "broadcast" to all the "local" register files. This arrangement of "local" register files minimizes the number of pins required and, using very large scale integration (VLSI) techniques, high densities can be achieved. These "local" register files eliminate off-chip delays, and performance is further enhanced by the shorter wire lengths in the local register files.

1. Field of the Invention
The present invention generally relates to parallel computer architectures and, more particularly, to a Very Long Instruction Word (VLIW) computer architecture having multiple arithmetic logic units (ALUS) with an optimal register file organization within chip boundaries to minimize off-chip crossing delays and to maximize communications between the ALUS.
2. Description of the Prior Art
There is a diversity of parallel computer architectures. Michael J. Flynn in "Very High Speed Computing Systems", Proceedings of the IEEE, Vol. 54, 1966, pp. 1901-1909, adopted a taxonomy to classify architectures based on the presence of single or multiple streams of instructions and data. There are generally four categories defined as follows:
SISD (single instruction, single data stream) which defines serial computers.
MISD (multiple instruction, single data stream) which involves multiple processors applying different instructions to a single data stream.
SIMD (single instruction, multiple data streams) which involves multiple processors simultaneously executing the same instruction on different data streams.
MIMD (multiple instruction, multiple data streams) which involves multiple processors autonomously executing diverse instructions on multiple data streams.
Using Flynn's taxonomy, the subject invention is related to architecture that may be loosely described as being MISD. In more detail, the computer architecture relevant to the invention is SISD in the sense that there is a single instruction stream operating on a single stream of data. However, unlike conventional SISD processors, each of the "single" instructions contains multiple operations. For example, a "single" instruction may include eight arithmetic operations, several load/store operations, and a multiple-way branch. The term that is attached to such processors is VLIW for Very Long Instruction Word. A description of a particular version of a VLIW computer architecture is provided by K. Ebcioglu in "Some Design Ideas for a VLIW Architecture for Sequential-Natured Software" published in Parallel Processing, M. Cosnard et al., editors, pp. 3-21, North Holland, 1988.
The connection between the VLIW and a conventional sequential machine is the VLIW compiler which, in principle, accepts a program for a sequential machine and re-compiles that program into VLIW instructions, with re-ordering of instructions taking place to keep the multiple operations of the VLIW hardware active while preserving the net effect of the original sequential program. Thus, from the point of view of the original sequential code, the engine is MISD; but from the point of view of the VLIW instructions, it is SISD.
The subject invention implements a VLIW parallel architecture employing register files. In the application of conventional multiport register file techniques to VLIW machines, the large number of ports quickly creates size and performance problems. One approach to the problem was presented by Junien Labrousse and Gerrit A. Slavenburg in their paper entitled "A 50 MHz Microprocessor with a Very Long Instruction Word Architecture" at the 1990 IEEE International Solid-State Circuits Conference, Feb. 14, 1990. Their 32-bit VLIW chip consisted of several independent functional units controlled on a cycle-by-cycle basis by a 200-bit instruction. The functional units include two identical 32-bit ALUS, a 32-bit data memory interface, a register file, a constant-generation unit and a branch unit. All units are connected to a shared on-chip multiport memory from which the ALUs take operands and into which results are written. Any previously computed result can be used as an operand by either ALU.
In order to gain the necessary bandwidth, the multiport memory of the Labrousse et al. VLIW architecture required a special design with each operand of each functional unit having a local storage unit called a funnel file. All functional units and funnel files are located on both sides of a crossbar switch. The register file is considered as but one of the functional units and, therefore, access to the register file by the ALUs is through the multiport memory.

IC chips including ALUs and identical register files whereby a number of ALUs directly and concurrently write results to every register file per cycle

International Business Machines Corporation


The present invention concerns a receiver and an error correction method at a receiver, comprising the steps of receiving data information from a broadcast network in a sequence of packets, detecting a first packet within the sequence of packets being a corrupted packet, identifying a packet identifier and a sequence number of the first packet, requesting, on a second network, to receive a transport packet identified with the sequence number and comprising the first packet and receiving the first packet embedded in the transport packet, from the second network.

This section is intended to introduce the reader to various aspects of art, which may be related to various aspects of the present invention that are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Communication systems are generally subject to transmission errors. In broadcast systems, error correction is used to improve transmission robustness. Forward Error Correction (FEC), based on the addition of redundant information, performs error correction without the need of repeating information and without using a return channel. FEC is commonly used on communication networks, such as terrestrial, mobile or satellite networks. Another correction mode uses repetition, where data is sent several times to the receivers. Repetition may be performed on demand from a receiver, where the receiver detects an error and requests repetition to the transmitter. This is possible when a return channel is available. The return channel is used by a receiver to send a request to the transmitter for repeating lost or corrupted information.
In the digital television domain, television decoders, also called set-top boxes, are used to access a set of television channels that are transmitted with encryption and that are decrypted within the decoder. Television decoders are the interface units between the television signal transmission systems, notably digital television signals in MPEG and DVB format, and the display monitors. The transmission means that broadcast the television transmissions to these decoders can be standard aerial transmission means, coaxial cables, optical cables, re-transmission satellites serving a region, or the Internet network. The decoder comprises the reception means to receive the transmitted signals and the formatting means to transform the received signals into signals that can be directly applied to the display device command units. The decoder also usually comprises error detection and error correction means. They are bound to the broadcast transmission means. In particular, in a satellite transmission system, the forward error correction may be used. In a transmission over the Internet Protocol, retransmission may be used.
Set-top boxes are today adapted to receive content from at least two networks, such as the Internet and the terrestrial transmission system. Broadcast video is usually transmitted in the broadcast network, the Internet network being used for interactive services. When receiving video content from the unidirectional terrestrial distribution network, the forward error correction mechanism available on that distribution network is used. However transporting FEC packets may be burdensome and costly for the distribution network. It would be valuable to minimize the impact of the error control over the broadcast network.

Digital receiver and corresponding digital transmission system server


Methods for the authentication of a web site by a visitor to the web site. The visitor uses a device, such as a portable device like a cell phone to compute a dynamic identification string and a one-time password. The dynamic identification string is sent to a service provider, such as a certification service server associated with the web site. In response, the server computes a one-time password that is transmitted to the visitor's device. The device computed one-time password can then be compared to the server computed one-time password in order to authenticate the web site.

Various service providers (e.g., financial institutions, banks, brokers, merchants, etc.) are often involved in transactions requiring the identification and validation of a remote entity (e.g., an individual, organization, smart card, message, account, etc.) and the certification of transaction data. These service providers often provide their services to remote entities over the Internet in what is often referred to as electronic commerce (e-commerce). One of the limitations of e-commerce is that the remote entity requires a personal computer or similar device to complete the transaction. In addition, the remote entity requires the necessary skills for utilizing the Internet.
Recently, there have been intense efforts to develop technology for bridging the gap to remote entities that do not have access to the Internet in order to make e-commerce more widely available. This emerging technology (e.g., Web Telephony Engine of Microsoft) often makes use of a voice browser. A voice browser is software that executes on a personal computer or similar device, and "understands" spoken instructions by utilizing speech recognition technology and "reads out" text by using text-to-speech technology. The voice browser is used by a remote entity to browse the internet over a voice line such as a telephone line. Thus, voice browsers enable a remote entity to perform an internet transaction over a phone. In order to identify himself, the caller or consumer can use a smart card, or other known technology. However, these identification activities are limited in that additional hardware is required (e.g., a card reader) and certain telephones (e.g., public phones) cannot be utilized.
Regardless of whether the transaction takes place over a telephone, the Internet (including voice over IP) or other telecommunications media, it is important for service providers to ensure during each transaction that the remote entity is not an impostor. Accordingly, service providers often employ various identification devices to identify and validate remote entities, these devices being referred to herein as Identification Devices. For ease of discussion, a remote entity authorized to engage in transactions, but perhaps not yet identified and/or authenticated by an Identification Device for a particular transaction, is referred to herein as an "Authorized Remote Entity" or "Authorized Entity."
One method commonly known in the art and employed by Identification Devices for securely identifying a remote entity is to add "authentication" to an otherwise normal identification process. Authentication is typically accomplished by providing an additional piece of information to an Identification Device, e.g., a secret code, along with identification information. This additional information then may be used to corroborate that the identification is accurate and that the remote entity is not an impostor attempting to impersonate an authorized entity. The additional piece of information is often a secret code or a password (e.g., PIN), but also may be a Dynamic Code, preferably computed using a software implemented algorithm. Alternatively, the additional information may be provided by a token (e.g., Bio-Token) carried by the entity (e.g., individual) to be identified.
Non-variable (i.e., constant or static) information or data (e.g., PIN) can only add limited security to the identification process because a static piece of information eventually may become known to a third party (e.g., potential attacker/impostor/eavesdropper) in which case an authorized entity can easily be impersonated. On the other hand, authentication by means of a variable piece of information (referred to herein as a Dynamic or One Time Code) provides enhanced security.
Currently known methods of authentication which use a Dynamic or One Time Code typically require a prior step of identifying the remote entity to the Identification Device, e.g., by providing a name (e.g., a login name), a serial number, an additional fix code, etc. as part of a message transmitted from a Remote Entity to an Identification Device. This constant part of a message will be referred to herein as an Identification Message. Thus, a method commonly employed by an Identification Device to securely identify a Remote Entity by authentication typically comprises the three following steps:
Identification: identify who the Remote Entity is supposed to be, by receiving a constant (non-variable, or at least non-constantly-variable) piece of information, referred to herein as an Identification Message;
Database Search: the Identification Devices searches a database containing the Authorized Entity's secret information or computing keys, to compute a dynamic piece of information (referred to herein as a Valid Dynamic Code) which is associated with and expected from the Authorized Entity at that particular moment; and
Authentication: the Identification Device compares the Valid Dynamic Code (computed at the Identification Device) with a Dynamic Code received from the Remote Entity (referred to as the Received Dynamic Code) to check if both codes match; if so, the Identification Device corroborates the identification of the Remote Entity as being the Presumed Entity.
A variation of the above-described authentication method is referred to as the Challenge and Response method, comprising the following steps:
The Remote Entity is identified (as described in step 1 above);
The Remote Entity receives a Challenge generated and sent by the Identification Device and computes a Response, the Response playing the role of a Dynamic Code;
The Identification Device, after identifying the Remote Entity (the Pre-Authentication Identification), searches a database containing the Authorized Entity's secret information or computing keys, to determine the expected response to the challenge, for that Remote Entity at that moment.
Each of the authentication schemes described above requires the Identification Device to employ a database or look-up table. Naturally, each database must be maintained and updated, which creates problems associated with the management of keys, synchronized database updates, etc. Furthermore, these problems become acute when a service provider utilizing an authentication process has a multitude of Identification Devices disseminated through several countries.
Another problem associated with conventional schemes for Remote Identification is the possibility of "repudiation" by an identified and authenticated Remote Entity. For example, a Remote Entity, which has been identified and authenticated as being an Authorized Entity, may later deny the genuineness of a particular communication or event under scrutiny. To illustrate, in the case of a Gambling Service Provider (although identification and authentication techniques may apply to any service provider, Gambling Service Providers are used for this example), Remote Entities (e.g., gamblers) may place bets from remote locations and pay for those bets using Credit Cards. Naturally, before a particular Remote Entity places any bets, the Gambling Service Provider identifies and authenticates that Remote Entity by a procedure similar to those described above. Once the bets have been placed, one of the Remote Entities wins a prize, while all of the remaining Remote Entity gamblers lose. This situation presents an opportunity for any number of losing Remote Entities to repudiate their particular betting transaction, including the identification and authentication process, claiming that they never made the transaction/bet, and that the Gambling Service Provider fabricated the transaction or made a mistake. Because each Remote Entity is authenticated by the Provider's Identification Device, and further because the provider includes a database containing secret information, the Provider has the capability to compute as many Valid Dynamic Codes as the Gambling Service Provider may desire, and an unscrupulous Gambling Service Provider thereby has the ability to fabricate transactions. Accordingly, when a Remote Entity repudiates a transaction, there is no way to prove whether the Gambling Service Provider fabricated the transaction or the Remote Entity has repudiated a valid transaction. Of course, if all the losing Remote Entities repudiate their transactions, the effect on the Gambling Service Provider may be disastrous.
As illustrated in the example above, present methods of authentication intrinsically are subject to the negative effects of transaction repudiation, due to the fact that the receiving/identifying/authenticating side of each transaction has the capability to compute a secret Dynamic Code as accurately as the Remote Entity.
A further drawback of authentication methods known in the art and described above is the fact that a Remote Entity is trackable. In other words, an eavesdropper may follow every transaction made a particular Remote Entity because that Remote Entity transmits the same constant identification information for every transaction. This ability to track a Remote Entity creates a lack of security and privacy for many Remote Entities (e.g., especially government officers, ministers, police officers, etc.).
In addition, another problem encountered is the impersonation of a service provider by a third party. For example, a third party may impersonate a service provider in order to obtain information from the remote entity without the remote entity's knowledge. The third party may then use the obtained information to complete transactions to the detriment of the remote entity.
Thus, a new method and apparatus for the identification of a remote entity is needed that overcomes the limitations and problems of the prior art.

This patent is subject to a terminal disclaimer.

Method and apparatus for the secure authentication of a web site