A semiconductor integrated circuit includes: a first n-well defined in a p-type semiconductor region; word lines; data lines; and a DRAM array. In the array, memory cells are arranged in matrix over the first n-well. Each memory cell includes a p-channel MOS access transistor and a capacitor. The access transistor has its gate connected to an associated one of the word lines, its source connected to an associated one of the data lines and its drain connected to the capacitor. The integrated circuit further includes: a row of sense amplifiers coupled to the data lines; a word line driver for driving the word lines; and a power supply circuit. The power supply circuit receives an external supply voltage, generates internal supply voltages by stepping down the external supply voltage and then applies the internal supply voltages to the sense amplifiers, word line driver and first n-well.

The present invention relates to a semiconductor integrated circuit with a dynamic random-access memory (DRAM).
Recently, an LSI, in which a logic circuit, like a central processing unit (CPU) or application-specific integrated circuit (ASIC), and a DRAM have been integrated together on a single semiconductor substrate, has been the object of much attention. In the following description, a semiconductor integrated circuit of this type will be referred to as a xe2x80x9cDRAM-built-in LSIxe2x80x9d, which is also called an xe2x80x9cLSI with an embedded DRAMxe2x80x9d. A DRAM-built-in LSI is attractive, because an LSI of this type realizes various functions, which have had to be executed using multiple chips including logic and general-purpose DRAM chips, by a single chip.
For a DRAM-built-in LSI, there is no need to interconnect multiple chips together by way of long wires. In addition, the same bonding pad can be used for both the logic and memory circuits alike. Accordingly, the LSI occupies a smaller area when mounted on a circuit board. Furthermore, the shorter wire length contributes to decreasing the wiring capacitance and increasing the data transfer rate. Moreover, no drivers of a great size are needed anymore because those long wires can be eliminated. As a result, the power dissipation of the overall system can be reduced advantageously.
Hereinafter, a typical known DRAM-built-in LSI, including a stacked capacitor DRAM, will be described. In the LSI of this type, its logic circuit is implemented as a complementary metal-oxide semiconductor (CMOS) circuit.
FIG. 8 is a cross-sectional view schematically illustrating a structure for a known DRAM-built-in LSI including a stacked capacitor DRAM. The LSI shown in FIG. 8 includes p-type semiconductor substrate (p-SUB) 91, n-wells (NWs) 92 and 94, p-well (PW) 93, n-channel MOS (NMOS) memory access transistor 95, stacked memory cell capacitor 96 and NMOS and p-channel MOS (PMOS) transistors 97 and 98 for a logic circuit.
As shown in FIG. 8, the NWs 92 and 94 and the PW 93 have been defined in the p-SUB 91. Multiple n+- and p+-type doped regions have also been defined in the p-SUB 91. The NMOS memory access transistor 95 is connected to a data line BL and a word line WL. A supply voltage VDD is applied to the NWS 92 and 94, while a substrate bias voltage VBB, lower than the ground voltage, is applied to the PW 93.
In a DRAM-built-in LSI in general, the transistors and capacitors thereof are downsized to increase the operating speed of its logic circuit, and the transistors are integrated together highly densely in its DRAM to reduce the necessary chip area. As shown in FIG. 8, an NMOS transistor is used as the memory access transistor 95. On the other hand, the memory cell capacitor 96 has a three-dimensional structure (e.g., implemented as a stacked type) to produce a capacitance large enough to stabilize the operation of the DRAM. Furthermore, the PW 93 is included in the NW 92 that has been defined in the p-SUB 91, thus forming a so-called xe2x80x9ctriple well structurexe2x80x9d.
The PW 93, NW 92 and p-SUB 91 are supplied with such voltages that will make their pn junctions reverse biased.
Specifically, the p-SUB 91, NW 92 and PW 93 are biased to the ground voltage, the supply voltage VDD and a negative voltage VBB, which is lower than the ground voltage, respectively. The voltages VDD and VBB are output from a power supply circuit (not shown) formed on the p-SUB 91.
By forming the memory access transistor 95 and memory cell capacitor 96 over the triple well structure and by biasing those wells to these levels, the memory and logic circuits can be electrically isolated from each other. In addition, the threshold voltage of the memory access transistor 95 is set high enough so that the charges stored on the memory cell capacitor 96 do not leak into the data line BL by way of the memory access transistor 95.
The voltage on the data line BL will be somewhere between the ground voltage and the supply voltage VDD. To read or write data from/on the memory cell capacitor 96, a voltage higher than the supply voltage VDD by the threshold voltage of the memory access transistor 95 should be applied to the gate electrode of the transistor 95. Accordingly, either a voltage generated by an internal booster or an externally in-put voltage should be applied onto the word line WL.
In the logic circuit section on the other hand, the NMOS and PMOS transistors 97 and 98, existing over the p-SUB 91 and NW 94, respectively, form part of a CMOS logic circuit. In the CMOS logic circuit, the NMOS and PMOS transistors 97 and 98 operate mutually complementarily. Since the p-SUB 91 is biased to the ground voltage, the threshold voltage does not increase or the operating speed does not decrease.
A DRAM-built-in LSI of this type, however, requires a fabrication process much more complicated than a normal CMOS process. Also, a greater number of process steps or masks are needed, thus raising the fabrication costs disadvantageously. For example, the process steps of forming the triple well structure and forming the stacked memory cell capacitor should be carried out in addition to those of a normal CMOS process.
Moreover, where the stacked capacitor is formed over the data line, the upper electrode thereof should be located at a rather high level, thus increasing the aspect ratio of a via that connects the first- and second-level interconnects together. Accordingly, it is much more difficult to form such an interconnect structure. Furthermore, after the transistors have been formed for the CMOS logic circuit, a capacitive insulating film should be formed at an elevated temperature for the stacked capacitor. Thus, the transistors of the CMOS logic circuit might have their performance degraded.
Furthermore, a charge-pump-type voltage step-up power supply circuit should be provided to apply the voltage, higher than the supply voltage VDD, as a word line drive voltage. A charge-pump-type negative voltage power supply circuit should also be provided to bias the well, on which the memory cell will be formed, to the voltage lower than the ground voltage. These charge-pump-type power supply circuits, however, often cause a great, inconstant variation in the voltage supplied. This is a problem inevitable for the power supply circuits of this type due to their constructions. Accordingly, not so great a margin is allowable for the voltage or temperature range in which the DRAM can operate stably enough.
Considering the compatibility with the CMOS process, it would be more advantageous to integrate a static random-access memory (SRAM), not the DRAM, with the CMOS logic circuit on the same semiconductor substrate. However, a normal six-transistor SRAM cell is greater in area than a DRAM cell almost tenfold. Accordingly, the SRAM would require a much greater chip area. Consequently, even in compliance with the currently minimum possible design rule of 0.18 xcexcm, for example, the SRAM built in the chip can have a storage capacity of just several hundreds kilobits at most.
In contrast, a DRAM cell is much smaller in area than an SRAM cell. Thus, a great number of DRAM cells can be integrated together on a single chip. That is to say, a CMOS logic circuit and a DRAM with a large storage capacity can be integrated together on a small-area chip. However, the known DRAM-built-in LSI requires a much higher process cost and likely results in performance degradation of the CMOS logic circuit thereof as described above. Accordingly, the effective applications of the known DRAM-built-in LSI are virtually limited to transferring an enormous quantity of data at a high speed by using a DRAM that has a rather great storage capacity and a bus of a broad enough bit width (e.g., graphics applications).
On the other hand, there are many applications requiring a memory with a storage capacity of about 1 to 4 megabits, which may be regarded as a xe2x80x9cmedium capacityxe2x80x9d in accordance with the minimum design rule of 0.18 xcexcm. Accordingly, demand for integrating a medium-capacity memory, which needs a much smaller chip area than an SRAM with a similar capacity, along with a high-performance logic circuit on the same chip at a low cost has been on the rise.
It is therefore an object of the present invention to provide a semiconductor integrated circuit, including a stably operating DRAM, at a low cost.
Specifically, an inventive semiconductor integrated circuit includes: a first n-well defined in a p-type semiconductor region; word lines; data lines; and a dynamic randomaccess memory (DRAM) array. In the DRAM array, multiple memory cells are arranged in matrix over the first n-well. Each said memory cell includes a p-channel metal-oxide semiconductor (MOS) access transistor and a capacitor. The access transistor has its gate connected to an associated one of the word lines, its source connected to an associated one of the data lines and its drain connected to the capacitor. The integrated circuit further includes: a row of sense amplifiers coupled to the data lines; a word line driver for driving the word lines; and a power supply circuit. The power supply circuit receives an external supply voltage, generates internal supply voltages by stepping down the external supply voltage and then applies the internal supply voltages to the sense amplifiers, the word line driver and the first n-well.
In the inventive integrated circuit, the power supply circuit steps down the external supply voltage. Accordingly, there is no need to use any charge pump circuit that cannot operate stably enough due to its own circuit configuration. Instead, a voltage, generated by a voltage step-down circuit that realizes high-speed response and can supply a large current at a time, can be applied as an internal supply voltage to the sense amplifiers, for example. Thus, the memory array can operate stably enough.
In one embodiment of the present invention, the integrated circuit preferably further includes a logic circuit that has been formed in the p-type semiconductor region.
In such an embodiment, memory and logic circuits are formed on the same semiconductor substrate. Thus, the overall circuit area can be reduced and data can be transferred from the memory circuit to the logic circuit, or vice versa, at an increased rate.
In another embodiment of the present invention, the power supply circuit may step down the external supply voltage to generate primary and secondary internal supply voltages as the internal supply voltages. The primary internal supply voltage may be lower than the external supply voltage, while the secondary internal supply voltage may be lower than the external supply voltage but higher than the primary internal supply voltage. The primary internal supply voltage may be applied to the sense amplifiers, while the first n-well may be biased to the secondary internal supply voltage.
Then, the substrate can be biased in such a manner that the access transistor of each memory cell can have its threshold voltage raised and that the charges stored on the capacitor of the memory cell will not leak into the data line by way of the access transistor. In addition, the junction capacitance also decreases, so it is possible to reduce the parasitic capacitance associated with the data line. Accordingly, even if just a small quantity of charges have been stored on the capacitor of a memory cell, the memory cell still can be read accurately. That is to say, a broader margin is allowable for the operation range of the memory.
In this particular embodiment, the integrated circuit preferably further includes: a second n-well defined in the p-type semiconductor region; and a logic circuit. The logic circuit preferably includes: an n-channel MOS transistor formed in the p-type semiconductor region; and a p-channel MOS transistor formed in the second n-well. The power supply circuit preferably biases the second n-well to the primary internal supply voltage.
Then, memory array and CMOS logic circuit can be formed on the same semiconductor substrate without using the triple well structure. As a result, the fabrication process can be simplified.
Specifically, the capacitor of each said memory cell preferably includes: a planar insulating film formed over the first n-well; and a planar upper electrode formed over the planar insulating film and biased to a ground voltage.
Then, the memory cell can be made without performing any complicated process for forming a stacked or trenched capacitor. In addition, a capacitive insulating film for the capacitor of each memory cell can be made of an insulator with a dielectric constant higher than that of silicon dioxide. Accordingly, the capacitance per unit area can be increased for the capacitor, so the memory cell including that capacitor may have a smaller area. As a result, the fabrication cost can be cut down.
More specifically, the planar insulating film is preferably a silicon dioxide film that is almost as thick as the gate oxide film of the n- and p-channel MOS transistors.
In such an embodiment, the gate oxide film of transistors for a CMOS logic circuit and the capacitive insulating film of capacitors for memory cells can be formed in a single process step. Accordingly, a CMOS logic circuit and a DRAM array can be. formed on the same semiconductor substrate through a completely standard CMOS process, thus cutting down the fabrication cost. In addition, while the DRAM array is being formed for a semiconductor integrated circuit, the CMOS logic circuit does not have its performance degraded.
In still another embodiment, the power supply circuit may include a first MOS transistor and a first differential amplifier. The first MOS transistor may be interposed between an external supply voltage terminal and a first output terminal. The external supply voltage is applied through the external supply voltage terminal. The first differential amplifier may receive a first reference voltage and a voltage at the first output terminal. The power supply circuit may control the first MOS transistor by the output of the first differential amplifier. Also, the power supply circuit may set the primary internal supply voltage at a substantially constant voltage in accordance with the first reference voltage and output the primary internal supply voltage through the first output terminal.
Then, the power supply circuit can apply a constant primary internal supply voltage, which does not change depending on the external supply voltage, to various peripheral circuits (e.g., sense amplifiers) of the memory array. Thus, the memory can operate stably enough with a broader operation margin allowed against a variation in the external supply voltage.
In this particular embodiment, the power supply circuit preferably further includes a first reference voltage generator for generating the first reference voltage. The first reference voltage generator preferably includes a first fuse and regulates the first reference voltage by trimming the first fuse.
Then, the output voltage of the power supply circuit is regulable by trimming the fuse when the memory is tested after the integrated circuit has been fabricated. Thus, a constant voltage can be output without being affected by any process-related variation. That is to say, the memory can operate stably enough with a great margin allowed against the process-related variations. In addition, it is also possible to optimize the output voltage of the power supply circuit and stabilize the memory operation according to how much the characteristic value of the transistors has changed with the process-related variations.
Alternatively, the power supply circuit may further include a second MOS transistor and a second differential amplifier. The second MOS transistor may be interposed between the external supply voltage terminal and a second output terminal. The second differential amplifier may receive a second reference voltage and a voltage at the second output terminal. The power supply circuit may control the second MOS transistor by the output of the second differential amplifier. Also, the power supply circuit may set the secondary internal supply voltage at a substantially constant voltage corresponding to the second reference voltage and output the secondary internal supply voltage through the second output terminal.
Then, the power supply circuit can output a constant secondary internal supply voltage that does not change depending on the external supply voltage. Generally speaking, a voltage step-down circuit has higher current supplying ability and higher response speed than a voltage step-up circuit. Accordingly, if the first n-well is biased to this secondary internal supply voltage, a variation in voltage at the first n-well, resulting from a substrate current produced during the memory operation, can be minimized. As a result, the memory array can operate stably enough.
Specifically, in this case, the power supply circuit preferably generates the second reference voltage based on the primary internal supply voltage.
optionally, the power supply circuit may further include a second reference voltage generator for generating the second reference voltage. The second reference voltage generator may include a second fuse and regulate the second reference voltage by trimming the second fuse.
In yet another embodiment, the power supply circuit may step down the external supply voltage to generate primary and secondary internal supply voltages as the internal supply voltages. The primary internal supply voltage may be lower than the external supply voltage, while the secondary internal supply voltage may be lower than the external supply voltage but higher than the primary internal supply voltage. The primary internal supply voltage may be applied to the sense amplifiers, while the secondary internal supply voltage may be applied to the word line driver. The sense amplifiers may supply the primary internal supply voltage as a high-level voltage to the data lines. The word line driver may supply the secondary internal supply voltage as a non-selected-state voltage to the word lines.
In such an embodiment, when a memory cell is non-selected to store charges thereon, the access transistor of the memory cell has its gate voltage raised. Then, the sub-threshold current can be reduced drastically and the leakage of the charges from the capacitor into the data line by way of the access transistor can be minimized. That is to say, the charge retainability of the capacitor improves. Also, when the secondary internal supply voltage is set at a substantially constant value, the variation in sub-threshold current, resulting from the change in gate voltage of the access transistor of the memory cell, can be minimized. Accordingly, the capacitor can retain stored charges thereon almost completely even against the variation in external supply voltage.
In yet another embodiment, the power supply circuit may step down the external supply voltage to generate primary and secondary internal supply voltages as the internal supply voltages. The primary internal supply voltage may be lower than the external supply voltage. The secondary internal supply voltage may be approximately equal to an average of the absolute value of a threshold voltage of the access transistor and the primary internal supply voltage. The data lines may be supplied with the secondary internal supply voltage as a precharge voltage. And the word lines may be supplied with a ground voltage as a selected-state voltage.
In such an embodiment, a voltage, approximately equal to an average of the high- and low-level voltages on the data lines, is the precharge voltage for the data lines. This voltage is almost equal to an average of the capacitor voltage of a memory cell on which charges are stored and the capacitor voltage of the same memory cell on which no charges are stored. Accordingly, the variation in voltage on the data lines when stored charges are read out from a capacitor onto the data lines can have almost the same absolute value as the variation in voltage on the data lines when no charges are read out from the capacitor. For that reason, the read data can have its logical level determined accurately enough by the variation in voltage on the data lines with the read error minimized.
In this particular embodiment, a voltage representing the low level of the data lines is preferably the ground voltage.

Matsushita Electric Industrial Co., Ltd.


A satellite radiowave receiving device includes a receiver and a processor. The receiver acquires and receives radiowaves from a positioning satellite. The processor performing a positioning operation based on the radiowaves received by the receiver to obtain a current position of the satellite radiowave receiving device. The processor causes the receiver to stop an acquiring operation of radiowaves from a new positioning satellite under a predetermined condition while radiowaves are being acquired from a required number of positioning satellite for the positioning operation. If an error range of the obtained current position no longer satisfies a predetermined accuracy standard during a stop of the acquiring operation, the processor causes the receiver to resume the acquiring operation.

The present invention relates to a satellite radiowave receiving device, an electronic timepiece, a method for controlling positioning operations, and a storage device.
A satellite radiowave receiving device (positioning device) receives radiowaves containing positioning information from positioning satellites and performs positioning operations. The satellite radiowave receiving device can perform positioning operations at various countries and regions of the world based on the current positions of a plurality of positioning satellites and gaps in propagation time (pseud distance) of radiowaves transmitted from these positioning satellites.
In global navigation satellite systems, such as Global Positioning System (GPS) in the U.S.A and GLONASS in the Russia, the orbits of positioning satellites are determined such that radiowaves from approximately six positioning satellites can be always received on flat surfaces of the ground or the sea. Since power consumption in acquiring radiowaves from positioning satellites is larger than that in tracking positioning satellites, portable satellite radiowave receiving devices with a limited power consumption stops an acquiring operation when radiowaves from a required number of positioning satellites have been acquired.
However, a change in the position of a positioning satellite during a continuous positional operation makes it no longer possible to receive radiowaves from a positioning satellite, while making it possible to receive radiowaves from another positioning satellite. To cope with this situation, Japanese Unexamined Patent Application Publication No. 2014-66550 discloses techniques that enables stopping of an acquiring operation when the number of positioning satellites from which radiowaves are received is equal to or greater than a predetermined maximum number of positioning satellites, and resumption of the acquiring operation when the number of positioning satellites from which radiowaves are received is reduced to less than the minimum number of positioning satellites required for positioning.
However, the positioning accuracy depends on a spatial distribution of positioning satellites which is acquired and used for positioning calculations and on the receiving state of radiowaves from the positioning satellites. Determination of necessity for a re-acquiring operation solely based on the number of positioning satellites from which radiowaves are acquired precludes accurate positioning operations when the number of positioning satellites from which radiowaves are acquired is reduced to a number near the minimum number of positioning satellites.

Satellite radiowave receiving device, electronic timepiece, method for controlling positioning operations, and storage device


A mat assembly including a planar mat body formed to cover a preselected area of a surface region. The preselected area partially defines a volume of ground to be broken by explosion therein. The mat body includes one or more layer elements. The mat body has an engagement surface for engagement with the preselected area. The mat assembly includes a skirt element connected with the mat body having an external portion extending from the mat body, for at least partially restraining matter ejected from the volume of ground upon initiation of the explosion.

In the prior art, blasting mats are typically designed to have the greatest area density possible, taking into account the materials used and other practical constraints. This is because until recently all the explosives used (e.g., ANFO (ammonia nitrate and fuel oil)) in commercial blasting operations are high-velocity explosives, for which a higher-density blasting mat is required in order to achieve an acceptable degree of containment of the matter (gases, dust, and flyrock) ejected from the ground (i.e., rock) that is broken by a high-velocity explosive blast.
The conventional blasting mats are available in a number of sizes, e.g., 20 feet by 20 feet (400 square feet). Typically, the conventional high-density blasting mats are made of pieces of used rubber tires that are held together by steel cables that have been passed through the pieces. The steel cables are used also to keep the pieces compressed, to maintain the high density that is thought to be desirable.
As is well known in the art, the conventional high-density blasting mats have a number of disadvantages. First, due to their relatively high area densities (e.g., usually about 18 kg per square foot (39.7 lbs per square foot)), the conventional blasting mats are difficult to handle at the site, and they are also expensive to ship over long distances. Second, the conventional blasting mats are bulky, and this also makes their shipping difficult, and relatively expensive.
In practice, the conventional blasting mats are often overlain with each other, in order to ensure comprehensive coverage over an entire blast pattern. However, the extent of the overlap is significant, e.g., two to three feet at each end of each mat. Because of the overlap, a greater number of conventional blasting mats are required than would otherwise be needed, in the absence of the overlap.

Low density blasting mat and method of utilizing same


A goods-handling door for closing or opening a bay formed in a wall, said door comprising: a raisable curtain (3) capable of being collected together at the top of the door; a vertical slideway (5) on either side of the curtain, each slideway being suitable for receiving a respective side edge of the curtain and having a face placed against the wall at the edge of the bay, the side edges of the curtain being adapted to slide in said side vertical slideways to hold the curtain substantially in the plane of the door; and mechanical means for operating the door, the mechanical means comprising a shaft (4) disposed at the top of the door for winding up the curtain or curtain-raising straps, a motor (104) for driving said shaft, an end-of-stroke device (105), and control means (106), said door being characterized in that each slideway is fixed in position by disengageable means (9) to hold the slideway in the plane of the door during normal operation thereof while allowing the slideway to leave its location when sufficient force is exerted thereon.

The present invention relates to a "goods-handling" door for an industrial building such as a factory, a workshop, a warehouse, a hangar, or the like, to enable a bay cut out in a wall to be closed or opened.
A door of this type comprises a curtain that must be capable of being raised and lowered quickly to allow vehicles to pass through, while remaining open as short a time as possible so as to restrict the passage of noise and air between two premises or between the inside and the outside. The curtain is flexible or made up of rigid panels, and it is capable of being wound up or folded up at the top of the door. The curtain may optionally be reinforced by horizontal stiffening bars. At its top, the door includes mechanical members: a motor, a shaft for winding up the curtain or curtain-raising straps, a stepdown gear box, end-of-stroke detector means, etc. . . . . Slideways are provided on either side of the door to guide the edges of the curtain, and optionally also the ends of stiffening bars. The slideways may optionally form vertical side uprights with the mechanical elements being fixed to the tops thereof. The tops of the uprights may be interconnected by a top cross-beam. The beam may also be fixed to the wall, above the door or on either side thereof.
The uprights are usually placed against the wall, at the edges of the opening constituted by the bay, and they may optionally be within the opening in the thickness of the wall, against the end section thereof. This disposition is uncommon since it reduces the available area in the opening.
In certain industries, such as the pharmaceutical, food, chemical, etc. industries, it is necessary to clean the elements of the door completely on a regular basis. Unfortunately, it is not possible to clean the gap between one of the sides of an upright and the portion of the wall against which it is placed. An object of the present invention is to enable such cleaning to be performed completely.
When a vehicle comes up to the door, the curtain is generally raised automatically and the vehicle can pass through almost without slowing down, with the door closing again after the vehicle has gone through. Nevertheless, it can happen that the vehicle is travelling too fast, and that it strikes the curtain before it has been raised far enough. Means and dispositions have already been proposed to limit the physical damage suffered by the door under such circumstances. In one proposal, the slideways may be flexible, allowing the curtain to escape if excessive force is applied thereto (European patent EP-0 272 733 ). In another proposal, the stiffening bars of the curtain may be flexible, so they flex to escape from the slideways if they are subjected to too great a force (EP-0 398 791 ). Hinged doors have also been proposed in which the hinges come undone if they are subjected to too much force (FR-1 196 095 ).


Disclosed are systems, circuits and methods related to low-loss bypass of a radio-frequency (RF) filter or diplexer. In some embodiments, a switching network circuitry can include a first switch that has an input pole configured to receive a radio-frequency (RF) signal, a pass-through throw configured to be connectable to the input pole to allow routing of the RF signal to an RF component, and at least one dedicated bypass throw configured to be connectable to the input pole and at least one bypass conduction path. The switching network circuitry can further include a second switch that has a pole and a throw, and is connectable between an output of the RF component and the bypass conduction path. Use of the dedicated bypass throw(s) in the first switch allows implementation of low-loss bypass of the filter or diplexer.

Field
The present disclosure generally relates to systems and methods associated with low-loss bypass of a radio-frequency filter or diplexer.
Description of the Related Art
In a radio-frequency (RF) system, a filter or diplexer is typically needed or desired in some conditions. When not needed, it can be desirable to bypass the filter or diplexer to avoid incurring loss associated with the filter or diplexer.

Systems, circuits and methods related to low-loss bypass of a radio-frequency filter or diplexer


An imaging apparatus which is effective to make it easier to manually adjust a focus is provided. An imaging apparatus has: a display unit; an image capturing unit configured to capture a subject image which is formed on an imaging plane and to output image data; a distance information obtaining unit configured to obtain distance information of a single subject or each of a plurality of subjects in the image data; and a display controller configured to display an image on the display unit. The display controller is configured to associate a plurality of different colors respectively with a plurality of areas partitioned according to distances from the imaging apparatus, determine based on the distance information to which one of the plurality of areas each subject corresponds, and display on the display unit each captured subject with the color associated with the area corresponding to the each captured subject.

1. Field of the Invention
The present disclosure relates to an imaging apparatus which has a manual focus (MF) function.
2. Background Art
Unexamined Japanese Patent Publication No. 2009-103912 discloses an imaging apparatus which has a manual focus function for allowing a user to manually adjust focus. According to this imaging apparatus, when the user operates a focus ring to rotate, a focus lens of an optical system is driven according to a direction of the operation and a rotation amount, and a focus position of the optical system moves. By this means, the user can manually adjust the focus of the imaging apparatus.
Unexamined Japanese Patent Publication No. 2013-21682 discloses a method of calculating a distance from an imaging apparatus to a subject by DFD (Depth From Defocus) processing.

Imaging apparatus and method for displaying captured image with different colors associated with distances

PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.


A piezoelectric/electrostrictive device is provided with a stationary portion, a thin-plate portion supported by the stationary portion, and piezoelectric/electrostrictive element formed by alternately laminating a plurality of electrodes and a plurality of piezoelectric/electrostrictive layers. The piezoelectric/electrostrictive device is produced by cutting a thin-plate body that composes the thin-plate portion afterward and a laminated body comprising the piezoelectric/electrostrictive layers and thereafter applying prescribed specific processing (for example, heat treatment) to the cut plane (the lateral end surfaces). By so doing, the ratio of the actual surface area of the lateral end surface of the piezoelectric/electrostrictive element to the area of the lateral end surface of the piezoelectric/electrostrictive element in the orthographic projection is four or less, and the deposition of moisture on the lateral end surfaces is suppressed to the extent of not substantially generating electric leakage or ion migration. As a result, a highly durable piezoelectric/electrostrictive device can be provided.

Piezoelectric/electrostrictive devices of the above-described type have been actively developed as an actuator for precision machining; as an actuator for controlling the position of a read and/or write element (e.g., a magnetic head of a hard disk drive) for reading and/or writing optical information, magnetic information, or the like; as a sensor for converting mechanical vibration to an electrical signal; or as a similar device.
Japanese Patent Application Laid-Open (kokai) No. 2001-320103 discloses an example of such a piezoelectric/electrostrictive device, which is shown in FIG. 13. The piezoelectric/electrostrictive device includes a stationary portion 100; thin-plate portions 110 supported by the stationary portion 100; holding portions (movable portions) 120 provided at corresponding tip ends of the thin-plate portions 110 and adapted to hold an object (e.g., a magnetic head of a hard disk drive); and piezoelectric/electrostrictive elements 130 formed at least on corresponding surfaces of the thin-plate portions 110, each piezoelectric/electrostrictive element 130 including a plurality of electrodes and a plurality of piezoelectric/electrostrictive layers which are laminated alternately. In the piezoelectric/electrostrictive device, an electric field is generated between electrodes of the piezoelectric/electrostrictive elements 130 to thereby expand and contract the piezoelectric/electrostrictive layers of the piezoelectric/electrostrictive elements 130, whereby the thin-plate portions 110 are deformed. The deformation of the thin-plate portions 110 causes displacement of the holding portions 120 (accordingly, displacement of the object held by the holding portions 120).
The piezoelectric/electrostrictive device of FIG. 13 is manufactured as follows. Firstly, as shown in FIG. 14, a plurality of ceramic green sheets (and/or a ceramic green sheet laminate) are prepared. As shown in FIG. 15, these ceramic green sheets are laminated together and then fired, thereby forming a ceramic laminate 200. As shown in FIG. 16, piezoelectric/electrostrictive laminates 210, each including a plurality of electrodes and a plurality of piezoelectric/electrostrictive layers which are laminated alternately, are formed on the surface of the ceramic laminate 200. Through wire sawing (or, for example, dicing) by use of a wire saw WS, the piezoelectric/electrostrictive laminates 210 are cut along cutting lines C1 to C4 shown in FIG. 17, thereby yielding the piezoelectric/electrostrictive device.
Meanwhile, in the case where the above-disclosed piezoelectric/electrostrictive device is actually used (for example, in the case where the device is used as an actuator for the positioning of the magnetic head of a hard disk drive), moisture may sometimes deposit on lateral end surfaces (cut planes along the cutting line C3 or C4 in FIG. 17) of piezoelectric/electrostrictive elements 130. Such moisture can be caused by, for example, condensation or the like of water vapor in an atmosphere (in the air).
When moisture deposits on lateral end surfaces of piezoelectric/electrostrictive elements 130 (particularly on lateral end surfaces of piezoelectric/electrostrictive layers as parts of lateral end surfaces of piezoelectric/electrostrictive elements 130), the electric resistance of the piezoelectric/electrostrictive layers on the lateral end surfaces of which moisture has deposited lowers and thereby electric leakage tends to occur between the electrodes on both the sides that interpose the respective piezoelectric/electrostrictive layers. Otherwise, so-called ion migration is promoted on the lateral end surfaces of the piezoelectric/electrostrictive layers due to the existence of the moisture that deposits on the lateral end surfaces and, as a result, short circuit tends to occur between the electrodes on both the sides that interpose the respective piezoelectric/electrostrictive layers on the lateral end surfaces of which the moisture has deposited.
When such electric leakage occurs, voltage between the electrodes lowers and thereby the strength of the electric field formed between the electrodes weakens. As a result, the amount of the expansion and contraction of the piezoelectric/electrostrictive layers reduces and the piezoelectric/electrostrictive elements 130 (namely the piezoelectric/electrostrictive device) cannot attain intended operations. Further, when such short circuit occurs, voltage is not generated between the electrodes, thereby the piezoelectric/electrostrictive elements 130 do not expand or contract, and as a result the piezoelectric/electrostrictive elements 130 (namely the piezoelectric/electrostrictive device) cannot operate.
In addition, when such an above-disclosed piezoelectric/electrostrictive device is used as, for example, an actuator for the positioning of the magnetic head of a hard disk drive, the attachment of debris, dust, or the like on a hard disk, etc., may cause incorrect reading/writing of information. Hence, the piezoelectric/electrostrictive device is to be placed in an environment where the generation of debris, dust, or the like (the generation of debris, dust, or the like may hereunder be referred to as "dust generation" occasionally) can be suppressed to a lowest possible level.
In such a case, the above-disclosed piezoelectric/electrostrictive device is used in the state where the lateral end surfaces (cut planes along the cutting line C3 or C4 in FIG. 17), constituting a single planar plane, of the device face the surface of the hard disk with a relatively small gap in between and hence it is particularly necessary to prevent dust generation caused by the separation of microparticles (the separation of microparticles may hereunder be referred to as "particle separation" occasionally) from the lateral end surfaces (cut planes along the cutting line C3 or C4 in FIG. 17) of the constituent elements constituting the lateral end surfaces of the piezoelectric/electrostrictive device. From the above viewpoint, test items related to dust generation have been added to such a piezoelectric/electrostrictive device in recent years.
In view of the above situation, the above-disclosed piezoelectric/electrostrictive device is required to effectively suppress the deposition of moisture on the lateral end surfaces of piezoelectric/electrostrictive elements 130 and dust generation from the lateral end surfaces when the piezoelectric/electrostrictive device is actually used.


A method for automatically detecting waste gas. The waste gas is led into a multiple switching valve through which the waste gas is sampled. Then, the waste gas sample is conveyed to an empty column and/or a chromatographic column, via the multiple switching valve. Then, the total hydrocarbon content of the waste gas sample is measured when the waste gas sample is conveyed to the empty column, and the waste gas sample is separated for measuring individual volatile organic compound concentrations of the waste gas sample when the waste as sample is conveyed to the chromatographic column.

1. Field of the Invention
The present invention relates generally to a method for automatically detecting the total hydrocarbon content and major organic contaminant concentration of waste gas.
2. Description of the Related Art
Nowadays, environmental protection has become increasingly important. Various on-line waste-gas-detecting instruments have been widely used to monitor large-scale stationary sources of pollution such as petrochemical plants. However, none of them can simultaneously measure the total hydro-carbon (THC) content and individual volatile organic compound (VOC) concentrations in the sources of pollution.

Method for automatically detecting total hydrocarbon content and individual volatile organic compound concentrations of waste gas

Industrial Technology Research Institute


The electric conversion stage according to the invention can be connected on one hand to intermediate terminals of a DC voltage electric bus, and on the other hand to output terminals. It comprises P switching branches, P≧2, the switching branches being connected in parallel between the intermediate terminals, each switching branch including first and second controllable electronic switches connected serially and connected to each other by a midpoint, each switch including a semiconductor switching element and a diode connected in anti-parallel to the semiconductor element, and means for controlling the electronic switches according to a control law.

The present invention relates to an electric conversion stage, capable of being connected on one hand to intermediate terminals of a DC voltage electric bus, and on the other hand to output terminals, the conversion stage comprising P switching branches, P being greater than or equal to 2, preferably equal to 3, the switching branches being connected in parallel between the intermediate terminals, each switching branch including first and second controllable electronic switches connected serially and connected to each other by a midpoint, the first switch being connected between the first intermediate terminal and the corresponding midpoint, and the second switch being connected between the second intermediate terminal and the corresponding midpoint, each switch including a semiconductor element and a diode connected in anti-parallel to the semiconductor element, each semiconductor element being switchable between an on state and an off state, and control means for controlling the electronic switches according to a control law.
The present invention also relates to an electric converter, capable of being linked to an AC electrical network including M phase(s), M being greater than or equal to 1, the converter comprising a first conversion stage forming a voltage rectifier and a second conversion stage connected as output of the first conversion stage, the second conversion stage being as defined above.
The invention also relates to a device for converting AC current into a DC current including such an electric converter.
The invention also relates to a terminal for recharging an electric battery, in particular a motor vehicle electric battery, comprising such an electric converter or such a conversion device.
The invention in particular applies to a recharging terminal capable of delivering, as output, a DC voltage comprised between 5 V and 1 kV, preferably comprised between 10 V and 500 V, and a DC current comprised between 0 and 250 A, preferably comprised between 0 and 125 A.
In order to recharge an electric battery, a device is known for converting AC current into a DC current that can be linked to an AC electric network, such as a three-phase network. This conversion device comprises a voltage rectifier connected to the three-phase network, the voltage rectifier being formed by a diode bridge. This conversion device also comprises a Buck converter connected as output of the voltage rectifier and capable of converting a DC voltage from the rectifier into another DC voltage with a lower value.
The Buck converter comprises two input terminals, two output terminals, as well as a switch and a diode that are connected between the input terminals and linked to each other by an intermediate point. The Buck converter also comprises a capacitor connected between the two output terminals and an electromagnetic coil connected between a terminal of the capacitor and said intermediate point. This switch is a semiconductor element, such as a transistor.
However, the transistor and the electromagnetic coil are relatively expensive and also have a significant bulk, the transistor and the electromagnetic coil being dimensioned to allow the passage of strong currents, such as currents of approximately 100 A.

Conversion stage, electric converter including such a conversion stage, device for converting an AC current into DC current including such a converter, terminal for recharging an electric battery including such a converter or conversion device

Abstract: It also comprises a capacitor connected between the two output terminals and, for each switching branch, an electromagnetic coil connected between a terminal of the capacitor and the midpoint of the corresponding switching branch, and the control law is selected from among a first control law and a second control law, the first control law being such that the semiconductor element of each first switch is always off, and the second control law being such that the semiconductor element of each second switch is always off.


Macrocyclic polyether oligomers, preferably as mixtures of oligomers of different degrees of polymerization, are incorporated in a direct displacement reaction mixture for the formation of polyetherimides, said reaction mixture comprising at least one alkali metal salt of a dihydroxy-substituted aromatic hydrocarbon and at least one bis(halo- or nitrophthalimide). The macrocyclic oligomers can be isolated from an earlier-prepared linear polyetherimide composition. Their incorporation in the reaction mixture does not increase the proportion of oligomers in the polyetherimide product.

This invention relates to the preparation of polyetherimides.
Polyetherimides are a known class of high performance polymers characterized in particular by resistance to high temperature conditions. At least two methods for their preparation from monomeric reagents are known. The first method includes the steps of displacement of a chloro- or nitro-substituted phthalimide with a salt of a dihydroxyaromatic compound followed by conversion of the resulting bisimide to the corresponding dianhydride and its reaction with at least one diamine. This method, hereinafter designated "displacement-condensation", is disclosed in many publications and patents.
The second method, hereinafter designated "direct displacement", is frequently advantageous by reason of minimization of processing steps and by-product formation. It typically comprises the reaction of a salt of a dihydroxyaromatic compound with a bis(halo- or nitrophthalimide). The direct displacement method is also disclosed in numerous patents. Particular reference is made to U.S. Pat. No. 5,229,482, which describes direct displacement in a solvent of low polarity such as a dichloro- or trichloroaromatic compound in the presence of a phase transfer catalyst which is stable at the relatively high reaction temperatures employed. The phase transfer catalysts having this property which are often preferred are the hexaalkylguanidinium halides, especially chlorides and bromides. A similar direct displacement method, employing an alkoxyaromatic compound such as anisole as a solvent is disclosed in copending, commonly owned application Ser. No. 08/799,886.
It is known that formation of many linear polymers, especially condensation polymers such as polycarbonates, polyesters and polyetherimides, is accompanied by the formation of various proportions of macrocyclic oligomers. These oligomers typically comprise principally molecular species having degrees of polymerization from 2 to about 12 and having an overall cyclic configuration, apart from the presence of any aromatic or heterocyclic rings present in the polymer chain, in contrast to the linear polymers which constitute most of the product.
It is also known that macrocyclic polyetherimide oligomers, hereinafter sometimes simply designated "oligomers" for brevity, can be prepared in high yield by various methods. For example, U.S. Pat. No. 5,357,029 describes their preparation by the reaction of diamines with tetracarboxylic acids or their dianhydrides, and U.S. Pat. No. 5,514,813 by the reaction of salts of dihydroxyaromatic compounds with bis(halo- or nitrophthalimides) in the presence of phase transfer catalysts and in specific molar ratios of reactants. The polymerization of these oligomers is preferably conducted in the presence of a primary amine as initiator and a macrocyclic polyimide polymerization catalyst which may be a metal or hydroxide or salt thereof, as further disclosed in said U.S. Pat. No. 5,357,029.
While macrocyclic oligomers are detected in essentially all polyetherimides, those polyetherimides prepared by displacement-condensation generally contain very low proportions thereof, most often no more than 1% by weight. In such proportions, the macrocyclic oligomers have little or no detrimental effect on the properties of the linear polymer.
It has been discovered, however, that the direct displacement method for preparing linear polyetherimides affords a product having a substantially higher proportion of oligomers. Proportions as high as 10% and most often in the range of about 7-8% by weight are typical.
It is possible to separate oligomers from the linear polyetherimide by such methods as anti-solvent precipitation of linears, whereupon the soluble fraction contains a major proportion of oligomers. The previously known methods for polymerizing said oligomers, however, are disadvantageous in this context since the conditions required therefor are different from those of displacement-condensation and direct displacement.

Polyetherimide preparation method including addition of macrocyclic polyetherimide oligomers


An image-pickup apparatus for picking up an image using a solid-state image pickup device. The apparatus includes a first and a second input receiving parts for receiving different input signals in accordance with a user's input operation, an image-pickup-condition determination part for determining an optimum image-pickup condition to be set at image-pickup time, and an image-pickup controller for controlling such that the image-pickup-condition determination part starts a determination operation at input-signal receiving time of the first receiving part, when the input signal is received continuously and the second input receiving part receives an input signal after the optimum image-pickup condition is determined, an image picked up by applying the image-pickup condition determined to be the best is captured, and when the second input receiving part receives the input signal on the other conditions, a plurality of pickup images are captured continuously by applying different image-pickup conditions in sequence.

1. Field of the Invention
The present invention relates to an image pickup apparatus for picking up images using a solid-state image pickup device. More particularly, the present invention relates to an image pickup apparatus including an auto-bracket function for continuously capturing a plurality of pickup images to which different image-pickup conditions are applied in sequence and an automatic adjustment function for automatically determining the optimum image-pickup condition to pickup an image, and to a method of controlling image pickup and a program.
2. Description of the Related Art
An image-pickup apparatus, such as a digital still camera picking up images using a solid-state image pickup device, etc., often has a function of automatically adjusting focus, brightness, hue, etc., appropriately at image-pickup time. For example, AF (Auto Focus), AE (Auto Exposure), AWB (Auto White Balance), etc., are typical automatic adjustment functions. Also, the apparatus is commonly equipped with a function of automatically going off electronic flash light only when an object of image-pickup is in the dark.
Some of known image-pickup apparatuses perform an operation of obtaining control values by the above-described automatic adjustment functions when a user half-presses the shutter-release button using a shutter-release button having two states, namely, a "half-pressing" and a "full-pressing". A half-pressing of a shutter-release button is called a "half-release", etc. In such an image-pickup apparatus, for example, the following procedure is performed for picking up images. In this regard, the AF function is taken for example here.
First, when the shutter-release button is half-pressed, the AF function is activated, the focus lens is moved with capturing pickup images continuously, and the evaluation values of a degree of focussing are obtained from the captured signals. The lens position with the largest evaluation value is the focused position. When that position is obtained and the focus lens is moved to that position, the completion of the automatic adjustment is notified by a screen display and a sound, etc. Thus, the user full-presses the shutter-release button to make it possible to record the pickup image in focus into a recording medium. In such an image-pickup apparatus, when the shutter-release button is full-pressed at once without going into a half-release state, the above-described automatic adjustment functions is not activated, the image-pickup signal is captured on the image-pickup condition at that time without change to record it into a recording medium. Alternatively, in some of the image-pickup apparatuses, even if full-pressed, a pickup image is not recorded into the recording medium until the optimum control value is obtained by the automatic adjustment function.
Here, if the automatic adjustment function is activated at half-release time as described above, there is a problem in that it takes some time until the optimum image-pickup condition is obtained, thereby losing chances of taking a picture. Also, there is a problem in that the control value determined to be the best by the image-pickup apparatus might be different from the user's intention because of the performance limit of the automatic adjustment. Accordingly, up to now, an increase in the speed of the automatic adjustment and an improvement in the adjustment performance are demanded.
In order to solve these problems, there has been an image-pickup apparatus having a function called "auto-bracket" which continuously records a plurality of images on different image-pickup conditions in a short time when a shutter-release button is pressed once. As a commonly-used auto-bracket function, a function for picking up images by changing the amount of exposure adjustment using an AE function is known. By such a function, a user can make his or her choice from a plurality of recorded images afterward, and thus it has been possible to obtain an image in accordance with the user's intention without losing chances of taking a picture. However, at the same time, there has been a drawback in that a recording medium is used wastefully. On the other hand, for example, there has been a digital camera (for example, refer to Japanese Unexamined Patent Application Publication No. 2004-135029 (paragraph numbers [0047] to [0065], FIG. 3)) in which focus-evaluation values are calculated for individual images picked up with changing the focus-lens positions by the auto-bracket function and the image with the highest value is automatically selected and recorded into a recording medium.
Also, in an image-pickup apparatus having an auto-bracket function, it is possible to change an image-pickup mode using the auto-bracket and a usual image-pickup mode which picks up an image one by one. Furthermore, it is thought that a plurality of kinds of adjustment values are changed when the auto-bracket function is activated and that the combination thereof is allowed to be set in accordance with a user's operation. By these functions, it becomes possible to pick up an image more suited to user's intention. However, the number of user operation steps increases that much. On the other hand, there has been an electronic still camera in which the auto-bracket function is automatically determined to be necessary or not based on the picked-up images, and if necessary, images are picked up using the auto-bracket function to record a plurality of images on different image-pickup conditions into a recording memory, thereby improving the operationality (for example, refer to Japanese Unexamined Patent Application Publication No. 2001-8087 (paragraph numbers [0020] to [0034], FIG. 1)).
As described above, as the technique disclosed in Japanese Unexamined Patent Application Publication No. 2004-135029, by automatically selecting the image with the optimum image-pickup conditions out of the pickup images by the auto-bracket function and recording it into a recording medium, it is possible to use the recording medium effectively, and to increase the possibility of obtaining the image preferable to the user without losing chances of taking a picture. Also, by finely adjusting the image-pickup conditions at auto-bracket time, it becomes easy to reflect the user's intention. As the technique disclosed in Japanese Unexamined Patent Application Publication No. 2001-8087, by automatically determining the necessity of the auto-bracket function, it is possible to further increase the operationality of the user.
However, the technique for automatically keeping images in a recording medium and the technique for automatically determining the necessity of the auto-bracket function are basically the same as an automatic adjustment technique at half-release time described above, and thus there remains a possibility of recording images which are not in accordance with the user's intention. The advantage of the auto-bracket function lies in the fact that the images preferable to the user can be selected by that user from a plurality of recorded images after picking up images. Thus, that advantage is sometimes lost if the above-described automatic selection and automatic determination are performed.
On the other hand, if the auto-bracket function is used, it is commonly necessary to change the operation modes by a key operation, etc. A large number of users pick up images in an operation mode in which an automatic adjustment function is activated at ordinary use time, and use the auto-bracket function by changing the operation mode if necessary. However, in such a way of use, the user often loses a chance of taking a picture while changing the operation modes. In spite of this, if the auto-bracket function is activated all the time, even in a case of obtaining an appropriate image by the automatic adjustment function, a lot of images are recorded, the capacity of the memory is used unnecessarily, and it takes time and effort to select necessary images. That is to say, in a known image-pickup apparatus, there has been a problem in that the operationality for a user of using the auto-bracket function at once when necessary has not been considered and the advantage of the auto-bracket function has not been utilized.

Image pickup apparatus, method of controlling image pickup and computer-readable storage medium


A unidirectional condenser microphone includes a diaphragm, a fixed electrode disposed opposite a back face of the diaphragm and an electrode extraction part for the fixed electrode disposed at a backside of the fixed electrode and having a through hole adapted to capture a sound wave from a rear acoustic terminal into a backside of the diaphragm. The through hole has a horn-shaped opening formed in continuation of the through hole at the rear acoustic terminal side thereof such that an inner diameter of the horn-shaped opening is increased toward the rear acoustic terminal side. The electrode extraction part has a plurality of the through holes formed therein at regular intervals along a concentric circle around an axial center of the electrode extraction part, and all the through holes along the concentric circle have the horn-shaped openings formed therein, respectively.

Field of the Invention
The present invention relates to a unidirectional condenser microphone and its manufacturing method with which a polar pattern of the microphone can selectively be set from a cardioid pattern to a hyper cardioid pattern.
Description of the Related Art
For using a microphone, it is desired that a directivity of the microphone is appropriately selected in accordance with sound-collecting condition.
For example, for microphones belonging to a class of unidirectional microphones, in the case of collecting a sound of an instrument such as a drum, a microphone with a hyper cardioid characteristic is preferably used. And in the case of using a microphone for amplifying vocal sound or the like, a microphone with a cardioid characteristic is preferably used.
The unidirectional condenser microphone is generally configured to capture a bi-directional component into a backside of a diaphragm through an acoustic resistor provided at a rear acoustic terminal side.
Thus, in the unidirectional condenser microphone, it is technically important to set a stable acoustic impedance. Setting of the acoustic impedance affects performance of the unidirectional condenser microphone, thus, various proposals have been conventionally made.
For example, the applicant of the invention has proposed a condenser microphone with a stable acoustic resistance by adopting a device for controlling passage of a sound wave through a surface boundary between an insulating base for supporting a fixed electrode and an acoustic resistance material provided at the front side of the insulating base. This is disclosed in JP 2010-183249 A.
In addition, the applicant of the invention has proposed a configuration in which the fixed electrode is bonded to an electrode extraction part that supports the fixed electrode in JP patent application No. 2013-136102.
The unidirectional condenser microphone with a stable acoustic impedance can also be obtained by using this configuration and sandwiching the acoustic resistance material between the fixed electrode and the electrode extraction part.
In the above-mentioned unidirectional condenser microphones, the acoustic impedance is set by the acoustic resistance material in order to obtain desired directional characteristics.
Therefore, fine control of the acoustic resistance material is required for obtaining the cardioid or hyper cardioid directional characteristics as described in the beginning. This fine control of the acoustic resistance material is heavily dependent on experience and intuition of a person in charge of manufacturing.
Further, there is a problem that the acoustic impedance is not stable enough because the acoustic resistance material shows significant change over time.
For these reasons, there was a problem of variations of characteristics caused by difference among people in charge of manufacturing or deterioration of the acoustic resistance material in the conventional techniques. It was difficult to set the acoustic impedance of the unidirectional microphone stably, and there was a problem in productivity and stability of the characteristics in the conventional techniques.

Unidirectional condenser microphone and method of manufacturing the same


An EED capable of reducing noise influence between a high voltage element and a low voltage logic element in an EED panel includes: a high voltage ground for a high voltage element, a low voltage ground for a low voltage element, and a ferrite bead, connected between the high voltage ground and the low voltage ground, to block RF noise from the high voltage ground.

1. Field of the Invention
The present invention relates to an Electron Emission Display (EED), and more particularly, to an EED which can reduce noise influence transferred through a ground between a high voltage element and a low voltage element.
2. Description of the Related Art
An Electron Emission Display (EED) includes an EED panel and a driver. When the driver supplies a positive voltage to an anode of the EED panel, if a positive voltage is supplied to a gate electrode and a negative voltage is supplied to a cathode electrode, electrons are emitted from the cathode. The emitted electrons are accelerated toward the gate electrode and converged into the anode. Then, the electrons collide with fluorescent cells disposed in front of the anode, thereby emitting light.
The driver includes a video processor to convert an external analog video signal into a digital signal, a panel controller to generate driving control signals according to the internal video signal, a data driver and a scan driver to process the driving control signals and to output the processed control signals to electrode lines of the EED panel. The electrode lines include cathode electrode lines and gate electrode lines, which receive RF high voltage from the data driver and the scan driver, and an anode connected to a high voltage power supply.
Voltages supplied to the cathode electrode lines, the gate electrode lines and the anode are very high compared with those supplied to logic circuits of the drivers. Therefore, when a high voltage element and a low voltage element make use of a common ground, RF noise generated by the high voltage element is transferred to the low voltage element through the ground, causing an error in the low voltage element, for example, a logic circuit.
Also, the cathode electrode lines, the gate electrode lines and the anode are supplied with different high voltages rather than equal high voltages. Thus, RF noise has a bad influence upon them mutually. Specifically, as a frequency of a high voltage pulse supplied to the drivers increases, RF noise increases as much. In a large-size panel, data signals and scan signals must be supplied to more pixels with respect to the same horizontal and vertical synchronization signals. Thus, the frequency inevitably becomes higher. As the panel becomes larger in size, it needs to be designed considering the noise.
Furthermore, when a digital logic element and an analog logic element operate at a high frequency, the low voltage elements (logic elements) can also be mutually influenced by RF noise. Thus, noise reduction is necessary between the digital logic element and the analog logic element.
In an EED, low voltage elements (logic elements) and high voltage elements are commonly grounded. One side of the EED includes a substrate on which high voltage elements and low voltage elements are mounted together, and another side includes a high voltage element.
The low voltage logic element includes digital logic elements and analog logic elements and usually operates with ±5 V. As to the high voltage elements, a high voltage of ±50-100 V is supplied to a gate electrode line or data electrode line of the EED panel. A high voltage of about 4000 V is supplied to an anode. As to the digital logic elements, the driver is supplied with a high voltage in order to control a high voltage, which is supplied to the data electrode lines and scan electrode lines of the panel.
Therefore, the logic circuits, such as the driver for controlling the high voltage, are low voltage elements on the one hand, but are high voltage elements on the other hand. Since the high voltage elements are driven at an RF high voltage, noise occurs therein. The noise influences the low voltage elements through the ground.
For example, noise occurring in the anode having an electrical potential of 4 kV can influence the digital logic element and the analog logic element through the ground. Also, RF noise occurring in the high voltage element can influence other digital logic elements through the ground. Thus, the EED has a problem in that the picture quality of the images displayed on the EED panel is degraded.

Electron Emission Display (EED) with separated grounds

Maetan-dong, Yeongtong-gu, Suwon-si, Gyeonggi-do


Examples communication methods and communications apparatus are described. In one example method, a base station sends a first synchronization signal block, where the first synchronization signal (SS) block includes a primary SS, a secondary SS, and information carried on a physical broadcast channel (PBCH). In addition, the base station sends a second SS block, where the second SS block includes a primary SS or includes a primary SS and a secondary SS, and does not include information carried on the PBCH. The first SS block is used by a terminal to access the base station. The second SS block is used to perform time and frequency synchronization after the terminal accesses the base station.

As communications technologies develop, a larger communication capacity is required, and existing frequency band resources can no longer satisfy the communication capacity requirement. Therefore, using frequency band resources of a high frequency (which is above 6 GHz, such as a millimeter-wave band or a centimeter-wave band) in mobile communications technologies becomes a trend of future development.
After being powered on, a terminal performs cell searching, learns of an identifier of a serving cell by searching for a synchronization signal (SS), and performs frame synchronization. The SS includes a primary synchronization signal (PSS) and a secondary synchronization signal (SSS). The SS may be periodically sent. After accessing a wireless network, the terminal may perform time and frequency synchronization by using the SS.
After high-frequency communication is introduced, a concept of synchronization signal block (SS block) is introduced. In addition to the primary synchronization signal and the secondary synchronization signal, a physical broadcast channel (PBCH) may further be transmitted on a resource of the SS block. In this case, sending the SS block to implement time and frequency synchronization of the terminal may cause a waste of resources.

Communication method and communications apparatus


A food steamer is described hereinafter. The food steamer includes a base unit, a steam basket supported on the base unit, a heating device configured in the base unit for converting water into steam, a water tank configured for supplying water for the heating device, a drip tray configured for collecting water drops from the steam basket, and an electronic controller configured for control the heating device. The heating device includes at least a steam outlet for jetting steam to the steaming basket. The water tank is detachably sited on the base unit and beside the steam basket. This food steamer can reserve much more water, extend the cooking time and shorten the time of steam generation, convenient and safe operation.

The present disclosure relates to improvement of a food steamer.
A currently available food steamer includes a base, a water tank, a heater, drip tray, one to three steam baskets. The water tank is fixed on the base. The heater has a shape of cap or plate, which is mounted in the centre of water tank. The drip tray is fitted on the water tank. The steam basket is set on the drip tray. A heater-cover is fitted and surround the cap or plate of the heater. When the water is filled in the water tank, the water go through from a hole of the heater-cover to the heater cap or plate. When the heater cap or plate is heated, the water become boiling and steam is generated. The steam rise and go into the steam basket for food cooking.
This food steamer has the disadvantage: the water tank is fixed on the base and limited by the size of the unit, it cannot be reserved much water for longer cooking food, so it needs to refill water in the midway during the cooking process and very inconvenient. The water tank is not detachable and the user only can fill the water or empty the water tank with the base together. Also it is very difficult to clean the water tank, during the water tank cleaning, the water may go easily to the inside of the base and may cause electrical danger. If the water tank capacity is increased the whole unit would become larger and higher, affecting the look and use friendliness, the cost may also be increased.
During the cooking procedure, the user needs to fill the water in to the heater cap or plate which surround with the heater-cover, then the heater heat up the water temperature to reach the boiling point to provide the steam, and some heat may transfer through the heater cover to the outside water, so the heater needs long time to product the steam for cooking. As the heater can not convert the water into the steam at once, the user can not cook the food immediately, it would affect the food taste and quality, it would also reduce the nutrition of the food due to the prolonged cooking process.
The heater cap or plate is exposed on the base, the user can be easy to touch the heater cap or plate that may burn the hand of user, and thus it is unsafe.
This invention concerns a food steamer which provides a large storage capacity of water that allows long time steam cooking, the heater device is mounted in the base and much faster and high efficiency of steam generation and heating, easy to use and safer operation.

Huiyang Allan Plastic & Electric Industries Co., Ltd.


The present invention provides a solid-state imaging device which compensates a field curvature which occurs due to an aberration of the optical imaging system and surely receive light incident with a wide angle. Each pixel (pixel size of 2.2 μm square) in a solid-state imaging device includes a light-transmitting film with the first effective refractive index distribution and a light-transmitting film with the second effective refractive index distribution, a light-receiving element, a wiring, a wavelength selection filter, and a Si substrate. A pixel (1) is a pixel placed an approximate center of the solid-state imaging device. A pixel (n) is a pixel placed in the periphery of the solid-state imaging device, and a pixel (n-x) is a pixel that are placed between the pixel (1) and the pixel (n). The light-transmitting film of each pixel has approximately same effective refractive index distribution. Θ0 which is a main light angle on the light-receiving element side, is approximately same. A main light angle in the optical imaging system is represented as Θ1, Θn-x, and Θn. The light-transmitting film varies for each pixel so that a condition Θ0/Θ1>Θ0/Θn-x<Θ0/Θn.

(1) Field of the Invention
The present invention relates to a solid-state imaging device utilized in digital cameras and the like, and particularly to a solid-state imaging device with a function for correcting a field curvature caused by aberration of an optical imaging system.
(2) Description of the Related Art
Together with the rapid spread of digital still cameras, cell phone cameras and the like, the market for solid-state imaging devices has significantly developed. In addition, along with an increasing demand for thinner digital still cameras and cell phone cameras, miniaturization of camera modules has become a major concern. Miniaturization of the camera modules requires reduction of the number of lenses for an optical system, and thus the focal length of the optical system becomes short. As a result, the reduction of the number of lenses makes it difficult to correct a field curvature caused by an aberration and incident light on a solid-state imaging device has a wide incident angle at the periphery (a wide angle against a vertical axis of an incidence plane of a solid-state imaging device).
On this account, a solid-state imaging apparatus or the like which corrects a field curvature caused by the aberration of an optical imaging system has been proposed (see Japanese Laid-Open Patent Application No. 2003-188366 (Patent Reference 1) and Japanese Translation of PCT International Application laid open as JP2004-526300 (Patent Reference 2)).
The solid-state imaging apparatus according to Patent Reference 1 is configured of thin-filmed solid-state imaging devices which are curved so as to fit a field curvature caused by an aberration of the optical imaging system. With this configuration, even if there is a field curvature caused by an aberration of an optical imaging system, imaging at a high resolution can be performed. In addition, with this configuration, since solid-state imaging devices are curved, an incident angle of light that enters in a solid-state imaging device is compensated.
In addition, in the optical imaging system according to Patent Reference 2, a step is installed for a curved surface corresponding to a field curvature which occurs due to the aberration of the optical imaging system, and microlenses of different focal lengths are set adaptively. With this configuration, it is possible to correct field curvatures. In addition, there is a disclosure of a technology regarding correction of a field curvature. According to this technology, diameter of microlens increases toward the periphery of a solid-state imaging device so as to change the focal length. In this case, light with a wide incident angle can be received relatively well since the diameter of the microlens is wider at the periphery of the solid-state imaging device.
However, with the technology disclosed in aforementioned Patent Reference 1, in the case where solid-state imaging devices are made of thin films or when devices are curved, there is a problem that a pixel defect such as white defect and the like occur due to stress caused by the curve. Furthermore, it is difficult to curve and fix the solid-state imaging devices to correct a field curvature.
In addition, with the manufacturing method for microlenses according to Patent Reference 2, it is difficult to make microlenses of different focal lengths. Note that in Patent Reference 2, the diameter of microlenses set for a solid-state imaging device increases toward the periphery of the solid-state imaging device. However, with this conventional manufacturing method for microlenses, it is difficult to manufacture microlenses of different diameters and of different focal lengths.

Solid-state imaging device using light-transmitting film as a micro lens


The compressor machine has two rotors rotating in opposite directions, which are fitted to two parallel, spaced apart shafts mounted in a housing. One of the shafts is driven directly and the other by intermeshing toothed gears mounted on the shafts. The housing has two radial walls which are configured in one piece with each other and with a peripheral wall and in which the shafts are mounted. The toothed gears are arranged between these radial walls. A side wall of the housing has an opening sealed by a removable cover. With the cover removed, the toothed gears can be fitted to the shafts through these openings. The bearing bores for the shafts can be produced and machined in the one-piece housing in a single set-up, so that, with a minimum number of parts, any causes of alignment errors are avoided.

Compressor machines with two rotors rotating in opposite directions can operate as compressors or vacuum pumps. EP 1 163 450 A1 discloses a machine of this type, having claw-type rotor blades, which is adapted to generate both suction air and blown air and is particularly suitable for use in the field of paper processing. The internal compression of machines of this type allows to attain markedly higher pressure ratios than for instance by means of a Roots pump. The cantilevered arrangement of the rotors in a pot-shaped housing results in a simple structure. However, the gear that couples the two shafts, on the one hand, and the shaft mounting, on the other hand, are disposed in separate housing parts which need to be exactly aligned with each other and pinned together. Similarly, the pot-shaped housing accommodating the rotors needs to be precisely pinned together with the gear casing. This results in the requirement of having to machine pin holes from two different sides of a housing part as precisely as possible. Any imprecision will lead to slanting shafts and thereby to increased bearing loads, toothed gear noises, and other malfunctions.

Compressor machine with two counter-rotating rotors


A timepiece having a movement having a hammer and a hammer drive device that drives the hammer, a case that houses the movement, a sound source that produces sound by vibrating when struck by the hammer, and a striking force transmission member that can move bidirectionally between the hammer and the sound source, and transmits the striking force of the hammer to the sound source.

1. Field of Invention
The present invention relates to a timepiece and a portable device that have a sound source such as a gong or a bell.
2. Description of Related Art
Sonnerie timepieces that have a C-shaped gong and a hammer for striking the gong are known from the literature. See, for example, "2002 Guide to the latest wristwatches with full specifications," K. K. Gakushu Kenkyusha, published Mar. 1, 2002, page 117. The timepiece in this example has the gong fastened to the base plate and disposed along the outside of the movement. The hammer is attached to the base plate on the inside of the gong so that the hammer can pivot, and is driven at a predetermined time by the drive power of a spring. A spring that returns the hammer that strikes the gong to its original position is also attached to the base plate.
The sonnerie timepiece according to the related art described above strikes the gong directly with a hammer, and a spring that urges the hammer toward the gong when striking the gong and another spring that pulls the hammer away from the gong and back to its original position after striking the gong are disposed to the hammer. However, in a mechanism such as this that has springs urging the hammer in two different directions disposed to the hammer, the hammer may not separate from the gong after striking the gong, and may therefore inhibit vibration of the gong, if the spring force of the spring that urges the hammer to the gong is high. On the other hand, if the force of the spring that pulls the hammer away from the gong is strong, the hammer strikes the gong with less force and the gong may not produce a good sound. It is therefore necessary to appropriately set the strength of these springs.
However, if the springs urging in opposite directions are attached directly to the hammer, adjusting the force of each spring appropriately is difficult.


A car includes a car body having a bottom portion, a wheel that is rotatable, and a supporting member for supporting the wheel, the supporting member being provided to the bottom portion. At least eight pairs of the wheel and the supporting member are provided. The supporting member has a first supporting portion for supporting the wheel rotatably, a second supporting portion for supporting the first supporting portion so that a direction of the wheel supported by the first supporting portion can be changed, and a turning portion that is rotatable about a rotation axis with its axial direction along a direction orthogonal to the bottom portion, the turning portion being provided to the bottom portion. The turning portion supports the second supporting portion so that a distance between the wheel and the bottom portion can be changed, and a position of the wheel can be moved by a rotation of the turning portion in a state that the distance is maintained.

1. Technical Field
The present invention relates to cars.
2. Related Art
Cars are well-known. The car includes a car body having a bottom portion, a rotatable wheel, and a supporting member for supporting the wheel provided at the bottom portion, and the car runs in a predetermined traveling direction by the rotation of the wheel (refer to JP-A-2002-227883).
By the way, a typical well-known car has four wheels, and some or all of the four wheels are driven, so that the car runs in a predetermined traveling direction. Although, the car can turn by changing the direction of the wheels or back up by rotating the wheels in a reverse direction, the variety of movements is such that it is limited.


There is provided a dual pump floating layer recovery apparatus for pumping a floating layer of contaminant out of a well. The apparatus comprises an upper pump and a lower pump. The lower pump creates a cone of depression which increases the amount of the floating layer within the well. The upper pump pumps the contaminant from the well or cone of depression. The upper and lower pumps preferably are gas-actuated pumps. The lower pump preferably includes an automatic switching device to activate the lower pump upon sensing a predetermined amount of fluid within the pump. A gas conduit interconnects the actuation chambers on both pumps such that when the lower automatic pump is provided with pressurized gas, the upper pump is simultaneously provided with the identical pressurized gas. Upon deactivation, both pumps relieve the activation pressure through the lower pump.

Recent increases in public concern for the environment have resulted in various government imposed environmental regulations. Among such regulations are requirements relating to the monitoring of groundwater quality. In response to these requirements, water quality analytic capabilities have been improved and water sampling equipment has been developed. Increased monitoring and sampling of groundwater and environmental quality has resulted in a substantial increase in the number of identified sites of contaminated groundwater. Along with the identification of an increased number of contaminated sites has been an increased effort to clean up these sites. This effort at cleaning of contaminated groundwater has lead to a need for improved below ground pumping systems to assist in these clean up efforts.
Once it has been determined that groundwater is contaminated, the clean up effort will often include decontamination of the groundwater by pumping the contaminant from the well. This is feasible where, for example, the contaminant is a floating layer lying above the groundwater. By selectively pumping the contaminant from the groundwater the site may be thereby decontaminated. An added benefit and incentive to pumping groundwater contaminants, such as hydrocarbons, is that the pumped contaminants may be recycled for reuse. Much of the previously developed floating layer equipment has not been effective, however, in permitting the efficient pumping of the floating layer to the exclusion of the groundwater.
It is common to employ what is known as a dual pump system to recover contaminants that are floating on the water within a well. The dual pump system uses a lower pump submerged in the groundwater to create a draw-down in the recovery well by the action of its pumping. This draw-down extends out away from the well and forms what is known as a "cone of depression". The cone of depression defines an area around and away from the recovery well where the natural static water level is lowered, or depressed and the contaminant is induced to flow toward and collect in the recovery well. A second, upper or product pump is then used to pump the contaminant. In this way, the contaminant is collected at a higher rate than by pumping the contaminant alone. In the preferred embodiment, the lower pump removes pure groundwater and the upper pump removes pure contaminant.
Many different types of pumps have been used for both the lower draw-down pump and the upper contaminant pump. For lower recovery wells it is common to use the various types of pneumatic pumps for both functions. When using pneumatic pumps for both the upper and lower pumps, the question of control of the pumps and the coordination of the two pumps working together has always been a costly and complex problem. Whether used for the upper or lower pump, pneumatic pumps are normally under the control of a surface located pneumatic control unit. While the surface located control unit has been used successfully for these types of pumps, there are additional costs and complexity which are added to the cost of the pump itself. When attempting to control two pumps and coordinate the pumping action of both pumps, there is an additional increase in both the cost and complexity of the total system. The cost and complexity can be somewhat reduced by using the pumps which avoid the necessity of external controllers by incorporating sensing means within the pump to detect when fluid has entered the pump to a desired level. Unfortunately, the use of these type of pumps alone does not solve the linking of the two pumps to operate as a total system.
Accordingly, what is needed is a dual pump system which reduces both the cost and complexity of controlling the total pumping system when the two pumps are working together to remove a floating layer of contaminants.
Additional objects, advantages and features of the present invention will become apparent from the following description and appended claims taken in conjunction with the accompanying drawings.

Dual pump floating layer recovery apparatus


A system for identifying artifacts in an image. The system includes an input for receiving images from an imager, the images comprising a pixel of interest. The images can be generated by reflecting light off an object. The system further includes a processor coupled to the input for defining and using at least one contrast value of a second pixel associated with the pixel of interest to identify artifacts in the image.

There are a number of applications in which it is of interest to detect or image an object. The object may be detected in daylight or in darkness, depending on the application. Wavelength-encoded imaging is one technique for detecting an object, and typically involves detecting light reflecting off the object at two or more particular wavelengths. Images of the object are captured using the reflected light and the presence of the object is then detected in the images. Light reflecting off elements other than the object result in artifacts in the captured images.
FIG. 1 is a graphic illustration of a conventional image 100. Image 100 includes object 102 and artifact 104. Object 102 is the object to be detected, but artifact 104 can make it difficult to detect object 102. A system designed to detect object 102 may mistake artifact 104 for object 102, thereby resulting in a false detection of object 102. Alternatively, the system may be unable to distinguish object 102 from artifact 104 and therefore fail to detect the presence of object 102 in image 100.
A system for detecting artifacts in an image would be an improvement over the art.

Contrast-based technique to reduce artifacts in wavelength-encoded images

Avago Technologies General IP (Singapore) Pte. Ltd.


A mono-gate memory device and fabricating method thereof are provided, which may reduce or solve over-erasing problems by implementing a mono split-gate SONOS type non-volatile memory cell, and which do not affect logic circuit characteristics by enabling logic circuit fabrication after completing the ONO structure. The present memory cell includes an ONO layer on the active area of the substrate, a gate oxide layer on the active area adjacent to the ONO layer, a gate on the gate oxide layer and on a portion of the ONO layer, a drain partially covered by the ONO layer, and a source partially covered by the gate oxide layer.

1. Field of the Invention
The present invention relates to a memory device and fabricating method thereof, and more particularly, to a mono-gate memory device and fabricating method thereof, in which a mono split-gate is provided by forming an ONO (oxide-nitride-oxide) layer prior to a logic circuit process and forming polysilicon on the ONO layer and the like.
2. Discussion of the Related Art
Generally, semiconductor devices are categorized into a volatile memory and a non-volatile memory. RAMs such as DRAM (dynamic random access memory), SRAM (static random access memory), and the like belong to the volatile memory category, which enables data input and storage with power application thereto only, but fails to keep storing data therein since the stored data is lost in case of power removal.
In a fabricating process, the non-volatile memory devices are categorized into (i) a floating gate type and (ii) an MIS (metal insulator semiconductor) type having a multi-layer (dual or triple layer) of at least two kinds of dielectric materials.
The floating gate type memory device implements memory characteristics using a potential well, and mainly employs an ETOX (EPROM tunnel oxide) structure applicable to flash EEPROM (electrically erasable programmable read only memory).
On the other hand, the MIS type memory device performs a memory function using charge traps in a dielectric bulk, at a dielectric-to-dielectric interface, and/or at a dielectric-to-semiconductor interface, and mainly employs a MONOS/SONOS (metal or silicon/oxide-nitride-oxide [ONO]/semiconductor) structure, which is also applicable to flash EEPROM.
FIG. 1 is a cross-sectional diagram of a conventional SONOS type memory device. Referring to FIG. 1, the SONOS type memory device includes a tunnel oxide layer 101, a trap nitride layer 102, a block oxide layer 103, and a gate 104, stacked in turn on a P type silicon substrate 100 provided with a source 105 and drain 106.
The SONOS type memory device in FIG. 1 is a charge-trap type device using a mechanism in which an electric charge tunnels through oxide film 101 on silicon 100 by a voltage applied to gate 104, causing electric charges to be injected into or to be released from a trap within silicon nitride layer 102 or at its interface with oxide film 101. In this case, a thin ONO layer is used instead of polysilicon to decrease the overall thickness of the memory device, relative to the floating gate type device. Moreover, using a tunnel oxide layer below several nanometers, it is able to remarkably reduce a size of a memory cell. Hence, SONOS type memory devices enable a high degree of integration, as well as a remarkably lowered drive voltage.
However, in case of the conventional SONOS memory device, leakage current generated from a non-selected memory cell is regarded as flowing from a selected memory cell. For instance, an over-erase phenomenon appears to lead the selected memory cell to be misread as erased on programming. Hence, the SONOS cell design or configuration may affect the logic circuit characteristics of the memory device.

Mono gate memory device and fabricating method thereof