A tonneau cover is arranged to mount on the truck box of a conventional pick up truck for enclosing the box. The cover comprises a pair of panels which are pivotally mounted on respective sides of the box. The panels extend laterally inward such that free ends of the panels engage each other in a closed position. The panels may be pivoted upward and secured in an upward orientation by a pair of rails connected between the free ends of the respective panels in an extended position of the panels. The panels form a pair of side walls in the extended position for supporting large cargo in the box. The rails form a rack in the extended position for supporting additional cargo thereon. A locking device secures the panels in the closed position while a plurality of struts provides additional support to the panels when pivoting the panels between the closed and extended positions.

Conventional pick up trucks generally have a truck box on a rearward end for carrying cargo. The use of a tonneau cover which is secured to the truck box is common for enclosing the truck box and for preventing theft of the cargo while the vehicle is unattended.
In U.S. Pat. No. 5,110,021 (Dawson) issued May 5, 1992 is disclosed a tonneau cover which includes two separate panels each of which is hinged to a respective side wall of the truck box. Each panel can pivot from a raised position in which it stands generally upwardly from the side wall to a closed position in which it lies generally horizontally across the truck box so that the two panels in the middle and close the open top of the truck box. A pair of rails are provided each mounted on a respective one of the panels and each extending from that panel to the other panel. The rails are spaced so that one is toward the front and one is toward the rear to hold the panels in the raised position and to act as a support for a load over the truck box. This arrangement has achieved no commercial success and the construction shown in the patent is of a simple and schematic nature with little attention to the important details of the mounting of the construction on the truck. box.
U.S. Pat. No. 6,224,140 (Hoplock) issued May 1, 2001 discloses a further device of the same general type which gives further details concerning constructions of the device and how it is attached to the side walls of the truck box. Again however this device has achieved no commercial success requiring a significant redesign of the construction.
In U.S. Pat. No. 6,340,915 (Hall) issued Jan. 22, 2002 is disclosed an arrangement of this general type and in particular shows a locking arrangement for locking the edge of one panel to the next adjacent panel to hold the panels in closed position.
In U.S. Pat. No. 6,254,169 (Arthur) issued Jul. 3, 2001 is disclosed a hinging arrangement for attachment of the panels to the top wall of the truck box.
In U.S. Pat. No. 6,598,930 (Tilton) issued Jul. 29, 2003 is disclosed a further arrangement of this type which includes a locking arrangement for locking the edge of one panel relative to the other.
In U.S. Pat. No. 6,799,784 (Rios) issued Oct. 5, 2004 is disclosed an arrangement of this type which is particularly concerned with the mounting of the transverse rails to the underside of the panels.
None of the above devices has achieved commercial success and it is believed that this is primarily due to failure of the products to apply sufficient attention to the construction and details of the mounting arrangement and the formation of the panels by which the panels can be properly mounted and provide a proper stable structural arrangement which can be carried on the truck box and held in position without deformation or twisting.


A digital TV and a driving method thereof enable a user to view the digital TV without interruption even if the present operating system is in an abnormal state. The digital TV includes a digital TV receiving part for receiving and decoding a broadcasting stream from an outside, a host CPU for controlling the digital TV receiving part, a local CPU for controlling the digital TV receiving part if the host CPU operates in an abnormal state, and a programmable logic device for switching the control of the digital TV receiving part from the host CPU to the local CPU if the host CPU operates in the abnormal state.

1. Field of the Invention
The present invention relates to a digital TV (television receiver), and more particularly to a digital TV and a driving method thereof which enable a user to view the digital TV without interruption even if the presently used operating system is in an abnormal state.
2. Description of the Related Art
Web boxes or Internet TVs mainly use Windows™ or Linux™ as their operating system for the convenience of users.
However, if the operating system becomes unstable, the system should be rebooted. If the operating system is rebooted as above, all application programs, which are operating in the present system, should be terminated.
In order to solve this problem, the existing digital TV receivers heighten their reliability by using an embedded operating system having a high stability. However, such an embedded operating system has the drawbacks in that it cannot provide a user-friendly interface.
Also, the embedded operation system has many difficulties in implementing functions, which electric home appliances should necessarily have, by a web browser and so on.
Accordingly, in order to solve the problems, many manufacturers have developed many PC-based digital TVs having the operating system such as Windows™ or Linux™.
However, if many applications are simultaneously driven under the above-described operating system, the reliability of the operating system may deteriorate. That is, due to an error of the operating system, the operation of the PC system may be stopped. As a result, if the rebooting of the PC causes any problem in a receiving part of the digital TV, the use value of the PC-based digital TV may deteriorate. Accordingly, even if the operating system operates in error, it is required for the user to continuously view the PC-based digital TV.
In the PC-based digital TV operating system, due to the error of the applications programs, the system is stopped more frequently than the embedded operating system. Accordingly, if the receiving part of the digital TV can be controlled even though the system is stopped due to the error of the application programs, the viewer will be able to view the digital TV without interruption.

Digital TV with operating system and method of driving same


A manufacturing method of a semiconductor device includes the steps of forming an insulating film having a prescribed repetition pattern on one surface of a semiconductor substrate and then depositing semiconductor layers on the one surface of the semiconductor substrate; forming trenches from the other surface of the semiconductor substrate in such a manner that the trenches come into contact with the semiconductor layer, that plural trenches are formed for each semiconductor chip to be formed on the semiconductor substrate, and that at least one pattern of the insulating film is exposed through the bottom of each trench; and covering the inside surfaces of the trenches and the other surface of the semiconductor substrate with a metal electrode.

The present invention relates to manufacturing methods for a high-breakdown-voltage, high-power vertical insulated-gate semiconductor device and rectification element (diode). More specifically, the invention relates to an IGBT and a MOSFET having an insulating film formed on the surface of a semiconductor layer or in trenches and a control electrode formed on the insulating film, a pn junction diode not having such a control electrode, and like devices.
To satisfy the recent requirements of miniaturization and enhanced performance of power source equipment in the power electronics field, efforts have been made in a concentrated manner to improve the performance, more specifically, to increase the breakdown voltage, increase the current, decrease the loss, increase the breakdown resistance, and increase the operation speed, in power semiconductor devices used in such power source equipment. In medium to high breakdown voltage range of 600 V to 6,500 V, insulated-gate bipolar transistors (hereinafter abbreviated as IGBTs) are the mainstream of power semiconductor devices. In IGBTs in the breakdown voltage range of 600 V to 1,700 V, remarkable improvements have been made in breakdown voltage among the above-mentioned various characteristics. The wafer thinning technique is a major technique that supports such improvements in the characteristics of IGBTs.
A device wafer process of the wafer thinning technique is as follows. First, a main device structure is formed on an FZ high-resistivity n− silicon wafer. At a stage that is close to a final step of device formation, the wafer is ground from its back side to such a thickness that a necessary device breakdown voltage can be secured and a sufficiently low loss characteristic can be obtained. A shallow p-type collector layer and a deep n-type layer are formed by implanting impurity ions through the thus-ground wafer back surface and a metal electrode is contact-formed on the back surface. (T. Laska et al., "The Field Stop IGBT (FS IGBT)—A New Power Device Concept with a Great Improvement Potential," IEEE ISPSD 2000, pp. 355-358)
However, to secure a necessary device breakdown voltage and attain a low-loss characteristic, the wafer thickness after grinding is about 60 to 70 μm in devices having a breakdown voltage of 600 V and has a very small value of 100 μm+α in devices having a breakdown voltage of 1,200 V. If an 8-inch wafer, for example, having such a small thickness is handled and subjected to ion implantation and electrode formation from the back side, there is a very high probability that the wafer is broken during that course of processing. Accordingly, productivity cannot be increased easily. Furthermore, since ion implantation and activation are performed from the wafer front side at a stage that is after formation of a main device structure on the wafer front surface and close to a final step, the activation anneal temperature is restricted to 600° C. or less. This makes it difficult to control the impurity concentrations and the thicknesses of the p-type collector layer and the low-resistivity n-type layer.
On the other hand, the manufacturing process of what is commonly called a punchthrough IGBT using a thick wafer, which was employed before the invention of the wafer thinning technique, is as follows. An IGBT is formed by inputting, to a manufacturing process, a thick wafer in which an optimum-designed low-resistivity n-type layer and high-resistivity n− drift layer are epitaxially grown in advance on a low-resistivity p+ silicon substrate of 300 to 500 μm in thickness. In this method, the impurity concentrations and the thicknesses of the low-resistivity n-type layer and the high-resistivity n− drift layer are optimum-designed in advance and the thickness of the wafer (low-resistivity p+ silicon substrate) is as sufficiently large as 300 to 500 μm. Therefore, there is almost no probability that the wafer is broken during a device formation process and hence productivity using this process is high.
However, since the impurity concentration of the low-resistivity p+ silicon substrate is high and its thickness is too large, the minority carrier injection efficiency during an IGBT operation is very high. For example, it is known that an IGBT formed by this process is much worse in the on-voltage vs. turn-off loss characteristic etc. than an IGBT formed by the wafer thinning process even if such electrical characteristics as the turn-off characteristic are adjusted by a lifetime control process.
To solve this problem, in the above thick wafer process, a method has been proposed in which a low-resistivity p+ silicon substrate is ground from the back side at a final stage of the process to reduce its thickness to such an extent that it becomes a p-type collector layer of about 1 μm in thickness, and the minority carrier injection efficiency becomes low whereby the on-voltage vs. turn-off loss characteristic is improved (Tomoko Matsudai et al., "Advanced 60 μm Thin 600V Punch-through IGBT Concept for Extremely Low Forward Voltage and Low Turn-off Loss," IEEE ISPSD 2001, pp. 441-444).
Furthermore, the following technique is described in JP-A-2002-76326 (abstract and paragraph 0026), in which a semiconductor functional portion is formed on one surface of a bonded semiconductor substrate. As for the other surface, whereas an outermost peripheral portion of each semiconductor chip is left in a frame form, the central portion is etched away to form a recess in such a manner that the thickness of the bottom portion of the recess is reduced to a limit value that secures necessary semiconductor characteristics. The recess is filled with a metal. In this manner, a semiconductor device having a low switching loss is formed while a manufacturing process using a thick, large-diameter semiconductor substrate is executed. Also disclosed are methods for detecting an etching end point in etching the back side of the semiconductor substrate in a frame form. In one method, an etching method is employed in which a substrate obtained by bonding semiconductor substrates having different crystal face orientations is used and etching anisotropy is provided because of the different crystal face orientations. Etching is performed at a correct depth from the back surface to the bonding boundary. In another method, an etching method is employed in which an insulating film is formed at the bonding boundary and used as an etching end point sensor.
Still further, a vertical MOSFET is known which has a trench gate structure and a trench drain opposed to it (See Japanese Patent No. 3,957,638). Trench gate bottoms and a semiconductor substrate that faces the trench gate bottoms are insulated from each other by an oxide film and trench drains penetrate through the oxide film and are in contact with the semiconductor substrate.
However, in the thick wafer grinding method of Matsudai et al., since the wafer grinding accuracy is usually about ±5 μm, the p-type collector layer may be lost entirely by excessive grinding when it is formed by grinding the thick, low-resistivity p+ silicon substrate in a final step so as to leave a 1-μm-thick layer. In this case, the on-voltage becomes very high. Conversely, if a p-type collector layer that is thicker than the design value 1 μm is left, a drawback arises that the loss characteristics vary to a very large extent as exemplified by a large turn-off loss. Furthermore, in the thick wafer grinding method of Matsudai et al., the thickness of a ground wafer is 60 to 70 μm. Therefore, as in the wafer thinning technique of Laska et al., there is a drawback that a wafer may be broken in steps that follow the step of thinning the wafer, such as a back surface electrodes forming step. As such, the thick wafer grinding method of Matsudai et al. has not been put into practical use yet.
That is, in the wafer thinning technique of Laska et al., an optimum design value of the thickness of the p-type collector layer can be attained more reliably than in the thick wafer grinding method of Matsudai et al. but a wafer is prone to be broken during a process (i.e., the productivity is low). In the thick wafer grinding method of Matsudai et al., optimum design values of the impurity concentration of the p-type collector layer and the impurity concentration and the thickness of the low-resistivity n-type layer can be realized and the productivity in terms of a low likelihood of wafer breakage during a process is high. However, it has a problem that device characteristics are made very bad due to thickness variation of the p-type collector layer.

Manufacturing method of a semiconductor device

Fuji Electric Device Technology Co., Ltd.


The disclosure provides a method of immunotherapy for a cancer patient, comprises administering vaccines against Globo series antigens (i.e., Globo H, Stage-specific embryonic antigen 3 “SSEA3” and Stage-specific embryonic antigen 4 “SSEA4”). Specifically, the method comprises administering Globo H-KLH (OBI-822) in patients with Metastatic Breast Cancer. The disclosure also provides a method of comprises selecting a cancer patient who is suitable as treatment candidate for immunotherapy. In addition, the disclosure provides therapeutic agents, including monoclonal antibodies (mAbs) that bind specifically to Globo series antigens and related biomarkers useful in focusing such therapeutic and diagnostic regimens.

The carbohydrate antigen Globo H (Fucα1→2 Galβ1→3 GalNAcβ1→3 Galα1→4 Galβ1→4 Glc) was first isolated as a ceramide-linked Glycolipid and identified in 1984 by Hakomori et al. from breast cancer MCF-7 cells. (Bremer E G, et al. (1984) J Biol Chem 259:14773-14777). Further studies with anti-Globo H monoclonal antibodies showed that Globo H was present on many other cancers, including prostate, gastric, pancreatic, lung, ovarian and colon cancers and only minimal expression on luminal surface of normal secretory tissue which is not readily accessible to immune system. (Ragupathi G, et al. (1997) Angew Chem Int Ed 36:125-128). In addition, it has been established that the serum of breast cancer patient contains high level of anti-Globo H antibody. (Gilewski T et al. (2001) Proc Natl Acad Sci USA 98:3270-3275; Huang C- Y, et al. (2006) Proc Natl Acad Sci USA 103:15-20; Wang C-C, et al. (2008) Proc Natl Acad Sci USA 105(33):11661-11666). Patients with Globo H-positive tumors showed a shorter survival in comparison to patients with Globo H-negative tumors. (Chang, Y-J, et al. (2007) Proc Natl Acad Sci USA 104(25):10299-10304). These findings render Globo H, a hexasaccharide epitope, an attractive tumor marker and a feasible target for cancer vaccine development.

Cancer immunotherapy by immune activation or immune modulation via Globo series antigens


A light electric dental flosser with a rechargeable battery compartment includes a motor casing, interchangeably individualized head units, and disposable plastic floss tips that snap mount within the hinged end of the head unit. The floss tips exhibit bidirectional flossing motion provided from a motion translation system including an eccentric cam, a yoke, and an output shaft with a cam follower mechanism that follows a generally Z-shaped tracking surface with a vertical track component and a horizontal track component enabled by the yoke to complete the resulting "Z" movement. The floss tips have a molded-in filament and are molded from a shock absorbing substance which absorbs the vertical component of the "Z" shaped motion upon the application of pressure to the filament thereby outputting horizontal motion until the filament passes through the contact area between two teeth. In an automatic mode, an infrared sensor in the head activates the motor when the line of sight between infrared sensors is broken by the filament approaching a contact area between two teeth.

Satisfactory oral hygiene practices include the use of dental floss as an interdental cleaner. Approximately ninety percent (90%) of all dental disease originates between the teeth, an area ineffectually cleaned by existing manual and electric tooth brushes. Unchecked bacterial proliferation between the teeth may cause dental plaque and consequent gum disease. Gum disease is the leading cause of tooth loss.
Dental floss is currently the most widely prescribed interdental cleaning aid. For manual use, the individual typically maneuvers a length of dental floss back and forth across the contact point between two teeth until the floss passes through the contact point into the interproximal space between the teeth. The floss is then pressed against the tooth surface and moved vertically up and down against the surface to clean the tooth.
Proper use of dental floss is essential for thorough interdental cleaning. Proper manual flossing technique includes horizontal motion of the floss until the floss passes through the contact point, followed primarily by vertical movement of the floss to clean the tooth once the floss is in the interproximal area.
Frequently, users mistakenly apply downward pressure to force the floss through a tight contact point thereby causing the floss to snap against the gingiva causing damage thereto, such as "floss cuts". Gingiva damage from improperly flossing techniques may contribute to the formation of gum disease.
Most adults have silver or composite filling materials between the teeth which increase the difficulty in maneuvering the floss through tight contact points. Dental fillings frequently include sharp or irregular edges which may cause the floss to shred, break or become stuck in the contact area. Users may also fail to vertically manipulate the floss against the tooth in a manner calculated to clean the entire tooth surface.
The principle reported problem with dental floss is the publics' reluctance to floss on a regular basis, or to floss at all. Individuals are reluctant to place their fingers in the mouth. Studies have also shown that individuals report dental floss is difficult to handle, and that flossing is extremely unpleasant, hard to perform, and time consuming.
Dental floss holders and threaders are available to eliminate the necessity of placing the fingers in the mouth while flossing. Such floss holders do not solve the problem of incomplete and improper manual flossing techniques.
Power driven dental flossing devices are described in prior art literature, but tangible prototypes and/or commercial embodiments of such devices are not believed to exist. A number of these described devices merely reciprocate floss between the teeth. Such devices are described in U.S. Pat. No. 3,759,274 and U.S. Pat. No. 4,014,354.
Several prior art power driven dental flossing devices combine reciprocation of floss and vertical oscillation. One such device is described in U.S. Pat. No. 4,706,695. The user is required to manually work the floss through the contact point prior to powered advancement of floss through a vertically oscillating, tined tip to a take-up spool for used floss. U.S. Pat. No. 4,338,957 incompletely describes a flosser with reciprocating floss and vertical oscillation. The device in U.S. Pat. No. 4,307,740 is similar to the '957 device and includes vertical oscillation with simultaneous reciprocation of floss.
Another prior art flosser is found in U.S. Pat. No. 4,605,025 which describes circular or ovoid floss oscillation produced by vertical motion from an oscillating unit. U.S. Pat. No. 4,235,253 describes a flosser where the floss must be worked manually through the teeth prior to vertical oscillation. U.S. Pat. No. 4,245,658 describes horizontal movement applied to the headpiece which holds the tines.
Other prior art power driven flossing devices are designed to attach to power tooth brushes, such as the device shown in U.S. Pat. No. 4,830,032.
None of the above described prior art flossers provide automatic, powered, high torque horizontal motion through the tight contact points with a vertical motion component added in the interproximal space. Additionally, most of the described devices use spools of dental floss which undesirably store bacteria contaminated, used floss within the device, and which require the user to periodically perform floss replacement and difficult manual re-threading operations.
As may be seen by the above discussion of the prior art, a heretofore unmet need exists for a power driven dental flosser that is easy to use, safe, provides high torque horizontal motion to pass the floss through the tight contact points without snapping the floss against the gums, and then provides a combined vertical/horizontal pattern of motion while the floss is in the interproximal area to effectively remove bacterial plaque in this critical area.


A standard characteristic which is an average characteristic of multiple samples is approximated in a polygonal-line fashion by first to third lines. The coordinate-point positions of the first and second lines at comparison adjustment points are stored as standard data in a data memory of an electronic control apparatus. An actual-product characteristic as a calibration target is approximated in a polygonal-line fashion by first to third lines. The resistance value of a label resistor is adjusted to a value corresponding to ratios of monitoring outputs. The electronic control apparatus reads the resistance values of one or two label resistors, combines them with the stored standard characteristic, and interpolates a third line portion, thereby restoring and generating the actual-product characteristic.

1. Field of the Invention
The present invention relates to improvement in an electronic control apparatus that includes a microprocessor performing drive control for an electric load group in accordance with the operation state of an input sensor group and the content of a program memory, and in which a specific sensor of the input sensor group has a label resistor for calibrating a device-variability variation in the detection characteristic of the specific sensor, or a specific load of the electric load group has a label resistor for calibrating a device-variability variation in the output characteristic, and relates to improvement in a control characteristic adjustment method for the electronic control apparatus.
2. Description of the Background Art
An electronic control apparatus is known in which: a specific sensor or a specific load is used which has a label resistor for calibrating a device-variability variation in a detection characteristic which is a relationship of measurement input-to-detection output of an input sensor, or in an output characteristic which is a relationship of control input-to-generated output of an electric load that is an electromagnetic actuator such as a motor or a solenoid; a microprocessor reads a resistance value of the label resistor; and the detection characteristic of the applied specific sensor or the output characteristic of the applied specific load is accurately recognized by the read resistance value.
For example, according to "GAS SENSOR, CONNECTOR OF GAS SENSOR, AND GAS CONCENTRATION DETECTION APPARATUS" of Japanese Laid-Open Patent Publication No. 11-281617 (see FIGS. 4 and 8 and paragraphs [0062] and [0065], hereinafter, referred to as Patent Document 1), as shown in FIGS. 23A to 23C, a label resistor RL is provided at a connector portion for external connection of a gas sensor that detects an oxygen concentration based on a first pump current IP1 (see FIG. 23A) and detects a NOx concentration based on a second pump current IP2 (see FIG. 23B), and ranks 1 to 36 are allocated on a two-dimensional map using six grades of correction coefficient β of −2, −1, 0, 1, 2, 3 for the first pump current IP1 and six grades of correction coefficient α of −2, −1, 0, 1, 2, 3 for the second pump current IP2 (see FIG. 23C). Then, one of the ranks 1 to 36 is specified by the resistance value of the label resistor RL, and as a result, the correction coefficients α and β are determined. Then, the oxygen concentration and the NOx concentration are detected by predetermined arithmetic expressions (1), (3), (4), and (5).
In addition, according to "INJECTOR AND FUEL INJECTION SYSTEM" of Japanese Laid-Open Patent Publication No. 2000-220508 (see FIGS. 14 and 18 and paragraphs [0064] and [0067], hereinafter, referred to as Patent Document 2), a correction resistor is provided on an injector so as to correct a device-variability variation included in the output response characteristic of a fuel injection electromagnetic valve. As shown in FIGS. 24A and 24B, in order to calculate an injection pulse period for determining a valve opening period of the fuel injection electromagnetic valve required for an instruction injection amount for obtaining a target fuel injection amount, a corrected injection pulse period characteristic indicated by a dotted line is generated which is obtained by algebraically adding first and second reference correction amounts to a basic injection pulse period characteristic indicated by a solid line in FIG. 24A.
For each of the first and second reference correction amounts, five grades of correction amounts of −20, −10, ±0, +10, +20 μs can be selected. Ranks 1 to 25 are allocated on a two-dimensional map using the first and second reference correction amounts (see FIG. 24B), and one of the ranks 1 to 25 is specified by the resistance value of the correction resistor.
The specific sensor of Patent Document 1 which is the gas sensor has a feature of being capable of determining the two types of correction coefficients α and β by one label resistor. However, each of the correction coefficients α and β is used for correction of a proportional gain GP1st(β) or GP2st(α) of the first pump current IP1 and the second pump current IP2, and an offset component IP2off of the second pump current IP2 is not corrected but a constant value is applied thereto.
Thus, a concept of performing correction, using a label resistor, for a detection characteristic including an offset component or a curved detection characteristic which is at least difficult to be represented as a linear line, is not shown, and in the case of such a complicated curved detection characteristic, characteristic data needs to be transmitted via an IC memory.
It is noted that, according to FIGS. 6A and 6B of Patent Document 1 showing the second embodiment thereof, a correction resistor Rc1 for adjusting the proportional gain of the first pump current IP1, a correction resistor Rc2 for adjusting the proportional gain of the second pump current IP2, and a correction resistor Rc3 for adjusting the offset current of the second pump current IP2 are used as circuit components of an amplifier circuit in a detection apparatus. In such a hardware style, there is a problem that noise malfunction can occur when a weak current signal circuit is connected to the outside of the detection apparatus or that the hardware cost of the detection apparatus increases.
In addition, the specific load of Patent Document 2 which is the injector merely corrects a device-variability variation in a response time of the fuel injection electromagnetic valve, but variability correction for a proportional gain which determines the relationship between the magnitude of an instruction current for the fuel injection electromagnetic valve and the injection pulse period is not taken into consideration.
In addition, a concept of performing correction by a correction resistor when the injection pulse period is not represented as a simple linear line, is not shown. In the case of such a complicated curved detection characteristic, characteristic data needs to be transmitted via an IC memory.

Electronic control apparatus and control characteristic adjustment method for the same having a label resistor for calibrating a device-variability variation


A magnetic memory device in which the memory cell of MRAM is reduced in size, and a method for producing the magnetic memory device are provided. The lower wiring is formed below the word line. The connecting hole and the plug connected to it are provided. The reading wiring and the lower layer wiring are connected through this plug. Alternatively, the local wiring is provided in the connecting hole and the reading wiring and the lower layer wiring are connected. In this way it is possible to form the connecting hole close to the word line, and hence it is possible to reduce the cell size in the direction along the bit line.

The present invention relates to a magnetic memory device and a method for production thereof. The magnetic memory device is a magnetic random access memory (MRAM) of nonvolatile type consisting of memory elements each having a magnetization pinned layer in which the direction of magnetization is pinned and a magnetic layer in which the direction of magnetization is variable, with one laid on top of the other.
The recent wide spread of information and communications equipment, particularly personal small ones such as portable terminals, requires their constituents (such as memory elements and logic elements) to have improved performance, including high integration, high speed, and low power consumption.
Particularly, non-volatile memory is regarded as indispensable in the age of ubiquitous computing because it preserves personal important information in case of dead battery and network failure or server breakdown. Recent portable equipment is so designed as to reduce power consumption as much as possible by keeping idle circuit blocks in stand-by mode. It would be possible to save power and memory if a non-volatile memory functioning as both high-speed work memory and high-capacity storage memory is realized. It would make the "instant-on function" feasible which permits equipment to start working instantly as soon as power is turned on.
Among non-volatile memory are flush memory, which relies on semiconductors, and FRAM (ferroelectric random access memory), which relies on ferroelectric substances.
Flush memory is limited in writing speed to the order of microseconds. FRAM is also limited in the number of rewriting cycles to 1012 to 1014, that is, it is too poor in endurance to replace SRAM (static random access memory) and DRAM (dynamic random access memory). Moreover, it presents difficulties in microprocessing of ferroelectric capacitors therein.
There is noteworthy non-volatile memory free of these disadvantages, which is magnetic memory called MRAM (Magnetic Random Access Memory). MRAM in the early stage is one which is based on spin valve. It utilizes the AMR (Anisotropic Magneto Resistive) effect, which was reported by J. M. Daughton in "Thin Solid Films", vol 216 (1992), pp. 162 to 168. Alternatively, it utilizes the GMR (Giant Magneto Resistance) effect, which was reported by D. D. Tang et al. in "IEDM Technical Digest" (1997), pp. 995 to 997. Unfortunately, they have the disadvantage that the memory cell has a low resistance of 10–100 Ω which leads to a large power consumption per bit for reading. This disadvantage makes it difficult to realize a large-capacity memory.
There is another type of MRAM which utilizes the TMR (Tunnel Magneto Resistance) effect. It has come to attract attention because of its remarkable increase in the rate of change in resistance from 1 to 2% at room temperature (as reported by R. Meservey et al. in "Physics Reports", vol. 238, pp. 214 to 217, 1994) to nearly 20% (as reported by T. Miyazaki et al. in "J. Magnetism & Magnetic Material", vol. 139, (L231), 1995).
MRAM is a semiconductor magnetic memory that relies on the magnetoresistance effect resulting from spin dependent conduction of nanomagnetic substances. It is a non-volatile memory that retains memory without external power supply.
MRAM has such a simple structure that it can be highly integrated with ease. It is capable of rewriting many times because it relies on the rotation of magnetic moment for recording. It is also expected to have a very high access speed. In fact, its ability to run at 100 MHz has been reported by R. Scheuerlein et al. in ISSCC Digest of Technical Papers, pp. 128 to 129, February 2000.
MRAM is broadly divided into two types. One is cross-point type and the other is 1T1J type or 2T2J type. MRAM of cross-point type is disclosed in U.S. Pat. No. 5,640,343. MRAM of 1T1J type consists of one selecting element and one TMR element. MRAM of 2T2J consists of two selecting elements and two TMR elements which are complementary to each other.
The MRAM consisting of one selecting element and one TMR element is shown in FIG. 33. The memory cell (or memory element) of MRAM is the TMR element 10, which consists mainly of a supporting substrate 9 and a memory layer 2 (in which the direction of magnetization rotates comparatively easily) and two magnetization pinned layers 4 and 6.
The magnetization pinned layer consists of a first magnetization pinned layer 4 and a second magnetization pinned layer 6. Between these two layers is interposed a conducting layer 5 through which they are coupled antiferromagnetically.
The memory layer 2 and the magnetization pinned layers 4 and 6 are formed from a ferromagnetic material such as nickel, iron, cobalt, and alloys thereof. The conducting layer is formed from any of ruthenium, copper, chromium, gold, and silver. The second magnetization pinned layer 6 is in contact with the antiferromagnetic material layer 7, so that it has a strong unidirectional magnetic anisotropy due to exchange interaction between these layers. The antiferromagnetic material layer 7 may be formed from a manganese alloy with iron, nickel, platinum, iridium, or rhodium, or a cobalt oxide or nickel oxide.
Between the memory layer 2 (which is a magnetic layer) and the first magnetization pinned layer 4 is interposed a tunnel barrier layer 3 formed from an insulating material such as an oxide or nitride of aluminum, magnesium, or silicon. It cuts off the magnetic coupling between the memory layer 2 and the magnetic pinned layer 4, and it also permits tunnel current to flow. The magnetic layer and the conductor film are formed mainly by sputtering. The tunnel barrier layer 3 may be formed by oxidizing or nitriding the metal film which has been formed by sputtering. The top coat layer 1 prevents mutual diffusion between the TMR element 10 and the wiring connected thereto. It also reduces contact resistance and protects the memory layer 2 from oxidation. It is usually formed from Cu, Ta, or TiN. The underlying electrode layer 8 serves for connection between the TMR element and a switching element connected thereto in series. This underlying layer 8 may function also as the antiferromagnetic layer 7.
The memory cell constructed as mentioned above reads information by detecting the change in tunnel current due to magnetoresistance effect (which will be described later). The magnetoresistance effect depends on the relative direction of magnetization of the memory layer and the magnetization pinned layer.
FIG. 34 is a partly simplified enlarged perspective view of an ordinary MRAM, with reading circuits omitted for brevity. This MRAM has nine memory cells and mutually intersecting bit lines 11 and writing word lines 12. Each TMR element 10 is placed at the point of intersection. Writing into the TMR element 10 is accomplished by applying current to the bit line 11 and the writing word line 12 simultaneously so that the two currents produce a combined magnetic field which changes the direction of magnetization of the magnetic layer 2 of the TMR element 10 parallel or antiparallel with respect to the magnetization pinned layer.
FIG. 35 is a schematic sectional view showing a memory cell which has a four-layered metal wiring. This memory cell is composed a reading n-type field effect transistor 19, a writing word line 12, a TMR element 10, and a bit line 11, which are arranged one over another. The field effect transistor 19 is composed of, for example, a p-type silicon semiconductor substrate 13 and a p-type well region 14 formed thereon, in which are formed a gate insulating film 15, a gate electrode 16, a source region 17, and a drain region 18. To the source region 17 is connected to a sense line through a source electrode 20. The field effect transistor 19 functions as a switching element for reading. The reading wiring 22 leading out between the word line 12 and the TMR element 10 is connected to the drain region 18 through the contact plugs 27a to 27c and the landing pads 28a to 28c in the insulating layers 29a to 29g of laminate structure placed between the reading wiring 22 and a drain electrode 23. Incidentally, the transistor 19 may be an n-type or p-type field effect transistor or any other switching element such as diode, bipolar transistor, and MESFET (metal semiconductor field effect transistor).
FIG. 36 is an equivalent circuit diagram of MRAM. It is assumed that this MRAM has six memory cells and mutually intersecting bit lines 11 and writing word lines 12. At each point of intersection are arranged a memory element 10 and a field effect transistor 19 connected thereto. The field effect transistor 19 is connected also to a sense line 21 so that it selects the element at the time of reading. The sense line 21 is connected to a sense amplifier 21b, so that stored information is detected. There are also shown a bidirectioal current drive circuit 24 for the writing word line and a current drive circuit 25 for the bit line.
FIG. 37 is an asteroid curve showing the writing condition for MRAM. It represents the reversal threshold value in the direction of magnetization of the memory layer by the magnetic field HEA applied in the direction of easy axis and the magnetic field HHA applied in the direction of hard axis. The combined magnetic field vector outside the asteroid curve brings about the reversal of magnetic field. By contrast, the combined magnetic field vector within the asteroid curve does not reverse the cell from one bistable state into the other. Any cell which is not at the intersection of the word line and the bit line receives the magnetic field generated individually by them, and it has its direction of magnetization reversed if the magnitude of the magnetic field is larger than the one-direction reversal magnetic field Hk. Consequently, only if the combined magnetic field is in the gray area, the selected cell permits selective writing.
As mentioned above, MRAM usually performs writing by means of two writing lines (the bit line and the word line), which reverse the magnetic spin in a specified cell owing to the characteristics of asteroid magnetization reversal. The combined magnetization in a single memory region is determined by the vector synthesis of the magnetic field HEA in the direction of easy axis and the magnetic field HHA in the direction of hard axis, both applied to the memory region. Current flowing through the bit line applies to the cell the magnetic field HEA in the direction of easy axis, and current flowing through the writing word line applies to the cell the magnetic field HHA in the direction of hard axis.
FIG. 38 illustrates the reading action by MRAM. Each TMR element 10 in MRAM is of layer structure as schematically shown. The magnetization pinned layer (mentioned above) is represented by a single layer 26, and other layers are omitted except for the memory layer 2 and the tunnel barrier layer 3.
As mentioned above, the writing of information is accomplished by applying current to the bit lines 11 and word lines 12 which are arranged in a matrix pattern. Current applied to these lines produces a combined magnetic field at the point of their intersection, thereby reversing the magnetic spin of the cell. The direction of magnetic spin represents either "1" or "0" as information. The reading of information is accomplished by using TMR effect resulting from magnetoresistance effect. TMR effect is a phenomenon that resistance varies depending on the direction of magnetic spin. High resistance (with the magnetic spin antiparallel) represents "1" and low resistance (with the magnetic spin parallel) represents "0". The reading of information is accomplished as follows. Reading current (tunnel current) is applied across the word line 12 and the bit line 11, and output in proportion to resistance is detected by the sense line 21 through the field effect transistor 19 for reading.
In the case of MRAM consisting of one selecting element and one TMR element as shown in FIG. 35, it is necessary to electrically insulate the TMR element 10 by an insulating layer from the writing word line 12 (referred to as word line for short hereinafter) which intersects with the bit line 11. This makes it necessary to provide connecting holes for connection between the reading wiring 22 and other wiring layers (lower or upper layers). Moreover, there should be a certain distance between the word line 12 and the landing pad 28c in the same layer. Therefore, the size of the memory cell of the MRAM cannot be equal to or smaller than 8F2.
In other words, even though the TMR element 10 shown in FIG. 39 has an aspect ratio of 1:1 (A:B), the size of the memory cell of the MRAM cannot be equal to or smaller than 8F2 (or 2F×4F) in the direction of the bit line. (The aspect ratio of 1:1 means that the TMR element 10 is approximately round and 3F is reduced to 2F in the direction in which it intersects with the bit line 11.) However, as mentioned later, it is necessary that the shape of the TMR element 10 should be elongated in the direction in which it intersects with the bit line 11. Therefore, it becomes an ellipse with an aspect ratio of 1:2, as shown in FIG. 39.
As mentioned above, there has been proposed means to solve problems with MRAM of such structure that the lower layer wiring exists in the same layer as the word line. (Refer to U.S. Pat. No. 5,940,319 (p. 5, column 5, lines 45 to 56, and FIG. 10).) However, the proposed means for solution is not necessarily satisfactory.
FIG. 39 is a schematic diagram showing a conventional MRAM (of 1T1J type) consisting of one selecting element and one TMR element. FIG. 39A is a partial plan view, and FIG. 39B is a sectional view taken along the line b—b in FIG. 39A. As shown in FIG. 39B, the word line 12 is electrically insulated from the TMR element 10 by an insulating layer (not shown). The TMR element 10, which is connected to the bit line 11, is connected to the landing pad 28, which is arranged on the same layer as the word line 12, through the reading wiring 22. This landing pad 28 is further connected to the lower layer wiring 30 through the plug 27.
FIG. 39 shows the size of the memory cell of the MRAM. As FIG. 39A shows in plan, there should be a distance of F/2 between the boundary C of adjacent memory cells and the landing pad 28, between the boundary C of adjacent memory cells and the word line 12, and between the landing pad 28 and the word line 12. Therefore, a length of 4F is necessary in the direction along the bit line 11. On the other hand, a width of 3F is necessary in the direction of intersection with the bit line 11. (The width of 3F is a sum of the distance F/2 between the boundary C of adjacent memory cells and the width (2F) of the bit line 11.) In actual, the TMR element 10 is formed elliptic, such that the aspect ratio A:B (where A is the minor axis of ellipse and B is the major axis of ellipse) is 1:2 from the standpoint of easy magnetization. Therefore, the length in the direction of intersection with the bit line 11 cannot be made smaller than 3F.
In brief, the memory layer of the TMR element practically has its direction of energetically stable magnetic moment determined by its shape anisotropy. Therefore, it is necessary that the aspect ratio of the TMR element pattern should be larger than 2 so that the reversal of magnetization takes place with a minimum of variation. The result is that the cell size cannot be made smaller than 12F2, which is calculated from (F+3F)×(2F+F), where F is the shorter side of TMR element and 2F is the longer side of TMR element. In this case, a space of F/2 should be provided between the side of the landing pad 28 and the word line and between the side of the landing pad 28 and the hole (not shown) for connection of the reading wiring 22 to the lower layer wiring 30. (The second space is equivalent to the width of the plug 27.) That is, the distance between the word line 12 and the connecting hole should be F.

Magnetic memory device and method for production thereof


A Trojan horse method and apparatus to permit email access to secure enterprise resources within an enterprise's firewall. An email message is used to permit a user to gain access to computer resources such as databases maintained within a secure enterprise's firewall. An email message generated from a palmtop computer or any other computer capable of sending and receiving email messages is used to pass through the firewall as a conventional email message would. The email message is received at a designated computer that recognizes reserved command words as a part of the email message, preferably as a part of the subject line thereof. Upon recognizing the reserved command word, the email message is parsed to determine key components of a command that can be executed on a desired enterprise computer resource. An appropriate command (e.g., an SQL query) is then created for execution on the enterprise computer resource (e.g., a database). A response or acknowledgement is then returned to the sender as an email message.

As the components required to build a computer system have reduced in size, new categories of computer systems have emerged. One of the new categories of computer systems is the "palmtop" computer system. A palmtop computer system is a computer that is small enough to be held in the hand of a user and can be "palm-sized." Most palmtop computer systems are used to implement various Personal Information Management (PIM) applications such as an address book, a daily organizer and electronic notepads, to name a few.
While these palm sized computers ("palmtop" computers) have dramatically reduced size when compared to a desktop or notebook computer, the user might often like to be able to perform many of the same types of functions performed using physically larger and more powerful computers. One way to accomplish this, as described in accordance with the present invention, is to use the palmtop computer to control the functions of a more powerful computer.
The term "Trojan horse" generally refers to a computer program that hides its true function within another computer program or data. Computer viruses often rely on such programming techniques to infiltrate a computer system and cause mischief. Many such computer programs have been developed to function as computer viruses, and many of them utilize email functions to hide the true purpose of the program.

This patent is subject to a terminal disclaimer.

System for using email message to transmit a command to remotely control a computer resource


A cab body has a panel section. The panel section includes a concave section that is recessed upward. A floor frame includes a convex section and supports the cab body. The convex section has a shape that protrudes facing upward and is arranged to protrude from the concave section. A seal member seals a gap between the concave section and the convex section. The seal member has a first contact surface, a second contact surface, and an inclined surface. The first contact surface contacts the convex section. The second contact surface contacts the panel section. The inclined surface is inclined with regard to the first contact surface and the second contact surface. A bracket has an attachment section and a pressing surface. The attachment section is attached to the panel section. The pressing surface presses the inclined surface.

1. Field of the Invention
The present invention relates to a cab and a work vehicle.
2. Background Information
As shown in, for example, Japanese Unexamined Patent Application Publication No. 2008-279852, a work vehicle is provided with a cab where a seat where a driver sits, an operating member, and the like are arranged. The cab has a cab body and a floor frame. The cab body is arranged on the floor frame. The floor frame supports the cab body.


Yaw brakes for wind turbines are proposed, the wind turbines having a tower, a nacelle and a yaw system for rotating the nacelle with respect to the tower. The yaw brakes comprise a locking part, having a toothed profile at a side facing a toothed profile of an annular gear of the yaw system. The locking part of the yaw brakes is movable in a radial direction relative to the annular gear, between a brake position and a non-brake position. Brake discs and callipers may be eliminated.

Modern wind turbines are commonly used to supply electricity into the electrical grid. Wind turbines of this kind generally comprise a tower and a rotor arranged on the tower. The rotor, which typically comprises a hub and a plurality of blades, is set into rotation under the influence of the wind on the blades. Said rotation generates a torque that is normally transmitted through a rotor shaft, either directly or through the use of a gearbox, to a generator. This way, the generator produces electricity which is supplied into the electrical grid.
Most wind turbines comprise a yaw system used for orienting the rotor of the wind turbine in the prevailing wind direction. Normally, when the rotor is aligned with the wind direction, the yaw system maintains the position by means of brakes (e.g. hydraulic brake callipers and/or electro-brakes of the yaw motors). When the rotor is misaligned from the wind direction the yaw system rotates the nacelle to reach an appropriate alignment with the wind.
The yaw system normally performs this rotation of the nacelle by means of a yaw drive that includes a plurality of (electric or hydraulic) motors with suitable gearboxes for driving gears (pinions) that mesh with an annular gear attached to the nacelle or to the wind turbine tower. The nacelle can thus be rotated around the tower's longitudinal axis in or out of the wind direction. The rotatable connection between the wind turbine tower and the nacelle is called a yaw bearing. The yaw bearing can be of the roller or gliding type and is generally able to handle very high loads.
In order to stabilize the yaw bearing against rotation a means for braking is often necessary.
Such means for braking are known in the prior art. FIG. 1 shows a typical yaw brake system. The yaw brake of FIG. 1 comprises a circular slew bearing 150 (i.e. a yaw bearing) for rotatably mounting the nacelle on the wind turbine tower; an outer ring 130 of the slew bearing is connected with a main frame 160 of the nacelle, and an inner ring 140 is connected to the tower. A hydraulically actuated disk brake may be used to slow rotation of the outer ring. The disk brake typically requires a flat circular brake disk, such as brake disk 120, and a plurality of brake callipers, such as brake callipers 110, with hydraulic pistons and brake pads. The brake disc 120 may be connected to the inner ring 140 of the slew bearing. Brake callipers 110, attached to main frame 160 may engage with brake disc 120 to brake the inner ring 130.
A plurality of yaw drives (not shown) may be provided. The yaw drives comprise a motor, a gearbox (sometimes referred to as a reducer or as reduction gearing), and a pinion which is arranged to engage with annular gear 170. The hydraulic yaw brakes are able to fix the nacelle in position thus relieving the motors from that task. However, the electro-brakes of the yaw drives typically serve to further brake the yaw system.
Considering the azimuth wind direction and the rotor direction, a wind turbine generally operates as follows:                When the wind turbine rotor is aligned with the wind direction it maintains the position usually by means of the yaw brake system involving hydraulic brake callipers and possibly the electro-brakes of the yaw motors.        When the wind turbine rotor is not aligned with the wind direction, the yaw system rotates the nacelle to reach an appropriate alignment with the wind by means of the yaw drives (yaw motor with gearbox and pinion).
In the majority of conventional wind turbines, the hydraulic brake callipers are dimensioned to resist approximately 20% of the maximum aerodynamic load torque. The rest is provided by the motors' electro-brakes.
The main technical problem with this type of solution is that the brake callipers' linings don't have a constant friction coefficient over time. The friction coefficient may be affected e.g. due to wear, temperature, brake disc conditions and undesired contamination (oil or grease). If the friction coefficient increases it may cause a premature failure to the brake callipers themselves. On the other hand, if the friction coefficient decreases it may encumber the gearbox motors and in the worst case it may wear down the annular gear.
Furthermore, brake discs require frequent maintenance which increases the operational cost of the wind turbine. Additionally, the yaw brake may further require electro-brakes in the gearboxes to resist the over torques. This may cause unpredictable damages in the gearboxes. Finally, contamination of the linings may not be avoided completely.


A memory control apparatus generates a plurality of commands whose unit of transfer is smaller than the unit of data transfer of a memory access request, and when the memory access request are transmitted from a plurality of request sources, issues the plurality of commands to a memory in alternate order for each request are executed by time division and concurrently.

1. Field of the Invention
The present invention relates to a memory control apparatus and method.
2. Description of the Related Art
As the semiconductor and microprocessor technologies progress, the field of application of embedded systems is steadily expanding. Most popular electronic and electric devices use embedded systems. Additionally, along with the recent increase in integration of LSIs, a so-called system LSI is becoming common which integrates the controller function of an embedded device in one LSI.
FIG. 7 is a view showing a configuration that implements an embedded system of OA equipments by using a system LSI disclosed in, e.g., U.S. Pat. No. 6,480,916.
Referring to FIG. 7, a system LSI 100, memory 101, and various kinds of IO interfaces are mounted on an embedded system board 110. The system LSI 100 is a single-chip scanning printing engine. More specifically, the system LSI 100 incorporates a processor core, processor peripheral controller, memory controller, scanner controller, printer controller, PCI interface, and USB device interface.
The IO interfaces provided on the embedded system board 110 are a scanner IF 131, FAX IF 132, USB IF 134, and printer IF 133. These IO interfaces are connected to a scanner 121, FAX 122, PC 124, and printer engine 123 to form the entire system. The system LSI 100 also has a PCI bus IF 136. With the PCI bus IF 136, an HDD 125 connected to an IDE bus 135 can be used through a PCI-IDE bridge 102.
FIG. 2 is a block diagram for explaining the system LSI 100 in more detail.
A processor 201 can incorporate a cache memory of 32 Kbytes (16 Kbytes for each of instruction and data), FPU (Floating Point Unit), MMU (Memory Management Unit), and user-definable coprocessor.
Since a PCI bus interface 232 is present, the system LSI 100 can be used together with a computer system having a PCI bus slot. In addition to the PCI satellite configuration, the PCI host bus bridge configuration can issue a PCI bus configuration. Hence, when combined with an inexpensive PCI peripheral device, the system LSI 100 can be used as the main engine of a multifunction peripheral. The system LSI 100 can also be combined with a rendering engine or compression/decompression engine having a PCI bus interface.
The chip incorporates two independent buses, i.e., an IO bus (B bus) 221 to connect a general-purpose IO core and a graphics bus (G bus) 220 optimized for image data transfer. A memory 204 (101), the processor 201, and these buses are connected through a system bus bridge 203 serving as a cross bus switch. With this configuration, high-speed parallel data transfer necessary for simultaneous operation in a multifunction system is implemented.
The system LSI 100 also incorporates a memory controller 202 that supports a synchronous DRAM (SDRAM) with high cost performance for access to a continuous data sequence represented by image data.
The system LSI 100 also incorporates a scanner controller 205, printer controller 206, PCI controller 207, USB controller 208, UART 209, MISC module 210 including a timer/GPIO function, and LAN controller 211. Reference numerals 230 to 233 denote IO interfaces of the controllers 205 to 208. These IO interfaces are identical to the interfaces 131, 133, 134, and 136 with the same names in FIG. 7.
FIG. 3 is a timing chart for explaining the sequence of a typical composite operation. In this example, a so-called copy operation is executed in which the scanner 121 scans a document, and the printer engine 123 prints the scanned document. Image data obtained by scanning a document is transmitted from the scanner 121 to the scanner controller 205 incorporated in the system LSI 100 through the scanner interface 131 (230) (301). The scanner controller 205 stores the received image data in the memory 204 (101) by DMA (302). The printer controller 206 reads out the data from the memory 204 by DMA (303) and transmits the data to the printer engine 123 through the printer interface 231 (133) (304). The printer engine 123 prints the data.
At this time, PDL data is also transmitted from the PC 124 through the USB interface 134 (233) (311). The PDL data is received by the USB device controller 208 and temporarily stored in the memory 204 by DMA (312). The PDL data is interpreted by the processor 201 in the system LSI 100. The bitmapped image is stored in the memory 204 again (313). Finally, the image data is read out from the memory 204 by the printer controller 206 (314), transmitted to the printer engine 123 through the printer interface 231 (133) (315), and printed.
FIG. 4 shows a physical address space handled by the processor 201 at this time. Actually, the processor 201 is compatible with MIPS R4000. Software on the processor 201 runs by using a virtual address. The processor 201 always operates in a kernel mode. Physical addresses 0x0000—0000 to 0x1fff_ffff correspond to virtual addresses 0x8000—0000 to 0x9fff_ffff (kseg0: cached) and 0xa000—0000 to 0xbfff_ffff (kseg1: uncached).
In this prior art, the memory 204 has a capacity of 32 MB and incorporates a 256-Mbit SDRAM with a 16-bit×4-bank×4M-word configuration. Hence, the physical address space usable as a RAM corresponds to addresses 0x0000—0000 to 0x01ff_ffff.
When the composite operation shown in FIG. 3 is executed, software running on the processor 201 manages the buffer area on the memory 204 used by hardware. Like a normal case wherein a memory area is dynamically ensured by software, an area with a necessary size is ensured in the Heap area by using a memory allocate function (a system function provided by the OS: e.g., malloc).
In the composite operation shown in FIG. 3, the buffer area write-accessed by the scanner controller 205 by DMA is the same as the buffer area read-accessed by the printer controller 206 by DMA. If there is only one buffer area, the address written by the scanner controller 205 is read out by the printer controller 206 later. However, the speed of read from a scanner and the speed of printing by a printer are normally different. Hence, if there is no mechanism for synchronizing the scanner controller 205 with the printer controller 206, the read address may go ahead of the write address.
To avoid this, the buffer is generally doubled. More specifically, while the scanner controller 205 write-accesses one buffer area by DMA, the printer controller 206 read-accesses the other buffer area by DMA. When DMA transfer of both controllers is ended, the buffers to be used by them are replaced, and next DMA is started.
For example, when 1-MB data is continuously transmitted from the scanner 121 to the scanner controller 205, the argument of the memory allocate function is set to 1 MB and called. The returned address is (converted from a virtual address to a physical address) set to the DMA start address of the scanner controller 205. In this case, addresses 0x0080—0000 to 0x008f_ffff are ensured, and the first address 0x0080—0000 is set to the DMA start address. When data arrives, the scanner controller 205 continuously stores the data from the start address by DMA. When DMA is ended, the address 0x0080—0000 is set to the DMA start address of the printer controller 206. When software instructs to start DMA, the data is sequentially read out from the set start address in accordance with the signal of the printer interface 231 and transferred to the printer engine 123 through the printer interface 231.
At the same time, the next DMA setting is done for the scanner controller 205. The argument of the memory allocate function is set to 1 MB and called again. When addresses 0x0090—0000 to 0x009f_ffff are ensured, the first address 0x0090—0000 is set to the DMA start address. When data from the scanner interface 230 arrives, the scanner controller 205 continuously stores the data from the start address by DMA.
In this way, the DMA operation is repeatedly executed while using the two areas corresponding to the addresses 0x0080—0000 to 0x008f_ffff and 0x0090—0000 to 0x009f_ffff in alternate order between the scanner controller 205 and the printer controller 206.
For the USB controller 208, addresses 0x0b0—0000 to 0x00bf_ffff are ensured, and the first address 0x00b0—0000 is set to the DMA start address. When data is transmitted from the PC (USB host) 124, the USB controller 208 continuously stores the data from the start address by DMA. When all transfer is ended, the software is notified of it by an interrupt. Next, the software interprets PDL data and generates print image data. The finally generated print image data is stored in a newly ensured buffer area. To do this, the memory allocate function is called again to ensure a 3-MB area corresponding to addresses 0x00c0—0000 to 0x00ef_ffff. The address 0x00c0—0000 is set to the DMA start address, and the printer controller 206 is activated. DIMA transfer of the printer controller 206 at this time is executed exclusively of DMA transfer of the printer controller 206 in the above-described scanner printer operation.
As described above, when the scanner and printer simultaneously access the HDD, a plurality of hardware devices simultaneously DMA-access the memory in the system LSI.
When a plurality of masters issue access requests for only one memory source in the system LSI, the access requests always conflict at a certain probability. For, e.g., the printer controller that must continuously supply data to the printer engine, an increase in latency in case of access confliction must be taken into consideration. Hence, the FIFO capacity to buffer the data rate must be large to deal with the worst delay value. This increases the circuit scale and chip cost. In addition, various adverse effects such as an increase in heat and a decrease in reliability occur.
For example, assume that 32-byte data is transferred in one cycle of DMA transfer. If the capacity of the FIFO memory is only 32 bytes, the next DMA transfer cycle can start after the FIFO becomes vacant. This configuration cannot be used when data must continuously be supplied to the printer engine once the printer operation starts, like the above-described printer controller. The FIFO is always required to have a capacity to store data of a plurality of DMA transfer cycles. The FIFO needs to have a capacity for at least two DMA transfer cycles, i.e., a capacity of 64 bytes.
Assume the printer interface has a FIFO with a capacity of 64 bytes. When the contents of the FIFO decrease to 32 bytes or less, the printer interface can issue the next DMA transfer request to the memory controller. When the next data is read out from the memory and written in the FIFO by DMA transfer before the FIFO becomes vacant, data can continuously be supplied to the printer engine.
If there is no master issuing a memory access request simultaneously as the printer interface issues a DMA transfer request to the memory controller, the data can be read out and stored in the FIFO before the FIFO becomes vacant. However, if another master has issued an access request to the memory controller immediately before, the printer controller cannot read out the data from the memory and store it in the FIFO until the memory access request is processed.
Under some circumstances, data read by the printer controller may delay along with the increase in delay time, and the FIFO may be vacant meanwhile.
To avoid this, the printer controller has a FIFO capacity of at least, e.g., 128 bytes to prevent any problem even in the worst case. If memory conflict rarely occurs, a capacity of 64 bytes or 96 bytes at best suffices in most cases. However, to deal with a rare case, the circuit scale is increasing.


A bonded wafer is produced by comprising a step of implanting oxygen ions from a surface of a wafer for active layer to form an oxygen ion implanted layer at a given position inside the wafer for active layer; a step of bonding the wafer of active layer to a wafer for support substrate directly or through an insulating film; a step of subjecting the resulting bonded wafer to a heat treatment for increasing a bonding strength; a step of removing a portion of the wafer for active layer in the bonded wafer to a given position not exposing the oxygen ion implanted layer by a given method; a step of exposing the entire surface of the oxygen ion implanted layer; and a step of removing the exposed oxygen ion implanted layer to obtain an active layer of a given thickness, wherein the step of exposing the entire surface of the oxygen ion implanted layer is carried out by a dry etching under given conditions.

1. Field of the Invention
This invention relates to a method for producing a bonded wafer, and more particularly to a method for producing a bonded wafer in which an oxygen ion implanted layer is provided on a wafer for active layer as an etching stop layer.
2. Description of the Related Art
The bonded wafer normally means a bonded SOI wafer. As a production method thereof are mentioned, for instance, a method wherein an oxidized wafer for active layer is bonded to a wafer for support substrate and thereafter a surface of the wafer for active layer is thinned to a given thickness by grinding and polishing as disclosed in a literature, "Science of Silicon", edited by USC Semiconductor Substrate Technology Workshop, published by REALIZE INC. on Jun. 28, 1996, pp 459-462, and an ion implantation-isolation method or a so-called smart cut (Smart Cut (registered trademark)) method comprising a step of forming an ion implanted layer by implanting, ions of a light element such as hydrogen, helium or the like into a wafer for active layer at a given depth position, a step of bonding the wafer for active layer to a wafer for support substrate through an insulating film, a step of exfoliating at the ion implanted layer and a step of thinning a portion of the active layer exposed at a state bonded to the wafer for support substrate by exfoliation to form an active layer of a given thickness as disclosed in WO 2005/074033.
In the above silicon wafer, it is assumed that it is important to make the thickness of the active layer thin and to enhance the uniformity thereof. To this end, the inventors have also disclosed the production technique of a bonded wafer satisfying the requirements for the thinning and the uniformity of the thickness of the active layer in WO 2005/074033.
In the technique disclosed in WO 2005/074033, however, when oxygen ions introduced in the oxygen ion implantation (oxygen ion implanted layer) do not form a complete oxide film and is existent at a discontinuous state, an etching solution-penetrates from a portion of the wafer not forming the oxide film to remove the active layer at a subsequent step (at a time of exposing the oxygen ion implanted layer), and hence the thickness uniformity of the active layer may be deteriorated and defects may be caused. Although the deterioration of the thickness uniformity and the occurrence of defects may be reduced at a next oxidation treatment step and at a step of removing an oxide film, it is particularly feared that the defects are further increased at a step of heat treatment.


A system for encoding control data onto a clock signal includes at least one clock cycle in the clock signal; a first transition in the at least one clock cycle, the first transition is from a first voltage level to a second voltage level, the first transition is in a first location in the at least one clock cycle; a second transition in the at least one clock cycle, the second transition is from the second voltage level to the first voltage level, the second transition has a variable location in the clock cycle; and an encoder circuit for positioning the second transition in the variable location in response to the control data.

Without limiting the scope of the invention, its background is described in connection with a color display panel having an image size of 768.times.1024 pixels at a 60 Hz frame rate, as an example. The 768.times.1024 pixels are Just the active, viewable area. In addition, there is a blanked area around the viewable area, and horizontal and vertical sync pulses. The blanked area includes 180 additional pixels per line and 32 additional lines for an effective image size of 800.times.1204 pixels. Also, there are an additional 136 pixels per line during horizontal sync and 6 additional lines during vertical sync. This provides an effective image size of 806.times.1340. An 806.times.1340 image at a 60 Hz refresh rate requires a pixel rate of 64,802,400 pixels per second. A color image with 8 bits each for red, green, and blue, plus three bits for three control lines requires 27 bits/pixel to be transferred across a notebook computer hinge at about 65 MHz for an image of 768.times.1024.

System for encoding an image control signal onto a pixel clock signal


A water inlet system for an aquarium is disclosed along with a siphon stopper and a method of attaching the system to an aquarium. The water inlet system is designed to pass through an aperture formed in a sidewall of the aquarium. A tubular member is connected to a pump which can supply water from a reservoir to the aquarium. The tubular member passes through the aperture and into the aquarium. An adapter having a spout is connected to one end of the tubular member. In addition, a siphon stopper is secured to the adapter, above the spout, and serves to break any back siphon that may develop should the water line in the aquarium drop below a predetermined point. The method includes the steps of attaching the water inlet system to the aquarium.

Aquariums are water filled enclosures in which living fish and/or other aquatic animals and plants are kept. The water in an aquarium needs to be filtered on a regular basis. The clean, filtered water is then pumped back into the aquarium via a water inlet system. The pump operates on electricity and is subject to power outages which can occur fairly frequently. The pump is also a mechanical piece of equipment which is prone to failure at some point. Either of these events would cause the pump to stop working and this would disrupt the return water flowing back into the aquarium. Sometimes, a back siphon occurs when the pump stops working. A back siphon allows the water in the aquarium to flow backward into the reservoir tank of the filtering system. This extra water can quickly overflow the reservoir tank and create a flood. Since many aquariums are set up in a home or in the lobby area of an office, the aquariums are normally residing in a carpeted room with fine furniture located nearby. The filtering system is usually situated in a cabinet below the aquarium. Any water that overflows the reservoir tank will flow downward onto the carpeting. This water will wet the carpeting and possibly leave a water stain or worst, ruin the carpeting. Furthermore, if the overflowed water becomes deep enough, it could possibly soak and/or stained adjacent furniture.
To prevent a flood from occurring, most aquariums employ a water inlet system which includes a one-way check valve positioned in the incoming water line. However, many one-way check valves utilize a gasket or seal, a spring, and a ball that mates with a concave surface. Over time, the gasket or seal can become brittle, hard or worn and will not function properly. In addition, rust, corrosion, or oxidation can cause the spring to malfunction or cause the ball to become pitted such that it does not form a tight seal with the concave surface. Also, the presence of a foreign particle on the concave surface could prevent the one-way check valve from working properly. Therefore, there is a need for a water inlet system that does not rely on a one-way check valve to prevent a back siphon from occurring should the pump stop working.
Now, a water inlet system for an aquarium, a siphon stopper and a method of attaching the system to an aquarium have been invented which does not utilize a one-way check valve.

Water inlet system for an aquarium, a siphon stopper and a method of attaching the system to an aquarium


A semiconductor structure that provides both N-type and P-type doping from a single dopant source is provided. A first doping region (13) comprising a first material composition includes holes and electrons in a doping energy level (E.sub.D)- A first undoped spacer region (12) comprising the first material composition covers the doping region (13). An undoped channel (11,14) comprising a second material composition covers the first spacer region (12) and a second undoped spacer region (12) comprising the first material composition covers the undoped channel (11,14). The first material composition has a wider bandgap than the second material composition and the doping energy level (E.sub.D) is selected to provide electrons to the undoped channel (11,14) when the second material composition has a conduction band minimum less than the doping energy level (E.sub.D) and to provide holes to the first undoped channel (11,14) when the second material composition has a valence band maximum greater than the doping energy level (E.sub.D).

The present invention relates, in general, to semiconductor devices and, more particularly, to quantum well semiconductor structures having a single source for both n-type and p-type doping.
Traditional semiconductor devices are formed on a semiconductor substrate. Intrinsic semiconductor material is very high resistivity or semi-insulating. Conventionally, the resistivity of semiconductor material is lowered by doping portions of the semiconductor material with atoms that provide excess electrons and holes. For example boron is a P-type dopant in silicon, while phosphorous and arsenic are N-type dopants. This type of doping is called extrinsic doping.
One problem with extrinsic doping is that the dopant atoms increase scattering of charge carriers moving in the semiconductor material. Increased scattering is reflected in lower mobility in the semiconductor material. Moreover, lower mobility results in devices with slower switching and higher power consumption. This problem is addressed to some degree by modulation doping in heterostructure semiconductor devices. Modulation doping physically separates the dopant atoms from the excess charge carriers that they provide using quantum wells and barriers.
Another problem with conventional extrinsic as well as modulation doping is that one kind of atom is required for N-type doping and another kind of atom is required for P-type doping. To manufacture bipolar devices, which are devices having both N-type and P-type regions, both kinds of doping atoms must be supplied. This increases capital requirements for manufacturers and complicates processing. Because many of the dopant atoms used in semiconductor processing are toxic, manufacturing safety is directly affected by the number of chemicals and dopants required to produce a device.
What is needed is a semiconductor structure that provides both N-type and P-type doping from a single dopant source and that is compatible with modulation doping techniques.

Bipolar doped semiconductor structure and method for making


A printed wiring board has an aluminum backing, a dielectric layer overlying the aluminum backing, and a copper layer overlying the dielectric layer. Holes are drilled through the copper and the dielectric layers, and either partially or fully through the aluminum backing, and plated to provide a conductive path between the copper layer and the aluminum backing. Tin-lead traces are applied to the upper surface of the copper layer and the copper layer is etched to define conductive paths. The copper exposed and aluminum exposed surfaces are protected so as to permit processing of the printed wiring board in otherwise-incompatible etchants and other solutions.

This invention relates to printed wiring boards (PWBs) with a copper/dielectric/aluminum structure, and, more particularly, to the processing of such PWBs to produce plated holes therein.
Copper-clad laminates with an aluminum backing are patterned with electrical circuitry and used in a number of applications such as high-frequency microwave circuits. Such laminates, termed printed wiring boards or PWBs, include an aluminum backing, a layer of a dielectric such as a resin overlying the aluminum backing, and a patterned copper layer overlying the dielectric layer. It is often necessary to provide holes through the copper layer and the dielectric layer, and into the aluminum backing. The bores of the holes are plated with an electrical conductor so that they provide electrical continuity between the copper layer and the aluminum backing. The holes may extend through the aluminum backing or may be blind holes terminating within the aluminum backing.
The uniform plating of the bores with sufficient thickness, and in an economical manner, is difficult, for several reasons. The holes are long and narrow, making difficult the uniform plating of the bore with minimal defects. Bubbles may become trapped within the bores and physically block the subsequent plating. Copper and aluminum are chemically dissimilar. Chemicals used to process copper, such as etchants, often attack aluminum, and vice versa.
A number of techniques have been used to accomplish the plating of the bores in conventional low-frequency (less than 500 MHZ) PWBs. Since these low-frequency PWBs have copper layers on both the top and bottom sides, the plating of the bores is relatively simple. In industry, electroless copper plating or direct metallization is used to provide electrical continuity between the top and bottom sides. When there is an aluminum backing, however, the plating of the bores is difficult without proper processing sequences and techniques. In one approach, the conductive copper layer is applied by a physical technique such as physical vapor deposition. This approach provides an adherent copper coating on the readily exposed surface of the bore, but uniform deposition of copper inside deep holes is difficult, with the result that the electrical path between the copper and aluminum may be unreliable.
There is a need for an improved approach to the production of aluminum-backed PWBs having blind or through holes therein. The present invention fulfills this need, and further provides related advantages.

Fabrication of aluminum-backed printed wiring boards with plated holes therein


An eyepiece lens has a single lens element having a positive optical power, and the single lens element has a refractive power of an aspherical surface and a diffractive power. The eyepiece lens satisfies the following condition: EQU -0.0006<{1 /(fl.multidot..nu.)}+.phi.DOE/.nu.DOE<0.0002. where fl represents the focal length resulting from both refractive effect and diffractive effect of the eyepiece lens, .nu. represents the Abbe number of the eyepiece lens, .phi.DOE represents the power resulting from the diffractive effect of the eyepiece lens, and .nu.DOE represents the Abbe-number-equivalent value resulting from the diffractive effect of the eyepiece lens.

1. Field of the Invention
The present invention relates to an eyepiece lens and a viewfinder optical system.
2. Description of the Prior Art
It is known to use a diffractive optical surface in an optical system. For example, U.S. Pat. No. 5,148,314 proposes an optical system consisting of a single lens having a diffractive optical surface, and so does a treatise by G. J. Swanson and W. B. Veldkamp, titled "Infrared Applications of Diffractive Optical Elements" SPIE proceedings, vol. 885, paper 22 (1988). On the other hand, U.S. Pat. Nos. 5,044,706 and No. 5,446,588 propose viewfinder optical systems that consist of an objective optical system and an eyepiece optical system and that correct chromatic aberration by the use of a diffractive optical surface. U.S. Pat. No. 5,044,706 proposes a viewfinder optical system in which the objective optical system has a diffractive optical surface, and U.S. Pat. No. 5,446,588 proposes a viewfinder optical system in which the eyepiece optical system has a diffractive optical surface.
In an example described in the above-mentioned treatise by Swanson et al., a single lens having a diffractive optical surface is used to correct chromatic aberration. In this example, the lens acts as an aperture diaphragm, and accordingly the position of the aperture diaphragm coincides with the position of the lens. In a practical viewfinder optical system, however, if the eyepiece lens is composed of a single lens, the pupil (which corresponds to the aperture diaphragm) is located away from the lens, and therefore chromatic aberration (in particular, lateral chromatic aberration) appears with a different pattern than in the example of Swanson et al.
On the other hand, in the viewfinder optical systems proposed in the above-mentioned U.S. Pat. No. 5,044,706 and U.S. Pat. No. 5,446,588, the eyepiece lens is composed of a plurality of lenses to achieve proper correction of aberration. By contrast, when the eyepiece lens of a viewfinder optical system is composed of a single lens, aberration needs to be corrected with only two lens surfaces, and therefore it is necessary, not only to use a diffractive optical surface to achieve proper correction of chromatic aberration, but also to elaborately design the power of the diffractive optical surface and the shapes of the lens surfaces to achieve proper correction of spherical aberration, coma aberration, astigmatism, curvature of field, and distortion.
From the viewpoint of the efficiency of diffraction of a diffractive optical surface, as well as the flare caused by rays resulting from diffraction of orders other than designed, it is desirable to use as few diffractive optical surfaces as possible. In the optical system proposed in the above-mentioned U.S. Pat. No. 5,148,314, the power of a diffractive optical surface and its distance from the aperture diaphragm are optimized (i.e. exactly defined) so that chromatic aberration (i.e. longitudinal chromatic aberration and lateral chromatic aberration) will be minimized with as few diffractive optical surfaces as possible. However, in an eyepiece lens, the pupil acts as an aperture diaphragm, and therefore the position of the aperture diaphragm (i.e. the position of the pupil) is not fixed. Accordingly, this optical system, when used as an eyepiece lens, does not achieve proper correction of chromatic aberration, as long as it is composed of a single lens.
In either of the optical systems proposed by the above-mentioned U.S. Pat. No. 5,044,706 and U. S. Pat. No. 5,446,588, the lens having the diffractive optical surface is given a strong power relative to the power of the entire viewfinder optical system, that is, the diffractive optical surface is used simply to correct chromatic aberration. The inventors of the present invention, however, noticed that the power of a lens having a diffractive optical surface can as well be used to solve the following problems associated with a viewfinder optical system as described above.
In general, when a viewfinder optical system is incorporated into a camera, the viewfinder optical system is, on its front and rear sides, additionally fitted with outer covering members such as protection glasses that are used as eyepiece-side and objective-side windows of the viewfinder of the camera. If parts of the viewfinder optical system can be directly fitted to the outer covering of the camera, there will be no need to use separate outer covering members such as the above-noted protection glasses, and, as a result, it is possible to reduce the cost of the camera. However, fitting optical members such as a viewfinder optical system directly to structural members such as outer covering members is not practical for the following reasons.
Optical members are far more sensitive to fitting errors than structural members, that is, optical members require far higher fitting accuracy than structural members. Accordingly, fitting an optical member directly to an outer covering member or any other elastic member of the camera results in poorer optical performance than designed.
Moreover, as the power of an optical member becomes stronger, it becomes more sensitive to fitting errors, that is, it requires higher fitting accuracy. In the optical systems of the patents cited previously, the lens having the diffractive optical surface is given a strong power, and accordingly it requires considerably high fitting accuracy. This means that, even though the diffractive optical surface serves to correct chromatic aberration properly, its use is meaningless as long as the lens is fitted to a more roughly fitted member of the due to a considerable degradation of optical performance.
If it were possible to fit a lens having a diffractive optical surface to a more roughly fitted member without degrading optical performance, then it would be possible to achieve not only proper correction of chromatic aberration, but also reduction of the number of the components, and thus the cost, of the camera. The possible advantages of this constitution are such that the inventors of the present invention were motivated to study it more closely until led to the conclusion that it is in fact possible to fit a lens having a diffractive optical surface to a more roughly fitted member if the power of that lens is made weaker than in conventional viewfinder optical systems but not weaker than is necessary to achieve sufficient correction of chromatic aberration.
A Kepler-type real-image viewfinder optical system in which the image of an object is formed by an objective lens and is then magnified by an eyepiece lens for observation is provided with an erecting optical system such as an inverting prism to reflect the vertical and horizontal directions of the object correctly in the observed image. The use of the erecting optical system, however, inevitably makes the viewfinder optical system as a whole larger.
It is known that a lens system can be made compact by providing a curved surface on a prism. For example, U.S. Pat. No. 5,206,675 proposes an example in which a Porro prism is provided with a curved surface to omit a separate eyepiece lens.
However, providing a prism with a curved surface causes large chromatic aberration.


A battery monitoring routine is executed at a short period such as one minute as an initial value when a key switch is turned on to drive an electric vehicle (so that the battery is discharged). On the other hand, when the key switch is turned off to stop or park the electric vehicle so that the battery is released open from discharge, the battery monitoring routine is executed at a short period such as one minute to measure the battery data finely within a specified time such as 30 minutes, but at a long period such as one hour to measure the battery data coarsely after the specified time such as 30 minutes to save monitoring power. The battery deterioration can be monitored by measuring the restoration status of the battery after released open from discharge, for recharging or replacement of the battery.

The present invention relates to a battery management system for an electric vehicle, and more specifically to battery management system for monitoring the status such as a remaining battery capacity of a high voltage battery mounted on the electric vehicle by detecting various battery conditions, for example, terminal voltage, temperature, etc.
Recently, an electric vehicle has been developed more and more. In the electric vehicle, it is important to always detect the status of the battery mounted thereon, so that various battery management system have been so far proposed.
For instance, Japanese patent application laid-open (Kokai) No. 5-227603 (1993) discloses such a battery management system that: various drive data related to an electric vehicle (e.g., vehicle starting and traveling conditions) detected by various vehicle sensors and various data related to battery charged status such as charge time, charged capacity or the number of charged times, which is detected by various battery sensors are recorded in an IC (integrated circuit) card; and that the remaining battery capacity is read and displayed for the driver where necessary, so that the car battery can be charged timely and effectively.
Further, Japanese patent application laid-open (Kokai) No. 6-54402 (1994) discloses a battery management system such that: the remaining capacity of the battery can be obtained accurately, with the use of a bi-directional power capacity meter for detecting a power capacity of the battery mounted on an electric vehicle; reading means for reading battery-related data such as specific battery data, history data, from a recording medium as battery power correction data for correcting the battery power capacity; and calculating means for calculating a corrected battery power capacity on the basis of the power capacity detected by the bi-directional power capacity meter and the correction data obtained by the reading means.
In the above-mentioned prior art battery management system, however, it is necessary to always obtain the correction value of the remaining capacity of the vehicle drive battery, by detecting the battery terminal voltage, the battery temperature and the time elapsed after released open from discharge, not only during traveling but also when the key switch is kept turned off (i.e., when, the electric vehicle is kept stopped or parked at night or for many hours in daytime).
In this method, however, since the current consumed for a battery management system is relatively large, when the battery management system is kept activated, even after the key switch has been turned off such as during a parking, there exists a possibility that the car battery is used up.
Here, the reason why the battery must be monitored even after the battery is released open from discharge, will be explained hereinbelow with reference to FIGS. 1(a) to 1(e)
As shown in FIG. 1(a), when the electric vehicle is stopped and further the key switch is turned off at t.sub.0 ; that is, the terminal battery voltage is restored relatively sharply up to a peak value after about 30 minutes at t.sub.1 when the battery is released open. After that, the terminal voltage begins to decrease gradually. Here, the time between t.sub.0 and t.sub.1 is referred to as a specific time T.sub.p. FIG. 1(b) shows this restoration status in an enlarged scale, which indicates that it is possible to know the deterioration status of the drive battery by measuring the restoration rate (.DELTA.V/.DELTA.t) of the terminal voltage with the lapse of time. In other words, a criterion for exchange the battery with new one can be known.
However, this restoration rate of the battery obtained immediately after the battery has been released open differs according to the past discharge status of the battery. FIG. 1(c) shows an example where a small power is discharged for a long time; FIG. 1(d) shows another example where a large power is discharged for a short time; and FIG. 1(e) shows the other example where a small power is discharged for a medium time.
Therefore, when the battery is always monitored so often, even after the key switch has been turned off in the same way as with the case where the key switch is turned on, there exists a problem in that the current consumption required for the battery management system increases, with the result that the battery is used up for battery management or monitoring.

Battery management system for electric vehicle