This invention provides a power unit for an automobile including a motor 6 for starting an engine by transmitting a power thereto and generating a power by receiving a power from the engine during rotation thereof, a power converting circuit 5 for transmitting a power to the motor 6, a battery 1, an energy storing source 20 for storing energy, and a DC/DC converter including at least two switching elements 10, 11, charging the energy storing source 20, and recovering energy in the energy storing source 20 to the battery 1. Since the switch provided in the DC/DC converter is normally turned on when the motor 6 generates power by receiving a power from the engine and charges the battery 1 through the power converting circuit 5 and the DC/DC converter, generation of heat from the DC/DC converter circuit part can be suppressed greatly.

In some of conventional automobile battery power circuits, a battery group and a capacitor group are connected in series, for example, as disclosed in JP 2002-218667 A (FIGS. 3 and 10).
In the aforementioned JP 2002-218667 A, the battery group is composed of a single battery with a rated voltage of 12 V, and the capacitor group is composed of a plurality of capacitors. A DC/DC converter is connected between both ends of the capacitor group and the battery group, and supplies the battery group with a power by lowering a voltage of the capacitor group. Here, the battery group is intended to supply a power to an electrical component with a rated voltage of 12 V, and loads are connected to both ends of the battery group.
In a conventional unit, a power conversion circuit starts operating at the time of a start (in starting an idling stop operation), and a bidirectional DC/DC converter is operated at the same time to transmit a power from the battery group to the capacitor group, whereby the amount of a current flowing through the capacitor group can be reduced. Therefore, the capacitance of the capacitor group can be reduced. After the power conversion circuit has been turned off, the bidirectional DC/DC converter recharges the capacitor group until its voltage reaches a predetermined voltage, thus preparing for a subsequent restart.
As shown in FIG. 10 of JP 2002-218667 A, a circuitry of the bidirectional DC/DC converter of the conventional power unit is provided with two MOSFETs that perform switching at a high frequency (50 to 200 kHz) in boosting and lowering a voltage. In the first MOSFET that performs switching in boosting a voltage, a drain terminal is connected to a high-voltage-side terminal of a capacitor, a source terminal is connected to one terminal of a choke coil, and a gate terminal is connected to a control circuit. In the second MOSFET that performs switching in lowering a voltage, a drain terminal is connected to the choke coil and the source terminal of the first MOSFET, a source terminal is connected to a low-voltage-side terminal of the battery group, and a gate terminal is connected to the control circuit. The other terminal of the choke coil is connected to a high-voltage-side terminal of a battery group and one electrode of a smoothing capacitor, and the other terminal of this capacitor is connected to a low-voltage-side terminal of the battery group.
The power unit supplies energy from the battery group and the capacitor group to the power conversion circuit in starting an idling stop operation, and the power conversion circuit operates. A motor thereby rotates, and an automobile starts moving. The motor causes a rise to an idling rotational speed, and an engine is ignited, so that a shift in driving source is made from the motor to the engine. At the time of a start, the motor operates for 0.2 to 1 second approximately. On the other hand, the motor also functions as a generator. Therefore, while the automobile is running, the power unit is in operation. This operation time is much longer than an operation time at the time of the start.
Because of a short operation time, the amount of heat generated at the time of the start is sufficiently smaller than the amount of heat generated during a power generation operation. The amount of instantaneous heat generation at the time of the start is very large, but can be sufficiently absorbed with a heat capacity of the unit. Accordingly, heat generation at the time of power generation is taken into account in thermally designing the power unit (designing the unit such that its temperature does not exceed an allowable temperature). In the conventional unit, the DC/DC converter is driven at a high frequency at the time of power generation so as to lower energy generated on the high voltage side (Vf3 in the drawing) to the level of a 12V battery. When high-frequency switching is performed, a switching loss increases and thus causes heat generation in a DC/DC converter portion. Because a power conversion circuit portion operates in a diode rectifying mode at the time of power generation, its frequency is low even when a switching operation is performed. The amount of heat generated by the power conversion circuit portion at this moment is small. Therefore, heat generation in the DC/DC converter portion must be sufficiently considered in thermally designing the unit. To keep the temperature of the unit at an allowable value, such measures as enlarging a radiation fin of the unit and mounting a forced air cooling fan or disposing a water cooling radiation fin on a lower face of the unit and turning it into a water cooling mechanism are required. Those measures bring about a rise in cost as well as an increase in size of the unit. Thus, the conventional power unit has a problem of being bulky and costly.


The present invention relates to novel series of amine-containing flavonoids and compositions containing the compounds, as well as the synthesis and the use of the same. The invention also relates to methods of treatment and prevention of diseases, in particular, parasitic infections including Leishmaniasis, comprising administration of the compounds.

Leishmaniasis is one of the six major parasitic diseases in the world. Different clinical manifestations of leishmaniasis include cutaneous, mucocutaneous, diffuse cutaneous, visceral and post kala azar dermal leishmaniasis (PKDL). Out of a total of 2 million annual cases of leishmaniasis, 500,000 of them belong to the visceral leishmaniasis (VL), the most serious and potentially fatal form of leishmaniasis (Ashford R W, et al., Parasitol Today. 1992; 8:104-5). VL is caused by Leishmania donovani in Indian subcontinent, Asia and Africa, and by L. infantum or L. chagasi in the Mediterranean region and South America. There are currently no vaccines available for leishmaniasis.
The primary method for treatment of leishmaniasis has been pentavalent antimonials (SbV):Pentostam (sodium stibogluconate; SSG) and Glucantime (meglumine antimoniate). However, large-scale antimony resistant cases have been reported in regions, including North Bihar of India. Antimonial drugs suffer from many problems including numerous side effects and a long treatment period (20 mg/kg in 2 divided doses for 30 days, intramuscular i.m. or intravenous i.v.).
Amphotericin B is normally considered a secondary treatment for VL, due to its potent antileishmanial activity. Although the use of Amphotericin B (in doses of 0.75-1 mg/kg for 15 to 20 treatments results in high cure rate, this drug suffers from the need for hospitalisation for prolonged periods, high-cost and high incidence of adverse side-effects. A liposomal formulation of amphotericin B (AmBisome® by Gilead) with lower nephrotoxicity has become available, however, this drug is not only expensive, it has other drawbacks including the need for intravenous administration and temperature instability (therefore requiring cold storage).
Paromomycin is an aminoglycoside that can be used alone or in combination with antimonials drugs. Intramuscular administration of paromomycin (15 mg/kg for 20 days) in a clinical trial in India demonstrated 94% efficacy (Sundar S, et al., N Engl J Med. 2007; 356:2571-81). Another antileishmanial agent, pentamidine, requires intramuscular or intravenous administration (2 to 3 mg/kg once a day or every second day for 4 to 7 doses), with higher doses up to 15 doses used for visceral leishmaniasis. The application of this drug is also limited by its toxicity. All of the above currently available treatment options necessitate parenteral administration, and/or hospitalization. Given the poor social infrastructure in the developing countries where most leishmaniasis are found, a chemotherapy-based disease eradication program will rely on the availability of oral drug(s) that can be self-administered without hospitalization.
Miltefosine is currently the only oral treatment available for VL. However, the use of miltefosine is associated with a number of limitations, including (i) potential teratogenicity, (ii) long treatment period of 28 days which leads to poor compliance, (iii) long residence time of miltefosine in patients' plasma which potentially can lead to emergence of miltefosine-resistant parasites, and (iv) high-cost.
In VL, resistance to SSG is a problem in Bihar of India, where half of the world's VL cases are reported. The efficacy of SSG (20 mg/kg/day for 28 days) has steadily dropped from 80% to 40% between 1988 and 2002 (Croft S L, et al. Clin Microbiol Rev. 2006; 19:111-26). In India where VL is anthroponotic (as opposed to zoonotic in other regions), mono-therapy of miltefosine could lead to rapid emergence of resistance (Bryceson A., Trop Med Int Health. 2001; 6:928-34).
Some natural flavonoids are known to have antileishmanial and anti-malarial activities as described in Phytochemistry, 55, 481-504 (2000) and Bioorg. Med. Chem., 22, 18-45 (2014). Nevertheless, due to their unsatisfactory efficacy and bioavailability, usage of these naturally occurring compounds is limited.
More recent studies have demonstrated that amine-linked flavonoid dimers are highly effective anti-promastigotes and anti-amastigotes agents with IC50 ranging from 0.2 to 0.63 μM, rendering them as preferred compounds over naturally occurring flavonoids (Wong I L K, et al., Journal of Medicinal Chemistry. 2012; 55, 8891-8902). One of the preferred potent flavonoid dimers, compound 39 (as shown in FIG. 1) disclosed in Wong I L K et al., which has the following structure:
is also shown to be effective in reducing foot pad lesion size in L. amazonensis cutaneous leishmaniasis murine model (Wong I L K, et al., Antimicrob Agents Chemother. 2014, 58, 3379-3388). However, amine-linked flavonoid dimers are expected to have poor oral bioavailability, and hence would not provide a solution to the problems encountered in the treatment of leishmaniasis as descried above.
There is a need to provide compounds that are able to overcome at least one, but preferably more, of the problems of the prior art. It would be desirable to provide new antileishmanial agents that are effective and safe, and preferably orally bioavailable. It would be desirable to have new antileishmanial agents that are effective against both promastigotes and amastigotes.

Synthesis and use of amine-containing flavonoids as potent anti-leishmanial agents


The relay includes a coil assembly enclosed in a top enclosure made from insulating material. The coil assembly includes a spooled coil body, a core, pole shoes and winding terminal elements assembly and is disposed above a pivoting armature which is connected to contact springs via a carrier element of insulating material. The relay also includes a base made from insulating material and which contains terminal paths for stationary cooperating contact elements as well as contact terminal elements. The armature is disposed above the base via bearing supports and bearing bands integrated in the contact springs. A frame is disposed over the base and forms a housing for the relay together with the base and with the top enclosure. The housing encapsulates the contact space of the relay, wherein the frame with the base represents the lower housing part and the top enclosure for the coil assembly represents the upper housing part.

In DE 195 20 220 C1, a relay is disclosed with a body which forms the sidewalls of the housing serves therein for the separation of the contact space from the coil space. The body is made of insulating material and has an H-shaped profile which accepts the coil, permanent magnet and pole shoes and overlaps the base. Furthermore, the coil space is filled with a sealing compound up to an upper edge of the basic body following insertion of the coil, permanent magnet and pole shoes. The attachment of a housing cover is a separate step. This additional step makes the production of the relay costlier. In addition, the sidewalls of the basic body which overlap the base offer poor accessibility to armature, carrier element and stationary and moving contact elements as well.
WO 94/22 156 teaches a polarized electromagnetic relay in which magnet system, armature and base are respectively arranged over one another in the aforementioned order. There, however, the coil with the components appurtenant thereto is not coated, so that this relay contains none of the contact space encapsulated by the windings of the coil. In addition, this relay does not contain any specific fastening possibilities for the various individual parts of the magnet system. Besides only weak assembly accessories, the structural shape of relay taught by WO 94/22 156 comprises a lower mechanical stability conditional to not accepting a coated basic body as carrier element for the components of the magnet system. This poses a disadvantage, insofar as the working air gap can misadjust during assembly. In addition, there exists no metal protection against the coil wire vapors or exhalations which could arise, for example, in the SMT soldering process.


A method of separating, recovering and reusing components of an exhausted slurry used in slicing silicon wafers from a silicon ingot. In the method, the solid particles and lubricating fluid of the exhausted slurry are separated without decreasing the viscosity of the exhausted slurry. The separated lubricating fluid may be collected and reused in the preparation of a fresh slurry. Additionally, the silicon particulate and metal slicing wire particulate are dissolved and separated from the abrasive grains. The abrasive grains are separated into spent abrasive grains and unspent abrasive grains. The separated unspent abrasive grains are suitable for reuse in the preparation of a fresh slurry.

The present invention relates generally to a method for the regeneration of an abrasive slurry utilized in the preparation of silicon wafers. More particularly, the present invention relates to a method of separating components of an exhausted slurry, used in slicing wafers from a single crystal or polycrystalline silicon ingot, such that the desirable abrasive grains and lubricating, or cooling, fluid therein may be reused.
Silicon wafers are obtained from a single crystal or polycrystalline silicon ingot by first slicing the ingot in a direction normal to its axis. Typically, the slicing operation is accomplished by means of a wire saw, wherein the silicon ingot is contacted with a reciprocating wire while a slurry containing abrasive grains is supplied to the contact area between the ingot and the wire. Conventional wire saw slurries typically comprise a lubricating, or cooling fluid, such as, for example, mineral oil or some water soluble liquid (e.g., polyethylene glycol, or "PEG"), and abrasive grains, such as silicon carbide.
During the slicing operation, silicon particulate from the ingot and metal particulate (primarily iron) from the slicing wire and metal pipes form and are incorporated into the slurry. As the concentrations of the silicon and metal particulate in the slurry increase, the efficiency of the slicing operation decreases. Eventually, the slurry becomes ineffective, or "exhausted," and must be discarded. Typically, the exhausted slurry is disposed of by incineration or treated by a waste water treatment facility. However, burning this slurry generates carbon dioxide and sending this slurry to a waste water treatment facility typically results in the formation of a sludge which must be disposed of in a landfill. Accordingly, both approaches of disposal are unfavorable from an environmental point of view. It is therefore desirable to eliminate, or significantly reduce the amount of, this waste which is generated.
In addition to the negative environmental consequences and the costs associated with the disposal of the exhausted slurry, silicon wafer production costs are also increased due to the fact that the slurry is generally disposed of prematurely. More specifically, the rate at which the abrasive grains in the slurry are "spent" (i.e., worn to a size too small for effective slicing) by the slicing operation is generally much less than the rate at which the slurry becomes contaminated by silicon and metal particulate. Furthermore, the useful life of a typical lubricating or cooling fluid is dictated almost entirely by the build-up of silicon and/or metal particulate; that is, the lubricating or cooling solution could be used for a much longer period of time, if it were not for the increasing concentration of silicon and metal particulate in the slurry. As a result, the slurry is typically discarded once the level of silicon and/or metal particulate in the slurry is too high, even though much of the abrasive grains and lubricating fluid are still usable.
In view of the foregoing, a need continues to exist for a method which may be utilized to separate silicon and metal wire particulate from the slurry, thus enabling the reuse of abrasive grains and the lubricating fluid. Such a process would reduce the manufacturing costs associated with the slicing of silicon ingots. In addition, such a process would reduce the amount of waste product and/or waste byproduct emitted into the environment.

Method for treating an exhausted glycol-based slurry


The subject invention provides a remote control signal reception circuit that carries out quantization of an input data signal 101 by sampling the signal with a first sampling frequency that is higher than a frequency of said input data signal, and stores a result of the quantization 105 in storing means; and then, the result of the quantization 105 stored in said storing means is corrected according to each result, and is outputted as quantization data 106. In this way, the present invention provides an infrared light reception unit that achieves highly-faithful reproduction of the original waveform, allowing multi-stages transmission in a simple manner.

An infrared remote control unit (generally simply called an infrared remote controller or a remote controller; hereinafter referred to as a remote controller) is a general equipment for a video device or an air conditioner to enable remote manipulation of the device. Normally, a remote controller modulates data of an infrared pulse sequence having a predetermined period, approximately 38 kHz, with an ON/OFF operation by a longer period, and then transmitting the modulated data to a remote control signal reception device such as a TV set.
Receiving the modulated data, the reception device demodulates the data, denoting ON with repeated pulses of about 38 kHz, into a signal with a smooth pulse from the beginning to end, before supplying the data to a decoding device.
In this way, the ON and OFF states are temporarily converted into digital signals of "H" level and "L" level, respectively, and then are supplied to a microprocessor provided inside the reception machine as remote control signals, and the remote control code of the signal is deciphered to interpret the command. PWM (Pulse Width Modulation) is a modulation mode using a rising point of the ON signal. PPM (Pulse Position Modulation) uses positions of a constant-sized pulse.
As may be seen, the period with a continuous pulse and the period with no discharge of pulse are very important in terms of proper decoding of the remote control signal in a later-stage circuit. Further, in PPM, pulse-size needs to be properly transmitted, otherwise accurate detection of the position fails.
Incidentally, conversion of the pulse into a smoothed signal denoting "H" level is generally performed by using a characteristic of the capacitor. Once change is accumulated in the capacitor, the output level dos not rapidly decrease even when the pulse turns OFF in a moment, as long as the capacitor holds the charge. Therefore, by appropriately setting the threshold, it is possible to digitally keep it in "H" level, as long as the pulse continues.
However, on the contrary, it is digitally maintained at "H" level even when the pulse ends until the charge of the capacitor is discharged, and the output level falls below the threshold. Accordingly, even when the transmission end transmits a regular ON-time signal, the "H" level signal in the receiving end becomes slightly longer due to the characteristic of the reception side. Further, as a result, the "L" level signal becomes shorter than its original regular signal. This defect is publicly-known, and is disclosed in, for example, Japanese Laid-Open Patent Application Tokukai 2001-145184 (published on May 25, 2001).
Here, the following describes conversion of the pulse into a smooth signal denoting "H" level, with reference to a part of FIG. 1.
In FIG. 1, the reference numeral 100 is an infrared pulse transmitted from a remote control transmission machine, that is generally a carrier of frequency of approximately 38 kHz (generally approximately 38 kHz-40 kHz). In the figure, the reference numeral 101 denotes a waveform having been smoothed by a smoothing circuit (not shown) including a condenser.
In the signal denoted by the reference numeral 101, the voltage gradually decreases in the portion corresponding to the trough of the infrared light pulse. However, the threshold value denoted by the reference numeral 103 (uniform voltage) is set so that the next pulse comes before the output voltage comes at or lower than the threshold value. After the pulse stops, the condenser carries out discharging at a certain time constant, and therefore it takes a little while for the voltage to decrease to "L" level (low-level).
The reference numeral 102 is a digitalized waveform of the output voltage (denoted by the reference numeral 101) of the smoothing circuit, created based on level comparison with the threshold value denoted by the reference numeral 103. As explained, it takes a certain time (denoted by the reference numeral 104) for the output voltage to decrease to or below the threshold value due to the characteristic of the condenser, and therefore, "H" level (high-level) period of the waveform 102 is extended by the period of the reference numeral 104, compared to the waveform denoted by the reference numeral 100.
To deal with such a characteristic, the receiving end needs to carry out decoding of the received signal in consideration of such difference with the original signal. In a general use, the problem may be solved in the remote control signal receiving end with a relatively simple arrangement corresponding to the degree of extension of the period of "H" level.
However, in a recent remote control technology, the signal transmitted from the remote controller is not simply processed directly in the general receiving end, but transferred to the receiving end via a separate device. For example, "Liquid Crystal FACE Wireless" (liquid crystal TV), a product of TOSHIBA, that became commercially available in September 2002, is equipped with a function called a 'Remote Control Pass-Through (http://www.toshiba.co.jp/webcata/ctv/201f10.htm)". In this function, the signal operated by a user using a remote controller is temporary received in a TV image reception machine, and then transmitted via a wireless medium to an image transmission machine or the like provided in front of a different device, such as a VCR.
This image transmission machine transmits the received remote control signal via the built-in remote control transmission machine while maintaining the original condition of the signal as much as possible. In the case of the foregoing example, it is assumed that the user watches a video image with a liquid crystal TV, that is distant from the VCR and the image transmission machine. When the user gives some kind of instruction, such as "pause" through the remote controller of the video, the instruction signal is temporarily received in the image/infrared signal reception machine included in the liquid crystal TV, and the signal is transferred to the image transmission machine by an electric wave. As a result, an infrared signal corresponding to the received signal is transmitted from a remote control transmission machine included in the image transmission machine. Then, the machine (VCR in this case) that received the infrared signal carries out operation of "pause", as if the machine directly receives instruction of "pause" from the remote controller of the VCR.
The problem raised here is the error of the "H" level period in reception of the infrared light. A general structure assuming direct operation of the remote controller is designed with a margin to handle a stage of delay of relay transmission; however, the foregoing "Remote Control Pass-Through Function" requires the infrared light reception twice, thus increasing the error. The allowable range of the error differs for each case, and therefore, the user has to confirm proper operation of the system by referring to experiences, or by carrying out some kind of test. This problem is disclosed in the Japanese Laid-Open Patent Application Tokukai 2001-145184 in detail and some other publications.
To solve this problem, various methods have been proposed. For example, Japanese Laid-Open Patent Application Tokukaihei 04-302525/1992 (published on Oct. 26, 1992) discloses a pulse demodulation circuit that achieves reduction of the concerned false "H" period after termination of the pulse by using a constant-current load circuit and a limiter circuit. Further, the Tokukai 2001-145184 discloses a particular method to be used with the 'Remote Control Pass-Through' function.
However, the foregoing prior art has the following problems. The method of Tokukaihei 04-302525 achieves reduction of the concerned period; however, since the delay can still not be reduced to 0, this cannot completely solve the problem. For example, when the method is adopted for multi-stages relay operation, the error may be accumulated, causing some kind of defect.
Further, the method of Tokukai 2001-145184 gives up reduction of the concerned period, and instead intentionally causes a delay of the start time for the same length as the period, thereby matching the "H" level period with the time intended in the receiving end of the remote control signal.
However, to cause such a delay of the start time, this method requires adjustment of the capacitor, the resistor, and the reference voltage. Besides, such adjustment is performed in an analog manner, that may not be highly compatible with a digitalized device, and also may require a larger number of components.
Further, decipher of a remote control signal is generally performed by a CPU or a dedicated IC. Since, the capacitor or the resistor are not suitable to be included in these digital ICs, it increases manufacturing cost.
Furthermore, when such a circuit is provided in a semiconductor, the characteristic varies, and there will be some difficulties for adjustment. Since a recent technology uses various photoelectric conversion elements for converting an infrared light to an electric signal, those defects prevent the circuit from adjustment for each type of element.

Remote control signal reception circuit, remote control signal reception method, remote control signal reception program, and computer-readable storage medium storing the program


In a semiconductor device comprising an N channel MOS device, and P channel MOS device, or additionally comprising a MONOS device, provided with a gate insulating film and gate electrode formed on a semiconductor substrate or semiconductor layers of a SOI substrate, respectively, the gate insulating film of at least the P channel MOS device is made up of a dual-layer film consisting of a gate oxide film composed of a silicon dioxide film, and a gate silicon nitride film.

1. Field of the Invention
The invention relates generally to a semiconductor device and a method of fabricating the same, and more particularly, to the structure of a semiconductor device provided with an N channel MOS device and a P channel MOS device, or a MONOS device in addition thereto which are all formed on top of a common semiconductor substrate, or a common SOI substrate, and a method of fabricating the same.
2. Description of the related Art
A MOS (Metal-Oxide-Semiconductor) device using a semiconductor substrate made of silicon, and the same using a semiconductor substrate having a semiconductor layer on top of an insulating layer formed on a supporting substrate, a so-called SOI (Silicon on Insulator) substrate are well known.
First, the structure of a conventional MOS device using a semiconductor substrate made of silicon is described by way of example with reference to a schematic cross sectional view shown in FIG. 69.
The MOS device shown in FIG. 69 comprises an N channel MOS device 11, and a P channel MOS device 12, which are both formed on a semiconductor substrate 1 made of silicon, making up a complementary MOS device.
The N channel MOS device 11 is provided with a gate oxide film 2 and gate electrode 3 formed on the surface of the semiconductor substrate 1 over a P well 4 formed of a p-type doped layer diffused in the semiconductor substrate 1, and also with a source 6 and drain 7, formed of a heavily doped n-type layer on the surface of the semiconductor substrate 1, matching the gate electrode 3.
The P channel MOS device 12 is provided with a gate oxide film 2 and gate electrode 3 formed on the surface of the semiconductor substrate 1 over an N well 5 formed of an n-type doped layer diffused in the semiconductor substrate 1, and also with a source 16 and drain 17, formed of a heavily doped p-type layer on the surface of the semiconductor substrate 1, matching the gate electrode 3.
The N channel MOS device 11 and P channel MOS device 12 are isolated from each other by a field oxide film 13 formed on the surface of the semiconductor substrate 1.
An interlevel insulator 8 is formed on the entire surface of the semiconductor substrate 1, and via contact holes 9 formed in the interlevel insulator 8, connection to other MOS devices formed on the semiconductor substrate 1 is made with interconnections 10 (interconnection 10 connected to the gate electrodes 3, 3, respectively, is disposed at a position different in cross-sectional view from that shown in FIG. 69), one end of which are connected to the gate electrode 3, source 6 and drain 7 of the N channel MOS device 11 as well as the gate electrode 3, source 16 and drain 17 of the P channel MOS device 12, respectively.
Now the structure of a conventional MOS device using a SOI substrate is described by way of example with reference to a schematic cross sectional view shown in FIG. 70.
The MOS device shown in FIG. 70 makes use of the SOI substrate 23 comprising a supporting substrate 20, an insulating film 21, and a plurality of semiconductor layers 22a, 22b, each patterned in an island-like shape
A gate oxide film 2 and gate electrode 3 are formed on top of the respective semiconductor layers 22a, and 22b, making up a semiconductor device comprising an N channel MOS device 11 and a P channel MOS device 12.
The N channel MOS device 11 is provided with a source 6 and drain 7, formed of a heavily doped N type layer, in a region of the semiconductor layer 22a, matching a gate electrode 3.
Similarly, the P channel MOS device 12 is provided with a source 16 and drain 17, formed of a heavily doped P type layer, in a region of the semiconductor layer 22b, matching a gate electrode 3.
The N channel MOS device 11 and the P channel MOS device 12 are completely isolated for insulation from each other with an interlevel insulator 8 and the insulating film 21.
Then, via respective contact holes 9 formed in the interlevel insulator 8, connection to other MOS devices formed on the SOI substrate 23 is made with interconnections 10 (interconnection 10 connected to the gate electrodes 3, 3, respectively, is disposed at a position different in cross-sectional view from that shown in FIG. 70), one end of which is connected to the gate electrode 3, source 6 and drain 7 of the N channel MOS device 11 as well as the gate electrode 3, source 16 and drain 17 of the P channel MOS device 12, respectively.
Next, the structure of a conventional semiconductor device incorporating a MONOS device in addition to the semiconductor device shown in FIG. 69 is described by way of example with reference to FIG. 71.
In the semiconductor device shown in FIG. 71, an N channel MOS device 11, a P channel MOS device 12, and a MONOS device 35 are formed on a semiconductor substrate 1 made of silicon.
The N channel MOS device 11 is provided with a gate oxide film 2 and gate electrode 3 formed on the surface of the semiconductor substrate 1 over a P well 4 formed of a p-type doped layer diffused in the semiconductor substrate 1, and also with a source 6 and a drain 7, formed of a heavily doped n-type layer on the surface of the semiconductor substrate 1, matching the gate electrode 3.
The P channel MOS device 12 is provided with a gate oxide film 2 and gate electrode 3 formed on the surface of the semiconductor substrate 1 over an N well 5 formed of an n-type doped layer diffused in the semiconductor substrate 1, and also with a source 16 and a drain 17, formed of a heavily doped p-type layer on the surface of the semiconductor substrate 1, matching the gate electrode 3.
The MONOS device 35 is provided with a memory insulating film 34 comprising a memory oxide film 31, a memory nitride film 32, and a top oxide film 33, and also with a memory gate electrode 50, which are all formed on the surface of the semiconductor substrate 1 over a P well 4 formed of a p-type doped layer diffused in the semiconductor substrate 1, and also with a source 7 (for common use as the drain 7 of the N channel MOS device 11) and a drain 18, formed of a heavily doped n-type layer on the surface of the semiconductor substrate 1, matching the memory gate electrode 50.
The P channel MOS device 12, N channel MOS device 11, and MONOS device 35 are isolated from each other with field oxide films 13 formed on the surface of the semiconductor substrate.
An interlevel insulator 8 is formed on the entire surface of the semiconductor substrate 1 and via contact holes 9 formed in the interlevel insulator 8, connection to other MOS devices formed on the semiconductor substrate 1 is made with interconnections 10, ends of which are connected to the gate electrodes 3, the sources 6, 16 and the drains 7, 17, 18 of the respective semiconductor devices 11, 12, and 35.
A method of fabricating the semiconductor device shown in FIG. 71 is described hereinafter with reference to FIGS. 72 through 76, which are cross-sectional views showing respective steps of a fabrication process.
The first half of the fabrication process of the semiconductor device described above comprises the same steps as those of a third embodiment of a method of fabricating a semiconductor device according to the invention as described hereinafter with reference to FIGS. 29 through 34. Accordingly, illustration of these steps is omitted, and the fabrication process is described with reference to FIG. 72 only.
First, by oxidizing the semiconductor substrate 1 made of silicon in an oxidizing atmosphere, an oxide film is formed on the surface thereof
Subsequently, a photo-resist which is a photosensitive polymer is formed on the entire surface of the oxide film by use of a spin coater, and by applying exposure and development treatment thereto with the use of a predetermined mask, the photo-resist is patterned in such a way as to form an opening delineating an N channel region where the N channel MOS device and the MONOS device are to be formed. Thereafter, the oxide film is etched by use of the photo-resist as an etching mask.
Then, a first buffer oxide film is formed by oxidizing the semiconductor substrate 1 in an oxidizing atmosphere, whereupon ions of boron, a p-type dopant, are implanted to form a P well. As a result, boron is implanted in the surface region of the semiconductor substrate 1, in the N channel region 42 where the first buffer oxide film with a thin oxide film is formed.
Subsequently, after removing the oxide film described in the foregoing and the first buffer oxide film, a second buffer oxide film is formed on the entire surface of the semiconductor substrate 1 by oxidizing the same in an oxidizing atmosphere, and the photo-resist is patterned in such a way as to form an opening delineating a P channel region 43 where the P channel MOS device is to be formed.
Ions of phosphorus, an n-type dopant, are implanted into the P channel region 43 with the use of the photo-resist described above as a mask against ion implantation. The second buffer oxide film is then removed.
Thereafter, by oxidizing the semiconductor substrate 1 in a thin oxidizing atmosphere and applying heat treatment thereto, the ion-implanted dopants are activated, thereby forming the P well 4 and an N well 5, and at the same time, a pad oxide film is formed on the surface of the semiconductor substrate 1.
Subsequently, on the entire surface of the pad oxide film, a nitride film composed of a silicon nitride film is formed by means of the chemical vapor deposition process, and a photo-resist is formed in regions where the N channel MOS device, P channel MOS device, and MONOS device are to be formed, respectively.
The nitride film is then etched using the photo-resist described above as an etching mask.
Thereafter, field oxide films 13 shown in FIG. 72 are formed through selective oxidation in an oxidizing atmosphere, and the nitride film as well as the pad oxide film are removed.
As shown in FIG. 72, gate oxide films 2 are then formed through oxidation in an oxidizing atmosphere, and a first gate electrode material 48 is formed over the gate oxide films 2.
Then, photo-resists 113 are patterned in regions where the gate electrodes are to be formed. The first gate electrode material 48 is etched using the photo-resists 113 as etching masks, forming the gate electrodes 3 as shown in FIG. 73. Further, the gate oxide film 2 except portions thereof underneath the gate electrodes 3 is removed.
Thereafter, through oxidation in an oxidizing atmosphere, the memory oxide film 31 shown in FIG. 74 is formed and turned into a nitride oxide film by annealing in an ammonia atmosphere.
In the course of annealing in an ammonia atmosphere, ammonia and hydrogen are diffused into the gate oxide films 2, a constituent part of the MOS devices already formed, causing a problem of positive electric charge being induced in the gate oxide films 2 and at the interface between the gate oxide films 2 and the semiconductor substrate 1.
Since the electric charge remains without electrical neutrality being restored before completion of the fabrication process, there will arise a problem that shift in the threshold voltage of the respective MOS devices occurs.
Subsequently, on the entire surface of the memory oxide film 31, the memory nitride film 32, the top oxide film 33, and the second gate electrode material 49 are formed in sequence.
Thereafter, photo-resist 114 is patterned in a region where the memory gate electrode of the MONOS device is to be formed.
The second gate electrode material 49, the top oxide film 33, the memory nitride film 32, and the memory oxide film 31 are etched using the photo-resist 114 as an etching mask, forming the memory gate electrode 50 as shown in FIG. 75.
Then, ions of arsenic, an n-type dopant, are implanted into the surface of the semiconductor substrate 1, in parts of the N channel region 42, matching the gate electrode 3, and the memory gate electrode 50, forming the source 6 and the drains 7, belonging to a heavily doped N layer as shown in FIG. 76.
Subsequently, ions of boron, a p-type dopant, are implanted into the surface of the semiconductor substrate 1, in part of the P channel region 43 shown in FIG. 75, matching the gate electrode 3, forming the source 16 and the drain 17 belonging to a heavily doped P layer as shown in FIG. 76. Thereafter, heat treatment is applied thereto in order to activate the dopants.
Further, an interlevel insulator 8 is formed on the entire surface as shown in FIG. 76, openings for the contact holes 9 are formed in the interlevel insulator 8, and the interconnections 10 is provided.
Thus, using the semiconductor substrate 1 made of silicon, the semiconductor device comprising the N channel MOS device 11, the P channel MOS device 12, and the MONOS device 35, which are formed on the same semiconductor substrate 1, is fabricated.
There are cases where MOS devices of the aforesaid structure are used in the controller of a satellite sent up into space, or the controller of a nuclear reactor.
However, when the conventional MOS devices described above are put to use in an environment where radiation such as gamma rays are present, positive electric charge is developed in the gate oxide films, or at the interface between the semiconductor substrate and the gate oxide films, lowering the threshold voltage of the N channel MOS device, and generating leakage current.
On the other hand, this will raise the threshold voltage of the P channel MOS device, rendering the controller inoperative.
Also, when fabricating a semiconductor device comprising the N channel MOS device, the P channel MOS device, and the MONOS device, all formed on a semiconductor substrate made of silicon, the memory oxide film is turned into a nitride oxide film by applying heat treatment thereto in an ammonia atmosphere in order to improve the writable and erasable characteristic of the MONOS device. At this point in time, positive electric charge is induced in the gate oxide films and at the interface between the gate oxide films and the semiconductor substrate as described in the foregoing due to the reaction of ammonia and hydrogen, creating a cause for malfunction due to shift in the threshold voltage.
It is therefore an object of the invention to inhibit shift in the threshold voltage of MOS devices in a radiation environment, and another object of the invention is to inhibit shift in the threshold voltage of MOS devices which occurs when annealing in an ammonia atmosphere during a process of fabricating a semiconductor device comprising MOS devices and a MONOS device, formed on the semiconductor substrate, by solving the problems described in the foregoing.
To this end, a semiconductor device according to the invention has the structures described as follows:
The semiconductor device comprises a semiconductor substrate, and an N channel MOS device and a P channel MOS device having a gate insulating film formed on the semiconductor substrate and a gate electrode formed on the gate insulating film, the gate insulating film being made up of a dual-layer film consisting of a gate oxide film composed of a silicon dioxide film and a gate silicon nitride film respectively.
Or, in a semiconductor device comprising an SOI substrate made up of a supporting substrate, an insulating film, and a plurality of semiconductor layers, each patterned in an island-like shape, and an N channel MOS device and a P channel MOS device having a gate insulating film formed on each of the semiconductor layers, and a gate electrode formed on the gate insulating film, respectively, the gate insulating film may be made up of a dual-layer film consisting of a gate oxide film composed of a silicon dioxide film, and a gate silicon nitride film.
These semiconductor devices may further comprise a MONOS device having a memory insulating film composed of a memory oxide film, a memory nitride film, and a top oxide film, formed on the semiconductor substrate, and a memory gate electrode formed on the memory insulating film.
Further the gate insulating film of the N channel MOS device is made up of a gate oxide film composed of a silicon dioxide film, and only the gate insulating film of the P channel MOS device is made up of a dual-layer film consisting of a gate oxide film composed of a silicon dioxide film, and a gate silicon nitride film.
The method of fabricating a semiconductor device according to the invention comprises the following steps (1) to (18) to accomplish the object of the invention:
(1) step of forming an oxide film on the entire surface of a semiconductor substrate through oxidation thereof in an oxidizing atmosphere;
(2) step of etching the oxide film on the semiconductor substrate, in a N channel region where an N channel MOS device is to be formed;
(3) step of forming a first buffer oxide film for implanting a p-type dopant into the N channel region;
(4) step of implanting the p-type dopant into the N channel region of the semiconductor substrate;
(5) step of forming a second buffer oxide film on the entire surface of the semiconductor substrate after etching the oxide film formed on the entire surface of the semiconductor substrate;
(6) step of implanting an n-type dopant into a P channel region of the semiconductor substrate, where a P channel MOS device is to be formed, using photosensitive polymer as a mask;
(7) step of forming a pad oxide film on the entire surface of the semiconductor substrate after etching the second buffer oxide film, and activating the respective dopants implanted in an oxidizing atmosphere;
(8) step of forming a nitride film composed of a silicon nitride film, on the pad oxide film;
(9) step of etching the nitride film in regions of the semiconductor substrate where field oxide films are to be formed;
(10) step of removing the nitride film and pad oxide film after forming the field oxide films on the semiconductor substrate by means of a selective oxidation method for effecting device isolation between the N channel region and the P channel region;
(11) step of forming a gate oxide film on the entire surface of the semiconductor substrate, in the N channel region and P channel region, in an oxidizing atmosphere, forming a gate silicon nitride film on the entire surface of the gate oxide film, and forming a gate electrode material on the entire surface of the gate silicon nitride film;
(12) step of forming gate electrodes by etching the gate electrode material and the gate silicon nitride film;
(13) step of forming a highly doped n-type layer in regions for forming a source and drain, in the N channel region of the semiconductor substrate, using photosensitive polymer as a mask against ion implantation;
(14) step of forming a highly doped p-type layer in regions for forming a source and drain, in the P channel region of the semiconductor substrate, using photosensitive polymer as a mask against ion implantation;
(15) step of forming an interlayer insulating film composed primarily of a silicon dioxide film on the entire surface of the semiconductor substrate;
(16) step of activating the highly doped n-type and p-type layers by annealing thereto, and step of forming a plurality of contact holes in the interlayer insulating film by means of the photo-etching method; and
(17) step of forming interconnections connected, via the contact holes, to the gate electrode, the source, and the drain of the N channel MOS device and the P channel MOS device, respectively.
Further, the following steps may be included instead of the aforementioned steps (11) and (12):
step of forming a gate oxide film on the entire surface of the semiconductor substrate, in the N channel region and P channel region in an oxidizing atmosphere, forming a gate silicon nitride film on the entire surface of the gate oxide film;
step of removing the gate silicon nitride film by photo-etching such that the gate silicon nitride film in the N channel region is left intact;
step of forming a gate electrode material on the entire surface of the semiconductor substrate; and
step of forming gate electrodes by etching the gate electrode material.
Further, in the case of fabricating the semiconductor device provided with a MONOS semiconductor device, it comprises the following steps instead of the aforementioned steps (11) and (12)
step of forming a gate oxide film on the entire surface of the semiconductor substrate, in the N channel region and the P channel region, in an oxidizing atmosphere, and forming a gate silicon nitride film on the entire surface of the gate oxide film;
step of forming a first gate electrode material on the entire surface of the gate silicon nitride film, and forming gate electrodes by a photo-etching method;
step of forming a memory oxide film by oxidizing the entire surface of the semiconductor substrate in an oxidizing atmosphere, and turning the memory oxide film into an nitride oxide film by annealing in an ammonia atmosphere;
step of forming a memory nitride film on the memory oxide film, forming a top oxide film by oxidizing the memory nitride film in an oxidizing atmosphere, and forming a second gate electrode material on the entire surface of the top oxide film;
step of forming a memory gate electrode by photo-etching the second gate electrode material, the top oxide film, the memory nitride film, and the memory oxide film; and
step of forming interconnections connected, via the contact holes, to the gate electrode, the source, and the drain of the N channel MOS device, the P channel MOS device, and a MONOS device, respectively in the aforementioned step (17).
In the case of using an SOI substrate made up of a supporting substrate an insulating film and the semiconductor layer, the following steps (1) to (14) are included:
(1) step of forming a first semiconductor layer patterned in an island-like shape on which an N channel MOS device is to be formed, and a second semiconductor layer patterned in an island-like shape on which a P channel MOS device is to be formed, by etching the semiconductor layer on the SOI substrate using the photosensitive polymer as an etching mask;
(2) step of forming a gate oxide film on the surface of the first and second semiconductor layers, respectively, by oxidizing the respective semiconductor layers in an oxidizing atmosphere;
(3) step of forming a P channel doped layer in the region of the first semiconductor layer using photosensitive polymer as a mask against ion implantation;
(4) step of forming an N channel doped layer in the region of the second semiconductor layer using photosensitive polymer as a mask against ion implantation;
(5) step of forming a p-type doped layer for prevention of surface inversion in the boundary region surrounding the first semiconductor layer using photosensitive polymer as a mask against ion implantation;
(6) step of forming an n-type doped layer for prevention of surface inversion in the boundary region surrounding the second semiconductor layer using photosensitive polymer as a mask against ion implantation;
(7) step of forming a gate silicon nitride film on the gate oxide film formed on the surface of the respective semiconductor layers and forming a gate electrode material on the gate silicon nitride film;
(8) step of forming gate electrodes by etching the gate electrode material and the gate silicon nitride film.
(9) step of forming a highly doped n-type layer in regions of the first semiconductor layer, for forming a source and a drain, using photosensitive polymer as a mask against ion implantation;
(10) step of forming a highly doped p-type layer in regions of the second semiconductor layer, for forming a source and a drain, using photosensitive polymer as a mask against ion implantation;
(11) step of forming an interlayer insulating film composed primarily of a silicon dioxide film on the entire surfaces of the semiconductor layers;
(12) step of activating the highly doped n-type and p-type layers by annealing;
(13) step of forming a plurality of contact holes in the interlayer insulating film by means of a photo-etching method; and
(14) step of forming interconnections connected, via the contact holes, to the gate electrode, the source, and the drain of the N channel MOS device and the P channel MOS device, respectively.
The following steps may be included instead of the aforementioned steps (7) and (8):
step of forming a gate silicon nitride film on the gate oxide film formed on the surface of the respective semiconductor layers;
step of removing the gate silicon nitride film by the photo-etching method except that the region of the first semiconductor layer is kept intact;
step of forming a gate electrode material on the entire surfaces of the semiconductor layers; and
step of forming gate electrodes by etching the gate electrode material.
Still further, in the case of fabricating a semiconductor device provided with a MOS semiconductor device and a MONOS semiconductor device using an SOI substrate made up of a supporting substrate, an insulating film and a semiconductor layer, the following steps (1) to (17) are included:
(1) step of forming photosensitive polymer on the semiconductor layer of the SOI, and forming a first semiconductor layer patterned in an island-like shape on which an N channel MOS device is to be formed, a second semiconductor layer patterned in an island-like shape on which a P channel MOS device is to be formed, and a third semiconductor layer patterned in an island-like shape on which a MONOS device is to be formed, by etching the semiconductor layer using the photosensitive polymer as an etching mask;
(2) step of forming a gate oxide film on the surface of the first through third semiconductor layers, respectively, by oxidizing the respective semiconductor layers in an oxidizing atmosphere;
(3) step of forming a P channel doped layer in the regions of the first and the third semiconductor layers using photosensitive polymer as a mask against ion implantation;
(4) step of forming an N channel doped layer in the region of the second semiconductor layer using photosensitive polymer as a mask against ion implantation;
(5) step of forming a p-type doped layer for prevention of surface inversion in the boundary regions surrounding the first and the third semiconductor layers using photosensitive polymer as a mask against ion implantation;
(6) step of forming an n-type doped layer for prevention of surface inversion in the boundary region surrounding the second semiconductor layer using photosensitive polymer as a mask against ion implantation;
(7) step of forming a gate silicon nitride film on the entire surfaces of the semiconductor layers;
(8) step of forming a first gate electrode material on the entire surface of the gate silicon nitride film, and forming gate electrodes by means of a photo-etching method;
(9) step of forming a memory oxide film by oxidizing the entire surface of the semiconductor layers in an oxidizing atmosphere, and annealing in an ammonia atmosphere for turning the memory oxide film into a nitride oxide film;
(10) step of forming a memory nitride film on the memory oxide film, forming a top oxide film by oxidizing the memory nitride film in an oxidizing atmosphere, and forming a second gate electrode material on the top oxide film;
(11) step of forming a memory gate electrode by etching the second gate electrode material, the top oxide film, the memory nitride film, and the memory oxide film by means of the photo-etching method;
(12) step of forming a highly doped n-type layer in regions of the first and third semiconductor layers, respectively, for forming a source and a drain, using photosensitive polymer as a mask against ion implantation;
(13) step of forming a highly doped p-type layer in regions of the second semiconductor layer, for forming a source and a drain, using photosensitive polymer as a mask against ion implantation;
(14) step of forming an interlayer insulating film composed primarily of a silicon dioxide film on the entire surfaces of the semiconductor layers;
(15) step of activating the highly doped n-type and p-type layers by annealing;
(16) step of forming a plurality of contact holes in the interlayer insulating film by means of the photo-etching method; and
(17) step of forming interconnections connected, via the contact holes, to the gate electrode, the source, and the drain of the N channel MOS device, the P channel MOS device, and the MONOS device, respectively.
As described above, in the semiconductor device and the method of fabricating the same, according to the invention, the gate insulating film of the N channel MOS device and the P channel MOS device, respectively, or the gate insulating film of the P channel MOS device only, is made up of the dual-layer film consisting of the gate oxide film composed of the silicon dioxide film, and gate silicon nitride film.
As a result, diffusion of reacting gas such as ammonia and hydrogen is inhibited in the course of heat treatment in an ammonia atmosphere during the fabrication process owing to the effect of the gate silicon nitride film which is a closely packed film, making up the gate insulation film.
Consequently, reaction in the gate oxide film, and at the interface between the gate oxide films and semiconductor substrate can be inhibited with the result that generation of positive electric charge in these regions is prevented, thereby inhibiting shift in the threshold voltage.
Further, since the gate insulating film is made up of the dual-layer film consisting of the gate oxide film composed of the silicon dioxide film and the gate silicon nitride film, there will arise a matching problem at the interface between the gate oxide film and the gate silicon nitride film with the result that an electrically charged interfacial energy level occurs at the interface.
In the MOS devices of the invention, the threshold voltage is controlled by regulating the concentration of dopants in the wells to cope with the interfacial energy level.
Hence, when the semiconductor device according to the invention is put to use in a radiation environment, positive electric charge generated by the presence of gamma rays or the like decreases in magnitude due to the effect of the interfacial energy level, thereby inhibiting shift in the threshold voltage.
The above and other objects, features and advantages of the invention will be apparent from the following detailed description which is to be read in conjunction with the accompanying drawings.

Semiconductor device and fabricating the same


The present invention is a conductive polymer composition containing a π-conjugated conductive polymer, a polyanion, and a gemini surfactant. There can be provided a conductive polymer composition that has excellent antistatic performance and excellent application properties, does not adversely affect a resist, and can be suitably used in lithography using electron beam or the like.

Field of the Invention
The present invention relates to a conductive polymer composition containing a π-conjugated conductive polymer, a coated article using the same, and a patterning process. In particular, the present invention relates to a conductive polymer composition that is suitably used for prevention of electrification of a resist in lithography using ultraviolet light, electron beam, or the like, an article having an antistatic film formed by using the same, and a patterning process using the composition.
Description of the Related Art
Conventionally, in a process of producing a semiconductor device such as IC and LSI, microprocessing by a lithography process using a photoresist has been carried out. This is a method of etching a substrate using as a mask a resist pattern that is obtained by a development treatment using a solvent or the like, the development treatment in which light irradiation induces bridging or a decomposition reaction of a thin film to remarkably change the solubility of the thin film. In recent years, with increased integration of a semiconductor device, high-precision microprocessing using light beam with short wavelength has been required. The development of lithography using electron beam has been advanced as a next generation technique since the electron beam has short-wavelength properties.
The lithography using electron beam has a specific problem of electrification phenomenon (charge-up) during exposure. This is a phenomenon in which in a substrate to be irradiated with electron beam that is covered with an insulating resist film, the resist film is charged with electricity by accumulation of charge on or in the resist film. An orbital of incident electron beam is bent by this electrification, and therefore the precision of drawing is significantly reduced. Accordingly, an antistatic film to be applied on an electron beam resist has been investigated.
However, when the antistatic film is formed on a chemically amplified resist, the shape or the sensitivity of the resist may change. For example, when an acid produced by exposure is neutralized by a component in the antistatic film, an exposed area of the resist in a positive type is not dissolved during development, or an exposed area of the resist in a negative type is partially dissolved during development. Alternatively, by an acid component in the antistatic film, a non-exposed area of the resist in the positive type is partially dissolved during development, or a non-exposed area of the resist in the negative type is not dissolved during development. Since the chemically amplified resist does not have resistance to most organic solvent, an aqueous antistatic agent to be formed on the resist is often used. However, since a surface of the chemically amplified resist is hydrophobic, the aqueous antistatic agent is unlikely to be applied. Therefore, it is necessary to add a surfactant, and the like. However, the addition of the surfactant may also adversely affect the resist, for example, on the surface of which a mixing layer is formed.
In order to reduce such adverse effects on the resist, Patent Document 1 discloses a conductive composition for formation of a resist pattern that contains an acidic group-substituted aniline-based conductive polymer (A) and a solvent (B), wherein the content of acid component with a molecular weight of 500 or less is 0.03% by mass or less.
Patent Document 2 discloses a conductive composition containing a water-soluble conductive polymer (a) having a sulfonic acid group and/or a carboxyl group, a water-soluble polymer (b) having a nitrogen-containing functional group and a terminal hydrophobic group as a polymeric surfactant that is unlikely to adversely affect a resist, and a solvent (c).
Patent Document 3 discloses an antistatic agent containing a water-soluble conductive polymer, a solvent, and a water-soluble polymer having a chemical structure represented by —(N(R′)—CH(R)—C(═O))—.

Conductive polymer composition, coated article having antistatic film formed from the composition, and patterning process using the composition


A calibration block and method for sensitivity calibration. The calibration block has a curved calibration surface having a central axis and a surface for coupling to a transducer element of an angular scanning phased array ultrasonic testing scanner. The block is configured such that the surface positions the transducer such that its scanning axis is coaxial with the central axis of the curved calibration surface.

Non-visible areas of materials, such as the interiors of components, welds and composite materials can be analysed using ultrasonic testing. This type of non-destructive testing utilises the reflection of sound waves to detect faults and features which would otherwise be very difficult to detect without destroying the component in the process. Ultrasonic testing is a common technique in the aerospace sector to test the integrity of materials at manufacture and during service.
Phased array ultrasonic testing scanners generally include a transducer having a plurality of transducer elements. The array of transducer elements may be selectively energised to launch a number of individual wave fronts into a test material. The wave fronts constructively and destructively combine within the material, resulting in a primary wave front which travels through the material and reflects off cracks, discontinuities or the like therein. Such cracks, discontinuities and the like will be herein referred to as "target features". The primary wave front can be considered to define a beam. The beam can be dynamically steered across a scanning envelope by firing groups of transducer elements in a particular sequence. The sequence and related parameters (e.g. voltage) are sometimes referred to as a "focal law".
The signal response from primary wave front at a plurality of contiguous beam angles can be combined by the scanner to create a two dimensional "S-Scan" image corresponding to the scanning envelope. This type of scanner is known in the art as "sectorial" or "angular" scanning. The transducer of such a scanner has a central transmission axis and the amount by which the envelope extends from the central axis may be represented in degrees e.g. +50°>−50°, or +70°>+50°, although the envelope may also be expressed with reference to a plane, such as a central plane, or an axis of the test object. When the scanning envelope extends in both the positive and negative directions it is known as a "lateral" scan.
While it may be advantageous to increase the size of the scanning envelope, doing so can be problematic because the magnitude of a primary wave front created by the energised transducer elements may vary across the envelope. Thus, the response signal strength from a target feature at one angle from the central axis may differ to that from an identical target feature at another angle from the central axis. This may result in a loss of signal amplitude from a range of values when visualising signal response, which may relay to a user of the scanner that a target feature at, say, +50° is smaller than a target feature at, say, +20°, when in fact both target features are of the same size and equidistant from the transducer.
Some ultrasonic testing scanners can compensate for the above-mentioned problem by providing sensitivity calibration functionality. One example is the Omniscan MX scanner marketed by Olympus. The sensitivity calibration process generally involves moving the transducer along a "calibration standard" block which is provided with a cross drilled hole and using the signal response from the cross drilled hole to calibrate the control signals to the transducer elements. However, even following such sensitivity calibration, the signal response across a wide scanning envelope may be more irregular than is desirable. Following this, a separate "reference standard" block is scanned using the transducer to set the calibration gain of the ultrasonic testing scanner such that the gain is at an appropriate level to search for a target feature.


A lane controller system installed on a vehicle may include components for self-diagnosing malfunctions on the vehicle. The system may include a desired path generator for generating a desired path that keeps the vehicle within a road lane; a steering controller for providing steering a steering correction to keep the vehicle within the road lane; a vehicle state estimator for estimating the state of the vehicle; a lane marking detector for detecting position of road lane markings; a path predictor for predicting a path actively followed by the vehicle; a virtual dynamics module for modeling the anticipated path of the vehicle following input of the steering controller; a comparer that compares the results of actual steering corrections applied with those predicted by the virtual dynamics module, and a diagnostic system that determines a root cause of malfunctions, based on the comparison by the comparer.

Lane departure warning systems are designed to warn a driver of a vehicle when the vehicle begins to move out of its lane without a turn signal being activated by the driver to indicate that the lane change is intentional. Such lane departure warning systems may be used on freeways and arterial roads and supply a visual, audible, and/or vibration warning if the vehicle is leaving its lane. These departure warning systems may be designed to minimize accidents by addressing the main causes of collisions: driver error, distractions and drowsiness. There are also lane keeping systems that not only warn the driver that the vehicle is straying from the center of its lane, but if no action is taken by the driver, automatically take steps to ensure the vehicle stays in its lane.
Lane centering systems may further assist the driver by maintaining the vehicle's position at the center of a lane. Lane centering systems may be composed of many units, including sensors, computers, actuators, communication modules and other systems and components. Since lane centering systems automatically correct the movement of a vehicle, a driver of the vehicle may not be aware of malfunctions that exist.


The invention relates to a method and a device for the generation of checkable forgery-proof documents with an externally supplied cryptographic module, whereby the checking of authenticity of the document is carried out without using key information belonging to the cryptographic module. According to the invention, the method and the device are characterised in that the cryptographic module is supplied with two types of data, even on supply from a communication partner which is cryptographically not trustworthy, which either remain in the cryptographic module or are attached to the document. The information remaining in the cryptographic module is used to secure the document information by means of a check value and the information transferred into the document serves to verify the securing of the document by the cryptographic module during a check of the authenticity of the document at a checkpoint.

The invention relates to a method for the generation of forgery-proof documents or data records, whereby key information is generated and encrypted checking information is formed from the key information and from a transaction indicator.
The invention also relates to a value transfer center and to a cryptographic module.
Numerous methods are known for generating forgery-proof documents and for checking them. Familiar methods are based on the generation of digital signatures or encrypted checking information, which are produced within the scope of the generation of the document.
A distinction has to be made between documents for which the writer has an interest in their genuineness and those for which third parties have an interest in their genuineness.
If a third party has an interest in documents being forgery-proof, then it is a known procedure to use a so-called "cryptographic module" for generating the document. Such known cryptographic modules are characterized in that they contain electronic data within them or that they process data that cannot be accessed or manipulated from the outside.
A cryptographic module can be regarded as a secure, sealed unit in which security-relevant processes are carried out that cannot be manipulated from the outside. A worldwide recognized standard for such cryptographic modules is the standard for cryptographic modules published under the designation FIPS Pub 140 by the United States National Institute of Standards and Technology—NIST.
If a cryptographic module is used to generate forgery-proof documents for which third parties have an interest in their genuineness, then a customary implementation is that the cryptographic module is used to securely deposit cryptographic keys that serve within the module, and only there, to encrypt check values. For example, so-called signature cards of the type issued by certification agencies or trust centers for generating digital signatures are a familiar approach. These signature cards, in the form of microprocessor chip cards, also contain a cryptographic module precisely in this microprocessor chip.
As a rule, one or more asymmetrical key pairs are deposited in such modules which are characterized in that encryptions that have been generated with the so-called private key can only be reversed with the associated public key, and in that encryptions that have been generated with the public key can only be reversed with the associated private key. As their name indicates, public keys are intended for public disclosure and widespread dissemination, whereas private keys may not be handed out and, when used together with cryptographic modules, they must not leave these modules at any point in time. Also deposited in such modules are algorithms, for example, for forming checksums or, in the example of the digital signature, for generating a so-called digital fingerprint or "hash value" which is characterized in that it maps any desired data contents onto generally quantitatively considerably abbreviated information in such a way that the result is irreversible and unambiguous and in that, for different data contents with which the algorithm is supplied, different results are obtained in each case.
The generation of a forgery-proof document in whose genuineness third parties have an interest, which is done by means of a cryptographic module containing asymmetrical keys and an algorithm to form check values, is generally carried out in the following manner: first of all, using the algorithm to form check values, a check value is formed that relates to the document that is to be secured. Then a private key in the cryptographic module is used to encrypt the check value. The combination of these two processes is referred to as the generation of a "digital signature."
The checking of such a digital signature is normally carried out as follows: the recipient receives the document and the encrypted check value. The recipient also needs—and this is the objective of the invention described below—the public key of the document producer and the recipient uses this public key to decrypt the check value that the document producer has encrypted within the cryptographic module with his private key. Therefore, after the decryption, the recipient has the unencrypted check value. Moreover, in the next step, the recipient applies the same algorithm in order to form a check value for the received document. Finally, in the third step, the recipient compares the check value he himself has generated to the decrypted check value of the document producer. If both check values match, then the document was not forged and the genuineness of the document is substantiated beyond a doubt. Normally, in the case of known digital signatures, the authenticity of the document producer is checked. This is done in that the public key of the document producer is likewise digitally signed by a so-called certification agency or "CA" and it is allocated to a certain cryptographic module, or to a certain owner of the cryptographic module. In this case, the recipient of the document does not simply accept the public key of the document producer as a given but rather he likewise ascertains whether it belongs to the document producer by checking the digital signature of the public key in the manner described above.
With this known method, the problem exists that, in order to check the genuineness of a document, it is necessary to have information that is directly related to the document producer's use of keys by means of the cryptographic module. In the typical example described above for generating digital signatures, this is the public key of the document producer or of his cryptographic module, which has to be used for the checking procedure. In the case of the signature of the public key by a certification agency, the entire set comprising the public key, the identification of the user of this key and the digital signature of the certification agency is designated as the "key certificate."
To sum it up, this problem can be illustrated with reference to an example as follows: in order to check the genuineness of a normally digitally signed document, the public key or the key certificate of the document producer or of his cryptographic module has to be available during the checking procedure. If, as is customary, documents of different document producers are to be checked in a checking station, then it is necessary for all of the public keys or all of the key certificates of all document producers to be available there.
There are various ways to meet the requirement that the public key of the document producer has to be available during the checking procedure. Thus, it is possible to attach the public key or the key certificate of the document producer to the document that is to be secured. Another possibility is to deposit the public key at the checking station and to access it as the need arises.
The known methods, however, are associated with drawbacks.
Attaching the key or the key certificate is disadvantageous if the size of the document has to be kept as small as possible and if an attached key would excessively enlarge the data record that is to be printed, transmitted or processed.
Depositing a public key at the checking station is especially disadvantageous if access to keys deposited at the checking station is not possible for practical or time reasons, for example, in case of a very large number of stored keys which would have to be accessed within a very short period of time.
In order to overcome these known disadvantages, with a method of this generic type, it is disclosed in German patent specification DE 100 20 563 C2 to generate a secret in a security module, to transfer the secret together with information that reveals the identity of the security module in encrypted form to a certification agency, to decrypt the secret in the certification agency, thus recognizing the identity of the security module, to subsequently encrypt the secret together with information on the identity of the document producer in such a way that only a checking station can carry out a decryption, in order to then transmit the secret to a document producer. With this method, the document producer enters his own data into the security module, whereby the data entered by the document producer himself is irreversibly linked to the secret by means of the security module and whereby the secret cannot be reconstructed.
This known method is characterized in that the document that is transmitted to a checking station is formed from the result of the irreversible linking of the secret to the data entered by the document producer, from the data entered by the document producer himself and from the encrypted information of the certification agency.
This known method is especially suitable for generating and checking forgery-proof postage stamps of a postal service provider. Such postage stamps are generated by customers of a postal service provider using a personal cryptographic module and they are applied onto the mail piece as a machine-readable barcode. The machine-readable barcode has only a very limited data scope and consequently, it does not allow the entry of the public key of the customer. Moreover, during the so-called letter production, the digital postage stamps have to be read and checked within a very short period of time, as a result of which the possibility of accessing a database containing perhaps many millions of public keys is likewise not an option.
A method for providing mail pieces with postage indicia is known from German Preliminary Published Application DE 100 20 402 A1. With this method, information that serves to generate a postage indicia is transmitted in encrypted form from a loading station to a crypto-module of a customer system and then serves to generate digital postage indicia. The postage indicia contains a hash value that is formed from the mailing data and from the information that was transmitted and stored temporarily in the crypto-module and also contains a "Crypto-String" encrypted in this information that can only be decrypted in a mail center during the checking of the postage indicia, after which it is provided with a digital signature.
German Preliminary Published Application DE 100 20 566 A1 describes a method of the same type in which customers can load value amounts from a value transfer center and said value amounts can be consumed in order to print out digital postage indicia. Here, in particular, a customer system transmits a random number to the value transfer center and the latter encrypts the random number with a symmetrical key and sends it back to the customer system.
The postage indicia are generated in the same manner as described in German Preliminary Published Application DE 100 20 402, whereby in particular, the encrypted random number can only be decrypted in a mail center.
The invention is based on the objective of allowing the generation of forgery-proof documents in such a way that it can be carried out, independent of direct communication between the cryptographically reliable contact station and the document producer.

Method and device for the generation of checkable forgery-proof documents


The invention relates to a set of doors for closing off a bay (6) in a wall (4), comprising a first flexible door (1) and a second door (2) having at least a rigid bottom edge (17), it being possible to impart an upward movement and a downward movement to each of these doors (1, 2) respectively into an open position and a closed position, the second door (2) being disposed so as to create a slit (31) between the wall (4) and the rigid bottom edge (17) of this second door (2) as it is moved upwards into the open position. The flexible door (1) is disposed at least partially between said second door (2) and said wall (4) and can be displaced through said slit (31) between its closed position and its open position when the second door (2) is in the open position.

Currently known sets of doors are of a relatively cumbersome and complex construction. Furthermore, these known sets of doors do not enable a sealed closure to be obtained when the flexible door is in the closed position and said second door is in the open position. In particular, spaces are left, through which insects, an air flow or dust are able to penetrate the enclosure closed off by this set of doors. In practice, it is relatively complicated to make a set of doors which provides satisfactory sealing.
Document U.S. Pat. No. 2,501,454 describes a set of two doors, each of which is wound on a drum to enable them to be opened. An attempt has been made to provide a seal between the wall and the set of these doors by mounting a housing above the bay in which said drums are enclosed. Naturally, mounting such a housing is relatively complex and it is not possible to use such a housing if one of these doors is not wound on a drum. This might be the case, for example, if the second door is a rigid door or a sectional door.


A driven catheter system (2) includes broadly a driven catheter assembly (6) coupled to a control unit (4). The driven catheter assembly includes a motor drive unit (8) and a catheter assembly (10) mounted thereto. The catheter assembly includes a rotational and translational drive coupling (26) and a catheter (14) extending therefrom. The catheter includes a sheath (16) and a core (18) slidably housed within the sheath. The drive coupling includes an elongate rotary drive element (36), defining a first longitudinal drive path, mounted for rotation about a longitudinal axis (42). A termination element (44) is mounted to the proximal end of the core and slides along the first longitudinal drive path but rotates with the rotary drive element. A bearing (46) has an inner race (48) secured to the termination member and an outer race (50) coupled to the longitudinal drive element (54, 62) of a longitudinal driver (56). Rotation of the rotary drive element rotates the termination element and the proximal end of the core therewith about the longitudinal axis. Longitudinal movement of the longitudinal drive element translates the bearing parallel to the longitudinal drive path; this causes the termination element and the proximal end of the core therewith to be translated along the first longitudinal drive path, the translational and rotational movements being independent of one another.

The present invention relates generally to catheters systems. In particular, the present invention is directed to a drive coupling for a catheter assembly that provides for the controlled longitudinal movement of an elongate elementxe2x80x94such as a rotatable catheter core with an operative element, for example an ultrasonic transducer or an optical fiber imaging device, at its distal end, or a drive cable with an arthrectomy cutter at its distal endxe2x80x94housed within a sheath positioned within a patient.
Arteriosclerosis, also known as atherosclerosis, is a common human ailment arising from the deposition of fatty-like substances, referred to as atheromas or plaque, on the walls of blood vessels. Such deposits occur in both peripheral blood vessels which feed the limbs of the body and the coronary vessels which feed the heart. When the deposits accumulate in localized regions of a blood vessel, stenosis, or narrowing of the vascular channel, occurs. Blood flow is restricted and the person""s health is at serious risk.
Numerous approaches for reducing and removing such vascular deposits have been proposed, including balloon angioplasty where a balloon-tipped catheter is used to dilate a region of atheroma, and other devices that are pushed or pulled along or through a deposit, such as arthrectomy where a blade or cutting bit is used to sever and remove the atheroma, spark gap reduction in which an electrical spark burns through the plaque, laser angioplasty where laser energy is used to ablate at least a portion of the atheroma, and opening of vessels through the use of stents.
Two major difficulties in using such devices are maintaining a constant translational rate for the device and obtaining images of and information on the region of the blood vessel to be treated. Several imaging techniques have been proposed. Catheters incorporating mechanical rotation of ultrasonic transducers for imaging are disclosed in U.S. Pat. Nos. 4,794,931; 5,000,185; 5,049,130; and 5,024,234. These catheters scan in a plane normal to the catheter axis. Catheters employing phased array imaging systems are disclosed in U.S. Pat. Nos. 4,841,977 and 4,917,097. Catheters employing fiber optic imaging components are also known.
Generally deposits extend some longitudinal distance along the length of a vessel. To view different portions of the deposit a physician typically moves a handle attached to a proximal end of the imaging catheter along the vessel, for example, by pushing or pulling the catheter.
Imaging using computer-assisted reconstruction algorithms enables physicians to view a representation of the patient""s interior intravascular structures in two or three dimensions (i.e., so-called three-dimensional or longitudinal view reconstruction). In this connection, image reconstruction algorithms typically employ data-averaging techniques which assume that the intravascular structure between an adjacent pair of data samples will simply be an average of each such data sample. Thus, the algorithms use graphical xe2x80x9cfill inxe2x80x9d techniques to depict a selected section of a patient""s vascular system under investigation. Of course, if data samples are not sufficiently closely spaced, then lesions and/or other vessel abnormalities may in fact remain undetected (i.e., since they might lie between a pair of data samples and thereby be xe2x80x9cmaskedxe2x80x9d by the image reconstruction algorithms mentioned previously).
Even with the most skilled physician, it is practically impossible to manually exercise sufficiently slow constant rate longitudinal translation of the ultrasound imaging device (which thereby provides for a precisely known separation distance between adjacent data samples). In addition, with manual translation, the physician must manipulate the translation device while observing the conventional two-dimensional sectional images. This division of the physician""s attention and difficulty in providing a sufficiently slow constant translation rate can result in some diagnostic information being missed. To minimize the risk that diagnostic information is missed, it is necessary to lengthen the imaging scan time which may be stressful to the patient. Similarly, it is difficult for physicians to manually control the translational rate of arthrectomy catheters and other interventional devices that are longitudinally advanced and retracted through blood vessel and other body lumens.
U.S. Pat. No. 5,485,486 discloses an ultrasound imaging transducer which is capable of being translated longitudinally within a section of a patient""s vascular system at a precise constant rate through the use of a longitudinal translation assembly. The longitudinal translation assembly moves the entire rotary drive assembly to provide the desired longitudinal movement of the transducer. Such an ability enables a series of precisely separated data samples to be obtained thereby minimizing (if not eliminating) distorted and/or inaccurate reconstructions of the ultrasonically scanned vessel section (i.e., since a greater number of more closely spaced data samples can reliably be obtained). Also, such an assembly can be operated in a xe2x80x9chands-offxe2x80x9d manner which allows the physician to devote his or her attention entirely to the real-time images with the assurance that all sections of the vessel are displayed. While such a longitudinal translation assembly can work well, it is relatively large, bulky and heavy; it is expensive; and it is cumbersome to set up, in part because the rotary drive and longitudinal translation assemblies are wrapped in separate sterile drapes or barriers (plastic bags) for sterility.
One of the disadvantages with some conventional pullback systems is separate modules are used to provide the rotational and translational movement. These modules require the use of sterile barriers about each. Also, some prior art pullback systems lack the capability to permit the user to manually translate the catheter core to preposition the operative element along the distal end of the catheter core.
The present invention is directed to a driven catheter system including rotational and translational drive coupling as part of a catheter assembly. The invention eliminates the need for a sled as is used with many conventional catheter pullback units. User set up is greatly simplified with the invention. The catheter assembly is typically a disposable unit and is thus supplied to the user in a sterile condition so only a single sterile drape about a motor drive unit is needed.
The driven catheter system includes broadly a driven catheter assembly coupled to a control unit. The driven catheter assembly includes the motor drive unit and the catheter assembly mounted thereto. The catheter assembly includes a catheter extending from the rotational and translational drive coupling. The catheter includes a sheath and a core slidably housed within the sheath, the proximal end of the sheath being mounted to the housing of the drive coupling. The drive coupling includes an elongate rotary drive element, defining a first longitudinal drive path, mounted to the housing for rotation about a longitudinal axis. A termination element couples the proximal end of the core to the rotary drive element for longitudinal movement along the first longitudinal drive path. The termination element is also mounted to the rotary drive element for of the termination element and the core therewith by the rotary drive element. A bearing has a first part coupled to the termination member. The bearing also has a second part, the first and second parts being freely rotatable relative to one another. A longitudinal driver is mounted to the housing and has a longitudinal drive element coupled to the second part of the bearing. The longitudinal drive element is movable along a second longitudinal drive path. Accordingly, rotation of the rotary drive element rotates the termination element and the proximal end of the core therewith about the longitudinal axis. Longitudinal movement of the longitudinal drive element translates the bearing parallel to the longitudinal drive path; this causes the termination element and the proximal end of the core therewith to be translated along the first longitudinal drive path.
The rotary drive element preferably has a hollow interior which defines the first longitudinal drive path. A slot, opening into the hollow interior, can be provided to be oriented parallel to the longitudinal drive path. The first part of the bearing, typically the inner race of the bearing, is preferably connected to the termination member through the slot. The longitudinal drive element could be provided by a number of different drive structures, such as a continuous belt, a lead screw or worm drive. In a preferred embodiment a continuous loop drive belt is used. The drive belt is driven through a drive pulley. The drive pulley is preferably driven through a pair of bevel gears. A flexible data/signal line, in the preferred embodiment, extends between the termination element at the proximal end of the core and a data/signal terminal carried by the housing of the drive coupling. The data/signal terminal may be a separate terminal but is preferably part of a dual data/signal-rotary drive connector. The dual connector provides the necessary data/signal connection and also the rotary drive connection for the rotary drive element.
The motor drive unit includes first and second rotary drive outputs which are coupled to the elongate rotary drive element and the longitudinal driver, respectively. The motor drive unit preferably includes first and second drive trains each having driving and driven ends. The driving ends terminate at the first and second rotary drive outputs. The second drive train couples the second rotary drive outputs with a drive source, typically an electric motor. A clutch-type element and a movement indicator, such as an optical encoder, may be used along the second drive train. The optical encoder is preferably positioned between the clutch type element and the second rotary drive output. Provision of the clutch-type element permits a user to physically disengage the longitudinal driver from the drive source so that the termination element and the core therewith can be manually translated within the sheath without the drag which would otherwise be created by the drive source. The preferred position of the movement indicator ensures that the longitudinal position of the core is continuously updated even when the core is being manually translated.
Other features and advantages of the present invention will appear from the following description in which the preferred embodiment has been set forth in detail in conjunction with the accompanying drawings.

Rotational and translational drive coupling for catheter assembly