A system may include a reactor vessel comprising an outer wall, a heat source thermally coupled to the reactor vessel, at least one reactor inlet in the outer wall, and at least one reactor outlet. The reactor vessel may be configured to house a porous preform in a radially central core region. The at least one reactor inlet may be configured to introduce a precursor gas to the reactor vessel to produce swirling flow of the precursor gas around the radially central core region of the reactor vessel. The at least one reactor outlet may be configured to remove exhaust gas from the reactor vessel and assist in maintaining a dynamic pressure of the reactor vessel greater than a pressure in the porous preform.

Chemical vapor infiltration (CVI), a form of chemical vapor deposition, may be used to deposit ceramic matrix materials for ceramic matrix composites (CMCs). CMCs include ceramic fibers embedded in a ceramic matrix. CMCs may have excellent mechanical, physical, and chemical properties such as high fracture toughness, thermal shock resistance, and elongation resistance. CMCs may be used for a variety of applications such as gas turbine engines, brake discs, and the like.
An example CMC is silicon carbide-fiber reinforced silicon carbide (SiC/SiC) composite.

Rolls-Royce High Temperature Composites, Inc.


Method for the manufacture of mixed packages and device for carrying out said method. The abstract of the disclosure is submitted herewith as required by 37 C.F.R. §1.72(b). As stated in 37 C.F.R. §1.72(b): A brief abstract of the technical disclosure in the specification must commence on a separate sheet, preferably following the claims, under the heading “Abstract of the Disclosure.” The purpose of the abstract is to enable the Patent and Trademark Office and the public generally to determine quickly from a cursory inspection the nature and gist of the technical disclosure. The abstract shall not be used for interpreting the scope of the claims. Therefore, any statements made relating to the abstract are not intended to limit the claims in any manner and should not be interpreted as limiting the claims in any manner.

1. Technical Field
This application relates to a method for the manufacture of mixed packages and device for carrying out the method.
2. Background Information
Containers or packaging units, such as, for example, bottles, cartons or other packaging formats etc. filled with a product may be packed in external packages such as, for example, cartons, trays, beverage cases etc. and the marketing of the products in this form.
The containers in a package of this type generally all contain one and the same product, which can be, for example, a beverage of a certain type or variety (for example exclusively juice or soft drinks or beer etc.) and/or of one and the same flavor. Packages that are made up of containers or other packaging units that contain one and the same product are designated "single-variety packages" below.
The retail trade and/or the final consumer often demand packages that contain more than one variety and are referred to as "mixed packages" below, in which case they contain, in their external packaging, packaging units or containers that contain different products, such as, for example, containers with beverages (e.g. soft drinks) of different varieties and/or different flavors (e.g. cola beverages and fruit-flavored soft drinks etc.).
Mixed packages of this type can also include, for example, trays that hold animal food packaged in cans, in which case the tray in question can contain cans of different flavors.
A device of this type was described in DE 10 2004 062 958.7. This application related to a device in which containers are taken from single-variety packages and are then assembled into mixed packages with additional containers of other varieties to form packages that contain more than one variety.
The specific focus of DE 10 2004 062 958 is the description of a device for the unpacking of single-variety packages.
In the framework of that application, the function of the assembling of different varieties or mixing of the containers of different varieties is described only in general terms and with a different emphasis, which is to show that the assembling of the containers with different varieties could be done, for example, by means of a controlled pick/place or gripper arrangement.

Method for the manufacture of mixed packages and device for carrying out the method


A method and system in a data processing system of permitting concurrent processing of multiple conditional branch instructions are disclosed. A condition register is established within the processing system. First and second conditional branch instructions are dispatched during a single cycle of the processing system. Prior to speculatively executing the first conditional branch instruction, a first copy of the condition register is stored. Prior to speculatively executing the second conditional branch instruction, a second copy of the condition register is stored. Multiple copies of the condition register are concurrently maintained so that the first and second conditional branch instructions may be concurrently processed during a single cycle of the processing system.

1. Technical Field
The depicted illustrative embodiment relates to superscalar data processing systems, and in particular to concurrent processing of a particular type of instructions in a superscalar data processing system. Still more particularly, the depicted illustrative embodiment relates to establishing an array within which multiple statuses of a plurality physical registers are stored during a single clock cycle permitting concurrent processing of a plurality of instructions of a particular type.
2. Description of the Related Art
A superscalar data processing system is a data processing system which includes a microprocessor architecture which is capable of executing multiple instructions per clock cycle. In order to execute multiple instructions per clock cycle, multiple independent functional units that can execute concurrently are required.
The overlap of the fetching and decoding of one instruction with the execution of a second instruction is called pipelining. In pipelined superscalar data processing systems, care must be taken to avoid dependencies where multiple instructions are fetched, decoded, and executed in a single cycle.
There are three types of data dependencies. A read after write hazard occurs when an instruction tries to read a source before a previous instruction writes the source. A write after read hazard occurs when an instruction tries to write a destination before a previous instruction reads it. A write after write hazard occurs when an instruction writes a destination before a previous instruction writes it.
One solution to solving the dependence problem is to rename the logical registers associated with the instructions. By renaming the logical registers, each instruction within the cycle can be executed concurrently and correctly. A problem arises, however, when an instruction is a conditional branch instruction. Register renaming is a mechanism for dealing with these dependencies in a processor which executes instructions out-of-order. The target register associated with each instruction is renamed to a unique physical register. Thereby, the instructions may execute properly concurrently, and out-of-order.
A condition branch instruction is an instruction which specifies a conditional branch and the conditions that have to be satisfied for the conditional branch to occur. In order to speed execution of instructions, for each conditional branch, a prediction is made regarding whether the conditions will occur which will cause the branch. This prediction is made during the cycle during which the conditional branch is decoded, and prior to completing the execution of each conditional branch. In the event a conditional branch is predicted incorrectly, the state of all registers affected by the conditional branch must be restored to their states which existed just prior to encountering the conditional branch. Upon completion of execution of the instruction, if the branch instruction was correctly predicted, the stored register values are discarded.
Therefore a need exists for a method and system in a superscalar data processing system to permit concurrent processing of a plurality of instructions of a particular type within a single clock cycle.

Method and system in data processing system of permitting concurrent processing of instructions of a particular type

International Business Machines Corporation


A sensor device having small variations in sensor characteristics and improved resistance to electrical noise is provided. This sensor device has a sensor unit, which is provided with a frame having an opening, a movable portion held in the opening to be movable relative to the frame, and a detecting portion for outputting an electric signal according to a positional displacement of the movable portion, and a package substrate made of a semiconductor material, and bonded to a surface of the sensor unit. The package substrate has an electrical insulating film on a surface facing the sensor unit. The package substrate is bonded to the sensor unit by forming a direct bonding between an activated surface of the electrical insulating film and an activated surface of the sensor unit at room temperature.

In recent years, a method for producing compact sensor devices such as an acceleration sensor and a gyro sensor by using a micromachining technique has attracted lots of attention.
For example, Japanese Patent Early Publication No. 2005-292117 discloses a gyro sensor comprising a sensor unit formed by use of a silicon substrate, and first and second package substrates each formed by use of a glass substrate. In the sensor unit, a part of a sensing portion is formed on a movable portion, which is disposed inside of a frame portion. The first package substrate has a through-hole wiring electrically connected to the sensing portion. The first package substrate is bonded to a surface of the sensor unit over the entire circumference of the frame portion. The second package substrate is bonded to the other surface of the sensor unit over the entire circumference of the frame portion.
In this gyro sensor, however, since the sensor unit is bonded to the package substrates by means of anodic bonding, there is a problem that variations in sensor characteristics increase due to the influence of thermal stress resulting from a difference in linear expansion coefficient between silicon and glass. In addition, even when the package substrate is formed by use of the same silicon substrate as the sensor unit, the variations in sensor characteristics may occur due to the residual stress at a bonding portion formed by a high temperature bonding process such as reflow soldering.
Additionally, in a sensor device such as the gyro sensor described above where a part of the sensor unit is utilized as an electrode such as a movable electrode and a stationary electrode, a silicon substrate having a relatively smaller resistivity than the silicon substrate suitable for the formation of integrated circuits is used as the silicon substrate for the sensor unit. Thereby, the impedance component of the electrode can be reduced to achieve high performance. However, since the package substrate and the sensor unit easily work as an exogenous noise transmission channel, the noise component may be overlapped with output signals of the sensing portion. In this case, a reduction in resistance to electrical noise comes into problem.

Sensor device and production method therefor


A pressure regulating valve usable in combination with a hydraulic steering system has a spring mechanism axially disposed between a pair of axially aligned valve spools. Movement of the spring mechanism in a first direction resiliently moves one of the valve spools to a position for communicating an inlet port with a control port and regulating the pressure in the the control port so that the pressure is proportional to the degree of movement of the spring mechanism. Conversely, movement of the spring mechanism in a second direction resiliently moves the other valve spool to a position for communicating the inlet port with another control port and regulating the pressure in the other control port so that the pressure is proportional to the degree of movement of the spring mechanism.

U.S. Pat. No. 4,955,442 illustrates a steering mechanism for converting the rotational movement of a steering wheel to linear actuation of one or the other of a pair of pressure regulating valves connected to the main hydraulic steering control. That mechanism includes an input shaft and a single actuating cam which are co-jointly rotatable away from a neutral position in either direction. A cam follower assembly is cooperatively associated with a substantially spiral shaped cam slot defined in the actuating cam and includes a cam following roller wheel received in a guide slot. The cam follower assembly also includes a bell crank supporting the roller wheel and indirectly connected to the pilot valves so that rotating the input shaft in opposite directions imparts controlled displacement of the pressure regulating valves through a separate spring in each control valve.
One of the problems encountered therewith is that the spring tolerances of the valves must be tightly controlled to provide equal control pressures at the control port of each valve relative to a steering input so that rotating the steering wheel equally in opposite directions from the straight ahead position results in the same degree of left or right steering. Moreover, the preload on the springs must be precisely matched to insure that the initial ramp-up control pressures for left and right turns are equal so that steering commences at the same degree of steering wheel rotation from the straight ahead position. The term ramp-up control pressure commonly refers to the minimum regulated control pressure setting of a pressure regulating or pressure control valve and is a function of the spring preload.
Thus, it would be desirable to have a pressure regulating valve for use in a steering system for providing substantially equal ramp-up control pressures and substantially equal rates of pressure rise of the regulated control pressures in both directions of operation.


An SRAM is provided wherein each memory cell has first and second storage nodes to be maintained at complementary potentials corresponding to storage data and first and second inverters provided in anti-parallel between the first storage node and the second storage node. Also, a DRAM is provided wherein each memory cell has a single storage node to be maintained at a potential corresponding to storage data and a capacitor provided between the storage node and a low potential source. In each of predetermined memory cells in which storage data is to be initialized, an MOS transistor, which is controlled to turn on for a fixed time period at the time of power supply, is connected between a potential source capable of supplying a potential corresponding to the initialization data and at least one of the first and the second storage nodes (in the case of the SRAM) or between the potential source and the single storage nodes (in the case of the DRAM). In the case of the SRAM, the first or the second inverter in each of the predetermined memory cells is replaced by a two-input NAND gate or a two-input NOR gate for which the output potential at the time of the power supply is controlled to correspond to the initialization data irrespective of the potential at the first (or the second) storage node.

1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to semiconductor memory devices having a function of initializing storage data of memory cells.
2. Description of the Background Art
At present, semiconductor memory devices such as RAMs (Random Access Memories) are incorporated into a single chip for use in various semiconductor integrated circuits or in various fields as units. Memory arrays of some of such semiconductor memory devices must be set to a predetermined storage data pattern (initialized) depending on their usages when a power is applied (at the start of the use) in an actual use. One example of such semiconductor memory devices is a cache memory or a matching memory. A cache memory is a memory operating at a very high speed for use in transferring and storing storage data of a main memory device. A matching memory includes memory storing identifiers which perform various data processing according to these identifiers in a computer system such as a data flow processor requiring the same. In a semiconductor memory device requiring such "initialization of data", the storage data of all the memory cells or part of the memory cells (for example in a case of a cache memory, memory cells of addresses storing identifiers) in a memory array is set to a logical value "1" or a logical value "0" in this initialization.
FIG. 14 is a schematic block diagram showing one example of an entire arrangement of a conventional SRAM (Static Random Access Memory) having a function of performing such initialization. Referring to FIG. 14, the SRAM includes a memory array 1b of a plurality of blocks each having memory cells for storing input data arranged in a matrix of rows and columns, a data input/output terminal T.sub.D for receiving input data and output data, a row address input terminal Ar for receiving an external row address signal which selects a row of a block in memory array 1b, a column address input terminal Ac for receiving an external column address signal which selects a column of a block in memory array 1b and a block address input terminal 1b for receiving an external block address selecting signal which selects a block in memory array 1b.
FIG. 15 is a circuit diagram showing an internal arrangement of memory array 1b. FIG. 9 shows a representation of memory cell columns in an arbitrary block.
Referring to FIG. 15, a memory cell MC is connected between two paired bit lines BIT and BIT.
The memory cell MC includes two inverters INV1 and INV2 connected in anti-parallel, an N channel MOS transistor TR1 connected between the input end of inverter INV2 and the bit line BIT and an N channel MOS transistor TR2 connected between the input terminal of inverter INV1 and the other bit line BIT. Both of the gates of transistors TR1 and TR2 are connected to the same word line WL. The word line WL is connected to a row decoder 3 and the paired bit lines BIT and BIT are connected to a I/O circuit 6 in FIG. 14.
I/O circuit 6 forms a path for transferring the data read from memory array 1b to an output buffer 9 and a path for transferring the data to be written in memory array 1b from an input data control circuit 10 to memory array 1b. The former path includes a sense amplifier for amplifying data read from memory array 1b.
In data writing, row address buffer 2 accepts a row address signal applied to row address input terminal Ar.
Then, row decoder 3 decodes the row address signal accepted by row address buffer 2 to selectively render data writable/readable in the memory cells in one row corresponding to the row address designated by the row address signal.
That is, row decoder 3 applies a "H" (logical high) level voltage to the word line WL (see FIG. 15) corresponding to the row of the memory cells designated by the row address signal. As a result, transistors TR1 and TR2 are turned on in all the memory cells connected to the word line WL for attaining the "H" level, and thereby electrically connecting all the memory cells to the corresponding bit line pairs of BIT and BIT.
At the same time, a block address signal applied to block address input terminal 1b is accepted by a block address buffer 7. Then, a block decoder 8 decodes the block address signal accepted by block address buffer 7 to select all the bit line pairs corresponding to one block designated by the accepted block address signal in I/O circuit 6. That is, block decoder 8 selects one block from among the blocks in memory array 1a.
Similarly, a column address signal applied to column address input terminal Ac is accepted by a column address buffer 4. Then, a column decoder 5 decodes the column address signal accepted by column address buffer 4 to selectively enable only the data transmission to the memory cells of one column corresponding to the column address designated by the column address signal out of the memory cells in the block selected by block decoder 8. In other words, column decoder 5 electrically connects only the bit line pair corresponding to the column designated by the column address signal with input data control circuit 10 in I/O circuit 6 out of the bit line pairs of BIT and BIT in the selected block connected to I/O circuit 6. That is, column decoder 5 selects one pair from among the bit line pairs in memory array 1b.
Meanwhile, an input buffer 11 accepts each bit signal of the data applied to data input/output terminal T.sub.D and applies the same to input data control circuit 10 in the data writing. In ordinary data writing other than data writing for "initialization", input data control circuit 10 applies the data applied from input buffer 11 to I/O circuit 6. In I/O circuit 6, however, input data control circuit 10 is electrically connected to only the bit line pair corresponding to the memory cell column selected by column decoder 5 as described above. Then, I/O circuit 6 applies the data supplied from input data control circuit 10 as signals of complementary level voltages to the bit line pair of BIT and BIT of FIG. 15, respectively. More specifically, all the transistors TR1 and TR2 are turned on in memory array 1b, and each of the transistors has a gate connected to one word line (selected word line) WL supplied with a "H" level potential by row decoder 3.
In addition, I/O circuit 6 applies a potential of a logical value corresponding to the data applied from input data control circuit 10 and an inversion potential thereof to two bit lines BIT and BIT constituting the bit line pair selected by column decoder 5, respectively. As a result, the potential applied to the corresponding bit line BIT is supplied to inverter INV1 through transistor TR2 in the memory cell arranged at the cross-over point between the column selected by column decoder 5 and the row selected by row decoder 3, with reference to FIG. 15. Inverter INV1 inverts that potential and outputs the inverted potential to inverter INV2. Inverter INV2 is supplied with a potential of an opposite level to the input potential of inverter INV from the other bit line BIT through transistor TR1. In this memory cell, therefore, the nodes between inverters INV1 and INV2 are fixed to the potential applied to bit line BIT and corresponding to the inverse logical value to the input data and the potential applied to bit line BIT and corresponding to the input data. That is, the input data is written in this memory cell.
Thereafter, row decoder 3 lowers the potential on the word line WL corresponding to this memory cell to a "L" level. As a result, the transistors TR1 and TR2 are turned off in all the memory cells connected to the selected word line WL including this memory cell. However, the respective outputs of inverters INV1 and INV2 are fed back to their inputs, so that the potentials at the nodes between inverters INV1 and INV2 are maintained at the level in the data writing. That is, the written data is stored in this memory cell. A node to be maintained at a potential corresponding to data such as the node between inverters INV1 and INV2 is referred to as storage data hereinafter.
The data input from data input/output terminal T.sub.D is written and stored in this way in the memory cell arranged at the cross-over point between the column designated by the column address signal and the row designated by the row address signal in the block designated by the block address signal out of the blocks in memory array 1b.
FIG. 16 is a circuit diagram showing in more detail the respective arrangements of a memory cell included in memory array 1b shown in FIG. 14. Referring to FIG. 16, each memory cell MC in memory array 1b includes the above-described transistors TR1 and TR2, two P channel MOS transistors 210 and 220 and two N channel MOS transistors 230 and 240. Transistors 210 and 230 are connected in series between a power supply Vcc and ground GND to constitute inverter INV1. A node n1 between transistors 210 and 230 is the output end of this inverter INV1. Transistors 220 and 240 are also connected in series between power supply Vcc and ground GND to constitute inverter INV2. A node n2 between transistors 220 and 240 is the output end of this inverter INV2. The gate of transistor 210 and the gate of transistor 230 are connected to each other. The gate connection point between transistors 210 and 230 is connected to an output end n2 of inverter INV2 as the input end of inverter INV1. The gate of transistor 220 and the gate of transistor 240 are also connected to each other. The gate connection point between transistors 220 and 240 is connected to output end n1 of inverter INV1 as the input end of inverter INV2.
In data reading, row address buffer 2 and row decoder 3, column address buffer 4 and column decoder 5, and block address buffer 7 and block decoder 8 operate similarly to those in the data writing, for thereby rendering data writable/readable only the memory cell selected by the block address signal, the column address signal and row address signal out of the memory cells in memory array 1b.
In other words, referring to FIG. 15, the transistors TR1 and TR2 are turned on and the corresponding bit line pair of BIT and BIT is electrically connected to output buffer 9 through I/O circuit 6, in one memory cell corresponding to the word line WL supplied with a "H" level potential by row decoder 3 and corresponding to the bit line pair selected by column decoder 5 in the block selected by block decoder 8. Upon the turning-on of transistors TR1 and TR2, the potentials on the corresponding bit line pair of BIT and BIT change in response to the potentials at the connection points, that is, the storage nodes, between inverters INV1 and INV2. In other words, the storage data of the selected memory cell is read onto the corresponding bit line pair. The potential change of this bit line pair of BIT and BIT is sensed/ amplified by a sense amplifier in I/O circuit 6, and converted to the potential corresponding to the storage data and then applied to output buffer 9. Output buffer 9 outputs the potential corresponding to this storage data as the read data to data input/output terminal T.sub.D.
In actuality, a chip and input/output control circuit 13 controls an operation timing of row address buffer 2, column address buffer 4, block address buffer 7, output buffer 9 and input buffer 11 such that the SRAM operates in data writing and reading in such a manner as described above.
This control circuit 13 carries out this controlling based on a chip enable signal externally applied to a chip enable terminal CE, a write enable signal externally applied to a write enable terminal WE and an output enable signal externally applied to an output enable terminal OE. The chip enable signals is for selecting a chip to be operated at present in the device containing this SRAM chip and the signal attains a "L" level when this SRAM chip should be operated. A write enable signal is for indicating whether this memory cell should be set at a data writing mode at present or not and attains a "L" level when this SRAM is set at the data writing mode. An output enable signal is for indicating whether or not the read data should be output from this SRAM at present and the signal attains a "L" level when the read data should be output.
Control circuit 13 activates the operations of row address buffer 2, column address buffer 4 and block address buffer 7 in a period when this SRAM chip should be operated, and the period when a chip enable signal is at a "L" level. Control circuit 13 activates input buffer 11 in a period in which data should be written in this memory, and the period when a write enable signal is at a "L" level, such that the data applied to input/output terminal T.sub.D is taken into the SRAM. Control circuit 13 activates output buffer 9 such that the read data from memory array 1b is externally output in a period when the read data should be output, and the period when an output enable signal is at a "L" level.
The foregoing operation of this SRAM is the same as that of an ordinary SRAM without an initialization function.
This SRAM shown in FIG. 14, however, includes an initialization data control circuit 12, a clock generation circuit 14 and an initialization address generating circuit 15 in addition to the function part provided in such an ordinary SRAM as described above.
Initialization address generating circuit 15 generates a block address signal, a row address signal and a column address signal indicative of a block address, a row address and a column address, respectively, corresponding to the address of a predetermined memory cell to be initialized and applies the same to block decoder 8, column decoder 5 and row decoder 3, respectively.
Initialization data control circuit 12 generates predetermined data (initialization data) to be applied to the memory cell to be initialized at initialization and applies the same to input data control circuit 10.
Clock generation circuit 14 generates clock signals for controlling initialization address generation circuit to generate a block address signal, a row address signal and a column address signal and for controlling initialization data control circuit 12, to generate initialization data, based on control signals (initialization signals) for initialization externally applied to an initialization signal input terminal T.sub.1.
An initialization signal is applied to initialization signal input terminal T.sub.1 at the application of power. Clock generation circuit 14 generates the above-described clock signal in response to this initialization signal. Then, initialization data control circuit 12 and initialization address generation circuit 15 operate as described above in response to this clock signal. In such initialization, input buffer 11 which accepts external input data, is still disabled by control circuit 13, whereby input data control circuit 10 receives none of ordinary data to be written as an input but applies the data supplied from initialization data control circuit 12 as data to be written to I/O circuit 6. Similarly, at this time, row address buffer 2, column address buffer 4 and block address buffer 7 are still disabled by column circuit 13 at this time, whereby row decoder 3, column decoder 5 and block decoder 8 receive none of the external input address signals. At the initialization, therefore, row decoder 3, column decoder 5 and block decoder 8 receive only the row address signal, column address signal and block address signal applied from initialization address generation circuit 15, respectively, and decode the same. In this case therefore, memory cells to be initialized are sequentially selected on an address basis in memory array 1b, so that the initialization data generated by generation data control circuit 12 is written thereto.
Initialization data control circuit 12 and initialization address generation circuit 15 may directly receive necessary clocks as inputs.
As described in the foregoing, in this semiconductor memory device the storage data of a predetermined memory cell is initialized by a circuit for initialization additionally provided in the device, that is, by means of the hardware, at the power on. The circuit for initialization, that is, initialization data control circuit 12, clock generation circuit 14 and initialization address generation circuit 15 is incorporated in this semiconductor memory device beforehand. Thus, the address signal generated from the initialization is uniform, making it impossible to initialize memory cells of different addresses at each initialization and to initialize the data of memory cells to different data at each initialization. Therefore, initialization is not performed by means of hardware but initialization is generally carried out by software for such irregular initialization as this.
Initialization by software performs initialization by using software such as a program in the system including a semiconductor memory device for example. More specifically, the system, supplied with a program for initialization to generate addresses and data, generates by itself the addresses to be initialized and initialization data outside the semiconductor memory device and applies the same to the semiconductor memory device by executing the program. Then, the semiconductor memory device operates similarly to that in ordinary data writing to write the generated data in the generated addresses. Such initialization requires none of such circuits for initialization in the semiconductor memory device as described previously. That is, the semiconductor memory device performs an operation of writing given data in given addresses both in data writing for initialization and in ordinary data writing. In this case, of course a mode setting instruction for setting the semiconductor memory device to operate in a writing mode, when write addresses and write data to be applied to the semiconductor memory device for initialization should be written in the program or the like.
In the initialization by hardware, when the data bit to be initialized is fixed irrespective of address and the addresses of the memory cell which storage data should be initialized are regular such as all the addresses, all the even-numbered addresses, all the odd-numbered addresses and the serial addresses from address 0 to a predetermined address in the memory array and the initialization data to be written is also regular data that it is the same for each address, initialization data control circuit 12, clock generation circuit 14 and initialization address generation circuit 15 of FIG. 14 can be achieved by circuits of relatively simple structure. However, if the data bit to be initialized, the address to be initialized and the initialization data to be written and the like are irregular, these circuits for initialization are made complicated. For example, initialization address generation circuit 15 is a circuit for generating an address signal by counting clocks from clock generation circuit 14 which includes a counter for carrying out this counting. If the address to be generated is irregular, complicated control is required of the counting operation of this counter. Thus, a complicated address to be initialized results in a complicated arrangement of initialization address generation circuit 15. As a result, execution of the complication initialization requires an increased circuit for initialization in scale, for thereby making it impossible to provide these circuits in the semiconductor memory device. In such a case, these circuit portions should be structured separately from the semiconductor memory device. For this reason, complicated initialization is generally performed by software as described above.
As shown in the foregoing, initialization of storage data of a semiconductor memory device conventionally includes that by means of hardware and that by software.
In the former case, a time period required for initialization depends on a time required for the circuits for initialization (initialization data control circuit 12, clock generation circuit 14 and initialization address generation circuit 15 of FIG. 14) provided in the semiconductor memory device to generate addresses and data and to write all the generated data in all the generated addresses. In the latter case, a time period required for initialization depends on a time period required for the system containing the semiconductor memory device to carry out the program for initialization. However, writing of the initialization data is carried out by an ordinary writing operation of the semiconductor memory device in both cases.
In such a semiconductor memory device as a SRAM, addresses in which data is written are sequentially selected one by one and the corresponding data is written in one of these selected addresses in a data writing as described above. Therefore, data cannot be written simultaneously in a plurality of addresses. The time required for writing the initial data is accordingly increased as the number of memory cells to be initialized is increased, that is, the number of addresses and data bits to be initialized is increased, which results in the increased time period required for initialization. In recent years semiconductor memory devices have been made large in scale, which is followed by the increased number of memory cells to be initialized. As a result, such a conventional initialization method makes an initialization time period longer and consequently decreases an operational speed of a semiconductor device, which results in a reduced operational speed of a system containing the device.
In initializing storage data of a semiconductor memory device by means of hardware as described above, the execution of complicated initialization requires large additional circuits. Such additional circuits require more power to be consumed and an increase in a chip area results, which are not preferable in view of low power consumption and miniaturization of a semiconductor integrated circuit device. Such complicated initialization by means of software also makes the program complicated to increase an execution time due to the increased program size, which results in an increase in initialization time.

Semiconductor memory device capable of initializing storage data


A queuing apparatus having a hierarchy of queues, in one of a number of aspects, is configured to control backpressure between processors in a multiprocessor system. A fetch queue is coupled to an instruction cache and configured to store first instructions for a first processor and second instructions for a second processor in an order fetched from the instruction cache. An in-order queue is coupled to the fetch queue and configured to store the second instructions accepted from the fetch queue in response to a write indication. An out-of-order queue is coupled to the fetch queue and to the in-order queue and configured to store the second instructions accepted from the fetch queue in response to an indication that space is available in the out-of-order queue, wherein the second instructions may be accessed out-of-order with respect to other second instructions executing on different execution pipelines.

Many products, such as cell phones, laptop computers, personal digital assistants (PDA), desktop computers, or the like, incorporate one or more processors executing programs that support communication and multimedia applications. The processors need to operate with high performance and efficiency to support the plurality of computationally intensive functions for such products.
The processors operate by fetching instructions from a unified instruction fetch queue which is generally coupled to an instruction cache. There is often a need to have a sufficiently large in-order unified instruction fetch queue supporting the processors to allow for the evaluation of the instructions for efficient dispatching. For example, in a system having two or more processors that share a unified instruction fetch queue, one of the processors may be a coprocessor. In such a system, it is often necessary to have a coprocessor instruction queue downstream from the unified instruction fetch queue. This downstream queue should be sufficiently large to minimize backpressure on processor instructions in the instruction fetch queue to reduce the effect of coprocessor instructions on the performance of the processor. However, large instruction queues may be cost prohibitive in terms of power use, implementation area, and impact to timing and performance to provide the support needed for coprocessor instructions.

Hybrid queue for storing instructions from fetch queue directly in out-of-order queue or temporarily in in-order queue until space is available


In one exemplary aspect of the present invention a method for cleaning a media drive transducer head is provided. The method includes transporting a portion of a cleaning tape over a transducer head under a first set of conditions, the first set of conditions associated with a cleaning process of the transducer head, and transporting the portion of the cleaning tape over the transducer head under a second set of conditions, the second set of conditions associated with a writing process.

1. Field of the Invention
The present invention relates generally to cleaning cartridges and associated methods for cleaning media drives, and more particularly to methods of controlling cleaning cartridges in media drives.
2. Description of the Related Art
Magnetic tape cartridges have proven to be an efficient and effective medium for data storage in computer systems. Magnetic tape cartridge storage systems generally include one or more tape cartridges housing a tape coated with a magnetic medium and one or more tape drives. A tape drive typically includes a data transducer, e.g., a read and/or write head, and various control electronics for writing data to the magnetic tape and reading data from the magnetic tape and for moving the data transducer laterally with respect to the tape.
The data transducer heads in the media drive may experience a build up of debris or contaminants over time. The build up of debris on the data transducer heads may cause a decrease in performance or damage to the tape drive and/or tape cartridge. Various devices and methods for cleaning transducer heads have been provided. For example, a cartridge housing a cleaning tape, commonly referred to as a "cleaning cartridge," may be used. A cleaning cartridge may include a tape that is manufactured with particular mechanical and/or chemical properties that provide for increased abrasiveness to clean debris from the transducer head of the drive. The cleaning cartridge may be loaded into the tape drive and spooled across a transducer head thereby removing debris and contaminants. Further, during a cleaning process, the transducer head may be moved laterally up and down with respect to the direction of tape transport to further enhance the cleaning process.
Generally, only a portion of the length of the cleaning tape in a cleaning cartridge is used in a single cleaning process, and it is typically undesirable to reuse the same portion of a cleaning tape more than a certain number of times. Therefore, one method of cleaning transducer heads includes writing data to the cleaning tape during a cleaning process to indicate which portions of the cleaning tape have been used. The data may be read before a subsequent cleaning process to eliminate the potential of reusing the same portion of the cleaning tape. A drawback of this method includes that the optimum speed for cleaning a transducer head is significantly slower than the optimum speed for writing data to the cleaning tape. Accordingly, this method may sacrifice cleaning efficiency by operating at speeds suitable for reading and writing to the cleaning tape.

Methods for controlling the use of a cleaning cartridge for tape drives


Crimping apparatus for crimping separate parts of a metal sleeve arranged concentrically about the junction between a shielded cable and a plug connector, including a pair of colinearly arranged annular crimping dies that are operable by an annular operating member arranged concentrically about the crimping dies, such that upon a single angular movement of the operating member in a given direction from a retracted position to a crimping position, one end of the sleeve is crimped to the plug in one desired manner, and the other end of the sleeve is crimped to the shielded cable in another desired manner.

1. Field of the Invention
Crimping apparatus for crimping separate parts of a metal sleeve arranged concentrically about the junction between a shielded cable and a plug connector, such that upon a single angular movement of an annular operating member in a given direction about its longitudinal axis, one end of the sleeve is crimped to the plug in one manner, and the other end of the sleeve is crimped to the shielded cable in another manner.
2. Description of Related Art
Various models of crimping devices are well known in the electrical connector art, as shown, for example, by the prior U.S. patents to Schmode No. 6,997,028, Hetland et al No. 7,055,361, Heggemann et al No. 7,325,438, each assigned to the same assignee as the present invention.
The present invention was developed to provide a crimping device that can be used especially for the crimping of cables, where the terminal segment of a shielded cable (or conductor) is to be crimped several times with at least one metal sleeve in the exposed area. The invention-based crimping device is designed to create at least two or more axially mutually offset crimping areas in only one work step. In this way, the time needed for crimping is kept at a minimum, and one can also make sure that the two crimping areas always have a constant interval from each other.
Preferably, two or more axially mutually offset crimping dies are provided, which again, in a particularly preferred manner, are coupled together in a non-rotatable fashion. These crimping dies are of simple structure and preferably include crimping dies that are coupled together in a non-rotatable fashion and that in each case act upon radially displaceable crimping bars.
Preferably, the crimping depth of at least one crimping die is made adjustable, and the crimping depth of the other crimping die is firmly preset in order to be able to make or process the various crimping depths and cable diameters.

Crimping apparatus for cables, particularly shielded cables


In an axial flow gas turbine, the outlet blading followed by an exhaust casing (5) whose boundary walls essentially comprise a ring-shaped inner part (6) at the hub and a ring-shaped outer part (7) which delimit a diffusor (9). The outlet-end bearing arrangement (4, 11) of the turbomachine is arranged in the hollow space within the inner part. The bearing casing (11) can be repositioned by adjustment elements (12) arranged on the inner part (6) of the exhaust casing and is supported on the foundation via at least one sprung support (15).

1. Field of the Invention
The invention concerns a thermal turbomachine, in particular an axial flow gas turbine, whose outlet blading is followed by an exhaust casing whose boundary walls essentially comprise a ring-shaped inner part at the hub and a ring-shaped outer part which delimit a diffusor and are connected to each other by a plurality of ribs uniformly distributed over the circumference, the outlet-end bearing arrangement of the turbomachine being arranged in the hollow space within the inner part.
In the case of stationary gas turbine installations, relatively long outlet diffusors are provided, preferably extending in the axial direction, for reasons of fluid mechanics and the better to influence the efficiency. As a result, it is necessary to arrange the exhaust-end turbine runner bearing in the diffusor structure itself. Because of the differing requirements of the diffusor casing, which should be free to expand, and the turbine runners, which cannot be allowed to move about, problems arise which have previously been solved in various ways.
2. Discussion of Background
Thus, for example, in the diffusor of a jet engine gas turbine, which is connected via streamlined ribs to an outer casing, it is known from U.S. Pat. No. 3,261,587 to support the load-bearing ring of the shaft bearing on the outer casing by pins inserted in a thermally mobile fashion in radial planes in the diffusor. Consequently, both the dominant dynamic forces and the expansion forces of the exhaust diffusor are transferred to the outer casing. The outer casing itself is supported on the foundation via claws or suspension supports.
In unsteady operation, as often occurs, for example, in the case of power station gas turbines used for peak-load supply, the casings are subject to thermal stresses and differential expansions which lead to variations in clearance between casing and runner and can also affect the shaft bearing arrangement. Damage to the bearings and stuffing boxes as well as blading damage can then arise. In particular, these disadvantages become effective to a greater extent in today's modern machines with their large dimensions and high temperatures.
An early solution, in which the exhaust diffusor was separated completely from the outer casing of the gas turbine, is known from DE-C-768,036. The outer and inner ring walls of the diffusor are connected together via thermally mobile and expansion compensating elements and the end bearing of the runner is supported in the interior of the inner wall at the hub. Shaft movements can also occur with this type of construction as a result of differential expansions. In particular, large thermal stresses occur at the thermally mobile joints between the exhaust diffusor and the exhaust casing, complicating the sealing problems prevailing there.
In modern machines, the diffusor is no longer itself supported directly on the foundation but is flanged onto the gas turbine casing. The exhaust-end shaft bearing arrangement within the diffusor inner ring is located in an exceptionally hot environment when the machine is operating. Both the positioning of the bearing and the acceptance of the normally vertical load are located in the diffusor structure However, because of the low creep rupture strength of the materials used, the whole load-bearing structure can deform in the course of time.

Bearing arrangement for a thermal turbo machine


A messaging system includes a messaging platform storing a message from a calling party, a switching mechanism for receiving a call from a subscriber to access the stored message, and a routing application at a server. The subscriber accesses the message at the messaging platform and signals for a callback connection with the calling party. In response, the messaging platform sends bookmark information to the routing application describing a current state of the messaging platform with regard to the subscriber. The routing application directs the switching mechanism to disconnect the subscriber from the messaging platform and connect the subscriber to the calling party. When the callback connection is completed, the routing application directs that the subscriber be re-connected with the messaging platform and sends the stored bookmark information back to same. The messaging platform employs such bookmark information to re-establish the current state.

In recent years, a number of new telephone service features have been provided by an Advanced Intelligent Network (AIN). The AIN evolved out of a need to increase the capabilities of the telephone network architecture in order to meet the growing needs of telephone customers or users. Additionally, as the number of people who rely on the Internet for communication increases, so too does the demand for the electronic transfer of data.
Referring now to FIG. 1, it is seen that an AIN-based network arrangement is provided within and/or in conjunction with a wire line telephone system LATA (Local Access and Transport Area) 101 that defines a calling service area. Note that a similar arrangement is also provided with and/or in conjunction with a wireless telephone system. Each LATA 101 (only one being shown in FIG. 1) includes stations (i.e. telephone lines and telephone equipment at the respective ends thereof) 103 and corresponding service switching points (SSPs) 105 (i.e., end offices or central offices). The SSPs 105 are each programmable switches which: recognize AIN-type calls; launch queries to service control points (SCPs) 107 (only one being shown in FIG. 1); and receive commands and data from SCPs 107 to further process and route AIN-type calls. A signal transfer point (STP) 109 may be employed to route signals between the SSPs 105, the SCPs 107, and other network elements. When one of the SSPs 105 is triggered by an AIN-type call, the triggered SSP 105 formulates an AIN service request and responds to call processing instructions from the network element in which the AIN service logic resides, typically at an SCP 107.
One type of event that may be arranged to set off an AIN trigger in an SSP 105 or the like is a call from a calling party to a called party where the called party subscribes to a messaging service and is unavailable to answer the call. Accordingly, the AIN trigger at issue is associated with the called party and with the SSP 105 of such called party. In response to the set-off trigger, the SSP 105 determines from the SCP 107 routing instructions for routing the call to the messaging platform. As may be appreciated, the messaging platform may play a greeting message to the calling party and then collect and store a voice message or the like therefrom. In addition, the messaging platform may collect and store call-related information including the time of the call and the telephone number of the calling party.
Thus, the called party/subscriber may at some later time call into the messaging platform and retrieve the stored voice message from the calling party, as well as the stored time of the call and the stored telephone number of the calling party. In addition, and in at least some instances, the calling party may signal to the messaging platform to call back the calling party at the stored telephone number.
In the prior art, the messaging platform resided on a telephone line of the public telephone system and thus was called into by the message-retrieving called party over the telephone line thereof. As a result, the messaging platform called back the calling party at the stored telephone number by way of another telephone line, and then bridged the call between the messaging platform and the called party and the call between the messaging platform and the calling party to form the callback connection between the called party and the calling party. Such an arrangement leaves the messaging platform involved in the call, and accordingly the messaging platform may continue to be accessed by the called party/subscriber after the called party and the calling party are finished with the connection therebetween. Accordingly, the called party/subscriber may listen to another voice message stored at the messaging platform, for example.
However, and significantly, such an arrangement is inefficient in that the messaging platform is using two telephone lines and bridging resources to form the callback connection, and in that the messaging platform is dedicating resources including call connection information and circuits that are essentially sitting idly until the callback connection is terminated by the called party, the calling party, or the like. In particular, the called party is callback connected to the calling party by way of the two telephone lines of the messaging platform and the bridging resources even when the messaging platform is not actively involved, and the messaging platform must watch over the callback connection the entire time. Potentially, the two telephone lines of the messaging platform, the bridging resources, and the messaging platform could be tied up for hours on end without any significant involvement on the part of the messaging platform with the callback connection between the called party and the calling party.
Accordingly, a need exists for a callback function for a messaging platform in a public telephone system, where the callback function more efficiently establishes a callback connection between a called party and a calling party. More particularly, a need exists for such a callback function that establishes a direct callback connection so that messaging platform resources employed during the callback are minimal, and yet that leaves the messaging platform available later should the called party/subscriber for example wish to listen to another voice message stored at the messaging platform.

Callback function for messaging platform in public telephone system

BellSouth Intellectual Property Corporation


A condensation-curing type curable composition which comprises a diorganopolysiloxane or polyoxyalkylene blocked by hydrolyzable silyl group at both terminal ends of its molecular chain as a base polymer, in which a carbonyl group-containing organic compound and an amino group-containing organic compound are compounded. This composition is capable of forming water through dehydration condensation between carbonyl and amino groups, simultaneously with curing of the composition by moisture in air. The formation of water offers marked improvements in fast-curing property and also in depth curing property.

1. Field of the Invention
The present invention relates to a room temperature fast-curing composition, and more particularly to a condensation-curing type room temperature fast-curing composition which has good fast-curing property and depth curing property (i.e., property for curing to deep, or inside, portions thereof).
2. Description of the Prior Art
As a condensation-curing type room temperature fast-curing composition, there have been known those of one-pack type in which the amount of crosslinking agent is reduced to an utmost degree so as to enhance curing rate and those of two-pack type in which a crosslinking agent and a curing agent are enclosed in separate packs.
However, the one-pack type compositions have only the advantage of high rate of cure from the surface thereof, and they need a certain period of time for curing to their deep portions. Thus, such compositions cannot be said really "fast-curing".
The two-pack type compositions are comparatively better in depth curing properties. However, the two-pack type compositions are bothersome to deal with, and are not well suited to use with mixing machines or the like, because the two parts in separate packs are not formulated for a mixing ratio of 1:1. Furthermore, for complete cure to the depth, it is necessary to specify strictly the addition amounts of crosslinking agent and curing agent or to add water as a depth curing agent.
On the other hand, addition-curable organopolysiloxane compositions of two-pack type are superior in workability, because the two parts in separate packs are formulated for a 1:1 mixing ratio. However, this type of compositions usually require a heating furnace for curing. Besides, they have limitations as to working atmospheres because a curing catalyst used therein is poisoned in the presence of a substance poisonous to the catalyst or to the addition reaction.

Room temperature fast-curing composition


A device for separating two zones of a passenger cabin including a frame element and an area element which is fastened to said frame element and includes, at least in certain sections, a flexible stretch material. The separating device is detachably fastenable in such a way to a passenger seat installed in the passenger cabin, that the area element extends substantially in one plane with a backrest of the passenger seat and that the section of the area element which includes of a flexible material is transferrable from a non-tensioned physical state into a flexibly stretched physical state in the event of the backrest of the passenger seat being adjusted from an upright position into a reclined position.

The invention relates to a device for separating two zones of a passenger cabin, in particular an aircraft passenger cabin, and also to a passenger cabin interior component layout, in particular an aircraft passenger cabin interior component layout, which comprises a separating device of this kind. The invention further relates to a method of reconfiguring a passenger cabin, in particular an aircraft passenger cabin, using a separating device of this kind.
The passenger cabin of a modern commercial aircraft is usually subdivided into various zones, for example a business class zone located in a front region of the passenger cabin and a tourist class zone located in a rear region of said passenger cabin. For the purpose of separating the business class zone from the tourist class zone, use is made, as a rule, of partitions installed in a fixed manner in the passenger cabin, such as are described, for example, in DE 10 2008 031021 A1 or WO 2010/000700 A2 or in DE 10 2008 016 419 A1 or US 2009/242149 A1, or of curtains which are mounted in a fixed manner in said passenger cabin. It is also known, from DE 10 2009 041 581 A1 or US 2011/0062283 A1, for a crew rest area which is provided directly within the passenger cabin of an aircraft to be separated off by means of a curtain from a region of said cabin that surrounds said crew rest area.
In order to be able to cope with different conditions of use, it is becoming increasingly more important to organise the subdivision of an aircraft passenger cabin into different zones in the most flexible manner possible. For example it may be economically sensible, from an airline's point of view, to use the largest possible area within the passenger cabin of a commercial aircraft as a tourist class zone at certain times when there is a higher volume of flights, e.g., during the holiday season. On the other hand it may be sensible at other times, for example when there are lots of bookings by business travellers, to identify a larger area of the aircraft passenger cabin as a business class zone.

Device for separating two zones of a passenger cabin


A seal for use with a tapered roller bearing includes a seal affixed to a first seal support, and comprises an inner sealing member in contact with a second seal support, an outer sealing member extending toward and contacting the second seal support, and a central sealing member extending toward but not contacting the second seal support. A rain shield covering a gap between the first and second seal supports may also be included.

The present invention relates generally to bearing assemblies and in particular to devices and methods for sealing bearing assemblies used in railway vehicles or other similar applications. Bearing assemblies allow a wheel to rotate relative to a shaft (also called an axle journal). Bearing assemblies are often sealed to maintain a lubricant within the bearing assembly and to prevent dirt, sand, and moisture to enter the bearing assembly. The seal is typically formed of an annular rubber lip seal which rotates about the shaft.
Referring to FIG. 1, a conventional embodiment of a seal 200 for a bearing assembly 100 is shown. The bearing assembly 100 may include, for example, a journal shaft 101 supporting a wear ring 106, an inner race 103, and a backing ring 102. The inner race 103, may support, for example, a tapered roller bearing 105 and a outer race 104. Sealing the grease in the tapered roller bearing is a seal 200 including an upper seal support 202, a lower seal support 209, and a plurality of rubber projections which include: a inner rubber seal 203 having grease seal portion 206, a dust seal 205, and a non-contact side seal 204. The prior art, however, suffers from a number of deficiencies including a propensity for moisture to enter the bearings and degrade the seal.
Accordingly, there exists a need for an improved bearing seal which reduces torque, i.e., is a low-torque seal, while at the same time maintaining the high reliability normally associated with higher torque seals.
Aspects of the present invention overcome one or more of the above-mentioned problems by using improved seal assemblies and/or approved sealing surfaces and/or materials. For example, an aspect of the present invention utilizes a polymeric main seal such that grease is permanently sealed in the tapered roller bearings. In the most preferred embodiments, a Teflon or PTFE is utilized to provide the main seal. The main seal may extend horizontally from a upper seal support and contact and ride along an extended portion of a horizontal lower seal support.
In other aspects of the present invention, a rain shield is provided over the gap between the upper seal support and the lower seal support. In still further aspects of the invention, a side seal is a contact side seal which runs and/or contacts the vertical surface of the lower seal support. In still further aspects of the invention, a non-contact seal is provided which rotates spaced from the surface of the a horizontal surface of the lower seal support. The non-contact seal may include two closely spaced fingers or times having lengths substantially longer than widths. This improves resiliency of tines, improving reliability.
These and other features of the invention will be apparent upon consideration of the following detailed description of preferred embodiments. Although the invention has been defined using the appended claims, these claims are exemplary in that the invention is intended to include the elements and steps described herein in any combination or subcombination. Accordingly, there are any number of alternative combinations for defining the invention, which incorporate one or more elements from the specification, including the description, claims, and drawings, in various combinations or subcombinations. It will be apparent to those skilled in the art of roller bearing seals, theory and design in light of the present specification, that alternate combinations and subcombinations of one or more aspects of the present invention, either alone or in combination with one or more elements and/or steps defined herein, may be utilized as modifications or alterations of the invention or as part of the invention. It is intended that the written description of the invention contained herein cover all such modifications and alterations. For example, in alternate aspects of the invention, the seal may include one or more of the water shield, the non-contact shield, the contacting side seal and/or the grease seal in any combination or subcombination.


Logs are cut to firewood length and split on a trailer that has a jacking foot at the trailer tongue and that defines an elongated bed for supporting the log lengthwise of the trailer. A superstructure pivotably supports a chainsaw for cutting the log, and a driven roller engages the top of the log to feed it incrementally into the cut-off saw's path. A conventional wood splitter is also incorporated in the same trailer.

While complex log processing equipment is available to the sawmill industry for the automated handling of logs in connection with the fabrication of lumber, the need exists for a portable log processing machine capable of producing firewood at various sites to which the device can be towed in the manner of a typical log splitting trailer for example.
U.S. Pat. No. 4,269,242 shows an endless carrier for feeding logs into the path of a reciprocating guillotine type blade which severs the log into sections of firewood length. The firewood then drops into a position where a hydraulic ram can drive the log section endwise against a fixed wedge.
Another prior art U.S. Pat. No. 4,273,171 illustrates an improvement over that prior art disclosure wherein the cutting blade is provided for movement in a horizontal direction against a stop, and wherein a wedge is provided in conjunction with that cutting blade to aid in the severing of firewood length logs from the log itself.
Both of these prior art disclosures are quite complex, and require considerable maintenance to keep them operational in the field.
The purpose of the present invention is to provide a readily transportable, low maintenance trailer which not only contains a wood splitter, but which also includes means for advancing the log into a cut-off station for severing a log of any length into sections to be split by a conventional wood splitter of the type adapted to move the log against a fixed wedge. See U.S. Pat. No. 4,303,112 for a disclosure of a typical trailer mounted wood splitter. See also U.S. Pat. No. 4,800,937 which shows a somewhat more sophisticated wedge arrangement for splitting a single firewood length log section into more than two pieces.
While complex structures are available for performing the tasks for which the present apparatus has been designed, these prior art apparatus have tended to be unduly complex as mentioned previously. See for example U.S. Pat. No. 4,869,303 wherein a wood processor is disclosed for cutting a log into a series of shorter lengths, and subsequently splitting the shorter lengths into individual pieces of firewood. This processor of the '303 patent includes a carriage for receiving the log, clamps which engage the log from both sides to secure it in the carriage, and a mechanism for advancing the carriage so that the log is brought into contact with a plurality of parallel rotating saws. After the carriage has been retracted a pusher rod moves the cut log pieces along an axis onto a plurality of cradles which support the individual log sections. These cradles are tilted to dump the sections alternately into opposite sides of the direction of log movement so that they can be fed into a plurality of individual hydraulically operated log splitters.


A content addressable memory cell (10) includes a circuit (20) operating from a predetermined supply voltage (VDD) for storing a first bit of data at a first point (35) and a second bit of complementary data at a second point (36). A first transistor (40) comprising a first gate (42) is switchable to first and second states in response to predetermined relationships between the first and second bits and third and fourth test bits transmitted on first and second lines (14 and 16). Second and third transistors (50, 60) comprise gates (52, 62) coupled to the first line (14) and second line (16) and comprise circuit paths (54, 56, 64, 66) coupling the first and second points to the first gate.

This invention relates to memory cells and more particularly relates to content addressable memory cells.
Many memory devices store and retrieve data by addressing specific memory locations. As a result, this path often becomes the limiting factor for systems that rely on fast memory access. The time required to find an item stored in memory can be reduced considerably if the stored data item can be identified for access by the content of the data itself rather than by its address. Memory that is accessed in this way is called content-addressable memory (CAM). CAM provides a performance advantage over other memory search algorithms (such as binary and tree-based searches or look-aside tag buffers) by comparing the desired information against the stored data simultaneously, often resulting in an order-of-magnitude reduction of search time.
A CAM cell is the basic circuit determining the speed, size and power consumption of CAM systems. Known CAM cells employ a match circuit that changes state depending on whether there is a match or mismatch between data stored in the cell and test data. In the past, the match transistor has provided an unreliable indication of a match because, under some conditions, the voltage transmitted to the gate of the match transistor has been in a range of values between the VDD supply of the cell and the reference potential used in the cell, such as ground potential. This range of values provides an ambiguous indication that is difficult to interpret. In addition, the circuitry involved in determining whether there is a match condition typically has drawn current from the bit lines supplying the test data. This current draw increases the power consumption of the cell, because the current is conducted through the bit line. The bit line driver must be larger because all the cells connected to the same bit line draw current. In some other circuits, there are two series transistors to detect a match. This makes the matching response slow. This invention addresses these problems and provides a solution.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.

This patent is subject to a terminal disclaimer.

Content addressable memory cell techniques


The present invention relates to cache coherent node controllers for scale-up shared memory systems. In particular it is disclosed a computer system at least comprising a first group of CPU modules connected to at least one first FPGA Node Controller configured to execute transactions directly or through a first interconnect switch to at least one second FPGA Node Controller connected to a second group of CPU modules running a single instance of an operating system.

The introduction of Field Programmable Gate Arrays (FPGAs) has opened opportunities to use such circuits in a plurality of ways as components in computing systems. The present invention combines the FPGA capabilities with a specific type of functionality. The functionality can be described as a Node Controller in a scalable computer system with multiple central processing units (CPUs) where all the processors can share and operate on all the available memory and where all the caches and the corresponding memory locations in the system are kept coherent with respect to the valid data produced by the processors.
Modern processors have capabilities of interconnecting a relatively low number of processor modules to form larger systems by direct connections between the processors across point-to-point links. Each processor module contains a number of CPU cores. These links are not capable of expanding the system size beyond typically 4-8 modules, although some may go as far as a maximum of 16. For performance reasons, the directly connected systems are limited to 8 modules due to the increasing inefficiency in the protocols that handle the housekeeping task to maintain data coherency across all memories and high speed caches in the system.
By cache coherence, it is meant consistency of shared data stored in multiple local caches. In a multi-processor system with multiple local caches, data that reside in these caches must be updated or invalidated such that accesses to the data will reflect the latest values stored by any given processor with access to that data. Processors operate independently of each other and thereby influence on the caches independently of each other and without cache coherence logic, shared data would not be valid and would cause inconsistent results for multithreaded programs that use the data.
Cache coherence is intended to manage and maintain consistency between the caches and memory.
Multiprocessor memory sharing systems has normally been carried out with hard-wired application specific integrated circuits (ASICs) using state machines that cannot be changed after the ASIC has been manufactured. This requires a very comprehensive verification program to be conducted before the ASIC is produced and leaves no room for correcting any potential errors in the state machines without making a new ASIC. This is both expensive and time consuming.
U.S. Pat. No. 7,406,086 B2 discloses a method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being connected to each node controllers, a memory connected to each controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers.

Cache coherent node controller for scale-up shared memory systems having interconnect switch between a group of CPUS and FPGA node controller


Among other things, we describe techniques for electric power steering torque compensation. Techniques are provided for a method implemented by a computer, e.g., a computer onboard an autonomous vehicle. A planning circuit onboard the vehicle and connected to an EPS of the vehicle determines a compensatory torque signal to modify an actual steering angle of a steering wheel of the vehicle to match an expected steering angle of the steering wheel. The planning circuit transmits the compensatory torque signal to a control circuit that controls the steering angle of the steering wheel. The EPS modifies the actual steering angle based on the compensatory torque signal resulting in a modified steering angle. The control circuit operates the vehicle based on the modified steering angle.

An electric power steering (EPS) system is a system that applies a torque on a steering column of a vehicle to turn the vehicle one way or another. The EPS (sometimes called electric power-assisted steering) system is mounted on either the steering column or steering gear and applies torque to the steering column which turns the steering wheel. In an autonomous vehicle, an EPS system can apply a torque to the steering column, thereby controlling the operation of the vehicle.

Electric power steering torque compensation


An absorbent garment has a minimum crotch width less than 30% the front region width. The absorbent garment has an absorbent member minimum width less than 80 mm. The absorbent member minimum width is less than 53% the minimum crotch width and is less than 60% the absorbent member maximum width.

Disposable absorbent garments are designed for absorbing body exudates and are similar in appearance, size, and shape to regular cloth underwear but are not designed to be laundered and reused. Many absorbent garments are designed to be pulled up around the user's body by utilizing stretchable materials that facilitate conformance to the anatomy of the user's torso like regular cloth underwear. However, the desire to make absorbent garments more like cloth underwear has to be balanced with the need to maintain product absorbency and performance. This balance is difficult on all product forms but is particularly pronounced with absorbent garments designed for use by adults because adequate amounts of absorbent material are initially needed at the crotch of the product near the point of insult. However, placement of excessive absorbent material at this location could have a negative effect on the comfort, fit, and discretion of the product. Thus, there remains a need for absorbent articles designed to fit a wide range of adult shapes and sizes that has a close and comfortable fit and yet provides the necessary leakage and absorbency performance expected by the user.


A plug unit configured for use in high performance liquid chromatography is described. The plug unit comprises a capillary comprising a capillary distal face; a sealing element, wherein at least a portion of the sealing element is located distal from the capillary distal face; and a biasing element configured to bias the capillary towards the sealing element.

HPLC is a method of separating samples into their constituent parts. The constituent parts can be separated for subsequent use or their portions can be quantified. In order to fluidly connect HPLC equipment, capillaries mostly made of stainless steel, glass (fused silica) or PEEK are used. For biocompatible HPLC systems, titanium, fused silica, MP35N™ or PEEK™ capillaries are used, e.g., in order to be as iron-free as possible. In order to interconnect such capillaries, suitable connectors are advantageous.
Capillary connecting lines are equipped at their ends with devices suitable to establish a leakproof connection to the connectors of the components. These devices are also designated as fittings. Such fittings are already mentioned as state of the art in U.S. Pat. No. 4,083,702 and in U.S. Pat. No. 4,619,473.
According to one present system for interconnecting a capillary to another element, a threaded ring is squeezed against a cone, whereby the threaded ring seals outwards radially and inwards in the direction of the capillary tube. In order to provide leakproof connections, the connection must be turned inwards and tightened with a torque of several Newtons.
At the same time, the exact moment when a screw connection is safely sealed cannot be defined accurately. Moreover, there is a risk that the fittings might be damaged by applying excessive torques.
A further system for connecting a capillary to another unit is disclosed in WO2010133192. However, the system disclosed therein may have certain drawbacks and limitations: The system may not be completely free from dead volume, as, due to the production process, it cannot be ensured that the fused silica capillary is directly adjacent to the seal. Further, a clearance to the base would have to be left in, as otherwise the glass capillary would rest on the base, which would destroy the capillary.
A further system is disclosed in EP3163298. However, also this system may have certain drawbacks and limitations: It may also not be completely free from dead volume, as, due to the production process, it cannot be ensured that the fused silica is directly adjacent to the seal.
In light of the above, it is an object to overcome or at least alleviate the shortcomings and disadvantages of the prior art. That is, it is an object of the present invention to provide a plug unit and a capillary connection system providing a secure seal and/or protecting components from damage.
These objects are met by the present invention.

Plug units, particularly for HPLC, connection system and corresponding use


A portable apparatus for dispensing and foaming of a product, including: a product container which contains a product that is to be foamed by and dispensed from the apparatus; a gas container, at least containing a gas, for example a single gas or a gas mixture, wherein the gas substantially does not contain any greenhouse gases such as N2O; a dispersion device, having a product entrance that is connectable to the product container for receiving product, the dispersion device further being connectable to the gas container for supplying the gas to the product during product discharge; a processing device downstream of the dispersion device for performing a mixing treatment and/or pressure reduction on the product provided with the gas; and a product dispensing head, being part of a top section of the apparatus and being arranged downstream of the processing device.

The invention concerns a portable apparatus for dispensing (and foaming) of a product.
An example of a known product dispensing and foaming apparatus is an aerosol can, see e.g. WO2008/033005. The known apparatus includes a reservoir containing a propellant and a foodproduct, operable discharge means to discharge the foodproduct, as well as a dispensing head defining a foodproduct receiving space to receive the foodproduct from the discharge means. A distal part of the head includes foodproduct shaping projections, for shaping of the outflowing foamed product.
The known apparatus is convenient, lightweight, compact and designed to be disposed after being used-up. This has major advantages over e.g. commercially available, bulky and expensive cream whipping machines (usually having an electrically driven pump, and requiring regular maintenance and cleansing operations).
Particularly, during operation of the known aerosol container, in case of operating the discharge means, cream is ejected via the dispensing head and undergoes a so called 'overrun' (i.e. volume increase), such that a 'spray cream' which resembles common whipped cream, is obtained.
The foodproduct is safe for consumption. As a non limiting example, the known aerosol container can be packed with foodproduct and propellant, the initial pressure in the container being for example in the range of 7-18 atmospheres, depending on the amount of packed foodproduct, as will be appreciated by the skilled person. The propellant of the known apparatus can consist of one or more gases acceptable from the viewpoint of food technology, for example a gas which substantially dissolves in the foodproduct, a gas which substantially does not dissolve in the foodproduct and a combination of these gases. Particularly, according to WO'005 the propellant can comprise CO2, nitrogen (N2), laughing gas (N2O) or a combination of these gases (such as nitrogen and laughing gas). For example, 15-25 w % (weight %) of the propellant can be N2 and the remainder of the propellant (i.e. 85-75 w %) can be N2O.
In practice, the aerosol container at least comprises N2O as a propellant since this gas can provide good foodproduct propelling and foodproduct-overrun results, at the afore-mentioned pressures. One problem is that N2O is a so-called greenhouse gas. There is a general desire to limit or ban the use of green-house gases to protect the earth from global heating.

Apparatus and methods for dispensing and foaming of a product


An air bag (20) for use in a vehicle (200) having a border region (22) having a top (24) situated about at least one inflatable region (30, 30a, 30b); the top of the border region configured to be secured directly or indirectly to a portion of the vehicle or component of the vehicle; wherein the border region includes at least one slit.

The present invention relates to air bags for protecting a vehicle occupant.
The preferred embodiment of the present invention is described in the context of a curtain air bag that is deployable from a roof rail of the vehicle. The prior art illustrates curtain air bags with a peripheral border fastened directly or indirectly to a roof rail. In one variation a tab is sewn to the top of the border and a fastener is inserted through the tab into the roof rail. The tab can also be an integral part of the border region or main panel of the air bag. It is not necessary to use a tab, for example the top of the border region may include one or more fastener holes and a fastener is received through each hole. When an air bag inflates it does so rapidly, moving a mass of material from a folded configuration to its expanded, inflated configuration. As the air bag inflates the various stresses are created in the air bag at the point of attachment to the vehicle; generally at or about the mounting hole or fastener. The present invention substantially reduces these stresses providing for a more robust airbag.
More specifically the invention comprises: an air bag for use in a vehicle comprising: a border region having a top situated about at least one inflatable region; the top of the border region configured to be secured directly or indirectly to a portion of the vehicle or component of the vehicle; wherein the border region includes at least one slit. The inclusion of one or more slits permits the top of the border region to deform as the air bag deploys to its inflated condition; as the slit is stretched and opens, energy is absorbed and less stress is seen on those portions secured to the vehicle or to a vehicle component. An additional benefit of the present invention is that the incorporation of the slits permits the bottom (or generally an opposite end, side or region) of the air bag to extend further away from the mounting locations than could be achieved without the slits thereby increasing the effective size of the air bag. This feature permits a smaller air bag to replace a larger prior art air bag.

Air bag having a slit in a border region


A flag holder for attachment to a standard highway sign, for holding a pair of symmetrically arrayed warning flags at the top of the sign, and for permitting the flags to be folded downwardly for transport and storage. When used on roll-up highway signs the flags may be rolled up along with the roll-up sign. The holder includes an elongated rigid holder body which is adapted for attachment adjacent the top of a standard rigid or roll-up highway warning sign. Attachment is by means of bolts in the case of a rigid sign, or at least one clamp attached to the body for fixedly securing the body to the strut or brace of a roll-up sign. A pair of elongated flag staffs are pivotally attached at one end to the holder body and each has a flexible warning flag at the other end. To hold the flags in open operable position a pair of elongated spring clips extend between a point on the holder body spaced from the pivotal attachment of the flat flag staffs to the body and a point on the flag staffs spaced from their pivotal attachment to the holder body. The spring clips have a pivotal connection at one end and a separable male-female stud-aperture connection at the other end. The spring clips may be pivotally connected to the holder body and make a separable male-female stud-aperture connection to the flag staff, or the spring clip may be pivotally connected to the flag staff and make a separable connection with the holder body.

1. FIELD OF THE INVENTION
This invention relates to a flag holder used on portable highway or road signs to increase visibility of such signs to approaching traffic. It is common practice to affix one or more warning flags which extend above the top of the highway sign. This invention is directed to a flag holder in which pivotally mounted symmetrically arranged flags may be easily snapped into operating position from their folded storage position, and just as easily refolded after use.
2. THE PRIOR ART
Sarkisian U.S. Pat. No. 4,288,053 and Kulp et al U.S. Pat. No. 4,980,984 are exemplary of patents directed to highway signs having flags mounted to extend above the top of the signs. Applicant's co-pending application Ser. No. 954,311, filed Sep. 30, 1992, also discloses a portable highway sign having warning flags mounted at the top thereof.


An electronic device for contemporaneously obtaining, with a processor connected to a memory, a forward image from a forward facing camera of the electronic device and a rear image from a rear facing camera of the electronic device, and embedding the rear image in the forward image or the forward image in the rear image, thereby creating a composite image. Optionally, the rear image is embedded as a watermark in the forward image thereby creating the composite image. Alternatively, the rear image is steganographically embedded in the forward image thereby creating the composite image.

The present invention generally relates to electronic devices including at least one camera, and to the electronic devices performing image processing, and more particularly relates to an electronic device processing images where the electronic device, with at least one camera, obtains and processes a forward image and a rear image.
Smartphones often have two cameras, pointed in opposite directions. The first smartphones mainly combined the functions of a personal digital assistant (PDA) and a mobile phone or camera phone. Today's models also serve to combine the functions of portable media players, low-end compact digital cameras, pocket video cameras, and global positioning system (GPS) navigation units. Modern smartphones typically also include high-resolution touchscreens, web browsers that can access and properly display standard web pages rather than just mobile-optimized sites, and high-speed data access via Wi-Fi and mobile broadband. With such integration of functions, untold numbers of capabilities and functions are now within reach of development and implementation.

Method and apparatus for tagging media with identity of creator or scene

International Business Machines Corporation


A gyro of the type having a multimode optical fiber loop in which light propagates in both directions before being recombined, together with a device constituting a phase conjugate "mirror", wherein the device is a double phase conjugate "mirror" and is disposed in the loop so that the light reaches said device from both sides thereof, with the incident light at each side of the device serving as a pumping wave for phase conjugation of the incident wave arriving at the other side of the device.

Optical fiber gyros are now conventional practice.
In general, as shown diagrammatically in FIG. 1, they comprise a laser emitter module 1 and a detector module 2 connected via a coupler 7 and a Y junction 8 to a looped optical fiber 3, together with modulator means 4 disposed at the input/output ends of the loop, in the vicinity of the point--referenced A in FIG.1--where the ends of the loop 3 come together, said means 4 being controlled by a processor unit 5 to which the output signals from the module 2 are sent.
Such gyros make use of the Sagnac effect which occurs in the loop when the loop is subjected to rotation about its axis.
The wave rotating in the same direction of rotation as that imposed on the loop is subjected to a phase shift .phi..sub.1 of: EQU .phi..sub.1 =KL-2.pi.RL.OMEGA./.lambda.C
where:
K=wave number=2.pi./.lambda.
R=radius of the coil
L=optical path length in the fiber
.OMEGA.=angular velocity
.lambda.=wavelength
C=speed of light
while the wave rotating in the opposite direction is subjected to a phase shift .phi..sub.2 of: EQU .phi..sub.2 =KL+2.pi.RL.OMEGA./.lambda.C
The detector module 2 and the processor unit 5 make it possible, in theory, to measure the phase difference: EQU .phi..sub.2 -.phi..sub.1= 4.pi.RL.OMEGA./.lambda.C
from the output signal, which output signal corresponds to interference between the two waves when they return to point A after travelling along the full length of the coil.
Unfortunately, in reality, the term KL is much greater than 2.pi.RL.OMEGA./.lambda.C, and the ratio between them can be as great as 10.sup.15.
It will be understood that as a result the proper operation of optical fiber gyros requires the optical paths to present perfect reciprocity in both directions, i.e. the term KL in the equation for .phi..sub.1 must be exactly the same as the term KL in the equation for .phi..sub.2.
As a result, optical gyros normally operate only with monomode fibers that conserve polarization. With multimode fibers, the results obtained with a structure of the kind shown in FIG. 1 are disturbed by mixing and interference between the various modes, with each mode corresponding to a different value of L.
Unfortunately, polarization-conserving monomode fibers are much more expensive to manufacture than are multimode fibers.
The invention thus seeks to propose a multimode fiber gyro in which the various modes are recombined correctly, without their various waves interfering with one another.
Proposals have already been made to solve this problem of making multimode fiber gyros with phase conjugation.
It is recalled that phase-conjugating materials (wrongly called phase-conjugate "mirrors") are non-linear materials, e.g. photorefractive crystals, in which interference between an incident wave and a pumping wave creates refractive index gratings. The conjugate wave obtained at the outlet from such a crystal is the result of the pumping wave diffracting on said index gratings.
Unfortunately, the time required to build index gratings is very long compared with the time taken by light to pass through said gratings in photorefractive materials, such that any rapid variation in the parameters of the incident wave is absent from the conjugate wave, even though rapid variations in the parameters of the pumping wave are indeed to be found in the conjugate wave.
That is why the phase-conjugate gyros that have been proposed in the past have long response times.
For example, it can be shown that with phase-conjugate gyro structures of the kinds proposed in:
1! FR 2 503 862--"Dispositif optique interferometrique avec miroir(s) gyro conjugaison de phase, en particular gyrometre laser" Interferometer optical device with phase-conjugate mirror(s), in particular a laser gyro!, C. Borde, CNRS; and
2! Applied Optics, Vol. 25, No. 7, Apr. 1, 1986, "Phase conjugate optic gyro", a phase shift of .DELTA..phi. in the gyro loop that is established for a length of time that is shorter than the response time of the phase-conjugating crystal gives rise, in said phase shift, whether reciprocal or otherwise, to a phase difference of .DELTA..phi. or of--.DELTA..phi. on the detected outlet signal, whereas for a phase shift established for a duration greater than the response time of the crystal, the phase difference in the detected output signal is 2.DELTA..phi..
Similarly, with self-pumped phase-conjugate mirror gyro structures, such as those proposed in:
3! EP 79268 --Michelson type interferometer with a photorefractive mirror.
4! Optics Letters, Vol. 11, No. 10, Oct. 1986, "Self-pumped phase-conjugate fiber optic gyro",
5! Optics Letters, Vol. 12, No. 12, Dec. 1987, "Phase-conjugate multimode fiber gyro", C*W. H. Chen, P. J. Wang;
6! SPIE, Vol. 838, Fiber optic and laser sensors, 1987, "Phase-conjugate fiber optic gyro with multimode fibers"; and
7! Yasuo Tamita, IEEE Journal of quantum electronics, Vol. 25, No. 3, Mar. 1989, "Polarization and spatial recovery by modal dispersal and phase conjugation: properties and applications", a .DELTA..phi. phase shift in the gyro loop established during a length of time that is shorter than the response time of the phase-conjugating crystal gives rise, depending on whether said phase shift is reciprocal or not, to a phase difference of 2.DELTA..phi. or of 0 in the output signal as detected, whereas for a phase shift that is established for a length of time greater than the response time of the crystal, the phase difference in the detected signal is 2.DELTA..phi..
Consequently, prior art gyros and phase-conjugate gyros are incapable of operating with signals at a frequency greater than the frequency which corresponds to the response time of the phase-conjugating crystal.
In particular, such large response times prevent such phase-conjugate gyros being used with phase shift type modulation such as that implemented by the processor unit 5 and the modulator means 4 of the structure of FIG. 1, since such phase shift keying requires fast response times.
Unfortunately, processing by means of phase shift, which makes it possible to ignore the high degree of power non-linearity in the detectors as a function of phase, turns out to be essential for proper operation of present gyros.

Multimode optical fiber gyro with a double phase conjugate mirror