A method and apparatus for storing and accessing a patterned array of data for a storage device, includes inputting the array, an upper bandwidth and a lower bandwidth, defining a band within the array based on the upper bandwidth and the lower bandwidth, areas of the array outside the band contain zero value data elements. The upper bandwidth, the lower bandwidth and data within the band are stored in the storage device, and the array is reproduced based on the upper bandwidth the lower bandwidth and the data within the band.

1. Field of the Invention
The present invention generally relates to a method and apparatus for addressing multidimensional numerical arrays using fixed overhead resources and more specifically to a method and apparatus for accessing very large, general banded numerical arrays with reduced data storage and formatting requirements. Moreover, the invention is for use as a data cache address generator that decreases the processing time of general banded numerical arrays.
2. Description of the Related Art
The workstation and its microprocessor data cache memory are used in a variety of scientific and engineering applications involving very large general banded numerical arrays. For purposes of this application, "very large general banded numerical arrays" are defined as linear systems of equations with hundreds, or more, unknowns where non-zero coefficients are clustered around the diagonal. Current storage methods for these arrays require relatively large amounts of memory capacity.
A microprocessor typically includes one or more fixed- and floating-point data processors and one or more instruction and data caches, all of which are implemented using one or more integrated circuits (ICs), as shown in FIG. 10.
FIG. 10 shows the five major subassemblies of a microprocessor according to the prior art: the central processing unit 10 (CPU), the data cache 11, the instruction cache 12, the system bus 13, and the memory 14. Addresses are transferred along the CPU address bus 19 and data is transferred along the CPU data bus 20. The CPU 10 has one or more fixed point arithmetic logic units (ALUs, not shown) and one or more floating-point arithmetic units (not shown). The instruction address and data address are maintained by the fixed-point processor.
In high performance computers, caches serve to reduce the observed latency to memory. The cache provides a relatively small but high performance memory close to the processor. The data cache is a local microprocessor memory that stores/retains relatively recent operands (e.g., a predetermined number of the most recent operands) and improves microprocessor performance by reducing the need to access (i.e., read or write) the more remote system memory (which typically consumes many microprocessor cycles). Instead of accessing the remote system memory, access can simply be made to the data cache (e.g., typically within one or at most several machine cycles), thereby reducing processing time, as shown in FIGS. 11a and 11c.
The data cache 11 provides copies of data within the memory 14 to the CPU 10. The data cache 11 includes the data cache directory and control 15 (DIR and CNTRL). Both the data cache 11 and the data cache directory and control 15 are random access memories (RAMs). The data cache 11 holds the data. The directory and control 15 holds the address of the data currently in the data cache 11. Variables currently used by the CPU 10 are located in the data cache 11. The contents of the data cache 11 can be stored back to system memory 14 after use.
The instruction cache 12 provides copies of instructions from memory 14 to the CPU 10. The instruction cache 12 includes the instruction cache directory and control 16. The contents of the instruction cache 12 usually are not stored back to system memory 14 since the instructions are not modified by the CPU 10.
The system bus 13 is the electrical connection to the memory 14. The system bus is divided into a data bus 13a, an address bus 13b and a control bus 13c, all having multiple signal lines. Unidirectional buffers 17 and bi-directional buffers 18 prevent interference between the data cache 11 and the instruction cache 12 when either are accessing memory 14. The buffers 17, 18 are controlled by the cache directory and control units 15,16.
FIG. 11(a) shows a "read-hit" cache operation, which occurs when the CPU 10 executes a load register instruction: EQU R.rarw.MEM (ADDR)! {EQ 1}
where the left hand side R is a CPU register, and MEM (ADDR)! is the data from memory as pointed to by the CPU supplied address (ADDR).
FIG. 12 shows the format of a typical address request that may be issued by the CPU 10. The address request appears on the CPU address bus 19 and includes "set bits" and "tag bits" as shown in FIG. 12. The directory and control unit 15 monitors the set bits that appear in the address on the address bus 19 to determine if they match the set bits of the directory and control unit 15. The tag bits contain address information of the associated data that is stored in the cache. If the directory and control unit 15 match the set bits on the address bus to those in the directory, then the data associated with these set bits is stored in the cache and the tag bits provide a cache address of that data. If the set bits on the address bus do not match those in the directory and control unit 15, then the related data is not in the cache.
In the case of a read hit, the set bits in a load request from the CPU 10 match set bits within the directory and control unit 15. After such a match, directory and control 15 disables the address buffers for the system bus, and enables the data cache 11 to load a register within the CPU 10. The register load operation for a read-hit is EQU R.rarw.MEM (ADDR)!.sub.CACHE {EQ 2}
where R is a CPU register and MEM(ADDR)!.sub.CACHE is the data available in the cache at the CPU supplied address (ADDR).
FIG. 11(b) shows a "read miss", where set bit entries in the directory and control 15 do not match the address of the load request shown in Equation 1. In this case, the system bus address buffers are enabled, and the memory provides the data for the CPU register.
Normally, several data elements are read from memory 14 or the data cache 11, starting from the address provided by the CPU 10. This set of data elements is referred to as a "line" of data. The directory and control 15 configures the bi-directional data buffers to receive the incoming data, signals the CPU 10 to load the register with the first incoming data element along with the remainder of the data into the data cache 11. The directory and control 15 also records the set bits and tag bits for the first data element in the line. Thus, the register load operation for a read miss is EQU R.rarw.MEM (ADDR)!.sub.MEMORY {EQ 3}
FIG. 11(C) shows a "write hit", where the set bits in a store request from the CPU 10 match set bits within the directory and control unit 15. After such a match, directory and control 15 enables the address buffers for the system bus, and enables the data cache and memory to store the contents of the CPU register 10. This process is referred to as a "write-through" operation where both the data cache memory and main memory are updated. This operation can be denoted as EQU MEM(ADDR)!.sub.MEMORY .rarw.R
and, EQU MEM(ADDR)!.sub.CACHE .rarw.R {EQ 3.1}
FIG. 11(d) shows a "write miss". Since the directory and control 15 does not have set bits correlating to the register store operation, the data is written only to the system memory 14. This is denoted as EQU MEM(ADDR)!.sub.MEMORY .rarw.R {EQ 3.2}
Data from the much larger, and slower, main memory is automatically staged into the cache on a demand basis, as shown in FIG. 11(b). If the program running on the computer exhibits good locality of reference in the main memory address space, most of the accesses by the processor are satisfied from the cache, and the average memory access time seen by the processor is close to that of the cache (e.g., on the order of one to two cycles). When the processor does not find the requested data in the cache, it incurs a "cache miss penalty", which is a longer access time to the main memory.
For a given cache structure, a program can be characterized by its "cache hit ratio" (CHR) which is the fraction of the accesses that are satisfied from the cache and hence do not suffer the longer latency to main memory. Compressing data improves the CHR and overall microprocessor performance by allowing more of the needed data to fit in the data cache.
Turning now to arrays, a sparse matrix is a two dimensional array that has few non-zero entries relative to the number of zero entries. The zero entries represent the zero coefficients of the linear system, whereas the non-zero entries in the matrix represent coefficients that have a non-zero value. A "band array" is a special type of sparse array where all non-zero elements are contained between two symmetric lines drawn parallel to the diagonal.
FIG. 6 illustrates a conventional band array. The band array contains entries that are zero entries that do not perform a useful function, but consume memory space that could be used for other purposes. This problem creates inefficiencies by unnecessarily using increased memory space and thereby reducing overall speed of the microprocessor.
To solve problems represented by band arrays efficiently, space and time requirements must be minimized. Current storage methods for general band arrays consume a relatively large amount of memory.
The BLAS, or Basic Linear Algebra Subprograms, storage method is illustrated in FIG. 7. In this method, each diagonal in the original matrix becomes a row in the transformed matrix. The BLAS are a set of industry standard Fortran subroutines that perform linear algebra operations. The asterisks shown in FIG. 7 are unused positions that must be stored in order to maintain the regularity of the matrix structure. Therefore, the storage overhead for this method is proportional to the size of the array. The BLAS storage method does not scale to an arbitrary number of dimensions, N.
Different storage representations are needed for different types of band arrays. For example, a dense array represented in the BLAS scheme requires almost twice the memory actually needed to represent all the non-zero array elements. Therefore, different storage schemes are used for various type of arrays (i.e. banded, triangular, dense), and different programs must be written to handle each different type of array. Further, prior to this invention, there was no general, scalable, uniform method to operate on any N-dimensional band array.
The conventional systems do not provide a formally-stated patterned sparse array indexing method that promotes automated handling of array operations (i.e., array operations which are optimized by the compiler for either local or distributed processing).
Moreover, prior to this invention, there was no efficient hardware address generator method that allowed high-speed patterned sparse array processing. Also, prior to this invention, there was no general, scalable method for addressing compressed multi-dimensional patterned sparse arrays.

Method and apparatus for indexing patterned sparse arrays for microprocessor data cache

International Business Machines Corporation


A content addressable memory includes a first plurality of search lines, a second plurality of search lines, a first match line, and a storage location. Each search line of the first plurality of search lines receives a corresponding high voltage level or low voltage level during a match detect operation, and each search line of the second plurality of search lines to receive a corresponding high voltage level or low voltage level during the match detect operation. The storage location of the content addressable memory includes a plurality of CAM cells, each CAM cell a first thyristor and second thyristor.

1. Field of the Disclosure
The present disclosure is related to devices having memory and more particularly to devices have thyristor based memory.
2. Description of the Related Art
Content addressable memories (CAMs) are typically area intensive. A typical CAM uses a Ternary CAM cell requiring as many as 16 transistors. Therefore, a CAM that overcomes this problem would be useful.


A method and system for code generation and inlining. The method includes: scanning a code, where the code includes a method; determining whether the method includes a branch if the method is too large in size to be inlined, where the branch is based on runtime types of argument; profiling runtime types of actual arguments at a call site in the method if the method includes the branch; generating a polymorphic inline cache (PIC) code from a plurality of arguments, where the plurality of arguments are based on a result of the profiling step; generating a specialized method for a frequently appearing combination of the runtime types of argument and arguments that can be invoked from the PIC code; and inlining body of the specialized method into the call site if the specialized method has a body size within a permissible range.

1. Field of the Invention
The Present Invention relates to optimization of an executable code in a programming language processor. More particularly, the Present Invention is related to an inlining technique.
2. Description of Related Art
Dynamic scripting languages such as PHP and more static programming languages such as Java(R) have conventionally been used for programming language processors or execution systems in the server environments. In recent years, in order to allow Java(R) class resources to be readily invoked from PHP and the like, a mechanism has been proposed, where the mechanism declares a class of static language platform from a program in a dynamic scripting language such as PHP to allow untyped accesses on a Java(R) virtual machine or a static language platform. (e.g., common language infrastructure (CLI)).
Particularly, known platforms that operate on Java(R) virtual machine include P8 and Quercus as PHP, JRuby as Ruby, Jython as Python, and Groovy.
Almost all the bytecodes generated by these scripting language processors form a subroutine threading style in order to process language constructs, which can contain complex semantics. A feature of a function or method which is invoked as a subroutine is sometimes referred to as a runtime helper function. Such a subroutine call can be optimized by inlining at least one function or method being invoked and combining the same with other inlined functions or methods.
The following is an example of such inlining. First, assume that the following bytecode has been generated:
 Obj f(Obj a, Obj b, Obj c){load aload binvoke add(Obj,Obj)load cinvoke sub(Obj,Obj) . . .invoke print(Obj) . . .
When the above code is expressed as pseudo-source code for ease of understanding (the same applies below), the following is derived.
 Obj f(Obj a, Obj b, Obj c){print(sub(add(a,b), c)) . . .
Assume that the above code of add(Obj,Obj) which is invoked is as follows.
 Obj add(Obj x, Obj y){ if (x instanceof Int && y instanceof Int){  return new Int(x.getInt( ) + y.getInt( )); } else if (x instanceof Dbl . . . ){  . . . } else if ( . . . ){. . .
Also, assume that the above code of sub(Obj,Obj) being invoked is as follows.
 Obj sub(Obj x, Obj y){ if (x instanceof Int && y instanceof Int){  return new Int(x.getInt( ) − y.getInt( )); }else if (x instanceof Dbl . . . ){  . . . }else if ( . . . ){. . .
If add(Obj x, Obj y) and sub(Obj x, Obj y) are inlined into the original bytecode, evaluation of the common sub-expressions can be performed at once, and generation of intermediate data can be eliminated, leading to increased speed of code execution.
The code of such a subroutine, however, is too large in size to be inlined using a conventional scripting language compiler. Therefore, the size of the inlined code will become too large, and optimization can be hindered within a realistic time frame.
Japanese Unexamined Patent Publication No. 2007-109044 discloses a code conversion program that includes: a dedicated invoked program generation unit which detects an invoked program from a program group, an argument for differentiating processes of the invoked program, and the content of the argument, and generates a program for only executing a process that corresponds to the content of the argument within the processes of the invoked program; a call site detection unit which detects a call site that invokes the invoked program from the program group; and an invoking program rewriting unit which rewrites the call site to invoke the dedicated invoked program generated by the dedicated invoked program generation unit. This technique, however, does not suggest an application for code inlining. Furthermore, in cases where the contents of a plurality of arguments potentially vary, the number of dedicated invoked programs will become too many that corresponds with the number of combinations. It is impractical to do the same at runtime.
Suganama, et al., "An Empirical Study of Method In-lining for a Java Just-in-Time Compiler," Proceedings of the 2nd JVM Symposium, p. 91-104, August, 2002, discloses a technique that inlines a hot path in a large method body. Suganuma's technique, however, cannot be applied to cases where a runtime helper function is invoked from a large number of call sites in different contexts, because the hot path cannot be determined.
Whaley, "Dynamic Optimization through the use of Automatic Runtime Specialization", thesis for MASSACHUSETTS INSTITUTE OF TECHNOLOGY, Can 1999, particularly in Chapter 3.4.16, discusses about predicting the benefit obtained from a code which is specialized on the basis of the parameter type.
Arnold, et al. "A Comparative Study of Static and Profile-Based Heuristics for Inlining", ACM SIGPLAN Notices archive, Volume 35, Issue 7, pp. 52-64, July 2000, discusses profile-based heuristics for inlining.

Method and system for code generation and inlining

International Business Machines Corporation


An article of footwear including a sole structure attached to an upper defining an internal void configured to receive a foot of a wearer is described. The sole structure includes a sole body portion having a central ridge element located in an aperture in the sole body portion. The central ridge element has a bottom surface configured to contact the ground and move vertically within the aperture. The movement of the central ridge element pushes a top surface of the ridge element attached to a portion of the upper against the foot of the wearer. The central ridge element is arranged approximately centrally between lateral and medial sides in the forefoot region of the sole structure. The central ridge element provide sensory feedback about lateral movement and to the foot of the wearer.

The present disclosure is directed to an article of footwear and, more particularly, to an article of footwear and a sole structure having ridge elements located along a sole perimeter.
Conventional articles of athletic footwear include two primary elements, an upper and a sole structure. The upper provides a covering for the foot that comfortably receives and securely positions the foot with respect to the sole structure. The sole structure is secured to a lower portion of the upper and is generally positioned between the foot and the ground. In addition to attenuating ground reaction forces (that is, providing cushioning) during walking, running, and other ambulatory activities, the sole structure may influence foot motions (for example, by resisting pronation), impart stability, and provide traction, for example. Accordingly, the upper and the sole structure operate cooperatively to provide a comfortable structure that is suited for a wide variety of athletic activities.
The upper is often formed from a plurality of material elements (for example, textiles, polymer sheets, foam layers, leather, and synthetic leather) that are stitched or adhesively bonded together to define a void or cavity on the interior of the footwear for comfortably and securely receiving a foot. More particularly, the upper forms a structure that extends over instep and toe areas of the foot, along medial and lateral sides of the foot, and around a heel area of the foot. The upper may also incorporate a lacing system to adjust fit of the footwear, as well as permit entry and removal of the foot from the void within the upper. In addition, the upper may include a tongue that extends under the lacing system to enhance adjustability and comfort of the footwear, and the upper may incorporate a heel counter or other stabilizing structure.
In some cases, cushioning provided by a sole structure, while attenuating ground reaction forces, may undesirably reduce sensory feedback by isolating the foot of the wearer from the ground contact. Therefore, there exists a need in the art for a sole structure that includes provisions for increasing sensory feedback to a foot of a wearer.

This patent is subject to a terminal disclaimer.

Article of footwear and sole structure with a central forefoot ridge element


Provided is a method and apparatus for reducing transmission of location information when tracking the geographic location of one or more mobile devices. A mobile device generates location information using GPS technology and provides the location information to a communication device on an ongoing basis. In a first embodiment, if the location information of the mobile device is not needed, then the communication device transmits a message indicating that the location information of the mobile device is not needed. Upon receiving the message, the mobile device stops providing location information to the communication device on the ongoing basis. This can reduce the amount of information that gets transferred over the air between users sharing their location information.

A location-based service (LBS) is an information and entertainment service that makes use of the geographical position of one or more mobile devices. Some applications involves tracking the geographic location of one or more mobile devices. In order for a communication device to track the location of a mobile device, the communication device receives location information from which the geographical location of the mobile device can be determined. The location information can be generated by the mobile device using GPS technology or by other means. The communication device can receive location information on an ongoing basis in order to keep up to date on the geographical location of the mobile device.
In order to accurately track the geographical location of the mobile device, location information might be provided rather frequently, for example every few seconds. Unfortunately, this can involve a lot of messaging. Excessive messaging can be costly in terms of network utilization and power consumption for the mobile device. If the communication device performing the tracking is also mobile, then power consumption for the communication device is also a concern.
This problem can be worsened if the communication device is tracking more than one mobile device. Tracking the geographic location of several different mobile devices increases the number of messages involved.

Method and apparatus for reducing transmission of location information


In a perpendicular magnetic recording medium in which at least a soft magnetic underlayer, an orientation control layer, a magnetic recording layer and a protective layer are formed on a non-magnetic substrate in order from the bottom, the orientation control layer has a laminated structure of two or more layers including an intermediate layer and a seed layer which is disposed closer to the non-magnetic substrate than the intermediate layer. The seed layer includes two or more kinds of elements having a face-centered cubic structure, has face-centered cubic (111) plane crystals oriented in a direction perpendicular to a substrate surface, and has a pseudo-hexagonal structure.

1. Field of the Invention
The present invention relates to a magnetic recording medium, a method of manufacturing the magnetic recording medium, and a magnetic recording reproducing apparatus using the magnetic recording medium.
2. Description of the Related Art
In recent years, the range of applications of magnetic recording apparatuses such as magnetic disk drives, flexible disk drives and magnetic tape apparatuses has markedly increased, and the importance of such apparatuses has increased. Also, the recording density of magnetic recording media which are used in such apparatuses is now increasing greatly. In particular, a steeper increase in surface recording density followed the introduction of a magneto-resistive (MR) head and a partial response maximum likelihood (PRML) technique. Also in recent years, the introduction of a giant magneto-resistive (GMR) head and a tunneling magneto-resistive (TuMR) head has led to significant increases in the surface recording density of magnetic recording media.
In addition, there is a demand for achieving a high coercive force, a high signal-to-noise ratio (SNR) and a high resolution of a magnetic recording layer in order to achieve a further increase in the recording density of magnetic recording media in the future.
In a widely used longitudinal magnetic recording system, self-demagnetization, that is, recording magnetic domains adjacent to each other in a transition region of magnetization weakening each other's magnetization, becomes dominant as linear recording density is increased. Accordingly, in the longitudinal magnetic recording system, it is necessary to make a magnetic recording layer thin in order to avoid self-demagnetization and increase shape magnetic anisotropy. However, when the film thickness of a magnetic recording layer is reduced, the magnitude of an energy barrier for maintaining magnetic domains and the magnitude of thermal energy become so close in level to each other that a phenomenon (thermal fluctuation phenomenon) in which the recorded amount of magnetization is relaxed due to the influence of temperature cannot be ignored. This is regarded as a determinant of the linear recording density.
In such circumstances, an anti-ferromagnetic coupling (AFC) medium has recently been proposed as a technique to meet the demand for improving the linear recording density in the longitudinal magnetic recording system, and efforts are being made to avoid the thermal magnetic relaxation problem with longitudinal magnetic recording.
A perpendicular magnetic recording system is attracting attention as a promising technique for achieving a further increase in surface recording density. Whilst a known medium is magnetized in an in-plane direction in the conventional longitudinal magnetic recording system, the perpendicular magnetic recording system is characterized by magnetization in a direction perpendicular to a medium surface. Accordingly, the perpendicular magnetic recording system is thought to be more suitable for high-density recording because it is possible to avoid the influence of self-demagnetization, which is a hindrance to achievement of high linear recording density in the longitudinal magnetic recording system. In addition, the perpendicular magnetic recording system is thought to be comparatively unsusceptible to thermal magnetic relaxation, which is a problem with longitudinal magnetic recording, because it is possible to maintain a certain magnetic layer thickness.
In ordinary cases, when a perpendicular magnetic recording medium which uses a perpendicular magnetic recording system is manufactured, an orientation control layer, a magnetic recording layer, and a protective layer are formed in this order on a non-magnetic substrate. In some cases, a lubricating layer is applied on a surface of the protective layer. Moreover, in general, a soft magnetic film called an underlayer is formed under the orientation control layer. In the orientation control layer, a seed layer and an intermediate layer are laminated in order from the substrate side. The intermediate layer is formed for the purpose of improving the characteristics of the magnetic recording layer. The seed layer is regarded as having the functions of aligning crystals in the intermediate layer and the magnetic recording layer and of controlling the shape of the magnetic crystals.
The crystal structure of the magnetic recording layer is important in order to manufacture a perpendicular magnetic recording medium having excellent characteristics. That is, in many cases, a hexagonal close-packed (hcp) structure is employed as the crystal structure of a magnetic recording layer in a perpendicular magnetic recording medium. However, it is important that a hexagonal close-packed (hcp) (002) crystal plane be parallel to a substrate surface, in other words, that crystal c-axis [002] axes be aligned in the perpendicular direction with as little disturbance as possible.
However, whilst a perpendicular magnetic recording medium has an advantage in that a comparatively thick magnetic recording layer can be used, the total film thickness of all the laminated thin films in the medium tends to increase in comparison with the current longitudinal magnetic recording medium, so there is a disadvantage in that the medium layer laminating process includes a factor responsible for disturbance in the crystal structure.
Conventionally, in order to align crystals in a magnetic recording layer with as little disturbance as possible, Ru, which employs an hcp structure, has been used as an intermediate layer in perpendicular magnetic recording media, in the same way as in a magnetic recording layer. Since crystals in the magnetic recording layer are epitaxially grown on a Ru (002) crystal plane, a magnetic recording medium having excellent crystal orientation is obtained (see, for example, JP-A 2001-6158).
In addition, a seed layer positioned under an intermediate layer is required to improve the crystal orientation of the intermediate layer. For this, a seed layer employing a face-centered cubic (fcc) structure has been used (see, for example, JP-A-2002-109720). In this case, a (002) crystal plane which has an hcp structure in an intermediate layer is preferentially oriented on the orientation of a (111) crystal plane which has an fcc structure. In this manner, the total film thickness for obtaining the same orientation can be reduced more than in the case in which Ru, as an intermediate layer, is directly formed on an underlayer.
JP-A-2005-190517 describes that Ti, Au-50Cu having an hcp structure is used for a first intermediate layer, Ag-40Cu having an fcc structure is used for a second intermediate layer, and Ru is used for a third intermediate layer on an underlayer.
JP-A-2004-46990 describes that a material of a composition employing a C11b structure is used as an orientation control film. As the orientation control film employing the C11b structure, a material including at least one or two or more kinds of Al, Ag, Au, Cu, Ge, Hf, Ni, Si, Ti, Zn and Zr are described.
However, the conventional seed layer is insufficient to obtain a perpendicular magnetic recording medium having excellent recording and reproducing characteristics. A perpendicular magnetic recording medium is desired which is capable of maintaining writing ability at the time of recording by reducing the film thickness between a soft magnetic underlayer and a magnetic recording layer; achieving an improvement in the crystal orientation of the magnetic recording layer and the uniformity and reduction in the crystal grain diameter; and being easily manufactured.
For example, as in JP-A-2002-109720, it is necessary to thickly set the film thickness of a seed layer to a certain thickness (10 nm or greater) in order to improve the crystal orientation of a magnetic recording layer when a material having an hcp structure is used for the seed layer. However, when the seed layer is made of a non-magnetic material and the film thickness of the seed layer is increased, the distance between the magnetic recording layer and a soft magnetic underlayer is increased, thus weakening the attraction of magnetic flux from a recording head at the time of recording and reducing writing ability.
On the other hand, when a material having an fcc structure is used as the seed layer, the crystal orientation of the magnetic recording layer can be improved to a certain level even if the film thickness is about 5 nm. However, when the material having an fcc structure is used as the seed layer, a problem occurs in that the crystal grain diameter of the seed layer is increased along with the improvement in the crystal orientation of the magnetic recording layer. In general, one crystal in an intermediate layer and one crystal in a magnetic recording layer are sequentially grown on one crystal of a seed layer, and thus an increase in the crystal grain diameter of the seed layer means an increase in the crystal grain diameter of the magnetic recording layer. When a crystal grain diameter of the magnetic recording layer is increased, a recording bit transition border is not formed in a smooth straight line and this causes problems when improving recording density. In this manner, when a seed layer having an fcc crystal structure is used, it is difficult to achieve both an improvement in the crystal orientation of a magnetic recording layer and uniformity and reduction in the crystal grain diameter of the magnetic recording layer.
However, in order to further improve surface recording density, it is essential to achieve high crystal c-axis orientation in the magnetic recording layer and uniformity and reduction in the crystal grain diameter of the magnetic recording layer.

Magnetic recording medium, method of manufacturing magnetic recording medium and magnetic recording reproducing apparatus


A method for forming a metal filled semiconductor feature with improved structural stability including a semiconductor wafer having an anisotropically etched opening formed through a plurality of dielectric insulating layers revealing a first etching resistant layer overlying a conductive area; a plurality of dielectric insulating layers sequentially stacked to have alternating etching rates to a preferential etching process; subjecting the anisotropically etched opening to the preferential etching process whereby the sidewalls of the anisotropically etched opening are preferentially etched to produce etched dielectric insulating layers to form roughened sidewall surfaces; anisotropically etching through the etching resistant layer to reveal the conductive area; and, filling the anisotropically etched opening with a metal to form a metal filled semiconductor feature.

In typical multilayer semiconductor device the uppermost layers which are electrically interconnected with underlying layers by way of, for example, vias, additionally include bonding pads for forming electrical connection with the semiconductor device (chip) surface to a package which contains the chip. The bonding pads are typically formed in an array on the individual die or chips likewise forming an array on the semiconductor wafer surface.
In forming wire bonding pads on the chip upper surface for subsequent wire bonding from the chip to a package frame by various techniques, a conductive area, for example copper, is covered by a series of passivation layers in which an opening is subsequently anisotropically etched to form closed communication with the copper conductive area and filled with another metal, for example aluminum or an aluminum/copper alloy.
For example, referring to FIG. 1A is shown a portion of a multilevel semiconductor device including a stage in formation of a bonding pad including conductive area 11A formed in dielectric insulating layer 11B having an overlying silicon oxynitride or silicon nitride etching stop liner 12. Overlying the etching stop liner 12 is a passivating dielectric insulating layer 14 typically formed of undoped silica glass (USG) with an overlying layer of silicon nitride 16. A photoresist layer 18A is deposited and photolithographically patterned to form an opening 18B for anisotropically etching a bonding pad opening.
Referring to FIG. 1B, the bonding pad opening 20A is anisotropically etched through the silicon nitride layer 16 and the USG layer 14 to form closed communication with the etching stop liner 12. Referring to FIG. 1C, the photoresist layer 18A is then removed by a plasma ashing process and another anisotropic etching step is carried out to etch through the etching stop liner 12 to reveal the underlying conductive 11A to complete the formation of bonding pad opening 20A. Referring to FIG. 1D, the bonding pad opening is filled with an aluminum or aluminum copper alloy to form wire bonding pad 20B.
One problem with the prior art method of formation of wire bonding pads is that adhesion of the metal bonding pad, for example aluminum or aluminum/copper alloy, to the passivation layers is poor. As a result, during wire bonding operations including for example, thermocompression or thermosonic wire bonding, a downward compressive force is exerted causing some deformation of the bonding pad as well an upward force on removing the wire bonding stylus. The bonding pad is further subjected to a variety of other stresses during the packaging process including stresses caused by heating and cooling together with thermal coefficients of expansion mismatches between the various materials. Frequently, the exposure of the wire bonding pad to repeated stresses causes peeling of the bonding pad due to poor adhesion of the wire bonding pad the passivation layers and to the underlying conductive area, for example, copper. As a result, chip yields are reduced leading to costly re-working procedures.
There is therefore a need in the semiconductor processing art to develop a method whereby metal filled semiconductor features are formed to improve structural stability to avoid or prevent peeling during subsequent processing steps.
It is therefore an object of the invention to provide a method whereby metal filled semiconductor features are formed to improve structural stability to avoid or prevent peeling during subsequent processing steps while overcoming other deficiencies and shortcomings of the prior art.

Metal filled semiconductor features with improved structural stability

Taiwan Semiconductor Manufacturing Co., Ltd.


The invention relates to a loading device having N loading heads offset by N/360°, wherein N is the number 3 or an integer multiple thereof, wherein each of the N loading heads has a connecting device for a hose arranged at the upper end, through which hose the catalyst material can be delivered from above, wherein each of the N loading heads has a deflecting cone with the tip pointing upwards beneath the connecting device and joined to the connecting device, a vertical holder is mounted on the underside of said deflecting cone, at least two circular deflector funnel elements are mounted on the vertical holder by means of horizontal braces, the deflector funnel elements open more narrowly at the top than at the bottom, gaps are provided between the deflector funnel elements and the lower deflector funnel elements have a larger diameter than the deflector funnel elements above them.

Typically, for the production of ammonia in synthesis plants that operate in accordance with the Haber-Bosch process, use is made of ammonia reactors which, depending on the synthesis concept, contain up to three catalyst beds. The reactors consist of cylindrical pressure vessels and comparatively complicated internal constructions, the converter inserts, for receiving the catalyst beds and optionally heat exchangers. On account of the high pressure level of the synthesis of usually more than 200 bar, the diameters of the pressure vessels are kept as small as possible and the catalyst beds are arranged one beneath another along the container vessel axes. This arrangement has the consequence that the accessibility of the catalyst beds that are further away from the apparatus cover is highly restricted and filling with the catalyst material is rendered more difficult.
As a result of the different plant capacities and process engineering conditions, the catalyst beds have very different dimensions. On account of the efficiency with regard to the overall size and the pressure loss, the radial type of construction prevails nowadays, i.e. the catalyst beds are in the form of hollow cylinders and are flowed through in the radial direction.
In the case of continuous "hose loading", as it is known, in which the reactor beds are filled with catalyst via one or more hoses, only average bulk densities that are beneath the required value for the synthesis reaction are achieved. Therefore, the catalyst beds have hitherto been filled using the batchwise stratified loading method, that is to say catalyst layers of 250-300 mm are introduced using a hose and subsequently compacted, by means of concrete vibrators and other vibrators, to the required bulk density of at least 2.8 kg/l of oxidized catalyst, or 2.3 kg/l in the case of pre-reduced, that is to say specifically lighter catalysts. The vibration of a layer can take more than an hour depending on the bed geometry.
This procedure is acceptable when new plants are filled for the first time, since the operations take place during preparation for start-up and are not on the time-critical path, that is to say do not result in expensive production stoppages.
However, during a catalyst change, the catalyst-changing operations usually take place on the time-critical path and can be decisive for the length of the downtime. For conventional catalyst-containing vessels, it is conventional in such cases to use the "dense loading" method, as it is known, to effect the desired bulk density in a continuous loading method without an interposed compaction step, and in this case the catalyst can be introduced in a correspondingly quicker manner.
In terms of phenomena, the difference in the achievable bulk densities between hose loading and dense loading can be explained in that during hose loading a large number of particles drop onto a small area in a short period of time, wherein the particles obstruct one another in the event of arrangement in a dense packing structure, whereas in dense loading a large number of particles drop onto a larger area in a short period of time, with the result that the particles have enough space and time to be arranged in a denser packing structure.
A large number of systems and methods for dense loading are known from the prior art. For example, US 2010/0019952 A1 describes, in which a rotating distribution system is arranged in the top of a catalyst vessel, said system distributing the dropping catalyst particles uniformly over the cross section of the reactor area, wherein the distribution system is fixed at the top. EP 1 152 967 B1 describes a similar system in which the speed of rotation of the rotating distribution system is adapted such that, as the level of the bed increases, the particles can still be thrown into the outer region of the bed without, however, striking the vessel wall.
U.S. Pat. No. 5,687,780 describes a system in which a rotating distribution system is likewise arranged in the top part of a catalyst vessel, said system distributing the dropping catalyst particles uniformly over the cross section of the reactor area, wherein the system can be displaced axially, however, thereby reducing the dropping height of the particles. EP 1 687 223 B1 describes such a system, which additionally operates with gas jets which drive the rotating distribution system and also influence the paths of the particles.
GB 2 287 016 A describes a system which is likewise arranged in the top of a catalyst vessel, said system distributing the dropping catalyst particles uniformly over the cross section of the reactor area, and in which the system can also be lowered and positioned in the reactor. The system is not rotatable and has vanes which project at different angles and which effect the uniform distribution of the particles.
These mentioned dense loading systems and also all further dense loading systems that are known from the prior art are not usable in ammonia synthesis reactors which are flowed through radially, since there is no top-side access and neither are the reactors which are flowed through radially able to be filled at all centrally along their axis of symmetry, since they are bounded on both sides in the radial direction by grid structures. Design details further constrict the clearances within the beds and thus impede accessibility for the loading systems. At the same time, specifically in reactors which are flowed through radially, it is particularly important for the particles not to be able to slip down during operation, since otherwise short-circuit currents would arise in the upper region of the radial bed.


The present invention is a method for the color correction of digital images that have been compressed. In a preferred embodiment, aspects of the color correction are carried out on the compressed image data to improve computational efficiency. One of a number of alternative methods is employed to accomplish the color correction on lossy or losslessly compressed images. The color transformation process accomplishes color correction on compressed image data in conjunction with compression or decompression operations. A second, simplified phase of the color correction may be applied subsequently to the decompressed image data in certain embodiments. Accordingly, the technique has application to any number of color imaging systems, including digital printers and copiers where there is a necessity to color correct compressed digital images.

The present invention is directed to improving the efficiency of color correction operations. In particular, this invention capitalizes on the need to store digitized images in a compressed format, and incorporates color correction with compression or decompression operations so as to accomplish certain aspects of color correction on compressed images in a computationally efficient manner.
Data compression is required in data handling processes, where too much data is present for practical applications using the data. Commonly, compression is used in communication links, to reduce the transmission time or required bandwidth. Similarly, compression is preferred in image storage systems, including digital printers and copiers, where "pages" of a document to be printed are stored temporarily in precollation memory. The amount of media space on which the image data is stored can be substantially reduced with compression. Generally speaking, scanned images, i.e., electronic representations of hard copy documents, are often large, and thus make desirable candidates for compression.
The present invention has application to both lossy and lossless compression schemes. The DCT (Discrete Cosine Transform), a variable-length encoding standard, disseminated by the JPEG committee, is a lossy compression scheme which reduces data redundancies based on pixel to pixel correlations. The Lempel-Ziv scheme is for lossless compression, including for example, the LZW scheme described in the U.S. Pat. No. 4,558,302 and U.S. Pat. No. 4,814,746 patents. Like LZW, the Huffman scheme and other lossless compression equivalents are capable of compressing data without any loss of image data, albeit typically at a compression ratio that is lower than that for lossy compression. Generally, an image does not change very much on a pixel to pixel basis and therefore has what is known as "natural spatial correlation". In natural scenes, correlation is generalized, but not exact. Noise makes each pixel somewhat different from its neighbors, but the natural spatial correlation enables not only the compression of digital image data, but the performance of certain image processing operations on the compressed data. Contrariwise, in synthetic graphics and computer-generated text, the correlation tends to be much higher, with colors limited to a small set. The limited set of colors and high correlation make these image types good candidates for lossless compression, at possibly higher compression ratios than those achievable with lossy compression schemes.
Heretofore, a number of patents and publications have disclosed image compression and color correction, the relevant portions of some may be briefly summarized as follows:
U.S. Pat. No. 5,408,425 to H. S. Hou, issued Apr. 18, 1995, hereby incorporated by reference for its teachings, discloses a processor and method of computation for performing a discrete cosine transform.
U.S. Pat. No. 5,31 9,724 to S. M. Blonstein et al., issued Jun. 7, 1994, teaches an apparatus and corresponding method for compressing still images while remaining compatible with a JPEG transformation.
U.S. Pat. No. 4,275,413 to Sakamoto et al. discloses a color space transformation where information is placed into lookup tables and stored in a memory--where the lookup table relates input color space to output color space. Sakamoto teaches a "unit cube interpolation unit" having known vertices. The lookup table is commonly a three dimensional table since color is typically defined with three variables.
U.S. Pat. No. 5,581,376 to Harrington teaches the conversion of input device signals Rs, Gs, Bs, generated by an image input terminal, to colorimetric values Rc, Gc, Bc, the colorimetric values being processed to generate address entries into a lookup table to convert them to Cx,Mx,Yx,Kx colorant signals or any multi-dimensional output color space, which includes but is not limited to CMYK or spectral data. Values not directly mapped may be determined using tetrahedral interpolation over a hexagonal lattice where the lattice is formed by offsetting every other row in at least one dimension.
In accordance with the present invention, there is provided a method for performing color correction of a compressed digital image, comprising the steps of: retrieving from memory a compressed unit of image data; partially decompressing the compressed unit to produce a partially decompressed unit representing part of the information describing a region of the image in a first color space; performing color correction on the partially decompressed unit to produce a corrected unit in the first color space; subsequently decompressing the entire corrected unit to produce decompressed, corrected image data; and converting the decompressed, corrected image data into a second color space image for rendering.
One aspect of the invention deals with a basic problem in digital image processing systems--the memory and computationally intensive operations of image processing, particularly color correction. This aspect is further based on the discovery of a technique that alleviates this problem. The technique accomplishes the color conversion of an image segment or block while it is in a digitally compressed form--produced by lossy or lossless compression operations.
This technique can be implemented, for example, by the modification of basic JPEG or LZW compression engines, where correction operations are performed on the compressed image data (compressed units). Accordingly, the technique has application to any number of systems, including digital printers and copiers where there is a requirement to provide color correction of the digital image. A machine implementing the invention can include a data or image processing system having the capability of image compression. The techniques and system described herein are advantageous because they are efficient and result in the ability to accomplish basic image processing with little additional hardware or processing as compared to other memory intensive approaches.


The present invention is a self-measuring container that dispenses only a specific amount of fluid each time fluid is poured from the container. This container has a storage chamber where the fluid initially resides and a measuring/dispensing chamber, below the storage chamber, where the specific amount of the fluid that will be dispensed during the next pouring operation resides. An aperture at one end of the container connects the storage and dispensing chambers. This aperture permits the fluid in the storage chamber to flow into the dispensing chamber. The container dispenses the fluid through an exit channel that extends from the dispensing chamber to the top of the container. The storage chamber bottom serves to separate the storage and dispensing chambers and acts as a barrier during a pouring operation to prevent fluid from flowing from the storage chamber to the dispensing chamber until desired. In another embodiment, the storage and dispensing chamber do not have a common wall, but the dispensing chamber is formed to minimize the draw necessary during the formation process. The measuring chamber may also contain a diaphragm to permit the volume within the chamber to be adjusted.

This invention relates to an apparatus for containing and dispensing fluid and more particular to a container having an integral measuring device for dispensing a predetermined volume of liquid.
The use of fluid products pervades all aspects of life. There are many types of containers that hold these products. For many applications, the entire contents of a container may be used at one time. For other applications, only a small amount of the fluid product may be required for an application, such as washing detergent, bleach, fabric softener, drain opener, floor wax, cooking oil, lubrication oil, insecticide, etc. In cases where only a small amount of the product is required at any one time, there is usually a need to measure the amount of the product to use in that application. One common measuring means utilizes the container cap as the measuring device. The cap may have a built-in cup with various graduations or xe2x80x9cfill linesxe2x80x9d representing different fluid volumes. Other containers may have graduations along the side to assist in dispensing a desired amount of fluid. Where such measuring aids are not incorporated into the container itself, one may have to find other means to measure the amount of fluid necessary for a specific application. The extra time and effort needed to find and utilize a suitable measuring device presents added difficulties. The procedure of pouring the fluid from the storage container to a measuring container and then to the container in which the fluid is to be utilized is a tedious and time-consuming process. In addition, because of the variations in the size and shape, sight-measuring aids such as this can yield inaccurate and imprecise results.
There are many different containers that dispense fluid in measured amounts, where the container holds a substantially greater amount of the fluid relative to the dispensed amount. Many of these devices have the capacity to store, measure and dispense fluids without the need for sight measuring. Such characteristics are desirable especially when contact with the fluid could be harmful to humans, such as poisons, bleach, etc. Typically however, prior art devices capable of dispensing a measured volume of fluid are unduly complex in design and manufacture, undependable and expensive. It is this complexity and multi-peice design that prevents prior art devices from being profitable and thus not marketable in today""s competitive environment.
Specifically, many such pouring devices have been made which themselves combine the pouring function and the measuring function so that as the pouring operation proceeds, a fixed volume of fluid will be dispensed with each pouring operation. However, many of these devices are bulky and have complicated inner structures. In addition, the complexity of the device make it difficult and expensive to manufacture. Further, many of these devices are undependable and inaccurate when attempts are made to rapidly and successively dispense fluid therefrom in controlled quantities. Therefore, there remains a need for a one step self-measuring container that can reliably dispense a specific amount of fluid while at the same time having a simplified one-piece body structure which facilitates manufacturing.
It is an object of the present invention to provide a container that dispenses a specific amount of fluid during each pouring operation.
It is another objective of the present invention to provide a self-measuring dispensing container in which the amount of measured fluid to be dispensed can be adjusted.
It is another objective of this invention to provide a self-measuring dispensing container that is only one piece.
It is a fourth objective of the present invention to provide a container that automatically measures a specific amount of the fluid in the container for pouring.
It is a fifth objective of the present invention to provide such a container that when blow molded, requires a reduced draw ratio.
It is a sixth objective of this invention to provide a such container with the potential for a low pour angle configuration.
It is a seventh objective of this invention to provide such a container with smooth sides for increased effectiveness in labeling.
The present invention is a container that dispenses only a specific amount of a fluid substance each time the fluid is poured from the container. This container has a storage chamber or reservoir where the fluid initially resides and a dispensing chamber, below the storage chamber, where the specific amount of the fluid that will be dispensed during the next pouring operation resides. An aperture at one end of the container connects the storage and dispensing chambers. This aperture permits the fluid in the storage chamber to flow into the dispensing chamber. The container dispenses the substance through an exit channel that extends from the dispensing chamber to the top of the container. A second channel provides a vent to the storage and dispensing chamber. A diaphragm adjacent the dispensing chamber may be incorporated to permit the volume of said chamber, and hence the volume of liquid measured therein, to be adjusted. Additionally, a low draw ratio (depth/width of draw) feature may be included in the bottom of the container to form the dispensing chamber to allow increased ease of manufacturing and to facilitate the changing of the dosing volume at the manufacturing level.
In operation, the container is initially filled with a fluid. In an upright position, the fluid in the storage chamber will flow into the dispensing chamber until the dispensing chamber is full. During a pouring operation, the container is tilted to pour the fluid from the dispensing chamber. The fluid in the dispensing chamber will exit the container through the exit channel. The tilted position of the container and the bottom of the storage chamber prevent any of the fluid in the storage chamber from flowing into the dispensing chamber and through the exit channel. After the pouring operation ends, the container is repositioned to an upright/vertical position. As the tilt angle decreases during the repositioning of the container, the fluid in the storage chamber again begins to flow into the now empty dispensing chamber. The flow of fluid into the dispensing chamber will continue until the dispensing chamber becomes full. The container is then ready for the next pouring operation.


A data processing apparatus is provided which is configured to select 2M selected identifiers within a possible range of up to 2N identifiers, where M≦N. The data processing apparatus comprises a selection storage unit configured to store at least N+1 identifier selection bits, wherein a position of a first marker bit in the at least N+1 identifier selection bits determines M, and an identifier selection unit configured to determine the 2M selected identifiers. The 2M selected identifiers fall within a range defined by a base identifier and a ceiling identifier. N-M bits of the N+1 identifier selection bits form N-M bits of the base identifier, and M zeroes form a further M bits of the base identifier. The ceiling identifier corresponds to the base identifier, except that the M zeroes of the base identifier are replaced by M ones.

1. Field of the Invention
The present invention is concerned with the selection of a subset of identifiers from within a range of identifiers. In particular the present invention is concerned with the selection of 2M identifiers within a range of up to 2N identifiers, where M is less than or equal to N.
2. Description of the Prior Art
There may be various situations in which it is required to select a subset of identifiers from a range of identifiers, for example in a tracing unit which monitors the activity of a processor core, the processor core may be configured to issue data indicative of its activities to the tracing unit over a number of different channels. In such a situation, it may be desired to filter those channels, so that only a subset of all possible channels are actively monitored and have their associated information converted into a trace stream for output. Another such situation is the use of a large number of addresses, where it is desired to monitor only a subset of those addresses, for example in a watchpoint unit embedded within a processor core. Typically such identifiers are defined by a sequence of bits, such that up to 2N identifiers may be defined by N bits.
In order to select a subset of identifiers (e.g. the above mentioned channel or addresses) various techniques are known. For example, it is known to configure a register to define an identifier of interest, such that when use of that identifier occurs a match with the identifier as defined in the register may trigger a suitable response. More generally, it is known to provide a number of such registers corresponding to a number of identifiers of interest, such that when any of those identifiers are used the corresponding response may be triggered. However, this approach has the disadvantage that if a large number of identifiers form the subset of interest it will be necessary to provide a corresponding large number of registers defining those selected identifiers. In other words, this approach can be expensive to implement in hardware.
It is also known to select a range of identifiers by defining a starting identifier and an end identifier, using a register for each, wherein any identifier falling within the range spanned by the start identifier and end identifier is selected. However, this approach not only requires two registers of equal size to the identifier space to identify the upper and lower limit, but also further and more complex comparison units configured to determine if a given identifier falls within the range. In other words, this approach can be expensive to implement in hardware.
It is also known to select a range of identifiers by defining a base identifier and a window size, for example a N-bit base identifier and a log2(N) bit window size. However, this approach requires a configuration register for each, and further logic to determine if a given identifier falls within the defined window. In other words, this approach can be expensive to implement in hardware.
In some situations where such a subset of identifiers is required to be monitored, for example in system-on-chip (SoC) arrangement, space may be at a premium, and consequently it is desirable to be able to define and identify the subset of identifiers as efficiently as possible.
Hence it would be desirable to provide an improved manner of efficiently selecting a subset of identifiers from within a possible range of up to 2N identifiers.


Image degradation that can occur in a flat-panel CRT display as a result of electron deflection caused by energy flowing through a spacer system (16) in the display is alleviated by appropriately controlling thermal, electrical, and dimensional parameters of the spacer system. In particular, spacer parameter C is selected to be low. Parameter C equals .alpha..sub.AV h.sup.2 /f.kappa..sub.AV, where .alpha..sub.AV is the average thermal coefficient of electrical resistivity of the spacer system, h is the height of the spacer system, .kappa..sub.AV is the average thermal conductivity of the spacer system, and f is the fraction of the spacer cross-sectional area to the display's active area. Parameter C is normally 6.times.10.sup.--5 m.sup.3 /watt or less. Height h is normally 0.3 mm or more.

A flat-panel CRT display basically consists of an electron-emitting device and a light-emitting device. The electron-emitting device, commonly referred to as a cathode, contains electron-emissive elements that emit electrons over a wide area. The emitted electrons are directed towards light-emissive elements distributed over a corresponding area in the light-emitting device. Upon being struck by the electrons, the light-emissive elements emit light that produces an image on the viewing surface of the display.
The electron-emitting and light-emitting devices in a flat-panel CRT display are connected together, typically through a largely annular outer wall, to form a sealed enclosure having an active region in which the electrons travel from the electron-emitting device to the light-emitting device. For the display to operate efficiently, the pressure in the sealed enclosure needs to be very low, typically a high vacuum of 10.sup.-6 torr or less. The exterior-to-interior pressure differential across the display is thus typically close to 1 atm.
The electron-emitting and light-emitting devices of a flat-panel CRT display are usually quite thin. In a flat-panel CRT display of significant viewing area, e.g., at least 10 cm.sup.2, the electron-emitting and light-emitting devices are normally incapable of resisting the exterior-to-interior pressure differential on their own. Accordingly, a spacer (or support) system is typically provided inside the sealed enclosure to prevent air pressure and other external forces from collapsing the display. The internal spacer system also maintains a relatively uniform spacing between the electron-emitting and light-emitting devices.
The spacer system typically consists of a group of laterally separated spacers positioned so as to not be visible on the display's viewing surface. The spacers can be shaped in various ways such as walls or posts. Regardless of how the spacers are shaped, electron flow through the display occurs in portions of the active region not occupied by the spacers.
The presence of the spacer system can adversely affect the electron flow. For example, electrons can occasionally strike the spacer system, causing it to become electrically charged. The potential field in the vicinity of the spacer system changes. Consequentially, the electron trajectories are affected, often leading to degradation in the image produced on the viewing surface. As discussed in Spindt et al, U.S. Pat. No. 5,532,548, and Schmid et al, U.S. Pat. No. 5,675,212, electrodes are typically provided along the faces of the walls of a spacer system to overcome certain adverse affects that arise from the presence of the spacer walls.
In short, spacer system design is a critical part of overall flat-panel CRT display design. The spacer system is subjected to a variety of environmental conditions. It is important that the spacer system be capable of accommodating a wide range of environmental conditions without causing image degradation.

Flat-panel display having temperature-difference accommodating spacer system


A system for providing a constant current to airport or airfield signs is disclosed. The system receives input currents of varying amperages which also supply, and allow dimming of, runway or taxiway lights. According to various exemplary embodiments of the present invention, a high power factor is achieved which provides greater cost efficient operation of the signs.

The present invention generally relates to circuitry for supplying current to electrical devices. More specifically, the present invention relates to circuitry for supplying a constant current to airport signs so as to maintain a uniform brightness despite varying input currents.
Typically, airports or airfields have numerous electrical devices and systems which are used to guide airplanes and personnel through the increasingly complex maze of runways and taxiways. Such electrical devices include, for example, lighting systems which outline the runways and taxiways, as well as signs used to direct traffic or identify areas.
Airfield series circuits are usually provided with different brightness level amperage steps so that the brightness of the lights which outline the runways and taxiways can be adjusted to provide a dimming function. For example, taxiway edge light circuits may have a fixed intensity requiring 6.6 amperes or they may have three intensity steps at 6.6 amperes, 5.5 amperes, or 4.8 amperes. On the other hand, runway edge light circuits usually have five step settings of 6.6, 5.2, 4.1, 3.4, and 2.8 amperes. This allows the brightness of these various lights to be adjusted from the control tower as needed.
The difficulty with this arrangement is that the airfield signs are usually also driven by the same series circuitry that feeds current to the runway and taxiway lights. Since the FAA requires that the light output from airport signs remain at a constant level, even when the circuits to which they are attached change current levels, designers of airfield series circuits have been forced to adapt these circuits to provide this required functionality.
Conventionally constant brightness of airfield signs has been achieved by providing a transformer associated with each of the signs that saturates over a relatively large range of input current values and an associated constant current regulator. A problem with this solution is that it provides a resultant power factor of less than 0.5 which greatly reduces the cost efficiency of the system.

Input current responsive, tap changing transformer system


A boosting circuit is disclosed. The boosting circuit includes an input circuit part for outputting a differential current proportional to input voltages; a bias circuit part for mirroring the differential current, and producing an inverted differential current that the differential current is inverted; and an output circuit part for adjusting magnitudes of the differential current and the inverted differential current based on a predetermined ratio of MOS transistors, respectively, adding the adjusted differential current and inverted differential current, and producing an output current in a push-pull form. Accordingly, the boosting circuit has a broad maximum differentiable frequency bandwidth, and facilitates the adjustments of differentiation characteristics of an output current. Further, an amount of output current of differentiation form is not affected by external factors such as voltages, processes, temperatures, and so on.

1. Field of the Invention
The present invention relates to a boosting circuit, and more particularly, to a boosting circuit to be used for a high frequency equalizer without having the amount of boost affected by external factors of not only frequency operation characteristics, but also voltages, processes, temperatures, and so on.
2. Description of the Related Art
The boosting circuit for an equalizer employed in optical recording/reproducing devices or hard disk drives for compact disk (CD)/digital video disk (DVD) is required to output differential currents from input voltages, and to adjust the amount of boost without affecting group delay characteristics up to a high frequency bandwidth of about 100 MHz.
FIG. 1 is a view for illustrating a conventional boosting circuit. As shown in FIG. 1, the conventional boosting circuit is constructed with capacitors C1 and C2, resistors R1 and R2, an operational amplifier A1, and a transconductor Gm1. The operational amplifier A1 is a fully differential operational amplifier having two input terminals and two output terminals.
In such a circuit constructed as above, an input voltage Vi is differentiated in a differentiation circuit constructed with the operational amplifier A1, capacitors C1 and C2, resistors R1 and R2 and converted into a current for output through the transconductor Gm1. If R=R1=R2 and C=C1=C2, the relationship between the input voltage Vi and an output current io(=iop−ion) can be expressed in Equation 1 as follows:io(s)=gmRCsvl(s),  [Equation 1]wherein gm denotes a transconductance of the transconductor Gm1. Accordingly, the magnitude of output current io can be adjusted by varying the transconductance gm of the transconductor Gm1.
However, such a boosting circuit is affected by external factors such as temperatures, voltages, processes, and so on, since the magnitude of output current io is adjusted by varying the transconductance gm. Therefore, there is a drawback in that an additional tuning circuit is needed to prevent such influences. Further, there exists a problem in that power consumption becomes high and frequency characteristics are deteriorated, since a two-stage process is needed to differentiate and then convert input voltages into currents.
FIG. 2 is a view for showing another conventional boosting circuit. The boosting circuit of FIG. 2 has capacitors C3 and C4, an operational amplifier A2, and NMOS transistors M1, M2, M3, M4, M5, and M6.
In such a circuit constructed as above, an input voltage Vi is converted into a differential current through the operational amplifier A2 and the capacitors C3 and C4. If C=C3=C4, the relationship between the input voltage Vi and an output current io(=iop−ion) can be expressed in Equation 2 as follows:io(s)=kCsvl(s),  [Equation 2]wherein k denotes a size ratio, that is, Width(W)/Length(L), of NMOS transistors M1 and M2 or M4 and M5. Therefore, an amount of output current can be adjusted by using a size ratio of NMOS transistors.
In the boosting circuit of FIG. 2, an extra tuning circuit is not needed since the amount of output current is adjusted with the size ratio, k, of the MOS transistors, resulting in an advantage of directly converting an input voltage into a differential output current, compared to the boosting circuit of FIG. 1.
However, unlike the boosting circuit of FIG. 1, an output of an output amplifier constructed with the NMOS transistors M1 and M4, current sources IB, and so on, is used as an input to the NMOS transistors, so that the input terminals of the operational amplifier A2 are formed with p-type elements, which causes a drawback in broadening bandwidth since the p-type elements have a small transconductance compared to the n-type elements. Further, the two-stage amplification structure formed with the operational amplifier A2, NMOS transistors M1 and M4, and current sources IB results in a drawback in that frequency compensation is needed for stability. Moreover, the DC bias currents IB to the NMOS transistors M1 and M4 are reflected in the NMOS transistors M2 and M5, which, as a drawback, require compensations at a bias stage connected to a rear stage of the differentiation circuit.


Package (1) having a sensor assembly (2) with at least one sensitive surface (21) and an attachment surface (22), a carrier element (3) with a sensor attachment area (31), and a sensor attach material (4) for attaching the sensor assembly (2) to the sensor attachment area (31) of the carrier element. The package (1) comprises an encapsulation (5) of a first material, in which the encapsulation (5) covers the sensor attachment area (31) of the carrier element (3) and the sensor attach material (4) and leaves the at least one sensitive surface (21) free from the first material.

International patent publication WO2007/017301 discloses a package for a pressure sensor of a micromechanical type. The package is completely sealed, and the external pressure is transmitted mechanically to the sensor surface in the package, using various embodiments of pressure transmission means. Such a sealed package has the advantage that the sensitive surface of the sensor is completely blocked from the external environment and thus protected against possibly damaging influences of the external environment. In some applications however, it is desired that a direct contact path is available from the environment to the sensitive surface of a sensor in a package.


A skills learning method for a student gathers objective data relating to the student in response to various stimuli, and produces a predicted feedback units as a function of the objective data using a machine learning-base classifier. The method can include training a neural network using objective data of student interactions and associated subjective assessments of a skill of each objective data. The method includes receiving a new dataset with objective data of a new student and an associated subjective assessment of a skill of the first student represented by the new objective data. A predicted assessment of the skill of the new objective data is calculated by inputting the new objective data into the neural network. The method can include updating the neural network by combining the initial dataset and the new dataset and recompiling the neural network to fit the model dataset based on a learning algorithm.

International Universities and Higher Education Institutions have been recently challenged for not being able to help students to properly develop those skills and competencies required by the marketplace. Universities have been challenged for providing credits to students only on the basis of hours of lessons attended rather than on the basis of skills developed, undesirably producing graduates not ready for the market place.
Universities are indeed developing online programs accessible by anyone, from anywhere and anytime in the world. These programs could deliver credits to students on the basis on the competencies they improved upon rather than on the basis of the hours of training they attended. These institutions can grant access to the market place to the students who will be able to better prove and to show to their future employers, that they have gained the desired skills. A critical problem here is that there are no currently, intelligent systems that can monitor and measure the level of specific skills/competencies developed (per each online student) that can suggest at the same time targeted resources and activities to each learner for improvement. Moreover, it is difficult, in this new system, to state how a student has developed some specific skills or competencies. Indeed, it usually is the teacher or the tutor who solely detects, measures and makes a judgment over the knowledge gained by a student and on the achieved learning goals. In addition, current educational technology tools known by the inventors available in the market measure students' drop out risk, or students' degree of achievement of learning goals, or amount of knowledge acquired, but not yet competencies.

Systems and methods for assessing and improving student competencies


A technique for operating a source follower buffer circuit, such as employed in a charge domain pipeline, to eliminate floating diffusion signal charge contamination from downstream circuits. The method and apparatus places an output of the circuit in a known state immediately prior to charge transfer into a floating diffusion, and again in known state immediately prior to charge transfer out of the floating diffusion.

In charge domain pipeline circuits, such as used in Analog to Digital Converters (ADCs) and other applications, signal charge is transferred from a sending capacitive net to a pre-charged receiving capacitive net using a charge transfer device. These capacitive nets are typically implemented as floating diffusions. Transfer of a signal charge into a capacitive net causes the voltage on the capacitive net to drop from a pre-charged voltage by an amount proportional to the amount of charge.
In order to measure the size of the signal charge, as needed for the purpose of comparing it to another charge packet on an opposing floating diffusion of a differential design, it is necessary to either amplify or buffer the change in voltage. This is normally done by connecting the Floating Diffusion (FD) to the gate of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) which acts as an input device to a buffer circuit.
After the change in voltage has been measured, the received charge packet is sent to the next receiving floating diffusion in the pipeline. This charge packet should be completely transferred without losing any charge to the gate of the buffer/amplifier input device. Unfortunately, this is difficult due to the charging of the parasitic capacitance of these input devices with some of the signal charge. Opposite sides of these parasitic capacitors are connected to internal nets of the amplifier/buffer circuitry and, thus the amount of coupling from these nets back onto the floating diffusion is un-deterministic.

Avoiding floating diffusion contamination


A bracket assembly is provided with a shell, a pivotal first curved member on one end of a recessed shell bottom, a pivotal second curved member on the other end of the shell bottom, a link including a slot, a first pin driven through the first curved member and the slot to fasten the first curved member and the link together, and a third hole at an other end, a cylindrical first actuation member, a cylindrical second actuation member, a second pin for fastening the first actuation member and the link together; a biasing member biased between the first stop member and the first actuation member; and a knob at a cap. A retaining device is also provided so that the sliding tube can slide in a transverse channel of retaining device, thereby adjusting length of the sliding tube.

1. Field of the Invention
The invention relates to machine stands and more particularly to a bracket assembly and a retaining device for a collapsible stand for supporting a machine (e.g., circular sawing machine).
2. Description of Related Art
U.S. Publication Number 2006/0272744 to Liu et al. discloses a bracket assembly for a mobile stand having a long beam and a plurality of legs that support the long beam for supporting a machine, the bracket assembly comprising a bracket body mountable on the long beam of the mobile stand; a front clamp mounted in the bracket body, the front clamp having a front stop face contactable with the long beam of the mobile stand; a rear clamp pivoted to the bracket body and corresponding to the front clamp, the rear clamp having a rear stop face contactable with the long beam of the mobile stand, and a guide face opposite to the rear stop face; and a locking control device having an eccentric member and a follower rotatably coupled to the eccentric member, the eccentric member being pivoted to the bracket body and having an operating handle extending out of the bracket body, the follower having a push face kept in contact with the guide face of the rear clamp.
However, when the bracket assembly is mounted on a power tool, an upward or downward of the handle offers a little cam force to the long beam in operation. Thus, the long beam may hit the handle accidentally if the handle is not secured and the handle pivots upward or downward. This is very dangerous especially in cutting.
U.S. Pat. No. 8,528,870 to Liu et al. discloses a retaining device for a stand having a drawable extending rod, the retaining device comprising a base having a through hole for penetration of the extending rod; a shaft inserted in the base; a handle having a cam portion and an eccentric hole through the cam portion, and pivotally mounted on the shaft through the eccentric hole; a retainer moveably mounted in the base and having a receiving hole in which the cam portion of the handle is received such that the retainer is moveable by a pivotal movement of the cam portion of the handle to stop the extending rod in position; and an adjustment unit including the shaft having an eccentric shaft portion passing through the eccentric hole of the handle, and a teeth portion at an end of the eccentric shaft portion, a screw inserted in the shaft and provided with a distal end passing through a retaining hole of the base, a nut screwed to the distal end of the screw, and an elastic member sleeved on the screw and stopped against the base and the shaft; wherein when the screw is tightened, the teeth portion of the shaft is engaged with a teeth hole of the base for preventing the shaft from rotation, and when the screw is loosened, the teeth portion of the shaft is disengaged from the teeth hole of the base by an elastic force of the elastic member for allowing the shaft to be rotatable.
However, an upward or downward of the handle offers a little cam force to the long beam in operation and its positioning effect is poor. Thus, the extending rod may be vibrated by the cam in an urging action. And in turn, it may adversely affect the safety in a cutting operation. Thus, the long beam may hit the handle accidentally if the handle is not secured and the handle pivots upward or downward. This is very dangerous especially in cutting.
Notwithstanding the prior art, the invention is neither taught nor rendered obvious thereby.

Bracket assembly and retaining device for collapsible stand


An electrically conductive brush box is located against the upper surface of a base and has crimping tabs located against an oppositely disposed crimping surface. The base is formed of high temperature resistant plastic. A field case housing has a seat with a retention member adapted to retain the base against the seat. A screw is threaded into the field case housing such that the head presses against a surface of the base member to retain the base member in the seat. The screw member is located in non-contacting relationship with the electrically conductive brush box. A spacer member is adapted to space the portion of the crimping tab against the crimping surface away from the field case housing. The brush box includes a biasing member holder and the crimping tabs are located adjacent the holder.

Electric motors are used in a variety of applications, including power tools. Such electric motors typically include a motor shaft, a motor armature, magnets, a fan baffle, a commutator assembly, brushes and electrical leads. The electrical leads selectively link brushes to a power source. The motor armature is fixed for rotation with the motor shaft and a series of copper conducting wires are wound in various patterns about peripheral slots. Ends of the wires are fused to the commutator. The commutator is fixed for rotation with the motor shaft and provides an electrical connection between the rotating armature and the stationary brushes.
The brush is often held in place by an electrically conductive brush box. The electrical current powering the motor flows through this electrically conductive brush box through the brushes and into the commutator. As a result, the temperature of the brush box (which is typically made of brass) can be raised to fairly high levels; particularly when high amperage applications are concerned like battery operated power tools. As such, the temperature of the brush box can be sufficient to potentially damage the field case housing. Thus, it is desirable to minimize any such risk of damage.


A boiler is described comprising a housing with a flue gas inlet for receiving a hot gas flame and an outlet for venting a hot gas produced by the hot gas flame, and a tube assembly mounted within the housing. The tube assembly comprises a lower manifold for receiving a liquid, an upper manifold for receiving a heated version of the liquid; and, a plurality of tubes disposed between the lower and upper manifolds. Each tube is shaped to provide a hot gas pathway that travels in a parallel fashion along at least a lower portion of the longitudinal extent of each tube in the tube assembly to the outlet, whereby the liquid introduced into the lower manifold travels in the plurality of tubes and receives heat from the hot gas along the extent of the hot gas pathway.

A boiler is a pressurized system in which heat is transferred to a fluid. Water is typically used as the fluid for economical reasons and its suitable thermodynamic characteristics. The water is heated by heat transferred to the water from a source of higher temperature (i.e. a flue gas), which is usually produced by the combustion of fuels. The water may be heated to a suitable temperature or heated such that it is vaporized to a steam. Accordingly, connections are made for the off-take of the heated water or the generated steam and for the replenishment of water. The heated water or generated steam can be used as a heating medium or as a working fluid in another device that converts thermal energy to mechanical work. The water also acts to cool the heat-absorbing surfaces of the boiler while the water circulates through the boiler. The heated water or generated steam, as the case may be, is removed at a controlled rate that is comparable to the rate of heat addition to the water so that the pressure in the water-vessel can be maintained at a desired, safe value.
A water-tube boiler is a particular type of boiler that includes a plurality of small-diameter, water-containing tubes arranged in a certain configuration to allow hot gases to pass over the outer surface of the tubes thereby transferring heat to the water contained inside the tubes. The water is confined in the small tubes such that the water flows upwards in a rapidly controlled manner. Water-tube boilers are typically economical for heat capacities greater than 20,000 pounds of steam per hour.
Evolution in water-tube boiler design for higher pressures and capacities has led to use of steel and increasing the length, number and orientation of the tubes. In particular, bent-tube, water-tube boilers are used for high-pressure designs. Bent-tube water-tube boilers terminate in upper and lower steam and water drums (also known as manifolds). The bent-tube water-tube boilers also have sloped tubes that reduce the possibility of steam pocket formation thereby increasing the rate of heat absorption.
Water-tube boilers can operate at an efficiency, defined by the ratio of thermal energy output to heat input, of up to 80 percent. However, to obtain a higher throughput of heated water or generated steam, either a higher efficiency boiler is needed, which, if conventionally designed, results in increased costs due to the need for additional more expensive equipment, or a larger boiler is needed which also results in increased costs due to the need for more material.


In a first aspect, a method for optimizing efficiency of a transport provider is provided, comprising: receiving, by a processor, a first departure time of a vehicle, which is administered by the transport provider, at a first location; receiving, by the processor, a second departure time of the vehicle at a second location which is located after the first location; determining, by the processor, a difference between the first departure time and the second departure time; and updating, by the processer, a current schedule to provide an updated schedule in response to the determination of the difference, the updated schedule indicating an updated estimated arrival time of the vehicle at a location after the second location.

With the rapid development of urban transport, road network structure is becoming more complex, increasing delivery traffic. There are many factors affecting the proper and efficient operation of an urban transit system. Some of these factors include infrastructure, the advanced nature of operations management and the corresponding technical means.
Urbanization poses many challenges for providing transportation services in urban area. This includes optimizing efficiency of a transport provider. One such example is the increased difficulty in improving capacity and improving service quality of bus service operators.
There are two possible ways to manage operations of a transport provider, namely, on time adherence against a predefined schedule and managing headway equality between trips. In that regard, schedule optimization technology is a technology that has been applied in the management of urban transit operation. Schedule optimization can be based on real-time traffic information, the initial schedule, and speed data of the vehicles to optimize the efficiency. Parameters that the transport providers are working on to improve are a headway which is a measurement of the distance or time between vehicles in a transit system. The minimum headway is the shortest distance or time achievable by a system without a reduction in the speed of vehicles. Around the world, transport providers aim to optimize efficiency by working towards headway equality between trips.

Method and apparatus for optimizing efficiency of a transport provider


A method comprises on a first port, receiving a frame from a network device and determining whether the received frame includes a system identifier (ID) that matches a system ID corresponding to a second port. If the received frame's system ID matches the second port's system ID, the method further comprises discontinuing an aggregation protocol that otherwise enables multiple ports to be operated together as a virtual port.

In some networks, servers are employed that have multiple network interface controllers (NICs). Some such servers employ a protocol which enables groups of such NICs to function together as a "team." A team of NICs may have a single address (e.g., an Internet Protocol (IP) address) which facilitates communication through the team of NICs. To other logic and drivers, the team of NICs appears to be, and is interacted with as, a single NIC.
Servers typically connect to other servers or network devices through one or more network switches. A switch typically comprises multiple ports. The concept of "teaming" (or port aggregation or port trunking) can be applied to switches as well as to servers to permit groups of ports to function together as a team. On industry standard example of this type of functionality is described in IEEE 802.3ad.
An aggregation protocol may be employed to permit aggregation-based servers and aggregation-based switches, or other aggregation-based network devices, to discover each other's teaming capability. An aggregation protocol permits multiple aggregation-based network devices to discover that the devices have two or more physical ports in common that can be "bound" together as a single virtual port. Unfortunately, connecting a network device into such a network that does not comply with the aggregation protocol of the other network devices, or does not implement an aggregation protocol at all, may result in erroneous network behavior.

Discontinuing the implementation of an aggregation protocol

Hewlett-Packard Development Company, L.P.