An aluminum-silicon carbide composite suitable for a base plate for power module, having an aluminum-silicon carbide composite, with a front and a rear surface plane, that is a flat plate-shaped silicon carbide porous body impregnated with a metal mainly containing aluminum, and an aluminum layer made of a metal mainly containing aluminum formed only on the front surface plane, wherein the rear surface plane of the composite is exposed to the outside, and the shape of the exposed aluminum-silicon carbide composite is rectangular, optionally having peripheral portions encompassing holes removed. Plating is imparted to the composite by providing an aluminum layer on the rear surface plane. Flatness of the composite is improved by grinding its rear surface so that the composite is exposed to the outside. Warpage after grinding the rear surface, is controlled by controlling the thickness of the aluminum layer.

In recent years, along with progress of high-integration and downsizing of semiconductor elements, heat generation amount at a time of using such semiconductor element simply increases, and efficient dissipation of such heat has become a problem to be solved. For this purpose, as a circuit substrate for power module, a circuit substrate is used, which comprises a ceramic substrate such as an aluminum nitride substrate or a silicon nitride substrate having high insulation property and high thermal conductivity, a metal circuit made of copper or aluminum formed on the ceramic substrate, and a metal heat dissipation plate made of copper or aluminum formed on the rear surface of the substrate.
A typical heat dissipation structure of conventional circuit substrate is that a base plate is soldered to a rear surface (heat dissipation surface) of a circuit substrate via a metal plate such as a copper plate, and such a base plate is made of copper. However, in this structure, there has been a problem that when a heat load is applied to a semiconductor device, a crack of solder layer due to the difference of thermal expansion coefficient between the base plate and the circuit substrate occurs, and as a result, heat dissipation becomes insufficient to cause malfunction or destruction of a semiconductor element.
To cope with such a problem, an aluminum alloy-silicon carbide composite is proposed, which has a thermal expansion coefficient close to that of a circuit substrate (Patent Document 1). However, Patent Document 1 does not describe as to the shape, particularly, a warped shape of the aluminum alloy-silicon carbide composite, and accordingly, when it is actually used as a base plate for power module, there is a case that sufficient heat dissipation property is not obtained.
A base plate is used as it is joined with a heat-dissipation fin in most cases, and the shape and warpage of the joined portion are also important properties. For example, when a base plate is joined with a heat-dissipation fin, usually a heat-dissipation grease having high thermal conductivity is applied to portions to be joined, and the base plate is fixed to e.g. a heat-dissipation fin or a heat-dissipation unit by screws through holes provided in the peripheral portion of the base plate. However, if many fine irregularities are present on the base plate, a gap is formed between the base plate and the heat-dissipation fin, and even if a heat-dissipation grease having high thermal conductivity is applied, thermal conductivity is significantly decreased. As a result, there has been a problem that heat dissipation property of entire module constituted by the ceramic circuit substrate, the base plate and the heat-dissipation fin, etc. is significantly decreased.
To cope with this problem, in order to reduce such a gap between the base plate and the heat-dissipation fin as much as possible, a base plate formed to have a convex warpage in advance is used. This warpage is obtainable is by applying a pressure to the base plate as it is heated, by using a jig having a predetermined shape. However, since warpage obtained by such a method varies in the warpage amount and shape, and thus there has been a problem that its quality is not consistent. Further, due to the variation of warpage shape or surface irregularities, there has been a problem that a large gap is still formed between the base plate and the heat-dissipation fin.
There is a method of forming a warpage by cutting the base plate surface by machining. However, in this method, since the aluminum-silicon carbide composite is extremely hard, significant amount of grinding by a tool such as a diamond is required, and there has been a problem that its cost is high. To solve the above problem, a method is proposed, in which a flat silicon carbide porous body is impregnated with a metal containing aluminum as the main component, an aluminum alloy layer made of a metal containing aluminum as the main component is formed on each primary plane, and the aluminum alloy layer in the heat dissipation side is mechanically fabricated.
However, in a case of producing a base plate by using this method, when the aluminum alloy layer is mechanically fabricated, it is necessary to fabricate the aluminum alloy layer so that the aluminum-silicon carbide composite is not exposed to the outside. For this reason, considering warpage or distortion of the base plate itself and variation of its fabrication, the thickness of aluminum alloy layer to be formed on each primary plane needs to be inevitably thick, and for this reason, the thermal expansion coefficient of the base plate itself increases, and when it is soldered with a ceramic circuit substrate at a time of assembling a power module, there has been a case where a recess is formed on a heat dissipation plane of the ceramic circuit substrate.
Further, in this method, since it is necessary to control the thickness of the aluminum alloy layer on each primary plane to have uniform thickness and not to make the aluminum-silicon carbide composite exposed to the outside, there has been a problem that high degree of fabrication technique is required.
Patent Document 1: JP-A-5-507030

Aluminum-silicon carbide composite and heat dissipation device employing the same


A system for automatically positioning zoom regions located on imaging surfaces of an ECT camera system during ECT rotation to track relative movement of an object that is located offset from the center of rotation of the ECT camera system. During an ECT scan session, the imaging surfaces of the camera system rotate about an object of interest that is located offset from the center of rotation of the camera system in order to minimize the separation between the imaging surfaces and the object surface. Since the object of interest is offset from the center of rotation, a predetermined zoom region located on the imaging surfaces must alter its position relative to the imaging surface during an ECT scan session in order remain aligned with the object being imaged. The system determines this alignment position and thereby adjusts, in real-time, the location on the imaging surface of the zoom regions for increased image quality.

(1) Field of the Invention
The present invention relates to the field of zoom techniques for imaging. Specifically the present invention relates to the field of tracking an object with a varying position of a zoom area in an ECT nuclear medicine imaging camera system providing a varying field of view.
(2) Prior Art
Gamma detection cameras, also called gamma cameras, are used for medical imaging of particular body tissues, organs, or bone that may otherwise not be available for examination. In a typical medical camera of this sort, a special gamma ray emitting radiopharmaceutical is injected into the body and accumulates into the area of interest within the patient. The patient is then placed within the medical camera's imaging surface. As is well known, the radiopharmaceutical emits gamma rays which are then detected by the gamma camera as a series of photon emissions from a specialized crystal layer. Before the gamma rays reach the crystal they travel through a collimator layer which allows only those gamma rays which travel perpendicular to the collimator's orientation. A matrix of photomultiplier tubes is optically coupled to the crystal layer to receive the photon bursts, or scintillations, within the crystal layer and converts these photon bursts into electrical signals indicating a spatial coordinate of the gamma radiation. By using computers and other processing equipment to store and display the signals from the gamma camera, an image of the organ containing the radiopharmaceutical can be obtained and displayed for examination and diagnosis. When the gamma camera rotates around the patient and transverse images are reconstructed the system is called an emission computed tomography or ECT system. The surface of the gamma camera which receives the gamma rays from the patient is called the imaging surface. Since the collimator of the gamma camera is the first or outermost layer of the gamma camera, the collimator surface is commonly referred to as the imaging surface of the camera.
In practice, an object (patient) is placed horizontally into a central location while a gamma camera rotates (transaxial rotation) around a predetermined portion of the object to collect a number of images about that portion. This "ECT" rotation is orthogonal to the cranial-caudal axis of the patient. The acquired images are reconstructed into cross-sectional slices or images of the patient or object organ (or bone) at the predetermined location along the cranial-caudal axis of the object. For an total body scan, the gamma camera moves along the patient. As the camera surface translates, it collects the radiated gamma rays from the radiopharmaceutical. To obtain best quality images, it is desired to place the collimator surface as close as possible to the patient's outer surface. It is universally understood that when the collimator to patient distance is minimized better image resolution develops.
The resolution in the final reconstructed cross-sectional images is limited by the detector, the collimator, the distance between the collimator and the patient and by several other factors. One limitation is the sampling or size of the computer picture elements (pixels). Resolution improves if the size of the pixels is reduced (increased sampling). The gamma camera computer processor (image processor) processes a finite number of pixels to create an image. It would be advantageous to reduce the pixel size to improve image quality. The number of display pixels on the display screen, is distributed throughout the field of view of the imaging surface of a scanning camera. Therefore, a small object located within a large field of view of the imaging surface may appear relatively small on the display screen.
Recent ECT scanning cameras contain large rectangular field of views, typically 20 inches by 15 inches in dimension. This value represents the area of the imaging surface (collimator layer) of an ECT scanning camera. This is enough to accommodate the width of a human chest for a total body scan. However, if the particular organ or tissue of interest is only on the order of 4 to 5 inches wide, its representative image on the display screen will be small relative to the large field of view of the imaging surface. To this extent, relevant features of the small object may become obscured, hidden or difficult to interpret using a large field of view camera. To solve this problem, prior art systems have created a zoom region over a portion of the total field of view of the imaging surface. This zoom region has a zoom field of view that is smaller than the total field of view. The zoom region may be thought of as the active scanning region of the imaging surface; while those areas of the imaging surface not in the zoom region are passive in that they are temporarily not sending data to be imaged. For instance, for a square ECT imaging surface 20 inches by 15 inches, the zoom region may become 10 inches by 10 inches in area. The smaller zoom region (area) would then totally exist within the field of view of the imaging surface of the camera. All of the pixels available to the scanning camera would then be employed on this zoom region. The resulting image display of the small object within this zoom region would be larger than if the small object was imaged by the entire field of view.
The image discrimination resolution of a gamma camera is typically about 3-4 mm. The resolution of the collimator is about 6 to 20 mm depending on the proximity of the collimator to the object. Given a 20 inch by 20 inch field of view there are approximately 508 mm by 508 mm in the field of view. Using an ECT study of 64 by 64 pixels, each pixel is approximately 9 mm by 9 mm in dimension. If the field of view of the imaging surface was reduced to 300 mm then the dimension of the pixel is now 5 mm and capable of finer discrimination of the object and the radiopharmaceutical. Typical resolution of the gamma camera is from 10-15 mm thus pixels are approximately 5-7.5 mm in dimension. Therefore, by reducing the field of view of the gamma camera, the resultant pixel dimension reduces in size and the imaging camera is capable of discerning more image detail. By utilizing the above procedure, a small object or organ can be displayed with excellent resolution by relatively minor modifications to an existing ECT system.
FIG. 1 illustrates the zoom region implemented in the prior art as discussed above. FIG. 1 is a frontal view along the long axis of the ECT scanning camera in one dimension. The side view of one position of the imaging surface 200 of an ECT camera is illustrated. A relatively small object 59 is also shown. In a well known manner, this ECT camera may rotate about a center of rotation 10 along a gantry structure (not shown) during the ECT scan; this rotation is called ECT movement. The object of interest 59 is located about the center of rotation 10 of the ECT system. The fixed location zoom region 80 of imaging surface 200 is also shown as the shaded portion. By locating the object of interest in and around the center of rotation 10, when the imaging surface rotates to a new position 200' (shown by the dashed lines), the zoom region 80 of the imaging surface remains in exactly the same relative fixed location with respect to the imaging surface. As is seen within position 200' the zoom region 80 is still located within the center of imaging surface 200'.
Systems of the prior art usually locate the object of interest close to the center of rotation of the ECT system because the zoom region 80 of the prior art systems occupies a fixed location with respect to the dimensions of the imaging surface 200. Therefore, as the imaging surface 200 moves through position 200', the zoom region 80 remains situated within the same relative position with respect to the imaging surface. However, if the object 59 was located off of the center of rotation 10, the object would not remain within the fixed zoom region 80 throughout the ECT scan movement because the imaging surface rotates around the center of rotation and not around the object. This is disadvantageous because in many ECT scanning operations it is desirable to place the object of interest as close to the imaging surface as possible to increase the quality of the resultant image. By placing the object 59 close to the imaging surface the object is inherently placed off of the center of rotation of the ECT camera.
Also, some scanning camera systems employ dual camera imaging surfaces that may be placed orthogonal to each other. It would be desirable to place the object 59 as close as possible to each imaging surface for high quality images. However, it is impossible to place the object 59 close to both orthogonal imaging surfaces while maintaining the object 59 within the center of rotation 10 of both imaging surface. It is desirable, rather, to place the object in the inside corner of the two imaging surfaces. Therefore, what is needed is a system capable of defining a zoom region corresponding to the initial placement of an object of interest within the field of view of an imaging surface then allow the relative position of that zoom region with respect to the imaging surface to move during ECT motion of the imaging surface. This would allow an object to be placed in the corner of two orthogonal imaging surfaces because the zoom regions (relative to the imaging surface) of each imaging surface could vary during the ECT motion of the imaging surface. The present invention allows for such an advantageous capability.
Therefore, it is an object of the present invention to allow a zoom region within an imaging surface of an ECT camera to be initially defined by the position of an object of interest (that may be off of the center of rotation of the imaging surface), then to move the zoom region relative to the imaging surface as the imaging surface undergoes ECT motion around the object of interest. In so performing the above, it is an object of the present invention to image a point of interest located on an object of interest where the point of interest is not located on the center of rotation of the ECT camera system. It is further an object of the present invention to advantageously utilize the above capability within the environment of a dual scanning camera ECT system. Therefore, the zoomed region will track a small point of interest or an organ of interest that is offset from the center of rotation of the ECT camera system. These and other objects of the present invention not specifically mentioned will be further discussed in the detailed discussion of the present invention.
(3) Related Patent Applications
The following related co-pending application for patent having Ser. No. 07/981,833, and entitled, Proximity Detector for Body Contouring System of a Medical Camera, and assigned to the assignee of the present application for patent is herein incorporated by reference.

Apparatus and method for automatic tracking of a zoomed scan area in a medical camera system


A resistor network is provided which significantly reduces the total number of resistors required to achieve a given resolution. It comprises a cell of resistors that consists of a nonbinary number of resistors that is not evenly divisible by an integer power of two and is specifically selected to permit the group of resistors to be sequentially reduced to subgroups, or combinations, of resistors which yield a plurality of subgroup resistances that differ from preceding or subsequent subgroup resistances by a generally equivalent differential. The cell of resistors is combined with a plurality of resistor cells that consist of binary numbers of resistors in a conventional resistor ladder format. When combined with the binary resistor cells, the cell consisting of a nonbinary number of resistors provides a substantially similar resolution with a significant reduction in the number of resistors required. One embodiment of the present invention permits the resolution of a sixty-two resistor ladder to be simulated by a ladder that comprises only twenty-three resistors.

1. Field of the Invention
The present invention relates generally to resistor network circuits and, more particularly, to a resistor network that comprises a plurality of resistor ladders in which the number of resistors in each ladder is related to the number of resistors in at least one other ladder by a factor of two to form a binary progression and, in addition, an arrangement of resistors in an additional ladder which consists of a nonbinary number of resistors which is reducible in stages to a plurality of combinations which each have a resistance that is related to the resistances of the other combinations in a manner that results in a plurality of resistance differences between combinations that are sufficiently equivalent to each other to provide a series of incremental resistive steps which are monotonic and which provide a greater resolution than any of the other resistors ladders.
2. Description of the Prior Art
In the field of miniaturized electronics, it is often necessary to select the value of a component, such as a resistor, so that the performance of a circuit is optimized to meet certain requirements. To reduce the cost of these components, methods have been developed which utilize film resistors that are made from resistive paste or ink. These resistive areas of a circuit can be cut by laser trimming to obtain a desired resistive value. In integrated circuits, the trimmable resistive components are included on the silicon chip by depositing films of resistive material on silicon areas and trimming the resistive material with lasers which are integral to the wafer probing system that is used to inspect and test the operation of the integrated circuit.
One possible technique for setting the precise resistance of a resistor network is to measure the resistance of the network, compare that resistance to a desired predetermined value and then selectively trim resistors in order to achieve the necessary change in resistance. The resulting resistance could then again be measured to determine if additional trimming is necessary. This technique is disadvantageous when high volume production rates are desired. It has therefore been replaced by higher speed methods which calculate the precise resistors that should be cut and then trim those resistors to achieve the desired resistance in one step.
The use of resistor networks for the purpose of providing the high resolution resistive trimming of electronic circuits is well known to those skilled in the art. In a typical application of the known techniques, a plurality of resistor ladders is arranged in series association with each other and each of the resistor ladders consists of a preselected number of parallel connected resistors. Each one of the resistors in each of the ladders is removable, by trimming or severing, from its associated ladder.
In the newer methods of providing a trimmable resistive network, the network is arranged in such a way that the effects of cutting or trimming in the most significant cell, or ladder, are twice the effect of cutting in the next cell and so on. These binary weighted trimming techniques, using resistor ladder networks such as those described immediately above, are very well know in the art and result in fast and highly predictable resistance trimming.
In a typical application of modern integrated circuit techniques, a resistor network is fabricated from a series connection of several cells. Each cell comprises two identical resistive elements, which can possibly each comprise a plurality of resistive components, connected in parallel with each other and the resistive value of the resistive elements is halved as each subsequent cell is added. For example, FIG. 1 shows four exemplary cells, 10, 12, 14 and 16, connected in series between circuit points 20 and 22. The first cell 10 comprises two resistive elements, 30 and 32, which each have a value of R.sub.0. The second cell 12 comprises two resistive elements, 34 and 36, which each have a resistive value of R.sub.0 /2. The two resistive elements, 38 and 40, of the third cell 14 each have a resistive value of R.sub.0 /4. The fourth cell 16 comprises two resistive elements, 42 and 44, which each have a resistive value equal to R.sub.0 /8. Although the cells in FIG. 1 are arranged in order, from left to right, from the cell with the highest resistive values to the cell with the lowest resistive values, it should be understood that the effective resistance between circuit points 20 and 22 is not dependent on the order in which the cells are connected in series. The cell with the highest resistive values is the most significant cell. In FIG. 1, this is the first cell 10. The next cell 12 is the second most significant cell and so on with the fifth cell 18 being the least significant cell. The relationship of the cells described above is achieved by making the resistive elements in each cell equivalent to half the resistance of the components in the next more significant cell. In other words, resistive elements 42 and 44 each have a resistive value which is one half the resistive value of components 38 and 40. As a result, the resistive components 46 and 48 of the fifth cell 18 each have a resistance equal to R.sub.0 /16. As will be described in greater detail below, each resistive element, 30-48, could be replaced by a plurality of individual resistors of a predetermined value to achieve equality for each resistor.
With continued reference to FIG. 1, it can be seen that the network is arranged to permit one branch of each cell to be opened or trimmed. The most significant cell 10 can therefore have a resistance value of either R.sub.0 /2 if both branches remain intact or R.sub.0 if one of the two resistive components, 30 and 32, are cut or trimmed. The second most significant cell 12 will have a resistance value of R.sub.0 /4 if both resistive elements, 34 and 36, remain intact and R.sub.0 /2 if one of the two branches is cut. It should be clear that the change in resistance of the cells is halved in each sequential cell in FIG. 1. EQU R.sub.MIN =R.sub.0 (1/2+1/4+1/8+1/16+1/32) (1) EQU R.sub.MIN =31/32 (2)
Therefore, the network in FIG. 1 can have a minimum resistance value defined by equation 1 which can be simplified as illustrated in equation 2. EQU R.sub.MAX =R.sub.0 (1+1/2+1/4+1/8+1/16) (3) EQU R.sub.MAX =R.sub.0 (31/16)=2(R.sub.MIN) (4) EQU .DELTA.R=R.sub.0 /32 (5) EQU R=R.sub.MIN +K(.DELTA.R) (6) EQU R=R.sub.0 ((K.sub.1 +1)/2+(K.sub.2 +1)/4+(K.sub.3 +1)/8+(K.sub.4 +1)/16+(K.sub.5 +1)/32) (7) EQU V=16K.sub.1 +8K.sub.2 +4K.sub.3 +2K.sub.4 +1K.sub.5 (8)
The maximum possible resistance of the network shown in FIG. 1, which is achieved if one leg of each cell is trimmed, is defined by equation 3 which is simplified in equation 4. As can be seen in equation 4, the maximum resistance achievable by the network in FIG. 1 is twice the minimum resistance achievable by that network. The resolution, or the magnitude of the differential between each possible sequential value achievable by the network in FIG. 1, is defined in equation 5. The five cell network therefore has 32 distinct possible values between the minimum resistance of equation 2 and the maximum resistance of equation 4. The possible resistances are defined by equation 6, where K can be any integer between 0 and 31. These 32 possible resistance values for the network shown in FIG. 1 are illustrated in FIG. 2. As can be seen, the binary progression that is possible with the network shown in FIG. 1 provides a monotonic progression of equal steps between the minimum resistance defined in equation 2 to the maximum resistance defined in equation 4 with the resolution defined in equation 5. One skilled in the art will recognize that any value of resistance between the minimum and maximum resistances of the network can be provided within an accuracy of plus or minus one half of the resolution defined in equation 5. It should further be understood that the resistance of the network shown in FIG. 1 can be mathematically expressed as shown in equation 7, where K.sub.N is equal to zero if the Nth cell is intact and is equal to one if the Nth cell is cut or trimmed. If the values of K.sub.N are considered to be coefficients of a binary number, the decimal value of the number is represented by the relationship shown in equation 8. EQU R.sub.N =(R.sub.0)/(2.sup.N-1) (9) EQU .DELTA.R=R.sub.0 /2.sup.N (10)
With continued reference to FIG. 1, the concepts described above can be stated for the general case for N cells. The values of the resistors in the first cell are each equal to R.sub.0 and subsequent division by two in each cell results in a resistance value for the Nth cell equal to that shown in equation 9. Furthermore, the resolution of the circuit is defined by equation 10, the maximum resistance is equal to twice the minimum resistance and the range of possible resistances is equal the minimum resistance. Those possible resistances achievable by the network are defined by equation 6 where the magnitude of K is defined by equation 8, but with the numeric coefficients shown in equation 8 being replaced by the values 2.sup.N-1, 2.sup.N-2. . . 2.sup.O. This relationship shows that any resistance value between the minimum and maximum resistance can be provided with an accuracy of one half of the resolution.
As an example of a particular application of the relationships described above, suppose that a circuit design requires that a particular resistor will have to be trimmed to any value between 1,250 ohms and 1,750 ohms with an accuracy of plus or minus 15 ohms or better in order to meet the requirement. From the above description of the relationships inherent in a network such as that shown in FIG. 1, .DELTA.R must be less than or equal to 30 ohms and the range must be greater than or equal to 500 ohms. The range of the network is equal to the minimum resistance, as shown above. Solving equations 11 and 12 for this example, the value R.sub.0 is equal to 530 ohms and the magnitude of 2.sup.N must be greater than or equal to 530/30 or 17.666. Since the value of N must be an integer, the designer must select N=5. EQU R.sub.0 (1-1/2.sup.N).gtoreq.500 (11) EQU R.sub.0 /2.sup.N .ltoreq.30 (12)
According to the discussion above in association with FIG. 1, this would seem to indicate that a network with 5 cells is appropriate and the resistive value of the elements, 30 and 32, in the first cell would be equal to R.sub.0 and the resistive value of the elements, 46 and 48, in the fifth cell would be equal to R.sub.0 /16. However, if each cell in the network of FIG. 1 comprises individual resistors of unequal value to the resistors in the other cells, a severe manufacturing problem can occur.
With reference to FIG. 3, an individual resistor 50 is shown with two conductive pads, 52 and 54, attached to it to provide a path for current to flow through the resistor 50. As is well known to those skilled in the art, a resistive element in an integrated circuit is typically manufactured by depositing a resistive solution, such as a resistive paste or ink, on a suitable substrate. Then, in order to provide the conductive path shown in FIG. 3, a pair of conductive leads are deposited in an overlapping association with the resistor as shown. With the conductive pads disposed over the end portions of the resistor 50, the resistive part of the conductive path has an effective length L and an effective width W as shown in FIG. 3. The resistance of the resistor 50 can be increased by decreasing the width W or by increasing the length L. Similarly, the resistance of resistor 50 can be decreased by increasing the width W or decreasing the length L. If the plurality of resistive elements shown in FIG. 1 comprise several different resistive magnitudes, they would also comprise several different dimensional configurations to achieve the different resistances for each of the individual cells in the network. If the resistors comprise several different sizes, it would be extremely difficult to maintain sufficiently tight tolerances to maintain the accuracy necessary to achieve the binary weighted relationships described above. For example, if one resistor in the network had dimensions L and W and another resistor had dimensions L and 2 W, and an error in manufacturing made each resistor too wide by a dimension of 0.1 W, the effects on the two resistors would be disproportionate. The widths of the two resistors, after the manufacturing deviation occurred, would be 1.1 W and 2.1 W, respectively, and the resistance of the thinner resistor would be 1.90909 times the resistance of the wider resistor rather than being twice its resistance. Therefore, it is very difficult and undesirable to manufacture a resistor network like that shown in FIG. 1 with individual resistors that are unequal in value. The desire to utilize identical resistors throughout the network of FIG. 1 can be achieved by replacing the resistive elements shown in FIG. 1 by a predetermined number of identical resistors. For example, if it is desirable to use resistors having a value of R.sub.0, resistive elements 30 and 32 would each comprise a single resistor having that value. Resistive elements 34 and 36, on the other hand, must have a resistive value equal to R.sub.0 /2 as described above. Therefore, each of the resistive elements, 34 and 36, would be replaced by two parallel resistors which each have a resistive value of R.sub.0. This procedure would be followed accordingly for each cell, or ladder, in FIG. 1 with the fifth cell 18 having each resistive element, 46 and 48, replaced by 16 individual parallel resistors that each have a value of R.sub.0. In keeping with the desire to achieve a binary weighted network and also be able to achieve the resolution described above, the resistors in each ladder would be trimmed by always cutting either no resistors or half of all the resistors in each cell. As an example, the 32 resistors in the fifth cell 18 would either be left uncut or 16 of those resistors would be trimmed. This satisfies the desire to provide a binary weighted ladder network while also achieving the coincident goal of utilizing identically valued resistive elements throughout the entire network.
Since the resistance value of a single resistor, such as that shown in FIG. 3, is a function of its length and its width, the total area of an integrated circuit required for a resistor network, such as that shown in FIG. 1, is a function of the total number of resistors used to provide the network which, in turn, is a function of the individual resistance value selected for each resistor in the network. For example, FIG. 4 illustrates a hypothetical resistor ladder network that comprises three cells, 61, 62 and 63, in which each resistor shown in the network has a resistance value of R.sub.0. As can be seen, the network shown in FIG. 4 requires 14 resistors to achieve a resolution equal to R.sub.0 /8. The identical resolution can be achieved in an alternative network which utilizes individual resistors that each have a resistive value of R.sub.0 /2. This is shown in FIG. 5 where the network comprises three cells, 71, 72 and 73. If each resistor in FIG. 5 is equal to one half the resistance of each resistor in FIG. 4, the networks shown in FIGS. 4 and 5 are electrically equivalent to each other. In addition, cell 61 and cell 71 are electrically equivalent to each other cell 62 is electrically similar to cell 72 and cell 63 is electrically similar to cell 73.
With continued reference to FIGS. 4 and 5, it can be seen that the network of FIG. 5 only requires the use of 10 resistors to achieve the identical electrical characteristics that required 14 resistors in FIG. 4. However, it should also be understood that since the resistors in FIG. 5 are half the value of the resistors in FIG. 4, they must either be shorter or wider than the individual resistors in FIG. 4. As described above in conjunction with FIG. 3, a resistor's value can be reduced by reducing the length L or by increasing the width W. Since the length L can not be reduced beyond a predetermined limit because of the necessity to provide a sufficient length L to permit a laser to cut the resistor along its width W, it is likely that the resistance of the resistor would be decreased by increasing its width W. Therefore, each resistor in FIG. 5 would probably have to be slightly larger than each resistor in FIG. 4. On the other hand, fewer resistors are necessary in the network in FIG. 5.
FIG. 6 illustrates this relationship between the resistance value R of each individual resistor and the total area required to contain the complete ladder network. As an example, the use of resistors having a value of R.sub.0, as in FIG. 4, could hypothetically require a total area equal to A.sub.1 to contain the 14 resistors of the network. By reducing the individual value of each resistor to R.sub.0 /2, as shown in the network of FIG. 5, the number of resistors is reduced to 10. However, if the length L of each resistor cannot be reduced to achieve the reduced resistance, the width W must be doubled. Therefore, although the number of resistors in the network was reduced by approximately 28 percent, the size of each individual resistor was doubled. Therefore, the replacement of the network shown in FIG. 4 with the network shown in FIG. 5 may actually result in an increase in total area, from A.sub.1 to A.sub.2, as shown in FIG. 6. Although it should be understood that these examples are hypothetical, they illustrate the complex considerations that must be examined in order to reduce the area necessary to contain the resistor ladder network.
With continued reference to the above example in which a particular resistor network was required to provide a value between 1,250 ohms and 1,750 ohms with an accuracy of plus or minus 15 ohms, it was determined that a resolution of 30 ohms was necessary and that the network required 5 cells. With N equal to 5, equations 11 and 12 provide the information that R.sub.0 must be greater or equal to 560 ohms and less than or equal to 960 ohms in order to achieve the required results. The skilled artisan will understand that the lower limit for R.sub.0 is set by the required range, whereas the upper limit is determined by the accuracy or resolution required. Experts will also realize that an additional series resistor will sometimes be required to complete a network. FIG. 7 illustrates the network of FIG. 1 with each resistive element, 30-48, of FIG. 1 replaced by a preselected number of identical resistors to achieve the binary weighted effect described above. The network of FIG. 7 also satisfies the requirements determined above in conjunction with the hypothetical example that wa determined to require individual resistors having a value R.sub.0 between 516 ohms and 960 ohms. If a resistor value of 700 ohms is selected for each of the resistors in the five cells, 10-18, and an individual resistor 80 is added in series with the cells and has a resistance value of 500 ohms, the network shown in FIG. 7 satisfies the requirements described above. The minimum value of the circuit shown in FIG. 7 is 1,178 ohms and the maximum resistance value is 1,856 ohms. Of course, it should be understood that the range provided by the five cells in the network is between 678 ohms and 1,356 ohms and resistor 80 provides an additional resistance of 500 ohms. The resolution is smaller than 22 ohms and the accuracy is better than plus or minus 11 ohms.
Although the network shown in FIG. 7 is sufficient to satisfy the requirements of the hypothetical example described above, it should be noted that 62 resistors are necessary to satisfy the resolution requirements which necessitated the inclusion of the five cells, 10-18. It should also be noted that when the necessary resolution requires the inclusion of one more additional cell, the number of additional resistors needed for that cell is greater than the total number of resistors needed for all of the preceding cells combined. For example, with continued reference to FIG. 7, if a sixth cell is necessary to achieve a smaller desired resolution, that sixth cell would contain 64 resistors and would double the space required for the network. Therefore, it would be significantly beneficial if a network configuration required significantly fewer resistors while providing a substantially equivalent resolution.

High resolution resistor ladder network with reduced number of resistor elements


A shift range control device switches a shift range by controlling the driving operation of a motor. When a difference between a target angle at which the motor is to be stopped and an actual angle becomes smaller than an angle determination threshold, the shift range control device switches from a feedback control to a control with a fixed duty. When the motor reverses, the shift range control device switches from the control with the fixed duty to a stationary phase energization control for energizing a stationary phase of the motor.

A shift range switching device has been known which switches a shift range by controlling a motor in response to a shift range switching request from a driver. For example, in Patent Literature 1, a switched reluctance motor is used as a driving source of a shift range switching mechanism. Hereinafter, the switched reluctance motor is referred to as an "SR motor".


A system for creating a log of a conversation includes a convener computer and a plurality of conversation computers interconnected by a computer network. The system includes an arbiter computer and a plurality of conversation computers interconnected by a computer network. The arbiter computer creates a public key pair comprising a new public key and a new private key, and causes the new public key to be transmitted to the conversation computers. The conversation computers receive the public key and transmit messages during the conversation. The arbiter computer uses the new private key to encrypt messages transmitted by at least some of the conversation computers during a conversation among the conversation computers, and to store the encrypted messages in a message log. The conversation computers cause messages in the message log to be decrypted using the new public key.

A text Appendix A is being submitted with this application.
The present invention relates in general to certifying authorizations in computer networks such as public packet switched communications networks.
Certifying authorities are known that generate public key certificates, enciphered with the private key of the certifying authority, that serve as letters of introduction of a particular party to any other party that can recognize the certifying authority as an introducer. The certifying authority typically makes the party seeking the certificate of introduction prove that it is who it says it is, and then the certifying authority accepts the public key of the party and returns it in the certificate of introduction signed with the private key of the certifying authority, thereby binding the name of the particular party to the public key of the party.
One aspect of the invention features a system for certifying authorizations that includes an authorizing computer and an authorized computer interconnected by a computer network. The authorizing computer creates a public key pair comprising a new public key and a new private key, and creates an authorization certificate that certifies that a holder of the authorization certificate is authorized to perform an action referred to in the authorization certificate. The authorization certificate includes the new public key. The authorizing computer causes the authorization certificate and the new private key to be transmitted to the authorized computer. The authorized computer receives the authorization certificate and the new private key and decrypts messages using the new private key as evidence that the authorized computer has obtained the authorization certificate legitimately.
Because the authorization certificate certifies that the holder is authorized to perform a certain action, rather than certifying only the identity of the holder, the authorization certificate can be issued by any arbitrary computer having a smart token such as a smart card that uniquely and securely identifies the owner of the card and may be removable from the computer. The authorized computer can use the authorization certificate as evidence that the authorized computer is authorized by the owner of the smart token at the authorizing computer to perform the action referred to in the authorization certificate.
According to another aspect of the invention the authorizing computer receives a first authorization certificate that certifies that a holder of the authorization certificate is authorized to perform an action referred to in the first authorization certificate. The authorizing computer then create a second authorization certificate that includes the first authorization certificate and certifies that a holder of the second authorization is granted additional authority with respect to performing the action referred to in the first authorization certificate. Thus, for example, a junior officer may create a first authorization certificate for purchase of a product and send it to a senior officer at the authorizing computer, who creates a second authorization certificate that includes the first authorization certificate and also grants additional authority for the purchase in the form of a countersignature grant of purchasing power. Then the senior office sends the second authorization certificate to an electronic merchant. The temporal order of authorizations in a chain is preserved because the each successive authorization certificate is incorporated into the next authorization certificate.
According to another aspect of the invention the authorization certificate has a file structure that supports critical components and extension components. The authorized computer accepts certificates having file structures that support critical components and extension components when the authorized computer is programmed to accept the critical components but rejects certificates having file structures that support critical components and extension components when the authorized computer is not programmed to accept the critical components. The authorizing computer includes information unique to the action referred to in the authorization certificate as at least one critical component of the authorization certificate in order to prevent the authorization certificate from being accepted by computers that are not programmed to accept the information unique to the action referred to in the authorization certificate. This helps to ensure against misuse of the authorization certificate.
Another aspect of the invention features a system for escrowing private keys that includes a computer and a smart token interconnected with the computer. The smart token includes a private key of a public key pair associated with the smart token. The computer encrypts the private key of the public key pair associated with the smart token with a public key of a public key pair associated with a user of the smart token. The computer also encrypts a private key of the public key pair of the user of the smart token with a public key of the public key pair associated with the smart token. The computer transmits to an escrow agent the encrypted private key of the public key pair associated with the smart token and the encrypted private key of the public key pair associated with the user of the smart token. This ensures that if one private key is lost, the other private key can be retrieved from the escrow agent.
Numerous other features, objects, and advantages of the invention will become apparent from the following detailed description when read in connection with the accompanying drawings.

Enabling business transactions in computer networks


A non-aqueous inkjet ink containing at least two kinds of color pigments, a pigment dispersing agent and an organic solvent, wherein the two kinds of color pigments are a watching red pigment and a benzimidazolone pigment.

The inkjet recording system is a printing system in which a liquid ink having high fluidity is ejected from a fine nozzle and attached on a recording medium, for example, paper, to perform printing. The system has a feature in that an image having high resolution and high quality can be printed at a high speed and with a low noise using a relatively inexpensive device and has rapidly become widespread. Since a colorant of the ink used in the inkjet recording system is superior in light fastness, weather fastness and water resistance required for high image quality printing, inks containing pigment as the colorant are increasing.
Color printing in inkjet recording is ordinarily performed by expressing various hues by using a three color ink set composed of pigment inks of the three colors yellow (Y), magenta (M) and cyan (C) which are the three primary colors in subtractive color mixing, or a four color ink set that includes black (K) in addition to these three colors. Since pigments may differ in the structure, surface treatment or particle size thereof; when two kinds of pigments are used in one ink (for example, Y ink), dispersion states of the pigments change, leading to deterioration of storage stability, and causing changes in tint. Therefore, a single pigment is ordinarily used in the respective inks of Y, M, C and K.
In aqueous inks, on the other hand, it has been attempted to use plural kinds of pigments in one ink from the standpoints of color-forming property and glossiness. For example, in Patent Document 1, it is described that the color-forming property of an aqueous ink is improved by using a mixture of pigment dispersions dispersed by different dispersion means. Also, in Patent Document 2, it is described that the glossiness in the case of printing on glossy paper is improved by microencapsulation of a pigment mixture composed of plural kinds of organic pigments using a resin having a dispersing function.


If a second operation is performed on a driver's seat side button (or a front passenger seat side button) when a door of a vehicle is in a locked state, a controller unlocks the door and then opens a sliding door for a rear seat behind a driver's seat (or a front passenger seat). If the second operation is performed on the driver's seat side button (or the front passenger seat side button) when the door of the vehicle is in an unlocked state and the sliding door for the rear seat behind the driver's seat or the front passenger seat is in an opened state, the controller closes the sliding door and then locks the door.

1. Technical Field
The present invention relates to a door lock system for allowing a user to lock and unlock a door of a vehicle by operating an operation unit provided on an outer surface of the door.
2. Description of Related Art
In a vehicle, a door lock system for locking or unlocking a door of the vehicle when a user carrying a vehicle key assigned to the vehicle performs a pressing operation, a touch operation or the like in an operation unit provided on an outer surface of the door of the vehicle, that is, what is called a smart entry system, is installed (see, for example, Japanese Patent Application Laid Open No. 2011-58329). The operation unit of the door lock system is provided, for example, in the vicinity of a door handle used for opening/closing the door, and may be provided in the vicinity of door handles of all the doors of the vehicle in some cases.
Besides, in a vehicle using a sliding door as a rear seat door, a door lock system capable of not only performing a door locking/unlocking operation but also automatically performing a closing/opening operation of the sliding door when a user performs an operation in an operation unit provided on the sliding door may be installed. In using this door lock system, for example, if a user performs an operation in the operation unit provided on the sliding door when the doors of the vehicle are locked, the doors of the vehicle are unlocked, and thereafter, an opening operation of the sliding door is performed (namely, the sliding door is opened). Alternatively, if the user performs an operation in the operation unit provided on the sliding door when the sliding door is opened, a closing operation of the sliding door is performed (namely, the sliding door is closed), and thereafter, the doors of the vehicle are locked.


A computing device is described that identifies an element that specifies content in accordance with a markup language, where an attribute of the element defines a size of at least a portion of the content specified by the element. Prior to rendering the content specified by the element for display at a display device, the computing device modifies, based at least in part on a screen size of the display device, the attribute of the element to adjust the size of the portion of the content specified by the element based on the screen size of the display device. The computing device renders, for display, the content in accordance with the element and the modified attribute.

There is an ever-increasing demand on computing devices, including mobile computing devices, to output, for display, richer and more complex types of content. Presenting richer and more complex content can present some unique challenges for some computing devices, such as computing devices that utilize a smaller sized screen of a display device.
For example, some computing devices output content, such as an e-mail message or a webpage, for display at a display device, such as a built-in screen or external display. In some instances, an e-mail message or webpage may include richly formatted content (e.g., tagged content conforming to the hypertext markup language ("HTML")) including one or more elements associated with a variety of attributes, such as color, font, alignment, size, and the like. In such cases, an email application or web browser executing on the computing device typically presents a set of email messages or webpages as a scrollable, rendered HTML page. In some instances, a content developer can embed specific attributes within the content (e.g., by way of cascaded style sheets (CSSs), media queries, etc.) of an e-mail message or webpage to cause a rendering engine to produce a rendering of the e-mail message or webpage based on one or more predefined screen layouts that automatically fit the size of the screen at which the rendering is displayed. In some instances, by simply using one or more predefined screen layouts to produce the rendered HTML based e-mail or webpage, some of the content on the rendered HTML based e-mail or webpage may appear unrecognizably small when presented at a smaller sized screen (e.g., of a mobile phone).

Dynamic adjustment to content for a display device


In a motor-driven steering wheel position adjustment apparatus, a nut 17 being a driven member is mounted such that it can be detached from an inner column of a steering column, based on a shock load applied at the time of a secondary collision, and therefore a threaded rod of a feed screw mechanism does not have resistance with respect to displacement of the inner column in the forward direction at that time. Improvement in the protection of a driver at the time of a collision can thus be achieved, and, since an integrated member can be used for the threaded rod, silence during the position adjustment of a steering wheel by the feed screw mechanism can be ensured.

A position adjustment apparatus of a steering wheel, such as a fore-aft position adjustment apparatus called a telescopic steering apparatus, or an up-down position adjustment apparatus called a tilt-type steering apparatus, is widely used as an apparatus for adjusting the position of a steering wheel according to the physical dimensions and posture of a driver. Furthermore, conventionally, a motor-driven position adjustment apparatus for a steering wheel is also widely used, in which the position is adjusted by an electric motor based on a switching operation. For example, FIG. 35 shows a motor-driven fore-aft position adjustment apparatus for a steering wheel, which is disclosed in Patent Document 1.
In the case of this conventional structure, a steering column 1 is a so-called telescopic steering column whose overall length can be extended and contracted freely by inserting the front part of an inner column 3 provided toward the rear (right side in FIG. 35) into an outer column 2 provided toward the front (left side in FIG. 35). The rear end part (right end in FIG. 35) of a driving rod (push-pull rod, threaded rod) 5 is joined and fixed to a joining plate 4 fixed toward the rear end part of the inner column 3. Moreover, a male thread 6 provided on the front end part (left half of FIG. 35) of the driving rod 5 is screwed into a nut which is provided inside a housing 7 fixed on the outer peripheral surface of the outer column 2, such that it can only rotate freely, and which is rotated in a desired direction by an electric motor, to thereby form a feed screw mechanism. When adjusting the fore-aft position of a steering wheel 8, the inner column 3 is pushed or pulled in the axial direction (left/right direction in FIG. 35) by the feed screw mechanism to extend and contract the steering column 1. A steering shaft 9, on the rear end part of which is fixed the steering wheel 8, is supported inside of the inner column 3 such that it can only rotate freely, and can be extended and contracted freely by a spline engagement part. Accordingly, the fore-aft position of the steering wheel 8 can be adjusted as the steering column 1 is extended and contracted.
The construction and operation of a motor-driven steering wheel fore-aft position adjustment apparatus is as described above. However, in order to protect a driver at the time of a collision accident, regardless of the existence of the above-described driving rod 5, a structure is required whereby the steering wheel 8 can be displaced forward. That is, at the time of a collision accident, following a so-called first collision where a vehicle collides with another vehicle or the like, a so-called secondary collision occurs where the driver's body (mainly chest or head) collides with the steering wheel 8. In order to relieve the impact on the driver's body at the time of this secondary collision, a construction is required in which the steering wheel 8 is displaced forward simultaneously with the secondary collision.
In the case of the construction shown in FIG. 35, since the steering column 1 and the steering shaft 9 are constructed such that they can both be extended and contracted freely, it is possible to form a structure directly in which the steering wheel 8 is displaced forward simultaneously with the secondary collision. However, since the driving rod 5 does not contract by its full length as it stands, but creates an impediment between the outer column 2 and the inner column 3 constituting the steering column 1, the steering column 1 does not contract. Needless to say, since the outer column 2 is supported relative to the vehicle such that it falls away forward simultaneously with the secondary collision due to the structure disclosed in Patent Documents 2 and 3 for example, even if there is a driving rod 5 as described above, it does not mean that there is no displacement of the steering wheel 8 forward at all. However, to the degree that the steering column 1 does not contract, not only does the peak of the shock load tend to occur at the initial stage of the secondary collision, but also the amount of forward displacement of the steering wheel 8 is reduced, and hence it is a disadvantage from the aspect of satisfactory protection of the driver.
Therefore, the abovementioned Patent Document 1 describes an invention related to a driving rod 5a that contracts by its full length based on a shock load applied during a secondary collision, using a structure as shown in FIG. 36 for example. The driving rod 5a comprises a cylindrical outer casing 10, and an internal shaft 11 joined by a pin 12 formed from a synthetic resin or a soft metal. The driving rod 5a as described above contracts by its full length as the pin 12 is broken by the shock load applied during the secondary collision. Accordingly, the driving rod 5a does not create an impediment between the outer column 2 and the inner column 3, and hence the steering column 1 is allowed to contract during the secondary collision.
However, it is difficult to ensure the concentricity of the driving rod 5a comprising the outer casing 10 and the internal shaft 11, over its full length. That is, the part toward one end and the part toward the other end of the driving rod 5a tend to be out of alignment. If it becomes eccentric, a non-uniform force acts on the part where the male thread 6 of the driving rod 5a and the nut screw together, and when rotating the driving rod 5a in order to adjust the fore-aft position of the steering wheel 8, annoying grinding noises, and uncomfortable vibrations are likely to occur.
Furthermore, it can also be considered that forming a nut, which constitutes a feed screw mechanism with a driving rod, from a synthetic resin, and breaking the female thread of the nut during the secondary collision, enables the displacement in the axial direction of the driving rod with respect to the nut, enabling the steering column to contract. However, in the case where such a structure is used, it is difficult to design to ensure the reliability (difficulty of breaking) of the threaded part of the male thread of the driving rod and the nut, and also to break the female thread reliably during the secondary collision.
[Patent Document 1] Japanese Patent Application Publication No. 2003-276616
[Patent Document 2] Japanese Patent Application Publication No. Hei 11-165643
[Patent Document 3] Japanese Patent Application Publication No. 2000-233758

Motor-driven position adjustment apparatus for steering wheel


Methods for correcting errors in a GFP-T superblock include buffering the 64 bytes of data in an 8×8 byte buffer, buffering the flag byte in a separate buffer, calculating the CRC remainder, and performing single and double bit error correction in three stages. In the first stage, the CRC remainder is compared to a single bit error syndrome table and if an error is located, it is corrected. In the second stage, the CRC remainder is compared to a double bit error syndrome table and if an error is located, it is corrected. The third stage corrects the second error of a double bit error. The flag byte is processed first, followed by the data bytes, eight bytes at a time.

1. Field of the Invention
This invention relates broadly to telecommunications. More particularly, this invention relates to highly efficient error correction of GFP superblocks.
2. State of the Art
The Synchronous Optical Network (SONET) or the Synchronous Digital Hierarchy (SDH), as it is known in Europe, is a common telecommunications transport scheme. SONET was designed in the early 1980s to accommodate a plurality of time division multiplexed continuous signals such as T-1 or E-1 signals. T-1/E-1 signals were designed in the 1960s to carry a plurality of digitized audio (telephone) signals from one telephone company office (switch) to another.
Developed in the early 1970's, ETHERNET was designed primarily to allow multiple personal computers to share a single laser printer. Although ETHERNET has gone through many changes since the first version was used in 1973, it is still fundamentally not synchronous. Unlike SONET/SDH which was developed to carry many continuous streams of data multiplexed in a regularly occurring frame of fixed length, ETHERNET was designed to carry discontinuous data streams in randomly occurring packets of widely varying length. A word used to describe this nature of ETHERNET is "bursty". In addition to ETHERNET, some other networking protocols have been developed for storage area networks (SANs). These other protocols include Fiber Channel, ESCON (enterprise system connection), and FICON (fiber connection). They are similar to ETHERNET in that they are bursty.
For many years, it has been recognized that it would be desirable to transmit ETHERNET packets over long distances using a SONET/SDH network. However, because of the fundamental differences between synchronous frames and asynchronous packets, some mechanism was needed to encapsulate the ETHERNET data within a SONET/SDH frame. The challenge in doing this is to fill the SONET frame with as much ETHERNET data as possible so that bandwidth is not wasted while at the same time providing minimal latency (time data waits in a buffer before being transmitted). One of the latest methods for accomplishing this task is called the Generic Framing Procedure (GFP). GFP is "generic" because it is designed to transport any signal including ETHERNET, Fiber Channel, ESCON, FICON, and others over fixed data rate optical channels in a SONET/SDH network or OTN (optical transport network).
GFP is used in conjunction with other SONET/SDH specifications such as Virtual Concatenated Groups (VCGs) and Link Capacity Adjustment Scheme (LCAS) to map variable length packets into "containers" (also known as "tributaries") of a SONET/SDH frame.
There are currently two modes of mapping data into a GFP frame: frame mapped GFP (GFP-F) and transparent mapped GFP (GFP-T). GFP-F is used for ETHERNET (some versions but not all) and other protocols where the entire client frame is mapped into a single GFP frame. GFP-T facilitates the transport of block coded signals such as those of Fiber Channel, ESCON, FICON, and Gigabit ETHERNET, which also require very low transmission latency.
Prior art FIG. 1 illustrates the fields of a GFP frame. The two basic parts of the frame are the core header (4 bytes) and the payload area (variable length up to 65535 bytes). The core header includes a payload length indicator (PLI, 2 bytes) and the core header error correction (cHEC) code (2 bytes). The payload area includes the payload header (4 to 64 bytes), the payload information field (up to 65531 bytes), and an optional payload FCS (4 bytes). The payload header includes the type (4 bytes) and an extension header identifier (0 to 60 bytes).
The present invention is concerned with GFP-T. As mentioned above GFP-T facilitates the transport of block coded signals which also require very low transmission latency. These signals are encoded by clients with an 8B/10B block code. This code is used to communicate data and control information. More particularly, the 8-bit data values are mapped (encoded) into a 10-bit "transmission character". The code assignment is arranged so that the number of 1s and 0s transmitted on the line remains balanced. This increases the number of line transitions, thereby facilitating PLL synchronization. It also maintains DC balance over time. In addition, twelve of the 10-bit codes are reserved for use as control codes so that the data source may signal the data sink.
In order to transport 8B/10B encoded signals over the SONET/SDH network, GFP-T decodes the 8B/10B characters into 8-bit data characters and control codes. Eight of the decoded characters are mapped into the eight payload bytes of a 64B/65B code. This is shown by example in prior art FIG. 2. The (leading) flag bits of the 64B/65B code (shown as octet L in FIG. 2) indicate whether the 64B/65B block includes any control codes, i.e. a flag=1 indicates that the octet in the corresponding position of the next eight octets is a control code. In a GFP-T frame, after the 4 byte payload header, the payload area is filled with a plurality of "superblocks". Each superblock includes eight 64B/65B blocks and one 16-bit CRC, i.e. 67 bytes. The last octet of the superblock before the CRC includes eight flag bits. This is often referred to as the "superblock control byte". Prior art FIG. 3 illustrates the mapping of the superblock.
In order to address the physical properties of the transport medium and to aid in maintaining synchronization, GFP frames are scrambled by a self-synchronous scrambler. The scrambler uses a polynomial of x43+1. The scrambler takes each bit of the payload area (including the superblock CRC) and exclusively ORs it with the scrambler output bit that precedes it by 43 bit positions. The scrambler state is retained between successive GFP frames, making it more difficult for a user to purposely choose a malicious payload pattern (e.g. one which would cause loss of synchronization). The superblock CRC is calculated prior to scrambling and is checked at the decoder after descrambling. An unfortunate drawback of this scrambling technique is that each transmission error produces a pair of errors (43 bits apart) in the descrambled data stream. The CRC, therefore, must be able to correct these two errors. The recommended CRC generator polynomial generates a superblock CRC which can detect three bit errors, correct single bit errors, and correct double bit errors spaced 43 bits apart. To accomplish this, the syndromes for single bit errors and double bit errors spaced 43 bits apart are all unique.
When demapping a GFP-T signal, the superblock control byte must be "realigned" (the flag bits moved back to their original leading bit locations) before the 64B/65B code can be mapped back into 8B/10B code. Before this is done, the superblock CRC is used to detect and possibly correct bit errors in the superblock. The recommended demapping procedure is detailed in ITU specification G.7041, the complete disclosure of which is hereby incorporated herein by reference.
The following description is taken from the G.7041 specification. The 16 error control bits in a superblock contain a CRC-16 error check code over the 536 bits in that superblock. If the demapper detects an error, it should output either 10B error characters or unrecognized 10B characters in place of all of the client characters contained in that superblock. This replacement guarantees that the client receiver will be able to detect the presence of the error. The generator polynomial for the CRC-16 is G(x)=x16+x15+x12+x10+x4+x3+x2+x+x0 with an initialization value of zero, where x16 corresponds to the MSB and x0 to the LSB. The superblock CRC is generated by the source adaptation process using the following steps:
1. The first 65 octets of the superblock are taken in network octet order, most significant bit first, to form a 520-bit pattern representing the coefficients of a polynomial M(x) of degree 519.
2. M(x) is multiplied by x16 and divided (modulo 2) by G(x), producing a remainder R(x) of degree 15 or less.
3. The coefficients of R(x) are considered to be a 16-bit sequence, where x15 is the most significant bit.
4. This 16-bit sequence is the CRC-16.
Single error correction is also possible with this CRC-16. However, since the sink adaptation process performs the CRC-16 check after the payload descrambling is performed, the error correction circuit should account for single bit errors as well as double errors spaced 43 bits apart coming out of the descrambler.
The sink adaptation process performs steps 1-3 in the same manner as the source adaptation process. In the absence of bit errors, the remainder shall be 0000 0000 0000 0000.
Though not stated in the G.7041 specification, when the remainder is not zero it is referred to as a "syndrome". Syndromes can be used to detect the location of a bit error in conjunction with a syndrome table which has a 1:1 correspondence with each bit in the payload.
The G.7041 recommendation has several disadvantages. Processing an entire superblock according to the recommendation requires a 536-bit datapath and a relatively large amount of storage space which complicates implementation on a chip. It is also difficult to support high speed applications when processing all sixty-seven bytes at one time. The physical size of the logic introduces latency.
Although parts of the G.7041 recommendation can be ignored while still maintaining interoperability, there are several issues which cannot be ignored. These issues include the following: the flag byte (which is the last byte before the FCS bytes in the superblock) must be corrected before processing any of the other bytes in the superblock; double bit error correction requires that errors be correctable for bits which are 43 bits apart; and there needs to be an indication of whether a detected error has been corrected.

Methods and apparatus for error correction of transparent GFP (Generic Framing Procedure) superblocks


A low-k organic dielectric material having stable nano-sized porous is provided as well as a method of fabricating the same. The porous low-k organic dielectric material is made from a composition of matter having a vitrification temperature (Tv-comp) which includes a b-staged thermosetting resin having a vitrification temperate (Tv-resin), a pore generating material, and a reactive additive. The reactive additive lowers Tv-comp below Tv-resin.

The semiconductor industry's drive to continually improve performance and density has forced the use of advanced materials and interconnect structures. High interconnect performance requires the reduction of resistance and capacitance. Copper metallization was introduced in 1998 to reduce the resistance of interconnect wiring. Capacitance reduction or the introduction of low dielectric constant insulators, herein referred to as low-k dielectrics, are needed for future performance enhancements.
For over 25 years, silicon dioxide has been the dielectric insulator of choice for the semiconductor industry. Silicon dioxide possesses excellent dielectric breakdown strength, a high modulus, good thermal conductivity, a low coefficient of thermal expansion, and excellent adhesion to metallic liners, plasma enhanced chemical vapor deposited (PECVD) barrier cap layers, and other like materials. However, with reduced ground rule dimensions and the need for improved performance, silicon dioxide is slowly being phased out and replaced with materials possessing lower permitivity to achieve reduced capacitance. For example, at the 180 nm technology node, fluorosilicate glass is replacing silicon dioxide in many applications.
At the 130 nm technology generation, "true" low-k dielectrics are being implemented into semiconductor products. There are several candidate materials but the industry has focused primarily on two material classes: spin-on polymers and carbon-doped PECVD silicon dioxide dielectrics.
Polymer dielectrics may be used as insulating layers between various circuits as well as layers within circuits in microelectronic devices, such as integrated circuits, multichip modules, and laminated circuit boards. The microelectronics fabrication industry is moving toward smaller geometries in its devices to enable lower power and faster speeds. As the conductor lines become finer and more closely packed, the requirements of the dielectrics between such conductors become more stringent.
While polymer dielectrics often provide lower dielectric constants than inorganic dielectrics, such as silicon dioxide, polymer dielectrics often present challenges to process integration during fabrication. For example, to replace silicon dioxide as a dielectric in integrated circuits, the polymer dielectric must be able to withstand processing temperatures during metallization and annealing steps of the process. Preferably, the dielectric material should have a glass transition temperature greater than the processing temperature. The dielectric must also retain the desirable properties under device use conditions. For example, the dielectric should not absorb water which may cause an increase in the dielectric constant and dielectric loss and which may potentially lead to corrosion of metal conductors.
Porous thermoplastic polymers, particularly thermally stable polymers, such as polyimides, have also been investigated for use as low-k alternatives to silicon dioxide. Although such porous thermoplastic materials can be made to have acceptable dielectric constants and are relatively tough, being able to withstand the mechanical processing steps necessary to fabricate microelectronic devices, the pores tend to collapse during subsequent high temperature processing thereby precluding porous thermoplastic polymers for applications of interest.
Another class of low-k polymers that are attracting considerable interest in the microelectronics industry is thermosetting resins, particularly polyarylene resins. Such thermosetting resins are disclosed, for example, in WO 98/11149. Specifically, WO 98/11149 discloses dielectric polymers, which are the reaction products of a cyclopentadienone functional compound and an acetylene functional compound.
Although thermosetting resins are available, it has been determined that such resin formulations may suffer from pore collapse when attempting to form a porous structure from the resin by introducing a porogen into the b-staged formulation, thereby rendering such porous thermosetting resins also unsuitable for use in many microelectronic applications.
The prior art literature in this field may be divided into a number of different classes. The first is the formation of bloomers that are functionalized with acetylenic substituents that are capable of inducing chain extension or crosslinking during processing. The crosslinking may be thermal or promoted by a catalyst. These prior art references are characterized by oligomeric materials containing acetylenic substituents bound to the oligomers. The prior art falling into this group include, for example, U.S. Pat. Nos. 4,587,315, 5,493,002, 5,426,234, 5,446,204, 6,265,753, 5,268,444 and 5,312,994.
There are a number of patents such as, for example, U.S. Pat. Nos. 6,288,188, 6,252,001 and 6,121,495, that describe the preparation of b-staged solutions of polyarylenes prepared from different intermediates and subsequent thermosetting after processing. While the matrix materials are similar, the reactive functionality (type and number) is determined by monomer stoichiometry before b-staging.
U.S. Pat. No. 6,093,636 describes the preparation of porous organic thermosets including polyarylene compositions by the thermal labile porogen approach. These porous organic thermosets may suffer from pore collapse.
U.S. Pat. Nos. 5,426,234, 5,446,204, 5,268,444 and 5,312,994 describe the use of various acetylenic reactive diluents which react with functionalized oligomers. In these prior art references the goal was to lower viscosity for polymer melt processing and to increase the crosslinking density after curing. This technique was applied to the formation of dense thermosetting polymers with no mention of porosity.
U.S. Pat. No. 6,359,091 describes a polyarylene composition in which the thermosetting resin does not undergo a significant drop of modulus at temperatures above 300° C. during curing. That feature reportedly enabled one to form porous films by avoiding pore collapse. Specifically, the '091 patent discloses that by modifying the formulations so that the resins do not undergo a significant drop in modulus during cure or alternatively shifting the temperature at which the minimum modulus occurs to a lower temperature enables one to avoid pore collapse. Thus, in the '091 patent the modulus-temperature profile is modified such that the modulus drop of the b-staged resin prior to network formation is minimized. In the '091 patent, a crosslinker is added to a polyarylene oligomer solution.
U.S. Pat. No. 6,468,589 describe a composition for film formation which comprises a poly(arylene ether) polymer having repeating structural units represented by formula (1) mentioned at Col. 2, lines 25-34. The poly(arylene ether) polymer is made by heating a bisphenol compound and a dihalogenated compound in a solvent in the presence of a catalyst such as an alkali metal compound. Crosslinking agents such as actylenes may be present in this prior art composition.
In view of the state of the art mentioned hereinabove, there is still a need for providing thermosetting polymer compositions which are capable of providing a low-k dielectric material having nano-sized pores which are substantially stable and do not collapse during further high temperature processing
In the present invention, a low molecular weight compound that plasticizes the resin and acts as a reactive additive is employed in forming thermosetting polymer compositions. During the thermal ramp to the cure temperature, one role of the additive of the present invention is to create a situation where the glass transition temperature of the materials advances to a temperature above the actual cure temperature of the system, i.e., to modify the classical Time Temperature Transformation profile for the thermoset. This aspect of the present invention is not described in any of the above mentioned references. A characteristic of many organic thermosets is that the glass transition temperature of the thermoset closely tracks the cure temperature. In the present application, by using the inventive additive, the applicants have unexpectedly determined that a condition is created where the glass transition temperature of the thermoset increases to a temperature above the cure temperature, provided a threshold temperature is exceeded. This feature is not mentioned in any of the prior art mentioned above.

Porous composition of matter, and method of making same

International Business Machines Corporation


Provided are hydroxycucurbituril derivatives, their preparation methods and uses. The hydroxycucurbituril derivative is easy to further functionalize with enhanced solubility in common solvents, thereby providing wider applications.

1. Field of the Invention
The present invention relates to hydroxycucurbituril derivatives, their preparation methods and uses, and more particularly, hydroxycucurbituril derivatives which can easily introduce substituents according to uses, their preparation methods and uses.
2. Description of the Related Art
Cucurbituril was first reported by R. Behrend, E. Meyer and F. Rusche in 1905. According to their report (Liebigs Ann. Chem. 1905, 339, 1.), the condensation of glycoluril and excess formaldehyde in the presence of hydrochloric acid (HCl) produces an amorphous solid. Dissolution of the solid in hot concentrated sulfuric acid, dilution of the solution with water followed by slow cooling of the solution to room temperature produces a crystalline material. They wrongly characterized this substance as C10H11N7O4.2H2O without discovery of its structure.
In 1981, this substance was rediscovered by Mock and coworkers. They correctly characterized it as a hexameric macrocyclic compound with composition of C36H36N24O12, which was also confirmed by X-ray crystal structure determination (J. Am. Chem. Soc., 1981, 103, 7367). They named it cucurbituril which we from now on refer to as cucurbit[6]uril. Since then an improved preparation procedure for cucurbit[6]uril has been disclosed (DE 196 03 377 A1).
In 2000, Kim and coworkers synthesized novel cucurbit[6]uril homologues thereof, cucurbit[n]uril (n=5, 7, 8) and isolated the same, which were confirmed by X-ray crystal structure determination (J. Am. Chem. Soc., 2000, 122, 540).
WO 00/68232 discloses cucurbit[n]uril having the formula:
wherein n is an integer between 4 and 20.
The cucurbituril derivatives are compounds of substitutent-free glycoluril monomers.
A cucurbituril deriviative synthesized from glycoluril having a substituent introduced thereto has been reported (Angew. Chem. Int. Ed. Engl. 1992, 31, 1475). According to this report, decamethylcucurbit[5]uril was synthesized using five dimethanodimethylglycoluril units forming a cyclic structure by the condensation of dimethylglycoluril and formaldehyde.
However, in the cucurbiturils and their derivatives proposed up to now, it is not easy to introduce functional groups thereto by substitution, and thus their applications are limited. Also, in order to produce substituted cucurbituril derivatives, different glycoluril monomers must be synthesized and subjected to cyclization, making their synthetic methods complex.

Hydroxycucurbituril derivatives, their preparation methods and uses


(Meth)acrylates are prepared in a single-step method from a mixture of (meth)acrylic acid and at least one biobased oil and/or its derivative(s), including at least one unsaturation. The (meth)acrylates are made by directly adding the (meth)acrylic acid to the biobased oil by reacting in the presence of an acid catalyst, including an inorganic or organic acid having at least one oxygen atom present thereon and which possesses at least one acid functionality having an ionization constant in water which is not greater than 3.

(Meth)acrylate functional biobased oils (derived from plants and animals) and biobased oil derivatives are an important platform of chemicals. For example, acrylated epoxidized soybean oil can be a starting material for coatings, adhesives, plasticizers, inks, paints, lubricants and other applications. (Meth)acrylate functional oils are traditionally synthesized through a two step process: 1) epoxidation of unsaturations in the hydrocarbon structure of the oil, followed by 2) (meth)acrylation of the epoxide groups to yield a desired product. Scheme I illustrates such a global reaction scheme using soybean oil and acrylic acid as example starting materials.

Methods of direct addition of (meth) acrylic acid to bio-based oils


Examples herein describe an accelerator device that shares the same coherent domain as hardware elements in a host computing device. The embodiments herein describe a mix of hardware and software coherency which reduces the overhead of managing data when large chunks of data are moved from the host into the accelerator device. In one embodiment, an accelerator application executing on the host identifies a data set it wishes to transfer to the accelerator device to be processed. The accelerator application transfers ownership from a home agent in the host to the accelerator device. A slave agent can then take ownership of the data. As a result, any memory operation requests received from a requesting agent in the accelerator device can gain access to the data set in local memory via the slave agent without the slave agent obtaining permission from the home agent in the host.

In the traditional I/O model, a host computing system interfaces with a peripheral I/O device (e.g., an accelerator) when executing accelerator tasks or functions using custom I/O device drivers unique to the peripheral I/O device. The disadvantage of this model is that all accelerator-memory interactions must go through the home agent node in the main CPU-memory complex, sometimes referred to as a server host. This model uses hardware enforced coherency and thus, regardless of whether the accelerator-memory data footprint is orders of magnitude (MB, GB, or even TB) larger than a cacheline, all accelerator-memory interactions are both serviced and tracked by the home agent node even if the processor (producer) on the server host may eventually only access a fraction of that data footprint on which the accelerator has performed computations over. Another disadvantage is that all memory accessed and cached by the accelerator is remote, server host attached memory. A further disadvantage of this model is that a PCIe I/O based accelerator is unable to cache the memory. Accelerator-memory interactions only take place with server host attached memory and the latency, bandwidth, and protocol messaging overhead disadvantages of that approach.
Meanwhile, the hardware cache-coherent shared-memory multiprocessor paradigm leverages a generic, instruction set architecture (ISA)-independent, model of interfacing in the execution tasks or functions on multiprocessor CPUs. The generic, ISA-independent (e.g., C-code) model of interfacing scales with both the number of processing units and the amount of shared memory available to those processing units. Traditionally, peripheral I/O devices have been unable to benefit from the coherent paradigm used by CPUs executing on the host computing system.

Hybrid hardware-software coherent framework


A fuel injection nozzle includes: a nozzle body having a plurality of injection holes; and a needle accommodated in the nozzle body to inject a DME fuel containing dimethyl ether as a main component. The nozzle body has a seat part to which the needle seated or from which the needle separated, and a tip end chamber arranged downstream of the seat part in a flow of the DME fuel to communicate with the plurality of injection holes. The DME fuel in the tip end chamber is heated with combustion heat in a combustion chamber of an internal combustion engine to have a supercritical state.

Supercritical injection is used in a diesel engine to prevent ignition delay which is caused by evaporation latent heat generated in liquid phase injection. Furthermore, there is a merit that a mass-based injection rate can be made higher in the supercritical injection than in gas phase injection.
In U.S. Pat. Nos. 7,488,357 B2 and 8,197,558 B2, fuel containing light-oil as a main component and inactive gas such as exhaust gas or liquid CO2 is heated to have a supercritical state, and is supplied to an injector. In this case, the fuel can be injected in the supercritical state, preventing a caulking.
However, in order to make the fuel into the supercritical state from the liquid phase, a very high temperature is required, so large-scale complicated heating system is used to provide the supercritical state before supplying to the injector. Moreover, the system becomes further complicated since a fuel mixture equipment is provided for preventing the caulking in U.S. Pat. Nos. 7,488,357 B2 and 8,197,558 B2.
Moreover, U.S. Pat. Nos. 7,488,357 B2 and 8,197,558 B2 are difficult to be applied to a DME fuel mainly containing dimethyl ether (DME) because a phase change is easily generated in the DME fuel.


A fiber optic faceplate for coupling with optical sources or detectors. The optical sources or detectors are arranged in a two-dimensional array. Each of the sources or detectors has a pixel area precisely located at a predetermined coordinate. The faceplate includes a plurality of drawn and fused optic fibers. Each of the optic fibers is positioned at a corresponding position to the pixel areas of the optical sources or detectors. Interstitial fillers are located at each interstitial space between optic fibers and have an outside diameter corresponding to the space between the optic fibers to maintain the optic fibers in an aligned position as they are drawn.

The present invention is directed to a fiber optic or wave guide faceplate for transmission of a light signal from or to a source or detector. More particularly, the present invention provides a faceplate for use with an array of sources or detectors in which the optical fibers or wave guides are precisely aligned with the sources or detectors.
Fiber optic faceplates are known in the field of imaging applications. In these prior known faceplates, it was desirable that the fibers be as small as possible to improve resolution of the sample image. In the past, faceplates have been fabricated with fiber sizes as small as three microns. Typically, these faceplates utilized an over-sampled approach in which as large a number as possible of these small fibers were utilized within the area of an optical source or detector in order to transmit a light signal. An example of a faceplate having an over-sampled approach is shown in FIG. 1, where the optical fibers 7 are closely packed. The interface with the pixels 8 of the optic sources or detectors is a random alignment. The actual active optical fibers are designated as 7xe2x80x2 and shown with an unshaded center.
This over-sampled approach allows for ease of alignment of the array to the source or detector. However, this approach has inherent drawbacks as additional source and detector pixels are added. It has been recently proposed to move to two-dimensional arrays of sources and detectors having over four hundred elements. In such applications, there is an increase in the desire to save power and thus reduce the amount of heat generated. With the over-sampled approach, over 30% percent of the light is lost to the cladding surrounding each fiber. In addition, it is desirable to provide faceplates having optical fibers which are compatible with the system optical fibers. This indicates a future need for faceplates having graded index (GRIN) fibers and single mode fibers. These structures are not possible with the known over-sampled approaches.
It would be desirable to provide a faceplate having precision-aligned fibers located in the position of the pixel areas of the sources or detectors which are being optically linked.
Briefly stated, the present invention is directed to a fiber optic faceplate for coupling with optical sources or detectors. The optical sources or detectors are arranged in a two-dimensional array. Each of the sources or detectors has a pixel area precisely located at a predetermined x-y coordinate spaced at an equal distance from neighboring pixel areas. The faceplate includes a plurality of drawn and fused optic fibers and interstitial fillers. Each of the optic fibers is positioned at a corresponding position to the pixel areas of the optical sources or detectors. The optic fibers are drawn to an outside diameter corresponding to the spacing distance between the predetermined x-y coordinates. The interstitial fillers are located at each interstitial space between optic fibers and have an outside diameter corresponding to the space between the optic fibers to maintain the optic fibers in an aligned position as they are drawn.
In another aspect, the present invention provides a fiber optic faceplate for coupling with optical sources or detectors. The optical sources or detectors are arranged in a two-dimensional array, with each individual source or detector being precisely located at predetermined position spaced apart from neighboring sources or detectors. The faceplate includes a plurality of drawn and fused optic fiber bundles. Each optic fiber bundle includes a plurality of optic fibers and has a greater cross-sectional area than an area of a pixel of the source or detector. Each optic fiber bundle is located in a generally aligned position with a corresponding pixel of the source or detector such that the pixel is aligned with at least half of the active area of the corresponding bundle. A filling material is located between the adjacent fiber bundles to maintain the fiber bundle in position as they are drawn and fused.
In another aspect, the present invention provides a wave guide faceplate including a plurality of fused and drawn wave guides and interstitial fillers. Each of the wave guides is positioned at a corresponding position to the optical sources or detectors. The wave guides have an outside diameter corresponding to the spacing distance between predetermined x-y coordinates. The interstitial fillers are located at each interstitial space between neighboring wave guides and have an outside diameter corresponding to the space between the wave guides to maintain the wave guides in an aligned position as they are drawn.


An apparatus and a method for effectively recovering acetic acid and catalyst from a mother liquor discharged from a series of processes including an oxidation process, a crystallization process and a solid-liquid separation process, in a continuous process for preparing naphthalenedicarboxylic acid by oxidizing dimethylnaphthalene in the presence of an oxygen-containing gas and an acetic acid solvent, using a catalyst system comprising a transition metal such as cobalt or manganese, and a bromine-based compound, are provided.

1. Field of the Invention
The present invention relates to an apparatus and a method for effectively recovering acetic acid and catalyst from a mother liquor discharged from a series of processes including an oxidation process, a crystallization process and a solid-liquid separation process, in a continuous process for preparing naphthalenedicarboxylic acid by oxidizing dimethylnaphthalene in the presence of an oxygen-containing gas and an acetic acid solvent, using a catalyst system comprising a transition metal such as cobalt or manganese, and a bromine-based compound.
2. Description of the Related Art
In general, a variety of separation processes can be employed to recover acetic acid and catalyst that have been used in the process.
For the method of recovering acetic acid, it is common to use an acetic acid recovery process using a distillation method, but this process is economically unfavorable. Meanwhile, a filtration method and an absorption method are not suitable for separating acetic acid and catalyst. Thus, a variety of different methods for recovering acetic acid and catalyst have been suggested. U.S. Pat. No. 4,883,912 describes a process for recovering acetic acid by extracting acetic acid from an acetic acid solution containing metallic substances, using tertiary amine and an organic diluent as the solvent for acetic acid extraction. However, this method is not suitable as the method for recovering acetic acid and catalyst in the process for preparation of naphthalenedicarboxylic acid, because the method of extraction requires a post-treatment process after the separation and recovery of acetic acid, and the reactivities of the solvent for extraction and of the oxidation catalyst need to be taken into account.
There are available an incineration method, a vacuum filtration method, and an electrochemical method as the methods for catalyst recovery, but these methods are still not commercialized.

Apparatus and method for recovering acetic acid and catalyst in process for preparation of 2,6-naphthalenedicarboxylic acid


A package on package (PoP) apparatus includes a shared ZQ calibration path and a shared ZQ calibration resistor for calibrating multiple channels of DRAM on a memory package of the PoP apparatus. Arbitration circuitry on a processor package of the PoP apparatus is coupled to separate memory controllers for the multiple memory channels. The arbitration circuitry is configured to indicate availability of the shared ZQ calibration resistor. The memory controllers are configured to communicate with the arbitration circuitry before performing a ZQ calibration and to delay the ZQ calibration when the arbitration circuitry indicates the ZQ calibration resistor is busy.

Numerous semiconductor packaging methods facilitate increased scaling of circuitry and reduce the size and cost of electronic systems for products such as mobile phones, tablets and other mobile computing devices. For example, package on package (PoP) is a semiconductor packaging method that is commonly used to reduce the area of printed circuit boards that support multiple semiconductor packages in a mobile device. PoP involves stacking of multiple ball grid array (BGA) packages in which a bottom BGA package is coupled to a printed circuit board, and one or more top BGA packages are coupled to the bottom BGA package. The bottom BGA package may be a processor package, such as a system on a chip (SoC) package for a mobile device. The top package may be a memory package such as a mobile dynamic random access memory (DRAM) package coupled to the SoC in the bottom package. The mobile DRAM may include one or more independently accessible system channels.

Semiconductor package on package memory channels with arbitration for shared calibration resources