The invention provides biomedical devices. In particular, the invention provides biomedical devices on the surfaces of which stable, hydrophilic, amide-containing coatings are formed.

This invention relates to biomedical devices. In particular, the invention provides biomedical devices on the surfaces of which stable, hydrophilic, amide-containing coatings are formed.
Devices for use in and on the human body are well known. The chemical composition of the surfaces of such devices plays a pivotal role in dictating the overall efficacy of the devices. For example, many devices, including catheters, stents, lenses, and implants require biologically non-fouling surfaces, meaning that proteins, lipids, and cells will not adhere to the surfaces. Lenses also must be wettable by tear fluid in order to ensure wearer comfort. Additionally, providing such devices with an antimicrobial surface is advantageous.
A wide variety of methods have been developed to coat device surfaces to provide them with desired characteristics. However, the need still exists for a simple, efficient process that will provide a stable, hydrophilic coating.
The present invention provides a simple, economical process for producing devices with stable amide group-containing coatings including, without limitation, polyacrylamide coatings. In one embodiment, the invention provides a method for manufacturing biomedical devices comprising, consisting essentially of, and consisting of contacting at least one surface of a biomedical device, the surface comprising, consisting essentially of, and consisting of an effective amount of carboxyl groups with a coating-effective amount of an amine and a coupling effective amount of at least one coupling agent under conditions suitable to produce a stable, amide-containing coating on the surface. In another embodiment, the invention provides biomedical devices comprising, consisting essentially of, and consisting of a biomedical device at least one surface of the device having an amide-containing coating coupled thereto by at least one coupling agent.
By xe2x80x9cbiomedical devicexe2x80x9d is meant any device designed to be used while in or on either or both human tissue or fluid. Examples of such devices include, without limitation, stents, implants, catheters, and ophthalmic lenses. In a preferred embodiment, the biomedical device is an ophthalmic lens including, without limitation, contact or intraocular lenses. More preferably, the device is a contact lens.
It is an unexpected discovery of the invention that devices having carboxyl groups on their surfaces may be contacted with an amine to provide a hydrophilic, amide-containing coating for biomedical devices. It is another unexpected discovery of the invention that a high conversion of carboxyl groups to amide groups is obtained through the process of the invention. More specifically, a conversion of greater than about 80 percent, more preferably greater than about 90 percent, most preferably about 95 percent or greater, of the carboxyl groups to amide groups may be obtained. The carboxyl groups must be present in an amount effective to produce the desired number of amide groups when reacted with an amine. This amount is an amount of carboxyl groups per square centimeter of lens surface of about 0.65 to about 65 nMol/cm2, preferably about 1 to about 50, more preferably about 1 to about 10 nMol/cm2 of carboxyl groups.
In the process of the invention, a coating-effective amount of an amine is used, which amount is sufficient to convert the carboxyl groups present to the desired degree. The amine may be used as a part of a solution containing a solvent, such as an alcohol, tetrahydrofuran, or the like, or an aqueous solution. Preferably, an aqueous solution is used. The amount of amine in the solution may be about 5 volume percent, preferably about 1 volume percent, more preferably less than about 1 volume percent. The coatings produced by the process of the invention are stable, meaning that subjecting the coating to autoclaving, washing with a cleaning agent, and/or rinsing with a saline solution does not substantially alter the chemical properties of the coating.
A coupling effective amount of the coupling agent is used which amount is sufficient to enable to reaction of the carboxyl groups with the amine. The precise amount of coupling agent used will depend on the surface""s chemistry as well as the amine and coupling agent selected. The amount of coupling agent used generally will be about 0.01 to about 25 weight percent, preferably about 0.1 to about 15, more preferably, about 0.1 to about 10 weight percent of the coating solution, or solvent, coupling agent and optional buffer. Suitable solvents are those capable of solubilizing both the amine and the coupling agent. Preferably, the process is carried out in a water, or aqueous, solution.
The contacting time typically may be about 1 to about 360 minutes, preferably 1 to about 240 minutes. The contacting temperature may be about 0 to about 95, preferably about 5 to about 80xc2x0 C. The contacting, or reacting, of the amine and carboxyl groups may be carried out in any convenient manner.
Amines useful in the invention are any primary or secondary amines, their corresponding acid salts, amine-containing proteins, amine-containing antibiotics, and the like, and combinations thereof Examples of useful amines, proteins, and amine-containing antibiotics include, without limitation., ammonium chloride, glucosamine hydrochloride, dimethylamine hydrochloride, ethanolamine hydrochloride, diethanolamine hydrochloride, polyethylene glycol amines such as hexa(ethyleneglycol)-bis-amine, lactoferrin, lysozyme, albumin, casein, cytochrome C, immunoglobulins, avidin, heparin, polymyxin, and the like, and combinations thereof.
Coupling agents useful in the invention include any coupling agent capable of enabling the reaction of a carboxyl group with an amine group to form an amide. Useful suitable classes of coupling agents include, without limitation, dehydrating agents such as carbodiimides, acid halides of inorganic or organic acids, isocyanides, and the like, and combinations thereof Examples of suitable coupling agents include, without limitation, carbodimides, N,Nxe2x80x2-carbonyldiimidazole, phosphoryl chloride, titanium tetrachloride, sulfuryl chloride fluoride, chlorosulfonyl isocyanate, phosphorus iodide, pyridinium salts of tributyl amine, phenyl dichlorophosphate, polyphosphate ester, chlorosilanes, and the like as well as mixtures of tributyl phosphorus and phenyl isocyanate, alkyl chloroformates and triethyl amine, 2-chloro-1,3,5-trinitrobenzene and pyridine, methyl sulfuryl chloride and diethyl amine, and triphenylphosphine, carbon tetrachloride and triethyl amine. Preferred coupling agents are carbodiimides. More preferred are 1-ethyl-3-(3-dimethylaminopropyl) carbodiimide and dicyclohexyl carbodiimide.
The devices used for purposes of the invention may be made of one or more carboxyl functional hydrophilic polymers. Alternatively, one or more surfaces of a device may be coated with one or more carboxyl functional polymers. Thus, in yet another embodiment, the invention provides a method for manufacturing biomedical devices comprising, consisting essentially of, and consisting of coating at least one surface of a device with one or more carboxyl functional polymers, subsequently contacting the at least one surface with a coating-effective amount of an amine and a coupling effective amount of at least one coupling agent under conditions suitable to produce a stable, amide-containing coating on the surface.
Examples of suitable carboxyl functional hydrophilic polymers include, without limitation, poly(acrylic acid), poly(methacrylic acid), poly(maleic acid), poly(itaconic acid), block or random copolymers of (meth)acrylic acid, acrylic acid, maleic acid, itaconic acid with any reactive vinyl monomer, carboxymethylated polymers, such as carboxymethylcellulose, and the like, and mixtures thereof. Preferably, the carboxyl functional hydrophilic polymer is poly(acrylic acid) or poly(methacrylic acid). More preferably, poly(acrylic acid) is used.
The carboxyl functional polymers may be of any molecular weight. Preferably, the polymers are of a relatively high molecular weight, or about 10,000 to 10,000,000 more preferably about 50,000 to about 4,000,000 g/mole, most preferably about 100,000 to about 1,000,000 g/mole.
Suitable surfaces for coating with a carboxyl functional polymer are any surfaces with hydroxyl groups, amino groups, or mixtures thereof Preferably, the surface is made of a silicone elastomer, silicone-containing macromers including, without limitation, those disclosed in U.S. Pat. Nos. 5,371,147, 5,314,960, and 5,057,578 incorporated in their entireties herein by reference, hydrogel, or silicone-containing hydrogel. More preferably, the surface is a siloxane, or contains a siloxane functionality, including, without limitation, polydimethyl siloxane macromers, methacryloxypropyl polyalkyl siloxanes, and mixtures thereof, silicone hydrogel or a hydrogel, such as etafilcon.
If the surface material to be coated does not contain the requisite hydroxyl or amine groups, such groups may be incorporated into the surface material. For example, hydroxyl groups may be incorporated by addition of one or more hydroxyl-containing monomers into the polymers used to form the surface. Examples of such hydroxyl containing monomers include, without limitation, mono(meth)acrylates of ethylene glycol, propylene glycol, glycerol, tetraethylene glycol, and the like. Amino groups may be incorporated using, without limitation, (meth)acrylates of aminoalcohols such as aminoethanol, tert-butylaminoethanol, or (meth)acrylamides of diamines such as bisaminopropane.
Alternatively, amine or hydroxyl functional, silicone-containing monomers or macromers may be used to incorporate the hydroxyl or amino functionalities into the surface. Suitable hydroxyl containing macromers include, without limitation, silicone containing linear or branched hydroxyalkylamine functional monomers of the structure:
wherein: n is 0 to 500, m is 0 to 500, and n+m=10 to 500, preferably 20 to 250; R2, R4, R5, R6, and R7 are each independently a substituted or, preferably, unsubstituted monovalent alkyl of 1 to 10 carbon atoms or a substituted or, preferably, unsubstituted aryl group, suitable substituents for which include alcohol, ester, amine, ketone, carboxylic acid, or ether groups; R1, R3, and R8 are each independently a substituted or, preferably unsubstituted monovalent alkyl of 1 to 30 carbon atoms or a substituted or, preferably, unsubstituted aryl group suitable substituents for which are alcohol, ester, amine, ketone, carboxylic acid, or ether groups, and at least one of R1, R3, and R8 is of the formula:
wherein R9 is any group capable of linking N to Si, including without limitation, a linear or branched divalent alkyl of 1 to about 10 carbon atoms or an ether group, R10 and R11 are each independently H, a substituted or unsubstituted monovalent alkyl of 1 to 5 carbon atoms, a substituted or unsubstituted aryl group, suitable substituents for which are substituted with alcohol, ester, amine, ketone, carboxylic acid, or ether groups, or the structure:
wherein R14 is H or a monovalent (meth)acryloyl, styryl, vinyl, allyl, or N-vinyl lactam polymerizable group and preferably H or methacryloyl; R16 is H, a monovalent substituted or unsubstituted alkyl group of 1 to 6 carbon atoms, a substituted or unsubstituted aryl group, suitable substituents for which are alcohol, ester, amine, ketone, carboxylic acid, or ether groups, or a (meth)acrylate, styryl, vinyl, allyl, or N-vinyl lactam polymerizable group and preferably is an alkyl group of 1 to 6 carbon atoms substituted with an alcohol or is a methacrylate; R12, R13, and R15 are independently H, a substituted or unsubstituted monovalent alkyl of 1 to 6 carbon atoms, a substituted or unsubstituted aryl, suitable substituents for which include alcohol, ester, amine, ketone, carboxylic acid, or ether groups, or R12 and R15 or R13 and R15 form a ring structure with the proviso that at least some of the structure II groups on the monomer are polymerizable groups. Preferably, R12, R13, and R15 are H.
Silicone-containing polymers useful in the present invention may also be copolymers incorporating one or more hydrophilic monomers. The hydrophilic monomers used to make the hydrogel used in the invention may be any of the known monomers useful for hydrogel formation.
Preferred hydrophilic monomers used in forming the carboxyl functional hydrophilic containing surfaces useful in the process of this invention are acrylic or vinylic-containing. Acrylic-containing monomers contain the group (CH2xe2x95x90CRCOX) wherein R is H or CH3, and X is O or N. Examples of such monomers include, without limitation, N,N-dimethylacrylamide, 2-hydroxyethyl methacrylate, glycerol methacrylate, 2-hydroxy ethyl methacrylamide, polyethylene glycol monomethacrylate, methacrylic acid, acrylic acid, and the like.
Vinylic-containing monomers refers to monomers containing the group (xe2x80x94CHxe2x95x90CH2). Examples of such monomers include, without limitation, N-vinyl lactams, such as N-vinyl pyrrolidone, and N-vinyl-N-methyl acetamide, N-vinyl-N-ethyl acetamide, N-vinyl-N-ethyl formamide, N-vinyl formamide and the like. Preferably, the monomer is N-vinyl pyrrolidone.
Other hydrophilic monomers that may be employed in forming the surfaces of the invention include, without limitation, polyoxyethylene polyols having one or more terminal hydroxyl groups replaced with a functional group containing a polymerizable double bond. Examples include, without limitation, polyethylene glycol, ethoxylated alkyl glucoside, and ethoxylated bisphenol A reacted with one or more equivalents of an end-capping group such as isocyanatoethyl metliacrylate, methacrylic anhydride, methacryloyl chloride, vinylbenzoyl chloride, or the like to produce a polyethylene polyol having one or more terminal, polymerizable, olefinic groups bonded to the polyethylene polyol through linking moieties such as carbamate or ester groups.
Additional exemplary hydrophilic monomers are disclosed in U.S. Pat. Nos. 5,070,215 and 4,910,277, which are incorporated herein in their entireties by reference. Preferred hydrophilic monomers are N,N-dimethylacrylamide, 2-hydroxyethyl methacrylate, glycerol methacrylate, 2-hydroxyethyl methacrylamide, N-vinyl pyrrolidone, polyethylene glycol monomethacrylate, and (meth)acrylic acid. Most preferably, N,N-dimethylacrylamide is used.
The surface to be coated with the carboxyl functional hydrophilic polymer is contacted with the polymer and at least one coupling, agent in any convenient manner. For example, the device may be placed in a solution of polymer and solvent into which the coupling agent is added. As an alternative, and preferably, the device surface may first be contacted with one of the coupling agent or polymer and then contacted with the other. Most preferably, the surface is first contacted by any convenient method with the coupling agent for a period of about 0.5 to about 60 minutes, preferably for about 1 to about 30 minutes. For example, the surface may be soaked in a coupling agent solution. Subsequently, the surface is contacted with the carboxyl functional hydrophilic polymer solution for a period of about 1 to about 1000 minutes, preferably about 5 to about 200 minutes.
Suitable solvents for use in the invention are those that are capable of solubilizing both the carboxyl-functional polymer and the coupling agent. Preferably, the coating process is carried out in a water or aqueous solution, which solution preferably contains buffers and salts. The carbodiimide 1-ethyl-3-(3-dimethylaminopropyl)carbodiimide (xe2x80x9cEDCxe2x80x9d) is effective in aqueous solutions and, thus, is a most preferred coupling agent.
The coupling agents may be used alone or in combination with agents capable of stabilizing any reactive intermediate formed. For example, EDC may be used with N-hydroxysuccinimide as a stabilizer. Additionally, it may be necessary to adjust the solution pH in order to optimize ester or amide linkage formation. Preferably, the pH is adjusted to from about 2.0 to about 8.0, more preferably from about 4.5 to about 5.0.
A coupling effective amount of the coupling agent is used which amount is sufficient to couple the polymer to the device surface. The precise amount of coupling agent used will depend on the surface""s chemistry as well as the polymer and coupling agent selected. Generally, about 0.01 to about 10 weight percent, preferably about 0.01 to about 5.0, more preferably, about 0.01 to about 1 weight percent of the coating solution is used. By coating solution is meant the polymer with one or more of the solvent, coupling agent, and buffer. Typically, the amount of coating solution used per lens will be about 0.1 to about 100 g, preferably about 0.5 to about 50 grams, more preferably about 1 to about 10 g per lens.
A coating effective amount of carboxyl functional hydrophilic polymer is used meaning an amount sufficient to coat the surface to the desired degree. Generally, the amount of polymer used is about 0.001 to about 100, preferably about 0.01 to about 50, more preferably, about 0.01 to about 10 weight percent of the coating solution.
Temperature and pressure are not critical to the process, which may be conveniently carried out at room temperature and pressure. However, in a preferred embodiment, a temperature of about 30 to about 80xc2x0 C. is used. The contact time used will be a length of time sufficient to coat the surface to the extent desired. If the surface is being contacted with a coupling agent-polymer solution, generally, contact times will be from about 1 minute to about 24 hours, preferably from about 1 to about 120 minutes, more preferably from about 1 minute to about 60 minutes.
If the surface is first treated with only the coupling agent, the contacting time will be about 1 to about 120, preferably 2 to about 60 minutes. The surface then is contacted with the polymer-solvent solution as described above.
One ordinarily skilled in the art will recognize that the formulation for producing the surface to be coated by the method of the invention may contain other monomers and additives. For example, ultra-violet absorbing monomers, reactive tints, processing aids, and the like may be used.
Following contacting, the surface may be washed with water or buffered saline solution to remove unreacted polymer, coupling agent, solvent, and byproducts. Optionally, the coated surface may be heated in water to extract residual coating, coupling agent, and byproducts and to ensure the break down of any coupling agentxe2x80x94stabilizer complexes that may have formed.
The invention will be further clarified by a consideration of the following, non-limiting examples.

Biomedical devices with amid-containing coatings


A diode structure that facilitates tuning the breakdown voltage of the diode structure, and a method for forming and operating the diode structure. In a P− substrate, a N+ layer is implanted. The N+ layer has an opening whose size affects the breakdown voltage of the diode structure. Upon the N+ layer, an N− layer is implanted in the substrate. Then, a P+ region is formed to serve as an anode of the diode structure. An N+ region can be formed on the surface of the substrate to serve as a cathode of the diode structure. By changing the size of the opening in the N+ layer during fabrication, the breakdown voltage of the diode structure can be changed (tuned) to a desired value.

1. Technical Field
The present invention relates to semiconductor diodes, and more particularly, to tunable semiconductor diodes.
2. Related Art
ESD (electrostatic discharges) diodes are well known in present day semiconductor technology in order to protect I/O and other internal circuitry from electrostatic discharges and other overvoltage conditions that could cause catastrophic failure in integrated circuits. See e.g. U.S. Pat. No. 5,629,544 to Voldman et al., "Semiconductor Diode with Silicide Films and Trench Isolation," which teaches ESD diodes having silicided electrodes to reduce series resistance, and U.S. Pat. No. 5,945,713 to Voldman, "Electrostatic Discharge Protection Circuits for Mixed Voltage Interface and Multi-Rail Disconnected Power Grid Applications," which teaches an ESD diode that can interface with multiple supply voltages.
Because of high sheet resistance, these ESD diodes must be made large in order to discharge the ESD currents. Voldman et al using a p+/n well diode showed that ESD improvement can be achieved by reduction of the n well sheet resistance in a CMOS technology from 1000 Ohms/square to 300 Ohms/square. In a CMOS technology, this also leads to an increase in the capacitance per unit area which is acceptable for CMOS technologies below 1 GHz application frequencies but not for application speeds above this frequency range. Large ESD structures are also unacceptable for high speed RF (Radio Frequency) applications due to the high capacitance load placed on the RF circuit.
As integrated circuit (IC) switching speeds approach and pass 1 GHz, there is a need to reduce the capacitance of ESD diodes. This is because as switching speeds increase, device area decreases, such that device reactance remains relatively constant. As capacitance decreases, it is desirable to avoid compromising the ESD robustness (that is, the breakdown voltage) of the diode. In general, these goals have been mutually exclusive; ESD robustness is typically preserved by making the diode structure fairly large, which drives up capacitance. Thus, there is a need in the art for an ESD diode that has reduced capacitance without reduced ESD robustness.

International Business Machines Corporation


Methods and apparatus are disclosed for dynamically updating service profiles in a network system. A device, such as an edge device providing network services to subscribers, is configured to dynamically update profiles for services provided to subscribers with no downtime required. Devices may be configured in accordance with this disclosure to receive a request by a first subscriber to access a network service having an associated service profile. The device may then cache the current version of the service profile into memory. Upon receiving a request from a second subscriber to access the same network service, the device may then determine whether a newer version of the service profile exists. If a newer version exists, then the device may then associate the newer version of the service profile to the second subscriber's session. Older versions may be purged as they are no longer used.

1. Field of the Disclosure
The disclosure relates generally to the service providers of data communications, and in particular, to the upgrading of service profiles for network subscribers.
2. The Prior Art
Background
Edge services provided to subscribers can take the form of basic Internet access through DSL, cable access and the likes, or more specific services such as secure access to corporate Intranets. Users typically are provided the services through an "Edge" device, usually a router coupled between the subscriber and the Internet that is configured to provide gateway services.
In operation, each subscriber has an associated subscriber profile maintained by the service provider that indicates which of the many offered services a particular subscriber is entitled to access.
When a subscriber begins a new session, typically the edge device accesses a AAA server to authenticate the subscriber's profile, and then loads the subscriber's profile into a cache memory located in the edge device. The subscriber is then presented with the authenticated services in the form of a dashboard or home page that includes indications of what services have been authorized for the subscriber's account. When the subscriber selects a particular service, a service selection request is then sent from the edge device to the AAA server for authentication, and a subscriber service profile is returned to the edge device for storage locally.
In providing the service profile to the edge device, the service profile also enables the edge device to be configured to provide the service. For example, routing paths, secure tunnels, and gateway configuration parameters may be uploaded to the edge device as a result of a service request from the subscriber.
Overall policies exist to further define and authenticate a session associated with a particular subscriber. When a subscriber requests access to a given feature, the subscriber's session activates service profile associated with the new service. The services can then activate flows associated with their particular traffic requirements. Thus each session can have many activated services associated with the user, and each service can have respective flows, all being managed by the subscriber's particular session.
As will be appreciated by those of ordinary skill in the art, many subscribers will access many of the same service offered by the service provider. To reduce overhead, typically the policies and profiles associated with a particular service are then cached by the edge device the first time accessed by a subscriber, and these cached profiles are retrieved locally when subsequent subscribers request the same service.
A problem presents itself when a profile provided by the service provider needs to be upgraded. For example, the profile of an Intranet secure access service may be needed to be upgraded in light of newly-discovered security threats. If a service provider has many sessions active that are using a particular service that is in need of an update, each session would need to be brought down and re-started with the updated service profile.
In prior art systems, the service profile is updated off-line from the edge box, i.e., on the AAA server and 'pushed' to the edge server. At a scheduled downtime, all sessions are taken down and updated. Alternatively, the service profiles may be simply pushed and overlayed on active sessions that have services that need to be updated, in an attempt to update the services in real-time. However, if service attributes are changed, many active sessions may be left in unstable states, causing problems for subscribers.
As will be appreciated, this forced updating in the prior art will necessarily interrupt service for the subscribers who are currently using the services. Hence, there is a need for a procedure to update services without interrupting a subscriber's experience or requiring scheduled downtime.

Method and apparatus for providing service profile upgrades with minimal downtime


An optical deflector comprises a control means for controlling at least either a light source or a deflection means adapted to gauge the distance between the position of a deflected beam of light moving on a light receiving element in one direction and the position of another deflected beam of light moving on the light receiving element in the opposite direction and control the distance so as to make it agree with a predetermined value. Thus, the optical deflector can very accurately control the operation of the deflection means in such a way that it is not affected by changes of environmental temperature of the deflection means and the detection circuit, because a detection means for detecting the time when a beam of light passes by a predetermined angle of deflection of the deflection means is not used.

1. Field of the Invention
This invention relates to an optical deflector having a deflection means for deflecting light.
2. Related Background Art
FIG. 1 of the accompanying drawings illustrates a galvano-mirror as an example of optical deflector that is driven by electromagnetic force. A mirror is arranged on a movable section, which is supported by a main body by way of a pair of torsion bars so that it may be rotated relative to a central axis. In FIG. 1, reference symbol 50 denotes a silicon substrate and reference symbols 51 and 52 respectively denote an upper glass substrate and a lower glass substrate. There are also shown a movable plate 53, a pair of torsion bars 54, a planar coil 55, a total reflection mirror 56, a pair of electrode terminals 57 and permanent magnets 60 through 63. The illustrated optical deflector is of the electromagnetic type that is driven by causing a drive current to flow through the planar coil 55 and utilizing the Lorentz force that is generated by the drive current and the permanent magnets (see, inter alia, U.S. Pat. No. 5,606,447).
Japanese Patent Application Laid-Open No. 2001-305471 describes an electromagnetic actuator. This patent document has much in common with U.S. Pat. No. 5,606,447 in that a movable part is driven by electromagnetic force. The electromagnetic actuator disclosed in Japanese Patent Application Laid-Open No. 2001-305471 also has a total reflection mirror arranged on a movable part.
Japanese Patent Application Laid-Open No. 2001-305471 describes a system as follows in terms of problems, objects and means. The invention disclosed in the above patent document paid attention to the fact that the resonance period of an electromagnetic actuator normally drifts with temperature and time and hence, if an electric current having a predetermined, constant resonance frequency is continuously supplied to the planar coil, there arises a problem that it is not possible to control the angle of deflection and keep it to a constant value with temperature change and time lapse. Thus, the first object of that invention is to provide an electromagnetic actuator that can be driven to reciprocate with its resonance period without providing a separate detection means as well as a drive control device and a drive control method to be used for such an electromagnetic actuator. The second object of that invention is to provide an electromagnetic actuator whose angle of deflection can be controlled without providing a separate detection means as well as a drive control device and a drive control method to be used for such an electromagnetic actuator. The third object of the invention is to provide a resonance frequency signal generating device and a resonance frequency signal generating method to be used for an electromagnetic actuator that can output a resonance frequency signal corresponding to the resonance period of the electromagnetic actuator.
The invention of the above cited patent document utilizes a coil as means for exciting the movable section of the electromagnetic actuator and also as detection means. The induced voltage or current in the coil is utilized for detection.
While Japanese Patent Application Laid-Open No. 2001-305471 describes that the resonance period of an electromagnetic actuator drifts with temperature and time, it proposes to detect the time when the actuator passes by a predetermined angle of revolution (deflection) from the coil that is a detection means as time-related information.
U.S. Pat. No. 5,606,447 does not pay attention to the problem that the resonance period of an electromagnetic actuator drifts with temperature.
With the method of detecting the time when the actuator passes by a predetermined angle of deflection gives rise to a signal delay in the detection circuit due to changes of environmental temperature. Additionally, timing errors can occur when gauging the change with time of the angle of deflection and detecting the time on the basis of the gauged change because the detection timing can be shifted by signal noises and offsets.
Thus, the problem of signal delays and timing errors arises when accurately controlling an actuator by such a method of detecting the time when the actuator passes by a predetermined angle of deflection.


An object of the present invention is to provide a new granulating process which can recover desired coagulated latex particles with a significantly excellent yield, and can suppress secondary coagulation under the condition having a higher temperature than a softening point of a polymer, without deteriorating the original quality of the polymer itself. A process for producing coagulated latex particles which can suppress the secondary coagulation under the condition having the broad temperature range, without deteriorating the original quality of the polymer itself by spraying or dropping a polymer latex into a gas-phase containing an inorganic salt and/or an acid, and a dispersant in an aerosol form, and dropping or feeding the droplets of the polymer latex into an aqueous phase containing a dispersant.

In order to recover a desired polymer contained in a latex from a polymer latex prepared by emulsion polymerization or suspension polymerization, granulating processes for coagulating and granulating the latex are required. Polymers are recovered from polymer lattices by the following procedure: a coagulant is added to a polymer latex at a temperature sufficiently lower than the softening temperature of the polymer to form coagulated latex particles. The resulting mixture is then heated to at least the softening temperature of the polymer to produce slurry, followed by dehydrating and drying. Thus, a powdered polymer is recovered. In this process, the reason for setting a temperature sufficiently lower than the softening temperature of the polymer when a coagulant is added to a polymer latex is to suppress the secondary coagulation among the coagulated latex particles generated. In general, when a coagulant is added at a temperature more than the softening temperature of the polymer, generation of rough and large coagulated latex particles frequently occurs, and in the worst case, it may happen that the whole latex particles get aggregated.
As opposed to the above process, granulating processes of a polymer latex which can obtain coagulated latex particles having satisfactory powder properties, a gas-phase coagulation process (for example, see JP-A-53-30647), a moderate coagulation process (for example, see JP-A-60-217224), a granulating process using a spray dryer, and the like are widely known. Even though these processes are employed, in view of suppressing the secondary coagulation, granulating processes at a temperature lower than a softening temperature of a polymer is desirable, and for the purpose, in general, the granulating processes are conducted at a temperature around or lower than the softening temperature of the polymer.
However, it can not be better to set a temperature lower in the above granulating processes, when the granulation temperature is set too lower than the softening temperature of the polymer, mechanical strength of the coagulated latex particles generated tends to lower, thus, a large amount of a fine powder is generated, which may cause a factor of problems in the steps such as a filter fabric clogging.
Namely, in the conventional granulating processes, it is important to suppress the secondary coagulation and generation of fine powder in order to obtain coagulated latex particles having a desired particle size with a satisfactory yield, and it is essential to operate in a temperature range for granulating at which influences of both secondary coagulation and generation of fine powder is minimum (generally, from around a polymer softening temperature to about 10° C. lower than it). However, when the granulating temperature fluctuates due to various factors during producing process, it is a problem of producing process to cause troubles such as lowering the yield by secondary coagulation and impairing filterability by generation of fine powder.
In addition, the conventional granulating processes has restriction in compositions of a polymer possible to be recovered, as for a rubbery polymer latex having the softening point of the polymer at most 0° C., when water is a medium, it is difficult even to set a temperature of the system within the range of the optimum granulating temperatures. Also when the granulating processes are conducted at around 0° C., the secondary coagulation frequently occurs, and the coagulated latex particles can not be obtained with a satisfactory yield.
In addition to the above granulating techniques, as a process for granulating a rubbery polymer latex having a softening temperature of the polymer of room temperature or lower, which is extremely difficult to be granulated due to easiness in the secondary coagulation, a process of adding a high-molecular weight polyanion having a carboxyl group and/or a hydroxyl group in its molecule to a rubber latex, and dropping the mixed latex into an aqueous solution containing at least one alkaline earth metal is known (for example, see JP-A-52-37987).
In this process, however, for example, at least 2 to 8 parts by weight and preferably 4 to 6 parts by weigh of the high-molecular weight polyanion must be added relative to 100 parts by weight of rubber solid content of the rubber latex, the viscosity of the resulting mixed latex must be adjusted to 200 to 8,000 m·Pa·s, and subsequently the latex must be dropped from 1 to 80 cm higher than the liquid level of a coagulant. Thus, according to the description of this process, satisfactory spherical coagulated latex particles cannot be produced unless many conditions are satisfied.
In general, it is easily assumed that the addition of 2 parts by weight or more of a high-molecular weight polyanion to a polymer latex causes the following problems, and thus this is not a satisfactory process. Examples of the problems are as follows: (1) The original quality (for example, thermal stability) of a recovered polymer itself used for various purposes may be deteriorated; (2) The addition of a large amount of high-molecular weight polyanion leads to the significant increase in the production cost; and (3) Since the viscosity of the latex, which is generally 10 m·Pa·s or less, must be adjusted to 200 m·Pa·s or more and preferably 1,000 m·Pa·s or more by adding the high-molecular weight polyanion, the transferring property of the resulting latex liquid is impaired.
On the other hand, we developed the technology which can recover the desired coagulated latex particles with a satisfactory yield, suppressing the secondary coagulation and generation of a fine powder, under the temperature condition having as a broad range as possible, without deteriorating the original quality of the polymer itself, and filed the technology (Japanese Patent Application No. 2005-052783). In this process, the coagulated latex particles having a desired particle size can be recovered with an extremely satisfactory yield compared with the conventional granulating processes, by suppressing the secondary coagulation among coagulated latex particles entering into the aqueous phase. However, in this process, it is difficult to suppress the secondary coagulation by collision and uniting among the coagulated latex particles in the gas phase, thus, further development in efficiency has been desired.

Process for producing coagulated latex particles


Method and circuit for automatic correction of emulated inductor current without knowledge of actual inductor current ramp for an emulated current mode (ECM) PWM switching regulator. In an ECM-PWM switching regulator a compensation ramp component is usually added to an up-slope. An excess ramp component may also be added compared to actual inductor current. According to one embodiment of the present invention, an integrating negative feedback circuit is employed to reduce both extra components. According to another embodiment, a single integrating negative feedback loop is added to the ECM-PWM regulator to retain the compensation ramp component while reducing the excess ramp component. According to a further embodiment, excess ramp component is reduced by adding the integrating negative feedback loop at an end stage of the circuit. Finally, the feedback loop with two duplicate track-and-hold circuitry may be added to reduce the excess ramp component, while retaining the compensation component.

Advances in one area of technology often require commensurate advances in supporting technologies to realize the full benefit of the advance. For example, observers of the microprocessor industry are familiar with "Moore's Law," which posits that the complexity of semiconductor devices doubles every two years. Microprocessor development arguably represents the most dramatic illustration of Moore's Law. Pioneering microprocessors released in the 1970's operated at clock speeds well under 500 KHz, and included fewer than five thousand transistors. Modern microprocessors operate at clock speeds in excess of 1 GHz and include millions of transistors. Exploiting these dramatic gains required advances in a host of supporting technologies, from advances in memory technology and circuit fabrication, to advances in power supply design.
Indeed, modern microprocessors could not provide their dramatic performance gains absent today's sophisticated power supplies. For example, high-end microprocessors can consume in excess of 80 Watts of power and operate at 2 VDC or less. These requirements translate into power supply output current requirements in excess of 40 Amps, yet the power supply must maintain tight output voltage regulation, even when faced with dramatic step changes in output current. In general, modern electronic systems require responsive power supplies capable of providing relatively clean power at well-controlled voltages, over a wide range of quickly changing load conditions.
Linear regulators are relatively responsive, accurate, and low noise. Such regulators operate using controlled impedance, typically implemented as a pass transistor, to create a voltage drop across the controlled impedance such that the input voltage minus the voltage drop equals a desired output voltage. With proper use of load capacitors, linear regulators offer good line and load regulation performance, with virtually no noise problems. However, linear regulators are inefficient when required to regulate to an output voltage significantly below their input voltage. Because of high currents required by modern electronic systems, main power supplies often operate at 12 VDC or 24 VDC. Regulating such primary voltages down to 2 VDC, or even 5 VDC, for high-current loads is impractical using linear regulation.
Switch-mode power supplies offer significant efficiency advantages compared to linear regulation, and avoid most of the power dissipation problems associated with linear regulators. Switch-mode power supplies operate, as their name suggests, by switching some type of reactive element in and out of a supply path to effect output voltage control. The reactive elements may be one or more capacitors, such as in a charge-pump type switcher. However, inductor-based switch-mode power supplies are more common in high-current, high-performance power supply applications. Typically, an inductor is switch-connected to a voltage source at one end, and to an output load at the other end. An output capacitor sits in parallel with the output load. A switch controller rapidly connects and disconnects the inductor to the voltage supply to regulate the load voltage. The output capacitor serves as a low-impedance current source to the load, and helps smooth the output voltage of the power supply.
The switch controller in a switch-mode power supply requires some form of feedback to effect closed loop voltage regulation on the load. Many different regulation topologies exist, including voltage-mode feedback and current-mode feedback. In both voltage-mode and current mode feedback, an error amplifier typically generates a control signal by amplifying a difference between a feedback signal and a reference signal. This error amplification can reduce the bandwidth of the feedback loop, diminishing the switch controller's ability to respond to highly dynamic load changes, as are common with microprocessors and other high-performance electronic circuits.
Thus, it is with respect to these considerations and others that the present invention has been made.

Emulated inductor current automatic correction without knowledge of actual inductor current ramp for emulated peak control mode PWM


A method of manufacturing a mask assembly for thin film deposition includes: positioning a division mask on a mask frame, wherein the division mask has a length in a first direction that is greater than a width in a second direction perpendicular to the first direction; and spot welding opposing ends of the division mask along the first direction to the mask frame, wherein the spot welding comprises: forming first welding points in a first zigzag pattern starting from a peripheral portion along the second direction of the division mask toward a central portion along the second direction of the division mask; and forming second welding points between the first welding points.

1. Field
The present invention relates to a method of manufacturing a mask assembly for thin film deposition.
2. Description of the Related Art
In general, among flat panel displays, an organic light emitting display has a relatively fast response speed as well as a relatively wide viewing angle and excellent contrast.
The organic light emitting display realizes a color by emitting light through recombination of holes and electrons injected to an anode and a cathode in an emission layer, and has a deposition structure in which the emission layer is positioned between the anode and the cathode. However, with this structure it is difficult to obtain high efficiency light emission. Accordingly, intermediate layers such as an electron injection layer (EIL), an electron transport layer (ETL), a hole transport layer (HTL), and a hole injection layer (HIL) may be selectively added between the electrode and the emission layer.
The intermediate layers, the electrodes, and the emission layer of the organic light emitting display may be formed by several methods, such as a deposition method. The deposition method is a method of depositing an original material of a thin film on a substrate through a fine metal mask (FMM) aligned to the substrate to form a thin film pattern.
The size of the fine metal mask may be increased as the size of the flat panel display is increased. As a large-sized fine metal mask may be formed using a division mask having several separate masks with a stick shape and attaching them in parallel to each other to a mask frame.
The division mask may be attached to the mask frame by spot welding. However, the welding process may deteriorate or warp the division mask, causing undesired separation between the division mask and the substrate.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.

Method of manufacturing mask assembly for thin film deposition


A multi-direction input device for computers includes a direction wheel, a toggle mechanism and a plurality of electrodes. The direction wheel has one-degree of rotational freedom and two-degree of freedom to perform clicking, forward rolling, backward rolling, leftward moving and rightward moving operations. Thereby mating electrodes are electrically connected to generate corresponding signals. In normal conditions, the toggle mechanism and a movable contact jointly support the direction wheel. When the direction wheel is depressed, the toggle mechanism drives and connects a corresponding electrode to generate a click signal.

The technique of including a wheel in a computer input device such as mouse or keyboard is known in the art. For instance, U.S. Pat. No. 6,700,564 of Microsoft Co. and U.S. patent publication No. 2003/0025673 A1 disclose an input device equipped with a rotary wheel. When users browse documents on the screen of a computer, they can move the wheel with fingers to change pages, scroll text contents or perform document editing operations. It is especially handy for users to do document browsing, Web searching or image zooming operation. There is no need to maneuver the PAGE DOWN/UP keys on the keyboard or the scroll bar on the screen through the mouse. Through the wheel on the input device, scroll of text pages or lines can be done easily.
However, the conventional wheel structure is complex and bulky. Fabrication and assembly are difficult. Production cost is higher. To shrink the size of electronic products that include the wheel input device is not easy. This makes conforming to the prevailing trend of thin and light difficult.


An optical disc reproducing apparatus includes: a decode processing circuit configured to generate decoded data by decoding encoded data read out from an optical disc such that the decoded data is written into a buffer memory, and to output a write signal to indicate a data rate when the decoded data is written in the buffer memory. A data processing circuit converts the decoded data read out from the buffer memory into an output data, and outputs a read signal to indicate a data rate when the decoded data is read out from the buffer memory. An optical disc rotation control circuit controls a number of rotations of the optical disc based on the write signal and the read signal.

1. Field of the Invention
The present invention relates to an optical disc reproducing apparatus.
2. Description of Related Art
A technique for converting analog audio data into digital audio data (hereinafter to be simply referred to as "audio data") has been widely known. Compression techniques which can reduce an amount of audio data are also known. A plurality of standards for generating compressed audio data are known. For example, typical standards include MP3, WMA and AAC.
Along with a progress of information technology, techniques for recording the compressed audio data on an optical information recording medium such as CD-R and DVD-R are widespread. The compressed audio data recorded on the optical information recording medium is converted into analog audio data by an optical disc reproducing apparatus (for example, a CD drive) and then the audio data is outputted from an output unit such as a speaker.
The optical disc reproducing apparatus for the compressed audio data is provided with a buffer memory. The optical disc reproducing apparatus executes processes such as a decoding process on read data read out from the optical information recording medium and held in the buffer memory, and then suppresses such fault that audio data which is being reproduced is suspended.
When data is sequentially transferred from the optical disc reproducing apparatus to a host computer, the data after a decoding operation by a decoding circuit is stored in a buffer if a transfer rate is smaller than a read rate from the optical disc. When the read data is fully written into the buffer memory, a read operation from the optical disc must be brought to a halt until the buffer memory has a room for storage. In the meantime, power may be consumed due to rotation of the optical disc. Thus, a technique of varying rotation speed of the optical disc depending on an amount of data held in the buffer memory is known in Japanese Patent Application Publication (JP-P2003-242708A: conventional example 1).
FIG. 1 is a block diagram showing an information recording disc reproducing apparatus described in the conventional example 1. In the information recording disc reproducing apparatus described in conventional example 1, rotation of the information recording disc 103 is controlled by a DVD-ROM drive 102 and a signal read from the information recording disc 103 is decoded by the DVD-ROM drive 102 and transferred to a host computer 101. The DVD-ROM drive 102 includes a microprocessor 104, a ROM 105, a buffer 106, a reproduction speed control section 107, an information recording disc reading apparatus 108, a decoder 109 and a RAM 110.
According to a program previously stored in the ROM 105 and an instruction issued from the host computer 101, the microprocessor 104 controls other blocks in the DVD-ROM drive 102. Data read out from the information recording disc 103 by the information recording disc reading apparatus 108 is supplied to a decoder 109 and decoded by the decoder 109. The decoded data is sequentially stored in the buffer 106 and, after temporary storage, is transferred to the host computer 101. Depending on a transfer type such as transfer method or transfer mode for a transfer section adapted to transfer data to the host computer 101, a line speed at a reproduction position of the information recording disc 103 is controlled to be highest line speed determined based on a transfer rate of each transfer type or less. By controlling the line speed at the reproduction position of the information recording disc 103 so that a data transfer rate to the host computer 101 does not exceed a data rate at which the decoded data is stored in the buffer 106, a high-speed rotation of the information recording disc 103 is suppressed. When the amount of data stored in the buffer 106 is a predetermined value or more, the buffer 106 is prevented from being fully filled by reducing a rotation speed of the information recording disc 103.
The conventional example 1 describes a technique of an information recording disc reproducing apparatus which varies the rotation speed of the information recording disc 103 depending on a transfer section. The decoder 109 of the information recording disc reproducing apparatus performs a CD decoding process and a CD-ROM decoding process to the CD-ROM disc. Here, when the data recorded on the information recording disc 103 is compressed audio data, the decoder 109 decodes the compressed audio data in addition to the CD decoding process and the CD-ROM decoding process.
When multiple compressed audio data having different data compressibilities are recorded on the information recording disc 103, a decoding process corresponding to the data compressibility is performed. For this reason, the data rate at which the decoded data is stored in the buffer 106 varies depending on the decoding process. That is to say, when the technique described in conventional example 1 is applied to the optical disc reproducing apparatus capable of reproducing the compressed audio data, it may be difficult to determine a data rate in the decoding process. In addition, it may be difficult to determine a line speed in read of the optical disc.
Furthermore, there is a variable bit rate method in which the data compressibility of a part of the compressed audio data is not fixed but variable. When the technique described in conventional example 1 is applied to the optical disc reproducing apparatus capable of reproducing the compressed audio data, it is difficult to cope with variance of a decoded data rate.
Unlike an apparatus in which the line speed of the optical disc can be calculated by an external transfer section, the line speed of the optical disc which stores the compressed audio data cannot be previously known. Thus, conventional systems cannot rotate at a low speed and control the optical disc which stores the compressed audio data. There is a conventional method of monitoring the number of stages of FIFO and performing a phase comparison of data write/read into/from a buffer memory. However, when data rates of data write/read into/from the buffer memory are different or the data rate is extremely low, there is no technique for coping with such a state.

Optical disc reproducing apparatus and operation method thereof


In order to stably generate a high voltage of a prescribed level, a Vpp detection circuit which is activated in response to an activation signal for comparing the high voltage with a reference voltage is forcibly brought into an active state for a prescribed period under control of an initial control circuit.

1. Field of the Invention
The present invention relates to a semiconductor circuit device, and more particularly, it relates to the structure of a circuit generating an internal voltage of a prescribed voltage level in its interior. More specifically, the present invention relates to the structure of a boosted voltage generation circuit generating a boosted voltage of a voltage level higher than that of an operating power supply voltage in a semiconductor memory device.
2. Description of the Prior Art
FIG. 53 schematically illustrates the structure of a conventional semiconductor circuit device CH. Referring to FIG. 53, the semiconductor circuit device CH includes a Vpp generation circuit PG generating a high voltage Vpp of a constant voltage level higher than that of an externally supplied power supply voltage VCC using this power supply voltage VCC, and an internal circuit NK performing a prescribed operation using the high voltage Vpp and the power supply voltage VCC. The internal circuit NK includes a Vpp utilization circuit NKa utilizing the high voltage Vpp from the Vpp generation circuit PG.
When the density and the degree of integration of a semiconductor circuit device including a MOS transistor (insulated gate field effect transistor) are enhanced, the size of the MOS transistor is refined. In order to ensure the reliability of a gate insulation film of the refined MOS transistor, it is necessary to prevent application of an excessive high voltage to the MOS transistor. Therefore, the voltage level of the power supply voltage VCC is reduced as the degree of integration and the density of the semiconductor circuit device are enhanced. Further, a high-speed operation is attained by reducing a signal amplitude, and current consumption is reduced by reducing a charge/discharge current for a signal line.
The semiconductor circuit device having such a refined MOS transistor utilizes the high voltage Vpp of a higher voltage level than the power supply voltage VCC for the following reason.
FIG. 54 illustrates a voltage application manner for an n-channel MOS transistor NQ included in the conventional semiconductor circuit device. Referring to FIG. 54, the n-channel MOS transistor NQ is supplied on its gate CG with a voltage changing between the high voltage Vpp and a ground voltage GND (0 V). An input signal IN changes between the power supply voltage VCC and the ground voltage GND (0 V). When the n-channel MOS transistor NQ has a threshold voltage Vth, it is possible to transmit a voltage (gate voltage V (CG)xe2x88x92Vth) from its source to its drain. When the high voltage Vpp is set at a voltage level exceeding the voltage VCC+Vth, therefore, an output signal OUT changing between the power supply voltage VCC and the ground voltage GND (0 V) can be obtained with no threshold voltage loss across the MOS transistor NQ.
High voltage Vpp is utilized for n-channel MOS transistor NQ in order to prevent the problem of threshold voltage loss thereby reliably transmitting a signal of the amplitude of the power supply voltage VCC. Thus, an internal signal of a desired amplitude can be correctly transmitted even if the power supply voltage VCC is at a low voltage level. Influence by such threshold voltage loss most remarkably appears on data read from a memory cell when this semiconductor circuit device is a semiconductor memory device.
FIG. 55 illustrates the structure of a memory cell MC of a conventional semiconductor memory device. Referring to FIG. 55, the memory cell MC is arranged in correspondence to a crossing between a word line WL and a bit line BL. The memory cell MC includes a capacitor Cm for storing information and an access transistor Qm conducting in response to a signal potential on the word line WL for connecting the capacitor Cm with the bit line BL. The access transistor Qm is formed by an n-channel MOS transistor. Such memory cells MC are arrayed in rows and columns, so that a row of memory cells MC are arranged in correspondence to the word line WL and a column of memory cells MC are arranged in correspondence to bit lines BL and /BL. In the example shown in FIG. 55, no memory cell MC is arranged at a crossing between the word line WL and the bit line /BL.
The bit lines BL and /BL are precharged at an intermediate voltage level. When the word line WL is selected, the access transistor Qm conducts so that the potential of the bit line BL changes in accordance with charges stored in the capacitor Cm. A sense amplifier (not shown) differentially amplifies and latches the potential difference between the bit lines BL and /BL. When the capacitor Cm stores high-level data, the bit line BL is driven to a power supply voltage Vcca (array power supply voltage) level. At this time, the word line WL is driven to a voltage level which is higher than the high-level voltage Vcca by the threshold voltage Vth of the access transistor Qm. Thus, the capacitor Cm stores data of the high-level voltage Vcca level with no influence by the threshold voltage Vth of the access transistor Qm.
The quantity of charges stored in a storage node (connection node between the access transistor Qm and the capacitor Cm) of the capacitor Cm is determined by the difference between the high-level data and a constant voltage (cell plate voltage) Vcp and the capacitance value of the capacitor Cm. Even if refinement (miniaturization) progresses to reduce the capacitance value of the capacitor Cm, therefore, it is possible to stably hold the high-level data by transmitting the voltage Vcca of the high-level data to the capacitor Cm with no threshold voltage loss thereby storing a sufficient quantity of charges. Also in data reading, it is possible to cause sufficient voltage difference (read voltage) on the bit line BL.
In the conventional semiconductor memory device (dynamic random access memory), therefore, the word line WL is generally driven to a voltage level higher than the power supply voltage Vcca supplied to a memory cell array. Therefore, a circuit driving the word line WL to the high voltage Vpp level utilizes the high voltage Vpp.
FIG. 56 shows another structure of the Vpp utilization circuit NKa. Referring to FIG. 56, an output circuit OB converts data D and /D read from an internal memory cell of a semiconductor memory device to external read data DQ and outputs the same. Referring to FIG. 56, the output circuit OB includes a level conversion circuit OBa converting the voltage level of the internal read data D to a high voltage Vpp level, an n-channel MOS transistor OBb conducting, when an output signal of the level conversion circuit OBa is at a high level, for driving the external data DQ to a power supply voltage VQ level, and an n-channel transistor OBc conducting when the complementary internal read data /D is at a high level, for setting the external read data DQ at the ground voltage level.
The power supply voltage VQ determines a high level of the external read data DQ. If the n-channel MOS transistor OBb causes threshold voltage loss when the voltage level of the power supply voltage VQ is lowered, the high level of the external read data DQ is so reduced that an external circuit receiving the read data DQ cannot correctly determine the high/low level. In order to eliminate the threshold voltage loss in the MOS transistor OBb, the level conversion circuit OBa generates a signal of the high voltage Vpp level in accordance with the internal read data D (level conversion of the internal read data). Thus, the output circuit OB outputs the read data DQ of the power supply voltage VQ level to an exterior, enabling correct data reading.
This structure including the n-channel MOS transistors OBb and OBc as MOS transistors for charging/discharging an output node in the output circuit OB shown in FIG. 56 is widely employed in a highly integrated semiconductor memory device, in view of prevention of a latch-up phenomenon and reduction of an occupation area due to reduction of an area for P-N isolation.
FIG. 57 schematically illustrates the structure of the Vpp generation circuit PG shown in FIG. 53, along with a circuit block which is supplied with the high voltage Vpp.
Referring to FIG. 57, the Vpp generation circuit PG includes a Vpp generator PGa generating the high voltage Vpp when activated, and a Vpp level detector PGb detecting the level of the high voltage Vpp and selectively activating the Vpp generator PGa in accordance with the result of detection. The Vpp generator PGa includes a clock signal generator generating a clock signal of a constant cycle, and a charge pump circuit generating the high voltage Vpp through a charge pump operation of a capacitor in accordance with the clock signal from the clock signal generator. The Vpp level detector PGb stops the high voltage generating operation of the Vpp generator PGa when the high voltage Vpp is in excess of a prescribed voltage level. In general, the Vpp level detector PGb selectively activates the Vpp generator PGa in accordance with a result of comparison of the high voltage Vpp with a prescribed reference voltage.
The high voltage Vpp from the Vpp generator PGa is supplied to a Vpp load NK1 included in the internal circuit NK. The Vpp load NK1 includes the Vpp utilization circuit NKa shown in FIG. 53 and the parasitic capacitance of a signal line through which the high voltage Vpp is transmitted.
In the semiconductor circuit device, it is necessary to quickly set an internal circuit in an operable state after the start of power-on. When the Vpp load NK1 has a large load, the Vpp generator PGa cannot drive the high voltage Vpp to the prescribed voltage level at a high speed after the start of power-on. Thus, the semiconductor circuit device cannot be set in an operable state at a faster timing in this case.
On the other hand, the Vpp level detector PGb must correctly detect the voltage level of the high voltage Vpp. If the voltage level of the high voltage Vpp is excessively high, the gate insulation film of the MOS transistor NQ is reduced in reliability. When the high voltage Vpp is at a low level, on the other hand, influence by threshold voltage loss of the MOS transistor NQ cannot be effectively eliminated.
FIG. 58 schematically illustrates the structure of a part of the semiconductor circuit device related to the high voltage Vpp, with the semiconductor circuit device being a semiconductor memory device. Referring to FIG. 58, the internal circuit NK includes a memory cell array NKb including a plurality of memory cells (see FIG. 55) arranged in rows and columns, a row selection circuit NKaa driving an addressed row of the memory cell array NKb to a selected state (high voltage Vpp level) using external power supply voltage VDD and the high voltage Vpp from the Vpp generation circuit PG, and the output circuit OB outputting the data of a selected memory cell of the memory cell array NKb to an exterior.
An output power supply voltage VDQ is supplied to the output circuit OB independently of the external power supply voltage VDD, so that fluctuation of the power supply voltage VDD in operation of the output circuit OB exerts no bad influence on the internal circuit operation and the output circuit OB stably operates even when the number of such output circuits OB is increased (multi-bit structure). The output circuit OB is also supplied with the high voltage Vpp from the Vpp generation circuit PG.
The voltage levels of the power supply voltages VDD and VDQ are set depending on a system including this semiconductor circuit device (semiconductor memory device). In SSTLxe2x80x942 (operating in accordance with a signal nominally switched in the range of 0 V to 2.5 V) in SSTL (stab series terminated logic) for transmitting a small amplitude signal at a high speed, for example, standards of classes I and II are settled so that the voltage level of the output power supply voltage VDQ is decided in accordance with each standard and the voltage level of a permissable minimum output voltage (external read voltage) is decided accordingly.
The power supply voltage VDD, which is employed for the internal circuit operation, is merely required to be higher than the output power supply voltage VDQ. When the voltage levels of the power supply voltages VDD and VDQ are different from each other, therefore, the output circuit OB cannot be supplied with an optimized high voltage Vpp. Particularly when the voltage level of the output power supply voltage VDQ is varied with a different standard, the level of the high voltage Vpp must also be adjusted. In the conventional structure, however, the high voltage Vpp is generated in accordance with the power supply voltage VDD for the internal circuit operation which is independent of the output power supply voltage VDQ, and hence the high voltage Vpp for the output circuit OB cannot be optimized. Further, no optimum high voltage Vpp can be generated for each standard.
An object of the present invention is to provide a semiconductor circuit device which can stably generate an internal voltage of a desired voltage level at a high speed.
Another object of the present invention is to provide a semiconductor circuit device which can bring an internal voltage to a desired voltage level at a high speed in power on.
Still another object of the present invention is to provide a semiconductor circuit device which can correctly detect the level of an internal voltage for stably generating a reference voltage of a desired voltage level.
A further object of the present invention is to provide a semiconductor circuit device which can readily cope with a plurality of standards of output supply voltages with a single chip.
A semiconductor circuit device according to a first aspect of the present invention includes internal voltage generation circuitry generating an internal voltage of a prescribed voltage level in activation thereof, internal voltage level detection circuitry for detecting the level of the internal voltage of the prescribed voltage level in activation thereof and selectively activating the internal voltage generation circuitry in accordance with the result of the detection, an internal circuit using the internal voltage, and initialization circuitry for forcibly activating the internal voltage level detection circuitry for a prescribed period in power-on for applying a power supply voltage to a first power supply node.
A semiconductor circuit device according to a second aspect of the present invention includes an internal voltage generation circuit for generating an internal voltage of a prescribed level and an internal voltage level detection circuit for detecting the voltage level of the internal voltage. The internal voltage level detection circuit includes a first conductivity type first insulated gate field effect transistor connected between a first power supply node and a second node for receiving a voltage corresponding to the internal voltage on its gate, a first conductivity type second insulated gate field effect transistor connected between the first node and a second node for receiving a reference voltage on its gate, a first conductivity type third insulated gate field effect transistor connected between the second node and a third node for receiving the voltage of the first node on its gate, and a current stage connected between the second and third nodes and a second power supply node for feeding a current between the second and third nodes and the second power supply node.
A semiconductor circuit device according to a third aspect of the present invention includes a first conductivity type first insulated gate field effect transistor connected between first and second nodes for receiving a first signal on its gate, a first conductivity type second insulated gate field effect transistor connected between the first node and a third node for receiving a second signal on its gate, a first conductivity type third insulated gate field effect transistor is connected between the second node and a fourth node connected to a prescribed voltage source supplying a prescribed voltage with its gate connected to the second node, a first conductivity type fourth insulated gate field effect transistor connected between the third and fourth nodes with its gate connected to the second node, and an output stage outputting a signal indicating a result of comparison of the voltage levels of the first and second signals in accordance with the voltages of the second and third nodes.
A semiconductor circuit device according to a fourth aspect of the present invention includes circuitry generating an internal voltage from the voltage of a power supply node, comparing the internal voltage with a reference voltage and activating the internal voltage generation circuitry in accordance with the result of the comparison, and reference voltage switching circuitry selecting a comparison voltage generated on the basis of the voltage of a power supply node for a prescribed time from the start of application of a power supply voltage to the power supply node as the reference voltage and selecting a voltage corresponding to an internal power supply voltage generated from the voltage of the power supply node after a lapse of the prescribed time as the reference voltage. The reference voltage switching circuitry includes a circuit for determining whether or not the internal power supply voltage has reached a prescribed level on the basis of the voltage level of the power supply node and a selection circuit switching the reference voltage in accordance with an output signal of the determination circuit.
A semiconductor circuit device according to a fifth aspect of the present invention includes circuitry receiving a main clock signal of a constant cycle for generating first, second and third control clock signals synchronized with the main clock signal, a first capacitive element receiving the first control clock signal and transmitting the same to its output node, a second capacitive element receiving the second control clock signal and transmitting the received control clock signal to its output node, a third capacitive element receiving the third control clock signal and transmitting the received third control clock signal to its output node, a first precharge element connected between a power supply node and the output node of the first capacitive element for precharging the output node of the first capacitive element at a prescribed voltage, a second precharge element precharging the output node of the third capacitive element at the voltage level of the power supply node in response to the signal voltage of the output node of the first capacitive element, a third precharge element precharging the output node of the second capacitive element at the voltage level of the power supply node in response to the signal voltage of the output node of the first capacitive element, an output element transmitting the signal voltage of the output node of the third capacitive element to an internal voltage output node in response to the signal voltage of the output node of the second capacitive element, and a clamp element clamping the voltage level of the output node of the first capacitive element at a prescribed voltage level in conduction thereof.
It is possible to activate the internal voltage generation circuitry having relatively large current drivability by forcibly activating the internal voltage level detection circuitry detecting the level of the internal voltage generated by the selectively activated internal voltage generation circuitry for a prescribed period in power-on, thereby generating the internal voltage of a prescribed voltage level at a high speed.
Further, it is possible to stabilize the internal voltage at a high speed in response to the reference voltage by generating the reference voltage determining the level of the internal voltage on the basis of an external power supply voltage immediately after the start of power-on.
In addition, it is possible to correctly determine whether or not the internal voltage has reached a desired voltage level with reference to a stable voltage level by detecting the level of the generated internal voltage on the basis of the level of the external power supply voltage serving as the generation source therefor.
Further, it is possible to drive the insulated gate field effect transistors in substantially identical operating regions for forming a signal responsive to the difference between the internal voltage and the reference voltage thereby enabling correct internal voltage level detection by comparing the internal voltage with the reference voltage with only the same conductivity type insulated gate field effect transistors.
When the output circuit and the internal circuit are supplied with power supply voltages independent of each other, the power supply voltage for the output circuit can be set at an optimum value responsive to the externally supplied power supply voltage and an internal voltage of an optimum level can be generated in response to the level of the externally supplied power supply voltage by generating the internal voltage in response to the respective power supply voltages, thereby coping with interface standards of a plurality of power supply voltages with a single chip.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

Internal high voltage generation circuit capable of stably generating internal high voltage and circuit element therefor


There is provided a manufacturing method for obtaining an MOS transistor which has a homopolar gate structure and a high-melting metallic silicide structure and is suitable even for high speed operation, while at the same time having a structure in which a sufficient withstand voltage can be attained by forming, by a simple method, low concentration drain regions with a long distance. A source and a drain, which have a low concentration, are formed and a thick insulating film and positive resist is formed (applied) on a gate electrode. Then, the positive resist is exposed at an amount of exposure suitable to expose a portion corresponding to a film thickness of the positive resist formed on a flat portion of the thick insulating film as a base and developed. The thick insulating film is etched by an amount substantially corresponding to a film thickness thereof by anisotropic etching using as a mask those portions of the positive resist partially remaining in a step portion. An impurity having a high concentration is simultaneously introduced into the source, the drain, and the gate electrode using a remaining portion of the thick insulating film as a mask. After that, high-melting metallic silicide is formed on exposed portions of the gate electrode and the source and drain regions of the MOS transistor, respectively.

1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
2. Description of the Related Art
A mask-offset drain (offset region is also formed in the source side in some cases) structure has been known as one of conventional high withstand voltage (about 10 V) MOS transistor structures. This structure is characterized in that a low concentration drain region (offset drain region) having a relatively long distance of about 0.5 to 1.0 ìm is provided near the gate electrode by using a photo mask, with the result that an electric field is relaxed to attain a higher withstand voltage. Further, an overlap capacitance between the gate and the drain is small. As a result, a gate charging speed is high in the case where this structure is used for a circuit, so that the mask-offset drain structure is suit able high-speed operation. Further, a drain impurity concentration in the offset region is low, so that a depletion layer can be extended, with the result that a drain withstand voltage can be increased. At this time, since a length L of the transistor can be shortened, it is suitable as an element having high driving power and a high withstand voltage.
On the other hand, with respect to a fine MOS transistor having a slightly low voltage range of about 5 V, a transistor of an LDD structure including source and drain regions each having a low impurity concentration, which are called LDDS, is known. The source and drain regions each having a low impurity concentration are defined in a self-alignment manner with respect to the gate electrode by side spacers and the length thereof is about 0.1 to 0.2 xcexcm.
In the case of the transistor of the LDD structure, a homopolar gate and high-melting metallic silicide (including self-aligning silicide) can be also achieved as means for further improving the performance of the transistor.
However, when adopting a homopolar gate structure and a high-melting metallic silicide structure for the MOS transistor having the mask-offset drain structure, which is suitable for an application in which a withstand voltage is required, there arises a problem such that, since it is necessary to form low concentration drain regions having a distance longer than that required in the MOS transistor having the LDD structure, the entire processing steps become very complicated.
The present invention has been made to solve the above problem, and an object of the present invention is to provide a manufacturing method capable of obtaining an MOS transistor which has a homopolar gate structure and a high-melting metallic silicide structure and is suitable even for high speed operation, while at the same time having a structure in which a sufficient withstand voltage can be attained by forming, by a simple method, low concentration drain regions with a long distance.
In order to achieve the above-mentioned object, according to the present invention, there is provided a method of manufacturing a semiconductor device, characterized by comprising the steps of: patterning a gate electrode formed on a thin insulating film on a silicon substrate, into a predetermined shape and then forming source and drain regions having a relatively low concentration by an ion implantation method using the gate electrode as a mask; forming a thick insulating film on the gate electrode, thickly applying a positive resist onto an entire surface of the thick insulating film, and then exposing the positive resist at an amount of exposure suitable to expose a portion corresponding to a film thickness of the positive resist formed on a flat portion of the thick insulating film as a base and developing the exposed positive resist; etching the thick insulating film by an amount substantially corresponding to a film thickness thereof by anisotropic etching, using those portions of the positive resist partially remaining in a step portion as a mask; removing the remaining portions of the positive resist and then introducing an impurity having a high concentration into the gate electrode and the source and drain regions of an MOS transistor using a remaining portion of the thick insulating film as a mask; and then forming a silicide layer on exposed portions of the gate electrode and the source and drain regions of the MOS transistor, respectively, to thereby obtain a high-melting metallic silicide structure.
According to the present invention, there is provided a method of manufacturing a semiconductor device, by which it is capable of obtaining an MOS transistor having low concentration drain regions with a long distance, by a simple method and at a low cost.

Method of manufacturing a semiconductor device with a silicide


A ceramic shroud assembly includes a tip shroud having an outer platform supporting at least one seal tooth, a shroud cap less brittle than the outer platform and including a shroud cap base on the outer platform, and clockwise and counter-clockwise facing clockwise and counter-clockwise contact surfaces located at clockwise and counter-clockwise distal ends respectively of the base. A rotor assembly may include a circumferential row of turbine blades made of a ceramic material and extending radially outwardly from a disk of a turbine rotor. The turbine blades include airfoils having the airfoil tip shrouds and the shroud caps at blade tips. The clockwise and counter-clockwise contact surfaces of circumferentially adjacent ones of the shroud caps contact each other. The shroud and the platform may be made of a ceramic or ceramic matrix composite material and the shroud cap may be made of a metallic material.

1. Technical Field
The present invention relates generally to gas turbine engine turbine blade tip shrouds and, more particularly, to turbine blade tip shrouds for ceramic turbine blades.
2. Background Information
Some gas turbine engines employ blade tip shrouds on individual airfoils to limit blade amplitudes when vibrating due to forced or resonant response and to reduce aerodynamic flow losses and leakage over the tip of the airfoil and to guide fluid flow over the airfoils. This is particularly true in the low pressure section of a gas turbine engine. Neighboring shrouds abut in the circumferential direction to add mechanical stiffness, and provide damping during blade vibration. When a series of such assemblies are mounted together, the tip shrouds define, in effect, a continuous annular surface. Circumferentially opposite edges of the tip shrouds are provided with abutment faces and are designed to provide desired tip constraint at assembly and engine operating conditions.
Annular seal teeth extend radially outwardly from the shrouds to engage seal lands to seal the gas flowpath between the tip shrouds and casing surrounding the rotor. The seal lands typically are in the form of a honeycomb covered stator shroud. It is known to use ceramic or ceramic matrix composite (CMC) materials for turbine airfoils.
It is known that light weight, uncooled, high temperature capability, ceramic matrix composite (CMC) airfoils may be used for turbine blades in the low pressure turbine. Ceramic and ceramic matrix composite (CMC) materials are low strain to failure materials. One ceramic matrix composite material suitable for turbine blades is a SiC—SiC CMC, a silicon infiltrated silicon carbide composite reinforced with coated silicon carbide fibers. CMC's are an attractive alternate material to Nickel based superalloy low pressure (LPT) blades because of their high temperature capability and light weight. These characteristics provide opportunities for cooling flow savings as compared to cooled LPT blades. This also provides possible improvement in design optimization of disks which support LPT blades.
Design challenges posed by CMC LPT blades include low thermal coefficient of expansion, low strain to failure, and relatively poor wear characteristics. The low thermal coefficient of expansion results in smaller growth of the tip shroud in the tangential direction during operation relative to metal blades. The impact of this is a reduction and possible loss of interlock load between adjacent blade tip shrouds which may also be a potential HCF issue and an increase in leakage area around the tip shrouds perimeter which is a performance issue.
Due to the brittle nature and lack of damage tolerance of CMC's compared to metals, the material is very susceptible to chipping, cracking, and impact damage. For these reasons, CMC on CMC contact at the interlock faces of the blade tip shrouds is a design concern. The main concern is loss of material and reduction and possible loss of interlock load. The poor wear characteristics are an issue with regards to the rotating seal teeth cutting the static shroud honeycomb and the relative motion of interlock surfaces on adjacent LPT blade tip shrouds.
The impact of wear on the seal teeth can increase environmental degradation resulting in an excessively large leakage path between the seal teeth and the shroud which lowers overall engine performance and fuel efficiency. It can also result in fraying of CMC plies which is a durability issue. The impact of excessive wear on the interlock surface could be a loss of interlock load resulting in an undamped airfoil prone to forced or resonant response.
Accordingly, it is desirable to have a CMC LPT blade and blade tip shroud designs which lower or prevent loss of CMC material and prevent reduction and possible loss of interlock load between adjacent blade tip shrouds, and possible sealing issues.


This invention relates to a method, system and apparatus for detecting when an animal is in heat. The invention further relates to a method of alerting a responsible individual that the animal is in heat. The method for detecting when an animal is in heat comprises the steps of, using a sensor mounted on a bull, monitoring the activity of the bull in the proximity of the animal. Thereafter, the activity of the bull is analysed before finally it is determined, based on the analysed activity of the bull, whether or not the animal is in heat. The invention shifts the focus from the animal, such as a cow, to the bull and leans on the natural instincts of the bull to determine when the cow is in heat. By implementing such a system, a more reliable and/or less expensive system than many of the existing offerings is provided.

The present invention is particularly suited, although not limited solely to, detecting when a cow is in heat. For simplicity, the invention will be described in terms of detecting when a cow is in heat however it will be understood that the invention may be used with other animals such as horses and the like.
Accurate detection of when a cow is in heat is fundamental to the efficient management of a herd. In the northern hemisphere, it is preferable for cows to be calving in February or March in order to maximise the use of grass to feed the cows and the weaned calves. As the typical gestation period for cows is approximately 283 days, it is therefore important to ensure that the cows are impregnated in or around May or June of the preceding year. In order to achieve this, it is important to accurately detect when a cow is in heat so that the cow may be impregnated.
The complete reproductive cycle of a cow lasts approximately 21 days, and the cow is in estrus, i.e. that period when they are receptive to a mate, for a period of approximately 12 hours. If this relatively narrow window to inseminate the cow is missed, the farmer will have to wait for approximately 21 days before they get another opportunity to have the cow inseminated. In dairy herds, cows produce milk for about 10 months after a calf is born. The cows produce the best and cheapest milk when they have good access to grass/feed. The farmer will milk the cows for 10 months, then dry the cows off and give them 2 months rest before the cows give birth again; then the cycle continues. If a dairy farmer misses a cow's heat, come dry off time for the herd, he will have milked that animal for 21 days less than the others and the farmer has to decide whether or not to continue milking the cow (i.e. to maximise revenue and disrupt the process) or to dry the cow with the rest of the herd. At present values, an average cow produces 240 euro of milk every 21 days, hence this is the value potentially lost by the farmer.
Various devices have been proposed to detect when a cow is in heat. For example, one such device is the Heat Seeker (Registered Trade Mark®) sold by Beacon Heat Detectors Pty Limited of Muswellbrook, New South Wales, Australia. This device comprises a self-adhesive patch that may be mounted on the rump of the animal. The patch is provided with a pressure-activated capsule that will rupture if pressure is applied thereto and will cause the patch to change colour, indicating that the cow is potentially in heat. Another device provided by Beacon Heat Detectors Pty Limited is the ScratchE® which comprises a self-adhesive patch that has a sacrificial top layer that may be rubbed off to expose a colourful under-layer. In both cases, the devices are activated by mounting activity of herd mates. Although useful and relatively inexpensive when compared with some of the other solutions, these devices may be prone to false alarms, may lack accuracy and require regular on-site monitoring of the animals.
A similar device to the Heat Seeker® and the ScratchE® is the bull chin collar as described in U.S. Pat. No. 3,842,802. This is a device mounted on a bull that uses a paint ball to mark the cow when the mounts the cow. However, this device is prone to false alarms, may lack accuracy, requires regular on-site monitoring of the animals and requires regular access to the bull.
Other devices operate by monitoring the activity levels of the cow. It is well known that a cow in heat walks more than a cow that is not in heat. Accordingly, it is known to place a pedometer on each of the cows in a herd to track the cows' activity. The data is then captured in a base station twice a day when the cows are led in to be milked and the data is relayed to a computer where it may be processed. Cows that are in heat may be identified and inseminated. One such system is that sold under the brand AfiAct II® by Afimilk Limited of Kibbutz Afikim, Israel. Although also useful, there is a difficulty in that it is necessary to place a pedometer on each of the cows in the herd and this can result in considerable capital expenditure for the farmer. Also, this detection methodology is rather crude and generally speaking is not highly accurate.
Another heat detection product sold by Afimilk Limited is their Silent Herdsman® which comprises a smart collar worn around the neck of the cow. The smart collar may be used to monitor the heat expression of the animal. Another smart collar device worn by a cow and used for heat detection is the Moo Monitor+® as sold by Dairymaster Limited of Tralee, Ireland. Another still smart collar device worn by a cow and used for heat detection is the Heatime® HR system as sold by SCR of Netanya, Israel. Although useful and effective, there is a problem with these devices in that an intelligent collar must be placed on each of the animals in the herd and this can result in considerable expense and greater computational burden.
One alternative offering is the Herd Navigator® as sold by DeLaval Group of Tumba, Sweden. This offering samples milk from each cow in the herd for progesterone levels in the milk. From this, it is possible to predict with good accuracy whether or not a cow is in heat. The Herd Navigator® forms part of a larger, more comprehensive dairy management system and would be considered to be a relatively expensive solution.
More recently, a number of systems and methods have been proposed that monitor the actions of a bull as well as the animal and more specifically the interactions between the bull and the animal. For example, PCT Patent Application Publication No. PCT/EP2016/103079 in the name of Castro Lisboa et al, US Patent Application Publication No. US2008/128486 in the name of Breedcare, PCT Patent Application Publication No. WO03/045273 in the name of De Boer and U.S. Pat. No. 4,503,808 in the name of McAlister all disclose systems and method for monitoring the interaction between a bull and an animal. Although an improvement on many of the existing offerings, there is a desire to improve the accuracy of the known devices and minimise the number of false alarms generated by some of the known devices. False alarms are a continuing source of annoyance to the farmer as they result in the waste of valuable and scarce resources.
It is an object of the present invention to provide a method, system and apparatus for detecting when an animal is in heat that overcomes at least some of the above-mentioned problems. It is a further object of the present invention to provide a method, system and apparatus for detecting when an animal is in heat that is accurate, relatively inexpensive and that offers a useful choice to the consumer.

Method, system and apparatus for detecting when an animal is in heat


A method of forming a body-tie. The method includes forming the body-tie during an STI scheme of an SOI process. During the STI scheme, a first trench is formed. The first trench stops before a buried oxide layer of the SOI substrate. The first trench may determine a height of body tie that is shared between at least two FETs. A second trench may also be formed within the first trench. The second trench stops in the SOI substrate. The second trench defines the location and shape of a body-tie. Once the location and shape of the body-tie are defined, an oxide is deposited above the body-tie. The deposited oxide prevents certain implants from entering the body tie. By preventing these implants, a source and a drain implant may be self-aligned to the source and drain areas without requiring the use of the photoresist mask to shield the body tie regions from the source and drain implant.

One issue that FETs fabricated in an SOI substrate may experience is a floating body effect. In such FETs, floating body effects are a result of having a body region that is electrically isolated from a bulk substrate. In order to supply a voltage potential to the body, and therefore mitigate floating body effects, an applied bias is often supplied from a body-contact to the body. When the body-contact receives an applied bias, which may be a ground or a positive or negative potential, it carries it to the body via a body tie. Often times, the body-tie is formed in device layer silicon and runs beneath an oxide.
In general, the body-tie allows the body region and the body-contact to be in remote locations in an SOI substrate. Unfortunately, however, the body-tie may be exposed to a variety of processing steps during the fabrication of a FET. Implant steps, for example, may cause ions to penetrate the oxide layer and alter a body-tie's conductive properties. To prevent such exposure, an SOI based process flow may need to include additional process steps to accommodate a body tie. In the example above, an additional photo-resist mask may be needed to prevent implantation into the body-tie. This and other types of accommodation increase process complexity and decrease yield.