Innovative self-adaptive and self-calibrated methods and structures for Multi-Level Cell (MLC) Non-Volatile Memory (NVM) are disclosed. In the MLC NVM, NVM cells are self-adaptively programmed into a fixed response tolerance window centered at the reference current or voltage corresponding to a selected level gate voltage applied to the controlled gates of NVM cells. The fixed response tolerance window is related to the threshold voltage tolerance window through the sense circuit gain. Properly choosing the sense circuit gain and the response window can control the threshold voltage tolerance window to a desired value. An incremental gate voltage larger than the threshold voltage tolerance window of each NVM cell will guarantee that each NVM cell will produce the correct output current (voltage) in response to applying to the control gate of the NVM cell the stepped voltage corresponding to the level of information stored in the NVM cell. As the stepped voltage applied to the gate of an NVM cell transitions from a voltage just below the threshold voltage of the NVM cell to a voltage corresponding to the threshold voltage of the NVM cell, the output current (voltage) from the NVM cell will pass the current (voltage) transition in comparison with the reference current (voltage). The current (voltage) transition can be detected and converted into the bit-word information representing the voltage level stored in the NVM cell. When the response of an NVM cell falls outside the response tolerance window into the guard-band regions, the NVM cell can be re-calibrated and the bit-word information can be saved from fading away.

Data is stored in an NVM cell by modulating the threshold voltage, Vth, of the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) in the NVM through the injection of charge carriers into the charge-storage layer from the channel of the MOSFET. For example, with respect to a MOSFET, an accumulation of electrons in the floating gate, or in a dielectric layer above the FET channel region, causes the MOSFET to exhibit a relatively high Vth, while an accumulation of holes in the floating gate, or in a dielectric layer above the FET channel region, causes the MOSFET to exhibit a relatively low Vth. As illustrated in FIG. 1, the curves for source-to-drain current Ids versus the applied gate voltage Vg under the same drain voltage bias are parallel shifted toward the right along the applying gate voltage axis with higher threshold voltages and vice versa.
The number of bits stored in an NVM cell is determined by the number of resolvable threshold voltage levels, given by Number of Bits=log2 (number of resolvable threshold voltage levels). The more threshold voltage levels that can be sensed and resolved, the more bits that can be stored in a single NVM cell.
In the conventional MLC NVM, the threshold voltage level sensing has been done by comparing the current (voltage) responses from the memory cells with the current (voltage) response of reference cells, whose threshold voltage levels are pre-trimmed to the reference response current (voltage) levels under the same gate voltage bias. However, due to the non-uniformity of transconductance "gm" (where gm=ΔIds/ΔVg) and threshold voltage Vth for NVM cells inherited from the manufacturing process, the drive current-gate voltage curves are different in slopes (transconductance) and threshold voltages (onset point) for different NVM cells supposedly having the same threshold voltage as illustrated in FIG. 1. In FIG. 1, for each specified threshold voltage level, the solid-line represents the typical cell drive current vs. control gate voltage curve for a cell having the median transconductance, the dashed-line represents this curve for a cell having the maximum transconductance associated with this specified threshold voltage level, and the dotted-line represents this curve for a cell having the minimum transconductance with this specified threshold voltage level). Note that each line group (solid, dashed, dotted) for a specified threshold voltage level represents three different transconductances of the NVM cells. The four line groups shown vary their threshold voltages (ΔVth0, ΔVth1, ΔVth2, and ΔVth3) at four different threshold voltage levels. Specifically, in a population of NVM cells, the variations from cell to cell in aspect ratio (width/length) due to lithography, oxide thickness, or oxide trap density cause the variations in NVM cell transconductance, while the variations in channel impurities or fixed charges cause the variations in NVM cell original threshold voltages before programming. The variations among NVM cells including the reference cells impose a limitation on the number of resolvable threshold voltage levels capable of being achieved especially in the reference cell comparison scheme with a constant gate voltage applied as seen in FIG. 1.
Furthermore, since the memory cells experience more write-erase cycles than the reference cells, the transconductance degradation (smaller slope in the drive current-gate voltage curves) in memory cells become more severe than the transconductance degradation in reference cells. Throughout the device lifetime, other techniques to compensate this effect such as cycling the reference cells or re-adjusting the offsets of the sense amplifiers are required.
Other techniques to sense the drive current in NVM cells using stepped gate voltages to NVM cells have been applied to NOR-type NVM (M. Bauer et al., Intel Corporation, 2005 IEEE International Conference on Integrated Circuit and Technology) and to NAND-type NVM (T. S. June et al., Samsung Electronics, IEEE J. of Solid-State Circuit, Vol. 31, No. 11, pp. 1575, November 1996). In both these techniques, there is no requirement for the pre-trimmed reference cells. The stepped gate voltages are chosen in between specified threshold voltage levels. Besides including the whole threshold voltage distribution associated with a plurality of memory cells programmed to be at a specified threshold voltage level, the stepped voltage increment requires a guard-band voltage between the minimum (maximum) acceptable threshold voltage for a cell programmed to be at the specified level and the maximum (minimum) acceptable threshold voltage for a cell programmed to be at the next lower (higher) specified level such that the whole threshold voltage distributions of the programmed NVM cells for the levels after erase-write cycling and high temperature baking must still reside between the stepped gate voltages as illustrated in FIG. 2 (solid-line original and dotted-line worn). With large enough gate voltage increments to the control gates of NVM cells, combination logic circuitry receiving the responses of sense circuitry can determine the threshold voltage levels of the NVM cells after applying all three stepped voltages and thus determine the binary information represented by the charges stored on the memory cell.
As seen in the stepped gate voltage schemes as illustrated by FIG. 2, the resolvable levels for the MLC NVM are limited by the distribution of the programmed NVM threshold voltages and the guard-band voltages between levels. The width of the threshold voltage distribution associated with the MLC NVM cells for each threshold voltage level depends on the uniformity of programming conditions (speed, background coupling, and noise) and the characteristics of the NVM cells. It has been reported that the distribution of programmed threshold voltages for an NAND-type flash memory is widened by cell program speed, background pattern dependency, read-verification offset, and neighboring floating gate coupling (T. H. Cho et al., Samsung Electronics, IEEE J. of Solid-State Circuit, Vol. 36, No. 11, pp. 1700, November 2001). The widened distribution of threshold voltage after erase-write cycling and high temperature baking (as shown in FIG. 2 by the dotted line curves) strongly depends on the gate dielectric thickness and quality of the NVM cells. These parameters can vary with the NVM cells in a given memory as well as with the NVM cells from memory to memory. Thus FIG. 2 shows in solid lines the distributions of actual threshold voltages associated with four different given threshold voltage levels when the NVM cells are relatively new and have been programmed only a few times and also shows in dotted lines the same distributions after the NVM cells have been used for some time and reprogrammed a large number of times. The dotted line distributions show that with use, the threshold voltages of the NVM cells shift down. To determine the particular threshold voltage associated with a given NVM cell, stepped gate voltages are applied to the control gate of the cell and the drive current Ids is measured. The two stepped gate voltages which result in no Ids current and an Ids current allows a sense amp together with logic circuitry to detect the actual threshold voltage level of the NVM cell and thus the binary information stored in the cell.
In order to ensure that the threshold voltage of some cells in the NVM cell array do not, with age, have a threshold voltage which falls below the lower of the stepped gate voltage for a given reference threshold voltage, a guard band is provided between what is expected to be the lowest threshold voltage for an NVM cell in the memory array and the stepped gate voltage directly below that given reference threshold voltage. A similar guard band is provided between the highest expected threshold voltage associated with a given threshold voltage level and the stepped gate voltage directly above this given threshold voltage level to ensure that no NVM cell in a memory array has an actual threshold voltage which, when the cell is being programmed to the given threshold voltage, exceeds this next higher stepped gate voltage. FIG. 2 shows these guard band voltages in relation to the stepped gate voltages for a typical array of NVM cells.

Self-adaptive and self-calibrated multiple-level non-volatile memories


An MRI pulse sequence control system includes a pulse sequence controller, a controller, and a performance monitor module. The pulse sequence controller generates pulse sequence control data. The controller controls scanner devices according to the control data. The performance monitor module monitors performance of the controller during an MRI scanning procedure and provides controller performance information to the pulse sequence controller. The pulse sequence controller modifies the control data in response to the controller performance information. The controller responds to the control data during the MRI scanning procedure. A process for detecting errors in an MRI scan process includes monitoring performance of the controller during the MRI scanning procedure. Controller performance information is provided to the scanning pulse sequence controller. Control data generated by the scanning pulse sequence controller is modified in response to the controller performance information. The controller responds to the control data during the MRI scanning procedure.

An MRI scanning procedure requires a coordinated effort among many pieces of hardware and software. Collection of scan data and production of images from the scan data must be carried out with precision if the resulting images are to have diagnostic value. Glitches in the procedure, due to hardware fatigue, software malfunction, electrical noise, temperature effects, or any other deviation by any operational parameter outside of an acceptable tolerance can have a negative effect on the results.
For example, timing problems in pulse sequence hardware and firmware can cause image artifacts due to shifting of pulse sequence waveforms. In a typical MRI scanner a pulse sequence system governs the timing and control of scanning devices. A stream of control data, typically generated by software on a PC, is transferred to a controller that times the provision of data to the various devices. Often, an intermediate processor receives the control data in a stream, buffers the control data, and provides blocks of the control data to the controller, which typically is hardware that resides on a circuit board.
The timing of the data transfer to the controller is determined by interrupts generated by the controller and provided to the intermediate processor. Occasionally, timing aberrations in the interrupt sequence result in device miscues, which in turn result in artifacts in the resulting image. If the timing errors are not detected, or if they are only reported at the end of a scan procedure, the artifacts will be present in the images, and the scan procedure might have to be repeated.
It would be advantageous to detect operational parameter deviations and other errors during the course of the scan procedure. It would also be advantageous to provide a report of these errors, and to act on the report during the scan procedure to correct portions of the scan procedure sequence while the procedure is taking place, so that the resulting image will be sufficient for diagnostic use.

Process and system for detecting and correcting errors in an MRI scan process


An elongate inserter has a distal end releasably connected to an expandable interbody fusion device and a proximal end including a trigger actuator. The interbody fusion device comprises a superior endplate and an inferior endplate that are movable in an expansion direction relative to each other in the intradiscal space. The inserter includes a lifting platform and an elevator that define cooperatively engaging ramps and ramps surfaces that upon operation of the trigger actuator cause the superior and inferior endplates to move relatively away from each other. A driver is supported by the inserter for pushing an insert into the expanded device between the superior and inferior endplates.

Spinal implants such as interbody fusion devices are used to treat degenerative disc disease and other damages or defects in the spinal disc between adjacent vertebrae. The disc may be herniated or suffering from a variety of degenerative conditions, such that the anatomical function of the spinal disc is disrupted. Most prevalent surgical treatment for these conditions is to fuse the two vertebrae surrounding the affected disc. In most cases, the entire disc will be removed, except for a portion of the annulus, by way of a discectomy procedure. A spinal fusion device is then introduced into the intradiscal space and suitable bone graft or bone substitute material is placed substantially in and/or adjacent the device in order to promote fusion between two adjacent vertebrae.
Certain spinal devices for achieving fusion are also expandable so as to correct disc height between the adjacent vertebrae. Examples of expandable interbody fusion devices are described in U.S. Pat. No. 6,595,998 entitled "Tissue Distraction Device", which issued on Jul. 22, 2003 (the '998 patent), U.S. Pat. No. 7,931,688 entitled "Expandable Interbody Fusion Device", which issued on Apr. 26, 2011 (the '688 patent), and U.S. Pat. No. 7,967,867 entitled "Expandable Interbody Fusion Device", which issued on Jun. 28, 2011 (the '867 patent). The '998 patent, the '688 patent and the '867 patent each discloses sequentially introducing in situ a series of elongate inserts referred to as wafers in a percutaneous approach to incrementally distract opposing vertebral bodies to stabilize the spine and correct spinal height, the wafers including features that allow adjacent wafers to interlock in multiple degrees of freedom. The '998 patent, the '688 patent and the '867 patent are assigned to the same assignee as the present invention, the disclosures of these patents being incorporated herein by reference in their entirety.
One issue that has arisen regarding such interbody fusion devices that use inserts or wafers to incrementally expand such devices is the determination of when full expansion has been achieved as a result of ligamentotaxis and no further inserts may be inserted. It is therefore desirable for a surgeon to know when a sufficient number of inserts has been introduced to stabilize the spine and correct spinal height and whether any additional inserts may be introduced.
Accordingly, there is a need for a method and instrument to expand an expandable interbody fusion device and introduce inserts therein and to determine when proper expansion of the device has been achieved and no further inserts may be introduced.

This patent is subject to a terminal disclaimer.

Apparatus and method for expanding opposing body tissue


In a lithium ion secondary battery having a positive electrode, a negative electrode, non-aqueous electrolyte, and a container sealing the electrodes anrd electrolyte therein, the positive electrode is formed of a positive electrode active material which is produced by electrochemically intercalating lithium ions into lithium manganese oxide in the container to give a positive electrode active material precursor comprising lithium manganese oxide of which lithium ion contents are increased, and then releasing lithium ions from the positive electrode active material precursor in the container, and the negative electrode is formed of a negative electrode active material which is produced by intercalating the released lithium ions into a negative electrode active material precursor of a metal oxide in the container.

A lithium ion secondary battery is known as an advantageous secondary battery which is able to give a high voltage of about 4 volts and a high discharge capacity. As the positive electrode active material of the lithium ion secondary battery, LiMn.sub.2 O.sub.4 having the spinel crystal structure, as well as LiMnO.sub.2, LiCoO.sub.2, LiCo.sub.1-x Ni.sub.x O.sub.2 or LiNiO.sub.2 which has the rock salt crystal structure have been generally employed. The LiCoO.sub.2 having the rock salt crystal structure shows higher voltage and higher discharge capacity than other oxides and therefore is advantageous. However, the LiCoO.sub.2 has such drawbacks that cobalt is high in its cost and less available than other metals, and moreover may cause environmental pollution if battery wastes containing the lithium cobalt oxide are left outside
Japanese Patent Provisional Publication H3(1991)-147276 proposes a lithium ion secondary battery using LiMn.sub.2 O.sub.4 of the spinel crystal structure as the material for its positive electrode, that is, cathode. Manganese is less expensive and easily available, and moreover scarcely causes environmental pollution. However, LiMn.sub.2 O.sub.4 gives a charge capacity (corresponding to amount of releasable lithium ions) per unit volume less than LiCoO.sub.2 by 10 to 20%. This means that if the LiMn.sub.2 O.sub.4 is combined with a negative electrode active material of high capacity to prepare a secondary battery, the volume of the LiMn.sub.2 O.sub.4 (namely, positive electrode active material) to be used should be increased so as to balance its capacity with the high capacity of the negative electrode active material. As a result, the amout of the negative electrode active material encased in a container of a battery should be reduced, and then the battery capacity lowers.
Japanese Patent Provisional Publication H4(1992)-147573 describes a lithium ion secondary battery using Li.sub.1+M Mn.sub.2 O.sub.4 (x>0) as the positive electrode active material precursor in combination of a negative electrode active material precursor such as carbonaceous material. Such positive electrode active material precursor--negative electrode active material precursor combination in a container of a battery is electrochemically converted into a positive electrode active material--negative electrode active material combination by electrically charging thus prepared battery so as to release lithium ions from the positive electrode active material precursor and intercalate the released lithium ions into the negative electrode active material precursor in the container.
The Li.sub.1+x Mn.sub.2 O.sub.4 having a lithium ion amount higher than LiMn.sub.2 O.sub.4 is advantageous because it gives a charge capacity higher than LiMn.sub.2 O.sub.4. In the lithium ion secondary battery described in the last Publication, the positive electrode active material of Li.sub.1+x Mn.sub.2 O.sub.4 is produced electrochemically once in an electric cell or chemically in a known process outside an electric cell and then placed in a container of a final battery product. Li.sub.1+x Mn.sub.2 O.sub.4 is known to be extremely unstable and easily oxidized. Therefore, this process and the secondary battery prepared by this process may cause problems in industrial preparation and use.


A unit: (a) sets event largest possible values used for limitation of the number of tasks and/or the size of areas in a buffer; (b) generates a task without reaching the event largest possible values when receiving an event, and reserves an area in the buffer for the task; (c) determines whether another event has been received before process of the task is completed; (d) deletes the task and releases the area if another new event has not been received; (e1) if it has been received and both the number of tasks and the size of the areas do not reach the event largest possible values, generates a new task and reserves another area in the buffer; and (e2) if it has been received and any of them reaches any of the event largest possible values, reuses the task and the area for the new event.

1. Field of the Invention
This invention relates to an information processing system and a computer readable recording medium storing an information processing program for processing tasks generated based on events transmitted from one or more peripheral devices after storing the task into a buffer.
2. Description of the Related Art
In general, when print data is transmitted from a personal computer to an image forming device such as a printer, processing rate of image forming process based on the print data received by the image forming device is much lower than communication rate between the computer and the image forming device.
Consequently, image forming process may stop intermittently due to low rate of the image forming process when the image forming device receives print data transmitted from one or more personal computers one after another. For this reason, generally, a buffer of semiconductor or the like is set up for processing the print data in the image forming device or a print server between the computer and the image forming device so that image forming process is performed at the same rate as printing rate by storing the received print data temporarily and reading out it in turn.
As described above, it is well known that in an information processing system, a controller such as a print server generates tasks based on events (e.g. print data) transmitted from one or more peripheral devices (e.g. personal computers), and the tasks generated by the controller are stored in a buffer, then a processing device (e.g. an image forming device) processes the tasks.
There is well known one of such information processing systems that has an intermediate buffer having continuous physical addresses, buffer-device intermediate transferring means that performs data transfer between physical addresses of an input/output device and the intermediate buffer, buffer-to-buffer intermediate transferring means that performs data transfer between the intermediate buffer and a target buffer as the final destination of the data transfer, and data transfer controlling means that controls the buffer-device intermediate transferring means and the buffer-to-buffer intermediate transferring means to get unit and timing of the data transfer suitable for the input/output device, and moreover, a transmission buffer as the intermediate buffer has been provided before transmitting data from a peripheral device to a host device. See Japan Laid-Open Patent Application H02-214960, for example.

Information processing system and computer readable recording medium storing an information processing program


This invention provides an apparatus for identifying and sorting part of recycling plastic bottles and aluminum cans. The invention eases the process of sorting recyclable material at the recycle bin to avoid the sorting later in the process. After sorting the material, the recycle bin compresses the bottles or the cans to accommodate more material into the corresponding material compartment. The invention is a modular arrangement allowing ease of replacing any of the three units of the apparatus: compression, classification, and storage.

Waste and garbage management is one of the most critical problems of our time. Several attempts have been made in the past to overcome the problems associated with waste management and efficient trash recycling. For example, U.S. Pat. No. 7,143,905 provides an enclosure for a refuse container and a recyclable container includes a frame; a front and a rear carried by the frame and including an advertising holder, a refuse opening, and a recyclable opening, the refuse opening receiving refuse therethrough for depositing the refuse in the enclosed refuse container, the recyclable opening receiving recyclables therethrough for depositing the recyclables in the enclosed recyclable container; a rear carried by the frame and including an advertising holder for holding advertising; a left side carried by the frame and including an advertising holder for holding advertising; a right side carried by the frame and including an advertising holder for holding advertising thereon; and a roof carried by the frame. U.S. Pat. No. 5,447,017 provides an automatic recycling machine and automatic waste disposal system for plural types of household and commercial waste materials which automatically sorts, processes, shreds, crushes, compacts, rinses by cleaning liquid for removal of contamination and dirt from certain washable waste types, packages the waste material, and identifying the package with waste type and waste source by barcode marking. U.S. Pat. No. 4,821,969 provides in a can crusher, cans lying in a semicylindrical compaction chamber are crushed between a movable ram and a stationary anvil plate. The ram is driven by a ram rod extending from the ram, a ram rod crank arm pivoted to the ram rod and rotated by a power driven crankshaft. Crushed cans are ejected from between the ram and anvil plate after being crushed, and uncrushed cans are fed to a lengthwise position in the compaction chamber each time the ram moves back from the anvil plate. The uncrushed cans are fed, end-to-end, into the compaction chamber from a feed tube located above the chamber. The feed tube has a skewer-receiving opening provided in it, and a skewer-retaining sleeve extends out from the feed tube in surrounding relationship to the opening. The skewer crank arm is fixedly mounted on the crankshaft in fixed angular relationship with respect to the ram rod crank arm. When the ram is in its closest position to the anvil plate, the skewer is clear of the interior surface of the feed tube to allow uncrushed cans to move into contact with a can restricting camming surface of the ram rod, but just before the bottom can slides over the can restricting camming surface of the ram rod, the next-to-the bottom uncrushed can has been impaled by this skewer. U.S. Pat. No. 6,141,945 provides a multi-unit, automatic machine for compaction, packaging, and disposal of plural types of material such as newspaper, plastic containers, glass bottles, aluminum cans, or other household and commercial waste. Each type of material is automatically processed in a separate unit and than separately packaged and sealed in a special bar coded bag, which is then disposed of the machine.
However, there is long felt need for a low-cost integral recycling solution that allows modular replacement of its components while gathering associated data to share and analyze with other users or recycling apparatus.


A semiconductor memory device including semiconductor memory cells with at least one memory cell capable of either acting as a storage device for ECC information or of acting as a redundant memory cell is provided. The semiconductor memory device further includes a signal control device for signaling if the at least one memory cell is to be used either as a storage device or as a redundant memory cell. A method of operating a semiconductor memory device is also provided including the steps of registering a status of a signal device and, depending on the status of the signal device, operating the at least one memory cell either as a storing device for ECC information or as a redundant memory cell.

Most memory components (e.g., integrated circuits such as DRAMs) are generally fabricated with 1 bit-, 4 bit-, or 8 bit-wide input/output lines. In any of these configurations, the components cannot operate as memories having an error correction code (ECC). There are, however, memory components fabricated with 5 bit- or 9 bit-wide input/output lines. These components operate as memories having an ECC, with the 5th (or the 9th) line used as an ECC line.
Memory modules (e.g., DIMMs (Dual Inline Memory Modules) or SIMMs (Single Inline Memory Modules)) comprise, among other components, a plurality of memory components. These memory modules may include memory components equipped with only 1 bit-, 4 bit-, or 8 bit-wide input/output lines; consequently, no ECC mode can be run on the memory module. To provide an ECC function, an extra memory component is provided that operates exclusively as an ECC, cooperating with memory components comprising 1 bit-, 4 bit- or 8 bit-wide input/output lines. Alternatively, memory modules may include memory components equipped with 5 bit- or 9 bit-wide input/output lines. In this case, ECC operation is available with each of the memory components.
The use of such memory components is exclusive—semiconductor memory components or semiconductor memory modules equipped with ECC capability can only be used in an ECC computer system (and not in a computer system lacking ECC functionality). Conversely, individual memory components or modules not equipped with an ECC capability can only be used in systems having no ECC functionality (i.e., they cannot be used in ECC-capable systems).

Semiconductor memory device including a signal control device and method of operating the same


An illuminated protective headgear (10) has an inner core (11) of resilient cushioning material with cavities (18a, 18b, 19a, 19b), an outer shell (12) with portions overlying said core (11) with windows (13) that are clear to translucent or open and are of graphical configuration disposed on opposite sides of the headgear (10), and a power circuit supported by said inner core with lighting panels (44) having light sources (21–23, 25–27, 21a–23a, 25a–27a) disposed in the cavities (18a, 18b) so as to be viewed through a respective window (13), and timing circuitry for timing the on-off sequence of the lights, so as to create an effect of motion of the illumination within each window (13). Several embodiments are disclosed.

The use of various protective headgears is growing in today's society. Protective headgears are used in many recreational activities including, but not limited to, cycling, walking, running and participation in sports activities. These activities may be carried out at night or in low light conditions such that illumination would be advantageous. For example, strips of reflective material are well known for use in jogging clothing and shoes.
There have been attempts to develop illuminated headgears in industrial fields such as for mining and construction, for firefighting, and more recently for recreational use, including motorcycling.
Such headgears have been limited to use of large incandescent lights, electroluminescent light strips and more recently to use of small lighting elements such as light emitting diodes (LEDs).
Ippoliti et al., U.S. Pat. No. 4,319,308, discloses a motorcycle helmet which makes use of LEDs to direct light between two thin shells of curvilinear profile such that characters, such as alphabet letters, are illuminated on the side of the helmet. The light sources are located in the bottom of the helmet to direct light upward and generally parallel to the thin shells, with light being reflected between the shells due to the curvilinear profile of the shells.
Chien, U.S. Pat. No. 5,871,271, shows a cycling helmet with hard shell outer layer and a protective shock absorbing layer in which LEDs in star shapes and other shapes are proposed to be mounted on circuit boards that fit within recesses in the helmet. In one embodiment, the LED's are placed inside of enclosures with opaque and translucent portions to form illuminated star shapes. These shapes are quite small and intended to impart a shape to an individual LED element.
Mantha et al., U.S. Pat. No. 5,743,621, shows a helmet with illuminated translucent panels in the front and back of the helmet.
Many other prior patents show various types of illuminated headgears. Although each type of illumination process has their advantages and disadvantages, they are for the most part non-cost effective, difficult to produce and not very eye-appealing to the consumer. As a result these designs have not been widely seen in the recreational field.
Another technical problem in providing illuminated headgears, is retaining the strength of the helmet to impacts. Thus, the lighting assemblies should not result in a weakening of the structure of the headgear or a substantial lessening of the headgear's ability to distribute and absorb energy due to an impact.


A buckle that is compact in a longitudinal direction and uses an unlatching force that may be effectively applied to a latch member when releasing a tongue from a buckle. The buckle is configured so that as an operation button is manipulated in the unlatching direction from a state in which a tongue and a latching portion of a latch member are latched, the slider moves so that the inclined face of a pressed portion of the slider comes in contact with the inclined face of a pressing portion of an ejector and presses the ejector. Then, the ejector is spaced from the tongue and the biasing force of an ejector spring is effectively applied to the latch member via the ejector and the slider in the unlatching direction. An unlatching force is thereby applied to the latch member so that the latch member pivots in the unlatching direction, causing release of the tongue.

The present invention relates to a buckle to be used in a seat belt apparatus and a seat belt apparatus which is installed in a seat of an automobile or other vehicle that employs the buckle.
Conventionally, seats of various vehicles such as automobiles are equipped with seat belt apparatuses for protecting occupants in the event of an emergency such as a vehicle collision. Such a seat belt apparatus is normally provided with a buckle in order to facilitate an occupant putting on and removing the seat belt apparatus. Generally, the buckle is latched with a tongue which is slidably supported to a seat belt, whereby the seat belt can restrain the occupant.
A buckle has been proposed in Japanese Unexamined Patent Publication No. 2001-063515 (incorporated by reference herein) in which, for latching a tongue into the buckle, a latch member pivots so that a latch portion formed at an end of the latch member is inserted into a latch hole of the tongue, the tongue is held in the state latched with the latch portion by an ejector with the biasing force of an ejector spring, and the latch member is held in the latched state by a slider to prevent the latch member from moving in a unlatching direction and a lock pin for depressing the slider in a state to prevent the movement of the latch member in the unlatching direction, while, for releasing the tongue from the buckle, the lock pin is moved by an unlatching operation with an operation button to cancel the latched state of the latch member, and the ejector causes the latch member to pivot in a unlatching direction and push out the tongue from the buckle with the biasing force of the ejector spring.
In such a buckle, because the ejector causes the latch member to pivot when releasing the tongue from the buckle, it is desired to effectively apply the biasing force of the ejector spring as an unlatching force to the latch member. For this purpose, because the biasing force of the ejector spring is applied to the end of the latch member via the ejector in the aforementioned buckle, it is conceivable to construct a straight line connecting the end (a portion to which the biasing force of the ejector spring is applied) of the latch member and the pivotal axis of the latch member in a perpendicular orientation to the moving direction of the ejector as possible.
However, to achieve this the buckle must be long in the longitudinal direction because the pivot path of the end of the latch member projects largely toward a tongue insertion opening when the latch member pivots. Alternatively, it is conceivable to simply increase the unlatching force in order to improve the releasing performance between the tongue and the buckle. However, as the unlatching force is increased the slider and the lock pin receive the increased unlatching force. To compensate this, the strength of the slider and the lock pin must be increased.
Therefore, it is difficult to effectively apply the biasing force of the ejector spring to the latch member in the conventional buckle because the conventional buckle has a limitation in making the aforementioned straight line nearly perpendicular to the moving direction of the ejector without increasing the length of the buckle in the longitudinal direction and without increasing the strength of the slider.
It is also desired to improve the comfort to occupant wearing the seat belt as much as possible.


A first AD converting part of an AD converter converts an input voltage into a digital value of a predetermined number of bits and output the digital value to a digital output circuit and a DA converting part. The DA converting part converts the digital value into an analog value. A subtracting part outputs a difference between the analog value output from the DA converting part and the original input voltage. An amplifying part amplifies the difference output from the subtracting part. An output from the amplifying part is input to the first AD converting part via a feedback path. A subsequent output from the amplifying part is input to the second AD converting part via a branch path so as to produce a digital value of a predetermined number of bits. While the second AD converting part performs conversion, a subsequent input voltage is subjected in parallel to AD conversion by the first AD converting part.

1. Field of the Invention
The present invention relates to an analog-to-digital converting circuit and, more particularly, to a technology of cyclic AD converters.
2. Description of the Related Art
In recent years various additional functions such as an image shooting function, an image reconstruction function, a moving image shooting function, a moving image reconstruction function are provided in a portable phone set. As a result of this, there is a growing demand for miniaturization of and power-saving in analog-to-digital converting circuits (hereinafter referred to as "AD converters"). A cyclic AD converter is known as one configuration of AD converters. For example, reference is made to Japanese Laid-Open Patent Application No. 11-145830.
The cyclic AD converter mentioned above is more advantageous than a multi-stage pipelined AD converter in that the circuit area is reduced since the number of components constituting the cyclic AD converter is smaller than that of the multi-stage AD converter. However, reduction in circuit area is normally a trade off for a reduced conversion speed. Therefore, a task to be challenged in a cyclic AD converter is to promote efficiency in configuration and power consumption.

Analog-to-digital converting circuit and image processing circuit cyclically repeating AD conversion


A rocker shaft arrangement for a valvetrain system of an engine is provided. The rocker shaft arrangement includes a split rocker shaft having two fluidly separate internal regions. Each of the fluidly separate internal regions is arranged to selectively carry an independent supply of pressurized oil for distribution to valvetrain components. The two fluidly separate regions of the split rocker shaft are each further arranged to supply pressurized oil independent of each other to one of a high lift rocker arm and a low lift rocker arm of a rocker arm assembly for an engine valvetrain system.

In today's competitive automotive industry, it is becoming increasingly important for automotive manufacturers to deliver refined engines that offer strong performance while also balancing fuel economy considerations. Cylinder deactivation is being explored in the automotive industry as one option to increase fuel economy by deactivating certain cylinders of an engine when there is not a demand for such cylinders. Often such cylinder deactivation systems involve add on hardware that increases the cost and complexity of manufacturing the engines as well as requires additional parts that may increase the potential for long term durability concerns.
In addition, while the aforementioned cylinder deactivation systems are designed to improve fuel economy, such systems are generally not designed to increase engine performance. Similar to cylinder deactivation, the automotive industry has also been exploring variable lift valvetrains to improve engine performance under certain engine operating conditions. Generally, such variable lift systems have also required the addition of complex components that are independent of the cylinder deactivation hardware. These variable lift systems have thus resulted in a complex and costly valvetrain that is difficult to manufacture and potentially prone to durability issues.
Another disadvantage associated with both the cylinder deactivation systems and the variable lift systems is that the size and complexity of the add on hardware for each independent system results in a larger cylinder head that is difficult to package in today's relatively congested under hood engine compartment. Such a larger cylinder head is more expensive to manufacture and adds additional weight to the engine which is counterproductive to the goals of improving fuel economy and other engine performance characteristics.
Thus, there is a need for a compact valvetrain system having a rocker shaft arrangement that overcomes the aforementioned and other disadvantages.


Disclosed is a digital dividing circuit for dividing a timing signal. Memory elements are disposed in opposed pairs at opposed sides of a data loop. Each memory element is clocked to change the data bit it stores on each clock pulse. At least two opposed nodes along the data loop are coupled to one another by a memory content check MCC sub-circuit. The MCC checks for a desired relation between nodes. If the desired relation exists, then data values and phases rotate a step around the data loop during each clock cycle. If the desired relation does not exist, then the data value on one node is used to correct the data value on the opposed node so to achieve the desired relation. The clock signal is divided based on the number of memory elements around the data loop, and some or all pairs of opposed memory elements may be coupled through the MCC.

The vast majority of digital logic circuits require a clock signal to operate in cooperation with other circuits. This is especially true in modern telecommunications where signal sampling, channel feedback parameters, and information used to despread and decode a transmitted message are all highly dependent upon precise timing among devices. In the telecommunications realm, the changeover from analog to digital is generally described as moving the converter (analog to digital for transmitting, and digital to analog for receiving) as close as possible to the antenna, close meaning in the electronic pathway sense. As electronic sub-systems have become digitized, they are increasingly being integrated in fabricated circuit chips. Pure complementary metal-oxide semiconductor (CMOS) processes are becoming standard platforms for an increasing number of applications, including hardware for radio-frequency (RF) communications. Line-widths of the CMOS silicon processes continue to shrink as engineers learn to manipulate wafer fabrication with more precision. This results in more densely packed devices on a single chip, increasing electronic speed while decreasing physical size of implementing electronics and reducing chip costs.
One electronic bottleneck in RF ASICs has been generation of clock signals at a frequency less than that output by a high frequency oscillator. Many different processes within any individual electronic device—for example, sampling and decoding processes of a mobile station—must operate synchronously for seamless real-time communications. A single system clock is therefore desirable to maintain synchronous operation among the different sub-circuits, though those sub-circuits may operate at different clock speeds. Synchronous operation is obtained by dividing the system clock signal for those sub-circuits operating at less than the oscillator frequency. For example, co-owned International Patent Publication No. WO 00/31885, published on Jun. 2, 2000 and concerning RF signal processing in a radio telecommunication system, describes a divider that is used to divide a synthesizer signal so that received mixing signal corresponds to the selected frequency receive band. That reference is incorporated herein by reference for a particularly apt environment for the present invention, as detailed below. For example, a 4 GHz synthesizer may enable the same receiver to receive transmissions in the 2 GHz band or the 1 GHz band by dividing either by two or four, respectively. During transmission in the same system, that published application describes a similar function for a divider.
Analog dividers are known in the art, but occupy a large physical space and draw a large amount of power, both disadvantages for mobile telephony equipment. They often require some biasing to be functional, and are generally more sensitive to process variations. Conversely, classic digital dividers suffer from signal asymmetry, where the clock signal divider has outputs that are not balanced in phase (balanced being either matching or opposing phases). Digital clock dividers have also exhibited high noise, have imposed delays in signal processing, and typically draw a large current as compared to other more processing-intense circuits. For the above reasons, clock division continues to represent a bottleneck in the 'digital revolution'.
One well-known prior art circuit 20 to digitally divide a clock signal is shown in FIG. 1. A clock signal 22 drives a clocked memory element 24 (CME). The CME 24 lies within a data loop 26 with an inverter 28. First 30 and second 32 output nodes along the data loop 26 are labeled 30 and 32, respectively. The CME is, for example, a flip-flop circuit, where the rising edge of the clock pulse causes the data bit stored in the flip flop to be output and the falling edge of the same clock pulse causes the next data bit to be input and stored within. The inverter is a simple logic gate, generally implemented in CMOS via transistors. The designator "M" represents the data bit stored in the CME 24 of FIG. 1. Assume high and low data states of 1 and 0, respectively, where an initial data bit (e.g., following a first falling edge of the clock) stored in the CME 24 is high (1). Upon the next rising edge of the clock, the high bit (1) is output from the CME 24 and lies on the first output node 30, and is input into the inverter 28 where it is changed to low (0) and output to lay on the second output node 32. At the next falling edge of the clock, the low bit (0) is input into the CME 24 from the second node 32, and the bits at the first 30 and second 32 nodes remain unchanged. At the next rising edge of the clock, the low data bit (0) from the CME 24 is output to the first node 30, and also inverted at the inverter 28 to lie on the second node 32 as a high bit (1).
The following truth table shows the above results and make clear that the output on either the first or second node is at one half the rate of the clock signal. By using several clocked memory elements 24, the division factor can be increased from 2 to any multiple of 2 (i.e. 4, 6, 8 . . . ). Odd divisions like 3, 5, 7 etc. can be-obtained by using more sophisticated feedback logic. However, there are inherent disadvantages to the circuit of FIG. 1. Following each of the rising edges of clock pulses, there is a delay in inverting node 30 with the inverter 28, resulting in the outputs at the first and second nodes (30&32) being out of phase with one another. (i.e. the first rising edge of the clock changes the 1st node from 0 to 1 and the second rising edge changes the 1st node from 1 to 0; and so on. So two rising edges of the input clock cause only one rising edge (0 to 1) at the output clock, which means that the output clock is divided by two.
Clock pulseCME1st node2nd nodeFirst Falling Edge1First Rising Edge10Second Falling Edge0Second Rising Edge01
What is needed in the art is a circuit and method to digitally divide a clock signal that is low in noise, low in power consumption, adaptable to divide the clock signal by any fraction, and that keeps a phase relationship between various outputs of the circuit. Such a circuit would be particularly advantageous if it also operated without imposing circuit delays in real time signal processing of mobile telecommunications, and if it were made from circuit devices already used and readily fabricated.


An adjustable control valve for flow regulation of gas or liquid includes a controlled hose clamp device, preferably with two clamping members disposed on respective sides of a hose for adjustable compression of the hose and thereby setting of the flow cross-section of the hose at a compression site between the clamping members. The control valve comprises further a movable cam disk, e.g. a rotatable eccentric sheave actuated by a shifting mechanism, preferably a step motor, disposed for variable compression of the hose in accordance with the position of the cam disk or eccentric sheave. For automatically controlled setting of the flow cross-section of the hose, the shifting mechanism may be arranged to be controlled from a measuring device mounted for gauging the flow in the hose downstream of the compression site (As). In practice such regulation may be used for controlling the quantity ratios between the supplies of paint, jet formation air and atomizing air, respectively, to an atomizing gun, preferably by a common data processing unit inserted between the control valves and measuring device(s) in all control loops for the supplies of paint, jet formation air and atomizing air to the spray gun.

The present invention is related to an adjustable control valve flow regulation of gas or liquid, in particular for use in controlling the quantity of paint and air supplied during a spray painting operation.
Control of paint quantity and air supply for atomizing and jet formation with manual as well as robot controlled spray painting has up to now usually been performed by means of air pressure regulated mechanical controllers. Regarding the paint quantity control, these controllers have the disadvantage that they are substantially temperature and viscosity dependent and thus require cost and energy demanding regulation of the prevailing conditions in the spray boxes and paint flow circulation.
Another disadvantage of the known technical equipment is the difficulty associated with the cleaning thereof when the color of the paint is to be changed.

Adjustable control valve for flow regulation of gas or liquid and use of such valve


To provide flexibility for a guided terminal belt, a rolling member is used to feed a terminal carrier. The rolling member has a contact area to make rolling contact with the carrier. The contact area presses the carrier against a guiding face as the carrier advances in a feeding direction. The feeding is performed when the terminal fitting of the terminal belt is in a released or disengaged state. This makes feeding possible regardless of the type of terminal fitting to be crimped, thus, providing flexibility for the terminal belt to be guided.

1. Field of the Invention
The present invention relates to an improved terminal belt guiding mechanism to be used with a terminal crimping unit, and, more specifically, relates to a terminal belt guiding mechanism which is to be incorporated into a terminal crimping unit.
2. Description of Background Information
It is generally known to have a series of terminal fittings extending perpendicular to a carrier belt. Such a terminal belt is normally fed in a predetermined supply direction by, for example, a guiding mechanism incorporated into a terminal crimping unit.
The conventional guiding mechanism includes a first guide plate that surrounds a contact face that supports the upper or lower surface of the carrier and a guiding face that positions the edge of the carrier. The contact face is perpendicular to the guiding face at all times. The conventional guiding mechanism further includes a guide member that guides the terminal area of the terminal belt by the first guide plate.
The conventional guiding mechanism was disadvantageous because the terminal belt is not flexible. The lack of flexibility is caused by the terminal belt being guided through a space primarily controlled by both a first and a second guide plate.

Terminal belt guiding mechanism to be used with a terminal crimping unit


A holding device for use with a patient during an X-ray procedure includes an elongated arm having a proximal end and a distal end, a handle at the proximal end, and a retainer mounted on the distal end of the elongated arm for retaining something that is to be used adjacent to the patient during the X-ray procedure. An X-ray shield may be mounted on the arm between the retainer and the handle. There may be hinged joints between the retainer and the handle.

When a patient is being X-rayed, the operator tries to avoid exposure to the radiation in order to avoid the long-term effects of repeated radiation exposure. Normally, the operator stands behind the radiation source and is thereby protected. However, there are many situations, especially in pediatric dentistry, in which the operator holds an X-ray sensor in position during the X-ray, which may expose the operator's hand and lower arm to radiation. Similarly, there are situations in which the operator administers a medication to the patient during the X-ray, such as during a barium swallow test, holding a cup to the patient's mouth so the patient can drink a barium-containing compound during the X-ray procedure, which again may expose the operator to radiation.
In normal dental X-ray procedures, the operator positions the X-ray sensor assembly in the patient's mouth in specific positions depending upon whether it is desired to take, for example, horizontal or vertical bitewing X-rays, posterior periapical or anterior periapical X-rays. The patient may bite down on the assembly to hold it in place while the X-ray is being taken, or the operator may position and retain the X-ray sensor assembly in the patients mouth with a retaining device that generally consists of an elongated arm that is provided with means for holding the X-ray sensor assembly so that the operator's hand is off to the side of the patient and not in direct line of the emitted X-rays. However, the known retaining devices are bulky and often not well-received by the patient. Even when the known retaining devices are properly used, the operator's hand may be exposed to substantial scattered radiation.
In some situations, particularly in pediatric dentistry, a portable, hand held X-ray emitter is used to take the patient's X-rays. It is ideal for the operator to stand directly behind the portable hand held X-ray emitter to avoid scattered radiation as much as possible. Both when using a stationary X-ray emitter and when using a hand held X-ray emitter, if the operator manually holds the sensor assembly or some other device in the desired orientation during emission of the X-ray radiation, the operator's hand and lower arm may be subjected to undesirable doses of scattered radiation over time.
Various means are employed to minimize the exposure to radiation. For example, most portable hand held X-ray devices are provided with a radiation shield at or adjacent to the emitter end of the device. However, such shields do not protect the operator's hand and lower arm when the operator holds the X-ray sensor or other device in place in an area exposed to radiation during the X-ray.


An image forming apparatus to form an image on a recording sheet by transferring electrophotographic developer onto the recording sheet is provided. The image forming apparatus includes a heat roller to thermally fix the transferred developer onto the recording sheet, a rotating member to convey rotation force to the heat roller, a bearing to support the rotating member rotatably, a frame in which the bearing is assembled so that the rotating member is supported by the frame through the bearing. The bearing is made of a material having sliding resistance lower than sliding resistance of a material of the frame. The bearing is arranged on an opposite side of the heat roller with respect to the frame and receives the rotating member on the opposite side. The bearing and the frame are assembled to have clearance therebetween.

1. Technical Field
An aspect of the present invention relates to an image forming apparatus capable of electrophotographically forming an image with components having higher heat-resistance and friction-resistance.
2. Related Art
An image forming apparatus is configured with various components including rollers and gears, which rotate about shafts supported by bearings. As the shafts rotate in the bearings, frictional heat is caused, and the bearings may be deformed by the frictional heat.
In order to avoid the heat-deformation, for example, Japanese Patent Provisional Publication No. H08-6470 suggests bearings to receive a rotatable shaft of a gear to rotate a photosensitive drum, which are made of a material having higher heat-resistance than a material to form a cartridge frame. Thus, deformation of the bearings, which may be caused by the frictional heat, can be avoided.


A data storage system is provided that implements a command-push model that reduces latencies. The host system has access to a nonvolatile memory (NVM) device of the memory controller to allow the host system to push commands into a command queue located in the NVM device. The host system completes each IO without the need for intervention from the memory controller, thereby obviating the need for synchronization, or handshaking, between the host system and the memory controller. For write commands, the memory controller does not need to issue a completion interrupt to the host system upon completion of the command because the host system considers the write command completed at the time that the write command is pushed into the queue of the memory controller. The combination of all of these features results in a large reduction in overall latency.

A storage array or disk array is a data storage device that includes multiple hard disk drives (HDDs) or similar persistent storage units. A storage array can allow large amounts of data to be stored in an efficient manner. A server or workstation may be directly attached to the storage array such that the storage array is local to the server or workstation. In cases in which the server or workstation is directly attached to the storage array, the storage array is typically referred to as a direct-attached storage (DAS) system. Alternatively, a server or workstation may be remotely attached to the storage array via a storage array network (SAN). In SAN systems, although the storage array is not local to the server or workstation, the disk drives of the array appear to the operating system (OS) of the server or workstation to be locally attached.
FIG. 1 illustrates a block diagram of a typical data storage system 2 that implements a command-pull model. The system 2 includes a host system 3, a memory controller 4, and a peripheral interconnect (PCI) or PCI Express (PCIe) bus 5. The controller 4 includes a central processing unit (CPU) 6, a memory device 7, and an I/O interface device 8. The I/O interface device 8 is configured to perform data transfer in compliance with known data transfer protocol standards, such as the Serial Attached SCSI (SAS) standard, the Serial Advanced Technology Attachment (SATA) standard, or the Nonvolatile Memory Host Controller Interface Express (NVMe) standard. The I/O interface device 8 controls the transfer of data to and from multiple physical disks (PDs) 9. The memory controller 4 communicates via the PCI bus 5 with a system CPU 11 and a system memory device 12. The system memory device 12 stores software programs for execution by the system CPU 11 and data. A portion of the system memory device 12 is used as a command queue 13.
During a typical write action, the system CPU 11 runs a memory driver software stack 14 that stores commands and data in the command queue 13. When the memory driver 14 stores a command in the command queue 13, it notifies the memory controller 4 that a command is ready to be executed. When the controller CPU 6 is ready to execute a command, it pulls the command, or multiple commands, and the associated data from the system queue 13 via the bus 5 and issues a completion interrupt to the host system 3. When the commands are executed by the memory controller 4, the controller CPU 6 causes the data associated with the commands to be temporarily stored in the controller memory device 7 and then subsequently written to one or more of the PDs 9 via the I/O interface device 8.
Historically, the performance of an HDD-based system of the type shown in FIG. 1 has been measured in terms of input/output (IO) per second (IOPS), and in some cases, megabytes per second (MB/s). Latency of such a storage system is typically given as: Latency_Overall=Latency_SW_Stack+Latency_Controller+Latency_HDD=1/IOPS, where Latency_Overall is the overall latency of the system, Latency_SW_Stack is the latency associated with the memory driver 14, Latency_Controller is the latency associated with the memory controller 4, and Latency_HDD is the latency associated with the PDs 9. Latency_SW_Stack is typically on the order of microseconds (10−6 seconds). Likewise, Latency_Controller is typically on the order of tens of microseconds. However, Latency_HDD is typically on the order of milliseconds (10−3 seconds) or tens of milliseconds. Approximately 99% of overall latency is due to extremely slow mechanical parts of the HDDs. Therefore, for practical purposes, Latency_SW_Stack and Latency_Controller can be ignored when determining system performance. In other words, system performance can be estimated as being equal to Latency_HDD.
Recently, there has been a transition from using magnetic HDDs as the PDs 9 to using solid state drives (SSDs), or a combination of SSDs and HDDs, as the PDs 9. In the industry, the use of SSD-based solutions is viewed as an evolution of HDD-based solutions. However, SSD-based solutions are approximately one hundred times faster and consume much less power than HDD-based solutions. This view of SSD-based solutions has led the industry to continue using the pre-existent, above-described pull methodology in SSD-based solutions to pull commands from the command queue into the memory controller. Also, because SSD-based solutions have been viewed in the industry as merely an evolution of HDD-based solutions, TOPS have been used as the performance metric for measuring system performance in storage systems that implement SSD-based solutions.
However, the differences between SSD-based solutions and HDD-based solutions are much greater than it appears, and traditional metrics should not be used to measure the performance of systems that implement SSD-based solutions. In a system that implements an SSD-based solution, the overall latency of the storage system is given as: Latency_Overall=Latency_SW_Stack+Latency_Controller+Latency_SSD=1/IOPS, where Latency_SW_Stack is the latency associated with the memory driver 14, Latency_Controller is the latency associated with the memory controller 4, and Latency_SSD is the latency associated with the SSDs that are used as the PDs 9. Unlike the latency of the HDDs, the latency of the SSDs is on the order of tens to hundreds of microseconds, e.g., generally in the range of 100 to 300 microseconds, and the latencies associated with the memory driver 14 and the memory controller 4 add much more than that to the overall latency. Therefore, in calculating the overall latency of the storage system that implements an SSD-based solution, Latency_SW_Stack and Latency_Controller should no longer be ignored.
The command-pull approach requires quite a bit of interaction between the memory driver 14 and the memory controller 4. This is a convenient approach in HDD-based systems in that it allows the fast operating system (OS) side of the host system 3 to be almost completely independent of the slower HDD-based controller side so that the OS side can pile up as many commands as possible in the queue 13 to provide greater queue depth (QD), which is very desirable and common in HDD-based solutions. The memory controller 4 can then pull the commands from the queue 13 at its own pace. While this method is very convenient in HDD-based solutions, it adds a large amount of extra latency due to the synchronization that is required between the memory controller 4 and the host system 3, and due to the fact that the memory controller 4 may pick up commands at times much later than when they were issued. In addition, if there is lot of work to be done by the memory controller 4, as is often the case, all of the command processing must compete with the rest of workload of the memory controller 4, which adds more latency to the overall latency.
The above-described command-pull model works very well for HDD-based solutions where adding 50 to 500 microseconds to a command that typically may take about 10,000 microseconds to complete is negligible given the other advantages that the method provides. However, the command-pull model does not produce acceptable results when used in a storage system that implements an SSD-based solution where the access time may be as low as 100 microseconds, or, in cases in which a dynamic random access memory (DRAM) write back (WB) buffer is used in the memory controller 4, as low as 1 to 5 microseconds.
Nevertheless, as indicated above, the overall latency of storage systems that implement SSD-based solutions is still being estimated as being equal to Latency_SSD, while leaving Latency_SW_Stack and Latency_Controller out of the estimation. For this reason, attempts at reducing the overall latency of storage systems that implement SSD-based solutions have focused primarily on reducing Latency_SSD rather than on reducing Latency_SW_Stack or Latency_Controller.
A need exists for a storage system that implements an SSD-based solution and that significantly reduces overall latency by significantly reducing one or both of Latency_SW_Stack and Latency_Controller.

Method and system for reducing write latency in a data storage system by using a command-push model

Avago Technologies General IP (Singapore) Pte. Ltd.


An image segmentation system to perform operations that include causing display of an image within a graphical user interface of a client device, receive a set of user inputs that identify portions of a background and foreground of the image, identify a boundary of an object depicted within the image based on the set of user inputs, crop the object from the image based on the boundary, and generate a media item based on the cropped object, wherein properties of the media object, such as a size and a shape, are based on the boundary of the object.

Various multimedia editing tools to enable users to select objects or layers in images are among the most useful and widely used tools available for editors. Such applications generally require users to provide multiple, often painstakingly precise and detailed, inputs to define a border of an object within an image. As a result, such tools are not particularly user friendly for beginners, or users that may be operating devices with limited display screens.


A device for feeding poultry comprises a substantially dish-shaped pan, above which a feed drop tube is disposed, which drop tube opens out above a central part of the pan. At least one grill with bars extends between the feed drop tube and the pan. Provision is made for a second grill with bars, which second grill is fitted adjacent to the first grill. The first and the second grill are movable relative to each other.

The invention relates to a device for feeding poultry, comprising a substantially dish-shaped pan, above which a feed drop tube is disposed, which drop tube opens out above a central part of the pan, while at least one grill with bars extends between the feed drop tube and the pan.


To make it possible to accurately grasp an exposure state even in the case where noise is included in captured image data. An input image data acquisition unit configured to acquire input image data including a chart, a noise reduction unit configured to perform noise reduction on the input image data, and a histogram generation unit configured to generate a histogram of luminance of the input image data based on noise reduced image data are included, and the noise reduction unit performs noise reduction on the chart area of the input image data in a degree greater than that in which noise reduction is performed on an area other than the chart.

Field of the Invention
The present invention relates to visualization of image information for checking an exposure state of captured image data.
Description of the Related Art
As one method of visualizing information on exposure of captured image data, the histogram display technique is known as a conventional technique. The histogram display technique makes it possible to visually check a distribution state of luminance values in captured image data by plotting the luminance values that occur in the captured image data on a two-dimensional plane on which, for example, the horizontal axis represents the luminance value and the vertical axis represents the frequency.
Japanese Patent Laid-Open No. 2008-172732 has disclosed a method of displaying a histogram in a size in accordance with a detected area by detecting the area of a main subject of interest in image data in order to determine whether the exposure of the main subject of interest is appropriate.
However, captured image data generally includes noise even though noise reduction processing is performed on the captured image data. Because of this, by the method described in Patent document 1, the generated histogram is affected by noise and there is a case where it is difficult to check the exposure state.
In view of the above, an object of the present invention is to generate a histogram for accurately grasping an exposure state of captured image data.

Image processing apparatus, image processing method, and storage medium for checking an exposure state of captured image data


A wireless power feeding control apparatus for a vehicle includes a positioning unit and an examination unit. The vehicle is provided with a power receiving coil that wirelessly receives electrical power from a power transmitting coil of a power transmission facility, a parking lock mechanism, and a parking lock sensor that outputs an electrical signal corresponding to a locked state of a wheel established by the parking lock mechanism. The positioning unit positions the power transmitting coil or assists in positioning the power transmitting coil on the basis of a quantity of electricity generated by the power receiving coil receiving a magnetic field from the power transmitting coil subjected to weak excitation weaker than excitation during electrical power transmission. The examination unit checks the locked state of the wheel after the weak excitation is stopped and before the electrical power transmission is started.

The disclosure relates to a wireless power feeding control apparatus and a wireless charge system that wirelessly feed electrical power from a power transmission facility to a vehicle including a power receiving coil.
There is a known technique for wirelessly feeding electrical power from a power transmitting coil of a power transmission facility to a power receiving coil of a power reception facility. For example, the power transmitting coil and the power receiving coil are positioned to face each other, and electrical power is fed from the power transmitting coil to the power receiving coil by electromagnetic action. Efficient feeding of electrical power is achieved by arranging the power receiving coil at an appropriate position relative to the power transmitting coil. An application of such a wireless power feeding technique to a vehicle is being studied. The application of such a technique requires the vehicle to be stopped in a stationary state during power feeding so as to prevent the power receiving coil from being displaced from the appropriate position.

Wireless power feeding control apparatus for vehicle and wireless charge system for vehicle


In a method of forming a metal wiring line, a first insulating film is formed directly or indirectly on a semiconductor substrate. A second insulating film is formed on the first insulating film. A wiring line groove is formed to pass through the second insulating film to an inside of the first insulating film. A conductive film is formed to fill the wiring line groove and to cover the second insulating film. The conductive film and the second insulating film are removed by a first CMP polishing process, using the first insulating film as a stopper film, until the first insulating film is exposed.

1. Field of the Invention
The present invention relates to a method of forming a metal wiring line of a semiconductor device.
2. Description of the Related Art
With the enlargement of a chip size and the miniaturization of a minimum processing dimension, an interval between wiring lines, the sectional area of the wiring line decrease, and the length of the wiring line increases. In association with them, the capacitance and resistance of the wiring line are sharply increased, resulting in a larger propagation delay of a signal.
In order to reduce the wiring line capacitance, it is tried to decrease the dielectric constant of an interlayer insulating film. An insulating material with a small dielectric constant is typically used in order to decrease the dielectric constant to a small value. For example, a method is known of decreasing the relative dielectric constant to about 3 by doping impurities into a conventional inorganic silicon dioxide film with the relative dielectric constant of 4.2. Otherwise, a method is known of using an organic polymer with the relative dielectric constant of 2 to 3, as the insulating film. This dielectric constant value is lower than that of the silicon dioxide film.
As a method of decreasing the wiring line resistance, a method is known of replacing aluminum with the specific resistance of 3.0 Ωcm used in the conventional wiring line by copper with the specific resistance of 1.7 Ωcm. Also, since an average wiring line length is inversely proportional to the number of wiring layers, the wiring line may be formed as a multiple-layer. Also, the multiple-layer wiring line is formed to have a wider width. In this case, of the wiring line, the upper layer having the smaller resistance is used for global wiring, and the lower layer is used for local wiring in a highly integrated circuit. This structure can decrease the wiring line resistance while reducing the chip area. As a result, the employment of those methods makes it the propagation delay to be largely reduced.
However, the conventional multiple-layer wiring technique has the following problems. That is, the problems will be described with reference to FIGS. 1A to 1C. FIGS. 1A to 1C are cross section views showing a process for forming a damascene wiring line in a semiconductor device.
The semiconductor device shown in FIGS. 1A to 1C includes a substrate 101, an interlayer insulating film 102, a hard mask 103, a barrier film 104, a metal wiring line film 105 and a wiring line groove 106.
The substrate 101 is a silicon substrate on which semiconductor elements, wiring lines and the like are formed.
The interlayer insulating film 102 is an insulating film formed of an organic material such as a polymer of a hydrocarbon system. The dielectric constant of the interlayer insulating film 102 is small, differently from an inorganic insulating film such as a silicon dioxide film. For example, the interlayer insulating film 102 has the relative dielectric constant of 2.0 to 3.0.
The hard mask 103 is an insulating film formed of an inorganic material such as silicon dioxide. However, the hard mask 103 may be formed of silicon dioxide including hydrogen group or methyl group such as silicon nitride (SiN), silicon carbide (SiC), silicon carbide nitride (SiCN), MSQ (Methyl Silsesquioxane) and HSQ (Hydrogen Silsesquioxane). The structure of the hard mask is not limited to a single layer. The hard mask 103 may has a lamination structure in which a plurality of films are laminated. The hard mask 103 is essential to protect the interlayer insulating film 102 in a photolithography process for forming a wiring line groove. Also, the hard mask 103 has a stopper function when the barrier film 104 is polished by using a chemical mechanical polishing (CMP) method.
The barrier film 104 is a thin metal film. The barrier film 104 protects the metal wiring line film 105 from being diffused into the interlayer insulating film 102. For example, the barrier film 104 is formed of titanium nitride and tantalum.
The metal wiring line film 105 is formed of a metal with a small specific resistance. The metal wiring line film 105 is formed in the wiring line groove formed in the insulating film, and is used for a damascene wiring line. For example, the metal wiring line film 105 is formed of copper.
Next, the manufacturing process will be described below.
In FIG. 1A, the interlayer insulating film 102 and the hard mask 103 are formed on the substrate 101 in order. Then, wiring line grooves 106 are formed by the photolithography process. After that, the barrier film 104 and the metal wiring line film 105 are deposited.
In FIG. 1B, the metal wiring line film 105 is polished by a first CMP polishing process in which the barrier film 104 is used as a stopper film. Consequently, an upper portion of the metal wiring line film 105 located above the barrier film 104 is removed.
In FIG. 1C, the barrier film 104 is polished by a second CMP polishing process in which the hard mask 103 is used as a stopper film. Consequently, the barrier film 104 and an upper portion of the metal wiring line films 105 located above the hard mask 103 are removed.
However, as shown in FIGS. 1A to 1C on the left sides, in a portion in which the wiring lines are dense, a rate of a total area of the exposed metal wiring line films 105 is equal to or greater than that of the exposed hard mask 103. For this reason, when the barrier film 104 is polished in the second polishing process, the hard mask 103 is excessively polished and thinned around the exposed portion of the metal wiring line films 105. On the other hand, such phenomenon is never caused in the right side portion of FIGS. 1A to 1C. That is, the hard mask 103 remains in its original state. Thus, since the cross section area of the wiring lines are different depending on a position, the pattern dependency of the wiring line resistance becomes larger.
Also, since the polishing result of the hard mask 103 is different depending on the position, many concave and convex portions are induced on the surface of the substrate. When a multiple-layer wiring line is to be formed, concave and convex portions become larger in the upper layer if a step difference due to the concave and convex portions are induced for each layer. In this case, because of a focal depth in an exposing process, it is difficult to form the desirable film pattern. Hence, a CMP-polishing process of the interlayer insulating film is required in order to solve the step difference.
In addition, in the conventional technique, the hard mask 103 remains in its original state even after the CMP polishing process. The hard mask 103 is typically an inorganic insulating film, and the dielectric constant of the hard mask 103 is larger than that of the interlayer insulating film 102. Thus, the wiring line capacitance increases due to the difference in the dielectric constant. The increase in the wiring line capacitance leads to the increase in the propagation delay. Hence, this has a severe influence on the improvement of an integration degree.
In conjunction with the above-mentioned description, Japanese Laid Open Patent Application (JP-A-Heisei 11-274122) discloses a semiconductor device and a method of manufacturing the same. This reference will be described below with reference to FIGS. 1A to 1C. This reference uses an organic SOG film as the hard mask 103. Because the dielectric constant of the organic SOG film is smaller than that of silicon dioxide film, a parasitic capacitance between wiring lines can be reduced. Also, in the CMP polishing process using aluminum abrasive particles, the hard mask 103 functions as an effective stopper in the second CMP polishing process of the barrier film 104 in FIG. 1C. However, the dielectric constant of the organic SOG film is higher than that of the interlayer insulating film 102. Also, the organic SOG film is not removed after the second CMP polishing process.
Also, Japanese Laid Open Patent Application (JP-P2000-223490A) discloses a method of manufacturing a semiconductor device. This reference will be described below with reference to FIGS. 1A to 1C. In this reference, the hard mask 103 is removed by plasma etching after the second CMP polishing process of the barrier film 104 in FIG. 1C. Then, an entire copper wiring is covered by an insulating film with a low dielectric constant formed of the same material as the interlayer insulating film 102. Through the above-mentioned processes, the parasitic capacitance between the wiring lines can be largely reduces. However, the hard mask 103 is removed by a plasma etching, so that a tact time increases extremely, and the throughput decreases extremely. Also, there may be a possibility of increase in a cost of a processing apparatus.

Method of forming metal wiring line including using a first insulating film as a stopper film


The present invention relates to a process for preparing isobutene-cyclodiene copolymers having a number-average molecular weight of at least 100,000 and an unsaturation of 1.about.30% by mol, characterized in that polymerization is carried out without gelation by reacting 75.about.99.5% by weight of an isobutene and 0.5.about.25% by weight of a cyclodiene or a mixture of cyclodiene as reaction materials, in a polar reaction solvent of 1.about.10 times by weight with respect to the reaction materials, wherein a catalyst solution of 0.02.about.2% by weight in the polar solvent is used in the amount of 0.2.about.2 times by weight with respect to the reaction materials, at a reaction temperature of -100.degree..about.-85.degree. C., thereby obtaining a copolymer, and then removing the residual catalyst activity at a temperature of -100.degree..about.-25.degree. C.

Heretofore, the process for producing isobutene-cyclodiene copolymers has been well known. In order to appreciate the commercial utility of the copolymer as a rubber, the copolymer should possess appropriate mechanical strength and strong adhesive strength as well as a high number-average molecular weight and a high degree of unsaturation.
It is known that as the number-average molecular weight of the copolymer increases, the copolymer's tensile strength tends to increase, and as the number of unsaturation bond of the copolymer increases, the copolymer's adhesive strength with respect to another rubber tends to increase. In other words, when the copolymer is vulcanized together with highly unsaturated rubber such as natural rubber etc., the adhesive strength of the copolymer increases as the number of unsaturation bond increases and the crosslinking reaction increases and the similarity in crosslinking behavior will also increase.
Isobutene-isoprene copolymer ("butyl rubber") is well known as a representative example of existing isobutene-diene copolymer. But butyl rubber has less than 2.5 mol % of isoprene content as comonomer, which has double bond; thus, it has low number of crosslinking sites which can bond with other rubber. Also its crosslinking reaction behavior is different from the highly unsaturated rubber. All of the above for example, results in its weak adhesive strength which decreases further when exposed to external shock, vibration etc. As a method of improving adhesive strength of butyl rubber, it has been proposed to incorporate halogen compounds into butyl rubber, such as chorine and bromine which can promote the crosslinking reaction, and to increase isoprene content. But in case of the former, investment on additional equipment is required for halogenation process of the resulting polymer after the production of the polymer. In case of the latter, although improved adhesive strength is obtained, there exists the problem of decreasing gas barrier property, which is one of the most desirable properties of butyl rubber. Moreover, U.S. Pat. Nos. 3,356,661, 3,165,503 and 3,466,268 etc. reported that the higher the content of isoprene, the lower the number-average molecular weight and as a result, the copolymer of little utility value is produced. Also it is known that the structure and quantity of the unsaturated bond influence the resistance of rubber against aging. In case of butyl rubber, the degree of unsaturation is lower than that of natural rubber, so it is somewhat stable against aging, but because the site of unsaturation is in the polymer backbone, this polymer is subject to ozone cleavage, thus the aging of rubber cannot be avoided.
On the other hand, in case of isobutene-cyclodiene copolymer which is similar to butyl rubber, improvement in adhesive strength is obtained as well as excellent gas barrier property even at high degree of unsaturation. Even if the unsaturation bond is attacked and cyclic structure is severed, the copolymer backbone will be highly resistant to ozone attack because the diene compound having cyclic structure is copolymerized and the unsaturation bond does not exist on the backbone. Thus the resistance of rubber against aging is excellent and its improved characteristics makes it an excellent tire material. Even though the above-mentioned isobutene-cyclodiene copolymer solved the problem associated with existing butyl rubber and are considered excellent material for tires, the copolymer faces another problem in that it is difficult to maintain the comonomer in high purity because the comonomer is unstable against heat. Also as the degree of unsaturation increases, the gel formation increases and the molecular weight decreases. These problems in preparation have prevented said polymer from being producted for commercial use.
Among processes for preparing isobutene-cyclopentadiene copolymer of the prior slurry polymerization methods, U.S. Pat. No. 2,356,128 produced only copolymers of low molecular weight. U.S. Pat. No. 2,577,822 disclosed a process for preparing terpolymer having high molecular weight which used a divinylbenzene to give crosslinking. U.S. Pat. No. 3,080,337 disclosed a process for preparing isobutene-cyclopentadiene-isoprene terpolymer without gelation and U.S. Pat. No. 3,239,495 disclosed a process for preparing terpolymer of high molecular weight using divinylbenzene.
However, these slurry processes produce a polymer of low molecular weight due to cyclopentadiene dimer (DCPD) and water which were included in their reaction materials, or a polymer of poor physical properties which cannot be used as a commercial product due to the addition of divinylbenzene which increased the crosslinking of the polymer produced.
Although isobutene-cyclopentadiene copolymers having a useful degree of unsaturation and molecular weight can be produced by effectively removing water and dicyclopentadiene from the reaction materials, problems such as gelation and fouling were experienced as the degree of unsaturation and molecular weight of the copolymer increased. Particularly, in a slurry batch polymerization process, it was impossible to produce a polymer having a homogeneous degree of unsaturation because in the initial stage of the polymerization reaction, when cyclopentadiene having a high reaction rate was used, a polymer having a high degree of unsaturation was obtained and gelation was observed.
By conducting a slurry continuous polymerization together with the removal of impurities which would decrease the molecular weight of copolymer, isobutene-cyclopentadiene copolymer without gelation can be produced. However, it was difficult to prevent reactor fouling in a slurry continuous reaction. The technique to extend continuous operation time by preventing fouling is an important index to measure the economical performance of a slurry process.
The problem with gel formation and molecular weight decrease can be solved by the well known solution process, however, it is impossible to obtain high conversion because the viscosity of the reactants increases sharply when the polymerization proceed. Also, in order to obtain high molecular weight of the polymer, the production cost together with the investment cost will increase since the temperature has to be maintained at a level of -120.degree. C.
A number of examples of process for producing isobutene-cyclodiene copolymers by solution process are shown below:
In U.S. Pat. No. 3,808,177, an isobutene-cydopentadiene copolymer having a number-average molecular weight of at least 120,000 and a degree of unsaturation of 8.about.30 mol % at no more than 10% of conversion, was prepared by carrying out a polymerization reaction using aluminium chloride dissolved in methyl chloride as catalyst and aliphatic saturated hydrocarbon with 5.about.10 carbon atoms as reaction solvent at polymerization temperature of -120.degree. C.
In U.S. Pat. No. 3,856,763, an isobutene-cyclopentadiene copolymer having a number-average molecular weight of at least 120,000 and a degree of unsaturation of 8.about.40 mol % at no more than 10% of conversion, was prepared using the chioro or bromo allyl aluminium dihalide with alkyl groups of 1.about.4 carbon atoms as catalyst at polymerization temperature of -120.degree. C.
In U.S. Pat. No. 4,031,360, an isobutene-cyclopentadiene copolymer having a number-average molecular weight of at least 90,000 and a degree of unsaturation of 8.about.35 mol % at no more than 10% of conversion, was prepared by carrying out a solution polymerization method using aluminium halide or alkyl aluminium dihalide as catalyst at polymerization temperature of -120.degree. C.
In U.S. Pat. No. 4,139,695, an isobutene-methylcyclopentadiene copolymer having a number-average molecular weight of at least 120,000 and a degree of unsaturation of 8.about.30 mol % at no more than 5% of conversion, was prepared using alkyl aluminium dichloride as catalyst and methylcyclohexane as reaction solvent at polymerization temperature of -120.degree. C.
Even though an isobutene-cyclodiene copolymer, including cyclopentadiene of which the number-average molecular weight and the degree of unsaturation are high and gel content is low, can be prepared by the solution process, this solution process has several problems as shown below.
In solution process, since the produced copolymer is dissolved in the reaction solvent, the viscosity of the solution increases rapidly as the reaction proceeds, so that the homogeneous mixing of the solution is impossible, and a large amount of power is used for stirring the solution. Also, since the viscosity of the solution increases, it becomes difficult for the solution which serves as a medium for removing reaction heat to transfer the heat to refrigerant and to control the reaction temperature. In particular, a temperature gradient inside the reactor occurs by local temperature increases, so that it is difficult to prepare polymers having homogeneous physical property. Therefore, there is a high risk of producing low quality products.
For preparing polymers having a number-average molecular weight of at least 100,000, the increase of viscosity becomes a bigger problem since the polymerization must be carried out at a extremely low temperature of -120.degree. C. compared to that of slurry process. Further, in order to maintain the low temperature, very large cooling capacity is required, and the amount of refrigerant used must be increased, resulting in an increase of the production cost.
Also, to keep the solution in homogeneous phase at lower polymerization temperature, the required amount of reaction solvent becomes larger; however, the problem of producing lower molecular weight polymers becomes more severe with the increase of the amount of solvent used.
Therefore, in order to overcome the above mentioned problems, the conversion of reaction must be kept as low as 10%. However, in this case, due to the rapid increase of amounts of reactant and solvent which are recycled, the distillation unit and moisture purification unit would have to be enlarged, resulting in increase of the production cost. Further, when conversion of reaction is maintained at a low level, there is a burden to separate and recycle the comonomer since cyclopentadiene does not completely react at low conversion. And, since the reaction solvent is not readily volatilized, high temperature is required for degassing the residual solvent, impairing the double bond in the produced isobutene-cyclodiene copolymer and deteriorating the copolymer's physical property.

Process for preparing isobutene cyclopentadiene-methylcyclopentadiene terpolymers


Reference generator embodiments are provided with low output impedances to enhance reference stability in the presence of varying loads. The generators are structured to provide these impedances in an efficient manner (i.e., with low supply currents) and also to provide both sink and source currents to better handle large transient current demands. The generators also include cascode structures that facilitate operation with low values of a supply voltage and that provide a low sensitivity to variations in this supply voltage. The embodiments are especially suited for use in signal converter systems.

1. Field of the Invention
The present invention relates generally to generators of referenced signals and applications thereof.
2. Description of the Related Art
The accuracy of many electronic systems is degraded if reference generators cannot efficiently supply reference signals that are stable under various operational conditions which include rapidly varying load impedances, large transient current demands, and varying supply voltages.
An exemplary reference generator application is for use in a pipelined analog-to-digital converter system. Such systems are configured with successive converter stages which each convert an analog input signal to respective digital bits of a final digital code that corresponds to the analog input signal. Except for a final converter stage, each converter stage also passes a residue signal to a succeeding stage for further conversion processing.
The residue signal is the difference between the analog signal presented to the stage and the analog equivalent of this stage's respective digital bits. Errors in generation of the residue signal cannot be corrected and, accordingly, they contribute directly to errors in the corresponding digital code.
The residue signal is often generated in switched-capacitor versions of a multiplying digital-to-analog converter (MDAC). In these MDACs, capacitors are switched in a first portion of each sample period to receive a charge from the residue signal of the preceding converter stage and switched in a second portion of each sample period to transfer this charge to an output capacitor. These charging and transferring processes are generally accomplished with the aid of reference signals from a reference generator and the accuracy of these processes is dependent upon the ability of the generator to maintain the accuracy of its reference signals in the presence of various operational conditions.

Reference generators for enhanced signal converter accuracy


A frequency divider or dual module prescaler having a division factor switchable between 1/N and 1/(N+1) with an input signal frequency of approximately 1 GHz. The divider includes only one input flip-flop to process the input signal and an intermediate signal having half the frequency as supplied to a divider expansion either directly, or in inverted.

The present invention generally relates to frequency divider circuits. In particular, the invention relates to what are referred to as "dual module prescalers" such as are employed in frequency synthesizers in mobile telephone communication systems. Such frequency dividers exhibit division factors switchable between 1/N and 1/(N+1), where N typically is a number such as 64 or 128. These frequency dividers work with frequencies on the order of magnitude of 1 GHz and are a component part of every GSM or DECT telephone. Due to the use of battery supplies in such devices, low power consumption is of rather critical significance.
Examples of the use and structure of such prescalers are provided in the IEEE Journal of Solid-State Circuits, Vol. 29, No. 10, October 1994, pages 1206 through 1211, and as Volume 27, No. 12, December 1992, pages 1794 through 1798. The disclosures of these articles are fully incorporated herein by reference. In these disclosed devices, further asynchronous divider expansion or expander stages respectively follow a synchronous 1:4/5 divider (also referred to as a divide by 4/5 or .div.4/5).

Frequency divider with low power consumption