The present invention relates to a therapeutic polypeptide and methods for its creation and use for modulating an immune response in a host organism in need thereof. In particular, the invention relates to the administration to an organism in need thereof, of an effective amount of a pre-coupled polypeptide complex comprising a lymphokine polypeptide portion, for example IL-15 (SEQ ID NO: 5, 6), IL-2 (SEQ ID NO: 10, 12) or combinations of both, and an interleukin receptor polypeptide portion, for example IL-15Ra (SEQ ID NO: 7, 8), IL-2Ra (SEQ ID NO: 9, 11) or combinations of both, for augmenting the immune system in, for example, cancer, SCID, AIDS, or vaccination; or inhibiting the immune system in, for example, rheumatoid arthritis, or Lupus. The therapeutic complex of the invention surprisingly demonstrates increased half-life, and efficacy in vivo.

Lymphocytes are a type of white blood cell involved in immune system regulation. There are two broad categories of lymphocytes, namely T cells and B cells. T-cells are responsible for cell-mediated immunity whereas B-cells are responsible for humoral immunity (relating to antibodies). T-cells are named such because these lymphocytes mature in the thymus and B-cells mature in bone marrow. Lymphocytes are much more common in the lymphatic system, and include B cells, T cells, killer T-cells, and natural killer cells. B cells make antibodies that bind to pathogens to enable their destruction. CD4+ (helper) T cells co-ordinate the immune response (they are what become defective in an HIV infection). CD8+ (cytotoxic) T cells and Natural Killer (NK) cells are able to kill cells of the body that are infected by a virus or display an antigenic sequence.
Natural killer cells are CD56(+)CD3(−) large granular lymphocytes that constitute a key component of the human innate immune response. In addition to their potent cytolytic activity, NK cells express a host of immunoregulatory cytokines and chemokines that play a crucial role in pathogen clearance. Furthermore, interactions between NK and other immune cells are implicated in triggering the adaptive, or antigen-specific, immune response.
The interactions between immune and inflammatory cells are mediated in large part by cytokine proteins, for example, lymphokines such as interleukins (IL), which are able to promote cell growth, differentiation, and functional activation. Currently, at least twenty-three interleukins and their various splice variants have been described. Some of these cytokines mediate distinct biological effects but many have overlapping activities. The understanding of interleukin structure and function has led to new and important insights into the fundamental biology of immunity and inflammation. For example, Interleukin-2 (IL-2) and IL-15 are two distinct cytokines with partially overlapping properties that are implicated in the development, homeostasis, and function of T cells and NK cells.
IL-2, formerly referred to as T-cell growth factor, is a powerful immunoregulatory lymphokine that is produced by antigen-activated T cells. It is produced by mature T lymphocytes on stimulation but also constitutively by certain T-cell lymphoma cell lines. IL-2 is useful in the study of the molecular nature of T-cell differentiation, and because it augments natural killer cell activity, it can be useful in modulating the immune response to cancers, viral or bacterial infections. Also, IL-2 can act as a growth hormone for both B and T lymphocytes, and stimulates clonal expansion and maturation of these lymphocytes. IL-2 binds to its receptor (R) complex comprised of IL-2R alpha ("IL-2Ra"), IL-2R beta ("IL-2Rb"), and -gamma ("gC") chains, and exerts its effect via second messengers, mainly tyrosine kinases, which ultimately stimulate gene expression.
The heterotrimerization of the receptor chains leads to high affinity binding for IL-2. The functional importance of IL-2Ra in hematopoietic cell systems is well known. However, the potential role that IL-2Ra plays in tumorigenesis is still not fully elucidated. IL-2Ra expression has been found in many types of cancers, including leukemia, lymphoma, lung, breast, head-and-neck, and prostate. Also, high expression of IL-2Ra in tumors correlates with a poor prognosis for the patient.
IL-15 is a member of the four alpha-helix bundle family of lymphokines and its mRNA can be detected in a wide variety of tissues of both non-hematopoietic, and hematopoietic lineages but it is not produced by T cells. IL-15 is difficult to detect at the protein level in vivo perhaps due to short protein half-life and tight transcriptional and translational control. IL-15 is a soluble protein made by many cells in the body which play an important role in the development of the immune system. IL-15 was simultaneously discovered in an adult T-cell leukemia cell line and a simian kidney epithelial cell line as a 14 kDa-16 kDa protein able to stimulate cytotoxic T cell lymphocyte cell line (CTLL) and peripheral blood T cell proliferation, and to induce peripheral blood mononuclear cells to exhibit effector function.
IL-15 plays a multifaceted role in development and control of the immune system. More specifically, IL-15 influences the function, development, survival, and proliferation of CD8+ T cells, NK cells, killer T cells, B cells, intestinal intraepithelial lymphocytes (IEL) and antigen-presenting cells (APC). It has been demonstrated that both IL-15−/−, and IL-15Ra−/− transgenic mice lack peripheral NK and killer T cell populations, certain IEL subsets, and most memory phenotype CD8+ T cells. In addition, while antigen-specific memory CD8+ T cells can develop in response to pathogens in both types of knockout mice, the resulting memory CD8+ T cell pool undergoes dramatic erosion over time. Suggesting a crucial role for IL-15 in mediating long term memory CD8+ T cell proliferation and survival.
The IL-15 receptor (R) consists of three polypeptides, the type-specific IL-15R alpha ("IL-15Ra"), the IL-2/IL-15Rbeta ("IL-2Rb"), and the common gamma chain ("gC," which is shared by multiple cytokine receptors). The high affinity IL-15Ra chain (Kd≈10−11M) is thought to form a heterotrimeric complex with the shared IL-2Rb, and the gC. Similar to IL-15, IL-15Ra is thought to be expressed by a wide variety of cell types but not necessarily in conjunction with IL-2Rb and gC. Although the IL-15Ra, the IL-2Rb, and the gC chains are believed to associate as a heterotrimeric receptor, whether this is the physiologically relevant form of the IL-15 receptor remains a matter of speculation. For example, the IL-15Ra chain does not co-precipitate with the IL-2Rb/gC in the presence of IL-15.
Moreover, unlike the IL-2Ra chain, the IL-15Ra chain apparently mediates signal transduction. IL-15Ra is a 58-60 kDa protein that shares structural similarities to the IL-2Ra protein. IL-15Ra and IL-2Ra genes also share similar intron-exon organization and are closely linked on human chromosome 10p14-p15. Human IL-15Ra shares about 45% amino acid (aa) homology with the mouse form of the receptor. Eight isoforms of IL-15Ra mRNA have been identified resulting from alternative splicing events involving different exons. The exclusion of exon 2 (ΔExon2) results in an IL-15Ra isoform that does not bind IL-15. Human IL-15Ra-ΔExon3 cDNA encodes a 267 amino acid (aa) protein that contains a 30 aa signal sequence, a 175 aa extracellular region containing one N-linked glycosylation site, a 21 aa transmembrane domain and a 41 aa cytoplasmic tail.
IL-15 signaling can occur through the heterotrimeric complex of IL-15Ra, IL-2Rb and gC; through the heterodimeric complex of IL-2Rb and gC; or through a novel 60-65 kDa IL-15RX subunit found on mast cells. (Anderson, D. M. et al., 1995, J. Biol. Chem. 270:29862-29869; Waldemann, T. A. and Y. Tagaya, 1999, Ann. Rev. Immunol., 17:19-49; Dubois, S. et al., 1999, J. Biol. Chem. 274:26978-26984). Recently, the binding of IL-15 to IL-15Ra has been reported to antagonize the TNF-alpha-mediated apoptosis in fibroblasts by competing with TNFRI for TRAF2 binding (Bulfone-Paus, S. et al., 1999, FASEB 13:1575-1585).
Given the known effects of IL-15 on the immune system, a number of groups have proposed targeting IL-15, to manipulate the immune system for the hosts benefit. While IL-15 administration has been employed to bolster immune responses or augment immune system reconstitution, blockade of IL-15 activity can inhibit autoimmune responses. For example, administration of an IL-15-activity blocking mutant IL-15-Fc protein or a soluble form of the IL-15Ra has therapeutic potential in a mouse model of arthritis and allograft survival.
Conversely, IL-15 (protein or DNA-expression vector) administered as an adjuvant during vaccination or infection augments CD8+ T cell immunity, and IL-15 treatment can enhance protection of mice from lethal doses of Mycobacterium tuberculosis and Escherichia coli. Furthermore, IL-15 therapy stimulates anti-HIV immunity and increases survival of CD4+ and CD8+ lymphocytes from HIV-infected patients in vitro. IL-15 can also accelerate immune reconstitution after bone marrow transplant. Several groups have found that IL-15 therapy, in conjunction with chemotherapy, Toll-like receptor agonists, or adoptive transfer of tumor reactive CD8+ T cells, can result in increased survival or complete tumor regression in mouse tumor models, in contrast to each therapy alone. Thus, manipulation of IL-15 activity has potential as a therapeutic modality in a number of clinical situations.
IL-15 is currently being used in many studies in which augmentation of the immune response is desirable. These include increasing the efficacy of vaccines against tumors and infections as well as augmenting the ability of the body to remove cancers in the absence of overt vaccination. In addition, IL-15 may aid in regenerating the immune system following bone marrow transplant or in AIDS. However, the half-life of IL-15 in vivo is very short (minutes to 1 hour or so) and this is one reason for poor efficacy. At present the only way to obtain any effect of IL-15 activity is by using large doses, and IL-15 alone is not always effective. Researches have attempted to increase the half-life of IL-15 using molecular modifications but these have generally been ineffective. For example, PEGylation (a common technique to increase protein half-life) of IL-15 increases the half-life but destroys the majority of the activity of the cytokine, in fact, PEG-IL-15 is an antagonist of IL-15 activity.
Therefore, there exists an unmet need to provide a suitable therapeutic form of IL-15 that demonstrates a longer half-life, and a greater efficacy at lower dosages when administered to an organism in need thereof for purposes of modulating or enhancing immunity. Such a therapeutic would allow for the administration of less cytokine while simultaneously providing for the augmentation of the hosts immune system beyond the effects of IL-15 alone.
Our studies showed that the IL-15Ra acts to "transpresent" IL-15 to opposing cells expressing the IL-2/15Rb/gC complex without a requirement for IL-15Ra expression. In addition, in vitro, IL-15 bound to a chimera comprised of the soluble portion of the IL-15Ra covalently linked to an antibody Fc region (IL-15Ra-Fc) (R&D Systems, Inc., Minneapolis, Minn.), supports the survival of IL-15Ra−/− memory CD8 T cells, in contrast to either component alone.
It is generally perceived by those in the pertinent art that the soluble portion of the IL-15Ra is an inhibitor of IL-15 action. In fact, published research has demonstrated that IL-15Ra can inhibit IL-15 activity in vitro and in vivo. Presently, no one has yet devised a system in which IL-15 and IL-15Ra are pre-coupled prior to administration as an in vivo treatment.

Compositions and methods for immunomodulation in an organism


Recessing a trench using feed forward data is disclosed. In one embodiment, a method includes providing a region on a wafer including a trench area that includes a trench and a field area that is free of any trench, and a material applied over the region so as to fill the trench in the trench area and form a step between the trench area and the field area; etching to partially etch the trench; determining a target etch duration (tD) for etching to the target depth (DT); and etching the trench to the target depth (DT) for a period approximately equal to the target etch duration (tD). The target etch duration tD may be fed forward for recessing another trench to the target depth DT. The method does not require a send ahead wafer, is fully compatible with conventional automated processes and provides in-situ etch time correction to each wafer.

1. Technical Field
The invention relates generally to semiconductor device fabrication, and more particularly, to recessing a material in a trench to a target depth.
2. Background Art
A common process in trench technology is filling a trench with a filling material and then recessing the filling material to a predetermined depth. For example, to form a buried plate of a trench capacitor, an arsenic-doped glass (ASG) layer is deposited on a trench sidewall and the trench is filled with resist. The resist is then recessed to a predetermined depth to expose the ASG in the upper trench. The exposed ASG is then selectively removed to the resist in the lower trench. The resist is then removed from the trench, leaving ASG only on the lower trench sidewall. Arsenic in the ASG is then driven into the silicon substrate in a subsequent thermal process to form the buried plate—a heavily doped region in the substrate.
One challenge in this process is precisely controlling the depth of the resist recess, which is critical to determining device characteristics such as trench capacitance and parasitic leakage current. One approach to this challenge includes a 'send ahead' technique in which a wafer from a lot is processed first and the recess depth is measured. The process for the rest of the wafers is then adjusted based on the measured depth from the 'send ahead' wafer. The 'send ahead' approach has a number of disadvantages. First, it is destructive because the resist recess of the send ahead wafer is traditionally measured by a scanning electron microscope (SEM), which requires the send ahead wafer to be cleaved (destroyed) for SEM analysis. This approach is prohibitively costly. Second, the 'send ahead' approach is time-consuming. When a lot gets to the recess process, a send ahead wafer has to be split from the lot and processed first and the process is adjusted based on the send ahead. The turn-around-time for this send ahead approach may take several hours. Third, the process delay between the send ahead and the lot adds process variation since a condition of the recess chamber from which the send ahead wafer is pulled may change when the lot is processed. Fourth, the send ahead approach is not compatible with the currently automated 300 mm process because it requires dedicated manpower to take the send ahead wafer out of the lot, deliver it to SEM lab, and analyze the recess depth after the SEM is completed. Finally, the send ahead approach cannot accommodate incoming wafer-to-wafer variations such as variations of trench profile and the filling characteristics. The possible chamber condition change aggravates this situation. All these variations cause the recess depth variation from wafer to wafer. With the send ahead approach, the process is adjusted only once and then all wafers are processed with the same process setup. Accordingly, process adjustment to accommodate the above variation on each wafer is impossible using the send ahead approach.
Therefore, a simple process with precise recess control but without send ahead is desired.

This patent is subject to a terminal disclaimer.

Recessing trench to target depth using feed forward data

International Business Machines Corporation


The present invention provides an etched leadframe flipchip package system comprising forming a leadframe comprises forming contact leads and etching a plurality of multiple dotted grooves on the contact leads, and attaching a flipchip integrated circuit having solder interconnects on the contact leads between each of the plurality of the multiple dotted grooves.

As the electronics industry progresses integrated circuit (IC) products are shrinking in size. The applications supported by these IC's are becoming more powerful with ever increasing features and functions. This is exemplified as the telephone was transformed into the cellular phone and most recently into the camera phone. All the while these devices continue to shrink in size. Other devices that have evolved include computers, memory devices, personal music players and personal data assistants (PDA's). Each is operated by an integrated circuit die.
An IC die is a small device formed on a semiconductor wafer, such as a silicon wafer. A leadframe is a metal frame that usually includes a paddle that supports an IC die that has been cut from the wafer. The leadframe has lead fingers that provide external electrical connections. That is, the die is attached to the die paddle and then bonding pads of the die are connected to the lead fingers via wire bonding or flip chip bumping to provide the external electrical connections. Encapsulating the die and wire bonds or flip chip bump with a protective material forms a package. Depending on the package type, the external electrical connections may be used as-is, such as in a Thin Small Outline Package (TSOP), or further processed, such as by attaching spherical solder balls for a Ball Grid Array (BGA). These terminal points allow the die to be electrically connected with other circuits, such as on a printed circuit board.
Use of packaged ICs is widespread. Moreover, the size and cost of electronic devices puts continuous pressure on the need for small, yet less costly packaged ICs. Furthermore, for high bandwidth RF devices and high operating frequency devices, there is a push for shorter electrical paths inside the IC package. Flip chip bonding can replace the traditional wire bonding interconnection.
There are also manufacturing issues that plague the flipchip assembly process. With the attachment of the flipchip solder balls to the leadframe or substrate, the IC die has a tendency to move during the reflow connection. As the solder becomes viscous, the die can be moved by the surface tension in the liquid solder. Due to the small size of the IC die, it is difficult to hold the IC die in a fixed position. Any movement during the attachment process can cause a package failure and reduced yield.
A key component in the die attach process is the leadframe preparation. As the solder liquefies, during reflow, it will flow to any surface that will bond with it. Preparing a leadframe for flipchip attachment can be a meticulous and costly process. Thus, it is desirable to provide an inexpensive method of flip chip interconnection packaging ICs. It also is desirable to have a method of decreasing the size of such packaged ICs.
Thus, a need still remains for a reliable high volume capable process for flipchip assembly on leadframe packages. In view of the demand for high volume low profile packages, it is increasingly critical that answers be found to these problems. The ever increasing need to save costs and improve efficiencies, makes it is more and more critical that answers be found to these problems. Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.

Etched leadframe flipchip package system


A power supply system that supplies electric power to a load includes a first power storage device, a second power storage device, a power line for transmitting electric power input and output to and from the load, a converter for executing bidirectional DC voltage conversion between the first power storage device and the power line, and a switch connected between the second power storage device and the power line. When the switch is OFF, the control device performs voltage control of the converter so that a voltage value of the power line becomes a voltage command value, and when the switch is ON, the control device performs current control of the converter so that a current value of the first power storage device becomes a current command value.

In a power supply system applied to an electric powered vehicle, a power conversion apparatus that converts output electric power of a power storage device mounted on the vehicle into electric power for driving a drive motor is configured with a combination of a converter that can step-up the output voltage of the power storage device, and an inverter that converts output DC voltage of the converter into AC voltage and applies the AC voltage to the inverter.
Japanese Patent Laying-Open No. 2009-159663 (PTD 1) discloses a power supply system that includes a plurality of power storage devices, and a plurality of converters provided between DC power lines connected to inverters and the plurality of power storage devices, respectively. In the power supply system described in PTD 1, one of two converters is controlled in accordance with voltage control for bringing a voltage value of a DC power line to a prescribed voltage target value, while the other converter is controlled in accordance with current control for bringing the charge and discharge current of a corresponding power storage device to a prescribed current target value.

Power supply system and method for controlling the same


Methods and systems for collecting dust produced in paper making involve an air inlet passage including an opening to receive dust laden air. The opening to the inlet passage may have a width approximately equal to a width of a paper web in a paper making machine. The air inlet passage is devoid of water injection. The dust collector may include a central vortex chamber and may be defined by an outer wall and an internal guide vane. There may be a water injector mounted in the outer wall and injecting water into the central vortex chamber, and there may be a discharge outlet of the central vortex chamber connectable to a water and air separator.

This invention relates to dust collection and, specifically, to the collection of paper dust generated by papermaking machines, such as tissue making machines.
Dust, e.g., paper fibers and other small air borne debris, is formed during the production of tissue paper and other types of paper. The amount of dust generated by paper making machines (e.g., tissue making machines) has increased as the speed increases of the paper webs passing through paper making machines. Greater amounts of dust tend to be created with paper machines that produce soft tissue paper and papers having high crepe ratios.
There is a need to remove dust produced during paper making processes. Dust removal is needed to avoid problems that may arise with dust collecting on the paper making machines and paper webs formed by these machines. Removal of substantial portions of the dust generated by paper making allows for improved paper quality and printability of the generated papers.
Conventional dust removal systems, such as disclosed in U.S. Pat. No. 6,176,898 ('898 Patent), utilize various shapes of exhaust cross machine headers. Dust collectors typically uses large amount of exhaust air to evacuate the dust developed during the paper making process. The '898 Patent discloses a dust collection cylinder having an interior air vortex and water spray that entrains dust laden air as soon as the air enters the collector. In the dust collector shown in the '898 Patent, the inlet to the dust collector is short and recessed with respect to the cylindrical collector such that the dust laden air is immediately wetted by the vortex of air and water within the collector.

Method and system for collecting paper dust


An organic light-emitting apparatus has a structure capable of reducing defects during the formation of an insulation layer (e.g., a pixel defining layer). The organic light emitting apparatus includes a substrate having a display area and a peripheral area surrounding the display area; a step forming layer on the peripheral area of the substrate; an insulation layer on the substrate across the display area and the peripheral area, wherein the top surface of a portion of the insulation layer corresponding to the step forming layer by covering the step forming layer is higher than the top surface of the remaining portion of the insulation layer; and a first conductive layer on the insulation layer, an end portion of the first conductive layer being close to the portion of the insulation layer corresponding to the step forming layer.

1. Field
One or more embodiments of the present invention relate to an organic light-emitting display apparatus.
2. Description of the Related Art
Generally, an organic light-emitting display apparatus includes a plurality of organic light-emitting devices, each of which includes a pixel electrode, a counter electrode, and an intermediate layer that is interposed between the pixel electrode and the counter electrode. The intermediate layer includes an emission layer. In such an organic light-emitting display apparatus, the pixel electrodes are arranged apart from one another, whereas the counter electrode is formed as a single body with respect to the plurality of organic light-emitting devices. Furthermore, the counter electrode contacts an electrode power supply line outside a display area, and receives a preset electric signal.
However, in the manufacturing process of such a comparable organic light-emitting display apparatus, after the electrode power supply line has been formed, and when a material for forming an insulation layer (e.g., a pixel defining layer) is applied thereon to form the insulation layer, the material for forming the insulation layer may not be smoothly applied due to the electrode power supply line underneath.

Organic light-emitting display apparatus


A microwave oscillator includes a waveguide that is short-circuited on one side and a diode arranged therein, which receives its supply voltage by way of a coupling pin passed through a waveguide wall. At least one adjustment pin, extends into the waveguide and is adjustable in its penetration depth, for tuning the oscillator frequency. Because the adjustment pin is aligned at an acute angle to the coupling pin, the oscillator frequency can be tuned very precisely.

A microwave oscillator having a Gunn diode is disclosed, for example, by German Patent No. DE 28 26 767 B2 or by German Published Unexamined Application No. DE-OS 27 09 210. This related art describes arranging the adjustment pin either in the narrow side or in the wide side of the waveguide supporting the Gunn diode. Thus, in the one case, the adjustment pin is aligned vertically and, in the other case, parallel to the coupling pin feeding the supply voltage to the Gunn diode. Usually, in a microwave oscillator of this kind, the short-circuiting wall of the waveguide is movable, so that the possibility of tuning the oscillator frequency with inductive action is given. This tuning action mainly has an effect on the power output by the oscillator. The adjustment pin that feeds the supply voltage to the Gunn diode is provided in the feed-through orifice to the waveguide with a stop filter (choke), to prevent any oscillator power from leaking off unintentionally through the feed-through orifice.
The object of the present invention is to devise a microwave oscillator whose frequency adjustment will be able to be carried out as simply as possible.

Microwave oscillator having at least one adjustment pin


A multi-temperature cryogenic refrigeration system for a container is selectively operable to maintain its cargo in frozen and non-frozen conditions. The system includes a cargo compartment defined by a floor, a pair of opposed side walls, a pair of opposed end walls, and a lower ceiling. A roof is located above the lower ceiling. Upper and lower compartments or bunkers are provided between the lower ceiling and the roof, and are separated by a fixed, non-porous upper ceiling. A plurality of openings extend through the lower ceiling for fluid communication between the lower compartment and the cargo compartment. Upper and lower cryogenic snow-forming devices are provided in the upper and lower compartments, with each snow-forming device having a coupling connecting it to a supply of cryogenic liquid. Conduits or passages are located in the walls and floor to convey the cryogenic snow and gas from the upper compartment and through the walls and floor in a manner that isolates the cryogenic snow and gas from the cargo compartment.

Cryogenic refrigeration systems are replacing mechanical systems for transporting frozen cargo, particularly by railcar. A particularly effective system for transporting cargo at frozen temperatures is disclosed in U.S. Pat. No. 4,704,876 to Hill, the subject matter of which is hereby incorporated by reference. In the system of the Hill patent, the railcar walls are insulated, and a ceiling between the railcar roof and floor separates an upper refrigerant compartment or bunker from the lower cargo compartment. The ceiling of the cargo compartment or bunker floor is provided with openings. A distribution pipe coupled to a source of liquid carbon dioxide extends along the length of the upper bunker. The distribution pipe converts liquid carbon dioxide to carbon dioxide snow which is stored in the bunker. During transit, the carbon dioxide snow sublimates and the gas escapes through the openings in the bunker floor to pass into and to cool the cargo in the cargo compartment. The floor of the cargo compartment is provided with open top, lengthwise channels which receive the carbon dioxide and conduct it to one end of the car where it is discharged out an exterior vent in one end wall of the railcar.
The railcar according the Hill patent has been successfully used for transporting frozen products which can be directly exposed to the carbon dioxide gas without adverse effects. However, such system cannot be used with products which cannot be frozen or cannot be exposed to direct contact with the carbon dioxide gas.
Cargo requiring refrigeration at non-frozen temperatures and sensitive to carbon dioxide gas is typically transported in mechanical refrigeration systems employing a circulating refrigerant and a power-driven compressor. Such mechanical systems are disadvantageous due to the need for extensive maintenance.
Carbon dioxide refrigeration systems have been proposed for non-frozen goods, as well as frozen goods. U.S. Pat. No. 4,761,969 discloses a carbon dioxide refrigeration system for storing both frozen and non-frozen goods. For frozen goods, liquid carbon dioxide is conveyed to an upper distribution pipe or manifold for depositing snow into a refrigerant compartment or bunker located above the cargo compartment. The bunker floor separates the refrigerant compartment from the cargo compartment and has openings to permit sublimating carbon dioxide gas to pass from the refrigerant compartment into the cargo compartment. For non-frozen goods, liquid carbon dioxide is conveyed to a lower manifold or distribution pipe located within an expandable bladder. The carbon dioxide gas generated in the bladder is vented directly to the outside of the container, and does not pass into the cargo compartment. The expandable bladder, when filled with carbon dioxide snow, acts as a cold plate to cool the load by convection. This system is disadvantageous in view of the need for an expandable bladder which will retain its resiliency, even when subjected to the extremely cold temperatures of the carbon dioxide snow and since inadequate cooling may be provided along the sides and bottom of the container.
Another dual purpose cryogenic system is disclosed in U.S. Pat. No. 5,152,155. This patent discloses a refrigerated railcar wherein carbon dioxide snow is formed and deposited on a bunker floor from a single distribution pipe located within the single refrigerant compartment in the railcar. For frozen goods, carbon dioxide gas is conveyed through serpentine ducts in the railcar walls and through openings in the bunker floor directly into the cargo compartment. For non-frozen goods, the openings in the bunker floor are closed by a switchable valve such that the flash gas and the sublimating carbon dioxide gas can only pass through the serpentine passages in the walls, isolating the carbon dioxide gas from the cargo. This system is disadvantageous due to the difficulty and potential problems in the mechanism for opening and closing the switchable valves in order to convert the railcar from a frozen mode to a non-frozen mode. Additionally, inadequate cooling may be provided in the walls and floor.

Multi-temperature cryogenic refrigeration system


An assembly for post-operatively treating an abnormal curvature of vertebrae of a spinal column. The assembly includes an elongate member extending in a generally vertical direction along a posterior side of the spinal column and a transverse member fastened to a vertebra of the spinal column with a plurality of fasteners and extending in a generally horizontal direction. The transverse member has a threaded region. The assembly further includes a coupler coupling the elongate member to the transverse member. The coupler includes a rotating member threadedly engaged with the threaded region of the transverse member. Rotation of the rotating member provides lateral movement of the transverse member relative to the elongate member, thereby moving the vertebra in a horizontal direction and applying a corrective force to the vertebra.

The spinal column of a patient includes a plurality of vertebrae linked to one another by facet joints and an intervertebral disc located between adjacent vertebrae. In a healthy spinal column, viewed posteriorly, the vertebrae are aligned along the sagittal plane of the patient. Viewed laterally, the spinal column exhibits several curves corresponding to different regions of the spinal column, named the cervical, thoracic, and lumbar curves.
There are many types of spinal column disorders and abnormal curvatures of the spinal column including scoliosis (abnormal lateral curvature of the spine), kyphosis (abnormal forward curvature of the spine, usually in the thoracic spine), excess lordosis (abnormal backward curvature of the spine, usually in the lumbar spine), spondylolisthesis (forward displacement of one vertebra over another, usually in the lumbar or cervical spine), as well as other disorders caused by abnormalities, disease or trauma.
Various correction systems have been proposed and used in attempting to correct abnormal curvatures of the spinal column. However, each of these correction systems includes deficiencies making the correction system less than optimal. For instance, many systems require some form of repeated surgeries to achieve a satisfactory correction of the curvature, exert excessive stresses on anatomical structures of the spinal column and/or include limitations as to the extent of correction which is possible.
Accordingly, there is an ongoing need to provide alternative apparatus, devices, assemblies, systems and/or methods that can function to correct spinal abnormalities, such as abnormal curvature of the spinal column.

Adjustable assembly for correcting spinal abnormalities


An image processing apparatus capable of reducing storage capacity and lightening processing loads while keeping visual quality of shooting information high. An output unit resizes a taken image into images with resolutions corresponding to respective resolutions of a plurality of image output destinations including a display unit and output the images at the same time. A superimposition unit individually superimposes shooting information corresponding to the respective resolutions of the plurality of image output destinations on the images. A control unit provides control such that the shooting information is superimposed on the image output to the display unit and a selected image output destination and the output unit outputs the same, and that the output unit outputs the image to an image output destination that has not been selected without superimposing the shooting information on the image.

1. Field of the Invention
The present invention relates to an image processing apparatus, a control method therefor, and a computer-readable storage medium storing a program for implementing the control method, and in particular to a display control technique for use in displaying a variety of information as well as images on a display which the image processing apparatus has.
2. Description of the Related Art
In recent years, the resolution of images during video shooting by video cameras have been continuously increasing from Standard Definition (SD) to High Definition (HD) and further to 4K or Super High-Definition (SHD). It should be noted that 4K is a video format with a screen resolution of approximately 4000 horizontal pixels by 2000 vertical pixels, and examples thereof include a resolution of 4096×2160/24p defined by DCI (Digital Cinema Initiatives). In step with this trend, not only HD televisions but also 4K televisions have come along as ordinary televisions, and environments from shooting to viewing have been improving.
On the other hand, there are image pickup apparatuses whose main body is equipped with displays such as a panel monitor and a viewfinder, which display an image being taken, so that during actual shooting, a user can check the angle of view and the brightness of an image being taken. Also, there are known image pickup apparatuses which have a video output terminal for outputting an image being taken to a relatively large external monitor so that details of an image being taken such as image quality can be checked. In either arrangement, when an image being taken is to be displayed on each of the panel monitor, the viewfinder, and the external monitor, which are image output destinations, information for grasping various statuses during shooting (hereafter referred to as "shooting information") when necessary needs to be displayed in a superimposed manner.
The panel monitor, the viewfinder, and the external monitor have different resolutions in many cases, and it is thus necessary to resize an image according to image output destinations. When decimation or interpolation is performed in such resizing, degradation of quality such as streaking or blurring of straight lines or the like with clear brightness and color difference which are used for characters that represent shooting information, or turning-off of display may be more likely to occur particularly in a taken image that does not have a fine gradation.
To prevent this problem, superimposition data for shooting information is created in advance with respect to image output destinations in accordance with resolutions thereof, and shooting information is displayed using the corresponding superimposition data in a manner being superimposed on an image being taken, which is to be displayed on the mage output destination, in many cases.
On the other hand, as a method to display shooting information superimposed on an image while maintaining quality in accordance with resolutions of image output destinations, there has been proposed a method that generates font information, which is suited to a plurality of resolutions, from one piece of font data (see Japanese Laid-Open Patent Publication (Kokai) No. 2007-243923). According to this method, from one piece of font data, thick-line font data is generated in a case where resizing is to be performed for a small screen, and font data with an optimum design is generated in a case where resizing is to be performed for a large screen.
However, according to the method that creates superimposition data for shooting information with respect to image output destinations and in accordance with resolutions of the image output destinations, the amount of data increases with an increase in the number of image output destinations and hence high-capacity ROM or RAM is required so as to hold superimposition data. Moreover, a problem of an increase in the load of a display signal generation process carried out by a control circuit of an apparatus main body so as to superimpose superimposition data on an image arises.
On the other hand, the technique described in Japanese Laid-Open Patent Publication (Kokai) No. 2007-243923 can reduce the storage capacity of ROM, RAM, or the like, which stores display fonts which are superimposition data.
Display fonts created using the method described in Japanese Laid-Open Patent Publication (Kokai) No. 2007-243923, however, are not completely suited to resolutions of image output destinations. For this reason, the quality of shooting information displayed when resizing is performed as a result is worse compared to the method that creates superimposition data in advance according to resolutions of image output destinations. Moreover, generation of data for displaying shooting information is required for each of image output destinations, and this process as well as a process to generate font data for respective resolutions from one piece of font data brings about an increase in processing loads on the control circuit of the apparatus main body.

Image processing apparatus having display device, control method therefor, and storage medium


An edge extraction unit extracts vertical and horizontal wiring edges and slanted wiring edges from overall wiring graphics, and a wiring width classification unit executes a scaling process for the overall wiring graphics to classify the wiring graphics into wiring width ranges which are divided by a predefined reference wiring width. A vertical and horizontal wiring edge extraction unit extracts the vertical and horizontal wiring edges which are in contact with graphics classified into the wiring width ranges, and a vertical and horizontal wiring interval verification unit verifies intervals between the vertical and horizontal wiring edges and opposed edges to be verification counterparts based on a vertical and horizontal reference interval for each wiring width range. A slanted wiring edge extraction unit extracts slanted wiring edges which are in contact with graphics classified into the wiring width ranges, and a slanted wiring interval verification unit verifies intervals between the slanted wiring edges and opposed edges to be verification counterparts based on a slanted reference interval for each wiring width range.

1. Field of the Invention
The present invention relates generally to a computer-aided wiring graphic verification method, program and apparatus for verifying wiring graphic data for wiring masks created from layout data for circuit design of a large-scale semiconductor integrated circuit, etc., and more particularly to a wiring graphic verification method, program and apparatus for verifying wiring intervals and wiring widths of vertical and horizontal wiring and slanted wiring mixed in the wiring graphic data.
2. Description of the Related Arts
Traditionally, in computer-aided large scale semiconductor integrated circuits design work, a location of devices is determined on the integrated circuit according to a logic circuit diagram or an electronic circuit diagram referred to as a wiring location design of a layout design, and after wiring paths between these devices are determined, a plotting operation for generating mask based on this is performed.
As is well known, in layout design, layout verification is performed. This layout verification is to confirm accuracy of design of plot data (artwork data) for generating mask in final design stage.
In this layout verification, the verification called design rule check (DRC) is performed. This is an operation which verifies that the plot data does not violate geometrical design rules which is designed with various constraint obtained after examining fabrication processes, or the design rules.
In conventional design rule check, it is verified that intervals between wiring graphics and wiring widths do not violate the design rules. In verification of intervals between wiring graphics, verification reference values vary according to the wiring widths. Also, acceptable minimum wiring width and maximum wiring width are defined for each wiring layer.
In verification of wiring intervals targeting the conventional vertical and horizontal wiring, there are a method that extracts wiring graphics which are to be verification targets and checks intervals between the wiring graphics and a method that extracts edges between wirings which are to be verification targets and checks intervals between these edges. Also, for verification of wiring widths, there are a method that extracts wiring graphics which are to be verification targets and checks widths between the wiring graphics and a method that extracts edges between wirings which are to be verification targets and checks intervals between these edges (See Japanese Patent Application Laid-open Pub. Nos. 2001-13673, Hei8-55140 and Hei11-96200).
By the way, in conventional layout design, wiring patterns are arranged in horizontal and vertical directions, but in recent years, slanted wiring in which wiring patterns are arranged in 45 degrees slanted direction has been introduced in order to shorten wiring paths, reduce line resistance and stray capacitance and improve transmission properties associated with higher frequency.
However, in verification of the layout design in case that the vertical and horizontal wiring and the slanted wiring are mixed, if the design reference values for the wiring intervals of the vertical and horizontal wiring and the slanted wiring are different respectively and also if the design reference values for minimum wiring widths and maximum wiring widths of the vertical and horizontal wiring and the slanted wiring are different respectively, then a problem occurs, in which so-called pseudo-errors, which is output as error even when it is not error, is generated by mutual interferences of different design reference values.
In other words, if layout verification is performed according to the design reference value of the vertical and horizontal wiring, the design reference value of the vertical and horizontal wiring is also applied to the slanted wiring and the pseudo-errors is generated. Conversely, if layout verification is performed according to the design reference value of the slanted wiring, the design reference value of the slanted wiring is also applied to the vertical and horizontal wiring and the pseudo-errors is generated.
Therefore, layout verification can not accommodate the layout verification in which the design reference values of the vertical and horizontal wiring and the slanted wiring are different, and different design reference values can not be applied to the vertical and horizontal wiring and the slanted wiring, so the problem occurs, in which the degree of freedom of the layout design is limited.

Wiring graphic verification method, program and apparatus


The disclosure provides for a mixture suitable for extrusion and firing to form a ceramic honeycomb substrate, said mixture comprising a batch composition selected from the group consisting of a cordierite batch composition and an aluminum titanate batch composition, an optional pore former material; a binder material and water; wherein said binder is a methyl ether of cellulose binder having a count of less than 300 water-insoluble fibers per gram of binder material.

Ceramic honeycombs, for example cordierite or aluminum titanate honeycombs, are made by extrusion of a ceramic paste. The ceramic paste is prepared by mixing dry raw materials followed by the addition, with further mixing, of liquid components and plasticizing the resulting mixture using an augur or twin screw mixing system. After plasticizing, the ceramic paste is pushed through an extruder die to form a honeycomb "green body" that is further processed. The overall process can be summarized as providing a plasticized ceramic honeycomb precursor batch material comprising inorganic ceramic-forming components, optional pore forming materials (for example a starch or graphite material), liquid components (for example, water), lubricating materials (to aid in extrusion) and binders; plasticizing the mixture; forming a green body having the desired shape, size and cells density from the plasticized ceramic precursor batch material; optionally drying the green body to remove excess moisture and prevent slumping during firing; and firing the dried green body under conditions sufficient to convert the green body into a ceramic honeycomb. Depending on the choice of inorganic materials, the fired honeycomb can be a cordierite or aluminum titanate honeycomb. In the above process one problem that is frequently encountered is the plugging of the die during the extrusion process, particularly when ultra-thin wall honeycomb substrates are formed. The present invention presents a solution to the plugging process.

Selected binders for the extrusion of ultra-thin wall cellular ceramics


Embodiments of a medical vial holder apparatus and system are disclosed. A main body has a mount engagement portion and a vial engagement portion. A facing wall is attached to the vial engagement portion thereby defining a vial retention cavity therebetween. A lever element is mounted to the main body for pivotal movement between a grip position and a release position. The lever element has a grip portion with a vial engagement face. A grip distance is defined between the vial engagement face and the facing wall. Movement of the lever element from the release position toward the grip position reduces the grip distance. Movement of the lever element from the grip position toward the release position increases the grip distance. The lever element is biased toward the grip position. A plurality of the apparatuses are adjustably mountable in line with one another by way of their mount engagement portions.

Conventional expedients for capturing and retaining a medical vial in an inverted position exist in the prior art. However, such conventional devices may require excessive dexterity on the part of the user, may be costly and complex to assemble, and may lack features which would otherwise help a user operate such a device more quickly, effectively and safely while under pressure in a medical treatment environment.

Medical vial holder apparatus and method


A battery assembly includes a plurality of electric cells each having an external terminal at one end thereof, a first cap attached to the one end of each of the electric cells and a first holder attached to the plurality of electric cells and is in contact with the first caps.

Patent Document 1 discloses a battery assembly configured such that a plurality of electric cells aligned in one row are sandwiched and fixed by a pair of side plates located at both ends in the alignment direction.
Patent Document 2 discloses a battery assembly configured such that a plurality of electric cells are aligned in a case having a box shape and open upper end and the opening of the case is closed by a cover.
In the configuration according to Patent Document 1, the number of the electric cells in the alignment direction can be increased and decreased by relatively easy redesign. Other than the above, change in arrangement of the electric cells requires significant redesign. In the configuration according to Patent Document 2, it is necessary to redesign both the case and the cover in order to change the arrangement of the electric cells. Each of the case and the cover is typically made of a resin. It is thus necessary to prepare new expensive molds for shaping the case and the cover due to such redesign. As described above, the battery assemblies according to Patent Documents 1 and 2 each have the low degree of freedom of the arrangement of the electric cells in view of the restriction in cost. It is thus difficult to achieve various kinds of small quantity production at a low cost.
Patent Document 3 discloses a battery assembly in which each of rectangular electric cells is provided at both sides thereof with protrusions and a through hole is provided at each of a pair of exterior plates laterally sandwiching the electric cells. Vibration proof and impact resistance are improved by fitting the protrusions to the through holes.
In order to assemble the battery assembly according to Patent Document 3, after the plurality of electric cells are aligned, the electric cells need to be laterally sandwiched by the pair of exterior plates in a state where the through holes are accurately positioned at the protrusions provided at the both sides of the electric cells. In this regard, the battery assembly according to Patent Document 3 requires complicated assembly work with less easiness.


A method to handle data dependencies in a pipelined computer system is disclosed. The method includes allocating a plurality of registers, enabling execution of computer instructions concurrently by using the plurality of registers, and tracking and reducing data dependencies in the computer instructions by correlating a busy condition of a computer instruction to each register.

The present invention relates to a predicate register file. More particularly, the present invention relates to scoreboarding and renaming such a predicate register file.
Microprocessors often use instruction pipelining to increase instruction throughput. An instruction pipeline processes several instructions through different stages of instruction execution concurrently, using an assembly line-type approach. The pipeline stages are often controlled by predicate registers. One predicate register may be assigned to each stage in the pipeline. All instructions for that stage may then share the same predicate register. Thus, this enables determination of whether the instructions for the stage are executed or not. In other applications, such as Itanium applications, each instruction (referred to as "syllable") has its own "qualifying predicate" that determines whether it executes or not.
However, the performance of pipelined computers may be degraded by data dependencies. A data dependency exists between two instructions if the execution of one depends upon the results of executing the other. Each instruction has the potential to stall later instructions that depend on it.
Accordingly, each of the predicate registers may be associated with a bit which indicates whether the data inside each respective register is either updated and ready to be used, or is being modified or produced and therefore not available. This bit is often referred to as a "scoreboard" bit. For example, if a scoreboard bit for a particular predicate register is set, then the next instruction that needs to access this register cannot execute until the scoreboard bit for this register has been cleared. To clear this register bit, a preceding operation needs to complete execution.
Out-of-order execution may also be used to substantially reduce the effect of stalls due to data dependencies. Upon encountering an instruction that depends on data still in use, the out-of-order execution processor checks for later independent instructions in the program and executes these later instructions before the instruction with dependent data. This reduces the impact of execution stalls because the execution of later independent instructions is overlapped with the execution of instructions requiring multiple clocks to complete.

Predicate register file write by an instruction with a pending instruction having data dependency


There is an information registration apparatus for registering patrons entering a club or other commercial use. The apparatus comprises a housing (1) with a top panel (3) and sign-in window (4). A form (14A) is displayed in the window (4) for handwritten entry of information by a patron. The information is then photographed from the underside by means of a camera (9) and image reversing reflective mirror (10) and stored or transmitted to a viewing station.

This invention relates to information recording and processing equipment. More particularly, although not exclusively it discloses an improved apparatus for registering patrons entering a club or collecting and processing information entered by customers of commercial establishments.
Current laws relating to licenced clubs require that the identities and addresses of members and visitors entering the premises be recorded. Such information must be kept by the clubs for a number of years. At present clubs use books of pre-printed forms on carbonless sheets or NRC paper. Each patron upon entering has to fill out a form which is then torn off and kept as proof of temporary membership. The duplicate remaining in the book becomes the club""s record of the visit. Such books however are expensive and bulky to store. Further, there is no way for management to easily process or analyse the records to obtain marketing information on for example the frequency that certain persons use the club or the geographic areas most served by the club. While paperless registration systems have been proposed which to some extent address the above problems using such apparatus is often difficult and daunting for elderly persons.
It is therefore an object of this invention to ameliorate the aforementioned disadvantages and accordingly a registration apparatus for club or retail use is disclosed. said apparatus including a console with a window aperture for display of a pre-printed form for handwritten completion by a customer, means for obtaining information off the underside of said form, and means for paperless storage and/or transmission of said handwritten information to viewing stations.
Preferably said written information is stored on hard disk with an in house sequential number linked to the patron""s issued entry docket.
It is further preferred that said written information be displayed on a remote monitor and/or a monitor at the back of said console for viewing by club personnel.
It is further preferred that said form or a copy thereof be returned to said customer after photographing original handwritten details by the camera capture unit.


Disclosed is an organic EL device as an light emitting device according to this application example includes a base material as a substrate, and an organic EL element as a plurality of light emitting elements having a light emitting functional layer as a functional layer in which an organic light emitting layer is included between a pixel electrode as an anode and an opposed electrode as a cathode and a sealing layer sealing the plurality of organic EL elements which are formed on the base material, and the opposed electrode is formed over the plurality of organic EL elements as a common cathode, and the sealing layer is formed so as to cover the common cathode in the same region where the common cathode is formed or inwards from the region.

1. Technical Field
The present invention relates to a light emitting device including light an emitting element, a method of manufacturing a light emitting device, and an electronic apparatus.
2. Related Art
An organic electroluminescence (EL) element which is easy to be made thinner and more compact compared to a light emitting diode as a light emitting element attracts attentions. An organic EL element has a functional layer including an organic light emitting layer between an anode and a cathode, if a voltage is applied between the anode and the cathode, light emission is obtained from the organic light emitting layer depending on an amount of current flowing through the functional layer.
In such a functional layer, a light emitting function thereof is decreased or lost if water, or oxygen, or the like penetrates from outside. Therefore, it is necessary to provide ways for preventing the water, or the oxygen, or the like from penetrating in order to ensure a light-emission lifetime of the organic EL element.
For example, in JP-A-2007-157606, there is proposed a sealing structure of the organic EL element covering a second electrode as a common cathode, in which a first inorganic layer, a second inorganic layer, an organic buffer layer, and a gas barrier layer are sequentially laminated.
According to this, since the organic buffer layer is provided between the organic EL element and the gas barrier, for example, when cracks occur by expansion and contraction due to heat, it is possible to provide a long-lifetime light emitting device by preventing water, or oxygen, or the like from penetrating from respective cracks. According to the above-described JP-A-2007-157606, the gas barrier layer is formed not only to cover the organic buffer layer but also to cover a peripheral edge portion of the first inorganic layer covering the second electrode. Accordingly, on a substrate, a peripheral region that covers a region in which a plurality of organic EL elements are disposed is necessary in order to reliably cover the peripheral edge portion of the first inorganic layer by the gas barrier.
However, if decreasing an area of the peripheral region in an attempt to reduce the size of the light emitting device itself, there has been a problem in that it is difficult to adopt the sealing structure of the above-described JP-A-2007-157606.

Light emitting device, method of manufacturing the same, and electronic apparatus


A fuse and filter arrangement for limiting and ameliorating electrode shorting in capacitive deionization water purification systems utilizing carbon aerogel, for example. This arrangement limits and ameliorates the effects of conducting particles or debonded carbon aerogel in shorting the electrodes of a system such as a capacitive deionization water purification system. This is important because of the small interelectrode spacing and the finite possibility of debonding or fragmentation of carbon aerogel in a large system. The fuse and filter arrangement electrically protect the entire system from shutting down if a single pair of electrodes is shorted and mechanically prevents a conducting particle from migrating through the electrode stack, shorting a series of electrode pairs in sequence. It also limits the amount of energy released in a shorting event. The arrangement consists of a set of circuit breakers or fuses with one fuse or breaker in the power line connected to one electrode of each electrode pair and a set of screens of filters in the water flow channels between each set of electrode pairs.

The present invention is directed to electrode shorting, particularly to limiting and ameliorating electrode shorting in systems such as capacitive deionization water purification systems, which utilize a stack of electrode pairs, and more particularly to electrically protect an entire system from shutting down if a single pair of electrodes is shorted and to mechanically prevent a conducting particle from shorting a series of electrode pairs.
Various capacitive systems utilize a plurality or stack of electrode pairs. For example, one such system which utilizes stacks of electrode pairs is a capacitive deionization water purification system. An example of such a water purification system involving capacitive deionization utilizing carbon aerogel electrodes is described and claimed in U.S. Pat. No. 5,425,858 issued Jun. 20, 1995, to J. C. Farmer and is directed to a method for removing ionic solutes from water. The patented method makes use of pairs of carbon aerogel electrodes arranged with interelectrode gaps of small size (about 0.5 mm), through which the water is made to flow. Large stacks containing many electrode pairs are powered by a common power supply and are wired in parallel. Water flow passes through the gaps between the electrode pairs in series. In such a configuration of electrode pairs, if a single electrode pair becomes electrically shorted, such as by a conducting particle that spans the interelectrode gap, the entire stack could be shut down and considerable energy could be released. In addition, it would be possible for a single conducting particle to move through the stack, shorting a series of electrode pairs in sequence. One possible source of such conducting particles, and thus shorting of electrode pairs, would be due to debonding or fragmentation of the carbon aerogel electrodes. Thus there has been a need for means to prevent electrode pair shorting and to prevent migration of particles through the electrode pairs.
The present invention addresses both the shorting of a single electrode pair and the sequential shorting of a series of electrode pairs, either by carbon aerogel fragments or by any other particles or conducting solid materials.

Means for limiting and ameliorating electrode shorting

The Regents of the University of California


A write amplifier power generating circuit includes a control unit for changing an output voltage. In a first write cycle in which a pair of bit lines are being amplified, a write operation is performed by an overdrive write method in which a high level from a write amplifier is set to a first voltage (for example, a power supply voltage). In a second write cycle after amplification in the pair of the bit lines has been completed, a write operation is performed by a write method in which the high level from the write amplifier is set to a second voltage (for example, an internal voltage).

1. Field of the Invention
The present invention relates to semiconductor memory devices, and in particular, relates to an overdrive write method in which a write operation is performed by an overdrive method, a write amplifier power generating circuit, and a semiconductor memory device that includes the same.
2. Description of the Related Art
In recent semiconductor memory devices, high-speed processing and low power consumption are achieved. A typical method for achieving high-speed processing and low power consumption is the Boosted Sense Ground (BSG) method. In the BSG method, internal voltages VDL and VSL are used as the high and low levels of bit line read signals. The internal voltage VDL is lower than a power supply voltage VEXT supplied from an external source by a predetermined amount, and the internal voltage VSL is higher than a ground voltage GND by a predetermined amount. The internal voltage VDU the internal voltage VSL is supplied as a power supply voltage of an internal circuit in which the BSG method is adopted. The internal voltage VDL/the internal voltage VSL is smaller than the power supply voltage VEXT/the ground voltage GND. Thus, the signal amplitude in an internal circuit that includes a complementary metal-oxide semiconductor (CMOS) is also the internal voltage VDL/the internal voltage VSL. Low power consumption is achieved by operating an internal circuit with a low voltage in this way, and moreover, high-speed data transfer is achieved by suppressing noise by a small signal amplitude.
However, in the BSG method, although high-speed data transfer is achieved by a small signal amplitude, a problem exists in that a restore operation of a cell is slow. Thus, an overdrive sense method is adopted. In the overdrive sense method, a power supply voltage applied to a sense amplifier is increased at the beginning of a restore operation of a cell. Moreover, in a write operation, when the amplitude of an input signal is small, the capability in inverting a bit line pair falls short, and thus the write time gets longer. Thus, even when a write operation is performed, the overdrive method is used. In the overdrive method, the power supply voltage VEXT and the ground voltage GND are supplied.
Some types of overdrive method are described in, for example, International Publication No. WO97/24729 and Japanese Unexamined Patent Application Publication No. 10-255470. General overdrive methods described in International Publication No. WO97/24729 and Japanese Unexamined Patent Application Publication No. 10-255470 will now be described. In the description of International Publication No. WO97/24729, a power supply voltage VEXT and a ground voltage GND are supplied as operating power supplies for a sense amplifier at the beginning of a sensing operation. After sensing and amplification operations are quickly performed, internal voltages VDL and VSL are supplied. In the description of Japanese Unexamined Patent Application Publication No. 10-255470, a power supply voltage VEXT and a ground voltage GND are supplied as operating power supplies for a write amplifier only for a predetermined period. After a sense amplifier is rapidly inverted, the operating power supplied for the write amplifier are internal voltages VDL and VSL.
In a write operation by the overdrive method described in Japanese Unexamined Patent Application Publication No. 10-255470, the high and low levels of write signals from a write amplifier WAMP are the power supply voltage VEXT and the ground voltage GND for the predetermined period until voltages of a bit line pair cross each other. After the predetermined period, the high and low levels of write signals are changed to the internal voltages VDL and VSL so that the level to be written to a memory cell and the signal levels in a pair of complementary bit lines BIT T and BIT N are the internal voltages VDL and VSL. In this way, the substantial achieved amplitude of write signals in the pair of the complementary bit lines BIT T and BIT N is set so as to be larger than the achieved amplitude of amplified read signals in the pair of the complementary bit lines BIT T and BIT N, and a write operation by the overdrive method is performed.
However, the inventor found that a problem existed with these overdrive write methods in the case of successive write operations. The problem is that, when successive write operations are repeated on the same word line, a bit line voltage may be excessively boosted. In this case, an overdrive operation is performed, with the power supply voltage VEXT (VDD), which is higher than the internal voltage VDL, on bit lines in which sufficient voltage difference is generated by performing amplification on the basis of data stored in a memory cell. In this way, when an overdrive operation is repeated, the bit line voltage is excessively boosted. This is because the power supply voltage VEXT from a write amplifier, which is higher than the internal voltage VDL, is supplied to the bit lines via an input/output (IO) data line and a column selection switch.
For example, in general, an IO data line and a bit line are connected by a column selection switch YSW that includes an N-channel transistor. The power supply voltage VEXT is applied as the gate voltage of the column selection switch YSW. When the high level of the IO data line is also the power supply voltage VEXT, VEXT−Vtn is applied to the bit line. When successive write operations are performed, in one of the complementary bit lines, the voltage is excessively boosted, so that the voltage is equal to or higher than the internal voltage VDL. When a precharge operation is performed, after the bit line voltage is excessively boosted, a correct reference level cannot be obtained. The precharge operation is performed to charge the complementary bit lines to a reference level (VDL/2).
Thus, in order to obtain a correct reference level in the overdrive write method, the voltage level of the bit line needs to be decreased to the VDL level so as to prevent the voltage from being excessively boosted. Alternatively, the overdrive write method may not be performed so that the output level of the write amplifier is set to the internal voltage VDL. However, when a write operation is performed using the internal voltage VDL, high-speed processing is adversely affected. At the beginning of a sensing operation by a sense amplifier, a high voltage (VEXT) is supplied to the sense amplifier. It takes long time for the sense amplifier operating with the high voltage (VEXT) to invert and write data at the internal voltage VDL, which is lower than the high voltage (VEXT). When a high-speed write operation needs to be performed at the internal voltage VDL, a power supply for a write circuit that has a large charge capacity is necessary. Thus, the power supply for a write circuit needs a large compensation capacitance, thereby adversely affecting a reduction in the chip size, and the power efficiency.
The problem will now be described in detail with reference to FIGS. 1 to 6. FIGS. 1 and 2 are a first schematic block diagram of a semiconductor memory device and a second schematic block diagram of another semiconductor memory device, respectively. FIG. 3 is a circuit diagram of a write amplifier (WAMP). FIG. 4 is a circuit diagram of a sense amplifier (SA) and a column selection switch (YSW). FIG. 5 is a circuit block diagram for illustrating a write operation. FIG. 6 is a timing chart of a write operation by a known overdrive write method.
In the semiconductor memory device shown in FIG. 1, memory cells are disposed in the form of a matrix in a memory cell array 1 surrounded by a word driver row (WD) 2 and a sense amplifier row (SA) 3. The sense amplifier row (SA) 3 includes a plurality of sense amplifiers. Each of the sense amplifiers is selected according to a column selection signal YSW. A selected sense amplifier is connected to a write amplifier (WAMP) and a data amplifier (DAMP) 6 (hereinafter called a write amplifier WAMP 6) via a pair of complementary IO data lines IO T and IO N. Hereinafter, a word driver row and a word driver are not distinguished, and both of them are called a word driver (WD) 2. A sense amplifier row and a sense amplifier are not distinguished, and both of them are called a sense amplifier (SA) 3.
The second schematic block diagram in FIG. 2 shows the other semiconductor memory device that includes a plurality of memory cell arrays. When a plurality of blocks of memory cell arrays exist, data lines are stratified and connected to the write amplifier WAMP 6. A pair of bit lines BIT T and BIT N in a memory cell array is selected by a column selection switch YSW and connected to a pair of complementary IO data lines IO T and IO N. Moreover, the pair of the complementary IO data lines IO T and IO N is selected by an IO selection switch 5 and connected to the write amplifier WAMP 6. A current semiconductor memory devices includes a plurality of memory cell arrays, and the data lines are stratified. However, the essence of the present invention does not relate to the stratification of data. Thus, in the following description, the schematic block diagram in FIG. 1 is used.
In the write amplifier (WAMP) 6 in FIG. 3, when a write enable signal WAE is at the high level, data in a read write bus RWBS is output to a pair of complementary IO data lines IO T and IO N. The power supply voltage of an output driver of the write circuit is VRW, and the high and low levels of data are VRW and GND. In a general overdrive write method, VRW is an external power supply voltage VEXT supplied from an external source. It does not matter whether the data in the read write bus RWBS is complementary data.
Write data from the write amplifier WAMP 6 is transferred to the pair of the complementary IO data lines IO T and IO N, as shown in FIG. 4. Moreover, the write data is transferred to a pair of bit lines BIT T and BIT N via a column selection switch YSW 4 and written to the sense amplifier (SA) 3 and a selected memory cell. The sense amplifier (SA) 3 is a flip-flop circuit that includes two inverter circuits and is connected to the pair of the bit lines BIT T and BIT N. A high power supply voltage (SAP)/a low power supply voltage (SAN) is supplied to the sense amplifier (SA) 3. As the power supply of the sense amplifier (SA) 3, the external power supply voltage VEXT/the ground voltage GND is supplied during an overdrive period at the beginning of a sensing operation, and an internal voltage VDL/an internal voltage VSL is supplied during a regular operation period. When the sense amplifier (SA) 3 is not activated, the power supply voltages are not supplied.
The column selection switch YSW 4 includes an N-channel transistor and is selected according to the selection signal YSW and brought into conduction. When the column selection switch YSW 4 is brought into conduction, data in the pair of the complementary IO data lines IO T and IO N is transferred to the pair of the bit lines BIT T and BIT N, respectively. The data levels from the pair of the complementary IO data lines IO T and IO N are the high level VRW and the low level GND, which are the signal levels of an output stage of the write amplifier WAMP 6.
The problem with successive write operations will now be described with reference to FIGS. 5 and 6. The write amplifier WAMP 6 outputs write data to the complementary IO data lines IO T and IO N. In the case of the overdrive write method, the power supply voltage VEXT is supplied as the power supply VRW of the write amplifier WAMP 6. A sense amplifier power circuit 7 generates the power supply voltage SAP/the power supply voltage SAN of the sense amplifier (SA) 3. The power supply voltage VEXT is supplied from an external source. The internal voltage VDL is an array voltage and is lower than the power supply voltage VEXT. The sense amplifier power circuit 7 supplies the power supply voltage to the common source power supply SAP/SAN of the sense amplifier (SA) 3 according to a sense amplifier enable signal SE.
A path exists for supplying the power supply voltage VEXT to the common source power supply SAP of a high voltage according to a sense overdrive signal (ODV or ODV2) during an overdrive period at the beginning of a sensing operation. A small voltage difference from the charge from a memory cell is sensed at the beginning of a sensing operation. In this case, in order to turn on a P-channel transistor in the sense amplifier (SA) 3, a high voltage is necessary as the high voltage power supply SAP. The high voltage exceeds a threshold voltage Vt of the P-channel transistor from the reference level of the internal voltage VDL/2. The high voltage power supply SAP is overdriven to be set to the power supply voltage VEXT to obtain the high voltage. After row address strobe (RAS) to column address strobe (CAS) delay (tRCD) LONG, i.e., after sufficient time has elapsed since the beginning of a sensing operation, amplification in the bit lines BIT T and BIT N by the sense amplifier (SA) 3 is almost completed, and the high voltage power supply SAP is again set to the VDL level, which is a predetermined voltage.
Various types of overdrive method exist for boosting the high voltage power supply SAP. For example, a type of overdrive method exists, in which the power supply voltage VEXT is connected to the sense amplifier power circuit 7 in FIG. 5 according to a sense overdrive signal (ODV2), as indicated by a dotted line. Moreover, another type of overdrive method exists, in which a node VDL of a VDL power circuit is overcharged according to a sense overdrive signal (ODV), and the voltage is supplied as the high voltage power supply SAP according to the sense enable signal SE. In the description of the present invention, the other type of overdrive method is used, in which an overcharge operation is performed. The write amplifier WAMP 6 has the circuitry shown in FIG. 4, and the power supply voltage VRW of the output driver is the power supply voltage VEXT supplied from an external source. Thus, the high and low levels of write data are VEXT and GND.
FIG. 6 shows the waveforms of successive write operations in the case of the tRCD LONG. FIG. 6 shows the waveforms of a word line WL, the sense overdrive signal ODV, the sense enable signal SE, a write enable signal WAE, column selection switches YSW, the node VDL, and the pair of the bit lines BIT T and BIT N. The node VDL is a node of the sense amplifier power circuit 7, which generates a voltage to be supplied to the high voltage common source SAP of the sense amplifier (SA) 3. When a selected word line is activated, a small voltage difference in a memory cell is detected in the pair of the bit lines that are precharged to the reference level VDL/2. The node VDL is overcharged according to the overcharge signal ODV.
A voltage is applied to the common source of the sense amplifier (SA) 3 according to the sense enable signal SE. At the beginning of a sensing operation, an overdrive operation is performed so that the power supply voltage VEXT is applied to the high voltage power supply SAP. The power supply voltage VEXT is higher than the internal voltage VDL. Thus, a sensing operation is performed quickly. FIG. 6 shows parts (indicated by full lines) of the pair of the bit lines BIT T and BIT N near the sense amplifier (SA) 3 and other parts (indicated by dot lines) of the pair of the bit lines BIT T and BIT N far from the sense amplifier (SA) 3. When amplification is almost completed in the parts of the pair of the bit lines BIT T and BIT N near the sense amplifier (SA) 3, the voltages of the node VDL and the high voltage power supply SAP are again set to the internal voltage VDL. Then, amplification is completed in the other parts of the pair of the bit lines BIT T and BIT N far from the sense amplifier (SA) 3.
Then, when the write enable signal WAE is activated, successive write operations are performed by the overdrive write method. The voltage VRW (in this case, VEXT), which is higher than the internal voltage VDL, and the ground voltage GND are respectively output as the high and low levels of write data from the write amplifier WAMP 6. When one of the column selection switches YSW selected according to the column selection signal is brought into conduction, write operations are performed on the sense amplifier (SA) 3, the pair of the bit lines BIT T and BIT N, and the memory cell. In this case, since the high level of the column selection signal is also the power supply voltage VEXT, a voltage of VEXT−Vtn is applied to a bit line. The voltage in the bit line is excessively boosted from the internal voltage VDL to VEXT−Vtn.
Since no path exists for discharging the charge, the more times successive write operations are performed, the more excessively the voltage in the bit line is boosted. The high voltage power supply SAP of the sense amplifier (SA) 3 is also boosted. In this way, the voltage in the bit line and the high voltage power supply SAP of the sense amplifier (SA) 3 are boosted from the internal voltage VDL to VEXT−Vtn. In FIG. 6, when the column selection switches YSW are sequentially selected and when the number of times successive write operation are performed increases, the voltage is boosted. When successive write operations are performed n times, the voltage is boosted to VEXT−Vtn. In this way, the bit line voltage is excessively boosted, so that the voltage in one of the complementary bit lines is boosted to VEXT−Vtn.
In a status in which the voltage in one of the complementary bit lines is boosted to VEXT−Vtn, write operations are completed, and a precharge operation is performed. However, since a precharge circuit does not include any path for discharging the charge, the voltage is excessively boosted to a voltage level that is equal to or more than the internal voltage VDL. In this status, in a precharge operation in which complementary bit lines are shorted, the reference level is set to a voltage level that is equal to or more than VDL/2. Thus, a correct reference level (VDL/2) cannot be obtained. When the voltage is not precharged to the correct level, the operation of the sense amplifier (SA) 3 becomes unstable, and this may cause an erroneous read operation. In order to obtain the correct precharge level, the voltage of a boosted bit line needs to be decreased to the VDL level to prevent the voltage in the bit line from being excessively boosted.
In FIG. 6, the waveforms of successive write operations in the case of the tRCD LONG are described. The tRCD LONG includes the tRCD plus a margin. Write operations may be performed after the tRCD LONG or tRCD MINIMUM.
(1) At the time when write operations are performed after the tRCD MINIMUM, the sense amplifier (SA) 3 is activated, and amplification is being performed in the other parts of the pair of the bit lines BIT T and BIT N far from the sense amplifier (SA) 3.
(2) At the time when write operations are performed after the tRCD LONG, sufficient time has elapsed since the sense amplifier (SA) 3 was activated. Thus, the voltage difference in the other parts of the pair of the bit lines BIT T and BIT N far from the sense amplifier (SA) 3 is also sufficient.
(1) Even in the case of the tRCD MINIMUM, the sense amplifier (SA) 3 is overdriven to reduce the tRCD. Since a voltage that is equal to or more than the internal voltage VDL is applied to the sense amplifier (SA) 3, the level that needs to be inverted by the write amplifier WAMP 6 is higher than the internal voltage VDL. Thus, in a write operation with the internal voltage VDL, it may be the case that the write amplifier WAMP 6 cannot invert the bit lines BIT T and BIT N sufficiently, which are amplified by the sense amplifier (SA) 3 operating in an overdrive mode, to write data. In this case, after a corresponding column selection switch YSW is closed, the voltage difference in the bit lines BIT T and BIT N in the sense amplifier (SA) 3 is not sufficient. Thus, subsequently, a delay occurs in the sense amplifier (SA) 3 (in a restore operation) and amplification in the bit lines BIT T and BIT N. Accordingly, a write operation by the overdrive method needs to be performed by the write amplifier WAMP 6. In the overdrive write method using the power supply voltage VEXT, a problem exists in that the bit line voltage is excessively boosted, as described above.
(2) In the case of the tRCD LONG, the operation is as described above. During the tRCD plus a margin, the write amplifier WAMP 6 is overdriven to quickly invert the bit lines BIT T and BIT N sufficiently amplified by the sense amplifier (SA) 3 to write data. In this way, when a write operation is performed after either the tRCD LONG or the tRCD MINIMUM, the write amplifier WAMP 6 is overdriven to achieve high-speed processing. However, in the overdrive write method using the power supply voltage VEXT, a problem exists in that the bit line voltage is excessively boosted.
In this way, in the overdrive write method using the power supply voltage VEXT, a problem exists in that the bit line voltage is excessively boosted when successive write operations are performed. Moreover, another problem exists in that, when the bit line voltage is excessively boosted, a correct reference level cannot be obtained in a precharge operation, thereby causing an erroneous operation of the sense amplifier (SA) 3. In International Publication No. WO97/24729 and Japanese Unexamined Patent Application Publication No. 10-255470, the problem that the bit line voltage is excessively boosted, which was found by the inventor, is not described and not recognized. Thus, no technique for solving the problem is suggested.
When successive write operations are repeated on the same word line, an overdrive operation is repeated on bit lines in which a sufficient voltage difference is generated by performing amplification. Thus, a problem exists in that the bit line voltage is excessively boosted. When the bit line voltage is excessively boosted, the voltage in one of the complementary bit lines is excessively boosted to a voltage that is equal to or more than the internal voltage VDL. In this status, after a precharge operation in which the complementary bit lines are shorted, a correct reference level cannot be obtained. Thus, a problem exists in that an erroneous operation of the sense amplifier may occur.

Overdrive write method, write amplifier power generating circuit, and semiconductor memory device including the same


Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for three-dimensionally stacked neural network accelerators. In one aspect, a method includes obtaining data specifying that a tile from a plurality of tiles in a three-dimensionally stacked neural network accelerator is a faulty tile. The three-dimensionally stacked neural network accelerator includes a plurality of neural network dies, each neural network die including a respective plurality of tiles, each tile has input and output connections. The three-dimensionally stacked neural network accelerator is configured to process inputs by routing the input through each of the plurality of tiles according to a dataflow configuration and modifying the dataflow configuration to route an output of a tile before the faulty tile in the dataflow configuration to an input connection of a tile that is positioned above or below the faulty tile on a different neural network die than the faulty tile.

This specification generally relates to three-dimensionally stacked neural network accelerators.
Neural networks are machine learning models that employ one or more layers of nonlinear units to predict an output for a received input. Some neural networks include one or more hidden layers in addition to an output layer. The output of each hidden layer is used as input to the next layer in the network, i.e., the next hidden layer or the output layer. Each layer of the network generates an output from a received input in accordance with current values of a respective set of parameters.
Typically, neural network processing systems use general purpose graphics processing units, field-programmable gate arrays, application-specific integrated circuits, and other hardware of the like to implement the neural network.

Yield improvements for three-dimensionally stacked neural network accelerators