A combined wall and door assembly includes a static wall assembly including a segmented support frame with a rectilinear shape. The static wall assembly further includes a plurality of transparent fiberglass panels directly coupled to the support frame and spaced along an entire longitudinal length of the support frame. The assembly further includes a mechanism for automatically biasing the access doors between open and closed positions when the subway train arrives and leaves a train terminal respectively such that passengers are prohibited from premature ingress and egress of the subway train during a schedule stop.

1. Technical Field
This invention relates to subway door assemblies and, more particularly, to a combined subway wall and door assembly for providing a safe passageway to ingress and egress a subway train from an adjacent platform.
2. Prior Art
The first subway, which began operating in 1863 in London, England, used steam locomotives. The subway was successful and it expanded, converting to electricity in about 1896. The first electric subway line in the United States opened in Boston, Mass., in 1897 to immediate success. New York City followed in 1904 with approximately nine miles of subway track. New York's subway system, is now one of the world's largest, covering hundreds of miles. Subways primarily serve highly populated metropolitan areas. Because of this core of passengers, subways have not been as challenged as other forms of mass transit to maintain their rider base during the past half-century. In addition, such systems are comparatively environmentally-sound and inexpensive to operate and their use helps mitigate traffic congestion. Although subways provide millions of individuals with an affordable and efficient way to commute, subways are inherently dangerous and many individuals are injured or killed each year. Most accidents result from individuals accidentally falling or intentionally jumping onto the rails, ahead of an oncoming subway. Although a few individuals survive, death is invariably the result of jumping in front of a fast-moving subway train, hurtling into the subway station at nearly 40 mph. Based on the above mentioned needs, it would be advantageous to provide a means for increasing public safety on subway platforms.
U.S. Pat. No. 6,926,462 to Fuganti discloses a safety barrier for road use that comprises a barrier element which can be displaced between an operative position, above the road surface, and an inoperative position, in which it does not substantially project above the road surface. Preferably provided is a number of sets of aligned barrier elements, rigidly connected to one another, the adjacent sets being connected together by articulated connecting structures which enable one set of barrier elements to be displaced between its inoperative position and its operative position without modifying the positions of the adjacent sets. In this way, one or more stretches of the barrier can be brought into the inoperative condition, leaving the adjacent stretches of barrier in the normal operative condition. Unfortunately, this prior art example does not prevent the specific dangers associated with subway platforms.
U.S. Pat. No. 6,056,038 to Foster discloses a safety barrier comprising a support, a partition frame hingedly connected to the support, and a retractable membrane attached to one end of the partition frame. The partition frame and the support can be extended across an opening, such as a doorway, to securely position the barrier within the opening. The partition frame includes a first member hingedly connected to the support and a second member slidingly engaged to the first member. The retractable member may be deployed toward an opposite end of the partition frame to close off the opening. Unfortunately, this prior art example does not automatically biased to an open position when it becomes appropriate for a user to enter the blocked opening.
U.S. Pat. No. 5,649,396 to Carr discloses a semaphore type loading dock safety barrier for use across a vehicle passageway to prevent accidentally driving a vehicle off the end of the loading dock. A barrier mount is attached to a guidepost inside the loading dock doorway and is horizontally rotatable about a vertical axis. A rigid barrier arm is rotatably affixed to the barrier mount so that the barrier arm raises and lowers vertically in a semaphore arm fashion. The barrier arm is typically constructed from an I-beam or box beam and is of sufficient strength to resist vehicle impact. A receiving rest is attached to an opposite guidepost inside the loading dock doorway and is horizontally rotatable about a vertical axis and positioned to receive the free end of the barrier arm. The receiving rest has locking means on the receiving rest to lock the free end of the barrier arm in the receiving rest so that upon vehicle impact with the barrier arm deformation of the barrier arm and rotation of the barrier mount and receiving rest about their respective vertical rotation axes occurs while retaining the barrier arm in a locked relationship with the receiving rest. Unfortunately, this prior art example does not prevent the specific dangers associated with subway platforms.
Accordingly, the present invention is disclosed in order to overcome the above noted shortcomings. The present invention is convenient and easy to use, durable in design, and designed for providing a safe passageway to ingress and egress a subway train from an adjacent platform. The present invention is simple to use and designed for many years of repeated use.

Combined subway wall and door assembly and associated method


The present invention generally relates to methods and compositions for preventing or treating axonal and/or neuronal degeneration in a subject by administering a composition comprising a peptide that comprises the amino acid sequence Arginine-Glycine-Aspartate (RGD).

Neurodegenerative disorders are hereditary and sporadic conditions which are characterized by progressive nervous system dysfunction. These disorders are often associated with atrophy of the affected central or peripheral structures of the nervous system. They include diseases such as Alzheimer's Disease and other dementias, Brain Cancer, Degenerative Nerve Diseases, Encephalitis, Epilepsy, Genetic Brain Disorders, Head and Brain Malformations, Hydrocephalus, Stroke, Parkinson's Disease, Multiple Sclerosis, Amyotrophic Lateral Sclerosis (ALS or Lou Gehrig's Disease), Huntington's Disease, Prion Diseases, polyneuropathy, and others. Interventions include preventative measures, lifestyle changes, physiotherapy or other therapy, neuro-rehabilitation, pain management, medication, or operations performed by neurosurgeons (WHO Neurological Disorders: Public Health Challenges, 2006).
Axonal degeneration is a common hallmark of many neurodegenerative diseases. A longstanding clinical observation is the tendency for demyelinated nerve fibers to undergo degeneration and loss. There is now a wealth of evidence that demyelination contributes to altered axonal transport, axonal degeneration, and loss (de Waegh et al., 1992; Trapp et al., 1998; Coleman and Perry, 2002; Ciccarelli et al., 2003; Oh et al., 2004). Examples include heritable demyelinating diseases of both the CNS and PNS. Many of the genetic defects in these diseases are abnormalities in genes encoding intrinsic myelin proteins and not expressed in axons. The clinical manifestations are often attributable to progressive, distally predominant axonal degeneration (Berciano et al., 2000; Krajewski et al., 2000).
The myelin-associated glycoprotein (MAG) is a component of all myelinated internodes. MAG is a transmembrane glycoprotein containing five Ig-like domains in its extracellular domain. It is an adhesion molecule belonging to the immunoglobin superfamily. MAG is distinctively located in the adaxonal plasmalemma that apposes the axon as well as the paranodal loops, Schmidt-Lanterman incisures, and mesaxons (Trapp and Quarles, 1982). The normal role of MAG is not well understood. MAG is not necessary for myelination, and myelin sheaths of MAG knock-out mice (MAG−/−) are largely normal (Yin et al., 1998). Its distribution has prompted the hypothesis that MAG prevents compaction of myelin membranes and contributes to the uniform intermembranous distance characteristic of the periaxonal space (Trapp and Quarles, 1982). MAG is known to signal to the axon, locally influencing the phosphorylation of axonal neurofilaments immediately beneath MAG-bearing membranes because of reduced interfilament spacing (Hsieh et al., 1994; Dashiell et al., 2002). Myelinated axons of MAG−/− mice have smaller diameters than normal as a result of hypophosphorylation of the neurofilament proteins NF-H and NF-M (Garcia et al., 2003; Rao et al., 2003).
Much of the published research on MAG has focused on its ability to inhibit axonal growth and elongation during regeneration. Multiple axonal receptors have been proposed to mediate MAG-induced growth cone collapse. One is a multicomponent complex consisting of a ligand-binding Nogo-66 receptor (NgR) and two transmembrane coreceptors, LINGO-1 and either p75 or TROY (Fournier et al., 2003; Mi et al., 2004). A second is proposed to be gangliosides GD1a and GT1b. Interaction of MAG with axons involves at least two recognition sites on MAG: one around arginine 118 (R118) in Ig domain 1 and second in Ig domains 4 and 5 (Kelm et al., 1994; Tang et al., 1997; Cao et al., 2007). Whereas Ig domains 4 and 5 are believed to be important for the interaction with NgR, the R118 binding site is thought to involve in interactions with gangliosides. Other roles of MAG at the R118 binding site remain unclear.
MAG−/− mice develop axonal loss in the CNS and PNS (Yin et al., 1998; Pan et al., 2005) suggesting that MAG may influence axonal maintenance. A recent study indicated that MAG promotes axonal stability and survival in cell culture and in vivo (Nguyen et al., 2009). This study showed that MAG signals to the axon to promote stability of axonal microtubules, and promotes axonal survival in the face of insults such as vincristine, acrylamide, and inflammatory mediators. The effect of MAG on axonal stability is independent of Nogo signaling in the axon and depends on the arginine 118 residue in the RGD (Arginine-Glycine-Aspartate) domain of the extracellular segment of the molecule. An R118-mutated MAG failed to prevent axonal degeneration caused by vincristine. This suggested that MAG-induced axonal protection depends on the functional binding site around arginine 118.
Despite the axon protective abilities of MAG, its potential as a candidate drug in the treatment of neurodegenerative disorders is limited due to its high molecular weight which makes it unable to cross the blood-brain barrier in patients. There continues to be a pressing need in the art for novel therapies and molecules that exhibit neuronal and axonal protective effect and are effective in vivo, crossing the plasma membrane and the blood-brain barrier.

Methods and compositions for the treatment of axonal and neuronal degeneration


A pedal system for an aircraft comprising a pedal and a pedal mounting mechanism is provided. The pedal is configured for manipulation through at least one operational degree of freedom by a pilot to provide control inputs to the aircraft. The pedal mounting mechanism is configured for supporting the pedal within a cockpit of the aircraft for manipulation by the pilot. The pedal mounting mechanism provides at least two adjustment degrees of freedom for adjusting the position of the pedal within the cockpit.

Pedals in aircrafts are manipulated by a pilot's legs to control some aspect of the aircraft, such as for example the rudder or breaks of the aircraft. Currently, pedals have a single degree of freedom of adjustment within the cockpit to adjust for pilot comfort and optimal operating position. There are two typical philosophies related to adjustment of the pedals.
The first philosophy requires that the pedals remain substantially at a fixed distance above the floor of the cockpit. Typically, the adjustability will only be toward and away from the pilot's seat. In this configuration, the pilot's heel will be able to rest on the floor while at the same time the arch of the pilot's foot rests on the cylindrical part of the pedal no matter the position of the pedal.
The second philosophy transitions the pedals away from the floor as the pedals are adjusted aft (i.e. toward the pilot's seat). This philosophy is based on the assumption that the shorter pilot will have the seat raised and thus needs the pedals higher and closer to his body. Adjustment may also require rotation of the pedal toes in the forward motion direction (i.e. away from the seat) as the pedals move toward the seat to accommodate the shorter pilot's more vertical attitude.
Another problem with pedals in an aircraft is that the pedals are only used for a very small percentage of the total aircraft flying time. However, the pedals take up a large portion of the leg space in the cockpit causing discomfort for the pilot when the pedals are not in use.
The present invention provides improvements over the current state of the art of pedals for aircrafts.

Multiple degrees of translational adjustment pedals


A lens driving device includes a stator, a rotor magnetized to have a plurality of poles, an arm fixed to the rotor in such a manner as to be rotatable together with the rotor, a moving member for rectilinearly moving a lens in response to a rotation of the arm and a coil for causing the stator to generate a magnetic flux to rotate the rotor.

1. Field of the Invention
The present invention relates to a driving device and an optical apparatus, such as a camera, having the driving device.
2. Description of the Related Art
Conventionally, stepping motors have been employed as driving means for driving lenses.
However, such a conventional arrangement has the following problem.
In general, a stepping motor involves unique variations in rotating torque (torque ripples) during a stepping operation. If the stepping motor is rotated, the driving part of the stepping motor produces a vibration, and this vibration is transmitted to a lens holding member and the like and causes the problem of producing noise.
There is also a device which is arranged to move a lens barrel, which is a driven object, along the optical axis by means of a voice coil motor to detect the position of a moving lens by means of a magneto-resistance element.
Since this driving device is of a so-called direct drive type, the noise problem can be solved, but a weight to be moved becomes the total of the weight of the lens barrel which is a driven object and the weight of a movable portion of the voice coil motor. As a result, a thrust force stronger than the thrust force required to move the lens barrel is needed, so that a voice coil motor of a large size must be prepared or a large electric power is needed.


A seismic detector for boreholes is described that has an accelerometer sensor block for sensing vibrations in geologic formations of the earth. The density of the seismic detector is approximately matched to the density of the formations in which the detector is utilized. A simple compass is used to orient the seismic detector. A large surface area shoe having a radius approximately equal to the radius of the borehole in which the seismic detector is located may be pushed against the side of the borehole by actuating cylinders contained in the seismic detector. Hydraulic drive of the cylinders is provided external to the detector. By using the large surface area wall-locking shoe, force holding the seismic detector in place is distributed over a larger area of the borehole wall thereby eliminating concentrated stresses. Borehole wall-locking forces up to ten times the weight of the seismic detector can be applied thereby ensuring maximum detection frequency response up to 2,000 hertz using accelerometer sensors in a triaxial array within the seismic detector.

In the oil and gas industry, numerous techniques of determining the geological structure of formations in the earth have been developed. One of the most common techniques is called "vertical seismic profiling" (VSP). This method is used to obtain information concerning a formation of interest. Typically, this technique requires the lowering of a geophone into a wellbore while providing at the surface seismic energy sources such as a dynamite charge. The explosion of the dynamite charge creates a seismic wave which is detected by the geophone located in the wellbore.
Another technique that is used is reverse vertical seismic profiling (RVSP) where numerous geophones are located on the surface and a dynamite charge or other energy source is activated in the borehole. By using these types of well known methods, subterranean formations can be probed with seismic waves to delineate their structure and physical properties. These conventional VSP and RVSP methods typically operate using seismic waves in the frequency range of 10-200 hertz and are capable of resolving structural details having dimensions of about 15-20 meters or larger.
In order to obtain improved resolution of underground geologic structures, the VSP and RVSP methods must be capable of operating at seismic wave frequencies up to about one order of magnitude higher than the conventional methods. However, one of the common problems with conventional seismic detectors is that their low-frequency design attributes are inappropriate for high-frequency measurements up to 2,000 hertz. To detect frequencies over the entire range, the seismic detector needs to be approximately the same density as the formation being measured and must be held in place in such a manner that it appears to be part of the formation itself. Some examples of seismic borehole devices can be found in U.S. Pat. No. 4,845,990 to Kitzinger, U.S. Pat. No. 4,715,470 to Paulsson, and U.S. Pat. No. 4,702,343 to Paulsson. However, the devices as described in each of these patents are not suitable for operating over a frequency range of 200 to 2,000 hertz because the devices are considerably heavier than the mass density of the geological formations in which they must operate. For such a heavy device to be held in position by the formation, the borehole clamping mechanism causes concentrated stresses at the points of contact with the geological formation. Concentrated stresses impose borehole resonance effects which distort the signal being received.
It is also important to know the azimuthal orientation of the seismic waves being detected. None of the patents described have an azimuthal orientation means for determining the direction from which the signal may originate. Directional orientation has been used in other types of downhole devices such as shown in U.S. Pat. No. 4,923,030 to Meynier and U.S. Pat. No. 3,614,891 to Nolte. However, neither of these devices pertain to probes intended to be oriented first and then clamped into place in a borehole for seismic detection.
High resolution seismic measurements have been used in characterizing the physical properties of rock, geological structure, and fluid migration pathways in oil and gas reservoirs by using seismic source and detector devices capable of operating over the frequency range of 200 to 2,000 hertz. Several seismic source transducers designed for borehole operation are available for this high resolution application. For example, borehole hydrophones have been used as detectors because of their useable frequency response up to 2,000 hertz and higher. Hydrophones generally provide a wideband frequency response to the incident seismic waves, but, because of the indirect nature of their response (i.e. scalar-pressure response to motional displacements of the borehole wall), the output signal does not contain information on the vector seismic displacement of the formation the borehole.
An important requirement in seismic characterization of oil and gas reservoirs is to detect and resolve the direction of the propagating wavefronts of both compressional and shear waves arriving at the detector. In the case of shear waves, the polarization orientation of the detected shear waves must be resolved. Hydrophone detectors, although indirectly responsive to incident shear waves, are not capable of providing a quantitative response indicating the vector of the seismic wavefront or the polarization of the shear wave motional displacements. Therefore, a seismic detector capable of accurately and directly sensing the three-dimensional motional displacement of the borehole wall is needed. The requirements for this type of seismic detector may be met by the use of three vector type sensors such as geophones or accelerometers aligned along orthogonal axes and mounted in a rigid borehole probe which can be temporarily clamped into place. This will allow the detector to be responsive to the three-dimensional seismic motions of the drilled formation.
Previous forms of borehole wall-locking seismic detector probes have consisted of a combination of one or more seismic detector elements; typically velocity sensitive geophones combined with one or more clamping arms which serve to hold the probe against the borehole wall for measurements. The clamping arms may be electrically or hydraulically driven. These types of probes have been relatively heavy, consisting of a pressure-resistant housing and a high-force mechanical clamping mechanism. In these prior devices, their inertial mass and self-contained compliant locking arm comprise a resonant structure that has prevented their use as three-component seismic detectors at frequencies above about 300 hertz. This creates spurious transverse resonances at frequencies above about 300 hertz, depending upon the particular design characteristics of the detector under consideration. Moreover, the geophone detector elements widely used for such seismic measurements typically exhibit a transverse (cross-axis) sensitivity in the range of 10-15 percent of the primary axis sensitivity.
Smaller and lighter weight borehole wall-locking seismic detectors are needed to overcome these limitations and to provide three-component seismic measurements for high resolution applications primarily in the frequency range of 200 to 2,000 hertz.

Three-component borehole wall-locking seismic detector


In a method of forming a pattern, a mold layer having an opening is formed on a substrate. A conductive layer is formed on the mold layer having the opening, the conductive layer having a substantially uniform thickness. A buffer layer pattern is formed in the opening having the conductive layer, the buffer layer pattern having a cross-linked structure of water-soluble copolymers including a repeating unit of N-vinyl-2-pyrrolidone and a repeating unit of acrylate. An upper portion of the conductive layer exposed over the buffer layer pattern is etched. Accordingly, a conductive pattern for a semiconductor device is formed on the substrate. The method of forming a pattern may simplify manufacturing processes for a capacitor and a semiconductor device, and may improve their efficiencies.

1. Field of the Invention
Example embodiments of the present invention relate to a method of forming a pattern and a method of manufacturing a capacitor using the same. More particularly, example embodiments of the present invention relate to a method of forming a conductive pattern using a buffer layer pattern and a method of manufacturing a capacitor using the method of forming a conductive pattern.
2. Description of the Related Art
Generally, a capacitor employed in an electronic device, for example, a dynamic random access memory (DRAM) device, includes a lower electrode, a dielectric layer, and an upper electrode. In order to improve a capacitance of a memory device having the capacitor, it is important to improve an electric capacitance of the capacitor.
Recently, an area of a unit cell of the DRAM device has been reduced as integration of the DRAM device has been increased to have a giga-size. Thus, the capacitor having a flat shape has been manufactured so as to have a great capacitance. However, the shape of the capacitor has been gradually changed into a box shape or a cylindrical shape in order to have a relatively higher aspect ratio.
The cylindrical capacitor includes a lower electrode having a cylindrical shape. A buffer layer pattern may be used in a node-separation process for forming the lower electrode having the cylindrical shape, and examples of a material that may be used for the buffer layer pattern may include an oxide, a photosensitive material, etc.
In order to form a buffer layer pattern including an oxide, the buffer oxide layer is formed through an oxide deposition process, and then the buffer oxide layer is etched through an etch-back process or chemical mechanical polishing process. Accordingly, the process of forming the butter layer pattern requires a relatively long duration of time for the deposition process and the etching process. Additionally, a void may be formed in the buffer layer pattern. An atomic layer deposition process is employed to form a buffer layer pattern without the void.
In order to form the buffer layer pattern including the photosensitive material, a photoresist film is formed. Thereafter, an exposing process, a developing process using a developing solution, a cleaning process, and a baking process are sequentially performed on the photoresist film. Thus, high cost exposure devices are needed for forming the buffer layer pattern. Furthermore, a baking process hardening the photoresist film at a temperature higher than about 270° C. is essentially needed. The photoresist film hardened through the high temperature baking process may not be easily removed through a plasma ashing process.
The lower electrode of the buffer layer pattern may be damaged while the ashing process and the cleaning process are performed. Furthermore, the buffer layer pattern is not easily removed by a conventional ashing process, and a residue of the buffer layer pattern remaining in an opening may serve as a resistance to cause malfunction of the capacitor. In order to improve an efficiency of the ashing process for removing the buffer layer pattern, an oxygen plasma ashing process may be performed at a high temperature of about 150° C. to about 250° C. However, the high temperature ashing process may deteriorate and/or oxidize the lower electrode so that the capacitor does not have a desired electric capacitance.

Method of forming a pattern and method of manufacturing a capacitor


A multi-plate clutch (2) having a first plate carrier (48) and second plate carrier (50) and one or more first plates (52) received by the first plate carrier and one or more second plates (54) received by the second plate carrier, a pressure element (58) which can especially be actuated hydraulically for generating an axial load on the clutch pack configured by the first and second plates and closing the multi-plate clutch, in which the pressure element configuring the second plate carrier and/or being connected to the second plate carrier in a rotationally fixed manner.

Multi-disk clutches which comprise a first disk carrier and a second disk carrier, which is disposed rotatable about a rotation axis relative to the first disk carrier, are well-known. Thus, a plurality of first disks are non-rotatably received and axially moveable at the first disk carrier and plural second disks are non-rotatably received and axially moveable at the second disk carrier. Thus, the first and the second disks typically alternate in axial direction. Furthermore a multi-disk clutch is known, which is provided with a press component configured as a piston, which can be actuated hydraulically and which can load the disk packet in axial direction, which is formed from the first and second disks in order to lock the multi-disk clutch, so that a torque is transferable between the first disk carrier and the second disk carrier through the first and second disks. In the known embodiments, the piston is disposed axially moveable relative to the first disk carrier and also relative to the second disk carrier. A force opposite to the loading of the piston is imparted, in known embodiments, by a press plate and/or by a retaining ring, which is disposed on the side of the disk packet opposite to the piston and engages the first disk carrier in an axially fixated manner.
A hydrodynamic torque converter transmission device comprising a multi-disk clutch of the type is shown, e.g., in Figure of German Patent No. DE 103 52 963 A1. The hydrodynamic torque converter device shown therein comprises a converter torus formed by a pump shell, which is not illustrated, a stator shell, which is partially illustrated and a turbine shell, which is partially illustrated, as it is shown on right in the portion of the break line. The torque converter device furthermore comprises a torsion vibration damper, which comprises a first energy accumulator means, which comprises first energy accumulators. Furthermore, the torque converter device illustrated in the figure comprises a converter lock up clutch, which is the multi-disk clutch. The torque converter-transmission device furthermore comprises a converter housing, which is non-rotatably coupled to a shaft on the input side.
In the converter housing, the converter torus, the torsion vibration damper and the converter lock up clutch are received. The first disk carrier of the multi-disk clutch, which forms the converter lock up clutch, is integrally formed with the converter lock up clutch housing. The second disk carrier is non-rotatably coupled to an input component, which is, in particular, a flange, or which is formed by a plate of the torsion vibration damper, or it forms the input component of the torsion vibration damper. The piston of the converter lock up clutch, as discussed above, is disposed axially moveable relative to the first disk carrier and relative to the second disk carrier. When the converter lock up clutch is closed, a torque imparted through the converter housing transfers through the converter lock up clutch and the input component into the first energy accumulator means and through an output component, which is a flange, in particular, or which is formed by a plate of the first energy accumulator means and a hub, into a shaft on the output side. When the converter lock up clutch is completely open, torque transfers through the converter torus and is transferred from an output side extension of an outer turbine dish to a second input component of the torsion vibration damper, which is attached to the input component.
From there, the torque is transferred through the first energy accumulator means and the output component to the hub, and from there, to the shaft on the output side. In the configuration illustrated in FIG. 1 of DE 103 52 963 A1, the piston is disposed on the side of the disk packet formed by the disks of the multi-disk clutch, wherein the side is axially opposed to the first energy accumulator means. Since the piston is radially supported on the inside at this location, the disposition of the piston at this location is essentially required, otherwise the connection between the second disk carrier and the input component could not be created, or the second disk carrier could not be non-rotatably connected to the input component of the torsion vibration damper. Furthermore, in this configuration of a torque converter device, a pressure plate or a retaining ring is essentially required, which engages the first multi-disk carrier fixated in axial direction, and which is disposed on the side of disk packet facing away from the piston, in order to impart an opposite force against the piston force when locking the clutch, thus facilitating a friction locked connection of the disks.

Multi-plate clutch and hydrodynamic torque converter device having said multi-plate clutch


According to the invention, at least one end of the elevator ropes (8) is fixed to a guide rail (4,7) of the elevator. According to an embodiment of the invention, the whole elevator is so suspended by its ropes (8) that all vertical forces are transmitted by the guide rails (4 . . . 7) to the bottom (27) of the shaft (1). The invention provides the advantages that the elevator is easy to install and that the ical forces are transmitted by the guide rails (4 . . . 7) to the bottom (27) of the shaft (1), permitting a lighter construction of shaft walls.

The present invention relates to an arrangement for fixing the elevator rope in an elevator and to an arrangement for the use of guide rails as supporting elements of an elevator and its equipment.
In traction sheave elevators, the ends of the elevator ropes are conventionally fixed to the elevator shaft or to anchorages in a machine room in the upper part of the elevator shaft. The other ends of the elevator ropes are usally fixed by means of springing elements. Similarly, the diverting pulleys of an elevator are typically mounted in the elevator shaft or in the machine room, but diverting pulleys mounted on an elevator guide rail are also known.
Previously known solutions for the fixing of elevator ropes have the drawback that the elevator ropes require a strong anchorage in the building and that the position of the anchorage in relation to the building, elevator, elevator shaft, elevator machinery and diverting pulleys must be closely defined. Therefore, fixing the elevator ropes by known techniques requires a long installation time because a holding element for a rope fixing element has to be installed first in the elevator shaft or machine room.


A cascode I/O driver is described that includes a barrier formed in the shared region between the two transistors. The barrier region allows the I/O driver to be designed to primarily meet I/O requirements. Accordingly, improved operating speeds are achieved. An system is described that includes an I/O driver in parallel with an ESD device. In an embodiment, the I/O driver may assist the ESD device in discharging electrostatic, after the ESD begins conducting.

An IC chip electrically communicates with off-chip electronics to exchange information. The IC chip may employ a different voltages than are employed by off-chip electronics. Accordingly, the interface between the IC chip and off-chip electronics must accommodate the voltage differences. One such interface includes a mixed voltage input/output ("I/O") driver as discussed in ESD Protection For Mixed-Voltage I/O Using NMOS Transistors Stacked In A Cascode Configuration, by Warren Anderson and Davis Krakauer and published in EOS/ESD Symposium 98-55, herein incorporated by reference. FIGS. 2 and 3 of this publication show an ESD protection structure including two NMOS transistors in a cascode configuration, where the transistors are merged into the same active area of a substrate. The two NMOS transistors allows a 5V signal to be dropped to 3.3V during normal operation while providing a parasitic lateral NPN bipolar transistor during electrostatic discharge. Under ESD conditions, the stacked transistors operate in snapback with the bipolar effect occurring between the source of the bottom NMOS transistor and drain of the top NMOS transistor. While this I/O driver has been used for some generic designs, it has been a continuing challenge to balance electrostatic discharge protection performance and I/O performance. Accordingly, it is desired to improve upon the performance of a cascode MOS driver. More specifically, there is a need to remove the ESD design constraints from drivers to achieve maximum I/O performance.

Cascode I/O driver with improved ESD operation


An analog circuit includes a pulse control circuit for outputting pulse signals for operating component circuits based on reference pulse signals for driving an image sensor, a noise reduction circuit that is operated in accordance with a pulse signal of a horizontal drive frequency output from the pulse control circuit to reduce noise present in image signals output from the image sensor, a gain variable amplifier for adjusting an amplitude of signals output by the noise reduction circuit, an AD converter for converting the output signals of the gain variable amplifier into digital signals and output these digital signals, a clamp circuit that is operated in accordance with a pulse signal at a horizontal drive frequency output from the pulse control circuit to perform feedback control of the digital signals output by the AD converter, and a frequency-dependent bias circuit that supplies a current amount corresponding to the frequency of at least one kind of pulse signal from among the reference pulse signals and the pulse signals that are output from the pulse control circuit. The analog circuit is operated at a sufficient current amount required for the processing of signals from various image sensors having different horizontal drive frequency specifications.

1. Field of the Invention
The present invention relates to circuits for analog processing the signals output from image sensors such as CCD (Charge Coupled Device) area sensors and CMOS sensors, and imaging apparatuses provided with the same.
2. Description of the Related Art
FIG. 8 shows an example of a conventional analog circuit 10 for analog processing the output signals of an image sensor (see for example JP 2000-270267A and JP 2001-36358A). The analog circuit 10 is made of a noise reduction circuit 3 that receives signals output by a CCD 2, a gain variable amplifier 4 that receives signals output by the noise reduction circuit 3, an AD converter 5 that receives signals output by the gain variable amplifier 4 and converts them into digital signals that it outputs, a clamp circuit 6 for performing feedback control with respect to the digital signals output from the AD converter 5, a pulse control circuit 7 that supplies pulses for operating these component circuits, and a bias circuit 9 for supplying current to the noise reduction circuit 3, the gain variable amplifier 4, and the AD converter 5.
Four pulses are input to the pulse control circuit 7, namely a signal sampling pulse A for sampling the video period in the signals for each pixel at the horizontal drive frequency of the CCD, a reference sampling pulse B for sampling the reference voltage period in the signals for each pixel at the horizontal drive frequency, an AD converter pulse C for conversion to digital for each pixel at the horizontal drive frequency, and a clamp pulse D for fixing the DC voltage of the signals at the horizontal drive frequency. The pulse control circuit 7 creates and outputs various pulses for operating the other component circuits based on these pulses.
The noise reduction circuit 3 is operated in accordance with a pulse at the horizontal drive frequency that is output from the pulse control circuit 7 and reduces the noise in the output signals from the CCD 2. The gain variable amplifier 4 is operated in accordance with a pulse at the horizontal drive frequency that is output from the pulse control circuit 7 and adjusts the amplitude of the output signals of the noise reduction circuit 3 by altering the gain. The AD converter 5 is operated in accordance with a pulse at the horizontal drive frequency that is output from the pulse control circuit 7 and converts the output signals of the gain variable amplifier 4 into digital signals that it outputs. The clamp circuit 6 is operated in accordance with a pulse at the horizontal drive frequency that is output from the pulse control circuit 7 and performs feedback control such that the signal data of the reference period in the digital signals output from the AD converter 5 are identical to data that have been set freely.
The horizontal drive frequency, which is the repeat frequency of the signals output from the CCD 2, spans a wide range from several MHz to several 10 MHz due to the specifications for the number of pixels and the number of frames per second serving as video signals. The noise reduction circuit 3, the gain variable amplifier 4, and the AD converter 5 require a large amount of current if the horizontal drive frequency, which is the repeat frequency of the signals output from the CCD 2, is high, but are capable of operating adequately at less current if the horizontal drive frequency is low.
On the other hand, the output bias current, which is the current supplied to the noise reduction circuit 3, the gain variable amplifier 4, and the AD converter 5 from the bias circuit 9 of the conventional analog circuit 10 shown in FIG. 8, stays constant regardless of the frequency of the signals output from the CCD 2 that are to be processed. It is thus necessary that the current amount is set such that it is possible to process the output signals of a CCD 2 with the highest horizontal drive frequency specification that can be adopted. Consequently, a current amount that is greater than necessary is used if a CCD 2 with a lower horizontal drive frequency specification whose output signals can be processed with a smaller current amount is employed as is. Alternatively, it becomes necessary to redesign for a separate bias circuit that supplies a smaller current amount that is sufficient for this operation.
However, sending more current than is necessary shortens the charge life of the battery in battery-driven portable devices. Also, redesigning for a separate bias circuit results in an increase in the design time that is required to match the specifications of the CCD camera, for example.

Analog circuit for processing output signal of image sensor and imaging apparatus using the same

Matsushita Electric Industrial Co., Ltd.


A flexible measuring tape is extended from a predetermined location on a face a predetermined distance to a location on a scalp. A 2 cm by 2 cm square bundle of hair about that location is isolated. The bundle of isolated hair is captured in a slit in a two-part cartridge, one part being slidable in the other part about a changeable length slit 1 mm wide. The cartridge is placed in an “L” shaped end of a plunger extending from a first end of a body of a measuring device. The plunger is drawn into the body of the device to compress the hair in the changeable length slit as the two parts of the cartridge are pushed together between an end of the “L” and the first end of the body. A spring is provided on the plunger between a second end of the body of the device and an inner end of a knob at an outer end of the plunger. The spring applies the same load regardless of the bundle's size and urges the “L” shaped end toward the body to compress the bundle of hair and the amount of compressed hair is read off of a gauge as DDI, Density-Diameter Index, which represents the cross-sectional area of the compressed bundle of hair. After the measurement is made, the smaller part is pulled part way out of the larger part of the cartridge so the cartridge easily can be pulled off of the bundle of hair and discarded.

1. Field of the Invention
The present invention relates to a method, device and a two piece cartridge for measuring fluctuations in the cross sectional area of a bundle of hair for the purpose of documenting the clinical course of medical hair loss disorders and the effectiveness of hair growth treatments and/or for the purpose of indirectly calculating the severity of balding disorders or efficacy of hair growth treatment as evidenced by a decrease or increase in hair population and/or hair shaft diameter.
2. Description of the Related Art
Heretofore, a hair volume-measuring device used for measure of hair damage was disclosed in the Kabacoff et al. U.S. Pat. No. 4,665,741.
Also, see the hair measurement methods disclosed in "Current and Novel Methods for Assessing Efficacy of Hair Growth Promoters in Pattern Hair Loss" in J. Am. Acad. Dermatol, 2003; 48:253–62.
Hair shedding is a condition characterized by loss of hairs of normal-sized diameters. It is one of the two major categories of hair loss. Shedding is diffusely distributed over the scalp and may be the sign of several medical abnormalities and toxicities. It may physiologically follow high fever, cessation of birth control pills, or childbirth. Shedding is characterized by the appearance of skin on the scalp where hair was once present. Shedding may be quantified by measuring the density of hairs present in an area of one-centimeter square of scalp. Hair density usually is measured by closely cutting the scalp hair (about 2 mm long in an area 5 mm×5 mm) and then counting the remaining cut hairs present on the scalp and multiplying that value times 4. The hair density of normal individuals in the absence of shedding ranges between 120 to 200 hairs per sq cm of scalp.
Hair thinning is a condition characterized by the gradual miniaturization of individual scalp hairs. It is the second major category of hair loss, and by far the more common. The appearance of hair loss is the result of decreasing diameters resulting in the eventual absence of hairs. Thinning (like shedding) also is characterized by the appearance of skin on the scalp where hair was once present. Thinning affects an estimated 75% of men and 10% of women. Unlike shedding, it is not diffuse in its distribution over the entire scalp surface, but almost always appears in a pattern, with hair loss on the top of the scalp. Thinning characteristically spares the posterior and sides of the lower scalp, (see Zone 10 as pictured in FIG. 19) creating a familiar horse-shaped fringe that persists in spite of the most advanced cases.
Thinning occurs in healthy individuals and is referred to as balding, pattern balding, male or female pattern alopecia, androgenctic alopecia, male or female pattern balding. It is considered normal in 75% of men. And, although it may occur in healthy women, it may indicate an endocrine abnormality in a small group of women.
Early pattern balding is difficult to recognize and difficult to quantify. Simple density measurements (as performed in shedding) are of little value because there is a mixed population of both normal-sized and miniaturized hairs. When density counts are performed, a normal and miniaturized hair would each be counted as one hair. Therefore, in order to detect and quantify thinning in a meaningful manner, the actual hair mass (the collective cross sections of hair from a pre-determined area of scalp) must be measured. This alone would reflect the density of hairs and the array of mixed diameters that are present.
In order to quantify pattern and diffuse hair loss, scientists have commonly used three basic methods:
1. Hair density count or target-area hair count
2. Clinical photography
3. Hair weight.
Quantification of hair loss by measuring the collective cross sections in a pre-determined area of scalp has not been reported in the scientific literature nor disclosed in prior U.S. Patents.
The three commonly used methods are described in more detail below:
Density count or target-area hair count. The density of closely cropped hair in an area of scalp is compared to a known normal range of values, which are 150 to 250 hairs per sq cm. To determine if a hair growth product is efficacious, before and after treatment evaluations are performed. To determine the percent loss of density of a single individual, the density on the top part of the scalp (the area of loss) may be compared to the density on the lower back and sides (the normal and permanent hair zone). The percent hair loss is calculated by dividing the hair count in the hair loss area by the hair count in the permanent zone.
This method is quite imprecise in conditions of thinning, because it measures only the number of hairs and makes no allowance for their variations in diameter. The method is used in a simple office setting because it is a bit more precise than clinical photography. It requires closely cropping the hair and directly examining the scalp exam with a hand lens or video microscope. The method may be brought to a higher level of precision if macrophotographs of the area are taken and enlarged and then only the hairs above a certain diameter (usually 40 microns) are counted.
Clinical photography: Photography is performed comparing the patient's hair loss area to the permanent zone. It may also compare the patient's hair loss zone to a picture of the same zone of a patient with no hair loss, or of a prior or subsequent state of loss in the same patient. To determine if a hair growth product is efficacious, before and after treatment evaluations are performed. In this manner, the growth or loss is grossly quantified by visual observation alone. No insight is gained into whether or not the hair loss is the result of thinning or shedding. Photography is quite imprecise and obscured by various hairstyles and hair lengths. It is however the most common form of hair loss documentation because it is rapid, requires not special training and is easily archived. It requires the cutting of hair to a uniform length, standard photo equipment lighting, and care positioning of the subject, to yield any kind of comparable data.
Hair weight: A small area of hair (usually 5 mm×5 mm) is shaved from a balding area. The patient returns in 30 days and the newly grown hair is cut and weighed. To determine if a hair growth product is efficacious, before and after treatment evaluations are performed. In cases of pattern loss, the procedure may be performed in the permanent zone (lower posterior and lateral horseshoe shaped zone) and compared to the value in the thinning zone of the same patient. The percent hair loss may be calculated by dividing the hair weight in the thinning area by the hair weight in the permanent zone. Hair weight is a very precise method of measuring hair loss because it considers both the number of hairs and their diameters and the hair length in its calculation. Its disadvantage is that the sample size represents a relatively small sample of the scalp surface, but because it measures hair length as well, it may not be as meaningful as thought.
Furthermore it is a very tedious process, requiring strict humidity controls, and is impractical to perform in a clinical setting. It also requires cutting off hair. It is used primarily by commercial laboratories to measure the effectiveness of hair-growing preparations i.e. finasteride, dutasteride, and minoxidil.

This patent is subject to a terminal disclaimer.

Method, device and cartridge for measuring fluctuations in the cross-sectional area of hair in a pre-determined scalp area


A personal scheduler is proposed. The scheduler is used to define tasks, each one consisting of an activity to be performed by a defined deadline at a specific location, and appointments, each one consisting of an activity to be performed at a precise time at a specific location. The scheduler warns the user whenever s/he passes close to the location of each task. Moreover, at the morning the scheduler reminds all the tasks that might be performed during the day, according to an expected traveling path of the user based on the appointments to be attended.

Several mobile data processing devices have been proposed in the last years for aiding a user to perform a number of activities. For example, so-called organizers have become very popular for specific applications; typically, these devices are used as a phone book, a calendar, an alarm clock, a scheduler, and the like.
Considering in particular the scheduler, the organizer is very useful for managing a personal agenda of a corresponding user. For this purpose, the scheduler allows the user to define different types of activities to be performed. Typical examples are tasks without specific time constraints (i.e., which may be executed at any time, generally within a defined deadline); generally, the tasks are location-dependent, that is, they must be performed at specific locations (such as an office, a shop, and the like).
Most of the schedulers known in the art provide different functions for remembering the tasks to be performed to the user. Typically, the scheduler warns the user when the deadline of each task is approaching (for example, some days before); moreover, the scheduler continues remembering the task periodically (for example, every 1-2 hours) until it has been completed.
However, the available solutions are not completely satisfactory. Indeed, the user generally forgets the tasks to be performed until the corresponding deadlines are very close (when the organizer remembers them). Moreover, it might now be difficult (if not impossible) to perform some task; a typical example is when the user is far away from the corresponding location, or when the task is remembered during a holiday period. Moreover, the user can be very busy at the moment. A worst situation arises if the user is away (for example, for a trip) and s/he is then unable to perform the task by its deadline.
All of the above is even more frustrating if the user had passed several times close to locations where the tasks were to be performed in the preceding days (without realizing that s/he could have done the tasks at that moment).
Another problem arises when the tasks require some prerequisites for their execution (such as carrying a document, having specific information available, and the like). In this case, even if the user had remembered the tasks when around their locations it would have been very unlike that s/he had all the required documents or information.
The above-described drawbacks cause a substantial waste of time for the user. Moreover, in some cases they can even result in the missing of some tasks (with the corresponding negative consequences).

International Business Machines Corporation


A positive type resist composition comprising an alkali-soluble resin and a quinonediazide compound, wherein the alkali-soluble resin containing resin (A) is obtainable through a condensation reaction with at least one phenol compound represented by the following general formula (I): ##STR1## wherein R.sub.1 to R.sub.3 independently of one another each represent a hydrogen atom or an alkyl or alkoxy group having 1-4 carbon atoms and k represents 1 or 2, at least one compound represented by the following general formula (II): ##STR2## wherein R.sub.4 represents a hydrogen atom, an alkyl group having 1-4 carbon atoms or a phenyl group, R.sub.5 to R.sub.7 independently of one another each represent a hydrogen atom or an alkyl or alkoxy group having 1-4 carbon atoms and n represents 1 or 2, and an aldehyde compound. This composition is excellent in the balance between performances such as sensitivity, heat resistance and profile, and is free from scum.

1. Field of the Invention
This invention relates to a positive type resist composition suitable for use as a positive type photoresist sensitive to radiations such as ultraviolet rays including g ray and i ray, far ultraviolet rays including excimer laser and the like, electron beams, ion beams, X ray and the like.
2. Related Art
Compositions comprising a quinonediazide compound and an alkali-soluble resin are used as positive type photoresists, because their quinonediazide groups decompose when irradiated by a light having a wavelength of 500 nm or shorter and, as its result, they change from an alkali-insoluble material to an alkalisoluble material. Since these positive type photoresists are much superior to negative type ones in resolution, they are used for the preparation of integrated circuits such as IC, LSI, etc.
In the current integrated circuits, the improvement in the degree of integration has brought about a decrease in the width of wiring, due to which the hitherto employed wet etching process is being replaced by the dry etching process. Dry etching process is accompanied by an elevation of the substrate temperature, which can result in a deformation of resist pattern and a drop in dimensional accuracy. Thus, at the present time, an improvement of the heat resistance of resist is demanded more earnestly than ever. Further, if a scum remains after the development or the profile is not rectangular, undesirable influences are exercised on the dimension of substrate after dry etching, so that a resist free from scum and giving a good profile is requested. However, if a good pattern profile and a high resolution are aimed at simultaneously, the sensitivity is greatly deteriorated usually. From such a viewpoint, the positive type photoresists today in use cannot be said to be satisfactory in the balance between performances such as sensitivity, profile, scum and heat resistance.


The present invention provides a system and a method for sampling groundwater under in-situ condition state in reliable, efficient and economic manner without disturbing environment of formation water present in under-ground layer. There are provided a continuous water sampling process and a batch style water sampling process for sampling formation water by confirming the same environment as that of the groundwater in the under-ground layer. After drilling water has been removed by the continuous water sampling process, formation water is repeatedly sampled by the batch style water sampling process, and a downhole system equipped with the continuous water sampling process and the batch style water sampling process is designed in such structure that it is moved up and down in a casing pipe and inserted into or removed from a packer system in the hole.

The present invention relates to a packer type groundwater sampling system, which can be used for an apparatus for sampling groundwater in a borehole or a well or for an apparatus for carrying out test at any desired depth in a borehole or a well. The invention also relates to a method for sampling groundwater using such a system.
Continuous water sampling method has been used for sampling groundwater in the past. A typical method is a pumping-up method. In this method, a pump is installed in a probe placed in a borehole, and groundwater in a water sampling section is continuously sampled and brought up to the ground surface. Also, an air-lift method using air pressure from ground surface is known as one of the continuous water sampling methods.
On the other hand, a batch style water sampling method has also been proposed (Japanese Utility Model Publication Laid-Open 3-69090 and Japanese Patent Publication Laid-Open 6-201542). In this method, a completely sealed water sampling container is used to characterize groundwater chemistry and water can be sampled under in-situ condition.
Also, a water sampling apparatus has been proposed, which combines the above two methods to overcome the disadvantages of these methods (Japanese Patent Publication Laid-Open 6-193101).
The pumping-up method, i.e. the most typical of the continuous water sampling methods, is higher in working efficiency than the batch style water sampling method. However, because pumping ability of the pump is effective for the depth of several hundreds of meters in the current technical level, water cannot be pumped up if the groundwater level in borehole is lower than the limit of the pumping ability.
Also, because it is impossible to sample groundwater under in-situ condition from structural reason, there are problems in that dissolved gas in the groundwater is released at the ground surface when it is opened to the atmospheric air due to pressure change. Further, because water is sampled continuously for long time, load applied on the pump is high, and this extensively reduces durability of the pump.
In the air-lift method, compressed air sent from the ground surface is used, and it is impossible to sample groundwater in in-situ condition.
By the batch style water sampling method, it is possible to sample formation water under in-situ condition without disturbing geological environment where the groundwater is present. However, it is not possible to strictly judge whether the formation water under in-situ condition has been sampled or not unless there is the function to confirm that the pressure in the container for sampling groundwater has reached the same level as the underground condition.
Also, in the practical procedure, drilling fluid has been used for the drilling of boreholes and the groundwater will be contaminated by this fluid. The absence of drilling fluid in water has been checked by continuous monitoring of:
(1) concentration of tracers (e.g. Uranine dye or Li) which are introduced into the drilling fluid; and PA0 (2) concentration of chemical components.
The absence of tracers, or constant concentrations of chemical components can be regarded as an indication of the absence of drilling fluid. Water sampling volume per batch is also low, and much time is required to carry out the work by this method alone, and there is also problems in working efficiency.
On the other hand, the combination of the continuous water sampling method and the batch style water sampling method is not yet used in practical application, but it overcomes the disadvantages of these two methods. By this method, however, formation water necessary for water quality analysis is sampled by one time in the batch style water sampling method. If the required quantity has not been sampled, the water sampling section is sealed off for once and the water is mixed with the groundwater of the other level when the second batch style water sampling is carried out. Thus, the continuous water sampling must be carried out again. Further, in case water chemistry is to be monitored over a long period, the continuous water sampling and the batch style water sampling must be performed each time, and problems arise about quality or economic feasibility of the sampled groundwater. Also, there are problems in that the formation water sampled and brought to ground surface by the batch style water sampling method cannot be easily taken out and transported.
In testers in a borehole, there are hydrological tester, pore water pressure measuring apparatus, flow direction and velocity measuring apparatus, borehole expansion tester, etc. in addition to groundwater sampler. In major functions of these apparatuses, there are the following problems at present:
(a) Packer structure
The tester in the borehole normally uses packer or mechanical packer based on water pressure or air pressure to set up a measuring section. As depth increases, water packer is used because of safety and maneuverability. In the conventional type water packer structure, there are the following problems:
Because diameter of water supply hose in the packer expansion system is small, pressure loss inside the pipe increases, and longer time is required for expansion of the packer. PA1 To expand the packer, water in hose (such as tap water), and not in-hole water (i.e. mixture of groundwater at various depths in a borehole), is used in many methods. In this case, if leakage occur, water other than the in-hole water is brought into the hole, and this results in contamination of the groundwater in the borehole. PA1 When the level of groundwater in borehole is lowered, packer is spontaneously expanded due to water pressure from ground surface to the level of groundwater. As a result, it is difficult to recover the packer. PA1 In many cases, water supply hose of the packer expansion system is installed outside casing pipe. This causes damage of wall of borehole and makes it difficult to recover the apparatus. Also, much time is required for installing hoses and cables, leading to lower working efficiency. PA1 Because water hose is present in a packer expansion circuit system, volume inside the hose and volume change due to creeping of hose are also included in water injection quantity, and it is not possible to accurately identify quantity of water injected into the packer itself.
(b) Installation of pipes and signal cable
Also, it is difficult to identify quantity of the water extracted from the packer.
To solve the above problems, it is an object of the present invention to develop and provide a water sampling system, by which it is possible to sample formation water under in-situ condition at deeper depth reliably, efficiently and economically without disturbing geological environment of groundwater present in underground formation by means of borehole.
It is another object of the present invention to limit a water sampling section to a certain depth, to quickly discharge drilling water and other water mixed with water of the other level from the sampling section and to replace them with the formation water.
It is still another object of the present invention to sample the formation water under in-situ condition.
It is another object of the present invention to sample the formation water by batch style water sampling method continuously and by many times without carrying out continuous water sampling after the groundwater in the water sampling section has been replaced with the formation water.
It is another object of the present invention to make it possible to confirm that pressure in a water sampling container is in equilibrium with water pressure environment where the formation water has been present in the batch style water sampling method and to confirm water sampling volume in the water sampling container in order to reliably perform water sampling under in-situ condition.
It is still another object of the present invention to make it possible to easily take out formation water sampled and brought to ground surface by the batch style water sampling method and to transport the water under in-situ condition.
It is another object of the present invention to make the packer expandable by utilizing in-hole water in order to reliably and safely limit the water sampling section without disturbing the geological environment where the groundwater is present.
It is still another object of the present invention to make it possible to sample and bring groundwater safely to ground surface by protecting major functional components even when it is not possible to recover the packer system due to collapse occurring in the borehole.

Packer type groundwater sampling system and water sampling method


A planar light unit provided with field emitters and a method for fabricating the same. According to the present invention, the planar light unit has a first substrate, a plurality of first conductive strips, a plurality of second conductive strips, a plurality of field emitters, a second substrate and a fluorescent film. The plurality of first conductive strips are formed over the first substrate, and the plurality of second conductive strips are formed over the first substrate and interposed inbetween the plurality of first conductive strips. The plurality of field emitters are formed in proximity of the plurality of first conductive strips. The second substrate is provided to be attached to and spaced apart from the first substrate to form a chamber therebetween, whereas a fluorescent film is formed over the interior surface of the second substrate facing the plurality of field emitters.

1. Field of the Invention
The present invention generally relates to a planar lamp for illuminating a flat panel display. More particularly, the present invention relates to a planar light unit of field emitters whose cathodes and gates are arranged in strip shape for use in flat panel displays.
2. Background of the Invention
In recent years, flat panel display devices have been developed and widely used in electronic applications such as computer monitors and televisions. One of the popularly used flat panel display device is an active matrix liquid crystal display (LCD) that provides improved resolution. Other flat panel display devices have been developed in recent years to replace the liquid crystal display panels. One of such devices is a field emission display (FED) device that overcomes some of the limitations of LCD and provides significant advantages over the traditional LCD devices. For instance, the FED devices have higher contrast ratio, larger viewing angle, higher maximum brightness, lower power consumption and a wider operating temperature range when compared to a conventional thin film transistor (TFT) LCD panel.
A most drastic difference between a FED and a LCD is that, unlike the LCD, FED produces its own light source. In a FED, electrons are emitted from a cathode and impinge on phosphors coated on the back of a transparent cover plate to produce an image. Such a cathodoluminescent process is known as one of the most efficient methods for generating light. Contrary to a conventional CRT device, each pixel or emission unit in a FED has its own electron source, i.e., typically an array of emitting microtips. A voltage difference existed between a cathode and a gate which extracts electrons from the cathode and accelerates them toward the phosphor coating. The emission current, and thus the display brightness, is strongly dependent on the work function of the material formed on the emitting microtips.
Referring to FIG. 1A, a top view of a conventional field emission display device 1 using carbon nanotube (CNT) emitters as electron emission sources is shown. FIG. 1B is a partial, cross-sectional view of the conventional field emission display device 1 taken along a line A-A of FIG. 1A. As shown in FIGS. 1A and 1B, the FED device 1 is constructed by a first insulative plate 10, cathode electrodes 12 formed on the first insulative plate 10 by a material that includes metal, CNT emitters 16 formed on the cathode electrodes 12 to form emitter stacks 17, dielectric strips 18 formed on the insulating plate 10 and perpendicular to a multiplicity of the emitter stacks 17, gate electrodes 14 formed on top of the dielectric strips 18, and anode electrodes 15 coated with phosphorous particles formed on a second insulative plate 11 mounted on top of the first insulative plate 10, and an intermittent conductive layer of indium-tin-oxide (ITO) layer 13 formed between the second insulative plate 11 and the anode electrodes 15 to further improve the brightness of the phosphorous layer of the anode electrodes 15 when bombarded by electrons.
It is therefore an object of the present invention to provide a planar light unit utilizes field emitters which higher maximum brightness, lower power consumption and a wider operating temperature range.

Planar light unit using field emitters and method for fabricating the same

Industrial Technology Research Institute


A system and computer-implemented method of providing an incentive for a customer to purchase non-fuel products or services at a store that sells the products or services and fuel. The system detects that the customer purchased a number of non-fuel products or services in a first visit to the store, and provides the customer with a first reward entitling the customer to a first amount of free fuel. The system then detects that the customer purchased a number of non-fuel products or services in a second visit to the store, and provides the customer with a second reward entitling the customer to a second amount of free fuel. The customer is identified during a subsequent fueling transaction, and the system dispenses an amount of free fuel to the customer equal to the total of the first and second amounts of free fuel.

This invention relates to automated retail systems and, more particularly, to a system and method for providing an incentive for a customer to purchase non-fuel products or services at a store that sells the products or services and fuel.
Typically, a cash back machine can be used to return unused monies to a consumer that uses a bill accepting device or magnetic card reader to pay for fuel. However, cash back machines are costly. Furthermore, using cash back machines to return unused monies to consumers do not increase consumer loyalty.
The present invention is directed to overcoming one or more of the limitations of systems for purchasing fuel.

System and method providing customer incentive to purchase non-fuel products and services


Described herein are techniques for improving disaster recovery, in particular disaster recovery pertaining to data transfer requests. The data transfer request can be received by each of multiple deployments; however, only a primary deployment can process the request. The data transferred by the primary deployment may be replicated in the secondary deployments. In response to a failover event, one of the secondary deployments can be designated as the new primary development and continue the data transfer based on the data transfer request and the replication information received from the old primary deployment prior to the failover.

Data systems, such as database systems, may be provided through a cloud platform, which allows organizations and users to store, manage, and retrieve data from the cloud. A variety of techniques can be employed for uploading and storing data in a database or table in a cloud platform. Those techniques are typically limited to situations where a source and a target table are provided in the same cloud provider.
Moreover, uploading techniques can be susceptible to system failures and disaster recovery. For example, if a system experiences a failure while data is being uploaded, some or all of that data can be lost.

Data ingestion replication and disaster recovery


A silica residue is generated, due to a presence of a step formed by a presence of the first layer metallic interconnect, and then, the residual silica is etched to form hollow portions when vias for the metallic interconnect provided in a layer above thereof is formed, and further, insulating materials remained above the hollow portions flakes off to create contaminants, leading to a reduction in the production yield. In the present invention, interconnects provided in a layer underlying a via group, which are provided for coupling to the upper layer interconnect layer, are disposed so as to cover vias composing its via group.

1. Field of The Invention
The present invention relates to a semiconductor device and a method for designing the semiconductor device, and, in particular, relates to a semiconductor device provided by employing a planarization with silica for an interlayer film and a method for designing the semiconductor device.
2. Related Art
In recent circumstances in modern semiconductor devices, number of layers required for composing an interconnect structure is more and more increased for achieving higher density of elements with lower production cost, and new technologies and new materials are proposed for achieving an improved multiple-layered interconnect. Among these new technologies, a typical technology is to achieve a planarization of an interlayer insulating film by employing a silica film produced via a rotation coating process (hereinafter referred simply as "silica"). In this technology, an interlayer insulating film such as a plasma oxidization film is deposited, and then, the film is coated with silica to fill depressions created between the interconnects with silica, thereby reducing the unevenness in the surface to provide a flat interlayer film.
In addition to above, a method for planarizing a multiple-layered metallic pad on a semiconductor device is described in Japanese Patent No. 2,970,232.
The present inventors have conducted relevant experiments, and have found the following problems.
FIG. 5 is a schematic plan view of a semiconductor device experimentally produced in the experiment.
A semiconductor device shown in FIG. 5 is formed by providing a second layer metallic interconnect 12 on a first layer metallic interconnect 11, and providing via hole group 13 for coupling to a third layer metallic interconnect on an insulating film that is provided on the second layer metallic interconnect 12. As shown in FIG. 5, ends of the first layer metallic interconnect 11 are provided to overlap with the via hole group 13.
A process for manufacturing the above-described semiconductor device will be described in reference to FIGS. 6A and 6B.
A first layer metallic interconnect 11, an insulating film 22 and a second layer metallic interconnect 12 are formed on an insulating film 21. Next, a deposition of a plasma oxide film is conducted to form an interlayer insulating film 23. Next, a silica coating operation (silica coating+baking+etchback) is conducted to planarize the interlayer film 23. Deposition of a plasma oxide film is conducted again to form an insulating film 25. (FIG. 6A). Subsequently, in order to form via holes for coupling to the third layer metallic interconnect, a resist is patterned, and a wet etch process is conducted, and subsequently, a dry etch process is conducted to form via holes 13 (FIG. 6B).
While a surplus silica remained on the surface is removed via an etchback process in this occasion, a silica residue 24 remained during the silica coating process is generated, due to a presence of a step, which is created due to a presence of the first layer metallic interconnect 11. Silica remained in the step is also simultaneously etched via a wet etch process for forming vias that provides an electrical coupling between the second layer metallic interconnect and the third layer metallic interconnect, and thus hollow portions are generated. Then, insulating materials remained above these hollow portions flake off to create contaminants, leading to a reduction in the production yield.

Semiconductor device and method for designing same


The drive current capability of a pull-down transistor and a pass transistor formed in a common active region may be adjusted on the basis of different strain levels obtained by providing at least one embedded semiconductor alloy in the active region, thereby providing a simplified overall geometric configuration of the active region. Hence, static RAM cells may be formed on the basis of a minimum channel length with a simplified configuration of the active region, thereby avoiding significant yield losses as may be observed in sophisticated devices, in which a pronounced variation of the transistor width is conventionally used to adjust the ratio of the drive currents for the pull-down and pass transistors.

1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to the manufacture of field effect transistors in complex circuits including memory areas, for instance, in the form of a cache memory of a CPU.
2. Description of the Related Art
Integrated circuits comprise a large number of circuit elements on a given chip area according to a specified circuit layout, wherein transistor elements represent one of the major semiconductor elements in the integrated circuits. Hence, the characteristics of the individual transistors significantly affect overall performance of the complete integrated circuit. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips, ASICs (application specific ICs) and the like, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using MOS technology, millions of transistors, i.e., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, the latter aspect renders the reduction of the channel length, and associated therewith the reduction of the channel resistivity, a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
On the other hand, the drive current capability of the MOS transistors also depends on the transistor width, i.e., the extension of the transistor in a direction perpendicular to the current flow direction, so that the gate length and thus the channel length, in combination with the transistor width, are dominant geometric parameters which substantially determine the overall transistor characteristics in combination with "transistor internal" parameters, such as overall charge carrier mobility, threshold voltage, i.e., a voltage at which a conductive channel forms below the gate insulation layer upon applying a control signal to the gate electrode, and the like. On the basis of field effect transistors, such as N-channel transistors and/or P-channel transistors, more complex circuit components may be created, depending on the overall circuit layout. For instance, storage elements in the form of registers, static RAM (random access memory), may represent important components of complex logic circuitries. For example, during the operation of complex CPU cores, a large amount of data has to be temporarily stored and retrieved, wherein the operating speed and the capacity of the storage elements have a significant influence on the overall performance of the CPU. Depending on the memory hierarchy used in a complex integrated circuit, different types of memory elements are used. For instance, registers and static RAM cells are typically used in the CPU core due to their superior access time, while dynamic RAM elements are preferably used as working memory due to the increased bit density compared to registers or static RAM cells. Typically, a dynamic RAM cell comprises a storage capacitor and a single transistor wherein, however, a complex memory management system is required so as to periodically refresh the charge stored in the storage capacitors which may otherwise be lost due to unavoidable leakage currents. Although the bit density of dynamic RAM devices may be very high, a charge has to be transferred from and to the storage capacitors in combination with periodic refresh pulses, thereby rendering these devices less efficient in terms of speed and power consumption compared to static RAM cells. Thus, static RAM cells may be advantageously used as high speed memory with moderately high power consumption, thereby, however, requiring a plurality of transistor elements so as to allow the reliable storage of an information bit.
FIG. 1a schematically illustrates a circuit diagram of a static RAM cell 150 in a configuration as may typically be used in modern integrated circuits. The cell 150 comprises a storage element 151, which may include two inversely coupled inverters 152A, 152B, each of which may include a couple of transistors 100B, 100C. For example, in a CMOS device, the transistors 100B, 100C may represent an N-channel transistor and a P-channel transistor, respectively, while, in other cases, transistors of the same conductivity type, such as N-channel transistors, may be used for both the transistors 100B and 100C. A corresponding arrangement of N-channel transistors for the upper transistors 100C is illustrated at the right-hand side of FIG. 1a. Moreover, respective pass or pass gate transistors 100A may typically be provided so as to allow a connection to the bit cell 151 for read and write operations, during which the pass transistors 100A may connect the bit cell 151 to corresponding bit lines (not shown), while the gate electrodes of the pass transistors 100A may represent word lines of the memory cell 150. Thus, as illustrated in FIG. 1a, six transistors may be required to store one bit of information, thereby providing a reduced bit density for the benefit of a moderately high operating speed of the memory cell 150, as previously explained. Depending on the overall design strategy, the memory cell 150 may require the various transistor elements 100A, 100B, 100C to have different characteristics with respect to drive current capability in order to provide reliable operational behavior during read and write operations. For example, in many design strategies, the transistor elements are provided with minimum transistor lengths, wherein the drive current capability of the transistors 100B, which may also be referred to as pull-down transistors, may be selected to be significantly higher compared to the drive current capability of the pass transistors 100A, which may be accomplished by appropriately adjusting the respective transistor width dimensions for the given desired minimum transistor length.
FIG. 1b schematically illustrates a top view of a portion of the memory cell 150 as a hardware configuration in the form of a semiconductor device. As illustrated, the device 150 comprises a silicon-based semiconductor layer 102, in which an active region 103 is defined, for instance, by providing a respective isolation structure 104 that laterally encloses the active region 103, thereby defining the geometric shape and size of the transistors 100A, 100B. As illustrated, the transistors 100A, 100B may be formed in and above the same active region 103 since both transistors may have the same conductivity type and may be connected via a common node, as is for instance illustrated as nodes 153A, 153B in FIG. 1a. As previously explained, the transistors 100A, 100B, i.e., the pass transistor and the pull-down transistor, may have substantially the same length so that respective gate electrodes 106 may have substantially the same length 106L, whereas a transistor width 103B of the pull-down transistor 100B may be greater compared to a transistor width 103A of the pass transistor 100A, in order to establish the different current capabilities of these transistors.
FIG. 1c schematically illustrates a cross-sectional view taken along the line 1c of FIG. 1b. As illustrated, the device 150 comprises a substrate 101 which may typically be provided in the form of a silicon substrate, possibly in combination with a buried insulating layer (not shown) if a silicon-on-insulator (SOI) is considered. Above the substrate 101 and a possible buried insulating layer, the semiconductor layer 102, in the form of a silicon layer, is provided, in which the isolation structure 104 (see FIG. 1b) may be formed according to the desired shape so as to define the active region 103 according to the configuration as shown in FIG. 1b. That is, the active region 103 has the width 103B in the transistor 100B and has the width 103A in the transistor 100A. In this respect, an active semiconductor region is to be understood as a semiconductor region having an appropriate dopant concentration and profile so as to form one or more transistor elements in and above the active region, which have the same conductivity type. For example, the active region 103 may be provided in the form of a lightly P-doped semiconductor material, for instance in the form of a P-well, when the semiconductor layer 102 may extend down to a depth that is significantly greater than the depth dimension of the transistors 100A, 100B, when the transistors 100A, 100B may represent N-channel transistors. Similarly, the active region 103 may represent a basically N-doped region when the transistors 100A, 100B represent P-channel transistors. Furthermore, in the manufacturing stage shown in FIG. 1c, the transistors 100A, 100B may comprise the gate electrode 106, for instance in the form of a polysilicon material, which is separated from a channel region 109 by a gate insulation layer 108. Furthermore, depending on the overall process strategy, a sidewall spacer structure 107 may be formed on sidewalls of the gate electrodes 106. Additionally, drain and source regions 110 may be formed in the active region 103 and may connect the transistors 100A, 100B. Typically, metal silicide regions 111 are provided in the gate electrode 106 and an upper portion of the drain and source regions 110 so as to reduce contact resistance of these areas.
The device 150 is typically formed on the basis of the following processes. First, the isolation structure 104 may be formed, for instance, as a shallow trench isolation by etching respective openings into the semiconductor layer 102 down to a specific depth, which may even extend to a buried insulating layer, if provided. Thereafter, the corresponding openings may be filled with an insulating material by deposition and oxidation processes, followed by a planarization such as chemical mechanical polishing (CMP) and the like. During the process sequence for the isolation structure 104, advanced lithography techniques may have to be used in order to form a corresponding etch mask, which substantially corresponds to the shape of the active region 103, which requires the definition of a moderately narrow trench to obtain the desired reduced width 103A of the transistor 100A. Thereafter, the basic doping in the active region 103 may be provided by performing respective implantation sequences, which may also include sophisticated implantation techniques for introducing dopants for defining the channel doping and the like. Next, the gate insulation layers 108 and the gate electrodes 106 may be formed by depositing, oxidizing and the like an appropriate material for the gate insulation layer 106, followed by the deposition of an appropriate gate electrode material, such as polysilicon. Subsequently, the material layers are patterned by using advanced lithography and etch techniques, during which the actual length 106L of the gate electrodes 106 may be adjusted, thereby requiring extremely advanced process techniques so as to obtain a gate length of approximately 50 nm and less. Next, a part of the drain and source regions 110 may be formed by implanting appropriate dopant species followed by the formation of the spacer structure 107, or at least a portion thereof, followed by a subsequent implantation process for defining the deep drain and source areas, wherein a corresponding implantation sequence may be repeated on the basis of an additional spacer structure if sophisticated lateral concentration profiles may be required in the drain and source regions 110. Thereafter, appropriate anneal processes may be performed to re-crystallize implantation-induced damage in the active region 103 and also to activate the dopant species in the drain and source areas 110. It should be appreciated that, for a reduced gate length in the above-defined range, the sophisticated geometric configuration of the active region 103 may result in process non-uniformities, for instance during the deposition and etching of a spacer material for forming the sidewall spacer 107. Typically, the spacer structure 107 is formed by depositing an appropriate material, for instance a silicon dioxide liner (not shown) followed by a silicon nitride material, which may subsequently be selectively etched with respect to the silicon dioxide liner on the basis of well-established anisotropic etch recipes. However, at areas indicated as 112 in FIG. 1b, irregularities may be observed which may even be increased due to respective non-uniformities created during previously performed lithography processes, such as the lithography process for patterning the gate electrodes 106 and the like. Consequently, the areas 112 may have a significant influence on the further processing of the device 150, which may finally result in non-predictable behavior of the transistor 100B and thus the overall memory cell 150. For example, during the further processing, the metal silicide regions 111 may be formed by depositing a refractory metal, such as nickel, cobalt and the like, which may then be treated to react with the underlying silicon material, wherein typically the isolation structure 103 and the spacer structure 107 may substantially suppress the creation of a highly conductive metal silicide. However, due to the previously generated irregularities, respective leakage paths or even short circuits may be created, thereby undesirably influencing the final drive current capability of the transistor 100B, which may result in a less stable and reliable operation of the memory cell 150, thereby significantly contributing to yield loss of sophisticated semiconductor devices including static RAM areas.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.

Drive current adjustment for transistors formed in the same active region by locally providing embedded strain-inducing semiconductor material in the active region