In a cache DRAM including a DRAM memory array and a SRAM memory array provided on the same chip, a plurality of pairs of MOS transistors are provided, as block transfer gates, so as to connect bit line pairs in the DRAM memory array and bit line pairs in the SRAM memory array one pair by one pair, and a data transfer amount controlling circuit for controlling the plurality of pairs of MOS transistors, a block including a predetermined number of pairs at a time, is newly provided. Data transfer amount controlling circuit is constructed to simultaneously turn on only pairs of MOS transistors included in blocks of a number in accordance with a predetermined external signal out of the plurality of pairs of MOS transistors. Therefore, the amount of data transferred at a time between the DRAM memory array and the SRAM memory array can be changed by changing the combination of the logical levels of external signals.

1.Field of the Invention
The present invention relates to semiconductor memory devices, and, more particularly, to a semiconductor memory device having on the same chip a DRAM (Dynamic Random Access Memory) and a SRAM (Static Random Access Memory). Description of the Background Art
Generally, a high-speed memory referred to as a cache memory is provided between a CPU (Central Processing Unit) and a main memory in a computer or the like. A main memory generally has a large capacity, so that it is difficult to implement a main memory with a high-speed memory in respect of costs, for example. Therefore, a method of increasing the operating speed of a main memory by using a high-speed memory having a small capacity is adapted. This high-speed memory having a small capacity is a cache memory. In execution of a program, a CPU first makes access to a cache memory. In a case where data of a designated address is in the cache memory, execution of the program is continued, and, in a case where data of a designated address is not in the cache memory, execution of the program is interrupted, and storage data in the cache memory and the main memory are exchanged so that the data of the designated address is transferred from the main memory to the cache memory. In many cases, a semiconductor memory such as a DRAM or the like with a small memory cell area having advantage in increasing the capacity is used as a main memory, while a semiconductor memory such as a SRAM or the like in which importance is attached to the operating speed rather than reduction in the memory cell area is used as a cache memory.
Conventionally, a cache memory and a main memory are provided on separate chips, so that it is necessary to provide a bus for transferring data between the main memory and the cache memory, and, accordingly, the structure of a storage device including the main memory and the cache memory is complicated. Therefore, it is proposed to implement a high-speed memory with a large capacity having a structure more simple than that of the conventional one by providing a DRAM and a SRAM on the same chip. Such a high-speed memory with a large capacity is described in Japanese Patent Laying-Open No. 62-38590 (1987), for example. A high-speed memory with a large capacity having a structure in which a DRAM and a SRAM are provided on the same chip is hereinafter referred to as a cache DRAM.
FIG. 5 is a schematic block diagram illustrating the whole structure of a conventional cache DRAM. Referring to FIG. 5, the cache DRAM includes a DRAM memory array 100 having memory cells (not shown) arranged in a matrix of 512 columns.times.512 rows and a SRAM memory array 200 having memory cells (not shown) arranged in a matrix of 512 columns.times.16 rows. A row decoder 110 selects one row out of the 512 memory cell rows in DRAM memory array 100. A column decoder 120 selects one column out of the 512 memory cell columns in DRAM memory array 100. A sense amplifier.multidot.I/O gate 130 includes sense amplifiers each for amplifying a storage data signal in DRAM memory array 100 and an I/O gate for performing giving and receiving of data between DRAM memory array 100 and the outside. One sense amplifier is provided corresponding to each bit line pair in DRAM memory array 100. The I/O gate controls giving and receiving of data between each sense amplifier and the outside.
A row decoder 210 selects one row out of the 16 memory cell rows in SRAM memory array 200. Column decoder 220 selects one column out of the 512 memory cell columns in SRAM memory array 200. An I/O gate 230 performs giving and receiving of data between SRAM memory array 200 and the outside. A data transfer gate 300 performs data transfer between DRAM memory array 100 and SRAM memory array 200. A data transfer controlling circuit 310 controls data transfer gate 300 in response to an externally applied controlling signal TR. A column address buffer 320 designates memory cell columns to be selected by column decoders 120 and 220 in response to
externally applied nine bit address signals A0-A8. A row address buffer 330 designates a memory cell row to be selected by row decoder 110 in response to the externally applied nine bit address signals A0-A8. A row address buffer 340 designates a memory cell row to be selected by row decoder 210 in response to external four bit address signals A9-A12 other than the external address signals A0-A8. When data is read from DRAM memory array 100 and when data is read from SRAM memory array 200, all of the sense amplifiers in sense amplifier.multidot.I/O gate 130 are activated. Bit line pairs in DRAM memory array 100 and bit line pairs in SRAM memory array 200 correspond to each other with one-to-one correspondence through data transfer gate 300.
SRAM memory array 200 is used as the cache memory, and DRAM memory array 100 is used as the main memory. Memory cells arranged in the same row are connected to the same word line (not shown), and memory cells arranged in the same column are connected to the same bit line pair (not shown), in both of DRAM memory array 100 and SRAM memory array 200.
When data is read from DRAM memory array 100, row decoder 110 selectively activates only one word line corresponding to a memory cell row designated by row address buffer 330 out of the 512 word lines in DRAM memory array 100. This causes storage data of 512 memory cells included in the one memory cell row designated by row address buffer 330 out of the memory cells in DRAM memory array 100 to appear onto corresponding bit line pairs, respectively. In sense amplifier.multidot.I/O gate 130, column decoder 120 electrically connects only a sense amplifier, which corresponds to one bit line pair connected to a memory cell column designated by column address buffer 320 out of 512 pairs of bit line pairs in DRAM memory array 100, to the I/O gate. Accordingly, only storage data in a memory cell included in the column designated by column address buffer 320 out of storage data in the 512 memory cells is amplified and then provided to the outside by sense amplifier.multidot.I/O gate 130.
When data is written into DRAM memory array 100, data is externally applied to the I/O gate in sense amplifier.multidot.I/O gate 130. Row decoder 110 and column decoder 120 operate in the same manner as in the case of reading data from DRAM memory array 100. Accordingly, the external data applied to the I/O gate in sense amplifier.multidot.I/O gate 130 is applied only to one bit line pair designated by column address buffer 320 through a corresponding sense amplifier. Row decoder 110 activates only one word line corresponding to a memory cell row designated by row address buffer 330 out of word lines in DRAM memory array 100, so-that the data applied to the one bit line pair through sense amplifier.multidot.I/O gate 130 is written only into a memory cells included in the memory cell row designated by row address buffer 330 out of 512 memory cells connected to that bit line pair.
When data is read from SRAM memory array 200, row decoder 210 and column decoders 120, 220 operate. Specifically, row decoder 210 selectively activates only one word line corresponding to a memory cell row designated by row address buffer 340 out of 16 word lines in SRAM memory array 200. This causes storage data in 512 memory cells included in the memory cell row designated by row address buffer 340 out of the memory cells in SRAM memory array 200 to appear on to corresponding bit line pairs, respectively. Column decoder 220 electrically connects only one bit line pair, which corresponds to a memory cell column designated by column address buffer 320 out of 512 bit line pairs in SRAM memory array 200, to I/O gate 230. Column decoder 120 operates in the same manner as in the case of writing data into DRAM memory array 100 and in the case of reading data from DRAM memory array 100. An output from column address buffer 320 is applied in common to column decoder 120 and 220, so that column decoders 120 and 220 select bit line pairs, which correspond to each other, from DRAM memory array 100 and SRAM memory array 200, respectively. At the same time, data transfer gate 300 is controlled by data transfer controlling circuit 310 to electrically connect each bit line pair in DRAM memory array 100 to a corresponding bit line pair in SRAM memory array 200. According to this, data appearing on each bit line pair in SRAM memory array 200 is transmitted through data transfer gate 300 to a corresponding bit line pair in DRAM memory 100. Then, the data transmitted to each bit line pair in DRAM memory array 100 is amplified by a corresponding sense amplifier in sense amplifier.multidot.I/O gate 130. Each amplified data is transmitted again through data transfer gate 300 to a corresponding bit line pair in SRAM memory array 200. Only one bit line pair selected by column decoder 220 out of bit line pairs in SRAM memory array 200 is electrically connected to I/O gate 230. Accordingly, in SRAM memory array 200, only storage data in a memory cell at crossing of the memory cell column designated by column address buffer 320 and the memory cell row designated by row address buffer 340 is provided through I/O gate 230 to the outside.
When data is written into SRAM memory array 200, data is externally applied to I/O gate 230, and row decoder 210, column decoders 220, 120, and data transfer gate 300 operate in the same manner as in the case of reading data from SRAM memory array 200. Accordingly, the external data applied to I/O gate 230 is amplified in sense amplifier.multidot.I/O gate 130 through a bit line pair corresponding to a memory cell column designated by column address buffer 320 and then, in SRAM memory array 200, is written into a memory cell at crossing of the memory cell column designated by column address buffer 320 and a memory cell row designated by row address buffer 340.
When data is transferred from DRAM memory array 100 to SRAM memory array 200, first, data transfer controlling circuit 310 controls data transfer gate 300 so that the bit line pairs in DRAM memory array 100 and the bit line pairs in SRAM memory array 200 are electrically separated. Then, with the bit line pairs in DRAM memory array 100 and the bit line pairs in SRAM memory array 200 being electrically separated, row decoder 110 operates, and the sense amplifiers in sense amplifier.multidot.I/O gate 130 are activated. This causes storage data in 512 memory cells in a memory cell row designated by row address buffer 330 to be read onto corresponding bit line pairs, respectively, in DRAM memory array 100. Then, row decoder 210 operates. This causes only a word line corresponding to a memory cell row designated by row address buffer 340 to be activated in SRAM memory array 200. Subsequently, data transfer controlling circuit 310 controls data transfer gate 300 so that the bit line pairs in DRAM memory array 100 and the bit line pairs in SRAM memory array 200 are electrically connected to each other. As a result, data read onto respective bit line pairs in DRAM memory array 100 are written through data transfer gate 300 into memory cells connected to the one activated word line in SRAM memory array 200. Specifically, storage data in memory cells in one row in DRAM memory array 100 are transferred in a lump into memory cells in one row in SRAM memory array 200.
When data is transferred from SRAM memory array 200 to DRAM memory array 100, first, data is read from SRAM memory array 200. Specifically, in a period during which data transfer controlling circuit 310 controls data transfer gate 300 so that the bit line pairs in DRAM memory array 100 and the bit line pairs in SRAM memory array 200 are electrically separated, row decoder 210 operates. This causes only a word line corresponding to a memory cell row designated by row address buffer 340 to be activated in SRAM memory array 200, so that storage data in 512 memory cells included in the designated memory cell row appear onto corresponding bit line pairs, respectively. Then, row decoder 110 operates, and the sense amplifiers in sense amplifier.multidot.I/O gate 130 are activated. According to this, in DRAM memory array 100, a word line corresponding to a memory cell row designated by row address buffer 330 is activated, and it becomes possible that data appearing on respective bit line pairs are amplified in sense amplifier.multidot.I/O gate 130. Then, data transfer controlling circuit 310 controls data transfer gate 300 so that the bit line pairs in DRAM memory array 100 and the bit line pairs in SRAM memory array 200 are electrically connected. This causes the data appearing on respective bit line pairs in SRAM memory array 200 to be written through data transfer gate 300 into memory cells connected to the one activated word line in DRAM memory array 100. Specifically, storage data in memory cells in one row in SRAM memory array 200 are transferred in a lump to DRAM memory array 100.
FIG. 6 is a circuit diagram illustrating the relations of connection between a SRAM memory array and a DRAM memory array in such-a conventional cache DRAM. Referring to FIG. 6, each of sense amplifiers 135 is provided corresponding to one of memory cell columns 1000 in DRAM memory array 100. Each of sense amplifiers 136 is provided corresponding to one of memory cell columns 2000 in SRAM memory array 200. Sense amplifiers 135 and 136 are included in sense amplifier.multidot.I/O gate 130 in FIG. 5. Two N-channel MOS transistors 305 and 306 ar provided between each sense amplifier 135 and a corresponding sense amplifier 136. Two N-channel MOS transistors 307 and 308 are provided between each sense amplifier 136 and a corresponding memory cell column 2000 in SRAM 200. Transistors 305 to 308 are included in data transfer gate 300 in FIG. 5. Gate potentials of transistors 305, 306 and transistors 307, 308 are provided in common from data transfer controlling circuit 310. Specifically, data transfer controlling circuit 310 provides a potential at a high level or a low level in response to an external controlling signal TR to electrically connect and separate DRAM memory array 100 and SRAM memory array 200. A differential amplifiers to which two signals of potentials complementary to each other are applied is used both as sense amplifier 135 and as sense amplifier 136.
In a mode in which data writing and data reading into/from DRAM memory array 100 are performed, the output potential of data transfer controlling circuit 310 attains the low level. Accordingly, transistors 305 and 306 are both turned off, so that each sense amplifier 135 differentially amplifies the potential of one bit line BLa1 included in a bit line pair connected to a corresponding DRAM memory cell column 1000 and the potential of the other bit line BLb1 included in the bit line pair connected to the corresponding DRAM memory cell column 1000. According to this, the potentials of bit lines BLa1, BLb1 in each bit line pair become complementary potentials in accordance with storage data in a memory cell connected to an activated word line out of the memory cells included in the corresponding DRAM memory cell column 1000.
In a mode in which data is read from SRAM memory array 200, the output potential of data transfer controlling circuit 310 attains the high level. Accordingly, in this case, transistors 305, 306 and transistors 307, 308 are all turned on, so that each sense amplifier 136 supplies to a corresponding sense amplifier 135 two signals of complementary potentials, which are obtained by differentially amplifying the potential of one bit line BLa2 included in a bit line pair connected to a corresponding SRAM memory cell column 2000 and the potential of the other bit line BLb2 included in the bit line pair connected to the corresponding SRAM memory cell column 2000, through corresponding transistors 305 and 306. Each sense amplifier 135 differentially amplifies two output signals of a corresponding sense amplifier 136. As a result, the potentials of bit lines BLa2, BLb2 in each bit line pair in SRAM memory array 200 become complementary potentials in accordance with storage data in a memory cell connected to an activated word line out of memory cells included in a corresponding memory cell column 2000.
In a mode in which data is transferred from DRAM memory array 100 to SRAM -memory array 200, after complementary potentials in accordance with storage data in each of memory cells connected to an activated word line in DRAM memory array 100 appears onto a corresponding bit line pair BLa1, BLb1, the output potential of data transfer controlling circuit 310 attains the high level. If the output potential of data transfer controlling circuit 310 attains the high level, two signals of complementary potentials obtained by differentially amplifying the potentials of corresponding bit lines BLa1 and BLb1 by sense amplifier 135 are applied through corresponding transistors 305 and 306 to a corresponding sense amplifier 136. Each sense amplifier 136 differentially amplifies two output signals of a corresponding sense amplifier 135, applies one of the two signals of complementary potentials obtained as a result of that through a corresponding transistor 307 to a corresponding bit line BLa2, and applies the other of the two signals of the complementary potentials through a corresponding transistor 308 to a corresponding bit line BLb2. Consequently, complementary potentials in accordance with storage data in each of memory cells connected to an activated word line in DRAM memory array 100 appear onto a corresponding bit line pair in SRAM memory array 200.
In a mode in which data is transferred from SRAM memory array 200 to DRAM memory array 100, after complementary potentials in accordance with storage data in each of memory cells connected to an activated word line in SRAM memory array 200 appear onto a corresponding bit line pair BLa2, BLb2, the output potential of data transfer controlling circuit 310 attains the high level. Accordingly, in this case, if the output potential of data transfer controlling circuit 310 attains the high level, each sense amplifier 136 applies two signals of complementary potentials obtained by differentially amplifying the potentials of a corresponding bit line pair BLa2, BLb2 through corresponding 305 and 306 to a corresponding sense amplifier 135. Each sense amplifier 135 differentially amplifies the two output signals of a corresponding sense amplifier 136, applies one of the two signals of complementary potentials obtained as a result of that to a corresponding bit line BLa1, and applies the other of the two signals of the complementary potentials to a bit line BLb1. Consequently, complementary potentials in accordance with storage data in each of memory cells connected to an activated word line in SRAM memory array 200 appear onto a corresponding bit line pair BLa1, BLb1 in DRAM memory array 100.
As described above, by using a cache DRAM, a data bus for transferring data from a main memory becomes unnecessary, and it becomes possible to transfer data of more bits (data in memory cells in one row) than in the conventional case at a time between a main memory, DRAM memory array 100, and a cache memory, SRAM memory array 200.
As described above, in a conventional cache DRAM, the number of memory cell columns in a DRAM memory array and the number of memory cell columns in a SRAM memory array are set to be the same, and data transfer between the DRAM memory array and the SRAM memory array is performed by block transfer in which each memory cell row in the memory arrays is made to be one block. Therefore, if the number of memory cell columns in the DRAM memory array and that in the SRAM memory array is assumed to be n, the amount of data which can be transferred at a time between the DRAM memory array and the SRAM memory array is fixed to n bits.
Now, a cache memory is provided for the purpose of apparently relieving a gap between an operation cycle of a CPU and the access time of a main memory; however, according to a so-called two-hierarchy system in which a single cache memory is provided between a CPU and a main memory, when a gap between the access time of the cache memory and the access time of the main memory is large, it is not possible to sufficiently relieve a gap between an operation cycle of the CPU and the access time of the main memory.
Specifically, if the access time of a main memory is considerably slower than the access time of a cache memory, in a case where storage data in the cache memory is sequentially transferred to the main memory, after certain data is applied to the main memory, the cache memory cannot apply the next data until the applied data is written into the main memory completely, and, in a case where storage data in the main memory is transferred to the cache memory, after certain data read out in the main memory is written, the cache memory cannot perform the next data writing until the next data is read out in the main memory completely. As a result, time required for reading data from the main memory to the CPU and for writing data from the CPU to the main memory is not so reduced. Therefore, recently, there are some cases where a so-called three-hierarchy memory configuration in which one more cache memory is provided between a cache memory and a main memory for relieving a gap between the access time of them is adopted. In a three-hierarchy memory configuration, first, a CPU makes access to one of two cache memories and thereafter makes access to the other cache memory only when desired data is not in the one cache memory. One of two cache memories which is accessed by the CPU is hereinafter referred to as a primary cache, and the other cache memory is hereinafter referred to as a secondary cache.
Now, it is assumed that a conventional cache DRAM is used as a secondary cache. As described above, the amount of data which can be transferred at a time between a SRAM memory array and a DRAM memory array is constant in a conventional cache DRAM. Therefore, a problem arises in a case where the size of a block in a primary cache and the size of a block in a secondary cache are different. This problem will be described with reference to FIG. 7. FIG. 7 is a diagram conceptually illustrating a three-hierarchy memory configuration in a case where a conventional cache DRAM is used as a secondary cache.
Referring to FIG. 7, in a case where it is desired to read data from a memory part 700, a CPU 400 first makes access to a primary cache 500. If data desired by CPU 400 is in primary cache 500, CPU 400 instructs primary cache 500 to read the desired data and continues execution of a program. However, if the data desired by CPU 400 is not in primary cache 500, CPU 400 interrupts execution of the program and makes access to secondary cache 600. Specifically, in a case where a desired data is in a SRAM memory array 200 in a cache DRAM used as secondary cache 600, CPU 400 instructs reading of the data from SRAM memory array 200, and, in a case where the desired data is not in SRAM memory array 200, CPU 400 instructs data transfer from a block in DRAM memory array 100 wherein the desired data is stored to a block in SRAM memory array 200. This causes all data of one block to be read from the block in SRAM memory array 200 to which data has been transferred from DRAM memory array 100 in response to instruction by CPU 400. The read data of the one block are transferred to one block in primary cache 500. CPU 400 indicates reading of data from the one block to primary cache 500 to obtain the desired data.
Thus, in a case where data desired by CPU 400 is in DRAM memory array 100 in secondary cache 600, all data in a block wherein the desired data is stored is transferred in a sequence of DRAM memory array 100--SRAM memory array 200--primary cache 500. Conversely, in a case where CPU 400 instructs storing of a desired data in primary cache 500 into DRAM memory array 100 in secondary cache 600, data in primary cache 500 is transferred, one block by one block, in a sequence of primary cache 500--SRAM memory array 200--DRAM memory array 100.
However, if the amount (m bits) of data in one block in primary cache 500 is larger than the amount (n bits) of data in one block in secondary cache 600, in a case where data desired by CPU 400 is in DRAM memory array 100, data transferred from SRAM memory array 200 to primary cache 500 fill only n/m of a block in primary cache 500. Specifically, when data in a block B1 out of blocks in primary cache 500 from which data should be finally read in accordance with instruction by CPU 400 and data in a block B2 in SRAM memory array 200 are exchanged, data which should be transferred from secondary cache 600 are not in a region of (m-n) bits of block B1, and there is no region to which data stored in advance in the region of (m-n) bits of block B1 are to be transferred in block B2 in SRAM memory array 200 to which data from block B1 is to be transferred.
Thus, if the size of a block in primary cache 500 and the size of a block in secondary cache 600 are different, there is a possibility of causing a so-called mishit in which an address of a destination of data transfer is not in a memory of the destination of data transfer when data in an arbitrary block in primary cache 500 and data in an arbitrary block in secondary cache 600 are exchanged.
However, in such a memory configuration of a three-hierarchy system, a mishit should be caused only in a case where data desired by CPU 400 is not in primary cache 500 and SRAM memory array 200. Accordingly, there should not be mishits caused on the occasion of data exchange between a block in primary cache 500 and a block in secondary cache 600 in CPU 400 which lower functionality of the whole system loaded with CPU 400 and memory circuitry 700.
In order to solve such a problem, it is desired that the amount of data transferred at a time from DRAM memory array 100 through data transfer gate 300 into one block in SRAM memory array 200 on the occasion of data exchange between an arbitrary block in primary cache 500 and an arbitrary block in SRAM memory array 200 should be equal to the amount of data in one block in primary cache 500.
However, the amount of data transferred at a time between SRAM memory array 200 and DRAM memory array 100 in a conventional cache DRAM is constant, so that it is not possible to avoid the problem as described above unless the size of a block in a cache DRAM used as secondary cache 600 is set appropriately in accordance with the size of a block in a memory used as primary cache 500. Accordingly, in order to solve the problem as described above by using a conventional cache DRAM, it is necessary to manufacture the cache DRAM to be used as secondary cache 600 with the size of a block being changed for sizes of a block in the memory used as primary cache 500, and the efficiency of manufacture becomes worse.

Semiconductor memory device having on the same chip a plurality of memory circuits among which data transfer is performed to each other and an operating method thereof


A medical patient restraint device is provided for additional comfort while restraining patients during surgical procedures such as the circumcision of infants. The patient restraint device has a generally planar support member which is sized to receive and support a patient in a lying position thereon. The support member defines opposite side edges. A pair of support straps are fixed to the support member and extend along respective side edge portions in a generally parallel relationship. The pair of support straps are laterally spaced apart a distance sufficient to receive the patient therebetween with the support straps being parallel to and adjacent the sides of the patient. Individual restraining straps are provided for releasable connection to respective ones of the patient's arms and legs. Mating fasteners are fixed to the pair of support straps and the individual restraining straps such that each of the restraining straps may be releasably attached to one of the pair of support straps so as to permit the individual straps to retain the patient in a spread-eagle position on the support member and without having the individual restraining straps extending across the torso of the patient.

Some patients, such as infants, small children, and the elderly, characteristically resist attempts at diagnosis or treatment by physicians or by other medical personnel. Often, the combined efforts of several persons are required to restrain these patients for various medical procedures such as injections of drugs, drawing blood samples, performance of surgery requiring no or only local anesthesia, setting fractures, taking x-rays, and the like.
Medical restraint devices are generally known for restraining patients for ambulatory movement, for patient protection, for surgical procedures, and these various other medical procedures. These restraint devices for ambulatory movement and for surgical procedures typically have a support member and some type of means for securing the patient to the support member. Examples of these restraint devices may be seen in U.S. Pat. No. 4,854,305 by Bremer entitled "Radiolucent Transport And Diagnostic Procedure Board"; U.S. Pat. No. 4,757,811 by Clark entitled "Infant Restraining Device"; U.S. Pat. No. 4,108,168 by Craig entitled "Hip Splint Device"; U.S. Pat. No. 4,027,869 by Ruiz entitled "Patient Restraint For X-Ray Studies Of Infants"; U.S. Pat. No. 3,650,523 by Darby, Jr. entitled "Infant Restraining Board"; U.S. Pat. No. 3,526,222 by Dreibelbis entitled "Pediatric Restraining Apparatus"; and U.S. Pat. No. 3,215,334 by Tayman entitled "Infant Immobilizer, Particularly For Radiological Exposure." These prior restraint devices, however, constrain the patient in a rigid extended manner, block easy access to the torso area of the patient, and fail to secure the patient in an appropriate position for many surgical procedures such as circumcision of an infant.
Thus, there is a need for a medical restraint device which comfortably and flexibly secures the patient in an appropriate position for surgical procedures or the like.


The disclosed embodiments include an electrical disconnect system and method for a vehicle having a high voltage electrical system. In one embodiment, the system includes a service disconnect base being electrically coupled to the electrical system. A service disconnect plug is attachable to the service disconnect base and has a resistive device integrally formed therein. Current within the electrical system flows through the service disconnect base and the service disconnect plug when the service disconnect plug is connected to the service disconnect base. The current is limited to a current level no greater than a predetermined current level.

Vehicles such as hybrid electric vehicles (HEVs) and electrical vehicles (EVs) typically utilize a high voltage electrical system. To ensure safety when servicing these vehicles, a number of electrical protection systems have been developed. In many cases, these protection systems employ a switching device or arrangement that causes an open circuit in the vehicle's electrical system so as to prevent the flow of current. Although the conventional protection systems are useful, there exists a wide horizon for improvement. Particularly, diagnoses and servicing of some electrical system anomalies are possible only when the electrical system is energized. Accordingly, the servicing and/or diagnoses of vehicle electrical systems with the conventional protection systems further complicated, if not impossible.
The embodiments described herein were conceived in view of these and other disadvantages of systems adapted to ensure safety when servicing vehicles with high voltage electrical systems.


In a method, tomography apparatus and software product for evaluating time varying diagnostic images, a series of images are obtained in a time sequence from an examination subject in a tomography system, the sequence including exposures in a first image dataset obtained before occurrence of a diagnostically relevant event associated with the subject, and a second image dataset obtained at or after the event. A first correction of the image data is undertaken by displacing the image contents in each image to bring the position of the subject in each image into coincidence. A second correction of the image data is undertaken by obtaining an average value image from the image data corrected by the first correction. All of the images in the first and second datasets, corrected by the first correction, are normalized to the average value image on a picture element-by-picture element basis. A third correction is undertaken wherein the value of a picture element of a structurally uniform image region in an image in the first image dataset, corrected according to the second correction, or an average of picture elements in this image region in the first image dataset, is subtracted from the respective values of all picture elements in this region in the first and second image datasets.

1. Field of the Invention
The present invention relates to medical and diagnostic imaging, in particular the evaluation of medical image data sets in relation to the variation over time of changes which have been caused by diagnostic preparations (administered substances) in a region under examination.
2. Description of the Prior Art
The meaningfulness of an examination of the propagation of a diagnostic preparation, such as a contrast agent or a radiopharmaceutical, in an organ or a region of the body of a patient, using magnetic resonance tomography or scintillography, is adversely affected by various influences. An appropriate examination is carried out by using a sequence of measurements, which supplies exposures of the region under examination for various successive times. For an assessment of possible pathological changes, the changes in image intensity effected by the diagnostic preparation must be evaluated exactly from the image data of the series of exposures produced in such a way.
In general, reliable evaluation of the image intensity changes caused by a diagnostic preparation is made more difficult by three influences.
A first influence is the deformation and displacement of organs in the body because of bodily functions, such as the beating of the heart or breathing. Therefore, the times at which an image is obtained generally are synchronized with a defining bodily function in a measuring sequence. For example, during a perfusion measurement of the heart, the ECG signal is used to synchronize the recordings with the beat cycle of the heart. As a result, each individual recording in the measuring sequence is always obtained in the same state of deformation (phase) of the heart. However, since breathing follows a different cycle from that of the heart, there is a displacement of the heart or its representation in the individual recordings. In general, this means that the same regions of an organ under examination or a bodily region under examination are depicted at different positions in the individual images of a series of exposures. The determination of the position of a body region to be examined in an image therefore cannot be transferred to other images in the series of exposures.
In order to prevent a movement of an organ, caused by breathing, making the evaluation of the image data of a series of exposures more difficult or even impossible, the series of exposures of a measuring sequence is often carried out with the patient holding his or her breath. This necessitates great stress on the patient during the corresponding measuring sequence, as a result of which in turn an untrue stressed situation of the patient can be produced.
Furthermore, the evaluation is influenced by the characteristics of the detectors used to produce the image data. In particular, changing the sensitivity of a detector with the distance and/or direction to the object to be measured makes it more difficult to compare the measured data or the image intensities provided thereby from different positions of the region under examination. For example, in magnetic resonance tomography, identical tissues exhibit different intensities depending on the distance from the detector (reception) coil. The intensity in this case decreases with increasing distance from the coil.
If, therefore, a tissue close to the detector coil is compared with a tissue which is located at some distance from the detector coil, and if both tissues contain the same concentration of a diagnostic preparation, then the preparation results in a higher image intensity in the tissue close to the coil than the tissue remote from the coil.
A correct assessment is very difficult to carry out visually for these measurement-induced signal changes, as well as because the measured signal intensities are also influenced by the magnetic characteristics of the tissue itself, in addition to the imaging characteristics of the detector coil or the measuring system.
There are similar conditions in scintillography, wherein the measured image intensities are composed of the imaging characteristics of the gamma camera and the enrichment of the radiopharmaceutical in the tissue.
Furthermore, the image intensity or the value of the image elements of a body region in the image data set of an exposure from a measuring sequence is composed of a contribution from the tissue of this body region itself and a contribution from the concentration of the diagnostic preparation in this tissue at the time of the exposure, so that it is not possible to use the image intensity to make conclusions about the concentration of the diagnostic preparation.

Method, tomography apparatus and software product for evaluation of time-varying diagnostic procedures


An electronic circuit is provided. An error amplifier comprises a first input terminal coupled to a reference voltage, a second input terminal coupled to a feedback voltage, and a transistor comprises a first terminal coupled to an input voltage, a control terminal coupled to an output terminal of the error amplifier and a second terminal outputting an output voltage. A switching-capacitor circuit is coupled between the output voltage and the error amplifier and comprises a plurality of switching elements and at least first and second capacitors. The switching elements are switched by non-overlapping clocks such that the second capacitor is discharged to a bias voltage during a first period, and the first and second capacitors are connected together during a second period thereby extracting a division voltage from the output voltage to serve as the feedback voltage.

1. Field of the Invention
The invention relates to voltage regulators, and in particular to voltage regulators using switching elements and capacitors to serve as a feedback resistor.
2. Description of the Related Art
Power management control systems including voltage regulators are incorporated within portable electronic devices, such as laptop computers, hand-held electronic devices, and cellular phones, to generate a stable output voltage from a varying input voltage supply. The purpose of the voltage regulator is to regulate the external power supplied to the internal circuitry for efficient current usage or quiescent power. The useable operating voltage is called the "drop-out" voltage, which is the difference between the input and output voltages of regulator regulation. The smaller the difference, the more efficient the system. Additionally, batteries can supply only a finite amount of charge, so, the more quiescent current the regulator uses, the less operating lifespan the battery will have and therefore the system will be less efficient.

Voltage regulator having a plurality of capacitors configured to obtain a feedback voltage from a division voltage


A method for detecting structural flaws in a structural member that includes plastic composite matrix material involves taking a quantity of matrix material that is substantially free of any non-optic glass fibers, molding the matrix material into a structural loadbearing member having a length and opposite end surfaces, placing a plurality of straight continuous spaced elongated fiber optic strands having the same length as the loadbearing member in the matrix material before molding, loading the structural member to exert stress and strain thereon, exposing one of the ends of the fiber optic strands to a source of light, viewing the opposite ends of the fiber optic strands to determine if light is being emitted therefrom by passing through the fiber optic strands, and making an evaluation of any structural flaws in the member by determining whether light from the light source has been fully transmitted through the fiber optic strands.

The present invention relates to the field of use of optical fibers for non-destructive evaluation (NDE) of polymer matrix composite structural members. More particularly, the present invention is a method for detecting flaws in structural members made of polymer matrix composite materials by utilizing optical fibers in the structural composites themselves.
Various polymer resin matrix composite materials are well known in the art. Glass fibers are the most common of all reinforcing fibers for polymer matrix composites. For structural composites, the two commonly used glass fibers are E-glass and S-glass. These glass fibers are primarily composed of a silica (SiO2) backbone in the form of a SiO4 tetrahedra. The silicas are then doped with modifier ions that can contribute to their glass properties and manufacturing capability. However, fiberglass composites have not been able, as of yet, to prove their durability and serviceability. Fiberglass composites need to become more predictable, like steel, in order to be used extensively with a high degree of confidence in their structural integrity. Therefore, there is a need for a method for detecting flaws in the composite polymer matrix structural members.
A primary objective of the present invention is the provision of a method of detecting flaws in structural members.
Another objective of the present invention is the provision of a method of detecting flaws in structural members that involves the integration of optical fibers into the composite matrix to the substantial exclusion of traditional glass fibers.
Another objective of the present invention is to more easily permit non-destructive evaluation of structural members.
Another objective of the present invention is the provision of a method of detecting flaws in structural members that permits an onlooker or investigator to easily evaluate the integrity of the entire composite structural member.
Another objective of the present invention is the provision of a method of detecting flaws in structural members that is reliable and inexpensive to use.
These and other objectives will become apparent to one skilled in the art in view of the drawings, as well as the description and claims that follow.
The present invention relates to a method for detecting flaws in structural members made of polymer matrix composite materials by utilizing optic fibers and preferably only optic fibers, in the structural composites. The method includes taking a quantity of polymer matrix material that is substantially free of any non-optic glass fibers, molding the matrix material into a structural loadbearing member having a length and opposite ends surfaces, placing a plurality of continuous individual straight elongated fiber optic strands having the same length as the loadbearing member in the matrix material before molding, loading the structural member to exert stress and strain thereon, exposing one of the ends of the fiber optic strands to a source of light, viewing the opposite ends of the fiber optic strands to determine if light is being emitted therefrom by passing through the fiber optic strands, and making an evaluation of any structural flaws in the member by determining whether light from the light source has been fully transmitted through the fiber optic strands.

Method of detecting flaws in structural members


Lactone compounds of formula (1) are useful as monomers to form base resins for use in chemically amplified resist compositions adapted for micropatterning lithography.

This invention relates to novel lactone compounds useful as monomers to form base resins for use in chemically amplified resist compositions adapted for micropatterning lithography, and a method for preparing the same.
While a number of recent efforts are being made to achieve a finer pattern rule in the drive for higher integration and operating speeds in LSI devices, deep-ultraviolet lithography is thought to hold particular promise as the next generation in microfabrication technology. In particular, photolithography using a KrF or ArF excimer laser as the light source is strongly desired to reach the practical level as the micropatterning technique capable of achieving a feature size of 0.3 xcexcm or less.
The resist materials for use in photolithography using light of an excimer laser, especially ArF excimer laser having a wavelength of 193 nm, are, of course, required to have a high transmittance to light of that wavelength. In addition, they are required to have an etching resistance sufficient to allow for film thickness reduction, a high sensitivity sufficient to eliminate any extra burden on the expensive optical material, and especially, a high resolution sufficient to form a precise micropattern. To meet these requirements, it is crucial to develop a base resin having a high transparency, rigidity and reactivity. None of the currently available polymers satisfy all of these requirements. Practically acceptable resist materials are not yet available.
Known high transparency resins include copolymers of acrylic or methacrylic acid derivatives and polymers containing in the backbone an alicyclic compound derived from a norbornene derivative. All these resins are unsatisfactory. For example, copolymers of acrylic or methacrylic acid derivatives are relatively easy to increase reactivity in that highly reactive monomers can be introduced and acid labile units can be increased as desired, but difficult to increase rigidity because of their backbone structure. On the other hand, the polymers containing an alicyclic compound in the backbone have rigidity within the acceptable range, but are less reactive with acid than poly(meth)acrylate because of their backbone structure, and difficult to increase reactivity because of the low freedom of polymerization. Additionally, since the backbone is highly hydrophobic, these polymers are less adherent when applied to substrates. Therefore, some resist compositions which are formulated using these polymers as the base resin fail to withstand etching although they have satisfactory sensitivity and resolution. Some other resist compositions are highly resistant to etching, but have low sensitivity and low resolution below the practically acceptable level.
An object of the invention is to provide a novel lactone compound useful as a monomer to form a polymer for use in the formulation of a photoresist composition which exhibits firm adhesion and high transparency when processed by photolithography using light with a wavelength of less than 300 nm, especially ArF excimer laser light as the light source. Another object is to provide a method for preparing the lactone compound.
We have found that a lactone compound of formula (1) can be prepared in high yields by a simple method, that a polymer obtained from this lactone compound has high transparency at the exposure wavelength of an excimer laser, and that a resist composition comprising the polymer as a base resin is improved in adhesion.
The invention provides a lactone compound of the following general formula (1).
Herein R1 is hydrogen or a straight, branched or cyclic alkyl group of 1 to 6 carbon atoms. R2 is hydrogen or an acyl or alkoxycarbonyl group of 1 to 15 carbon atoms in which some or all of the hydrogen atoms on the constituent carbon atoms may be substituted with halogen atoms. Z is a divalent organic group of 1 to 15 carbon atoms which forms a lactone ring with the carbonyloxy group. The letter k is 0 or 1, and m is an integer from 0 to 5.
In another aspect, the invention provides a method for preparing a lactone compound of the following general formula (4), comprising effecting addition reaction of a metal enolate of the following general formula (3) to a carbonyl compound of the following general formula (2).
Herein k, m, R1 and Z are as defined above, and M is Li, Na, K, MgY or ZnY wherein Y is a halogen atom.
In a further aspect, the invention provides a method for preparing a lactone compound of the following general formula (5), comprising subjecting to acylation or alkoxycarbonylation reaction the hydroxyl group on a compound of the following general formula (4).
Herein k, m, R1 and Z are as defined above, and R3 is an acyl or alkoxycarbonyl group of 1 to 15 carbon atoms in which some or all of the hydrogen atoms on the constituent carbon atoms may be substituted with halogen atoms.
The lactone compounds of the invention are of the following general formula (1).
Herein R1 is hydrogen or a straight, branched or cyclic alkyl group of 1 to 6 carbon atoms. Exemplary alkyl groups include methyl, ethyl, n-propyl, isopropyl, n-butyl, isobutyl, sec-butyl, tert-butyl, tert-amyl, n-pentyl, n-hexyl, cyclopentyl, and cyclohexyl.
R2 is hydrogen or an acyl or alkoxycarbonyl group of 1 to 15 carbon atoms in which some or all of the hydrogen atoms on the constituent carbon atoms may be substituted with halogen atoms. Exemplary of R2 are formyl, acetyl, propionyl, pivaloyl, methoxycarbonyl, ethoxycarbonyl, tert-butoxycarbonyl, trifluoroacetyl, trichloroacetyl, and 3,3,3-trifluoropropionyl.
Z is a divalent organic group of 1 to 15 carbon atoms which forms a lactone ring with the carbonyloxy group in formula (1). Specifically, the partial structure represented by
is exemplified by lactone structures represented by
and structures having fused to these lactone structures a hydrocarbon ring (such as cycloalkane, cycloalkene or aromatic hydrocarbon) or a heterocyclic ring containing a hetero atom.
The letter k is 0 or 1, and m is an integer from 0 to 5 (i.e., 0xe2x89xa6mxe2x89xa65), and preferably from 0 to 3.
Illustrative, non-limiting, examples of the lactone compounds of formula (1) are given below.
The inventive lactone compounds can be prepared, for example, by the following process, although the process is not limited thereto.
As seen from the reaction scheme shown below, the desired lactone compound can be prepared by the first step of treating a lactone compound of formula (6) with a base in a solvent in an inert gas atmosphere of nitrogen, argon or the like, forming a metal enolate of formula (3). The enolate solution is then reacted with a carbonyl compound of formula (2) to form a hydroxylactone compound of formula (4).
Preferably 0.8 to 2.0 mol, especially 1.0 to 1.5 mol of the base is used per mol of the lactone compound (6), and 0.8 to 2.0 mol, especially 0.9 to 1.5 mol of the carbonyl compound (2) is used per mol of the lactone compound (6).
Herein, k, m, R1, R2 and Z are as defined above, X is a hydrogen or halogen atom, M is Li, Na, K, MgY or ZnY wherein Y is a halogen atom.
When X is hydrogen, the bases used herein include metal amides such as sodium amide, potassium amide, lithium diisopropylamide, potassium diisopropylamide, lithium dicyclohexylamide, potassium dicyclohexylamide, lithium 2,2,6,6-tetramethylpiperidine, lithium bistrimethylsilylamide, sodium bistrimethylsilylamide, potassium bistrimethylsilylamide, lithium isopropylcyclohexylamide, and bromomagnesium diisopropylamide; alkoxides such as sodium methoxide, sodium ethoxide, lithium methoxide, lithium ethoxide, lithium tert-butoxide, and potassium tert-butoxide; inorganic hydroxides such as sodium hydroxide, lithium hydroxide, potassium hydroxide, barium hydroxide, and tetra-n-butylammonium hydroxide; inorganic carbonates such as sodium carbonate, sodium hydrogen carbonate, lithium carbonate and potassium carbonate; metal hydrides such as sodium hydride, lithium hydride, potassium hydride, and calcium hydride; and alkyl metal compounds such as trityl lithium, trityl sodium, trityl potassium, methyl lithium, phenyl lithium, sec-butyl lithium, tert-butyl lithium, and ethyl magnesium bromide. When X is halogen, the bases used herein include metals such as zinc and magnesium. The bases are not limited to these examples. Useful solvents are ethers such as tetrahydrofuran, diethyl ether, di-n-butyl ether, and 1,4-dioxane, hydrocarbons such as n-hexane, n-heptane, benzene, toluene, xylene and cumene, alcohols such as methanol, ethanol, isopropyl alcohol and tert-butyl alcohol, amines such as liquid ammonia and methyl amine, and aprotic polar solvents such as dimethyl sulfoxide and N,N-dimethylformamide. Any of these solvents may be selected depending on reaction conditions and used alone or in admixture thereof. A compound having a ligand such as N,N,Nxe2x80x2,Nxe2x80x2-tetramethylethylenediamine (TMEDA), hexamethyl-phosphoric triamide (HMPA), N,Nxe2x80x2-dimethylpropyleneurea (DMPU) or 1,3-dimethyl-2-imidazolidinone (DMI) may be used complementally.
The reaction temperature and time vary with particular starting reactants used. In one example where a lactone compound (6) wherein X is hydrogen and a strong base such as lithium bistrimethylsilylamide are used, the resulting metal enolate is thermally unstable, and the preferred conditions for reaction of the metal enolate with the carbonyl compound (2) include a reaction temperature in the low range of xe2x88x9280xc2x0 C. to xe2x88x9220xc2x0 C. and a reaction time of about xc2xd to about 3 hours. In another example where an xcex1-halolactone compound (6) wherein X is halogen and a metal such as zinc are used, it is generally preferred to keep the reaction temperature in the range of 0 to 80xc2x0 C. and the reaction time in the range of about 1 to 20 hours. The reaction conditions are not limited to these ranges. From the reaction mixture containing the nucleophilic addition product, the desired hydroxy compound (4) is obtained by a conventional aqueous work-up procedure. If necessary, the compound (4) is purified by any conventional technique such as distillation, chromatography or recrystallization.
By esterifying the hydroxy compound (4) thus obtained, a corresponding acyl or alkoxycarbonyl compound (5) is obtained.
Esterification may be carried out in a conventional way using 1 to 5 mol, preferably 1 to 2 mol of an esterifying agent per mol of the hydroxy compound (4). The esterifying agent is R3W wherein W stands for a hydroxyl group, halogen atom, acyloxy group, alkoxycarbonyloxy group, or an eliminatable group such as p-nitrophenyloxy. Examples of the esterifying agent R3W include carboxylic acids such as formic acid (where W=OH), acid halides such as acetyl chloride, acetyl bromide and propionyl chloride (where W=halogen), acid anhydrides such as acetic anhydride, trifluoroacetic anhydride, mixed acid anhydride of formic acid/acetic acid, and di-t-butyl dicarbonate (where W=acyloxy or alkoxycarbonyloxy), and activated esters such as p-nitrophenyl acetate and p-nitrophenyl propionate (where W=eliminatable group such as p-nitrophenyloxy). The reaction may be carried out in a solventless system or in a suitable solvent selected from among chlorinated solvents such as methylene chloride, chloroform, trichlene; ethers such as tetrahydrofuran, diethyl ether, di-n-butyl ether, and 1,4-dioxane; and hydrocarbons such as n-hexane, n-heptane, benzene, toluene, xylene and cumene, alone or in admixture of any. Except the case wherein the esterifying agent is a carboxylic acid (W=OH), it is desirable to use a base in an amount of 1 to 30 mol, especially 1 to 5 mol per mol of the hydroxy compound (4). Exemplary bases are triethylamine, pyridine, dimethylaniline, and 4-dimethylaminopyridine, which may be used alone or in admixture. The reaction is carried out by adding the esterifying agent and the base sequentially or simultaneously while heating or cooling the system if necessary. The reaction yields a reaction mixture containing the esterified product. The desired ester compound (5) is separated from the reaction mixture by a conventional aqueous work-up procedure. If necessary, the compound (5) is purified by any conventional technique such as distillation, chromatography or recrystallization.
A polymer is prepared using the inventive lactone compound as a monomer. The method is generally by mixing the monomer with a solvent, adding a catalyst or polymerization initiator, and effecting polymerization reaction while heating or cooling the system if necessary. This polymerization reaction can be effected in a conventional way.
A resist composition is formulated using as a base resin the polymer resulting from polymerization of the lactone compound. Usually, the resist composition is formulated by adding an organic solvent and a photoacid generator to the polymer and if necessary, further adding a crosslinker, a basic compound, a dissolution inhibitor and other additives. Preparation of the resist composition can be effected in a conventional way.
The resist composition formulated using the polymer resulting from polymerization of the inventive lactone compound lends itself to micropatterning with electron beams or deep-UV rays since it is sensitive to high-energy radiation and has excellent sensitivity, resolution, and etching resistance. Especially because of the minimized absorption at the exposure wavelength of an ArF or KrF excimer laser and firm adhesion to the substrate, a finely defined pattern having sidewalls perpendicular to the substrate can easily be formed. The resist composition is thus suitable as micropatterning material for VLSI fabrication.

Lactone compounds having alicyclic structure and their manufacturing method

Abstract: R1 is H or C1-6 alkyl, R2 is H or an acyl or alkoxycarbonyl group of 1-15 carbon atoms which may be substituted with halogen atoms, Z is a divalent C1-15 organic group which forms a lactone ring with the carbonyloxy group, k is 0 or 1, and m is an integer from 0 to 5.


An image processing method, an apparatus and a device are provided. The method includes: a first image is captured according to a preset first exposure time and a second image is captured according to a second exposure time by using dual cameras; a first foreground area and a first background area of the first image are determined, and a second foreground area of the second image is determined; image fusion is performed on the second foreground area and the first foreground area to generate a third foreground area; and blurring processing is performed on the first background area, and the third foreground area and the first background area subjected to the blurring processing are composed to generate a target image.

The disclosure relates to the field of photographing technology, and in particular to an image processing method, an apparatus and a device.
Generally, in order to highlight a shot subject, a foreground area and a background area in an image are recognized and the background area is blurred. However, during capturing of an image, if brightness of a foreground is not appropriate, the subject in the image subjected to the blurring processing may not be highlighted. For example, if the shot subject is in a dark scene, an imaging effect is relatively poor, the brightness is quite low, and details are relatively fuzzy. After the background area is blurred, the shot subject still cannot be highlighted, and a visual effect achieved through the image processing is relatively poor.
In a related technology, to improve a visual effect achieved through the image processing, different exposure parameters are used for shooting to obtain multiple frames of images, and the multiple frames of images are composed to generate a high dynamic range image. However, a lot of time is required in both composite calculation and the process of capturing the multiple frames of images, which results in low generation efficiency of the high dynamic range image.

Image processing method, apparatus and device

GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.


Aspects of the disclosure relate to computing technologies. In particular, aspects of the disclosure relate to mobile computing device technologies, such as systems, methods, apparatuses, and computer-readable media for scheduling an execution of a task, such as a non-real time, non-latency sensitive background task on a computing device. In one implementation, the technique includes detecting a first state of a device, wherein the first state of the device is associated with a first power level and a first task, wherein the first power level is at least partially based on power consumption of a first task, determining that the first power level associated with the first state is above a threshold, and in response to determining that the first power level associated with the first state is above the threshold, and scheduling an execution of a second task on the device, wherein the second task is associated with automatically collecting of calibration data using at least one sensor.

Aspects of the disclosure relate to computing technologies. In particular, aspects of the disclosure relate to mobile computing device technologies, such as systems, methods, apparatuses, and computer-readable media that automatically calibrate one or more accelerometers and/or one or more other sensors, such as motion sensors, magnetometers, gyroscopes, and/or the like.
Increasingly, computing devices, such as smart phones, tablet computers, personal digital assistants (PDAs), and other mobile devices, include accelerometers and/or other motion sensors that may allow these devices to capture motion and/or other sensed conditions as a form of user input. As the inclusion of accelerometers and/or other motion sensors in computing devices becomes more common, the ways in which the computing devices process and/or otherwise use the motion information provided by such accelerometers and/or other motion sensors likewise becomes more sophisticated. Aspects of the disclosure provide more convenient and effective ways of enhancing how the information provided by accelerometers and/or other motion sensors can be interpreted and/or otherwise processed by a computing device, for instance, by providing ways of automatically calibrating accelerometers and/or other motion sensors.


A method and apparatus use a photonic-crystal fiber having a very large core while maintaining a single transverse mode. In some fiber lasers and amplifiers having large cores problems exist related to energy being generated at multiple-modes (i.e., polygamy), and of mode hopping (i.e., promiscuity) due to limited control of energy levels and fluctuations. The problems of multiple-modes and mode hopping result from the use of large-diameter waveguides, and are addressed by the invention. This is especially true in lasers using large amounts of energy (i.e., lasers in the one-megawatt or more range). By using multiple small waveguides in parallel, large amounts of energy can be passed through a laser, but with better control such that the aforementioned problems can be reduced. An additional advantage is that the polarization of the light can be maintained better than by using a single fiber core.

Rare-earth (RE) doped, pulsed fiber lasers and amplifiers constitute efficient and compact optical sources that can emit a diffraction-limited Gaussian beam of highly controlled spectral quality. The output power generated by these sources is limited, however, by parasitic nonlinear optical effects, amplified spontaneous emission, and damage to optical components due to high optical power.
Nonlinear effects include stimulated Brillouin and Raman scattering (SBS and SRS), self- and cross-phase modulation (SPM and XPM), and four-wave mixing (FWM). The common origin of these effects is the high optical intensity in the fiber core and long path for the nonlinear interaction between the in-fiber optical beam and fiber material (e.g., silica). These effects hamper in particular the generation of high-peak-power pulses by causing unwanted spectral broadening, distortion of the pulse temporal profile, and sudden power instabilities that result in optical damages.
The build-up of amplified spontaneous emission (ASE) is due to the high optical gain available in the fiber core in the time interval between pulses. ASE constitutes an unwanted continuous-wave (CW) noise, which degrades the pulse/background contrast and, most importantly, limits the attainable pulse energy by using up gain.
Finally, optical damages can occur in the fiber because of material breakdown in the presence of high optical intensities. The fiber facets are especially vulnerable because exposed to potential contaminants and subject to defects that can initiate damage.
There is a need for fiber lasers and optical amplifiers configured to emit pulses of considerably higher energy and peak power than currently available. These sources must be designed so as to circumvent the limitations described above.

Method and apparatus for spectral-beam combining of megawatt-peak-power beams from photonic-crystal rods


An RFID tag mounting circuit board has a configuration in which an RFIC chip, a minimum antenna, a circuit which matches the impedance of the RFIC chip and that of the antenna are mounted on a printed circuit board. With this configuration, the area occupied by the antenna of an RFID tag is suppressed, and a decrease in the component mounting density of the printed circuit board is also suppressed. The RFID tag mounting circuit board is configured to be capable of managing the histories of all components on a per-printed-circuit-board basis by attaching a reading device for an RFIC chip to a chip mounter which mounts an IC chip.

Examples of a conventional technique for managing the history of an electronic component on a printed circuit board using an RFID tag include one disclosed in JP-A-2007-66989 (Patent Document 1). Patent Document 1 discloses management of the history of an electronic component by mounting an RFID tag having an antenna and an IC chip within a printed circuit board. More specifically, there is disclosed a printed circuit board including at least one conductor layer and having an RFID tag placed therein or thereon which is configured such that the upper and lower surfaces of the RFID tag have no wiring pattern made of the conductor layer. There is also disclosed a printed circuit board including at least one conductor layer and having an RFID tag which is structured such that a through hole having the same vertical and horizontal dimensions as those of the RFID tag is formed in a part of the printed circuit board without any wiring pattern made of the conductor layer and such that the RFID tag is embedded in the through hole.
WO 97/09641 (Patent Document 2) discloses a formation of an antenna of an RFID tag on a printed circuit board (PCB) or at a metal layer in a PCB. The RFID tag includes a semiconductor circuit contained in an electronic package, and an RF antenna unit of the tag is formed in or on the PCB. The electronic package is disclosed to be connected to the antenna via pads on the PCB.
In the technique disclosed in Patent Document 1, a common IC tag, i.e., an antenna having an IC chip mounted thereon is affixed to a printed circuit board. For this reason, printed wiring cannot be provided in a region on the printed circuit board where the antenna is arranged in Patent Document 1.
In the technique disclosed in Patent Document 2, a printed circuit board has an antenna formed thereon and an IC chip mounted thereon. To this end, a multilayer board is employed as the printed circuit board, and the antenna is formed using layers (see FIG. 2 in Patent Document 2). An area larger than that of the IC chip is required to achieve this configuration. In other words, since an antenna is present on a printed circuit board in each of Patent Documents 1 and 2, the component mounting density of the printed circuit board decreases.
The capacitance between an antenna and printed patterns (wiring patterns) peripheral to an RFID tag changes depending on the layout of the printed patterns. This changes the tuning frequency of the antenna and may cause the communication distance of the RFID tag to fluctuate. Accordingly, antenna design needs to consider and include matching of the impedances of an IC chip and an antenna and further needs to be done with peripheral patterns in mind. Printed circuit board-based design is thus required, and the number of man-hours required for design increases.
A case where replacement of lots of mounted components has occurred when a large number of electronic boards are continuously manufactured, i.e., production of electronic boards managed in units of a plurality of electronic boards will be considered next. Hereinafter, one production unit will be referred to as a batch. In a conventional case using a barcode or the like, if components A have run out during processing for a batch, and replacement of component reels for components A has occurred, information indicating that the component reel for components A has been replaced with another is managed as management information, but it is impossible to determine for which printed circuit board of the batch the replacing reel for components A has been used. In other words, lot management of components A to be used cannot be performed. Even if an RFIC (Radio Frequency Integrated Circuit) chip which is easier to individually manage than a barcode is mounted, since an ID can be generally read until after a reflow process, i.e., until the RFIC chip is soldered to a printed circuit board, it is impossible to determine the time of occurrence of replacement of reels for components A (replacement of lots) during processing for a batch, as in the case of a barcode.
When an RFID tag is attached to a printed circuit board in advance, if an ID in an RFIC can be read before a component mounting process (before the RFIC enters a chip mounter), component reel replacement histories can be managed on a per-printed-circuit-board basis. However, the position where a reader antenna is set needs to be adjusted according to the size of the printed circuit board and the position where the RFID tag is attached. If an RFID tag is affixed, poor silk screening may occur due to the thickness of the tag in a solder paste silk screening process. If an RFID tag is embedded in a printed circuit board, costs and the yield in an embedding process become issues.


A support system for a trough-shaped solar collector assembly includes a support arm comprising first and second curved rails and an interconnecting web structure. The web structure is secured along first and second opposite edges thereof to first and second web engaging structures, which are provided along facing surfaces of the first and second rails, respectively. Prior to fixedly securing the web structure to the web engaging structure of the first and second curved rails, the location and/or the orientation of the web structure are adjustable for supporting interconnection of the first and second curved rails with different rates of convergence between the first and second curved rails. The support arm further includes a plurality of mirror-attachment brackets coupled to the first rail for attaching the trough-shaped solar collector assembly to the support arm and structure attachment brackets for mounting the support arm to a structure.

Concentrating Solar Power (CSP) systems utilize mirrors to concentrate the sun's energy onto points or lines. For instance, trough-shaped solar concentrators focus the sun's energy onto a fluid filed tube; the hot fluid is then transferred to a more conventional steam turbine power plant or similar system to generate electricity. One specific and non-limiting example utilizes a trough that is parabolic in a cross section taken in a plane that is normal to the length of the trough. With the assistance of a tracking system, parabolic trough collectors are very efficient as they follow the movement of the sun during the course of a day. For simplicity, the following discussion refers to parabolic troughs and parabolic mirrors. Of course, other suitable shapes are known.
As solar energy collector apparatuses incorporating parabolic type collectors are now being required to satisfy ever-larger energy requirements, they necessarily become physically larger. In some apparatuses, the aggregate collector surface may typically approach thousands of square meters. Consequently, reliable support for the large parabolic mirrors is critical to ensure excellent performance (focus) in varying atmospheric conditions and to guard against mirror breakage. Some of the key issues include overall frame deflection from its own weight, and that of the attached mirrors and wind loads. Prior art frames for solar trough designs relied on steel fabrications and weldments or aluminum extrusions configured and joined using techniques developed in the building construction industry. Such techniques require pre-assembly and transportation of large frame sections, often to locations that are difficult to access, or they require labor intensive assembly of components on-site, often under unfavorable conditions.
U.S. Pat. No. 4,423,719 discloses a parabolic trough solar energy collector that is fabricated without the need for any blind fasteners or blind fastening devices. An integrated parabolic solar energy collector is provided which can be welded or fastened with spot welds, seam welds, rivets, bolts or the like.
U.S. Pat. No. 4,135,493 discloses a parabolic trough solar energy collector including an elongated support with a plurality of ribs secured thereto and extending outwardly therefrom. One surface of the ribs is shaped to define a parabola and is adapted to receive and support a thin reflecting sheet, which forms a parabolic trough-shaped reflecting surface. One or more of the collectors is adapted to be joined end-to-end, and supported for joint rotation to track the sun.
U.S. Patent Application Publication No. 2010/0050560 discloses a parabolic trough solar energy collector frame including a plurality of chords. The frame comprises a plurality of extruded profiles, including chord sleeves, struts and strut end pieces, each chord sleeve having at least one chord sleeve fin, each chord sleeve positioned about one of the chords. The frame comprises a plurality of struts, at least one of the struts having a strut end piece having at least one strut end piece fin that connects with a chord sleeve fin to connect the plurality of chords. The frame comprises a platform supported by the chords and struts, on which the solar mirrors are disposed.
PCT Publication WO 2010/078004 discloses a solar energy collector apparatus comprising a solar collector panel having a parabolic shape, and a base comprising a pair of spaced apart support frames. Each support frame has a parabolic shape, which corresponds to the parabolic shape of the solar collector panel. Spaced apart rollers may be positioned along an upper surface of each support frame to support the solar collector panel. A drive mechanism may be coupled to the solar collector panel for rotation thereof. The solar collector panel may include a pair of spaced apart rollers to ensure that the solar collector panel rotates squarely with respect to the base.
Unfortunately, even in view of the systems that have been discussed in the preceding paragraphs, there still exists a need for a simplified support system and method for use with trough-shaped solar energy concentrators. It would therefore be advantageous to provide a system and a method that overcomes at least some of the limitations of the prior art.

Support system and method for trough-shaped solar energy concentrations


The application discloses a method and apparatus for providing interoperability for a mobile subscriber unit (MSU), employing a first protocol e.g., SCEP, with a packet-data subsystem operating at a second protocol e.g., SNDCP. The method includes determining that the first protocol employed by the MSU is different from the second protocol operated by the packet data subsystem. The method then includes creating a context information for the MSU when the determined first protocol is different from the second protocol. Further, the method includes determining a header associated with the second protocol based on the created context information and then receiving at least one data packet associated with the first protocol from the MSU. The method then encapsulates the at least one data packet with the determined header associated with the second protocol. The method then transmits the at least one encapsulated data packet to the communication network through a context manager.

As the public safety market continues to require increased functionality of two-way radio, association of public safety communications officials (APCO) through project 25 (P25) encourages participation of equipment suppliers and organizations to find solutions that meet the needs of the public safety market. In general the APCO standard specifies two approaches for providing packet data internet protocol (IP) bearer service on conventional channels. The first approach employs simple common air interface Encapsulation protocol (SCEP), and the second approach employs sub-network dependent convergence protocol (SNDCP).
In the existing conventional systems, the subscriber units employing the SCEP protocol can communicate only with the infrastructure system operating at the SCEP protocol. Similarly, the subscriber units employing SNDCP protocol can communicate only with the infrastructure system operating at the SNDCP protocol. However, migrating the subscriber unit employing the SCEP protocol to the system having SNDCP protocol currently requires replacement of the system's infrastructure as well as all of its subscriber units. This is costly and undesirable.
In the existing technology, the challenge is that the SCEP and SNDCP based subscribers cannot operate on the same channel. Other systems may face similar challenges when attempted to handle multiple protocols on the same channel.
Accordingly, there exists a need for providing interoperability between two different protocols.

Method and apparatus for providing interoperability between a first protocol and a second protocol


A duobinary optical transmission apparatus is provided to generate duobinary optical signals, without using an electric low-pass-filter (LPF), by restricting a bandwidth of a Mach-Zehnder-interferometer-type optical intensity modulator (MZ MOD). Alternatively, a LPF having a single pole with a single capacitor is implemented instead of an expensive LPF, thereby providing a simple transmitter with a lower production cost in comparison with a transmitter using a conventional electric LPF.

1. Field of the Invention
The present invention relates to a duobinary optical transmission apparatus using a duobinary optical transmission technique.
2. Description of the Related Art
Typically, a Dense Wavelength Division Multiplexing (DWDM) optical transmission system transmits an optical signal comprised of a plurality of channels with different wavelengths using a single optical fiber in such a way that it enhances transmission efficiency. As such, the DWDM optical transmission system has been widely used in a superhigh-speed Internet network requiring a large amount of data transfer due to its ability to transmit optical signals irrespective of the transfer rate. Recently, systems capable of transmitting more than 100 channels via a single optical fiber using the DWDM optical transmission techniques have been produced commercially, and a new system capable of transmitting more than 200 channels each having a transfer rate of 40 Gb/s (Gigabit per second) simultaneously to accomplish a transfer rate of more than 10 Tbps is being intensively researched.
Although new system accommodates rapidly increasing data traffics as well as transfer requests for high-speed data of more than 40 Gbps, a conventional optical intensity modulation method using a NRZ (Non-Return to Zero) method has a limitation in increasing the transfer quantity as an abrupt interference and distortion between channels occurs in a prescribed zone, which is less than a channel interval of 50 GHz. In addition, the DC frequency components of a conventional binary NRZ transmission signal and the high-frequency components spreading in a modulation process cause nonlinear characteristics and dispersion while the signals are propagated along the optical fiber medium, thereby limiting a transmission distance at a high-speed transfer rate over 10 Gbps.
Currently, an optical duobinary technique has been intensively researched as a new optical transmission technique for obviating the transmission distance limitation caused by the chromatic dispersion. The optical duobinary technique has an advantage in that it reduces a width of a transmission spectrum much more than a general binary transmission method. The transmission distance in a dispersion limitation system is inversely proportional to a square of the transmission spectrum bandwidth. As such, in the case where the transmission spectrum bandwidth is reduced by half, the transmission distance increases by four times. Moreover, a carrier wave frequency is suppressed in a duobinary transmission spectrum such that limitations in the output optical power caused by the Brilloum Scattering stimulated in the optical fiber are reduced.
FIG. 1 is an exemplary view illustrating a block diagram of the conventional duobinary optical transmission apparatus, and FIGS. 2a˜2c are views illustrating eye-diagrams of output signals at A, B and C nodes shown in FIG. 1, respectively.
Referring to FIG. 1, a conventional duobinary optical transmission apparatus includes a Pulse Pattern Generator (PPG) 10 for generating electric pulse signals using a NRZ method; a pre-coder 20 for encoding the electric pulse signals; drive amplifiers 30 and 31 for amplifying a two-level signal generated from the pre-coder 20; LPFs (Low Pass Filters) 40 and 41 for converting the amplified two-level signal into a three-level signal and reducing a bandwidth of the three-level signal; a laser source 50 for generating a carrier wave; and, a Mach-Zehnder-interferometer-type optical intensity modulator (MZ MOD) 60 for receiving the amplified three-level signal and converting the carrier wave into a two-level optical signal.
In operation, the NRZ-type electric pulse signals generated by the PPG 10 are encoded as binary signals of 0 or 1 by the pre-coder 20. An output eye-diagram at a node A is shown in FIG. 2a. The two-level binary signal generated from the pre-coder 20 is amplified by the drive amplifiers 30 and 31, then transmitted to the LPFs 40 and 41. The LPFs 40 and 41 each have a bandwidth corresponding to about ¼ of a clock frequency of the two-level binary signal. This excessive bandwidth restriction causes interference between codes, and the two-level binary signal is converted into a three-level duobinary signal because of this interference between codes. An output eye-diagram at a node B is shown in FIG. 2b.
Note that the amplified three-level duobinary signal is used as a driving signal of the Mach-Zehnder-interferometer-type optical intensity modulator (MZ MOD) 60. The carrier wave generated from the laser source 50 modulates its own phase and its own optical intensity according to the driving signal of the MZ MOD 60, and is thereby generated as a two-level optical duobinary signal. An output eye-diagram at a node C is shown in FIG. 2C. Referring back to FIG. 1, a reference character Q indicates the inverted signal of a signal Q, and the signals Q and Q are respectively transmitted to a positive electrode (+) and a negative electrode (−) of the MZ MOD 60 with a dual electrode structure.
The MZ MOD 60 is classified into a Z-cut type MZ MOD and an X-cut type MZ MOD according to its own electrode structure. As shown in FIG. 1, the Z-cut type MZ MOD having a dual electrode connects its own both arms to the drive amplifiers 30 and 31 and the LPFs 40 and 41 in such a way that a three-level electric signal is applied to each of both electrodes of the Z-cut type MZ MOD. Although the X-cut type MZMOD having a single electrode is not shown in the drawings, it connects its own one arm to a drive amplifier and a LPF in order to transmit a three-level signal to one electrode.
FIGS. 3a˜3b are views illustrating the eye-diagrams of output signals transmitted via a single mode optical fiber using a duobinary optical transmission apparatus. Referring to FIGS. 3a˜3b, it is noted that eye-diagrams are relatively maintained clearly in the range of a transmission distance from 0 km (shown in FIG. 3a) to 160 km (shown in FIG. 3b).
However, the aforementioned conventional duobinary transmission technique generates a three-level electric signal using a LPF, such that a difference is generated on the basis of dependency of transmission quality corresponding to the transmission characteristics of a LPF and the length of a Pseudo Random Bit Sequence (PRBS), thereby causing a serious problem in an overall system. This jitter problem is generated in the Z-cut type or X-cut type conventional structure. Accordingly, a dependency of such signal patterns provides a limitation in a real optical transmission operation.
Furthermore, in case of using the Z-cut type MZ MOD having a dual electrode, the output signals Q and Q are respectively input to LPFs of both arms of the Z-cut type MZ MOD, amplified by amplifiers, and then transmitted to both terminals of the Z-cut type MZ MOD. In this case, the Z-cut type MZ MOD must perform a push-pull operation, where electric signals applied to both terminals of the Z-but type MZ MOD must have different polarities having a difference 180° therebetween. In the case where the electric signals do not have such different polarities, it is necessary to adjust a phase using a delay line. Thus, two LPFs and two amplifiers must have the same characteristics. However, it is impossible to manufacture two LPFs and amplifiers with same characteristics as a tiny difference between the two LPFs or the two amplifiers is unavoidable during the manufacturing process.
In addition, a Bessel-Thomson type LPF widely used as a LPF is very expensive, thereby increasing the cost of production of an overall optical transmission apparatus.

Duobinary optical transmission apparatus


A 3-D observation apparatus and 3-D observation system, as well as another observation apparatus, are provided such that it is possible to make observations while substantially in the same posture, without glasses, of either a plurality of 3-D images, or of a 2-D image and a 3-D image. Bright images are provided, there is great freedom in the position at which observations can be made, no distortion of the images is created even if the observer changes his position, and observations can be made with a comfortable observation posture.

The present invention relates to a three-dimensional observation apparatus and a three-dimensional observation system of the type that enables an individual to make three-dimensional (hereinafter 3-D) observations without using glasses. Previously, an observation apparatus as disclosed in Japanese Laid-Open Patent Publication S51-24116 has been proposed for such a 3-D observation apparatus. As shown in FIG. 32, this observation apparatus comprises two display apparatuses 51R and 51L, two concave mirrors 52R and 52L, and a single concave mirror 53 that faces the concave mirrors 52R and 52L. The concave mirrors 52R and 52L are designed and positioned so that the radii of curvature and the centers of curvature thereof match. In FIG. 32, reference numbers 54R and 54L designate the right and left pupils, respectively, of an observer.
FIG. 33 is a side view of the observation apparatus illustrated in FIG. 32. In FIG. 33, the top and bottom have been reversed in order to simplify understanding its operation and, in addition, the display apparatus has been omitted from the drawing. Furthermore, in FIG. 33 reference numbers 54R′ (54L′) and 54R″ (54L″) indicate conjugate positions of the observer's pupils. Each of the display apparatuses 51R (51L) shown in FIG. 32 is positioned in the range from the position PR(∞) (PL(∞)) (i.e., at infinity) to the focal point PR(f) (PL(f)) shown in FIG. 33. When the display apparatuses 51R (51L) are placed at the position PR(∞) (PL(∞)), light emitted from the display apparatuses 51R (51L) is reflected by the concave mirrors 52R (52L) and then forms an image at the front-side focal position A of the concave mirror 53. Furthermore, the light is then reflected by the concave mirror 53 and is guided to the observer's pupils 54R (54L) as substantially collimated light rays. When the display apparatuses 51R (51L) are placed at the front-side focal position PR(f) (PL(f)) of the concave mirrors 52R (52L), light emitted from the display apparatuses 51R (51L) is reflected by the concave mirrors 52R (52L) and becomes substantially collimated. Furthermore, after being reflected by the concave mirror 53, the light forms an image at the back-side focal point B of the concave mirror 53. Following this, the image spreads and is guided to the observer's pupils 54R (54L).
Furthermore, as this kind of conventional observation apparatus does not use a half-mirror, bright 3-D images may be obtained. However, with such a conventional 3-D observation apparatus, it is impossible to observe at one position while substantially in the same posture, the observation images from different display apparatuses. In addition, it is impossible to make multi-surface observations such as observations that allow 2-D images and 3-D images to be observed while substantially in the same posture.
Moreover, with the above-described 3-D observation apparatus, there are two concave mirrors that create distortions in the image, and consequently the positioning of the two concave mirrors which face each other is limited to positions that mutually compensate for this distortion. With this type of arrangement, distortion of the image and size of fluctuations in the focal point are determined in response to errors in installing the concave mirrors. In order to mitigate such problems, the surface precision of the concave mirrors must be kept high, while errors in installing the two concave mirrors must be kept extremely small. However, this results in high manufacturing and installation costs for the mirrors.
In addition, because the surface that the observer faces is that of a concave mirror, image distortion is large with respect to differences in observation position. Consequently, there is no freedom in observation position. This results in the observer's posture also being restricted, and results in observations being somewhat inconvenient.
Furthermore, in order to increase freedom in observation, it is necessary to enlarge the exit pupils. However, in an observation apparatus having the above-described design, enlarging the exit pupils requires that the concave mirrors be enlarged. Consequently, this results in the display apparatus as a whole becoming larger.

Three-dimensional observation apparatus and three-dimensional observation system


A weather radar detects and removes spurious aircraft from a weather radar display by using one of the methods of differentiating radar return length, estimating a vertical gradient of reflectivity, tracking radar returns into regions that are eliminated from the weather display to provide differentiation, tracking areas of radar returns that allow detection and removal of the spurious aircraft in relative geometries, differentiating Doppler velocity, and differentiating spectral width. The methods may be used individually or in combination to improve performance.

This invention relates to weather radar, spurious aircraft detections, and specifically for removal of spurious aircraft detections from a weather radar display when displaying of such detections is not desired.
Weather radars are known in the art for detecting and displaying severe weather to a crew in an aircraft on a two-dimensional map display showing range, bearing, and intensity of a detected weather system, which may be convective or stratiform in nature. Flight hazards due to weather conditions are primarily the result of precipitation and turbulence. Airborne weather radars have been optimized to detect rain.
As weather radars become more sensitive and hold and process previously sampled state information, other aircraft are being detected and displayed to flight crews when not desired. Newer radars use longer transmitter pulse widths that make the problem worse since the length of the radar return from aircraft on the radar display is not substantially different from the radar return length as produced by a small area weather feature.
A spurious aircraft may appear as multiple images on a weather radar system display due to storage of the target echo in internal memory and the motion of the spurious aircraft. Having a weather display with spurious aircraft displayed is undesirable since it may lead to difficult decision making about the weather and the spurious aircraft motion.
What is needed is a reliable low-cost system for detection and removal of spurious aircraft from a weather radar display.

Removal of spurious aircraft detections on weather radar


The present invention relates to a solid electrolytic capacitor provided with a anode made of a metal or an alloy having valve action, a dielectric layer formed on the anode, and an electrolyte layer consisting of a conductive polymer layer formed so as to have contact with a portion of the region on the dielectric layer surface and a manganese dioxide layer formed so as to have contact with the other portion of the region on the dielectric layer surface.

1. Field of the Invention
The present invention relates to a solid electrolytic capacitor and a method of production the same.
2. Description of the Related Art
Since niobium has a dielectric constant about 1.8 times as high as that of tantalum, which is a material for conventional solid electrolytic capacitors, it draws attention as a material for next generation, high capacity solid electrolytic capacitors. Japanese Patent Application Laid-Open (JP-A) No. 07-153650 discloses a solid capacitor obtained by successively forming a solid electrolyte of manganese dioxide and a conductive layer for a cathode on an anode sintered body obtained by sintering a metal powder for valve action such as tantalum and niobium.
However, in the solid electrolytic capacitor disclosed in JP-A No. 07-153650, since the conductivity of manganese dioxide is low, there occurs a problem that ESR (equivalent series resistance) becomes high.
JP-A No. 5-136005 discloses a technique of forming a conductive polymer layer by electrolytic polymerization on a manganese dioxide layer. However, by this technique, ESR could not decrease sufficiently.

Solid electrolytic capacitor and method of producing the same