Some embodiments provide a method for optimally decomposing patterns within particular spatial regions of interest on a particular layer of a design layout for a multi-exposure photolithographic process. Specifically, some embodiments model the spatial region using a mathematical equation in terms of two or more intensities. Some embodiments then optimize the model across a set of feasible intensities. The optimization yields a set of intensities such that the union of the patterns created/printed from each exposure intensity most closely approximates the patterns within the particular regions. Based on the set of intensities, some embodiments then determine a decomposition solution for the patterns that satisfies design constraints of a multi-exposure photolithographic printing process. In this manner, some embodiments achieve an optimal photolithographic printing of the particular regions of interest without performing geometric rule based decomposition.

An integrated circuit ("IC") is a device (e.g., a semiconductor device) or electronic system that includes many electronic components, such as transistors, resistors, diodes, etc. These components are often interconnected to form multiple circuit components, such as gates, cells, memory units, arithmetic units, controllers, decoders, etc. An IC includes multiple layers of wiring that interconnect its electronic and circuit components.
Design engineers design ICs by transforming logical or circuit descriptions of the ICs' components into geometric descriptions, called design layouts. IC design layouts typically include (1) circuit modules (i.e., geometric representations of electronic or circuit IC components) with pins, and (2) interconnect lines (i.e., geometric representations of wiring) that connect the pins of the circuit modules. A net is typically defined as a collection of pins that need to be connected. In this fashion, design layouts often describe the behavioral, architectural, functional, and structural attributes of the IC.
To create the design layouts, design engineers typically use electronic design automation ("EDA") applications. These applications provide sets of computer-based tools for creating, editing, analyzing, and verifying design layouts.
Fabrication foundries ("fabs") manufacture ICs based on the design layouts using a photolithographic process. Photolithography is an optical printing and fabrication process by which patterns on a photolithographic mask (i.e., photomask) are imaged and defined onto a photosensitive layer coating a substrate. To fabricate an IC, photomasks are created using the IC design layout as a template. The photomasks contain the various geometries (i.e., features) of the IC design layout. The various geometries contained on the photomasks correspond to the various base physical IC elements that comprise functional circuit components such as transistors, interconnect wiring, via pads, as well as other elements that are not functional circuit elements but that are used to facilitate, enhance, or track various manufacturing processes. Through sequential use of the various photomasks corresponding to a given IC in an IC fabrication process, a large number of material layers of various shapes and thicknesses with various conductive and insulating properties may be built up to form the overall IC and the circuits within the IC design layout.
As circuit complexity continues to increase and transistor designs become more advanced and ever smaller in size (i.e., die shrink), advances in photolithographic processes are being pursued to enable the large scale, low cost manufacturing of such circuits. However, constraining factors in traditional photolithographic processes limit the effectiveness of current photolithographic processes. Some such constraining factors are the lights/optics used within the photolithographic processing systems. Specifically, the lights/optics are band limited due to physical limitations (e.g., wavelength and aperture) of the photolithographic process. Therefore, the photolithographic process cannot print beyond a certain pitch, distance, and other such physical manufacturing constraints.
A pitch specifies a sum of the width of a feature and the space on one side of the feature separating that feature from a neighboring feature. Depending on the photolithographic process at issue, factors such as optics and wavelengths of light or radiation restrict how small the pitch may be made before features can no longer be reliably printed to a wafer or mask. As such, the smallest size of any features that can be created on a wafer is severely limited by the pitch.
FIG. 1 illustrates a typical pitch constraint of a photolithographic process. In FIG. 1, a pitch 110 acts to constrain the spacing between printable features 120 and 130 of a design layout. While other photolithographic process factors such as the threshold 140 can be used to narrow the width 150 of the features 120 and 130, such adjustments do not result in increased feature density without adjustments to the pitch 110. As a result, increasing feature densities beyond a certain threshold is infeasible via a pitch constrained single exposure process.
Certain reticle enhancement techniques (RET) allow for photolithographic processes to extend beyond some of the various photolithographic manufacturing constraints such as the width constraint. Some common techniques include: using optical proximity correction (OPC) to distort photomask shapes to compensate for image errors resulting from diffraction or process effects that cause pattern inaccuracies, using off-axis illumination (OAI) for optimizing the angle of illumination for a particular pitch, using alternating phase shift masks (PSM) for improving lithographic resolution by introducing a particular phase shift between adjacent patterns or features on a photomask, and using scatter bars to place narrow lines or spaces adjacent to a feature in order to make a relatively isolated line behave more like a dense line.
However, these and other techniques are limited both by cost and effectiveness. To overcome these and other constraints, some fabrication processes have implemented a multiple exposure photolithographic process as illustrated in FIG. 2.
In FIG. 2, a design layout 205 specifies three features 210-230 that are pitch constrained and therefore cannot be photolithographically printed with a conventional single exposure process. Analysis of the characteristics (e.g., the band limitation) of the available photolithographic process and of the design layout 205 results in the decomposition of the design layout 205 into a first exposure 240 for printing features 210 and 230 and a second exposure 250 for printing feature 220. As such, the features 210 and 230 are assigned to a first photomask for printing during the first exposure 240 and feature 220 is assigned to a second photomask for printing during the second exposure 250.
FIG. 3 illustrates a decomposition of a pattern 310 defined in a layer of design layout for fabricating an IC into two sets of polygons 320 and 330. Each such decomposed set of polygons 320 and 330 is printed during an exposure of a multiple exposure photolithographic printing process. For instance, polygon set 320 is printed during a first exposure in order to produce contours 340 and polygon set 330 is printed during a second exposure in order to produce contours 350. The resulting union of the contours 340 and 350 generates pattern 360 that is sufficient to approximately reproduce the original pattern 310. Accordingly, a valid decomposition solution is such that the union of the contours created/printed from each exposure closely approximates specifications within the original design layout and satisfies multi-exposure photolithographic printing constraints (e.g., the band limit and the target layout specified within the design layout) with no resulting "opens", "shorts", or other printing errors materializing on the physical wafer.
Existing decomposition tools for decomposing layouts into one or more exposures are often rule based and proceed on a pattern by pattern (i.e., geometry by geometry) basis. Such tools are therefore applicable only to patterns for which a pre-programmed or known decomposition solution exists within a library. These tools are effective for decomposing simple designs with regular repeating patterns such as gradings including lines and spaces. However, design layouts with more sophisticated geometries (e.g., logic designs and microprocessor designs containing complex patterns and shapes with bends and jogs) cannot be processed using these existing decomposition tools as solutions do not exist for the unique patterns appearing within such design layouts. Instead, layout designers would be notified of the patterns for which a known solution does not exist. The layout designers would then be prompted to manually produce a decomposition solution for these patterns. To remedy this issue, solution providers must continually update the pattern libraries and algorithms used by these tools to accommodate the growing complexity of the design layouts.
Moreover, existing decomposition tools are inefficient in the manner by which they perform decomposition analysis. Repeated polygonal patterns within a single design layout are each independently analyzed and a solution is provided for each instance as if each instance is the first such instance. Therefore, the more dense a design layout, the more time and processing resources needed to process and decompose the design layout. Also, traditional prior art decomposition tools often operate in a local area by local area basis such that solutions provided to remedy printability issues appearing within a particular local area may have a detrimental effect to other unprocessed or processed local areas of the layout.
Therefore, there is a need to efficiently and effectively decompose an entire layout or section of a layout while avoiding the pitfalls associated with geometric rule based decomposition techniques. Moreover, there is need to generalize such techniques and tools such that the applicability of these techniques and tools is no longer restricted to a known or pre-programmed set of solutions.

System and method for model based multi-patterning optimization


A valve operating system includes: a decompression cam member that is provided on a camshaft, and moves between an operative position C where an exhaust tappet is operated in a valve opening direction in a compression stroke and an inoperative position D where the exhaust tappet is released; an exhaust gas recirculation cam member that is provided on the camshaft, and moves between an inoperative position F where the exhaust tappet is released and an operative position G where the exhaust tappet is operated in a valve opening direction in an intake stroke of the engine; and a common centrifugal mechanism that is driven by the camshaft to operate the decompression cam member to the operative position C in a starting rotation region of the engine and to the inoperative position D after the starting, and operate the exhaust gas recirculation cam member to the inoperative position F in a low speed operation region of the engine and to the operative position G in a high-speed operation region. Thus, the valve operating system can exert both a decompression function and an exhaust gas recirculation function.

1. Field of the Invention
The present invention relates to a valve operating system for an internal combustion engine including a camshaft interlocked with a crankshaft, and an intake cam follower member and an exhaust cam follower member that are driven by an intake cam and an exhaust cam formed on the camshaft to open and close an intake valve and an exhaust valve, respectively. More particularly, the present invention relates to a valve operating system for an internal combustion engine that uses the exhaust valve to exert a decompression function at starting and exert an exhaust gas recirculation function during high speed operation.
2. Description of the Related Art
Japanese Utility Model Application Laid-Open No. 55-137245 discloses a valve operating system for an internal combustion engine that slightly opens an exhaust valve in an intake stroke to recirculate an exhaust gas into a combustion chamber, thereby preventing an excessive increase in an exhaust gas temperature to prevent generation of NOx during high speed operation of the engine.
The conventional valve operating system can exert an exhaust gas recirculation function, but has no decompression function that slightly opens the exhaust valve in a compression stroke to appropriately reduce a cylinder pressure thereby reducing a starting operation load at starting of the engine.

Valve operating system for internal combustion engine


A switched reluctance motor is provided that includes a housing, a stator and a rotor received and installed within the housing, and a rotor position detector that detects a rotational position of the rotor at an outer side of the housing. With such structure, assembly may be quickly and easily performed, a sensor may be easily repaired and checked, and a bad influence on the sensor by temperature and dust may be reduced.

As known, the switched reluctance motor (SRM), which is so-called an SR motor, rotates a rotor by using a reluctance torque according to a change in the magnetic reluctance and has advantages in that its fabrication cost is low, it does not need much maintenance and has such high reliability that its life span is substantially permanent.
FIG. 1 is a sectional view of the related art switched reluctance motor, and FIG. 2 is a sectional view taken along line II-II in FIG. 1. As shown in the drawings, the switched reluctance motor includes a housing 11, a stator 21 fixed within the housing 11, a rotor 31 rotatably disposed with respect to the stator 21, and a rotor position detecting unit 41 that detects a rotational position of the rotor 31.
A plurality of through holes 13 are formed at side portions of the housing 11 to allow the interior and exterior to communicate with each other, and the stator 21 is fixedly disposed within the housing 11. The rotor 31 is installed to be rotatable centering around a rotational shaft 33 within the stator 21. The rotational shaft 33 is rotatably supported by a bearing 35 fixed at the housing 11.
The rotor position detecting unit 41 includes a sensor disk 43 integrally and rotatably combined with the rotational shaft 33, and a sensor unit 51 interworks with the sensor disk 43 to detect a rotational position of the rotor 31.
The sensor disk 43 is formed in a disk type and includes multiple protrusions 45 formed to be protruded to outer side along a radial direction at the circumference thereof. A support member 47 is combined at one side of the sensor disk 43 and combined with the rotational shaft 33 to support the sensor disk 43.
The sensor unit 51 includes multiple PCBs 53, a PCB fixing member 55 for fixing the PCBs 53 at the housing 11, and a photo-interrupter 57 having a light emitting part 58 and a light receiving part 59 that are disposed to be spaced apart with the protrusion 45 of the sensor disk 43 interposed therebetween. Here, the PCBs 53 and the photo-interrupters 57 are provided by the number corresponding to the phases (three phases) of a coil of the stator 21 and combined at each pre-set position.
The related art switched reluctance motor has the following problems. That is, because the sensor unit 51 is combined in the through holes 13 formed at the side of the housing 11, the stator 21 needs to be combined within the housing 11 in consideration of the position of the sensor unit 51 during assembling, so much attention and precision are required for the assembling.
In addition, because the light emitting part 58 and the light receiving part 59 are disposed within the housing 11 in which temperature is high and there is much dust, the life span and sensitivity of the light emitting part 58 and the light receiving part 59 are negatively affected.


A semiconductor wafer incorporating process control monitors and a method of incorporating the same are provided. In one aspect, the semiconductor wafer has a plurality of fields formed in a pattern thereon that is subdivided into n zones and has a center point. The semiconductor wafer is provided with a plurality of integrated circuits each of which is positioned in one of the plurality of fields. The semiconductor wafer also includes a plurality of diagnostic integrated circuits dispersed in a pattern. The pattern is such that each of the plurality of diagnostic integrated circuits is positioned in one of the plurality fields, one of the plurality of diagnostic integrated circuits is positioned in each of the n zones, and a circle of radius R from the center point will intersect at least one of the plurality of diagnostic integrated circuits where R is greater than or equal to the distance between the center point and the innermost of the plurality of diagnostic integrated circuits and less than or equal to the distance between the center point and the outermost of the plurality of diagnostic integrated circuits.

1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to structure and method for implementing diagnostic integrated circuits on a semiconductor wafer.
2. Description of the Related Art
Testing has been an integral component of semiconductor processing since the development of the earliest germanium-based bipolar integrated circuits. The need for testing then and now stems from both engineering and economic considerations. Circuit designers must be able to verify that circuits designed on paper and simulated on computer, work as intended when implemented in actual silicon. Similarly, process engineers must be able to track the behavior of the multitude of individual process steps used to fabricate a given integrated circuit. From an economic standpoint, it is critical for semiconductor manufacturers to be able to quickly pinpoint the origin of unacceptable yields so that the circuit design or the fabrication process may be altered as necessary without needlessly wasting lots of wafers that may cost several hundred thousand dollars or more.
Electrical and process verification testing of most integrated circuits is provided by test structures that are incorporated into a semiconductor wafer during the process of fabricating the various operational integrated circuits (e.g., microprocessors, random access memories, etc.) thereon. The test structures are designed to provide electrical verification test data on various components of the operational integrated circuits as well as verification of many of the myriad of process steps performed during the fabrication of the operational integrated circuits. In modem test structures, well over a hundred or more different types of parameters are routinely captured by the test structures.
Early test structures consisted of individual die commonly known as process control monitors ("PCM") that were placed in various die locations across the face of a given wafer and fabricated in concert with the surrounding operational integrated circuits. This type of test structure prevailed throughout the period of semiconductor manufacturer when 1.times. reticles were used for direct print or contact printing or projection scanning of semiconductor devices. Early in the last decade, the semiconductor industry transitioned away from 1.times. reticle processing in favor of lithographic stepping. As a consequence, PCMs as test structures were largely abandoned in favor of scribe line monitors ("SLM").
There are several disadvantages associated with conventional structures and methods for implementing PCMs and SLMs. In the conventional design and fabrication of PCMs, little attention has been paid to the tailoring of the configuration of a given PCM relative to surrounding operational integrated circuits or the particular dispersal of PCMs across the face of a given wafer. Manufacturing experience has demonstrated that the differences in the structural densities of the PCM and the surrounding operational integrated circuits can significantly degrade the yield of those operational integrated circuits that do surround a particular PCM. The differential structural density between a given PCM and the operational integrated circuits that surround it impacts the behavior of various etch and polish steps that are performed on the wafer. A given conventional PCM typically has a much lower structural density, that is, number and/or size of physical structures, e.g. gates, metallization lines, isolation structures, etc. per unit area than the surrounding operational integrated circuits, which typically have many more circuit devices and structures per unit area. As a result, etchants and polish solvents may be more aggressively consumed by the less structurally dense areas in the PCM than in the surrounding operational integrated circuits, resulting in inadequate etching and/or polishing of certain structures in the operational integrated circuits. The problem of differential structural density is further compounded by the fact that the die borders for conventional PCMs are routinely much larger than the die borders for the surrounding operational integrated circuits.
Conventional SLMs do not present the same types of yield problems associated with conventional PCMs. However, conventional SLMs often cannot provide sufficient electrical data. The problem is primarily one of packing density. SLMs are, as the name implies, fabricated in the scribe lines. Space is accordingly limited. As die sizes have increased to accommodate more complex circuits, the number of different test parameters and thus SLMs that are required has increased proportionally. However, it is frequently difficult to pack the requisite number of SLMs into the confined spaces of the scribe lines. Thus, compromises in the amount of date gathered must be made.
Another short coming common to both conventional PCM and SLM techniques is the propensity to inadequately capture data on certain types of process variations that can propagate at various locations on a given wafer. Process variations can occur during many of the scores of process steps performed on a wafer during integrated circuit manufacture. Many of these are due to the dynamics of heat transfer across a flat disk. For example, during the formation of a thermal oxide layer on a given wafer, a band or ring of the thermal oxide may develop with a significant variation from the anticipated nominal thickness. The band itself may have a uniform thickness that deviates from the anticipated nominal thickness of the rest of the film or may exhibit a gradient. In either event, if the band of variable thickness does not form over one of the appropriate test structures fabricated on the wafer, the extent and impact of the area of process variation may not be adequately characterized so that its origin may be determined and appropriate modifications to the process flow may be made to eliminate it.
Some conventional process flows avoid the problem of degraded yield due to the impact of PCM fabrication on adjacent operational integrated circuits by utilizing dedicated test wafers upon which only test structures are fabricated. While this technique avoids the aforementioned yield problems, data acquired from dedicated test wafers does not necessarily correlate well with the behavior of the electrical circuits and the processes used to form them on actual production wafers.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.

Useable drop-in strategy for correct electrical analysis of semiconductor devices


The present disclosure relates to systems and methods for image processing. The method may include receiving an original image including a plurality of pixels; determining a plurality of smoothed images by applying a plurality of filtering kernels to the plurality of pixels of the original image, wherein each of the plurality of filtering kernels may be associated with a respective kernel size; determining a plurality of enhanced images by comparing the original image with the plurality of smoothed images; and generating a target image based on at least one of the plurality of enhanced images and at least one of: the original image or at least one of the plurality of smoothed images.

Images usually contain a plurality of features, which can provide significant reference information in various fields (e.g., medical field). However, images obtained based on existing imaging techniques usually include blur or noise, which may influence image quality and subsequent application (e.g., medical diagnosis). Therefore, image enhancement becomes increasingly important for image processing research. Generally, an image includes a plurality of features under different scale sizes. Accordingly, it is desirable to provide systems and methods for image enhancement for features under different scale sizes.

Systems and methods for image processing

SHANGHAI UNITED IMAGING HEALTHCARE CO., LTD.


A distributed private branch telephone exchange (PBX) including a local area network carrying telephony traffic, an interface to the PSTN and a station interface connecting to a telephone device transmitting telephony over the local area network. The distributed PBX may contain a number of multi-port modules connected over a local area data network. The multi-port modules convert between synchronous and asynchronous signals and connect between a telephony environment, such as a telephone device, a local area network, and a personal computing device. The distributed PBX also includes PBX software and a graphical user interface (GUI) which facilitate the management of various PBX functions.

The present invention relates in general to telephone voice communication networks, more particularly, it relates to an local area computer network capable of delivering telephone services.
A typical modern office building provides each worker with their own telephone. Rather than purchasing all the required telephone lines from the local telephone company, most offices have established their own private telephone networks. The private telephone network can handle calls originating and terminating within the building without going through the public switched telephone network (PSTN) provided by the telephone companies. Thus, an office building need only purchase a smaller number of access lines or trunks to connect its private telephone network to the PSTN. Such private telephone networks are commonly known as Private Branch Exchanges (PBXs).
In addition to a PBX, a modern office typically has a number of personal computers (PCs) connected by a local area network (LAN). The PC LAN connects together the PCs in the office to share data, printers or other computer peripheral hardware. Although many different PC LAN configurations are possible, each PC on the network is typically connected via a connecting medium to one or more central hubs or switches which allow communication between network nodes. A primary computer or file server typically stores a large quantity of data and implements a data transmission control protocol to arbitrate the distribution of data over the network.
Traditionally, LANs and PBXs have served different functions and have been developed as independent systems. For example, a typical Ethernet LAN simultaneously broadcasts digital data across a shared common bus to all network destinations at data rates up to ten million bits per second (Mbps). Because of the broadcast transport scheme of Ethernet LANs, a number of devices on the network may transmit data simultaneously. Network transmissions are therefore subject to collisions which require the data to be retransmitted. In contrast, a PBX establishes separate dedicated point-to-point connections which are typically operated at lower data rates of only tens of thousand-bits per second (Kbps). Moreover, PBXs must handle the telephony supervision and signaling functions required to interface with the PSTN, and to handle calls within the local telephone network. The real-time event handling and audio distribution required to implement real-time telephony functions are generally inconsistent with the architecture of LANs.
Attempts to integrate PBXs and LANs have been unsuccessful partly due to the increased cost of building a single system which meets the requirements of both networks. In addition to the cost, the functionality and performance of the integrated system is often compromised when compared to separate dedicated systems. For example, providing a PBX with the increased data capacity required by LANs have prohibitively increased the cost of the PBX without delivering the performance provided by dedicated LANs.
A typical office today thus uses two separate and independent networks: a PC LAN to distribute computer data, and a PBX to provide telephone services. The hardware infrastructure of the two networks is independent and separate. Each network requires its own dedicated physical connection medium such as coaxial cable, twisted pair wiring, etc. Traditionally, PBX switching equipment, terminal equipment, control computer resources and in-house wiring are separate devices, not shared or leveraged by the two networks.
The term computer telephone integration (CTI) describes any system which employs a computer to enhance or control telephony. This is implemented by interfacing PBXs and computers, bringing caller information to the computer so database lookup and screen pops to the called agent are possible. Other implementations utilize separate servers with new buses to add voice processing capability. Recently, CTI developers have developed equipment which, when added to a standard PC, allows the functions of a PBX to be implemented. The same PC which operates on the LAN may now also be used to implement the PBX.
Despite the integration afforded by CTI, artifacts of the different development of PBXs and LANs remain. Although the PBX and LAN may be implemented by a standard PC, and may even physically reside within the same device, the two networks remain separate and independent systems. The LAN continues to use its own data transport protocol and physical connection media to each device on the network. The PBX uses its telephony signaling scheme, switching equipment, and separate dedicated physical connection media to transmit voice data.
More recently, ATM (asynchronous transfer mode) networks have been envisioned to integrate digital data with multimedia voice and video onto a single high speed line or "pipe". ATM packages and transmits digital data in small 53 byte fixed-length messages or cells while providing high bandwidths of 25 Mbps and higher. Although ATM networks were envisaged to provide transport of data, voice and video, little has been done to facilitate the transmission of real-time, low latency voice traffic on ATM local area networks. ATM voice transmission efforts to date have primarily been focused on higher-capacity wide area networks, campus backbones and longer haul transmission networks.
The ATM forum has developed ATM standards for local area networks. A great strength of ATM is the ability of the network to assign an appropriate quality of service (QoS) class to a particular transmission. ATM networks can guarantee that strict requirements on available bandwidth and minimal delay can be guaranteed for those connections requiring predictable service. This makes reliable voice transmission possible over an ATM network. Although the bandwidth requirements for voice are easily met by other local area networking technologies, ATM can today provide the predictable quality of service required for real-time bi-directional communication.


A pin definition layout of electronic paper display screen is provided. The electronic paper has a first pin area, a data signal source driver area, and a second pin area sequentially disposed at any side thereof. The first pin area and the second pin area each have a first power supply pin set and a second power supply pin set disposed thereon, and a plurality of No connections is disposed by intervals in the first power supply pin set and the second power supply pin set, so as to separate potential pins. Therefore, no interference is generated between the pins, thus achieving good electrical properties and reducing the wire complexity.

1. Field of the Invention
The present invention relates to an electronic paper, and in particularly, to a pin definition layout of electronic paper display screen having good electrical output properties and high yield after definition arrangement of pins, which is advantageous in being light, thin, short, and small.
2. Related Art
Generally speaking, liquid crystal display (LCD) is most used in 3C products. Many information must be stored into a computer or PDA, and then displayed on LCD when reading, so LCD can not replace newspapers and magazines. Therefore, a new generation display technique is an electronic paper display screen.
The development of the electronic paper display screen technology substantially includes electronic display and paper media. The electronic display is mainly made to be further light and thin, and be an animation display having the main features such as high chromaticity, high definition, and high brightness. The paper media mainly adopts an electronic ink technology, such as cholesteric liquid crystal, microcapsule electrophoresis, or Gyricon. The manufactured paper media is light and thin, and thus can replace the current paper. At the same time, the paper media has the functions of display the content of books and magazines for reading, thus being capable of replacing the conventional paper. Further, the paper media can be reused to achieve the environmental friendly feature.
As having no color filter and polaroids, the electronic paper display screen has the advantages such as a light weight, a high resolution, being read under sunlight, and bistable low-power consumption, thus being capable of replacing the current LCD gradually.
Referring to FIG. 1, a block diagram of a conventional electronic paper is shown. An electronic paper display screen 1 has an electronic paper 10. The electronic paper 10 has a source signal pin set 101 and a gate signal pin set 102 disposed at two adjacent sides thereof. The source signal pin set 101 and the gate signal pin set 102 are connected to a display unit 103 in the electronic paper 10 respectively.
Pins of the source signal pin set 101 are connected to a source driver 11, and pins of the gate signal pin set 102 are connected to a gate driver 12, such that the display unit 103 generates corresponding patterns or letters according to the signals input by the source driver 11 and the gate driver 12.
However, when being connected to an external circuit, the electronic paper display 1 still has the following disadvantages to be overcome.
1. In order to facilitate the circuit connection, the electronic paper 10 has the source signal pin set 101 and the gate signal pin set 102 disposed at two adjacent side, for being connected to the source driver 11 and the gate driver 12 respectively, and thus the volume of the circuit can not be effectively reduced.
2. The source signal pin set 101 and the gate signal pin set 102 each have pins for power supply input respectively, and at least include a positive potential, a negative potential, and a ground, which are disposed in parallel, so interelectrode capacitance or interference is easily generated between the pins.
Thus, the electronic paper display screen must control the change of the picture through a driving circuit, which is the same as the LCD, and the wire connection of the electronic paper display screen and the driving circuit is much important. Therefore, how to design the output/input pins of the electronic paper display screen to eliminate the interference between the pins, reduce the wire complexity, improve the circuit stability, achieve good electrical properties, and facilitate the manufactured products being lighter, thinner, shorter, and smaller, is an issue to be solved by the present invention.

Pin definition layout of electronic paper display screen


Method of controlling a hearing instrument comprising at least one hearing device, the method comprising determination of an acoustic environment at least partially by means of calculating the complex coherence of signals from either a pressure microphone and a particle velocity transducer; a pair of pressure microphones in a single hearing device; or a pair of pressure microphones, one situated in each of a pair of hearing devices. This enables finer determination of acoustic environments, thus improving the hearing experience for the wearer of the hearing instrument.

The present invention relates to a method of controlling a hearing instrument based on identifying an acoustic environment, and a corresponding hearing instrument.
It is common for state-of-the-art hearing instruments to incorporate automatic control of actuators such as noise cancellers, beam formers, and so on, to automatically adjust the hearing instrument to optimise the sound output for the wearer dependent on the acoustic environment. Such automatic control is based on classifying types of acoustic environments into broad classes, such as "clean speech", "speech in noise", "noise", and "music". This is typically achieved by processing sound information from a microphone and extracting characteristic features of the sound information, such as energy spectrums, frequency responses, signal-to-noise ratios, signal directions, and so on. Based on the result of the extraction of characteristic features, parameters of the audio signal processing unit are adjusted to optimise the wearer's hearing experience in his or her present surroundings. This optimisation can be by means of predefined programs, or adjusting individual parameters as required.
With various prior art systems, there are several limitations: the detectable classes of acoustic environments are rather broad, leading to insufficient hearing performance for some specific hearing scenarios; extra hardware is often required, increasing costs, power consumption and complexity; and many of the prior art solutions rely on real-time communication between hearing devices and sometimes also a beacon or other separate module that has to be carried by the wearer. Real-time communication uses a lot of power, leading to short battery life and frequent battery changes.

Abstract: The invention further relates to a corresponding hearing instrument.


The invention concerns a high frequency surgery apparatus for cutting and/or coagulating biological tissue and methods of operating same. The high frequency surgery apparatus includes at least one high frequency generator which in operation forms a high frequency circuit with the tissue to be treated, with the production of an arc, and at least one measuring and calculating device which is connected for signal transmission to the high frequency circuit and which is adapted in operation to ascertain both a DC voltage in the high frequency circuit and also the amplitudes of at least one even and at least one odd harmonic of a fundamental frequency of the high frequency generator and to form a first tissue parameter representative of the kind of tissue to be treated from the relationship of the sum of the amplitudes of the even and the odd harmonics to the DC voltage and to output a tissue signal dependent on the first tissue parameter for subsequent processing.

The invention concerns a high frequency surgery apparatus for cutting and/or coagulating biological tissue comprising at least one high frequency generator which in operation forms a high frequency circuit with the tissue to be treated with the formation of an arc.
The invention further concerns a method of operating a high frequency surgery apparatus, wherein for cutting and/or coagulating biological tissue a high frequency circuit is formed between at least one high frequency generator and the tissue to be treated, with the formation of an arc.
The term high frequency surgery is used essentially to denote cutting and coagulating (sclerosing) biological tissue using high frequency currents (about 0.2 MHz to 3 MHz). In that respect the cutting effect in biological tissue is based on the formation of an arc between an active electrode and the tissue. To achieve a cut which is as uniform as possible, with constant haemostasis (cutting result) the arc parameters are used as a regulating criterion for the high frequency generator.
In coagulation the high frequency current is used for haemostasis or for the ablation of tissue. In that case the tissue surrounding the electrode is heated by the current to such an extent that body-specific albumins break down and stick together and intracellular as well as extracellular fluids vaporise. That results in denaturing and shrinkage of the tissue and the blood vessels and thus ultimately stopping of hemorrhages. In ablation a tissue region which is to be destroyed or removed from the body is denatured in that way. The tissue region treated in that way heals up and is broken up by body-specific processes without having to be removed by an operative procedure.
In the cutting operation arcs are produced through a vapour layer of cell fluid between a cutting electrode and the tissue. The point concentration of the high frequency current in the arc gives rise to a flash-like increase in the temperature of the cellular tissue, which leads to abrupt vaporisation of the cell fluid and ultimately cell explosion. The cutting effect occurs due to the distribution of the arcs as they ignite over the active electrode, wherever the vapour layer between the tissue and the electrode is sufficiently thin. In that case electrically conductive tissue can be severed virtually without mechanical pressure. Due to the high temperatures the risk of germs being spread is reduced, in addition at the same time it is possible to achieve coagulation of surrounding pieces of tissue.
The monopolar procedure involves the use of an active coagulation or cutting electrode and a neutral electrode which is applied over a large area. In that case the high frequency current flows from the active electrode to the neutral electrode by way of the tissue to be treated. The crucial consideration for the thermal action of the current at the application placement is an active electrode of small area, in relation to a neutral electrode of large area. That provides for a high current density and thus a substantial increase in the temperature of the tissue at the operation location and at the same time avoids unwanted tissue damage at the neutral electrode.
Bipolar applications involve the use of two evenly matched electrodes which are combined in one instrument. In that case the high frequency current flows from the one electrode of the surgical instrument to the other electrode thereof by way of the tissue to be treated. Alternatively the electrodes can also be provided on different units. The best-known instruments in that respect are coagulation forceps with which blood vessels can be specifically and targetedly gripped and then closed.
In the present document the arc intensity is defined as a measurement in respect of the frequency of occurrence and the number of ignited arcs. It is proportional to the power which is converted at the arc for spark flash-over and for maintaining the vapour layer. With a constant power delivery from the HF generator arc intensity depends on parameters such as cutting depth, cutting speed and tissue factors. Regulation of the arc intensity is used to achieve cutting results which as far as possible are independent of the tissue factors and cutting parameters. In that respect the term cutting result is used to denote the degree of coagulation (desired) and the degree of carbonisation (carbonisation: unwanted material or tissue carbonisation) of the cut surfaces.
Biological tissue is not a homogeneous mass. Muscle, fat and other kinds of tissue as well as blood vessels alternate. The speed and the depth of penetration of the electrode also change during the cutting operation. As a result the electrical conditions under which the cutting electrode is guided are constantly changing. HF generators without arc regulation cannot adapt their electrical output parameters to those variable use conditions. In the case of a cutting operation the active electrode is surrounded by a film of vaporised cell fluid. The vapour layer is compressed and displaced by virtue of the advance movement in the region in front of the electrode. It is there that the arcs are ignited in the case of an optimum cutting operation due to the thinner vapour layer. With an excessively high power output from the HF generator the arcs are ignited distributed over the entire electrode surface.
The desired result in the case of a cut made with an HF surgery apparatus is tissue separation in which the cut surfaces are coagulated but not carbonised. An excessively high power delivery from the HF generator does not lead to an improved cutting result but an increased level of arc intensity. That involves more severe necrosis and carbonisation of the cut surfaces. That delays the healing process and is therefore absolutely to be avoided. In contrast if the power is too low an arc can no longer be ignited and the cutting operation comes to a halt.
Commercially available HF generators regulate the output voltage of the generator to keep the arc intensity between the cutting electrode and the tissue constant. With that regulating system the output power of the HF generator can be substantially better adapted to the prevailing operative requirements than with constant voltage regulation or completely without regulation. In the case of an ideal HF surgery apparatus the cutting result would always be constant and reproducible under all conditions. It is here that previously technically implemented arc regulating systems meet their limits for there is a marked residual dependency in respect of the degree of coagulation and carbonisation of the cut surfaces for example on the cutting speed and the cutting depth.
Technical recognition of the tissue in which the operator is cutting considerably increases the level of certainty when using HF surgery. In the ideal case the surgery apparatus should detect the kind of tissue in which the operation is to be carried out and should shut down or react with signalling as soon as the cutting electrode comes into contact with other pieces of tissue in order to avoid unwanted damage thereto.
High frequency surgery apparatuses and methods of operating same are known from the state of the art.
DE 25 04 280 describes for example an apparatus for cutting and coagulating human tissue with high frequency current, which is regulated on the basis of the state of the cutting or coagulating procedure.
Detecting arc intensity for controlling a high frequency generator is set forth in DE 195 42 418.
A high frequency generator with tissue differentiation on the basis of a current-voltage characteristic measured at a high frequency generator is described in DE 195 42 419.
DE 28 01 833 shows an electrosurgical cutting apparatus in which a regulator for the HF voltage of the HF generator responds to a DC voltage which is produced in the cutting operation.
DE 41 26 607 describes an arrangement for cutting biological tissue with high frequency current.
The problem with the known high frequency surgery apparatuses and the control methods thereof is that different cutting results can occur because there is a dependency on the parameters determined by the operator such as for example cutting speed and cutting depth and the kind of tissue, such as for example muscle tissue or fat tissue.

High frequency surgery apparatus and method of operating same


High compression rate codecs in gateways servicing Voice-over-Internet Protocol (VoIP) and Voice Band Data (VBD) calls distort modem/fax Answer Back Tones (e.g., 2100 Hz), which may lead to signal distortion and call hang-ups. To prevent such occurrences, a method or corresponding apparatus forces originating and terminating gateways to stay in a low complexity non-voice compression codec (e.g., ITU G.711) after prenegotiating a high complexity, voice compression codec (e.g., G.729 or G.726) during a short beginning period of a voice call. The low complexity codec avoids distorted answer back tone leakage associated with previous solutions that use a notch filter to block the leakage, thereby significantly improving the success rate of a VBD call by completely eliminating modem answer back tone distortion caused by high complexity codecs that use voice compression and by completely eliminating use of the notch filter.

A traditional telephone system provides an ability for users with modems to connect to a Remote Access Server (RAS) for digital communications over standard voice lines. This same capability is provided by Voice-Over-Internet Protocol (VoIP) gateways (GW) through the use of a Modem Pass Through (MPT) or voice band data (VBD) mode. VoIP gateways also provide telephone voice services replacing traditional telephony switches.
During a call set-up procedure, an originating gateway (OGW) and terminating gateway (TGW) exchange capabilities via a call control protocol (International Telecommunications Union (ITU) H.323 or Media Gateway Control Protocol (MGCP)) and negotiate a voice encoder/decoder (codec) that is supported by both gateways. Some complex codecs, such as ITU G.729, are supported and most commonly used by VoIP gateways for bandwidth saving purposes. These complex codecs work well in most voice-only calls. However, due to the compression algorithm of complex codecs, VBD calls experience problems, including signal distortion and call hang-ups. Therefore, in voice mode, once a VoIP gateway detects a modem/fax Answer Back Tone (ABT), it switches into VBD mode, which uses a low complexity codec, such as ITU G.711, thereby preventing VBD signal distortion and providing reliable VBD call connections.
During the voice-to-VBD mode change, the OGW and TGW communicate with each other using peer to peer messages via a packet switched network, such as an Internet Protocol (IP) network. There are several such protocols for this, including one that uses peer-to-peer messages that carry a Named Signaling Event (NSE) packet with an Event ID defined by a manufacturer or service provider. The NSE packet uses an Network Terminating Equipment (NTE) format defined in ITU Request for Comments (RFC) document 2833 ("RFC 2833").
RFC 2833 is an IETF "standards track" proposal for carrying Named Signaling Events as RTP packets. According to this standard, the RTP Payload Format for Named Telephone Events includes an Event ID indicating the Particular named telephone event, as well as a volume and a duration for each DTMF digit.
All of the work during a VBD mode switch, including modem/fax answer back tone detection, peer-to-peer message exchange, and the mode switch, introduces time delay. Therefore, if the original voice call is running in a complex codec other than G.711, a certain duration of modem/fax answer back tone may be distorted and transmitted to the client side before the VBD mode switch is completed. This may cause some client modem hang-ups due to the unrecognized modem answer back tone, thus lowering the success rate of VBD calls.
One current solution is to apply a notch filter to block 2100 Hz modem Answer Back Tones so that the tone leakage (i.e., unwanted tones passing through to the client side) does not exceed 50 msec when a call is running on a complex codec other than ITU G.711.

Method and apparatus for improving voice band data (VBD) connectivity in a communications network


Concurrently fed into a reaction zone held at about 10° C. or less are brominating agent, aluminum halide catalyst, and a solution of anionic styrenic polymer having a GPC Mn about 2000-30,000. The components are in at least two separate feed streams. The feeds are proportioned to maintain (a) the amount of aluminum halide being fed at about 0.8 mole percent or less based on the amount of aromatic monomeric units in the polymer being fed, and (b) amounts of brominating agent and unbrominated polymer in the reaction zone that produce a final washed and dried polymer product containing about 60-71 wt % bromine. The catalyst is deactivated, bromide ions and catalyst residues are washed away from the reaction mixture, and the brominated anionic styrenic polymer is recovered and dried. The dried polymer has a volatile bromobenzene content of about 600 ppm (wt/wt) or less as well as other beneficial properties.

Commonly-owned U.S. Pat. Nos. 5,677,390, 5,686,538, 5,767,203, 5,852,131, 5,852,132, 5,916,978, 6,133,381, 6,207,765, 6,232,393, 6,232,408, 6,235,831, 6,235,844, 6,326,439, and 6,521,714 describe what is believed to be the best known prior process technology for producing brominated styrenic polymers such as brominated polystyrene having the best known properties of any previously-known brominated styrenic polymer. In this connection, the terms "brominated styrenic polymer" and "brominated polystyrene" as used anywhere herein including the claims refer to a brominated polymer produced by bromination of a pre-existing styrenic polymer such as polystyrene or a copolymer of styrene and at least one other vinyl aromatic monomer, as distinguished from an oligomer or polymer produced by oligomerization or polymerization of one or more brominated styrenic monomers, the properties of the latter oligomers or polymers typically being considerably different from brominated polystyrene in a number of respects.
In producing brominated anionic styrenic polymers by bromination of anionic styrenic polymers, bromobenzene impurities tend to be formed in greater than desired quantities. Among these impurities are species in which benzene rings can be substituted by 2 to 6 bromine atoms. Because of their greater volatility at elevated temperatures encountered in molding, the species containing 2, 3, or 4 bromine atoms as ring substituents are more undesirable than those containing 5 or 6 bromine atoms on the ring. In the case of bromination of anionic polystyrene using aluminum halide catalysts in which the halide atoms are bromine or chlorine or both, the species containing 2, 3, or 4 bromine atoms as ring substituents as determined by NMR are, respectively, 1,4-dibromobenzene, 1,2,4-tribromobenzene, and 1,2,4,5-tetrabromobenzene. These volatile species have a strong odor and are considered to be skin and lung irritants. Also, the formation of these species in the process results from cleavage of aromatic rings from the polymer chain. This in turn introduces irregularities in the polymer chain and/or addition of bromine atoms to the polymer chain. Such addition results in reducing the thermal stability of the brominated styrenic polymer. Thus, it would be highly advantageous if a way could be found for reducing the formation of bromobenzene impurities, especially the more volatile dibromo, tribromo and/or tetrabromo species, during the actual preparation of brominated anionic styrenic polymers rather than relying upon purification steps during product workup or purification.

This patent is subject to a terminal disclaimer.

Brominated anionic styrenic polymers and their preparation


An electronic apparatus is described. The electronic apparatus includes an image capture unit, a first image processor, a second image processor, a display unit, and an image storage unit. The image capture unit generates an input image by a photoelectric conversion of incident light. The first image processor generates a display image from the input image and generates a first stored image from the first input image. The input image is divided into a first input image and a second input image. The second image processor generates a second stored image from the second input image. The display unit displays the display image. The image storage unit stores a combined stored image. The combined stored image is a combination of the first stored image and the second stored image.

1. Field
One or more embodiments relate to an electronic apparatus, a method of controlling the same, and a computer readable recording medium having recorded thereon a program for performing the method.
2. Related Art
As imaging technology changes from analog methods to digital methods, in order to provide a more realistic image, the imaging technology has developed from a Standard Definition (SD) format to a High Definition (HD) format. The SD format has an image resolution of 704×480 and is composed of approximately 350,000 pixels. The HD format differs from a Full High Definition (FHD) format which has a higher image resolution. The FHD format has an image resolution of 1920×1080 and is composed of 2,000,000 pixels, therefore, the FHD format has a substantially higher picture quality compared to the SD format.
Recently, imaging technology has developed again from the FHD format to an Ultra High Definition (UHD) format. Since the UHD format supports higher image resolution than FHD, the UHD format is highlighted as the next generation image for media environments. The UHD format includes a 4K (3840×2160) image resolution and an 8K (7680×4320) image resolution, and supports up to a 22.2 channel surround sound. Compared to the HD image, the 4K UHD image has 4 times higher picture quality, and the 8K UHD image has 16 times higher picture quality.
Much research has been conducted to enable electronic apparatuses such as digital cameras to generate UHD-level resolution images. It is important not only to process a photographed image into a UHD-level resolution image, but also to reduce delay of the actual image relative to the image displayed on a display unit of the electronic apparatus.

Electronic apparatus, method for controlling the same, and computer readable recording medium


To provide a motion vector estimating device which is capable of calculating the optimum motion vector by a trade-off between the bit rate of a motion vector and a differential amount, and estimating a motion vector in a pipeline structure at high speed, a motion vector estimating method which enables the same. The motion vector estimating device (100) includes: a first motion vector estimating unit (102) which calculates an evaluation value based on the amount of distortion calculated using search blocks and an input block and a correction value calculated using a motion vector with respect to each search block, a first prediction vector, and a weighting coefficient, and estimates a first motion vector of the input block based on the location of the input block and the location of a search block which provides the smallest evaluation value; a weighted coefficient calculating unit (103) which calculates the weighted coefficient; a prediction vector generating unit (104) which generates the first motion vector based on the first motion vector; and a second motion estimating unit (105) which estimates a motion vector determining, as an evaluation value, only the amount of distortion calculated using the search blocks and the input block.

In an image compression method such as the Moving Picture image coding Experts Group (MPEG) scheme where a correlation between pictures of a moving picture is used, a motion vector must be estimated for a block unit based on which motion compensation is performed. Conventionally, as a circuit which estimates this motion vector, a motion vector estimating circuit which is capable of reducing the information amount of the motion vector has been proposed (for example, refer to Patent Reference 1).
FIG. 1 is a block diagram showing the structure of a conventional motion vector estimating circuit. As shown in FIG. 1, this motion vector estimating circuit includes: frame memories 61 and 62, a motion vector storage memory 63, an inter-block difference arithmetic unit 64, an addition amount arithmetic unit 65, and a comparator 66. Here, the inter-block difference arithmetic unit 64 includes two hundred and fifty-six inter-block difference arithmetic units 64a, 64b, . . . 64c, and the addition amount arithmetic unit 65 includes two hundred and fifty-six addition amount arithmetic units 65a, 65b, . . . 65c. They perform two hundred and fifty-six searches.
First, the inter-block difference arithmetic unit 64a calculates a difference between an original macroblock (hereinafter referred to as original MB) to be inputted from the frame memory 62 and a search macroblock (hereinafter referred to as search MB) to be inputted from the frame memory 61, and outputs it as a differential amount. In addition, the inter-block difference arithmetic unit 64b outputs a differential amount between the same original MB as the one used in the inter-block difference arithmetic unit 64a and a search MB shifted by one from that used in the inter-block difference arithmetic unit 64a. Similarly, the 256th inter-block difference arithmetic unit 64c outputs a differential amount between the same original MB as the one used in the inter-block difference arithmetic unit 64a and the shifted search MB. Subsequently, each of the addition amount arithmetic circuits 65a, 65b, . . . 65c outputs a corrected differential amount by adding an addition amount to the corresponding differential amount, and codes a motion vector by the corrected differential amount of a neighboring macroblock. Next, the comparator 66 determines the optimum motion vector having the highest correlation between the original MB and the search MB. At this time, in the addition amount arithmetic circuit, the addition amount is determined depending on respective horizontal components and vertical components that motion vectors have and the coded status. More specifically, when it is assumed that the motion vector Vn at nth search point is Vn=(vnx, vny) and the previous motion vector PV determined through motion search of the immediately-previous search macroblock stored in the motion storage memory 63 is PV=(pvx, pvy), the addition amount Addn of the block differential amount is obtained by the following Equation.Addn=α·(|vnx−pvx|+|vny—pvy|)
Here, α represents a constant, and | | represents calculation for obtaining an absolute value. The addition amount is set so as to become greater as the variance from the previous block motion vector becomes greater. Subsequently, the motion vector is coded according to the corrected differential amount corrected by the previous motion vector of the left neighboring search MB in a picture.
Patent Reference 1: Japanese Laid-open Patent Application No. 2001-197501

Motion vector estimating device, and motion vector estimating method


A method, system, and apparatus include a clustered charge distribution and prioritized charge distribution system for electric vehicles (EVs). Distributed processing units (DPUs) receive member information about an EV or EV user. A power distribution manager (PDM) is coupled to each of the DPUs. The PDM includes a prioritizer. The prioritizer determines a prioritization for charging the EVs based on the member information received by each of the DPUs. Also disclosed is a method for providing clustered charge distribution and charge prioritization for electric vehicles. The method includes sensing whether power is requested by any one of a plurality of EVs within a cluster, generating individual EV-specific information for the EVs using the DPUs, transmitting the EV-specific information to the PDM, and selecting and applying a prioritization algorithm based at least in part on the transmitted information.

Electric Vehicles (EVs) need to be periodically recharged. This is done by connecting the EV to a charger, which receives its power from an electrical supply line. Plug-in hybrid vehicles also need to be recharged to take advantage of the lower energy costs associated with the established electrical infrastructure. As the adoption rate for these kinds of vehicles (collectively referred to herein as EVs) increases across the globe, users of EVs will have increasing needs for connecting to chargers. The power consumption characteristics of EV chargers are such that when an EV is initially being charged, the EV charger draws substantial power. Conversely, when no EV is connected to the charger, or when an EV is connected but has a "nearly full" charge or a "full" charge, very little or no power is needed by the charger.
The proportion of time the charger is drawing power and charging an EV is, in all cases, less than 100%, and in some cases, can be very low at just a few percent. While chargers can automatically switch off the charging of an EV when the EV is fully charged, the electrical supply line and other location-specific infrastructure are rated to support a generally fixed amount of power (or other related measure such as current), which limits the number of chargers, even if the chargers are not fully being utilized. The requirements of the National Electrical Code (NEC) dictate system design. Systems are designed where all load devices associated with an electrical supply line are simultaneously switched on and all are drawing power at the same time. In other words, designers of such electrical systems plan for a worse-case scenario to ensure that safety conditions and standards are satisfied.
It is conceivable that as EVs are more widely embraced by society at large, multiple chargers will be clustered in a single location, such as an apartment complex or a parking garage. If multiple chargers were to be clustered to meet such charging needs using conventional techniques, the electrical infrastructure required to support such a cluster would be cost prohibitive for the owner of the location in which the cluster is to be installed (e.g., such as the apartment complex or parking garage) because of the large up-front infrastructure investment.
Employing existing technology while maintaining compliance with the NEC limits the size of the cluster to the number of chargers that will draw the maximum line current when all are switched on simultaneously. This, in turn, limits the number of chargers deployable using the existing electrical infrastructure, even though the line load will only infrequently be fully exercised. If more chargers are desired, additional electrical infrastructure must be built out at additional cost and delay, which would impede the acceptance and ramp of EVs into the marketplace.
Moreover, if multiple chargers were carelessly connected to a single electrical supply line, the power demands on the electrical supply line would, in many cases, exceed the maximum line current of the electrical supply line, or otherwise violate safety limits of a supply line breaker associated with the electrical supply line. Such an approach could lead to personal injuries, electrical fires, or other tragedies. Thus, creating such clusters of chargers can be dangerous if done improperly, and is otherwise expensive because it usually means that additional infrastructure must be purchased and installed, including additional supply lines, supply line breakers, safety switches, and the like. This inevitably deters the wider adoption of EVs.
These are only a few of the challenges presented by conventional approaches, which are impeding the wider adoption of electric vehicle technologies, and ultimately hurting efforts for energy independence and environmental responsibility.
Accordingly, a need remains for an improved apparatus, system and method for distributing charges to EVs in a cluster environment. In addition, a need remains for prioritization algorithms for charging the electric vehicles in the cluster environment. Embodiments of the invention address these and other limitations in the prior art.
The foregoing and other features of the invention will become more readily apparent from the following detailed description, which proceeds with reference to the accompanying drawings.

Electric vehicle clustered charge distribution and prioritization method, system, and apparatus


Object recognition techniques are disclosed that provide both accuracy and speed. One embodiment of the present invention is an identification system. The system is capable of locating objects in images by searching for local features of an object. The system can operate in real-time. The system is trained from a set of images of an object or objects. The system computes interest points in the training images, and then extracts local image features (tokens) around these interest points. The set of tokens from the training images is then used to build a hierarchical model structure. During identification/detection, the system, computes interest points from incoming target images. The system matches tokens around these interest points with the tokens in the hierarchical model. Each successfully matched image token votes for an object hypothesis at a certain scale, location, and orientation in the target image. Object hypotheses that receive insufficient votes are rejected.

Object recognition describes the task of automatically recognizing objects in digital video images. It can be divided into two sub tasks: detection and identification. In detection, objects belonging to a certain class (e.g., the class of cars or faces) have to be located in a given input image. In identification, a certain object has to be recognized in an image (e.g., Jim's face or Helen's blouse).
There are three main problems in object recognition. In case of detection, objects belonging to the same class might vary in their shapes and colors (e.g., different types of chairs). In case of identification, two different objects might look very similar (e.g., in face identification, the faces of siblings might be hard to distinguish). Thirdly, the appearance of an object in an image changes with its pose, the illumination, and the camera. Recognition systems have to be invariant to those changes.
In addition to these inherent problems, many conventional recognition systems suffer from a number of drawbacks. For instance, such convention systems typically require a large database of training pictures, which is tedious to build. In addition, they are too slow to be used in real-time applications. In this sense, object recognition systems can be evaluated using two main criteria: accuracy and speed. The recognition accuracy is defined by how well the system can locate objects in an image relative to the number of false alarms). The speed of the system at run-time defines how much time it takes to process a new image.
What is needed, therefore, are object recognition techniques that provide both accuracy and speed (e.g., without requiring a large database of training images and enabling real-time processing).

Creating a model tree using group tokens for identifying objects in an image


Disclosed is a micromirror for a hybrid optoelectronic integrated circuit, a method for manufacturing the same, a micromirror-photodetector assembly and an assembly of hybrid optoelectronic integrated circuit for receiving light. The micromirror the present invention comprises a silicon substrate and at least one V-shaped groove formed in the silicon substrate and the V-shaped groove has an inclined surface reflecting light emitted from an optical waveguide to a photodetector. The alignment of the photodetector and the optical fibers is achieved without an additional attachment equipment, by inserting the optical fibers into the V-groove.

1. Field of the Invention
The present invention relates to a micromirror for a hybrid optoelectronic integrated circuit, a method for manufacturing the same, a micromirror-photodetector assembly and an assembly of hybrid optoelectronic integrated circuit for receiving light; and, more particularly, to a micromirror for a hybrid optoelectronic integrated circuit capable of causing light, which is emitted from optical fibers and optical waveguides and is in parallel to a surface of a substrate, to be received by an active region of the photodetector manufactured by the planar-processed method. Also, the present invention relates to a micromirror-photodetector assembly wherein a micromirror is integrated with a photodetector and to an assembly of hybrid optoelectronic integrated circuit for receiving light, which is formed by arranging a micromirror-photodetector assembly on optical waveguides of a hybrid substrate.
2. Description of the Related Arts
Recently, various researches are made on demand for the high-speed and broadband telecommunications. Accordingly, optical transmitters and receivers essentially required in the optical communication have been developed.
In general, the integration of the optical devices can be divided into the optical electronic integrated circuit method(OEIC) and the hybrid method. One of them, the hybrid method, is widely used in the integration, because it can be easily implemented by using an established fabrication technology in its fabrication method. This hybrid method may have the benefits in its integration.
The above-mentioned hybrid optoelectronic integrated circuit is implemented by the surface mounting method on a silicon wafer board to integrate, photoelectric transducers including a semiconductor laser diode and a semiconductor photodetector and passive elements such as, an optical fiber, a waveguide, an interferometer,and a filter. At this time, the photodetector, which is used as an optical receiver for converting optical signals into electric signals, receive lights when the ray of light upon it is in the direction normal to its surface, because active regions to sense light are widely distributed on the surface of the substrate. Also, since waveguides and optical fibers, which are key elements in the hybrid optoelectronic integrated circuit, emit light from the cross-section of the waveguide, beam emitted from it propagates in parallel to the substrate. The photodetector, a surface receiving element, can receive light in parallel with the substrate in two methods.
In the first method, the photodetector is mounted vertically on the surface of the substrate and a ray of light is incident normally upon an active region of the photodetector. In the second method, after making the light path normal to the substrate by reflecting light on an inclined mirror, the active region of the photodetector is attached on the inclined mirror with its surface turned toward the inclined mirror.
The thickness of the mirror for this usage must be in the range of several ten microns and the mirror must be easily accommodated below the photodetector. Accordingly, the mirror must be small size. Typically, the mirror is fabricated by one side of a V-groove which is formed by the anisotropic etching process in a silicon substrate and the mirror is also fabricated by one side of a waveguide having inclined surfaces in silica and polymer materials.
Referring to FIG. 1, in which there are shown a micromirror according to the prior art, a waveguide 2 or an optical fiber are directly formed on a substrate 1, such as a silicon wafer, or they are attached to the substrate after being fabricated by individual process. A reflect surface 5 of a mirror 4 is formed just near by a core 8 of the waveguide 2 in order for it to be opposite to the core 8. Also, to arrange a photodetector 6 on the mirror 4, supports 3, which are usually fabricated by the same material as the waveguide 2, are formed on the substrate 1 and the photodetector 6 is mounted on the supports 3.
At this time, in order that the axis of beam reflecting from the reflection surface 5 of the mirror 4 corresponds to the active region 7 of the photodetector 6, the photodetector 6 is aligned with the reflection surface 5 of the mirror 4 and the optical waveguide 2.
As stated above, since the mirror 4 should be positioned below the photodetector 6 and the supports 3 has a thickness of about 40 to 60 .mu.m, the thickness of the mirror 4 must be thin. On the other hand, because the mirror 4, which is made of a thin silicon, breaks easily, it is difficult to treat it. Also, in the case of the array consisting of a plurality of the optical waveguides 2 and the photodetector 6, as shown in FIG. 1, it is impossible for each of them to use a separate mirror. Accordingly, it is desired that only one mirror is used for a plurality of the optical waveguides 2, as shown in FIG. 1. When light emitted form the optical waveguide 2 is reflected on the surface of the mirror 4, the reflected light can be received by other photodetectors which is adjacent to the corresponding photodetector so that a crosstalk may be generated.
In the conventional micromirror, to drive the photodetector 6, an electrical signal must be provided for the active region 7 of the photodetector 6. Referring to FIG. 2a, as stated above, the supports 3 are formed on the substrate 1. Solder-bumps 10 are formed between the supports 3 and the height of the solder-bumps 10 is similar to that of the supports 3. Also, metal pads 9 are formed beneath the solder-bumps 10 and some of the solder-bumps 10 are extended to connecting points, which are positioned to achieve an electrical connection to an external circuit from the substrate 1.
Furthermore, metal pads 8 is formed on the photodetector 6, being opposed to the solder-bumps 10. Some of the metal pads 8 is electrically connected to the active region 7 of the photodetector 6. After arranging the photodetector 6 on the supports 3, the substrate 1 is heated until the melting point of the solder-bumps 10. By doing so, as shown in FIG. 2b, the melted solder-bumps 10 bond the metal pads 8 of the photodetector 6 to the metal pads 9 of the substrate 1, to thereby achieve a mechanical attachment and an electrical connection in the photodetector 6.
However, since the height of the solder-bumps must be similar to that of the supports and it is approximately a few tens of microns, it is very difficult to employ common semiconductor processes in fabricating solder-bumps. Also, because the automatic alignment due to the surface tension of the solder-bumps doesn't act to the best of its ability, it is also very difficult to horizontally align the photodetector. Accordingly, these complete fabrication processes decrease the yield on the optoelectronic integrated circuit and also increase the unit cost of production.

Micromirror for a hybrid optoelectronic integrated circuit, a method for manufacturing the same, a micromirror-photodetector assembly and an assembly of hybrid optoelectronic integrated circuit for receiving light

Electronics and Telecommunications Research Institute


A method for programming a multi-level-cell NAND flash memory device having plural memory cells is disclosed to reduce the programming time. The method comprises: programming each memory cell to a zero state, programming from the zero state to a first state by activating a first program signal and programming from the zero state to a quasi-second state and a semi-third state by activating a second program signal, programming from the quasi-second state to a second state and programming from the semi-third state to a quasi-third state by activating the second program signal, and programming from the quasi-third state to a third state by activating the first program signal. The present invention also discloses a page buffer to perform the method for programming a multi-level-cell NAND flash memory device, which comprises a bit line selection circuit, a first register, a second register, a first verify circuit, a second verify circuit and an exclusion circuit.

1. Field of the Invention
The present invention relates to a method for programming a NAND flash memory device and a page buffer performing the same, and more particularly, to a method for programming a multi-level-cell NAND flash memory device, which stores 2-bit information per memory cell and a page buffer performing the same.
2. Description of the Related Art
In a traditional NAND flash memory device, memory cells can take one of two information storing states, namely, the "ON" state and the "OFF" state. One bit of information is defined by the ON or OFF state of a respective memory cell. In order to store data of N bits (N: a positive integer of 2 or greater) in the aforesaid traditional NAND flash memory device, N independent memory cells are necessary. When it is required to increase the number of bits of data to be stored in a NAND flash memory device having one-bit memory cells, the number of such memory cells should increase accordingly. Information stored in the one-bit memory cell is determined by the programmed status of the memory cell where programming is used to store the desired information in the memory cell. The information storing state of the memory cell is determined by the threshold voltage which is a minimum voltage to be applied between the gate and source terminals of the transistor included in the memory cell to switch the cell transistor to its ON state.
FIG. 1 shows a memory cell transistor 10 capable of storing 2-bit information, which is used in the NAND flash memory device. The memory cell transistor 10 has two gates including upper and lower layers laminated on a channel region between source and drain regions. The upper gate is called a control gate 11 and the lower gate is called a floating gate 12. The floating gate 12 is a charge storage portion surrounded by an insulating material 13 between the control gate 11 and the channel region. Accordingly, the state of information stored in each memory cell can be distinguished by the threshold voltage of that memory cell.
FIG. 2 shows two strings in a memory cell array 20 of a NAND flash memory device, where each memory cell 10 stores two-bit information. The memory cell array 20 comprises plural memory cells 10 connected in series between a bit line (BL1 or BL2) and a ground select line GSL. A group of memory cells 10 connected in series to one bit line (BL1 or BL2) along with select transistors (a string select transistor SST and a ground select transistor GST) used to select the memory cells 10 is called a string. The string select transistor SST is selectively switched on to couple the associated string and the bit line together. The ground select transistor GST is selectively switched the connection between each string and a common source line CSL.
FIG. 3 shows a threshold voltage distribution of a memory cell according to programmed data. As shown in FIG. 3, the programmed data exhibits one of a threshold voltage (indicating 2-bit data of (11)) lower than −2.0V, a threshold voltage (indicating 2-bit data of (10)) between 0.3V to 0.7V, a threshold voltage (indicating 2-bit data of (01)) between 1.3V to 1.7V, and a threshold voltage (indicating 2-bit data of (00)) between 2.3V to 2.7V. Data can be stored in four different stages in one memory cell on the basis of such threshold voltage distributions.
As for the program operation applied in a multi-level-cell NAND flash memory device, some traditional program methods are given as follows. U.S. Pat. No. 5,768,188, herein incorporated by reference and hereinafter '188, discloses a three-phase program operation with a timing chart (refer to FIG. 5 of '188). Before program operation, all memory cells are reset to the state of (11) and the 2-bit information to be programmed is loaded into registers Q2 and Q1 (refer to FIG. 1 of '188), and the registers Q2 and Q1 latch the MSB and the LSB of the 2-bit information, respectively. FIGS. 4(a) through 4(c) show the state transition of the memory cells for each phase of the program operation, and are used to program the memory cells to be programmed to the states of (10), (01) and (00), respectively. In FIG. 4(a), Phase One, the memory cells to be programmed to the state of (10) are programmed from the state of (11), which is indicated by a solid pointer A1; and the memory cells to be programmed to the state of (00) are programmed from the state of (11), which is indicated by a dashed pointer A2; but the memory cells to be programmed to the state of (01) are not programmed. The solid pointer A1, starting from (11) and ending in (10), means the program operation for the memory cells to be programmed to the state of (10) is completed; however, the dashed pointer A2, starting from (11) and ending in (00), means the memory cells to be programmed to the state of (00) are still under programming. In FIG. 4(b), Phase Two, the memory cells to be programmed to the state of (01) are programmed directly from the state of (11), which is indicated by a solid pointer A3 that means the program operation thereof is completed; in the meantime, the memory cells to be programmed to the state of (00) are programmed from the state of (10), which is indicated by a dashed pointer A4 that means the memory cells to be programmed to the state of (00) are still under programming. The states of (01) and (00) latched in the registers Q2 and Q1 change to (11) and (10), respectively, according to the logic of FIG. 1 of '188 (i.e., the verify operation following the program in Phase Two, referring to FIG. 5 of '188). That is, the Q2 state changes from logic low to logic high. Thus, the program operation is inhibited for the memory cells that have already been programmed to the state of (01) or (00), due to the high state of the register Q2 that latches the MSB of the 2-bit information to be programmed. Also, there is no over program concern for the state of (00) when the state of (00) is programmed concurrently with the state of (01). In FIG. 4(c), Phase Three, the memory cells to be programmed to the state of (00) are programmed from the state of (01) to the state of (00), which is indicated by a solid pointer A5 that means the program operation for the memory cells to be programmed to the state of (00) is completed.
FIGS. 5(a) through 5(c) show the state transition of the memory cells for each phase of the program operation disclosed in U.S. Pat. No. 6,411,551, herein incorporated by reference and hereinafter '551. Note that FIGS. 5(a) through 5(c) are used to program the memory cells to be programmed to the states of (10), (01) and (00), respectively. The program operation disclosed in '551 attempts to address an issue with '188. The issue is that memory cells to be programmed to the state of (01) are programmed directly from the state of (11); consequently, a wider threshold voltage distribution is formed, which causes narrower margins with adjacent threshold voltage distributions. In FIG. 5(a), Phase One, the memory cells to be programmed to the state of (01) and (00) (indicated by dashed pointers B2 and B3, respectively) are also programmed from the state of (11), while the state of (10) is programmed (indicated by a solid pointer B1). Note that the dashed pointers B2 and B3 mean the associated program operations are not completed. In FIG. 5(b), Phase Two, the memory cells to be programmed to the state of (00) are still under programming (indicated by a dashed pointer B5); at the same time, the memory cells to be programmed to the state of (01) from the state of (10) are programmed and completed (indicated by a solid pointer B4). Finally, referring to FIG. 5(c), the memory cells to be programmed to the state of (00) are programmed and completed (indicated by a solid pointer B6).
FIGS. 6(a) through 6(c) show the state transition of the memory cells for each phase of the program operation disclosed in U.S. Pat. No. 5,986,929, herein incorporated by reference and hereinafter '929, and are used to program the memory cells to be programmed to the states of (10), (01) and (00), respectively. In FIG. 6(a), Phase One, the program operation for the memory cells to be programmed to the state of (00) is inhibited, which can reduce the over program of the state (00) (refer to FIG. 4(a)) of '188. That is, only the program operation for the memory cells to be programmed to the state of (10) (indicated by a solid pointer C1) is performed and completed. In FIG. 6(b), Phase Two, a solid pointer C2 means the program operation for the memory cells to be programmed to the state of (01) from the state of (11) is completed; however, a dashed pointer C3 means the memory cells to be programmed to the state of (00) are still under programming. In FIG. 6(c), Phase Three, a solid pointer C4 means the program operation for the memory cells to be programmed to the state of (00) from the state of (01) is completed.

Method for programming NAND flash memory device and page buffer performing the same

Elite Semiconductor Memory Technology Inc.


A protective carrier for a magnetic head magnetic head assembly includes a housing having buffering members attached to the housing. When the carrier is engaged with the magnetic head magnetic head assembly, the buffering members are rotated into the spacings between the magnetic heads so as to prevent direct physical contact of the magnetic heads. When the carrier is disengaged from the magnetic head magnetic head assembly, the buffering members are rotated out of the spacings between the magnetic heads. The carrier prevents collision of the magnetic heads during handling and transportation and consequently reduces production loss.

Magnetic recording media in the form of tapes or disks have widely been used for data storage. Magnetic heads are commonly employed to perform the tasks of interacting with these recording media.
FIG. 1 shows a typical arrangement of a magnetic head assembly 40 interacting with a stack of magnetic disks 66. The assembly 40 includes a magnetic transducer 50 disposed on a slider 52 which in turn is attached to a load beam 54 through a flexure 56. The slider 52, the flexure 56, and the load beam 54 are collectively called a gimbal assembly 58 which is joined to an actuator arm 60A of an arm assembly 62 rotatable about an arm axis 64. The stack of disks 66 includes a plurality of spaced apart disks 66 rotatable about a common spindle 68. The actuator arm assembly 62 includes head arms 60A-60C which extend to the disks 66A and 66B.
During normal operation, the disks 66A and 66B spin at high speed in the direction 70 about the spindle 68. The aerodynamics of the moving air between the slider 52 and the disk surface 72 provide sufficient buoyancy to suspend the slider 52 above the disk surface 72 of the disk 66A. At the same time, the spring forces of the load beam 54 and the resilient flexure 56 urge the slider 52 toward the disk surface 72. An equilibrium point is reached whereby the slider 52 flies over the disk surface 72 at a substantially fixed distance, which is called the flying height of the magnetic head 50. Data can be written onto or read from the disk surface 72 without the magnetic head 50 contacting the disk surfaces 72.
Switching from the normal operating mode to the idle mode, the stack of disks 66 decelerates in angular velocity. At the same time, the arm assembly 62 slowly sweeps toward the spindle 68 in the direction 73 as shown in FIG. 1. The decrease in angular velocity of the disks 66 consequently reduces the air buoyancy between the slider 52 and the disk surface 72. Eventually the slider 52 carrying the magnetic head 50 slowly decends onto data track 75 near the spindle 68. The reverse action occurs when the head 50 takes off from the idle mode and enters into the normal operating mode.
Inside the hard drive housing (not shown), the magnetic head 50 is controllably positioned both during the operating mode and the idle mode. That is, the movement of the magnetic head 50 is designed to encounter no direct impact force which can cause subsequent damages. However, prior to the installation of the head assembly 40 to the stack of disks 66, the magnetic heads 50 are normally exposed with no physical protection, much less any controlled head movement for safeguarding the magnetic head 50.
FIG. 2 is an enlarged view showing the relationship of the magnetic heads 50 in a multi-head assembly 40 without the magnetic disks 66A-66B. It should be noted that FIG. 2 merely illustrates the physical relationship between the various components associated with the magnetic heads 50. The sliders 52 are attached to the flexures 56 which are made of flexible material. It is apparent that collisions of the sliders 52 with each others are highly possible and may consequently cause damages to the heads 50. During transportation, the head assembly 40 is placed in a conventional carrier (not shown) in which the sliders 52 carrying the heads 50 are prone to collide with each other. Likewise, the assembly 40 is subject to similar treatment passing through an assembly line. As a consequence, portions of the sliders 52 may crack or chip away which will result in reduced production yield.
Protection of magnetic heads and sliders has been an ongoing problem. U.S. Pat. No. 5,482,164, Karns, entitled "E-Block Shipping Comb", issued Jan. 9, 1996, describes a design which includes a flexure comb attached to a frame. During usage, the plurality of flexures are placed into the comb having the flexures interleaving with the comb spikes. The placement of the flexures in between the comb spikes is a time consuming process as each flexure has to be carefully positioned between the spikes. Moreover, the manual insertion of the flexures in between the comb spikes may well deform the flexures. In addition, vibrational movement of the sliders can also possibly bend the delicate flexures.
Magnetic heads are now built with smaller sizes and with more delicate and flexible flexures. As a consequence, sliders are more likely to collide with each other and cause greater damage. Furthermore, the delicate flexures are extremely vulnerable to deformation if improperly handled. A deformed flexure, even if slight, would be prone to mechanically resonate at a lower frequency during usage and is detrimental to the performance of the magnetic head. To minimize losses in production shipping, there has been an increasing need to provide reliable packaging to magnetic heads.

Protective carrier for magnetic head assembly