Methods and materials for studying the effects of a newly identified human gene, APOAV, and the corresponding mouse gene apoAV. The sequences of the genes are given, and transgenic animals which either contain the gene or have the endogenous gene knocked out are described. In addition, single nucleotide polymorphisms (SNPs) in the gene are described and characterized. It is demonstrated that certain SNPs are associated with diseases involving lipids and triglycerides and other metabolic diseases. These SNPs may be used alone or with SNPs from other genes to study individual risk factors. Methods for intervention in lipid diseases, including the screening of drugs to treat lipid-related or diabetic diseases are also disclosed.

1. Field of the Invention
This invention generally relates to human lipid metabolism, particularly to apolipoproteins, genes encoding these apolipoproteins, related proteins, and their mutations and polymorphisms as they relate to cardiovascular, coronary and other diseases.
2. Description of the Related Art
Cardiovascular diseases are the number one cause of death in Western societies. Studies repeatedly show that individuals with high levels of very low-density lipoprotein, (VLDL) and/or low levels of high density lipoprotein (HDL) have significantly increased chances of developing cardiovascular disease. It has been established that strategies to reverse the levels of these lipoprotein particles will lower disease risk in susceptible individuals.
Lipoproteins function as transport vehicles for triacylglycerols (triglycerides), cholesterol and other lipids. These complexes solubilize highly hydrophobic lipids, and regulate entry and exit of particular lipids at specific targets. Lipoproteins form micelle-like particles that consist of a nonpolar core of triacylglycerols, more commonly known as triglycerides, and cholesteryl esters surrounded by a coating of protein, phospholipids, and cholesterol. The lipoproteins are classified according to density. Lipoprotein particles are composed of lipids and proteins and are such particles as chylomicrons, very low-density lipoproteins (VLDL), intermediate-density lipoproteins (IDL), low-density lipoproteins (LDL), and high-density lipoproteins (HDL). (Voet and Voet, Biochemistry, 1990; Stryer, Biochemistry, 1995). The protein components of lipoproteins are known as apolipoproteins.
Van der Vliet, H N et al., report on a gene that shares homology to APOAV and note its increase in expression following rat liver hepatectomy in J Biol Chem. Nov. 30, 2001;276(48):44512-20. The rat (GenBank Accession Nos. AF202888 and AF202887), mouse (GenBank Accessions No. AF327059) and human (GenBank Accessions Nos. AF202890 and AF202889) versions of these sequences were deposited in GenBank and entitled, Regeneration-associated protein 3 (Rap 3) mRNA, complete cds. Rap3 is noted in GenBank as an "apolipoprotein-like serum protein; concentration elevated after a 70% partial hepatectomy" in rats.
The human genomic region containing the DNA sequence for APOAV was sequenced by the Human Genome Project and deposited in GenBanK under Accesssion Numbers AC007707 and/or AC074203. These deposits cover approximately 200 kb of human genomic DNA. The deposits are associated with clustered 11q23 and 22q11 breakpoints, but no coding regions are described. Computational analyses indicate the previously described APOA-I, APOC-III, and APOA-IV are contained within this interval.
The GenBank Accession Number AC007707 sequence shows the opposite strand (reverse complement) of the sequences of the present invention. The reverse complement of AC007707 was used as the starting point of the present invention for finding the APOAV gene and coding sequence.
Yen et al., in PCT Publication WO 01/007803, entitled "Apolipoprotein A-IV-related protein: Polypeptide, polynucleotide sequences and bi-allelic markers thereof" describe a gene corresponding to the present APOAV. The gene is described as encoding an apolipoprotein A-IV-related protein (AA4RP) as well as regulatory sequences at the 5′ and 3′ end. Also disclosed are biallelic markers of the AA4RP gene useful in genetic analysis. However, Yen et al. describe their biallelic markers differently than the SNP's of the present invention. They disclose no description of any known linkages between these markers and any known disease phenotype.
Several human cDNA sequences derived from the APOAV gene have been previously disclosed in GenBank. A sequence file generated by the NCBI annotation project in July 2001 (transcript version 1) is disclosed as human mRNA/cDNA sequence, XM—052110. A second sequence file generated by the NCBI annotation project identifies in July 2001 (transcript version 2) can be found as XM—052109. AF202890 (called RAP3) is a third cDNA sequence that is related to the van der Vliet et al. Human ortholog of rat liver regeneration associated protein (transcript version 1). AF202889 (called RAP3) is the fourth cDNA sequence related to the van der Vliet et al. No. AF401201and was made public on 7 Oct. 2001.
Other related sequences include mouse mRNA/cDNA sequence (AF327059), called RAP3, which is the sequence identified as the mouse ortholog of rat liver regeneration associated protein. Three publicly generated mouse full-length cDNAs for apoAV are found under the following Accession Nos.: AK004903 (transcript version 2), BC011198 (transcript version 2), and AK004936 human ortholog of rat liver regeneration associated protein (transcript version 2).
Human protein sequences were predicted from mRNA sequences AF202890 and AF202889 and called AAF25662 and AAF25661, which correspond to the APOAV protein, which can be found under NP—443200 in NCBI.
The mouse genomic region (which includes additional genes sequenced and used used to create the knock-out mice described herein) is SEQ ID NO: 7 in this application. This sequence was deposited in GenBank under GenBank Accession (transcript version 1). The mouse RAP3 protein (GenBank Accession No. AAG49600) is the protein sequence predicted from mRNA sequence AF327059.

Apolipoprotein gene involved in lipid metabolism

The Regents of The University of California


A thermal test target with a uniform surface temperature which can be used to characterize and measure thermal image degradation due to atmospheric propagation of the image radiation field. This thermal test target board produces very uniform spatial frequency patterns with near perfect transitions between hot and cold portions which do not change during the diurnal cycle and which are not impacted by environmental changes.

1. Field of the Invention
The present invention is in the field of thermal (infrared) target simulators used in testing imaging systems.
2. Description of the Prior Art
In order to test thermal target viewers, imagers, and the like, simulators must be used. In addition, a target which can be used to characterize the thermal image degradation due to atmospheric propagation of the image radiation field from close to the target to the thermal image at the imager acquisition range is required. In the area of target acquisition the visible is the most convenient because the human eye has adapted to distinguishing objects by the dominant source of reflected spectral radiation, the sun a 6000 degree K blackbody radiator whose radiation peak is between 0.4 and 0.7 microns. The sun is not always present to illuminate the target and obscurants can prevent the observer from receiving the reflected solar radiation; hence, another spectral region (the 8 to 14 micron, far-infrared, or thermal) is often used to detect targets because ambient temperature radiation from the targets themselves are peaked in the 8 to 14 micron spectral region. In order to assess how well a thermal imaging system will perform for target detection the mechanisms which produce changes in the received thermal image must be quantitatively measured. These mechanisms which produce contrast include: solar radiation which is often variable for partly cloudy conditions, windspeed which cools surfaces convectively or through an evaporative process, precipitation which can rapidly cool warm objects, and a variety of atmospheric obscurants and turbulence which produce attenuation and distortion of the received scene radiation distribution. It is here that the present invention is utilized. The near field/far-field image comparison technique of the Target Contrast Characterizer (described in The Proceedings of the SPIE International Symposium on Optical, Infrared, and Millimeter Wave Propagation Engineering, VOL. 926. Orlando, Fla. [1988]) can be used to separate target contrast change components of interest or closeup target contrast changes from the propagation degradation of the inherent contrast to the distant observation location. To properly quantify the propagation degradation a stable thermal spatial target is needed because the inherent signature of a target against a background can change rapidly and even go through periods of no contrast during the thermal reversals of the diurnal cycle. The target board which is the subject of the invention presented herein can be used to produce very uniform spatial frequency patterns with near perfect transistions between hot and cold portions which do not change during the diurnal cycle and which are not impacted by environmental changes. To be useful such a target board must be large (on the order of two meters by two meters), yet lightweight for ease in transporting over rough terrain to typical target locations, and the spatial patterns must be changeable to meet specific target spatial feature characterization requirements. No prior art thermal test target with a uniform surface temperature is known which can be used to characterize and measure thermal image degradation due to atmospheric propagation of the image radiation field. Nothing currently exists which meets these surface temperature uniformity standards requirements. Those target boards which use other methods such as temperature controlled cooling liquids to create uniform surface temperatures weigh several times more than the thermal target test board, which is the subject of this invention.

The United States of America as represented by the Secretary of the Army


A computer includes a system unit which has a plurality of electronic components, a battery unit which supplies auxiliary electric power to the system unit, an adapter which receives a first alternating current (AC) electric power and outputs a second AC electric power; a rectifying unit which rectifies the second AC electric power and supplies a direct current (DC) electric power having a level higher than a minimum electric power level required to operate the system unit and lower than a charging electric power level required to charge the battery unit, to the system unit, a battery charging unit which charges the battery unit, and an electric power amplifying unit which amplifies the DC electric power that branches off from a point of an electric power supplying path between the rectifying unit and the system unit, and supplies a charging electric power to the battery charging unit.

1. Field of the Invention
The present general inventive concept relates to a computer and a power supply method thereof, and more particularly, to a computer and a power supply method thereof which can lower a range of an input electric power level supplied to a system unit thereof.
2. Description of the Related Art
A portable computer, such as a notebook computer and a personal digital assistant (PDA), having a battery attached thereto is widely utilized in that it can be carried and used as a mobile device. Generally, the computer uses an outer power source through an AC/DC adapter or conventional power devices, and also uses a battery as a secondary power source which can be recharged by an adapter.
FIG. 1A is a block diagram illustrating a conventional computer. As illustrated in FIG. 1A, the conventional computer is supplied with electric power of 19 V from an adaptor 1, and electric power of 6 to 8.4 V from a battery 2. Accordingly, a system unit 3 of the conventional computer receives an input electric power having a range of 6 to 19 V from the adapter 1 and the battery 2. As such a configuration has a large range of the input electric power, components, such as a metal oxide semiconductor field effect transistor (MOSFET) and an inductor, are required to have a large capacity when they are designed to output the same voltage, thus decreasing an overall efficiency and a battery life span.
To solve such a problem, narrow voltage direct current (NVDC) has been introduced. According to the NVDC, the electric power from the adapter 1 or the battery 2 is transformed into the level required to drive electronic components included in the system unit 3, thus decreasing the range of voltage level of the input electric power (VDC) inputted to a DC/DC converter 4.
However, as illustrated in FIG. 1B, a conventional NVDC causes a decrease in efficiency because the electric power received from the adapter 1 is not directly applied to the system unit 3 but applied via a battery charging unit 5. Also, the conventional NVDC requires a boost converter to step up the electric power received from the adapter 1 to the electric voltage level required for charging the battery 2.

Computer and power supply method thereof


A chip circuit comprising a chip which comprises a semiconductor substrate and substantially plane components formed on the said substrate, among which there are an emitting component capable of emitting electromagnetic radiation and an inductor sensitive to the incident electromagnetic radiation. At least one shield, external to the chip, is placed opposite the inductor at a distance of less than 500 microns. The shield thus makes it possible to shield the sensitive inductor from the emitting component, while maintaining the quality factor of the inductor.

Considerable progress has been made in microelectronics allowing more and more functions to be integrated onto a single chip. This increased integration has many advantages, among which is the fewer external components and the smaller footprint.
Thus, chips integrate complete RF (radiofrequency) transmission systems, which may include VCOs (voltage controlled oscillators), PLLs (phase-locked loops), mixers, power preamplifiers, etc.
However, the integration of many components on one and the same substrate has drawbacks. It causes, especially at high frequency, parasitic signal coupling that interferes with certain of the functions of the chip, for example the VCO. These parasitic signals are signals generated by elements of the chip that interfere with other elements of this same chip. Penetration of such parasitic signals into a VCO at its oscillation frequency is generally called "VCO pulling". VCO pulling is especially the result of a parasitic signal of frequency equal to the 2nd harmonic (H2) of the operating frequency. Particularly sensitive elements, and consequently in particular victims of such interference, are the inductors integrated into the chips.
There are many consequences of this parasite phenomenon within a chip, which may include, for example in the case of the VCO, generation of parasitic lines, modulation of the operating frequency of the VCO, degradation of the phase error or else oscillation of the VCO at a frequency other than that desired.
Various means are known for overcoming these drawbacks. A number of them rely on improving the linearity of the parasitic signal generator blocks at H2; this improved linearity may be achieved by supplying these blocks with a higher current. Other means are used to increase the useful signal of the VCO (at the frequency H1) relative to the interfering signal by increasing the current consumed by the VCO. However, these solutions involve an increase in the electrical consumption.
Document U.S. Published Patent Application No.A-2002/0180538 discloses a VCO architecture for reducing the effects of VCO pulling by using two signals at frequencies such that the sum of the frequencies is equal to the desired output frequency, while eliminating parasitic effects. However, this solution involves additional components and is relatively complex to implement.
Moreover, U.S. Pat. No. 6,611,041 discloses an integrated circuit comprising a substantially plane inductor and a shield that is parallel to the plane of the inductor and faces the latter, formed within silicon. The aim is to have the shape of the shield so as to prevent any current flow in the shield and therefore any magnetic field that would thus be generated. Such a shield therefore constitutes mainly one that shields out parasitic electrical signals. It also allows the quality factor of the inductor to be optimized by reducing ohmic losses towards the substrate. However, it requires the integration of an additional element in the substrate and increases the complexity of the chip. In addition, it does not shield out magnetic parasitic signals.
On the other hand, the prior art also teaches shields placed outside a chip of an integrated circuit in order to protect the chip or the integrated circuit from external interference. Such shields are in general placed outside the package containing the chip and are located on the electronic card in order to shield the circuits regarded as being sensitive and the circuits regarded as being sources of interference. In particular, they are placed a certain distance from the chip inductors for the purpose of not modifying the magnetic field of the inductors nor to degrade their quality factor. To do this, these shields are placed more than 500 microns (μm) from the inductor.
Moreover, U.S. Pat. No. 6,486,534 describes an integrated circuit comprising a first circuit and at least a second circuit in which a Faraday cage, comprising vias and a ground plane within the substrate, is placed around the first circuit in order to protect the second circuit from electromagnetic interference produced by the first circuit (column 2, lines 14–18). Thus, to protect a sensitive element, for example an inductor of a VCO, from disrupting elements, the teaching provided by that document suggests placing one or more Faraday cages around the disrupting elements. However, this means not forgetting one of them. Moreover, this solution is expensive. Furthermore, by implementing this solution, the sensitive element is not protected from an unanticipated external disrupting element, for example a user's finger coming close to the VCO.


According to some embodiments, system and methods are provided, comprising providing a dual-mode model for a reciprocating compressor, wherein the model includes a measurement mode and a tuning mode; receiving one or more inputs to the model from an operating reciprocating compressor; and in response to receipt of the one or more inputs, executing the model in at least one of the measurement mode and the tuning mode, wherein: in a measurement mode, execution of the model further comprises calculating an actual flow rate of gas in the compressor based on the one or more inputs; and in a tuning mode, execution of the model further comprises calculating one of an unloader setting and a speed set point of a physical element of the compressor for a given flow rate of gas. Numerous other aspects are provided.

Industrial equipment or assets, generally, are engineered to perform particular tasks as part of a business process. For example, industrial assets can include, among other things and without limitation, manufacturing equipment on a production line, wind turbines that generate electricity on a wind farm, power plant or aircraft turbines, healthcare or imaging devices, or drilling equipment for use in mining operations. The design and implementation of these assets often takes into account both the physics of the task at hand, as well as the environment in which such assets are configured to operate.
Low-level software and hardware-based controllers have long been used to drive industrial assets. However, the rise of inexpensive cloud computing, increasing sensor capabilities, and decreasing sensor costs, as well as the proliferation of mobile technologies have created opportunities for creating novel industrial assets with improved sensing technology that are capable of transmitting data that can then be transmitted to a network. As a consequence, there are new opportunities to enhance the business value of some industrial assets using novel industrial-focused hardware and software.
A reciprocating compressor used to deliver gases at high pressure is an example of industrial equipment. Conventionally, compressor control and diagnostic systems rely on a lot of additional hardware and sensors to monitor and operate the compressor and are costly. Operators typically face hurdles with respect to operating the compressor and diagnostic systems associated with compressors.
It would be desirable to provide systems and methods to improve reciprocating compressor control systems in a way that provides optimized compressor and engine operation.

Two-stage reciprocating compressor optimization control system


A method for the improvement of yield and freeness which does not discolor the paper product and gives a long life to the product and exerts stable yield improving effect even for the paper stuff containing much deinked pulp and filler as well as a yield improving promotor used in this method are provided.. In the method for the improvement of yield and freeness in the paper-making process and the waste water treating process according to the present invention, a special phenol resin is used in combination with polyethylene oxide (PEO). The phenol resin of the present invention is a sulfonated phenol-formaldehyde resin synthesized by sulfonating a phenol and then condensing it with formaldehyde. Preferred as the phenol to be sulfonated are Bisphenol A and Bisphenol S.. By using the method of the present invention, the yields of fine fiber and filler can be improved and the paper stuffs can be saved and the waste water treating load can be decreased.

In the paper-making process for newspaper and telephone directory paper and so, various yield-improving systems have been adopted for the purpose of improvement in the yield of fine fibers and fillers and improvement of freeness. Among them, the technology using polyethylene oxide as a yield-improving agent has an advantage in that it is not affected by a large amount of water-soluble anionic substance and suspended colloid substance contained in the paper stuff. In the yield-improving system by PEO, it is not substantially used alone but various agents are used in combination (yield-improvement promotor). Various water-soluble phenol resins have been developed as effective promotors.
However, when a well-known water-soluble phenol resin is added, the pH of paper stuff becomes high. When the amount of the phenol resin is increased, the paper product is discolored, the life of the product is reduced and it is hardened by thickening and self-crosslinking.
Further, in the case of a combination of a phenol resin and PEO according to the conventional technology, it has been pointed out that the yield becomes unstable by admixture of a deinking agent originated from deinked pulp (referred to as DIP hereinafter) thereby effecting the yield of fillers and making the removal of sticky materials are insufficient.
The subject of the present invention is to solve the conventional problems described above and to provide a method for the improvement of yield and freeness in the paper-making and waste water treating process which gives no discoloration of paper product and extends the product life and can exert stable yield improving effect on the paper product containing a large amount of DIP and filler.
Further, the subject of the present invention is to provide an excellent yield improvement promotor for paper-making which is a phenol resin used in combination with PEO in the method and gives no discolorarion of paper product and extends the product life and can exert stable yield improving effect on the paper product containing a large amount of DIP and filler.
We, inventors, have investigated eagerly to solve the above problems and have found that a reaction product able to provide an aqueous solution of neutral to acidic, to give no discoloration of paper product and to extend the product life and to exert stable yield improving effect on the paper product containing a large amount of DIP and filler can be obtained by sulfonating a phenol and then condensing it with formaldehyde, and have found that the improvement of yield and freeness in the paper-making and waste water treating process can be attained when the reaction product is used in combination with PEO to complete the present invention.

Sulfonated phenol-formaldehyde resin for paper-making


A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the cells in a row using a set of bit state assignments chosen by evaluating data that are to be written to the cells in the row. The control logic unit performs this evaluation by determining the number of cells in the row that will be programmed to each of a plurality of bit states corresponding to the write data. The control logic unit then selects a set of bit state assignments that will cause the programming level assigned to each bit state to be inversely proportional to the number of memory cells in the row that are programmed with the bit state. The selected set of bit states is then used to program the memory cells in the row.

Electrically erasable and programmable non-volatile memory devices having arrays of flash memory cells are found in a wide variety of electrical devices. One very common type of erasable and programmable non-volatile memory device is a flash memory device. A flash memory device uses flash memory cell, also known as a floating gate transistor memory cell, that are similar to a field effect transistor, having a source region and a drain region that is spaced apart from the source region to form an intermediate channel region. A floating gate, typically made of doped polysilicon, is disposed over the channel region and is electrically isolated from the channel region by a layer of gate oxide. A control gate is fabricated over the floating gate, and it can also be made of doped polysilicon. The control gate is electrically separated from the floating gate by a dielectric layer. Thus, the floating gate is "floating" in the sense that it is insulated from the channel, the control gate and all other components of the flash memory cell.
A flash memory cell is programmed by storing charge on the floating gate. The charge thereafter remains on the gate for an indefinite period even after power has been removed from the flash memory device. It is for this reason that flash memory devices are non-volatile. Charge is stored on the floating gate by applying appropriate voltages to the control gate and the drain or source. For example, a negative charge can be placed on the floating gate by grounding the source while applying a sufficiently large positive voltage to the control gate to attract electrons, which tunnel through the gate oxide to the floating gate from the channel region. The voltage applied to the control gate, called a programming voltage, determines the amount of charge residing on the floating gate after programming.
The flash memory cell can be read by applying a positive control gate to source voltage having a magnitude greater than a threshold voltage. The amount of charge stored on the flash memory cell determines the magnitude of the threshold voltage that must be applied to the control gate to allow the flash memory cell to conduct current between the source and the drain. As negative charge is added to the floating gate, the threshold voltage of the flash memory cell increases. During a read operation, a read voltage is applied to the control gate that is large enough to render the cell conductive if no charge is stored on the floating gate, but not large enough to render the cell conductive if charge is stored on the floating gate. During the read operation, the source is coupled to ground, and a positive voltage is applied through a suitable impedance to the drain, which is used as the output terminal of the cell. Therefore, if the floating gate of the flash memory cell is charged, the drain will remain at the positive voltage. If the floating gate of the flash memory cell is not charged, the cell will ground the drain.
Before a flash memory cell can be programmed, it must be erased by removing charge from the floating gate. The cell can be erased by applying a gate-to-source voltage to the cell that has a polarity opposite that used for programming. Specifically, the control gate is grounded, and a large positive voltage is applied to the source to cause the electrons to tunnel through the gate oxide and deplete the charge from the floating gate. In another approach, a relatively large negative voltage is applied to the control gate, and a positive voltage, such as a supply voltage, is applied to the source region.
A typical flash memory device includes a memory array containing a large number of flash memory cells arranged in rows and columns. Two common types of flash memory array architectures are the "NAND" and "NOR" architectures, so called for the logical form in which the basic flash memory cell configuration or each is arranged. FIG. 1 illustrates a typical NAND flash memory array 10 of conventional design. The array 10 is comprised of a large number of flash memory cells, collectively indicated by reference numeral 14. The array of flash memory cells 14 is typically divided into a number of blocks, with each block including a number of rows, such as, in the example shown in FIG. 1, 32 rows. The cells 14 in the same row have their control gates coupled to a common word select line 30, each of which receives a respective word line signal WL0-WL31. The cells 14 in the same column having their sources and drains connected to each other in series. Thus all of the memory cells 14 in the same column of each block are typically connected in series with each other. The drain of the upper flash memory cell 14 in the block is coupled to a bit line 20 through a first select gate transistor 24. The conductive state of the transistors 24 in each block are controlled by a source gate SG(D) signal. Each of the bit lines 20 output a respective bit line signal BL1-BLN indicative of the data bit stored in the respective column of the array 10. The bit lines 20 extend through multiple blocks to respective sense amplifiers (not shown). The source of the lower flash memory cell 14 in the block is coupled to a source line 26 through a second select gate transistor 28. The conductive state of the transistors 28 in each block are controlled by a source gate SG(S) signal. The source line 26 receives a signal SL having various magnitudes depending upon whether the memory cells 14 are being programmed, read or erased.
A read operation is performed on a row-by-row basis. When a read operation is to be performed for a selected block, the source line 26 is coupled to ground, and the select gate transistors 24, 28 for that block are turned ON responsive to high SG(D) and SG(S) signals. Also, the bit line 20 for each column is precharged to the supply voltage VCC. Finally, a read voltage is applied to a word select line 30 for the selected row, thereby applying the read voltage to the control gates of all of the flash memory cells 14 in that row. As explained above, the magnitude of the read voltage is sufficient to turn ON all flash memory cells 14 that do not have a charged floating gate, but insufficient to turn ON all cells that have a charged floating gate. A voltage having a higher magnitude is applied to the word select lines 30 for all of the non-selected rows. This voltage is large enough to turn ON the flash memory cells 14 even if their floating gates are storing charge. As a result, the bit line 20 for each column will be low if the cell 14 in that column of the selected row is not storing charge. Otherwise the bit line 20 remains high at VCC. The voltage on each bit line 20 is compared to a reference voltage by a respective sense amplifier (not shown). If the voltage on the bit line 20 is less than the reference voltage, the sense amplifier outputs a voltage corresponding to a "1" binary value of the read data bit. If the voltage on the bit line 20 is greater than the reference voltage, the sense amplifier outputs a voltage corresponding to a "0" binary value of the read data bit.
When a selected row of flash memory cells 14 are to be erased, the word select line 30 for the selected row is coupled to ground, and the source line 26 for each column is coupled to a positive voltage. A high SG(S) signal then turns ON the select gate transistors 28 to apply the positive voltage to the sources of the flash memory cells 14. The positive voltage then depletes charge from the floating gates in all of the cells 14, thereby erasing all of the memory cells 14 in the selected row. The flash memory cells 14 are normally erased on a block-by-block basis by grounding the word select lines 30 for all of the cells 14 in the block. Insofar as erasing the cells 14 removes charge from their floating gates, erasing the cells 14 effectively programs them to store logic "1" bit values.
When a selected row of cells 14 are to be programmed, a programming voltage is applied to the word select line 30 for the selected row, and a voltage sufficient to turn ON the remaining cells 14 is applied to the control gates of the remaining flash memory cells 14. Also, the first column select transistor 24 is turned ON and voltages corresponding to the data bits that are to be programmed are applied to the respective bit lines. If the voltage of a bit line 20 is at ground corresponding to a logic "0," charge will be stored in the floating gate of the flash memory cell 14 in that column of the selected row. Otherwise, a voltage on the bit line 20 corresponding to a logic "1" prevents any charge from being stored on the floating gate. Programming is therefore performed on a row-by-row basis.
The storage capacity of a flash memory array can be increased by storing multiple bits of data in each flash memory cell 14. This can be accomplished by storing multiple levels of charge on the floating gate of each cell 14. These memory devices are commonly referred to as multi-bit or multi-level flash memory cells, known as "MLC memory cells." In MLC cells, multiple bits of binary data corresponding to distinct threshold voltage levels defined over respective voltage ranges are stored within a single cell. Each distinct threshold voltage level corresponds to a respective combination of data bits. Specifically, the number N of bits requires 2N distinct threshold voltage levels. For example, for a flash memory cell to store 2 bits of data, 4 distinct threshold voltage levels corresponding to bit states 00, 01, 10, and 11 are needed. When reading the state of the memory cell, the threshold voltage level for which the memory cell 14 conducts current corresponds to a combination of bits representing data programmed into the cell. The two or more bits stored in each flash memory cell 14 can be adjacent bits in the same page of data. However, more frequently, one bit is treated as a bit in one page of data, and the other bit is treated as the corresponding bit in an adjacent page of data. The bit states assigned to respective charge levels are normally the same for all rows of memory cells in an array. The bit states assigned to the flash memory cells in the array are usually implemented in hardware and thus cannot be changed during operation of the flash memory device.
A multi-level flash memory cell is programmed by applying a programming voltage to the control gate and holding the drain to a constant voltage over a proper time period to store enough charge in the floating gate to move the threshold voltage of the flash memory cell 14 to a desired level. This threshold voltage level represents a bit state of the cell corresponding to the combination of data bits stored in the cell. As with programming single-level flash cells, programming of multi-level cells is performed on a row-by-row basis.
FIG. 2A illustrates the cell data map for a conventional one-bit-per-cell flash cell. As shown in FIG. 2A, two separate charge levels or ranges are defined within the overall flash cell threshold voltage range. When reading from such a flash cell, all that is necessary is to determine whether the threshold voltage is above or below the midpoint between the two levels. Voltages in one level are interpreted as a single binary bit (zero or one) while voltages in the other level are interpreted as the complementary binary bit (one or zero).
FIG. 2B, on the other hand, illustrates the cell data map for a multi-level flash memory cell capable of storing two bits. As can be seen in FIG. 2B, the data map defines four separate charge ranges or levels (Levels 0, 1, 2, and 3) within the range of the cell's overall maximum threshold voltage. Each level is assigned a two-bit pair or bit-set 00, 01, 10, or 11. The multiple bits stored in each row can be used as adjacent bits in a single page of memory. Alternatively, the multiple bits stored in each row can be used as corresponding bits in two different pages of memory. For example, the data bits X,Y stored in the first column can be used so that X is the first data bit of one page, and Y is the first data bit of an adjacent page.
There is also a limit to the precision with which circuitry can store an analog value on the floating gate of a flash cell, particularly where multiple levels of charge must be stored. In particular, because of process variations, the flash cells across an entire array and even across a single row may not all behave identically. For these reasons, conventional circuitry for programming or erasing the flash cells typically perform these task in an algorithmic manner. Specifically, the circuitry applies an appropriate voltage level to the control gate of a cell to charge the floating gate to a specific level, then interrogates the cell to determine if the floating gate has been charged to that level. If the floating gate has not been sufficiently charged, the circuitry again applies an appropriate voltage level to the control gate of the cell. This process is repeated until the floating gate has been charged to the desired level.
As the demand for memory capacity continues to increase, flash memory devices are being fabricated with increasingly higher densities. As a result, the spacing between the components of a flash memory device continues to decrease. As the spacing between these components becomes smaller, signals are more easily coupled between adjacent components. A signal applied to one component can therefore generate a spurious signal in an adjacent component. For example, a programming voltage applied to a selected word line to program a memory cell in a selected column can be coupled to the floating gate of memory cells in non-selected columns of that same row. These program disturb effects can increase the charge stored on the floating gates of memory cells in the row that either have been programmed or are being programmed to a lower charge level, thereby resulting in data storage errors. Similarly, an increase in the voltage of a floating gate caused by programming a selected memory cell can be coupled to the floating gate of an adjacent non-selected memory cell, thereby also inadvertently affecting the charge stored on the floating gate of the non-selected memory cell. These floating gate-to-floating gate and program disturb problems are most acute when programming multi-level flash memory cells, and it is for that reason that this description primarily refers to multi-level flash memory cells. However, these types of floating gate-to-floating gate and program disturb problems or similar problems can also exist when programming single-level flash memory cells and possibly other types of volatile memory devices.
As mentioned above, a flash memory cell is programmed by applying a programming voltage to the control gate and holding the drain to a constant voltage over a proper time period to store enough charge in the floating gate to move the threshold voltage of the flash memory cell to a desired level. Programming a flash memory cell with a higher charge level therefore requires applying a high programming voltage to the control gate of the cell through a respective word line. The magnitude of a spurious signal coupled to a word line from an adjacent word line or to a floating gate of a memory cell from the floating gate of an adjacent memory cell increases with increasing programming voltage. Therefore, higher programming voltages tend to induce a greater degree of floating gate-to-floating gate coupling and program disturb effects. Unfortunately, the magnitude of a programming voltage that must be applied to the control gate of a flash memory cell is fixed by the characteristics of the memory device, the number of charge levels to which each cell can be programmed in a multi-level memory cell, and the bit set to which the cell is to be programmed. The bit set used to program the cell is, of course, determined by the value of the data that is to be stored in the memory device.
There is therefore a need for a non-volatile memory device and method that reduces the coupling of spurious signals to components of the device, such as floating gate-to-floating gate coupling and program disturb effects.

This patent is subject to a terminal disclaimer.

Memory device and method having charge level assignments selected to minimize signal coupling


A telephone apparatus is connected to a plurality of telephone lines and has a transfer function for transferring a call among the plurality of telephone lines. The telephone apparatus includes circuit interfaces each of which has a 2-4 line substitution function and conducts an interface function between each of the plurality of telephone lines and a telephone apparatus internal circuit. A first amplifier amplifies a signal from a first telephone line and a second amplifier amplifies a signal from a second telephone line. A control unit compares the levels of the signals from the first and second telephone lines to control the amplification factors of the first and second amplifiers on the basis of a result of the comparison.

1. Field of the Invention
The present invention relates to a telephone apparatus, and more particularly relates to a telephone apparatus to which a plurality of telephone lines are connected and which has a transfer function at the time of a call between telephone sets.
2. Description of the Related Art
In general, a telephone apparatus with a transfer function is connected to a plurality of telephone sets as shown in FIG. 3 in the case where it is used in a tandem manner in an office. The operation of a telephone apparatus S when a telephone set P calls to the telephone apparatus S will be explained. When a dial signal based on a phone number which designates the telephone apparatus S is output from the telephone set P, a switching system Ex1 sends a ring signal to the telephone apparatus S, so that a speech path is formed between the telephone set P and the telephone apparatus S.
For the transfer, the telephone apparatus S sends a dial signal which designates a telephone set Q, so that a speech path is formed between the telephone apparatus S and the telephone set Q. Moreover, a speech path is formed between the telephone set on the side of a calling person (i.e. the telephone set P) and the telephone set on side of a called person (i.e. the telephone set Q). In other words, the telephone set P on the side of the calling person is connected to the telephone apparatus S with a transfer function through a switching system Ex2 and a switching system Ex1 by a public telephone line, and the telephone set Q on the side of the called person is connected to the telephone apparatus S with a transfer function through a switching system Ex3 and the switching system Ex1 by a public telephone line. A call between the telephone set P and the telephone set Q is produced by connecting the telephone set P and the telephone set Q with the telephone apparatus S.
By the way, the level of the call between such line wires becomes smaller than that of a call between two persons due to the circuit loss between the switching system Ex1 and the telephone apparatus S. If the damped signal is amplified by an amplifier, a loop is formed. Therefore, the signal return to the amplifier occurs, causing oscillation.

Telephone apparatus with call transfer function and with improved arrangement for hand-free operation

Matsushita Electric Industrial Co., Ltd.


Fractal image coding of single images or image sequences is described, which yields an improvement of the encoding result as well as a reduction of computations, wherein. each image is divided into range blocks which do not overlap and jointly comprise the complete image contents, PA1 range regions are generated, each comprising a range block which is smaller than the range region concerned, and the rest of the range region is filled up with a predetermined signal value, PA1 domain regions are generated having the same size as the range regions and comprise parts of the image contents, preferably also in a transformed form, PA1 the image data of the range regions and the domain regions are subjected to a Fourier transform, PA1 a conjugate-complex signal is formed from one of the two transformed signals and multiplied by the other signal, PA1 this product is normalized at a predetermined amplitude, PA1 the normalized signal is subjected to an inverse Fourier transform, PA1 for each range region, the maximum value of this retransformed signal is determined, indicating, within a domain region, the position of that domain block whose image contents best approximate the image contents of the range block, PA1 for these domain blocks, those scaling and offset factors are determined which, when used for the domain blocks found, enable these domain blocks to be imaged on the range blocks with the smallest deviation, and PA1 the encoded signal comprises the addresses of these domain blocks, whose image contents best approximate the range blocks, the scaling and offset factors.

The invention relates to a method of fractal image coding of single images or image sequences. The invention also relates to an arrangement for performing the method.
In known arrangements or methods for fractal image coding, the image is divided into range blocks. These blocks have mutually equal sizes, do not overlap and cover the complete image contents. Moreover, domain blocks are generated which comprise image data about a given image area. Since the domain blocks may overlap, the number of domain blocks is a multiple of the number of range blocks. Such a method is known from, for example the article "Fractal Image Coding and Magnification using Invariant Moments", by D. Gotting, A. Ibenthal and R.-R. Grigat, in Nato Advance Study Institute on Fractal Image Encoding and Analysis, Trondheim, Norway, 1995.
A domain block is searched for each range block, which domain block can be imaged on the range block with a minimal deviation by means of an (affine) transformation.
The problem with coding is that, due to the number of large domain blocks, the search for the most favorable domain block for each range block requires a considerably elaborate computation. Moreover, due to the fixed division of the image, this known method is inflexible, particularly in the domain blocks.

Method of fractal image coding and arrangement of performing the method


There is disclosed a utility robot for operating in multiple modes, in particular, at least one autonomous mode and at least one manual mode. The robot is configured with a recognition system for recognizing a signal indicating the particular mode in which to operate, and adjusts its control system accordingly. Methods for operation of this utility, performing various tasks, such as lawn mowing, vacuuming, floor cleaning and snow removing are also disclosed.

The present invention relates to a utility robot and to method for operating a utility robot. More specifically, the present invention relates to an autonomous utility robot comprising multiple action modes and to a method for its operation.
As society becomes more advanced, it looks to ways in which time can be better utilized. Accordingly, there is a desire to replace humans with robots to perform common tasks, freeing people to do other things, and thus, better utilize their time. U.S. Pat. Nos. 5,353,224 and 5,402,051 disclose robots that function as cleaners.
Robots that have been used as self propelled lawn mowers, operating on the principle of random motion within a boundary, are described in U.S. Pat. Nos. 3,550,714, 4,809,178 and 3,570,227. Autonomous self propelled lawn mowers operating along pre planned routes are described in U.S. Pat. Nos. 3,650,097, 4,500,970, 4,694,639 and 3,789,939. Lawn mowers autonomously operating along defined edges or boundaries are described in U.S. Pat. Nos. 3,924,389, 3,425,197, 4,184,559, 4,545,453, 4,573,547, 4,777,785, 4,831,813, 5,007,234 and 5,204,814. Finally, WO 96/38770 describes a robot covering an area within boundaries, continuously correcting its position by comparing calculated and actual coordinates of the boundaries.
These autonomous robots exhibit drawbacks in that they operate in an autonomous mode only. They are designed to cover relatively large areas and can not be applied to small areas such as edges or small patches of grass. Furthermore, there are limitations on the navigation systems of the described robots which cause them to miss certain areas within the work area, such as those very close to the boundaries of the work area or to boundaries of obstacles within the work area. These aforementioned autonomous robots, therefore, are limited in their ability to entirely cover a required area and are not suited for use in relatively small areas, sometimes required in households.
It is an object of the present invention to provide a utility robot for performing a task, in at least one area, which overcomes the limitations of the existing utility robots in that it comprises an autonomous task performing mode or modes and a manual task performing mode or modes. It is further an object of the present invention to provide a method for operating a utility robot which includes combining an autonomous task performing mode or modes of operation with a manual mode or modes of operation. This combination, as available in a single robot, allows for operating in areas that are not accessible to a utility robot that operates only in the autonomous mode.
In a preferred embodiment the utility robot is a lawn mower capable of operating in at least one autonomous mode and at least one manual mode. The lawn mower comprises a main body configured for receiving a signal from a control device, a recognition system for recognizing the signal and a controller, in communication with the recognition system, for changing the operative mode, in accordance with the recognized signal.
The method for operating a utility robot, according to the present invention comprises sending a first signal, to a recognition system in the utility robot, for performing at least one task in said at least one area in a first mode and sending a second signal, to the recognition system, for performing said task in a second mode in said at least one area.


Embodiments disclose an apparatus and methods for biological sample processing enabling isolation and enrichment of microbial or pathogenic constituents from the sample. A vessel for sample containment and extraction is further disclosed for engagement with a transducer capable of efficient sample disruption and lysis. Together these components provide a convenient and inexpensive solution for rapid sample preparation compatible with downstream analysis techniques.

Rapid and accurate identification of infectious agents in resource limited settings is considered critical for controlling the prevalence and spread of disease. This is especially the case in high burden areas of the globe where economic and technological limitations constrain efficient disease management. Accurate disease diagnosis and pathogen monitoring may involve obtaining and isolating biological materials from a subject or patient sample, for example, in the form of sputum, blood, tissue, urine, or other specimen. Sample extraction techniques may then be employed to isolate or enrich for nucleic acids, proteins or other biological indicators used to detect or identify the presence of a pathogen or infectious agent within the sample.
An important area of disease monitoring relates to respiratory infections, such as pulmonary tuberculosis. Diagnosis, evaluation, and monitoring of subjects may involve collection of sputum samples followed by extraction and isolation of pathogen-originating nucleic acids present in the sample. For such samples it can be challenging to perform sample collection and biomaterial isolation in a manner compatible with downstream processing and analysis techniques. For example, RNA or DNA associated with a suspected pathogen may be desirably enriched to facilitate detection by polymerase chain reaction (PCR), isothermal amplification or other methods. Efficiently breaking down sputum, tissue isolates, and other biological samples can be difficult to perform in a safe and effective manner. Furthermore, low yield isolation protocols may increase the difficulty in detecting the presence of suspected pathogens.
A particular problem exists when attempting to extract and analyze pathogen-identifying nucleic acids from biological samples where the overall amount of the sample or the amount of nucleic acid present in the sample is limited. This problem is further exacerbated in resource limited settings, such as field applications, rural settings, or in underdeveloped communities and countries where lab facilities and sophisticated lab equipment may not be readily available. Providing access to sensitive and accurate biomolecular testing and analysis techniques in these environments continues to be an important challenge to overcome. In this regard, the present disclosure provides significant advances in sample processing and analysis techniques that may improve pathogen monitoring and disease management capabilities in resource-constrained regions of the world.

Apparatus and method for cell, spore, or virus capture and disruption


A Method for washing items in an automatic washing line, and an automatic washing apparatus. When items (1) are conveyed to a washing zone (2), the method uses a sensor (6a) for detecting if there is a continuous flow of items (1) to the washing zone (2). If there is a break in the flow of items, washing in the washing zone (2) is interrupted. The apparatus comprises a sensor (6a) for detecting if there is a continuous flow of items (1) to be washed to the washing zone (2). In addition the apparatus comprises a program for interrupting the wash in the washing zone (2) when the sensor (6a) detects a break in the flow of items (1) to be washed.

The invention relates to a method for washing items in an automatic washing line wherein the items to be washed are conveyed to a washing zone in succession and a sensor is used to detect the presence of an item in the sensor area of the sensor.
The invention also relates to an automatic washing apparatus for washing items, the apparatus comprising an accumulation area for accumulating items to be washed in succession into a line, a conveyor in the accumulation area for conveying the items to the washing zone, and a sensor for detecting the presence of an item in the sensor area of the sensor.
In institutional kitchens, such as hotel or restaurant kitchens, large quantities of dishes are washed daily. Washing is effected by placing the dishes in racks which are conveyed through a washing line. Such washing lines usually comprise prewash, main wash and rinsing.
The operating costs of a washing line consist of water, energy and detergent consumed. Previously attention has not been paid to what the idle running costs of such a washing line may be. Unexpectedly, calculations show that the idle running costs of a kitchen washing e.g. 500 standard-sized racks daily may, at worst, exceed FIM 100.000 per year.
Idle running is caused by the wash running although no racks are conveyed through the line or there is space between the racks. With the line empty, water, energy and detergents are wasted.

Method of washing items in a washing line and washing apparatus


An insulated gate semiconductor device comprising an insulator substrate having provided thereon a source and a drain region; a channel region being incorporated between said source and said drain regions, said channel region comprising a polycrystalline, a single crystal, or a semi-amorphous semiconductor material; and a region provided under said channel region, said region comprising an amorphous material containing the same material as that of the channel region as the principal component, or said region comprising a material having a band gap larger than said channel region.

1. Field of the Invention
The present invention provides a thin film insulated gate semiconductor device, and more specifically, it relates to a thin film transistor (TFT) having a large ON current to OFF current ratio (ON/OFF ratio) with particularly low OFF current.
2. Description of the Prior Art
Recently, researches are made on insulated-gate type semiconductor devices having a thin film channel on an insulator substrate. In particular, an extensive study is made on thin film insulated gate transistors, i.e., on so-called thin film transistors (TFTs). Those TFTs are intended for controlling pixels of matrix-structured display devices such as those equipped with liquid crystals. The TFTs are classified according to the type of semiconductor which is used therein. For example, they include amorphous silicon TFTs and polycrystalline silicon TFTs. Particularly at present, more effort is paid on the study of materials which take an intermediate crystal structure between amorphous and polycrystalline. Such materials, which are called semi-amorphous silicon, are believed to comprise small crystals being suspended in an amorphous texture.
In an integrated circuit (IC) based on single crystal silicon, polycrystalline silicon TFT also is employed in the so-called SOI technology, for example, to use as a load transistor in a highly integrated SRAM. In this case, however, an amorphous silicon TFT is very rarely used.
Amorphous silicon in general cannot be applied to rapid TFTs because the electric field mobility thereof is low. In particular, a p-channel TFT (PTFT) is unfeasible because the p-type electric field mobility is extremely low. Accordingly, no complementary MOS (CMOS) circuits can be realized using an amorphous silicon because the PTFT cannot be used in combination with an n-channel TFT (NTFT).
However, because the OFF current of an amorphous semiconductor TFT is small, those TFTs based on amorphous silicon are made the best of in applications such as transistors for active matrices of liquid crystals. In such applications, no rapid operation is required, and a TFT having either of the conductivity types suffices the demand. As the requirement for the TFT for such applications being high charge retention capacity, the above mentioned amorphous semiconductor TFTs are favorably employed.
In the contrary to the amorphous semiconductors, polycrystalline semiconductors have larger field mobility and hence are capable of rapid operation. In a TFT employing a silicon film recrystallized by laser annealing, a field mobility as high as 300 cm2/Vs is obtained. It can be seen that the value above for the recrystallized polycrystalline silicon film is extremely high as compared with that of a MOS transistor having fabricated on an ordinary single crystal silicon substrate, which is about 500 cm2/Vs. Considering that the operation speed of a MOS circuit being fabricated on a single crystal silicon is considerably impaired by the stray capacitance between the substrate and the connections, an extremely high operation speed is expected for the device on polycrystalline silicon because an insulator substrate is used therein.
Furthermore, not only an NTFT but also PTFT can be fabricated using polycrystalline silicon. Accordingly, a CMOS circuit can be constructed as well. For example, in a liquid crystal display device operating on an active matrix mode, not only the active matrix but also the peripheral circuits (such as the driver circuit) can be established using polycrystalline TFTs in CMOS circuits, thereby giving a so-called monolithic structure.
The TFTs for use in SRAMs also make the best of the same advantage. The PMOS are constructed with the TFTs to use as the load transistor.
However, as compared with the amorphous TFTs, polycrystalline TFTs in general suffer a higher OFF current because of the larger field mobility, and hence are inferior in retaining the pixel charges in an active matrix. This disadvantage has not been regarded as a serious problem in the conventional matrix having a pixel size of several hundreds of micrometers square, however, with increasing elaboration and fineness of the pixels, the pixel capacitance decreases to make a stable and static display unfeasible.
Furthermore, the source and drain regions (referred to simply as "source/drain regions" or collectively, as "a source/drain region") cannot be established on an ordinary amorphous TFT by a self-aligning process as those commonly used in the single crystal integrated circuit (IC) technology. This leads to the problem of stray capacitance which generates by geometrical superposition of the gate electrodes and the source/drain regions. On the contrary, the self-aligning process can be applied to polycrystalline TFTs and hence the stray capacitance can be suppressed low.
More specifically, a conventional TFT comprises, as shown in FIG. 2, a substrate 201 having established thereon a source region 204, drain region 202, and a channel region 203, all at about the same thickness. In a TFT having fabricated by a self-aligning process, the channel region (activated layer) 203 is established at approximately the same shape as that of the gate electrode 205. A interlayer insulator 206, as well as drain and source electrodes 207 and 208, respectively, are also provided in the TFT as shown in FIG. 2.
The conventional polycrystalline TFTs are advantageous in some aspects as described above, but there are also some disadvantages that are pointed out. With respect to the problem of OFF current, several measures are proposed to present. One of such countermeasures is to reduce the thickness of the activated region. It has been reported that the OFF current can be reduced by establishing a thinner activated region. For example, it is reported that a channel region having a reduced thickness of 25 nm can suppress the OFF current to 10−13 A or lower. However, it is extremely difficult to crystallize the thin semiconductor film because the film would not readily crystallize. That is, an activated region (channel region) having a sufficiently high crystallinity to realize a practically useful field mobility requires annealing at a high temperature or annealing for a long duration. If a high temperature annealing were to be applied, a heat-resistant substrate such as of quartz is necessary. However, a quartz substrate is expensive, and particularly so for a large area quartz substrate. The use of a large-area quartz substrate is therefore economically disadvantageous. If an annealing for a long duration were to be applied, the throughput decreases, and again, the process results in poor economy.
Furthermore, making the activated layer thinner signifies reducing the thickness of the source/drain regions. This arises from the fact that, in a commonly employed fabrication process, the source/drain regions are fabricated at the same time with the activated region. Thinner source/drain regions mean an increase of resistance in these regions. To avoid this increase in resistance, another step for depositing thicker source/drain regions must be added. However, such an additional step is unfavorable from the viewpoint of yield.
Moreover, the present inventors have found that a MOS having fabricated from a TFT with an activated layer of 50 nm or less yields a low threshold voltage. Accordingly, when such TFTs are fabricated into a CMOS, the resulting product would suffer an extremely unstable operation.
If the activated layer is provided thicker, on the other hand, the OFF current increases but not in linear relation with the thickness of the activated layer. Hence, it is expected that the OFF current is increased non-linearly due to some reason. Characteristic curves for TFTs each having a 100 nm thick activated layer are given in FIG. 3(A). The TFT comprises a gate oxide film 150 nm in thickness, and an activated layer having fabricated by low-pressure chemical vapor deposition (LPCVD) process followed by annealing at 600° C. for 24 hours. The voltage between the source and the drain is 1 V. It can be seen from FIG. 3(A) that the both ON and OFF currents are large. Moreover, a shoulder-like anomaly can be observed to appear when a reversed bias is applied to the gate electrode.
When the activated layer is thickly provided, a TFT having a high electric field mobility results because a favorable crystallinity is obtained for the activated layer. No special high temperature annealing or long annealing is necessary in this case. As a result of the study of the present inventors, it has been found that the majority of the OFF current in the thick activated layer flow via the substrate side of the activated layer like flowing through a by-path. The flow path is indicated with an arrow 209 in FIG. 2. The ON/OFF ratio of a TFT can be expressed ideally by ION/IOFF, where ION and IOFF each represent the ON and OFF currents, respectively. When there is a leakage current ILK which flows through a by-path almost independently to the gate voltage, the ON/OFF ratio is expressed by (ION+ILK)/(IOFF+ILK). In practice, ILK is estimated to be far larger than IOFF, but smaller than ION. Hence the apparent ON/OFF ratio is expressed by ION/ILK. It can be seen that the ON/OFF ratio, which is an important index for a TFT, appears to be extremely reduced in this case.
The leakage current above in general occurs by the following two reasons. One is the poor crystallinity of the activated layer on the substrate side. Too many grain boundaries in this side of the activated layer generate many trap levels that the charge migrates by hopping along these trap levels. Since the trap levels are present irrespective of the presence of a gate voltage, they permanently serve as offset current sources. Theoretically, this problem can be overcome by optimizing the conditions for crystal growth, but with a great difficulty.
The other problem resides on the activated layer being rendered conductive on the substrate side because of the movable ions, such as sodium and the like, which have been incorporated into the activated layer from the substrate side. This problem can be solved by increasing the cleanness of the process.
Even if the problem of the leakage current were to be overcome by either of the measures above, the OFF current increases ohmically when the channel layer (activated layer) is thick. On the contrary, the resistivity of the source/drain is sufficiently small because the thickness thereof is thick enough.

Semiconductor device and method of forming the same

Abstract: A process for fabricating the device is also disclosed.

Semiconductor Energy Laboratory Co., Ltd.


Improved method of and apparatus for joining and aggregating data elements integrated within a relational database management system (RDBMS) using a non-relational multi-dimensional data structure (MDD). The improved RDBMS system of the present invention can be used to realize achieving a significant increase in system performance (e.g. deceased access/search time), user flexibility and ease of use. The improved RDBMS system of the present invention can be used to realize an improved Data Warehouse for supporting on-line analytical processing (OLAP) operations or to realize an improved informational database system or the like.

1. Field of Invention
The present invention relates generally to multi-dimensional relational databases and, more specifically to mechanisms for aggregating data elements in a multi-dimensional relational database system and for processing queries on such aggregated data elements, and also to informational database systems that utilize multi-dimensional relational databases and such aggregation/query mechanisms.
2. Brief Description of the State of the Art
Information technology (IT) enables an enterprise to manage and optimize its internal business practices through the analysis and sharing of data internally within the enterprise. In addition, IT enables an enterprise to manage and optimize its external business practices through the sharing of data with external parties such as suppliers, customers and investors, and through on-line transactions between the enterprise and external parties. Informational database systems (systems that store data, support query processing on the stored data, and possibly support analysis of the stored data) play a central role in many different parts of today's IT systems.
FIG. 1 illustrates exemplary domains where informational database systems are used. As shown, an operational environment 10 generates data which is stored in a data store 22 in the informational database system 20. These domains include data analysis systems (spread-sheet modeling programs, snap-shots, extraction, denormalization), data warehousing, data marts, OLAP systems, data mining systems, electronic commerce-enabled web servers, and business-to-business exchanges. Modern informational database systems typically use a relational database management system (RDBMS) as a repository for storing the data and querying the data.
FIG. 2 illustrates a data warehouse-OLAP domain that utilizes the prior art approaches described above. The data warehouse is an enterprise-wide data store. It is becoming an integral part of many information delivery systems because it provides a single, central location where a reconciled version of data extracted from a wide variety of operational systems is stored. Details on methods of data integration and constructing data warehouses can be found in the white paper entitled "Data Integration: The Warehouse Foundation" by Louis Rollleigh and Joe Thomas, published at http://www.acxiom.com/whitepapers/wp-11.asp. Building a Data Warehouse has its own special challenges (e.g. using common data model, common business dictionary, etc.) and is a complex endeavor. However, just having a Data Warehouse does not provide organizations with the often-heralded business benefits of data warehousing. To complete the supply chain from transactional systems to decision maker, organizations need to deliver systems that allow knowledge workers to make strategic and tactical decisions based on the information stored in these warehouses. These decision support systems are referred to as On-Line Analytical Processing (OLAP) systems. Such OLAP systems are commonly classified as Relation OLAP systems or Multi-Dimensional OLAP systems.
The Relational OLAP (ROLAP) system accesses data stored in a Data Warehouse to provide OLAP analyses. The premise of ROLAP is that OLAP capabilities are best provided directly against the relational database, i.e. the Data Warehouse. The ROLAP architecture was invented to enable direct access of data from Data Warehouses, and therefore support optimization techniques to meet batch window requirements and provide fast response times. Typically, these optimization techniques include application-level table partitioning, pre-aggregate inferencing, denormalization support, and the joining of multiple fact tables.
A typical ROLAP system has a three-tier or layer client/server architecture. The "database layer" utilizes relational databases for data storage, access, and retrieval processes. The "application logic layer" is the ROLAP engine which executes the multidimensional reports from multiple users. The ROLAP engine integrates with a variety of "presentation layers," through which users perform OLAP analyses. After the data model for the data warehouse is defined, data from on-line transaction-processing (OLTP) systems is loaded into the relational database management system (RDBMS). If required by the data model, database routines are run to pre-aggregate the data within the RDBMS. Indices are then created to optimize query access times. End users submit multidimensional analyses to the ROLAP engine, which then dynamically transforms the requests into SQL execution plans. The SQL execution plans are submitted to the relational database for processing, the relational query results are cross-tabulated, and a multidimensional result data set is returned to the end user. ROLAP is a fully dynamic architecture capable of utilizing pre-calculated results when they are available, or dynamically generating results from the raw information when necessary.
The Multidimensional OLAP (MOLAP) systems utilize a MDD or "cube" to provide OLAP analyses. The main premise of this architecture is that data must be stored multidimensionally to be accessed and viewed multidimensionally. Such non-relational MDD data structures typically can be queried by users to enable the users to "slice and dice" the aggregated data. As shown in FIG. 2, such MOLAP systems have an Aggregation module which is responsible for all data storage, access, and retrieval processes, including data aggregation (i.e. pre-aggregation) in the MDDB, and an analytical processing and GUI module responsible for interfacing with a user to provide analytical analysis, query input, and reporting of query results to the user.
A more detailed description of the data warehouse and OLAP environment may be found in copending U.S. patent application Ser. No. 09/514,611 to R. Bakalash, G. Shaked, and J. Caspi, commonly assigned to HyperRoll Israel, Limited, incorporated by reference above in its entirety.
In a RDBMS, users view data stored in tables. By contrast, users of a non-relation database system can view other data structures, either instead of or in addition to the tables of the RDBMS system. FIG. 3A illustrates an exemplary table in an RDBMS; and FIGS. 3B and 3C illustrate operators (queries) on the table of FIG. 3A, and the result of such queries, respectively. The operators illustrated in FIGS. 3B and 3C are expressed as Structured Query Language (SQL) statements as is conventional in the art.
The choice of using a RDBMS as the data repository in information database systems naturally stems from the realities of SQL standardization, the wealth of RDBMS-related tools, and readily available expertise in RDBMS systems. However, the querying component of RDBMS technology suffers from performance and optimization problems stemming from the very nature of the relational data model. More specifically, during query processing, the relational data model requires a mechanism that locates the raw data elements that match the query. Moreover, to support queries that involve aggregation operations, such aggregation operations must be performed over the raw data elements that match the query. For large multi-dimensional databases, a naive implementation of these operations involves computational intensive table scans that leads to unacceptable query response times.
In order to better understand how the prior art has approached this problem, it will be helpful to briefly describe the relational database model. According to the relational database model, a relational database is represented by a logical schema and tables that implement the schema. The logical schema is represented by a set of templates that define one or more dimensions (entities) and attributes associated with a given dimension. The attributes associated with a given dimension includes one or more attributes that distinguish it from every other dimension in the database (a dimension identifier). Relationships amongst dimensions are formed by joining attributes. The data structure that represents the set of templates and relations of the logical schema is typically referred to as a catalog or dictionary. Note that the logical schema represents the relational organization of the database, but does not hold any fact data per se. This fact data is stored in tables that implement the logical schema.
Star schemas are frequently used to represent the logical structure of a relational database. The basic premise of star schemas is that information can be classified into two groups: facts and dimensions. Facts are the core data elements being analyzed. For example, units of individual item sold are facts, while dimensions are attributes about the facts. For example, dimensions are the product types purchased and the data purchase. Business questions against this schema are asked looking up specific facts (UNITS) through a set of dimensions (MARKETS, PRODUCTS, PERIOD). The central fact table is typically much larger than any of its dimension tables.
An exemplary star schema is illustrated in FIG. 4A for suppliers (the "Supplier" dimension) and parts (the "Parts" dimension) over time periods (the "Time-Period" dimension). It includes a central fact table "Supplied-Parts" that relates to multiple dimensions—the "Supplier", "Parts" and "Time-Period" dimensions. FIG. 4B illustrates the tables used to implement the star schema of FIG. 4A. More specifically, these tables include a central fact table and a dimension table for each dimension in the logical schema of FIG. 4A. A given dimension table stores rows (instances) of the dimension defined in the logical schema. For the sake of description, FIG. 4B illustrates the dimension table for the "Time-Period" dimension only. Similar dimension tables for the "Supplier" and "Part" dimensions (not shown) are also included in such an implementation. Each row within the central fact table includes a multi-part key associated with a set of facts (in this example, a number representing a quantity). The multi-part key of a given row (values stored in the S#,P#, TP# fields as shown) points to rows (instances) stored in the dimension tables described above. A more detailed description of star schemas and the tables used to implement star schemas may be found in C.J. Date, "An Introduction to Database Systems," Seventh Edition, Addison-Wesley, 2000, pp. 711–715, herein incorporated by reference in its entirety.
When processing a query, the tables that implement the schema are accessed to retrieve the facts that match the query. For example, in a star schema implementation as described above, the facts are retrieved from the central fact table and/or the dimension tables. Locating the facts that match a given query involves one or more join operations. Moreover, to support queries that involve aggregation operations, such aggregation operations must be performed over the facts that match the query. For large multi-dimensional databases, a naive implementation of these operations involves computational intensive table scans that typically leads to unacceptable query response times. Moreover, since the fact tables are pre-summarized and aggregated along business dimensions, these tables tend to be very large. This point becomes an important consideration of the performance issues associated with star schemas. A more detailed discussion of the performance issues (and proposed approaches that address such issues) related to joining and aggregation of star schema is now set forth.
The first performance issue arises from computationally intensive table scans that are performed by a naive implementation of data joining. Indexing schemes may be used to bypass these scans when performing joining operations. Such schemes include B-tree indexing, inverted list indexing and aggregate indexing. A more detailed description of such indexing schemes can be found in "The Art of Indexing", Dynamic Information Systems Corporation, October 1999, available at http://www.disc.com/artindex.pdf. All of these indexing schemes replaces table scan operations (involved in locating the data elements that match a query) with one ore more index lookup operation. Inverted list indexing associates an index with a group of data elements, and stores (at a location identified by the index) a group of pointers to the associated data elements. During query processing, in the event that the query matches the index, the pointers stored in the index are used to retrieve the corresponding data elements pointed therefrom. Aggregation indexing integrates an aggregation index with an inverted list index to provide pointers to raw data elements that require aggregation, thereby providing for dynamic summarization of the raw data elements that match the user-submitted query.
These indexing schemes are intended to improve join operations by replacing table scan operations with one or more index lookup operation in order to locate the data elements that match a query. However, these indexing schemes suffer from various performance issues as follows:                Since the tables in the star schema design typically contain the entire hierarchy of attributes (e.g. in a PERIOD dimension, this hierarchy could be day>week>month>quarter>year), a multipart key of day, week, month, quarter, year has to be created; thus, multiple meta-data definitions are required (one of each key component) to define a single relationship; this adds to the design complexity, and sluggishness in performance.        Addition or deletion of levels in the hierarchy will require physical modification of the fact table, which is time consuming process that limits flexibility.        Carrying all the segments of the compound dimensional key in the fact table increases the size of the index, thus impacting both performance and scalability.
Another performance issue arises from dimension tables that contain multiple hierarchies. In such cases, the dimensional table often includes a level of hierarchy indicator for every record. Every retrieval from fact table that stores details and aggregates must use the indicator to obtain the correct result, which impacts performance. The best alternative to using the level indicator is the snowflake schema. In this schema aggregate tables are created separately from the detail tables. In addition to the main fact tables, snowflake schema contains separate fact tables for each level of aggregation. Notably, the snowflake schema is even more complicated than a star schema, and often requires multiple SQL statements to get the results that are required.
Another performance issue arises from the pairwise join problem. Traditional RDBMS engines are not design for the rich set of complex queries that are issued against a star schema. The need to retrieve related information from several tables in a single query—"join processing" —is severely limited. Many RDBMSs can join only two tables at a time. If a complex join involves more than two tables, the RDBMS needs to break the query into a series of pairwise joins. Selecting the order of these joins has a dramatic performance impact. There are optimizers that spend a lot of CPU cycles to find the best order in which to execute those joins. Unfortunately, because the number of combinations to be evaluated grows exponentially with the number of tables being joined, the problem of selecting the best order of pairwise joins rarely can be solved in a reasonable amount of time.
Moreover, because the number of combinations is often too large, optimizers limit the selection on the basis of a criterion of directly related tables. In a star schema, the fact table is the only table directly related to most other tables, meaning that the fact table is a natural candidate for the first pairwise join. Unfortunately, the fact table is the very largest table in the query, so this strategy leads to selecting a pairwise join order that generates a very large intermediate result set, severely affecting query performance.
This is an optimization strategy, typically referred to as Cartesian Joins, that lessens the performance impact of the pairwise join problem by allowing joining of unrelated tables. The join to the fact table, which is the largest one, is deferred until the very end, thus reducing the size of intermediate result sets. In a join of two unrelated tables every combination of the two tables' rows is produced, a Cartesian product. Such a Cartesian product improves query performance. However, this strategy is viable only if the Cartesian product of dimension rows selected is much smaller than the number of rows in the fact table. The multiplicative nature of the Cartesian join makes the optimization helpful only for relatively small databases.
In addition, systems that exploit hardware and software parallelism have been developed that lessens the performance issues set forth above. Parallelism can help reduce the execution time of a single query (speed-up), or handle additional work without degrading execution time (scale-up).). For example, Red Brick™ has developed STARjoin™ technology that provides high speed, parallelizable multi-table joins in a single pass, thus allowing more than two tables can be joined in a single operation. The core technology is an innovative approach to indexing that accelerates multiple joins. Unfortunately, parallelism can only reduce, not eliminate, the performance degradation issues related to the star schema.
One of the most fundamental principles of the multidimensional database is the idea of aggregation. The most common aggregation is called a roll-up aggregation. This type is relatively easy to compute: e.g. taking daily sales totals and rolling them up into a monthly sales table. The more difficult are analytical calculations, the aggregation of Boolean and comparative operators. However these are also considered as a subset of aggregation.
In a star schema, the results of aggregation are summary tables. Typically, summary tables are generated by database administrators who attempt to anticipate the data aggregations that the users will request, and then pre-build such tables. In such systems, when processing a user-generated query that involves aggregation operations, the pre-built aggregated data that matches the query is retrieved from the summary tables (if such data exists). FIGS. 5A and 5B illustrate a multi-dimensional relational database using a star schema and summary tables. In this example, the summary tables are generated over the "time" dimension storing aggregated data for "month", "quarter" and "year" time periods as shown in FIG. 5B. Summary tables are in essence additional fact tables, of higher levels. They are attached to the basic fact table creating a snowflake extension of the star schema. There are hierarchies among summary tables because users at different levels of management require different levels of summarization. Choosing the level of aggregation is accomplished via the "drill-down" feature.
Summary tables containing pre-aggregated results typically provide for improved query response time with respect to on-the-fly aggregation. However, summary tables suffer from some disadvantages:                summary tables require that database administrators anticipate the data aggregation operations that users will require; this is a difficult task in large multi-dimensional databases (for example, in data warehouses and data mining systems), where users always need to query in new ways looking for new information and patterns.        summary tables do not provide a mechanism that allows efficient drill down to view the raw data that makes up the summary table—typically a table scan of one or more large tables is required.        querying is delayed until pre-aggregation is completed.        there is a heavy time overhead because the vast majority of the generated information remains unvisited.        there is a need to synchronize the summary tables before the use.        the degree of viable parallelism is limited because the subsequent levels of summary tables must be performed in pipeline, due to their hierarchies.        for very large databases, this option is not valid because of time and storage space.Note that it is common to utilize both pre-aggregated results and on-the-fly aggregation in support aggregation. In these system, partial pre-aggregation of the facts results in a small set of summary tables. On-the-fly aggregation is used in the case the required aggregated data does not exist in the summary tables.
Note that in the event that the aggregated data does not exist in the summary tables, table join operations and aggregation operations are performed over the raw facts in order to generate such aggregated data. This is typically referred to as on-the-fly aggregation. In such instances, aggregation indexing is used to mitigate the performance of multiple data joins associated with dynamic aggregation of the raw data. Thus, in large multi-dimensional databases, such dynamic aggregation may lead to unacceptable query response times.
In view of the problems associated with joining and aggregation within RDBMS, prior art ROLAP systems have suffered from essentially the same shortcomings and drawbacks of their underlying RDBMS.
While prior art MOLAP systems provide for improved access time to aggregated data within their underlying MDD structures, and have performance advantages when carrying out joining and aggregations operations, prior art MOLAP architectures have suffered from a number of shortcomings and drawbacks which Applicants have detailed in their copending U.S. application Ser. Nos. 09/368,241 and 09/514,611 incorporated herein by reference.
In summary, such shortcomings and drawbacks stem from the fact that there is unidirectional data flow from the RDBMS to the MOLAP system. More specifically, atomic (raw) data is moved, in a single transfer, to the MOLAP system for aggregation, analysis and querying. Importantly, the aggregation results are external to the RDBMS. Thus, users of the RDBMS cannot directly view these results. Such results are accessible only from the MOLAP system. Because the MDD query processing logic in prior art MOLAP systems is separate from that of the RDBMS, users must procure rights to access to the MOLAP system and be instructed (and be careful to conform to such instructions) to access the MDD (or the RDBMS) under certain conditions. Such requirements can present security issues, highly undesirable for system administration. Satisfying such requirements is a costly and logistically cumbersome process. As a result, the widespread applicability of MOLAP systems has been limited.
Thus, there is a great need in the art for an improved mechanism for joining and aggregating data elements within a relational database management system, and for integrating the improved relational database management system into informational database systems (including the data warehouse and OLAP domains), while avoiding the shortcomings and drawbacks of prior art systems and methodologies.

Data aggregation server supporting rapid query response with sparse multi-dimensional data


The invention provides an electronic device that performs driving control of an electro-optical device by current driving at a high precision and reduces the number of components. The invention can include, along a data line to which pixel circuits are connected between a driving power source and a driver, a conversion transistor formed of a diode-connected transistor that is inserted between the driving power source and the pixel circuits. The conversion transistor can be used in common among the pixel circuits. Each pixel circuit can be formed of a driving transistor which forms a current mirror circuit with the conversion transistor, a control transistor driven by a scanning driver, for turning on and off the connection between the conversion transistor and the driving transistor, and a capacitive device for holding a voltage applied to the gate of the driving transistor by the control transistor. The driving transistor causes current corresponding to the voltage held by the capacitive device to flow into an organic electroluminescent device.

1. Field of Invention
The present invention relates to electronic devices, electro-optical devices, and electronic units having a current-driven device driven by electric current.
2. Description of Related Art
Currently, displays using liquid crystal have become quite popular as thin display apparatuses. This type of displays require lower power consumption and smaller spaces than CRT displays. Therefore, with the use of such display advantages, it is important to manufacture displays requiring lower power consumption and smaller spaces.
Some of the current displays use current-driven light-emitting devices instead of liquid crystal for display. Since the current-driven light-emitting devices emit light by themselves when current flows, unlike liquid crystal, the devices do not need backlight and can satisfy a market demand of low power consumption. In addition, the devices show superior display performances, such as a wide viewing angle and a high contrast. Among such current-driven light-emitting devices, electroluminescent devices are especially suited for displays because they can have a large area, a high definition, and full color. Further, among the electroluminescent devices, organic electroluminescent devices attract attentions because of their high quantum efficiency.
As such a display apparatus which uses an organic electroluminescent device, a display apparatus shown in FIG. 21 has been proposed. More specifically, in the display apparatus, pixel circuits are disposed correspondingly to the intersections of data lines X and scanning lines Y, the data lines are driven by a data driver 51, and the scanning lines Y are driven by the scanning driver 52.
The pixel circuit 55 is formed, for example, of two transistors 61 and 62, a capacitive device 63 for data storage, and an organic electroluminescent device 64, as shown in FIG. 22. A scanning line Y causes the transistor 61 to switch such that the capacitive device 63 holds a data signal sent from a data line X, as an electric charge. The electric charge held by the capacitive device 63 turns on the transistor 62, so that the amount of current corresponding to the data signal is supplied to the organic electroluminescent device 64. The organic electroluminescent device 64 emits light.
Current-driven devices, such as organic electroluminescent devices are more easily controlled by current than by a voltage. This results since the amount of current determines luminance in the organic electroluminescent devices, and therefore more accurate control is performed when current is used as a data signal.

System and method for manufacturing a electro-optical device


A rotary milking platform 1 has a deck 2, a circular upper beam 4 connected to and supporting the deck, a circular lower beam 6 and a series of carriages 5 connected end to end to form a ring between the beams. The platform is formed such that the upper beam 4 is arranged to rest and rotate on the ring of carriages 5 to rotate the deck 2. Each carriage has at least one carriage roller 10, and each roller 10 arranged to rotate on the lower beam 4. Each roller 10 also has a retention flange 11 at only one side. The flanges 11 of some of the rollers 10 are at or adjacent an inner side of the ring, and the flanges 11 of others of the rollers are at or adjacent an outer side of the ring. The rollers 10 of the ring are arranged such that at least one roller is oriented with its flange 11 on an opposite side to another of the flanged rollers immediately adjacent to it. The flanges prevent the carriages from moving off the lower beam 4 when the platform 1 is in use. Further, at least some of the carriages can be disconnected from the ring and swung laterally to be moved free of the beams 4, 6 for maintenance, repair or replacement.

It is known to locate dairy cows in bales on a rotary platform and to milk them as the platform turns through one revolution. Such platforms have an annular deck supported on at least one circular beam that rotates on rollers to move the platform with it. The beam takes the majority of the weight of the deck, milking equipment and cows, and that load is transmitted to the rollers. The weight can be substantial, particularly with platforms designed to take many cows and this can lead to deterioration of the rollers. Repair work, for example to replace the rollers, can be unduly inconvenient and cause economic loss through excessive downtime.

Waikato Milking Systems Limited Partnership