A gate of an NMOS transistor (N1) is connected to a memory terminal (Na) and a gate of an NMOS transistor (N2) is connected to a memory terminal (Nb). Sources of the NMOS transistors (N1, N2) are commonly connected to an internal terminal (Nc) and a ground potential (GND). Potentials of backgate terminals (BN1, BN2) of the NMOS transistors (N1, N2) are set to the ground potential (GND). When PMOS transistors (P1, P2) are in ON and OFF states, respectively, the memory terminal (Na) is brought into a logical xe2x80x9cHxe2x80x9d state and the memory terminal (Nb) remains a logical xe2x80x9cLxe2x80x9d state by a gate-leak current passing from the gate of the NMOS transistor (N2) to a semiconductor substrate. With such a structure, a semiconductor memory device having a memory cell structure to ensure reduction in cell area can be achieved.

1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a memory cell structure of a CMOS static RAM.
2. Description of the Background Art
FIG. 15 is a circuit diagram showing an exemplary memory cell (memory circuit) of multiport memory in the background art, e.g., disclosed in Japanese Patent Publication No. 58-27917 (FIG. 4).
As shown in FIG. 15, PMOS transistors PI1 and PI2 and NMOS transistors NI1 and NI2 constitute a memory cell storage unit 9. Sources of the PMOS transistors PI1 and PI2 are connected to a power supply VDD, and sources of the NMOS transistors NI1 and NI2 are connected to a ground potential GND. Drains of the PMOS transistor PI1 and the NMOS transistor NIl and gates of the PMOS transistor PI2 and the NMOS transistor NI2 are commonly connected to a memory terminal 21, and drains of the PMOS transistor PI2 and the NMOS transistor NI2 and gates of the PMOS transistor PI1 and the NMOS transistor NI1 are commonly connected to a memory terminal 22.
Specifically, a first CMOS inverter consisting of the PMOS transistor PI1 and the NMOS transistor NI1 and a second CMOS inverter consisting of the PMOS transistor PI2 and the NMOS transistor NI2 are cross-connected, to form the memory cell storage unit 9.
A drain of an access (NMOS) transistor NA1 is connected to the memory terminal 21. A bit line BL1 is connected to a source of an access transistor N1 and a word line WL1 is connected to a gate thereof. A drain of an access (NMOS) transistor NA2 is connected to the memory terminal 22. A bit line BL2 is connected to a source of an access transistor N2 and a word line WL2 is connected to a gate thereof.
Further, gates of NMOS transistors N21 and N22 are connected to the memory terminals 21 and 22, respectively, and sources thereof are commonly connected the ground potential GND. Sources of NMOS transistors N23 and N24 are connected to drains of the NMOS transistors N21 and N22, respectively. A read word line RWL1 and a read bit line RBL1 are connected to a gate and a drain of the NMOS transistor N23, respectively, and a read word line RWL2 and a read bit line RBL2 are connected to a gate and a drain of the NMOS transistor N24, respectively.
With respect to this structure, an operation of the memory cell storage unit 9 of multiport memory in the background art shown in FIG. 15 will be discussed. The memory terminals 21 and 22 have a complementary relation, and for example, when the memory terminal 21 is in a logical xe2x80x9cHxe2x80x9d state, the memory terminal 22 comes into a logical xe2x80x9cLxe2x80x9d state, being stable. Conversely, when the memory terminal 21 is in the logical xe2x80x9cLxe2x80x9d state, the memory terminal 22 comes into the logical xe2x80x9cHxe2x80x9d state, being stable. Thus, this structure can hold stored data of the two stable states, depending on whether the states of the memory terminals 21 and 22 are xe2x80x9cHxe2x80x9d or xe2x80x9cLxe2x80x9d.
If the memory terminal 21 is stable in the logical xe2x80x9cHxe2x80x9d state (in other words, the memory terminal 22 is in the logical xe2x80x9cLxe2x80x9d state), the PMOS transistor pI1 is in an ON state and the PMOS transistor PI2 is in an OFF state. Further, the NMOS transistor NI1 is in the OFF state and the NMOS transistor NI2 is in the ON state.
Next, a read/write operation using the word line WL1 (WL2) and the bit line BL1 (BL2) will be discussed. When the word line WL1 is in the xe2x80x9cLxe2x80x9d state, the transistor NA1 is in the OFF state, and the memory terminal 21 is electrically cut off with the bit line BL1 which corresponds to a read/write terminal for data. In other words, the stored data is held. When the word line WL1 is brought into the xe2x80x9cHxe2x80x9d state from the xe2x80x9cLxe2x80x9d state in response to an external signal, the transistor NA1 comes into the ON state from the OFF state and the memory terminal 21 electrically gets connected to the bit line BL1.
In this case, if the bit line BL1 is not externally driven, the data of the memory terminal 21 is propagated to the bit line BL1 through the transistor NA1 and read out. Thus performed is a read operation in the read/write operation.
On the other hand, when the word line WL1 is in the xe2x80x9cHxe2x80x9d state, if the bit line BL1 is strongly driven into the xe2x80x9cLxe2x80x9d or xe2x80x9cHxe2x80x9d state by a not-shown external circuit, the data of the bit line BL1 which is driven is propagated to the memory terminal 21 through the transistor NA1 and data of the memory terminal 21 is rewritten by the data of the bit line BL1. Thus performed is a write operation in the read/write operation.
When the word line WL1 is returned to the xe2x80x9cLxe2x80x9d state from the xe2x80x9cHxe2x80x9d state by an external signal, the memory terminal 21 comes into a hold-mode again. An operation of a port on the side of the transistor NA2 connected to the memory terminal 22 is the same as the above operation and therefore not discussed herein.
Next, a read operation using the read word line RWL1 (RWL2) and the read bit line RBL1 (RBL2) will be discussed. When the read word line RWL1 is in the xe2x80x9cLxe2x80x9d state, the NMOS transistor N23 is in the OFF state, and a read terminal m1 is electrically cut off with the read bit line RBL1. In an initial state, the read bit line RBL1 is precharged in the xe2x80x9cHxe2x80x9d state by a not-shown precharge circuit.
When the read word line RWL1 is brought into the xe2x80x9cHxe2x80x9d state from the xe2x80x9cLxe2x80x9d state in response to an external signal, the NMOS transistor N23 comes into the ON state from the OFF state and the memory terminal m1 electrically gets connected to the read bit line RBL1. If the hold-mode of the memory terminal 21 is xe2x80x9cHxe2x80x9d, the NMOS transistor N21 is in the ON state and the read bit line RBL1 electrically gets connected to the ground potential GND through the NMOS transistors N23 and N21. Therefore, the read bit line RBL1 is brought into the xe2x80x9cLxe2x80x9d state from the xe2x80x9cHxe2x80x9d state and data of xe2x80x9cLxe2x80x9d which is inverted data of the memory terminal 21 is read out.
Conversely, if the hold-mode of the memory terminal 21 is xe2x80x9cLxe2x80x9d, the NMOS transistor N21 is in the OFF state and the read bit line RBL1 is electrically cut off with the ground potential GND. Therefore, the read bit line RBL1 remains the xe2x80x9cHxe2x80x9d state and data of xe2x80x9cHxe2x80x9d which is inverted data of the memory terminal 21 is read out. When the read word line RWL1 is returned to the xe2x80x9cLxe2x80x9d state from the xe2x80x9cHxe2x80x9d state by an external signal, the memory terminal m1 gets cut off with the read bit line RBL1 again and the read bit line RBL1 is precharged into the xe2x80x9cHxe2x80x9d state again for the next read operation. Further, the read bit line RBL1 and the memory terminal 21 are not electrically connected to each other and no write operation is performed by the NMOS transistor N23. A read operation of a port on the side of the NMOS transistor N24 connected to another memory terminal m2 is the same as the above operation and therefore not discussed.
As discussed above, the memory cell including the memory cell storage unit 9 of multiport memory in the background art shown in FIG. 15 has a structure comprising two ports for reading and writing and two ports for only reading. FIG. 15 shows a four-port memory cell consisting of totally ten MOS transistors, i.e., eight NMOS transistors and two PMOS transistors.
The four-port memory cell is constituted of ten transistors as shown in FIG. 15, and in the structure of a multiport memory cell, like this example, the number of transistors constituting the multiport memory cell increases depending on the number of ports and this disadvantageously results in enlargement of cell area.
The present invention is directed to a semiconductor memory device. According to a first aspect of the present invention, the semiconductor memory device has a memory cell storage unit for data storage formed in a semiconductor substrate. The memory cell storage unit of the first aspect comprises first and second MIS transistors both of a first conductivity type, one electrode of the first MIS transistor and one electrode of the second MIS transistor being commonly connected to a first power supply, the other electrode of the first MIS transistor and the other electrode of the second MIS transistor serving as first and second memory terminals, respectively, the first and second memory terminals being connected to control electrodes of the second and first MIS transistors, respectively, and the first and second memory terminals each being set to a first power supply judged-potential that can be judged as a potential on the side of the first power supply when the first and second MIS transistors are in an ON state, and the memory cell storage unit of the first aspect further comprises third and fourth MIS transistors both of a second conductivity type, one electrode of the third MIS transistor and one electrode of the fourth MIS transistor being connected to each other, control electrodes of the third and fourth MIS transistors being connected to the first and second memory terminals, respectively, the other electrode of the third MIS transistor and the other electrode of the fourth MIS transistor being independent of the first and second memory terminals, and backgate terminals of the third and fourth MIS transistors for setting a substrate potential being connected to a second power supply, and in the semiconductor memory device of the first aspect, the first to fourth MIS transistors are provided so that a potential of the first memory terminal is stable at a second power supply judged-potential that can be judged as a potential on the side of the second power supply when the first MIS transistor is in an OFF state and a potential of the second memory terminal is stable at the second power supply judged-potential when the second MIS transistor is in the OFF state.
According to a second aspect of the present invention, the semiconductor memory device has a memory cell storage unit for data storage formed in a semiconductor substrate. The memory cell storage unit of the second aspect comprises first and second MIS transistors both of a first conductivity type, one electrode of the first MIS transistor and one electrode of the second MIS transistor being commonly connected to a first power supply, the other electrode of the first MIS transistor and the other electrode of the second MIS transistor serving as first and second memory terminals, respectively, the first and second memory terminals being connected to control electrodes of the second and first MIS transistors, respectively, and the first and second memory terminals each being set to a first power supply judged-potential that can be judged as a potential on the side of the first power supply when the first and second MIS transistors are in an ON state, and the memory cell storage unit of the second aspect further comprises third and fourth MIS transistors both of a second conductivity type, one electrode of the third MIS transistor and one electrode of the fourth MIS transistor not being fixed to any potential, control electrodes of the third and fourth MIS transistors being connected to the first and second memory terminals, respectively, the other electrode of the third MIS transistor and the other electrode of the fourth MIS transistor being connected to the second and first memory terminals, and backgate terminals of the third and fourth MIS transistors for setting a substrate potential being connected to a second power supply, and in the semiconductor memory device of the second aspect, the first to fourth MIS transistors are provided so that a potential of the first memory terminal is stable at a second power supply judged-potential that can be judged as a potential on the side of the second power supply when the first MIS transistor is in an OFF state and a potential of the second memory terminal is stable at the second power supply judged-potential when the second MIS transistor is in the OFF state.
According to a third aspect of the present invention, in the semiconductor memory device of the first aspect, assuming that currents flowing between one electrode and the other electrode of the first MIS transistor in the OFF state are first off-leak currents, currents flowing between one electrode and the other electrode of the second MIS transistor in the OFF state are second off-leak currents, currents flowing between the control electrode of the first MIS transistor and the semiconductor substrate are first gate-leak currents, currents flowing between the control electrode of the second MIS transistor and the semiconductor substrate are second gate-leak currents, currents flowing between the control electrode of the third MIS transistor and the semiconductor substrate are third gate-leak currents and currents flowing between the control electrode of the fourth MIS transistor and the semiconductor substrate are fourth gate-leak currents, the first to fourth MIS transistors are provided so that the amount of the third gate-leak currents is not less than the total amount of the first off-leak currents and the second gate-leak currents during a period until at least the potential of the first memory terminal becomes the second power supply judged-potential and the amount of the fourth gate-leak currents is not less than the total amount of the second off-leak currents and the first gate-leak currents during a period until at least the potential of the second memory terminal becomes the second power supply judged-potential.
According to a fourth aspect of the present invention, in the semiconductor memory device of the first aspect, one electrode of the third MIS transistor and one electrode of the fourth MIS transistor are set to a fixed potential.
According to a fifth aspect of the present invention, the semiconductor memory device of the first aspect further comprises a first access transistor having one electrode connected to an access memory terminal which is one of the first and second memory terminals, the other electrode connected to a write/read line and a control electrode connected to a write/read control line.
According to a sixth aspect of the present invention, in the semiconductor memory device of the fifth aspect, the write/read line includes first and second write/read lines, and the first access transistor includes a fifth MIS transistor having one electrode connected to the first memory terminal and the other electrode connected to the first write/read line; and a sixth MIS transistor having one electrode connected to the second memory terminal and the other electrode connected to the second write/read line.
According to a seventh aspect of the present invention, in the semiconductor memory device of the sixth aspect, the write/read control line includes first and second write/read control lines, the fifth MIS transistor has a control electrode connected to the first write/read control line, and the sixth MIS transistor has a control electrode connected to the second write/read control line.
According to an eighth aspect of the present invention, in the semiconductor memory device of the fourth aspect, the third and fourth MIS transistors include a MIS transistor which turns on/off when the potentials of the first and second memory terminals are the first/second power supply judged-potentials, respectively, and the other electrodes of the third and fourth MIS transistors are defined as first and second read terminals, respectively, and the semiconductor memory device of the eighth aspect further comprises: a second access transistor having one electrode connected to an access read terminal which is one of the first and second read terminals, the other electrode connected to a read only line and a control electrode connected to a read only control line.
According to a ninth aspect of the present invention, in the semiconductor memory device of the eighth aspect, the read only line includes first and second read only lines, and the second access transistor includes a seventh MIS transistor having one electrode connected to the first read terminal and the other electrode connected to the first read only line; and an eighth MIS transistor having one electrode connected to the second read terminal and the other electrode connected to the second read only line.
According to a tenth aspect of the present invention, in the semiconductor memory device of the ninth aspect, the read only control line includes first and second read only control lines, the seventh MIS transistor has a control electrode connected to the first read only control line, and the eighth MIS transistor has a control electrode connected to the second read only control line.
According to an eleventh aspect of the present invention, in the semiconductor memory device of the fourth aspect, the other electrodes of the third and fourth MIS transistors are defined as first and second read terminals, respectively, and the semiconductor memory device of the eleventh aspect further comprises: a seventh MIS transistor having one electrode connected to the first read terminal, the other electrode connected to a comparison judgment line and a control electrode connected to a first comparison judgment control line; and an eighth MIS transistor having one electrode connected to the second read terminal, the other electrode connected to the comparison judgment line and a control electrode connected to a second comparison judgment control line.
According to a twelfth aspect of the present invention, the semiconductor memory device of the first aspect further comprises: a seventh MIS transistor having one electrode connected to a comparison judgment line, the other electrode set to a fixed potential and a control electrode connected to one electrode of the third MIS transistor and one electrode of the fourth MIS transistor; and first and second comparison judgment control lines connected to the other electrodes of the third and fourth MIS transistors, respectively.
Preferably, in the semiconductor memory device of the fourth aspect, the fixed potential includes a potential of one of the first and second power supplies.
Preferably, in the semiconductor memory device of the first aspect, the first conductivity type includes a P-type conductivity, the second conductivity type includes an N-type conductivity, and a potential of the first power supply is higher than that of the second power supply.
Preferably, in the semiconductor memory device of the first aspect, the first conductivity type includes an N-type conductivity, the second conductivity type includes a P-type conductivity, and a potential of the first power supply is lower than that of the second power supply.
Preferably, in the semiconductor memory device of the second aspect, one electrode of the third MIS transistor and one electrode of the fourth MIS transistor are connected to each other.
Preferably, in the semiconductor memory device of the second aspect, one electrode and the other electrode of the third MIS transistor are connected to each other, and one electrode and the other electrode of the fourth MIS transistor are connected to each other.
Preferably, in the semiconductor memory device of the second aspect, one electrode of the third MIS transistor and one electrode of the fourth MIS transistor are in a floating state.
Preferably, in the semiconductor memory device of the second aspect, the first conductivity type includes a P-type conductivity, the second conductivity type includes an N-type conductivity, and a potential of the first power supply is higher than that of the second power supply.
Preferably, in The semiconductor memory device of the second aspect, the first conductivity type includes an N-type conductivity, the second conductivity type includes a P-type conductivity, and a potential of the first power supply is lower than that of the second power supply.
In the semiconductor memory device of the first aspect of the present invention, the first to fourth MIS transistors are provided so that the potential of the first memory terminal can be stable at the second power supply judged-potential when the first MIS transistor is in the OFF state and the potential of the second memory terminal can be stable at the second power supply judged-potential when the second MIS transistor is in the OFF state.
Accordingly, when either one of the first and second MIS transistors is made the ON state and the other is made the OFF state, one of the first and second memory terminals is set to the first power supply judged-potential through the first or second MIS transistor which is in the ON state and the other is set to the second power supply judged-potential as discussed above, whereby information storage is performed between the first and second memory terminals.
As a result, since the memory cell storage unit needs a cross connection of only the first and second MIS transistors and that allows a simple layout, a semiconductor memory device having a memory cell structure to ensure reduction in cell area can be provided.
According to the second aspect of the present invention, a semiconductor memory device having a memory cell structure which ensures reduction in cell area, like that of the first aspect, can be achieved.
Further, since the other electrodes of the third and fourth MIS transistors are connected to the second and first memory terminals, respectively, it is possible to improve the soft-error resistance by addition of capacitance between the other electrodes and the control electrodes of the third and fourth MIS transistors to the second and first memory terminals.
In the semiconductor memory device of the third aspect of the present invention, by providing the third and fourth MIS transistors so that the third and fourth gate-leak currents can satisfy the above condition, the potentials of the first and second memory terminals are always set to the second power supply judged-potential when the first and second MIS transistors are in the OFF state, whereby information storage can be performed between the first and second memory terminals.
In the semiconductor memory device of the fourth aspect of the present invention, if the third and fourth MIS transistors are set to turn on/off when the potentials of the first and second memory terminals are set to the first/second power supply judged-potential by setting one electrode of the third MIS transistor and one electrode of the fourth MIS transistor are set to fixed potentials, the stored content in the memory cell storage unit can be read out by utilizing whether the potential obtained by the other electrodes of the third and fourth MIS transistors are fixed potentials or not.
The semiconductor memory device of the fifth aspect of the present invention can perform a write operation by turning on the first access transistor by the write/read control line to set the potential of the access memory terminal while setting the potential of the write/read line and a read operation by turning on the first access transistor by the write/read control line to read the potential of the access memory terminal out to the write/read line.
The semiconductor memory device of the sixth aspect of the present invention can perform write/read operations on the respective two ports by utilizing the fifth and sixth MIS transistors. Further, a write operation is performed by setting such data on the first and second write/read lines as to have a complementary relation and a read operation is performed on the basis of the potential difference between the first and second write/read lines, and therefore a stable write/read operation can be achieved.
The semiconductor memory device of the seventh aspect of the present invention can perform write/read operations independent of each other on the respective two ports by the first and second write/read control lines.
In the semiconductor memory device of the eighth aspect of the present invention, since the potential of the read only line is set to a potential different from the fixed potential and thereafter the second access transistor is turned on by the read only line, a read operation can be performed on the basis of whether the potential of the read only line is the fixed potential or not.
The semiconductor memory device of the ninth aspect of the present invention can perform write/read operations on the respective two ports by utilizing the seventh and eighth MIS transistors. Further, a read operation is performed on the basis of the potential difference between the first and second read only lines. Therefore, a stable read operation can be achieved.
The semiconductor memory device of the tenth aspect of the present invention can perform write/read operations independent of each other on the respective two ports by the first and second read only control lines.
In the semiconductor memory device of the eleventh aspect of the present invention, since the potential of the comparison judgment line is set to a potential different from the fixed potential and thereafter one of the seventh and eighth MIS transistors is made the ON state and the other is made the OFF state by the first and second comparison judgment control lines, a comparison operation for checking if the data- stored in the memory cell storage unit and the search data match each other on the basis of whether the potential of the comparison judgment line is the fixed potential or not.
In the semiconductor memory device of the twelfth aspect of the present invention, since the potential of the comparison judgment line is set to a potential different from the fixed potential and thereafter one of the first and second comparison judgment control lines and the other are set to the potentials to turn on and off the seventh MIS transistor, respectively, a comparison operation for checking if the data stored in the memory cell storage unit and the search data match each other on the basis of whether the potential of the comparison judgment line is the fixed potential or not.
An object of the present invention is to provide a semiconductor memory device having a memory cell structure which ensures reduction in cell area.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


A method for effecting synchronous pulse generation for use in serial communications is provided. The method includes the steps of generating a difference signal representing a signal level difference between at least two data stream signals; providing a clock signal; providing a counter, defining a sample count value of the counter; incrementing the counter in relation to the clock signal; and determining whether a current count value of the counter corresponds to the sample count value. If the current count value corresponds to the sample count value, then the method performs a step of generating a synchronous pulse. If the current count value does not correspond to the sample count value, then the method performs a step of determining whether a signal level of said difference signal has changed, and if the signal level of the difference signal has changed then performing a step of ignoring further changes in the signal level of the difference signal until the current count value of the counter corresponds to the sample count value at which time the step of generating the synchronous pulse is repeated.

1. Field of the Invention
The present invention relates to serial communications, and, more particularly, to a method and apparatus for effecting synchronous pulse generation for use in serial communications.
2. Description of the Related Art
A Universal Serial Bus (hereinafter referred to as "USB") permits a variety of peripheral devices, such as a printer or scanner, to be connected to a generic port in a host computer. During communication between a host computer and peripheral device via a USB, data is transmitted over the bus, but the USB does not transmit a clock for synchronization. Therefore, it is necessary for a USB receiver to have some mechanism to synchronize itself with the incoming data. The USB Specification (version 1.1) describes methods of encoding transmitted data for keeping a receiving device synchronized with the incoming data. Each packet transmitted on USB begins with a synchronization field to allow the receiver to synchronize with the transmitted data. The receiver is kept in synchronization with the transmitter by the non return to zero invert (hereinafter referred to as "NRZI") encoding and by bitstuffing if the NRZI encoding does not signal a transition after 6 bits.
Current USB systems utilize multiple clocks, one of which is a 12 MHz clock that is synchronized to the data on the USB. For example, U.S. Pat. No. 5,910,742 issued to Snyder, et al. (hereinafter referred to as "Snyder") discloses a circuit and method for synchronizing a data signal to one of a plurality of clocks. Snyder discloses using two pulses generated by the transmission of data to select one of many clocks to use for recovering the transmitted data. In Snyder, a clock generator is configured to generate a plurality of clocks and/or a logic circuit is configured to select the clock signal having the closest timing in relationship with the data signal.
Typically, USB systems include a USB controller for synchronizing the timing relationships by relying on feedback to synchronize incoming data. A USB controller in a typical system uses a digital phase-locked loop hereinafter referred to as "DPLL") circuit that runs on a 48 MHz clock. The USB data signals, commonly referred to as D+ and D−, are inputs into the DPLL and the DPLL outputs a 12 MHz clock signal synchronized to the USB data. The USB controller uses the DPLL clock signal to extract the bit values of the USB data. In many systems, the clock synchronized with the USB is unsuitable for other logic that interfaces with the USB because the clock rate is slower and the clock frequency or period varies. For example, the 48 MHz clock signal may be divided to generate a 24 MHz clock signal for a processor or other logic. Thus, a separate clock is used for the processor and the other logic in those systems. Multiple clocks require additional logic for synchronization between the clock domains and multiple clocks complicate the testing of the system logic.
One method and apparatus for synchronizing circuitry between multiple clock timing domains, such as a USB, is disclosed in U.S. Pat. No. 5,923,193 issued to Bloch, et al. (hereinafter referred to as "Bloch"). In FIG. 2 of Bloch a timing diagram illustrates a source clock, a fixed clock and a latch signal. Bloch discloses that the source clock signal has a 48 MHz frequency and that the clock divider circuit divides the source clock signal frequency to produce a 12 MHz clock signal. It is important to note that Bloch discloses passing the arriving data signal through a DPLL, and thus, Bloch discloses at least two clock domains, the system clock and the DPLL clock. Once created, these two clock domains are delayed in such a way that they are staggered slightly aiding in decoding the incoming data. A latching pulse, created using the internal 48 MHz clock, pulses every four edges of the 48 MHz clock. These signals along with a latching scheme are used to decode the incoming data.
Attempts have been made to optimize the flow of isochronous data and clock rate information over a USB, such as that disclosed in U.S. Pat. No. 5,958,027 issued to Gulick (hereinafter referred to as "Gulick"). In Gulick, the USB conveys a control signal to a data producer to increase or decrease the clock rate of the data producer based upon the level of data within the buffer of the USB. Thus, in Gulick the clock rate of the data producer or data transmitter is changed.
What is needed in the art is a method and apparatus for effecting synchronous pulse generation for serial communications using a simplified hardware configuration.

Method and apparatus for effecting synchronous pulse generation for use in serial communications


A method and apparatus for automatically configuring a system based on a user's monitored system interaction and preferred system access times updates a user profile corresponding to the user based at least in part on the monitored user interaction with the system. Preferred system access times of the user are identified based at least in part on the user profile, and the system is automatically configured based at least in part on the user profile and the user's preferred system access times.

1. Field of the Invention
The present invention relates to the field of entertainment systems and, in particular, to a method and apparatus for automatically configuring a system based on a user's monitored system interaction and preferred system access times.
2. Background Information
Numerous advances have been made in recent years in the field of entertainment systems. For example, programming guides are now prevalent on many cable systems throughout the country. In one embodiment, these programming guides are offered on a particular channel within the cable broadcast, and provide programming information for the next several hours. More advanced ones of these prior art systems may allow the user to interact with the program guide to manually select a particular program to record or view.
Another example of advances in entertainment systems has been the advent of parental control, wherein a person may "lock out" or require a password for channels that may be unsuitable for certain members of the family. Equally impressive advances have been made in audio devices, video recorders/playback devices, etc. A number of these devices allow a user to manually program the device to record a program given appropriate information regarding the program (channel, date, start time, end time, etc.). Other current systems allow a user to manually "add" and "erase" channels and thereby generate a preferred "channel surfing" order. For example, the user may erase channels 3 and 4 in order to pass directly from channel 2 to channel 5 when channel surfing. However, with these systems the channel surfing order must be manually programmed by a user and must be manually re-programmed by the next user if he or she desires a different order. Typical prior art entertainment systems are not capable of automatically and dynamically configuring the entertainment system in accordance with a user's monitored system interaction (e.g., the channels a user watches and the times of day he or she watches them). Furthermore, typical prior art entertainment systems are not capable of altering their configuration based on what times (e.g., 5:00 pm-8:00 pm) the system is accessed.
Thus, a need exists for a method and apparatus for automatically configuring a system based on a user's monitored system interaction and preferred system access times.

Method and apparatus for automatically configuring a system based on a user's monitored system interaction and preferred system access times


Method of treatment of environmentally hazardous waste material and recovering MgCl.sub.2 brine, based on dissolving of the waste material in water and hydrochloric acid and simultaneous removal of ammonia at elevated temperatures, destruction of residual aqueous ammonia and removal of Mn, where the material is pre-treated in a special mixing unit adding water to provide a slurry and where hydrogen and other evolved gases are continuously diluted.

1. Field of the Invention
The present invention relates to a method of treatment of an environmentally hazardous waste material from production of magnesium metal, and also an apparatus for such treatment.
2. Description of the Related Art
The actual waste material from electrolyic production of Mg metal and sludge deposit from (foundry) furnaces for refining of magnesium, being a solidified mixture of chlorides, oxides (salts) and Mg metal, represents a hazardous waste deposit. The present practice of free deposits in open air will not be tolerated by regulation in most countries.
Presently known methods of "treatment" of such waste material are mainly limited to the recovery of entrapped organic particles with free deposits of the remaining salts or return of salts to the source of the Mg containing raw material (salt lakes).

Method for treatment of waste material and recovering MgCl.sub.2


A multi-channel, dual-band, radio frequency (RF) transmit/receive (T/R) module, for an active electronically scanned array, is provided. The module includes a compact, RF manifold connector and at least four T/R channels. Each of the T/R channels includes a notch radiator, a diplexer coupled to the notch radiator, a power amplifier, including at least one dual-band gain stage, coupled to the notch radiator, a low noise amplifier, including at least one lower-band gain stage and at least one upper-band gain stage, coupled to the diplexer, and a T/R cell, including a phase shifter, a signal attenuator and at least one dual-band gain stage, coupled to the power amplifier, the low noise amplifier and the manifold connector.

1. Technical Field
The present invention relates to radar systems. More particularly, the present invention relates to transmit/receive modules in compact packages.
2. Description of the Background Art
A variety of technical problems face one looking to equip an airplane with Ku and Ka band radars (for simplicity, K band radars are referred to with lower case letters, not the official subscripts). Modern radars systems are often implemented as active electronically scanned arrays with hundreds of transmit/receive modules aligned in an array. One advantage of an active electronically scanned array is that it can perform radar scans without physically turning the radar array. This is accomplished by altering the phase of the transmitted radars. By synchronizing the phases of each of the transmit/receive modules, the beam transmitted points in a different direction. However, in order to change the direction of the radar beam (i.e., the main lobe) the transmitted radars must be packed close enough together to work in unison.
Ka band radar, short for "K above," is transmitted at approximately 18-40 GHz. Because such high frequencies are being used, the transmit/receive modules must be packed very tightly. In an active electronically scanned array, the lattice spacing must be approximately half of the wavelength of the highest frequency used. Ka band radar requires five elements per inch. Systems operating in the X band, e.g. 10 GHz, had ten times as much area in which to place transmit/receive modules. The demanding space requirements were too small for the current size of transmit/receive modules.
In addition to the size of the modules, a designer must also contend with the size of the connections to and from modules. Prior art designs require bulky connectors connecting a module to a radiating element. Prior art designs also require a connector from the module to a manifold interconnect. The inventors discovered that current connectors did not meet the height requirements of a Ka band radar grid.
These issues are compounded where a plane needed both Ku and Ka band radars. The module must be small enough to be able to create an effective array of Ka band radar, but still make room for both Ka band radar technology and Ku band radar technology. Because these two bands are at different frequencies, they must be transmitted and received separately. At the same time, the circuitry for both must be compact enough that it can fit into the Ka space requirements.

Dual band quadpack transmit/receive module


The invention is a lumbar supported carrier for oxygen tanks comprising a main belt portion and a pouch for the tank. The belt has a shoulder strap for stabilizing the belt and tank extending over the shoulder and diagonally across the body. The shoulder strap comes with a series of smaller straps for securing the hose or cannula that is used in connection with the tank. The pouch is attachable to the belt by means of straps and has a drawstring with cord lock for securing the tank within the pouch. In addition, the pouch has separate D rings that allow the pouch to be attached to the shoulder strap and used separately from the belt. The belt has a padded portion to fit the curve of the lumbar area of the human spine.

There are many people nowadays who need to transport a secondary supply of oxygen for their needs. Such supplies take the form of an oxygen tank with related features for distributing the oxygen e.g. a face mask and a cannula to bring the oxygen from the tank to the nostrils of the patient. Such tanks can be quite heavy to carry around and may result in the patient doing permanent damage to his or her back or shoulder.
The invention herein described is believed to help those patients better able to transport their supply of oxygen by distributing the weight of the oxygen tank more evenly upon the body and in particular to allow the pelvic region of the body to support the majority of the weight of the bottle. The back of the belt is padded to further facilitate the resting of the tank against the user's back. A pouch feature is used in connection with the belt and has its own means for attaching to the belt. The pouch includes a draw string to further secure the tank in the pouch.
Additional features of the invention allow for adjustment of the strap that accompanies the support as well as allowing the user to detach the pouch portion of the apparatus from the belt and be used separately by attaching the pouch to the shoulder strap that is detached from the belt. Other features allow the hose to be attached to several places on the shoulder strap and prevent it from being caught on small objects. After removing the belt with the tank, the tank may easily be rested in an upright position to allow use of the oxygen while having the tank sitting beside the user. The belt itself is also adjustable to accommodate the different waist sizes of the users.


Disclosed is a protective hood for a wood-milling machine to cover a milling spindle which projects vertically out of a horizontal machine table. The protective hood is formed of two side walls connected to one another by a cover and a rear wall, and a front, vertically adjustable protective shield. The protective hood has a connection stub for an extraction device and can be attached adjustably to the machine table. A holding member for the removable attachment of a stop plate is releasably attached to each of the two side walls of the protective hood. In this way, the protective hood is permanently available as a basic element, so that when changing from curved milling to milling against a stop, it is easy to fit the stop plates.

The invention relates to a protective hood for wood-milling machines.
A protective hood of this nature forms the subject matter of EP-B 558 692. It is for machining curved workpieces, and utilizes a guide element which may be a curve-milling stop or an approach ring in combination with an approach strip. If straight workpieces are to be machined on the stop, for example with the aid of stop plates, which can be adjusted with respect to one another, of an xe2x80x9cintegral stopxe2x80x9d as described in EP-B 215 040, it is necessary to remove the protective hood for the curve milling and to fit a protective hood on which the stop plates can be arranged on the machine table. This change-over work is not only time-consuming, but, due to the considerable weight of the devices which have to be moved, generally also requires two people or appropriate lifting and cutting units.
An object of the present invention is to provide a protective hood for wood-milling machines which is designed in such a way that it can remain on the machine table as a universal basic element and can be used both for the installation of stop plates and for curve-milling work.
In a protective hood of the generic type the preamble of patent this object is obtained by a holding member for the movable attachment of a stop plate arranged on each of the two side walls of the protective hood, which holding member is formed of a side limb, releaseably attached to the side wall, and a front limb, which is at right angles to the side limb and bears the stop plate. The term covers not only the preferred option of removing the holding members altogether when required, but also the alternative of, for example, pivoting these members backward or sliding them upward, in order to provide sufficient space in the lower region of the protective hood to mill annular or curved workpieces. To be able to change from milling on the stop to curve milling, it is in any event sufficient to release the two holding members bearing the stop plates in accordance with the invention, so that the curved machining of wooden workpieces is possible without restrictions.
In this context, it is advantageous if the side limb is horizontally adjustable relative to the side wall of the protective hood, the two side walls of which engage in a horizontally displaceable manner in two parallel guide rails which are attached to the machine table. In this way, each of the two side walls of the protective hood can be adjustably attached to the guide rail by means of a clamping member.
According to the invention, it is possible to adjust either the entire unit, protective hood and stop plates, forward or backward via an adjustment mechanism or to adjust only one of the two stop plates on the protective hood relative to the other stop plate. The adjustment mechanism may be provided either on the protective hood or on the holding member.
The adjustment mechanisms may have adjustment spindles which can be actuated manually, and may be arranged in box-like housings which form the side limbs of the two holding members. In one of the two holding members, the adjustment mechanism is designed in such a way that it is used for the horizontal displacement of the entire unit, comprising the basic device (protective hood) and the two fitted stop plates, while the adjustment device in the other holding member is provided for relative displacement between the latter and the protective hood.
In an alternative embodiment, the two adjustment mechanisms are accommodated in the hollow side walls of the protective hood and are driven synchronously by two electric motors which displace the protective hood and any fitted stop plates together in the horizontal direction. By synchronously activating the two electric motors, it is possible to bring about easy, non-jamming movement of the protective hood, with the additional possibility of inputting the desired parameters via a keyboard using suitable control programs. In this solution, the relative displacement between one of the two stop plates and the protective hood is preferably carried out by a further electric motor which is accommodated in the side limb of the corresponding holding member.
In a refinement of this embodiment, it is particularly advantageous, in order to clamp the protective hood securely on the guide rails, to provide, in both side walls, a motor which drives a vertical spindle which acts as a clamping member. In this way, it is possible to input the desired parameters at the keyboard, so that not only the adjustment of the protective hood and the stop plate, but also the fixing of the protective hood in the working position reached, are carried out automatically.
According to another feature of the invention, the cover comprises a fixed support surface which is connected to the rear wall and on which a preferably transparent cover flap is articulatedly mounted via a hinge, which flap bears a pull-out extension plate with a rim which projects downward and on the front side of which the protective shield is arranged in a vertically adjustable manner. In this way, by pivoting up the cover flap, unimpeded access to the interior of the protective hood is created, in order, for example, to exchange the milling tool.
According to a further feature of the invention, the support surface has means for attaching a bearing block for the pivot arm of a protection and pressure device, for example in accordance with EP-B 637 276.
The various features of novelty which characterize the invention are pointed out with particularity in the claims appended to and forming a part of this specification. For a better understanding of the invention, its operating advantages and specific objects obtained by its use, reference should be had to the accompanying drawings and descriptive matter in which there is illustrated and described a preferred embodiment of the invention.

Protective hood for wood milling machines


The present invention discloses a personal computer that has circuit elements enclosed in a light transmissible case. The personal computer further includes a visible light enclosed in the light-transmissible case for providing indication of various functional statuses of the personal computer through the light transmissible case. In a preferred embodiment, the personal computer further includes a light controller for controlling the visible light for providing a plurality of visible light signals for indicating various functional statuses of the personal computer. In another preferred embodiment, the light controller further includes a light intensity controller for controlling an intensity of the visible light for indicating various functional statuses of the personal computer. In another preferred embodiment, the light controller further includes a light flash-pattern controller for controlling a flash-pattern of the visible light for indicating various functional statuses of the personal computer. In another preferred embodiment, the light controller further includes a color controller for controlling a color of the visible light for indicating various functional statuses of the personal computer.

1. Field of the Invention
This invention relates generally to status display and indication of electronic devices, computers and different types of data handling systems. More particularly, this invention relates to an improved status display configuration for showing the functional status or operational conditions of electronic devices or data handling systems such as a personal computer by making use of visible lights through light transmissible enclosure cases.
2. Description of the Prior Art
Due to the facts that electronic circuit elements either supported on a printed circuit board (PCB) or packaged as individual components are generally enclosed in a housing case made of non-transparent opaque materials, the operational conditions or functional statuses of these circuit elements are not directly shown. Because the enclosure case that is used for housing the circuits is not light transmissible, it is not feasible to provide visible light from the board or the components as indication signals. Typically, special light indications must be provided outside of the housing case for a user to see the operational conditions or functional statuses of a system. Electric wire connections and special lights must be designed and particularly arranged for making such indications possible. Simple examples of such indication are light indication to show the charge status of a rechargeable battery of a cellular phone or a flashing light to show an incoming voice message has been received by a phone answering machine.
However, as the data processing electronic devices, e.g., a personal digital assistant (PDA) and personal computer (PC), become more integrated with daily life, a need arises to provide more direct visible indications to inform a user of an operational condition or functional status of such devices. Furthermore, when these type of indication are not provided for the circuit elements supported on a board or formed as components, the diagnostic and repair operations of the system malfunctions become more complex and time consuming. Due to the fact that non-transparent enclosure cases are commonly employed for housing and protecting the electronic devices, the limitations as now encountered by conventional electronic devices or computers cannot be easily overcome. Therefore, as an electronic device or computer is manufactured and provided to users as xe2x80x9cnon-transparent dark boxxe2x80x9d, the operational conditions or functional statuses of such device become a xe2x80x9cblack boxxe2x80x9d to most common users. Only specialists apply special diagnostic or analytical instruments can determine the operational conditions and functional statuses of the circuits supported on a PCB or packaged as electronic components.
Therefore, an improved display configuration must be provided to more directly show the operational conditions and functional statuses of the circuit elements supported on a printed circuit board or packaged as components. It is desirable that such display configuration would further provide reminder or warning signals for user to perform timely maintenance or repair functions. It is further desirable that such display configuration will provide data reception statuses to enhance network communication for Internet applications.
It is therefore an object of the present invention to provide a novel display configuration for directly showing the operational conditions and functional statuses by visible signals transmitted from circuits on a board or components. Direct visible signals can provide additional information to aid in system diagnostic and repair operations or for upgrade and to perform upgrade or maintenance functions. Light transmissible housing cases are employed and indication lights are implemented to provide these functions such that the aforementioned limitations and difficulties encountered in the prior art can be overcome.
Specifically, it is an object of the present invention to provide a novel display configuration for directly showing the board level and component operational conditions and functional statuses. Light transmissible cases are employed and indication light signals for showing conditions and statuses are implemented such that a user is provided with more direct information related to the situations of the entire system.
Another object of the present invention is to provide a novel display configuration for directly showing the operational conditions and functional statuses of a networked computer. Light transmissible cases are employed and indication light signals for showing conditions and statuses of data transmission and reception are implemented such that a user is provided with more direct information related to the situations of the networked computers.
Another object of the present invention is to provide a novel display configuration for directly showing the operational conditions and functional statuses of electronic devices. Light transmissible cases are employed and indication light signals for showing conditions and statuses are disposed on circuit elements of the electronic device inside the light transmissible cases such that a user is provided with more direct information related to the situations of the electronic device.
Briefly, in a preferred embodiment, the present invention discloses a personal computer with circuit elements enclosed in a light transmissible case. The personal computer further includes a visible light enclosed in the light-transmissible case for providing indication of various functional statuses of the personal computer through the light transmissible case. In a preferred embodiment, the personal computer further includes a light control means for controlling the visible light for providing a plurality of visible light signals for indicating various functional statuses of the personal computer. In another preferred embodiment, the light control means further includes a light intensity control means for controlling an intensity of the visible light for indicating various functional statuses of the personal computer. In another preferred embodiment, the light control means further includes a light flash-pattern control means for controlling a flash-pattern of the visible light for indicating various functional statuses of the personal computer. In another preferred embodiment, the light control means further includes a color control means for controlling a color of the visible light for indicating various functional statuses of the personal computer. In another preferred embodiment, the personal computer further includes a printed circuit board (PCB) for supporting the circuit elements enclosed in the light-transmissible case and the visible light is disposed on the PCB for providing indication of various functional statuses of the personal computer through the light transmissible case. In another preferred embodiment, the personal computer further includes a packaged electronic component enclosed in the light-transmissible case and the visible light is disposed on the packaged electronic component for providing indication of various functional statuses of the personal computer through the light transmissible case.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment which is illustrated in the various drawing figures.

Light indication showing functional status or operational condition through light-transmissible enclosure case


The present invention provides an epitaxial imprinting process for fabricating a hybrid substrate that includes a bottom semiconductor layer; a continuous buried insulating layer present atop said bottom semiconductor layer; and a top semiconductor layer present on said continuous buried insulating layer, wherein said top semiconductor layer includes separate planar semiconductor regions that have different crystal orientations, said separate planar semiconductor regions are isolated from each other. The epitaxial printing process of the present invention utilizing epitaxial growth, wafer bonding and a recrystallization anneal.

In present semiconductor technology, CMOS devices, such as nFETs or pFETs, are typically fabricated upon semiconductor wafers, such as Si, that have a single crystal orientation. The term "FET" is used in the present application to denote a field effect transistor; the lower case 'n' and 'p' denote the conductivity of the transistor. In particular, most of today's semiconductor devices are built upon Si having a (100) crystal plane.
Electrons are known to have a high mobility for a (100) Si surface orientation, but holes are known to have a high mobility for a (110) surface orientation. That is, hole mobility values on (100) Si are roughly 2×–4× lower than the corresponding electron mobility for this crystallographic orientation. To compensate for this discrepancy, pFETs are typically designed with larger widths in order to balance pull-up currents against the nFET pull-down currents and achieve uniform circuit switching. pFETs having larger widths are undesirable since they take up a significant amount of chip area.
On the other hand, hole mobility on (110) Si is 2× higher than on (100) Si; therefore, pFETs formed on a (110) surface will exhibit significantly higher drive currents than pFETs formed on a (100) surface. Unfortunately, electron mobility on (110) Si surfaces is significantly degraded compared to (100) Si surfaces.
As can be deduced from the above, the (110) Si surface is optimal for pFET devices because of excellent hole mobility, yet such a crystal orientation is completely inappropriate for nFET devices. Instead, the (100) Si surface is optimal for nFET devices since that crystal orientation favors electron mobility.
Hybrid oriented substrates having planar surfaces with different crystallographic orientation have recently been developed. See, for example, U.S. patent application Ser. No. 10/250,241, filed Jun. 23, 2003. Additionally, hybrid-orientated metal oxide semiconductor field effect transistors (MOSFETs) have recently demonstrated significantly higher circuit performance at the 90 nm technology node. As discussed above, the electron mobility and hole mobility can be optimized independently by placing the nFET on a (100) surface and the pFET on a (110) surface.
In such technologies, the nFET is formed into a (100) SOI region of the hybrid substrate, while the pFET is formed into a (110) bulk-epi region. As is known to those skilled in the art, SOI devices generally have higher performance than bulk-like devices due to less parasitic capacitance. Hence, it is desirable to provide a semiconductor substrate that has separate SOI crystal orientations for both nFETs and pFETs.
In view of the above, there is a need to provide a hybrid substrate that has separate SOI regions with different crystal orientations.

International Business Machines Corporation


A light-emitting device includes a semiconductor light-emitting element arranged on a substrate having internal wiring, a reflector arranged around the semiconductor light-emitting element, and a light-emitting portion, filled in the reflector, having a phosphor which emits visible light when excited by light from the semiconductor light-emitting element. Electrical conduction to the light-emitting element is obtained via the internal wiring of the substrate and the reflector.

A light emitting diode (LED) is a semiconductor element converting electrical energy into light such as ultraviolet light, visible light or the like, and has advantages that it has a long life and high reliability, and when the LED is used as a light source, the time which exchanges lamps can be saved. A light-emitting device (LED lamp) having an LED element sealed with, for example, a transparent resin is used extensively as a component part for various types of displays such as portable communication devices, PC peripheral devices, office automation equipment, home electric appliances, signal equipment, various types of switches, backlight type display panels, and the like.
For example, the light-emitting device using the LED element has a structure that the LED element is fixed onto a substrate and each of electrodes of the LED element is electrically connected to terminal on the substrate via a conductive wire, respectively. In addition, a reflector for reflecting light irradiated from the LED element is disposed around the LED element. For example, a light-emitting layer having phosphor particles is filled in the reflector (see, for example, Reference 1).
The color tone of light emitted from the light-emitting device is not limited to the light emission wavelength of the LED element, and visible light ranging from blue to red can be obtained depending on usages by, for example, a phosphor dispersed into the light-emitting layer. Especially, a white light-emitting type light-emitting device is useful as a backlight for the liquid crystal display of portable communication devices and PCs (see, for example, Reference 2).
The conventional light-emitting device having the LED element and the reflector disposed on the substrate has a drawback that emission luminance tends to become low. In other words, since the conductive wires extended from the electrodes of the LED element are connected to the terminals on the substrate, the reflector cannot be approached enough to the periphery of the LED element. Therefore, there is a space enough for disposition of the conductive wires between the reflector and the LED element. Light irradiated from the LED element is diffused needlessly within the light-emitting layer before it reaches the reflector and not irradiated enough to the reflector, so that the emission luminance becomes low.
To avoid the lowering of the emission luminance, there is, for example, a method that the conductive wires extended from the LED element are connected to the terminals on the substrate, which are located outside of the reflector, and the space between the LED element and the reflector is decreased. But, since this method forms a connection point of the conductive wire outside of the reflector, the same portion cannot be used effectively for other usages. In addition, since the conductive wires must be disposed over the top of the reflector, the conductive wires become long, and the productivity and reliability of the light-emitting device are lowered.
Meanwhile, as a method that unnecessary diffusion of light within the light-emitting layer is suppressed while the distance between the LED element and the reflector is remained as it is, the amount of a phosphor contained in the light-emitting layer may be decreased. But, such a method causes further lowering of the emission luminance because the content of the phosphor is decreased.
[Reference 1]JP-A 2002-198573 (KOKAI)[Reference 2]JP-A 2003-160785 (KOKAI)

Light-emitting device, backlight using same, and liquid crystal display


Nanometer sized particles containing titanium and platinum are prepared by a sonochemical process. Compounds of the metals are dissolved, suspended, or diluted in a low vapor pressure liquid medium, preferably at a sub-ambient temperature. A reducing gas is bubbled through the liquid as it is subjected to cavitation to affect the reductive decomposition of the metal compounds. Titanium and platinum are co-precipitated in very small particles.

A challenge to the development of economically viable polymer electrolyte membrane (PEM)-containing fuel cells for automotive applications, is the high cost of platinum currently required in the cathode for the catalytic reduction of oxygen. Various platinum alloy catalysts have exhibited improved mass activities for oxygen reduction and platinum-titanium alloy catalysts have shown some of the more promising activities. In addition, the titanium component of the catalyst is expected to be reasonably stable under the acidic conditions encountered in a PEM fuel cell.
To be effective in a fuel cell, platinum alloy catalysts must be prepared as nanosize particles. Current methods of platinum-titanium catalyst synthesis require several wet chemical steps, culminating in a high-temperature reduction. This latter step is not ideal for obtaining nanoparticles since sintering of both metals occurs at the temperatures required to reduce titanium. A better method for the preparation of nanometer size platinum-titanium alloy particles is needed.

Preparing nanosize platinum-titanium alloys


A safety closure providing a top wall, an annular outer wall depending downwardly from an outer periphery of the top wall, an annular inner wall depending downwardly from an underside surface of the top wall, and, at least one locking lug integrally molded with the outer wall, whereby downward displacement of the top wall causes outward displacement of the at least one locking lug.

1. Technical Field of the Invention
The present invention relates to safety closures for use on containers. More particularly, the present invention relates to a safety closure for use on a container wherein the safety closure and the container are provided with cooperating means to inhibit access thereto.
2. Description of the Related Art
It is often desirable to provide a safety closure for use on a container wherein the safety closure and the container are respectively provided with cooperating locking means to inhibit access thereto by individuals of tender age. It is well-known in the prior art to threadingly fit a safety closure upon a neck portion of a container, wherein engageable lugs project inwardly from opposing mating surfaces of the safety closure and outwardly from opposing surface of the container neck, respectively. The cooperation of the engaged locking lugs and the threaded fit therebetween prevents removal rotation of the safety closure without first overcoming the engagement of the lugs. It is therefore desirable to provide a safety closure threadingly fit upon a container neck, wherein the safety closure and the container neck are provided with cooperating locking means.
Typically, safety closures of the prior art include a side wall having opposed locking lugs projecting inwardly therefrom, wherein the side wall is deformable upon application of an external force. For example, U.S. Pat. No. 3,667,636 to Landen provides a safety closure frictionally fit upon a container neck and being removable therefrom only after an annulus portion thereof is deformed downwardly a sufficient distance to permit a plurality of locking lugs projecting inwardly therefrom to overcome a plurality of locking formulations projecting outwardly from the container neck. However, it is further desirable to provide a safety closure threadingly fit upon a container neck and secured thereto by engagement between cooperating locking lugs provided respectively thereon, wherein the safety closure is threadingly removable from the container neck by moving the safety closure locking lugs radially-outwardly from the container neck locking lugs.
For example, U.S. Pat. No. 3,770,153 to Gach, et al., teaches a safety closure having locking lugs engageable with cooperating locking lugs provided on a container neck, wherein the safety closure locking lugs are radially outwardly-moveable upon application of radially inwardly-directed forces at locations on the safety closure annularly offset from the locking lugs. However, it is further desirable to provide a safety closure threadingly fit upon a container neck and secured thereto by engagement between cooperating locking lugs provided respectively thereon, wherein the safety closure is threadingly removable from the container neck by moving the safety closure locking lugs radially-outwardly from the container neck locking lugs, and wherein the safety closure locking lugs are radially outwardly-moveable upon application of downwardly-directed force to the safety closure.
It is further desirable to provide a safety closure threadingly fit upon a container neck and secured thereto by engagement between cooperating locking lugs provided respectively thereon, wherein the safety closure is threadingly removable from the container neck by moving the safety closure locking lugs radially-outwardly from the container neck locking lugs, and wherein the container neck is provided with means to move the safety closure locking lugs radially-outwardly from the container locking lugs.


The instant invention provides methods and compositions related to discovery of Free Fatty Acid Receptor 1 (FFA1) as a therapeutic target for treatment or prevention of diseases or disorders of neurons that are characterized by angiogenesis, or of vascular diseases of the eye, retinal degeneration and/or tumors more generally. Therapeutic and/or prophylactic uses and compositions of known FFA1 inhibitors, including small molecules and nucleic acid agents, are described. Methods for identification of novel FFA1 inhibitors are also provided.

Retinal neovascularization in the macula is the leading cause of blindness in older adults (Lim, L. S., et al., Lancet 379, 1728-1738 (2012)). Photoreceptors are amongst the highest energy consuming cells of the body (Wong-Riley, M. T. T. Eye Brain 2, 99-116 (2010), and Okawa, H., et al., Curr Biol 18, 1917-1921 (2008)) and the macula is the region of highest photoreceptor density.
Retinal angiomatous proliferation (RAP) vascular lesions are found in macular telangiectasia (MacTel) (Yannuzzi, L. A., et al. Retina 32 Suppl 1, 450460 (2012)) as well as in 15-20% of neovascular age-related macular degeneration (AMD) (Bottoni, F., et al. Arch Ophthalmol 123, 1644-1650 (2005)), consistent with high energy demands associated with retinal angiogenesis. Although VEGF contributes to neovascularization in macular diseases, the factors that initiate VEGF secretion remain largely unknown. Dyslipidimia and mitochondrial dysfunction (associated with aging) are important risk factors for neovascular AMD (Feehan, M., et al. BMC Med Genet 12, 83 (2011), Fritsche, L. G., et al. Nat Genet 40, 892-896 (2008), and Barot, M., et al., Curr Eye Res 36, 1069-1077 (2011)). There is currently no cure for AMD or MacTel. Therefore, there is a need in the field for the identification of therapeutics that ameliorate and/or prevent AMD and/or MacTel.

FFA1 (GPR40) as a therapeutic target for neural angiogenesis diseases or disorders


A heat exchanger core comprises a pair of header plates, each of which having a plurality of openings therein, a plurality of oval cross-section heat exchanger tubes adapted to receive a fluid medium therethrough extending in generally spaced parallel relationship between the header plates, the ratio between the major diameter and the minor diameter of each of the tubes being from about 12/1 to about 18/1, each of the plurality of tubes being positioned and arranged such that the ends of each of the tubes are joined to corresponding openings in each of the header plates to form a plurality of tube-to-header joints, and a plurality of louvered serpentine heat transfer fin elements disposed between the header plates in a heat exchange relationship with the plurality of tubes.

1. Field of the Invention
This invention relates to heat exchangers and more particularly, to truck and industrial heat exchangers.
2. Description of Related Art
Heat exchangers or radiators utilized in heavy trucks and some industrial applications are typically comprised of cores fabricated from three (3) or four (4) rows of oval shaped solder-coated brass tubes in a heat exchange relationship with corresponding louvered serpentine copper heat transfer fins. A heat exchanger comprising three (3) rows of heat exchanger tubes is known as the 3R VTD core, and a heat exchanger comprising four (4) rows of heat exchanger tubes is known as the 4R VTD core. The maximum fin count in these cores is about 16 fins per inch. Typically, the tubes are separated, in the direction of air flow, by a space of about 0.155 inch. However, it has been found that these spaces between the tubes do not transfer heat and thus, impede the cooling process of the hot fluid flowing through the tubes. Thus, these spaces are essentially wasted. It has also been found that the flat non-louvered portions of the copper fins, between the louver banks, are not as efficient as the louvered portions in effecting transfer of heat from the tubes.
FIG. 2a shows a conventional core layout 20 which is known as the 4R VTD heat exchanger. The 4R VTD core 20 is comprised of four (4) rows of heat exchanger tubes 12. The heat exchanger has a core depth W.sub.A of approximately 3.04 inches, a tube centerline spacing S.sub.A of approximately 0.57 inch and a space F.sub.R of approximately 0.155 inch between each heat exchanger tube 12 (in the direction of air flow). The spaces F.sub.R between the heat exchanger tubes do not effectively transfer heat and thus, are essentially wasted. FIG. 2b shows the dimensions of the oval heat exchanger tube utilized in the 4R VTD design of FIG. 2a. The major and minor diameters A.sub.R and C.sub.R, respectively, of tube 12 are approximately 0.625 inch and 0.078 inch, respectively. The ratio of major diameter to minor diameter is approximately 8 to 1 (8/1). The tube wall thickness T.sub.R is approximately 0.008 inches. The hydraulic diameter of tube 12 is about 0.1145 inch.
FIG. 3a shows another conventional core layout which is known as a 3R VTD heat exchanger 22. The 3R VTD heat exchanger is comprised of three (3) rows of heat exchanger tubes 12. The heat exchanger has a core depth W.sub.B of approximately 2.29 inches, a tube centerline spacing S.sub.B of approximately 0.57 inch and a space F.sub.R (in the direction of air flow) of approximately 0.155 inch between heat exchanger tubes 12. Similar to the 4R VTD design, the spaces F.sub.R between heat exchanger tubes 12 of the 3R VTD core 22 do not effectively transfer heat and thus, are essentially wasted spaces. FIG. 3b shows the dimensions of the oval heat exchanger tubes utilized in the 3R VTD design. The major and minor diameters A.sub.R and C.sub.R, respectively, of the heat exchanger tubes 12 are approximately 0.625 inches and 0.078 inches, respectively. The ratio of major diameter to minor diameter is approximately 8 to 1 (8/1), which is the same as in the 4R VTD design. The tube wall thickness T.sub.R is approximately 0.008 inches, which is also the same as the 4R VTD design. The hydraulic diameter of tube 12 in the 3R VTD core is 0.1145 inch, which is the same as in the 4R VTD core.
FIG. 5a shows another conventional core layout 28 which is known as the 2R VTD heat exchanger. The 2R VTD core 28 is comprised of two (2) rows of heat exchanger tube 12. The 2R VTD core 28 has a core depth W.sub.D of approximately 1.54 inch, a tube centerline spacing S.sub.D of approximately 0.57 inch and a space F.sub.R of approximately 0.155 inch between tubes 12. As found with the 3R VTD and 4R VTD core layouts, the 0.155 inch space between tubes 12 in the 2R VTD core does not effectively transfer heat and basically amounts to wasted space. FIG. 5b shows the heat exchanger tube 12 utilized in the 2R VTD core. This tube has dimensions that are the same as those of the tubes utilized in the 3R VTD and 4R VTD cores and thus, has the same 8 to 1 (8/1) major diameter to minor diameter ratio.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a new and improved heat exchanger that minimizes or eliminates wasted space between heat exchanger tubes in the direction of air flow, thereby facilitating efficient transfer of heat from the tubes.
It is a further object of the present invention to provide a new and improved heat exchanger that utilizes fewer heat exchanger tubes and heat transfer fins than conventional designs.
It is yet another object of the present invention to provide a new and improved heat exchanger that is smaller in size than the aforementioned conventional heat exchangers but yet, has the ability to cool larger engines.
It is a further object of the present invention to provide a new and improved heat exchanger that is of simple construction and light weight.
It is a further object of the present invention to provide a new and improved heat exchanger that allows vehicle manufacturers to improve vehicle aerodynamics.
It is another object of the present invention to provide a new and improved heat exchanger core that has a core face surface area that is less than that of the aforementioned conventional heat exchangers without sacrificing heat transfer efficiency.
It is another object of the present invention to provide a new and improved heat exchanger that has a core airside pressure drop that is approximately the same as that of the aforementioned conventional heat exchangers.
It is another object of the present invention to provide a heat exchanger that can be manufactured at a reasonable cost.


In an electroacoustic transducer of the present invention, a casing supports a diaphragm, a drive coil is provided on the diaphragm, a first magnetic structure has a first space in a center thereof provided within the casing such that a center axis penetrates the first space, and a second magnetic structure has a second space in a center thereof provided within the casing on a side opposed to the first magnetic structure with respect to the diaphragm, such that the center axis penetrates the second space. The first magnetic structure is oriented such that a magnetization direction thereof is parallel to the center axis. The second magnetic structure is oriented such that a magnetization direction thereof is opposite to the magnetization direction of the first magnetic structure.

1. Field of the Invention
The present invention relates to an electroacoustic transducer and an electronic apparatus including the electroacoustic transducer. More particularly, the present invention relates to an electroacoustic transducer having a structure in which magnets are provided both above and below a diaphragm, and also relates to an electronic apparatus including such an electroacoustic transducer.
2. Description of the Background Art
Recently, in the field of portable electronic apparatuses, such as a mobile telephone and a personal digital assistant (PDA), reduction in thickness and power consumption of an electronic apparatus has been accelerated. As in the case of the electronic apparatus, an electroacoustic transducer included in the electronic apparatus is demanded to reduce its thickness while achieving more efficient power consumption. Accordingly, in order to realize reduction in thickness and power consumption, an electroacoustic transducer as described below has been proposed.
FIG. 16 illustrates the structure of a conventional electroacoustic transducer. In the conventional electroacoustic transducer illustrated in FIG. 16, a casing 20 includes a circular cover 1 and a circular frame 2 joined to the cover 1. Each of the cover 1 and the frame 2 is open on one end. The cover 1 includes a plurality of holes 11 for emitting sound provided in a circle. A magnet 3 is fixed on an inner plane of the cover 1 such that the center axis of the cover 1 passes through the center of the magnet 3. A disc-like diaphragm 4 is provided within the casing 20 so as to provide space G between a lower surface of the magnet 3 and the diaphragm 4. The diaphragm 4 is secured at its outer circumferential portion sandwiched between the cover 1 and the frame 2. A drive coil 5 is fixed on a lower surface of the diaphragm 4 so as to have the same center axis as the center axis of the magnet 3. An electrode 6 for applying an electric current to the drive coil 5 is fixed on the bottom of the frame 2. A lead line (not shown) extending from the drive coil 5 is connected to an end of the electrode 6.
In the conventional electroacoustic transducer illustrated in FIG. 16, the magnet 3 emits magnetic fluxes from its lower surface, such that magnetic fluxes emitted from the vicinity of the center of the magnet 3 pass substantially perpendicularly through the drive coil 5, while magnetic fluxes emitted from an outer circumferential portion of the magnet 3 radiate from the lower surface of the magnet 3 so as to pass diagonally through the drive coil 5. In a magnetic field formed by emission of the above-described magnetic fluxes, when an electric current is applied to the drive coil 5, a drive force in a direction perpendicular to the diaphragm 4 is generated in the drive coil 5. Such a drive force causes the diaphragm 4 to vibrate up and down, thereby producing sound. The conventional electroacoustic transducer illustrated in FIG. 16 is configured to emit magnetic fluxes directly from the magnet 3. Accordingly, this conventional electroacoustic transducer requires neither a yoke nor a center pole, and therefore the entire thickness thereof can be reduced. Moreover, the drive coil 5 has a high degree of freedom in the range of possible winding widths, and therefore has a high degree of freedom in the range of possible impedance values. Accordingly, by increasing the impedance of the drive coil 5, it is made possible to achieve reduction in power consumption of the conventional electroacoustic transducer.
Further, in the conventional electroacoustic transducer illustrated in FIG. 16, the drive force generated in the drive coil 5 increases in proportion to the intensity of magnetic fluxes perpendicular to a direction of the electric current flowing through the drive coil 5 and a vibration direction of the diaphragm 4. In FIG. 16, magnetic fluxes parallel to the vibration direction of the diaphragm 4 are dominant over the magnetic fluxes perpendicular to the vibration direction of the diaphragm 4. Accordingly, the conventional electroacoustic transducer illustrated in FIG. 16 is not able to obtain a satisfactory drive force, and therefore is able to provide only a low reproduced sound pressure.
Furthermore, the intensity of the magnetic fluxes emitted from the magnet 3 decreases in proportion to the distance from the magnet 3. Accordingly, the drive force generated in the drive coil 5 varies between the case where the diaphragm 4 is located in a downward direction from its initial position as shown in FIG. 16 (i.e., a direction away from the magnet 3) and the case where the diaphragm 4 is located in an upward direction from its initial position (i.e., a direction toward the magnet 3). Such a variation of the drive force causes distortion of the drive force in the conventional electroacoustic transducer illustrated in FIG. 16, resulting in deterioration of reproduced sound.

Electroacoustic transducer and electronic apparatus

Matsushita Electric Industrial Co., Ltd.


An electronic device with a battery displays a label for indicating different power levels of the battery. The label comprises a plurality of columns. Each of the columns is capable of being illuminated. A number of the columns lighted correspond to a corresponding the power levels in a one-to-one relationship. The electronic device comprises a detection module, storage, an acquiring module, a check module, and a display module. The detection module detects the current voltage of the battery at regular intervals and stores the information in the storage. The acquiring module acquires a previous detected voltage from the storage. The check module checks whether the current voltage is a fluctuated voltage. The display displays the label with the numbers of the lighted columns corresponding to the power level which contains the previous detected voltage when the current voltage is a fluctuated voltage.

1. Technical Field
The present disclosure relates to electronic devices, particularly to an electronic device with power indicating function.
2. Description of Related Art
An electronic device powered by a battery, such as a mobile phone or a tablet computer, displays a label for indicating different power levels of the battery. The label is divided into a plurality of columns which correspond to different ranges of the voltage. Each of the columns is capable of switching between a lighted state and an off state. However, when the voltage of the battery fluctuates between two adjacent voltage ranges, one of the columns switches between the lighted state and the off state which looks like the label is flashing or twinkling.
Therefore, there is room for improvement in the art.

Electronic device with power indication function and indicating method thereof

ShenZhen Goldsun Network Intelligence Technology Co., Ltd.


A connector is adapted for mating with a header with one or more side grounding pins. The connector comprises a first insulating connector body part with one or more receiving spaces for a side grounding pin, a conductive shield, substantially covering a first face of the connector body part, and one or more outer flexible beams, in electrical contact with the shield, and each protruding into a receiving space. The connector comprises one or more inner flexible beams, each positioned relative to an outer flexible beam so as to make contact with the outer flexible beam when it is forced out of the receiving space.

Embodiments of such a connector and assembly are known. One example comprises a stackable configuration of connectors with ground tabs to mate with the optional side grounding pins in a mating header. Each connector has its own shield.
The conductive shield in such a connector is used for grounding. The conductive contact between the connector and the grounding pins of the header must therefore have a very low resistance, to take account of the low currents and voltage differences. Low resistance can be provided through high contact pressure between each flexible beam and its associated grounding pin. At the same time, plastic deformation of either the side grounding pin or the flexible beam should be prevented, so as to be able to repeatedly exert the same contact pressure. The flexible beam may not be very long either, since this would create extra inductance, leading to deteriorated shielding performance.
The known connector does not fully meet these requirements. To exert sufficient force, the beams must be made relatively thick, resulting in less flexibility. In addition, since only one face of the connector is covered by a conductive shield, the conductor is asymmetric, giving rise to impedance 'steps' and, consequently, sub-optimal shielding of high frequency signals.

Connector assembling with side grounding pin