A testing device for a semiconductor storage device suppresses the increase in the circuit size, provides for facilitated accommodation to a test with frequent changes in the test pattern, and improves testability of the semiconductor storage device. A plurality of holding circuits are provided holding write data for memory cells of a memory cell array. (Original) The write data from the holding circuits are written in the memory cells of the selected address. A plurality of comparators are supplied with data read out from the memory cells and with data held by the holding circuits as expectation data to compare the readout data and the expectation data. The non-inverted or inverted value of the write data held by the holding circuits is output as the write data to the memory cells and as expectation data to the comparators depending on the value of the inversion control signal.

As a parallel test, employing a testing device, a line mode test for semiconductor devices has become known (see for example the non-patent publication 1). First, the line mode test is briefly explained. FIG. 13 shows the structure of a semiconductor storage device disclosed in the non-patent publication 1. The storage device shown in FIG. 13 includes a multi-purpose register MPR (write/expectation value register) 1101 and a comparator circuit 1102 for complementary sub-IO lines SIO_T, SIO_B (bit line pair). The comparator circuit 1102 is formed by an Ex-OR circuit, and an output signal (coincidence detection signal) MATCH is wired-OR connected. The multi-purpose register MPR 1101, comprising a flip-flop formed by cross-connection of an output and an input of an inverter composed of a P-channel MOS transistor P41 and an N-channel MOS transistor N49 and an inverter composed of a P-channel MOS transistor P42 and an N-channel MOS transistor N50, is connected across a main I/O line pair (MIOT, MIOB) and a sub I/O line pair (SIO_T, SIO_B), in order to perform copy/write in a line mode test (LMT) and parallel comparison by line read. During the time of activation of the multi-purpose register MPR (write/expectation register) 1101, the power supply potential and the ground potential are supplied to CRE_B and CRE_T of the multi-purpose register MPR (write/expectation value register) 1101.
During the line mode test, test data are written in the multi-purpose register MPR (write/expectation value register) 1101, in which a random patterns possible on one line. The random pattern data are simultaneously written in the memory cells connected to the selected word line. A signal TR is in a high level, while a test compare trigger signal COMP is in a low level. The complementary data of the main IO lines MIOT, MIOB are stored in the flip-flop of the multi-purpose register MPR (write/expectation value register) 1101, and transmitted to the complementary sub-IO lines SIO_T, SIO_B via the N-channel MOS transistors N41, N42 in the on-state so as to be written in the memory cells connected to the selected word line.
When the test compare trigger signal COMP is in a high level and the signal TR is in a low level, parallel comparison is carried out in each comparator 1102 to detect coincidence between the readout data and the expectation data. Specifically, the N-channel MOS transistors N41, N42 are off, while the N-channel MOS transistors N43, N44 are on. When MIOT and MIOB as write data are in the high level and in the low level, respectively, the N-channel MOS transistor N46, the gate of which is supplied with a value held by the multi-purpose register MPR (write/expectation value register) 1101 is turned on, while the N-channel MOS transistor N45 is turned off. When the sub-IO line SIO_B, transmitting the readout data, is high (in case of failure), the N-channel MOS transistor N48 is turned on, with the coincidence detection signal MATCH being in the low level (error detected). When the sub-IO line SIO_B is low, the N-channel MOS transistor N48 is turned off, with the coincidence detection signal MATCH being in the high level. In case of writing with the main IO lines MIOT, MIOB being in the low level and in the high level, respectively, the N-channel MOS transistor N45 is turned on to detect an error in similar manner. If even only one of plural comparators, connecting to the signal line MATCH, is non-coincident, an error signal is sent out from MATCH and output to an output terminal DQ, not shown. Any failure on a line is detected by one read cycle.
As a modification of the line mode test, there is also known a structure in which write data and expectation data are directly supplied from a write bus (see for example the Patent Publication 1). In this conventional semiconductor storage device, the data read out from each selected one of plural columns is compared to expectation data by test means and the result of comparison is output. The test means for conducting a test on plural columns is provided common to the columns. Specifically, as shown in FIG. 14 hereof (corresponding to FIG. 2 of the Patent Publication 1), a first differential amplifier 60 is connected to bit line pairs BL, /BL. There are provided write buses W, /W, readout buses R, /R and a readout/test circuit 7. During a test, a column decoder 4 compares the data read out from every other bit line pair of plural bit line pairs BL, /BL to a given expectation data and respective results of comparison are output. The column decoder 4 then compares the remaining ones of the bit line pairs BL, /BL to a given expectation to output respective results of comparison. The readout/test circuit 7 includes a switch 71 connected across the readout buses R, /R and data buses DB, /DB, a switch 72 connected across the readout buses k, /R and buses for line test LB, /LB, a differential amplifier 73 connected to the data buses DB, /DB, an expectation data write circuit 74 connected to the buses for line test LB, /LB, and an error detection circuit 75 connected to the buses for line test LB, /LB, and outputs an error flag EF if an error is detected during the line mode test.
There is also known a structure including a coincidence detection circuit supplied with readout data from plural cell arrays to detect possible coincidence of the input data to compress 16 IO to 4 IO (see for example the Patent Publication 2).
The structure shown in the block diagram of FIG. 15 is that of a conventional test circuit of the semiconductor device described in the aforementioned Patent Publication 2, in which no expectation data is needed during reading. That is, data may be independently written in a write amplifier of each memory cell, in order to test data interference between neighboring memory cells. That is, first to fourth read/write amplifiers (Ramp and Wamp) 1302 are provided as peripherals of a memory cell array 1301. The memory cell array 1301 includes an X-decoder 1304, supplied with and decoding an X-address to select a word line, a sense amplifier 1305 connected to the bit line and a column decoder 1306 supplied with and decoding a Y-address to select a bit line. These elements as one unit are also termed a 'mat' or a 'cell array block'. In FIG. 15, the X-decoder 1304 may be provided common to plural cellblocks.
A first write data bus, a second write data bus, a third write data bus and a fourth write data bus are connected common to each of the first write amplifiers (Wamp), second write amplifiers (Wamp), third write amplifiers (Wamp) and the fourth write amplifiers (Wamp) of each of the four memory cell arrays 1301. During line testing, the first to fourth write amplifiers are supplied with data from the first to fourth write data buses in parallel. The data from the write amplifier (Wamp) is written in the memory cell connected to the selected word line.
FIG. 16 shows a connection structure of the circuit of FIG. 15 at the time of readout in the parallel test mode. The sense amplifier outputs of the bit lines selected by a column decoder 1306 are amplified by a read amplifier (Ramp), while four output signals output from the first read amplifiers (Ramp) of the four memory cell arrays are supplied to a first comparator 13030. In similar manner, the four output signals output from the second to fourth read amplifiers (Ramp) of the four memory cell arrays are supplied to second to fourth comparators 13031 to 13033. Each of the comparators 13030 to 13033 outputs a 'pass' and a 'fail' when the four input signals are all coincident and when any one of the signals is non-coincident, respectively. In an alternative structure, there is provided a comparator supplied with outputs of comparators 13030 to 13033 to verify the possible coincidence of the comparator outputs to compress the results of comparison.    [Non-Patent Publication 1]
K. ARIMOTO et al. "A 60-ns 3.3-V -Only 16-Mbit DRAM with Multipurpose Register", IEEE, journal of solid-state circuits, vol.24, No.5, October 1989, pp1184-1190    [Patent Publication 1]
Japanese Patent Kokai Publication No. JP-A-4-356799 (pages 5 and 6, FIGS. 1 and 2)    [Patent Publication 2]
Japanese Patent Kokai Publication No. JP-P2000-40397A (page 4, FIG. 3)


A high pressure first stage turbine and seal assembly are described. In one embodiment, a high pressure turbine section is provided. The turbine section includes at least one stage, at least one rotor and a bucket assembly. The bucket assembly includes a bucket and an attachment fixture. The stage has a high root reaction during operation. An intermediate space is between the bucket assembly and a stationary component of the turbine section. A seal is provided between the stationary member and the rotor to facilitate preventing leakage from the intermediate space toward an end of the stage. Steam balance holes are provided in the rotor or the bucket to facilitate feeding steam towards an end of the turbine stage.

The present invention relates generally to rotary machines and, more particularly, to a high pressure first stage turbine.
At least some steam turbines have a defined steam path which includes, in serial-flow relationship, a steam inlet, a turbine, and a steam outlet. Steam leakage, either out of the steam path or into the steam path, from an area of higher pressure to an area of lower pressure may adversely affect an operating efficiency of the turbine. For example, steam-path leakage in the turbine between a rotating rotor shaft of the turbine and a circumferentially surrounding turbine casing, may lower the efficiency of the turbine.
To facilitate minimizing steam-path leakage to the atmosphere, at least some known steam turbines use a packing casing that includes a plurality of labyrinth seals. Some known labyrinth seals include longitudinally spaced-apart rows of labyrinth seal teeth which are used to seal against pressure differentials that may be present in the steam turbine. Seal members, such as brush seals or leaf seals, may also be used in an attempt to reduce leakage through a gap defined between two components.
In an attempt to reduce leakage of steam from the root of the stage into the end of the section, low reaction roots have been used. Generally, a low reaction root causes the leakage steam at the root to be at a reduced pressure as compared to the main flow pressure. Negative reaction and steam balance holes induce steam from the discharge of the stage through the steam balance holes to feed the leakage path. As a result, most of the steam that leaks has already been expanded through the stage and produced useful work. Such low reaction roots, however, may result in less efficient expansion of the steam than high reaction roots. A high degree of reaction facilitates ensuring there is a positive pressure on the rotating blade at all diameters, which in turn facilitates efficient expansion of the steam.
Another known approach is to use steam from a space between a nozzle and a bucket to feed the leakage path. The leakage path through the end section is decreased because the nozzle decreases the steam pressure, thus decreasing the source pressure for the leakage path. However, none of the steam used to feed the leakage path expands through the bucket to produce useful work. In addition, in-service variations of the reaction of the stage due to wear and tear may impact other machine parameters in a disadvantageous manner.
Yet another known approach utilizes high reaction stage roots with the leakage flow fed from the bowl of the stage. However, the bowl pressure is higher than the intermediate pressure at the roots. As a result, the source pressure for the leakage flow is higher and the leakage flow will increase, which leads to decreased efficiency.

High pressure first stage turbine and seal assembly


An application device includes a network communication unit and an application system unit. The application system unit executes application communication utilizing one of a first TCP/IP protocol processing performed by the network communication unit and a second TCP/IP protocol processing performed by the application system unit. The network communication unit switches the process with which the application communication is processed to one of the first TCP/IP protocol processing and the second TCP/IP protocol processing based on a communication condition of the application communication.

1. Field of the Invention
The present invention relates to a communication apparatus and communication control method that provides application communication using TCP/IP protocol communication.
2. Description of the Related Art
In the present specification, "application device" refers to a device that is connected to a network and is capable of application communication in which TCP/IP protocol is the lower-layer protocol.
In general, TCP/IP protocol processing is often implemented through software called a TCP/IP protocol stack. FIG. 2 shows a hierarchy model of software processing in TCP/IP communication. In FIG. 2, the TCP/IP protocol stack is expressed by the software processing in a range indicated by the number 201. 202 in FIG. 2 is an application layer, and is application communication protocol processing that uses TCP/IP communication. Many protocols exist, including standard protocols such as Hyper Text Transfer Protocol (HTTP), protocols uniquely defined and implemented on an application-by-application basis, and so on.
203 is a socket layer, handling software interface processing through which the application layer process uses the lower-layer TCP/IP protocol. "Socket" refers to an end-point in TCP/IP communication, and can be identified by the IP address of the network device performing TCP/IP communication and the port numbers allocated in each instance of TCP/IP communication in the device. The socket interface is an interface for application software to handle TCP/IP communication, and is supported in many operating systems (OS).
204 is a transport layer protocol processing, and 205 is a network layer protocol processing. In TCP/IP, TCP and UDP (User Datagram Protocol) exist as protocols in the transport layer, and IPv4 (IP version 4) and IPv6 (IP version 6) exist as protocols in the network layer. 206 is a link layer, and is a communication protocol processing dependent on the physical medium of the network. 207, which is the lowest layer, is driver software for controlling the physical medium access control (MAC) device of the network.
Conventionally, TCP/IP communication has been realized in an application device by implementing the TCP/IP protocol processing by software executed by a central processing unit (CPU) included within the application device. Even now, in devices such as personal computers that are rich in processing resources, TCP/IP communication is realized by TCP/IP protocol processing incorporated within the OS.
However, in recent years, the amount of data sent and received by application devices has increased, and the processing load placed on the CPU by software processes for TCP/IP communication has become extremely large. For example, video server devices such as network cameras and network video distribution servers, digital audio/video (AV) devices such as network media players and network-compatible hard disk recorders, and the like have come into wide use. Moreover, in devices such as these that input and output video through a network, the processing load involved in communication processing for sending and receiving high-resolution image data in real time is growing.
As a response to this increase in the CPU processing load for TCP/IP communication, a method of offloading TCP/IP protocol processing is being implemented, with the aim of reducing the load on the CPU of the application device and increasing TCP/IP communication throughput. In TCP/IP communication, "offloading" refers to processing mainly the software indicated by the number 208 in FIG. 2 with a separate processing device rather than with the CPU of the application device. For example, there are cases where offloaded processing is performed by a microprocessor different from the CPU of the application device, and cases where parts in which the computational amount of TCP/IP processing in the software is large are processed at high speed by a dedicated hardware circuit.
U.S. Pat. No. 6,941,386 discloses a method related to an intelligent network interface card (INIC) that is installed in a communication processing device included in a host device or an external expansion interface of the host device. With this method, TCP/IP protocol processing through hardware circuit processing is realized, and the software processing of the TCP/IP protocol stack performed by the CPU of the host device is offloaded.
In this conventional example, the scheme is such that a generic protocol stack executed by the CPU is retained and the TCP/IP protocol processing realized by software is executed by the CPU. In other words, two types of processing are provided: slow-path processing performed by the generic protocol stack, and fast-path processing performed by hardware processing. This is because TCP/IP protocol processing is of a scope that cannot be supported by hardware processing or the cost of implementation as hardware cannot be justified.
In addition, in recent years, there are cases where TCP/IP protocol processing performed by the CPU of the application device is completely offloaded by dedicated hardware, thereby reducing CPU resource usage for TCP/IP communication to a minimum.
However, in the case of an integrated device in which strict limitations are placed on the cost of hardware resources, a scheme that offloads TCP/IP protocol processing with hardware limits the number of communication connections that can be processed to a small number. Thus, there is a problem that the application device cannot open many communication connections and execute communication simultaneously.
Furthermore, offloading all of the protocol processing in the range indicated by the number 208 in FIG. 2, which has conventionally been processed by software, with completely dedicated hardware results in the scale of the hardware circuit becoming large. Therefore, in terms of cost, such a scheme is inappropriate in an integrated device in which strict limitations are placed on the hardware resources.

Communication apparatus and communication control method


One example is an antenna structure with a metamaterial having a flexible metamaterial layer, a two-dimensional antenna layer and a spacer layer. The flexible metamaterial layer has a metamaterial thickness allowing the metamaterial layer to be attached to a curved conducting surface of a vehicle. The metamaterial layer is formed with a two-dimensional array of elements having a passive magnetic property with the array of elements formed with elongated individual elements each having a top end and a bottom end. The elongated individual elements have curved outer surfaces between the top end and the bottom end. The two-dimensional antenna layer receives electromagnetic signals. The spacer layer is located between the metamaterial layer and the antenna layer separating the metamaterial layer and the antenna layer.

It may be desirable to place a conformal antenna closely adjacent to or directly onto a metallic conducting surface. However, when an antenna such as a microwave antenna array is placed directly onto on a metallic surface, the metal surface will shield electromagnetic radiation in the GHz range near the surface. The metallic surface prevents the electric field from penetrating inside the metallic surface and essentially zeroes the in-plane components of the electric field near the surface. Thus, the operation of the antenna is compromised.

Government of the United States, as Represented by the Secretary of the Army


A method for controlling vibrations includes receiving the vibrations from a vibration-generating substructure at at least two vibration diverters and diverting the vibrations away from each of the vibration diverters, using the respective vibration diverters, to a vibration confiner that interconnects the vibration diverters. The vibration diverters can include passive elements, e.g., plates, ribs, notched plates, plates having wells, etc., active elements, e.g., actuators, sensor/actuators, etc., or a combination of passive and active elements. The vibration confiner can include a passive layer damping material for dissipating vibrations.

Alternating disturbances that are imparted to a structure frequently cause the structure vibrate. These disturbances can be internal to the structure. For example, when a gun is fired, the alternating explosions of the bullets within the gun cause the gun to vibrate. The alternating disturbances can also be external to the structure. For example, in military situations the firing action of a gun generates and transmits vibrations to the supporting structure of the gun. The gun supporting structure in turn transmits the generated vibrations through its connecting points to a turret connected to the main structure of a vehicle (e.g., helicopter, airplane, ground vehicle, etc.). The turret transmits the vibrations to the main structure of the vehicle. The transmitted vibrations often damage onboard electronics and increase crew fatigue. In another example, a rotating element of a machine can cause the machine to vibrate. This vibration can be transmitted to structures to which the rotating machine is attached. Vibrations generated by rotating machines should be isolated from the main structure or floor on which the rotating machine rests.
Vibration is typically undesirable. Vibration often results in excessive audible noise that gives rise to safety issues, causes fatigue in mounting structures, and the like. Because of the undesirable effects of vibration, numerous methods have been employed in mounts for gun turrets, rotating machinery, or the like to manage vibration. These methods include both passive and active methods. Passive methods usually involve placing a vibration isolator, absorber, or damper between a vibration source, e.g., gun, rotating machine, or the like, and the structure in which the vibration is undesirable, e.g., helicopter shell, rotating machine mount, or the like. Vibration isolators intercept the vibration energy from the vibration source and prevent it from being transmitted to the structure. Vibration absorbers absorb the energy from the source. Vibration isolators and absorbers can be tuned only to one or a few resonant frequencies and therefore are only effective within a narrow frequency band around the selected frequencies. In some instances, vibration isolators and absorbers can amplify undesired vibrations at certain frequencies. Moreover, vibration isolators are not effective for isolating severe shocks or extreme vibratory loads. Vibration dampers receive vibration energy from the source and dissipate it at a faster rate. Dampers add weight to systems, and their performance is temperature dependent and is limited to near-resonant frequencies.
Many commercial and military applications include vibrations over a broad range of frequencies, rendering the above-mentioned passive vibration control methods ineffective for these applications.
Active vibration control methods include feedback and feed-forward vibration cancellation. Feedback vibration cancellation includes measuring the vibration, feeding the measurement back to a controller, sending a control signal from the controller to an actuator, and using the actuator to apply a force or a moment to counteract the vibration. Feed-forward vibration cancellation includes measuring the vibration, feeding the measurement forward to a controller, sending a control signal from the controller to an actuator, and using the actuator to apply a vibration that is substantially identical to the source vibration, with an appropriate phase shift, at or near the source. These active vibration control methods are expensive and hard to implement. Moreover, these methods require excessive amounts of power in that they are applied globally to all parts of the system and therefore are applied to parts of the system that are irrelevant to system performance.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for mounts that include continuous structural elements with vibration energy managing features, that have broader frequency ranges, that are easy to implement, and that can be applied to only those structural areas where vibration control is critical to system performance and therefore are more power efficient.

Smart isolation mounts with continuous structural elements featuring vibration energy management

Quality Research, Development & Consulting, Inc.


The present invention provides a feeding tube adapter for enteral feeding tubes that comprises a central passageway having an exit port having an inside diameter smaller than the exit port inside diameter of an enteral feeding tube and constructed to provide a Venturi effect on material passing through the adapter thereby inhibiting blockage when feeding formulas or medications are infused therein. The adapter is advantageously constructed in the form of a Y-Port for ease of irrigating.

Historically, Studley was among the first to associate nutritional status and disease outcome. In 1936, this pioneering investigator made the classic observation that marked weight loss prior to peptic ulcer surgery resulted in a higher post-operative mortality rate relative to weight-stable patients. Modern health care workers have identified weight loss as a major determinant of prognosis in many disease states.
Total health care is contingent upon sound nutritional status. Practicing physicians and physician extenders evaluating the clinical and nutritional status of their patients should be able to implement an effective feeding program when needed. The wide range of nutritional preparations, catheters and feeding tubes available makes it possible to meet the differing requirements of varying pathological states, either accompanying or causing malnutrition.
The enteral route is a primary means of improving nutritional status in most patients. It is simple, economical and tolerated well in most patients. Optimal enteral feeding requirements can be achieved with the large number of enteral formulas available.
Formulas for enteral use can be subdivided into three basic types: elemental, polymeric, and modular. All of the enteral formulas differ in content and source of nitrogen, carbohydrate, fat and other nutrients, osmolality, taste, residue and expense. The formula components are either premixed by the manufacturer, or added together by the nutritionist shortly before administration. All formulas have the potential to have undissolved, condensed, coagulated, amalgamated, intermixed solids resulting in thickening and enteral tube clogging.
Obstruction of enteral feeding tubes is also precepitated by medications added to feeding formulas or administered via the feeding tube. A major problem is undissolved medications being forced down feeding tubes. The increased cost of injectable or liquid forms of medications and the accessibility to oral tablets is seen as the reason for this ongoing problem.
Feeding tube design has also been associated with higher occurrence of clogging. The small caliber feeding tubes are frequently occluded by feedings and/or medications. The addition of an irrigation port can lower the work to flush the feeding tube and may result in a reduction in obstruction. Medical grade components of the tubes, polyurethane, polyvinylchloride, silicone, etc. do not seem to make a difference in occlusion rates. Large exit ports have been added with claimed advantages, but obstructed enteral feeding tubes is still a major problem. Standard feeding systems provide high rates of feeding in the range of 800 to 1200 ml. per hour. These rates are adjusted with a clamp or pump in normal patient feeding. In jejunal feeding high rates are not desirable and the standard feeding equipment is not advantageously employed.
The added cost of a new tube, nursing time, and x-ray; possible complications of the tube placement; and concern about interruption of feeding to the patient have provided the impetus for developing new devices and methods to clean and open clogged feeding tubes and now to help prevent obstruction of feeding tubes.


A gas analyzer system for analyzing samples of compressed or ambient gas such as breathing air within a scuba tank, SCBA or ambient air within an industrial plant and informing the user as to the results of the sample's gas purity without the gas sample having to be physically transported to an accredited laboratory. The system comprises a gas analyzer situated at a user facility for receiving the contents of a gas sample and detecting gas purity characteristics, and a server situated at a remote certified testing site and electrically coupled to the gas analysis module via data transmission, such as a wireless or a computer network connection, wherein the server, maintained by a qualified third party receives and stores the gas purity characteristics in the form of computer-readable data signals. Computer instructions stored within the qualification server compares the computer-readable data signals representing gas purity characteristics with the contents of a database containing threshold gas purity parameters. After determining if the gas sample characteristics for that particular gas sample meet the required threshold limits, the user receives immediate notification, either by e-mail or by receipt of a fax at the user site, informing the user whether the given gas sample has achieved the required gas purity levels by a qualified third party.

1. Field of the Invention
The invention generally relates to a gas purity analysis system, and particularly to a portable system capable of analyzing a gas sample at a user facility and transmitting gas purity and/or oil and particle information to a remote site where it is quickly determined if the gas substance has passed certain gas purity requirements.
2. Description of the Prior Art
There is a growing need in the industry for gas purity testing systems that can provide gas purity analysis results to the user quickly and efficiently. The standard method in the art for testing the quality of gas samples is to first capture the sample and then transport the actual sample to a certified, accredited laboratory for analysis. The user must then wait, weeks perhaps, until the sample has been analyzed and certified by a qualified government laboratory.
However, given the demand for quality air sources, such as compressed air tanks for SCUBA diving, and compressed air used for human inhalation in industrial plants, hospital and by firemen, as well as ambient air, the standard method is not practical. It is cumbersome and costly, given the potential loss of sales a vendor may experience waiting for certification of the gas sample. These samples often must be taken periodically at short time intervals exacerbating the problem.
Further, a gas sample that passes the required gas purity standards and obtains certification one day may, if impurities enter the tank or facility, become tainted and fall below the certification requirement the next day. However, given the length of time and cumbersome nature of transporting gas sample to a test center, the facility, possibly a hospital, will rely on its prior certification, leading to a possibly dangerous, if not life-threatening situation wherein air, believed to be pure based upon a prior, three-week-old test, actually contains impurities.
Accordingly, what is needed in the art is a gas purity sample analysis system that allows a user to effectively test an air sample on site as often as the user would like and without the actual sample being physically carried to a testing facility, while still being certified by a qualified third party, by inserting the gas sample into a sampling unit located at the user's facility, and the results being electrically transmitted remotely to the certification facility. The gas purity and/or oil/particle content information is then sent, via electronic data transmission, to a monitoring center where the sample quality information is compared by qualified people to a database of industry standards, and the user is notified, within minutes, if the sample tested has attained certification by meeting or exceeding industry purity standards.
It is, therefore, to the effective resolution of the aforementioned problems and shortcomings of the prior art that the present invention is directed.


A print head for a line printer in which errors between print head chips and another component are reduced and ink leakage is prevented, and in which heat generated in print head chips is efficiently dissipated without making the structure of the print head complex or increasing the size of the print head. A plurality of print head chips (11) are arranged along an ink path (20) and are disposed on both sides of the ink path in a zigzag pattern. Dummy chips (21) which do not eject ink are disposed at regions between the print head chips (11) arranged along the ink path (20). In addition, an ink-path member (23) is provided, at least a part of the ink-path member (23) which includes portions adhered to the print head chips (11) being composed of a material having a high thermal conductivity, so that the ink-path member (23) also serves as heat-dissipating means which dissipates heat generated in the print head chips (11).

FIG. 21 is a schematic plan view of a print head 1 included in a known inkjet line printer.
In line printers, one line is simultaneously printed on a print medium. Accordingly, the print head 1 includes a plurality of print head chips 2 (2A, 2B, . . . ) which are arranged in a direction in which lines are printed. Although only five print head chips 2A to 2E are shown in FIG. 21, more print head chips 2 are actually arranged.
Although not shown in the figure, each print head chip 2 is constructed by, for example, disposing heating elements for heating ink on a semiconductor substrate, forming ink-pressurizing cells such that the ink-pressurizing cells surround their respective heating elements, and disposing a nozzle sheet having nozzles for ejecting ink drops above the heating elements. Ink contained in the ink-pressurizing cells is heated by rapidly heating the heating elements, and is ejected from the nozzles due to force applied by bubbles of ink vapor (ink bubbles).
In addition, the print head 1 is provided with an ink path 3 (region between the double-dotted chain lines in FIG. 21) which extends along the length of the print head 1. The ink path 3 is used for supplying ink to the ink-pressurizing cells of the print head chips 2. The print head chips 2 are arranged along the ink path 3 and are disposed on both sides of the ink path 3. In addition, the print head chips 2 on one side of the ink path 3 and the print head chips 2 on the other side face each other across the ink path 3. More specifically, the print head chips 2 on one side of the ink path 3 are rotated 180 degrees relative to the print head chips 2 on the other side. Accordingly, the ink-pressurizing cells of all of the print head chips 2 are communicating with the ink path 3.
In addition, in FIG. 21, the print head chips 2 are alternately disposed on the upper side and the lower side of the ink path 3 along the length of the ink path 3; that is, the print head chips 2 are arranged in a zigzag pattern.
More specifically, the print head chip 2A at the left end in FIG. 21 is placed on the upper side of the ink path 3, and the print head chip 2B, which is adjacent to the print head chip 2A, is placed on the lower side of the ink path 3 in FIG. 21. In addition, the print head chip 2C, which is adjacent to the print head chip 2B, is placed on the upper side of the ink path 3 in FIG. 21.
In addition, although not shown in the figure, the print head chips 2 are arranged such that if an interval between the adjacent nozzles in each print head chip 2 is L, an interval between the nozzles at the ends of the adjacent print head chips 2 (an interval in the direction in which the print head chips 2 are arranged) is also L. For example, in FIG. 21, an interval between the right end nozzle of the print head chip 2A and the left end nozzle of the print head chip 2B is L. Accordingly, even when ink is ejected from a plurality of print head chips 2, all ink drops land on the print medium at a constant interval L.
FIG. 22 is a sectional view of FIG. 21 cut along line A—A, and an ink-path member 4 placed on the print head chips 2 is also shown in FIG. 22. FIG. 23 is a sectional view of FIG. 21 cut along line B—B, and the ink-path member 4 is also shown in FIG. 23. FIG. 24 is a sectional view of FIG. 21 cut along line C—C, and the ink-path member 4 is also shown in FIG. 24.
As shown in FIGS. 22 to 24, the ink-path member 4 is placed on the top surfaces (surfaces facing the ink-path member 4) of the print head chips 2. The ink-path member 4 has a groove 4a (having a bracket shape in cross section) which extends along the length of the ink-path member 4 and which communicates with the ink path 3. In addition, the ink-path member 4 also has recesses 4b for receiving the print head chips 2 in the bottom surface thereof. The number of the recesses 4b provided is the same as the number of the print head chips 2, and the size of the recesses 4b is slightly larger than the size of the print head chips 2.
When the ink-path member 4 is placed on the print head chips 2, the groove 4a of the ink-path member 4 is positioned directly above the ink path 3 and the print head chips 2 are disposed in their respective recesses 4b. Then, the recesses 4b and the print head chips 2 are adhered to each other. The ink-path member 4 does not have the recesses 4b and is directly adhered to a nozzle sheet 5 at regions where the print head chips 2 are not disposed (see left side in FIG. 24). Accordingly, the spaces between the ink-path member 4 and the print head chips 2 and the spaces between the ink-path member 4 and the nozzle sheet 5 are sealed with an adhesive layer.
In the print head 1 which is constructed as described above, ink flows through the groove 4a of the ink-path member 4 and the ink path 3 and is supplied to the ink-pressurizing cells of each print head chip 2 without leaking out of the print head 1.
In the above-described known technique, there are certain limits to the processing accuracy of the print head chips 2, the positioning accuracy when the ink-path member 4 is adhered to the print head chips 2, and the processing accuracy of the recesses 4b of the ink-path member 4.
Accordingly, when the accuracy error exceeds a certain limit, there is a possibility that the spaces between the ink-path member 4 and the print head chips 2 cannot be completely sealed when the ink-path member 4 is adhered to the print head chips 2, and gaps will be generated between the ink-path member 4 and the print head chips 2. Accordingly, there is a risk in that ink will leak out of the print head 1 though these gaps.
FIGS. 25 and 26 are sectional views which correspond to FIGS. 22 and 24, respectively, showing the case in which the ink-path member 4 includes an error.
As shown in FIGS. 25 and 26, it is assumed that a surface 4c between the recesses 4b of the ink-path member 4 has an error and the amount of error of the surface 4c is X. In this case, when the ink-path member 4 is placed on the print head chips 2, the surface 4c of the ink-path member 4 first comes into contact with the nozzle sheet 5. At this time, the distances between the recesses 4b and the print head chips 2 are larger than the designed value by X, and gaps S are generated accordingly. Similarly, gaps S are also generated between the nozzle sheet 5 and the surfaces other than the surface 4c where the recesses 4b are not provided. If the gaps S are too large to be completely sealed with an adhesive, ink will leak out though the gaps S.
On the other hand, in the above-described known technique, heat is emitted from the print head chips when they are driven, that is, when the heating elements are heated, and there is a problem as to how the heat generated in the print head chips is to be dissipated.
A part of heat generated by the heating elements goes out along with ink when the ink is ejected, but the remaining heat accumulates in the print head chips. Accordingly, when ink is continuously ejected (when printing is continuously performed), a temperature increase of 100° C. or more occurs in a short time in the print head chips.
In particular, heat generation cannot be ignored in print heads for line printers since they include many print head chips and there are the same number of heat generators as the number of print head chips.
In order to properly eject ink, the operating temperature of the print head chips must not be higher than the boiling point of ink (approximately 100° C.). If the temperature exceeds this limit, a state in which a proper amount of ink is properly ejected cannot be obtained and the printing quality will be degraded.
Accordingly, a method is known in which when printing is performed for a predetermined time, the operation is stopped for a predetermined time interval to reduce the temperature before the operation is restarted. However, this method has a problem in that the overall print speed is reduced if the stopping time is increased to suppress the temperature increase.
Alternatively, a heat-dissipating member may be installed in the print head. However, in the case in which the heat-dissipating member is installed in the print head, sufficient ambient dissipation cannot be provided unless the surface area of the heat-dissipating member is large. Accordingly, there is a problem in that the size of the print head is increased if a large heat-dissipating member is installed. On the contrary, if the surface area of the heat-dissipating member is reduced, sufficient ambient dissipation cannot be provided.
In addition, print head chips are generally arranged in a zigzag pattern in known print heads for line printers, and it is difficult to accurately process the heat-dissipating member in accordance the arrangement of the print head chips and install it.


A sheet stacking apparatus has an abutment portion attached to a holding portion movably in first and second directions. The abutment portion is configured such that a movable range of the abutment portion is restricted by a second restricting portion from a first movable range in a state in which the move of the holding portion is restricted by the first restricting portion to a second movable range in a state in which the restriction on of the holding portion is released by the releasing portion. The movable range of the second movable range is narrower than a movable range of the first movable range.

1. Field of the Invention
The present invention relates to a sheet stacking apparatus configured to stack a sheet, a sheet feeding apparatus, and an image forming apparatus.
2. Description of the Related Art
Conventionally, an image forming apparatus such as a printer and a copier includes a sheet feeding apparatus including a sheet feeding cassette, i.e., an sheet stacking apparatus, configured to be able to store (stack) a large number of sheets, and a feed roller for feeding the sheets stored in the sheet feeding cassette one by one to an image forming portion of the image forming apparatus. In general, such sheet feeding cassette is provided with a rear end restricting portion restricting a rear end, i.e., an upstream end in a sheet feeding direction in which the sheet is fed of the sheet, and a side end restricting portion restricting a widthwise position orthogonal to the sheet feeding direction of the sheet.
Here, Japanese Patent Application Laid-open No. H09-118439, for example, discloses a sheet feeding cassette including a press member provided in the rear end restricting portion and biased toward the sheet rear end by a biasing portion to position a front end of the sheet to a position where the sheet can be in contact with a sheet feeding roller.
The press member reliably abuts against the rear end of the sheet and a rear end position of the sheet can be thus accurately positioned by configuring such that the press member is biased to the rear end of the sheet as described above. However, there is a case where the rear end restricting portion is set downstream in the sheet feeding direction i.e., to a forward side of the cassette, of a normal position corresponding to a sheet size in trying to set the rear end restricting portion along the rear end of the sheet after placing a regular size sheets in the sheet feeding cassette. That is, there is a case where the rear end restricting portion is set while pushing the sheets placed in the sheet feeding cassette further without being locked at the position restricting the regular size sheet. In such a case, there is a possibility that the press member is pushed in while resisting against a bias force of the bias member and the rear end restricting portion is locked at the position where the press member is pushed in. In this case, the rear end of the sheet is pressed unnecessary by the rear end restricting portion and a front end of the sheet comes into pressure contact with a front wall surface of the sheet feeding cassette. That is, there arises a problem that the sheet is held tightly between the front wall surface of the sheet feeding cassette and the rear end restricting portion, causing a large friction force between the front end of the sheet and the sheet feeding cassette.

Sheet stacking apparatus, sheet feeding apparatus and image forming apparatus


A marine propulsion system includes an outboard powerhead mounted to a horizontal mounting plate within a boat platform recess. A steering arm is attached to a yoke that extends through the transom plate for rotating an attached propeller drive unit. The yoke includes integral fluid paths for hydraulic cylinders coupled to the yoke to pivot the propeller drive unit, and for powerhead cooling water. A removable gearcase plate allows the outboard powerhead, the horizontal mounting plate, the steering arm and the yoke to be pre-assembled and dropped down through the boat platform recess.

This invention relates generally to propulsion systems and, more particularly, to an engine mounting assembly for a marine propulsion system.
Mechanical propulsion systems for propelling watercraft generally are classified as either outboard systems or inboard systems. Outboard systems typically are characterized by an outboard motor mounted to a vertical transom plate located on an outside stern of a boat hull. A propeller drive unit is attached to the motor, or powerhead, and extends from the powerhead into the water to generate thrust and propel the watercraft. Outboard motor systems are versatile, compact, and cost-effective units that are relatively easy to install on the boat hull. Also, because the outboard system is attached to the outside of the hull, the outboard motor system generally does not occupy interior space of the boat hull. However, due to structural constraints of the vertical transom plate mounts of outboard systems, watercraft with outboard systems are typically limited to certain motor capacities within size and weight constraints.
Inboard systems are typically characterized by larger, complicated, and relatively expensive engines in comparison to outboard systems. Inboard system engines are mounted in an engine compartment in a boat hull interior, and a drive unit, or stern drive, extends through a vertical wall of the boat hull into the water to generate thrust and propel the watercraft. Inboard systems, however, are much more complicated to install in a boat hull, which further increases the cost of a watercraft. Furthermore, bulky inboard engines and engine compartments often occupy a substantial amount of interior hull space due to the proximity of the engine compartment to a running surface of the hull.
In an exemplary embodiment of the invention, a removable gearcase plate for a marine propulsion system allows drop down installation of the marine propulsion system through a recess in a platform extending from a boat hull. The gearcase plate includes contoured edges conforming to a shape of a top surface of a gearcase, and covers only a portion of the gearcase top surface. The removable plate is attached to the gearcase adjacent a trunnion that is also attached to the gearcase top surface. After the gearcase is attached to a pre-installed trunnion of the marine propulsion system, the gearcase plate is attached to the gearcase to complete installation.
In an exemplary embodiment, the removable gearcase plate is part of a marine propulsion system including an outboard propulsion system powerhead mounted to a horizontal mounting plate in an outside engine compartment enclosed by an engine cover at a stern of a watercraft. The marine propulsion system includes an upper unit that includes the powerhead and a lower unit that includes a propeller drive unit. A four point mounting assembly eases installation of the upper and lower units and absorbs vibration of the upper and lower units to produce smooth, quiet propulsion of a watercraft. The outboard powerhead is mounted stationary to the horizontal mounting plate, and a steering arm yoke and trunnion assembly is attached to the transom plate and extends outside of the boat hull to maneuver the watercraft.
The outboard powerhead, the horizontal mounting plate, and the steering arm yoke and trunnion assembly are pre-assembled, and the assembly is lowered at least partially through a recess in the platform extending from the boat hull. The transom plate is secured horizontally to the platform above a running surface of the hull. A pre-assembled gear shift mechanism, gearcase, and propeller are then attached to the trunnion, and the removable gearcase plate is attached to the gearcase. Installation is completed by making hydraulic connections for trim, tilt, and steering of the propeller drive unit, and by making appropriate fuel, electrical and control system connections to the various components of the propulsion system.
Thus, the removable gearcase plate facilitates a marine propulsion system that provides the versatility, compactness and cost savings of an outboard powerhead with the stability and performance advantages of an inboard system. Structural limitations and instability of vertical transom plate mounts are avoided by mounting the outboard powerhead to the horizontal mounting plate in the boat hull interior.
Drop down installation of pre-assembled propulsion system components greatly simplifies installation in comparison to conventional inboard systems which, when combined with cost savings of an outboard powerhead, substantially reduces the cost of a completed watercraft. Further, because the outboard powerhead is located outside the vertical wall of the hull, the powerhead does not occupy any interior space available for use and enjoyment by operators, for placement of furniture, or for storage space.


An integrated circuit device has power and ground planes supplied through an interposer secured to the die side. The interposer may consist of a sandwich of metal sheets providing conductive planes for power supply and ground. The planes may be separated by a dielectric which may be designed to provide the necessary decoupling capacitance for the die. The lower of the conductive planes may be of larger surface area and may be adhesively secured to the die, for example, by adhesive tape. The smaller area plane may be secured to the larger area plane through the dielectric layer. With this configuration, each of the conductive planes may be independently wire bonded to the die.

Conventionally, an integrated circuit device receives power from a power supply and ground via a connection to Vss. Normally, the power and ground connections are connected to the integrated circuit device through power and ground planes.
One issue with power and ground planes in modern integrated circuit devices is that they contribute to inductive ringing. In memory devices, ringing due to package self-inductance can slow down the external interface. It is very desirable to minimize the inductive path for the power supply and ground connections to improve the performance of the integrated circuit.
Inductive ringing has been addressed previously by increasing the number of power and ground lines such that each line handles a reduced capacitive load. However, increasing the number of lines may contribute to increased package size, which may also be undesirable. Conventional power supply and ground planes are positioned on the semiconductor die contributing to larger die size. It is desirable to minimize, to the greatest possible extent, the die size to enable smaller integrated circuit devices to be produced.
Another issue with power supply and ground planes is the necessity to provide capacitive decoupling. Commonly, decoupling capacitors are used to provide the necessary decoupling for the integrated circuit device. Again, these decoupling devices add to cost and size.
As integrated circuits shrink, the importance of reducing package inductance will be even greater. Thus, there is a need for techniques to reduce package inductance.

Integrated circuit interposer with power and ground planes


In a variable valve timing apparatus in which a phase of an intake valve is changed at an amount of change according to a rotational speed of relative rotation between an electric motor as an actuator and a camshaft, the set upper limit value of the rotational speed of relative rotation and a coefficient Nθ of conversion from a required phase-change amount to the rotational speed of relative rotation ΔNm in each control period are set at smaller values at the time of engine stop than at the time of engine operation. As a result, the rotational speed of the electric motor in the VVT operation at the time of engine stop is reduced thereby reducing the operation sound of the variable valve timing apparatus.

1. Field of the Invention
The present invention relates to a variable valve timing apparatus and more particularly to a variable valve timing apparatus including an electric motor as an actuator and a control method thereof.
2. Description of the Background Art
VVT (Variable Valve Timing) has conventionally been known that changes the phase (crank angle) in (at) which an intake valve or an exhaust valve is opened/closed, according to an operating condition. Generally, a variable valve timing apparatus changes the phase by rotating, relative to a sprocket or the like, a camshaft that drives the intake valve or exhaust valve to open/close. The camshaft is rotated by such an actuator as hydraulic or electric motor.
Such a variable valve timing apparatus may be operated not only at the time of engine operation but also at the time of engine stop to change a valve timing (valve phase). As for the variable valve timing at the time of engine stop, for example, Patent Publication 1 (Japanese Patent Laying-Open No. 2004-300924) discloses control at the time of engine stop in a variable valve apparatus that continuously changes the valve timing and the valve lift amount by shifting a three-dimensional cam in the direction of a camshaft.
Specifically, the variable valve apparatus disclosed in Patent Document 1 drives valve lift amount change means and also detects the amount of shift of the cam, in a case where the camshaft need to be axially shifted at the time of engine stop. When the detected amount of shift of the cam is smaller than a set value, the driving time of the valve lift amount change means is checked. Then, if the driving time of the valve lift amount change means exceeds the set time, the driving of the valve lift amount change means is stopped thereby saving consumption power to prolong the battery life and preventing overheating resulting from overload to improve the reliability of the system.
Generally, in a vehicle on which an engine is mounted, among a variety of mounted equipment, the engine produces a relatively loud operation sound. Therefore, at the time of engine stop, the passenger is likely to perceive the operation sound of other equipment as unusual sound or noise. Therefore, the likelihood that the passenger perceives the operation sound of the variable valve timing apparatus is also preferably reduced by reducing the operation sound of an actuator such as an electric motor. However, Patent Document 1 never mentions such a problem. Although Patent Document 1 discloses that the driving time of the valve lift amount change means, namely the operation time of the actuator is restricted at the time of engine stop, the document does not make any mention of how to define the operation time.

Variable valve timing apparatus with reduced operation sound and control method thereof


A video processing circuit includes a processor that receives encoded images each having respective first and second regions and that receives a motion vector of the first region of a first one of the images. If the motion vector points to the second region of an image, the processor re-encodes at least a portion of the first region of the first image such that the first region of the first image has no motion vector that points to the second region of an image.

The invention relates generally to image processing circuits and techniques, and more particularly to a circuit and method for formatting each of a series of encoded video images into respective first and second regions. Such formatting facilitates the subsequent overlaying of another image, such as an electronic program guide, onto the video images.
FIG. 1 is a video image 6, which is a video frame that includes a first region 7 and a second region 8. Although described as a video frame for example purposes, the image 6 may also be a video field. Furthermore, although shown as two rectangles in a top-bottom arrangement, the number, shape, and respective locations of these regions is arbitrary.
Typically, one views a sequence of video frames 6 in their respective entireties. But one may sometimes wish to view another image, i.e., an overlay image, in one of the regions 7 and 8. For example, one may wish to view an electronic program guide (EPG) in the region 8 while he/she is watching a program in the region 7 (and also in the region 8 if the EPG is transparent). Or, one may wish to view an internet order menu in the region 8 while he/she is viewing merchandise for sale in the region 7 (and also in the region 8 if the menu is transparent). Thus, the overlay image is typically a partial frame that is the same size as or that is smaller than the frame region that it overlays, although the overlay frame can overlay an entire video frame. But for simplicity, both partial and full overlay frames are referred to as xe2x80x9coverlay framesxe2x80x9d.
FIG. 2 is a block diagram of a conventional television receiver system 10, which includes a set-top box 11 such as a cable TV (CATV) or satellite TV box, a remote control 12, and a digital video display 13. Generally, the box 11 allows one to view overlay imagesxe2x80x94such as those that compose an EPGxe2x80x94in the respective regions 7 of a sequence of video frames 6 (FIG. 1). The box 11 includes a processing circuit 14, which receives an encoded, multiplexed broadcast video signal on an input terminal 15, receives command signals from the remote control 12 on a command terminal 16, and generates a video display signal on an output terminal 17. The broadcast video signal includes one or more broadcast channels and one or more overlay frames such as the frames that compose an EPG, and is encoded according to a compression standard such as the Moving Pictures Experts Group (MPEG) standard (discussed below). In response to channel-select and overlay commands from the remote control 12, the circuit 14 blends the video frames from the selected channel with the appropriate overlay frame or frames and generates the display signal as a sequence of these blended video frames. The display 13 receives the display signal from the terminal 17 and decodes and displays the sequence of blended video frames.
More specifically, the processing circuit 14 includes a command decoder 18, which decodes the commands from the remote control 12 and generates corresponding control signals, such as an overlay signal, that control other portions of the processing circuit 14. A channel selector 20 receives the broadcast signal from the terminal 15 and, in response to a channel-select signal from the command decoder 18, demultiplexes the selected channel from the broadcast signal. In response to an overlay signal from the decoder 18, the selector 20 also demultiplexes the selected overlay frames from the broadcast signal. For example, the selector 20 may demultiplex the EPG that corresponds to the selected channel. A video decoder 22 decodes the video frames of the selected channel into pixel-domain frames, i.e., frames of pixel luminance and chromanance values. In response to the overlay signal, the video decoder 22 also decodes the selected overlay frames into the pixel domain, and an overlay/video combiner 24 blends the decoded video frames with the decoded overlay frames. Conversely, if the command decoder 18 does not generate an overlay signal, then the selector 20 does not demultiplex the overlay frames, and thus the combiner 24 merely passes through the decoded video frames from the decoder 22. In one embodiment, the output terminal of the combiner 24 is coupled directly to the output terminal 17. But because it is sometimes undesirable to couple decoded video frames (blended or unblended) directly to the display 13, in another embodiment the circuit 14 includes an optional re-encoder 26, which re-encodes the decoded video frames from the combiner 24 before providing them to the display 13. Although shown as including a number of separate circuit blocks, the processing circuit 14 may include one or more processors that perform the functions of the above-described circuit blocks 18, 20, 22, 24; and 26.
Still referring to FIG. 2, in operation during a period when a viewer does not want to view an overlay frame, he selects a channel with the remote control 12, which generates a corresponding control signal. The control terminal 16, which is typically an infrared detector, receives the control signal and couples it to the command decoder 18. In response to the control signal, the decoder 18 generates the channel-select signal, which causes the channel selector 20 to recover the encoded video signal of the selected channel by demultiplexing the broadcast signal. The video decoder 22 decodes the recovered video signal into frames of pixel values, and the combiner 24 passes these frames to the optional re-encoder 26, which re-encodes the frames and provides a re-encoded video signal to the display 13. If, however, the re-encoder 26 is omitted, then the combiner 24 passes the decoded frames directly to the display 13.
In operation during a period when the viewer wants to view an overlay frame, he selects a channel as described above and also selects an overlay frame or a series of overlay frames, such as an EPG, with the remote control 12. The decoder 18 generates the channel-select signal and an overlay signal, which together cause the channel selector 20 to recover both the encoded video signal of the selected channel and the encoded video signal containing the overlay frame or frames. The overlay signal causes the video decoder 22 to decode the recovered channel and overlay video signals from the channel selector 20 into respective sequences of frames, and causes the combiner 24 to blend the overlay frames with the channel frames to generate blended frames. The optional re-encoder 26 re-encodes these blended frames and provides them to the display 13, which decodes the re-encoded blended frames. If, however, the re-encoder 26 is omitted, then the combiner 24 provides the blended frames directly to the display 13.
Unfortunately, the set-top box 11 cannot utilize the decoding ability of the display 13, and thus includes its own redundant decoding circuitry, which often adds significant size and cost to the box 11. Typically, the display 13 includes channel-select and full decoding circuitry respectively similar to the channel selector 20 and the decoder 22 of the box 11. Thus, the display 13 typically can directly receive the encoded, multiplexed broadcast video signal, recover the encoded video signal of the selected channel, and decode and display the video frames of the recovered video signal. But the display 13 typically cannot blend overlay frames with the video frames. Therefore, to allow such blending, the box 11 includes the same decoding capability (the decoder 22) as the display 13. The viewer, however, typically requests the display of overlay frames for only a small portion of the time that he/she spends watching a program. Therefore, because the blending abilities of the box 11 are needed only a small part of the time, the decoding abilities of the box 11 are redundant to those of the display 13 most of the time. That is, the viewer paid for two full decoders when one decoder will do the job the vast majority of the time! Furthermore, where it is desired to provide the display 13 with an encoded video signal, the processing circuitry also includes the re-encoder 26, which adds even more size and expense to the box 11!.
To help the reader more easily understand the concepts discussed below in the description of the invention, following is a basic overview of conventional video-compression techniques.
To electronically transmit a relatively high-resolution image over a relatively low-band-width channel, or to electronically store such an image in a relatively small memory space, it is often necessary to compress the digital data that represents the image. Such image compression typically involves reducing the number of data bits necessary to represent an image. For example, High-Definition-Television (HDTV) video images are compressed to allow their transmission over existing television channels. Without compression, HDTV video images would require transmission channels having bandwidths much greater than the bandwidths of existing television channels. Furthermore, to reduce data traffic and transmission time to acceptable levels, an image may be compressed before being sent over the internet. Or, to increase the image-storage capacity of a CD-ROM or server, an image may be compressed before being stored thereon.
Referring to FIGS. 3-6, the basics of the popular block-based Moving Pictures Experts Group (MPEG) compression standards, which include MPEG-1 and MPEG-2, are discussed. For purposes of illustration, the discussion is based on using an MPEG 4:2:0 format to compress video images represented in a Y, CB, CR color space. However, the discussed concepts also apply to other MPEG formats, to images that are represented in other color spaces, and to other block-based compression standards such as the Joint Photographic Experts Group (JPEG) standard, which is often used to compress still images. Furthermore, although many details of the MPEG standards and the Y, CB, CR color space are omitted for brevity, these details are well-known and are disclosed in a large number of available references.
Still referring to FIGS. 3-6, the MPEG standards are often used to compress temporal sequences of imagesxe2x80x94video frames for purposes of this discussionxe2x80x94such as found in a television broadcast. Each video frame is divided into subregions called macro blocks, which each include one or more pixels. FIG. 3A is a 16-pixel-by-16-pixel macro block 30 having 256 pixels 32 (not drawn to scale). In the MPEG standards, a macro block is always 16xc3x9716 pixels, although other compression standards may use macro blocks having other dimensions. In the original video frame, i.e., the frame before compression, each pixel 32 has a respective luminance value Y and a respective pair of color-, i.e., chroma-, difference values CB and CR.
Referring to FIGS. 3A-3D, before compression of the frame, the digital luminance (Y) and chroma-difference (CB and CR) values that will be used for compression, i.e., the pre-compression values, are generated from the original Y, CB, and CR values of the original frame. In the MPEG 4:2:0 format, the pre-compression Y values are the same as the original Y values. Thus, each pixel 32 merely retains its original luminance value Y. But to reduce the amount of data to be compressed, the MPEG 4:2:0 format allows only one pre-compression CB value and one pre-compression CR value for each group 34 of four pixels 32. Each of these pre-compression CB and CR values are respectively derived from the original CB and CR values of the four pixels 32 in the respective group 34. For example, a pre-compression CB value may equal the average of the original CB values of the four pixels 32 in the respective group 34. Thus, referring to FIGS. 3B-3D, the pre-compression Y, CB, and CR values generated for the macro block 10 are arranged as one 16xc3x9716 matrix 36 of pre-compression Y values (equal to the original Y value for each pixel 32), one 8xc3x978 matrix 38 of pre-compression CB values (equal to one derived CB value for each group 34 of four pixels 32), and one 8xc3x978 matrix 40 of pre-compression CR values (equal to one derived CR value for each group 34 of four pixels 32). The matrices 36, 38, and 40 are often called xe2x80x9cblocksxe2x80x9d of values. Furthermore, because it is convenient to perform the compression transforms on 8xc3x978 blocks of pixel values instead of 16xc3x9716 blocks, the block 36 of pre-compression Y values is subdivided into four 8xc3x978 blocks 42a-42d, which respectively correspond to the 8xc3x978 blocks A-D of pixels in the macro block 30. Thus, referring to FIGS. 3A-3D, six 8xc3x978 blocks of pre-compression pixel data are generated for each macro block 30: four 8xc3x978 blocks 42a-42d of pre-compression Y values, one 8xc3x978 block 38 of pre-compression CB values, and one 8xc3x978 block 40 of pre-compression CR values.
FIG. 4 is a block diagram of an MPEG compressor 50, which is more commonly called an encoder. Generally, the encoder 50 converts the pre-compression data for a frame or sequence of frames into encoded data that represent the same frame or frames with significantly fewer data bits than the pre-compression data. To perform this conversion, the encoder 50 reduces or eliminates redundancies in the pre-compression data and reformats the remaining data using efficient transform and coding techniques.
More specifically, the encoder 50 includes a frame-reorder buffer 52, which receives the pre-compression data for a sequence of one or more frames and reorders the frames in an appropriate sequence for encoding. Thus, the reordered sequence is often different than the sequence in which the frames are generated and will be displayed. The encoder 50 assigns each of the stored frames to a respective group, called a Group Of Pictures (GOP), and labels each frame as either an intra (I) frame or a non-intra (non-I) frame. For example, each GOP may include three I frames and 12 non-I frames for a total of fifteen frames. The encoder 50 always encodes an I frame without reference to another frame, but can and often does encode a non-I frame with reference to one or more of the other frames in the GOP. The encoder 50 does not, however, encode a non-I frame with reference to a frame in a different GOP.
During the encoding of an I frame, the 8xc3x978 blocks (FIGS. 3B-3D) of the pre-compression Y, CB, and CR values that represent the I frame pass through a summer 54 to a Discrete Cosine Transformer (DCT) 56, which transforms these blocks of values into respective 8xc3x978 blocks of one DC (zero frequency) coefficient and sixty-three AC (non-zero frequency) coefficients. That is, the summer 54 is not needed when the encoder 50 encodes an I frame, and thus the pre-compression values pass through the summer 54 without being summed with any other values. As discussed below, however, the summer 54 is often needed when the encoder 50 encodes a non-I frame. A quantizer 58 limits each of the coefficients to a respective maximum value, and provides the quantized AC and DC coefficients on respective paths 60 and 62. A prediction encoder 64 predictively encodes the DC coefficients, and a variable-length coder 66 converts the quantized AC coefficients and the quantized and predictively encoded DC coefficients into variable-length codes, such as Huffman codes. These codes form the encoded data that represent the pixel values of the encoded I frame. A transmit buffer 68 then temporarily stores these codes to allow synchronized transmission of the encoded data to a decoder (discussed below in conjunction with FIG. 6). Alternatively, if the encoded data is to be stored instead of transmitted, the coder 66 may provide the variable-length codes directly to a storage medium such as a CD-ROM.
If the I frame will be used as a reference (as it often will be) for one or more non-I frames in the GOP, then, for the following reasons, the encoder 50 generates a corresponding reference frame by decoding the encoded I frame with a decoding technique that is similar or identical to the decoding technique used by the decoder (FIG. 6). When decoding non-I frames that are referenced to the I frame, the decoder has no option but to use the decoded I frame as a reference frame. Because MPEG encoding and decoding are lossyxe2x80x94some information is lost due to quantization of the AC and DC transform coefficientsxe2x80x94the pixel values of the decoded I frame will often be different than the pre-compression pixel values of the I frame. Therefore, using the pre-compression I frame as a reference frame during encoding may cause additional artifacts in the decoded non-I frame because the reference frame used for decoding (decoded I frame) would be different than the reference frame used for encoding (pre-compression I frame).
Therefore, to generate a reference frame for the encoder that will be similar to or the same as the reference frame for the decoder, the encoder 50 includes a dequantizer 70 and an inverse DCT 72, which are designed to mimic the dequantizer and inverse DCT of the decoder (FIG. 6). The dequantizer 70 dequantizes the quantized DCT coefficients from the quantizer 58, and the inverse DCT 72 transforms these dequantized DCT coefficients into corresponding 8xc3x978 blocks of decoded Y, CB, and CR pixel values, which compose the reference frame. Because of the losses incurred during quantization, however, some or all of these decoded pixel values may be different than their corresponding pre-compression pixel values, and thus the reference frame may be different than its corresponding pre-compression frame as discussed above. The decoded pixel values then pass through a summer 74 (used when generating a reference frame from a non-I frame as discussed below) to a reference-frame buffer 76, which stores the reference frame.
During the encoding of a non-I frame, the encoder 50 initially encodes each macro-block of the non-I frame in at least two ways: in the manner discussed above for I frames, and using motion prediction, which is discussed below. The encoder 50 then saves and transmits the resulting code having the fewest bits. This technique insures that the macro blocks of the non-I frames are encoded using the fewest bits.
With respect to motion prediction, an object in a frame exhibits motion if its relative position changes in the succeeding frames. For example, a horse exhibits relative motion if it gallops across the screen. Or, if the camera follows the horse, then the background exhibits relative motion with respect to the horse. Generally, each of the succeeding frames in which the object appears contains at least some of the same macro blocks of pixels as the preceding frames. But such matching macro blocks in a succeeding frame often occupy respective frame locations that are different than the respective frame locations they occupy in the preceding frames. Alternatively, a macro block that includes a portion of a stationary object (e.g., tree) or background scene (e.g., sky) may occupy the same frame location in each of a succession of frames, and thus exhibit xe2x80x9czero motionxe2x80x9d. In either case, instead of encoding each frame independently, it takes fewer data bits to tell the decoder xe2x80x9cthe macro blocks R and Z of frame 1 (non-I frame) are the same as the macro blocks that are in the locations S and T, respectively, of frame 0 (I frame).xe2x80x9d This xe2x80x9cstatementxe2x80x9d is encoded as a motion vector. For a relatively fast moving object, the location values of the motion vectors are relatively large. Conversely, for a stationary or relatively slow-moving object or background scene, the location values of the motion vectors are relatively small or equal to zero.
FIG. 5 illustrates the concept of motion vectors with reference to the non-I frame 1 and the I frame 0 discussed above. A motion vector MVR indicates that a match for the macro block in the location R of frame 1 can be found in the location S of frame 0. MVR has three components. The first component, here 0, indicates the frame (here frame 0) in which the matching macro block can be found. The next two components, XR and YR, together comprise the two-dimensional location value that indicates where in the frame 0 the matching macro block can be found. Thus, in this example, because the location S of the frame 0 has the same X,Y coordinates as the location R in the frame 1, XR=YR=0. Conversely, the macro block in the location T matches the macro block in the location Z, which has different X,Y coordinates than the location T. Therefore, XZ and YZ represent the location T with respect to the location Z. For example, suppose that the location T is ten pixels to the left of (negative X direction) and seven pixels down from (negative Y direction) the location Z. Therefore, MVZ=(0, xe2x88x9210, xe2x88x927). Although there are many other motion-vector schemes available, they are all based on the same general concept.
Referring again to FIG. 4, motion prediction is now discussed in detail. During the encoding of a non-I frame, a motion predictor 78 compares the pre-compression Y values (the CB and CR values are not used during motion prediction) of the macro blocks in the non-I frame to the decoded Y values of the respective macro blocks in the reference frame and identifies matching macro blocks. For each macro block in the non-I frame for which a match is found in the reference frame, the motion predictor 78 generates a motion vector that identifies the reference frame and the location of the matching macro block within the reference frame. Thus, as discussed below in conjunction with FIG. 6, during decoding of these motion-encoded macro blocks of the non-I frame, the decoder uses the motion vectors to obtain the pixel values of the motion-encoded macro blocks from the matching macro blocks in the reference frame. The prediction encoder 64 predictively encodes the motion vectors, and the coder 66 generates respective codes for the encoded motion vectors and provides these codes to the transmit buffer 48.
Furthermore, because a macro block in the non-I frame and a matching macro block in the reference frame are often similar but not identical, the encoder 50 encodes these differences along the with motion vector so that the decoder can account for them. More specifically, the motion predictor 78 provides the decoded Y values of the matching macro block of the reference frame to the summer 54, which effectively subtracts, on a pixel-by-pixel basis, these Y values from the pre-compression Y values of the matching macro block of the non-I frame. These differences, which are called residuals, are arranged in 8xc3x978 blocks and are processed by the DCT 56, the quantizer 58, the coder 66, and the buffer 68 in a manner similar to that discussed above, except that the quantized DC coefficients of the residual blocks are coupled directly to the coder 66 via the line 60, and thus are not predictively encoded by the prediction encoder 44.
Additionally, it is possible to use a non-I frame as a reference frame. When a non-I frame will used as a reference frame, the quantized residuals from the quantizer 58 are respectively dequantized and inverse transformed by the dequantizer 70 and the inverse DCT 72 so that this non-I reference frame will be the same as the one used by the decoder for the reasons discussed above. The motion predictor 78 provides to the summer 74 the decoded Y values of the I reference frame from which the residuals were generated. The summer 74 adds the respective residuals from the circuit 72 to these decoded Y values of the I reference frame to generate the respective Y values of the non-I reference frame. The reference frame buffer 76 then stores the non-I reference frame along with the I reference frame for use in encoding subsequent non-I frames.
Still referring to FIG. 4, the encoder 50 also includes a rate controller 80 to insure that the transmit buffer 68, which typically transmits the encoded frame data at a fixed rate, never overflows or empties, i.e., underflows. If either of these conditions occurs, errors may be introduced into the encoded data stream. For example, if the buffer 68 overflows, data from the coder 66 is lost. Thus, the rate controller 80 uses feed back to adjust the quantization scaling factors used by the quantizer 58 based on the degree of fullness of the transmit buffer 68. The fuller the buffer 68, the larger the controller 80 makes the scale factors, and the fewer data bits the coder 66 generates. Conversely, the more empty the buffer 68, the smaller the controller 80 makes the scale factors, and the more data bits the coder 66 generates. This continuous adjustment insures that the buffer 68 neither overflows nor underflows.
FIG. 6 is a block diagram of a conventional MPEG decompresser 82, which is commonly called a decoder and which can decode frames that are encoded by the encoder 60 of FIG. 4.
For I frames and macro blocks of non-i frames that are not motion predicted, a variable-length decoder 84 decodes the variable-length codes received from the encoder 50. A prediction decoder 86 decodes the predictively encoded DC coefficients, and a dequantizer 87, which is similar or identical to the dequantizer 70 of FIG. 4, dequantizes the decoded AC and DC transform coefficients. An inverse DCT 88, which is similar or identical to the inverse DCT 72 of FIG. 4, transforms the dequantized coefficients into pixel values. The decoded pixel values pass through a summer 90xe2x80x94which is used during the decoding of motion-predicted macro blocks of non-I frames as discussed belowxe2x80x94into a frame-reorder buffer 92, which stores the decoded frames and arranges them in a proper order for display on a video display unit 94. If a decoded I frame is used as a reference frame, it is also stored in the reference-frame buffer 96.
For motion-predicted macro blocks of non-I frames, the decoder 84, dequantizer 87, and inverse DCT 88 process the residuals as discussed above in conjunction with FIG. 4. The prediction decoder 86 decodes the motion vectors, and a motion interpolator 98 provides to the summer 90 the pixel values from the reference-frame macro blocks that the motion vectors point to. The summer 90 adds these reference pixel values to the residuals to generate the pixel values of the decoded macro blocks, and provides these decoded pixel values to the frame-reorder buffer 92. If a decoded non-I frame is used as a reference frame, it is stored in the reference-frame buffer 96.
Referring to FIGS. 4 and 6, although described as including multiple functional circuit blocks, the encoder 50 and the decoder 82 may be implemented in hardware, software, or a combination of both. For example, the encoder 50 and the decoder 82 are often implemented by a respective one or more processors that perform the respective functions of the circuit blocks.
More detailed discussions of the MPEG encoder 50 and decoder 82 of FIGS. 4 and 6, respectively, and of the MPEG standard in general are available in many publications including xe2x80x9cVideo Compressionxe2x80x9d by Peter D. Symes, McGraw-Hill, 1998, which is incorporated by reference. Furthermore, there are other well-known block-based compression techniques for encoding and decoding images.
In one aspect of the invention, a video processing circuit includes a processor that receives encoded images each having respective first and second regions and that receives a motion vector that is associated with the first region of a first one of the images. If the motion vector points to the second region of an image, then the processor re-encodes at least a portion of the first region of the first image such that the first region of the first image has no motion vector that points to the second region of an image.
Such a processing circuit can subdivide each image of a series of images into independent regions, each of which includes references to only the corresponding region in other images. Therefore, if one wishes to modify one of these regions, he need only decode the region and not the entire image. For example, suppose that one wishes to blend an EPG with the same bottom portion of each of a sequence of video frames. He first uses the processing circuit to re-encode these frames such that no motion vectors point between the bottom portion of one frame and the top portion of another frame. He then decodes the EPG and the bottom portions of the frames, blends the decoded EPG and bottom frame portions, and re-encodes the blended frame portions. Because the top portions of the frames need not be decoded or re-encoded, the processing circuit requires less decoding and encoding power, and is thus often faster, cheaper, and has a simpler design than a processing circuit that fully decodes the frames. So that the processing circuit requires even less decoding and encoding power, one can decode the bottom frame portions to the transform domain instead of all the way to the pixel domain.

Circuit and method for formatting each of a series of encoded video images into respective regions


Synchronized data is written to magnetic tape while reducing the number of backhitches. A controller detects a pattern of synchronizing events for received data records to be written to tape; writes each transaction of data records to the magnetic; tape; accumulates the synchronized transactions in a buffer; and subsequently recursively writes the accumulated transactions of data records from the buffer to the magnetic tape in a sequence. A single backhitch may be employed to place the recursively written accumulated data records following the preceding data, maximizing performance and capacity.

Magnetic tape provides a means for physically storing data which may be archived or which may be stored in storage shelves of automated data storage libraries and accessed when required. Data stored in this manner has an aspect of permanence which allows copies of the data stored in memory or disk at a host system to be erased, knowing that a copy exists on magnetic tape. The available storage space at the host system is relatively expensive, and there is a desire to release the storage space as soon as possible. Hence, data is typically transferred through an intermediate staging buffer, such as a hard disk, to the tape drive, and there is also a desire to release and overwrite the staging buffer as soon as possible.
Thus, it is often desirable to "synchronize" the data.
"Synchronized data" is defined as data or other information which is subject to a "synchronizing event" or similar command requiring the tape drive to not return "Command Complete" to a write type of command, or an indication that the command has been or will be successfully executed, until it has actually committed the data to media, specifically, the magnetic tape. As the result, if power is lost, the data can be recovered from the tape, whereas it may not be recoverable from a volatile DRAM storage of the tape drive buffer.
One example of a synchronizing event is a Write Filemark command with the Immediate bit set to "0". This means that the drive is not to respond immediately, but instead is to respond when the command has completed, meaning that any data sent as part of the command is written out to tape. A specialized case of a Write Filemark command is where the number of Filemarks field is also set to "0", meaning that the Write Filemark command has no data of its own, and all data which precedes the command must be written to tape before a command complete is sent. Hence, this command is often referred to as a "Synchronize" command, as is known to those of skill in the art.
Another example of a synchronizing event is a host selectable write mode known to those of skill in the art as "non-buffered writes", where an implicit synchronize must be performed after each record is written from the host. "Command Complete" is not returned for any write command until the data is successfully written on media.
Herein, writing any data record, group of records, or other mark, is defined as a "transaction", and writing such data record, etc., as the result of a synchronizing event is defined as a "synchronized transaction".
A difficulty with respect to magnetic tape is that the data is recorded sequentially without long gaps between data sets, whereas synchronized transactions are stored in separate bursts for each synchronizing event, with a noticeable time period before writing the next transaction. This requires that the tape drive "backhitch" after writing the synchronized transaction in order to write the next transaction closely following the preceding transaction. Tape is written or read while it is moved longitudinally at a constant speed. Hence, a backhitch requires that the tape be stopped, reversed to beyond the end of the previous transaction, stopped again, and accelerated up to speed in the original direction by the time that the end of the previous transaction is reached. As is understood by those of skill in the art, the backhitch process consumes a considerable amount of time, and, if a large number of small synchronized transactions are to be stored, the throughput of the tape drive is reduced dramatically. As an example, backhitch times can vary from about half a second to over three seconds.

Writing synchronized data to magnetic tape

International Business Machines Corporation