A serial number detection portion simultaneously transmits a detection command for requesting a first digit of a serial number to plurality of indoor units, and the serial number detection portion simultaneously transmits a detection command for requesting a second digit immediately preceding the first digit to the indoor units when a response to the detection command is absent. That is, the address setting is performed again from the immediately preceding digit without returning to an initial digit of the serial number, so that the time necessary for the address setting can be shortened. When the address setting is performed again from the immediately preceding digit, the address setting can be performed more securely by changing a method of recognizing the detection command in the indoor units.

In the case where one outdoor unit controls plurality of indoor units, it is necessary that addresses be set at the indoor units in order to transmit a control signal. The same holds true for the case in which one remote controller transmits the control signal to the plurality of indoor units.
In the conventional air conditioner, the outdoor unit or the remote controller requests a unique serial number of each indoor unit in each digit, the indoor unit responds to a number of the requesting digit, to detect the serial number, and the address setting is performed to the indoor unit having the serial number.
During the address setting, when the address setting is not normally performed because the indoor unit cannot normally receive a command for requesting a predetermined digit of the serial number due to a noise or ringing or the like, the address setting starts over by returning to the initial digit to detect the serial number again. For example, Patent Documents 1 to 3 disclose a technique concerning the address setting of the air conditioner.
Patent Document 4 also discloses a technique of preventing reception failure caused by the noise. In the technique disclosed in Patent Document 4, a whole time and a low time of a pulse signal are detected, and the whole time and the low time are compared to reference times to detect a start bit signal.    Patent Document 1: Japanese Patent Application Laid-Open No. 9-196443    Patent Document 2: Japanese Patent Application Laid-Open No. 9-257295    Patent Document 3: Japanese Patent Application Laid-Open No. 2000-74461    Patent Document 4: Japanese Patent Application Laid-Open No. 6-181592

Air conditioner and address setting method in air conditioner


A method provides a recessed isolation is provided in a semiconductor substrate by (a) growing a first field oxide, (b) selectively removing portions of the first field oxide to leave recessed areas in the semiconductor substrate, and (c) growing a second field oxide from the recessed areas in a controlled manner, so that the surface of the semiconductor substrate is substantially planar. In one embodiment, nitride spacers are provided to limit lateral encroachment by the second field oxide from encroaching the active areas of the semiconductor substrate.

1. Field of the Invention
The present invention relates to integrated circuit manufacturing; in particular, the present invention relates to methods for isolating devices on an integrated circuit.
2. Discussion of the Related Art
Local oxidation of silicon (LOCOS) has been widely used for isolating active components fabricated on the surface of a semiconductor substrate. Typically, LOCOS is used to create a region of electrically insulating silicon oxide, usually referred to as "field oxide", between two regions ("active regions" or "island regions") in which circuit elements or devices are fabricated. Without proper control, LOCOS creates an oxide region which grows not only in the vertical direction but also laterally. Thus, a field oxide formed under LOCOS suffers from two disadvantages. First, the field oxide "encroaches" into the active regions, forming a tapering structure (commonly referred to as a "bird's beak") extending into the active regions. Consequently, active regions have to be given additional area to compensate for this encroachment, such that the device density achievable in the integrated circuit is adversely affected. Second, the field oxide grows vertically, so that the semiconductor surface lacks planarity. Maintaining planarity is essential to successful fabrication of modern complex integrated circuits.
Various approaches are known in the prior art to enhance planarity. In one technique, known as recessed isolation, a groove or trench of predetermined depth is cut by an anisotropic etch into the semiconductor substrate. Under that approach, the field oxide is grown by LOCOS from the bottom of the groove or trench. Since it is grown from a recessed position, the resulting field oxide does not disrupt surface planarity as its non-recessed counterpart. However, because this approach requires an etching of silicon to create the trench or groove, undesirable damage to the semiconductor surface may result.
Various approaches have also been attempted in the prior art to limit the field oxide's encroachment into an active region. In one such technique, an oxidation resistant material, such as nitride or certain polymers, is provided on the side walls of the groove or trench, so as to check the lateral growth of the field oxide. Such techniques tend to require a high degree of process control to deliver the intended result.

Recessed isolation with double oxidation


In a semiconductor circuit apparatus and its test method according to embodiments of the present invention, the clock enable control circuit can generate in a test mode an enable clock signal by using the substitute enable signal instead of the enable signal output from the enable signal generation combinational circuit and supplies it to the enable input terminal of the sequential circuit. Accordingly, with the simple structure in which the substitute enable signal is used, a proper enable clock signal can be generated and a scan test can be performed by reliably setting the sequential circuit to the enable state.

1. Field of the Invention
The present invention relates to a semiconductor circuit apparatus and its test method, the semiconductor circuit apparatus having a plurality of combinational circuits for executing various logical calculations and sequential circuits such as flip-flops for executing a full scan test to test functionalities of the combinational circuits.
2. Description of Related Art
Various techniques have been proposed to detect defects of a variety of LSI's (e.g., refer to Japanese Patent Publication No. 2628154, Japanese Patent Laid-open Publication No. H10-123223). As one of these methods, an ATPG (automatic test pattern generation) method is known, which uses a full scan test by flowing a predetermined test pattern to all flip-flops in a circuit under the conditions that the flip-flops can be controlled and the outputs thereof can be observed, thereby observing the operation result of each logical circuit.
With this method, however, if the number of measurement points is increased in order to improve a defect detection rate, the number of flip-flops for the measurement purposes and the number of external terminals for output observation are required to be increased, resulting in a bulky scale caused by a complicated structure and an increased circuit space.
In the following description, a circuit for executing a logical calculation of an input value and outputting a unique output value is called a "combinational circuit" as its generic concept, and a circuit such as a flip-flop including a time sequential transition operation is called a "sequential circuit" as its generic concept.
It is desired for recent LSI's to adopt the mechanism of stopping an unnecessary clock in order to reduce a consumption power. For this structure, more complicated logical circuits are combined to finely control the supply/stop of the clock by using a clock enable signal.
The above-described ATPG method using the full scan test performs two operations, a shift operation of flowing a test pattern to each flip-flop and a capture operation of finding an actual detect in the state that logical circuits perform a normal operation. In the shift operation, it is designed such that a clock is always input to each flip-flop to be scanned, whereas in the capture operation, a clock line is not controlled at all, but the clock is controlled only by a test pattern to be flowed in the shift operation.
However, if the clock line is provided with a complicated circuit for controlling clock enable in order to reduce a consumption power as described above, it is necessary to form a test pattern by considering logic of both a test pattern for supplying a clock and a test pattern for identifying a detect. This results in drawbacks such as complicated test patterns, the increased number of defects unable to be properly detected, and a longer time to prepare the test pattern, thereby causing decrease in efficiency in circuit design and increase of production cost.
FIG. 4 is a block diagram showing an example of the structure of an LSI circuit having control circuits for the above-described clock enable (so-called clock enablers).
In this figure, a combinational circuit 110 is a circuit made of a logical circuit group for executing predetermined logical calculations. Input and output stages of the combinational circuit are provided with flip-flops 121, 122, 123 and 124 and selectors 131, 132, 133 and 134 for selecting data input to the respective flip-flops 121, 122, 123 and 124 between a normal mode and a test mode. By switching the selectors 131, 132, 133 and 134, for example, data transfer is possible without passing through the combinational circuit 110 to and from the respective flip-flops 121, 122, 123 and 124.
Combinational circuits 141, 142, 143 and 144 are provided at the input stages of the flip-flops 121, 122, 123 and 124 to generate enable signals for the flip-flops 121, 122, 123 and 124. Clock enablers 151, 152, 153 and 154 are provided at the output stages of the combinational circuits 141, 142, 143 and 144 to control supply/stop of a clock to the flip-flops 121, 122, 123 and 124.
The combinational circuits 142 and clock enabler 152 control the flip-flops 121 and 122 at the input stage of the combinational circuit 110, and the combinational circuit 141 and clock enabler 151 control another flop-flop 125.
The combinational circuits 143 and 144 and clock enablers 153 and 154 are an example of a multi-stage circuit for controlling the flip-flops 123 and 124 at the output stage of the combinational circuit 110.
FIG. 5 is a block diagram showing a clock enabler to be used with the circuit shown in FIG. 4.
A clock enabler 210 is disposed between a combinational circuit 200 for generating an enable signal and a flip-flop (omitted in FIG. 5) for scan test. The clock enabler 210 is constituted of an OR circuit 211, a latch circuit 212 and an AND circuit 213. The OR circuit 211 generates an OR between an enable signal E output from the combinational circuit 200 and a shift scan control signal SE which is a timing signal in the shift operation. The latch circuit 212 latches an output signal from the OR circuit 211. The AND circuit 213 generates an AND between an output of the latch circuit 212 and a clock signal CK, as an enable clock signal ECK which is supplied to the enable input terminal of the flop-flop.

Semiconductor circuit apparatus and test method thereof


[Object] To enable the communication device that has received a response frame to determine whether or not the response frame is a signal of the own BSS, while ensuring downward compatibility.

In recent years, a working group of IEEE802.11, and the like have been considering standardization of a new wireless LAN, which includes consideration of a method for setting a transmission prohibition period (hereinafter referred to as "network allocation vector (NAV)" for convenience).
Patent Literature 1 discloses a setting method and a canceling method for NAVs based on a transmission request frame (hereinafter referred to as "request to send (RTS)" for convenience) or a reception preparation completion frame (hereinafter referred to as "clear to send (CTS)" for convenience).

Communication device, communication control method, and program

Abstract: [Solution] Provided is a communication device including: a generation unit configured to generate a response frame prescribed in IEEE802.11 by setting a value corresponding to a BSS to which the own device belongs in a receiving station address field of the response frame; and a transmission unit configured to transmit the response frame.


A method, associated apparatus and program product for partitioning a plurality of interconnection elements among disjoint partitions of processors in a computer system so as to interconnect the processors within each of the disjoint partitions, and to isolate the processors in each interconnected partition from processors in the other partitions. The interconnection elements may be arranged into groups including node coupling elements and link coupling elements and in larger systems may include intermediate groups having intermediate coupling elements. The partitioning of the interconnection elements begins with the interconnection of processors in the largest disjoint partition and proceeds by connecting the successive largest processor partitions whose interconnection elements share a group with the interconnect elements used for the previously interconnected processor partitions until no such interconnect elements on shared groups remain, subsequently the process is repeated until all processors in the disjoint partitions are interconnected.

Parallel computer systems have proven to be an expedient solution for achieving greatly increased processing speeds heretofore beyond the capabilities of conventional computational architectures. With the advent of massively parallel processing machines such as the IBM RS/6000 SP1 and the IBM RS/6000 SP2, volumes of data may be efficiently managed and complex computations may be rapidly performed. (IBM and RS/6000 are registered trademarks of International Business Machines Corporation, Old Orchard Road, Armonk, N.Y., the assignee of the present application).
A typical massively parallel processing system may include a relatively large number, often in the hundreds or even thousands of separate, though relatively simple, microprocessor-based nodes which are interconnected via a communications fabric comprising a high speed packet switch network. Messages, in the form of packets are routed over the network between the nodes enabling communication therebetween. The nodes typically comprise a microprocessor and associated support circuitry such as random access memory (RAM), read only memory (ROM), and input/output I/O circuitry which may further include a communications subsystem having an interface for enabling the node to communicate through the network.
Among the wide variety of available forms of packet networks currently available, perhaps the most traditional architecture implements a multi-stage interconnected arrangement of relatively small cross point switches, with each switch typically being an N-port bi-directional router where N is usually either 4 or 8 and with each of the N ports internally interconnected via a cross point matrix. For our purposes herein, we will consider the switch to be an 8 port router switch. In such a network, each switch in one stage, beginning at one side (so-called input side) of the network is interconnected through a unique path (typically a byte-wide physical connection) to a switch in the next succeeding stage, and so forth until the last stage is reached at an opposite side (so called output side) of the network. The bi-directional router switch included in this network is generally available as a single integrated circuit (i.e. a "switch chip") which is operationally non-blocking, and accordingly a popular design choice. Such a switch chip is described in the U.S. patent application having Ser. No. 08/424,824, now U.S. Pat. No. 5,546,391, entitled "A Central Shared Queue Based Time Multiplexed Packet Switch With Deadlock Avoidance" by P. Hochschild et al. filed Mar. 4, 1996, (still pending and commonly assigned to the present assignee hereof).
A switching network typically comprises a number of these switch chips organized into two interconnected stages, for example: a four switch chip input stage followed by a four switch chip output stage, all of the eight switch chips being included on a single switch board. With such an arrangement, messages passing between any two ports on different switch chips in the input stage would first be routed through the switch chip in the input stage that contains the source or input port, to any of the four switches comprising the output stage and subsequently, through the switch chip in the output stage the message would be routed back (i.e. the message packet would reverse its direction) to the switch chip in the input stage including the destination (output) port for the message. Alternatively, in larger systems comprising a plurality of such switch boards, messages may be routed from a processing node, through a switch chip in the input stage of the switch board to a switch chip in the output stage of the switch board and from the output stage switch chip to another interconnected switch board (and thereon to a switch chip in the input stage). Within an exemplary switch board, switch chips that are directly linked to nodes are termed node switch chips (NSCs) and those which are connected directly to other switch boards are termed link switch chips (LSCs). Inter-switch chip routing is typically pre-defined during system initialization and rarely ever altered thereafter.
Switch boards of the type described above may simply interconnect a plurality of nodes, or alternatively, in larger systems, a plurality of interconnected switch boards may have their input stages connected to nodes and their output stages connected to other switch boards, these are termed node switch boards (NSBs). Even more complex switching networks may comprise intermediate stage switch boards which are interposed between and interconnect a plurality of NSBs. These intermediate switch boards (ISBs) serve as a conduit for routing message packets between nodes coupled to switches in a first and a second NSB. For purposes of the ensuing discussion, the switch chips located on these ISBs will be termed intermediate switch chips (ISCs).
In massively parallel processing systems, it is a popular implementation choice to partition the processing nodes of the system so as to establish multiple smaller parallel processing systems within the massively parallel processing system. Disjoint sets of the processing nodes of the massively parallel system are located exclusively within one of the plurality of smaller system partitions and cannot share communication paths with the sets of nodes residing in other system partitions.
The U.S. patent application having Ser. No. 08/664,990 entitled "System Partitioning for Massively Parallel Processors" by Brenner et al. (still pending and commonly assigned to the present assignee) as well as the pending, cross-referenced U.S. patent applications having Ser. Nos. 08/664,577 entitled "Method and Apparatus for Creating Persistent Isolated Sub-Environments in a Massively Parallel Processing System", 08/664,580 entitled "An Apparatus and Method for Creating Isolated Sub-Environments Using Host Names and Aliases", and 08/664,689 entitled "Use Of Daemons in a Partitioned Massively Parallel Processing System Environment" all by Brenner et al. and all commonly assigned to the present assignee, are directed toward creating node-based system partitions in a massively parallel processing system, and while they are not directed toward providing a method and apparatus for efficiently allocating the switching fabric of the massively parallel processing system among the system partitions, they do provide an excellent background for the present invention, and as such, are incorporated herein by reference.
Partitioning of multinode systems provides the user with the ability to completely isolate computing environments within the parallel processing system from one another. This ability to carve out isolated smaller partitions of processors from a larger processing system has proven advantageous for a variety of system implementations. For example, a test environment for a new beta-level version of an operating system may be run on the same system, but in a system partition which is completely isolated from a production environment operating system operating on a different system partition. Moreover, in designing optimized computing environments within a single partitioned parallel processing system, the cross-over of packet traffic from a first partition to the switches of a second partition may degrade the performance of the computing environment associated with the shared switches. For example, a plurality of processing nodes in the massively parallel processing system may be used for processing a parallel data base system, while the remaining nodes are used to process another, time critical, parallel processing application. While the massively parallel processing system can accommodate the concurrent execution of both of these jobs, each job that is executed competes for a limited set of node and switch resource. In a switching fabric of a massively parallel processing system utilizing a high performance switch it is possible for one job to monopolize the switch resource and thereby degrade the performance of the other job. Accordingly, to ensure optimal performance for concurrently operating computing environments within a single parallel processing system, disjoint partitioning of the switching resource among the disjoint system partitions must be implemented in a manner which ensures that each system partition makes the most efficient use of its allocated switching resource.
Massively parallel processing machines have previously been implemented so as to provide the user with a pre-defined static set of partition configurations incorporating many constraints. For example, in the case of the RS/6000 SP2, prior to the present invention, a maximum of only three partitions were permitted and the smallest partition would typically be set at all processing nodes connecting to a single NSB. The switch resource partitioning and allocation techniques presented herein advantageously free a system administrator to implement customized partitions within a parallel processing system which may not be included within the previously provided static configuration set, as well as providing system optimization capabilities.
From the foregoing it is clear that in order to accommodate a flexible partitioning of parallel processing systems, the switch network must likewise be capable of being flexibly partitioned among the system partitions to provide communication links between nodes within the same partition while ensuring that communication paths between nodes in different partitions do not intersect. Since a number of physical constraints exist for allocating resources on the switch network to system partitions, implementation of this partitioned switching network creates resource allocation problems which increase in complexity as the number of nodes in the system increases.
A number of generally applicable resource partitioning schemes have been implemented in computer systems. For example, U.S. Pat. No. 5,036,473 entitled "Method For Using Electronically Reconfigurable Logic Circuits" by Butts et al. describes a hierarchical partitioning scheme for a reconfigurable interconnection of logic chips. The system is designed to be partitioned into multiple clusters in accordance with a partitioning hierarchy which assigns design primitives to a box, board and logic chip, while satisfying system constraints. The hierarchical partitioning methodology initially places all primitives into a null cluster, and proceeds to form clusters by selecting a seed primitive from the null cluster and by moving primitives having the highest advantage function (a function that is specific to this implementation) into a cluster until it is full. This partitioning method is focused upon satisfying very specific system constraints, and proceeds by assigning the smallest logical levels of the system to build clusters which ultimately define the partitioned structure of the system. The partitioning method is a logic partitioning method rather than a solution for allocating switching resource among disjoint processing node partitions. Moreover, while the disclosed methodology for building logic partitions on a logic element-by-logic element basis is well suited for the logic design described in Butts et al., it would prove error-laden and time consuming in other partitioned systems. For example, in systems in accordance with the focus of the present invention in which sets of disjoint nodes have been previously partitioned and wherein it is desired to optimize switch partitioning to allocate disjoint sets of switches to each node partition, an element-by-element method for the creation of switch partitions would require numerous attempts before achieving a workable albeit less than optimal switch partition allocation.
An article entitled Programmable Interconnection Switch Structure for Large Scale Machine Prototyping, published in The IBM Technical Disclosure Bulletin (TDB) Vol. 35, No. 1A June 1992 describes a method and system for providing a prototype environment for large scale digital system design. The article proposes the use of "soft-chips" such as field programmable gate arrays (FPGAs) to create a prototype system partitioned into "islands" of logic function used to create connections to switch chips. Signals traversing a switch chip from a logic source to a destination require one input pin and one or more output pin on the chip. Multiple routes may be stored and implemented over the shared connection resource on a time shared basis. A switch chip in this system may participate in any number of routes and is not constrained as in typical partitioned parallel processing systems to exclusive use within a single partition. Accordingly, the TDB does not offer a scheme for creating disjoint partitions as is required in a partitioned massively parallel processing system.
In a more recent TDB article entitled Multi-Stage Interconnection Network Topologies for Large Systems (IBM TDB Vol. 38 No. 10 October 1995), topologies for systems having 129-512 nodes are presented. The TDB discusses the inclusion of NSBs and ISBs of the type previously described, and a method for connecting them in 256 and 512 way systems, however it does not address the issue of partitioning the switching network to allocate switches among system partitions.
It is apparent from the foregoing that a mechanism for managing resource allocation by partitioning a switch network so as to accommodate disjoint partitions of processing nodes in a partitioned parallel processing system would prove useful to a system administrator attempting to manage a partitioned multinode system. Moreover, a need exists for such a mechanism in which implementation of the switch partitioning and allocation is balanced, optimal and satisfies a wide range of system partition configurations. These requirements as well as other advantageous features are addressed by the present invention.

Method and apparatus for partitioning an interconnection medium in a partitioned multiprocessor computer system


Systems and methods for facilitating physiological coherence using respiratory training are disclosed. In one embodiment, an optimal respiratory cycle and/or RSA pattern is determined. A subject is then trained to adhere to this optimal respiratory level using one or more breath indicators. In another embodiment, the timing sequence of the breath indicators is optimized for a given subject's reaction time and/or atypical breathing events. In yet another embodiment, a subject's respiratory rhythms are used to detect their emotional state and corresponding feedback provided.

1. Field of the Invention
The invention relates to facilitating physiological coherence (also referred to as entrainment or resonance) and more particularly, to systems and methods for using respiration-training or mental/emotional self-management techniques to achieve physiological coherence and/or entrainment. Systems and methods for monitoring respiration patterns to detect emotional/stress state are also disclosed.
2. Background of the invention
With the growing complexity of life, the relation between physiological conditions and emotional health becomes of increasing interest and importance. Many studies have shown that stress and other emotional factors increase the risk of disease, reduce performance and productivity and severely restrict the quality of life. To this end, the medical communities around the world continually seek remedies and preventive plans. Recently, a focus on the self-regulation of systems within the body has led to research in the areas of increasing performance and facilitating recovery from numerous health challenges. Such research has suggested a causal link to, for example, enhanced academic performance, communication and listening skills, faster reaction times and better coordination.
In the last 25 years, a variety of new techniques have been introduced as alternatives to more traditional psychotherapies or pharmaceutical interventions for improving mental and/or emotional imbalances, reducing stress and improving performance. In addition to the more psychological approaches like cognitive re-structuring and neurolinguistic programming, psychologists have employed several techniques from Eastern cultures to "still the mind" during focused meditation. In yoga, for example, one generally focuses on the breath or parts of the brain, whereas in qigong one focuses on the "dan tien" point (below the navel). In the Freeze Frame® (FF) and other related techniques, developed by the Institute of Heart Math in Boulder Creek, Calif., one focuses attention on the area around the heart. All these techniques focus attention upon areas of the body which are known to contain separate but interacting groups of neuronal processing centers, and biological oscillators with which they interact. The heart, brain, and the intestines contain biological oscillators known as pacemaker cells. By intentionally focusing attention on any one of these oscillator systems, one can alter its rhythms. This is at least true for the brain (meditation), yogic breathing (respiration) and other cognitively-directed paced-breathing techniques, the heart (Freeze-Framer (FF) and other HeartMath techniques), and most likely the gut (qigong). The body also contains other oscillating systems such as the smooth muscles of the vascular system. In U.S. Pat. No. 6,358,201, entitled "Method and Apparatus for Facilitating Physiological Coherence and Autonomic Balance," which is assigned to the assignee hereof and hereby incorporated fully by reference, it was shown that the body's systems such as blood pressure rhythms (measured by recording pulse transit time (PTT), the heart (measured by a heart rate variability (HRV)), and the respiration system (measured by the respiration rate) can all entrain. Furthermore, they all synchronize to a frequency varying around 0.1 Hertz (Hz). Thus, one can intentionally bring these systems, acting as coupled biological oscillators, into synchronization with each other. In addition, in this coherent or resonant mode, several brain rhythms (measured by an electroencephalograph (EEG)) become more synchronized to the heart.
By applying spectral analysis techniques to the HRV waveform, its different frequency components, which represent the activity of the sympathetic or parasympathetic branches of the autonomic nervous system, can be discerned. The HRV power spectrum is divided into three frequency ranges or bands: very low frequency (VLF), 0.033 to 0.04 Hz; low frequency (LF), 0.04 to 0.15 Hz; and high frequency (HF), 0.15 to 0.4 Hz.
The high frequency (HF) band is widely accepted as a measure of parasympathetic or vagal activity. The peak in this band corresponds to the heart rate variations related to the respiratory cycle, commonly referred to as respiratory sinus arrhythmia (RSA). Reduced parasympathetic activity has been found in individuals under mental or emotional stress, suffering from panic, anxiety or worry, depression, high blood pressure, heart disease and many other disorders. As such, previous RSA training approaches have focused on increasing the HF peak in the HRV power spectrum. The low frequency (LF) region can reflect both sympathetic and parasympathetic activity, especially in short-term recordings.
While the FF technique described in previously incorporated U.S. Pat. No. 6,358,291 is a self-management technique which focuses on the heart, the respiratory cycle may also be linked to mental/emotional state and can be used to achieve physiological coherence and/or entrainment. Thus, there is a need to provide a method and apparatus for optimizing the respiratory cycle and RSA pattern in a manner that facilitates physiological coherence.

Systems and methods for facilitating physiological coherence using respiration training


The present invention provides a titanium-made plate-type heat exchanger comprising first-fluid flow paths and second-fluid flow paths arranged alternately, which is formed by joining titanium-made constituting members, wherein: a titanium-zirconium based brazing solder containing 20 to 40 wt. % of titanium and 20 to 40 wt. % of zirconium, which melts under 880° C., is coated over positions to be connected of the constituting members, and brazing solder coated constituting members are heated under 880° C. in an vacuum and/or inert gas atmosphere. The present invention also provides a production method of the heat exchanger, which can prevent titanium-made constituting members of the heat exchanger from being deteriorated due to over-heating.

1. Field of the Invention
The present invention relates to a production method of a titanium-made plate-type heat exchanger.
2. Related Art
A conventional titanium-made plate-type heat exchanger is disclosed in Japanese laid open patent No.2002-35929. In the heat exchanger by this invention, herringbone patterned titanium plates are layered such that herringbone patterns of the neighboring plates are arranged in opposite directions each other, and first-fluid flow paths and second-fluid flow paths formed by gaps between the two neighboring plates are alternately arranged so that heat is exchanged between the two fluids.
The above-mentioned heat exchanger is produced according to the following steps: positions to be connected on respective herringbone plates are coated with or filled by a brazing solder; the coated or filled plates are placed in a vacuum heating furnace and the plates are degassed as reducing the pressure of the furnace and gradually raising the temperature of the furnace; and after a required reduced pressure is attained, coated or filled positions are brazed by heating the plates over 850° C.
However, the conventional titanium-made plate-type heat exchanger has the following problems.    (1) Since herringbone patterns are formed by concave strips with a chevroned cross section, two neighboring plates are contacted on concave edge points of respective concave strips crossing each other. Consequently, connected positions by the brazing solder show a point to point connection pattern so that a connected strength between the neighboring plates is low. As a result, a pressure-resistant performance of the flow paths of the heat exchanger is not so good.    (2) Since a heat transfer area of fluid flow paths formed by the two herringbone plates corresponds to surface areas of the herringbone plates, a heat transfer area per unit volume of the heat exchanger is not so large. Consequently, a heat radiating performance of the flow paths is not so good.    (3) When the plates are brazed at a temperature more than the transformation temperature (882° C.) of α-titanium, the herringbone plates are deteriorated, which means a durability of the heat exchanger is deteriorated.
And in producing the conventional titanium-made plate-type heat exchanger, since the herringbone plates are brazed over 850° C., they are deteriorated. Because when the brazing solder is heated over 850° C., sometimes the titanium-made plates are heated over the transformation temperature (882° C.) of α-titanium so that these plates are deteriorated.
The present invention is carried out in order to solve the problems mentioned above, and provides:    (1) A production method of a titanium-made plate-type heat exchanger having fluid flow paths with a pressure resistant performance, an excellent heat radiating performance and an excellent durability;    (2) A method to produce a titanium-made plate-type heat exchanger capable of preventing titanium members constituting the fluid flow path from deteriorating due to over-heating.

Titanium-made plate-type heat exchanger and production method therefor


Pre-paid transaction card systems and methods are described. A transaction system can include a transaction database to store transaction objects that represent characteristics of a pre-paid transaction card. A deal engine communicatively coupled with the transaction database can receive an image of a marker-less portion of the transaction card and derive a set of image descriptors from the marker-less portion. The deal engine can also identify transaction characteristics associated with the card from the transaction database using the image descriptors. In addition, the deal engine can construct a deal recommendation based on the transaction characteristics previously identified. The deal recommendation can be transmitted to a user, and in some cases, displayed to the user as an augmented reality image.

The following description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
Pre-paid transaction cards have become a popular way of gifting money and engaging in financial transactions. Pre-paid transaction cards provide many advantages over other transaction methods. For example, pre-paid transaction cards can have a limited purchasing value that is disconnected from the user's other accounts. This allows the user to control the amount of spending and protects the user's other accounts from theft. Pre-paid transaction cards are also very convenient to use since it eliminates the need to exchange hard currency or write a check. In addition, debit and credit events are performed digitally, which allows for automatic balance calculations and easy electronic tracking of purchases.
One disadvantage of pre-paid transaction cards is that, in the context of gifting, a pre-paid gift card may not produce the same level of surprise and excitement as a wrapped gift. Some effort has been directed toward this problem. For example, US Patent Application No. 2011/0055049 to Harper et al. describes a system that provides an augmented reality experience in connection with a gift card. The system receives an image of the gift card, searches for a marker on the gift card, and uses the marker to track the position of the card. The system can then create an augmented view of the gift card in a user display, such as by placing a graphical representation of a consumer good or service next to the gift card image. While advantageous in some aspects, the system in Harper is limited in application to only those transaction cards that have markers. In addition, the system in Harper fails to leverage user data such as transactional histories, user preferences/profiles, and gifting scenarios, to provide targeted deal offers.
What is needed is a transaction system that manages transactional and user-related information, generates personalized deal recommendations, and displays the recommendations to the user in a fun and exciting way.
Harper and all other publications and extrinsic materials identified herein are incorporated by reference in their entirety, to the same extent as if each individual publication or patent application were specifically and individually indicated to be incorporated by reference. Where a definition or use of a term in an incorporated reference is inconsistent or contrary to the definition of that term provided herein, the definition of that term provided herein applies and the definition of that term in the reference does not apply.
Thus, there is still a need for pre-paid transaction card systems and methods.

This patent is subject to a terminal disclaimer.

Augmented pre-paid cards, systems, and methods


A compressor includes a casing, a compression mechanism, a drive shaft, a main frame, a motor, a flow path forming member, and a temperature measuring mechanism. The casing stores lubricating oil in its bottom portion. The main frame has the compression mechanism placed on it and supports the drive shaft in such a way that the drive shaft may freely rotate. The flow path forming member forms an oil flow path at a space adjacent an inner peripheral surface of the casing. The oil flow path carries a flow of lubricating oil, which lubricates sliding portions including the compression mechanism and the drive shaft. The temperature measuring mechanism is disposed outside the casing. The temperature measuring mechanism measures the temperature of a section of an outer peripheral surface of the casing adjacent the oil flow path.

Conventionally, in order to ensure the reliability of a compressor that configures the refrigeration cycle of an air conditioning apparatus or the like, a compressor protection device that prevents an abnormal rise in the temperature inside the compressor has been used. The compressor protection device is configured from a temperature detecting mechanism and an operation shutdown mechanism, the example. The temperature detecting mechanism is attached to the compressor body and measure the temperature inside the compressor. The operation shutdown mechanism performs an action to protect the compressor by shutting down the operation of the compressor in a case where the temperature that the temperature detecting mechanism has detected has exceeded a predetermined temperature.
It has been conventionally common for the temperature detecting mechanism to measure the surface temperature of a casing of the compressor or the surface temperature of a discharge tube that sends compressed refrigerant to a refrigerant circuit outside the compressor. For example, in the compressor described in Japanese Unexamined Publication No. 2009-197621, there is disposed a temperature sensor holding mechanism for closely fixing a temperature sensor to the surface of the top portion of the casing of the compressor. With this temperature sensor holding mechanism, the temperature sensor can be reliably installed in a predetermined position on the surface of the top portion of the casing of the compressor. Additionally, an action to protect the compressor is performed on the basis of the casing surface temperature that has been measured by the temperature sensor. Further, in the compressor described in Japanese Patent No. 2,503,699, the temperature of the compressed refrigerant inside the discharge tube is measured by a temperature sensor that is fixed to the surface of the discharge tube of the compressor. Additionally, an action to protect the compressor is performed on the basis of the temperature of the compressed refrigerant that has been measured by the temperature sensor.


A gas turbine engine includes a tip shroud ring rotatably supported on a last stage blade assembly in a turbine. The tip shroud ring is formed entirely of a fiber reinforced ceramic matrix composite material to provide a very light weight tip shroud ring, but also a very strong ring. The blades include pins extending from the tips, and the tip shroud ring includes holes in which the pins slide. Thus, the tip shroud ring is completely supported by the blade tip pins, and the centrifugal force developed by the rotation of the tip shroud ring does not add to the tensile force developed along the blades. Thus, the maximum rotational speed of the turbine rotor as defined by An2 can be increased. Also, because the blade tips are secured to the tip shroud ring in a circumferential direction, the tip shroud ring acts to dampen the bladed turbine by allowing only the middle of the blade to vibrate.

1. Field of the Invention
This Invention relates to the field of Gas Turbine Engines, and, more specifically, to an annular tip shroud for a full row of rotating turbine blades.
2. Description of the Related Art
Rotating blades in a gas turbine engine are known to include tip shrouds to provide a gas seal for the flow path through the turbine, to provide a change in vibration response, and to provide vibration damping of the blades. A tip shroud will add mass to the blade, which will increase the pull and airfoil stress of the specific blade. A designer typically will use the tip shroud for a set of blades in a particular row to control the modal frequency of the blade such that the natural frequency of the blade will not coincide with a driving frequency of the gas turbine engine. This matching of frequencies could produce resonant vibration in the blade, which can cause damage to the blade. Also, the size of the shroud will increase the stress in the blade and require the rotor disc to be larger in order to carry the increased load.
The last stage of the turbine has blades with the largest diameters. In order to extract the largest amount of power from the flowing gases, it is preferable to provide the last stage of the turbine with the largest diameter of blades possible. The power extracted from the last stage of the turbine is related to the equation An2, where A is the circumferential area of the rotational plane of the blade diameter and N is the rotational speed of the turbine. The larger the value of An2 the larger the amount of power the last stage of the turbine can extract from the flowing gases.
However, as the blade diameter increases, the centrifugal force acting on the blade increase, this force being larger with the addition of tip shrouds on the blades. Thus, the blade diameter—and, therefore, the power extracted from the flowing gases—is limited to the resulting stresses in which the blade is capable of withstanding.
U.S. Pat. No. 5,037,273 issued to Kreuger et al on Aug. 6, 1991 shows a compressor impeller with a ring shaped shroud band which is mounted at blade tips, each blade tip being enclosed in an identical radially slidable manner by a guide block, and the guide blocks being fastened to the shroud band. In the Kreuger et al invention, the blade tip slides within a closed opening in the shroud ring assembly, and the shroud ring assembly is made up of fiber reinforced and metal materials. The shroud tip assembly is relatively heavy and therefore would limit the rotational speed of the rotor and blades to a lower speed than the present invention.
Thus, there is a need to improve the sealing between blades by including a tip shroud, and to increase the diameter of the blades in the last stage of the turbine in order to extract the greatest amount of power from the flowing gases while also improving the vibration damping characteristics of the shroud ring.


A bus inversion apparatus includes exclusive-OR gates and an inversion detector. The exclusive-OR gates are coupled to an instant data bus and a last data bus. The data buses have a corresponding plurality of bits, where the exclusive-OR gates perform a bitwise comparison of the data buses, and provide an exclusive-OR bus. The states of the exclusive-OR bus indicate whether corresponding bits of the data buses are different. The inversion detector counts the number of the corresponding bits that are different, and indicates that the instant data bus should be inverted. The inversion detector has a plurality of left shift circuits, each configured to perform a logical left shift of input bits as directed by the states of shift bits, where outputs of the each of the plurality of left shift circuits indicate a number of a subgroup of the corresponding bits that are different.

1. Field of the Invention
This invention relates in general to the field of microelectronics, and more particularly to an apparatus and method for performing data bus inversion within a present day microprocessor.
2. Description of the Related Art
Many present day computer-based systems rely heavily on high-speed parallel buses to transfer address, data, control, and input/output information. The well-known source synchronous quad-pumped data bus that is employed in x86-compatible microprocessors is just one example of a 64-bit data bus that is divided into four data signal subgroups, each consisting of 16 bits. Each of the 16-bit data signal subgroups is routed over a separate path, typically via motherboard traces, and additionally includes source strobe signals and bus inversion signals that are unique to that data signal subgroup. The source strobe signals are strobed by a sending element on the bus to indicate validity of the data, or information, on the data signal subgroup. And the bus inversion signals are asserted to indicate that the information itself is being transmitted in complementary form. That is, when a sending element provides the inverted states of the data that is being transmitted over the data signal subgroup, the bus inversion signals for that data signal subgroup are asserted to indicate that inverted data is being transmitted rather than true data. When the states of a particular data signal subgroup are complemented for transmission over the data bus, this is known as a data bus inversion technique.
Data bus inversion is becoming increasingly prevalent in present day bused system designs as a result of increased emphasis on reducing the power required for bus transactions and a continuing need to minimize bus noise. Accordingly, as one skilled in the art will appreciate, both power and noise are minimized when the number of bits that change state on the bus, or signal group, are minimized.
Consequently, designers have provided elements within many present day integrated circuits that compare the current states of a given group of bus signals with the states which are to be transmitted during a following bus cycle. And if the number of signals that will change state during the next bus cycle is greater than, say, half of the total number of signals in the given group, then, rather than transmitting the true states of the given group during the next bus cycle, the bitwise complement of the true states are transmitted, and a corresponding data bus inversion signal is asserted to indicate that the inverted states of the data are being transmitted rather than the true states. Thus, a lesser number of state transitions occur over the bus from cycle to cycle, resulting in a savings in power and markedly reduced bus noise.
Determining which bits of a given signal group will change is relatively straightforward. The current, or last, data states are bitwise compared with the states to be transmitted via performing a bitwise exclusive-OR operation. The result is a number of exclusive-OR result bits that are asserted for those bits on the bus that will change during the next bus cycle. While determining which of the bits that will change is simple from a circuit design perspective, the operation of counting the number of bits that will change is not so simple.
In most systems, a series of full adders are employed to count the bits which will change, that is, the number of asserted bits on the exclusive-OR result bus. At a first stage, a number of 1-bit adders are employed to add the number of asserted bits in a subgroup of bits of the exclusive-OR result bus. As one skilled in the art will appreciate, 1-bit adders accept three inputs: a first input, a second input, and a carry input. And a 1-bit output along with a carry out bit are generated. Thus, the 1-bit adder generates the sum of its three inputs and generates a 2-bit binary output.
The 2-bit outputs from two adjacent 1-bit adders are next provided as inputs, along with an additional bit from the exclusive-OR result bus, to a 2-bit adder, which generates a 3-bit sum on its output. The 3-bit outputs from two adjacent 2-bit adders are then routed as inputs to a 3-bit adder along with another uncounted bit from the exclusive-OR result bus, which in turn generates a 4-bit sum on its output. The stages of full addition continue with increasing size of the adders in a subsequent stage, until all, or a majority of the bits on the exclusive-OR result bus have been counted for changed state. The output of a final adder stage indicates the number of bits that will change during the next cycle, of those bits which have been counted.
As one skilled in the art will appreciate, the implementation of a full adder requires that an exclusive-OR of the adder's inputs be performed. And to perform an exclusive-OR operation requires that all of the inputs be inverted to provide complementary states for performing the exclusive-OR operation.
The present inventor has observed that the generation of complementary states for the inputs to a full-adder does not create a problem when static logic design techniques are employed. However, more and more integrated circuit designs, and particularly those associated with high-speed bused systems, are utilizing dynamic logic design techniques, where many circuits therein utilize so-called domino logic.
Dynamic logic designs are different from static logic because they utilize a gated clock to evaluate combinational logic circuits. The clock is employed to synchronize transitions in sequential logic circuits, as in a pipeline microprocessor where the design is decomposed into many different pipeline stages, and the clock is used to synchronize the transfer of data from one stage to the next, like stations in an assembly line.
In most dynamic logic circuits, their output is driven high or low during a given half-cycle of the clock, and the circuits are allowed to transition to the opposite state as a function of the inputs, during the other half of the clock cycle. Thus, the clock signal becomes an integral and gating mechanism in all dynamic circuits. It is not within the scope of the present application to provide a tutorial on dynamic logic design techniques, however, it is sufficient to note that following a dynamic stage that is gated by the clock, with one or more static stages, for purposes of evaluating additional input data, is known as "domino" logic. This is because when the clock transitions to allow the inputs of the dynamic stage to evaluate, the states of the subsequent static stages transition like a row of dominoes.
Consequently, any additional gate delays that are required to evaluate a given set of inputs adds latency to the time required to evaluate a given set of inputs. And the present inventor has noted that when domino logic elements are employed, the additional gate delays that are required to generate the complements of the input states for any of the full adders in a data bus inversion mechanism as described above, are unacceptable. The present inventor has thus sensed a need in the art to provide a data bus inversion mechanism that can more easily be implemented using domino logic design techniques than that which is presently provided.
The present inventor has also observed that the use of 1-bit adders as a first stage to count bits in an exclusive-OR result bus accounts for bits on the bus in groups of three: a first input, a second input, and a carry input. So, for a 16-bit signal group, a designer is either forced to implement an additional 1 bit adder to account for the last bit in the group of 16, or to simply ignore one of the bits during the evaluation for data bus inversion. It is more likely than not that the last bit is simply ignored, and thus, the power and noise attributes on the bus are sacrificed.
Accordingly, the present inventor has also noted a desire in the art to evaluate all of the bits within a signal group for state transition in order to minimize the power consumed and noise produced from one cycle to the next over a high-speed bus.
Therefore, it is an object of the present invention to provide a bus state sense mechanism that tests all of the bits within a given signal group for state changes. In addition, it is an object of the present invention to provide a data bus inversion technique that reduces the latency incurred to determine whether or not a data bus inversion is to be performed, and particularly when using domino logic elements.


A water base ink set for ink-jet recording includes a water base ink which contains an acid dye, and a water base ink which contains a basic dye. The water base ink contains a polymer which has an average molecular weight of 3,000 to 20,000 and which is represented by the following formula (1):

1. Field of the Invention
The present invention relates to a water base ink set for ink-jet recording to be used for an ink-jet recording apparatus.
2. Description of the Related Art
In the ink-jet recording system, ink droplets are formed, for example, by means of the electrostatic attraction system, the system in which mechanical vibration or displacement is applied to the ink by using a piezoelectric element, and the system in which bubbles are generated by heating the ink to utilize the pressure generated thereby. All or a part of the ink droplets are adhered to a recording objective material such as paper to perform the recording.
The ink-jet recording system is advantageous in that the high printing or typing quality and the high print or photographic quality are obtained by controlling the discharge of the minute liquid droplets. Colors approximate to those obtained by the full color system can be reproduced and images without involving any granular texture can be formed by allowing the minute ink droplets of several picoliters to land highly accurately on the paper surface. However, in order to make it possible to discharge the minute liquid droplets as described above, it is necessary to establish a highly accurate landing control technique while using the sufficiently thin discharge nozzle. In order to highly accurately discharge the ink from the discharge nozzles having minute diameters as described above, it is necessary to remove the dust and impurities from the ink. Therefore, it is necessary that the precise filtration or microfiltration is performed for the ink for ink-jet recording, and materials, which are sufficiently washed, are used for all parts which make contact with the ink.
Most of general full color ink-jet printers, which are based on the use of an ink set of four colors of black, yellow, magenta, and cyan, use water base inks containing acid dyes in view of the toxicity and the coloring performance on the paper. However, the vividness is insufficient in some cases depending on the color. It is demanded to obtain a vivid image like those depicted with marker pens. Such a demand is especially great for the yellow. In order to satisfy the demand as described above, it is preferable that a basic dye, which develops a vivid color, is used as actually used for the marker pen. However, if water base inks, which contain basic dyes, are used for the water base inks of all colors to be used for the full color ink-jet printer, a resultant ink set is hardly considered to be appropriate in view of the color balance, even though the respective single colors are vivid.
On the other hand, Japanese Patent Application Laid-open No. 7-314880, which relates to an ink-jet recording material having an ink-receiving layer provided on a support, describes a method in which a basic dye is contained in the ink-receiving layer, and an ink for ink-jet recording containing an acid dye having a hue or tone different from that of the basic dye is used to perform the recording, and a method in which an acid dye is contained in the ink-receiving layer, and an ink for ink-jet recording containing a basic dye having a hue or tone different from that of the acid dye is used to perform the recording. However, in the methods as described above, it is necessary to use the ink-jet recording material which is allowed to contain the dye. Further, the inks of all colors are unbalanced to the use of the acid dyes or the basic dyes. The methods as described above are hardly considered to be appropriate in view of the color balance as well.
Therefore, when it is intended to obtain a vivid image having good color balance, it is preferable to use a water base ink containing an acid dye and a water base ink containing a basic dye in combination. However, in such a case, it is feared that the water base ink containing the acid dye and the water base ink containing the basic dye are mixed with each other at a head discharge section of an ink-jet printer to produce any deposit. The degree of the production of the deposit differs depending on, for example, the type of the dye, the concentration of the dye, the type of the solvent, and the concentration of the solvent. However, when the deposit is produced, then the clog-up arises at the head discharge section in some cases, and it is impossible to highly accurately control the discharge and the landing in other cases.
The acid dye and the basic dye are dissociated into cations and anions in the aqueous solution. It is considered that the deposit is produced as follows when the both dye solutions are mixed with each other. That is, the anion contained in the acid dye and the cation contained in the basic dye are attracted to one another, and the fundamental moieties of the dyes are bonded to one another. Therefore, if the anion contained in the acid dye and the cation contained in the basic dye are prevented from being attracted to one another, it is possible to avoid the production of the deposit. However, in general, the anion and the cation tend to effect the attraction. Therefore, it is difficult to avoid the production of the deposit when the both inks are mixed with each other.

Water base ink set for ink-jet recording

Abstract: wherein X represents H or COONa, and Y represents H, COONa, SO3Na, or CH2OR in the formula (1). R represents a substituted group having SO3Na with carbon atom or atoms of a number of 1 to 5. When the ink containing the acid dye and the ink containing the basic dye are mixed with each other, then the head discharge section is prevented from any clog-up, and it is possible to perform the stable jetting operation.


To provide a dialysate extraction apparatus which can automate disinfecting work for a collection port or a sealing device of an opening/closing device and can reliably and easily clean the collection port or the sealing device of the opening/closing device. A dialysate extraction apparatus includes a dialysate extraction device that has an introduction port and a discharge port which are connected to a flow route of a liquid and can circulate the liquid and that has a collection port which can collect the circulated liquid; a cap that is attachable to and detachable from the collection port of the dialysate extraction device and can open and close the collection port; a sealing device that is attached to the cap and seals the collection port in a state where the cap is attached to the collection port of the dialysate extraction device; and a heating device that can heat the sealing device of the cap.

In recent years, in a dialysis apparatus as a blood purification apparatus, a technology has been proposed in which priming, returning of blood and substitution (emergency fluid infusion) are performed by using a dialysate to be supplied to a dialyzer during dialysis treatment (in particular, online HDF or online HF), or a technology has been proposed in which the dialysate is used as a substitution solution for the online HDF or online HF treatment. For example, PTL 1 discloses a dialysis apparatus including a substitution line where one end is connected to a dialysate extraction port (collection port) formed in a predetermined section of a dialysate introduction line and the other end is connected to a blood circuit (arterial blood circuit or venous blood circuit): and a substitution pump which is arranged in the substitution line. In order for such a dialysis apparatus to perform the priming, the returning of blood or the substitution (emergency fluid infusion), the substitution pump is rotated to supply the dialysate in the dialysate introduction line to the blood circuit (arterial blood circuit or venous blood circuit).
In general, a cap (opening/closing device) is attachable to and detachable from the dialysate extraction port, and the substitution line is connected by detaching the cap and when the substitution line is not connected, the dialysate flowing in the dialysate introduction line is not caused to leak out by attaching the cap. For example, in order to clean and disinfect a pipe for circulating the dialysate, such as the dialysate introduction line and the dialysate discharge line, cleaning water or disinfecting solution is circulated in the pipe in a state where the cap is attached to the collection port. In this manner, the cleaning water or the disinfecting solution is prevented from leaking out. An example may be found in PTL 1: Japanese Unexamined Patent Application Publication No. 2004-313522.


The present invention relates to monovalent influenza vaccine formulations and vaccination regimes for immunizing against influenza disease, their use in medicine, in particular their use in augmenting immune responses to various antigens, and to methods of preparation. In particular, the invention relates to monovalent influenza immunogenic compositions comprising an influenza antigen or antigenic preparation thereof from an influenza virus strain being associated with a pandemic outbreak or having the potential to be associated with a pandemic outbreak, in combination with an oil-in-water emulsion adjuvant comprising a metabolizable oil, a sterol and/or a tocopherol such as alpha tocopherol, and an emulsifying agent.

Influenza viruses are one of the most ubiquitous viruses present in the world, affecting both humans and livestock. Influenza results in an economic burden, morbidity and even mortality, which are significant.
The influenza virus is an RNA enveloped virus with a particle size of about 125 nm in diameter. It consists basically of an internal nucleocapsid or core of ribonucleic acid (RNA) associated with nucleoprotein, surrounded by a viral envelope with a lipid bilayer structure and external glycoproteins. The inner layer of the viral envelope is composed predominantly of matrix proteins and the outer layer mostly of host-derived lipid material. Influenza virus comprises two surface antigens, glycoproteins neuraminidase (NA) and haemagglutinin (HA), which appear as spikes, 10 to 12 nm long, at the surface of the particles. It is these surface proteins, particularly the haemagglutinin that determine the antigenic specificity of the influenza subtypes. Virus strains are classified according to host species of origin, geographic site and year of isolation, serial number, and, for influenza A, by serological properties of subtypes of HA and NA. 16 HA subtypes (H1-H16) and nine NA subtypes (N1-N9) have been identified for influenza A viruses [Webster R G et al., Evolution and ecology of influenza A viruses. Microbiol. Rev. 1992; 56:152-179; Fouchier R A et al. Characterization of a Novel Influenza A Virus Hemagglutinin Subtype (H16) Obtained from Black-Headed Gulls. J. Virol. 2005; 79:2814-2822). Viruses of all HA and NA subtypes have been recovered from aquatic birds, but only three HA subtypes (H1, H2, and H3) and two NA subtypes (N1 and N2) have established stable lineages in the human population since 1918. Only one subtype of HA and one of NA are recognised for influenza B viruses.
Influenza A viruses evolve and undergo antigenic variability continuously [Wiley D, Skehel J. The structure and the function of the hemagglutinin membrane glycoprotein of influenza virus. Ann. Rev. Biochem. 1987; 56:365-394]. A lack of effective proofreading by the viral RNA polymerase leads to a high rate of transcription errors that can result in amino-acid substitutions in surface glycoproteins. This is termed "antigenic drift". The segmented viral genome allows for a second type of antigenic variation. If two influenza viruses simultaneously infect a host cell, genetic reassortment, called "antigenic shift" may generate a novel virus with new surface or internal proteins. These antigenic changes, both 'drifts' and 'shifts' are unpredictable and may have a dramatic impact from an immunological point of view as they eventually lead to the emergence of new influenza strains and that enable the virus to escape the immune system causing the well known, almost annual, epidemics. Both of these genetic modifications have caused new viral variants responsible for pandemic in humans.
HA is the most important antigen in defining the serological specificity of the different influenza strains. This 75-80 kD protein contains numerous antigenic determinants, several of which are in regions that undergo sequence changes in different strains (strain-specific determinants) and others in regions which are common to many HA molecules (common to determinants).
Influenza viruses cause epidemics almost every winter, with infection rates for type A or B virus as high as 40% over a six-week period. Influenza infection results in various disease states, from a sub-clinical infection through mild upper respiratory infection to a severe viral pneumonia. Typical influenza epidemics cause increases in incidence of pneumonia and lower respiratory disease as witnessed by increased rates of hospitalization or mortality. The severity of the disease is primarily determined by the age of the host, his immune status and the site of infection.
Elderly people, 65 years old and over, are especially vulnerable, accounting for 80-90% of all influenza-related deaths in developed countries. Individuals with underlying chronic diseases are also most likely to experience such complications. Young infants also may suffer severe disease. These groups in particular therefore need to be protected. Besides these 'at risk'-groups, the health authorities are also recommending to vaccinate health care providers.
Vaccination plays a critical role in controlling annual influenza epidemics. Currently available influenza vaccines are either inactivated or live attenuated influenza vaccine. Inactivated flu vaccines are composed of three possible forms of antigen preparation: inactivated whole virus, sub-virions where purified virus particles are disrupted with detergents or other reagents to solubilise the lipid envelope (so-called "split" vaccine) or purified HA and NA (subunit vaccine). These inactivated vaccines are given intramuscularly (i.m.), subcutaneously (s.c.), or intranasally (i.n.).
Influenza vaccines for interpandemic use, of all kinds, are usually trivalent vaccines. They generally contain antigens derived from two influenza A virus strains and one influenza B strain. A standard 0.5 ml injectable dose in most cases contains (at least) 15 μg of haemagglutinin antigen component from each strain, as measured by single radial immunodiffusion (SRD) (J. M. Wood et al.: An improved single radial immunodiffusion technique for the assay of influenza haemagglutinin antigen: adaptation for potency determination of inactivated whole virus and subunit vaccines. J. Biol. Stand. 5 (1977) 237-247; J. M. Wood et al., International collaborative study of single radial diffusion and immunoelectrophoresis techniques for the assay of haemagglutinin antigen of influenza virus. J. Biol. Stand. 9 (1981) 317-330).
Interpandemic influenza virus strains to be incorporated into influenza vaccine each season are determined by the World Health Organisation in collaboration with national health authorities and vaccine manufacturers. Interpandemic Influenza vaccines currently available are considered safe in all age groups (De Donato et al., 1999, Vaccine, 17, 3094-3101). However, there is little evidence that current influenza vaccines work in small children under two years of age. Furthermore, reported rates of vaccine efficacy for prevention of typical confirmed influenza illness are 23-72% for the elderly, which are significantly lower than the 60-90% efficacy rates reported for younger adults (Govaert, 1994, J. Am. Med. Assoc., 21, 166-1665; Gross, 1995, Ann Intern. Med. 123, 523-527). The effectiveness of an influenza vaccine has been shown to correlate with serum titres of hemagglutination inhibition (HI) antibodies to the viral strain, and several studies have found that older adults exhibit lower HI titres after influenza immunisation than do younger adults (Murasko, 2002, Experimental gerontology, 37, 427-439).
A sub-unit influenza vaccine adjuvanted with the adjuvant MF59, in the form of an oil-in-water emulsion is commercially available for the elderly and at risk population, and has demonstrated its ability to induce a higher antibody titer than that obtained with the non-adjuvanted sub-unit vaccine (De Donato et al. 1999, Vaccine, 17, 3094-3101). However, in a later publication, the same vaccine has not demonstrated its improved profile compared to a non-adjuvanted split vaccine (Puig-Barbera et al., 2004, Vaccine 23, 283-289).
By way of background, during inter-pandemic periods, influenza viruses that circulate are related to those from the preceding epidemic. The viruses spread among people with varying levels of immunity from infections earlier in life. Such circulation, over a period of usually 2-3 years, promotes the selection of new strains that have changed enough to cause an epidemic again among the general population; this process is termed 'antigenic drift'. 'Drift variants' may have different impacts in different communities, regions, countries or continents in any one year, although over several years their overall impact is often similar. Typical influenza epidemics cause increases in incidence of pneumonia and lower respiratory disease as witnessed by increased rates of hospitalisation or mortality. The elderly or those with underlying chronic diseases are most likely to experience such complications, but young infants also may suffer severe disease.
At unpredictable intervals, novel influenza viruses emerge with a key surface antigen, the haemagglutinin, of a totally different subtype from strains circulating the season before. Here, the resulting antigens can vary from 20% to 50% from the corresponding protein of strains that were previously circulating in humans. This can result in virus escaping 'herd immunity' and establishing pandemics. This phenomenon is called 'antigenic shift'. In other words, an influenza pandemics occurs when a new influenza virus appears against which the human population has no immunity. It is thought that at least the past pandemics have occurred when an influenza virus from a different species, such as an avian or a porcine influenza virus, has crossed the species barrier. If such viruses have the potential to spread from human to human, they may spread worldwide within a few months to a year, resulting in a pandemic. For example, in 1957 (Asian Flu pandemic), viruses of the H2N2 subtype replaced H1N1 viruses that had been circulating in the human population since at least 1918 when the virus was first isolated. The H2 HA and N2 NA underwent antigenic drift between 1957 and 1968 until the HA was replaced in 1968 (Hong-Kong Flu pandemic) by the emergence of the H3N2 influenza subtype, after which the N2 NA continued to drift along with the H3 HA (Nakajima et al., 1991, Epidemiol. Infect. 106, 383-395).
The features of an influenza virus strain that give it the potential to cause a pandemic outbreak are: it contains a new haemagglutinin compared to the haemagglutinin in the currently circulating strains, which may or not be accompanied by a change in neuraminidase subtype; it is capable of being transmitted horizontally in the human population; and it is pathogenic for humans. A new haemagglutinin may be one which has not been evident in the human population for an extended period of time, probably a number of decades, such as H2. Or it may be a haemagglutinin that has not been circulating in the human population before, for example H5, H9, H7 or H6 which are found in birds. In either case the majority, or at least a large proportion of, or even the entire population has not previously encountered the antigen and is immunologically naïve to it.
Several clinical studies have been performed to evaluate safety and immunogenicity in unprimed populations, with monovalent candidate vaccines containing a pandemic strain such as the non-circulating H2N2 or H9N2 strains. Studies have investigated split or whole virus formulations of various HA concentrations (1.9, 3.8, 7.5 or 15 μg HA per dose), with or without alum adjuvantation. Influenza viruses of the H2N2 subtype circulated from 1957 until 1968 when they were replaced by H3N2 strains during the 'Hong Kong pandemic'. Today, individuals that were born after 1968 are immunologically naïve to H2N2 strains. These vaccine candidates have been shown to be immunogenic and well tolerated. Results are reported in Hehme, N et al. 2002, Med. Microbiol. Immunol. 191, 203-208; in Hehme N. et al. 2004, Virus Research 103, 163-171; and two studies were reported with H5N1 (Bresson J L et al. The Lancet. 2006:367 (9523):1657-1664; Treanor J J et al. N Engl J. Med. 2006; 354:1343-1351). Other studies have reported results with MF59 adjuvanted influenza vaccines. One study has reported that two doses of an H5N3 influenza vaccine adjuvanted with MF59 was boosting immunity to influenza H5N1 in a primed population (Stephenson et al., Vaccine 2003, 21, 1687-1693) and another study has reported cross-reactive antibody responses to H5N1 viruses obtained after three doses of MF59-adjuvanted influenza H5N3 vaccine (Stephenson et al., J. Infect. Diseases 2005, 191, 1210-1215).
Persons at risk in case of an influenza pandemic may be different from the defined risk-groups for complications due to seasonal influenza. According to the WHO, 50% of the human cases caused by the avian influenza strain H5N1 occurred in people below 20 years of age, 90% occurred among those aged <40. (WHO, weekly epidemiological record, 30 Jun. 2006).
During a pandemic, antiviral drugs may not be sufficient or effective to cover the needs and the number of individuals at risk of influenza will be greater than in interpandemic periods, therefore the development of a suitable vaccine with the potential to be produced in large amounts and with efficient distribution and administration potential is essential. For these reasons, monovalent instead of trivalent vaccines are being developed for pandemic purposes in an attempt to reduce vaccine volume, primarily as two doses of vaccine may be necessary in order to achieve protective antibody levels in immunologically naïve recipients (Wood J M et al. Med Mircobiol Immunol. 2002; 191:197-201. Wood J M et al. Philos Trans R Soc Lond B Biol Sci. 2001; 356:1953-1960).
These problems may be countered by adjuvantation, the aim of which is to increase immunogenicity of the vaccine in order to be able to decrease the antigen content (antigen sparing) and thus increase the number of vaccine doses available. The use of an adjuvant may also overcome the potential weak immunogenicity of the antigen in a naïve population. Examples of the above have been shown using whole inactivated H2N2 or H9N2 virus adjuvanted with aluminium salt (N. Hehme et al. Virus Research 2004, 103, 163-171). Clinical trials with plain subvirion H5N1 vaccine or aluminium hydroxide adjuvanted split virus H5N1 vaccine have already been performed. The results of these trials indicate that both plain and adjuvanted H5N1 virus vaccines are safe up to an antigen dose of 90 μg (tested only as plain subvirion vaccine) (Bresson J L et al. The Lancet. 2006:367 (9523):1657-1664; Treanor J J et al. N Engl J. Med. 2006; 354:1343-1351)
New vaccines with an improved immunogenicity, in particular against weakly or non-immunogenic pandemic strains or for the immuno-compromised individuals such as the elderly population, are therefore still needed. New vaccines with a cross-protection potential are also needed, that could be used as pre-pandemic or stockpiling vaccines to prime an immunologically naive population against a pandemic strain before or upon declaration of a pandemic. Formulation of vaccine antigen with potent adjuvants is a possible approach for enhancing immune responses to subvirion antigens. Novel adjuvant formulations are hereby provided which allow an antigen sparing formulation affording sufficient protection (seroconversion of previously seronegative subjects to a HI titer considered as protective, 1:40 or fourfold increase in titer) of all age groups.


An optical-axis directional indicating apparatus for optical communication includes a photoreceptor having a light-receiving surface and a plurality of optical receiving elements arranged on the surface in a first direction and a second direction orthogonal to the first direction, to receive a transmitted light beam, a detector to detect levels of the light beam received at the optical receiving elements, a plurality of display elements arranged in the first and second directions so as to correspond to the optical receiving elements of the photoreceptor, and a switch circuit to selectively turn on or off the display elements in accordance with the levels of the light beam detected by the detector, to indicate whether or not an optical axis of the light beam is deviated in the first and/or the second direction on the light-receiving surface of the photoreceptor.

The present invention relates to an optical-axis directional indicating apparatus to be used in adjustments to the optical axis of an optical wireless communications system.
In optical wireless communications systems, a photoemitter transmits an infrared beam modulated with data signals and then a photoreceptor receives and demodulates the modulated infrared beam, thus achieving data transmission.
Higher transfer speed requires larger amount of light received at the photoreceptor, which further requires a focused beam from the photoemitter for higher light intensity. These requirements are satisfied by optical-axis adjustments between the photoemitter and the photoreceptor.
A known optical wireless communications system, such as illustrated in FIG. 1, employs optical-axis adjustments using a pilot beam.
In FIG. 1, the optical wireless communications system consists of a base unit 1 and a local unit 2.
The base unit 1 has a photoemitter 3 for emitting a data beam (carrying data) for data transmission, a pilot-beam emitter 4 for emitting a divergent beam (pilot beam) having a frequency different from that of the data beam, and a data receptor 5 for receiving data beam transmitted from the local unit 2.
The local unit 2 has a photoemitter 6 and a photoreceptor 7 both rotatable in a horizontal and also a vertical direction. It receives the pilot beam emitted by the pilot-beam emitter 4 of the base unit 1 while the photoemitter 6 and the photoreceptor 7 are rotating in the horizontal and vertical directions. The photoemitter 6 and the photoreceptor 7 stop at the maximum level of received light for optical-axis adjustments between the base unit 1 and the local unit 2. The photoreceptor 7 receives both of the data beam and the pilot beam, which may, however, be separated into two receiving sections to receive the data beam and the pilot beam separately.
As illustrated in FIGS. 2A to 5B, the photoreceptor 7 of the local unit 2 has a quadrant PD (photodiode) 8 having 2×2 PD cells in a horizontal and a vertical direction. Four PD cells PD_A PD_B, PD_C and PD_D are arranged into a 2×2 matrix in a package. Each PD cell performs photoelectric conversion to detect an electric signal carried by the data or pilot beam.
FIG. 6 shows a circuit block diagram installed in the local unit 2 of the known optical wireless communications system (FIG. 1), for rotating the unit 2 in the horizontal and vertical directions in optical-axis adjustments.
The operation of the circuit diagram is explained with reference to a flowchart shown in FIG. 7.
Step S1 at the photoreceptor 7: A pilot beam transmitted from the base unit 1 is received at the photoreceptor 7 of the local unit 2. Electric signals (Dir_A Dir_B, Dir_C and Dir_D) are detected from the pilot beam by the PD cells PD_A PD_B, PD_C and PD_D of the quadrant PD 8. The electric signals are converted into voltages and amplified by amplifiers 9.
Steps S2 to S6 at a controller 10: The amplified signals (Dir_A Dir_B, Dir_C and Dir_D) are selected by a switch 11 under control by a microcomputer 14. Each selected signal is amplified by an amplifier 12 and detected by a level detector 13 for its amplified DC level. The detected DC levels are sequentially supplied to the microcomputer 14 and compared with each other.
Steps S7 to S12 at a motor unit 15: A tilt (vertical) motor Mt and a pan (horizontal) motor Mp are driven by the microcomputer 14 to rotate the quadrant PD 8 so that the PD cells PD_A PD_B, PD_C and PD_D can receive the same amount of light.
Steps S5 to S12 are explained in detail.
Optical-adjustments in the vertical direction TILT:
(1) Comparison is made between addition of the levels of light received at the PD cells PD_A and PD_D and addition of the levels of light received at the PD cells PD_B and PD_C (step S5).
(2) If the former addition and the latter addition are equal to each other in step S5, the spot of pilot beam must have been received at the center of the quadrant PD 8 in the vertical direction TILT (step S5→step S9).
(3) If the former addition is larger than the latter addition in step S5, the spot of pilot beam must have been received at the upper section of the quadrant PD 8, as illustrated in FIGS. 2A and 2B. The tilt motor Mt is driven to tilt the quadrant PD 8 upwards, as indicated by an arrow in FIG. 2B. (step S6→step S7).
(4) If the former addition is smaller than the latter addition in step S5, the spot of pilot beam must have been received at th lower section of the quadrant PD 8, as illustrated in FIGS. 3A and 3B. The tilt motor Mt is driven to tilt the quadrant PD 8 downwards, as indicated by an arrow in FIG. 3B. (step S6→step S8).
(5) The procedures (3) and (4) are repeated so that the spot of pilot beam can be received at the center of the quadrant PD 8 in the vertical direction TILT.
Optical-adjustments in the horizontal direction PAN:
(6) Comparison is made between addition of the levels of light received at the PD cells PD_A and PD_B and addition of the levels of light received at the PD cells PD_C and PD_D (step S9).
(7) If the former addition and the latter addition are equal to each other in step S9, the spot of pilot beam must have been received at the center of the quadrant PD 8 in the horizontal direction PAN (step S9→END).
(8) If the former addition is larger than the latter addition in step S9, the spot of pilot beam must have been received at the right section of the quadrant PD 8, as illustrated in FIGS. 4A and 4B. The pan motor Mp is driven to turn the quadrant PD 8 right, as indicated by an arrow in FIG. 4B. (step S10→step S11).
(9) If the former addition is smaller than the latter addition in step S9, the spot of pilot beam must have been received at the left section of the quadrant PD 8, as illustrated in FIGS. 5A and 5B. The pan motor Mp is driven to turn the quadrant PD 8 left, as indicated by an arrow in FIG. 5B. (step S10→step S12).
(10) The procedures (8) and (9) are repeated so that the spot of pilot beam can be received at the center of the quadrant PD 8 in the horizontal direction PAN.
The known optical wireless communications system employs the automatic optical-axis adjusting technique explained above so that a user can easily set the local unit 2. Thus, this system requires a microcomputer and the peripheral circuitry for automatically driving gears of the motors Mt and Mp, etc., which makes the local unit 2 bulk and expensive.
Another known optical wireless communications system employing a manual optical-axis adjustment technique is disclosed in Japanese Unexamined Patent publication No. 7 (1995)-131422. In this optical-axis adjustment technique, the level of transmitted light is detected and displayed on a level monitor.
Monitoring the level of transmitted light on display or by sound is applied to adjustments to the direction of an antenna of a TV set towards an antenna of a TV station.
Monitoring the level of transmitted light on display or by sound like disclosed in the above Japanese Unexamined Patent publication, however, forces a user to adjust the optical axis upwards, downwards, right or left by cut and try because he or she dose not know in which direction the optical axis should be adjusted, which is troublesome and takes much time.

Optical-axis directional indicating apparatus for optical communication


In the financial-services industry, there are online centers that help brokers to match sellers and buyers of stock based on indications of interest (IOIs). However, at least some of these centers are not only limited in the types of IOIs that they provide, but also in the ways how they allow IOI senders to control IOI usage. Accordingly, to facilitate trades, one exemplary system provides an IOI which is associated with an online negotiation capability. Some versions of this system provide mechanisms for users, such as broker-dealers, to define different IOI response privileges for recipients of their IOIs. To reduce the market risks of failed negotiations, some versions provide automated features for comparing confidential information from traders and initiating online negotiations for stock transactions contingent on favorable comparisons.

The 1990s witnessed a rapid proliferation of computer technology into homes and businesses. During this time, computers, fueled by growth of the much-heralded Internet, advanced from facilitating tasks, such as word processing and bookkeeping, to become everyday communications tools, fast approaching the commonness of telephones and televisions. As a result, virtually every sector of public, private, and commercial life has been affected in some way by the power and reach of today's computer technology.
The financial-services industry, for example, has recently seen not only the emergence of Internet-based trading platforms that allow online trading of stocks, bonds, and commodities, but also the emergence of online listing centers that allow broker-dealers—individuals or firms in the business of buying and selling securities for themselves and others—to match sellers with buyers of securities based on listed indications of interest" (IOIs). A seminal example of such an online center is the AutEx™ service from Thomson Financial of New York, N.Y.
This service provides a secure and convenient means for broker-dealers to broadcast their desires, or interests, in purchasing or selling blocks of particular stock to a select group of securities traders, generally known collectively as buy-side traders. (Block trades are typically defined as trades of at least 10,000 shares or trades with a total market value of at least $200,000.) For example, the AutEx system provides three types of IOIs: 1) a general IOI which identifies a stock and a general number of shares, such as large, medium or small; 2) a super IOI which identifies a stock, a specific number of shares, and price; and 3) a natural IOI which not only identifies a stock, a specific number of shares, and a price, but also signals existence of an active customer order for the stock.
A buy-side trader viewing these IOIs in an online list can then select an IOI for a stock and create a placeholder trade ticket in her order management system, with the ticket order including information from the IOI. Next, the buy-side trader contacts the IOI sender via a separate telephone, email, or instant messaging system to discuss a potential trade. If agreement is reached, the buy-side trader manually edits the placebolder trade ticket (in their buy-side Order Management System (OMS)) to conform to the terms and electronically sends the agreed on trade terms to the dealer trading system. The dealer then proceeds to execute the trade, reporting the transaction to the public market place and returning resulting execution reports to the buy-side OMS.
Although the AutEx system is quite successful, the present inventors have recognized that it is limited in at least two ways. First, it forces users to exit the system to negotiate and to complete trades based on IOIs. This exiting is not only cumbersome and time consuming, but in fast-moving markets can result in lost trading or profit opportunities. Second, conventional systems, such as the AutEx system, provide few options for IOI senders to control usage of their IOIs. For example, a sender can define an IOI, its duration, and its recipients, but cannot offer one set of recipients different IOI response options than another.
Accordingly, the present inventors have recognized a need for better ways of using IOIs to facilitate trading.

IOI-based block trading systems, methods, interfaces, and software


A capillary dosing unit includes a stem provided with an axis of symmetry, a grip at a first end of the stem and at least one slit at a second end of the stem which emerges along the axis of the stem. This dosing unit allows accurate dosing of a liquid such as a nailcare oil.

1. Field of the Invention
The present invention relates to a capillary dosing unit for the local application of a precise quantity of an aqueous or oily liquid intended in particular for the cosmetic or dermopharmaceutical care of the nails, eyelids or other parts of the face or scalp.
2. Discussion of the Background
Related applicators in the field of cosmetics for delivering a liquid product, in particular to the eyelids, consist of a foam, a felt pad or a flocked adaptor provided with a large quantity of small fibers. These types of applicators preclude the delivery of a very small quantity of product and in particular of a precise dose of nailcare product, sufficient to be spread around the whole nail, to the edge of the nail and of the skin without it being necessary to wipe the nail to remove the excess. Furthermore, the felt pad and the foam release the product too slowly. Hitherto, none of the related applicators (see in particular those of the documents FR-A-2 505 150, FR-A-2 633 256) allows the delivery of exactly the required dose of care liquid at a suitable rate. Furthermore, the quantities delivered to the nail or the skin vary from one application to another. This is due in particular to the fact that these related applicators do not include a system for the automatic wiping of the surplus product.
A related applicator is also disclosed in U.S. Pat. No. 2 990 563 and GB-A-1 318 677, which comprises a stem furnished at a first end with a gripping member and at a second end with two slits of rounded shape. This rounded end allows only point contact with the surface of the skin or of the nail, thus requiring the application of the liquid to be repeated several times in order to treat the whole of the relevant region. Furthermore, with the rounded end of the stem it is difficult to spread the product over the area to be treated. Moreover, the contact area of a rounded end cannot be altered. Indeed, whatever the inclination of the applicator, the contact area is always the same and cannot be modified according to the area to be treated, especially according to the relief or shape of the area.
There is therefore still a need for a dosing applicator capable of delivering a small constant dose of liquid product, in particular to the nails or to localized lesions on the skin or scalp which enables the product to be spread easily and which can be used for various shapes of surfaces to be treated while also restricting the number of applications.

Capillary dosing unit with terminal slit