In one embodiment there is a comparison circuit (28) for selecting data in response to a first binary quantity (ADDRESS) and a second binary quantity (TAG). The comparison circuit includes a match circuit (34) for outputting a match signal (MATCH) in response to comparing the first binary quantity and the second binary quantity. The comparison circuit also includes a delay circuit (36) for outputting a delay signal (TC.sub.D) in response to a signal generated at a same time as the second binary quantity, and circuitry (38) for outputting a hit signal in response to the match signal and the delay signal. The hit signal indicates that a memory stores data corresponding to the second binary quantity. Still further, the comparison circuit includes dynamic select circuit (40) for outputting a logic state of data corresponding to the first binary quantity and in response to the hit signal. The dynamic select circuit comprises a precharge node (88) and at least one transistor (90) coupled in a discharge path coupled to the precharge node. The at least one transistor is operable to conduct in response to the hit signal reaching a discharge enable voltage such that the precharge node is discharged and the logic state of the data changes in response thereto. The hit signal has various attributes. First, the hit signal is initially at a disable level insufficient to discharge the precharge node of the select circuit. Second, the hit signal transitions from the disable level to the discharge enable voltage in response to the memory storing data corresponding to the second binary quantity. Third, a transition of the delay signal occurs at a time with respect to a transition of the match signal such that the hit signal does not reach the discharge enable voltage of the dynamic select circuit in response to the memory not storing data corresponding to the second binary quantity.

Cache circuits are important components which are frequently used in contemporary microprocessors and the like to increase system performance by reducing the potential amount of time needed to access information. Typically, a cache circuit includes various components, such as a tag memory which is commonly a random access memory ("RAM"). The tag RAM stores so-called tag information which corresponds to the cached data which is commonly stored in a separate cache data RAM. The tag information may include various characteristics corresponding to the cached data, such as the actual address where the cached data may be found in some other memory device (e.g., an external memory structure). Another component of a cache circuit is the hit detection circuit associated with the tag RAM. The hit detection circuit (of which there are N such circuits in an N-way set associative cache circuit) compares an incoming address with the actual address stored as part of the tag information. If the comparison matches, there is said to be a "hit" in the cache circuit, that is, the data sought at the incoming address may be retrieved directly from the cache data RAM rather than having to go to the original (i.e., often external) memory to retrieve that data; on the other hand, if the comparison does not match, there is said to be a "miss" in the cache circuit, that is, the data sought at the incoming address is not located, or for some other reason is not reliable, within the cache data RAM.
The hit detection circuit is typically part of the speed limiting path of the cache circuit as a whole. Therefore, various designs have arisen to reduce the time required for comparison by the hit detection circuit, as well as the selection in response to a hit determined by that circuit. For example, FIG. 1 illustrates a prior art configuration including a hit detection circuit designated generally at 10. Circuit 10 includes a gated clock signal connected to the gate of a p-channel transistor 14 which has a source connected to a system voltage level (e.g., V.sub.DD) and a drain connected to a match node 16. Match node 16 is connected to an integer number N+1 of single bit comparison circuits designated generally at 18, with two of those circuits 18.sub.0 and 18.sub.N shown for purposes of illustration. Each circuit 18 is constructed in a like manner and, therefore, circuit 18.sub.N is described in detail with it understood that like reference numbers are used in each similar such circuit with only a change in subscript to distinguish the different bit comparison circuits. Thus, turning to bit comparison circuit 18.sub.N, it includes an n-channel transistor 20.sub.N with its drain connected to match node 16 and its source connected to ground. The gate of transistor 20.sub.N is connected to the output of an exclusive OR ("XOR") gate 22.sub.N. A first input of XOR gate 22.sub.N receives an incoming address bit ADDRESS.sub.N, while a second input of XOR gate 22.sub.N receives a corresponding address bit from the tag information and designated TAG.sub.N. Match node 16 is also connected to the input of an inverter 24, and the output of inverter 24 is connected to a select circuit 26. Although not shown, note that actually the output of each XOR gate 22 is logically ANDed with the gated clock signal and the output of this logic AND combination is connected to a corresponding n-channel transistor 20. As a result, when the gated clock signal is low (i.e., when precharge is occurring), the output of this ANDed signal causes a low signal to be applied to each respective n-channel transistor 20 when precharging is occurring.
The operation of the components of FIG. 1 are well known to a person skilled in the art and, therefore, are only briefly addressed here. Generally the combination of all the XOR gates 22 from all of the bit comparison circuits 18 operate together to compare an entire incoming address with an address from the tag RAM (not shown). This determination indicates whether or not there is a hit in the cache circuit and, if a hit occurs, select circuit 26 selects the data, typically stored in a separate data RAM, which corresponds to the incoming address. Looking now more specifically to the circuit of FIG. 1, first the gated clock signal goes low during a precharge phase of operation. Consequently, the ANDing function described above with respect to the gated clock signal and the output of each XOR gate 22 (although not shown) forces the connection to the gate of each transistor 20 to be low during precharge. In addition, transistor 14 conducts and match node 16 is precharged to V.sub.DD. Thus, this signal is inverted by inverter 24 and the output signal, MATCH, is low during precharge. Thereafter, the gated clock signal goes high and each bit comparison circuit 18.sub.0 through 18.sub.N compares its two input bits. For example, looking to circuit 18.sub.N, XOR gate 22.sub.N determines whether ADDRESS.sub.N and TAG.sub.N are the same. If not (i.e., if there is a cache miss), XOR gate 22.sub.N causes transistor 20.sub.N to conduct, thereby discharging the precharge from match node 16 to ground. Consequently, the output of inverter 24 rises from low to high. Note further that if any one of the N+1 bit comparison circuits indicates a mismatch between its two inputs (i.e., again, if there is a cache miss), then it discharges match node 16 in a similar manner. Thus, only if each of those N+1 bit comparison circuits finds a match will match node 16 remain precharged. In other words, if the inputs for each of the XOR gates 22.sub.N through 22.sub.0 do match, each corresponding transistor 20.sub.N through 20.sub.0 remains off. Consequently, the output of inverter 24 remains low.
While the above discussion therefore demonstrates that circuit 10 may validly evaluate matches and mismatches between an incoming address and a tag address, note the configuration gives rise to various drawbacks. For example, typically the capacitive load imposed by select circuit 26 (as well as potential other loads) is considerably high. As a result, inverter 24 must be constructed of a sufficient size to drive that load. In turn, because inverter 24 is sized in this manner, each transistor 20 of a corresponding bit comparison circuit 18 also must be sized large enough to drive the large inverter 24. Otherwise, the speed of the circuit is reduced which may be an unacceptable performance penalty. On the other hand, there may be twenty or more bit comparison circuits and, therefore, it may be impractical to scale these components beyond a certain size. In addition to these drawbacks, note further the two output waveforms produced by the circuit of FIG. 1 when there is a miss or a hit. Specifically, when there is a hit, the output is originally precharged low, and then remains low in response to the hit. In contrast, when there is a miss, the output is again originally precharged low, but then transitions in response to the hit. The inventor of the present embodiments has recognized that given these waveforms, domino logic select circuits cannot be used as detailed below, and thus the types of circuitry within select circuit 26 may be limited to slower circuits, again thereby reducing the overall speed of the cache circuit.
In view of the above, there arises a need to address the drawbacks of prior art cache circuits and to provide higher speed self-timed cache circuits, systems, and methods for use with microprocessors and the like.

Self-timed comparison circuits and systems


An image is displayed on a rectangular display screen of the display unit by the steps of obtaining minimum or maximum positions of black dot in the width direction and longitudinal direction in an image data stored in an image memory; deciding a position of one corner portion of a rectangular effective image data area in the image data from the minimum or maximum positions in the width and longitudinal directions; and controlling the display unit to display the rectangular effective image data area based on the position of the decided one corner portion in the image data on the display screen of the display unit starting from the one corner portion.

1. Field of the Invention
The present invention relates to an image displaying method and an image display apparatus, and to a facsimile apparatus which has a function to display received facsimile image data.
2. Description of Related Art
Conventionally, suggested as an image display apparatus and a facsimile apparatus of this kind is, for example, a terminal device with a facsimile function which is described in Japanese Patent Application Laid-Open No. 05-327962 (1993). In this terminal device with a facsimile function, received facsimile data of a prejudged amount from the top thereof is displayed at a display unit as source information.
At the above terminal device with a facsimile function, however, only data of a prejudged amount from the top of received facsimile data is displayed at the display unit as described above, since the screen of the display unit is small. Consequently, the screen gets into a blank state in which nothing is displayed when data of a prejudged amount from the top is null data (blank).
For this reason, an operator of the above terminal device with a facsimile function might be misled into thinking that receiving has failed even though facsimile data has been received.

Image displaying method, image display apparatus and facsimile apparatus for displaying effective data on display screen


Provided are a seed-specific expression promoter derived from sesame microsomal oleic acid desaturase (Si-FAD2) gene, an intron for expression enhancement, a seed-specific expression vector including the promoter and/or the intron, and a transgenic plant transformed with the seed-specific expression vector. Therefore, a useful product can be produced in a seed-specific manner or a common product in a seed can be functionally modified. Also, the promoter can be used together with the intron for expression enhancement, thereby increasing the expression level of an inserted gene in a seed. Therefore, it is very useful in development of a transgenic plant which induces large-scale expression of a foreign gene in a seed-specific manner.

Fatty acids of plants are important components that make cell membranes and seed oils. In particular, microsomal oleic acid desaturase, which is present in the endoplasmic reticulum of plant cells, is an enzyme that catalyzes the conversion of monounsaturated fatty acid, oleic acid, at the sn-1 and sn-2 positions of phosphatidylcholine, into diunsaturated fatty acid, linoleic acid.
There have been reports about presence of genomic genes (FAD2) encoding the microsomal oleic acid desaturase in Arabidopsis, Petunia, and cotton. According to the reports, while one FAD2 gene is present on the genome of Arabidopsis, two or more FAD2 genes are present on each genome of Petunia and cotton [Okuley et al., 1994, Plant Cell; Verwoert et al., 2000, Biochemistry Society Transactions; Pirtie et al., 2001, Biochimica et Biophysica Acta]. In particular, it has been known that when two or more FAD2 genes are present on a plant genome, at least one is involved in production of linoleic acid that accumulates in a seed oil. Until now, while the presence of the FAD2 gene in the above-mentioned three plants has been reported, no studies on the functional analysis of its promoter have been reported.
Recently, many attempts have been made to improve genetic characteristics of plants using genetic engineering technology. In this respect, expression of a useful foreign gene in a transgenic plant requires a promoter for the gene expression. For this, conventionally, a promoter derived from a cauliflower mosaic virus (CaMV35S) gene that induces gene expression at all tissues of a plant has been widely used. However, this promoter cannot induce seed-specific gene expression. Meanwhile, there have been reports about promoters that induce tissue-specific expression, for example, seed-specific expression [Plant Cell Technology, 1991, 3: 568-576], leaf- or flower-specific expression [Science, 1990, 250: 931-936], and root-specific expression [Plant Cell Technology, 1991, 3: 577-587]. However, the above seed-specific expression promoter induces gene expression during whole stages for seed development, not during a specific development stage.
In view of these problems, based on the fact that the microsomal oleic acid desaturase derived from sesame is specifically expressed during a seed development stage, the present inventors cloned the genomic gene encoding microsomal oleic acid desaturase and its promoter, inserted the promoter into a binary vector and a transient expression vector, and then introduced the vectors into the seeds of model plants, Arabidopsis and sesame. As a result, the present inventors found that the sesame microsomal oleic acid desaturase (Si-FAD2) promoter is a novel promoter that induces the expression of a foreign gene in a seed development stage-specific manner, and completed the invention.
Furthermore, a 127 bp active fragment of the promoter essential for the seed-specific expression has been identified. Also, the present inventors found that when the promoter is used together with an intron present on the Si-FAD2 gene, the expression level of a foreign gene in a seed is enhanced by at least 40-fold, and completed the invention. In this regard, the intron is useful in high expression of a useful foreign gene.
Therefore, the present invention provides a seed-specific, in particular, a seed development stage-specific expression promoter derived from the Si-FAD2 gene and a 127 bp active fragment thereof.
The present invention also provides an intron that enhances the expression level of a foreign gene under the control of the above-described seed-specific expression promoter.
The present invention also provides a seed-specific expression vector containing the above-described promoter and/or intron and a transgenic plant transformed with the seed-specific expression vector.
The present invention also provides a method for expressing a foreign gene in a transgenic plant using the above promoter. This method is useful in producing a useful product in a seed development stage-specific manner or functionally modifying conventional product in seeds.

Plant seed-specific expression promoter derived from sesame and seed-specific expression vector comprising the promoter


An absorbent article such as a diaper, an incontinence guard or a sanitary napkin includes a liquid-permeable outer sheet, a liquid-impermeable bottom sheet and an absorbent body placed therebetween. The outer sheet and the absorbent body are at least partially joined together with a hydrophilic glue.

Hydrophilic glues are previously known from EP-A 1,297,769 for instance. This document describes a hydrophilic glue composition which can be used conveniently in products that are to be fastened to the skin, such as bandages.
U.S. Pat. No. 4,785,030 teaches a latex composition which when the liquid phase is removed, forms a film whose surface is hydrophilic. The latex composition can be used as a glue for fabric-like paper products.
U.S. Pat. No. 5,356,405 discloses adsorbent articles with a fast liquid transport through the outer layers to an absorbent body. This is achieved by arranging capillary channel fibres between the outer sheet and the absorbent body.
U.S. Pat. No. 5,356,963 describes hydrophilic hot melt adhesives for use in remoistenable applications. The document briefly mentions that the adhesives can be used in envelopes, bag sealing, bookbinding, diapers etc. without giving any construction details.
A surface sheet of an absorbent article, such as a diaper, an incontinence guard or a sanitary napkin, is normally comprised of nonwoven material, which is usually hydrophobic. In order to enable fluid, such as urine or menstruation fluid, to pass through this outer layer, the nonwoven layer is treated with a surfactant in order to make it hydrophilic. In order for a material to be considered to be hydrophilic, it must have a wetting angle of less than 90.degree.. Repeated wetting of the material will wash out the surfactant and the surface material will then become hydrophobic. This makes it difficult for liquid to pass down through the surface layer.

Absorbent article such as a diaper, an incontinence guard, a sanitary napkin or like article


A testing system includes an integrated circuit having an analog design under test and a processor; an digital-to-analog converter (DAC), coupled to the analog design under test and the processor, for converting a digital testing sequence output of the processor into an analog testing sequence fed into the analog design under test; a analog-to-digital converter (ADC), coupled to the analog design under test and the processor, for converting an analog testing response of the analog design under test into a digital testing response fed into the processor; and an external tester, coupled to the processor of the integrated circuit, for sequentially outputting a program sequence to the processor; wherein the processor executes the program sequence without un-predictable conditional jump to get a testing result of the testing system and then outputs the testing result to the external tester.

The present invention relates to a testing system for an integrated circuit, and more specifically, to a testing system and related testing method for an analog design under test of an integrated circuit using a built-in processor to execute a program sequence without conditional jumps.
Please refer to FIG. 1. FIG. 1 shows a block diagram of a conventional analog testing system 100. Traditionally, to test a plurality of analog design under tests (DUTs) 102, 103 of an integrated circuit 104 (for example, a SOC design) requires an analog channel of an external test machine 101 electrically connecting analog DUTs and external test machine 101. Certainly, the performance of this kind of analog testing system 100 is limited due to a settle time required to stabilizing signals transmitted between external test machine 101 and the integrated circuit 104. For example, when starting a new test session, the settle time for this new test session increases the whole testing time. Moreover, resolution of the analog channel of external test machine 101 also plays an important role. Obviously, these issues are closely related to cost and price of the external test machine 101.
Please refer to FIG. 2. FIG. 2 shows a block diagram of a conventional analog testing system 200 with an external processor 201. As shown in FIG. 2, the analog testing system 200 includes an external processor 201 coupled to an integrated circuit 206, where the integrated circuit 206 has a plurality of analog design under tests (DUTs) 202, 203, a built-in digital-to-analog converter (DAC) 204, and a built-in analog-to-digital converter (ADC) 205. The analog testing system 200 tests analog design under tests 202, 203 with a built-in DAC 204 used to convert a digital testing sequence generated from the external processor 201 into analog domain and feed the converted signals into the analog design under tests 202, 203. Then, the built-in ADC 205 is utilized to convert a testing response of the analog design under tests 202, 203 into digital domain for further processing and determination. With the help of built-in ADC 205 and DAC 204, the settle time of the testing system 200 is substantially reduced. Moreover, cost of analog testing is lowered, accordingly.
As shown in FIG. 1 and FIG. 2, no matter using external test machine 101 or external processor 201, ADC 205 and DAC 204 for testing analog under tests 102, 103, 202, 203, it requires an analog signal generator and a measuring tool. Using DAC 204 and ADC 205 together with external processor 201 as the analog signal generator to generate test patterns and the measuring tool for analyzing test results respectively has many advantages. For instance, if a testing sequence, i.e. the output of the DAC 204, is changed or the measuring point, i.e. the input of the ADC 205, is altered, it will not induce any extra settle time for starting the corresponding analog testing procedure because DAC 204 and ADC 205 are built-in. Analog testing system 200 certainly reduces the operating time required for analog testing. However, to realize analog testing system 200 as mentioned above, in most case external processor 201 is generally implemented as a testing module of external test machine 101 as shown in FIG. 1 Cost of external processor 201 will certainly increase the cost of applying this kind of testing system.
Please refer to FIG. 3. FIG. 3 shows a block diagram of a conventional analog testing system 300 using an internal processor 301, built-in DAC 304, built-in ADC 305, together with an internal memory 306 and a program loader 308. Built-in DAC 304 and built-in ADC 305 are connected to analog design under test 302 and 303. As shown in FIG. 3, the analog testing system 300 has an integrated circuit 307 coupled to a program loader 308, where the integrated circuit 307 includes an internal processor 301, a plurality of analog design under tests (DUTs) 302, 303, a built-in digital-to-analog converter (DAC) 304, a built-in analog-to-digital converter (ADC) 305, and an internal memory 306. In this testing system 300, internal processor 301 plays the role as external processor 201 shown in FIG. 2 but has an advantage of reducing the cost of testing module of the external test machine by using a processor which is originally embedded in the integrated circuit 307. However, the analog testing system 300 needs extra efforts such as applying a processing program for controlling internal processor 301 to generate the testing sequence and to measure the testing response to make decision if the analog testing result is pass or fail. To this end, the processing program must be input to internal processor 301 in a form of program sequence. Moreover, since the processing program must do conditional logical operation to decide if the analog testing result is pass or fail, executable codes for doing the logical operation in all kinds of conditions must be preloaded into the internal memory 306 through the program loader 308 so that the processing program is able to do logical operation, such as perform an "if" condition or an "else" condition. For example, a program sequence PROGRAM—1 (only part of the program sequence is illustrated) with conditional jumps is shown as below:
Line1: int result; //0 means testing failure, 1 means testing pass
Line2: if (analog_measure—1 meet spec—1) {result=1;}
Line3: else {result=0;}
In PROGRAM—1, if a condition "analog_measure—1 meet spec—1 is true, then the program sequence will conditionally jump to "result=1" in Line2. Otherwise, if the condition is false, the program sequence will conditionally jump to "result=0" in Line3. For storing these two conditions in Line2 and Line3 previously, it requires more cost in internal memory 306 and time for preloading the program sequence PROGRAM—1 into the internal memory 306, which could possibly dominate the whole testing time. In short, doing analog testing with analog testing system 300 is not efficient enough because the program with conditional jump operations need to be loaded into internal memory 306 first.

Testing system and related testing method for an analog design under test


A semiconductor device includes a square pellet, a gate electrode pad, a drain electrode pad, a pair of source electrode pads, and a source electrode path. The pellet has first and second diagonal lines. The gate electrode pad is arranged on one of two corners located on the first diagonal line on the pellet. The drain electrode pad is arranged on the other of the two corners located on the first diagonal line on the pellet. The pair of source electrode pads are arranged on two corners located on the second diagonal line on the pellet. The source electrode path connects the source electrode pads to each other.

The present invention relates to a semiconductor device and, more particularly, to a microwave transistor.
A low-noise transistor having a pattern as shown in FIG. 4 is conventionally widely used as a low-noise amplifying element for microwaves in the C to Ku bands. This pattern has a gate finger 12a, gate electrode pads 12, a source electrode pad 14, and a drain electrode pad 13. The gate finger 12a is straightly arranged on a pellet 11. The gate electrode pads 12 are led out from portions midway along the gate finger 12a to one side. The source electrode pad 14 surrounds the gate electrode pads 12. The drain electrode pad 13 is arranged on the other side of the source electrode pad 14 through the gate finger 12a. This pattern is called the .pi. type pattern. Bonding wires 16 are connected to the respective electrode pads 12, 13, and 14 through bonding balls 17.
In contrast to the .pi. type pattern, a low-noise transistor which forms a pattern by using aerial wirings has been developed in recent years. As shown in FIG. 5, this pattern has, e.g., a gate electrode pad 22, four gate fingers 22a, an H-shaped source electrode pad 24 and a source electrode path 24b, a source finger 24a, a drain electrode pad 23, two drain fingers 23a, and aerial wirings 25. The gate electrode pad 22 is arranged on a pellet 21. The four gate fingers 22a are led out from the gate electrode pad 22 to be parallel to each other. The source electrode pad 24 and the source electrode path 24b are arranged to sandwich the gate electrode pad 22 and the gate fingers 22a. The source finger 24a is led out from the source electrode path 24b and is arranged in a region sandwiched between the two central gate fingers 22a. The drain electrode pad 23 is arranged on the other side of the gate electrode pad 22 through the source electrode path 24b. The two drain fingers 23a are arranged in the two remaining regions sandwiched between the gate fingers 22a. The aerial wirings 25 connect the drain fingers 23a to lie across the source electrode path 24b. This pattern is called the H type pattern. Bonding wires 26 are connected to the respective electrode pads 22, 23, and 24 through bonding balls 27.
In the .pi. type pattern shown in FIG. 4, the gate electrode pads 12 are surrounded by the source electrode pad 14. In the H type pattern shown in FIG. 5, both the gate electrode pad 22 and the drain electrode pad 23 are sandwiched by the source electrode pad 24. Therefore, the area of the gate electrode pads or gate electrode pad 22 and the area of the drain electrode pad 23 are limited by the source electrode pads 14 and 24. More specifically, within the pellets 11 and 21 having a limited size, it is impossible to form the gate electrode pads 12 and 22 and the drain electrode pad 23 to have a large size, and a defect tends to be caused by misalignment in bonding.

Semiconductor device with connected source electrode pads at diagonal corners


A calcined cracking catalyst comprising zeolite crystals in an inorganic oxide matrix and containing less than about 0.75% Na.sub.2 O and, from 0.1 to 10% P expressed as P.sub.2 O.sub.5, the cracking catalyst being further characterized by exhibiting a spectra with a peak at about 3735 cm.sup.-1 when treated with pyridine and analyzed by FTIR. A process for manufacturing an FCC catalyst characterized by high tolerance to contaminated metals comprises providing fluid cracking catalyst microspheres containing zeolite Y in an inorganic oxide matrix and analyzing 20 to 60% by weight Al.sub.2 O.sub.3 and analyzing less than 0.75% wt. Na.sub.2 O; impregnating the catalyst with a solution of a phosphate or phosphite salt in amount such the microspheres analyze 0.5 to 10% by weight P.sub.2 O.sub.5 and calcining the microspheres in the absence of steam at a temperature above 1300.degree. F. and below 1600.degree. F. and recovering the product characterized exhibiting a spectra with a peak at about 3687 cm.sup.-1 and the intensity ratio of the peak at 3687 cm-.sup.1 to the peak at 3675 cm-.sup.1 is greater than about 0.8 when treated with pyridine and analyzed by FTIR.

In recent years the oil refining industry has shifted to processing a larger quantity of resid. Since the early 1980's many refiners have been processing at least a portion of residual oil as a feedstock in their units and several now crack a full residual oil in their units. Processing resid can drastically reduce yields of valuable products when compared to cracking a light feed.
Several factors are important to resid catalyst design. It is highly favorable if the catalyst can help increase gasoline yields, upgrade bottoms, minimize coke and gas formation, maximize catalyst stability, and minimize deleterious contaminant selectivity due to metal contaminants in resid feedstocks such as nickel and vanadium. It is well known that metal contaminants in oil feedstocks significantly adversely affect the performance of zeolitic cracking catalysts to various degrees depending inter alia on the matrix (non zeolite) portion of the cracking catalyst. Various additives ranging from antimony, tin, alumina and sources of phosphorus have been added to feedstock or incorporated in the catalyst or used in solid particles co-circulated with cracking catalyst particles in the cracking cycle to ameliorate the effects of metals.
While many present day catalysts show good yields of desired products, especially gasoline, even when used with feeds severely contaminate with Ni and V, further lowering of coke and dry gas yields, and in particular hydrogen yields, would be desirable to improve the catalytic cracking process.
U.S. Pat. No. 4,430,199 commonly assigned, Brown et al, teaches addition of a phosphorus compound to a zeolitic cracking catalyst (or component of such catalyst), preferably prior to contamination, or to feedstock to reduce gas and coke make due to contamination by metals. Among the phosphorus compounds was ammonium hydrogen phosphate. In illustrative examples, the catalyst was a rare earth exchanged catalyst commercially supplied by assignee under the trademark HEZ-55. Such catalyst is prepared from precursor microspheres composed of the spinel form of calcined clay mixed with a small amount, e.g., 5% by weight or less of the mixture of microspheres, of the metakaolin form of calcined clay. The mixture is reacted with a sodium hydroxide solution resulting in the crystallization of about 20-25% zeolite Y in a spinel derived matrix. Because the finished catalyst has essentially the same size and shape as the precursor microspheres, the catalyst is referred to as an "in situ" catalyst. See, for example, U.S. Pat. No. 3,506,594, Haden et al, commonly assigned. We found that HEZ-55 catalyst does not exhibit the unique feature of catalysts within the scope of this invention.
U.S. Pat. No. 4,454,241, Pine et al, teaches treating a partially cation exchanged calcined zeolite containing clay derived catalyst preferably of the type allegedly described in U.S. Pat. No. 3,663,165, assigned to the assignee of the subject patent application, with a dihydrogen phosphate anion or a monohydrogen phosphate anion. This phosphorus treatment is applied to a partially cation exchange intermediate of a catalyst and not to fully exchanged catalyst which must subsequently be calcined. This particular phosphorus treatment is intended to increase cracking activity when operating with conventional feed and is not intended to passivate metals when cracking contaminated feed.

Catalyst for cracking oil feedstocks contaminated with metal


A system-wide service can simultaneously harden multiple running JITs, for example by hooking into the memory protections of a target operating system and randomizing newly generated code on the fly when marked as executable. Some embodiments preserve the contents of the calling stack, presenting each JIT with the illusion that it is executing its own generated code.

The present invention relates generally to protection of software programs, and more particularly to protection of just-in-time compiled code.
A just-in-time (JIT) compiler transforms a program written in a high-level language (HLL), generating native code at program run-time. The compiler emits native code into a code cache, after parsing and optimizing high level language (HLL) source code. The compiler itself is written in another programming language, which may be called the host language. JIT compilers also contain a language runtime, which is a library of functions that are written in the host language and provide or manage access to system resources. Some examples of such resources are files, networks, operating system threads and complex data structures (maps, trees). When compiling a HLL program, the JIT compiler emits native calls into the runtime whenever the program uses these resources. FIG. 5 shows a high-level structure of a JIT compiler 511 and its interactions with the generated code, which is written into an executable portion of memory 513. After emitting all or part of the native code (usually enough code to start execution of the program), the compiler branches to an entry point 515 of the HLL program. The generated code continues execution, calling into other generated functions or the language runtime. The HLL program continues until termination, making repeated calls into the runtime whenever needed.
From a security point of view, JIT compilers have one characteristic that is important in our context: predictability. As JIT compilers usually optimize code for performance, there are only a few optimal translations of HLL code to native code, and a JIT compiler emits one of these.
Our computing infrastructure depends on high performance delivered by just-in-time (JIT) compilers to a large degree. Efficiently executing JavaScript is generally a prerequisite for complex Web 2.0 applications. Similarly, Java's success rests on performance delivered by efficient dynamic code generation. From the early beginnings, JIT compilers had to focus on producing code quickly. Usually, they achieve this by optimizing the common case and forgoing time-intensive optimizations altogether. As a result, this leads to highly predictable code generation, which attackers exploit for malicious purposes. This is evidenced by the rising threats of JIT spraying and similar attacks on sandboxes in JITs. The former is particularly interesting: JIT spraying relies on JIT compilers emitting constants present in input source code directly into binary code. Due to variable length encoding, attackers can encode and subsequently divert control flow to arbitrary malicious code arranged this way.
This attack vector is innate and specific to JIT compilers. From a security perspective, the state-of-the-art in the field is to address JIT spraying by encrypting and decrypting constants. This addresses the code injection part of JIT spraying, but attackers can fall back on code-reuse techniques. Specifically, return-oriented programming for JIT compiled code is also problematic. Instead of finding gadgets in statically generated code (as they would do an a generic return-oriented programming attack), an attacker uses the JIT compiler to create new binary code containing the necessary gadgets by supplying specially crafted source code. The ubiquity of JIT compilers amplifies this security risk to such a degree that JITs become a liability.
When presented with the same HLL code many times repeatedly, a compiler will emit the same native code; attackers can use this characteristic to their advantage. This is not a problem specific to JIT compilers, but compilers in general; however, predictability of JIT compilers has not been fully explored.
JIT spraying is one recent attack that relies on predictability of JIT compilers. This attack is a form of code injection targeted at dynamically generated code. In its original form, it relies on one unintended behavior of many JIT compilers: HLL program constants reach native code unmodified, therefore becoming part of the executable code. The attacker injects short sequences (32-bit constants in the original paper), and later jumps to the injected sequence through a separate attack vector. For the attack to work, the attacker must also predict the remaining bytes inserted between the controlled sequences, and use those bytes as part of the payload; this is often possible in practice, due to the predictability of the compiler. This allows the attacker to execute arbitrary native code, even when running on a compiler that runs the generated code in a sandbox (with restricted access to memory, for example).
For many years, most arbitrary code execution attacks used the same method of gaining control of the program: code injection attacks. To prevent these, most operating systems now forbid the same page to be both writable and executable at the same time. Sidestepping this measure, a new class of attacks against applications surfaced and gained popularity: code reuse attacks. Instead of adding new executable code to an application, code reuse attacks locate reusable code sequences inside the application, then thread these sequences into a program written by the attacker. Shacham described one of the first versions of this attack, called Return-Oriented Programming (ROP); he named the code sequences gadgets. A gadget is simply a valid sequence of binary code that the attacker can execute successfully (the gadget decodes correctly and does not contain invalid instructions); a gadget can start anywhere inside the generated code (including in the middle of a proper instruction) and spans one or more of the original instructions emitted by the compiler. ROP uses only gadgets that end in a RET instruction (encoded by the C3 byte on x86); the attacker places addresses of gadgets on the stack on consecutive stack slots, so that each gadget proceeds to the next one using a return. Later work extends this idea to other indirect branch instructions.
This attack is even more potent in the presence of a JIT compiler, as an attacker that controls HLL code can emit an arbitrary amount of native code containing gadgets (by emitting as much HLL code as needed to generate all the gadgets for the attack). For example, this can be a problem for web browsers that include a JavaScript compiler, as many web pages include JavaScript code from unreliable (or hostile) sources. Another problem is that current anti-ROP defenses target ahead-of-time compilers or binary rewriters, but do not offer protection to dynamically generated code.
Recent work addresses code-reuse attacks by attacking its foundation: the software monoculture. By diversifying the binary code, attackers cannot construct reliable attack code, because the binary code layout differs for each end-user. Consequently, diversity increases the costs for attackers, ultimately rendering them too costly. Unfortunately, existing approaches to artificial software diversity do not protect dynamically emitted code from a just-in-time compiler.

Code randomization for just-in-time compilers

The Regents Of The University Of California


A shoe having a preassembled spring assembly incorporated into the sole thereof is provided. The spring assembly includes a pair of plates having a plurality of apertures formed therein. The pair of plates define an upper plate and a lower plate in which the apertures formed in the upper and lower plates are axially aligned when the upper plate is disposed directly above the lower plate. A plurality of spring members are disposed between the upper and lower plates. The spring members are axially aligned with the plurality of apertures. A mechanism for retaining the spring members between the upper and lower plates is also provided. The mechanism for retaining is designed for retaining the upper and lower plates at a predetermined distance.

1. Technical Field
The present invention relates generally to footwear and more particularly to athletic-type shoes having a spring assembly module integrated into the sole and/or heel of a shoe for cushioning the impact forces placed thereon.
2. Discussion
As is generally known in the art, footwear is currently comprised of a sole made of foam, plastic, rubber, or leather in various forms and densities. A manufactured upper made of nylon fabric, plastic or leather in various combinations is then attached to the sole. As the wearer of the shoe walks, jogs, or runs in the shoe, the harder plastics and foams forming the sole give the shoe shape and support while the softer foams give comfort and absorb the shock of the foot pounding onto the hard surfaces of a court, street, or sidewalk. As the foam absorbs the impact energy from the walking or running forces, it converts some of that energy into shape deformation. Most of the remaining energy is converted into heat. Thus, the temperature inside the shoe can easily exceed 130.degree. F. As the foot gets hot, the body tries to manage the excess heat and the foot sweats. The sweat contains moisture, salt, ammonia and other chemicals that, together with the heat, attack and degrade the plastics, foams and rubber components of the shoe.
Additionally, the foam takes an increased set with more use resulting in less effectiveness in absorbing the impact forces. It is commonly recommended that shoes be used every other day to give the shoes a chance to dry out and for the foam to regain its shape, though the shape will never return entirely. Shoe manufacturers also recognize that the shoe's capability to absorb shock can be seriously degraded after only 100 miles of hard running.
In an attempt to overcome this problem, air bags or air bladders of various shapes have been used with some success to absorb shock and provide additional comfort. The currently used air bags are able to return more energy to the wearer through a higher rebound rate thereby converting less energy to heat. However, these air bags are also made of plastic which is susceptible to degradation problems resulting from the heat and chemical attack of the operating environment. As they degrade, air bags lose air and their strength. Air bags also have less stability as the air "squirts" away from the impact load requiring additional means of support to be utilized by designers to provide more stability to the shoe.
Accordingly, it is desirable to provide a device for absorbing the impact forces imparted on footwear which is lightweight and less sensitive to the destructive effects of heat and chemicals within the operating environment. It is further desirable to provide an impact absorbing device which does not break down structurally with extended use, and is further capable of returning a higher level of energy to the wearer during a walking or running activity.

Footwear having spring assemblies in the soles thereof


A rake adjustment mechanism for an electronically adjustable steering col disclosed.

The present invention relates to is directed to an adjustable steering column where the rake, or up and down motion of the steering wheel is controlled electronically. In prior adjustable steering columns, a linkage was used to translate the curved or arcuate motion of the pivoting steering column as the rake adjustment was made. Such linkages take up space in an area of the vehicle where space is at a premium. In addition, such linkages are expensive to manufacture and maintain, and have lash or undersirable movement. There is a need in the industry for an electronically adjustable rake mechanism that accommodates the rake adjustment is a smaller space while being easy and cost effective to manufacture.


According to an embodiment, management server includes estimator, scheduler, acquisition unit, monitoring unit, receiver and setting unit. Estimator calculates estimated value of energy demand in building with electric appliance. Scheduler creates schedule of appliance based on estimated value. Acquisition unit acquires actual value of energy demand. Monitoring unit monitors error between estimated value and actual value. Receiver receives DR signal containing information which prompts suppression of energy consumption in a designated period. Setting unit sets threshold. Estimator recalculates estimated value if error is equal or more than threshold. Scheduler reforms schedule based on the recalculated estimated value.

Buildings and factories consume large amounts of energy. The energy consumption amount of the commercial sector is particularly large and probably reaches 20% of the whole. Therefore, effective energy-saving measures are required in buildings. Also, the recent increasing severity in power demand and supply has caused upper limits to be placed on the power consumption of large users (customers). Accordingly, energy-saving techniques such as peak cutting and peak shifting to reduce energy consumption are attracting attention.
Energy-related apparatuses include various apparatuses such as an energy-consuming apparatus, energy-creating apparatus, and energy-storing apparatus. To effectively use energy, it is important to make these energy-related apparatuses cooperate with each other. For example, it is important to create an all-inclusive operation schedule to operate the energy-related apparatuses.
There is a proposal for determining an operation schedule capable of minimizing the energy consumption amount, cost, and CO2 generation amount in a predetermined period of an energy supply facility including a heat storage tank. Another proposal for increasing the overall energy efficiency of a building involves making an apparatus using renewable energy (e.g., a PV (PhotoVoltaic) system or solar water heater) cooperate with a storage battery, a heat storage device, or an existing electric apparatus.
A technique called demand response, by which an energy supplier requests a customer to suppress energy consumption, is also known. When a building or factory receives a DR (Demand Response) signal, an energy-saving target value, power-saving target value, or the like is changed, and an operation schedule is also changed accordingly. A measure for when a structure such as a building or factory has received the DR (Demand Response) signal is presently being examined. Related techniques have been applied as patents.
To timely execute an accurate operation schedule, it is desirable to reexamine an estimated demand immediately after the DR signal is received, and re-plan the operation schedule as needed. However, no technique for practically implementing the processing as described above is known.

Energy management server, energy management method, and program


A manually operated switch for a faucet has a body, an inner pipe, a switching valve assembly. The body is hollow. The inner pipe is located inside of the body and has a flowing way. The flowing way is formed through the inner pipe. The switching valve assembly is slidably mounted inside of the flowing way of the inner pipe and extends out the body. When the switching valve assembly closes the flowing way of the inner pipe, the water pressure will keep the switching valve assembly closed. After the water pressure applied to the switching valve assembly is released or dismissed, the switching valve assembly returns back to an original position so that the flowing way is opened. The opening and closing flowing way can manually control the way of water flowing so that a user may not be scared or burned by the water.

1. Field of the Invention
The present invention relates to a faucet, and more particularly to a manually operated switch for a faucet that is able to prevent an user being scared or burned by the water unintentionally sprayed from a shower head.
2. Description of Related Art
With reference to FIG. 5, a conventional faucet for a water pipe in accordance with the prior art comprises a body (90), a baffle (92) and a shower-driver knob (93).
The body (90) is attached to the water pipe and has a top, a bottom, a handle, a water channel (91), an upper hole, a lower hole and a shower head. The handle is pivotally mounted on the top of the body (90) to allow water to enter into the body (90) from the water pipe. The water channel (91) is formed inside of the body (90) and allows the water from the water pipe to pass through the body (90). The top hole is formed in the top of the body (90) and communicates with the water channel (91). The lower hole is formed in the bottom of the body (90), communicates with the water channel (91) and corresponds to the top hole. The shower head is connected to the lower hole of the body (90).
The baffle (92) is mounted at the water channel (91) to divide the water channel (91) into an upper channel and a lower channel and has a hole. The hole is formed in the baffle (92) and corresponds to the upper hole and lower hole of the body (90).
The shower-driver knob (93) is slidably mounted between the upper hole of the body (90), the hole of the baffle (92) and the lower hole of the body (90) and near the handle of the body (90) and has a bottom and a stopping valve (94). The stopping valve (94) is mounted at the bottom of the shower-driver knob (93) and selectively closes the lower hole of the body (90) or the hole of the baffle (92).
When the shower-driver knob (93) is pulled upward, the stopping valve (94) closes the hole in the baffle (92). The water from the water pipe enters into lower channel of body and is sprayed from the shower head.
When the shower-driver knob (93) is pushed downward, the stopping valve (94) closes the lower hole of the body (90). The water from the water pipe will enter into upper channel of body and is exhausted from the body (90).
A common requirement of the shower-driver knob (93) requires the shower-driver knob (93) to close the lower hole of the body (90) within 90 seconds after the lower hole of the body (90) is opened. However, if a user turns off the faucet for a while and then turns on the faucet again, the water may be sprayed form the shower head within 90 seconds. The spraying water may wet or scare the user. Furthermore, if the spraying water is at a high temperature, the hot water may burn the user so that the shower-driver knob (93) is not safe in use.
During transiting of pulling upward and pushing downward the shower-driver knob (93), the water is continuously exhausted from the body (90) to cause waste of water.
The shower-driver knob (93) and the handle of the body (90) are closed to each other. The user may accidentally switch the shower-driver knob (93) or the handle of the body (90) so that the water may unintentionally be exhausted from the body (90) or the shower head of the body (90) or be turned off.
To overcome the shortcomings, the present invention provides a manually operated switch for a faucet to obviate or mitigate the aforementioned problems.


Millimeter-wave optical imaging systems and methods. In one example, a mm-wave optical imaging system includes a mm-wave imaging detector located at a focal plane of the optical imaging system, an immersion lens directly coupled to the imaging detector and configured to focus the electromagnetic radiation onto the imaging detector, the immersion lens having a curved first surface and an opposing planar second surface, wherein the focal plane is located on the planar second surface and the imaging detector is directly coupled to the planar second surface, a positive power primary mirror configured to reflect the electromagnetic radiation towards the immersion lens, and a Schmidt aspheric corrector configured to receive and direct the electromagnetic radiation towards the primary mirror, wherein the system aperture stop is located on the Schmidt aspheric corrector.

The millimeter-wave (mm-wave) region of the electromagnetic spectrum (wavelengths on the order of a few millimeters or centimeters, for example) is used for a variety of communications applications. Additionally, there exist some mm-wave imaging systems. For example, U.S. Pat. No. 6,919,988 describes an example of a combined mm-wave and infrared imaging system. Generally, mm-wave transceivers have a very small field of view and therefore must be pointed over some larger field of regard. Pointing is often achieved using a classical gimbal arrangement, which requires additional volume, weight, and power to implement. Conventional attempts to achieve a "wide" field of view in mm-wave optics have been limited to a range of approximately 4-5 degrees.

Compact short flat-field schmidt optics for mm-wave operation


The invention provides a belt including a belt base having elasticity and a projection member having elasticity which is provided along at least one edge of the belt base so as to project from the belt base, and an adhesive layer which bonds the belt base and the projection member, wherein the ten-point average roughness Rz in the region of the belt base to be bonded with the projection member is about 4 μm or more and the ten-point average roughness Rz in the region of the projection member to be bonded with the belt base is about 6 μm or more.

(i) Technical Field
The present invention relates to a belt, and, particularly, to a belt suitable as an intermediate transfer belt and as a sheet conveyer belt that are used in image forming devices such as electrophotographic copying machines and printers, and to an image forming device provided with the belt.
(ii) Related Art
In image forming devices such as copying machines and printers utilizing a electrophotographic system, an electrostatic latent image formed on the surface of an image carrier by known electrophotographic processes is developed on the image carrier to form a toner image thereon. Then, this toner image is transferred electrostatically onto a recording medium using a transfer device, thereafter the toner image is fixed onto the recording medium, for example, by means of a heat fixing mechanism, to form an image.
When a belt is used in the transfer device that transfers the toner image onto the recording medium, the belt is trained over plural tension rolls and rotated in a predetermined running direction, thereby enabling conveying of the recording medium in a circulating manner. In transfer devices of such type, a phenomenon may occur, so-called belt walk, wherein the belt is shifted in the direction of the axis of the tension rolls, due to the dimensional tolerance of component parts constituting the transfer device or variation in parallelism and outer diameter of the tension rolls. If the image forming device is driven when this belt walk is present, the belt may be wrinkled, causing image unevenness, or even break.
On the other hand, an intermediate transfer type transfer device is used as the transfer device in some cases, from the viewpoint of advantages in conveying of paper, and the like. A system of intermediate transfer type has already been proposed, in which toner images of respective color components are sequentially formed on the image carrier, then the toner images of respective color components are primarily transferred onto the intermediate transfer body temporarily, thereafter the transferred multilayer toner images formed on the intermediate transfer body are secondarily transferred onto the recording medium, collectively, and thereby a color image is obtained. As the intermediate transfer body, one in the form of a belt or drum is commonly used. When a belt is used as the intermediate transfer body, belt walk may occur, as is the case of the aforementioned transfer device not using the intermediate transfer body.
Also, a belt having elasticity is used as the belt to meet the needs for higher quality image and operation speed, in some cases. Generally, in image forming devices using an elastic belt, the elastic belt is used in an expanded manner. Therefore, when a member forming a rib is attached to the elastic belt, it is more likely that the rib is peeled off than in the case where a resin belt is used, due to differences in thermal expansion coefficient, elastic modulus or the like, between the belt, adhesive and the rib.

Belt and image forming device using the same


A keyboard structure. The keyboard structure includes a base plate, a light guide member, a membrane circuit board, a key assembly and a light-emitting element. The light guide member is disposed on the base plate. The membrane circuit board is disposed on the light guide member. The key assembly is disposed on the membrane circuit board, with a key cap and a resilient element between the key cap and the membrane circuit board. The light-emitting element is adjacent to the light guide member and is disposed under the membrane circuit board. Light from the light-emitting element enters the resilient element and key cap via the light guide member.

1. Field of the Invention
The present invention relates to a keyboard structure, and in particular to a keyboard structure that provides uniform illumination of the keys thereof.
2. Description of the Related Art
Generally, illuminated keyboards or keypads have been deployed in portable computers or cellular phones to enhance versatility thereof.
Referring to FIG. 1, a conventional illuminated keyboard structure 2 includes a base plate 21, a membrane circuit board 22, a resilient element 23, a key cap 24, a light source 25 and a light guide plate 26. The light guide plate 26 is disposed on the base plate 21 and membrane circuit board 22. The light source 25 is disposed between the membrane circuit board 22 and the light guide plate 26. Light from the light source 25 enters the key cap 24 via the light guide plate 26, illuminating the key cap 24.
Nevertheless, as shown in FIG. 1, the light guide plate 26 has a complex shape, such that manufacture thereof is difficult. Additionally, uniform illumination of the central area of the key cap 24 is difficult to achieve due to the structure of the light guide plate 26.
Hence, there is a need to provide an improved keyboard structure. The present keyboard structure is simplified and provides uniform illumination.


A lighting module is provided that includes a single-piece lens having an input surface including a plurality of near-field lens elements, and an exit surface, each element having a different focal length. The lighting module also includes light-emitting diode (LED) source positioned to direct incident light through the input surface. Further, the elements are configured to shape the light from the input surface into a collimated light pattern emanating from the exit surface containing at least 60% of the incident light.

Conventional vehicle headlamps employ multiple components (e.g., a light source, collector, and light distributor). These headlamps are also subject to dimensional constraints associated with the lens shapes necessary to produce the required light output pattern (e.g., low-beam headlamp pattern, high-beam headlamp pattern, etc.). Light transmission efficiency is also a problem as conventional vehicular headlamps do not exceed 50% efficiency. Accordingly, these headlamps require significant energy usage. Hence, conventional headlamp options with a low profile and high light transmission efficiency are not available.
Vehicle lighting components with high transmission efficiency and design shape flexibility are therefore desirable to address these problems.

This patent is subject to a terminal disclaimer.

Low profile highly efficient LED lighting modules and assemblies


A resilient expansion joint insert member for insertion into the expansion joint between adjacent concrete floor slabs. As the concrete slabs move further apart due to settling or thermal contraction, insert member covers the widened gap. Likewise, as the concrete slabs move closer together due to settling or thermal expansion, the insert member is compressed and absorbs the force as the slabs move against each other. The flooring material on the slabs near the expansion joint move beneath a cap of the insert member.

When a concrete flooring surface is installed, a gap is ordinarily left between adjacent slabs of concrete. These gaps allow the concrete slabs room to move due to settling of a structure, and to expand and contract due to environmental temperature changes.
A typical concrete flooring surface consists of concrete slabs of large dimensions, such as by 30.times.30 feet square. Each slab is separated from adjacent slabs by a gap of approximately 1/2 inch. To provide a finished flooring surface, a flooring material such as vinyl or rubber tile is applied to the surface of the concrete slabs with the edges of the tiles even with the edges of the concrete slabs at each edge of the expansion joint. When adjacent concrete slabs contract, they separate, and they will carry the tile adhered thereto with them. If tile were laid over the crack, such as where it is filled with caulking, the tile will crack (it should not crack if it were laid up to the edge of crack of the flooring surface). Accordingly, the gap between the concrete slabs will also increase, thus causing a gap to appear between adjacent tiles applied to respective adjacent slabs of concrete. The ground may appear in the enlarged gap between the concrete slabs. In some cases, the exposed ground and enlarged gap may violate health codes. When adjacent concrete slabs expand and move closer together, the tiles adhered thereto may become damaged. In this respect, tiles adhered to adjacent concrete slabs may chip, crack, break or come unadhered from the concrete slab, as the tiles from adjacent slabs push against each other.
In view of the foregoing problems, there is a need for a device which can fill the gap between adjacent concrete slabs and prevent exposure of the gap and the underlying ground when adjacent concrete slabs move further apart, and for maintaining a generally continuous flooring surface when adjacent concrete slabs move closer.


A timing generator compensates the difference between the reference clock frequencies by converting the base number for generating the timing signals corresponding to the ratio of reference clock frequencies. The timing generator includes: a data memory for dynamically receiving the timing data through the software process to determine the time length of the timing signals where the timing data is formed of a quotient produced by a division of the time length by a time period of a reference clock and a fraction which is a remainder of said division; a counter for counting the number of pulses of a reference clock signal and generating an output signal when the number of counts of the pulse coincides with the quotient; an accumulator for accumulating the fraction data with the fraction data of previous cycle of the reference clock signal and generating a carry signal when the accumulated value exceeds the time period of the reference clock signal; a number converter which converts the timing data provided through the software process based on a first reference clock period Tn by a ratio of the first reference clock period Tn and a second clock period Tm; and means for providing a complementary number -Tm of the second reference clock period Tm to the accumulator.

In testing semiconductor IC devices by a semiconductor test system, such as an IC tester, the semiconductor IC device to be tested is provided with test signals for appropriate pins at a predetermined test timing, i.e., a tester rate. The IC tester receives output signals from the IC device under test generated in response to the test signals. The output signals are strobed, i.e., sampled, with reference to the tester rate, at predetermined delay timings to be compared with expected data to determine whether the semiconductor device functions correctly.
The timing signals for forming the tester rate and the delay times are basically generated by a highly stabilized reference clock oscillator such as a crystal oscillator. When the required timing resolution in an IC tester is equal to or an integer multiple of the shortest clock rate (a time period) of a reference clock oscillator, timing signals can be generated by simply dividing the reference clock by a counter and synchronizing the divided output with the reference clock.
However, a modern IC tester requires a higher timing resolution than the shortest clock rate (time period of one clock cycle) of the reference clock oscillator. For example, in case where a clock rate of a reference clock oscillator is 10 ns (nanosecond), the IC tester may require a tester rate of 32.5 ns and the delay timing of 6.2 ns from the start of test cycle. Furthermore, the modern IC tester dynamically changes such timings in a cycle by cycle basis based on a program, i.e., a software process.
To generate such timing signals of a timing resolution higher than the clock rate, it is known in the prior art that a combination of a counter and an accumulator can be used to form such timing signals while dynamically generating interpolation data based on a software program.
FIG. 10 is a block diagram showing an example of conventional semiconductor test system with an emphasis of a timing generator having the combinations of the counters and accumulators. The timing generator in FIG. 10 is generally formed of a rate generator 2 and a plurality of delay generators 3. A pattern generator 1 provides address data to the rate generator 2 to determine timings for each test pattern cycle. Although not shown, the pattern generator 1 also generates pattern data to determine a type of test signal and expected data to compare with resulting output signals from the device under test.
The rate generator 2 provides a tester rate RA and interpolation data RMD to the delay generator 3. The delay generator 3 provides a delay time defined by the interpolation data RMD to the tester rate RA. The delay generator 3 further provides a delay time on the basis of timing data provided in a timing memory therein. The test signal whose timing is thus determined by the delay generator 3 is wave shaped by a wave formatter 38 and is applied to a semiconductor device 4 through a pin electronics 39 which interfaces the IC tester with each pin of the IC device 4. In an actual IC tester, a large number of delay generators are prepared corresponding to input pins of an IC device to be tested.
The more detailed explanation of the conventional timing generator will be made with reference to FIGS. 10-12. The rate generator 2 includes a reference oscillator 20, a rate memory 21, an accumulator 22, registers 23 and 24, a counter 25, and a delay circuit 26. The reference oscillator 20 oscillates at a frequency f.sub.hz, for example 100 M.sub.HZ, which is a reference clock Ck and provides the reference clock Ck throughout the timing generator and other blocks of the IC tester. The rate memory 21 stores rate data which defines the tester rate RA for each test cycle. The rate data for the test signal is formed through a software process with various factors of surrounding circuit elements in mind.
The counter 25 receives a part of the rate data which is larger than the reference clock period T (=1/f.sub.HZ) of the reference clock Ck. The accumulator 22 receives a part of the rate data (fractional data) F which is smaller than the reference clock period T. The accumulator 22 adds the interpolation data RMD for the previous clock Ck provided from the register 23 to the fractional data F from the rate memory 21. For example, in a case where the desired tester rate for this cycle is 32.5 nanosecond, and the reference clock period is 10 ns, the data 30 ns (or simply 3 which is an integer multiple of 10 ns) is provided to the counter 25 and the fractional data 2.5 ns is provided to the accumulator 22.
The counter 25 is, for example, a download counter which counts the number of pulses of the reference clock Ck. When the count coincides with the data from the rate memory, the counter 25 generates a coincidence signal to be received by the delay circuit 26. When the data indicating 30 nanosecond is received by the counter 25, like the example above, the counter downloads the data by counting the number of reference clock pulses and generates a coincidence signal when counting three pulses.
When the accumulated data exceeds the reference clock period T, the accumulator 21 outputs a carry signal which is provided to the delay circuit 26 through the register 24. When the accumulated data does not exceed the reference clock period T, the resulting data is further added to the fractional data F from the rate memory 21 in the next cycle of the reference clock Ck. This process of accumulation is repeated throughout the generation of the timing signals in the IC tester.
When the carry is received by the delay circuit 26, the delay circuit 26 produces a tester rate RA at the timing of the reference clock Ck coming immediately after the carry. Thus, every time the carry is generated by the accumulator, the delay circuit provides one cycle delay to the output signal from the counter 25. The tester rate RA is supplied to the delay generator 3 to initiate the operation of the delay generator 3. The tester rate RA is also provided to the pattern generator 1 to access the next address of the rate memory 21. Further, in addition to the tester rate RA, the interpolation data RMD from the register 23 is received by the delay generator 3.
A carry is not generated until the accumulated value in the accumulator 22 is less than the reference clock period T. Thus, the output of the counter 25 is transferred as the tester rate RA without an additional delay time.
The delay generator 3 has a similar structure to the rate generator 2. The delay generator 3 includes a timing memory 31, an accumulator 32, registers 33 and 34, a counter 35, a delay circuit 36 and a variable delay circuit 37. The reference clock Ck is given to these circuit elements of the delay generator 3 to synchronize operations in the IC tester. The timing memory 31 stores timing data to determine the timings such as test signals and strobe signals further to the tester rate RA and the interpolation data RMD from the rate generator 2. The timing data for the timing memory 31 is formed through a software process with various factors of surrounding circuit elements in mind.
The counter 31 receives a part of the timing data which is larger than the reference clock period T (=1/f.sub.HZ) of the reference clock Ck in the manner same as the counter in the rate generator 2. The accumulator 32 receives a part of the timing data (fractional data) which is smaller than the reference clock period T. The accumulator 32 adds the interpolation data RMD for the previous clock Ck provided from the register 33 to the fraction data from the timing memory 21. As noted above with respect to the rate generator, in the case where the desired timing for the cycle is 32.5 ns, and the reference clock period is 10 ns, the data 30 ns is provided to the counter 35 and the fractional data 2.5 ns is provided to the accumulator 32.
The counter 35 is, for example, a download counter which counts the number of pulses of the reference clock Ck. When the counted data coincides with the data from the timing memory 31, the counter 35 generates a coincidence signal to be received by the delay circuit 36. Thus, when the data indicating 30 ns is received by the counter 36, like the example above, the counter 36 generates an output signal when counting three pulses of the reference clock CK.
When the accumulated data exceeds the reference clock period T, the accumulator 32 outputs a carry which is provided to the delay circuit 36 through the register 34. When the accumulated data does not exceed the reference clock period T, the resulting data is further added to the fractional data F from the timing memory 21 in the next reference clock Ck. This process of accumulation is repeated until the carry is generated by the accumulator within the tester rate.
When the carry is received by the delay circuit 36, the delay circuit 36 provides a delay time which is equal to one cycle of the reference clock Ck. A carry is not generated so long as the accumulated value in the accumulator 32 is less than the reference clock period T. Thus, the output of the counter 35 is transferred from the delay circuit 36 as the timing signal without additional delay time.
The output signal from the delay circuit 36 is provided with an additional delay time by the variable delay circuit 37. The delay time by the variable delay circuit 37 is determined by the sum of the fraction data from the timing memory 31 and the interpolation data RMD from the rate generator 2.
In the timing generator, a plurality of delay generators 3 are provided each of which is assigned with a corresponding test signal or a strobe signal to be used for testing the IC device. Further details of the operation of the timing generator of FIG. 10 are provided below with reference to timing charts.
Referring to FIGS. 11-13, the operation of the timing generator of FIG. 10 is explained for a case of generating a plurality of timing signals for IC testing. In this example, it is assumed that signals with timings shown FIG. 11A-11C are to be generated for testing an IC device. Test signals (clock signals as stimulus) CLK1 and CLK2 are to be supplied to the IC device while a strobe signal STRB is used for sampling the resulted output signals from the IC device. The timing relationship between the test signals CLK1, CLK2 and STRB are illustrated in FIG. 11C. In this example, it is also assumed that the time period of the reference clock Ck is 10 nanosecond.
As noted above, a plurality of delay circuits 3 are used in the timing generator. To generate these timing signals of FIG. 11, with the use of the timing generator of FIG. 10, the signal CLK1 is assigned to a delay generator 31, and the signal CLK2 is assigned to a delay generator 32, and the STRB is assigned to a delay generator 33. In this setting, each memory in the timing generator stores the timing data as shown in FIG. 12. The rate memory 21 is a memory in the rate generator 2 and the timing memories 311-313 correspond to the timing generators 3.sub.1 -3.sub.3. The address is provided to the rate memory and to the timing memories in the order of #0, #1, #2 . . . as shown in FIG. 12.
Since the signal CLK1 is a reference for the other timings in this example, the rate memory 21 is provided with the timing data of 35 ns, 38 ns and 30 ns for the addresses #0, #1 and #2. The timing memory 31.sub.1 for generating the signal CLK1 stores the timing data of 0 ns, 0 ns and 0 ns, respective to the addresses #0, #1, #2. The timing memory 31.sub.2 for generating the signal CLK2 stores the timing data of 7 ns, 5 ns, and 8 ns for the respective addresses of #0, #1, and #2. The timing memory 31.sub.3 for generating the strobe signal STRB stores the timing data 30 ns, 15 ns and 22 ns, respectively. As noted above, the fraction data F for the accumulator 22 in the rate generator 2 indicates 5 ns, 8 ns and 0 ns, respectively, which is differences between the integer multiple of the reference clock period 10 ns and the timing data.
FIGS. 13-17 are timing charts showing operations in the rate generator 2 and delay generators 3.sub.1 -3.sub.3 for generating the signals CLK1, CLK2 and STRB with the timings of FIG. 11. FIGS. 13A-13D are timing chart of the rate generator 2, FIGS. 14A-14E, 15A-15E, and 16A-16E are timing charts of the delay generators 3.sub.1 -3.sub.3, respectively. The rate memory 21 and the timing memories 31.sub.1 -31.sub.3 store the timing data as noted above based on the software.
As shown in FIG. 13A, the time period T of the reference clock Ck is 10 ns. The counter 25 in the rate generator 2 receives the data from the rate memory 21 and counts the reference clock Ck. The data in this case is 30 ns and thus, when counting three pulses, the counter 25 outputs a coincidence signal for every 30 ns as shown in FIG. 13B. Because the accumulator 22 generates a carry, when accumulating the fraction data 5 ns and 8 ns, the delay circuit 26 generates the tester rate RA which is one clock cycle delayed by the reference clock period T as shown in FIG. 13C. Thus, the tester rate RA in this example shows 30 ns for the test first cycle and 40 ns for the next test cycle.
The interpolation data RMD in the second cycle of FIG. 13D indicates 5 ns since the fractional data of 5 ns is provided through the accumulator 22 and the register 23 which is delayed by one cycle. In the second cycle, the next fraction data of 8 ns is accumulated by the previous RMD of 5 ns which is returned from the register 23. Thus, the accumulator 22 generates the carry indicating 10 ns as noted above, and the remainder data of 3 ns is provided as the interpolation data RMD at the output of the register 23. In this manner, the interpolation data RMD is dynamically changed by the accumulator 22 based on the fractional data in the rate memory 21.
The tester rate RA is received by the delay generator 31 through the counter 35 as shown in FIG. 14A. As noted above with reference to FIG. 12, the timing memory 31, stores the timing data indicating 0 ns, 0 ns and 0 ns for the respective three cycles as shown in FIG. 14B. There is no carry signal is generated by the accumulator 32, because the accumulation of the timing data and the interpolation data RMD in this situation will not exceed the reference clock period 10 ns. Thus, the delay circuit 36 outputs a signal having the same timing relationship as the tester rate received by the counter 35 as shown in FIG. 14C.
The output of the delay circuit 36 is received by the variable delay circuit 37 which is controlled by delay data from the register 33. Since the timing data stored in the timing memory 31 is 0 ns as above, the output of the accumulator 32 is unchanged from the interpolation data RMD, which is transferred to the register 33 in the next clock cycle. Therefore, the delay data from the register 33 shown FIG. 14D which is the same data as the interpolation data RMD.
The variable delay circuit 37 provides a high resolution delay time based on the delay data from the register 33 to the output of the delay circuit 36. For the first test cycle, the delay time 5 ns is added to the second pulse, and for the second test cycle, the delay time 3 ns is added to the third pulse. As a result, the test signal CLK1 as shown in FIG. 14E is generated by the delay generator 3.sub.1.
In a similar manner, the tester rate RA is received by the delay generator 3.sub.2 through the counter 35 as shown in FIG. 15A. As noted with reference to FIG. 12, the timing memory 31.sub.2 stores the timing data indicating 7 ns, 5 ns and 8 ns for the respective three cycles as shown in FIG. 15B. A carry signal is not generated by the accumulator 32 for the first test cycle since accumulation of the RMD data 0 ns and the timing data 7 ns does not exceed the reference clock period 10 ns. Thus, the accumulator 32 provides the delay data to the register 33 as the present form. The register 33 transfers the data indicating 7 ns to the variable delay circuit in synchronism with the next reference clock Ck as shown in FIG. 15D.
In the second cycle, since the accumulation of the timing data 5 ns and the interpolation data RMD of 5 ns results in 10 ns, the accumulator 32 produces a carry which is supplied to the delay circuit 36 through the register 34. Thus, second pulse from the delay circuit 36 is delayed by one clock cycle, as shown in FIG. 15C. The delay data from the register 33 indicates 0 ns as shown in FIG. 15D, which is supplied to the variable delay circuit 37.
Similarly, in the next test cycle, the timing data of 8 ns and the RMD 3 ns are added which exceeds the reference clock period 10 ns. Thus, carry is generated which again delays the third pulse from the delay circuit 36 by one clock cycle. The delay data from the register 33 indicates ins which is a difference between 11 ns (8 ns plus 3 ns) and the reference clock period 10 ns, and is provided to the variable delay circuit 37 as shown in FIG. 15D.
The output of the delay circuit 36 is received by the variable delay circuit 37 which is controlled by delay data from the register 33. Since the delay data from the register 33 is 7 ns in the first test cycle, the delay time 7 ns is added to the first pulse from the delay circuit 36 which results in the first pulse of the test signal CLK2 of FIG. 15E. For the next pulse, the delay time is 0 ns. For the third pulse, the delay time ins is added by the variable delay circuit 37. Thus, the test signal CLK2 is generated as shown in FIG. 15E.
Regarding the strobe signal STRB, the tester rate RA is received by the delay generator 32 through the counter 35 as shown in FIG. 16A. As noted above with reference to FIG. 12, the timing memory 31.sub.3 stores the timing data indicating 30 ns, 15 ns and 22 ns for the respective three cycles as shown in FIG. 16B. Since the timing data of 30 ns is greater than the reference clock period 10 ns, the data 30 ns is given to the counter 35 which down counts the number of reference clock Ck.
Thus, the output of the counter 35 is delayed by 30 ns for the first pulse which is transferred at the output of the delay circuit 36 as shown in FIG. 16C. For the second pulse, the timing data of 10 ns is provided to the counter 35 while the fraction data of 5 ns is provided to the accumulator 22. Thus, the counter 35 generates its output signal which is delayed by 10 ns from the second pulse of tester rate RA. The fraction data 5 ns is accumulated with the RMD data 5 ns by the accumulator 32 which produces a carry signal. The carry from the register 34 further causes one cycle delay in the delay circuit 36 as shown in FIG. 16C.
For the third pulse, the timing data 20 ns is provided to the counter 35 and the fraction data 2 ns is provided to the accumulator 22. Thus, the third pulse from the delay circuit 36 is delayed by 20 ns and the delay data which is the sum of the RMD data 3 ns and the fraction data 2 ns is produced at the output of the register 33 as shown in FIG. 16D. The strobe signal STRB is generated by combining the delay time from the register 33 to the output signal from the delay circuit 36 as shown in FIG. 16E.
FIG. 17 is a timing chart showing the more details of the operation of the rate generator 2 many aspects of which are the same as that shown in the timing chart of FIG. 13. The reference clock Ck in FIG. 17A has the time period of 10 ns. The rate memory 21 stores the rate data 35 ns, 38 ns and 30 ns for the first three test cycles as shown in FIG. 17B which is also listed in FIG. 12. The rate memory 21 stores the rate data 35 ns, 38 ns and 30 ns for the first three cycle in FIG. 17B and the counter 25 is provided with data indicating 30 ns or three counts for each test cycle as in FIG. 17C. Thus, the counter 25 down counts the reference clock Ck in FIG. 17D and generates the coincidence signal for every 30 ns as in FIG. 17E.
The fraction data F in this situation is 5 ns, 8 ns, and 0 ns as in FIG. 17F which is applied to the accumulator 22 from the rate memory 21. In the first test cycle, since the fraction data is less than the reference time period T (10 ns), the carry signal is not generated by the accumulator and the fraction data 5 ns at the output of the accumulator as shown in FIG. 17G is provided at the output of the register 23 in the next clock cycle as in FIG. 17H.
In the second test cycle, the accumulator 22 receives the fraction data 8 ns which is added to the interpolation data 5 ns returned from the register 23. Thus, the accumulated result is 13 ns which exceeds the reference 10 ns period. The accumulator 22 generates a carry signal which is received by the delay circuit 26 through the register 24 in the next clock cycle as in FIG. 17I. Also in the next cycle, the remainder data indicating 3 ns is transferred from the accumulator 22 to the register 23 as in FIG. 17G.
The delay circuit 26 outputs the input signal from the counter 26 with the same timing as the tester rate RA in synchronism with the reference clock Ck. When receiving the carry from the register 24, the delay circuit provides a 10 ns delay to the input signal so that the tester rate RA expanded by 10 ns for the corresponding test cycle.
Thus, as shown in FIG. 17J, in the first test cycle, the time interval is 30 ns while in the second test cycle, the time interval is 40 ns because of the carry from the accumulator 22. The interpolation data RMD is produced at the register 23 as shown in FIG. 17K. As in the example of FIGS. 13-16, the tester rate RA and the interpolation data RMD are supplied to the delay generators 3.sub.1 -3.sub.3 to form the required test signals and strobe signals.
FIG. 18 shows another example of circuit configuration for forming a timing generator of the kind of FIG. 10 based on the accumulator and the counter. The timing data greater than the reference clock period T is provided to a counter 125 while the fraction data smaller than the reference clock period is provided to an accumulator 122. When the fraction data accumulated to the previous data returned from a register 123 is greater than the reference clock period T, for example 10 ns, the accumulator 122 provides a carry to the counter 125.
When receiving the carry, the counter 125 holds the operation for the corresponding reference cycle. The output of the counter 125 is received by a variable delay circuit 137 wherein a delay time defined by the delay data from the register 123 is added to the counter output provided through a coincidence detector 126. The output signal of the variable delay circuit 137 is used as a test signal or a strobe signal as described above.
In the conventional timing generator as described above, however, is not able to generate the same timing signals when the reference clock period is changed. When the reference clock is changed, the data stored in the rate memory or the timing memory has to be changed accordingly through a software process. In other words, in the conventional timing generator, the software is not compatible when the frequency of the reference oscillator is changed. Such a need of frequency change in the reference clock arises, for example, when two or more IC testers having different reference frequencies one another are to be used in a parallel fashion while using the same timing signals.
In the timing generators as shown in FIGS. 10 or 11, since the weight of the data to be supplied to the counters and the accumulators vary with the variation of the reference frequency, it is not possible to generate the same timing signals for the new reference frequency without changing the data in the rate memory or timing memories. Namely, if the reference frequency or period has been changed from Tn to Tm, the rate data and the timing data for the reference period Tm have to be changed from that of the reference period Tn for the ratio determined by Tn/Tm. This means that the software is not compatible in this situation, since the rate data and timing data are determined by the software process.

Timing generator for plural reference clocks


The case comprises two plan supporting sheet members, and a hinge pivotally connecting the sheet members together, such that the sheet members and the hinge form a substantially flat surface when the sheet members are pivoted to be in line with one another and in an open position. Detachable legs for supporting the sheet members in the open position are also provided, and the legs are stored by the case when the legs are detached and the sheet members are closed up.

In the construction industry, building plans are consulted on a regular basis as the building construction is being completed. The plans are usually rolled up for ease of carrying to and from the construction site. In order to consult the building plans, the plans are either rolled out on a floor of the building under construction using various paper weights to prevent the plans from rolling back up, or a makeshift table is used on which the building plans can be placed at a reasonable height, and various objects serving as paper weights are used to prevent the plans from rolling up.
In the conventional way of transporting and consulting building plans, there is a tendency for the building plans to become torn, dirtied or damaged by exposure to the elements.


A fuel control system for an engine is disclosed. The fuel control system may have a source of pressurized fuel and at least one injector configured to receive and inject the pressurized fuel. The fuel system may also have a sensor configured to generate a signal indicative of an actual fuel pressure at the at least one injector, and a controller in communication with the sensor. The controller may be configured to determine a desired fuel pressure at the at least one injector, and compare the signal to the desired fuel pressure. The controller may also be configured to initiate a leak detection sequence in response to the comparison.

Fuel systems often include a source of pressurized fuel, one or more fuel injectors, and a distribution system for directing the pressurized fuel from the source to the fuel injectors. The fuel injectors are typically associated with an engine and it can be important for proper operation of the engine to monitor and adjust various parameters of the fuel system during operation of the engine. For example, over time, the different components of the fuel system may wear causing efficiency losses and/or gradual deviations from desired operating pressures. If these losses and pressure deviations are left unchecked, the performance of the engine may deteriorate. In addition, if the wear is excessive or damage to the system occurs, external fuel leakage and extreme system pressure drop may be possible.
However, if the efficiency losses and pressure deviations can be monitored, corrective and/or precautionary actions may be timely implemented. One example of monitoring fuel system operation and detecting fuel leakage is described in U.S. Pat. No. 5,708,202 (the '202 patent) issued to Augustin et al. on Jan. 13, 1988. Specifically, the '202 patent discloses a method of recognizing fuel leakage from the fuel injection system of an internal combustion engine. The method includes sensing a pressure of the fuel injection system during non-injection events, and comparing the sensed pressures. If a significant deviation in the sensed pressures occur, then leakage is determined. When determining large leaks between the pump and injectors of large flow systems, the non-injection events correspond with the time between the end of one injection and the start of another injection. When determining leaks between the pump and the injectors in small flow systems, the non-injection events must be created by eliminating at least one fuel delivery and at least one fuel injection step. If no leaks are detected between the pump and the injectors, other portions of the system can be leak tested only during a "driven operation" by comparing the pressures sensed when the injectors and the pump of the system are turned off.
Although the method of the '202 patent may sufficiently detect fuel system leaks, it may be limited and intrusive. In particular, the leak testing described in the '202 patent can only be performed during certain engine operations (e.g., when the engine is driven). This limited applicability may be problematic in some situations where continuous leak detection is critical. In addition, because leak testing within the fuel system of the '202 patent, other than between the pump and the injectors, requires the injectors and the pump to be turned off, engine operation may be undesirably interrupted. Further, the method of the '202 patent provides no way to determine if a low pressure event is due to leakage, periodic intentional pressure relieving, or normal wear, and no way to accommodate normal wear.
The control system of the present disclosure solves one or more of the problems set forth above.

System for dynamically detecting fuel leakage


A motor-driven actuator for a vehicle, in particular for a vehicle seat, is for being situated between two components of the vehicle or vehicle seat that can be displaced in relation to one another. The motor-driven actuator comprises a motor, at least one first gear stage that is located on the output side of the motor, a second gear stage that acts as a load-bearing gear and is located on the output side of the first gear stage, and at least one sealing element. The motor, gear stages and sealing element are integrated into the motor-driven actuator. The sealing element is adapted for being in a predetermined sealing configuration for protecting the motor and/or its electrical contact and/or at least one of the gear stages during manufacturing. The sealing element is adapted for not being in the predetermined sealing configuration when the motor-driven actuator is installed and ready to operate.

DE 10 2004 019 466 A1 discloses a motor-driven actuator of the type described in the Technical Field section of this disclosure, in which an electronically commutated motor and a differential gear (i.e., a first gear stage) are integrated spatially and functionally into a load-bearing gear (i.e., a second gear stage).

Motor-driven actuator for a vehicle seat


A process is described for reducing the level of benzene in a refinery gasoline feed containing benzene and at least one C5+ olefin, in which the refinery gasoline feed is contacted with a first alkylation catalyst under conditions effective to react at least part of the C5+ olefin and benzene in the refinery gasoline feed and produce a first alkylation effluent. The first alkylation effluent is separated into at least (i) a first fraction rich in benzene, (ii) a second fraction rich in C7 to C12 hydrocarbons and (iii) a third fraction rich in C13+ hydrocarbons. At least part of the first fraction is contacted with an alkylating agent comprising one or more C2 to C4 olefins in the presence of a second alkylation catalyst under conditions effective to produce a second alkylation effluent which has reduced benzene content as compared with the first fraction.

Benzene is considered to be environmentally hazardous. As a result, the State of California and the United States Environmental Protection Agency have instituted regulations to limit the amount of benzene which may be present in gasoline. As from January 2011, the US MSAT-2 (Mobile Source Air Toxics) regulation has required reduction of the annual average benzene content in gasoline to no greater than 0.62 volume %.
One known route for reducing the benzene content of gasoline is to selectively alkylate the benzene using a lower olefin. For example, U.S. Pat. No. 5,149,894 describes a process for converting benzene to alkylated benzenes in a gasoline blend stock. The process involves contacting a benzene-containing gasoline blend stock with a C2 to C4 olefin stream in the presence of a catalyst containing the zeolite, SSZ-25, to produce an alkylated light hydrocarbon stream with reduced benzene content.
U.S. Pat. No. 5,545,788 describes a process for the production of a more environmentally suitable gasoline by removing a substantial portion of the benzene in gasoline by alkylation of reformate. The process involves alkylation using a light olefin feed at low temperature over the zeolite catalyst, MCM-49.
U.S. Pat. No. 7,476,774 describes a process where light olefins including ethylene and propylene are extracted from refinery off-gases, such as from a catalytic cracking unit, into a light aromatic stream, such as a reformate containing benzene and other single ring aromatic compounds, which is then reacted with the light olefins to form a gasoline boiling range product containing alkylaromatics. The alkylation reaction is carried out in the liquid phase with a catalyst which preferably comprises a member of the MWW family of zeolites, such as MCM-22, using a fixed catalyst bed.
However, in addition to limiting the benzene level in gasoline, current and ongoing regulations restrict the content of residue, which consists of heavy hydrocarbon components with boiling points outside the gasoline boiling range. The US standard specification for automotive spark-ignition engine fuel (ASTM D4814) requires that the residue (heavies) in the gasoline product is no more than 2 volume %. Moreover, some refiners have low gasoline endpoint requirements such that, at high benzene conversion during reformate alkylation, the alkylation product may not be fully blendable into the gasoline pool at these refineries. This is believed to be at least partially due to the presence in the reformate feed of C5 and heavier olefins, such as C5-C8 olefins, which, during alkylation, can react with the benzene in the reformate in addition to the added light olefins to produce non-blendable C13 and heavier components.
There is therefore a need for improved processes for reducing the benzene content of gasoline which minimize the formation of C13 and heavier components, while maximizing the amount of the reformate feed available for blending into the gasoline pool.

Process for reducing the benzene content of gasoline