A unitized wheel hub and bearing assembly for use on the ends of stationary axles and particularly on tractor and trailer axles. A wheel hub, a pair of bearings and at least one seal are assembled with a mounting sleeve which is sized to be fitted on an axle end. The inclusion of a custom designed mounting sleeve permits the building of unitized assemblies to be used with existing axles as well as with new ones. The unitized construction allows pre-adjustment of the bearings and when two seals are employed, the bearings can also be pre-lubricated.

In wheeled vehicles of all types, it is necessary to provide bearings for axles so that associated wheel hubs may rotate freely on the end of a relatively stationary axle. Such bearings must be lubricated and seals are required to retain the lubricating medium whether it be grease or oil. Frequently, wear sleeves are employed to prevent undue wear of the axle by the seals. Sometimes such wear sleeves have been separate elements and sometimes they have been an integral part of a unitized seal.
Until quite recently, such bearing, seal and wheel hub means have been assembled piece by piece. The bearing races have been fitted to designated axle portions and corresponding portions of the associated wheel hub. The bearing elements are usually spaced as far apart axially as possible with a tapered axle portion between the elements. The assembly also includes one or two seals, depending upon the particular design. These wheel hub assemblies have typically provided long lasting performance when assembled properly. However, such an assembly process requires skilled personnel and proper equipment to achieve proper installation and operation. If repair or replacement of any part becomes necessary, correct positioning and adjustment of all elements becomes even more of a challenge and damaged parts are a quite likely result. Typical prior art assemblies are illustrated in U.S. Pat. No. 4,552,367 assigned to Garlock Inc and U.S. Pat. No. 4,037,849 assigned to The Mechanex Corp.
More recently, some efforts have been made to develop assemblies which permit more of the various elements to be pre-assembled and adjusted, thus resulting in less dependance on the skills of the field mechanic. One such attempt has been the SAF Euro-axle developed by Otto Sauer Achsenfabric of Keilberg, Germany. These units accomplish much in terms of allowing factory assembly and adjustment of sealed bearing units and avoidance of so much dependance on the skills of the field mechanic. However, these units are not constructed to allow prefilling with oil which is a preferred bearing lubricant as compared to grease. More significantly, a special axle is included in the assembly and the pre-assembled units cannot be adapted to the millions of existing axles presently in service.
Another recent effort at development of pre-assembled and pre-adjusted sealed bearing units has been made by SKF Sweden. However, as with SAF units described previously, the SKF units are not adapted to prefilling with oil lubrication and they are not adaptable to the millions of existing axles. Furthermore, since the bearing units are more closely located relative to one another, there can be a tendency toward lessened wheel stability in operation.


An outer conductor has a substantially cylindrical shape extending in an axial direction. A center conductor has a substantially cylindrical shape extending in the axial direction, and is provided inside the outer conductor. An insulator fixes the center conductor relative to the outer conductor. The center conductor is provided with a hole that communicates with the inside and the outside of the center conductor. The insulator extends, via the hole, to the inside of the center conductor from the outside.

A connector plug described in Japanese Unexamined Patent Application Publication No. 2009-104836, for example, is known as a coaxial connector plug according to the related art. FIG. 14 is a cross-sectional view showing the structure of a connector plug 510 described in Japanese Unexamined Patent Application Publication No. 2009-104836.
As shown in FIG. 14, the connector plug 510 includes a socket-shaped center conductor 512, a center conductor joint portion 514, an outside conductor 516, and an insulating housing 518. The outside conductor 516 has a substantially cylindrical shape extending in the up-down direction, and is kept at a ground potential. The socket-shaped center conductor 512 is provided at the center of the outside conductor 516, and has a substantially cylindrical shape extending in the up-down direction. A high-frequency signal is input to and output from the socket-shaped center conductor 512. The center conductor joint portion 514 is connected to the socket-shaped center conductor 512, and extends in the horizontal direction. The insulating housing 518 is a resin member that fixes the socket-shaped center conductor 512 at the center of the outside conductor 516.
It is difficult to lower the profile of the connector plug 510 described in Japanese Unexamined Patent Application Publication No. 2009-104836. Specifically, a receptacle connector is mounted to the connector plug 510. In this event, a pin-shaped center conductor of the receptacle connector is inserted into the socket-shaped center conductor 512 from the upper side. Therefore, the socket-shaped center conductor 512 is pressed downward. Accordingly, the socket-shaped center conductor 512 may be displaced downward.
Thus, in the connector plug 510, a portion of connection between the socket-shaped center conductor 512 and the center conductor joint portion 514 is cranked. This allows the insulating housing 518 to be positioned under the socket-shaped center conductor 512, which suppresses downward displacement of the socket-shaped center conductor 512 because of the presence of the insulating housing 518 even if the socket-shaped center conductor 512 is pressed downward.


An optical node apparatus according to the present invention amplifies a WDM signal light input to an input port, and thereafter, branches the amplified WDM signal light by an optical branching coupler to send the branched lights to first and second optical paths, and selects the light propagated through the first optical path by an optical switch to amplify the selected light by a post-amplifier, thereby outputting the amplified light from an output port, when the optical node apparatus is operated as an optical amplification repeating node. When the operational state is upgraded to an optical add/drop multiplexing node, an OADM section is connected between a set of connecting ports on the second optical path, and the adjustment of the OADM section is performed utilizing the WDM signal light branched by the optical branching coupler, and thereafter, the switching of the optical switch is performed to select the light on the second optical path side. As a result, since the switching the operational state from the optical amplification repeating node to the OADM node can be performed in a short time, it becomes possible to provide the continued communication service at the low initial installation cost.

1. Field of the Invention
The present invention relates to a method of upgrading an optical node, and an optical node apparatus, in an optical communication system for transmitting a wavelength division multiplexed (WDM) signal light. In particular, the present invention relates to a method of upgrading an optical amplification repeating node to an optical add/drop multiplexing (OADM) node, and an optical node apparatus.
2. Description of the Related Art
Currently, in the metro-core ring, a system for acquiring signal lights of the number of wavelengths (channels) corresponding to a required communication traffic is applied to an OADM node arranged in each metropolitan area, using a WDM transmission system. In a part of the area where such an OADM node is arranged, there is the case where the communications needs have been zero in the beginning of the system construction, but due to the area development thereafter or the location of data center, the communications needs are rapidly increased.
As a method of upgrading the system for coping with the increase of communications needs as described above, there is, for example, a method of installing an optical node apparatus having an OADM function in such an area from the beginning, to enable the OADM function when the communications needs occur (refer to Japanese Unexamined Patent Publication No. 2004-297235). Further, it is also possible to initially install an inline amplifier as an optical amplification repeating node which does not have the OADM function, and to replace the inline amplifier with the optical node apparatus having the OADM function when the communications needs occur, thereby upgrading an optical node from the optical amplification repeating node to the OADM node.
However, in the conventional upgrading method of installing the optical node apparatus having the OADM function from the beginning as described above, there is a problem in that the initial installation cost becomes expensive. Further, in the upgrading method of replacing the inline amplifier initially installed with the optical node apparatus having the OADM function when the communications needs occur, since the communication service in the entire system needs to be suspended for a fixed time when performing the replacement of the optical node apparatus, there is a problem in that the continued communication service cannot be provided.
Moreover, regardless of whether or not the optical node apparatus having the OADM function is installed from the beginning, in the case where an operational state of the optical node apparatus is switched from the optical amplification repeating node to the OADM node according to the communications needs, how quick an operation of the OADM node apparatus after switched can be adjusted to be in an optimum status corresponding to operational channels before switched is a major problem for stably providing the continued communication service.

Method of upgrading optical node, and an optical node apparatus


A pocket containing business form is formed from an intermediate which comprises a sheet of paperlike material having dimensions of about 8.times.11 inches. The sheet is guillotine cut in two lengthwise, and each of the sections is eccentrically Z-folded to form a pocket, with pressure activated adhesive strips sealed along the edges of the pocket. The portion of the sheet exposed above the pocket is imaged by a laser printer, etc., for example, to indicate due dates for library books. The form is glued on one of the inside covers of a library book, and a 3.times.5 card containing information about the book is inserted in the pocket.

In the construction of pocket forming elements which are fastened inside library books to hold a 3.times.5 card, and to indicate the due date for the library book, etc., typically it is necessary to purchase an envelope and a separate information card. The separate information card is preprinted and stapled or otherwise affixed to the open top envelope. This requires purchase of different components, assembly time, and is not conveniently practiced using on site conventional printers, such as laser printers.
According to the present invention, a method and business form, as well as an intermediate for construction of the business form, are provided which provide a much simpler procedure and structure than in the prior art, yet the product produced according to the invention is just as functional, although likely less expensive. Practicing the invention it is possible for a laser printer directly on site at an establishment utilizing the business forms according to the invention to print the appropriate information on the form, then to cut and Z-fold the intermediate form so as to readily produce a pocketed structure. The invention utilizes standard size sheets of paper (e.g., about 8.times.11 inches) making production on existing equipment simple and easy.
According to one aspect of the present invention, a method of making a pocket containing business from a sheet of paperlike material, having first and second faces, a length, and a width, and at least a first fold line extending widthwise thereof, is provided. The method comprises the following steps: (a) Imaging indicia on the first face of the sheet of paper at a first portion thereof. (b) Cutting the sheet lengthwise to provide two or more sections of essentially the same size. (c) Effecting eccentric folding of each of the sections about the first fold line so as to leave the first portion of the first face uncovered so that the indicia imaged thereon is readily visible. And (d) after step (c), affixing the eccentrically folded section portions together so as to form a pocket opening up toward the first portion, on the first face.
The sheet typically has a second fold line widthwise thereof, and step (c) is practiced to effect eccentric Z-folding of each of the sections about the first and second fold lines. Preferably the sheet has dimensions of about 8.times.11 inches, and step (b) is practiced to cut the sheet in half, forming two sections each of about 4.times.11 inches. Step (b) is typically practiced before step (c).
Step (a) is practiced to print due date indicia for a library book on a sheet portion, in the preferred embodiment. Also, there is then the further step of gluing the second face of the sheet to an inside cover portion of a library book, and placing an index card having information about the library book into the pocket.
Pressure activated adhesive strips are preferably provided on the first and second faces of the sheet that will come in contact with each other during Z-folding, prior to step (a), and then step (d) is practiced by applying pressure to the adhesive strips to seal them together.
The invention also comprises a business form intermediate. The intermediate has the following elements: A sheet of paperlike material having first and second faces a rectangular configuration, a length of about 11 inches, a width of about 8 inches, top and bottom edges, side edges, and a centerline intermediate the side edges. A first fold line extending parallel to the top and bottom edges and about 61/4 inches from the top edge. A second fold line extending parallel to the top and bottom edges and about 23/8 inches from the first fold line and the bottom edge. The first fold line defining a first panel between the top edge and the first fold line, and the second fold line defining a second panel between the first and second fold lines, and a third panel between the second fold line and the bottom edge. Cooperating adhesive patterns disposed on the first face of the first panel adjacent the fold line, and on the first face of the second panel, including adjacent the side edges and the centerline. And cooperating adhesive patterns disposed on the second faces of the second and third panels, including adjacent the side edges and the centerline, and the bottom edge. The cooperating adhesive patterns preferably comprise strips of pressure activated adhesive, and indicia imaged on the first face of the first panel is more than about 23/8 inches from the first fold line toward the top edge.
The invention also comprises a pocket containing business form. The business form according to the invention comprises a single sheet of paper like material, comprising: A first panel having a first length and a first width, and first and second faces. A second panel having a second length and the first width, the second length being less than one half the first length, and having first and second faces which are continuations of the first and second faces of the first panel. A first fold line between the first and second panels extending widthwise of the panels, the second panel folded about the first fold line so that the first face of the second panel comes into contact with the first face of the first panel, the first panel having a free portion not covered by the second panel. Indicia imaged on said free portion of said first panel. And adhesive connecting said first face of said second panel to said first face of said first panel to form a pocket capable of receiving an index card. The business form also further comprises, in the preferred embodiment, a third panel having a second length and the first width, having first and second faces which are continuations of the first and second faces of the first and second panels. A second fold line is provided between the second and third panels extending widthwise of the panels, the third panel folded about the second fold line so that the second face of the third panel comes into contact with the second face of the second panel; and adhesive connects the second faces of the second and third panels together so that they both cooperate with the first panel to form the pocket.
The indicia which is provided on the free portion of the first panel preferably indicates the due date of a library book, and the pocket containing business form is in combination with a library book with the second face of the second panel affixed to an inside cover portion of the library book with adhesive. While any type of paperlike sheet material may be utilized, a relatively stiff paper material, such as PMS-461 brown stock, is provided.
Each of the panels preferably has longitudinal edges defining the width thereof, and adhesive connecting the first and second panel first faces together comprises cooperating strips of pressure activated adhesive disposed adjacent the longitudinal edges of both the first and second panel first faces. The adhesive for connecting the second and third panel second faces together comprises cooperating strips of pressure activated adhesive disposed adjacent the longitudinal edges of both the second and third panel second faces.
It is a primary object of the present invention to provide a simple yet effective business form which can be used on the inside cover of library books for indicating the due date and for containing an index card. This and other objects of the invention will become clear from an inspection of the detailed description of the invention, and from the appended claims.

Pressure seal-eccentric Z-fold library envelope


Pump assembly for the lift cylinder of a hand fork-lift truck includes a piston pump activated by a bar of a hand fork-lift truck and has a piston chamber and an annulus collector. A three stage control valve connects the lift cylinder with a tank in the lowered setting and connects the piston chamber with the tank in a neutral setting and in a pump setting, connects the piston chamber with the lift cylinder through a first check-valve, with the tank through a second check-valve, a third check-valve between the piston chamber and the annulus collector open to the piston chamber, and a reversing valve between the piston chamber and the annulus collector.

Raising and lowering the load-fork of a hand fork-lift truck is normally performed with a hydraulically operated singled-sided lifting cylinder. The lifting cylinder is supplied with a piston pump which is actuated mechanically through a pumping action of a bar. The ratio, pump volume to displacement volume is normally designed so that the load can be raised with an acceptable number of pumping actions on the bar without the operator having to use too much power for lifting a full load. Consequently, this design presents a compromise between the acceptable number of pumping actions on one hand and the power to be used on the other. In many cases, the relatively large number of pumps is not acceptable however, especially with smaller loads. In most cases, the load fork also has to be raised by a certain amount before it takes on the weight of the load from underneath. The operator desires quicker lifting action for this distance.
A so-called quick-lift version is also planned for this kind of pump assembly therefore. The transmission ratio between the piston-pump and the lifting cylinder is reduced in this case. Switching from the quick-lift variation to the heavier ratio is necessary when taking on a certain load. Two different solutions are already known for this. For each of them, an additional valve is necessary. One embodiment has the lifting cylinder in two stages. In one operating version, a limited effective area takes on the pump pressure. In the second operating version, the first effective area is supplemented by a second effective area which is connected with the piston pump through a pilot controlled check-valve. The disadvantage in these cases, is the working length of the lifting cylinder which is almost double the length of standard lift cylinders.
A second solution reversing the pump volume. A reversing valve is situated between the piston chamber and the annulus collector of the piston pump and parallel to this is a check-valve. The reversing valve is controlled by the pressure in the output line of the piston chamber. If this achieves a certain value, the reversing valve opens and connects the piston chamber and annulus collector of the pump. The effective piston surface of the pump piston is therefore reduced to the difference of the effective surfaces in the piston chamber and annulus collector. In one popular solution, the described functionality is made effective in that a valve element is pressed against the sealing surface by a spring which is held in a hole in the pump piston. The hole is connected with the piston chamber and with the annulus collector with a radial opening. If pump pressure exceeds a predefined value, the valve element is opened and the medium flows into the annulus collector. The radial gap that is created here is very small so that significant throttle losses occur. The resulting, system-related loss of force that is characterized by the product from reversing pressure in the annulus collector and the difference from the base and rod surface of the pump piston. Since the reversing valve is opened and closed in time with the pump movement of the bar in this solution, the force that is required is relatively high in normal lifting operation compared with the load forces based on the described loss.


A first conductive film for forming a plurality of word lines is formed in a memory cell array formation region of a semiconductor substrate for a nonvolatile semiconductor memory device, and a second conductive film is formed in a semiconductor device formation region of the semiconductor substrate. Next, openings are formed in the first conductive film by a first dry etching process such that the word lines in the memory cell array formation region are located apart from one another. Thereafter, sidewall insulating films for the word lines are formed in the openings. Next, parts of the sidewall insulating films located adjacent to the ends of the word lines are removed by wet etching. Next, a part of the first conductive film located around a word line formation region is removed by a second dry etching process. The openings are formed in the first conductive film such that a part of the first conductive film remaining after the formation of the openings is continuous with the second conductive film, which is formed on an active region of the semiconductor substrate located outside the memory cell array formation region so as to be electrically connected to the active region.

(1) Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method for fabricating the same, and more particularly relates to a nonvolatile semiconductor memory device for avoiding or suppressing damage caused by charging during processing and a method for fabricating the same.
(2) Description of Related Art
In recent years, as the memory cell size is reduced with an increase in the integration level of nonvolatile semiconductor memory devices, thinner gate electrodes serving as word lines have been suggested. However, the thinner gate electrodes make high-speed operations difficult. The reason for this is that narrower word lines increase the word-line resistances, leading to the increased delay of word-line signals.
To cope with this, it should be considered to use a self-align silicide technology (hereinafter, referred to "salicide technology") as a measure for reducing the word-line resistances. When the salicide technology is applied to nonvolatile semiconductor memory devices, the sidewall of a gate electrode for each of memory cells need previously be covered with an insulating film to prevent shorting between a word line and a source diffusion layer or a drain diffusion layer and between a semiconductor substrate and a source diffusion layer or a drain diffusion layer.
For a memory cell of a nonvolatile semiconductor memory device, a relatively thick insulating film need usually be formed on the sidewall of a gate electrode to cope with characteristic variations and damage due to ion implantation for the formation of a source diffusion layer or a drain diffusion layer. Furthermore, in order to avoid exposing regions of a semiconductor substrate between word lines, spaces between all adjacent pairs of word lines need be completely filled with an insulating film with which the sidewall of the gate electrode is covered in accordance with the structure of a memory cell array.
Meanwhile, a nonvolatile semiconductor memory device is provided with a semiconductor device formed at a region of a semiconductor substrate outside a memory cell array region thereof. Since high performance is demanded for such a semiconductor device, it is desirable that a relatively thin insulating film is formed on the sidewall of the semiconductor device. In view of the above, it has been suggested that only the sidewall of a gate electrode serving as a word line in the memory cell array region is to be covered with a particularly thick insulating film.
As an example of a method in which the sidewall of a gate electrode serving as a word line in a memory cell array region is covered with a thick insulating film, a method for fabricating a nonvolatile semiconductor memory device according to a first known example will be described hereinafter with reference to FIGS. 16A through 18C and 19 (see, for example, Patent Document 1 (Japanese Unexamined Patent Publication No. 2003-17596)).
FIGS. 16A through 18C and 19 are cross-sectional views showing process steps in a method for fabricating the principal part of a nonvolatile semiconductor memory device according to the first known example. The method for fabricating a nonvolatile semiconductor memory device will be described hereinafter with reference to a stacked nonvolatile semiconductor memory device having a floating gate as an example of nonvolatile semiconductor memory devices. In FIGS. 16A through 18C and 19, a substrate region in which a memory cell array of a nonvolatile memory is formed is designated as a first area 100A, and a substrate region in which a semiconductor device is formed is designated as a second area 100B.
First, as shown in FIG. 16A, a p-type well region 101 is formed in the top surface of a p-type silicon substrate 100, and an isolation insulating film 102 is formed in the p-type well region 101. Thereafter, a tunnel oxide film 103 is formed on the p-type well region 101 and the isolation insulator film 102 located in both the first and second areas 100A and 100B. Next, a first polysilicon film 104 is selectively formed on the tunnel oxide film 103, and then a capacitive insulating film 105 is formed to cover the first polysilicon film 104.
Next, as shown in FIG. 16B, a first resist pattern 106 is formed to cover a part of the capacitive insulating film 105 located in the first area 100A, and etching is performed using the first resist pattern 106 as a mask. In this way, respective parts of the capacitive insulating film 105, the first polysilicon film 104 and the tunnel oxide film 103 located in the second area 100B are removed.
Next, as shown in FIG. 16C, a gate oxide film 107 is formed in the top surface of a part of the p-type well region 101 located in the second area 100B by thermally oxidizing the p-type silicon substrate 100. Thereafter, a second polysilicon film 108 is formed to entirely cover the first and second areas 100A and 100B. Although in the drawings the capacitive insulating film 105 in the first area 100A is not shown in detail, it typically has a three-layer structure (an ONO film) composed of an oxide film, a Si3N4 film, and an oxide film. In addition, although not shown for simplicity, an oxide film is formed also in the uppermost surface of the capacitive insulating film 105 in the first area 100A by thermal oxidation for the formation of the gate oxide film 107 in the second area 100B.
Next, as shown in FIG. 17A, a second resist pattern 109 is formed to cover a region of the first area 100A in which a stacked gate electrode of a nonvolatile memory is to be formed and the second area 100B, and the second polysilicon film 108, the capacitive insulating film 105, the first polysilicon film 104, and the tunnel oxide film 103 are successively etched using the second resist pattern 109 as a mask. In this way, a stacked gate electrode 108c is formed which is composed of a tunnel oxide film 103a, a floating gate electrode 104a, a capacitive insulating film 105a, and a control gate electrode 108a. In the second area 100B, the second polysilicon film 108 is patterned into a second polysilicon film 108a by etching.
Next, as shown in FIG. 17B, a third resist pattern 110 is formed to expose parts of the substrate region that will be source/drain regions of the nonvolatile memory, and n-type impurity ions are implanted (111) into the p-type well region 101 using the third resist pattern 110 and the stacked gate electrode 108c as masks. In this way, lightly-doped impurity regions 112 are formed which will become source/drain regions of the nonvolatile memory.
Next, as shown in FIG. 17C, an oxide film 113 that will partly become a sidewall insulating film of the stacked gate electrode 108c is deposited by chemical vapor deposition (CVD) to entirely cover the first and second areas 100A and 100B. Although the oxide film 113 has a thickness of, for example, about 200 nm, the thickness can be adjusted so that the sidewall insulating film formed on the sidewall of the stacked gate electrode 108c has a desired thickness.
Next, as shown in FIG. 18A, the oxide film 113 is subjected to anisotropic etching. In this way, the top surface of the stacked gate electrode 108c in the first area 100A and the top surface of the second polysilicon film 108a in the second area 100B are exposed, and first sidewall insulating films 113a are formed on the sidewall of the stacked gate electrode 108c in the first area 100A and the sidewall of the second polysilicon film 108a in the second area 100B, respectively. The above-described anisotropic etching is preferably carried out with such an etching selectivity that even if the respective top surfaces of the stacked gate electrode 108c and the second polysilicon film 108a have been exposed, the stacked gate electrode 108c and the second polysilicon film 108a are hardly etched.
Although not shown, the oxide film 113 may be subjected to anisotropic etching such that spaces between all adjacent pairs of stacked gate electrodes 108c are completely filled with first sidewall insulating films 113a formed on the sidewalls of the stacked gate electrodes 108c in accordance with the structure of a memory cell array. Furthermore, the thicknesses of the first sidewall insulating films 113a formed on the sidewalls of the stacked gate electrodes 108c can be controlled by adjusting the thickness of the oxide film 113 deposited by CVD in the process step shown in FIG. 17C.
Next, as shown in FIG. 18B, a fourth resist pattern 114 is formed to cover the first area 100A and a region of the second area 100B in which a gate electrode of a semiconductor device is to be formed, and the patterned second polysilicon film 108a and the gate oxide film 107 are etched using the fourth resist pattern 114 as a mask. In this way, a gate electrode 108b and a gate oxide film 107b for the semiconductor device are formed in the second area 100B.
Next, as shown in FIG. 18C, a fifth resist pattern 115 is formed to cover the first area 100A, and ions are implanted (116) into the second area 100B, thereby forming lightly-doped impurity regions 117 that will become a source or drain for the semiconductor device in the second area 100B.
Next, as shown in FIG. 19, an oxide film is deposited all over the first and second areas 100A and 100B by CVD and then subjected to anisotropic etching. In this way, second sidewall insulating films 118 are formed on the sidewalls of the first sidewall insulating films 113a and the sidewall of the combination of the gate electrode 108b and the gate oxide film 107b for the semiconductor device in the second area 100B. As seen from the above, a double-layer structure of the first and second sidewall insulating films 113a and 118 is formed on the sidewall of the stacked gate electrode 108c in the first area 100A. Thereafter, ions of n-type impurities are implanted (119) into the p-type well region 101 using the stacked gate electrode 108c, the gate electrode 108b, and the second sidewall insulating films 118 as masks. In this way, heavily-doped impurity regions 120a that will become a source and a drain for the nonvolatile memory are formed in the first area 100A, and heavily-doped impurity regions 120b that will become a source and a drain for the semiconductor device are formed in the second area 100B. Next, a silicide layer 121 is selectively formed on the respective top surfaces of the stacked gate electrode 108c, the gate electrode 108b and the heavily-doped impurity regions 120a and 120b using a salicide technology. Although not shown, an interlayer insulating film, contact holes and an aluminum interconnect will be formed later.
As described above, according to the method for fabricating a nonvolatile semiconductor memory device of the first known example, the sidewalls of the word lines can be covered with the sidewall insulating films of an arbitrary thickness. In addition, spaces between all adjacent pairs of the word lines can be completely filled with insulating films by adjusting the thickness of the oxide film deposited by CVD to cover the sidewalls of the word lines.
By the way, in recent years, with an increase in the integration level and processing speed of nonvolatile semiconductor memory devices, processes suitable for microprocessing, such as ion implantation or plasma-assisted dry etching, have come to be frequently used for fabrication methods for a nonvolatile semiconductor memory device. However, in these processes, charging is caused, for example, during the processing of gate electrodes.
In the fabrication method for a nonvolatile semiconductor memory device of the first known example, processes with a high possibility of charging are the ion implantation 111 shown in FIG. 17B and anisotropic etching in the formation of the first sidewall insulating films 113a by the deposition of the oxide film 113 shown in FIG. 17C and the repetition of the anisotropic etching shown in FIG. 18A.
The above-mentioned processes having a high possibility of causing charging cause the storage of excessive charges in the tunnel oxide film 103a and the capacitive insulating film 105a or damage to the tunnel oxide film 103a and the capacitive insulating film 105a. This leads to problems about the lifetime and reliability of nonvolatile semiconductor memory devices.
To cope with this, there has been suggested a method for fabricating a nonvolatile semiconductor memory device according to a second known example (see, for example, Patent Document 2 (Japanese Unexamined Patent Publication No. 11-54730)).
The fabrication method for a nonvolatile semiconductor memory device of the second known example includes the steps of: forming, around a memory array, an active region for dissipating, into a semiconductor substrate, charges to be injected into control gates corresponding to the word lines and a gate insulating film or a floating gate corresponding to the capacitive insulating film during a process for processing the control gates and the gate insulating film or the floating gate; processing the word lines and the floating gate with the control gates corresponding to the word lines connected to the active region; and disconnecting the control gates from the active region.

Nonvolatile semiconductor memory device and method for fabricating the same

Matsushita Electric Industrial Co., Ltd.


A programmable memory device includes circuits that permit the selective disabling of certain functions when a battery supply voltage falls below the point necessary to sustain those functions while not disabling other functions of the device capable of working at the lower supply voltage. The programmable memory device includes a controller (422), programmable memory (426), and a voltage monitor (424), and is used in an application having additional circuitry (430). Power is furnished between the main voltage V.sub.CC terminal and the ground GND terminal from an external power source, typically a set of batteries. The voltage monitor enables full extension of the operational voltage range for specific functions of the programmable memory device, or for the application circuitry, or for both by reliably detecting the voltage level of the power source and providing an indication thereof. The indication of the present voltage level is used for suppressing functions that cannot be sustained at the present voltage level.

1. Field of the Invention
The present invention relates to memory and applications that use memory, and more particularly to operating applications that use memory and memory having different operating modes with different power requirements, in accordance with available power.
2. Description of Related Art
Traditional channel hot electron ("CHE") Flash memory is used in many applications, but is not entirely suitable for use in portable battery operated applications because of its high active current consumption--on the order of 50 mA--and because of its need for two power supplies, V.sub.CC and V.sub.PP. However, programmable non-volatile memories requiring only a single power supply and having low power consumption, low voltage, and high density characteristics have become available, and have enabled or facilitated a variety of battery-operated applications. For example, the type NX25F080 memory available from Nexcom Technology, Inc. of Sunnyvale, Calif., is an 8 Mbit Serial Flash memory which has an SPI interface and draws only 5 mA of current at a V.sub.CC supply of 3.0 volts. The NX25F080 Serial Flash memory is tailored for battery operated microcontroller-based applications that use small form factor memory to store and/or transfer data, audio and images in a portable or mobile environment. Applications include digital cameras, portable scanners, voice/data recorders and pagers, cellular phones, hand held terminals, and portable data acquisition equipment.
In certain markets such as the consumer electronic market, the user application is extremely cost sensitive. Unfortunately, many battery operated consumer electronic products must include a costly voltage regulator to handle the problem of battery output voltage drop as the battery discharges. For example, an AA or AAA alkaline battery starts fresh with a 1.5 V output voltage and discharges with use until reaching its "end of life" voltage of 0.9 V. Where an electrical device is able to tolerate only a narrow range of voltages, from a low voltage that is high enough to operate the device properly to a high voltage that is low enough not to damage the device, a range typically of about ten percent (i.e., 5 V.+-.10% or 3.3 V.+-.10%), the system designer typically provides an on-board voltage regulator such as the step-up voltage regulator 110 shown in FIG. 1. FIG. 1 shows three batteries 102, 104 and 106, which provide the power input to the voltage regulator 110. The output of the voltage regulator 110 is furnished, for example, to a microcontroller 120, memory 130, and an application 140. If the output of the voltage regulator 110 drops below the low voltage specification, a reset output pin is asserted to notify the microcontroller 120 of a power failure. Unfortunately, this approach adds one or more components to the product, thereby increasing cost and shortening battery life.
Alternatively, a system designer may use components in the device having wider operational voltage ranges. For example, if all the components in a device have an operational range of from 2.7 V (3.times.0.9 V) to 4.5 V (3.times.1.5 V), then three AAA batteries can be used to power the product without the need for an on-board voltage regulator. In this case, more than 90% of the capacity of the batteries can be utilized. However when the supply voltage drops below 2.7 V, the system needs to be notified about the end of life of the batteries. For this, a CPU supervisor typically is utilized. CPU supervisors are available from numerous vendors, including Dallas Semiconductor of Dallas, Tex., which offers a family of such chips under the product numbers DS123.times.. FIG. 2 shows a CPU supervisor 210 installed in a system. If V.sub.CC drops below a certain voltage (in the case of the DS123.times. products, 4.5 V for 5 V systems and 2.7 V for 3.0 V systems), then a Reset output pin is asserted to notify the microcontroller 120 about a power failure so that the microcontroller 120 can act accordingly. Unfortunately, this approach retains a disadvantage of the previous method, which is the need for an additional chip which increases the cost of the product.
In order to address the cost issue associated with adding chips to a memory product to improve its operational voltage range, some memory integrated circuits combine a CPU supervisor with memory, as shown by the memory 330 in FIG. 3. For example, a single chip solution containing 4K bits of EEPROM memory as well as a CPU supervisor and a reset controller circuit is available as product number X25045 from Xicor Semiconductor, Inc. of San Jose, Calif. This chip monitors the system supply voltage level and generates a reset when the voltage declines below a certain value. In the 5 V part (X25043) a reset is asserted when the supply voltage falls below 4.5 V, while in the 3 V part (X25043-2.7) a reset is asserted when the supply voltage falls below 2.7 V.
Although the use of a CPU supervisor in combination with memory achieves a greater operational voltage range without significant additional cost, further improvement would be desirable.

Method and apparatus for operating functions relating to memory and/or applications that employ memory in accordance with available power


A photodetector for measuring the position of an incident light beam on an active surface area of the detector includes an inactive area and a concentric stray light absorbing area, both of which outwardly surround the light-absorbing active area. All light incident on the stray light-absorbing area and the inactive area will generate a photoelectric current which is conducted to an earth ground via an electrode in the stray-light area. An electrical signal from the active area representing a position of the measured light in the active area will be unaffected by any stray light incident on the detector externally of the active area.

1. Field of the Invention
The subject invention concerns a device for measuring the position of a lighting spot having an integrated function, in order to handle stray light.
2. Discussion of the Prior Art
A position-sensitive photodetector, PSD, consists of a semiconductor wafer having a doped active surface with electrodes positioned in mutually opposite sides. The doped active area forms a pn-junction in the semiconductor wafer, and a resistive layer. An incident light beam will generate a photoelectric current which is proportional to the intensity of the incident light. Also, the photoelectric current will be divided in the resistive layer in the two electrodes linearly with the distance from the respective electrode. By comparing the magnitudes of the currents the expression (I.sub.A -I.sub.B)/(I.sub.A +I.sub.B) gives the position of the light beam on the active surface of the detector. (I.sub.A and I.sub.B represent the currents from respectively electrodes A and B). This is true with a high degree of linearity when the lighting point is incident only on the active surface. On the other hand, if light is incident on the semiconductor wafer externally of the active surface (which normally is referred to as the inactive area) a photoelectric current is generated also in this area and is registered in both electrodes. However, these currents are non-linear as well as slow. In other words, the position signal becomes considerably more non-linear and also very much slower. Thus, the possibility of obtaining satisfactory position measurements is impaired and sometimes even made impossible. In cases when the detector is used in applications where stray light occurs, this a considerable problem.
When the stray light emanates from other light sources than the measuring light it is possible, provided that the stray light intensity is within reasonable boundaries, to handle the stray light by means of either electrical or optical filters. An electrical filter is effective by screening off, in the subsequent signal processing, signals emanating from light having a different modulation from that of the measuring light. This method is adopted above all when a modulated light source having a comparatively high degree of modulation is used, such as 10 kHz, and receiving low-modulated or non-modulated stray light from the environment, such as sun light or fluorescent light etc. Optical bandpass filters operate by only letting through light having wavelengths within a narrow wavelength range. This phenomenon is used when the stray light has a different wavelength from that of the measuring light but otherwise the same modulation (most often non-modulated).
When the stray light emanates from the measuring light itself, owing to reflections in the metal parts of the instrument, for instance, or has a wavelength and a modulation close to that of the measuring light, the problem becomes more difficult to solve. The only way to eliminate the effects of stray light has hitherto been to screen off the stray light from the detector in some way or other. This could be effected in two different ways. Either a diaphragm is placed immediately above the detector or by applying directly on the detector surface a means screening off the light from the inactive area; The diaghragm could either be in the shape of a thin metal foil which is placed immediately ahead of the detector, or a diaghragm which is integrated into the protective glass by means of thin-film technology. This method puts considerably demands on the mounting of the diaghragm, particularly in the case of small-size detectors. In addition, diffraction phenomena may occur in diaghragm opening which thus generates stray light. The other possibility, to apply, in the processing of the very detector, some material screening off the light from the inactive areas, may be effected through vapourization of a metal, gold or aluminium. The disadvantages are that the thickness required in order to obtain absolute screening off of the stray light is not compatible with a normal semiconductor process. In addition, the presence of metal on these surfaces generates problems concerning the electrical properties of the detector. The consequence frequently is high leak currents that and growth thereof may come adrift. An absorbing paint, alternatively an epoxy, may be applied directly on the inactive detector area. This does, however, entail some obvious disadvantages in as much as on the one hand it is difficult to achieve sufficient opacity in the paint/epoxy to prevent passage-through of stray light and on the other the work involved in applying the paint/epoxy is a pure manual task, possible to carry out only when small quantities are involved, in addition to which the task is difficult to perform with the desired accuracy.

Photodetector having an integrated function for elimination of the effects of stray light


A system and method for detecting defects in semiconductor wafers in a rapid non-destructive manner. Defects in semiconductor wafers can include micropipes and screw dislocations, stress striations, planer defects, polytype inclusions, and others. When a wafer is illuminated by polarized light, the defects induce birefringence of the polarized light that can be visualized by a polariscope to detect defects in wafers. Defects can cause linearly inputted polarized light to emerge as elliptically polarized light after transmission through a wafer having defects. Placing the wafer between a set of polarizers under the cross poles condition allows for a rapid non-destructive system and method for delineating and locating defects within a semiconductor wafer.

Semiconductor devices, such as diodes, transistors, and integrated circuits are found everywhere in modern society. These devices are used in automobiles, cell phones, computers, televisions, satellites, and many other products. The semiconductor market has grown at a staggering pace over the years with improvements in performance and reduction in cost measured in orders of magnitude. This drastic improvement in semiconductor technology is due to the skill and technology advances in the ability to miniaturize devices so that more complicated devices can occupy smaller footprints on a wafer. The technology for the manufacture of semiconductors, specifically silicon devices, has matured into a reproducible and reliable manufacturing process. However, the manufacturing process is not perfect and wafers are still created that contain defects. Some of these defects prevent the full area of the wafer from being used as any device located over such a defect causes the device to fail or otherwise become inoperable. When an imperfection exists on a wafer, it is advantageous to know the location and level of imperfection so that the area sufficient for placing a device on a wafer can be known. Further, by performing the automatic mapping of defects during the manufacturing process, the growth parameters can be advantageously modified for improving crystal quality in subsequent wafer growth. Once the wafers are manufactured, the invention can assist with insuring quality control by measuring defects in specific production runs.
Referring now to a specific example, silicon carbide (SiC) wafers can be used for manufacturing high-frequency, high-powered, or high-temperature operating conditions for devices. Some of the advantages of SiC devices are that they have lower power dissipation, lower current leakage, and higher operational temperatures. In creating SiC devices, a SiC wafer is used as a foundation for the device. Unfortunately, SiC wafers contain defects, including dislocations such as threading edge, screw, and basal plane dislocations, and stacking faults. Specifically, micropipes are small tubular voids in the wafer that are generally oriented normal to the polished surface. The existence of micropipes and screw dislocations in the wafer, especially in high densities, prevents the use of large device areas for more powerful and complex devices. In fact, micropipes and screw dislocations have been identified as the main obstacle for commercializing large-area power devices. Micropipes lead to premature reverse breakdown in the SiC p-n junction and clearly adversely affect the electrical performance of the SiC device. The ability to detect the existence and physical location of the micropipes and screw dislocations on a wafer allows device manufacturers to determine the physical areas of the wafer where devices can be placed so that such defects will not degrade or destroy the functionality of the device.
Previously, methods for determining the number and location of micropipes in SiC wafers include KOH etching and transmission electron microscope (TEM). However, both are destructive methods resulting in a non-usable SiC wafer and not well suited for production line testing. While other methods exist, they require expensive equipment or special facilities. For example, synchrotron white-beam x-ray topography (SWBXT) requires a synchrotron light source that is available in only a few research facilities in the world. Other methods, such as atomic force microscopy (AFM), scanning electron microscopy SEM, and optical microscopy, while detecting micropipes, cannot detect closed-core screw dislocations in a non-destructive fashion. More specifically, it is advantageous to delineate and locate defects of the epitaxial films or layers. It is known that threading defects, such as micropipes, threading edge and screw dislocations, and grain boundaries, originating in the SiC or other substrate, penetrate the device structure during epitaxial growth and cause device failure or other inoperability. Further, process induced morphological defects can be caused by processes such as cutting, polishing, and preparing a wafer for growth.
Previously, there has not been an effective method or system to characterize the crystallographic defects and resulting morphological defects in the epilayer. Further, there has not been previously an effective method or system to determining threading defects, their propagation, or their correlation with growth pits of the epilayer, with or without the epilayer present.
Therefore, the development of a non-destructive, inexpensive, and rapid detection system and method for determining defects in semiconductors is a problem to which much attention should be directed.
Accordingly, it is an object of this invention to provide for an inexpensive, rapid, non-destructive system and method for determining defects in wafers.
It is another object of this invention to provide for an inexpensive non-destructive system and method for determining defects in wafers, with or without an epilayer.
It is another object of this invention to provide for an inexpensive non-destructive system and method for investigating threading defect propagation.
It is another object of this invention to provide for an inexpensive non-destructive system and method for investigating the relationship between wafer defects and device performance.

System and method for detecting defects in semiconductor wafers


Apparatus for ensuring adequate sunscreen protection includes a light-activated sunscreen product, and an illuminator including a battery, a switch and a light source that causes the light-activated sunscreen product to glow when illuminated with the light source. The light-activated sunscreen product may include a zinc-oxide-based lotion and a fluorescent substance such as fluorescein dye causing the lotion to glow in any available color when applied to the skin and illuminated by the light source. The closure may be a cap with a threaded attachment to the container, and the light source may comprise one or more ultraviolet light-emitting diodes. The illuminator may be disposed in a cap with top and side surfaces, and the switch may be positioned on the side of the cap, and the light source on the top of the cap, or vice versa. The switch is preferably a momentary contact switch.

Sunscreens are an effective way to reduce harmful exposure to the sun's rays, but they are only effective if the skin is adequately covered. Since these products are applied by hand, there is often no way of knowing if body surfaces have been 'missed' during application.
U.S. Pat. No. 5,562,896 discloses a method and device for protecting a body against sunburn involving application of a sunscreen composition capable of fluorescing under black light illumination. The body is viewed under illumination from the black light so as to identify any non-fluorescing, missed external portions of the body to which the sunscreen was not previously applied. However, the "black light" in this case "is well understood in the art to mean ultraviolet lamps of the type which commonly are sold in novelty stores and the like," and the lamps are disposed in a walk-in booth including a mirror for viewing application of the fluorescing sunscreen to a body.
There are also containers with caps that have UV light sources, but such light sources are used for entirely different purposes. One example is US20160220006, entitled "NAIL POLISH BOTTLE CAP WITH INTEGRAL GEL CURING LIGHT." As evident from the title, the purpose of the illumination if for curing nail polish gels, and not for activating a sunscreen to determine coverage.

Container with luminescent sunscreen and closure with illuminator


A bracket for use in retro-fitting metal clad buildings to facilitate attachment of new roof or wall panels of any desired profile, directly over existing ribbed or fluted panels of various configurations. Commonly known in the trades as a sub purlin or sub girt. Generally a one piece Z shaped metal bracket with a substantially vertical web between opposed top and bottom flanges in a parallel plane. The bottom flange and adjacent lower portion of the web contain a series of notches that allow the bracket to nest onto and over existing ribbed roof or wall panels. The top flange is automatically in position, lying flat and continuous, to receive and attach the new panels thereto. An ant-roll tab further connects the web to the existing roof panel. The solid portion of lower flange is preferred to be positioned directly above the underlying substructural support system members of the existing building to assure a structurally sound attachment of bracket to the building. Pre-punched holes in the solid portion of lower flange dictate required location, number and size of fasteners to be inserted through lower rib surface of existing panel into substructural system members.

A metal building, generally, is a lightweight structure consisting of vertical steel columns, steel rafter beams bolted to the vertical columns and generally spaced from 20 to 30 feet apart. The rafter beams are generally sloped to provide positive drainage. Spanning the columns and rafter beams at sidewalls and roof are a series of light gauge sub-structural "z" or "c" sections bolted to the columns and rafter beams. These are generally on 4′ to 5′ spacing and run perpendicular to the columns and rafter beams, commonly known in the trade as purlins for roof support and girts for sidewall support.
Covering the structural system are ribbed, fluted, standing seam or profiled panels with alternating higher ribs and flat valleys or pans generally with high rib being 6″ to 24″ on center and valleys being 4″ to 18″ across the flat and of generally 26 gauge or 24 gauge sheet metal, creating a structural diaphragm when fastened to the substructural system. Such higher rib surface's lie substantially in an upper plane and the bottom valley or pan surfaces lie substantially in a lower plane spaced apart from the upper plane. The alternating top and bottom surfaces are interconnected by a series of webs extending parallel to the longitudinal axis of the formed panel diaphragm.
There are an infinite variety of shapes of such configurations commercially available. For simple reference refer to the top surface as being the top plane of the higher rib and base surface as being the lower plane of the low rib. The web being the connecting form of the two. The panels are generally attached to the aforesaid sub-structural members with generally a series of threaded screws, generally 12″ or less on center for the entire building length. Standing seam type roofing is attached to the sub-structural members by means of clips mounted on the sub-structural members. Certain installations of these panels separate the panels from the sub-structure by a distance of ½″ to 6″ to improve the thermal qualities of the roof and/or wall system. These assemblies are difficult and in some cases impossible to retrofit because of the problem of providing a solid, stable retrofit sub-framing system due to the compressibility of the insulating material or gap between the roof panel and sub-structure.
The design of metal building structures optimizes minimum weight materials to work in unison in meeting the building code requirements for wind, snow, ice and live loading for the many geographical location's exposure to the elements. In achieving that criteria, each component is engineered to meet the requirements of the codes.
In re-roofing of such structures, extreme attention is given to limiting imposition of further dead loads on the original structural design and yet to resist the full wind uplift requirements of multiple building codes.


The present invention is directed toward a method, software product, and apparatus for allowing various kinds of information existing on a client terminal to be referred to on a Web browser of another collaborating client terminal. If an image displayed on a display screen of client terminal is specified, the image is compressed to a predetermined formed image data and also given a unique name in the system. This file is automatically sent to a Web server. A Web browser operating on the client terminal is automatically switched to display the file. A Web browser of another client terminal collaborating with this client terminal is also switched to display the file.

The Internet comprises multiple computer networks interconnected so that any computer on a given network can communicate with one or plural computers on any other given network. A gateway computer is a computer interconnecting two networks and passing data from one network to another network.
All the computers on the Internet communicate via a specific communication protocol, namely the Internet Protocol. Most applications use Transmission Control Protocol (TCP) along with the Internet Protocol. Accordingly, the Internet is also called the TCP/IP network. A computer connected to the Internet is identified by a unique Internet address.
The Internet performs routing of information by using the well-known packet switching technique. On the Internet, data is transmitted via a packet with an address (also called an IP packet). General Internet applications include those incorporating electronic mail, FTP, TELNET, network news, etc. The Internet protocol and applications are well known.
World Wide Web (namely, WWW or Web) is an information service system based on the Internet. WWW uses hypertext and client/server techniques. Hypertext is a method for structuring and presenting information so that a data object in a hypertext file can have a link to another hypertext file or data object. For instance, while a hypertext page is displayed, a user can select a word which has a link. Accordingly, the user can move to another hypertext file including another text or picture to explain the word (there are cases where the new file also has a link to another hypertext file, and from then on they are linked likewise).
Currently, many of hypertext files are composed by using hypertext markup language (HTML). A hypertext data object can be almost any information medium such as text, image, speech, image sequence or an executable computer program. Any hypertext file on the Web is uniquely identified by its universal resource locator (URL).
A Web client or a client (in general, a computer which executes a program called a browser) is essentially a hypertext reader which communicates with a Web server via a specific data transfer protocol such as the hypertext transfer protocol (HTTP). A client requests a hypertext file by using the appropriate URL and displays the file (called a Web page) on a graphical user interface (GUI). A Client can also return specific data to a server and call a common gateway interface (CGI) program to perform a specific task. Currently, NETSCAPE NAVIGATOR (trademark of Netscape Communications Corporation) and INTERNET EXPLORER (trademark of Microsoft Corp.) are known as general browsers.
WWW allows a user anywhere on the Internet to send a hypertext file on WWW by using the worldwide connections of the Internet, and allows any hypertext file to be fetched as conveniently as using a local hard disk. Thus, a user is given a strong tool for acquiring information, and the Internet becomes a hypermedia global database, namely an information superhighway.
The Internet and WWW have been dramatically expanding in recent years. Companies also expect a great opportunity in the use of the Internet and WWW as a new-generation worldwide communication basis for advancing into a huge consumer market.
In such Internet technologies, there exists a technology which uses a whiteboard to refer to common information with two terminals connected with a network (http://www.vocaltec.com/iphone4/ip4.htm, etc.). However, such a technology merely sends information, to be mutually referred to, to the other party connected by using the HTTP protocol, and does not allow access to that information again after a session has ended.
Moreover, even during a session, the information cannot be accessed by a third party. In addition, since data commonly referred to is displayed on the Web browser, the number of windows displayed on a desktop can be reduced. Also, in one aspect of the present invention, each user has a unique name to be stored on a server, and thus a file created by a specific user can be specified and referred to.
In conjunction with the problems to be solved by the present invention, Japanese Unexamined Patent Publication No. Hei 10-247176 activates an application on a Web server from a client terminal side to have a running state of the application displayed on the Web browser screen of the client terminal. To utilize this technology, however, it is necessary to register an application to run on the server in advance. Also, since an application is run in compliance with a request from the client terminal, the server's burden increases. Moreover, since an application is run in response to a request from the client terminal and the result, etc. are sent to the client terminal, there are drawbacks, namely, communication time becomes longer and the load to the system increases.
On the other hand, as in Japanese Unexamined Patent Publication No. Hei 10-124461, a collaboration technology is proposed, which allows plural users to simultaneously perform collaborative work on an HTML page (access, loading or change). FIG. 11 is a diagram showing an example of applying this collaborative work on an HTML page to an Internet banking system. This technology allows an event, etc. occurred on a URL or a Web browser specified by one user to be sent to another user's terminal so that reference to a common page, etc. can be made. If this technology is used, a bank agent can refer to the same page as a customer and simultaneously have communication such as mutually confirming its contents by telephone 1365A and 1365B.
In communicating with another operator in a remote place by using such a collaboration technology, there was a request asking that a state of an application other than a Web browser is immediately shown to the other operator.

Method and system for collaborating among interconnected client terminals

International Business Machines Corporation


A field programmable gate array architecture having a plurality of input/output pads. The architecture comprising: a plurality of logic clusters; a plurality of input/output clusters; a plurality of input/output buffers; a plurality of dedicated input/output first-in/first-out memory blocks, the dedicated input/output first-in/first-out memory blocks having a first-in/first-out memory coupled to one of the plurality of input/output pads; an input/output block controller programmably coupled to the plurality of dedicated input/output first-in/first-out memory blocks; and a routing interconnect architecture programmably coupling the logic clusters, input/output buffers and the input/output clusters, wherein the dedicated input/output first-in/first-out memory blocks are programmably coupled between the input/output buffers and the input/output clusters.

1. Field of the System
The present system relates to field programmable gate array (FPGA) devices. More specifically, the system relates to an input/output first in/first out module for an FPGA.
2. Background
FPGAs are known in the art. An FPGA comprises any number of logic modules, an interconnect routing architecture and programmable elements that may be programmed to selectively interconnect the logic modules to one another and to define the functions of the logic modules. To implement a particular circuit function, the circuit is mapped into the array and the appropriate programmable elements are programmed to implement the necessary wiring connections that form the user circuit.
An FPGA core tile may be employed as a stand-alone FPGA, repeated in a rectangular array of core tiles, or included with other functions in a system-on-a-chip (SOC). The core FPGA tile may include an array of logic modules, and input/output modules. An FPGA circuit may also include other components such as random access memory (RAM) modules. Horizontal and vertical routing channels provide interconnections between the various components within an FPGA core tile. Programmable connections are provided by programmable elements between the routing resources.
An FPGA circuit can be programmed to implement virtually any set of digital functions. Input signals are processed by the programmed circuit to produce the desired set of outputs. Such inputs flow from the user's system, through input buffers and through the circuit, and finally back out the user's system via output buffers referred to as input/output ports (I/Os). Such buffers provide any or all of the following input/output (I/O) functions: voltage gain, current gain, level translation, delay, signal isolation or hysteresis.
The input/output ports provide the access points for communication between chips. I/O ports vary in complexity depending on the FPGA. FIG. 1 is a simplified schematic diagram illustrating a basic I/O circuit structure 10 as well known to those of ordinary skill in the art. I/O circuit structure 10 comprises an output buffer 12, an input buffer 14 and an I/O pad 16. Output buffer 12 receives signals from the FPGA core via output signal line 20. When the output buffer is enabled by a control signal sent through the output enable control line 18, output buffer 12 provides a signal to I/O pad 16 via output signal line 22. Input buffer 14 provides a signal to the FPGA core via input signal line 24 when the input buffer is enabled by a control signal sent through the input enable control line 26. Input buffer 14 receives a signal from I/O pad 16 through input line 28.
FIG. 2 is a simplified schematic diagram illustrating an I/O circuit structure 30 having registers. I/O circuit structure 30 comprises an I/O pad 32 coupled to output buffer 34 coupled to the FPGA core (not shown) through register 36. I/O pad 32 is also coupled to the FPGA core through input buffer 38 and register 40. Output buffer 34 receives signals from the FPGA core through register 36 via signal line 42 when register is enabled and provides the output signal to I/O pad 32 via signal line 48. Input buffer 38 receives signals from I/O pad 32 via signal line 50 and provides signals to the FPGA core through register 40 via input signal line 52.
As set forth above, FPGAs are programmable digital logic chips. A board level digital system is comprised of a printed circuit board with several digital chips interconnected to perform a digital function. Complex system level tasks are realized by smaller tasks that are carried out by specialized dedicated chips. The chips are then connected together to provide the overall system function.
The communication between the components of a system can be described by the signaling and the data format. The device's input/output (I/O) ports provide the signaling format. For example, the signaling format may be 3.3V PCI, low voltage transistor transistor logic (LVTTL) or low voltage differential signaling (LVDS). The data format for communication between chips is system dependent. Some of the system dependent parameters include the bus width and the clocking scheme. For example, data can be transmitted bit-wise serially or n-bits in parallel. Also, the clocking of the transmitters and receivers can be synchronous or otherwise. First-in/first-out memories (FIFO) are often used in systems to bridge data flow gaps between chips. Data flow gaps are the result of chips working with different clock rates, different clock skew, different data bus widths or readiness differences of two chips to send or read packets of data.
A FIFO is basically a SRAM memory with automatic read and write address generation and some additional control logic. Counters are used for address generation. The data sequence read from a FIFO memory is the same as the data sequence written to its memory. The sequencing of the write and read addresses is controlled by the control logic.
Circuits implementing a FIFO function are often used for transmitting and recovering data. In these applications, data can be received until the FIFO memory has become full, often indicated by a FIFO-full flag. Data can also be read from the FIFO until the memory has become empty often indicated by a FIFO-empty flag. Read and write operations need not be synchronized to each other.
FIFOs are suited for applications requiring frequency and phase coupling. The FIFO provides the means to pass data between one clock domain and the next. The write clock and the read clock need not be locked in frequency or phase to pass data between the clock domains. One example is a transmitter sending data at 66 Mbits/second serially and the receiver processing data in bursts at 132 Mbits/second. The receiver FIFO would have its write clock operating at 66 Mhz and the read clock at 132 Mhz. Handshake signals are required to prevent data from being lost at either the full or empty states of the FIFO. The empty and full flags provide such handshake control. Some applications have the write clock and the read clock at the same frequency, but the clocks are not locked in phase. The FIFO provides the means to pass data from one clock domain to the next.
FIFOs are also well suited for applications requiring data bus width matching. An example would be when data into the chip is wider that data inside the chip. Another example is when the data bus width internal to the FPGA is wider than the data bus width in the off chip direction.
An FPGA is capable of implementing a FIFO function. However, the implementation would require programming all of the FIFO components, the address counters, flag logic and memory into the FPGA's core logic. The implementation would consume a considerable number of logic modules and the performance would be dependent on the FPGA architecture.
Hence, there is a need for an FPGA that has dedicated logic specifically included to implement a input/output FIFO function. There is also a need for an FPGA that has dedicated logic to implement the FIFO control and flag logic. Ideally, the input/output FIFO logic would be included among the logic components in an FPGA core tile. Hence, what is needed is an FPGA having dedicated logic to implement a FIFO function. The result is improved performance and a decrease in silicon area needed to implement the FIFO functions due to the small silicon area needed to implement the FIFO function with dedicated logic.

This patent is subject to a terminal disclaimer.

Dedicated input/output first in/first out module for a field programmable gate array


A valve block, in particular for slip-controlled hydraulic brake systems, includes a plurality of valve domes (10) incorporating magnet coils (1) and insulating casings cast around the magnet coils (1), as well as a contact carrier (2) containing a plurality of electric conductors (4), with the insulating material (10) encompassing the magnet coils (1) forming an integral unit with the contact carrier (2). The resulting design improves manufacturability, functional reliability, modular design flexibility and serviceability.

A like valve block is known from patent application P 37 01 019.0. The external housing of the valve block is fixed on the valve block housing by a catch-type arrangement in this design, and the electric conductors and the magnet coils are soldered and are guided with a contact member designed as a multipoint plug in the housing cover to connect to a control unit. The requirement of a separate housing cover and soldering of the coils and the conducting paths have to be regarded as not favorable, since the comparatively great expenditure entailed for soldering the conducting path and the coils has adverse affects on manufacturing costs. Moreover, the complicated assembly of the large number of component parts, the risk of corrosion in the event of insufficient plug sealing and cover sealing as well as the insufficient heat emission through the housing cover and the heat expansion resulting therefrom are regarded as disadvantageous in the known conventional valve block design.

Valve block, in particular for slip-controlled hydraulic brake systems


The disclosure concerns face recognition systems. The aim is to identify candidate matching images to a probe image. There is provided methods, software and computer system to select (22, 24) a method of matching images from two or more methods of matching images based on an underlying resolution (20) of the probe image (8). Comparing two images of differing resolutions is common in surveillance environments. To alleviate this degradation, the method advantageously dynamically selects the most appropriate matching method for a probe image. The disclosure also provided methods to determine the underlying resolution of a probe (8) or gallery image (14).

The process performed by a typical face recognition system is shown in FIG. 1. The aim is to identify the person whose face is represented in the probe image 8 by comparing the probe image to a set of gallery images 14. Each image in the set of gallery images 14 includes the face of a person whose identity is known.
The size of the probe image 8 and gallery images 14 must be the same prior to feature extraction [3]. As such, the images are normally resized during pre-processing 10 to a common intermediate format (IF) size (e.g. small sized images are up-scaled to this IF size while large sized images are downscaled to this IF size).
The face matching method is previously tuned to work with that particular IF image size. Then this face matching method 12 is applied to each probe image 8 by comparison to each of the gallery images 14 to identify candidate matching images in the set of gallery images 14.
Face matching methods can be placed into two general families: holistic and local-feature based. In typical holistic methods, a single feature vector describes the entire face and the spatial relations between face characteristics (e.g. eyes) are rigidly kept. Examples of such systems include PCA and Fisherfaces [2]. In contrast, local-feature based methods describe each face as a set of feature vectors (with each vector describing a small part of the face), with relaxed constraints on the spatial relations between face parts [4]. Examples include systems based on elastic graph matching, hidden Markov models (HMMs) and Gaussian mixture models (GMMs) [4].
Local-feature based methods have the advantage of being considerably more robust against misalignment as well as variations in illumination and pose [4, 11]. As such, face recognition systems using local-feature based approaches are more suitable for dealing with faces obtained in surveillance contexts.
Post processing 16 is then performed on the results of the face matching method 12 such as referencing details of the people that were identified as candidate matches from an external database (not shown).
Finally, the likely identity information 18 of the candidate match(es) from the set of gallery images 14 are presented to the user.
The use of IF processing in typical face recognition systems leads to disadvantages in mismatched resolution comparisons which include:                (i) For images with low underlying resolution, upscaling does not introduce any new information, and can potentially introduce artifacts or noise. Also, upscaled images are blurry, which causes the extracted features to be very different than those obtained from the downscaled faces with high underlying resolution, resulting in a significant drop in recognition accuracy.        (ii) Downscaling reduces the amount of information available, thereby reducing the performance of the face matching method.
Any discussion of documents, acts, materials, devices, articles or the like which has been included in the present specification is solely for the purpose of providing a context for the present invention. It is not to be taken as an admission that any or all of these matters form part of the prior art base or were common general knowledge in the field relevant to the present invention as it existed before the priority date of each claim of this application.
Throughout this specification the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element, integer or step, or group of elements, integers or steps, but not the exclusion of any other element, integer or step, or group of elements, integers or steps.


A toner for electrophotography which comprises, as a binder resin, a polyester resin obtained from carboxylic acids containing aromatic monomer in a proportion of 80 mol % or more relative to the entire carboxylic acid component, and alcohols containing aliphatic diols having 2 to 4 carbon atoms in a proportion of 70-100 mol % relative to the entire alcohol component and alicyclic alcohols in a proportion of 0-30 mol % relative to the entire alcohol component, and having a specific gravity of 1.3 or more, a glass transition temperature of 58.degree. C. or more, and a number average molecular weight of 1,000-6,000. The toner of the present invention is superior in image characteristics, fixability, storage stability (resistance to blocking), resistance to plasticizer and charge stability. Therefore, even after a long-term storage of a sheet copied using the toner of the present invention, by keeping same in direct contact with a vinyl chloride transparent sheet or an eraser, transfer of coloring materials and attaching of resin onto the vinyl chloride sheet or the eraser do not occur.

In general, an electrophotographic method includes uniform charging of an inorganic photoconductive substance (photosensitive drum) such as selenium, amorphous silicon and zinc oxide, or an organic photoconductive substance (photosensitive drum) such as diazo compound, pigment, etc., which has been in most cases prepared into a drum, irradiation of an image modulated light to form an electrostatic latent image, said image being developed by allowing a powder material to be attracted by static electricity, transferring the powder material on a receiving surface such as paper, film, etc. as necessary, and fixing same by applying pressure, heat, and so on. The electrophotographic method has been widely used for copier, laser printer, facsimile, etc.
The powder for forming an image by developing the electrostatic latent image on the photosensitive drum, which is ultimately transferred onto a receiving surface such as paper or film in the electrophotographic method is referred to as a toner. A toner is usually mixed with a carrier such as glass beads, iron powder, ferrite, etc., and used as a developing powder. As the toner as a developing powder for electrophotography, used are particles prepared by the pulverizing method comprising mixing and kneading of a binder resin with colorants, charge control agents, flowability improvers, pulverization aids, etc., pulverizing the obtained mixture, and classifying the same.
As the toner binder resin, styrene/acrylic copolymers have been mainly used. However, polyester resins have been drawing attention recently in view of their excellent fixability at low temperatures as demanded by the increased speed and coloring of electrophotography.
In particular, colored electrophotography requires gloss on the image surface from the aspect of color reproduction, and polyester resins which afford superior surface gloss by low temperature fixing have been increasingly used.
The polyester resins conventionally used are mainly unsaturated polyester resins obtained by condensation polymerization of aliphatic unsaturated carboxylic acids such as fumalic acid, maleic acid, etc. with diols having bisphenol structure.
The glass transition temperature of the polyester resin depends mainly on number average molecular weight. The unsaturated polyester resin is generally polymerized by the normal pressure method, whereas a high molecular weight polyester resin cannot be produced by the production processes thereof, thus failing to achieve high glass transition temperature. The glass transition temperature of unsaturated polyester resin obtained by conventional methods is about 55.degree. C., which in turn causes poor storage stability of a toner comprising an unsaturated polyester resin as a binder resin, despite its superior low temperature fixing characteristics, as evidenced by the fact that a long-term storage at high temperature results in blocking of the toner.
In case where bisphenol diols are used, plasticizers used in sheets made of vinyl chloride resins and erasers tend to transfer. For this reason, when copied images are kept in a clear file or on a desk mat made of vinyl chloride resins, or an eraser or eraser refuse is left on the images, the plasticizer contained in the vinyl chloride sheet or eraser gives rise to the damaged images and staining of the clear sheet or eraser.
In the case of colored electrophotography, it is required that a toner should possess high transparency from the aspects of reproduction of intermediate colors and penetrability of the sheets for overhead projectors. The use of a dye as a colorant is preferable for increasing transparency of a toner. However, resins comprising bisphenol type diols do not permit sufficient color production by the dye, since they cause marked degradation of color fastness to heat and color fastness to light of the dye, for which reason the colorant is limited to pigments which are poor in transparency. In order to produce transparent toners by using pigments, it is necessary to disperse pigments finely pulverized to the size smaller than the light wavelength in a resin as primary particles, and this process gives rise to various problems while processing.
There has been an attempt to use aromatic polyester resins obtained from aromatic dicarboxylic acids such as terephthalic acid and isophthalic acid, and aliphatic diols such as ethylene glycol and neopentyl glycol as a toner binder, besides the above-mentioned unsaturated polyester resins.
The aromatic polyester resins can be easily made to have high molecular weight, since they are usually polymerized by the reduced pressure method. For this reason, high glass transition temperature of the aromatic polyester resins can be achieved rather easily, and can afford toners with good storage stability.
On the other hand, practical glass transition temperature of about 58.degree. C. or more, preferably 60 .degree. C. or more, more preferably 63.degree. C. or more requires extremely high number average molecular weight of polyester resin, which in turn raises melt viscosity of the polyester resin, impairing low temperature fixability possessed by the polyester resin.
For the realization of high glass transition temperature while retaining low temperature fixability, there has been proposed introduction of bisphenol type diols as a diol component. When the bisphenol type diols are introduced, both the glass transition temperature of not less than about 58.degree. C. and low temperature fixability can be obtained. In this case, however, the same problems as in the case of the aforementioned unsaturated polyester resin, namely, decrease in color fastness to heat, color fastness to light, and resistance to plasticizer can occur, and a toner for electrophotography having good characteristics cannot be obtained.


A capacitor array-based, successive approximation analog-to-digital signal converter includes a capacitor array with a central coupling capacitor having a unit-value capacitance and two sets of input coupling capacitors having capacitances which are binary weighted multiples of such unit-value capacitance. During the sampling phase, the first set of input coupling capacitors is grounded while the second set of input coupling capacitors is driven by the analog input voltage. During the holding, or conversion, phase, one of the input coupling capacitors in the second set is grounded while each one of the input coupling capacitors in the first set and each one of the remaining input coupling capacitors in the second set is driven by a respective binary multiple of a fixed reference voltage, with each one of such binary multiples corresponding to one of the bits of the successive approximation result.

1. Field of the Invention
The present invention relates to successive approximation analog-to-digital signal converters (SAR ADCs), and in particular, to capacitor arrays forming the digital-to-analog converter (DAC) portion of an SAR ADC.
2. Description of the Related Art
Referring to FIG. 1, a conventional SAR ADC implemented with an array of capacitors for the DAC portion includes a DAC 12, voltage comparator 14, and SAR logic 16, interconnected as shown. The analog input V.sub.IN is processed, i.e., weighted, within the DAC 12 in accordance with the digital data bits 17 from the SAR logic 16. This produces an analog voltage at output 13 which is compared to a reference voltage V.sub.CR by the comparator 14. The comparator output 15 is processed by the SAR logic 16 in accordance with well known principles to produce the digital output data bits 17.
Using a capacitor array-based DAC, as opposed to a resistive ladder network (the analog output of which is compared against the analog input V.sub.IN by the comparator), provides several advantages, such as no DC power dissipation, no static current drain through switches, plus good matching between the passive components, i.e., the capacitors.
Referring to FIG. 2, a conventional implementation of the capacitor array 12a within the DAC 12 uses binary weighted capacitor values. During the sampling phase, each of the capacitors C.sub.0, C.sub.1, C.sub.2, . . . , C.sub.N-1 within the array is driven by the analog input V.sub.IN, while during the hold phase, i.e., the successive approximation conversion phase, each capacitor is individually driven by a reference voltage V.sub.REF which is weighted with one of the input data bits D.sub.K.
Referring to FIG. 3, operation of the conventional binary capacitor array can be better understood. In addition to the capacitor array 12a itself, the DAC 12 also includes a switching matrix 12b which includes N switches S.sub.0, S.sub.1, S.sub.2 . . . , S.sub.N-1 (where N equals the number of digital data bits 17) and controls the driving of the individual capacitors C.sub.0, C.sub.1, C.sub.2, . . . , C.sub.N-1. During the sampling phase, the switch S across the inputs of the comparator 14, in accordance with a sample and hold control signal S/H, is closed and the input switches S.sub.0 -S.sub.N-1 are in position 1, thereby causing the capacitors to be driven by the analog input V.sub.IN. During the hold phase, the switch S across the inputs of the comparator 14, in accordance with the control signal S/H, is opened and each of the individual input switches S.sub.0 -S.sub.N-1, in accordance with its respective digital data signal bit D.sub.0 -D.sub.N-1, is switched into position 2 or 3. For example, for the first input switch S.sub.0, if its data bit D.sub.0 is a logic 0, the switch S.sub.0 is in position 2, while if the data bit D.sub.0 is a logic 1, the switch S.sub.0 is in position 3. Accordingly, the inputs to each of the capacitors C.sub.0 -C.sub.N-1 is a binary weighted version of the reference voltage V.sub.REF.
Notwithstanding the aforementioned advantages of a capacitor array-based DAC, however, such an implementation has a significant disadvantage. In order to provide good matching of the capacitors, the larger capacitors are constructed using multiples of a selected unit capacitance. However, for the implementation as shown in FIGS. 2 and 3, the ratio of the larger capacitor to the smallest capacitor increases exponentially with the number of bits. This increases the area needed for the capacitor array, as well as the input capacitance during the sampling phase of operation. For example, the input capacitance for such implementation during the sampling phase is the sum of the capacitances of all of the input capacitors C.sub.0 -C.sub.N-1 (i.e., C+2C+4C+ . . . +2.sup.N-1 .multidot.C).
Referring to FIG. 4, one conventional technique used to reduce the necessary area for the capacitor array, as well as reduce the large input capacitance during the sampling phase, is to use a split capacitor array. In such a DAC 12c which uses such an array, a coupling capacitor C.sub.C essentially splits the array into two smaller capacitor arrays. Operation of the primary input switches S.sub.0 -S.sub.K+M for driving the primary input capacitors C.sub.0 -C.sub.K+M (where K+M=N) is as described above in connection with the DAC 12b of FIG. 3. One additional input capacitor C.sub.S, driven by the sample and hold control signal S/H, is also used, along with a corresponding switch S.sub.S which is switched into position 1 during the sampling phase and is switched into position 2 during the hold phase. The areas of the necessary capacitors are reduced because of the reduced maximum capacitor value within each of the smaller capacitor arrays on either side of the coupling capacitor C.sub.C.
However, a significant disadvantage of this technique is the fractional value of the coupling capacitor C.sub.C used to split the overall capacitor array. Having such a fractional value results in poor matching between the coupling capacitor C.sub.C and the remaining individual capacitors C.sub.S, C.sub.0 -C.sub.K, C.sub.K+1 -C.sub.K+M within the array. While it is possible to improve this matching by appropriately ratioing the area and perimeter of the coupling capacitor C.sub.C to the area and perimeter of the unit capacitors C.sub.S, C.sub.0 -C.sub.K, C.sub.K+1 -C.sub.K+M, this makes the layout of the array more difficult to achieve. Further, any mismatch between the fractional coupling capacitor C.sub.C and the remaining capacitors C.sub.S, C.sub.0 -C.sub.K, C.sub.K+1 -C.sub.K+M affects the overall performance of the converter 12c in terms of its differential non-linearity.
Accordingly, it would be desirable to have an implementation of a capacitor array-based DAC which avoids problems associated with capacitors which increase exponentially in size with the number of bits, while also avoiding problems associated with matching between unit and fractional value capacitors.

Split capacitor array for digital-to-analog signal conversion


An image coding method according to one aspect includes dividing an input image into processing target block(s), determining a mode of an intra-picture prediction of the processing target block in units of the divided processing target block(s), holding the prediction mode into a holding unit, estimating the intra prediction mode of the processing target block, comparing the result of the prediction mode determination and the result of the prediction mode estimation to determine whether they match each other, coding the result of the comparison, and further, when the result of the comparison indicates a mismatch, coding the result of the prediction mode determination. An intra prediction mode of one or more predetermined processing units surrounding the processing target block from the holding unit is acquired and compared, and the coding is controlled based on the result of the mode comparison.

There is known a method for recording a moving image while compressing it such as H.264/Moving Picture Experts Group-4 Advanced Video Coding (MPEG-4 AVC) (hereinafter referred to as "H.264") (International Organization for Standardization/International Electrotechnical Commission (ISO/IEC) 14496-10: 2004, "Information technology—Coding of audio-visual objects—Part 10: Advanced Video Coding"). The H.264 coding method is widely used in, for example, one-segment digital terrestrial broadcasting. The H.264 coding method is characterized in that this method performs an integer transform per unit of four-by-four pixels and prepares a plurality of types of intra predictions (intra-picture predictions), in addition to the conventional coding method. Other characteristics of the H.264 coding method are that this method uses a loop filter, allows reference to a plurality of previous and subsequent frames, and provides motion compensation with use of seven types of sub blocks. Further, as is the case with the MPEG-4 method, the H.264 coding method can perform motion compensation with quarter pixel precision. Further, the H.264 coding method is characterized by use of, for example, universal variable length coding and context-adaptive variable length coding as entropy coding ("H.264: Advanced video coding for generic audiovisual services" published by International Telecommunication Union Telecommunication Standardization Sector (ITU-T))
The H.264 method has a plurality of modes for an intra prediction, and therefore bits should be assigned and coded for intra prediction mode information for identification of a selected mode as side information. For example, an intra prediction predicts a block from the surrounding blocks for each block constituted by four-by-four pixels in a macro block, and further estimates the prediction mode of the pixel block from the prediction modes of the surrounding blocks. Then, one bit is assigned to a flag (prev_intra4×4_pred_mode_flag) indicating a match/mismatch between the predicted mode and the estimated mode. Subsequently, in a case where the predicted mode does not match the estimated mode, three bits are assigned to a flag (rem_intra4×4_pred_mode) indicating the predicted mode for each block.

Image coding apparatus, image coding method and program, image decoding apparatus, and image decoding method and program