Methods and apparatus are provided for determining level-thresholds for q-level memory cells. A group of the memory cells are read to obtain respective read signal components. The read signal components are processed in dependence on signal level to produce a signal level vector, comprising a series of elements, indicative of the distribution of read signal components in order of signal level. A plurality of possible sets of q−1 elements corresponding, respectively, to q−1 level-thresholds which partition the signal level vector into q segments, is then defined. The q−1 level-thresholds for the group of memory cells are then determined by selecting from said possible sets that set for which a predetermined difference function, dependent on differences in signal level for elements in each of said q segments for the set, has an optimum value.

This invention relates generally to estimation of level-thresholds for memory cells. Methods and apparatus are provided for determining thresholds between successive cell levels on readout of q-level memory cells, together with data storage devices incorporating such apparatus.
In solid-state memory such as flash memory and phase-change memory, the fundamental storage unit (the "cell") can be set to q different states, or "levels", permitting storage of information. Each cell can be used to store a qary symbol with each of the q possible symbol values being represented by a different cell level. In so-called "single-level cell" (SLC) devices, the memory cells can be set to only two levels (q=2) and so can record only binary values. Other devices use so-called "multi-level cells" which can be set to q>2 different cell levels, thus permitting storage of more than one bit per cell.
Detection of data stored in q-level memory cells relies on identifying the different cell levels on readback. In flash and phase change memory (PCM), for example, the different cell levels exhibit different electrical charge and electrical resistance characteristics respectively, and these can be detected via current or voltage measurements on the cells. On readout of cells, the read signal level can be compared with a set of reference signal levels indicative of the q cell levels in order to determine which level each cell is set to and thus detect the stored symbol value. A basic problem here is that the physical quantity measured during cell readout is subject to variability, e.g. due to noise and/or drift in measured values with time or cell usage. Multiple read operations on cells set to any given cell level will therefore yield a distribution of read signal levels.
Accuracy of the reference signal levels used for data detection is crucial to readback performance. Reference signal levels can be expressed as "level-thresholds" for the q cell levels. For each pair of successive memory cell levels, the level-threshold indicates a read signal level defining the threshold, or boundary, between read signal level distributions corresponding to the two cell levels. The reference signal levels for detection of q-level cells can therefore be expressed as q−1 level-thresholds.
A conventional technique for reference level estimation uses training data derived from a pool of reference memory cells. Known information is written to the reference cells each time a block of user data is written to memory. The reference cells are read whenever the user file is read, and the reference cell readings are used to derive estimates for the reference signal levels. The reference cell approach has various disadvantages, including overhead due to use of memory area for reference purposes, and varying effectiveness due to inherent variability between cells in a memory array.
More sophisticated techniques for reference level estimation are self-adaptive, using the readback signals from cells storing actual user data to estimate the reference levels used for detection of data in those cells. Self-adaptive techniques for reference level estimation are described in our US patent Application publication no. US 2013/0227380 A1 and our UK Patent Application no. 1307788.8, filed 30 Apr. 2013. These applications disclose systems for read-detection of length-N, qary-symbol codes in MLC memory. Each symbol of an N-symbol codeword is recorded in a respective q-level cell by setting the cell to a level dependent on the qary symbol value. Memory cells are read in blocks to obtain read signals corresponding to a group of codewords. Each read signal has N read signal components corresponding to respective symbols of a codeword. The read signal components of the entire group of read signals are ordered according to signal value. The resulting ordered component sequence is then partitioned to obtain a plurality of segments each corresponding to a different memory cell level. The size (i.e. number of components) of each of these segments is determined based on predetermined frequency data indicative of expected frequency of occurrence of the corresponding level in use of the code. The resulting read signal level distributions corresponding to respective memory cell levels are then further processed to derive statistical data for use in the codeword detection process.
Another self-adaptive technique for estimating level-thresholds is described in our UK Patent Application no. 1317081.6, filed 26 Sep. 2013. The read signal components obtained by reading a block of q-level memory cells are processed in dependence on signal level to produce a signal level vector. This vector comprises a series of elements and indicates the distribution of read signal components in order of signal level. For example, the signal level vector can be produced by ordering the read signal components according to signal level, or by binning the components according to signal level. A sliding-window scan is performed on the signal level vector, and a metric, dependent on the elements of the signal level vector in the window, is calculated at each window position. The level-thresholds for the q cell levels are then determined based on variation of this metric over the scan. This technique performs well even in the presence of data asymmetry, i.e. where there is a significant difference in the numbers of cells set to the q different cell levels.
The foregoing self-adaptive techniques are a major advance on the reference cell approach, offering much-improved performance. As readback block sizes decrease, however, it becomes more difficult to meet the performance specifications for memory devices. In PCM devices, for example, in order to achieve the required bit error rates for specified data retention times, read detectors using current self-adaptive level-estimation systems require block sizes of at least 256 bits. This corresponds to 128 (q=4)-level cells. However, current PCM applications require block sizes of 64 bits or 128 bits, i.e. 32 or 64 4ary cells respectively, and further reduction in block size can be envisaged. In view of the above, improved techniques for determining level-thresholds would be desirable.

Estimation of level-thresholds for memory cells

International Business Machines Corporation


The present invention includes live strain of Francisella tularensis wherein a gene selected from the group consisting of priA and purA is inactivated. The present invention further includes a pharmaceutical composition comprising one or more live strains of Francisella tularensis according to the present invention and a pharmaceutically acceptable carrier. The present invention further includes a method of using one or more live strains of Francisella tularensis according to the present invention to confer immunity against a virulent strain of Francisella tularensis. The method comprises administering an effective amount of one or more live strains of Francisella tularensis according to the present invention or a pharmaceutical composition comprising one or more live Francisella tularensis strains to an animal such that an immune response is produced in the animal.

1. Field of the Invention
This invention relates generally to the field of vaccine strains. More particularly, it relates to attenuated strains of Francisella tularensis and methods of use thereof.
2. Description of the Related Art
Francisella tularensis (F. tularensis) is a Gram-negative coccobacillus with a natural reservoir that includes small mammals such as rabbits, hares, and rodents, as well as aquatic environments and soil. F. tularensis includes four subspecies—tularensis (type A), holarctica (type B), novicida, and mediasiatica—and the most virulent of these, F. tularensis subspecies tularensis, can cause infection with doses as low as 10 colony forming units (cfu). Transmission typically occurs via handling of infected animals and carcasses, consumption of contaminated food products, and occasionally through insect vectors. The strain and route of infection determines the progression of the disease, which generally involves spread to multiple organ systems and the lymphatic system. The U.S. Government currently classifies F. tularensis as a Tier 1 Select Agent, meaning that it has been determined to potentially pose a severe threat to human and animal health. Interest in the pathobiology of the bacterium has been rekindled with the recognition that F. tularensis may be deployed as a potent bioweapon due to its ease of dissemination via aerosolization and extremely low infective dose. Left untreated, F. tularensis has the potential to be lethal in 30-60% of infected individuals.
F. tularensis enters host macrophages and employs a variety of methods to evade host defense mechanisms throughout the infection cycle. The host immune system is evaded by a lipopolysaccharide (LPS) that interacts poorly with host pattern recognition receptors and does not induce inflammatory cytokines. In serum, F. tularensis binds Factor H to inactivate C3b by converting it to iC3b, which interferes with the formation of a membrane attack complex and opsonizes the bacterium to facilitate pathogen entry into the host by exploiting macrophages as a niche for replication. F. tularensis-containing phagosomes are arrested in the late endosomal stage and avoid fusion to lysosomes. The phagosome is transiently acidified leading to its disruption and escape of the bacteria into the cytosol. After replication in the cytoplasm, the bacteria induce autophagy and are released through apoptosis and pyroptosis.
Despite a generalized understanding of the F. tularensis infective cycle, more insight into the genes contributing to and controlling, for example, infection, intracellular survival, replication, pathogenicity, and effect on host immune response is needed for the development of effective vaccine and therapeutic countermeasures. An undefined vaccine strain of F. tularensis referred to as Live Vaccine Strain (LVS) was developed, which has demonstrated the ability confer at least partial immunity to challenges by F. tularensis subsp. tularensis. However, due to an incomplete understanding of the attenuation mechanism, presence of side effects, and other safety concerns, LVS has not been approved by the U.S. Food and Drug Administration for use as a vaccine.
In addition, a variety of methods such as random insertional mutagenesis using transposons, targeted gene replacement based on homologous recombination strategies, and targeted insertional inactivation using group II introns or targetrons have been used to mutagenize or disrupt F. tularensis genes and evaluate impact on intramacrophage survival and growth. Generation of transposon mutant libraries provide a high-throughput technique to screen for mutations that affect, for example, intramacrophage growth and virulence. However, the random nature of transposon insertions requires additional steps to ensure lack of hot spots and even distribution of insertions, as well as to determine the site of insertion and to demonstrate that a single insertion is responsible for the observed effects. Homologous recombination provides precise, targeted inactivation of genes but is difficult to adapt to high-throughput format. Use of targetrons combines the best aspects of transposon and homologous recombination techniques to provide a highly precise and easily adaptable method for disrupting and/or inactivating large numbers of genes throughout the genome.

The United States of America as represented by the Secretary of the Air Force


A semiconductor wafer comprising a substrate layer and a first GaN layer having one or more SiNx interlayers therein, wherein in the first GaN layer at least one SiNx interlayer has GaN penetrated through one or more portions of said SiNx interlayer and preferably has a thickness of from 0.5 to 10 nm.

Optoelectronic devices are well known and it is also known that for such devices it is desirable to minimise the occurrence of defects in the semiconductor layers that form part of the structure of the device. Common defects in LEDs, for example, include threading (edge or screw type) dislocations which lead to a reduced luminescent efficiency in the final product. The efficiency reduction can, at least in part, arise due to non-radiative recombination that can occur at dislocations and defects. These defects reduce the internal quantum efficiency (IQE) of the device.
One cause of such dislocations, as discussed in WO2006/014472, is lattice mismatches between dissimilar layers. Dislocations can arise simply due to different lattice parameters and/or due to thermal contraction at different rates following thermal growth techniques. One way to reduce the dislocation density is to rely on the growth of interlayers, as described in US2002/0069817. The technique described in US2002/0069817 relies in part on the growth of a thick layer of GaN.
A consequence of the mismatched lattice parameters and thermal expansion coefficients, particularly where the difference lies between the substrate and the overlying layers, is a high degree of curvature that is introduced into the wafer by the mismatch. This curvature affects the size of wafer that can be manufactured or leads to wafers with high defect levels.
If an overlying layer has a significantly larger thermal expansion coefficient than the substrate, the overlying layer would be in tension. This can lead to crack formation. For LED structures, where a GaN layer is preferably n-type doped, the doping adds additional tensile stress to the structure. As a consequence, stress management is critical, especially where Si substrates are used.
Several methods have been proposed to address the issue of tensile stress and associated curvation and/or cracking. Methods include the use of patterned substrates to guide the cracks in masked or etched parts of substrates, the use of compliant substrates, or the insertion of low-temperature AlN interlayers. US2010/0032650 discusses some of these techniques. It is, however, considered that to make, for example, GaN-based LEDs on Si substrates by a low-cost route, extra procedures such as ex-situ patterning before growth are not preferred, and a method is required that gives simultaneously crack-free layers, a low threading dislocation and a flat wafer.

Semiconductor wafer comprising gallium nitride layer having one or more silicon nitride interlayer therein


A cutting tool and a cutting insert, each of which including a base surface and an anti-slip arrangement adjacent thereto. Each anti-slip arrangement includes an actuator surface and non-parallel first and second abutment surfaces, and the actuator surface of the cutting tool is a surface of a clamp of the cutting tool. The cutting insert is mounted on the cutting tool via engagement of the base surfaces thereof and the clamp is operable to bias the actuator surfaces against each other and thereby force the first and second abutment surfaces against each other, for preventing slippage of the cutting insert along the tool's base surface.

Precise positioning of a cutting insert on a tool can allow for high precision cutting. However, cutting inserts are often subjected to high forces during cutting operations which can cause displacement or change of orientation of the cutting insert on a tool which holds them.
Maintaining a desired position may be assisted by biasing the cutting insert in a cutting direction. One such example is disclosed in U.S. Pat. No. 4,335,983. Notably, the side surfaces of the cutting insert constitute the abutment surfaces thereof.
By contrast, U.S. Pat. No. 6,536,996 discloses a cutting insert formed with non-parallel abutment surfaces adjacent to an insert base surface thereof.
It is an object of the present application to provide a new and improved anti-slip arrangement for maintaining a cutting insert position in a tool during a cutting operation.

Cutting tool having an anti-slip arrangement


A data storage temporarily stores an address conversion table associating the sector numbers with the physical addresses for each file. A conversion table memory allocator allocates a memory region for the address conversion table corresponding to a file when a request is made to open the file. A file system manager releases the allocated memory region at a given time. The file system manager stores sector numbers of one or multiple sectors constituting a file in each record of the address conversion table for which the memory region is allocated in sequence. Then, a memory control section searches the flash memory to acquire a physical address corresponding to a sector number in the each record of the address conversion table, and stores each acquired physical address in the corresponding record.

Recently, flash memories, a nonvolatile storage medium, are used with various electronic devices such as information processing devices including personal computers, cell-phones, and digital cameras. Also, various techniques for accessing a flash memory have been proposed in the prior art (for example, Patent Literature 1).
The memory card disclosed in Patent Literature 1 comprises a flash memory and a controller controlling the flash memory, wherein the controller can receives, from an external source, a command to write data in the direction that the address increases and detects the last writing position after the writing for the received command. The controller refers to a conversion table presenting the relationship between a sector and the corresponding physical address on a flash memory and searches for the physical address corresponding to the sector (logical data) on the flash memory.
Patent Literature 1: Unexamined Japanese Patent Application Kokai Publication No. 2006-40264.
However, the conversion table designed to make the physical address on a flash memory corresponding to a sector immediately known, as in the technique disclosed in the Patent Literature 1, grows in size as the flash memory size is increased. Therefore, it is not easy to use such a conversion table in a microcomputer system requiring a smaller memory or the like as in the prior art.


An engine generator including an engine, a generator and an air cleaner inside a case is disclosed. A wall section of the case is dented in the internal direction of the case to provide a filter accommodation section with a space for accommodating a filter. The space has an opening that opens toward the exterior of the case. The filter accommodation section has an outside-air intake port. The opening is blocked by an air cleaner cover.

An air-cooled multipurpose engine having an air cleaner on a fan cover that covers a cooling fan is already known as disclosed in, for example, Japanese Patent Application Laid-Open Publication No. 2000-213429.
An air-cleaner case of the air cleaner is integrally formed on the fan cover. A filter is placed inside the case via an opening in the air-cleaner case. The opening is covered by an air-cleaner cover.
When such an engine is used as, e.g., an engine generator, the engine, the cooling fan, the generator, the air cleaner, and the like must be accommodated inside an external case in order to ensure transportability or the like.
Ordinarily, a maintenance cover is provided for performing maintenance on the components inside the external case.
However, the air cleaner disclosed in the 2000-213429 publication has an air cleaner accommodated inside the air-cleaner case integrally formed with the fan cover, and the opening is covered by the air cleaner cover. Accordingly, when the air-cleaner cover is to be replaced, the maintenance cover disposed in the vicinity of the air-cleaner cover is first detached and the opening of the external case is exposed. Next, a worker inserts his hand into the external case through the opening in the external case, removes the air-cleaner cover from the air-cleaner case, and exposes the opening of the air-cleaner cover. The filter is then removed from the exposed opening and replaced with a new filter.
In other words, two covers, i.e., an air-cleaner cover and a maintenance cover, are required in the case that the air-cooled multipurpose engine is used as an engine generator or the like. Accordingly, time is required to perform maintenance on the air cleaner or to replace the filter, resulting in a hindrance to reducing the weight of the engine generator.


The charge assembly according to the present invention includes a charge member having a conductive support body on which a resistance adjusting layer and a surface layer covering the resistance adjusting layer are formed, to rotate a surface of the image support body to electrically charge the image support body, the surface layer having a static friction coefficient of 1.0 or more; and a cleaning member rotating the surface layer of the charge member in contact therewith to remove foreign particles on the surface layer.

1. Field of the Invention
The present invention relates to improvement and modification in a charge assembly having a charge member for charging an image support body, and an image formation apparatus including the same. In particular, the present invention relates to improvement and modification in a charge assembly suitable for an image formation apparatus such as a copying machine, a laser beam printer, and a facsimile machine.
2. Description of Related Art
There have been known image formation apparatuses of an electrophotographic type such as a copying machine, a laser beam printer, and a facsimile machine. Such an image formation apparatus includes an image support body supporting an electrostatic latent image; an exposure part exposing a surface of the image support body to write an electrostatic latent image on the surface; a developing part visualizing the electrostatic latent image formed on the surface of the image support body; a transfer part transferring the visualized image on a transfer body; a surface cleaning part cleaning the surface of the image support body; a lubricant coating member coating a lubricant on the surface of image support body for preventing the surface of the image support body from cracking; and a charge member electrically charging the surface of the image support body.
FIG. 1 is a pattern diagram showing an example of the above image formation apparatus. The operation thereof will be described with reference to the drawing. In FIG. 1, the number 11 represents a photoreceptor as an image support body to support an electrostatic latent image. Over the photoreceptor 11, the charge assembly 12 is provided for electrically charging the surface 11a thereof.
The charge assembly 12 includes a charge roller 12a as the charge member, and a cleaning member 12b to remove foreign particles on the surface layer by contacting the surface layer of the charge roller 12a. The charge roller 12a is disposed in contact with the surface 11a of the photoreceptor 11 or disposed close to the surface layer 11a but in no contact therewith.
An electrostatic latent image is written onto the surface 11a of the photoreceptor 11 by exposure light P from a not-shown exposure device.
A developing device 20 is provided forward in a rotational direction of the photoreceptor 11. The developing device 20 has a toner supporter 14 which functions as the developing part to attach a toner 15 to the electrostatic latent image on the photoreceptor 11 for visualization
Under the photoreceptor 11, a transfer roller 16 is provided as the transfer part to transfer a visualized image (toner image) formed on the surface 11a of the photoreceptor 11 onto a recording paper (recording medium) as the transfer body.
After the transfer processing, the toner remaining on the surface of the photoreceptor 11 is removed by a cleaning member 18 as the surface cleaning part to clean the surface of the image support body. Toner waste 19 is collected in a waste reservoir 21.
Then, in order to reduce friction due to electric discharge from the photoreceptor 11 and improve toner cleaning performance, a lubricant 22 is coated on the surface 11a of the photoreceptor 11 by a lubricant coating member 23 after the removal of the toner waste. The lubricant prevents the surface of the image support body from cracking.
Note that FIG. 1 omits showing components generally necessary for other photoelectric processes since they are not directly relevant to the present invention.
The image formation apparatus performs the image formation in the following steps:                (1) The surface 11a of the photoreceptor 11 is electrically charged to have a desired electric potential by the charge roller 12a;         (2) An electrostatic latent image corresponding to the desired image is formed on the surface 11a of the photoreceptor 11 by exposing the surface 11a with the exposure device;        (3) The developing device 20 attaches the toner 15 to the electrostatic latent image for visualization, thereby forming a toner image on the surface 11a of the photoreceptor 11;        (4) The transfer roller 16 transfers a toner image on the recording paper 17;        (5) The cleaning member 18 removes a toner 18 not transferred on the recording paper 17 and remaining on the surface 11a;         (6) The recording paper 17 on which the toner image has been transferred is conveyed to a not-shown fuser device. The fuser device fixes the toner on the recording paper 17 through heating and pressurization; and        (7) The lubricant 22 is coated on the surface 11a of the photoreceptor 11.
Desired images are repetitively formed on the recoding paper 17 by repeating the above steps (1) to (7).
In order to electrically charge the surface of the photoreceptor 11, there are two known electrification techniques, that is, contact electrification in which the charge roller 12a is made in contact with the surface 11a of the photoreceptor 11 (disclosed in Japanese Patent Gazette No. Hei 03-052058 and No. Hei 08-030915, etc.) and non-contact electrification in which the charge roller 12a is disposed close to the surface 11a of the photoreceptor 11 (disclosed in Japanese Patent Application Laid-Open Publication No. Hei 03-240076, No. 2001-312121, and No. 2005-91818). Both of the electrification techniques have the following problems.
(A) Problems in Contact Electrification
(a) In the contract electrification, the charge roller 12a need be an elastic body. The materials of which the charge roller 12a is made are leaked therefrom, attached to the surface 11a of the photoreceptor 11, and leaves a trace of the charge roller 12a thereon, causing an image to be defective.
(b) The remnant toner and toner components on the photoreceptor 11 are attached to the charge roller 12. Especially, the leakage from the materials of the charge roller 12a increases occurrence of the toner attachment, which causes a decrease in the electrification performance of the charge roller 12a and generation of defective images.
(c) Deterioration in the surface of the charge roller 12a due to the electric discharge further increases the occurrence of the attachment of the toner and toner components, which causes a decrease in the electrification performance of the charge roller 12a and generation of defective images.
(B) Problems in Non-Contact Electrification
In view of solving the problems in the contact electrification described in the above items (a) to (c), non-contact electrification has been proposed in which the charge roller 12a is disposed close to the 11a of the photoreceptor 11 (disclosed in Japanese Patent Application Laid-Open Publication No. Hei 03-240076, No. 2001-312121, and No. 2005-91818).
According to the non-contact electrification technique, the charge roller 12a and the photoreceptor 11 are configured to be in no contact with each other, so that it is able to solve the problems of the contact electrification technique, that is, the attachment of the materials of the charge roller 12a to the photoreceptor 11 and the attachment of the remnant toner and toner components on the photoreceptor 11 to the charge roller 12a.
Moreover, there is a similar technical member to the charge member according to the present invention for providing uniform electrification disclosed in Japanese Patent Application Laid-Open Publication No. Hei 10-161391 and No. Hei 11-149201.
However, the above member for the uniform electrification also has a problem that with application of both of a direct-current (DC) voltage and an alternating-current (AC) voltage, the attachments on the surface 11a of the photoreceptor 11 is reciprocatively flown between the charge roller 12a and the surface 11a of the photoreceptor 11, and attached to the surface of the charge roller 12a although they are in no contact with each other.
In particular, when the lubricant 22 made of fluorine resin as PTFE or metallic soap as zinc stearate is coated on the surface 11a of the photoreceptor 11 for the purpose of preventing the surface 11a from cracking and improving toner cleaning performance, organic compounds with low molecular weight such as the metallic soap are decomposed by the energy from the electric charge (corona discharge) to be attached and accumulated on the charge roller 12a over time.
Accumulation of the particles of the toner, toner external additive, and lubricant 22, and the decomposed particles of the lubricant 22 on the surface of charge roller 12a over time causes an increase in the resistance thereof, preventing occurrence of the electric discharge. Accordingly, a portion of the surface 11a which opposes to a portion of the charge roller 12a with the accumulated particles has a lower potential than the surrounding area. When it is imaged, dark lines will appear in the image on the recording paper 17.
The charge assembly has a cleaning member 12b to remove attachments from the surface of the charge roller 12a. However, there is a problem that the cleaning member 12b cannot remove all of the attached particles thereof.

Charge assembly and image formation apparatus including the same


In the manufacturing method of an array substrate for a planar display device, a first pattern is formed on a substrate by correcting in advance the size of the first pattern in view of an amount of deformation of the substrate. Then, the next pattern is formed on the substrate in conformity with the pattern formed in the preceding step.

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-085103, filed Mar. 24, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to a method of manufacturing an array substrate for display devices such as an active matrix type liquid crystal display device and an organic electroluminescence (EL) display device, particularly, to a method of manufacturing an array substrate using a polycrystalline silicon and a method of manufacturing a display device.
In recent years, a liquid crystal display device is widely used in a notebook type computer or various portable apparatuses because of its big merits such as a high image quality, a thin and lightweight structure, and a low power consumption. In this connection, keen attentions are paid to a further improvement in the performance and the manufacturing technology of the liquid crystal display device. Particularly, an active matrix type liquid crystal display device, in which a switching element such as a thin film transistor (TFT) is connected to each display pixel, attracts attentions because a large display screen can be obtained easily and the particular liquid crystal display device can be manufactured by the conventional semiconductor manufacturing technology. Also, the research and development of a TFT used in an array substrate of a liquid crystal display device are being made vigorously. Recently, a TFT using a polycrystalline silicon having a high field-effect mobility is being studied vigorously.
The array substrate of a liquid crystal display device equipped with such TFTs is manufactured as follows. In the first step, a semiconductor layer consisting of a polycrystalline silicon is formed on an insulating substrate such as a glass substrate. Then, a gate insulating film is formed in a manner to cover the semiconductor layer, followed by forming a first wiring layer (gate electrodes and gate wirings integral with the gate electrodes) on the gate insulating film.
In the next step, source regions and drain regions are formed by doping a large amount of phosphorus, boron or the like in the semiconductor layer by an ion implantation method, by using the first wiring layer itself or the resist film, used in forming the first wiring layer, as a mask.
Since the dopant as doped is not activated, a heat treatment is applied after the doping step so as to activate the dopant, thereby ensuring a desired low resistivity. The heat treatment is carried out at high temperatures, i.e., at 500 to 600xc2x0 C.
After the heat treatment, an interlayer insulating film is formed in a manner to cover the gate electrodes and the gate insulating film, followed by forming a contact hole in each regions of the gate insulating film and the interlayer insulating film which are positioned above the source regions and the drain regions.
Further, source electrodes and drain electrodes are formed as a second wiring layer on the interlayer insulating film. the source electrode is connected to each source region via the contact hole, and the drain electrode is connected to each drain region via the contact hole. Also, pixel electrodes are formed in parts on the interlayer insulating film except the TFT forming regions and connected to the respective source electrodes. Finally, a protective film is formed on the entire surface of the substrate, thereby preparing a desired TFT array substrate.
In the TFT described above, the semiconductor layer is formed of polycrystalline silicon and, thus, exhibits a high field-effect mobility, making it possible to enhance the driving capability of the liquid crystal and to miniaturize the individual TFT. As a result, where a liquid crystal display device is prepared by using the TFT array substrate described above, the aperture rate is improved so as to improve the brightness of the displayed image or to lower the power consumption.
Also, in the case of using a polycrystalline silicon, it is possible to obtain a high field-effect mobility, making it possible to form integrally a circuit such as a shift register for controlling the operation of the TFTs on the glass substrate by utilizing the foregoing semiconductor layer. In this case, it is unnecessary to provide separately an integrated circuit for driving the TFTs, and the external circuit can be simplified, with the result that it is possible to decrease the number of manufacturing steps of the entire liquid crystal display device and to lower the manufacturing cost.
However, in the manufacturing process of a polycrystalline silicon TFT array, the heat treatment is carried out at temperatures higher than that in the manufacturing process of an amorphous silicon TFT array in many cases. Particularly, the heat treatment after the impurity doping step is carried out at a high temperature in manufacturing a polycrystalline silicon TFT array, with the result that the glass substrate is thermally expanded or thermally shrunk greatly.
Under the circumstances, a glass substrate as used in an amorphous silicon TFT array substrate cannot be used in a polycrystalline silicon TFT array substrate, making it unavoidable to use an exclusive glass substrate having a higher durability in a polycrystalline silicon TFT array substrate.
However, even in the case of using the exclusive glass substrate in a polycrystalline silicon TFT array substrate, it is impossible to avoid the thermal expansion or thermal shrinkage of the glass substrate. Therefore, the finally prepared array substrate is expanded or shrunk relative to a counter substrate, though it is certainly possible to automatically correct the relative positional relationship among the light-exposed patterns by a light exposure machine in each photo engraving process (PEP) in which the light exposure, the development and the etching are carried out by using a photolithography, giving rise to the problem that it is difficult to assemble the array substrate accurately relative to the counter substrate.
It should also be noted that, in a PEP in which the automatic correction cannot be achieved by a light exposure machine, e.g., a collective light exposure step using a large mask, the patterning is performed without taking the expansion or shrinkage of the substrate into consideration, with the result that the formed pattern is deviated from the pattern formed in advance. Particularly, where contact holes are included in the pattern, the contact holes are deviated from desired positions, giving rise to a poor connection of the source electrodes, the drain electrodes, etc. and, thus, to a defective display such as a point defect.
The present invention has been contrived in consideration of the above circumstances and its object is to provide a method of manufacturing an array substrate and a method of manufacturing a display device, having a suppressed defective display such as a point defect and a high reliability while preventing the deviation of patterning due to deformation of the substrate.
According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for a planar display device, including a plurality of first wiring layers and a plurality of second wiring layers formed on a substrate and a plurality of pixels connected to the first and second wiring layers via thin film transistors, wherein each of the thin film transistors includes a semiconductor layer formed of polycrystalline silicon and a gate electrode formed on the semiconductor layer with a gate insulating film interposed therebetween, the method comprising:
a first pattern forming step of forming a first pattern on the substrate by correcting in advance the size of the first pattern in view of the amount of deformation of the substrate; and
a second pattern forming step of forming a second pattern on the substrate in conformity with the first pattern by a collective process.
According to the manufacturing method of the present invention defined as above, the pattern is corrected in the first pattern forming step in anticipation of the amount of deformation of the substrate taking place in a step such as a heat treating step, e.g., making it possible to form finally a pattern of a predetermined shape even if the substrate is deformed during the manufacturing steps. It follows that it is possible to prevent the occurrence of a defective display, making it possible to manufacture an array substrate of a high reliability with a high yield.
According to another aspect of the present invention, there is provided a method of manufacturing a display device including a plurality of pixels arranged in a matrix manner, each of the pixels having a first electrode provided on a substrate, a second electrode opposing the first electrode, and a light modulating layer provided between the first and second electrodes, the method comprising:
a first pattern forming step of forming a first pattern on the substrate by correcting in advance the size of the first pattern in view of an amount of deformation of the substrate; and
a second pattern forming step of forming a second pattern on the substrate in conformity with the first pattern by a collective process.
According to the method of the present invention for manufacturing a display device defined as above, the pattern is corrected in the first pattern forming step in anticipation of the amount of deformation of the substrate, making it possible to form finally a pattern of a predetermined shape even if the substrate is deformed in the manufacturing steps. It follows that it is possible to prevent the occurrence of a defective display, making it possible to manufacture an array substrate of a high reliability with a high yield. In addition, since the display device is assembled by using the array substrate defined in the present invention, a display device having a high assembling accuracy can be manufactured easily.
Additional objects and advantages of the present invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present invention. The objects and advantages of the present invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.

Method of manufacturing array substrate for display device and method of manufacturing display device


Methods, apparatus and systems for sharing information related to broadcast programs are described. One of the methods includes receiving data identifying at least a portion of a first broadcast of a program, receiving data identifying at least one recipient, and communicating information indicative of the identified at least a portion of the program to the at least one recipient. The method may also include identifying a subsequent broadcast of the program to the at least one recipient, and communicating data indicative of the subsequent broadcast of the program to the at least one recipient. Other aspects include systems, apparatus, and devices for sharing information related to broadcast programs.

Electronic devices such as mobile telephone handsets and other mobile devices may be configured to receive broadcasts of sports, entertainment, or informational multimedia programs. For example, audio and, or video data may be communicated via a broadband broadcast communications link to the electronic devices. Thus, a need exists for methods and apparatuses for enhancing a user experience and for and viewing broadcast media on such electronic devices.

Methods and apparatuses of user identification and notification of multimedia content


An image forming apparatus includes a plurality of process cartridges. Each process cartridge includes an image carrier configured to form an image intermediately, a drive transfer member engaged with the image carrier, a drive mechanism configured to drive to rotate the image carrier via the drive transfer member, a marking member mounted on the drive transfer member and configured to indicate a rotational position of the drive transfer member, a detector configured to detect the rotational position by detecting the marking member, and a balancer mounted on the drive transfer member configured to match a weighted center of the drive transfer member with a shaft center of the image carrier. A controller is configured to adjust rotational phases of the image carriers based on results detected by the detector.

1. Field of the Invention
The present invention relates to an image forming apparatus effectively producing quality color image without causing color slippage.
2. Discussion of the Background
A background color image forming apparatus generally includes a plurality of photosensitive drums as image carriers. It is known that there is a color slippage problem on a formed image due to a deviation of rotational speed shifts at each photosensitive drum. Each photosensitive drum is generally unified with a drive transfer member engaging with each other photosensitive drum and is driven by a driving force via the drive transfer members.
The deviation of rotational speed shifts is caused by an accuracy error and an eccentricity generated at an attachment process of the drive transfer member. Although this problem has been studied, no clear solution to solving this problem has yet been obtained. It has been proposed to adjust each phase of a rotational speed shift to a phase of a rotational speed shift of a drive transfer member so that an amount of color slippage is minimized by restraining the deterioration of image quality.
More specifically, a background method for adjusting the rotational speed shift is to adjust a phase of the each rotational speed shift within a predetermined minimum range. And the method includes the following procedure. At first, color slippage adjusting patterns are formed on intermediate carriers such as intermediate transfer belts and then are read by pattern detection apparatuses. The rotational speed shift and the amount of phase shift on each photosensitive drum axis are calculated.
Further, phase differences between the photosensitive drums are calculated until getting a result for achieving a minimum amount of color slippage. The result of the phase information is stored as profile data in a storage device, such as a rewritable nonvolatile memory. Then, phase relationships of the photosensitive drums are adjusted to follow the profile data calculated based on the phase information before an image forming process.
In the background image forming system, a base mark (marking) which shows a rotating position is arranged at each drive gear and a dedicated member of a photosensitive drum to adjust to follow the profile data. Marking detection sensors are arranged firmly at a main unit of the apparatus to detect the marking.
The markings of the photosensitive drums are detected by the marking detection sensors at every rotation. Then, differences of detection timing of the markings are determined. Based on the difference, each drive motor for driving each photosensitive drum is controlled to align the rotation phase to a phase of a photosensitive drum.
Namely, in this configuration, a detection signal is transmitted when a marking is passing through a detection zone during a rotation of each photosensitive drum. Then, the rotation phase is calculated from the timing differences of the transmitted signals. Then, each rotation phase is aligned by controlling the drive motor for each photosensitive drum in a predetermined manner to the profile data previously determined.
In this background configuration, the phase relationships between photosensitive drums are determined using the signals detected while each marking is passing through the marking detection sensor in accordance with the rotation of each photosensitive drum. For this reason, it may take a relatively long time to print a first page.
For example, when a position of the marking on the drive transfer member is in a position where it is just passing over the marking detection sensor at a start timing of a phase detection procedure, it is needed to wait until the marking rotates almost one more turn and passes through the marking detection sensor. This causes a time lag for detection and makes a delay for the first page printing.
To solve this time lag problem, it has been proposed to make a marking larger and to place a plurality of the markings, to detect the markings more efficiently and determine the rotation position in a shorter time. More specifically, it has been proposed to arrange a longer marking in a rotating direction and a plurality of markings that have different lengths on a circumference.

Image forming apparatus effectively producing quality color image without causing color slippage


Provided is a configuration method and device for timing advance information. The method comprises: a first transmission node indicates, through a number I of signaling, timing advance information corresponding to a number N of transmission links from a second transmission node to a number M of first transmission nodes, where I, M and N are all integers greater than or equal to 1.

With the opening of a fifth generation of mobile communications, the adoption of multi-beam transmission between a terminal and a single station or the adoption of multi-beam transmission between the terminal and multiple stations has become the core of increasing user and system capacity in a next generation of wireless communication systems. At the same time, the coexistence and concurrency of a traditional enhanced mobile bandwidth (referred to as eMBB) service and other internet of things (referred to as IoT) related services (such as ultra-high reliability and ultra-low latency communication (referred to as URLLC)) have also become the highlight of 5G communication.
However, the above-described features also pose new challenges to the timing advance of transmission links between existing communication nodes. Specifically, for uplink multi-link/multi-beam transmission (specifically, one or more uplink transmissions are transmitted between the terminal and the single station by adopting multiple beams, or different uplink transmissions are transmitted between the terminal and the multiple stations by adopting multiple beams), the absolute time delay difference between transmissions has a relatively large range due to different paths experienced by link transmissions, a traditional method of configuring a single timing advance (referred to as TA) information for uplink transmission can no longer deal with multiple transmissions. In addition, since other IoT-related services (e.g., URLLC) and eMBB scheduling will likely coexist in future communications, but the transmission configuration adopted by different services, such as Cyclic Prefix (CP) length and subcarrier spacing, may be different, and the performance impact of sharing the same TA information among different services on low latency and high reliability services also needs to be further addressed. These become important issues in communication systems that need to be addressed.
No effective scheme has been proposed to address low transmission performance caused by using single timing advance (TA) information in multi-beam/multi-station transmission.

Configuration method and device for timing advance information


A wall-mounted pipe clamp installation and a mounting kit therefor. The kit comprises an elongated wall bracket having its upper and bottom edges in the form of downwardly and upwardly facing and opposing channels respectively and a pair of pipe end receiving sockets slidably mountable in the bracket. Each socket has a base with exposed upper and lower edges spaced to fit in bracket supported relationship in the channels and a projecting socket formation for receiving a pipe end therein. Each socket formation is preferably provided with a set screw to secure therein the free pipe end of each pipe clamp of a pipe clamp installation.

This invention relates, generally, to a wall mounted pipe clamp installation and to kits for making the same.
Pipe clamps are well known, readily available tools. They are used both professionally and by do-it-yourself persons in order to accomplish a wide variety of clamping operations wherein relatively large workpieces need to be secured together for significant periods of time. In workshops space is often at a premium both for setting up a clamping operation and for maintaining it while waiting for glue to set or for another operation to be performed thereon.
According to the present invention, a wall mounted pipe clamp installation is provided, including a kit for making the same, which permits the use of a free or unused wall space which is often available. Such an installation may be used in performing various clamping operations wherein pipe clamps are advantageously supported in a cantilevered arrangement from a wall at a convenient working height.


In the manufacture of a semiconductor device, there are provided a method that enables reduction in the number of manufacturing steps thereof and a structure for realizing the method, to thereby realize improvement in yield and reduction in manufacturing cost. Wirings (source wiring, drain wiring, and the like), which are respectively formed in a row direction and a column direction on an element substrate, are formed of the same conductive film. In this case, one of the respective wirings in the row direction and the column direction is discontinuously formed at a portion where the wirings intersect with each other, and an insulating film is formed on the wirings. Thereafter, a connection wiring for connecting discontinuous wirings is formed of the same film as that for forming an electrode provided on the insulating film. As a result, a continuous wiring is formed.

1. Field of the Invention
The present invention relates to a semiconductor device having a circuit composed of a thin film transistor (hereinafter referred to as TFT) and a manufacturing method thereof. More specifically, electro-optical devices typified by liquid crystal display devices and light emitting devices having light emitting elements and also, electrical equipment in which such devices are mounted as parts will be included in this category.
2. Description of the Related Art
In recent years, techniques of forming thin film transistors (TFTs) by using semiconductor films (of about several to several hundreds of nm in thickness) formed on a substrate having an insulating surface have been attracting attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and especially, the development thereof as switching elements for display devices is being hastened.
Note that as display devices, liquid crystal display devices, light emitting devices and the like are known. In such display devices, driving methods such as passive matrix driving (simple matrix type) and active matrix driving (active matrix type) can be used. However, in the case where the pixel density is increased, the active matrix type in which a switch is provided for each pixel (or one dot) is considered to be advantageous in that a low voltage driving can be conducted.
In an active matrix liquid crystal display device, a display pattern is formed on a screen by driving pixel electrodes arranged in matrix. To be specific, a voltage is applied between a selected pixel electrode and an opposing electrode thereof, whereby optical modulation of a liquid crystal layer arranged between the pixel electrode and the opposing electrode is performed. Thus, the optical modulation is recognized as the display pattern by an observer.
Further, an active matrix light emitting device that uses organic electroluminescence has, in each pixel thereof, at least a TFT that functions as a switching element and a TFT that supplies a current to a light emitting element formed by sandwiching an organic compound layer between a pair of electrodes, and utilizes light emission obtained through recombination of carriers in the organic compound layer. Note that the light emitting device is expected to be applied to next-generation flat panel displays because of its features such as thinness and lightness, high-speed responsibility, and direct low-voltage drive. In particular, the light emitting device is considered to hold its superiority in a point that the device has a wider angle of view and excellent visibility compared with a conventional liquid crystal display device.
In a pixel structure in a liquid crystal display device, three of a gate wiring (scanning line), a source wiring (signal line), and a capacitor wiring each are patterned into a line shape. In this case, one of the source wiring and the gate wiring is arranged in a row direction while the other is arranged in a column direction, and plural pixels are formed in a region surrounded by both the wirings. Further, in order that both the wirings may not contact with each other at a portion where the wirings intersect with each other, the gate wiring and the source wiring are respectively comprised of conductive films formed at different layers through an insulating film. That is, there is provided such a structure in which the insulating film is formed between one of the source wiring and the gate wiring, which is formed of a first conductive film, and the other of the source wiring and the gate wiring, which is formed of a second conductive film.
On the other hand, in a pixel structure in a light emitting device, three of a gate wiring (scanning line), a source wiring (signal line), and a current supply line each are patterned into a line shape. In this case, one of the source wiring and current supply line and the gate wiring is arranged in a row direction while the other is arranged in a column direction, and plural pixels are formed in a region surrounded by the source wiring, the current supply line and the gate wiring. Further, in order that both the wirings may not contact with each other at a portion where the wirings intersect with each other, the gate wiring and the source wiring and current supply line are respectively comprised of conductive films formed at different layers through an insulating film. That is, there is provided such a structure in which the insulating film is formed between one of the source wiring and current supply line and the gate wiring, which is formed of a first conductive film, and the other of the source wiring and current supply line and the gate wiring, which is formed of a second conductive film.
However, application of such active matrix display devices (typically, liquid crystal display device and light emitting device) has been expanding, and the needs for high fineness, a high aperture ratio, and high reliability have been growing along with an increase in surface area of a screen. As a result, the needs for improvement in productivity and reduction in cost also have been growing.

Conductive film as the connector for thin film display device

Semiconductor Energy Laboratory Co., Ltd.


A motor vehicle fuel tank comprising a shell and inside the shell at least one add-on element such as a valve. Said shell presents a portion in relief and an add-on element is connected to the shell by means of an intermediate element having at least one elastically-deformable portion arranged to be connected after elastic deformation in or on said portion in relief, so as to hold the intermediate element to the shell. The add-on element is arranged to be connected to the intermediate element in such a manner as to prevent the elastically-deformable portion of the intermediate element from being subjected to inverse elastic deformation enabling it to become disengaged from said portion in relief.

It is known to make a fuel tank with a shell of thermoplastic material that is blown, thermoformed, or rotormolded, for example.
Such a shell can include a layer that forms a barrier against hydrocarbons so as to limit hydrocarbon losses by diffusion through the shell.
Such a barrier-forming layer can be made of ethylene-vinyl alcohol copolymer (EVOH).
There exists a need to secure elements, such as a valve for venting air or degassing, for example, on the inside face of the shell of the tank, regardless of whether or not the shell includes a barrier-forming layer.
Where appropriate, this should be done without damaging the barrier-forming layer.
In addition, the reliability of such a connection must be guaranteed throughout the lifetime of the tank, in spite of the vibrations to which the tank is subjected and any dimensional variations to which the shell might be subjected in particular under the effect of the thermoplastic material swelling on contact with hydrocarbons.
The present invention seeks to provide a reliable connection.
The invention achieves this by a novel motor vehicle fuel tank comprising a shell, and inside the shell at least one add-on element such as a valve, wherein the shell presents a portion in relief, wherein the add-on element is connected to the shell by means of an intermediate element including at least one elastically-deformable portion arranged to engage, after being elastically-deformed, in or on said portion in relief so as to hold the intermediate element to the shell, and wherein the add-on element is arranged so as to be connected to the intermediate element in such a manner as to prevent the elastically-deformable portion of the intermediate element from being subjected to inverse elastic deformation enabling it to become disengaged from said portion in relief.
The elastically-deformable portion of the intermediate element is held in a predetermined position when the add-on element is secured to the intermediate element, and while held in this way it prevents any displacement of the intermediate element in a direction leading to disengagement of the portion in relief of the shell of the tank.
The invention thus makes it possible to provide a locking system that is effective on securing the intermediate element in or on the portion in relief of the shell of the tank, and consequently of ensuring that the add-on element is held in stable manner.
In a preferred embodiment, it defines a housing in which the elastically-deformable portion of the intermediate element is suitable for being engaged.
Still in a particular embodiment, the above-mentioned housing communicates with a lateral passage enabling a lateral extension of the intermediate element or of the add-on element to be received.
This makes it possible to establish a keying system to guarantee that the add-on element is in a predetermined orientation once it has been secured to the shell of the tank.
In addition, where appropriate, the tank can be made more compact by reducing the axial extent of the add-on element, since the above-mentioned passage makes it possible to bring the portion of the add-on element constituting the above-mentioned lateral extension into the vicinity of the shell of the tank.
This embodiment also makes it possible to secure the add-on element substantially at the highest point of the tank, which is particularly advantageous when the add-on element is an air vent or degassing valve.
In a particular embodiment, the lateral extension in question is constituted by an endpiece for connection to a pipe.
The passage receiving the endpiece is then advantageously defined by walls that are substantially parallel to the axis thereof.
Still in a particular embodiment, the opening of the housing through which the intermediate element is inserted is not circularly-symmetrical, thus making it possible to secure the intermediate element in a predetermined angular position once it is engaged in the housing. In a variant, said opening can be circularly-symmetrical.
In a particular embodiment, the intermediate element is arranged to snap-fasten in the housing in the axial direction thereof.
The intermediate element can thus have elastically-deformable fastening tabs suitable for snap-fastening in the above-mentioned housing.
The intermediate element can thus be secured to the shell of the tank in a manner that is simple and fast.
In a particular embodiment, the intermediate element has at least two resilient tabs leaving a gap between them and arranged so as to snap-fasten in the housing formed by the shell of the tank, the add-on element including a locking portion suitable for engaging in said gap in such a manner as to prevent the tabs from moving towards each other and disengaging from the housing.
This embodiment is advantageous because the shell of the tank is likely to be subjected to variations in its dimensions over its lifetime.
In the absence of the above-mentioned locking portion, there would be a risk of the tabs disengaging from the housing in which they have been inserted.
In a particular embodiment, the intermediate element has two pairs of resilient tabs, each pair being disposed facing the other, the tabs in a given pair being disposed in such a manner as to come into contact with the same face of the housing.
In a variant, the intermediate element extends along a longitudinal axis and has a plurality of resilient tabs disposed at equal angular intervals around said longitudinal axis.
Still in a particular embodiment, the housing has an axial section of dovetail shape and the tabs are of flattened shape being angled outwards so as to fit substantially to the shape of the inside faces of the housing.
This configuration makes it possible to have a large bearing area for the resilient tabs and the inside faces of the housing, thereby improving the reliability of the connection.
Advantageously, the add-on element is arranged to snap-fasten on the intermediate element.
In a particular embodiment, the intermediate element has a tubular body with an elastically-deformable portion at one end for engaging in the above-mentioned housing, and the add-on element is arranged to connect to the inside of said tubular body.
The intermediate element and the add-on element preferably include portions in relief arranged to co-operate so as to enable the add-on element to be preassembled in the intermediate element before the intermediate element is connected to the shell of the tank.
Advantageously, the tubular body of the intermediate element has recesses and the add-on element has teeth suitable for snap-fastening in the recesses.
Preferably, the intermediate element has a first set of recesses disposed in such a manner as to enable the add-on element to be held in a first position relative to the intermediate element suitable for enabling the intermediate element to be put into place on the shell of the tank, and a second set of recesses enabling the add-on element to be held in the intermediate element in a second position relative to the intermediate element, said second position of the add-on element preventing the intermediate element from becoming detached from the shell of the tank.
This enables the add-on element to be connected in simple and low cost manner inside the intermediate element.
In a particular embodiment, the add-on element has an endpiece and the tubular body of the intermediate element has a window for passing said endpiece.
Advantageously, the window is set back from the end of the tubular body situated remote from the elastically-deformable portion.
Thus, the intermediate element retains good mechanical strength because of the strip of material situated between the above-mentioned window and the end of the tubular body.
In a particular embodiment, the shell is made by blowing a thermoplastic material. Advantageously, the shell then has at least one layer that forms a barrier against hydrocarbons.
In a particular. embodiment, the portion in relief for connecting the intermediate element is obtained by means of a predetermined shape being given to the blow mold.
In a variant, the portion in relief is obtained by overmolding an insert.
This embodiment is advantageous since the insert can form reinforcement opposing possible changes in the dimensions of the shell.
Also in a variant, the portion in relief can be obtained by fitting a fastener on the surface of the shell, which fastener can be heat-sealed to said surface.
By way of example, the add-on element is constituted by a valve or a check valve.
The invention also provides a method of manufacturing a motor vehicle fuel tank, the method comprising the following steps:
a) making a shell by shaping a plastics material, in particular by blowing, thermoforming, rotomolding, or injection molding a thermoplastic material;
b) making a portion in relief on the shell, during or after formation of the shell;
c) connecting an intermediate element to said portion in relief, the intermediate element being provided with at least one elastically-deformable portion arranged to engage by resilient deformation in or on said portion in relief so as to hold the intermediate element to the shell; and
d) connecting an add-on element to the shell of the tank at the same time as the intermediate element or thereafter, said add-on element being suitable for preventing the elastically-deformable portion of the intermediate element from moving in such a manner as to enable it to become disengaged from said portion in relief.
After the intermediate element has been put into place on its own on the shell of the tank, the add-on element can be connected to the intermediate element to prevent the elastically-deformable portion of the intermediate element moving in such a way as to enable it to disengage from the portion in relief.
In a variant, the add-on element can be preassembled to the intermediate element before the intermediate element is put into place on the portion in relief, the intermediate element can then be connected to the portion in relief, and finally the add-on element can be moved relative to the intermediate element in such a manner that the add-on element prevents the elastically-deformable portion of the intermediate element from moving in such a way as to enable it to disengage from the portion in relief.


A method for assessing a process of an organization is provided. First, information concerning the organization and the process is acquired, such as from a set of questionnaires, interviews and/or document reviews. Then, a plurality of preliminary findings are developed based upon the information. Each of the developed preliminary findings has an associated characterization of either a strength or a weakness. Next, a conclusion associated with each preliminary finding is voted for electronically, where the conclusion is either an agreement with the preliminary finding or a disagreement with the preliminary finding. A plurality of final findings are then developed based upon the vote for each conclusion. Each final finding also has a characterization of either a strength or a weakness.

In many industries today capability models (CMs) are used to assist organizations in developing their assets, including people, process and technology assets, to improve long-term organization performance. For example, the Software Engineering Institute (SEI) of Carnegie Mellon University and the Electronic Industries Alliance (EIA) have developed various CMs, including those for software, systems engineering and integrated product development. These CMs are typically used to assist organizations in the evolution of a process from an ad hoc, chaotic process to a mature, disciplined process. According to one CM, the Systems Engineering Capability Model (EIA-731) developed by EIA, a systems engineering process can be placed into one of five capability levels indicative of the level of development of the process. Increasing in maturity and including a default initial level, the capability levels consist of: performed, managed, defined, measured and optimizing.
To assess a process of an organization utilizing a particular CM, a sponsor typically sponsors an appraisal, or assessment, of the process, which is generally broken down into focus, best practice or process areas. Organizations typically use assessments to identify specific areas for improvement based on known, general areas of deficiency from within the process, and to help make the decisions required to effectuate change in the process and/or organization. To conduct an assessment, an assessment team typically utilizes a relevant CM in conjunction with an assessment method, such as the Systems Engineering Capability Model Appraisal Method developed by EIA.
Referring to FIG. 1, , conventional assessment methods generally proceed through several individual and group exercises, beginning with acquiring information about the process and the organization, and analyzing the information to develop an initial set of preliminary findings about the process, or specifically the identified focus areas within the process (blocks 20, 30, 40 and 50). The top preliminary findings are then presented to members of the organization participating in the assessment (i.e., the organization participants) for comments (block 60). Whereas the number of top preliminary findings presented can vary, the number is typically on the order of forty or more preliminary findings. From the comments, the top preliminary findings are then revised into final findings that are thereafter presented to the organization (blocks 70 and 80). After presenting the final findings, the assessment team typically presents a set of recommendations to improve the process (block 90). Whereas conventional assessment methods can provide an adequate assessment of the process of an organization, they have drawbacks. Conventional assessments are generally unpredictable due to variations in the training and experience of the organization participants and the assessment team. Typically, conventional assessments proceed through the several group exercises to arrive at a consensus with respect to developing the initial and final findings, generally with all or at least a majority agreement among members of the assessment team required for a piece of information to be made a preliminary finding, or a preliminary finding to be made a final finding. The nature of developing the final findings from difficult group exercises can further exploit the variations among organization participants and assessment teams, even though the exercises often involve checks on accuracy, corroboration, validation, and involve writing and rewriting by the assessment team and the organization participants.
Additionally, because of the difficult group exercises involved and the time required to arrive at a consensus with respect to developing the initial and final findings, conventional assessment methods can last for an unnecessarily long period of time and can result in inaccurate assessments. Conventional assessments typically require time commitments on the order of 500-1000 hours over a two or more week period, and can include group exercises that can last extended periods of time as members of the assessment team (as well as the organization participants in the case of providing comments regarding the top draft findings) discuss and re-discuss specific pieces of information and/or findings. In this regard, Table 1 illustrates a typical time frame to complete each step of a conventional assessment.
TABLE 1Time RequiredAssessment Stepto CompleteFill Out Questionnaire1DayAnalyze Questionnaire1DayReviewing Documents2DaysConducting Interviews2DaysDeveloping Draft Findings2DaysPresenting Draft Findings½DayRevising Draft Findings1DayPresenting Final Findings½DayProviding Recommendations1DayAssessment Complete:11DaysBecause of the unnecessarily long periods of time these group exercises can require, the tendency increases for members of the assessment team and/or the organization participants to halfheartedly acquiesce on particular issues of contention in an effort to end the group exercise. Such acquiescence increases the likelihood of inaccurate assessments as the agreed upon result of the issue can be inaccurate.

Method and computer program product for assessing a process of an organization


The present invention relates generally to a process that helps alleviate the pH gradient between anode and cathode compartments in any biological fuel cell or electrolytic cell configuration in which a pH gradient between anode and cathode is limiting the voltage efficiency. By providing acid to the cathode compartment in the form of CO2, the pH gradient is reduced and voltage efficiency and power output are increased. In one embodiment, carbon dioxide produced in the anode chamber is recycled to the cathode chamber.

1. Field of the Invention
The present invention relates generally to fuel cells. More particularly, it concerns improving the performance of biological fuel cells by reducing the pH gradient between the cathode and anode compartments.
2. Description of Related Art
Biological fuel cells (BFCs) are widely researched today as a means to produce combustionless electrical energy from a wide variety of organic compounds present in water. BFCs can contain either an anode and cathode, in addition to a biological component. The biological component can either be an enzyme or a full cell (e.g., bacterium, microbe, algae, etc.). Chemical fuel cells consume hydrogen (H2) and simple organic compounds (e.g., methane and methanol) by using precious-metal catalysts, usually platinum, and relatively high temperatures. BFCs use microorganism and/or enzymes as the catalysts and are capable of oxidizing many complex organic compounds, as well as simple organic molecules, present in water (Moon et al. 2006, Torres et al. 2007, Topcagic et al. 2006, Bullen et al. 2006). This capability of BFCs opens up the possibility of producing electrical energy directly from biomass feed stocks that are renewable and carbon-neutral fuels (Rabaey et al. 2005, Davis et al. 2007, Rittmann 2008).
All fuel cells have certain common features: (1) an electron donor (the fuel) is oxidized at the anode, which is a conductive solid that accepts the electrons from the donor; (2) a catalyst is needed to carry out the oxidation at the anode; (3) the electrons move through an electrical circuit from the anode to the cathode, which is another conductive solid; (4) at the cathode, the electrons are added to an electron acceptor, usually oxygen (O2); and (5) either protons (H+) move separately from the anode to the cathode or hydroxide ions (OH−) move from the cathode to the anode to maintain electroneutrality in the anode compartment. Failure to transfer the H+ ions from the anode compartment or OH− ions to the anode compartment can result in acidification of the anode compartment and a pH gradient between the compartments.
In chemical proton exchange membrane fuel cells (PEMFCs), an acidic pH condition (i.e., high concentration of H+ ions and a low pH) can facilitate the transport of protons that is required between anode and cathode, as described by the following reactions:Anodic PEMFC reaction: ½H2→H++e−Cathodic PEMFC reaction: ¼O2+H++e−→½H2OHowever, the use of microbes or other biological catalysts in the anodic compartment of a BFC normally requires a near-neutral pH (Bullen et al. 2006, Torres et al. 2008). The low proton concentration in the anodic compartment (0.1 μM at pH 7) contrasts with the relatively high concentration of other ionic components of biological media (buffers, salts in mM range), which are often needed to maintain the operation of BFC biological components. These high concentrations result in a limitation of proton transport between the anode and cathode compartments. To maintain electroneutrality, other ions are transported between the compartments (Rozendal et al. 2006, Chae et al. 2008). The result is a pH gradient, especially at high current densities, in which the anode compartment pH decreases and the cathode compartment pH increases (Gil et al. 2003). The practical effect of the pH gradient is a drop in voltage efficiency, which consequently decreases power generation. In microbial fuel cells, this pH difference was calculated by Rozendal et al. (2007) to be more than 4.4 pH units, which resulted in a potential loss of more than 0.26 V, or approximately 20% loss in available energy. Thus, there is a need for techniques for reducing the pH gradient between the cathode and anode compartments in biological fuel cells.

Bicarbonate and carbonate as hydroxide carriers in a biological fuel cell

Arizona Board of Regents for and on Behalf of Arizona State University


A method for manufacturing a circuit board, includes: stacking a first peelable film on a second peelable film, and disposing fluffy carbon nanotubes between the first peelable film and the second peelable film, thereby obtaining a carbon nanotube layer; pressing the first peelable film, the carbon nanotube layer, and the second peelable film to compact the fluffy carbon nanotubes, thereby obtaining a thermal conductive layer; removing the first peelable film, and disposing a first adhesive layer, a first dielectric layer, and a first circuit layer on a side of the thermal conductive layer away from the second peelable film; removing the second peelable film, and disposing a second adhesive layer, a second dielectric layer, and a second circuit layer on a side of the thermal conductive layer away from the first adhesive layer; mounting an electronic component on the first circuit layer.

Circuit boards may include circuit substrates and electronic components mounted on the circuit substrates. The number of the electronic components that a single circuit substrate needs to accommodate is increased because the electronic devices are becoming more multifunctional. However, electronic components generate heat when working, the circuit substrate may be deformed due to excessive heat and the electronic components may be damaged if the heat cannot be dissipated in time.

Method for manufacturing circuit board with heat dissipation function

QING DING PRECISION ELECTRONICS (HUAIAN) CO., LTD


The present invention relates to an identification mark portion and fabricating method thereof, more particularly, to an identification mark portion introduced in a liquid crystal display panel and a fabricating method thereof, which minimizes the error in verifying an ID of a pad by preventing at least two insulating layers from overlapping each other over the upper part of the pad. The present invention includes an insulating substrate, an ID mark pad including an ID mark on the insulating substrate, and a first insulating layer and a second insulating layer on the insulating substrate wherein the first and second insulating layers expose the ID mark in the ID mark pad. In another aspect, the present invention includes the steps of forming an ID mark pad including an ID mark on an insulating substrate, and forming a first and a second insulating layer which expose the ID mark in the ID mark pad.

1. Field of the Invention
The present invention relates to a method of fabricating a liquid crystal display panel, and more particularly, the present invention relates to a method of fabricating an identification mark portion on a liquid crystal display panel.
2. Discussion of the Related Art
A liquid crystal display (hereinafter abbreviated LCD) panel is fabricated with an identification (hereinafter abbreviated ID) mark as well as with LCD device patterns.
FIG. 1 shows a schematic plan view showing an LCD panel having an ID mark portion. Referring to FIG. 1, a glass substrate 1 has a device pattern portion 3 and a peripheral portion 2 surrounding the device pattern portion. The device pattern portion includes a matrix array area portion 3A and a blank portion 3B. The blank portion 3B contains an ID mark portion 4.
FIG. 2 shows a layout of an ID mark portion 4 of an LCD panel, and FIG. 3 shows a cross-sectional view of the ID mark portion 4 taken along the cross-section line I–I′ in FIG. 2.
Referring to FIG. 2, in the ID mark portion 4, an ID mark pad 20 containing an ID mark 21, is formed. The ID mark pad 20 has the ID mark formed thereon by removing portions of a conductive layer to transcribe the ID mark shape. The conductive layer provided for an ID mark pad 20 in the LCD panel is patterned, as shown in the drawing, in a predetermined form such as a rectangle.
Referring to FIG. 3, a lower insulating layer 210 is overlapped with an upper insulating layer 220 in the upper part of the ID mark pad 20. The lower insulating layer 210 and upper insulating layer 220 are a gate insulating layer and a passivation layer, respectively, in the LCD panel having a bottom gate typed thin film transistor (hereinafter abbreviated TFT). The upper and lower insulating layers are formed with insulating materials such as silicon oxide and silicon nitride.
As mentioned in the above explanation, the related art includes the lower and upper insulating layers constituting two layers over the ID mark pad. Unfortunately, opaqueness of the overlapped insulating layers results in difficulty in recognizing the ID mark. Specifically, the insulating layers have poor light permeability since the insulating layers consist of at least two layers, and the resultant diffusion, refraction, and/or reflection lower the reliability of recognizing the ID mark.

This patent is subject to a terminal disclaimer.

Identification mark portion in liquid crystal display panel and fabricating method thereof


A wearable self-defense apparatus having a body portion configured to be worn on or around a body part of a user includes a high voltage generator configured to generate high voltage electricity for disabling an attacker, a high voltage transmitter electrically coupled to the high voltage generator, a controller configured to control one or more operations of the high voltage generator and a gesture detector operationally coupled to the controller. The gesture detector signals the controller to control the operations of the high voltage generator upon detecting one or more gestures of the user using the body part attached with the wearable self-defense apparatus. Upon receiving the signal from the gesture detector, the controller triggers the high voltage generator to generate high voltage electricity. The high voltage electricity thus generated is transmitted to a target using the high voltage transmitter for temporarily disabling the target.

Various non-lethal self-defense devices exist in the prior art. Most of the existing self-defense devices make use of electricity to temporarily disable an assailant. One such example of such self-defense device is a stun gun, which when activated, transmits high voltage electricity to the body of the target through a set of electrodes connected to the stun gun. Some other self-defense devices available in the market are in form of a flashlight, which is capable of generating and transferring the high voltage electricity to the target upon activated by the user. However, all such self-defense devices are to be carried by the user in their carry bags or to be attached to a wearable holder. When needed, the user must reach for the self-defense device from the stored place and activate the device pointing the target. Sometimes, when a user carrying a self-defense device faces an assailant there might not be enough time left for the user to reach for the self-defense device and point towards the assailant to disable using high voltage electricity generated by the device. This leaves the user, especially women, vulnerable to such attacks even though they carry such self-defense devices.
The above said drawbacks associated with the use of existing self-defense devices are somewhat solved by the development of wearable self-defense devices. Such wearable self-defense devices are available in various shapes and designs and the user needs to wear the device all the time to protect themselves from getting attacked. Most of the existing wearable self-defense devices are difficult to be worn by the user for long periods and are not aesthetically pleasing. Further, these wearable self-defense devices require the users to activate the device, when in need, by pressing an actuator or a button on the device using a hand of the user. However, such as actuation method sometimes would not work if the attacker already sees the movement by the user to activate the self-defense device.
Hence, there is a need for a wearable self-defense device that would solve the problems and drawbacks associated with the existing self-defense devices as discussed above. The needed wearable self-defense device would also be comfortable for the wearer and aesthetically pleasing. Further, the needed wearable self-defense device would allow the users to activate, when in need, in a short time to disable the attacker.

Wearable self defense apparatus and method of self defense


Methods of fabricating multilayer circuits are presented. In accordance with the present invention, a plurality of circuit layers are stacked, one on top of the other. At least one of the circuit layers comprise a substrate composed of a polymeric material capable of undergoing bonding such as a fluoropolymeric based substrate having vias therethrough and a circuit comprised of a layer of suitable conductive material. A fusible conductive bonding material (e.g., solder) or a noble metal is applied wherever electrical connections are desired. At least one other of the circuit layers comprises a cofired multilayer ceramic circuit having vias and circuits comprised of a layer of suitable conductive material with a fusible conductive bonding material (e.g., solder) or a noble metal applied wherever electrical connections are desired. Once stacked the circuits are subjected to lamination under heat and pressure to adhere each polymeric substrate to an adjacent ceramic substrate and to diffuse the noble metal or fuse the solder layers together to form an integral multilayer circuit having solid conductive interconnects.

Multilayer circuits are well known and comprise a plurality of stacked substrate/circuit trace assemblies with interconnections between selected locations on the spaced circuit traces. Conventional manufacturing techniques for multilayer circuits generally do not yield multiple levels of interconnect. This limits the circuit density and the number of substrates. When high density, multiple interconnect levels are required, step intensive sequential process techniques are usually utilized. Such processing can drastically reduce yields.
U.S. Pat. No. 4,788,766 attempts to overcome these problems. This prior art patent discloses a method wherein a multilayer assembly is made up of a number of individual circuit boards and each board has conductive layers formed on opposing surfaces. The substrate is a dielectric material which insulates the conductive layers. Via holes are formed through the first conductive layer, the substrate and the second conductive layer at various locations. An outer conductive material, such as copper, is applied over the first and second conductive bonding layers and onto the side walls of the holes. A conductive bonding material is then deposited onto the outer conductive material in the areas around the holes. Once the individual boards have been fabricated, they are stacked in a predetermined order and orientation with a suitable low temperature dielectric bonding ply (meaning that the bonding ply has a lower softening temperature than the circuit substrate material) positioned between each pair of layers. The dielectric bonding ply requires registered apertures therethrough which correspond to areas where the conductive layers of one substrate is to make an electrically conductive connection with the conductive layer of an adjacent substrate. Thus, the dielectric bonding ply integrally bonds adjacent boards together while providing electrical isolation and/or electrical connections between conductive layers of different boards. The assembly of boards is then subjected to a cycle of heat and pressure to effect a bond between the various board layers.
While the method of U.S. Pat. No. 4,788,766 overcomes some of the problems in the prior art, this prior art method has certain disadvantages including the requirement for a substrate which has a melting temperature above the melting temperature of the bonding ply. In other words, the prior patent necessitates the use of a low temperature bond ply which limits the thermal rating of the multilayer circuit. In addition, this prior method necessitates registered apertures in the bonding ply (leading to alignment problems) and is limited to multilayer circuits having plated through holes.
U.S. Pat. No. 5,046,238, assigned to the assignee hereof and incorporated herein by reference, attempts to overcome these problems. This prior art patent discloses a method wherein a plurality of circuit layers comprised of a dielectric substrate having a circuit formed thereon are stacked, one on top of the other. The dielectric substrate is composed of a polymeric material capable of undergoing fusion bonding such as a fluoropolymeric based substrate. Fusible conductive bonding material (e.g., solder) is applied on selected exposed circuit traces (prior to the stacking step) whereupon the entire stack is subjected to lamination under heat and pressure to simultaneously fuse all of the substrate and conductive layers together to form an integral multilayer circuit having solid conductive interconnects.
In the first embodiment of U.S. Pat. No. 5,046,238, the discrete circuit layers are each prepared by (1) forming traces and pads on a removable mandrel; (2) laminating a layer of dielectric to the circuit and mandrel; (3) forming an access opening at selected locations through the dielectric layer (using laser, plasma, ion etch or mechanical drilling techniques) to expose selected circuit locations; (4) forming conductive posts in the access openings to a level below the top of the access openings; and (5) providing a fusible conductive material in the access opening. Thereafter, a stack-up is made of a plurality of these discrete circuit layers so that the exposed fusible conductive material contacts selected locations on an adjacent circuit. This stack-up is then subjected to heat and pressure to simultaneously fuse both the several layers of dielectric substrate and fusible conductive material to provide a cohesive fused multilayer circuit board.
In the second embodiment of U.S. Pat. No. 5,046,238, at least one discrete circuit board is made using any suitable technique to define a fusible dielectric substrate having a circuit pattern thereon. Next, a layer of fusible dielectric material having openings through selected locations is placed on the circuit board so that selected locations on the circuit pattern are exposed. Thereafter, a plug of fusible conductive material (e.g., solder) is placed in the openings (using manual, mechanical or like techniques). Next, a second circuit board is stacked on the first board so that the plugs of fusible conductive material align with and contact selected locations on the circuit pattern of the second circuit board. This stack-up is then subjected to heat and pressure to simultaneously fuse both the layers of fusible dielectric and the fusible conductive material to provide a cohesive fused multilayer circuit board.
While the method of U.S. Pat. No. 5,046,238 overcomes some of the problems in the prior art, this prior art method has certain disadvantages including problems commonly encountered with spreading of the solder mass during lamination, and evolution of the flux medium necessary to deoxidize the solder. Further, spreading of the solder mass is dependent on the low viscosity of the solder, the amount of solder and the proximity of other circuit features. Also, it is difficult to evolve all of the flux compound from the internal layers of the printed circuit board thereby presenting a potential long-term reliability problem from residual organics. With continued microminiaturization of circuit features, it is desired to produce circuit boards with feature sizes smaller than that possible using solder.
In addition, the multilayer structures made completely with the fusible dielectric may suffer from one or more of the following deficiencies:
(1) too soft, which leads to handling, rework and wire bondability problems; PA1 (2) too expensive because of the expense of the fusible dielectric; and PA1 (3) too low in thermal conductivity, which can restrict use in applications where heat management and removal are required.

Method of manufacturing a multilayer circuit board