Multicopy strains of gram-positive bacteria carrying multiple copies of a DNA sequence of interest may be constructed by use of a method involving introduction of a DNA construct comprising the DNA sequence of interest into the genome of the recipient cell by transposition and subsequent deletion of a marker gene used for selection of the cells having received the DNA construct by a resolution system. The multicopy strains are preferably free from a gene encoding an undesirable marker such as an antibiotic resistance marker.

Prokaryotic transposable elements are discrete DNA sequences capable of insertion at single or multiple sites within a prokaryotic genome. Normally, such elements consist of a gene encoding a transposase protein and a transposable cassette comprising a resistance gene flanked by sequences recognized by the transposase protein. Transposition of the transposable cassette into the genome of a host cell (which may, e.g. take place at random or at hot spot sites) occurs via recognition and interaction with the flanking sequences of the transposable cassette by the transposase protein.
Different classes of transposable elements exist. One class comprises i) insertion sequences (IS) which are small (less than 2 kb) DNA fragments encoding transposase proteins or other determinants mediating transposition, and ii) composite transposons, i.e. DNA fragments flanked by two copies of an insertion sequence. The terminal portions of all IS sequences comprises inverted repeat sequences. The transposase protein functions by recognizing these terminal sequences and interacting with the sequences to effect transpositions within the genome.
The second class of transposons is the Tn3 family of tranposons. These transposons encode two products involved in a two-step transposition process: a transposase and a resolvase.
Transposons belonging to this second class have inverted terminal repeats of approximately 35-40 bp.
The third class includes bacteriophage Mu and related phages. Bacteriophage Mu is large relative to other transposons with a genome of 36 kb. Mu encodes two gene products which are involved in the transposition process, a 70 kDa transposase and an accessory protein of approximately 33 kDa. An unusual feature of Mu that distinguishes it from other tranposons is that its ends are not inverted repeat sequences. The Mu transposase has, however, been shown to bind to both ends in an in vitro binding assay.
Transposons have been used extensively for mutagenesis and cloning in gram-positive and gram-negative bacteria: Youngman, P. J., Perkins, J. B., Losick, R. (1983) Genetic transposition and insertional mutagenesis in Bacillus subtilis with Streptococcus faecalis transposon Tn917, Proc. Natl. Acad. Sci. USA, 80, 2305-2309; Youngman, P., Perkins, J. B., Losick, R. (1984), Construction of a cloning site near one end of Tn917 into which foreign DNA may be inserted without affecting transposition in Bacillus subtilis or expression of the transposon-borne erm gene, Plasmid 12, 1-9; Youngman, P. (1985) Plasmid vectors for recovering and expoliting Tn917 transpositions in Bacillus subtilis and other gram positives, p. 79-103 in K. Hardy (ed.), Plasmids: a practical approach, IRL Press, Oxford; Kleckner, N., Roth, J., Botstein, D. (1977) Genetic engineering in vivo using translocatable drug-resistance elements. New methods in bacterial genetics, J. Mol. Biol., 116, 125-159; Wati, M. R., Priest, F. G., Mitchell, W. J. (1990) Mutagenesis using Tn917 in Bacillus licheniformis. FEMS microbiol. Lett., 71, 211-214; Petit, M.-A., Bruand, C., Janniere, L., Ehrlich, S. D. (1990) Tn10-derived transposons active in Bacillus subtilis. J. Bacteriol., 172, 6736-6740.
The latter reference describes pHV1248 and pHV1249, plasmids that are thermosensitive for replication, which carry a transposase gene from Tn10 modified to be expressed in B. subtilis, and sufficient sequences from the IS10 elements of Tn10 flanking a chloramphenicol resistance gene (mini-Tn10) to allow transposition of mini-Tn10 into the B. subtilis chromosome.
Maguin et al. (Maguin, E., Duwat, P., Hege, T., Ehrlich, D, Gruss, A. (1992) New thermosensitive plasmid for gram-positive bacteria, J. Bacteriol. 174, 5633-5638) describe an alternative version of this system.
EP 485 701 discloses the use of transposons for introduction of single copies of a DNA sequence into a prokaryotic cell genome, the transposase protein being encoded in cis.
Slugenova et al., ((1993), Enhanced .alpha.-amylase production by chromosomal integrtation of PTVA1 in industrial strain in B. subtilis, Biotechnology Letters, 15, 483-488) describe the multiple integration of plasmid pTVA1 comprising a modified transposon Tn917 and an .alpha.-amylase gene of interest located outside the transposon. Antibiotic resistance marker genes are present in the resulting strain.
EP 0 332 488 describes a transposition based system for construction of multicopy bacterial strains, i.e. strains comprising multiple copies of a gene of interest, which strains further comprise multiple copies of a selectable marker gene introduced with the gene of interest. The system is exemplified by use of a phage Mu transposon for modification of gramnegative bacteria.
WO 95/01095 describes the use of a minitransposon as a vector for stably tranforming an exogenous gene into a eukaryotic (e.g. animal) chromosome.
Simon, R., Priefer, U., Puhler, A. ((1983), A broad host range mobilization system for in vivo genetic enginering: Transposon mutagenesis in gram-negative bacteria, Bio/Technology, 1, 784-791) describe the use of E. coli specific vectors to transfer transposons into other gram-negative strains by conjugation.
Several of the above described multicopy strains have been produced by integration of a genetic construct comprising the gene of interest and an antibiotic selectable marker and amplifying said construct by culturing the cell in the presence of increasing dosages of antibiotic. Thus, the resulting cell typically comprises a number of antibiotic resistance genes. The presence of such genes are undesirable, in particular from an environmental and a product approval point of view.
Non-antibiotic selection markers have been used for construction of multicopy strains. Herrero, M., de Lorenzo, V., Timmis, K. N. ((1990), Transposon vectors containing non-antibiotic resistance selection markers for cloning and stable chromosomal insertion of foreign genes in gram-negative bacteria, J. Bacteriol., 172, 6557-6567) describe such as system in which herbicide or heavy metal resistances are used as selection markers.
Another alternative to the use of antibiotic resistance markers are described in DE 4 231 764 in which an alternating selection of Thy.sup.- (trimethoprim resistance) and Thy.sup.+ (thy prototrophy) is used for introduction of product genes in Bacillus spp. thereby avoiding the need for selectable markers.
Specific deletion of DNA segments from the chromosomes of bacterial species have traditionally been performed by the methods of homologous recombination (Hamilton, C. H., Aldea, M., Washburn, B. K., Babitzke, P. (1989). New method of generating deletions and gene replacement in Escherichia coli. J. Bacteriol., 171, 4617-4622.; Maguin, E., Duwat, P., Hege, T., Ehrlich, D, Gruss, A. (1992). New thermosensitive plasmid for gram-positive bacteria. J. Bacteriol. 174, 5633-5638.). However, the use of homologous recombination to delete resistance marker genes from strains having multiple, tandem copies of such genes each linked to a copy of the gene of interest is hardly applicable, as homologous recombination would delete also the extra copies of the gene of interest.
The concept of using site specific recombination systems for integration and retrieval of sequences from the bacterial chromosome, using elements from either phage lambda or P1, and some specific methods of achieving this, has been described (Hasan, N., Koob, M., Szybalski, W. (1994), Escherichia coli genome targeting, I. Cre-lox-mediated in vitro generation of ori.sup.- plasmids and their in vivo chromosomal integration and retrieval. Gene, 150, 51-56). The cre-lox system is further described by Abremski, K., Hoess, R., Sternberg, N. (1983), Studies on the properties of P1 site-specific recombination: Evidence for topologically unlinked products following recombination, Cell, 32, 1301-1311. An alternative system is based on the recombination system of the broad-host range plasmid RP4 (Eberl, L., Kristensen, C. S., Givskov, M., Grohmann, E., Gerlitz, M., Schwab, H. (1994), Analysis of the multimer resolution system encoded by the parCBA operon of broad-host-range plasmid RP4, Mol. Microbiol., 12, 131-141)). Stark, W. M., Boocock, M. R., Sherratt, D. J. (1992), Catalysis by site-specific recombinases, Trends in Genetics, 8, 432-439) is a review article on the mechanism of resolvase action. Camilli et al. ((1994), Use of genetic recombination as a reporter of gene expression, Proc. Natl. Acad. Sci. USA, 91, 2634-2638) describe the use of res sites and resolvase from the .gamma..delta. transposon in Vibrio cholera as a permanent, heritable marker of gene expression from a chromosomal gene. The resolution system is not used for excision of marker genes. Chang, L.-K. et al. ((1994, Construction of Tn917as1, a transposon useful for mutagenesis and cloning of Bacillus subtilis genes, Gene, 150, 129-134) describe the plasmids (pE194) containing erm-res-tnpA (transposase)-tnpR (resolvase) samt IR-res-ori colE1-AB.sup.R 1-AB.sup.R 2-IR (pD917; Tn917ac1). The two res sites are there to allow the transposon to function properly, not for excision of intervening DNA.
The broad host range, gram-positive plasmid pAM.beta.1 (Clewell, D. B., Yagi, Y., Dunny, G. M., Schultz, S. K. (1974) Characterization of three plasmid deoxyribonucleic acid molecules in a strain of Streptococcus faecalis: identification of a plasmid determining erythromycin resistance. J. Bacteriol. 117, 283-289) has been described to contain a resolution system, that resolves plasmid multimers into monomers via a site specific recombination event, requiring a specific plasmid encoded enzyme (resolvase) and a site, res, on the plasmid (Swinfield, T.-J., Janniere, L., Ehrlich, S. D., Minton, N. P. (1991). Characterization of a region of the Enterococcus faecalis plasmid pAM.beta.1 which enhances the segregational stability of pAM.beta.1-derived cloning vectors in Bacillus subtilis. Plasmid 26, 209-221; Janniere, L., Gruss, A., Ehrlich, S. D. (1993) Plasmids, pp. 625-644 in Sonenshein, A. L., Hoch, J. A., Losick, R. (eds.) Bacillus subtilis and other gram-positive bacteria: Biochemistry, Physiology and molecular genetics. American society for microbiology, Washington D.C.).
It has been suggested to use a site-specific recombination system to remove a single selectable marker gene from the genome of a bacterial cell. For instance, Dale, et al. ((1991) Gene transfer with subsequent removal of the selection gene from the host genome, Proc. Natl. Acad. Sci. USA, 88, 10558-10562) describe the use of the cre/lox system for removal of markers from transgenic plants and mentions that the use of this system would obviate the need for different selectable markers in subsequent rounds of gene tranfer into the same host. Kristensen, C. S. et al. (1995), J. Bacteriol., 177, 52-58, describe the use of the multimer resolution system of the plasmid RP4 for the precise excision of chromosomal segments (such as marker genes introduced with heterologous DNA) from gram-negative bacteria. It is stated that the system is envisaged to be of interest in the generation of chromosomal insertions of heterologous DNA segments eventually devoid of any selection marker.
WO 95/02058 describes a new transposon (tn5401) from B. thuringiensis containing transposase, resolvase, and res site. The transposon is used in a plasmid which contains B. thuringiensis DNA (e.g. origin and toxin gene) and, flanked by res sites, non-B. thuringiensis DNA (e.g. E. coli origin, selectable marker genes). The plasmid is introduced into B. thuringiensis. Subsequently, a plasmid expressing the resolvase is introduced (e.g. a thermosensitive plasmid containing the entire tranposons--but only used as resolvase donor) whereby the non-B. thuringiensis DNA is excised from the first plasmid.
Conclusions With Respect to the State of the Art
On the basis of the above citations, the following conclusions may be made as to the state of the art:
The insertion of multiple genes of interest by transposition was known, e.g. as described in EP 332 488. However, all strains carrying multiple transposed sequences of interest contain selectable markers.
The removal of markers via site-specific recombination was know from either chromosome or plasmids (cf. Kristensen et al. (1995), Eberl et al. (1994), WO 95/02058). It was known to remove a marker introduced by transposon.
Multicopy strains without presence of heterologous, selectable marker genes were known (DE 4231 764). These strains were constructed by a cumbersome method depending on the use of the Thy marker.
It is an object of the present invention to construct bacterial cells which harbour a stable, fixed and well-defined copy number of one or more genes of interest, without the presence of selectable marker genes in the final strain.


Methods, systems are provided for controlling a travel path of a vehicle. The method includes the steps of detecting a braking of the vehicle by a computing device, calculating a friction ellipse for the vehicle based on the current state of the vehicle, defecting an intended travel path of the vehicle, detecting an actual travel path of the motor vehicle during the braking and determining if there is a path error where the actual travel path is outside the intended travel path when the braking is detected. When the actual travel path is outside the intended travel path then the method calculates a prospective friction ellipse for the vehicle, determines a compensating yaw moment to correct the path error, determines a maximum acceleration based on the prospective friction ellipse, and transmits a command to the autonomous braking system based on the maximum acceleration and the compensating yaw moment.

There is a need for methods to determine an intended path of travel for a vehicle and to automatically provide steering and braking control to maintain a vehicle on the intended path during braking maneuvers by coupling the road path and the driver's intended path with the need for autonomous braking. The results of the methods herein disclosed maximize velocity reduction during the braking maneuver while maintaining the vehicle on the desired path.
Electronic Stability Control (ESC) is the generic term for systems designed to improve a motor vehicle's handling, particularly at the limits where the driver might lose control of the motor vehicle. See, for example, the Society of Automotive Engineers (SAE) document on "Automotive Stability Enhancement Systems", publication J2564 (December 2000, June 2004). ESC compares the driver's intended direction in steering and braking inputs to the motor vehicle's response, via lateral acceleration, rotation (yaw) and individual wheel speeds, and then brakes individual front or rear wheels and/or reduces excess engine power as needed to help correct understeer or oversteer. ESC also integrates all-speed traction control which senses drive-wheel slip under acceleration and individually brakes the slipping wheel or wheels, and/or reduces excess engine power until control is regained from a sliding situation. ESC cannot override a car's physical limits. It is a tool to help the driver maintain control. ESC combines anti-lock brakes, traction control and yaw control (yaw is spin around the vertical axis).
ESC systems use several sensors in order to determine the state the driver wants the motor vehicle to be in (i.e., a driver command). Other sensors indicate the actual state of the motor vehicle (i.e., motor vehicle response). The ESC control algorithm compares both states and decides, when necessary, to adjust the dynamic state of the motor vehicle. The sensors used for ESC have to send data at all times in order to detect possible defects as soon as possible. They have to be resistant to possible forms of interference (rain, potholes in the road, etc.). The most important sensors are: 1) steering wheel sensor, used to determine the steering angle the driver wants to take, often based on anisotropic magnetoresistive (AMR) elements; 2) lateral acceleration sensor, used to measure the lateral acceleration of the motor vehicle; 3) yaw sensor, used to measure the yaw angle (rotation) of the motor vehicle, can be compared by the ESC with the data from the steering wheel sensor in order to take a regulating action; and 4) wheel speed sensors used to measure the wheel speeds.
ESC uses, for example, a hydraulic modulator to assure that each wheel receives the correct brake force. A similar modulator is used with anti-lock brake systems (ABS). ABS needs to reduce pressure during braking, only. ESC additionally needs to increase brake pressure in certain situations.
The heart of the ESC system is the electronic control unit (ECU) or electronic control module (ECM), (i.e., motor vehicle controller or microprocessor). Diverse control techniques are embedded in the ECU and often, the same ECU is used for diverse systems at the same time (ABS, traction control, climate control, etc.). The desired motor vehicle state is determined based on the steering wheel angle, its rate of change and the wheel speed. Simultaneously, the yaw sensor measures the actual state. The controller computes the needed brake or acceleration force for each wheel and directs the actuation of, for example, the valves of a hydraulic brake modulator.
Motor vehicles utilizing electronic stability control systems require some means of determination of the driver's intended motor vehicle behavior (i.e., intended motor vehicle path or track). In General Motors' (GM's) StabiliTrak™ system these means are accomplished by the driver command interpreter, as described in U.S. Pat. No. 5,941,919 (issued Aug. 24, 1999), which is incorporated herein by reference in it's' entirety.
Referring now to FIG. 1, the exemplar prior art control structure described in U.S. Pat. No. 5,941,919 is shown. The controller 10 includes command interpreter 12 receiving the various system inputs from various vehicle sensors 14. The command interpreter 12 develops desired yaw rate commands responsive to the various system inputs and a data structure 16 stored in non-volatile memory of controller 10. The data structure 16 has a data subset 18 corresponding to vehicle operation in linear mode and a data subset 20 corresponding to vehicle operation in non-linear mode (e.g., skidding or sliding).
When the vehicle operation is in the linear mode, the command interpreter 12, using data structure subset 18, provides commands to a control block 22 designed to maintain the linear response of the vehicle. For example, when the control according to this system is used to control wheel brakes to affect vehicle yaw control, the commands provided by block 12 do not modify the wheel brake operation while the vehicle is in the linear mode. When the control is used to control a vehicle variable force suspension system, the suspension control is provided to maintain the current driving conditions, and not to induce a change in understeer or oversteer.
When the vehicle operation is in the non-linear region, the command interpreter 12, using data structure subset 20, provides commands to the control block 22 commanding a yaw rate linearly responsive to the vehicle steering wheel input. Block 22 uses the command generated at block 12 to control one or more vehicle chassis systems, such as controllable suspension actuators, represented by block 24 and/or brakes, represented by block 26 to bring the actual vehicle yaw into a linear relationship with vehicle steering wheel angle. This control thus maintains the yaw response of the vehicle linear with respect to the steering wheel input even when the vehicle is operating in its nonlinear performance region.
Also, collision preparation systems (CPS) are known in the art and are exemplified by U.S. Pat. No. 7,280,902 which discloses a motor vehicle deceleration control apparatus; U.S. Pat. No. 7,035,735 which discloses a method and device for automatically triggering a deceleration of a motor vehicle; and U.S. Patent Application Publication 2004/0254729 which discloses a pre-collision assessment of potential collision severity for motor vehicles.
U.S. Pat. No. 6,084,508, issued Jul. 4, 2000, the disclosure of which patent is hereby herein incorporated by reference. U.S. Pat. No. 6,084,508 discloses a collision preparation system which provides autonomous braking in certain situations. The method and arrangement for emergency braking of a vehicle, include a detection system on the vehicle which detects obstacles located in or near the direction of motion of the vehicle and generates corresponding data, sensors on the vehicle which generate data representing characteristic parameters of the condition of the vehicle, and an evaluating unit which determines, from the data on the obstacles and the parameters of the condition of the vehicle, target values for controlling the motion of the vehicle and, only upon determining that an impending collision of the vehicle with an obstacle is no longer avoidable by any action on the vehicle by steering or braking, triggers an autonomous emergency braking for rapid deceleration of the vehicle.
As described in U.S. Pat. No. 8,126,626, during an autonomous braking event as a result of actuation of a collision preparation system (CPS), the driver intended travel path and the actual motor vehicle travel paths are monitored. In the event that the vehicle departs from the driver intended motor vehicle travel path, the braking is lessened, so as to attempt to follow the motor vehicle travel path intended by the driver. However, the previous designs are strictly reactive. U.S. Pat. No. 8,126,626 was issued on Feb. 28, 2012 and is incorporated herein in its entirety.
Inputs from various sensors 14 and other data sources of the motor vehicle are provided to the stability controller 10. The stability controller 10 includes a command interpreter 12. The stability controller 10 utilizes the command interpreter 12 and the control commands block 22 to control operation of the braking system 26 in the manner described pursuant to U.S. Pat. Nos. 5,941,919 and 8,126,626.
The CPS braking adjustment controller 224 has provided to it, via a data line 226, the driver braking request, the yaw rate and/or other data providing actual motor vehicle travel path information, and the steering wheel position and/or other data providing the driver intended motor vehicle travel path information, are all available from the command interpreter 12 (although such an arrangement is exemplary and not intended to be limiting) and the CPS braking adjustment controller 224 further has available to it, via a data line 228, the activation status of the CPS 210 indicative of the autonomous braking status and the braking request of the CPS. The CPS braking adjustment controller 224 sends a braking reduction signal, via data line 230, to the braking system 26 in the event there is a detected difference (in practice, at least a predetermined small difference) between the driver intended motor vehicle travel path as compared to the actual motor vehicle travel path, wherein, preferably, the driver braking request does not exceed the CPS braking request.
However, this control action only seeks to correct the path by reducing the Collision Preparation System braking. The amount of velocity reduction by the braking system (the goal of the Collision Preparation System) is diminished with the expense of maintaining the intended path. Accordingly, what is needed in the art is a motor vehicle travel path control which monitors, during an autonomous braking event, the actual motor vehicle travel path in relation to the driver intended motor vehicle travel path and has the ability to minimize the difference between the two by generating a corrective yaw moment. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.

Method to control a vehicle path during autonomous braking


A resistive memory apparatus includes a memory unit including a resistive memory cell array, a voltage generation unit suitable for receiving a radio frequency (RF) signal, and converting the RF signal into a direct current (DC) voltage, and a control unit suitable for controlling a refresh operation to be performed on the resistive memory cell array, wherein the boosted DC voltage is used as an operation voltage for the refresh operation.

1. Technical Field
Various embodiments of the inventive concept relate to a semiconductor integrated circuit, and more particularly, to a resistive memory apparatus, an operating method thereof, and a system having the same.
2. Related Art
Semiconductor memory apparatuses are largely divided into volatile memory apparatuses and non-volatile memory apparatus.
Typical examples of the volatile memory apparatuses may be dynamic random access memories (DRAMs). The DRAM periodically refreshes a state of a cell capacitor constituting a unit memory cell to retain stored data. The DRAM may perform a read/write operation at high speed, but the DRAM has high power consumption.
Meanwhile, a non-volatile memory apparatus may include a flash memory apparatus and a resistive memory apparatus. The flash memory apparatus has a non-volatile property to retain data even in power off, but the flash memory apparatus have short lifespan with the limitation of the number of times of programming.
The resistive memory apparatus has advantages of the DRAM and the flash memory apparatus.
Typical examples of resistive memory devices are a phase-change random access memory (PCRAM) using a chalcogenide compound, a ferroelectric RAM (FRAM) using a ferroelectric capacitor, a resistive RAM (ReRAM) using metal oxide, and a magnetoresistive RAM (MRAM) using perovskite.
Among the resistive memory apparatuses, the PCRAM may determine data to be stored in the selected memory cell based on a crystalline state of a phase-change material. By heating the phase-change material, a phase of the phase-change material may be changed, and thus the resistance state may be controlled. The PCRAM has a unit memory cell including an access device and the phase-change material as a resistive device for storing data. Resistance of the phase-change material may increase due to various causes, and such phenomenon is called resistance drift. The resistance drift may be intensified, as a resistance of the phase-change material becomes high.
FIG. 1 is a view for explaining a fail due to the resistance drift.
A memory cell that may store two bits or more in one memory cell is called a multilevel cell (MLC). FIG. 1 illustrates change in resistance of a multilevel cell that stores data of four levels R1, R2, R3, and R4 as time passes.
As the memory cell has a high-resistance state (i.e., in order of R4>R3>R3 >R1), the resistance drift is serious. A fail may occur from a point in time 'A' when a resistance of the memory cell programmed to have a resistance of R3 exceeds a reference resistance Ref.
In other words, a time denoted by 'A' is referred to as a data retention time (or a drift retention time) of the memory cell.
A method for preventing a fail due to the resistance drift are in demand.

Resistive memory apparatus, operating method thereof, and system having the same


Method and apparatus for defrosting an evaporator in a closed loop refrigeration system are provided. In one embodiment, liquid is circulated from a receiver containing refrigerant through an evaporator in a reverse direction to normal flow and then to another evaporator in the system. Hot gas from a compressor may be used to displace the liquid to the evaporator being defrosted. Alternatively, gas from the top of the receiver may be used for displacement of the liquid. Steps are taken to insure that cold gas from the evaporator that is input to the compressor does not contain liquid. Apparatus making possible flow of liquid in reverse direction through an evaporator selected for defrosting and then to another evaporator is provided, along with apparatus for controlling the flow.

Field of the Invention
This invention relates generally to defrosting an evaporator coil in a multiplex evaporator system of a closed loop vapor cycle refrigeration system. More particularly, the present invention is directed to methods, controllers and apparatus for defrosting an evaporator coil of a multiplex evaporator refrigeration system by passing liquid refrigerant in reverse flow through an evaporator and passing the cooled refrigerant into other evaporators in the multiplex system.

Reverse liquid defrost apparatus and method


An adhering substance peeling apparatus provided with a vertically reciprocating scraping blade at the lower end of an operating rod of a proper length so that chewing gum, dirt and other adhering substances adhering to the ground surface or the like may be peeled off while the worker is standing upright.

Heretofore, in the case of removing a chewing gum adhering to a station platform or the like, the worker has worked with a spatula or the like in the hand while bowing or squatting.
However, in peeling off such adhering substance, there have been problems that a force larger than is anticipated is required, a pain accompanies the working posture, the working efficiency is low and the work is long. The present invention is made in view of the above mentioned circumstances and has it as an object to provide an apparatus whereby such adhering substance as is mentioned above can be quickly peeled off in a standing easy working posture.


A file system for nonvolatile memory media is disclosed, based on the assumptions that the file system structure is flat (i.e., does not contain directories), and that a relatively small amount of memory space is available. The nonvolatile memory medium is divided into logical blocks of predetermined size, depending on the typical file size expected for each particular implementation. Each of these logical blocks includes a header describing the contents of the block. For example, the block header may comprise a magic number indicating whether the block is a valid file system block or a free block, the name of the file to which the current block belongs, a flag indicating whether the current block is the first or last block of the file, the block number of the next block of the current file, if any, and the length of valid data in the present block.

1. Field of the Invention
The present invention relates in general to memory devices, and more particularly file systems suitable for use with nonvolatile memories.
2. The Background Art
As is known to those skilled in the art, numerous file system implementations have been developed. Most file systems known in the art have been developed with the assumption that the files would be stored on a magnetic disk or—in the case of data networking implementations—on a magnetic disk attached to a network file server ("NFS"). Typically, files are divided into data blocks, and these blocks are laid out on the disk in which the files are to be stored. The layout of the blocks on the disk is typically optimized for minimizing the access time for file blocks stored on these disks. These file systems are normally very large, and hence very efficient file searching strategies have been developed.
Most file systems known in the art assume that a complex directory structure will be imposed on the files, and hence complex data structures have typically been required to handle them. However, other file systems known to those skilled in the art store files in a contiguous fashion. For example, on some types of nonvolatile memory, such as flash memory media, files are typically stored in a contiguous fashion on the flash card containing the flash memory. In such a flash memory medium, there is typically no concept of "file blocks" involved. As known to those skilled in the art, however, flash media has its own peculiarities. For example, flash media typically must be reformatted to regain lost space.
Nonvolatile (sometimes written as "non-volatile") random access memory ("nvram," or "NVRAM") is typically a form of static RAM whose contents are saved when a computer is turned off or loses its external power source. As is known to those skilled in the art, nvram may be implemented in various ways, including by providing static RAM with backup battery power, or by saving its contents and restoring them from an Electrically Erasable Programmable Read Only Memory ("EEPROM").
The development of nvram enabled files to be stored in a system in a persistent way. However, existing file systems are inadequate for addressing the unique set of challenges presented by the nvram memory storage media. First and foremost, the nvram media is relatively small in terms of memory capacity (typically ranging from a few hundred kilobytes to a few megabytes). Thus, only a relatively small number of files can be stored on the media. Secondly, nvram can be accessed relatively quickly, in comparison to magnetic disks, and hence disk block layout is not a major factor that affects the seek time parameter. Also, no directory structure is typically imposed on the nvram medium.
Moreover, because critical system data is often stored in nvram (e.g., cryptographic keys, system start-up configuration files, or other types of secure files), an nvram file system must be reliable. Specifically, a system "crash" should not corrupt the file system. In order to deal with these problems, a simple but elegant file system storage for the nvram medium is disclosed herein. It provides all the necessary functionality without being burdened by unnecessary details and restrictions imposed by a traditional file system. The main assumptions of the file system design according to embodiments of the present invention are that (1) the file system structure is flat (i.e., does not contain directories), and (2) a relatively small amount of memory space is available. Also, an important design goal is not to have excessive file system information in the nvram memory medium at any given time. Most of the information is kept on the nvram, and based on this, other information may be obtained. Thus, a system crash will not result in loss of vital information which might have been buffered in memory. These and other features and advantages of the present invention will be presented in more detail in the following specification of the invention and in the associated figures.

This patent is subject to a terminal disclaimer.


Exemplary embodiments of the invention provide a sensor attachment mechanism capable of attaching a position detecting sensor having directivity in a proper direction to a fluid pressure cylinder having a rail extending along the length of a cylinder tube on the outer surface thereof. Embodiments include a position detecting sensor for sensing the operating position of a piston is attached with a sensor holder to a grooved rail extending along the length of a cylinder tube on the outer surface thereof. The position detecting sensor has directivity in magnetic detection. The sensor holder includes a base mounted on the rail and a sensor holding part extending from the base. The sensor holding part is close to or in contact with the surface of the cylinder tube outside rail walls. The sensor holding part has a holding guide for holding the position detecting sensor in a direction parallel to the axis line of the cylinder such that the directivity of the sensor in the magnetic detection is directed to substantially the center of the cylinder.

A position detecting sensor is attached to a fluid pressure cylinder to determine the operating position of a piston. The position detecting sensor is provided outside the cylinder to correspond to a magnet attached to the piston in the cylinder.
According to the forms of fluid pressure cylinders, conventional mechanisms for attaching a position detecting sensor include a rail-type mechanism in which a position detecting sensor is attached with a sensor holder to a rail disposed on the outer surface of a cylinder tube in the longitudinal direction, a tie-rod-type mechanism in which a sensor holder is attached using tie rods connecting the end covers of a cylinder tube, and a groove-type mechanism in which a position detecting sensor is attached directly into a groove provided on the outer surface of a cylinder tube.
Of these mechanisms, the use of the tie-rod-type mechanism is limited to fluid pressure cylinders having tie rods. For the groove-type mechanism, a plurality of position detecting sensors cannot be provided to a single groove such that they approach each other to a distance of not more than the length of the sensors. Accordingly, a plurality of grooves must be provided on the outer surface of a cylinder tube to dispose the sensors in close proximity. For a fluid pressure cylinder, generally, position sensing at the ends of a stroke is often demanded. If the cylinder has a long stroke compared to the length of position detecting sensors, the sensors may be easily attached. If, on the other hand, the cylinder has a short stroke, the position detecting sensors interfere physically with each other in the groove mechanism. For a compact cylinder, particularly, position detecting sensors cannot be attached because the placement of grooves is spatially limited.
For the rail-type mechanism, a position detecting sensor is attached outside the rail walls of a rail. This mechanism is therefore advantageous in that a plurality of position detecting sensors may be disposed on a single rail in close proximity using the outer surfaces of the pair of rail walls by modifying the structure of a sensor holder.
In the rail-type mechanism, the position detecting sensors may be attached directly to the rail. In this case, however, general-purpose position detecting sensors cannot be used, and position detecting sensors must be prepared which have a special attachment structure and strength against, for example, tension from a lead.
The above types of position detecting sensors for sensing the position of a piston are typified by reed switch sensors, which open and close a contact using a magnetic force, and electronic magnetic sensors, which include a magnetoresistive element and have no electrical contact.
In recent years, electronic position detecting sensors have often been used for their long life and environmental compatibility. The magnetoresistive element used detects and converts the amount of change in magnetic force into an electrical signal, and the operating position of a piston is determined according to the detection output. Since the magnetoresistive element itself has directivity in magnetic detection, it must be attached such that the central axis line of the directivity is directed toward the center of a cylinder.
For the above rail-type sensor attachment mechanism, however, a position detecting sensor is positioned outside the rail walls of a rail. If, therefore, the position detecting sensor is attached in a direction parallel to the line between the centers of the rail and a cylinder, the central axis line of directivity of the position detecting sensor is not directed to the center of the cylinder. In particular, if the cylinder tube has a small diameter, the central axis line of the directivity deviates significantly from the line between the centers of the rail and the cylinder.

Sensor attachment mechanism for fluid pressure cylinder


In a wireless LAN system, each wireless terminal device determines whether or not the wireless terminal device has entered into a wireless LAN domain established by a base station, and if it has entered, transmits an entry terminal identification information update control frame including identification information of its own device to the base station at a predetermined time interval. The base station receives the entry terminal identification information update control frame from the wireless terminal device, stores in a storage the identification information of the wireless terminal device entered into the wireless LAN domain established by its own base station, and when it receives an information frame from a wired transmission line connected to its own base station, relay-transmits only the information frame to the wireless terminal device having the identification information thereof stored in the storage by referring the information stored in the storage.

1. Field of the Invention
The present invention relates to a wireless LAN (Local Area Network) system, and more particularly to a wireless LAN system in which a base station and a wireless terminal device in a cell (wireless LAN domain) communicate to each other by using a spread spectrum system, a base station device and a wireless terminal device therefor, and a method for relaying an information frame.
2. Description of the Related Art
A wireless LAN system in which a base station and a wireless terminal device communicate to each other by using a spread spectrum system has been known.
A wireless LAN system in which a wired LAN is connected to the base station of such a wireless LAN system to allow intercommunication between the wireless terminal device and the wired LAN terminal device has also been known. Such a wireless LAN system is disclosed in JP-A-4-249443.
In the wireless LAN system which allows the interconnection of the wired LAN and the wireless LAN, it is necessary for the base station to determine whether a terminal which transmitted a user frame (information frame) is present in the wireless LAN or in the wired LAN and relay it to a designated destination terminal device.
For this purpose, a wireless LAN system which realizes the relay of the information frame by a bridge function has been proposed. Such a system is disclosed in IEEE Std 802.1D-1990 "Media Access Control Bridges", pp 31-47. Entry terminal information, that is, filtering database (FDB) is provided in the wireless LAN system to realize the bridge function. When the base station receives a user frame from the wireless LAN or the wired LAN, it stores a source address of the user frame in the FDB to identify whether the terminal which transmitted the user frame is present in the wireless LAN or in the wired LAN. When the base station receives a user frame, it compares a destination address thereof with the address registered in the FDB to relay or discard the user frame.
Namely, when the base station receives a new user frame from the wired LAN and the destination address has been registered as being present in the wired LAN, it discards the received frame, and if it has not been registered, the base station relays the received frame to the wireless LAN. Similarly, when the base station receives a new user frame from the wireless LAN and the destination address thereof has been registered as being present in the wireless LAN, it discards the received frame, and when it has not been registered, the base station relays the received frame to the wired LAN.
In this case, if a frame is transmitted from a non-registered terminal while a total number of addresses (specifically MAC (media access control) addresses) registered in the FDB in the base station has reached an upper limit of the total number of the MAC addresses registerable in the FDB in the base station, or if a frame is transmitted from a terminal which is not authorized to be registered in the FDB in the base station, the base station does not register the MAC address of that terminal in the FDB but discards the frame.
Accordingly, unless the same MAC address as the destination address of the user frame newly received from the wired LAN has been registered in the FDB of the wired LAN, the received frame is relayed whether or not the destination terminal is present in the wired LAN or the wireless LAN. Thus, when the destination terminal is not present in the wireless LAN, the wireless transmission line is wastefully occupied and a transmission efficiency of the wireless transmission line is lowered.
Further, when a wireless terminal device not registered in the FDB transmits a user frame to a terminal connected to the wired LAN, the frame is discarded by the base station and wasteful communication is conducted.
A terminal which is not authorized to be registered in the FDB in the base station cannot communicate with another terminal via the base station but it can communicate directly with another terminal in the same cell. In general, in the wireless LAN system, the communication between more than two terminals or between at least a terminal and a base station is permitted at a time within one cell. Accordingly, when a terminal not authorized for registration conducts the communication in the cell, normal terminal communication may be disturbed.

Wireless LAN system, base station device and wireless terminal device therefor, and method for relaying information frame


Improvements in a charged particle beam apparatus are contemplated and especially a column structure incorporating a superhigh vacuum evacuation system is provided which is reduced in size and weight and has high performance. In order to evacuate surrounding space of a charged particle source to superhigh vacuum, ion pumps are built in a vacuum enclosure of a column. Each ion pump includes a magnet unit 15, a yoke and an electrode, and the magnet unit per se is built in the vacuum enclosure. A charged particle beam focusing optics for focusing and deflecting a charged particle beam from the charged particle beam source is arranged in a space which is defined interiorly of the yoke. The column structure can be reduced in size and weight and a charged particle beam apparatus having high performance can be obtained.

This invention relates to charged particle beam apparatus. More particularly, the present invention relates to improvements in charged particle beam apparatus using a finely focused electron or ion beam such as for example scanning electron microscopes, Auger electron analyzers and ion microscopes and especially, to size reduction of a column containing a charged particle beam generator and a charged particle beam focusing optics of the apparatus.
In the charged particle beam apparatus using a finely focused electron or ion beam such as scanning electron microscope, Auger electron analyzer, ion microscope and secondary ion mass analyzer, a charged particle source of field emission type has hitherto been used widely for the sake of improving resolution. To stably operate the charged particle source of field emission type, however, the interior space of the charged particle source must be maintained at superhigh vacuum condition and to this end, a method has conventionally been employed wherein an evacuation opening is formed directly in the outer wall of vacuum enclosure of a charged particle source of field emission type, a superhigh vacuum pump such as for example an ion pump is connected to the evacuation opening through connection piping and the pump is operated to evacuate the surrounding space of the field emission type charged particle source to a requisite high vacuum (for example, see JP-A-55-148357).
When the aforementioned evacuation method is employed, however, the connection piping has to be arranged exteriorly of the column, thus making the construction of the evacuation system per se complicated and to meet maintenance of necessary evacuation capability, sufficient reduction in size of the connection piping cannot be permitted. If the connection piping is forced to be reduced in size, then the evacuation conductance is decreased and the necessary evacuation capability cannot be obtained. Accordingly, sufficient reduction in size of the overall column structure including the evacuation system for the charged particle source is difficult to achieve.


An antenna array system for directing and steering an antenna beam is described in accordance with the present invention. The antenna array system may include a feed waveguide having a feed waveguide length, at least two directional couplers in signal communication with the feed waveguide, at least two pairs of planar coupling slots along the feed waveguide length, and at least two horn antennas.

1. Field of the Invention
This present invention relates generally to microwave devices, and more particularly, to antenna arrays.
2. Related Art
In today's modern society satellite communication systems have become common place. There are now numerous types of communication satellites in various orbits around the Earth transmitting and receiving huge amounts of information. Telecommunication satellites are utilized for microwave radio relay and mobile applications, such as, for example, communications to ships, vehicles, airplanes, personal mobile terminals, Internet data communication, television, and radio broadcasting. As a further example, with regard to Internet data communications, there is also a growing demand for in-flight Wi-Fi® Internet connectivity on transcontinental and domestic flights. Unfortunately, because of these applications, there is an ever increasing need for the utilization of more communication satellites and the increase of bandwidth capacity of each of these communication satellites.
An obvious problem to solving this need is that individual communication satellite systems are very expensive to fabricate, place in Earth orbit, and operate and maintain. Another problem to solving this need is that there are limiting design factors to increasing the bandwidth capacity in a new communication satellite. One of these limiting design factors is the relative compact physical size and weight of a communication satellite. Communication satellite designs are limited by the size and weight parameters that are capable of being loaded into and delivered into orbit by a modern satellite delivery system (i.e., the rocket system). The size and weight limitations of the communication satellite limit the type of electrical, electronic, power generation, and mechanical subsystems that may be included in the communication satellite. As a result, the limit of these types of subsystems are also limiting factors to increasing the bandwidth capacity of the satellite communication.
It is appreciated by those skilled in the art, that in general, the limiting factors to increased bandwidth capacity of the communication satellite are determined by the transponders, antenna system(s), and processing system(s) of the communication satellite.
With regard to the antenna system (or systems), most communication satellite antenna systems include some type of antenna array system. In the past reflector antennas (such as parabolic dishes) were utilized with varying numbers of feed array elements (such as feed horns). Unfortunately, typically these reflector antenna systems scanned their antenna beams utilizing mechanical means instead of electronic means. These mechanical means generally include relatively large, bulky, and heavy mechanisms (i.e., antenna gimbals).
More recently, there have been satellites that have been designed utilizing non-reflector phased array antenna systems. These phased array antenna systems are capable of increasing the bandwidth capacity of the antenna system as compared to previous reflector type of antenna systems. Additionally, these phased array antenna systems are capable of directing and steering antenna beams sometimes without mechanically moving the phase array antenna system. Generally, dynamic phased array antenna systems utilize variable phase shifters to move the antenna beam without physically moving the phased array antenna system. Fixed phased array antenna systems, on the other hand, utilize fixed phased shifters to produce an antenna beam that is stationary with respect to the face of the phased array antenna system. A such, fixed phased array antenna systems require the movement of the entire antenna system (with for example, an antenna gimbal) to directing and steering the antenna beam.
Unfortunately, while dynamic phased array antenna systems are more desirable then fixed phased array antenna systems they are also more complex and expensive since they require specialized active components (such as power amplifiers and active phase shifters) and control systems. As such, there is a need for a new type of phased array antenna system capable of electronically scanning an antenna beam that is robust, efficient, compact, and solves the previously described problems.

Antenna array system for producing dual circular polarization signals utilizing a meandering waveguide


Though the sport of snowboarding is not new, it has taken many years to understand the specific characteristics which are required for making snowboards. There is better understanding of the dynamic bending properties needed for current riders, especially for the competition driven rider whose demands require boards with different tip, tail and middle characteristics. Early snowboard designers understood the use of snowboards as articles for gliding down a snow covered slope making long curving turns, where tips and tails would be as stiff as the middle core. But now, the boards are jumped into the air, launching from half pipes edges and sliding down steel rails, requiring different flex contours. Snowboards are now required to be very flexible yet elastic being required to bend convexly and concavely, yet springing back to their shape immediately, with some riders wanting stiff tips or soft tails or a combination of both.

This invention relates to the field of devices that are used to enable the user to slide or glide across surfaces such as snow and ice. The device that is particularly suited for this invention is a snowboard. As one skilled in the art will recognize, an application of this invention can extend further than just to the field of snowboarding, and as such would be covered by the concept and spirit of this invention.


The present embodiments relate generally to workload management and more particularly to a hybrid cloud workload management system and methodology which can effectively manage the execution of tasks of the same workload on both private and public clouds. In embodiments, user tasks are seamlessly and transparently executed on a public cloud if the private cloud does not have the necessary resources available. These and other embodiments automatically detect data dependencies of user tasks and build lists of data attributes of user tasks, which are used to populate and synchronize data needed for tasks before they are executed on the public cloud. Additional or alternative embodiments include the ability to intelligently scale the compute resources in the public cloud so that appropriate number of hosts with the resources needed by the user tasks are dynamically created and also properly purged upon user task completion.

Companies, such as those that develop computer software products for example, require substantial computer resources for developing and testing computer software products. Some companies have begun to rely on private compute clouds including a large number of virtual machines for allowing their employees to develop and test incremental "builds" or versions of software products or modules. However, private compute clouds suffer from compute resource shortages during peak workload periods, which can potentially delay product releases. A solution to this problem, among others, is needed.


A process for chemical vapor deposition of crystalline silicon nitride which comprises the steps of: introducing a mixture of a silicon source, a molybdenum source, a nitrogen source, and a hydrogen source into a vessel containing a suitable substrate; and thermally decomposing the mixture to deposit onto the substrate a coating comprising crystalline silicon nitride containing a dispersion of molybdenum silicide.

Recent years have seen significant progress in the development of engineered ceramics. These new materials are expected to find uses in structural applications at high temperatures or in other specific areas where metals or polymers are less desirable. Because of the combination of attractive mechanical, thermal, and thermo-mechanical properties, one of the most interesting ceramics is Si.sub.3 N.sub.4. Silicon nitride can exist in alpha or beta hexagonal structures, the properties of the two differing somewhat. Beta-Si.sub.3 N.sub.4 (.beta.-Si.sub.3 N.sub.4) is preferred because it generally exhibits higher strength, modulus, and hardness. Si.sub.3 N.sub.4 has high strength at high temperatures, good thermal stress resistance due to its low coefficient of thermal expansion, and high resistance to oxidation when compared to other non-oxides. These properties thus allow Si.sub.3 N.sub.4 components to be used to higher operating temperatures.
Potential applications for Si.sub.3 N.sub.4 materials are abundant, including use in combustion system components such as high temperature turbines, combustion chamber liners, rocket nozzles, and thrust deflectors. The low thermal conductivity of Si.sub.3 N.sub.4 makes it attractive as a thermal barrier, either as a coating or stand-alone component. Its low density allows it to replace superalloys with a 40% weight savings. Silicon nitride's dielectric properties are of interest for use in low observable (stealth) technology.
The conventional method for producing Si.sub.3 N.sub.4 is via the hot-pressing of powder. Generally, this requires the addition of a sintering aid which lowers the melting temperature at the grain boundaries to permit consolidation. Thus the ultimate utilization temperature of the component is reduced to well below that of pure Si.sub.3 N.sub.4, preventing full use of the material's advantages. Hot pressing of Si.sub.3 N.sub.4 with sintering aids such as mixtures of yttria and alumina is typically conducted at temperatures ranging from 1600.degree. C. to 2000.degree. C., usually above 1700.degree. C.
A technique used to produce pure Si.sub.3 N.sub.4, usually as a coating, is chemical vapor deposition (CVD). In CVD gaseous reactants are caused to flow over a heated substrate where they react, depositing one or more phases, and often producing gaseous byproducts. For Si.sub.3 N.sub.4 the reactants are typically silanes, chlorosilanes, or chlorides reacted with ammonia.
In the production of Si.sub.3 N.sub.4 there are distinct advantages to the use of CVD. Crystalline CVD Si.sub.3 N.sub.4 has demonstrated one-tenth the oxidation rate of hot-pressed material. The density of CVD material is easily near theoretical. CVD also has high throwing power (can uniformly coat surfaces not in the line of sight of the source). The CVD processing temperature for many materials is much lower than that for other production methods. Although CVD is generally used for coatings, it can and has been used to prepare stand-alone bodies of pure material by depositing on a mandrel which is then removed.
A difficulty in the CVD of Si.sub.3 N.sub.4 is that only amorphous material is deposited below about 1200.degree. C., and near 1200.degree. C. crystalline material is deposited at only very low deposition rates (5 um/h). Increasing the deposition rate via increased reactant flow quickly causes the deposit to be amorphous. The only exception is the deposition from highly dilute silane and ammonia, which deposits polycrystalline Si.sub.3 N.sub.4 at 1100.degree. C. at relatively low rates (<10 um/h). Attempts to crystallize deposited amorphous coatings at 1500.degree. C. results in the coating disintegrating to a fine powder.
Unfortunately, amorphous Si.sub.3 N.sub.4 is not desirable for most engineering applications. Deposited amorphous coatings greater than 1 um in thickness are heavily microcracked. Amorphous material also tends to retain contaminants that result from processing (e.g., HCl).
Another technique which utilizes CVD to prepare ceramic bodies is chemical vapor infiltration (CVI). In CVI the vapor phase reactants are caused to diffuse or flow through a porous perform where they deposit material on the contacted surfaces, filling the void space and forming a composite material. The preform is typically fibrous, allowing a fiber-reinforced composite to be produced at relatively low temperatures and without causing damaging stress to the fibers. This technique has been successfully used to produce amorphous Si.sub.3 N.sub.4 matrix-fiber reinforced material. Again, because of the amorphous nature of the matrix, the composite is of low strength (about one-half that of similar SiC-matrix material), and retains significant amounts of HCl, which causes chemical instability.
Raising the CVI processing temperature to at least 1300.degree. C. could form crystalline Si.sub.3 N.sub.4. However, this is not feasible for CVI. At such high temperatures the rate of deposition, which is governed by the exponential Arrhenius relation, is too high for effective infiltration to occur. Deposition tends to occur at the outer surface, eventually sealing the porosity thereof and creating a steep density gradient between the entrance surface and the center of the preform. In addition, many of the types of ceramic fibers used for CVI processing suffer substantial degradation at temperatures much in excess of 1100.degree. C.,
The deposition temperature for crystalline Si.sub.3 N.sub.4 has been reduced, and/or the physical, chemical, and mechanical properties of the deposit have been altered by the addition of dopants or contaminants. One approach was the addition of titanium in the form of titanium nitride. Titanium tetrachloride was added to a SiCl.sub.4 --NH.sub.3 --H.sub.2 reaction to produce a crystalline Si.sub.3 N.sub.4 coating with a dispersed TiN second phase. The deposition temperatures for the crystalline material were at least 1250.degree. C. At 1250.degree. C., alpha-type Si.sub.3 N.sub.4 was deposited, and at temperatures greater than 1400.degree. C., .beta.-Si.sub.3 N.sub.4 was produced. The materials were developed for improved thermal and electrical conductivity. TiN, however, degrades the corrosion/oxidation resistance properties of the Si.sub.3 N.sub.4 base material. Also, the deposition temperature for the preferred .beta.-Si.sub.3 N.sub.4 is still above the decomposition temperature of many otherwise suitable substrates such as silicon, nickel, nickel-based alloys, and many ceramic fibers. Examples of ceramic fibers are: Nicalon, a trade name for a Si--C--O manufactured by Nippon Carbon Co., Tokyo, Japan; Nextel, a trade name for Al--Si--B--O manufactured by 3M Corp., St. Paul, Minn.; and HPZ, a trade name for Si--N--C--O manufactured by Dow-Corning, Midland, Mich.
There is a need for a second phase material which improves chemical resistance, lowers the deposition temperature for crystalline material, especially that which contains .beta.-Si.sub.3 N.sub.4, and also provides a Si.sub.3 N.sub.4 coating with exceptional oxidation/corrosion resistance and chemical inertness.
For further information, the following documents are referenced, and the disclosure of each is expressly incorporated herein by reference:
1. R. A. Tanzilli, et al., "Processing Research on Chemically Vapor Deposited Silicon Nitride--Phase 3", Document No. 81SDR2111, final technical report prepared under contract No. N0014-78-C-0107 for the Office of Naval Research, (1981).
2. T. Hirai, "CVD of Si.sub.3 N.sub.4 and Its Composites, " pp. 329-345 in Emergent Process Methods for High Technology Ceramics, North Carolina State University, Ed. R. F. Davis, H. Palmour III, and R. L. Porter, Plenum Press, N.Y. (1984).
3. T. Hirai, et al., "CVD Fabrication of In-situ Composites of Non-oxide Ceramics," Tailoring Multiphase and Composite Ceramics, Proceedings of the Twenty-first University Conference on Ceramic Science, p. 165-178, Pennsylvania State University, Plenum Press, New York (1986).
4. F. Galasso, et al., "Pyrolytic Si.sub.3 N.sub.4," J. Am. Ceram. Soc. 55(8), 431 (1972).
5. J. J. Gebhardt, et al., "Chemical Vapor Deposition of Silicon Nitride," J. Electrochem. Soc.: Solid-State Science and Technology 123(10), 1578-1582 (1976).
6. A. C. Airey, et al., "Pyrolytic Silicon Nitride Coatings," Proc. Brit. Ceram Soc. 22, 305-320 (1972).
7. U.S. Pat. No. 4,598,024.
8. U.S. Pat. No. 4,580,524.

Molybdenum enhanced low-temperature deposition of crystalline silicon nitride


A semiconductor memory device is provided that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared sense amplification system, in a predetermined number of times which is (k−1) times or less among k-times of continuous word line selections of a selected memory block, the bit line separation gate of the unselected memory block is rendered conductive in the active period of the equalizing unit after the word line selection. Also, a circuit that equalizes a wiring higher in the capacity component is driven by a higher voltage level according to the wiring capacity component of the sense amplification power supply line and the bit lines.

1. Field of the Invention
The present invention relates to a semiconductor memory device and a control method thereof, and more particularly to a semiconductor memory device that improves the equalizing operation of bit lines and a control method thereof.
2. Description of Related Art
In a semiconductor memory device such as a dynamic random access memory (hereinafter referred to as "DRAM"), there is a shared sense amplifier system that shares one sense amplifier group by two memory blocks. In this case, in order to separate a bit line within an unselected memory block from a sense amplifier, a bit line separation gate (BT) is disposed.
FIG. 10 is a diagram showing a part of a shared sense amplifier system. A sense amplifier S/A is connected between a bit line BLZ and a complementary bit line BLX, and shared by memory blocks BLK1 and BLK2 adjacent to each other. Separation gates BTL and BTR are connected between the respectively corresponding memory blocks BLK1, BLK2 and the sense amplifier S/A, and perform conduction and non-conduction in response to the corresponding separation gate control signals sbltlx and sbltrx. The bit lines are equalized by an equalizer circuit 150 disposed at the sense amplifier.
In this example, an alternate sense amplifier S/As may be replaced by the sense amplifier S/A. In the above-mentioned sense amplifier S/A, an inner step-down voltage Vcc is applied to a sense amplifier active line PSA, and a ground voltage Vss is applied to a sense amplifier active line NSA, to thereby bring the sense amplifier S/A into an active state. On the other hand, in the alternate sense amplifier S/As, when an alternate sense amplifier active signal LEX of a low level is inputted to a transistor Tr9, and an alternate sense amplifier active signal LEZ of a high level is inputted to a transistor Tr10, Vcc and Vss are then applied to the alternate sense amplifier S/As, to thereby bring the alternate sense amplifier S/A into an active state.
FIG. 11 is a timing chart showing self refresh operation. The self refresh operation is conducted in response to a "high" level (active) of a self-refresh enable signal SREFE. In a period of time when the block BLK1 is self-refreshed, the control signal sbltlx is kept in the "high" level, the separation gate BTL is rendered conductive, and the bit lines BLLZ and BLLX within the block BLK1 continue to be connected to the bit lines BLZ and BLX that are connected with the sense amplifier S/A. During the period of time, word lines sw10, sw11, . . . are sequentially activated in response to the "low" level transition of /RAS that is an internal RAS signal, and the bit lines BLLZ and BLLX are restored. Simultaneously, the word lines sw10, sw11, . . . are inactivated in response to the "high" level transition of /RAS, and the bit lines BLLZ and BLLX are equalized.
Also, the separation gate BTR on the unselected block BLK 2 side is rendered conductive by putting the control signal sbltrx into the "high" level every period where /RAS is "high" level, that is, every period where the bit line of the BLK1 is equalized. As a result, the bit lines BLRZ and BLRX of the unselected block BLK2 are connected to the bit lines BLZ and BLX and equalized. Meanwhile, when the block BLK2 is self-refreshed, the same equalization control is conducted on the block BLK1. Subsequently, the same operation is conducted on the respective blocks, to thereby complete self refresh with respect to all of the memory cells.
On the other hand, as disclosed in JP 9-161477A and JP 10-222977A, in the control shown in FIG. 12, the control signal of the separation gate on the unselected block side is always kept in the "low" level in a refresh period of the memory cell on the selected block side. For that reason, the sense amplifier S/A and the bit line on the unselected block side are not connected to each other even during the equalizing period of the selected block. Unlike with the case shown in FIG. 11 where the unselected block is connected, the separation gate that is connected to the unselected block does not conduct switching operation every time the selected block is equalized, thereby reducing charge and discharge current.
In a semiconductor memory device disclosed by JP 8-153391A and JP 9-45879A, a bit line equalizer circuit is disposed in each of memory blocks separated from the sense amplifier with the bit line separation gate. Accordingly, the equalizing operation is conducted by means of the bit line equalizer circuit disposed in the unselected memory block even in a period where a bit line between the unselected memory block and the sense amplifier is rendered nonconductive. As a result, the potential displacement caused by the floating state of the bit line potential can be prevented.
Also, in FIG. 10, both of a bit line equalization control signal BRS, and an equalization control signal BRSS of sense amplifier active lines PSA/NSA are controlled between a step-up voltage Vpp and the ground voltage Vss. The driving performance of an equalization transistor is enhanced by driving with the step-up voltage Vpp that has been stepped up from an external supply voltage Vdd, thereby reduce an equalization period of time.
Also, in the recent semiconductor memory device, in order to increase the speed of the restoring operation or improve the sensitivity to accumulated charges by using the sense amplifier, a bit line length may be shortened. With this structure, the wiring capacity of the bit line is reduced, and a reduction in the current consumption at the time of restoring and a reduction in the equalization period of time are tried.

Semiconductor memory device and method of controlling the semiconductor memory device


A zoom lens system comprising at least three lens groups including a positive first lens group, a positive second lens group having at least one negative lens element, and a third lens group having a negative focal length, wherein upon zooming from the shortest focal length toward the longest focal length, all the lens groups are moved toward the object side, and the distance between the first and second lens groups increases and the distance between the second and third lens groups decreases, and wherein the system satisfies the conditions (1) -0.3<f.sub.W /f.sub.1G +f.sub.W /f.sub.2G +f.sub.W /f.sub.3G <0, and (2) 1.845<N.sub.2Gn, wherein f.sub.W designates the focal length of the entire optical system at the short focal length extremity, f.sub.1G designates the focal length of the first lens group (f.sub.1G >0), f.sub.2G designates the focal length of the second lens group (f.sub.2G >0), f.sub.3G designates the focal length of the third lens group (f.sub.3G <0), N.sub.2Gn designates the average refractive index of all the negative lens elements of the second lens group.

1. Field of the Invention
The present invention relates to a zoom lens system for a compact camera having a back focal distance smaller than that of a single lens reflex camera, and in particular, relates to a miniaturized zoom lens system with a high zoom ratio.
2. Description of the Related Art
In a zoom lens of a compact camera, there has been a need to attain a high zoom ratio of more than 3, and miniaturize the zoom lens itself. To meet this requirement, the Petzval sum has a tendency to become a large negative number, so that it is difficult to compensate astigmatism and field curvature particularly at the wide angle extremity (short focal length side).


A method and system for detecting the corners of a region in an image.

This invention relates generally to methods and systems for recognizing features, and, more particularly, to methods and systems for automatic detection of corners of a region.
Detection of features is a common operation in computer vision and character recognition. Specifically, the detection of corners is a necessary operation in many computer vision and character recognition problems. In one application, the recognizing of the address in the delivery items (parcels), the detection of the address label is one necessary step. When the delivery item (parcel) is imaged in order to recognize (read) the address label, the image of the label is often randomly orientated. The need to identify the four corners of the image of an address label after finding the image of the label is critical to further processing and character segmentation.
Corner detection methods, which work directly at the gray scale level, have been developed. Some of these methods compute a local measure of cornerness defined as the product of a gradient magnitude and the rate of change of gradient direction. Corner detection based on grayscale gradient or local measures of cornerness would highlight any texture areas including addresses inside the label and other noisy regions. For images of address labels, it is extremely difficult to isolate an image of an address label on parcel images due to poor contrast and a cluttered background. Traditional corner detection techniques based on grayscale gradients fail to isolate the four corners of an address label due to similar gradients existing throughout the contextual image region.
There is also a need for a method for detecting the corners of an image of an address label in order to determine the orientation.

Methods and systems for automatic detection of corners of a region


Disclosed herein are methods and systems that apply a multi-layer Hidden Markov Model (HMM) for intrusion detection. The methods and systems employ a dimension reduction technique to extract only important features from network packet data and apply a decomposition algorithm to lower levels of data to construct lower level HMMs (representing partial solutions), which lower level HMMs are then combined to form a final, global solution. The multi-layer approach can be expanded beyond the exemplary case of 2 layers in order to capture multi-phase attacks over longer spans of time. A pyramid of HMMs can resolve disparate digital events and signatures across protocols and platforms to actionable information where lower layers identify discrete events (such as network scan) and higher layers identify new states which are the result of multi-phase events of the lower layers.

Intrusion Detection Systems have been the subject of significant research both in academia and industry in the past few decades as the interest in information security has been growing rapidly. The National Institute of Standards and Technology (NIST) defines intrusion detection as "the process of monitoring the events occurring in a computer system or network and analyzing them for signs of intrusions, defined as attempts to compromise the confidentiality, integrity, availability, or to bypass the security mechanisms of a computer or network." A system which addresses or automates intrusion detection is referred as an "Intrusion Detection System" ("IDS").
Intrusion detection systems come in different forms. Based on their points of placement, they can be categorized into network-based intrusion detection system (NIDS) and host-based intrusion detection system (HIDS). A network intrusion detection system (NIDS) is placed at a strategic point in the network such that packets traversing a particular network link can be monitored. NIDSs monitor a given network interface by placing it in promiscuous mode. This will help the IDS in hiding its existence from network attackers while performing the task of network traffic monitoring. On the other hand, Host-based IDSs monitor and reside in individual host machines. HIDSs operate by monitoring and analyzing the host system internals such as operating system calls and file systems. In the same way as NIDS, it can also monitor the network interface of the host.
The techniques employed by modern day IDSs to gather and analyze data are extremely diverse. However, those techniques have common basic features in their structures: a detection module which collects data that possibly contain evidence of intrusion and an analysis engine that processes this data to identify intrusive activity. Those analysis engines mainly use two techniques of analysis: anomaly detection and misuse detection.
The intrinsic nature of misuse detection revolves around the use of expert systems that are capable of identifying intrusions mainly based on a preordained knowledge base. Consequently, misuse structures are able to reach very high levels of accuracy in identifying even very subtle intrusions which might be represented in their knowledge base; similarly, if this expert knowledge base is developed carefully, misuse systems produce a minimum number of false positives. Unfortunately, however, carry a disadvantage due to the fact that a misuse detection system is incapable of detecting intrusions that are not represented in its knowledge base. Subtle versions of known attacks may additionally affect the evaluation if a misuse system is not well-constructed. Therefore, the efficiency of the system is highly dependent on the thorough and accurate creation of this information base, an undertaking that calls for human expertise involvement and, thus, the need to develop anomaly detection methods.
A wide variety of strategies have also been explored to detect anomalous events from normal ones, including neural networks, statistical modeling and Hidden Markov Models ("HMMs") to name a few. Those approaches rely on the same principle. At first, a baseline model that is a representative of normal system behavior against which anomalous events can be distinguished is established. When an event indicates anomalous activity, as compared with the baseline, it is considered as malicious. This system characterization can be used to identify anomalous traffic from normal traffic.
One of the very attractive features of anomaly-based intrusion detection systems is their capability to identify previously unseen attacks. The baseline model in this case is usually automated and it does not require both human interference and the knowledge base. The aftermath of this approach is that the detection system may fail to detect even well-known attacks if they are crafted not to be substantially different from the normal behavior established by the system.
Currently, more than fifty percent of web traffic is encrypted—both normal and malicious. The volume of encrypted traffic is expanding even more, which creates confusion and challenges for security teams trying to monitor and identify malicious network traffic. The main goal of encryption is to enhance network security, but at the same time it provides intruders the power to hide command-and-control (C2) activity, giving them enough time to launch attacks and to cause damage. To keep up with the intruders, security teams need to include additional automation and modern tools that are developed using machine learning and artificial intelligence to supplement threat detection, prevention and remediation.
More enterprises are now exploring the fields of machine learning and artificial intelligence to prevail over the effect of encryption and to decrease adversaries' time. These advanced concepts have the capability to keep up their performance without humans having to clarify precisely the way to accomplish the tasks that they are provided. Unusual patterns of web traffic that can indicate malicious activity can be automatically detected as these advanced systems, which can, overtime, "learn" by themselves.
To automatically detect "known-known" threats, the types of attacks that have been known previously, machine learning plays a significant role. But its main advantage in monitoring encrypted web traffic is due to the fact that it is capable of detecting "known-unknown" threats (previously unknown distinct form of known threats, malware subdivision, or similar new threats) and "unknown-unknown" (net-new malware) threats. Those technologies automatically alert potential attacks to network administrators as they can learn to identify unusual patterns in massive volumes of encrypted web traffic. Those automatic alerts are very important in organizations where there is a lack of knowledgeable personnel in the enhancement of security defenses. Intelligent and automated tools using machine learning and artificial intelligence can help security teams fill the gaps in skills and resources, making them more capable in recognizing and responding to both well-known and prominent threats.
Several techniques of artificial intelligence (AI) have been explored in the path towards developing IDSs, such as fuzzy logic, artificial neural networks (ANNs), and genetic algorithms (GA). In addition, hybrid intelligent IDSs, such as evolutionary neural networks (ENN) and evolutionary fuzzy neural networks (EFuNN)—based IDSs, are also used.
The current implementations of HMMs for IDS are mainly based on a single HMM, which will be trained for any incoming network traffic to identify anomalous and normal traffic during testing.
Other HMM based IDS implementations rely on multi HMM profiles where each of the HMMs are trained for a specific application type traffic and posterior probabilities are used to select network applications using only packet-level information that remain unchanged and observable after encryption, such as packet size and packet arrival time. This approach, even if it includes factors based on application layer traffic, considers only a limited number of features and is unable to detect multistage attacks, which can be crafted to look like normal traffic. Further, other prior methods have applied several pre-processing techniques on the dataset considered to implement a multi-class system (MCS) HMM-based IDS.
HMMs use statistical learning algorithms that suffer in cost exponentially as the volume of data grows. This aspect is commonly referred as the curse of dimensionality. The HMMs tend to fail, more often than not, on a large dimension state space. Considering a single HMM-based IDS, as the incoming network traffic will have a large hidden state space, it will fall victim to this curse of dimensionality.
Thus, there remains a need in the art for methods and systems for implementing IDSs, and in particular HMM-based IDSs, that avoid foregoing disadvantages of such systems but that ensure the capability of detecting a wide variety of intrusion types over extended periods of time.

Method and system for intrusion detection


A controller area network transceiver and a transmission method for a controller area network provides improved symmetry between its differential output signal CANH and CANL such that capacitive imbalance is minimized. The transceiver disclosed herein includes a driver including a non-inverted output that couples to the first output terminal CANH and a inverted output that couples to the second output terminal CANL. A receiver comparator includes a non-inverted input coupled to the first output terminal CANH and a inverted input coupled to the second output terminal CANL. A first and second impedance matching circuit portions capacitively balance the first and second output terminals such that efficient common-mode rejection is enabled by setting the RC time constants formed by each impedance matching circuit and external resistances to be substantially equivalent. This transceiver provides a high performance, simple, and cost effective design which eliminates capacitive imbalance while decreasing required die area.

A controller area network (CAN) bus, such as that compliant with the ISO 11898 standard, is used in several systems including industrial, automotive, robotic, and motor control systems to provide a serial communication physical layer. The robust CAN bus provides low power requirements, space savings and reduced resources. As shown in FIG. 1, a CAN node is comprised of three basic parts: a processor, a network controller, and a transceiver. The transceiver interfaces the single-ended CAN controller with the differential CAN bus. The bus, as shown in FIG. 2, includes multiple nodes that transmit messages on-demand by any node whenever the bus is free. The transceiver broadcasts data such that all nodes receive each message sent on the bus, including the node that sent it. The effect of broadcasting of data allows multiple nodes to utilize the data transmitted.
Texas Instruments, Inc. ® has introduced CAN transceiver models: SN65HVD230, SN65HVD231, and SN65HVD232, for use in applications employing the CAN serial communication physical layer compatible with the ISO 11898 Standard. As a CAN transceiver, as shown in FIG. 3a, each model provides differential transmit capability to the bus and differential receive capability to a CAN controller at speeds of up to 1 Mbps. Designed for operation in especially harsh environments, the CAN transceiver features cross-wire, over voltage and loss of ground protection from −4 V to +16 V, over-temperature protection as well as −2 V to 7 V common-mode range, and withstands transients of ±25 V.
FIG. 3b represents the timing diagrams of several signals including the signals found at driver node D, receiver node R, differential nodes, CANH and CANL, and voltage output differential Vod of CAN transceiver 10. As shown, when the driver input D is low, the differential output nodes, CANH and CANL, are high and low respectively. When the driver input D is high, however, transceiver 10 goes into a tri-state mode where the differential output nodes, CANH and CANL, are both tri-state.
In general, the input capacitance of the receiver comparator 14 is capacitively balanced without any added circuitry if the transistors that form the input differential pair within the receiver comparator 14 are made the same size. Conventionally, these transistors are made the same size. Driver 12, however, includes driver outputs that tend to be the source of capacitive imbalance on the receiver input pins.
To correct this capacitive imbalance, additional impedance balancing circuitry must be added to the differential nodes, CANH and CANL, in compliance with the ISO 11898 physical layer standard. Driver arbitration problems arise when one driver on the bus is trying to pull a bus line low while another driver is trying to the pull the same bus line high. The ISO 11898 physical layer standard avoids driver arbitration problems by requiring that only an active pull-up device may be connected to the CANH node and only an active pull-down device may be connected to the CANL node.
A known CAN transceiver compliant with ISO 11898 physical layer standard, as shown in FIG. 4, includes impedance matching circuitry formed using bipolar transistors, 36 and 42, and blocking Schottky diodes, 38 and 40 connected as shown. Differential node CANH1 uses a PNP (or PMOS) transistor 36 as an active device, while differential node CANL1 uses a NPN (or an NMOS) transistor 40 as an active device. A disadvantage of this design is that the upper PNP transistor 36 connected to node CANH1 must be substantially larger than the lower NPN transistor 42 connected to node CANL1 to meet output differential voltage requirements of the ISO11898 standard. Since upper PNP transistor 36 has more capacitance than the lower NPN transistor 42 and the driver outputs, 44 and 46, are indirectly connected in parallel to the receiver inputs, CANH1 and CANL1, through transistors, 36 and 42, capacitive imbalance still exists on the receiver inputs, CANH1 and CANL1. Conventionally, the CANH1 node will have a capacitance of 18 pF while the CANL1 node will have a capacitance of 7 pF, leaving a difference of 11 pF.
Furthermore, capacitive imbalance presents another problem in that it prevents the transceiver from passing a common mode rejection test which is conducted in an effort to make certain that the impedance matching circuitry guards the receiver against common-mode transients such as noise which causes the differential output nodes, CANH1 and CANL1, to be pulled higher than the power supply rail voltage VCC or lower than ground.
Given a common-mode rejection test implementation, as shown in FIG. 5a, if during the application of the input differential voltage to the differential output nodes, CANH1 and CANL1, the receiver output node R1 experiences a change of state from low to high when it should remain low, then transceiver 30 has failed the common-mode rejection test. If, however, during application of the differential applied voltage, the receiver output node R1 remains low or does not experience a change of state, then transceiver 30 has passed the common-mode rejection test. Failure of the common-mode rejection test stems from the difference between the RC time constant of differential output nodes, CANH and CANL.
Conforming with ISO11898 requirements, FIG. 6 illustrates another approach to eliminate the capacitive imbalance in a transceiver architecture. As shown, driver 102 includes outputs, 104 and 106, couples to nodes, CANH2 and CANL2, respectively. Circuits 114 and 120 serve as active devices for transceiver 100. Circuit 114 includes transistor 122 having a gate coupled to power supply VCC, a drain coupled to the gate of transistor 124 and a source coupled to node CANH2. Transistor 124 includes a drain coupled to the power supply VCC and a source couple to node CANH2. Schottky diode 126 couples between power supply VCC and bulk nodes of transistors, 122 and 124. Circuit 120 includes transistor 140 having a gate coupled to power supply VCC, a drain coupled to a Schottky diode 138, a source coupled to ground and a bulk coupled to the source. Schottky diode 138 couples between node CANL2 and the drain of transistor 140. Redundancy through circuits, 116 and 118, is incorporated within this design to correct any capacitive imbalance, such that circuit 116 is a replica of circuit 114 and circuit 118 is a replica of circuit 120.
Dummy devices, 116 and 118, are placed on nodes CANH2 and CANL2 to mimic the capacitance of the active driver on the corresponding node opposite each respective node. Thereby, differential output nodes CANH2 and CANL2 are capacitively balanced. The disadvantage of this architecture is that the dummy devices, 116 and 118, are designed to be as large as the active devices, 114 and 120, to perfectly balance the receiver input capacitance. The capacitance, however, does not need to be perfectly balanced; rather, the RC time constant is formed by external resistors in a receiver common-mode rejection test implementation and the capacitance of nodes, CANH2 and CANL2, must be balanced.
Furthermore, in order to remain price competitive, minimization of the CAN transceiver die size is an important design criteria. Removing dummy devices, 116 and 118, from the CAN transceiver architecture would suffice to lower die area and would not result in any performance drawbacks; however, it will cause transceiver 100 to fail common-mode rejection test.
Therefore, a need exists for a CAN transceiver that provides improved impedance matching between differential output signals, CANH and CANL, while the requirements of die area are decreased. The impedance matching circuit portions must connect to differential output nodes, CANH and CANL, and capacitively balanced differential output nodes, CANH and CANL, such that the RC time constants formed with external test resistors are equivalent. As a result, the improved transceiver must provide superior common-mode rejection, passing the aforementioned common-mode rejection test.

Controller area network transceiver having capacitive balancing circuit for improved receiver common-mode rejection