A semiconductor memory device is provided, which prevents electrical short-circuit between the wiring lines (e.g., the bit lines) and the contact pads for electrically connecting the lower capacitor electrodes. The first conauctive pads are formed to fill the respective contact holes of the first interlayer dielectric film in such a way that the tops of the first pads are lower than the surface of the first interlayer dielectric film. Thus, the gaps are formed on the tops of the first pads in the respective contact holes. The wiring (or conductive) lines, the top faces and side faces of which are covered with the dielectric, are formed on the surface of the first interlayer dielectric film. The wiring lines of the first group are electrically connected to the first conductive pads. The wiring lines of the second group are apart from the respective first conductive pads, thereby electrically insulating the wiring lines of the second group from the first conductive pads.

1. Field of the Invention
The present invention relates to the technique relating to a semiconductor memory device and more particularly, to a semiconductor memory device (e.g., a Dynamic Random-Access Memory, a DRAM) with the so-called cylindrical capacitor structure, and a method of fabricating the device.
2. Description of the Related Art
Recently, the tendency to decrease the memory cell size or area has been progressing with the increasing storage capacity and the rising integration-scale or density. In particular, with the storage cell of DRAMS, the two-dimensional size of the storage capacitor for storing electric charge needs to be decreased without reducing the essential capacitance value of each storage cell for normal operation. Thus, to meet this need, various three-dimensional capacitor structures (e.g., the cylindrical stacked capacitor, fin-like stacked capacitor, and so forth) have ever been developed and some of them have been actually applied to manufacture. Some examples of them are disclosed in the Japanese Non-Examined Patent Publication Nos. 10-189910 published in July 1988 and 10-22483 published in January 1998.
With the conventional DRAMS of this type, the conductive contact pads in the storage cells are formed to fill the contact holes in an interlayer dielectric layer according to the minimum design rule. Thus, it has become difficult to form stably a patterned photoresist film for the contact pad. Also, due to the reduction of the alignment margin, electrical short-circuit tends to occur between the wiring lines and the storage capacitors.
An example of the conventional methods of fabricating the DRAM with the cylindrical stacked capacitor structure is explained below with reference to FIGS. 1 and FIGS. 2A to 2D.
The conventional DRAM has a typical configuration shown in FIG. 1, which includes active areas 116 formed in a semiconductor substrate 101. The areas 116 are arranged regularly in the substrate 101. Two Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs, not shown) are formed in each of the areas 116. Bit lines 107 and gate electrodes 114 of the MOSFETS are arranged in a matrix array over the substrate 101. The gate electrodes 114 are formed to be consecutive and serve as word lines. The bit lines 107 extend in the X direction while the gate electrodes (i.e., word lines) 114 extend in the Y direction.
Each of the active areas 116 includes two source regions and a common drain region of the two adjoining MOSFETs. The common drain region is electrically connected to the overlying, corresponding bit line 107 by way of a conductive contact pad 106.
Each of the two source regions is electrically connected to the overlying, lower electrode of the corresponding storage capacitor by way of the corresponding contact pad 106. The lower electrode has an approximately rectangular pattern (i.e., the plan shape), as shown in FIG. 1.
The conventional DRAM having the configuration shown in FIG. 1 is fabricated in the following way.
First, as shown in FIG. 2A, an isolation dielectric 102 is selectively formed in the substrate 101 by the known Shallow Trench Isolation (STI) method, forming the active areas 116. A specific impurity is selectively ion-implanted into the areas 116, forming the diffusion regions (e.g., source/drain regions) 103. Thereafter, MOSFETs are formed in the areas 116 using the regions 103 through known processes.
Subsequently, a first interlayer dielectric film 104, which is made of, for example, a borophosphor silicate glass (RPSG), is deposited over the whole substrate 101 and then, the surface of the film 104 is planarized by the chemical-mechanical polishing (CMP) method. After a patterned photoresist film (not shown) is formed on the film 104 thus planarized, the film 104 is selectively etched using the photoresist film as a mask. Thus, contact holes 105 for the conductive contact pads 106 are formed over the diffusion regions 103 which will be electrically connected to the overlying bit lines 107 and the overlying lower capacitor electrodes.
Following this, a polysilicon film (not shown) is formed on the first interlayer dielectric film 104 and etched back by a dry etching process, thereby forming polysilicon contact pads 106 to fill the respective holes 105. The state at this stage is shown in FIG. 2A.
Next, the bit line 107 are formed on the first interlayer dielectric film 104, as shown in FIG. 2B. Specifically, a tungsten polycide film and a silicon nitride film (both of which are not shown) are successively deposited on the film 104 and then, they are selectively etched by dry etching processes using the same patterned photoresist film as a mask. Thus, the bit lines 107 are formed on the film 104 by the remaining tungsten polycide film while dielectric caps 108 are formed on the tops of the lines 107 by the remaining silicon nitride film.
The bit line 107 located at approximately the middle in FIG. 2B is contacted with the underlying polysilicon contact pad 106. Unlike this, the bit lines 107 located at the left and right sides in FIG. 2B are slightly contacted with the underlying contact pads 106, respectively. This is undesired contact.
A silicon nitride film (not shown) is deposited on the first interlayer dielectric film 104 to cover the bit lines 107 with the caps 108. The silicon nitride film is then etched back by a dry etching process, forming sidewalls 109 at each side of each bit line 107, as shown in FIG. 2C. Thus, the top and both sides of each line 107 are entirely covered with silicon nitride. The state at this stage is shown in FIG. 2C.
A second interlayer dielectric film 110, which is thicker than the first interlayer dielectric film 104, is deposited on the film 104 over the whole substrate 101 to cover the bit lines 107 with the caps 108 and the sidewalls 109. The surface of the film 110 is then planarized by a CMP process. A patterned photoresist film (not shown) is formed on the film 110 and then, the film 110 is selectively etched by a dry etching process, thereby forming openings 111 in the film 110 for the lower capacitor electrodes. As shown in FIG. 1, the openings 111 are approximately rectangular in plan shape. This dry etching process is performed under the condition that the etch selectivity is sufficiently high between BPSG (i.e., the film 110) and silicon nitride (i.e., the caps 108 and the sidewalls 109). For example, a gaseous mixture of CHF3 and CO is used for this purpose.
Thereafter, a polysilicon film (not shown) is deposited on the interlayer dielectric film 110 to extend along the inner walls of the openings 111. Using a patterned photoresist film as a mask, the polysilicon film thus deposited is selectively etched by a dry etching process, forming the lower electrodes of the capacitors.
With the above-mentioned method of fabricating the conventional DRAM with reference to FIGS. 2A to 2D, there are the following problems.
The first problem is that electrical short-circuit tends to occur between the contact pad 106 in each opening 111 and the adjoining bit line 107. This is because the contact holes 105 in the first interlayer dielectric layer 104 are formed according to the minimum design rule and therefore, the alignment margin is extremely small between the opening 111 and the line 107.
As shown in FIG. 2D, the bottoms of the bit lines 107 located at approximately the left and right sides are in undesired contact with the tops of the respective contact pads 106.
The second problem is that the bit lines 107 tend to be undesirably etched in the dry etching process of forming the openings 111 in the second interlayer dielectric film 110 due to the reason described below.
The width of the bit line 107 may be decreased to avoid the first problem. In this case, however, the surface areas of the caps 108 and the sidewalls 109 (both of which are made of silicon nitride) decrease, resulting in an etch rate increase of the caps 108 and the sidewalls 109. In this way, the etch resistance of the caps 108 and the sidewalls 109 deteriorates. This leads to unwanted exposure of the bit lines 107 from the caps 108 and/or the sidewalls 109, contacting the lines 107 with the lower capacitor electrodes.
To solve the above-described first and second problem, an improved method has been developed, which is explained below with reference to FIGS. 3A to 3D.
First, the structure as shown in FIG. 3A is formed in the same way as explained in the above-described conventional method. The structure in FIG. 3A is the same as that shown in FIG. 2A.
Thereafter, as shown in FIG. 3B, an additional interlayer dielectric film 217 is deposited on the first interlayer dielectric film 104 over the whole substrate 101. Next, the film 217 is selectively etched to form a contact hole 217a located just over the contact pad 106 to be connected to the overlying bit line 107. The hole 217a is filled with a polysilicon contact pad 218.
The subsequent process steps are carried out in the same way as explained in the above-described conventional method.
Specifically, shown in FIG. 3B, the bit lines 107 are formed on the additional interlayer dielectric film 217 by the patterned tungsten polycide film while the dielectric caps 108 are formed on the lines 107 by the patterned silicon nitride film. Thereafter, the sidewalls 109 are formed by the silicon nitride film at each side of the bit lines 107, as shown in FIG. 3C.
The bit lines 107 located at the middle in FIG. 3B is electrically connected to the underlying polysilicon contact pad 106 by way of the contact pad 218. Unlike this, the bit lines 107 located at the left and right sides in FIG. 3B are separated from the underlying polysilcon contact pads 106 by the additional interlayer dielectric film 217.
The thick second interlayer dielectric film 110 is formed on the additional interlayer dielectric film 217 to cover the bit lines 107 with the caps 108 and the sidewalls 109 and then, the surface of the film 110 is planarized. The film 110 is selectively etched to form the openings 111 in the film 110 for the lower capacitor electrodes. Thereafter, the lower capacitor electrodes are formed in the openings 111 by the polysilicon film.
With the above-described improved method shown in FIGS. 3A to 3D, the above-described first problem can be solved. However, there arise another problem that the number of necessary process steps increases. For example, the steps of depositing the additional interlayer dielectric film 217, forming a pattered photoresist film, selectively etching the film 217 at the position just below the desired bit line 107 to form the contact hole 217a, and removing the pattered photoresist film are additionally required.
Accordingly, an object of the present invention is to provide a semiconductor memory device that prevents the electrical short-circuit between the conductive contact pads electrically connected to the lower capacitor electrodes and the wiring lines (e.g., the bit lines), and a method of fabricating the device.
Another object of the present invention is to provide a semiconductor memory device that prevents undesired etching of the wiring lines (e.g., the bit lines) when the interlayer dielectric layer is selectively etched to form the contact holes for the lower capacitor electrodes, and a method of fabricating the device.
Still another object of the present invention is to provide a semiconductor memory device that increases the alignment margin between the conductive contact pads electrically connected to the lower capacitor electrodes and the wiring lines (e.g., the bit lines), and a method of fabricating the device.
A further object of the present invention is to provide a semiconductor memory device that makes it unnecessary to reduce the width of the wiring lines (e.g., the bit lines) for higher integration, and a method of fabricating the device.
A still further object of the present invention is to provide a semiconductor memory device that eliminates the possibility to increase the height of the wiring lines (e.g., the bit lines) for higher integration, and a method of fabricating the device.
The above objects together with others not specifically mentioned will become clear to those skilled in the art from the following description.
According to a first aspect of the present invention, a semiconductor memory device is provided. This device comprises:
(a) a semiconductor substrate;
(b) a first interlayer dielectric film formed directly on or indirectly over the substrate through at least one film;
the first interlayer dielectric film having a surface and contact holes;
(c) first conductive pads formed to fill the respective contact holes of the first interlayer dielectric film;
tops of the first pads being lower than the surface of the first interlayer dielectric film, forming gaps on the tops of the first pads in the respective contact holes of the first interlayer dielectric film;
the gaps being divided into a first group and a second group;
(d) wiring (or conductive) lines formed on the surface of the first interlayer dielectric film;
a top face and side faces of each of the wiring lines being covered with a dielectric;
the wiring lines being divided into a first group and a second group;
the wiring lines of the first group being electrically connected to the respective first conductive pads of the first group;
the wiring lines of the second group being electrically insulated from the respective first conductive pads of the second group;
(e) a second interlayer dielectric film formed on the surface of the first interlayer dielectric film to cover the wiring lines of the first and second groups;
the second interlayer dielectric film having contact holes; and
(f) approximately cylindrical lower capacitor electrodes formed in the respective contact holes of the second interlayer dielectric film;
the lower capacitor electrodes being contacted with the first interlayer dielectric film.
With the semiconductor memory device according to the first aspect of the present invention, the first conductive pads are formed to fill the respective contact holes of the first interlayer dielectric film in such a way that the tops of the first pads are lower than the surface of the first interlayer dielectric film. Thus, the gaps are formed on the tops of the first pads in the respective contact holes.
The wiring (or conductive) lines, the top faces and side faces of which are covered with the dielectric, are formed on the surface of the first interlayer dielectric film. The wiring lines of the first group are electrically connected to the first conductive pads. On the other hand, the wiring lines of the second group are apart from the respective first conductive pads, thereby electrically insulating the wiring lines of the second group from the first conductive pads.
Thus, the electrical short-circuit between the wiring lines of the second group and the respective first conductive pads for electrically connection to the lower capacitor electrodes can be prevented from occurring. This means that reduction of the width of the wiring lines (e.g., the bit lines) is unnecessary for higher integration; in other words, the possibility to increase the height of the wiring lines (e.g., the bit lines) is eliminated for higher integration.
Besides, the wiring lines of the second group are apart from the respective first conductive pads and therefore, the alignment margin between the wiring lines of the second group and the respective first conductive pads for electrically connection to the lower capacitor electrodes is increased.
In a preferred embodiment of the device according to the first aspect of the invention, there are additionally provided with
second conductive pads formed to fill the respective gaps of the first group; and
dielectric pads formed to fill the respective gaps of the second group
In this embodiment, the dielectric pads are formed to fill the respective gaps of the second group and thus, there is an additional advantage that undesired etching of the wiring lines (e.g., the bit lines) can be prevented when the interlayer dielectric layer is selectively etched to form the contact holes for the lower capacitor electrodes.
In this embodiment, it is preferred that the dielectric pads are made of a same material as the second interlayer dielectric film.
Preferably, the second conductive pads are made of a different material from the first conductive pads, thereby providing a sufficient etch selectivity between the material of the second conductive pads and the conductive pads.
In another preferred embodiment of the device according to the first aspect of the invention, there are additionally provided with dielectric sidewalls formed in the respective gaps of the first interlayer dielectric film in such a way as to inner walls (or inner faces) of the respective contact holes of the first interlayer dielectric film.
According to a second aspect of the present invention, a method of fabricating a semiconductor memory device is provided. This method comprises the steps of:
(a) forming a first interlayer dielectric film directly on or indirectly over a semiconductor substrate through at least one film;
the first interlayer dielectric film having a surface and contact holes;
(b) forming first conductive pads to fill the respective contact holes of the first interlayer dielectric film;
tops of the first pads being lower than the surface of the first interlayer dielectric film, forming gaps on the tops of the first pads in the respective contact holes of the first interlayer dielectric film;
the gaps being divided into a first group and a second group;
(c) forming wiring (or conductive) lines on the surface of the first interlayer dielectric film;
a top face and side faces of each of the wiring lines being covered with a dielectric;
the wiring lines being divided into a first group and a second group;
the wiring lines of the first group being electrically connected to the respective first conductive pads of the first group;
the wiring lines of the second group being electrically insulated from the respective first conductive pads of the second group;
(d) forming a second interlayer dielectric film on the surface of the first interlayer dielectric film to cover the wiring lines of the first and second groups;
(e) selectively etching the second interlayer dielectric film to form contact holes therein; and
(f) forming approximately cylindrical lower capacitor electrodes in the respective contact holes of the second interlayer dielectric film;
the lower capacitor electrodes being contacted with the dielectric covering the wiring lines.
With the method according to the second aspect of the present invention, it is obvious that the device according to the first aspect of the invention is fabricated.
In a preferred embodiment of the method according to the second aspect of the invention, there are additionally provided with the steps of
(g) forming second conductive pads to fill the respective gaps of the first and second groups;
(h) removing the second conductive pads in the respective gaps of the second group; and
(i) forming dielectric pads to fill the respective gaps of the second group from which the second conductive pads have been removed. The steps (g), (h) and (i) are carried out between the steps (b) and (c).
In another preferred embodiment of the method according to the second aspect of the invention, there is additionally provided with the step of
forming dielectric sidewalls in the respective gaps of the first interlayer dielectric film in such a way as to inner walls (or inner faces) of the respective contact holes of the first interlayer dielectric film

Semiconductor memory device and method of fabricating the same


A tool support device for a machine tool includes a housing disposed beside a tool spindle, a tool storage rack having a shaft rotatably attached to the housing, a plate secured to the shaft and rotatably received in the housing, a number of rollers disposed on the plate, an axle rotatably disposed in the housing and having a rotary member which includes a helical groove for engaging with the rollers and for rotating the plate and the shaft and the tool storage rack relative to the tool spindle, the tool support device includes a compact structure for suitably shielding and protecting the tool support device and for preventing the tool support device from being contaminated and damaged by dirt and cut chips.

1. Field of the Invention
The present invention relates to a machine tool, and more particularly to a machine tool including an improved tool support device having a compact and shielded configuration for suitably shielding and protecting the tool support device and for preventing the tool support device from being contaminated and damaged by dirt and cut chips.
2. Description of the Prior Art
Typical machine tools comprise a tool support device having a tool storage rack for supporting various tools or tool adapters at the outer peripheral portion thereof and having a rotating or driving device for rotating the tool storage rack relative to a machine base of the machine tools.
For example, U.S. Pat. No. 4,335,498 to Hague et al. discloses one of the typical machine tools comprising a spindle assembly associated with an indexing tool storage rack on which a number of distinct tools are stored.
However, a complicated tool carrier and transport means is developed and includes a complicated sprocket-and-chain system for rotating or driving the tool storage rack to rotate relative to the machine base of the machine tools such that the manufacturing cost will be greatly increased, in addition, the complicated sprocket-and-chain system will be exposed and will be easily contaminated and damaged by dirt and cut chips.
U.S. Pat. No. 4,776,081 to Okunishi et al. discloses another typical multi-spindle head-replacing machine tool comprising a number layers or guide rails for supporting or carrying a number of multi-spindle heads, and an elevator mechanism disposed sideways from the guide rails at a place offset from the movable rail for providing replacement of the multi-spindle heads between the guide rails.
However, similarly, the complicated guide rails may have a greatly increased manufacturing cost, and the complicated guide rails may also be exposed and will be easily contaminated and damaged by dirt and cut chips.
U.S. Pat. No. 6,102,840 to Xiao discloses a further typical tool changer for a machine tool and comprising a tool storage rack or disc magazine on which a number of distinct tools are stored and retained with retainers. The typical tool changer discloses the retainers for retaining the tools on the tool storage rack or the disc magazine, but failed to disclose the rotating or driving device for rotating the tool storage rack or the disc magazine relative to the machine base of the machine tools.
The present invention has arisen to mitigate and/or obviate the afore-described disadvantages of the conventional tool support devices for the machine tools.


Methods and systems are provided for reducing turbo lag in a boosted engine. A boost reservoir coupled to the engine may be charged with compressed intake air and/or combusted exhaust gas. The pressurized charge may then be discharged during a tip-in to either the intake or the exhaust manifold.

A boosted engine may offer greater fuel efficiency and lower emissions than a naturally aspirated engine of similar power. During transient conditions, however, the power, fuel efficiency, and emissions-control performance of a boosted engine may suffer. Such transient conditions may include rapidly increasing or decreasing engine load, engine speed, or mass air flow. For example, when the engine load increases rapidly, a turbocharger compressor may require increased torque to deliver an increased air flow. Such torque may not be available, however, if the turbine that drives the compressor is not fully spun up. As a result, an undesirable power lag may occur before the intake air flow builds to the required level.
It has been recognized previously that a turbocharged engine system may be adapted to store compressed air and to use the stored, compressed air to supplement the air charge from the turbocharger compressor. For example, Pursifull et al. describe a system in US 2011/0132335 wherein compressed air is stored in a boost reservoir and is dispensed into the intake manifold when insufficient compressed air is available from the turbocharger compressor. In particular, the boost reservoir is charged with fresh intake air and/or effluent from one or more unfueled cylinders. By dispensing extra compressed air from the boost reservoir to the intake manifold, torque corresponding to the dispensed air can be provided to meet the torque demand while the turbine spins up.
However, the inventors herein have identified potential issues with such a system. As one example, if the boost reservoir has a small volume, the boost air may be initially able to supply sufficient air to provide increased desired torque, but after the supply is depleted, such as at higher engine speeds, the turbine may still not be spun up, and thus torque may drop following the initial increase. Such performance may be worse than no compensation at all. Further still, the pressure of the air dispensed by the boost reservoir may not be sufficiently high to overcome the boost pressure, or the charge in the reservoir may be primarily exhaust gas and thus provide little excess oxygen for combustion to compensate the turbo lag.
Thus, at least some of the above issues may be addressed by a method for a turbocharged engine. In one embodiment, the method comprises, in response to a tip-in, reducing turbo lag by discharging pressurized charge from a boost reservoir to an exhaust manifold. In this way, pressurized charge is discharged into the exhaust manifold to rapidly increase exhaust pressure.
For example, during previous engine operation prior to the tip-in, the boost reservoir may already be filled with primarily combusted exhaust gas from the exhaust manifold. In response to the tip-in, the pressurized charge including the combusted exhaust gas may be discharged into the exhaust manifold. As a result, an exhaust pressure at the turbine may be increased to expedite turbine spool-up. By providing the charge to the exhaust manifold, it can be more easily spread over a longer duration as the turbine consumes the gas at a lower rate than the engine induction. In this way, the increased exhaust pressure can assist in compensating for turbo-lag, and maintain a continuously increasing engine output while responding to the tip-in.
It should be understood that the summary above is provided to introduce in simplified form a selection of concepts that are further described in the detailed description. It is not meant to identify key or essential features of the claimed subject matter, the scope of which is defined uniquely by the claims that follow the detailed description. Furthermore, the claimed subject matter is not limited to implementations that solve any disadvantages noted above or in any part of this disclosure.

This patent is subject to a terminal disclaimer.

Boost air management for improved engine performance


An improved series and/or parallel connection of transistors within a logic gate is presented. The improved connection is brought about by a sacrificial structure on which gate conductors are formed adjacent sidewall surfaces of the sacrificial structure. The sacrificial structure thereby provides spacing between the series-connected or parallel-connected transistors. Upon removal of each sacrificial structure, a pair of transistors can be formed by implanting dopant species into the substrate on opposite sides of the spaced conductors. Beneath what was once a sacrificial structure is a shared implant area to which two transistors are coupled either in series or in parallel. By depositing the gate conductor material and then anisotropically removing the material except adjacent the vertical sidewall surfaces, an ultra short gate conductor can be formed concurrent with other gate conductors within a logic gate.

1. Field of the Invention
This invention relates to transistors coupled in series and/or in parallel to form a logic gate and, more particularly, to a more accurate method for forming ultra-small gate conductors for each of the transistors.
2. Description of the Related Art
Fabrication of a metal-oxide semiconductor ("MOS") transistor is well known. The manufacture of an MOS transistor begins by defining active areas where the transistor will be formed. The active areas are isolated from other areas on the semiconductor substrate by various isolation structures formed upon and within the substrate. Isolation structures come in many forms. For example, the isolation structures can be formed by etching trenches into the substrate and then filling the trenches with a dielectric fill material. Isolation structures may also be formed by locally oxidizing the silicon substrate using the well recognized LOCOS technique.
Once the isolation structures are defined between transistor active areas, a gate dielectric is formed. Typically, the gate dielectric is formed by thermal oxidation of the silicon substrate. Thermal oxidation is achieved by subjecting the substrate to an oxygen-bearing, heated ambient in, for example, an oxidation furnace or a rapid thermal annealer ("RTA"). A gate conductor material is then deposited across the entire dielectric-covered substrate. The gate conductor material is preferably polycrystalline silicon, or polysilicon. The polysilicon layer is then patterned using a photolithography mask. The mask allows select removal of a light-sensitive material deposited entirely across the polysilicon. The material which is exposed can, according to one embodiment, be polymerized, and that which is not exposed removed. Selective polymerization is often referred to as the "develop" stage of lithography. The regions which are non-polymerized are removed using the etch stage of lithography.
A typical n-channel MOS ("NMOS") transistor employs n-type dopants placed into a p-type substrate. Conversely, a typical p-channel MOS ("PMOS") transistor comprises p-type dopants placed into an n-type substrate. The substrate is generally a single crystalline silicon structure. Regions of the substrate which receive dopants on opposite sides of the gate conductor are generally referred to as junction regions, and the distance between junction regions is typically referred to as the physical channel length. After implantation and subsequent diffusion of the junction regions, the distance between the junction regions becomes less than the physical channel length and is often referred to as the effective channel length ("Leff"). In high density designs, not only does the physical channel length become small, so too must the Leff. As Leff decreases below approximately 1.0 .mu.m, for example, a problem known as short channel effects ("SCE") becomes predominant.
Integrated circuits designed with relatively small physical channel lengths in densely patterned circuit areas require careful attention be directed to the mechanism by which the gate conductor is formed. For example, if a set of gate conductors within a densely patterned area become too small, then SCE will be predominant for those transistors. It might be that the small Leff transistors will prematurely turn on or will incur sub-threshold currents, more so than the other transistors--even though all transistors were designed to have the same physical channel length.
Slight variations in gate conductor length (i.e., physical channel length) even though not intentional may drastically alter the performance of a circuit design with relatively small physical channel lengths. This problem is significant in areas of densely patterned gate conductors such as, for example, logic areas containing numerous interconnected NAND and NOR gates. While it is desired that the series-connected and parallel-connected transistors within each logic gate be closely spaced to one another, it is equally desired that those transistors maintain a consistent channel length amongst themselves. If, for example, Leff of one parallel-connected transistor differs from that of the other parallel-connected transistor, then uneven turn-on transience may occur across the parallel connection.
The conventional lithography used to pattern closely spaced gate conductors (e.g., gate conductors of series-connected and parallel-connected transistors) suffers many drawbacks. For example, selective exposure is highly dependent upon accurately placing light on the light-sensitive material. Furthermore, light-sensitive material must consistently respond to the light with fine-line resolution. Any elevational disparity on which the polysilicon resides will result in slight changes in the point at which the light impinges on the light-sensitive material. This results in a variation in the polymerized/non-polymerized boundary.
It is therefore desirable to produce gate conductors which have an extremely small physical channel length to achieve high density logic cells. Although small in physical channel length, the desired gate conductors must be of consistent size across a somewhat elevationally disparate topography. In order to accurately produce a small gate conductor, a process must be used which avoids lithographic limitations of exposure, develop and etch cycles used in defining conventional gate conductors upon a gate dielectric. In order for a transistor which employs a relatively small gate conductor to achieve commercial success, improvements must be undertaken not only to the lithography procedure but also possibly to the junction itself. It may be necessary to incorporate a lightly doped drain ("LDD") region at the interface between the junction and the channel area underlying the gate conductor. As Leff decreases commensurate with gate conductor size, LDD implants must be carefully controlled so as not to encroach into the relatively short channel while at the same time source/drain implants formed within the junctions must be sufficiently concentrated to minimize hot carrier effects ("HCE").

Parallel and series-coupled transistors having gate conductors formed on sidewall surfaces of a sacrificial structure


A substrate cleaning method including rotating a substrate at least for a period, supplying a liquid to the front surface of the substrate and cleaning the substrate, and drying the substrate is provided. Said drying of the substrate includes: reducing a rotational speed of the substrate to a first rotational speed lower than a rotational speed for cleaning the substrate; starting to move a liquid supply position from approximately the center of the substrate towards a peripheral portion when the rotational speed of the substrate is reduced down to the first rotational speed; stopping liquid supply when the second rotational speed lower than the first rotational speed is reached; increasing the rotational speed from the second rotational speed; and supplying a gas towards the substrate while rotating the substrate at a higher rotational speed than the second rotational speed.

1. Field of the Invention
The present invention relates to a substrate cleaning method and a substrate cleaning apparatus, which are used to clean semiconductor wafers, substrates for flat panel displays (FPDs) such as glass substrates for liquid crystal displays (LCDs), and substrates for other devices.
2. Description of the Related Art
In a semiconductor device manufacturing process, a semiconductor wafer (hereafter, simply referred to as wafer) is cleaned using a predetermined chemical (cleaning liquid), and a cleaning process of removing a polymer and the like after contamination and etching processes of particles, organic contaminants, metal impurities and the like adhered to the wafer is then carried out.
A sheet-fed wafer cleaning apparatus that carries out a chemical process by holding the wafer on a spin chuck, supplying a chemical onto the front and back surfaces of the wafer either at rest or spinning, supplies a rinsing liquid such as purified water onto the wafer while spinning the wafer at a predetermined rotational rate so as to wash away the chemical, and then carry out a drying process while spinning the wafer is known as such wafer cleaning apparatus for carrying out that cleaning process.
As such a sheet-fed wafer cleaning apparatus, in the case of cleaning using a hydrofluoric acid chemical, for example, the rinsing liquid in the periphery of the wafer may be shaken off in a short period by centrifugal force since the wafer front surface is hydrophobic; however, the timing of shaking off the rinsing liquid at the wafer center where the centrifugal force is small is delayed, and thus watermarks may generate in the wafer periphery that has already dried while shaking off the rinsing liquid at the center. In addition, liquid drops may remain at the wafer center, causing particle generation.
In order to resolve such disadvantages, a technology scanning from the substrate center out towards the peripheral portion using a nozzle that sprays purified water and a nozzle that sprays inert gas is disclosed in Japanese Patent Application Laid-open No. 2001-53051. Such configuration allows nearly simultaneous progression of wetting the substrate with sprayed purified water, removing a purified water film using sprayed inert gas, and removing a water film from the substrate by rotational centrifugal force, and since it dries from the substrate center out towards the periphery spreading out in an approximate concentric circle, watermarks and contamination are prevented.
However, with such technology, since the wafer or substrate is basically spun at a high speed when drying, rinsing liquid may rebound from a chamber or the like of the apparatus at this time, and water drops may adhere to dried parts of the wafer, leading to particles and the like.
Furthermore, while there are various product wafers such as ones with patterns formed thereon or various films formed thereon, and a cleaning process in which generation of particles on various wafers having such hydrophobic parts is sufficiently suppressed is desired, however, adequate results are not yet necessarily achieved so far.


A seat cover assembly is arranged for adherence interior surface of a vehicular window permitting the extension and retraction of a seat cover over an associated vehicular seat adjacent the rear window.

1. Field of the Invention
The field of invention relates to seat cover apparatus, and more particularly pertains to a new and improved retractable seat cover apparatus arranged for the selective extension over a seat outer surface.
2. Description of the Prior Art
Seat cover structure is indicated in the prior art and exemplified by the U.S. Pat. Nos. 4,600,238; 4 790,592; 4,955,665; and 4,969,683.
The instant invention attempts to overcome deficiencies of the prior art by providing for a retractable seat cover structure arranged for retrofit and mounting to a vehicular rear window for extension selectively over an adjacent seat member and this respect, the present invention substantially fulfills this need.


A testing system for check-in control in wafer testing. The testing system comprises a testing tool, an optical character recognition (OCR) device, and a controller. The testing tool performs a testing process of an article. The OCR device reads optical characters disposed on the article. The controller, connected to the testing tool and the OCR device, automatically initiates a check-in process for the article according to the read optical characters.

The present invention relates to wafer testing and particularly to a system providing check-in control in wafer testing.
Certain product families require wafers to be 100% tested before sawing. This "on-wafer" test allows device characterization and assurance of known good die for higher integration level products and die sales. At the end of wafer fabrication, all devices on a wafer undergo a performance test to identify faulty ICs. This provides customers with the ability to receive parts that meet their specifications.
Before wafer testing starts, a check-in process is performed to confirm wafer lot ID and corresponding test recipe. In a conventional wafer testing system, a cassette is delivered to circuit probe (CP) equipment, and lot and equipment IDs are input to a manufacturing executive system (MES) manually. The MES receives the lot and equipment IDs and performs a check-in process accordingly. The check-in process confirms the equipment to perform testing for the wafer lot and generates a list of allowable test recipes for an operator to choose from.
Such conventional wafer testing has two major disadvantages.
First, manual check-in for wafers requires additional manpower expended in inputting data and selecting test recipes.
Furthermore, the process is based on lot ID, providing a lot-based recipe control. The lot-based recipe control cannot meet the needs of smaller orders for various products. Accordingly, wafers in the same lot are processed using the same test recipe. The single recipe limitation places restrictions on test operation, resulting in inefficiency in wafer testing.
Hence, there is a need for a wafer testing control system that addresses the shortcomings of the existing technology.

System and method for check-in control in wafer testing

Taiwan Semiconductor Manufacturing Co., Ltd.


A door control device for use on a non-fire side of a fire-door mounted in a door frame in a fire-door safety installation has a door closer assembly filled with a hydraulic damping fluid and attached to a non-fire side of the fire-door by at least one fastener; a door control arm pivotally connected to the door frame at a first end and to the door closer assembly at a second end; and the hydraulic damping fluid is one of a group of fire resistant hydraulic fluids.

This invention relates generally to hydraulic fluid damped door closers and more particularly to fire resistant door closers incorporating features which discourage transfer of fire through a fire door.
Fire doors are designed to protect against passage of fire from one room to another in a building. In the U.S., the National Fire Protection Association promulgates construction and installation standards for fire doors and windows as a publication, NFPA 80. Listed fire doors are classified in twelve categories, and protection of an opening depends upon the use of a listed fire door, a listed frame, listed door hardware, and a listed door control device as specified under each door type. Fire classifications for buildings are specified in model building codes, government regulations, and state and local building codes. Fire door classifications are expressed in hourly ratings according to the Standard for Fire Tests of Door Assemblies--UL 10B, ANSI A2.2, ASTM E--152, CSFM 43.7, CAN4-S104 (ULC-S104), UBC 43-2-1991, and NFPA 252.
The classifications are determined by exposing the doors to fire testing under standard conditions, and hourly ratings indicate the duration of exposure which the door can withstand, such as 4, 3, 2, 11/2, 1, 3/4 hours, and 30 or 20 minutes. It is permissible to test a fire door with special hardware and installation. This is usually done by door manufacturers who wish to establish a fire rated door, frame, door control, and hardware combination which can be specified in a building contract. It should be noted that, although there are several very similar fire door assembly tests in use throughout the world, there is no single international fire test standard.
Generally, fire doors must be maintained closed and latched or must automatically close and latch under a broad range of fire exposure conditions in order to properly serve their fire protective function. Thus, the door control device must assure that the door closes after it has been opened, and the latch must maintain the door latched. Today, all fire door tests are performed without a door control device.
Most currently used door control devices employ hydraulic damping technology to control opening and closing speed of the door. The hydraulic fluid is commonly a petroleum based oil which is relatively inexpensive, plentiful, non-corrosive, and compatible with a wide range of metals and other materials. However, petroleum oils have an auto-ignition temperature ranging between approximately 500 and 750 degrees F. and may contribute to the spread of the fire, if exposed to high temperatures, even when the door control device is mounted on the non-fire side of the door.
Within a few minutes after a fire begins, assuming it is adjacent to a fire door, the temperature of the door control device on the non-fire side of the door begins to increase by conduction through the door. This causes the hydraulic fluid to expand, to leak around the seals of the door control device, and to run down the door. Approximately 10 to 15 minutes after the fire starts, the temperature on the non-fire side of the door is high enough to cause auto-ignition of the leaking fluid. Even though the door and frame assembly may have a fire rating of 2 hours, or more, the fire has transferred through the door in less than 15 minutes.
The foregoing illustrates limitations known to exist in present door control devices. It would be advantageous to provide an alternative directed to overcoming one or more of those limitations. Accordingly, a suitable alternative is provided including features more fully disclosed hereinafter.

Door closer for the non-fire side of a fire-door safety installation


Measurements of acoustic velocities are made through a case borehole in the absence and presence of an applied magnetic field. A formation resistivity parameter may be estimated from differences in the acoustic velocities.

1. Field of the Disclosure
The present disclosure relates generally to geological exploration in wellbores. More particularly, the present disclosure describes an apparatus, a machine-readable medium, and a method useful for obtaining improved resistivity measurements downhole.
2. Description of the Related Art
A variety of techniques are currently utilized in determining the presence and estimating quantities of hydrocarbons (oil and gas) in earth formations. These methods are designed to determine formation parameters, including, among other things, the resistivity, porosity, and permeability of a rock formation surrounding a wellbore drilled for recovering the hydrocarbons. Typically, the tools designed to provide the desired information are used to log the wellbore. Much of the logging is done after the wellbores have been drilled. Moreover, a significant amount of the logging, such as in the case of resistivity measurements of the formation, is done after the wellbores have been cased. Typically the casing is made of an electrically conductive metal.
The oil industry has long sought to measure resistivity through casing. Such resistivity measurements are useful for at least the following purposes: locating bypassed oil and gas; reservoir evaluation; monitoring water floods; measuring quantitative saturations; cement evaluation; permeability measurements; and measurements through a drill string attached to a drilling bit. Therefore, measurements of resistivity through metallic pipes, and steel pipes in particular, are an important subject in the oil industry. See, for example, U.S. Pat. No. 4,820,989; U.S. Pat. No. 4,882,542; U.S. Pat. No. 5,043,688; U.S. Pat. No. 5,043,669; U.S. Pat. No. 5,075,626; U.S. Pat. No. 5,187,440; and U.S. Pat. No. 5,223,794 (Ser. No. 07/754,96). Resistivity measurements of the formation that are conducted through an electrically conductive metal casing present significant challenges. In particular, the very small magnitudes of the measured resistivity signals obtained via current existing galvanic methodologies represent critical problems. When using induced magnetic excitations, the skin effects of the electrically conductive metal casing require that low frequencies be used.
A method for measuring shear wave velocity in a cased borehole is disclosed in U.S. Pat. No. 6,850,168 to Tang et al. A transmitter is operated at a frequency below a cut-off frequency of a signal propagating through the drill collar so that the signal received at receiver is uncontaminated by the collar mode. The cut-off frequency is determined by the thickness of the drill collar. In a preferred embodiment, the transmitter is a quadrupole transmitter. The quadrupole mode in the collar has a cut-off frequency that is higher than the quadrupole mode in the formation, so that operating a quadrupole transmitter below this cut-off frequency gives a signal relatively uncontaminated by the tool mode.
Measurements based on the velocity of acoustic waves through an earth formation in the presence of an applied magnetic field can yield useful information concerning a parameter of the earth formation. As the wellbore casing is generally electrically conductive, there is a need for addressing the presence of the casing in electrical measurements.

Resistivity measurement through metal casing using magnetic field and magnetoacoustic phenomena


A pixel includes an organic light emitting diode, a first transistor that controls an amount of current supplied to the organic light emitting diode, a second transistor connected between a gate electrode of the first transistor and an initialization power supply, and a third transistor diode-connected between an anode electrode of the organic light emitting diode and the initialization power supply.

Various flat panel display devices capable of reducing weight and volume have been developed. As these flat panel display devices, there are a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), an organic light emitting display (OLED), and the like.
Among them, the organic light emitting display device, which displays an image using an organic light emitting diode generating light by recombination between electrons and holes, has advantages in which it has a rapid response speed and may be driven at a low power.

Pixel and organic light emitting display device using the same


An improved system for preparation and utilization of a litter box for use by small domestic animals which utilizes a litter material of macroporous silica gel in granular form, with the particle size ranging from between about 1 millimeter to about 10 millimeters, and with a moisture content below about 15%. Advantageously, the receptacle for retaining the litter is treated with a thin film of disinfectant prior to introduction of litter material.

The present invention relates generally to an improved system and method for preparing a litter box for use by small domestic feline animals particularly cats, the box providing a highly desirable litter material which is not only highly absorbent for water and urine, but which is also effective for the elimination of odors from the waste. The treatment of the container for the litter enhances the effectiveness of the litter and reduces the build up of bacteria which would otherwise be present in the litter and its surrounding container and environment.
In the past, litter boxes for domestic felines such as cats were typically filled with pulverulent solids or granules such as sand or the like. While such materials have been generally effective, they suffer from the disadvantage of being only modestly absorbent, and fail to be effective for elimination of odor. These materials are not effective for elimination or reduction of bacteria and live viruses which may otherwise be present and indeed thrive in the used litter. The present invention overcomes certain of these disadvantages by virtue of the ability of the improved litter system to absorb water and moisture from the urine, and also effectively eliminate odors created from the waste. Furthermore, felines find the material workable for their feet and pads, and do not find the litter material and the accompanying disinfectant to be undesirable.
In the past, systems and facilities for providing litter for domestic cats and the like have generally included sand as the base material. However, such materials have been generally considered unsatisfactory and uncomfortable to domestic casts for their ongoing use, due in particular to the compacting nature of a pack of sand, and the resulting inability to release the entrained moisture to the ambient.

Method of preparing a litter box for small domestic felines


The present invention provides a substance which inhibits the binding between E2/NS1 protein of hepatitis C virus and a cell infectious with hepatitis C virus, a cell expressing CD81, or CD81. The present invention can provide a novel medicament which has an anti-viral effects such as an inhibitory action against HCV infection.

In 1989, Chiron Corporation (U.S.A.) cloned a gene fragment of human hepatitis virus which had been heretofore referred to as "non-A non-B hepatitis virus," and the fragment was named "HCV" (SCIENCE, Vol. 244, 359–362, 1989). HCV is a virus, the genome of which is single strand (+) strand RNA. Besides Chiron Corporation, Shimotohno et al. of the National Cancer Center (Proc. Natl. Acad. Sci. USA, Vol. 87, 9524–9528, 1990) and Takamizawa et al. of the Research Institute for Microbial Diseases at Osaka University (J. Virol, Vol. 65, No. 3, 1105–1113, 1990) thereafter published the entire gene sequences of hepatitis C virus. Thereafter, it was found that HCV comprise three types of structural proteins, i.e., core protein, envelope 1 protein (hereinafter sometimes referred to as "E1" or "E1 protein") and envelope 2 protein (hereinafter sometimes referred to as "E2/NS1" or "E2/NS1 protein") and 6 types of non-structural proteins.
Once HCV is developed, acute hepatitis, chronic hepatitis, and hepatocirrhosis are highly likely to be developed, and the disease condition is eventually transited to liver cancer leading a patient to death. Conventionally, interferon, an anti-viral agent, has been typically used in the treatment. However, there are problems of variation in the therapeutic effects for each patient and side effects such as fever (J. Med. Virol., Vol. 42, 299–305, 1994) (Journal of Gastroenterology, Vol. 91, 995–1002, 1994).
Although a treatment using other anti-viral agents such as ribavirin has been also studied, this could not provide sufficient effect (Lancet, Vol. 337, 1058–1061, 1991), and therefore the development of a novel anti-HCV agent has been awaited.
HCV gene is considered to very easily undergo mutation and HCV, because of its high mutation ability, was presumed to escape from the immunity in the body of a patient. In particular, at the N-terminus of E2/NS1 of HCV, there is presumed to be a region of 25 to 30 amino acids, referred to as a "hyper variable region," which is rich in mutation, and Kato et al. deduce that an epitope of a human immune system is a hyper variable region (J. Virol., Vol. 67, No. 7, 3923–3930, 1993) (J. Virol., Vol. 68, No. 8, 4776–4784, 1994). More specifically, since the region which is recognized by the human immune system such as neutralizing antibody is in the hyper variable region, even though the neutralizing antibody is generated in the body of the infected patient, it is considered that the hyper variable region immediately undergoes mutation and viruses escape from the antibody. However, Ishii et al. have reported that an antibody which inhibits the binding between E2/NS1 and human T cell Molt-4 is present in a highly active state only in the blood of a patient who naturally recovered from HCV, and it is suggested that a humoral immunity is involved in the treatment of HCV in spite of the high mutation ability of HCV (Hepatology, Vol. 28, No. 4, 1117–1120, 1998).
In 1999, Chiron Corporation (U.S.A.) isolated CD81 as a protein on a cell surface to which E2/NS1 bound (SCIENCE, Vol. 282, 938–941, 1999). CD81 and E2/NS1 which were expressed in Escherichia coli, bound to each other in the same manner as reported by Ishii et al. and the serum of a patient who naturally recovered from HCV inhibited this binding. This result suggested that CD81 was a receptor of HCV.
From the foregoing, it has been considered that the use, as an agent, of a substance such as an antibody, which binds to an envelope protein that is presumably deeply involved in the infection of HCV to a cell and inhibits the binding to a human cell infectious with HCV, can inhibit HCV in the blood from infecting organs capable of being infected such as liver again, and can lead the HCV patient to the recovery. However, as yet, infection-inhibiting substances for HCV-derived diseases have not been sufficiently studied.

Japan as Represented by Director General of Agency of National Institute of Infectious Diseases


There is disclosed a clock gating structure for a synchronous circuit comprising a plurality of clocked state holding elements, the clocked gating structure including at least one full-cycle clock gating cell and at least one half-cycle clock gating cell, and a method for designing and controlling such.

The model of a synchronous circuit is that the circuit is composed of logic blocks, which compute a value after a finite delay, and clocked state-holding elements such as D-type flip-flops (DFFs). Each computational step takes one clock period, and at the end of every clock period, every DFF in the design has its state re-assigned in dependence on the computational step taken place. In dependence on the computational step, the reassigned state may in fact be the same as the previous state.
Clocked state elements such as D-type flip-flops (DFFs) are well-known in the art, as is the construction of such elements. The clock input to a DFF element typically has about six times the capacitance of a normal gate if the internal gates of the element are included, and thus switching the clock input takes about six times the power that it takes to switch a typical gate in the circuit.
The clock input to a clocked state element also changes more frequently than any other wire in a circuit. The clock line changes state twice per clock cycle, a switching activity of 200%, whereas a reasonable upper bound for the switching activity of all other nodes in the circuit is about 30%. This implies that driving the clock input to a clocked state element is about 40 times (6*(200/30)) as expensive as driving any other gate input in the circuit. If it is assumed that 10% of the gates in a design are DFFs, which is a reasonable figure for a well-pipelined modern design, this equates to 70% of the total clock power being spent on clocking the DFFs.
As a consequence of the above disadvantages, clock gating is a well-known technique in which transitions on the clock wire to certain registers are blocked when it is known that those registers are not active. By preventing a rising and falling transition on a bank of registers whenever the output of that register will not change anyway, i.e. it is not active, a significant fraction of a circuits power consumption can be saved.
Automated tools exist in the art for designing synchronous circuits, which include tools for designing clock gating. The current state-of-the-art in automatic clock gating tools performs a technique known as RTL (register transfer level) clock gating, because it operates at the register transfer level. An RTL description is a structural abstraction of a synchronous circuit into programming language, like constructs, which can be easily translated (or synthesised) into a schematic by a tool such as a design compiler tool, which tools are well-known in the art.
An example of an RTL description is the following:
module test ( D, start, A, B, clock );output[7:0]D;input[7:0]A, B;inputstart;reg[7:0]C, D;always(@posedge clock)beginC <= A + B;if (start) D <= 0;else if (C<D) D <= C;endendmodule
In the example above, on every clock tick, A is added to B and placed in C. Also, a comparison is made between C and D. If start is true then D is set to zero, if start is false and C is less than D, then D is set to whatever C is, and otherwise D is left alone.
When this RTL code is synthesized (converted from a textual description to a circuit), the assumption that all DFFs are clocked on every cycle means that D cannot be just left alone —it must be assigned a value, and that value needs to be its current output. This wastes energy clocking the same value back in to the register, i.e. the current value is clocked back into the register as its new value.
A tool that performs RTL level clock gating has a way to avoid this wasted clock energy. It can see from the RTL that there is a condition under which the register may be left alone, as its state does not change; this is used to gate (i.e. to turn off) the clock to the register. Extra gates are inserted between the global clock pin and the clock inputs to the registers making up the register, which block the rising and falling clock edge if start is false and C is greater than or equal to D. If the register is only clocked when either (start=1) or (start=0 and C<D), then the multiplexer can be simplified to just consider the value of start, because this differentiates between the two remaining conditions. In this way, the logic for the register is simplified.
Clock gating as described above adds gates to the circuit, and these extra gates add both area and power. If a designer is not careful, the extra clock gating hardware can consume more power than is saved by limiting the clocking of the register. For this reason, existing clock gating tools specify a lower limit on the size of registers that can be gated. For example, a tool may apply a rule such as "only gate when the register is four bits wide or more". Area can be affected, although this can be either up or down. Removing the "D stays the same" case in the example above saves area, but adding the clock gating hardware costs area.
The style of clock gating that is usually used is termed full-cycle gating. This gating style adds a transparent latch and an AND gate to the clock wire, which is expensive because clocking a latch usually takes about two-thirds of the power of clocking a DFF (about 4 standard input loads) plus another single load for the AND gate. Effectively, this style adds almost an entire new DFF load to the clock, which is acceptable if a large bus is unused for most of the time. On the other hand, if a four-bit bus is unused 20% of the time, the extra gating hardware will actually take more power than it saves. The combination of the transparent latch and AND gate is often referred to as a "clock gating cell".
The alternative to full-cycle gating is termed half-cycle gating. In half-cycle gating only a single gate is attached to the clock, an OR gate, and so this arrangement would still save power in the case of a four-bit bus unused 20% of the time.
The timing behaviour of half-cycle clock gating is worse than full-cycle clock gating. A half-cycle gate used to create a rising clock edge needs to know on the previous falling edge whether the gating will occur or not. Assuming a typical mark-space ratio of 50%, this gives only half a cycle in which to make a decision. A full-cycle gate starts low, so it can wait to make a decision until the rising clock edge arrives.
The contrast between full-cycle and half-cycle gating is not well known, even though most experienced designers are aware of the two different styles. They are seen as alternative ways to achieve the same end, but there are very definitely advantages and disadvantages to each: full-cycle is safer from the timing point of view but consumes more power and a fair amount of area; half-cycle must be used with caution to avoid breaking timing, but is lightweight, consuming little power and little area.
Current RTL-level clock-gating tools require the designer to specify the kind of gating they require up front. If the designer chooses half-cycle gating, this would slow down the circuit by a factor of two, so the designer in practice always chooses full-cycle gating. Half-cycle and full-cycle gates have never been mixed in a single design, because their interactions are in general not well understood. Current design techniques thus produce a design with complete full-cycle gating, and thus all clock gating cells are implemented with maximum size, consuming maximum circuit area and power.
Current RTL-based clock gating tools create at most a single gating expression for every register in the design, so they insert a single full-cycle gating cell between the clock and a register. Thus current designs provide a number of full-cycle gates corresponding to the number of registers in the design, thus potentially each register takes up additional space and power in the implementation of clock gating. Methods have been suggested for gating clocks at a finer grain than at the RTL register level. Lang, Musoll, Cortadella, 'Individual Flip-Flops with Gated Clocks for Low Power Data Paths', IEEE Trans on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 44, no. 6, June 1997 has suggested using an XOR gate to directly compare the D input and Q output of an individual DFF element, and to gate the clock locally, at the element level, if the input and output are the same. The clock gate must be a half-cycle gate to save any power in this context, and this places unwelcome restrictions on either the cycle time (which almost doubles) or the mark-space ratio of the clock (which causes its own problems). Lang et al. also use NAND and OR gates to substitute for an XOR gate in the clock gate cell, if such gates would save more power. Although this approach is technically interesting, its drawbacks mean that it has been limited to academia, and has never been accepted in commercial design environments. The approach teaches that each individual gate which is to be clock gated should be connected to an individual clock gate, which introduces, in theory, multiple clock gates per register. Lang et al therefore does not offer an approach which can be implemented practically in a complex circuit design tool.
Thus although Lang et al offers an alternative to the conventional RTL approach, in analyzing a forced gating technique at a lower level, it does not offer a practical implementation.
It is an aim of embodiments of the present invention to provide an improved technique which addresses certain ones of the above-stated problems.


A circuit card clamp (300) including a base member (316), at least one first wedge member (446), and a thermally conductive membrane (350). The base member has an elongated shape configured for insertion in a circuit card chassis slot (106). The first wedge member is movable relative to the base member in response to a first actuator (304) for engaging the circuit card chassis slot. The thermally conductive membrane is coupled to the base member and the first wedge member. The thermally conductive membrane has slack for permitting the first wedge member to move relative to the base member between a first clamped position and a second unclamped position. The thermally conductive membrane defines a thermal conductive path (206) between a circuit card (104) and the chassis slot for releasably securing a circuit card in the circuit card chassis slot.

1. Statement of the Technical Field
The invention concerns clamping mechanisms, and more particularly, clamping mechanisms for fastening printed circuit boards or printed circuit cards to chassis.
2. Description of the Related Art
Traditionally, circuit card clamps have been used for fastening circuit cards within a slot of a chassis such as a heat exchanger, heat sink, or cold plate. For example, U.S. Pat. No. 4,775,260 to Kecmer (hereinafter "Kecmer"), U.S. Pat. No. 5,071,013 to Peterson (hereinafter "Peterson"), and U.S. Pat. No. 4,298,904 to Koenig (hereinafter "Koenig") describe circuit card clamps consisting of threaded rods with wedge-shaped bodies disposed thereon. A circuit card clamp coupled to a circuit card can be inserted into a chassis slot. Subsequently, the threaded rod can be rotated with a tool (i.e., torque wrench) in order to shorten the length of the circuit card clamp. By shortening the circuit card clamp, the wedge-shaped bodies are compressed thereby creating an increase in the circuit card clamp's width. As a result, a clamping force is exerted by the circuit card clamp securing the circuit card to the chassis.
The above described circuit card clamps suffer from certain drawbacks. For example, if the circuit card clamp is actuated so that it exerts a clamping force on the circuit card, then the circuit card is in contact with at least one wall of the chassis. In this scenario, thermal energy generated by the circuit card is passed to the chassis, thereby providing conduction cooling. However, the conduction cooling provided by such a clamp configuration is insufficient for Versa Module Eurcard (VME) cards having a fifty (50) watts power dissipation design. Further, the clamping forces exerted by the above described circuit card clamps are insufficient for adequately fastening a circuit card to a chassis to prevent loosening of the circuit card when exposed to external forces (such as vibration forces).
In view of the forgoing, there is a need for a wedge assembly that is able to provide improved conduction cooling (or thermal performance). The wedge assembly also needs to provide an improved clamping force for adequately fastening a circuit card to a chassis.


A bidirectional communication module jack assembly is disclosed to include a front bracket, a rear bracket fastened to the front bracket, and a plurality of jack modules mounted in between the front bracket and the rear bracket. The front bracket and the rear bracket cause a sense of beauty while giving a maximum protection to the jack modules. Except the use of the front bracket to support the jack modules, the rear bracket enhances the positioning of the jack modules and supports the pressure of module plugs and their electrical wires that are connected to the jack modules from the back side.

The present invention relates to bidirectional communication module jack assembly and more particularly, to an improved structure of bidirectional communication module jack assembly, which causes a sense of beauty while giving a maximum protection to the jack modules against pry attacks. The special structural design of the bidirectional communication module jack assembly requires less installation time and labor, thereby saving much the cost.
FIG. 1 illustrates a bidirectional communication module jack assembly according to the prior art. As illustrated, the bidirectional communication module jack assembly comprises a front base frame 5, which has plurality of chambers 51, and a plurality of jack modules 6 respectively mounted in the chambers 51. Each jack module 6 is comprised of a first shielding frame 71 (see FIG. 2), a second shielding frame 72 (see FIG. 2), and 12 pcs bidirectional module jacks 61 (see FIG. 3). The bidirectional module jacks 61 are inserted into the first shielding frame 71 and abutted against one another, and then the second shielding frame 72 is capped on the first shielding frame 71 to secure the bidirectional module jacks 61 in place. Further, the second shielding frame 72 has a plurality of springy hooks 721 that are fastened to respective hook holes 52 on the front base frame 5 (see FIG. 1).
This design of bidirectional communication socket assembly still has drawbacks as follows:
1. When module plugs (not shown) are inserted into the receiving holes 614 at the front side of the bidirectional module jacks 61 of the jack modules 6, the front base frame 5 bear the gravity weight of the cables of the module plugs. However, when module plugs (not shown) are inserted into the rear receiving holes 614 at the rear side of the bidirectional module jacks 61 of the jack modules 6, bidirectional communication module jack assembly has no means to bear the gravity weight of the cables of the module plugs, and the downward pressure of the gravity weight of the cables of the module plugs may cause disconnection of the junction between the jack modules 6 and the front base frame 5.
2. The bidirectional communication module jack assembly has no means to protect the rear side of the jack modules 6, and the rear side of the jack modules 6 can easily be opened or broken by an evil person.
3. The bidirectional communication module jack assembly has many component parts extended out of the rear side, obstructing the sense of beauty of the assembly.
4. Each bidirectional module jack 61 is comprised of a mini circuit board (not shown), terminal holder 611, conducting terminals 612, and a housing 613. The assembly procedure of each bidirectional module jack 61 is complicated. Further, it requires much time and labor to install total 12 pcs bidirectional module jacks 61 in the first shielding frame 71. After installation of the 12 pcs bidirectional module jacks 61 in the first shielding frame 71, the 2 pcs bidirectional module jacks 61 may be forced out of position accidentally, and the worker must aim the second shielding frame 72 at the 12 pcs bidirectional module jacks 61 and the first shielding frame 71 accurately before capping the second shielding frame 72 onto the first shielding frame 71. If the front base frame 5 has 4 chambers 51, there are total 48 pcs bidirectional module jacks 61 to be installed, requiring much installation time and labor.
The present invention has been accomplished under the circumstances in view. According to one aspect of the present invention, the bidirectional communication module jack assembly comprises a front bracket, a rear bracket fastened to the front bracket, and a plurality of jack modules mounted in between the front bracket and the rear bracket. Except the use of the front bracket to support the jack modules, the invention uses the rear bracket to enhance the positioning of the jack modules and to support the pressure of module plugs and their electrical wires that are connected to the jack modules from the back side. Further, the rear bracket gives a maximum protection to the rear side of each jack module against pry attacks.
According to another aspect of the present invention, the front bracket and the rear bracket cause a sense of beauty while giving a maximum protection to the jack modules.
According to still another aspect of the present invention, the front housing, rear housing and circuit boards for each jack module can easily be assembled with less time and labor, saving much installation cost.

Bidirectional communication module jack assembly


The invention includes a method in which a semiconductor substrate is provided to have a memory array region, and a peripheral region outward of the memory array region. Paired transistors are formed within the memory array region, with such paired transistors sharing a source/drain region corresponding to a bitline contact location, and having other source/drain regions corresponding to capacitor contact locations. A peripheral transistor gate is formed over the peripheral region. Electrically insulative material is formed over the peripheral transistor gate, and also over the bitline contact location. The insulative material is patterned to form sidewall spacers along sidewalls of the peripheral transistor gate, and to form a protective block over the bitline contact location. Subsequently, capacitors are formed which extend over the protective block, and which electrically connect with the capacitor contact locations. The invention also includes semiconductor constructions.

A continuing goal of integrated circuit fabrication is to increase the number of devices within a given amount of semiconductor real estate (in other words, to increase the level of integration). Electrical shorting between adjacent regions becomes increasingly problematic with increasing levels of integration. Accordingly, it is desired to develop new methods for creating highly integrated devices.

Methods of forming semiconductor constructions


A zoom finder optical system of real image type of the present invention is provided with an objective lens system of a positive refractive power, a condenser lens of a positive refractive power and an eyepiece system of a positive refractive power from an object side. The objective lens system includes from the object side a first lens unit of negative refractive power, a second lens unit of a negative refractive power, a third lens unit of a positive refractive power and a fourth lens unit of a positive refractive power.

1. Field of the Invention
The present invention relates to a zoom finder optical system, and more specifically, to a real-image zoom finder optical system for use in a lens shutter camera and the like.
2. Description of the Prior Art
In recent years, with the appearance of smaller-size, higher-zoom-ratio and wider-angle (because of the popularity of panorama-size photos) lens shutter cameras, similar specifications are required for finder optical systems used in the lens shutter cameras. Specifically, wide-angle, high-zoom-ratio (ranging from wide angle to telephoto) and small-size finder optical systems are required.
The conventionally used high-zoom-ratio finder optical system is a real-image finder optical system comprising from the object side a positive objective lens system, a positive condenser lens and a positive eyepiece system. As a zoom finder optical system of this type, an optical system has been proposed having an objective lens system provided with a special feature.
For example, with a zoom finder optical system of a type where the objective lens system is of positive, negative, positive configuration and zooming is performed by moving the second and third lens units (Japanese Laid-open Patent Application No. H3-87803), a compact finder optical system with a high zoom ratio is realized.
However, in view of the realization of a wide angle (corresponding to an angle of view of 28 mm) and a high zoom ratio (3.times. or higher), in an objective lens system whose first lens unit has a positive refractive power, although an appropriate refractive power arrangement is obtained paraxially, in actuality, the necessary effective aperture of the first lens unit is too large at the shorter focal length condition (wide angle condition), so that it is impossible to secure the necessary thickness of the edge of the positive lens.
Therefore, to realize a wide angle and a high zoom ratio, it is desirable for the first lens unit of the objective lens system to have a negative refractive power. As a zoom finder optical system of such a type, optical systems are known which are of negative, positive, positive configuration (Japanese Laid-open Patent Application No. H1-116616) or of negative, positive configuration where zooming is performed by moving the first and second lens units constituting the objective lens system.
Generally, lenses provide a light beam having a large angle of view with a large amount of aberration. In particular, distortion is generated in proportion to the cube of the angle of view. Therefore, since the angle of view is large at the shorter focal length condition, a large negative distortion is generated by the first lens unit. Conversely, at the longer focal length condition (telephoto condition), since the angle of view of the light beam incident on the first lens unit is small, distortion is hardly generated. For example, in the case of 3.times. zoom, the angle of view is also tripled, so that distortion generated by the first lens unit at the longer focal length condition is 1/27 times that at the shorter focal length condition.
Because of this, in the optical systems of the type having the objective lens system of negative, positive, positive configuration (Japanese Laid-open Patent Application No. H1-116616) or of negative, positive configuration, a large negative distortion is generated by the first lens unit due to the increase in angle of view at the shorter focal length condition, so that the difference between distortion at the shorter focal length condition and distortion at the longer focal length condition (hereinafter referred to as "distortion difference") increases to a impermissible level. Thus, if the realization of a wide angle and a high zoom ratio is intended with this type, a large negative distortion is generated by the first lens unit only at the shorter focal length condition, so that aberration correction is difficult.
The present applicant disclosed in Japanese Laid-open Patent Application No. H4-51108 a zoom finder optical system of a type where the objective lens system is of negative, negative, positive configuration and zooming is performed by moving the second and third lens units.
This negative, negative, positive type objective lens system is of an arrangement where the refractive power is divided into two by dividing into two units the negative first lens unit of the negative, positive type objective lens system, so that the effect of distortion generated at the shorter focal length condition is restrained to reduce the distortion difference. This is because in the negative, negative, positive type objective lens system, the distortion generated by the first lens unit decreases since the refractive power of the first lens unit is small compared to the negative, positive type objective lens system. In addition, in the negative, negative, positive type objective lens system, since the angle of view is reduced by the first lens unit, the distortion generated by the second lens unit is also reduced.
As described above, the objective lens system of negative, negative, positive configuration can realize the wide angle. However, since the refractive power of the third lens unit increases too much if the high zoom ratio is realized, a large aberration is generated at the longer focal length condition where the light beam passes the outermost periphery of the lens (in other words, the aperture of the entrance pupil of the lens is large). In particular, spherical aberration is generated in proportion to the cube of the entrance pupil.


A system and method of designating edit information for an original document. The system includes a mechanism for designating a location on the original document while the document is in a document feeder tray. The mechanism does not deface the original document.

1. Field of the Invention
The present invention relates to system and method for editing a document image, and more particularly to a system and method for designating edit information for a document in the document handling mechanism of a printing apparatus.
2. Discussion of the Related Art
Certain types of printers are capable of producing an altered copy of an original document, as well as an identical copy of the original document. In order to define an area to be altered, coordinates on the document must be specified. One method of specifying coordinates employs a special color pen. A user may draw an area on an original document and the printer then detects an area defined by dye from the special color pen. A disadvantage of this method is that it defaces the original document or requires the making of a copy of the original for marking with the special color pen. Copying a copy results in an image of less than optimum quality and involves additional manual steps.
Another method of specifying coordinates employs an edit pad. For example, the NP 3525 Copier manufactured by the Canon Corporation employs an edit pad that allows selected area on a document to be colored, highlighted or deleted. The disadvantage of the traditional edit pad method is that manual steps may be required to separate an original document from other documents and place the separated document on the edit pad.

System and method for editing a document image


A system and method for manufacturing a power bus assembly is provided. The power bus assembly includes a first conductive sheet configured to receive a positive charge and distribute the positive charge to a plurality of connection points formed thereon. The power bus assembly also includes a second conductive sheet configured to receive a negative charge and distribute the negative charge to a plurality of connection points formed thereon. Additionally, the power bus assembly includes an insulating sheet arranged between the first conductive sheet and the second conductive sheet to electrically isolate the first conductive sheet from the second conductive sheet. A plurality of vice fasteners are included to secure the first conductive sheet, the second conductive sheet, and the insulating sheet together to form the power bus assembly.

The present invention relates generally to power bus systems and, more particularly, to a bus assembly for DC bus links used in motor drive units and the like that can be assembled using a plurality of clamping fasteners. The clamping fasteners are designed to secure the multiple layers of the DC bus together without the need for adhesives.
Often, power delivered from a power source or supply is not properly conditioned for consumption. For example, power plants are linked to power consuming facilities (e.g., buildings, factories, etc.) via utility grids that are designed to be extremely efficient at delivering massive amounts of power. To facilitate efficient distribution, power is delivered over long distances as fixed frequency three-phase alternating current (AC) power. Similarly, in modern vehicle systems, especially hybrid vehicle systems, power management and storage systems handle power in various forms, such as those that are desirable for storage and those that are desirable for consumption. In either case, the power must typically be converted or "conditioned" prior to consumption.
For example, motors and their associated loads are one type of common inductive load employed at many consuming facilities that require power conditioning. When a motor is the consuming point, power "conditioning" systems are utilized to convert the fixed frequency AC power delivered over utility grids to a form suitable for driving the motor. To this end, power conditioning for motor systems typically include AC-to-DC (direct current) rectifiers that convert the utility AC power to DC power applied to positive and negative DC buses (i.e. across a DC link). The power distributed across the DC buses is then converted, for example by use of an inverter, to AC power designed to drive the motor.
Though the above-described system was described with respect to power conditioning for motor systems, such DC bus systems are utilized in a wide range of systems and applications. That is, regardless of the particulars of the consuming components or ultimate application within which the DC bus is employed, DC bus assemblies are often utilized to distribute DC power across various components for reconditioning, storage, and/or consumption.
To create a DC bus assembly, a variety of laminates or adhesively bound components are utilized. For example, a first sheet of copper or similar conductor is arranged as the negative bus line. A second sheet of copper or other conductor is then arranged over the negative bus line and separated by an insulator to serve as the positive bus line. Additional layers that are separated by insulation layers may then be arranged over or between the positive and negative bus layers.
In most applications, the DC bus assembly must be structurally sound so that various components can be securely mounted to the DC bus assembly. That is, each layer in the DC bus assembly must be joined to form a composite structure capable of at least partially supporting components mounted to the assembly. Furthermore, the DC bus assembly must meet various environmental and operational tolerances, such as vibration and heat tolerances. For example, in the above-described example of a motor drive system, typically, the DC bus must have sufficient structural integrity to support both the rectifier and the inverter, as well as various additional components, such as capacitors, water cooling systems, and the like. Furthermore, the DC bus must be able to sustain its structural integrity when subjected to vibrations and high temperatures often associated with motor systems.
To create a DC bus assembly that is suitable for the desired application (i.e. has suitable structural integrity and meets the vibration and temperature constraints), the layers (conductors and insulators) are typically bonded together using adhesives. That is, each conductive layer is bonded to each adjacent insulating layer, such that the assembly is formed by alternating layers of conductor and insulator that are all bonded through adhesives. These laminated DC bus structures provide noise cancellation properties and have become commonplace in power conversion equipment.
While such manufacturing methods have long been employed to great success with meeting the structural requirements needed to withstand vibrations and temperature changes associated with a wide variety of environments, they are rather costly. In particular, the process of aligning and gluing the individual layers requires a high degree of skill because the manufacturer must carefully align the adjacent layers to ensure that adjacent conductors; will not be in contact and will not later move into contact when the separating insulator is subjected to heat and vibration.
As such, the cost of more complex bus structures is often prohibitive. For example, a "3D" bus structure, where the bus sheets are bent to extend into multiple planes, is often cost prohibitive because the process of correctly aligning and gluing adjacent layers simultaneously across multiple planes is extremely difficult, if not impossible. Therefore, though such a 3D bus structure could be advantageously utilized in a wide variety of systems since it would permit the size and shape of the bus to be more compact and/or adapted to fit into non-traditional environments, it is generally foregone in favor of the traditional flat or planar bus design due to cost and quality control constraints.
Therefore, it would be desirable to have a system and method for creating Et power bus assembly that reduces manufacturing costs and complexities, is more adaptable to various bus designs, and provides increased structural integrity.

Adhesive-less DC bus system and method for manufacturing


An apparatus or a system having an integrated circuit (IC) or a microprocessor with an operational circuit, a proxy circuit and a voltage regulator. In various embodiments, the operational circuit operates at a first frequency, and the proxy circuit outputs a periodic signal at a second frequency reflective of a potential of the first frequency. The periodic signal is provided to the voltage regulator controller, which conditionally regulates voltage applied to the IC or microprocessor, based at least in part on the second frequency.

The present invention is related to the field of integrated circuits. More specifically, various aspects of the present invention are related to the detection of the potential of the operational frequency of an integrated circuit, and regulation of voltage applied to the integrated circuit, based at least in part on the detection.
Advances in integrated circuit (IC) technology have led to significant increases in the operational frequencies of IC. Typically, a manufacturer of an IC designs and guarantees the IC to operate properly up to a specification maximum operational frequency, if voltage supplied to the IC is within a targeted voltage range. Generally, to reduce power consumption, it is desirable to operate the IC near the lower end of the targeted voltage range.
In addition to being dependent on the applied voltage, the operational frequency of an IC may also be dependent at least in part on the temperature of the IC, the age of the IC, and/or other factors. Thus, various environmental limits, such as, but not limited to, temperature, voltage and so forth, are specified to facilitate a system designer to manage the usage of the IC, to ensure it functions properly. These environmental limits are typically conservatively specified (guard banded) to accommodate among other things, aging of the IC. The level of conservatism (or magnitude of the guardband) varies from manufacturer to manufacturer, depending in part on the quality experience of the manufacturer.

Regulating voltage applied to an integrated circuit and proxy frequency


A darning width adjusting device for a sewing machine includes a lower knife holder supported by a sewing machine frame such that a moving position of the lower knife holder is adjustable in a direction orthogonal to a cloth feeding direction, a thread-sliding piece which sets a darning width by picking up a thread at a tip thereof in the vicinity of a stitch point, a thread-sliding piece holder supported by the sewing machine frame such that a moving position of the thread-sliding piece is adjustable in the orthogonal direction to the cloth feeding direction, a thread-sliding piece adjusting means for adjusting the moving position of the thread-sliding piece, and a lower knife holder adjusting means for adjusting the moving position of the lower knife holder to a position exceeding a outside marginal position of the thread-sliding piece.

1. Field of the Invention
The invention relates to a darning width adjusting device for a sewing machine such as an overlock machine.
2. Description of the Related Art
A conventional over-edge sewing machine includes an upper knife and a lower knife, both cutting a workpiece cloth at upstream side of a stitch point in a cloth feeding direction, a lower knife holder provided movably in a direction orthogonal to the cloth feeding direction and holding the lower knife, a thread-sliding piece supported on the lower knife holder and adjusting a darning width by engaging a tip portion of the thread-sliding piece with a thread in the vicinity of the stitch point, and a positioning device positioning the lower knife in the direction orthogonal to the cloth feeding direction (for example, see JP-A-2005-000401).
However, in the conventional over-edge sewing machine, since the thread-sliding piece is supported on the lower knife holder, when the lower knife holder is moved outward to assure a wide cloth cutting width, an upper looper moving from underside of a throat plate toward a sewing needle and the thread-sliding piece interfere with each other (for example, see FIG. 6). Thus, there is an inconvenience that the outward moving amount of the lower knife is limited.
As a result, when over-edge sewing is carried out on an elastic cloth for example, a width from the stitch point to a cutting portion of a workpiece is insufficient so that a thread reeling piece cannot follow the expansion and contraction of the cloth (e.g., the cloth after being cut contracts and causes thread redundancy). Consequently, there is a problem that the darning cannot be suitably aligned with the cloth end.
In order to overcome the above problem, a thread tensioner can be operated to adjust a tension of the thread, thereby dealing with a change in the darning width. However, this leads to a serious problem that an adjusting operation is troublesome so that considerable labor is required for an operator and an operating efficiency is lowered,

Darning width adjusting device for sewing machine


There is provided a target game adapted to receive tokens into apertures having associated scores. The target game includes a horizontal playing surface having a plurality of apertures, and a vertical playing surface disposed at a back edge of and atop the horizontal playing surface. The vertical playing surface includes a plurality of apertures.

There exist many target games of various configurations and rules. One game in particular—Sapo or Toad (or Frog)—is a toss-style game that is played by tossing tokens onto a horizontal surface, constituting a playing surface, of a generally wooden box structure having apertures of different values in the horizontal surface for receiving the tokens. The object of the game is to toss the tokens so that they fall through highest-valued apertures on the playing surface.
The apertures have different point values depending on their difficulty. One aperture, generally having the highest point value, is protected by the Sapo, which is the most difficult aperture as the token must be tossed into the Sapo's mouth to earn points. Tokens that fall through the apertures slide through channels toward the front of the game and are collected or received in open scoring bins, with the scoring bins being associated with the particular apertures on the playing surface. To increase the requisite skill level and scoring potential, larger number of apertures, smaller sizes thereof and obstacles (such as spinning wheels) have been employed.
Generally, from the playing surface there rise a pair of low-profile opposing sidewalls and a low-profile back wall, which provide a boundary about the playing surface. This boundary provides little containment of tokens that are tossed at the playing surface, as these tokens may skip on the playing surface and bounce off the playing surface over the boundary.
Furthermore, the open bins provide no protection from tokens errantly tossed directly into the scoring bins. Additionally, tokens that may have rolled or vacillated on their edges sliding through the channels into the scoring bins instead of sliding flatly may errantly bounce out of the open bins.
As improved game play and enjoyment are of importance in the target games, it would be advantageous to increase requisite skill level, ways of scoring and containment to improve the play and enjoyment of the game of Sapo.