An amplifying type solid-state imaging apparatus includes an amplifying type photoelectric conversion device. The device including a transistor for accumulating a charge generated by incident light as a signal charge in a charge accumulation region proximate to the surface of the semiconductor substrate and for outputting a signal in accordance with the accumulated signal charge, and a resetting section provided adjacent to the transistor for performing a resetting operation. The signal charge accumulated in the transistor is discharged from the charge accumulation region based on an applied voltage. The device further includes a signal line for carrying a signal output from the transistor, a clamp circuit for clamping the voltage of the signal line at a first voltage, a sample hold circuit for sample-holding a difference signal representing a difference between the first voltage and a second voltage output from the transistor after the resetting operation, an output line connected to the sample hold circuit, and a controlling circuit for controlling the clamp circuit and the sample hold circuit and for reading out the difference signal held in the sample hold circuit to the output line.

1. Field of the Invention
The present invention relates to an amplifying type solid-state imaging apparatus in which amplifying type solid-state imaging devices are arranged in a matrix configuration, each of the amplifying type solid-state imaging devices amplifying a signal within a pixel by a transistor such as an MOS (Metal-Oxide-Semiconductor) FET (Field Effect Transistor) or a junction gate type FET.
2. Description of the Related Art
In order to replace a charge-coupled device (CCD) which is currently in wide use in a solid-state imaging apparatus, an amplifying type solid-state imaging apparatus is proposed. The amplifying type solid-state imaging apparatus does not read out a signal charge generated in a pixel as it is but amplifies it within the pixel, and then successively reads out the amplified signal charge by a scanning circuit. By amplifying the signal charge within the pixel, an amount of signals is sufficiently secured. Moreover, the limitation of an amount of signals in connection with the read-out is eliminated, and a dynamic range becomes better for the amplifying type device than for the CCD. Furthermore, it is sufficient to drive only the horizontal and vertical lines and the selection switch, which include pixels from which the signal is to be read out. As a result, the amplifying type solid-state imaging device is characterized with lower driving voltage and less power consumption than the CCD.
Transistors are typically used for amplifying a signal within each pixel. Depending on the type of transistors used, the amplifying type solid-state imaging device is categorized into an SIT type, a bipolar type, an FET type (MOS type or junction type), etc. In the SIT type and bipolar type devices, the scanning circuit for reading out the signal charge typically has a transistor structure constructed in the depth-direction. Since the MOS-FET type device has a transistor structure constructed parallel to the substrate surface, the MOS-FET type device has a simpler structure and can be readily produced. Therefore, it is structurally advantageous to employ the FET type device to a pixel when the overall structure of the apparatus is under consideration. Furthermore, the FET type device where the pixel includes a single FET is advantageous in increasing the pixel density. Reported as this type are a CMD (Charge Modulation Device) type, an FGA (Floating Gate Array) type, a BCM (Bulk Charge Modulated Device) type, etc.
FIGS. 1A and 1B illustrate a pixel of a conventional CMD type amplifying type solid-state imaging apparatus. FIG. 1A is a plan view of the pixel, and FIG. 1B is a cross-sectional view of the pixel taken along the G--G line in FIG. 1A. The CMD type pixel structure shown in FIGS. 1A and 1B is reported, for example, in "Gate accumulating type MOS phototransistor image sensor" by Nakamura et al., 1986 National Convention of the Institute of Television Engineers of Japan, page 57.
As illustrated in FIG. 1B, an n-type well 2 is formed on a p-type substrate 1 as a buried channel, and a gate electrode 4 is formed on the n-type well 2 with an insulating film 3 being inserted therebetween. A source region 5 and a drain region 6 which are made of a high concentration n.sup.+ -type layer and are separated from each other are also formed to the surface side of the n-type well 2.
As illustrated in FIG. 1A, the gate electrode 4 of each of the pixels arranged in the horizontal direction are all connected to a gate terminal 7, and the source region 5 of each of the pixels arranged in the vertical direction are all connected to a source terminal 8. Furthermore, each drain region 6 connects pixels in a mesh-like manner, and this drain region 6 is connected to a drain terminal 9. A plurality of such pixels are arranged both in the horizontal and vertical directions so as to form a matrix, thereby constituting a CMD type pixel unit.
Hereinafter, the operation of the CMD type pixel unit whose structure is described above will be described.
FIG. 2 shows the potential distribution in the depth-direction taken along the H--H line in FIG. 1B. As illustrated in FIG. 2, a voltage V.sub.L is applied as a gate voltage to the respective gate electrodes 4 of pixels arranged in the horizontal direction via the corresponding gate terminal 7, and a signal charge (positive holes) generated by photoelectric conversion in each pixel arranged in the horizontal direction is accumulated at the interface of the semiconductor and the insulator 3. Next, when reading out the signal, the gate voltage applied to the gate electrodes 4 is changed to a voltage V.sub.M which is higher than the voltage V.sub.L. When this is being done, the current flowing between the drain region 6 and the source region 5 of the transistor changes depending on the amount of accumulated signal charge. This changed current is to be read out as a signal output through the source terminal 8. When the changed current is being read out, since the gate voltage applied to other pixels connected to the same source terminal 8 remains at V.sub.L through other gate terminals 7, signal outputs from other pixels are not sensed.
Furthermore, the resetting operation which resets the pixels by clearing the accumulated signal charges and prepares the pixels for next signal accumulation is performed by changing the gate voltage applied to the gate electrodes 4 to a voltage V.sub.H so that a potential gradient which monotonically decreases in the depth-direction is provided. The signal charge (positive holes in this case) accumulated at the interface of the n-type well 2 and the insulating film 3 is discharged to the p-type substrate 1 side immediately below as illustrated by the broken lines in FIG. 1B.
In the above-described conventional CMD type pixels, if the impurity concentration of the buried channel layer which functions as the n-type well 2 is raised in order to increase the signal charge accumulation density, then the gate voltage V.sub.H during the above-described resetting operation must be set extremely high.
For example, the gate voltage V.sub.H during the resetting operation will be considered under the following conditions (condition 1).
(Condition 1)
Concentration in substrate: 1.0.times.10.sup.15 cm.sup.-3 PA0 Concentration in n-type layer: 3.0.times.10.sup.15 cm.sup.-3 PA0 Thickness of n-type layer: 1.5 .mu.m PA0 Thickness of gate insulating film: 80 nm
Under Condition 1, the critical condition for the potential to be monotonically decreasing from the surface of the n-type well 2 to the p-type substrate 1 is given by the following equation (1). ##EQU1## where N.sub.n denotes carrier concentration of the n-type well 2, N.sub.p denotes carrier concentration of the p-type substrate 1, K.sub.s denotes a dielectric constant of the substrate 1, .epsilon..sub.o denotes the permittivity in vacuum, q denotes the elementary electric charge, and D.sub.n denotes a junction depth X.sub.j of the n-type well 2.
Therefore, in the case where the flat band voltage is V.sub.FB =-0.85 V, the gate voltage V.sub.H required for the resetting operation is calculated to be V.sub.H =20.0 V from Equation (1), which is unpractically high.
Furthermore, other problems experienced by the conventional CMD type pixels include a large quantity of dark current due to the depletion at the interface between the n-type well 2 and the insulating film 3 when surrounding environment is dark.
In order to reduce the dark current in the FET type amplifying type solid-state imaging apparatus, an FGA type amplifying type solid-state imaging apparatus is proposed.
FIG. 3A is a cross-sectional view of a pixel of a conventional FGA type amplifying type solid-state imaging apparatus, and FIG. 3B shows the potential distribution in the depth-direction taken along the line K--K in FIG. 3A. This conventional technique is reported in "A New Device Architecture Suitable for High-Resolution and High-Performance Image Sensor", by J. Hynecek, IEEE Trans. Elec. Dev., p 646, (1988). In FIG. 3A, elements having similar functions as in FIG. 1A are designated by the same reference numerals and the descriptions thereof are omitted.
This FGA type device differs from the CMD type device in that a p.sup.+ -type layer 10 having relatively high impurity concentration is provided in a region of the n-type well 2 under the gate electrode 4 as illustrated in FIG. 3A.
In the FGA type amplifying type solid-state imaging apparatus having the above structure, the gate voltage is set at a voltage V.sub.L during the accumulation and read-out of a signal as illustrated in FIG. 3B. Then, a change in the channel potential in the n-type well 2 due to the accumulation of a signal charge (positive hole) in the p.sup.+ layer 10 is read out as a change in the threshold value. Other pixels connected to the same signal line are not read out since the gate voltage applied to these pixels is not V.sub.L.
Following the read-out operation, the resetting operation is similar to that of the above-described CMD type device. By changing the gate voltage to a voltage V.sub.H when resetting so as to provide a potential gradient which is monotonically decreasing in the depth-direction, the signal charge (positive hole) accumulated in the p.sup.+ -type layer is discharged to the p-type substrate 1 side directly below. Since this p.sup.+ -type layer 10 does not become depleted during the resetting operation, the dark current can be prevented. However, the fact that the p.sup.+ -type layer 10 does not become depleted also means that the signal charge is not completely transferred. This causes generation of an after image and an increase in the resetting noise.
In order to further improve the FGA type amplifying type solid-state imaging apparatus, a BCMD type amplifying type solid-state imaging apparatus has been proposed ("BCMD-An Improved Photosite Structure for High Density Image Sensor" by J. Hynecek, IEEE trans. Elec. Dev., p 1011, (1991)).
FIG. 4A is a cross-sectional view of a pixel of a conventional BCMD type amplifying type solid-state imaging apparatus, and FIG. 4B is a potential distribution in the depth-direction taken along the sectioning line L--L in FIG. 4A.
In FIG. 4A, the pixel of the BCMD type device includes a p-type layer 12, an n-type layer 13 and another p-type layer 14 successively deposited in this order on an n-type substrate 11. Then, a high impurity concentration p.sup.+ -type layer 15 which is intended for the source and the drain extending through the p-type layer 12, the n-type layer 13 and the p-type layer 14 is formed.
Comparing to the pixel of the above-described FGA type device, the pixel of the BCMD type device differs in that the signal charges are electrons accumulated in the n-type layer 13 functioning as the buried channel, that a potential change in the p-type layer 14 at the surface due to the signal charge is sensed as a change in the threshold value of P-MOS, and that the substrate 11 is an n-type and the gate voltage is set at a low voltage V.sub.L during the resetting operation so that the signal charge is discharged to the n-type substrate 11 side.
In this manner, a complete transfer of the signal charge is achieved. However, this structure requires the p-n-p-n multi-layer structure. As a result, the optimization of driving conditions becomes difficult to achieve, and its fabrication also becomes too complicated.
In order to solve those problems associated with each of the above-described amplifying type solid-state imaging apparatuses, the applicant of the present invention proposed four kinds of new structures to be described below, and separately filed the inventions in Japanese Patent Application Nos. 6-30953, 7-51641, 8-19199 and 8-19200, respectively.
FIG. 5 is a cross-sectional view of a pixel having a so-called TGMIS (Twin Gate MOS Image Sensor) type structure disclosed in Japanese Patent Application 6-30953. In the figure, an n-type well layer 62 is provided to the surface side of a p-type semiconductor substrate 61, and a source region 50 and a drain region 45 of the MOS-FET are provided to the surface side of the n-type layer 62. Furthermore, a first gate (photo gate) electrode 46 is provided on the n-type layer 62 with an insulating film 63 being inserted therebetween, and a second gate (resetting gate) electrode 48 is provided on the p-type semiconductor substrate 61 also with the insulating film 63 being inserted therebetween.
The first gate electrode 46 is connected to a control voltage terminal to which a read-out scanning voltage V.sub.A is applied. The source region 50 of the MOS-FET including the first gate electrode 46 as a gate is connected to a source terminal through which a pixel signal voltage V.sub.S read out from the pixel is obtained, and the drain region 45 of each pixel is connected to a drain terminal to which a drain voltage V.sub.D is applied.
Hereinafter, the operation of the above-described structure will be described.
First, a photon having optical energy h.nu. entering through the first gate electrode 46 creates an electron-hole pair due to photoelectric conversion, and the electron thus created flows into the drain region 45. The positive hole is confined by the potential barrier formed in the middle portion of the n-type layer 62 and by the potential barrier formed under the second gate electrode 48. The positive holes accumulate at the interface of the n-type layer 62 between the semiconductor and the insulating film as a signal charge.
A change in the potential within the n-type layer 62 in accordance with the signal charge can be read out as a voltage change in the source region 50, regarding it as an output signal of the pixel voltage.
The discharge of the signal charge is readily performed by lowering the potential barrier under the second gate electrode 48. The signal charge then flows to the p-type semiconductor substrate 61 side through the path indicated by the broken line in FIG. 5.
For example, in the structure where the signal charge is extracted directly to the substrate side as for the conventional CMD type, sufficient resetting cannot be performed unless relatively high voltage (10 V, for example) is applied to the first gate electrode. Moreover, if the impurity concentration in the n-type well layer is made small, a sufficient amount of charge cannot be accumulated. If the impurity concentration in the n-type well layer is made large, then a sufficient amount of accumulated charge can be obtained but, on the other hand, sufficient resetting cannot be performed unless high voltage (20 V, for example) is applied to the resetting gate. However, in the structure where the signal charge to be reset is first extracted in the horizontal direction and then to the substrate side as illustrated in FIG. 5, since the n-type well having the high impurity concentration can be used and a sufficient amount of the signal charge can be accumulated at the surface, a signal charge amount of sufficiently large magnitude can be handled and, at the same time, the resetting operation can be performed at lower voltage.
However, a problem still remains which is common to all currently known amplifying type solid-state imaging apparatuses, and the problem is associated with a fixed pattern noise (FPN) arising from the fluctuation of signal levels and amplification factors among pixels. Hereinafter, this problem associated with FPN will be described in detail with reference to the above-described TGMIS type amplifying type solid-state imaging apparatus as an example.
FIG. 6 schematically illustrates the structure of a two-dimensional amplifying-type solid-state imaging apparatus utilizing TGMIS type amplifying type solid-state imaging devices. A predetermined DC voltage V.sub.D is applied to a common drain 25 of each pixel such as pixels 21, 22, 23 and 24. First gate electrodes 26 of pixels arranged in the horizontal direction, such as pixels 21 and 22, are all connected to a first scanning line 26a placed in the horizontal direction so that a read-out operation is performed by a first vertical scanning circuit 27 via the first scanning line 26a. Second gate electrodes 28 of the same pixels as above arranged in the horizontal direction, such as pixels 21 and 22, are all connected to a second scanning line 28a placed in the horizontal direction so that a resetting operation is performed by a second vertical scanning circuit 29 via the second scanning line 28a in units of the horizontally-arranged pixels. Furthermore, source electrodes 30 of pixels arranged in the vertical direction, such as pixels 21 and 23 or pixels 22 and 24, are all connected to a signal line 31 in units of such pixels, and further connected to a video line 34 via a switching transistor 33 whose ons and offs are controlled by a horizontal scanning circuit 32. Furthermore, an MOS transistor 36 which provides a constant current load is connected to the output terminal 35 of the video line 34. This completes the construction of the two-dimensional amplifying type solid-state imaging apparatus utilizing the TGMIS type amplifying type solid-state imaging devices.
FIG. 7A is a timing chart for driving the two-dimensional amplifying type solid-state imaging apparatus in FIG. 6, and FIG. 7B is a structural diagram of its output signal.
In FIG. 7A, the scanning signal .phi.GI(i) is a control clock signal which is successively output from the first vertical scanning circuit 27 to the i-th group from the top of the first gate electrodes 26 of pixels arranged in the horizontal direction, and the scanning signal .phi.GII(i) is a control clock signal which is successively output from the second vertical scanning circuit 29 to the i-th group from the top of the second gate electrodes 28 of pixels arranged in the horizontal direction. For example, the scanning signal .phi.GI(1) from the first vertical scanning circuit 27 is input to the first gate electrodes 26 of pixels arranged in the horizontal direction such as pixels 21 and 22 so that read-out operation from pixels such as pixels 21 and 22 is selected.
Then, if the first gate electrodes 26 and the second gate electrodes 28 of the i-th group of horizontally arranged pixels from the top are at high levels VG(H) and VRG(H), respectively, while the first gate electrodes 26 and the second gate electrodes 28 of other pixels are all at low levels VG(L) and VRG(L), respectively, then only the pixel signals stored in the i-th group of horizontally arranged pixels from the top can be read out to the signal lines 31. The clock pulses .phi.S1, .phi.S2, .phi.S3, etc. which are output from the horizontal scanning circuit 32 during the period (.tau.H) successively select the signal line 31 placed in the vertical direction by controlling ons and offs of the switching transistors 33. Then, the pixel signals from the i-th group of vertically arranged pixels from the left are output to the video line 34 as output signals via the signal line 31 and the switching transistor 33.
Then, during the period (.tau.BL) in which the first gate electrodes 26 of the i-th group of horizontally arranged pixels from the top are at high level VG(H) but the second gate electrodes 28 of the same group of pixels are at low level VRG(L), the resetting operation is performed by the second vertical scanning circuit 29 in units of pixels arranged in the horizontal direction.
As illustrated in FIG. 7B, the signal output waveform of the pixel signal obtained by the clock pulses .phi.S1, .phi.S2, .phi.S3, etc. also includes a fluctuation component of an output voltage when there is no optical input (photoelectrically generated and accumulated charge is zero) to the pixels of the amplifying type solid-state imaging devices which are successively selected. As a result, it is not possible to obtain only the signal amount of the output signal due to the net amount of photoelectrically generated and accumulated charge, posing a problem associated with a fixed pattern noise arising from the fluctuation of signal level and amplification factor of each pixel.

Amplifying type solid-state imaging apparatus and method for driving the same


A system for suspending a computing device suspected of being infected by a malicious code is configured to receive a signal to initiate a suspension procedure of the computing device. The system captures states of instructions that are being executed by a processor of the computing device, where the instructions comprise the malicious code. The system prioritizes the operation of a kill switch button over the instructions being executed by the processor. The system sends notification signals to servers managing a user account associated with a user currently logged in at the computing device, indicating that the computing device is suspected of having been infected by the malicious code. In response to sending the notification signals to the servers, the user account is suspended. The system terminates network connections of the computing device such that the computing device is disconnected from other devices.

It can be a slow process to terminate dependent systems from a computing device that is discovered to be infected by a malicious code, where the malicious code is associated with a software application, such as malware. It is also difficult to terminate access to user accounts and revoke privileges associated with user accounts logged in at the computing device infected by the malicious code. It is also difficult to terminate network connections between the infected computing device and systems that are connected to the infected computing device through a network. Current information security and data loss prevention technologies are not configured to provide a reliable solution to suspend a computing device that is suspected of being infected by a malicious code.

System and method for suspending a computing device suspected of being infected by a malicious code using a kill switch button


An enlarged and weighted tip for replacing a multi-pod tip of a cane and for receiving a lower end of the cane and for allowing the cane to stand by itself. The tip includes a body portion that is shaped like a frustrum of substantially a pyramid. The body portion has a cavity therein that is disk-shaped and is disposed axially between the bore in the top surface of the body portion and the base of the body portion, parallel thereto. The tip further includes a plate that completely fills the cavity in the body portion and provides structural integrity, prevents rupturing of the base of the body portion caused by weight bearing on the cane tending to push it downwardly, and which adds sufficient weight to lower the center of gravity enabling the cane to stand by itself.

1. Field of the Invention
The present invention relates to a tip for a cane or the like. More particularly, the present invention relates to an enlarged and weighted tip for replacing a multi-pod tip of a cane or the like.
2. Description of the Prior Art
Numerous innovations for tips for canes or the like have been provided in the prior art that will be described. Even though these innovations may be suitable for the specific individual purposes to which they address, however, they differ from the present invention.
FOR EXAMPLE, U.S. Pat. No. Des. 378,551 to Shelnutt teaches the ornamental design for a crutch tip.
ANOTHER EXAMPLE, U.S. Pat. No. 4,881,564 to Fetterman teaches a crutch tip including an integrally fabricated tubular receiver for a crutch shaft and having on its lower end an enlarged depending skirt. Firmly secured conformably within the skirt are a rigid plate immediately beneath the receiver, an absorption or damping pad immediately beneath the plate, and a ground engageable tread piece immediately beneath the absorption pad, which tread piece includes depending projections for receiving and flexing about small articles on the ground while maintaining traction with the ground.
STILL ANOTHER EXAMPLE, U.S. Pat. No. 5,178,176 to Fetterman teaches a crutch tip for installation on the lower end of a crutch shaft for engagement with an underlying supporting surface. The crutch tip includes a first material having a first coefficient of friction with respect to the supporting surface and a second material having a second coefficient of friction with respect to the supporting surface. The crutch tip generally includes a radial outer skirt, a ring portion radially inwardly of the skirt, and a center portion. The ring portion may be formed from the first material and the outer skirt may be formed from the second material.
YET ANOTHER EXAMPLE, U.S. Pat. No. 5,301,704 to Brown teaches a walking cane that has an enlarged foot piece, formed with a convex arcuate lower surface, that functions as a small rocker. One, or two, rows of spikes extend downwardly from the arcuate surface, for penetration and gripping of icy surfaces. An elastomeric, resilient pad may be attached to the arcuate lower surface of the foot piece, to adapt the cane for use on normal walking surfaces, such as carpets, hard floors, and outdoor sidewalks. The pad has a series of sockets that fit onto the spikes for retention of the pad on the foot piece. The arcuate surface contour on the foot piece is advantageous in that it enables the spikes or resilient pad to maintain a non-slip, rocking engagement with the walking surface during the entire walking stride, i.e., while the person is using the cane to partially support his or her own weight during forward motion of the person's body.
FINALLY, YET ANOTHER EXAMPLE, U.S. Pat. No. 5,409,029 to Davis teaches a crutch tip assembly that includes a crutch tip base with a laterally protruding lip adjacent a base bottom surface and a resilient boot having the shape of a rocker. The boot defines a mounting cavity for snugly receiving the base bottom surface and the lip for holding the boot on the base. The boot has a sole with a bottom surface for contacting the ground and a tip surface in the cavity directed towards the base bottom surface. Protruding portions are positioned between the base bottom surface and the sole top surface for providing resilient cushioning between the sole top surface and the base bottom surface. Sidewall cavities are located around the perimeter of the boot allowing for lateral compression and reexpansion.
It is apparent that numerous innovations for tips for canes or the like have been provided in the prior art that are adapted to be used. Furthermore, even though these innovations may be suitable for the specific individual purposes to which they address, however, they would not be suitable for the purposes of the present invention as heretofore described.


Systems and methods configured to determine a machine-readable optical code based on screen-captured video are disclosed. Exemplary implementations may: receive, via a user interface of a client computing platform, an indication to begin a screen-captured video; initiate, based on the indication, the screen-captured video; effectuate an image decoding machine configured to parse and decode images and/or the video frames for information embedded into the images and/or the video frames to: parse the video frames for a machine-readable optical code; for individual ones of the video frames with the machine-readable optical code, extract embedded information from the machine-readable optical code; and decode the embedded information for metadata; and effectuate, via the user interface, presentation of information derived from the metadata.

Existing methods of capturing an image to extract embedded information from an electronic device (e.g., smartphone, tablet) may be limited to the use of a physical camera of the electronic device as the primary method of image capture. Such capturing involves several user interactions which tend to interrupt or obstruct presently ongoing activities, such as when a user is watching a video and does not want to be interrupted. The existing methods merely capturing images with the physical camera. However, this is limited and does not allow the user to capture images with embedded information on the electronic device screen they are currently viewing.

This patent is subject to a terminal disclaimer.

Systems and methods to determine a machine-readable optical code based on screen-captured video


Tools are provided for managing information technology (IT) devices in an IT environment in which at least some of the devices are connected to a network, and device information is presented to a user in a dynamic, manageable and informative manner. The device information presented may be on a global or enterprise-wide scale, or drilled down to a more specific level, geographically or otherwise.

In the current information age, information technology (IT) tools are extensively used in enterprises and other organizations in order to facilitate processing of documents and data. IT administrators typically have the responsibilities of monitoring and managing IT devices, such as computers, printers, scanners, multi-function devices (MFDs) and other network-connected or standalone devices.
For example, in an enterprise environment, such as in a multi-national corporation, or another organization, including offices over wide geographical expanse, an administrator may need or desire to detect global or local trends in device usage or operation patterns in the IT environment administered by the administrator, as well as immediate developments that may be evident from the appropriate view or views of device data.
Device management tools (such as application software, etc.) are available to IT administrators to assist the administrators to track, monitor and otherwise manage the devices. For example, such tools commonly include a list view of the devices in the IT environment, displaying device information (e.g., device name, status, location, make, etc.) in a list format. An example of such list is illustrated in FIG. 1.
There is a drawback, however, in that the number of IT devices connected to a network is generally increasing and, as a result, an IT administrator is required to oversee a growing number of IT assets. Thus, it is sometimes difficult to grasp the overall status of the network environment and locate or anticipate the problems in the network environment from such list view.
There exists a need for an improved method of monitoring the condition of a network environment including a large number of information technology devices.

Dynamic user interface for device management system


In a data processing system including a system bus supporting memory mapped devices, dynamic response to a memory mapped command is achieved by receiving a status response from each device attached to the system bus and comparing a priority associated with each such status response to a predetermined priority. If a priority associated with the status response from one of the devices equals or exceeds the predetermined priority, indicating that the address in the memory mapped command is acknowledged in some form by that device, the status response from that device is forwarded to all devices attached to the system bus. If no status response received from the devices has an associated priority equalling or exceeding the predetermined priority, the address is acknowledged and the memory mapped command accepted and forwarded to a lower bus. If the memory mapped command is not accepted by the lower bus, dummy data is returned and a machine check is signaled.

1. Technical Field
The present invention relates in general to attaching memory mapped devices to a multilevel bus hierarchy and in particular to allowing memory mapped devices to be attached to any level of a multilevel bus hierarchy. Still more particularly, the present invention relates to forwarding memory mapped commands to lower levels of a multilevel bus hierarchy without precluding attachment of memory mapped devices to higher levels of the bus hierarchy.
2. Description of the Related Art
Memory mapped devices in a data processing system use a portion of the date processing system's total memory address space for their input/output (I/O) address space rather than using a dedicated I/O address space. As is known in the art, use of memory mapped devices avoids the requirement of extra signals to identify or select devices and allows all processor instructions, rather than merely a limited set, to be used in conjunction with the device.
A common problem for data processing systems using memory mapped devices is the potential for decoding conflicts by multiple devices. Many data processing systems attach several memory mapped devices to secondary or tertiary buses attached to the system bus through a system memory controller. The system memory controller normally acknowledges all memory addresses and passes operations with memory addresses which it does not actually control to the buses below it. If the buses below do not accept the operation passed by the system memory controller, some error condition is asserted to the processor(s) on the system bus.
The method described above works if the bus hierarchy contains no memory mapped devices or buses above or at the same hierarchy level as the system memory controller. If additional devices are added to the bus hierarchy at or above the level of the system memory controller, addresses for these devices cannot be acknowledged by the system memory controller.
It would be desirable, in a system including secondary or tertiary buses attached to a system memory controller, to allow operations with memory addresses for devices on the secondary or tertiary buses to be passed below the system memory controller while allowing additional devices or buses to be attached to the system bus at a level equal to or above the system memory controller in the bus hierarchy. It would further be desirable to dynamically forward memory mapped commands to the appropriate memory mapped devices anywhere in the bus hierarchy.
It would also be desirable to allow the addition, at a later time or in other configuration, of other devices at or above the bus level of the I/O bridge connecting the secondary bus with the system bus without requiring either changes to the system memory controller hardware (adding decoding range registers or look up tables, etc.) to permit such later additions or other configurations or different programming of the system memory controller for different configurations.

Method for dynamic address coding for memory mapped commands directed to a system bus and/or secondary bused

International Business Machines Corporation


A solid soap composition which comprises as essential ingredients a soap ingredient (a), a specific polyoxyalkylene-modified polysiloxane Co), and a tetrakis(2-hydroxyalkyl)ethylenediamine(c). It is a detergent with which makeup removal and ordinary face washing can be simultaneously conducted at a time. It lathers well and gives a fresh use feeling after washing. It can sufficiently remove not only foundations but acid pigments.

Made-up skin is cleaned in the following procedure: first, make-up cosmetic materials are mixed with a cleanser for removing makeup such as cleansing creams and cleansing oils containing a large amount of oil that is easily mixed with the make-up cosmetic materials, and removed by flushing with water or lukewarm water, then sebaceous matters and stains on the skin are removed together with oil of the cleanser remaining on the skin using a face cleaner such as soaps and cleansing foams. This two-step cleaning provides a clean feel after cleaning.
This two-step cleaning is necessary because a cleanser for removing makeup contains a large amount of oil, and thus even when rinsed with water or lukewarm water, the oil of the cleanser remains on the skin, so that a clean feel cannot be obtained after cleaning, and because it is impossible to sufficiently remove oil-based make-up cosmetic materials from the skin only with an ordinary face cleaner such as soaps and cleansing foams.
In accordance with recent change in the life style, there is a request for simplicity in cleaning made-up skin, and with respect to this request, face cleaners have been proposed that can perform makeup removal and ordinary facial cleaning at the same time in single facial cleaning. For example, Patent Document 1 discloses a cleaning agent containing polyoxyethylene glycerine fatty acid ester and polyoxyalkylene-modified polysiloxane, and Patent Document 2 discloses a skin cleaner containing polyoxyethylene diester, an anionic surfactant, an amphoteric surfactant, and polyoxyalkylene-modified methyl polysiloxane. All of these face cleaners are in either liquid form or gel form.
In the cleaning agents described above, mainly polyoxyalkylene-modified methyl polysiloxane removes make-up cosmetic materials, but when mixing this component, there is a problem in that the foaming property becomes insufficient and in that this component remains on skin after facial cleaning and thus a clean feel cannot be obtained after cleaning. Furthermore, although this component can remove make-up cosmetic materials such as cosmetic foundations, it cannot sufficiently remove make-up cosmetic materials that are acid pigments (such as lipsticks).
Patent Document 1: JP H05-75723B
Patent Document 2: JP H11-106331A

Solid soap composition comprising polysilxoxane and diamine


Methods of making fiber-containing prepregs are described. The methods may include the steps of providing a plurality of fibers, and applying a reactive resin composition to the plurality of fibers to make a mixture of the plurality of fibers and the resin composition. The reactive resin composition may include at least one of monomers and oligomers capable of polymerizing into a polymerized resin matrix. The mixture may be heated to a polymerization temperature where the monomers, oligomers, or both polymerize to form a fiber-resin amalgam that includes the polymerized resin matrix. The fiber-resin amalgam may be formed into the fiber-containing prepreg. Also described are methods of forming a fiber-reinforced composite that includes the prepreg.

Conventional methods of making fiber-reinforced composites include bringing together a plurality of fibers with a resin composition and shaping the amalgam of fibers and resin composition into the final composite article. The fibers may include glass fibers that are organized into a woven pattern or randomly assembled into a nonwoven collection or mat. The resin composition applied to the fibers may be a powder, a suspension in a liquid medium, or a melt of thermoplastic polymer.
There can be many challenges applying the resin composition to plurality of fibers to make a homogeneous mixture of the fibers and resin composition in the amalgam. For example, when the resin composition is a powder, there is significant difficulty distributing the particles of the powdered composition beyond the surface of the fibers into the bulk. This can be especially challenging for woven fibers that are difficult or impossible to mechanically mix with the particles. Reducing the particle size to allow them to fit through the interstitial spaces between the fibers may help distribute them beyond the service layer, but milling the particles to very small sizes often requires complex and expensive processing. Moreover, fine-grained particles of organic materials mixed in air can create an explosion hazard, and should be applied to the fibers under an inert (i.e., reduced oxygen) atmosphere.
There are also challenges applying liquid resin compositions to fibers. If the liquid resin composition is a melt of thermoplastic polymer, it often has a viscosity significantly higher than water. A high viscosity melt makes the resin material difficult to impregnate into the bulk of the fibers. Increasing the temperature of the melt to reduce its viscosity can cause unwanted reactions or decomposition in the resin material, making this viscosity-reduction technique of limited value. Another technique increases the pressure on the amalgam using a double belt press in order to drive the high-viscosity melt into the fibers. However, this technique is prone to damaging and distorting the fibers, especially fibers that have been fashioned into a woven fabric. In some instances, the resin material can be mixed or dissolved in a solvent to reduce its viscosity and make it easier to wet the fibers. However, many thermoplastic resin materials are not easily dissolved, and additional time and steps may be required to separate (e.g., evaporate) the solvent from the fiber and resin amalgam. Similar problems can occur for resin compositions made of a suspension of particles in a liquid carrier medium such as water. In addition to the challenges getting the particles to quickly and evenly disperse throughout the fibers, additional steps are often needed to remove the solvent from the amalgam.
These and other problems are addressed by the present application, which includes the making and use of prepregs that have a resin material dispersed in a plurality of fibers. The prepregs may be used in fiber-containing composite articles, and reduce or eliminate the number of time-consuming process steps needed to combine resin compositions with the fibers.

Fiber-containing prepregs and methods and systems of making


A method for forming an insulator with a high dielectric constant on silicon is disclosed. This method overcomes one limitation of increasing the dielectric constant of a gate dielectric by using a high dielectric constant material, such as a paraelectric material, instead of silicon dioxide. First, nitrogen is implanted into the silicon through a sacrificial oxide layer. After annealing the substrate and stripping the sacrificial oxide, a dielectric layer is formed from a material with a high dielectric constant, such as a paraelectric material. Although the paraelectric material provides a source of oxygen for oxidation of silicon in subsequent high temperature process steps, no oxidation takes place due to the presence of the nitrogen in the silicon. Therefore, there is no undesired decrease in the overall capacitance of the dielectric system. When a gate electrode is formed on the dielectric layer, a nitrogen implant into the gate electrode can be used to prevent oxidation at the upper interface of the gate dielectric.

A desire to increase the speed and density of integrated circuits (ICs) has led to transistor scaling accompanied by progressive reductions in the thickness of the gate oxide. A thinner gate oxide provides greater drive current, thereby increasing speed. Also, a thinner gate oxide provides greater control over the channel charge, thereby reducing short channel effects. However, thinner gate oxides present greater problems of manufacturability, quality and reliability.
One way to avoid the problems of a thinner gate oxide but achieve the desired capacitive effect is to replace the gate oxide with a gate dielectric that has a greater dielectric constant than silicon dioxide. Paraelectric materials have dielectric constants that are usually at least two orders of magnitude above that of silicon dioxide, but several problems limit their use as gate dielectrics. One such problem is illustrated in FIGS. 1a and 1b. FIG. 1a is a cross sectional illustration of a prior dielectric system before any high temperature processing has occurred, such as source/drain dopant activation, and FIG. 1b is a cross sectional illustration of the same dielectric system after high temperature processing has occurred. During these high temperature processes, oxygen diffuses from gate dielectric 101 to interface 102 between gate dielectric 101 and gate electrode 103, and to interface 104 between gate dielectric 101 and channel 105. The diffused oxygen forms oxide layer 106 at these interfaces, decreasing the overall capacitance of the dielectric system and partially counteracting the effect of the high dielectric constant paraelectric material.
Therefore, a better way to form a high dielectric constant insulator in the fabrication of an integrated circuit is desired.

Method for forming a High dielectric constant insulator in the fabrication of an integrated circuit


A heat dissipation device and a method for fabrication thereof are disclosed. The heat dissipation device includes a heat sink having a base, and a heat pipe embedded in the base. A groove is defined in the base. The groove is enclosed by a top surface and two sidewalls slantwise extending downwardly and inwards from opposite edges of the top surface. A width of a bottom portion of the groove is shorter than that of a top portion of the groove. The heat pipe includes an evaporation portion directly pressed in the groove by punching and fully contacts with the groove. The evaporating portion is flattened when it is fully engaged in the groove to directly contact with an electronic component. The method involves directly pressing the evaporation portion of the heat pipe into the groove of the base.

1. Field of the Invention
The present invention relates to a heat dissipating device having a heat pipe and method for manufacturing the same, wherein the heat pipe is directly mounted into the heat dissipation device.
2. Description of Related Art
A computer central processing unit (CPU) is the core controller of electrical signals in the contemporary personal computers. Continued development of the CPUs has enabled them to perform more and more functions. Heat generated by the CPUs has thus increased enormously. Such heat can adversely affect the operational stability of the computers. Measures must be taken to efficiently remove the heat from the CPU. Typically, a dissipation device having great heat conductivity is mounted on the CPU to remove the heat therefrom.
The conventional heat dissipation device commonly comprises a heat sink thermally connecting with the CPU and a heat pipe sandwiched between the heat sink and the CPU. The heat pipe transfers heat generated by the CPU to the heat sink. The heat sink comprises a base. A groove is defined in the base to receive the heat pipe. The heat pipe is soldered in the groove of the base with solder cream. The solder cream is adhered to a surface of the heat pipe and connects with the base of the heat sink. Heat generated by the CPU is absorbed by the heat pipe, then transferred to the solder cream, finally transferred to the base of the heat sink. Thus, heat dissipation efficiency of the heat dissipation device is decreased because of a thermal resistance of the solder cream.
Thus, it is desired to devise a heat dissipating device which having a heat pipe can be directly mounted thereon without any solder cream.

Heat dissipation device and a method for manufacturing the same


A legacy-type fluorescent lamp fixture involves a magnetic ballast and a starter unit socket. Power savings are realized by using a retrofit fluorescent lamp assembly in place of the fluorescent lamp that would ordinarily by held in the fixture. The retrofit assembly may, for example, have a smaller fluorescent lamp. A digitally controlled electronic ballast within the retrofit assembly drives the smaller fluorescent lamp efficiently, thereby achieving power savings. In addition, an RF-enabled switch is installed in the starter unit socket. The RF-enabled switch communicates multi-bit digital control signals in serial fashion from the starter socket, through existing wires of the fixture, through the lamp holders of the fixture, and into the retrofit assembly. The electronic ballast receives these signals, decodes them, and in response turns on or turns off its lamp as commanded. Additional power savings are thereby achieved by keeping the lamp off when it is not needed.

FIG. 1 (Prior Art) is an exploded perspective view of an assembly involving one type of fluorescent lamp fixture referred to here as an old-fashioned or a "legacy" fluorescent lamp fixture. FIG. 2 (Prior Art) is a circuit schematic of the assembly of FIG. 1. Legacy fixture 1 includes a base portion 2, a transparent cover or lens 3, and a starter unit 5. Base portion 2 of the fixture includes a pair of T8 lamp holders 6 and 7, a starter socket 8, a magnetic ballast 9 that is disposed under a removable metal cover or tent 10, and other parts not shown. A fluorescent lamp 4 is installed in the fixture. Fixture 1 receives AC power via electrical cord 11. In one example, the fluorescent lamp 4 is a so-called T8 tubular fluorescent lamp having opposing G13 bi-pin bases 12 and 13. The T8 lamp is installed in the fixture so that the two pins of G13 bi-pin base 12 fit into lamp holder 6 and make contact with two corresponding electrical contacts in lamp holder 6. Similarly, the two pins of G13 bi-pin base 13 fit into lamp holder 7 and make contact with two corresponding electrical contacts in lamp holder 7. When starter unit 5 is installed, the two terminals of the starter unit fit up and into corresponding holes in starter socket 8 and make electrical connections to two corresponding electrical contacts in the socket.
As is known in the art, a starter unit is required to turn on the lamp. In a first step, when AC power is applied to the fixture via cord 11, a switch in starter unit 5 closes and forms an electrical connection between the filament 14 at one end of lamp 4 and the filament 15 at the other end of lamp 4. An alternating current can then flow from an AC power source 16, through inductive ballast 9, through filament 14, through the closed switch of the starter unit 5, and through the second filament 15, and back to the AC power source 16. This flow of this current causes the filaments to heat. The heating of the filaments causes gas surrounding the filaments to ionize. Once the gas is ionized in this way, then the switch in the starter unit is opened. The opening of the switch cuts current flow through magnetic ballast 9, thereby causing a large voltage spike to develop due to the inductive nature of the ballast. Due to the circuit topology, this large voltage is present between filaments 14 and 15. The voltage is large enough to strike an arc between the filaments through the gas within the lamp. Once the arc is established, the resistance between the two filaments through the gas decreases. This allows current to continue to flow through the gas without a large voltage being present between the filaments. The switch of the starter unit is left open, the current continues to flow, filaments continue to be heated, the arc is maintained, and the magnitude of current flow is limited by the ballast. The fluorescent lamp is then said to be on. The arc generates UV light that then strikes a phosphor coating on the inside surface of the glass of the lamp. The phosphor coating captures energy of the UV light and reemits visible light.
FIG. 3 (Prior Art) is a circuit diagram of an assembly involving another type of fluorescent lamp fixture 20. This type of fixture employs an electronic ballast 21. Due to the operation of the electronic ballast, no separate starter unit is provided. Wires 23-26 and lamp holders 27 and 28 are parts of the fixture. Electronic ballast 21 receives 50-60 Hz AC power from AC source 16, and then supplies a T8 fluorescent lamp 22 with an AC power signal having a higher frequency (for example, 20 kHz). Fluorescent lamps are generally more efficient in terms of converting electrical energy into visible light when they are driven at a higher frequency such as 20 kHz as opposed to when they are driven with an AC signal at 50-60 Hz. For these and other reasons, new fluorescent lamps fixtures are generally of the electronic ballast type. Legacy type fixtures as shown in FIG. 1 still exist, but generally are older fixtures that have been installed and in use for some time.
FIG. 4 (Prior Art) is a circuit diagram of an assembly in which a so-called "T8-to-T5 retrofit assembly" 30 has been installed in a legacy fluorescent lamp fixture. The T8-to-T5 retrofit assembly 30 has the approximate form factor of an ordinary T8 fluorescent lamp. In this form factor, the T8-to-T5 retrofit assembly 30 provides two G13 bi-pin bases 31 and 32 mounted in opposing fashion as illustrated so that the T8-to-T5 retrofit assembly 30 can be installed in lamp holders 33 and 34 in place of a T8 lamp. In addition, retrofit assembly 30 includes an electronic ballast 35, a T5 fluorescent lamp 36, and two T5 lamp holders 37 and 38 configured to hold the T5 lamp. The electronic ballast 35 receives 50-60 Hz AC power from AC source 16. A first conductive path extends from AC source 16, through ballast 39, through wire 40 of the legacy fixture, through contact 41 of lamp holder 33, and into the T8-to-T5 retrofit assembly, and to a first power input of electronic ballast 35. A second conductive path extends from AC source 16, through wire 42 of the legacy fixture, through contact 43 of lamp holder 34, into the T8-to-T5 retrofit assembly, through a short connection 44 within the retrofit assembly, back out of the T8-to-T5 retrofit assembly via contact 54 of lamp holder 34, through wire 45 of the legacy fixture, through a dummy short 46 that is installed in starter socket 47, through wire 48 of the legacy fixture, through contact 49 of lamp holder 33, back into the retrofit assembly, and to a second power input of electronic ballast 35. The electronic ballast receives AC power through these two conductive paths. The electronic ballast drives the T5 fluorescent lamp 36 via four conductors 50-53. The existence of magnetic ballast 39 in the AC current path between AC source 16 and electronic ballast 35 does not interfere with operation of the electronic ballast. The magnetic ballast is of such an inductance that at the low 50-60 Hz frequency of the incoming AC power signal, the magnetic ballast has only a small impedance. By replacing a T8 lamp of a legacy fixture with such a T8-to-T5 retrofit assembly, power savings due to more efficient operation of the lamp can be realized. The fact that the smaller T5 lamp may output less light than the original larger T8 lamp is generally acceptable considering the improved efficiency gained.
FIG. 5 (Prior Art) is a circuit diagram of a proposed circuit whereby an owner of a legacy fixture 55 can achieve even more power savings as compared to using the circuit of FIG. 4. In the assembly of FIG. 5, an RF-enabled switch 56 is provided in the starter unit socket 57 of the legacy fixture. The internal wiring of the legacy fixture of the circuit of FIG. 5 is identical to the internal wiring of the legacy fixture of FIG. 1. The T8-to-T5 retrofit assembly 61 of FIG. 5 is identical to the T8-to-T5 retrofit assembly 30 of FIG. 4. The legacy fixture is generally a fixture that has been installed and used with T8 bulbs for many years, and is now being retrofitted to improve efficiency.
In the assembly of FIG. 5, the circuitry of the RF-enabled switch 56 receives power via existing conductors 58 and 59 of the legacy fixture. A switch in the RF-enabled switch 56 can be made to open in response to receiving an RF control signal 60. If the switch is open, then power to the retrofit assembly 61 is cut off, lamp 62 is therefore off and is not powered. The switch in the RF-enabled switch 56 can also be made to close in response to receiving another RF control signal 63. If the switch is closed, then power is supplied through the RF-enabled switch 56 and to the retrofit assembly 61. The retrofit assembly 61 responds in standard fashion and drives lamp 62 so that lamp 62 is illuminated. By turning the lamp off when light is not needed, additional power savings can be realized in addition to the power savings achieved by simple use of the retrofit assembly.
In one example, the circuit of FIG. 5 is installed in a room. A remotely located infra-red occupancy detector circuit (not shown) detects whether there are people in the room. If no people are detected and it is determined that light from lamp 62 is not needed, then the infra-red occupancy detector circuit transmits RF control signal 60 to the RF-enabled switch 56 thereby causing lamp 62 to be turned off. If, however, people are detected to be in the room, then the infra-red occupancy detector circuit may transmit RF control signal 63 to the RF-enabled switch 56 thereby causing lamp 62 to be turned on. By keeping the lamp 62 off when it is not needed, the circuit of FIG. 5 achieves additional power savings as compared to the circuit of FIG. 4.

Remote control of a legacy fluorescent lamp fixture


A combinational commodity engaging unit which can connect by engaging plates of a computer desk, a TV cabinet etc. in order to assemble the combinational commodity without using an auxiliary tool, the engaging unit includes at least: a fixing seat embedded in a first plate, a hollow engaging member embedded in a second plate and having its bottom portion engaged in the fixing seat, and a fixing rod extended into the interior of the hollow engaging member to maintain the hollow engaging member in a state of engaging the fixing seat. By combination of the above stated fixing seat, hollow engaging member and fixing rod, the combinational commodity can be assembled without using an auxiliary tool.

1. Field of the Invention
The present invention relates to a combinational commodity engaging unit, and especially to such a unit which can connect by engaging plates of a computer desk, a TV cabinet etc. in order to assemble a combinational commodity without using an auxiliary tool.
2. Description of the Prior Art
Markets have been being located everywhere to make customers enjoy the fun and achievement of do it yourself DIY combination; hence there have been various combinational commodities such as computer desks, TV cabinets etc. for promotion on shelves for customers to do DIY combination. In assembling these combinational commodities, normally screws are screwed in or wooden dowels are hammered in to connect a top plate with a supporting side plate.
However, no matter the way of screwing in screws or hammering in wooden dowels to assemble a combinational commodity is used, during the process of assembling by a customer himself, he needs a tool such as a screw driver or hammer etc., for instance: he shall exert force to screw in screws or hammer in wooden dowels, this is energy consumptive and is inconvenient as well to the customer.
And more, plates on a combinational commodity mostly are highly compacted plates or wooden plates; when these plates are tightened for connecting by screwing in screws, they are subjected to making their screw holes get broken screw threads; this not only renders the commodity hard to be assembled firmly, but also renders the same unable to be repeatedly assembling and disassembling.
In view of this, the inventor of the present invention provides an engaging unit which is assembled by engaging, in order to assemble a combinational commodity without using an auxiliary tool.


The present invention describes modulator of protein kinase B (PKB)/Akt proteins, exemplified by the Tribbles (TRB) family. An exemplary member of the TRB family, TRB-3, binds to Akt and inhibits its catalytic activity, in turn causing altered regulation of glucose metabolism pathways. TRB-3 expression is strongly induced in the fasting state, and upregulated in mouse models of type II, causing disruptions in insulin signaling. Accordingly, the present invention further provides compositions and methods for disrupting the interaction between such a modulator and PKB/Akt protein kinases. Also provided are methods of determining if a subject has a predisposition to impaired glucose regulation and methods for treating diabetes mellitus using invention compositions.

Under physiologic conditions, binding of insulin to the insulin receptor stimulates its intrinsic tyrosine kinase activity, leading to tyrosine phosphorylation of the insulin receptor substrates (IRS1 and IRS2) (Virkamaki et al., J. Clin. Invest. 103:931–943, 1999; White, Mol. Cell. Biochem. 182:3–11, 1998), and activation of downstream signaling pathways via the recruitment of cytoplasmic effector proteins containing SH2 domains which recognize tyrosine phosphorylated IRS proteins. For example, recruitment of the p85 subunit of the PI3K (Ruderman et al., Proc. Natl. Acad. Sci. USA 87:1411–1415, 1990) in response to insulin triggers a phospholipid dependent kinase cascade that culminates in the activation of a protein kinase B (PKB)/Akt (Brazil and Hemmings, Trends Biochem. Sci. 26:657–664, 2001). The activation of PI3K appears particularly critical for insulin signaling; most of the effects of insulin on glycogen synthesis and glucose transport are blocked in cells treated with PI3K inhibitors (Shepherd et al., Biochem. J. 305:25–28, 1995).
Diabetes mellitus is among the most common of all metabolic disorders, affecting up to 11% of the population by age 70. Type I diabetes (also referred to as insulin dependent diabetes mellitus or IDDM) represents about 5 to 10% of this group and is the result of a progressive autoimmune destruction of the pancreatic beta-cells with subsequent insulin deficiency.
There are two classes of type II diabetes (also referred to as non-insulin dependent diabetes mellitus or NIDDM). One typically presents in older people; thus it is sometimes called mature onset diabetes. Another form, though similar to mature onset, presents in a subject at a very early age. Type II diabetes represents 90–95% of the affected population, more than 100 million people worldwide (King and Zimmer, Wld. Hlth. Statist. Quart. 41:190–196, 1988; Harris et al., Diabetes Care 15:815–819, 1992), and is associated with peripheral insulin resistance, elevated hepatic glucose production, and inappropriate insulin secretion (DeFronzo, Diabetes 37:667–687, 1988). Family studies point to a major genetic component (Newman et al., Diabetologia 30:763–768, 1987; Kobberling, Diabetologia 7:46–49, 1971; Cook, Diabetologia 37:1231–1240, 1994). However, few susceptibility genes have been identified.
Type II diabetes is characterized by a patient's inability to respond to insulin and/or insufficient insulin secretion. Insulin exerts a dominant effect on the regulation of glucose homeostasis. In the liver, insulin inhibits the production of glucose by inhibiting gluconeogenesis and glycogenolysis. Insulin is thought to act by causing cells to absorb glucose from the blood stream. Once absorbed, the liver converts glucose to glycogen. The liver supplies glucose by converting glycogen stores to glucose. Insulin also has a major role in the regulation of protein and lipid metabolism through a variety of actions that affect the flux of protein and lipid substrates.
Key molecules in the regulation of insulin are the protein kinase B/Akt family of enzymes. The protein kinase B (PKB)/Akt kinases consists of at least three members (Akt1, Akt2, Akt3), collectively referred to herein as "Akt", that share extensive sequence homology but appear to perform distinct biological functions (Brazil and Hemmings, supra). Targeted disruption of Akt2, for example, leads to insulin resistance and glucose intolerance due to elevated hepatic gluconeogenesis and reduced glucose uptake in skeletal muscle (Cho et al., Science 292:1728–1731, 2001). By contrast, disruption of the Akt1 gene leads to growth retardation and apoptosis in certain tissues, with no apparent change in glucose homeostasis (Chen et al., Genes Dev. 15:2203–2208, 2001; Cho et al., J. Biol. Chem. 276:38349–38352, 2001). The mechanism underlying functional specification of Akt1 and Akt2 in liver and other tissues is unclear, but may involve subtle differences in substrate preference or in the ability of these kinases to associate preferentially with certain modulatory factors. In a recent study, Hemmings and coworkers described a C-terminal Akt modulatory protein, referred to as CTMP, that inhibits Akt activity at the plasma membrane and in the cytoplasm by binding to the C-terminal regulatory domain of Akt and blocking its phosphorylation at Thr308 and Ser473 (Maira et al., Science 294:374–380, 2001). Relative affinities of CTMP for Akt1 or Akt2 were not examined in this study, however.
Following activation in response to insulin, Akt inhibits glycogenolysis and promotes glycogen synthesis via direct phosphorylation of glycogen synthase kinase 3β at Ser9 (Brady et al., J. Biol. Chem. 273:14063–14066, 1998; Delcommenne et al., Proc. Natl. Acad. Sci. USA 95:11211–11216, 1998; Hajduch et al., Diabetes 47:1006–1013, 1998; Mitsuuchi et al., J. Cell. Biochem. 70:433–443, 1998; van Weeren, J. Biol. Chem. 273:13150–13156, 1998). Akt also appears to block gluconeogenic genes such as glucose-6-phosphatase and PEPCK, in part by phosphorylating and promoting nuclear export of members of the Forkhead family of transcriptional activators (Guo et al., J. Biol. Chem. 274:17184–17192, 1999; Kops et al., Nature 398:630–634, 1999; Nakae et al., J. Biol. Chem. 274:15982–15985, 1999). In recent studies, insulin has also been found to block gluconeogenesis by inhibiting the expression of the nuclear hormone coactivator PGC-1, although the underlying mechanism has not been elucidated (Herzig et al., Nature 413:179–183, 2001; Yoon et al., Nature 413:131–138, 2001).
In response to insulin stimulation, Akt is recruited to the plasma membrane via an interaction between its pleckstrin homology (PH) domain and phosphoinositol-(3, 4, 5)P3 (PI3P), a product of phosphoinositol 1,3-dependent kinase (PI3K). Binding to PI3P is thought to promote a conformational change in Akt that renders the protein competent for subsequent activation events. Following binding to PI3P, Akt is phosphorylated at two residues: Thr308 within the active loop and Ser473 in the regulatory domain (Brazil and Hemmings, supra). Thr308 phosphorylation is mediated by the phosphoinositide-dependent kinase-1 (PDK-1) a PH domain kinase whose activity is also regulated by PI3K. Consistent with the importance of Thr308 phosphorylation for Akt catalytic activity, Akt activation is absent in PDK1−/−cells (Williams et al., Curr. Biol. 10:439–448, 2000). Ser 473 phosphorylation also contributes to Akt activation, although the identity of the Ser 473 Akt kinase is unknown.
By contrast with the well-characterized events leading to Akt activation, the mechanisms by which Akt activity is attenuated following insulin stimulation are less clear. Nevertheless, a number of upstream negative regulators have been identified; and the best characterized to date is the phosphatase-tensin homolog protein (PTEN), a potent lipid phosphatase that blocks Akt activation by dephosphorylating 3-phosphoinositides. PTEN is often mutated in a variety of sporadic cancers as well as in certain hamartoma syndromes; and tumors that harbor inactive PTEN correspondingly often contain elevated levels of Akt activity (Backman et al., Nat. Genet. 29:396–403, 2001; Ramaswamy et al., Proc. Natl. Acad. Sci. USA 96:2110–2115, 1999). In addition to PTEN, the SH2-containing inositol 5′ phosphatase (SHIP), which hydrolyzes PI(3,4,5)P3 to PI(3,4)P2, has also been found to inhibit Akt activity; and SHIP −/−cells exhibit prolonged activation of Akt upon stimulation (Aman et al., J. Biol. Chem. 273:33922–33928, 1998; Liu et al., Genes Dev. 13:786–791, 1999).
Although lipid phosphatases constitute important upstream regulators of Akt, the Ser/Thr protein phosphatase 2A (PP2A) also appears to inhibit Akt via direct dephosphorylation of Thr308 and Ser473. In this regard, dephosphorylation and inactivation of Akt in response to hyperosmotic shock can be blocked by addition of calyculin, a relatively specific inhibitor of PP2A (Meier et al., EMBO J. 17:7294–7303, 1998). The degree to which PP2A contributes to Akt inactivation in vivo, however, is not well understood.
In the fed state, insulin promotes glucose homeostasis by stimulating glucose uptake in muscle and fat, and by blocking glucose production in liver (Saltiel and Kahn, Nature 414:799–806, 2001). Mice with an insulin receptor knockout in liver show glucose intolerance due in part to elevated glucose production (Michael et al., Mol. Cell. 6:87–97, 2000). Unchecked hepatic gluconeogenesis is an important contributor to fasting hyperglycemia in Type II diabetes, suggesting that the liver is a major site for glucose intolerance and insulin resistance in this disease.
In the fasted state, blood glucose levels are maintained through hepatic output of glucose, mediated predominantly by a fall in insulin and a rise in counter-regulatory hormones, i.e. glucagon (cAMP) and adrenal glucocorticoids. Glucagon promotes gluconeogenesis, in part, by stimulating the protein kinase A (PKA) mediated phosphorylation of the cAMP responsive element binding protein (CREB) (Imai et al., J. Biol. Chem. 268:5353–5356, 1993; Liu et al., J. Biol. Chem. 266:19095–19102, 1991; Quinn and Granner, Mol. Cell. Biol. 10:3357–3364, 1990). Expression of a dominant negative CREB inhibitor, referred to as A-CREB, in liver either acutely by infection with A-CREB Adenovirus, or chronically by transgenic expression in mice, causes hypoglycemia with reduced expression of all gluconeogenic genes (Herzig et al., supra). CREB was found to promote expression of the gluconeogenic program by stimulating expression of the nuclear hormone receptor coactivator PGC-1 (Herzig et al., supra; Yoon et al., supra) via a cAMP response element (CRE) site in the PGC-1 promoter. The ability of PGC-1 to promote expression of gluconeogenic genes in response to glucocorticoid signals likely explains the cooperativity between cAMP and glucocorticoid pathways in regulation of hepatic glucose production (Herzig et al., supra; Yoon et al., supra).
In addition to stimulating glucose output, chronic fasting has been found to induce insulin resistance in liver downstream of the insulin receptor. Indeed, glucocorticoids and, to a lesser extent, catecholamines, also induce hepatic insulin resistance by blocking post-receptor insulin signaling (Paez-Espinosa et al., Mol. Cell. Endocrinol. 156:121–129, 1999; Rao, Metabolism 44:817–824, 1995). The mechanism underlying insulin resistance in this setting remains obscure, but suggests the presence of an inducible negative signal that impairs insulin signaling under fasting conditions.
Thus, there remains a need in the art for methods to modulate enzymatic pathways in glucose regulation, particularly modulators of PKB/Akt kinases. Among other essential pathways in glucose regulation, these critical kinases inhibit glycogenolysis, promote glycogen synthesis, and block gluconeogenic genes. These pathways are all involved in diabetes mellitus, and modulators of PKB/Akt kinases present novel methods of diagnosis and treatment.

Protein kinase B/Akt modulators and methods for the use thereof

The Salk Institute for Biological Studies


A series of electronic components formed using a carrier tape. The carrier tape is adapted to enable smoothly picking up even small-sized electronic components with a suction nozzle. The carrier tape has housing holes housing electronic components therein. The housing holes are arranged in the longitudinal direction. A top tape and a bottom tape are attached to the upper and lower surfaces of the carrier tape. Interval portions between the housing holes are provided with concave slots in their lower surfaces, thereby forming air flow paths. The air flow paths form air passages which enable smoothly picking up the small-sized electronic components using a suction nozzle.

Series of electronic components of interest for the present disclosure are as follows.
(1) Series of electronic components having a plastic embossed tape as a package tape, wherein concave portions are formed in the plastic base member through embossing processing and, further, the openings of the concave portions are covered with a top tape in a state where electronic components are housed within the concave portions (refer to JP 63-23259 A, for example).
(2) Series of electronic components having a base member made of a cardboard which necessitates a relatively-lower material cost, as a carrier tape, wherein the carrier tape is provided with housing holes which penetrates it, and cover films (a top tape and a bottom tape) are attached, through a heat sealing method, to the opposite surfaces of the carrier tapes in a state where electronic components are housed within the concave portions (refer to JP 6-286715 A, for example).
(3) Series of electronic components having, as a package tape, a cardboard base material which has one main surface maintained to be flat and, further, has the other main surface provided with concave portions, wherein a lid member is attached thereto in such a way as to cover the openings of the concave portions in a state where electronic components are housed within the concave portions (refer to JP 10-338208 A, for example).
Currently, for coping with small-sized electronic components having a planner dimension of 0.6 mm×0.3 mm (hereinafter, which will be referred to as "0603 size", in some cases) or smaller sizes, the main stream has been to employ the series of electronic components which is described in JP 10-338208 A, out of the series of electronic components which are described in JP 63-23259 A, JP 6-286715 A, and JP 3066370 B1. This is because the series of electronic components described in JP 63-23259 A and the series of electronic components described in JP 6-286715 A have inconveniences as follows.
At first, the series of electronic components described in JP 63-23259 A has the problem that the plastic embossed tape necessitates a relatively-higher material cost. On the other hand, in the series of electronic components described in JP 6-286715 A, the top tape is attached to the carrier tape only at its opposite side edges extending in the longitudinal direction, while the bottom tape is attached to the carrier tape over its entire surface except the portions of the housing holes. In this case, when the housing holes are made to have a reduced size for coping with size reduction of the electronic components to be housed therein, if the bottom tape is molten up to its portions for covering the housing holes during heat sealing, this may cause the electronic components housed therein to be adhered to the bottom tape.
However, even with the series of electronic components described in JP 10-338208 A, when the electronic components are picked up from the concave portions in the cardboard package tape, through suction with a suction nozzle, in a mounting process, there is no air passage in the bottom surfaces of the concave portions. This has induced the problem of difficulty of sucking them with the suction nozzle, in some cases. In order to overcome this problem, JP 3066370 B1 discloses a technique for providing air vent opening holes which penetrate the bottom surfaces of the concave portions.
However, when the electronic components to be housed therein have smaller sizes, such as a 0630 size or less, it is hard to form such air vent opening holes. This is because the ratio of the area of such opening holes to the area of the bottom surfaces of the housing holes should be increased and, furthermore, there is a risk of capture of the electronic components by the opening holes. Actually, JP 3066370 B1 makes no disclosure about the sizes of the electronic components to be housed therein.
Further, in the case of the series of electronic components described in JP 10-338208 A, it is necessary to employ, as a package tape, a cardboard base material which has one main surface maintained to be flat and, further, has the other main surface provided with concave portions. However, it should be noted that there are constraints on paper materials which enable such processing, thereby inducing the problem of larger material costs.

Carrier tape, package tape and series of electronic components


A deposition system for winding of a large-scale superconducting magnet coil. First and second conductor supports withstand the weight of a bent conductor and allow the conductor to be lowered down in spiral and be placed smoothly onto a rotary table. The rotary table bears the weight of coils, rotates according to a contour of the coil and forwarding speed of the conductor, and tracks the winding trajectory of the coil accurately, which avoids the extra stress induced onto the conductor. The conductor placed on the rotary table is reliably clamped by clamping fixtures and adjustable rod to ensure the conductors to be placed on correct radial and toroidal positions. After treated by the deposition system, the conductor is placed to a corresponding position on the rotary table smoothly and accurately to achieve a high-precision contour control of the coil.

Thermonuclear fusion is a sustainable and clean energy source, and there is a plan to set up the International Thermonuclear Experimental Reactor (ITER) within the next ten years. The required magnetic field is provided by superconducting magnet coils in a Tokamak to control and confine high-temperature plasma. The winding of coils which ensures the dimensions of coils is significant for the production of the superconducting magnet coils. Generally, the large-scale superconducting magnet coils are wound by using the strain-free multi-pancakes configuration. In this configuration, the winding is performed from the outer radius to the inner radius "outside-in" for the first pancake, and from the inner radius to the outer radius "inside-out" for the second pancake. The above steps are repeated until the winding of multi-pancake coils is completed. Turn-to-turn joggles are needed in each pancake to accomplish the proper positioning of the conductor during winding, as well as a joggle to make the transition from one pancake to the next. During the winding of coils, conductors are forwarded and bent through a bending machine, and each turn of the bent conductor is placed through a deposition system at a specific position on the rotary table smoothly and accurately, ensuring a high precision of coil dimensions after the winding. Therefore, as an important part of the winding superconducting magnet coils, the deposition system is required to withstand the weight of the coils, and ensure the conductors to be placed at specific position on the rotary table smoothly and accurately. Moreover, the rotary table is also functioning at tracking the winding trajectory, to avoid extra stress induced on the conductors.

Deposition system for winding of large-scale superconducting magnet coils

HEFEI INSTITUTES OF PHYSICAL SCIENCE, CHINESE ACAD


The present invention relates to the co-administration of two neurotransmitter agonists to patients with motor disorders, for the purpose of symptom reduction. In particular the present invention provides methods and compositions for alleviation of akinesia, rigidity and/or tremor associated with Parkinson's disease.

Parkinson's disease is a chronic, progressive, hypokinetic disorder characterized by impaired voluntary movement (See, Dale and Federman (eds.), WebMD Scientific American Medicine, NY: WebMD Corporation, Chapter 11, Section 15, pp. 1-21, 2001; Lang and Lozano, N Engl J Med, 339:1044, 1998; and Lang and Lozano, N Engl J Med, 339:1130, 1998). Parkinson's disease occurs as a result of the death of dopamine-producing neurons in the substantia nigra of the midbrain. Dopamine is a neurotransmitter, or chemical messenger, that transports signals to the parts of the brain that control movement initiation and coordination. The loss of dopamine in the brain is associated with multiple primary symptoms including: tremor of the hands, arms, legs, jaw, and face; rigidity or stiffness of the limbs and trunk; bradykinesia or slowness of movement; and postural instability or impaired balance and coordination.
Parkinson's disease afflicts more than one million persons in the United States alone (Lang and Lozano, supra, 1998), with approximately 50,000 new cases diagnosed each year. It is generally a disease of late middle age, with typical onset occurring at about age 60. About five percent of patients, however, have early-onset disease and are younger than 40 when symptoms begin.
Most current treatment strategies for Parkinson's disease (PD) focus on symptom control through one or more of medication, surgery, and physical therapy. The dopamine precursor, levodopa (L-DOPA) is still considered to be the gold standard in terms of treatment for PD (Schapira and Olanow, JAMA, 291:358-364, 2004). Unfortunately, L-DOPA can cause debilitating side effects (LeWitt and Nyholm Neurology, 62:S9-S16, 2004), including severe nausea, vomiting, and psychosis. Moreover, with prolonged use, patients frequently experience other side effects such as dyskinesias (spontaneous, involuntary movements) and "on-off" periods when the medication will suddenly start or stop working.
Surgical treatments are considered for patients with advanced disease or who have not responded adequately to medications. Accepted surgical treatments involve either the creation of small, precise lesions or the implantation of stimulating electrodes in specific brain regions that appear to be overactive in Parkinson's disease. More recently, implantation of fetal dopaminergic tissue has been utilized as a means of restoring dopamine levels in the brains of patients with Parkinson's disease (See, e.g., Freed et al., Arch Neurol, 47:505-512, 1990; and Lindvall et al., Science, 247:574-577, 1990). These types of methods, however, are highly invasive.
Thus, what is needed in the art are noninvasive treatment strategies for effectively controlling symptoms of Parkinson's disease and other movement disorders. In addition, it would be desirable to be in possession of therapy regimens that maximize the efficacy of existing medicines.

Pharmacological treatment of Parkinson's disease

The United States of America as Represented by the Department of Veterans Affairs


A system and method for facilitating a secured value transfer. A first user and the system obtain a pair of encryption and decryption apparatuses. The first user creates a request including his unique identifier and a value to be transferred. The first user encrypts the request using the encryption apparatus and sends it to the second user. The second user sends to the system the request and the second user's unique identifier. The system uses the decryption apparatus to decrypt the request. The system checks the usage of the request against a threshold limit. After a successful usage check, the system then transfers the value from the first user to the second user. The system may comprise (a) a plurality of system server for exchanging data with users' personal computing devices, registering users, and conducting transactions, and (b) data storages storing user accounts and other persistent data.

Nowadays electronic payment, for example mobile payment, is increasingly popular. Mobile payment provides an on-the-go payment option. The popularity of mobile payment is also assisted by the proliferation of handheld digital devices such as smart phones (e.g. iPhone, Android-based phones). Depending on whether payment is processed through a wireless carrier, the forms of mobile payment may be sorted to two categories: carrier-based ones and non-carrier-based ones.
A current form of carrier-based mobile payment is to use a text messaging service. User makes payment by sending a text message to a predefined number. For example, AT&T currently supports carrier-based mobile paperless payment option, in which a user (payer) can send a message to a short code. The message is sent through Short Message Service (SMS) and the short code is a special number which is significantly shorter than the full telephone number. Because SMS-based mobile payment is a carrier-based solution, it limits user's selection of payment processing agents to wireless carriers. The SMS-based mobile payment also requires that a wireless communication is present between a payer's mobile device and the system. There are also some security/privacy concerns on sending payment as a regular text message.
Mobile web payment is another form of mobile payment. A payer browses the webpage of a payee on an internet-connected mobile device, and makes an online purchase. After the transaction, the payee sends out the good that the user purchases, or provides a receipt page which the payer may print out and bring to the payee's store for pickup. Although this mobile web payment is through mobile device, it is just a special case of online payment which generally involves the user to use an internet-connected device such as his/her personal computer to view the payment page and make the purchase. Mobile web payment requires that an internet connection is presented between a payer's mobile device and the system. Another concern on mobile web payment is how well it may fit into a traditional workflow of off-line purchases: for example, to purchase a cup of coffee at a local coffee store through mobile web payment, a user views the store's webpage and makes a payment, instead of just paying at cashier directly.
Contactless Near-Field Communication (NFC)-Based Payment is yet another form of mobile payment. In NFC-based payment system, user's mobile device is equipped with a NFC chip. At the time of transaction, the payer touches his/her NFC-enabled mobile device at a NFC-equipped sales terminal. The system then processes the payment using the information provided by the payer's mobile device. The sales terminal may optionally request the payer to enter his/her PIN to authorize the transaction. NFC-enabled payment requires some significant infrastructure investment. To receive payments, small business owners need to invest on NFC-equipped sales terminals.

System and methods for using limit-use encrypted code to transfer values securely among users


A developing apparatus having a rotatable toner carrier for transporting a toner to a developing region where it faces an image carrier on which a latent image has been electrostatically formed. The surface of the toner carrier is constituted by a mixture of conductive surface portions and dielectric surface portions and selectively holds a charge to form microfields. The toner having been charged is electrostatically deposited on the toner carrier by the microfields and transported to the developing region as the toner carrier moves. In the developing region where the toner carrier and the image carrier face each other while defining a developing gap therebetween, the toner electrostatically flies from the toner carrier to the latent image formed on the image carrier to thereby develop it.

The present invention relates to a developing apparatus of the type causing a developer carrier to carry and transport a one-component developer to a developing region where the developer carrier faces an image carrier so as to develop a latent image electrostatically formed on the image carrier. More particularly, the present invention relates to a developing apparatus which develops a latent image by use of a developer carrier capable of forming microfields thereon.
A developing apparatus of the type using a powdery dry developer is extensively used with an electrophotographic copier, laser beam printer, facsimile transceriver or similar electrophotographic image forming equipment which electrostatically forms a latent image on an image carrier such as a photoconductive element and develops it by a developer. The powdery developer is available as a two-component developer which is the mixture of a toner and a carrier or a one-component developer which does not contain a carrier. Although a developing apparatus using the two-component developer reproduces attractive images relatively stably, the carrier is apt to deteriorate and the mixture ratio of the toner and carrier is apt to change. This results in troublesome management of the apparatus and a bulky construction. For this reason, a developing apparatus which uses the one-component developer free from the above problem is attracting much attention. The one-component developer is implemented with the toner only or with the toner and an auxiliary agent for controlling the polarity and amount of charge. The toner in turn is implemented as a magnetic toner containing magnetic power therein or a non-magnetic toner which does not contain it. Since a magnetic body is usually opaque, a color image, whether it be full-color or multicolor, developed by the magnetic toner does not appear sharp. Therefore, it is preferable to use the one-component developer constituted by the non-magnetic toner for color images.
In a developing apparatus implemented with a one-component developer, a developing roller or similar developer carrier carries the developer thereon and transports it to a developing region where the developer carrier faces an image carrier. In this region, the developer develops a latent image electrostatically formed on the image carrier. A prerequisite with this type of apparatus is that a great amount of sufficiently charged toner be fed to the developing region in order to insure high quality images having predetermined density. When the magnetic toner is used, a sufficient amount of one-component developer may be deposited on the surface of the developer carrier by magnets. However, the non-magnetic one-component developer is immune to magnetism, so that transporting a great amount of developer to the developing region is difficult.
Various implementations have been proposed in the past for eliminating the above problem. For example, a developing apparatus disclosed in Japanese Patent Laid-Open Publication No. 43767/1986 has a developer carrier covered with an insulative dielectric layer, and a sponge roller or similar developer supply member held in pressing contact with the dielectric layer. The developer carrier and the sponge roller are charged to opposite polarities by friction. A non-magnetic one-component developer charged to the opposite polarity to the dielectric layer is electrostatically deposited on the dielectric layer and transported to a developing region. A drawback with this scheme is that the electric field developed in the vicinity of the surface of the dielectric layer is not intense enough to deposit a great amount of toner on the surface of the developer carrier and, therefore, the developer available in the developing region is short. In this condition, forming a developed image or toner image with high density is not easy. To eliminate this drawback, the developer carrier is moved at a speed twice or more higher speed than the moving speed of the image carrier. This, however, brings about another problem that the density of a solid image formed on the image carrier becomes unusually high in a trailing edge portion of the image with respect to the moving direction of the image carrier, resulting in poor image quality.
Another conventional developing apparatus generates an electric field between the developer carrier and the image carrier in a direction for electrostatically transferring the non-magnetic one-component developer toward the developer carrier. Such an approach, however, also fails to deposit a sufficient amount of developer on the developer carrier.
Japanese Patent Laid-Open Publication No. 51841/1979 teaches another approach which uses a developer supply member for positively causing the non-magnetic developer to electrostatically deposit on the developer carrier. Specifically, after the developer carrier has moved away from the developing region, the non-magnetic one-component developer remaining thereon is scraped off. Then, the surface layer of the developer carrier is applied with a charge by corona discharge. The developer supply member positively and electrostatically deposits the non-magnetic developer on the charged surface of the developer carrier. With this approach, it is impossible to increase the amount of developer carried on the developer carrier and, therefore, to feed a great amount of toner to the developing region.
The developer carrier may be provided with undulations on the surface thereof so as to fill them with the non-magnetic one-component developer, as disclosed in Japanese Patent Laid-Open Publication No. 53996/1985. While such a configuration may be successful in increasing the amount of developer to reach the developing region, such a developer contains a substantial amount of toner whose charge is short and, therefore, cannot produce high quality images.
Further, Japanese Patent Publication No. 9711/1980 proposes a developing apparatus having a developer carrier made up of a conductive support member, an insulating layer provided on the support member, and a conductive lattice member provided on the insulating member. The insulating layer is exposed to the outside through numerous openings formed through the lattice member. A voltage opposite in polarity to a developer is applied between the lattice member and the support member to generate microfields, so that a great amount of developer may be deposited on the surface of the developer carrier by the microfields. However, such microfields are not attainable without resorting to at least an exclusive external power source, resulting in a complicated construction. Other approaches for generating microfields are taught in U.S. Pat. No. 3,739,748 (Rittler et al), U.S. Pat. No. 3,645,618 (Lancia et al), U.S. Pat. No. 3,759,222 (Maksymiak et al), and "Microfield Donors for Touchdown Development" by P. G. Andrus et al, SPSE 2nd International Conference on Electrophotography, October 1973.
Invention for eliminating the above problems are disclosed in our pending U.S. patent application Ser. No. 07/597,881 Filed Oct. 12, 1990 and our pending U.S. patent application Ser. No. 07/674,161 filed Mar. 25, 1991. The present invention constitutes a further improvement over such prior inventions.

Developing apparatus using a developer carrier capable of forming microfields on the surface thereof


A strain relief ferrule for attachment to a jacketed cable attaching the cable to a connector housing in a manner that transmits any load applied to the cable into the connector housing. The strain relief ferrule has a deformable body that is crimpable to the cable for attachment therewith. The ferrule is also attachable to said connector housing and characterized in that the deformable body carries at least one tab thereupon that after crimping of the strain relief ferrule, the tab is engageable by a retention member of the housing for attachment thereto.

1. Field of the Invention
This invention relates to connectors and in particular to crimpable strain relief ferrules that are attachable to a cable and a connector so that any load applied to the cable is transmitted to the connector housing so that the load does not effect the internal components of the connector.
2. Summary of the Prior Art
It is well known in electrical connectors to provide strain relief so that a load exerted on a cable is prevented from affecting the components within the connector. This is accomplished by anchoring a jacket of the cable directly to a connector housing. One way of doing so is to form the connector housing with a flange at a cable-receiving portion thereof and then by either spreading the jacket of the cable over the flange and attaching it thereto, such as by cable ties or crimp rings or by inserting the cable into the flange and then deforming the flange about the cable in a manner that retains the cable, such as by crimping. It is also known to over-mould a strain relief boot directly upon the cable that includes a strain relief tail extending along the cable and a strain relief body portion that may be held by the connector housing. Yet another known way of providing strain relief is to mould a strain relief body out of a deformable material and then use a metal or otherwise deformable crimp ring to deform the strain relief body such that the cable is tightly engaged therein. The body may then be attached to the housing.
While all of the afore going known strain relief apparatus perform admirably, it would be desirable to provide an improvement thereupon such that strain relief may be provided in a simpler and more economical manner. It would further be desirable to provide this strain relief in a manner that reduces the number of parts while still performing adequate strain relief. In addition, this strain relief should be provided in a manner that enables the cable to be easily coupled to the connector housing. Finally, it would be helpful if the strain relief were adapted so that the connector could not be assembled until complete crimping occurs.

Crimpable strain relief ferrule having a retention tab thereupon