There is provided a passive network monitoring device that monitors one or more network interfaces between network nodes including a SGW node, a PGW node, an ePDG node, and a PCRF node and a PCEF node. The device receives a handover indication for UE from untrusted non-3GPP network access to 3GPP network access and receives a response to an attach request from one or more of the network interfaces, the response including a MSIP address and a charging ID for the UE. The device determines the UE is from a single subscriber based on each of the handover, the MSIP address of the response and the charging ID of the response, and correlates information for the UE at each of the one or more network interfaces with the single subscriber.

1. Field of the Invention
The present disclosure relates to tracking User Equipment (UE) amongst various types of network access, and more particularly, to correlating UE to a particular subscriber during handover transitions.
2. Description of the Related Art
The 3rd Generation Partnership Project (3GPP) organization specifies the architecture of mobile cellular networks like Global System for Mobile Communications (GSM) and Universal Mobile Telecommunications System (UMTS). The latest mobile network architecture defined by the 3GPP is called Evolved 3GPP Packet Switched Domain—also known as the Evolved Packet System (EPS).
The EPS combines an Evolved Packet Core (EPC) network that is able to connect a new generation of an access network technology called Evolved Universal Terrestrial Radio Access Network (E-UTRAN) as well as the pre-successor of the E-UTRAN called Universal Terrestrial Radio Access Network (UTRAN). The 3GPP EPS is also able to provide connectivity to mobile terminals (also known as User Equipment(s) (UEs)) attached non-3GPP access networks.
3GPP networks also provide for inter-connection between the EPC and non-3GPP access networks. While the 3GPP access networks are based on access technologies standardized by the 3GPP organization, non-3GPP access networks are based on access technologies defined by other organizations like Institute of Electrical and Electronics Engineers (IEEE) and 3rd Generation Partnership Project 2 (3GPP2). For example two technologies defined by the IEEE that may interwork with the EPC are WLAN (Wireless Local Area Network), i.e. the IEEE standard 802.11 family, and WiMAX (Worldwide Interoperability for Microwave Access), also known as the IEEE standard 802.16 family.
Conventional mobile electronic devices such as mobile phones, tablets, computers, etc., are often equipped to communicate on both 3GPP communication networks as well as non-3GPP access networks (e.g., WLAN, etc.). In fact, mobile data offloading refers to the use of complementary network technologies for delivering data originally targeted for 3GPP communication networks. Rules triggering the mobile offloading action can be set by either an end-user (mobile subscriber) or an operator. The code operating on the rules resides in an end-user device, in a server, or is divided between the two. End users use data offloading for data service cost control, the availability of higher bandwidth and the like. Operators use data offloading to ease congestion of cellular networks. However, when subscriber UE transfers to/from 3GPP access from/to non-3GPP access (e.g., untrusted 3GPP access) subscriber information is typically lost. That is, tracking subscribers during UE transfers between networks is difficult at best, which affects accuracy when monitoring key performance indicators, Quality of Service (QoS), and other operating metrics for subscribers.

System and method to correlate handover transitions between 3GPP network access and untrusted non-3GPP network access


An organic electroluminescent device comprising: an organic thin-film transistor element including at least an active layer made of an organic material; and an organic electroluminescent element driven by the organic thin-film transistor element.

Thin film transistors (TFTs) are mainly used for driving pixels of flat-panel-displays typified by liquid-crystal displays, or organic electroluminescent displays. Known thin-film transistors have an active layer comprising an inorganic semiconductor such as silicon or the like.
Since known inorganic semiconductor-thin-film transistors have a little flexibility, it has been difficult to obtain a display in a desired shape. Further, forming known thin-film transistors require complex processes and sophisticated equipment such as high-vacuum equipment.
Subsequently, a first object of the present invention is to provide an organic electroluminescent device which is driven by a thin-film transistor using a flexible organic-semiconductive material, and an electronic apparatus. The second object is to provide a method of manufacturing a thin-film transistor and an organic electroluminescent element using a simple method, such as a liquid-phase process.

Organic electroluminescent device, method of manufacturing the same, and electronic apparatus


The disclosure provides a video coding method and a video coding apparatus and a video decoding method and a video decoding apparatus. The video coding method includes: when determining that a current block is coded in intra block copy prediction mode, carrying first indication information and second indication information in bitstream data corresponding to the current block by a video coder, wherein the first indication information specifies that a prediction mode of the current block is intra prediction, the second indication information specifies that the current block is coded in intra block copy prediction mode; and sending the bitstream data with the first indication information and the second indication information by the video coder. In this way, efficiency of a video decoder to know that a data block is coded in intra block copy prediction mode may be improved by using the video coding method, and consistence between syntax and semantics when prediction coding/decoding the data block in intra block copy prediction mode may be ensured.

Prediction coding is a common coding method in video compression. Commonly used prediction coding modes may include an intra prediction mode (also named as MODE INTRA) and an inter prediction mode (also named as MODE INTER). Intra prediction indicates a prediction realized by using only data elements of a current picture (such as sample values). Inter prediction indicates a prediction realized by using data elements of coded pictures other than the current picture (such as sample values or motion vectors). According to relevant video compression standard, slice types in a video may include I slice (intra coding slice), P slice (forward prediction coding slice), or B slice (bidirectional prediction coding slice)
Intra block copy technique has been proposed. In the intra block copy technique, also named as intra block matching, a coded reconstruction area of the current picture is taken as a reference area for prediction coding. A prediction mode of a coding unit that is coded in the intra block copy technique may be inter prediction. The intra block copy technique can be used for coding various slices including an I slice, a P slice, and a B slice. For an I slice, if the intra block copy technique is allowed for coding it, the slice type of it may be modified to P slice.


Techniques for profiling systems, such as mobile or embedded devices, are provided. The techniques can profile code executing on these systems based on power used by that code. The system may profile power usage for the entire system or a subsystem, component, or functional unit thereof, for example. The system may determine when a specified amount of power has been used, and a performance sampler may then temporarily stop execution of the code and sample state data. This sampled state data may be provided to a performance analyzer that determines performance of the executing code.

Power consumption of software applications is an essential performance characteristic in today's increasingly mobile computing market. Given the very limited advance in battery capacity in recent years, writing applications that are optimized for power is becoming ever more important.
For traditional desktop applications various performance analysis tools are used to identify performance bottlenecks and optimize code that causes performance degradation. These tools, however, lack an efficient and accurate mechanism for measuring and profiling power consumption of applications running on battery powered devices.
Performance analysis tools are an important component in a software development cycle, nevertheless. Such tools allow developers to identify performance bottlenecks in complex software applications and provide a valuable insight into what causes the bottleneck. Performance analysis may be used by developers in optimizing the code identified by the analysis tools as degrading performance.
To obtain data about application performance, the tools typically profile application code and quantify the usage of various system resources. Application code is loaded and executed in an environment that is able to monitor and record various performance characteristics during code execution. Monitoring a complex software application in its entirety is very expensive and impractical, however. Thus, for efficiency purposes, performance analysis tools periodically sample the code executing environment to obtain an 'accurate' measure of performance. This sampling is either time-based or event-based.
In a time-based analysis, the performance tool periodically takes a snapshot of the current state of the system after a predetermined time, or number of clock cycles. In an event-based analysis, a snapshot is taken every time a certain event occurs within the system, such as a cache miss or branch mis-predict. The sampled performance statistics are used to build a profile of the performance of the application running on the monitored system. For example, to identify code that causes an excessive number of data cache misses, a performance analysis tool can use event based sampling (the event being a data cache miss) to profile application code and determine which code modules are using memory inefficiently. These code modules may then be optimized.
Most performance analysis tools target applications written for desktop computers. However, with computing applications becoming increasingly mobile, mobile applications are becoming an important component of the software developing market. While traditional performance characteristics such as instruction count and memory performance are still relevant, with slow progress in increasing battery capacity, power efficiency of mobile applications has become an important performance characteristic too.
To analyze power requirements of mobile applications, performance analysis tools must include mechanisms that enable the profiling of application power consumption. However, simply incorporating power measurement into the existing performance analysis framework will not yield an accurate profile of an applications' power consumption. Neither time- nor event-based sampling is suited for generating profiles of system power usage that provide an accurate and detailed account of power consumption of different code modules.
Both time- and event-based sampling are driven by parameters unrelated to power consumption and thus cannot provide an accurate power profile. For example, time-based sampling will provide inaccurate measurement as different instructions consume different amounts of power, but may still have the same frequency of execution. Sampling applications periodically does not take into account this property of the system as it assumes that each instruction requires an equal amount of power to execute. Similarly, event-based sampling may be based on memory events or instructions executed, but none of the factors measured are indicative of power consumption. Two different code modules may execute the same instructions over the same time or may trigger a snapshot due to the same event (e.g., the same instruction causing a cache miss), but existing time-based and event-based sampling techniques would fail to recognize any differences in the amount of power consumed by the different modules.

Method and apparatus for profiling power performance of software applications


A method of identifying a wireless power receiver for a mobile device in a wireless power system includes transmitting a first identity of the mobile device to a wireless power base station of the wireless power system via a first wireless communication interface, receiving a first message including the first identity from the wireless power base station via a second wireless communication interface, and identifying the first message is destined to the mobile device according to the first identity.

1. Field of the Invention
The present invention relates to a method used in a wireless power system, and more particularly, to a method of identifying a wireless power receiver in a wireless power system.
2. Description of the Prior Art
With the proliferation of portable electronic devices such as mobile device (MD), smart phone and tablet PC, the demand for charging devices, especially for those provided in public areas, is increasing. In addition, people would like to get rid of annoying wires if possible. One technology which realizes this desire is wireless charging, in which portable electronic device(s) comprising a wireless power receiver is placed on and charged through a wireless power base station (e.g. a power base station comprising a wireless power transmitter).
Wireless Power Consortium (WPC) is a leading organization in the world in defining wireless charging specification. The document 'Wireless Power Transfer—Volume I, part I' in version 1.1.2 released in June 2013 describes an inter-operability interface between a wireless power transmitter (PTX) and a wireless power receiver (PRX).
Currently, the WPC is starting to define a new wireless power standard based on resonant technology, which is also known as Out-of-Band communication technology, wherein a communication interface based on the technologies with higher data rate such as Bluetooth Low Energy (BLE) and Near Field Communication (NFC) is discussed. Among the two candidates, the BLE can reach one Mbps data rate and the NFC can have four hundred Kbps data rate, which implies more applications become possible if such Out-of-Band communication technologies are adopted.
Communication interface is critical due to the need to exchange information between the wireless power transmitter and the wireless power receiver. However, since the Out-of-Band communication technology is not based on modulation of wireless power signals, a mismatch issue, or cross connection, shall be considered. Actually, such mismatch issue is already existed in another standard defined by Alliance for wireless power (A4WP), in which the communication interface between the wireless power transmitter and the wireless power receiver is based on the BLE.
Specifically, please refer to FIG. 1, which is a schematic diagram of a wireless power system 10. The wireless power system includes two wireless power base stations 120 and 140 and two mobile devices 100 and 130. The wireless power base station 120 is supplying power to the mobile device 100 while the wireless power base station 140 is supplying power to the mobile device 130 (denoted with a blank arrow). There shall be a communication interface between the wireless power base station 120 and the mobile device 100, which allows the wireless power base station 120 to get feedback information, such as the amount of power received, from the mobile device 100. However, in some cases the mobile device 100 mistakenly connects to the wireless power base station 140 instead of the wireless power base station 120 (denoted with a dashed arrow). On the other hand, the mobile device 130 which shall connect to the wireless power base station 140 now connects to the wireless power base station 120. In other words, the mobile device 100 connects to (and thus communicates with) the wireless power base station 140 which is not the wireless power base station 120 supplying power to this mobile device 100. It is indeed a mismatch and both the wireless power base stations 120 and 140 cannot identify the mobile devices 100 and 130 to which they are supplying power to get correct feedback information from the mobile devices 100 and 130. Due to the mismatch, the information sent from either the wireless power base station or the mobile device may go to wrong destination. For example, the wireless power base stations 120 and 140 may provide wrong, e.g. excess or deficient, charging power to the mobile devices 100 and 130.
Therefore, there is a need to implement identification mechanism between the mobile device and the wireless power base station to solve the abovementioned issue.

Method of identifying wireless power receiver in wireless power system


A method for simulating motion of cloth or other flexible membranes corrects surface-to-surface intersection involving a membrane. The method may be applied at time intervals of a conventional motion simulation for computer-generated animation. When a collision is detected, a function for a line of intersection between intersecting surfaces is parameterized in terms of vertices of the membrane model. The function is differentiated, and a correction factor is applied to the dynamic simulation in proportion to the value of the partial derivative for respected ones of the intersected vertices. The correction factor may be smoothed over a number of vertices in the vicinity of the intersected vertices.

1. Field of the Invention
The present invention relates to a computer-implemented method for simulating the motion of cloth and cloth-like materials, such as used in computer-generated animation and moving visual effects.
2. Description of Related Art
Computer-simulations of cloth and other thin flexible materials is known in the art of computer-generated graphics. Such simulation is used as an animation tool in the production of motion pictures, videos, computer games and other forms of video entertainment. Various methods have been developed to provide a plausible simulation of cloth movement, while limiting the computational complexity of the method so as to reduce the amount of computing resources required.
Notwithstanding their advantages, prior art methods for simulation of cloth and other thin materials are subject to certain disadvantages. These disadvantages may be frequently encountered when simulating the movement of clothing worn by a computer-generated character. Being made of thin, flexible material, clothing deforms and moves in a complex way in response to movements of the animated character. Prior-art methods for simulating cloth are not capable of accurately simulating certain types of movement, or require more computational resources than desired to do so.
For example, prior-art collision-response algorithms to do not provide accurate results when clothing is pressed or pinched tightly together. This situation may occur frequently as animated characters move about and interact. Simulated clothing can easily become pressed between or beyond simulated body parts and adjoining clothing. The modeled clothing therefore intersects with itself or adjoining objects in ways that would be impossible in nature, often while being wrinkled, crumpled, or folded in complex ways. Simulating cloth behavior while avoiding or recovering from self-intersections for complex garment meshes remains a vexing problem, particularly when known simulations cause a piece of cloth to intersect with itself. Prior-art methods may become confused and are generally unable to untangle severely self-intersected portions of cloth, or may require too many frames to correct a self-intersection problem. Expensive simulation runs may thereby be ruined, or placed in need of manual repairs and touch-up.
It is desirable, therefore, to provide a computationally-efficient method for simulating motion of cloth, and more particularly, for correcting intersections between adjacent portions of simulated cloth or other thin deformable material. The method should also provide for efficiently correcting or preventing intersections generally between simulated cloth and adjacent objects of any desired type.


A support is provided for supporting the lower header plate and adjacent tube ends of a radiator core within an oven area for even heating thereof preparatory to manually pry and scrapping softened epoxy material from the header plate and about the tube ends. A method also is incorporated wherein after the original epoxy has been removed, fresh epoxy is applied to the header plate about the tube ends and allowed to cure.

1. Field of the Invention
This invention relates to an apparatus for supporting, alternately in upright and inclined positions, a radiator core and includes structure whereby the lower header plate of the radiator core and the adjacent tube ends may be contained within a substantially closed oven into which heated air may be introduced, the heating of the lower end plate and the adjacent tube ends serving to soften the epoxy bonding the tube ends to the header plate in order that the epoxy may be removed. The invention also incorporates the method steps carried out through the utilization of the apparatus for re-epoxying a header plate to the corresponding tube ends.
2. Description of Related Art
Various different forms of radiator supports and methods and apparatuses for joining aluminum heat exchange coils through the utilization of epoxy heretofore have been known. Examples of these previously known apparatuses are disclosed in U.S. Pat. Nos. 1,410,410, 3,149,825, 3,726,466, 3,828,412 and 4,371,106. However, these previously known devices do not include the laterally slidable as well as pivotal oven component of the instant invention, various other components of the apparatus, nor a method of re-epoxying radiator core tube ends to end plates by heating the original epoxy for removal thereof and re-applying new epoxy.

Method and apparatus for re-epoxying radiator header plate to core tubes


A sense amplifier for a nonvolatile writeable memory is described. The sense amplifier has a preamplifier coupled to receive a signal from a cell of the nonvolatile writeable memory. The preamplifier uses a grounded-gate p-channel metal-oxide semiconductor input stage. A differential input latch is coupled to the preamplifier output. The differential input latch uses a pair of cross-coupled inverters. A logic device is coupled to the differential input latch output and provides the sense amplifier output signal. The logic device reduces the offset in the differential input latch and provides an output indicative of one of a number of states or voltage levels of the cell.

Many computing systems such as personal computers, automotive and airplane control, cellular phones, digital cameras, and handheld communication devices use nonvolatile writeable memories to store either data, or code, or both. Such nonvolatile writeable memories include Electrically Erasable Programmable Read-Only Memories (EEPROMs) and flash Erasable and Electrically Programmable Read-Only Memories (flash EPROMs, or flash memories). Nonvolatility is advantageous for allowing the computing system to retain its data and code when power is removed from the computing system. Thus, if the system is turned off or if there is a power failure, there is no loss of code or data.
Nonvolatile semiconductor memory devices are fundamental building blocks in prior art computer system designs. The primary mechanism by which data is stored in nonvolatile memory is the memory cell. Typical prior memory technologies provide a maximum storage capacity of one bit, or two states, per cell. Semiconductor memory cells having more than two possible states are known in the prior art, however.
One type of prior nonvolatile semiconductor memory is the flash electrically-erasable programmable read-only memory (flash EEPROM). Prior art flash EEPROMs typically allow for the simultaneous reading of several flash cells. Further, typical prior flash EEPROMs have a storage capacity that is much greater than the amount of data that can be output at any one time. Accordingly, each output of a flash EEPROM is typically associated with an array of flash cells that is arranged into rows and columns, where each flash cell in an array is uniquely addressable. When a user provides an address, row and column decoding logic in the flash EEPROM selects the corresponding flash cell.
A typical prior flash memory cell is comprised of a single field effect transistor (FET) including a select gate, a floating gate, a source, and a drain. Information is stored in the flash cell by altering the amount of charge on the floating gate, which causes the threshold voltage (V.sub.t) of the flash cell to be varied. The typical prior art flash memory cell is in one of two possible states, being either "programmed" or "erased." FIG. 1 shows flash cell voltage distribution as a function of V.sub.t for a prior art flash device. As can be seen, the erased state and the programmed state each specify a distribution or range of V.sub.t voltages. The flash cell can theoretically possess a separate identifiable state for each electron that is added to the floating gate. Practically speaking, however, prior flash cells typically have only two possible states because of inconsistencies in flash cell structure, charge loss over time, thermal considerations and inaccuracies in sensing the charge on the floating gate that affect the ability to determine the data stored in the flash cell.
To distinguish between the two possible states, the states are separated by a separation range. According to one prior method, when a flash cell is read, the current conducted by the flash cell is compared to a current conducted by reference flash cell having a threshold voltage V.sub.t set to a predetermined reference voltage that is a voltage in the separation range. A single comparator, or sense amplifier, typically makes the comparison and outputs the result.
When a flash cell is selected for reading, a biasing voltage is applied to the select gate. Simultaneously, the same biasing voltage is applied to the select gate of the reference cell. If the flash cell is programmed, excess electrons are trapped on the floating gate, and the threshold voltage V.sub.t of flash cell has increased such that the selected flash cell conducts less drain current than the reference flash cell. The programmed state of the prior flash cell is typically indicated by a logic 0. If the prior flash cell is erased, little or no excess electrons are on the floating gate, and the flash cell conducts more drain-source current than the reference cell. The erased state of the prior flash cell is typically indicated by a logic 1.
When a flash cell has three or more possible states, the prior art sensing schemes and circuits similar to that described above typically have disadvantages. FIG. 2 shows one prior art sense amplifier 200. The prior art sense amplifier 200 is comprised of a bias circuit 202, a differential amplifier 204, and shorters 206. The differential amplifier 204 is a metal-oxide semiconductor (MOS) differential pair using a current mirror load. One disadvantage of this design is that it limits the input-high level to a value of approximately 4 volts with a Vcc of 5 volts thereby limiting the common mode rejection of the sense amplifier. While an input-high voltage of 4 volts may be adequate for a single bit per cell nonvolatile writeable memory, it is typically inadequate for multi-level-cell applications because of the limited common mode range. This differential pair typically also has poor noise rejection because of the unbalanced design in that Vcc does not couple identically to both input transistors.
Another disadvantage in the prior art sense amplifier 200 is the high bias current requirement of the differential pair of the amplifier 204, the bias current requirement typically being approximately 2.5 milliamps per sense amplifier. With a large number of sense amplifiers 200 required for a multi-level-cell application, the cumulative bias current can present power problems.
Yet another disadvantage of the prior art sense amplifier 200 is the use of shorters 206 to initialize the sense amplifier 200 in a state from which it can switch quickly between the output signal levels used by the circuit. When the shorters 206 are enabled they bias the input and output of the second stage of the differential amplifier 204 by shorting them together so that the input is biased at the trip point of the stage. This shorting is required to limit problems due to slew rate limitations of the amplifier. A disadvantage of the shorting is that the shorters 206, upon release or shorting, typically create noise spikes that feed back into the sensing circuitry. This noise can propagate through the sensing circuitry before the data gets latched and can sometimes introduce error into the latched data.

Sense amplifier comprising a preamplifier and a differential input latch for flash memories


A fluid coupling device and coupling system that may start and stop the flow of a fluid is disclosed. In some embodiments, first and second couplings are provided having an actuator coupled with each of the couplings. The couplings and actuators may be detachable to provide quick disconnect features and, in some embodiments, provide unitary actuation for the actuators of the coupling device to facilitate connection in mobile applications. Actuation may occur as the two couplings and actuators are engaged and disengaged and may occur by rotational actuation of the actuators. Rotational actuation can be provided to ensure flow through the coupling device, which in some embodiments may further provide an offset venturi feature. Upon disengagement, a compression element such as a compression spring can be provided to return the actuators to a closed position. Some embodiments further provide a seal external to the actuators and provided at incipient engagement of the couplings.

Prior quick disconnect designs can often incur high pressure drop and associated energy losses at rated fluid flow conditions creating flow resistance in the system. For what may be the dominant technology, the poppet style quick disconnect, this flow resistance may be attributed to the tortuous and restricted flow path around the outside of the retracting poppets. The problem may become particularly troublesome when cryogens are pumped over long distances or through a complex configuration of valves and disconnects. Some efforts to address the problems of flow resistance may require larger pumps and more energy consumption to compensate for flow losses, creating additional problems relative to such past attempts in disconnect technology.
Furthermore, prior quick disconnect designs can typically waste a significant amount of fluid to the environment each time mating and de-mating occurs, creating fluid spillage and other potentially negative results. The spillage volume can be a function of the interface geometry of the mating halves of the disconnect. Aside from wasting valuable fluid, the problem can also pose safety risks if the fluid is toxic or an explosive substance such as liquid hydrogen.
Prior quick disconnect designs may also typically require high component weight to achieve required flow rates, representing a high mass-to-flow ratio. This can be a function of the length, envelope and complexity of the disconnect. Of particular concern for flight fueling systems, is the weight of the flight side half of the quick disconnect, which is attached to the launch or other vehicle and must be lifted into space or elsewhere. These prior designs may further require unacceptable engagement forces necessary to ensure proper operation, leading to an unnecessarily burdensome engagement sequence.

High flow, low mobile weight quick disconnect system


An arrangement for improving the operation of an analog to digital converter (A/D), which can form part of an integrated circuit, the A/D converter being coupled to a reference voltage and having a plurality of input pins associated therewith comprises: a resistor divider having a plurality of resistors coupled in series, the resistor divider having an upper node coupled to a source of voltage to be converted, having a lower node coupled to a source of reference potential and having a plurality of intermediate nodes; and, each of the upper intermediate nodes being coupled to a respective one of the input pins of the A/D converter. The A/D converter can have enhanced resolution and/or an extended dynamic range when the voltage level being tested is divided arid the reference voltage is reduced. A corresponding method comprises the steps of: successively scaling down a voltage to be converted to a series of stepped down voltage levels; applying the successively stepped down voltage levels to respective ones of the input pins; and, sequentially scanning and acquiring a plurality of scaled A/D converter values from the input pins.

1. Field of the Invention
This invention relates to the field of analog to digital converters, and in particular, to an arrangement for extending the range of analog to digital (A/D) converters found in microprocessors and other integrated circuits.
2. Description of Related Art
Many microprocessor controller chips provide integral A/D converters to allow measurement of external circuit potentials. These integral A/D converters often have multiplexed inputs, so that readings from multiple sources can be acquired with a single software command. While economical, these on board A/D converters usually only provide 8 or 10 bits of resolution. If circuit demands either require higher resolution or an enhanced dynamic range, a much more costly external A/D converter must be provided.
External A/D converters can also have a similar structure, namely a plurality of input pins, which acquire their samples simultaneously, or if not simultaneously, within a very short time relative to the parameter being measured. For purposes of this application, the term simultaneously and the phrase within a very short time will be deemed to be encompassed by the phrase substantially simultaneously.

Analog to digital converters with extended dynamic range


A device comprising a first package and a second package coupled to the first package. The first package includes a first substrate, at least one gradient interconnect structure coupled to the first substrate, and a first integrated device coupled to the first substrate. The second package includes a second substrate and a second integrated device coupled to the second substrate. The second substrate is coupled to the at least one gradient interconnect structure.

FIG. 1 illustrates a package 100 that includes a substrate 102, an integrated device 105, and an integrated device 107. The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122 and a plurality of solder interconnects 124. A plurality of solder interconnects 154 is coupled to a first surface of the substrate 102 and the integrated device 105. A plurality of solder interconnects 174 is coupled to the first surface of the substrate 102 and the integrated device 107. The package 100 is coupled to a board 106 through the plurality of solder interconnects 124. There is an ongoing need to provide robust and reliable packages with small form factors.

Package comprising inter-substrate gradient interconnect structure


Methods of preventing creaming and age gelation in heat treated dairy based products are provided herein. Heat treated dairy based products are also provided, in which physical instability is prevented.

The shelf life of long life liquid dairy products, such as ultra-high temperature (UHT) milk, is limited by physical and chemical changes which make the consumer reject the product rather than microbial spoilage. Chemical changes include the Maillard reaction and oxidation, resulting in off flavour generation and colour changes. The most important physical changes are sedimentation or age gelation and creaming in fat containing products. Gelation and sedimentation change the perception and appearance of products resulting in gel clumps, increase or decrease in viscosity and an overall inhomogeneous product. Creaming leads to an unwanted fat layer or fat clumps in the product.
Age gelation has been used in a broad sense to describe physical instability in sterilized milk and other heat treated dairy products. Different causes for gelation and gel characteristics have been described in literature and can roughly be divided into proteolysis induced gelation, non-enzymatic gelation and a combination of both (Nieuwenhuijse, J. A., & van Boekel, M. A. J. S. (2003). Protein Stability in Sterilised Milk and Milk Products. In P. F. Fox & P. L. H. McSweeney (Eds.), Advanced Dairy Chemistry—1 Proteins (pp. 947-974): Springer US).
Protease induced age gelation has been mainly ascribed to heat resistant indigenous and microbial enzymes. The major indigenous protease plasmin can withstand certain UHT treatments and hydrolyses mainly β- and α-caseins. The released peptides and polypeptides can dissociate from the casein micelle and aggregate resulting in a fine stranded gel (Manji, B., & Kakuda, Y. (1988). The Role of Protein Denaturation, Extent of Proteolysis, and Storage Temperature on the Mechanism of Age Gelation in a Model System. Journal of Dairy Science, 71, 1455-1463). Limited proteolysis by plasmin can also lead to a destabilization of casein micelles resulting in a gelled sediment. Heat resistant microbial proteases often originate from psychrotrophic bacteria and vary greatly in specificity. For unspecific proteases, similar gels compared to plasmin can be formed, while some proteases mainly hydrolyse K-casein resulting in a rennet like gel.
Gelation in products without proteolysis is dependent on the dry matter content of the product and storage temperature. Gelation time decreases with increasing dry matter content. At high storage temperatures above 35° C., gelation is thought to be caused by sedimentation followed by crosslinking of casein micelles resulting in a gelled sediment. At lower temperatures, casein micelles can slowly dissociate and individual proteins as well as protein particles aggregate and form a gel (Nieuwenhuijse & van Boekel, 2003).
The rate of creaming is dependent on the particle size of the fat globules and the difference in density of these particles and the surrounding serum phase. Aggregation of fat globules greatly enhances the creaming rate.
There is an increased demand for life of long life dairy products, and thus methods for providing such products. US 2012/058240 discloses physical stability of heat treated skim milk with fruit extracts (blueberry, pomegranate and cranberry) for stability. CN 103 181 414 discloses heat treated raw milk with flavonoids obtained from sea buckthorn, which is then fermented to a yogurt with several positive characteristics after 30 day of storage without refrigeration.
CN 103 503 998 relates to a milk tea, obtainable by dissolving a tea powder and adding a milk powder and UHT sterilizing, wherein a combination of thickener and emulsifier is added to improve stability. O'Connell et al. (International Dairy Journal, 1998, 8, 8, 689-693) discloses increased colloidal stability of heat treated skim milk with a freeze dried green tea extract. However, the disclosure of D4 relates to heat stability at differing pH and not physical stability upon long term storage (age gelation) after UHT sterilization.
However, there is still a need for improved methods for providing long life dairy products with high physical stability.

Preventing physical instability of heat treated dairy based products


A handheld instrument that accomplishes non-contact infrared (IR) temperature measurement, and the measurement of movement of an object. The instrument has a case, and a movement-sensing device coupled to the case and operable to be directed toward or placed against an object being measured, for generating an output signal based on the sensed movement. An IR detector, also carried by the case, senses IR energy emitted from a surface being measured along an IR-sensing axis that extends from the case, and generates an IR output signal. The sensed IR energy is converted to a temperature value, and the output signal from the current-sensing device is converted to at least a measured current value. A display device in the case displays instrument measurements to the user.

Many machines require the non-contact measurement of temperatures, such as bearings or heated surfaces, which may not be readily available or unsafe to measure directly due to moving machinery. These machines may also require measurement of rotating or linear speed. Present practices require the use of two different instruments to perform these tasks. This adds to the expense, and is inconvenient for the user.

Instrument for non-contact infrared temperature measurement combined with tachometer functions


This disclosure relates to a circuit for detecting the phase transitions in a PSK signal in the presence of a stronger CW signal. A SAW transform circuit carries out "piecewise" Chirp-Z transformations of the PSK and CW signals so as to achieve a separation of the same in the time domain. A gate and a pulse width discriminator are both coupled to the output of the Chirp-Z transform circuit. The discriminator rejects all signals except the transformed phase transitions of the PSK signal. The output of the discriminator is utilized to periodically enable the gate for short durations (e.g., 2nsec.) to selectively pass the transformed PSK signal including transformed phase transitions thereof. The gated output is delivered to a dual channel SAW differential delay line whose two channels are of different lengths to provide a predetermined amount of delay (t) therebetween (t.ltoreq.PSK bit duration). A comparator serves to compare the output signals of said two channels and when they differ it produces an output pulse. A counter serves to count the output pulses from the comparator.

For certain applications (e.g., ELINT Radar) it is necessary to detect the phase transitions in a PSK signal and, more particularly, to detect (and count) the phase transitions or chips in a low level PSK signal in the presence of strong (or stronger) CW signals. Attempts have been made to use phaselock loops for this purpose. Phaselock loops, however, usually take milliseconds to lock onto an unknown carrier, while the PSK signals of interest generally last only for microseconds with chip durations of only nanoseconds. Also, phaselock loops do not operate satisfactorily in the presence of multiple, interfering, signals.

Transition detection circuit for PSK signals using the SAW Chirp-Z algorithm (U)

The United States of America as represented by the Secretary of the Army


A lamina emergent torsional (LET) joint that includes an integrated membrane to reduce, or eliminate, certain unwanted motions and/or displacements associated with the operation of the LET joint is disclosed. The membrane-integrated LET joint (i.e., M-LET) can be used as a hinge for a lamina emergent mechanism and/or as a surrogate fold for an origami application to ensure accurate and repeatable transitions from a planar (i.e., lamina) state to a non-planar (i.e., lamina-emergent) state, and vice versa.

Compliant mechanisms are deformable, single-piece structures that are configured to transfer an applied force and/or deplacement via the elasticity of the structure. Lamina emergent mechanisms (LEMs) are subset of compliant mechanisms. LEMs are typically fabricated from a planar material (i.e., lamina). An LEM can be configured (e.g., via an applied force) into a shape that is non-planar via a motion that emerges from the plane of fabrication (i.e., fabrication plane). This motion can be facilitated by one or more LET joints.
LET joints can also be used for surrogate folds. Surrogate folds behave like preformed folds in a lamina that specify a preferred fold location, and in some cases, define a preferred (or required) folding direction. Surrogate folds can be useful in origami-based applications, which require folding in preferred locations and/or directions to operate properly.
Operation of a LEM and/or a surrogate fold may depend largely on the function of the LET joint. LET joints having relatively unrestrained rotation (i.e., low torsional stiffness) about a joint axis (i.e., folding axis, hinge axis, etc.) and a relatively restrained motion (i.e., high stiffness) in other directions are desirable for applications requiring precision and repeatability. A need, therefore, exists for new LET joints that provide low torsional stiffness about a joint axis while maintaining high stiffness in the other directions.

Membrane integrated lamina emergent torsion joint


A sacroiliac (“SI”) joint fastener apparatus, systems, and methods of using the device is described. The SI joint fastener apparatus can include a distal segment, a proximal segment, and an expandable portion. The expandable portion can be expanded by reducing the distance between the distal and proximal segments. The SI joint fastener apparatus can be used to fuse two bone portions together. The method can include steps of coupling the fastener apparatus to two bone portions, reducing the distance between the two bone portions to place the portions in compression, and applying an outwardly directed force proximate the location to be fused.

The sacroiliac ("SI") joint is a joint located in the pelvis formed by the juncture between the sacrum and the ilium. The SI joint can be a significant contributing factor in many patients having lower back pain. In some studies, dysfunctions of the SI joint, such as degenerative sacroiliitis and sacroiliac disruption, was believed to account for as many as 15% to 22% of patients having chronic lower back pain. In order to relieve pain caused by SI joint dysfunctions, there is a need to develop devices, systems and methods of stabilizing and fusing the SI joint.

Sacroiliac joint fastener, systems, and methods of using the same


A phase locked loop in a LSI comprises a phase comparator, a low-pass filter, a voltage controlled oscillator and a frequency divider, and receives an input clock signal to output an internal clock signal obtained by multiplication of the input clock signal. The output of the low-pass filter is supplied through a voltage follower from an external pin toward outside the integrated circuit. The output voltage of the low-pass filter is evaluated during a test mode for evaluating the function of the phase locked loop without affecting the characteristics of the phase locked loop.

(a) Field of the Invention
The present invention relates to a semiconductor integrated circuit having a phase locked loop and, more particularly, to a circuit structure for testing the phase locked loop.
(b) Description of the Related Art
A semiconductor integrated circuit, such as a logic LSI, generates an internal clock signal having a higher frequency than an input clock signal to operate the internal circuit thereof, such as a microprocessor or digital signal processor. For this purpose, a phase locked loop is generally used which multiplies the frequency of the input clock signal to provide the higher frequency clock signal which is in synchrony with the input clock signal. Some phase locked loops operate in an analog format, and it is generally important to test the phase locked loop by using a logic tester or analog tester to evaluate the characteristics of the phase locked loop.
FIG. 1 shows a conventional analog phase locked loop 13 incorporated in a logic LSI 11, which is under an evaluation test by a logic tester 29. The logic LSI 11 comprises an internal circuit 12 and a phase locked loop 13 for supplying an internal clock signal 104 to the internal circuit 12. The phase locked loop 13 comprises a phase comparator 15 for comparing an internal signal 105 against an input clock signal, a low-pass filter 16 receiving an analog output from the phase comparator 15, a voltage controlled oscillator (VCO) 17 controlled by an output 102 from the low-pass filter 16 to supply an internal clock signal 104 to the internal circuit 12, and a frequency divider 18 for dividing the frequency of an output 104 from the VCO 17 to provide the internal signal 105 to the comparator 15.
In a normal operation mode of the logic LSI 11, an input clock signal is supplied to the phase comparator 15, which outputs a phase difference signal representing the phase difference between the input clock signal and the internal signal 105 through the low-pass filter 16 to the VCO 17. The VCO 17 is controlled by the output 102 of the low-pass filter 16 to supply the internal clock signal 104 having a multiplied frequency which is a product of frequency of the input clock signal by a multiplication factor equal to the dividing ratio by the frequency divider 18.
In the evaluation test mode of the logic LSI 11, a driver 31 in the logic tester 29 supplies a test clock signal 101 to the phase comparator 15 of the phase locked loop 13. The output clock signal 104 of the VCO 17 is supplied to a comparator 30 of the logic tester 29, which evaluates the output clock signal 104 by judging whether or not the level of the output clock signal 104 resides within an expected range at a specified timing.
FIG. 2 shows a timing chart for the test mode of the logic LSI 11, wherein three examples for the test output signal 104, which are obtained by multiplication of the frequency of the test clock signal 101 by two, are shown together with the test clock signal 101. The timing chart also shows the specified timing of the evaluation for each of the examples by an arrow, as well as the results of the judgement in the examples, namely, "pass" or "fail". The first example shows a "pass" wherein the level of each clock pulse is judged to be correct at each specified timing, and the second example shows a "fail" wherein some clock pulses are judged to be incorrect because of the incorrect frequency of the output clock signal 104, which may cause a malfunction of the internal circuit 12.
The third example shows a "fail" determined by the logic tester 29 wherein the level of each clock pulse is judged to be incorrect, although the output clock frequency itself is correct and, therefore, there is no possible malfunction in the internal circuit 12 caused by the judged incorrect level of each clock pulse.
The logic LSI 11 of FIG. 1 can be tested also by an analog test circuit including an oscillator and a voltmeter such as shown in FIG. 3, as described in Utility Model Kokai Publication 2-32078. The oscillator 20 supplies a test clock signal 101 to the phase comparator 15, as in the case of the logic tester of FIG. 1, and the voltmeter 19 determines the voltage level of the output 102 of the low-pass filter 16 controlling the output frequency from the VCO 17.
FIG. 4 is a typical graph for showing the output frequency of the VCO against the output voltage of the low-pas filter, i.e., input control voltage of the VCO. The output frequency monotonically increases from a minimum frequency f.sub.min to a maximum frequency f.sub.max with the increase of the input control voltage of the VCO. Especially in the range between VB and VA, the VCO operates in a stable and normal state so that the output frequency is determined by the input control voltage. In the graph, assuming that the design frequency of the VCO 17 is f.sub.x and the dividing factor by the divider 18 is 1/2 in the example of FIG. 3, a frequency of f.sub.x /2 is supplied as the input test clock signal 101 from the oscillator 20. In this case, if the input control voltage (VX) resides between VB and VA, as shown in FIG. 5, the phase locked loop 13 operates in a stable and normal state. On the other hand, if the input control voltage (VX') does not reside between VB and VA, as shown in FIG. 5, the phase locked loop 13 does not operate in a stable and normal state. Namely, by measuring the input control voltage of the VCO 17, the phase locked loop 13 can be evaluated in its operation.
In the evaluation by the analog tester of FIG. 3, it is to be noted that if the voltmeter 19 has an input impedance comparable with or lower than the output impedance of the low-pass filter 16 or the input impedance of the internal circuit 12, the measurement by the voltmeter 19 is not satisfactory in its reliability. Accordingly, voltmeter 19 must have a sufficiently high input impedance to obtain a reliable result for the evaluation test.

Semiconductor integrated circuit having a phase locked loop


An electrical connector includes a housing (2). A floor (20) is defined in a middle of the housing and a plurality of side walls (22) is defined therearound. The side walls and the floor cooperatively define a substantially rectangular cavity (24) therebetween. A plurality of passageways (26) is defined in the floor for receiving a corresponding number of electrical contacts (3) therein. Each contact includes an arm (30) extending beyond the floor for contacting with corresponding contacting pad of the LGP (4). All the arms extend in a plurality of rows, parallel to one diagonal of the floor, and the arms in a same row are arranged side by side. Each passage includes an upper receiving portion extending into an adjacent passage in the same line, therefore, the passages in the same line are stringed, and a continuous support member is formed between two rows of stringed passages.

1. Field of the Invention
The present invention relates to an electrical connector for electrically connecting an electronic package such as an integrated circuit (IC) chip with a circuit substrate such as a printed circuit board (PCB), and particularly to a connector adapted for receiving a land grid package (LGP) therein and electrically connecting the LGP with a PCB.
2. Description of the Prior Art
Land grid array (LGA) connector for connecting a Land Grid Package (LGP) with a printed circuit board (PCB) is widely used in the field of electrical connectors.
Conventional Land Grid Array (LGA) connector comprises an insulative base mounted on a printed circuit board, a metal clip pivotably engaged on one end of the base, and a lever engaged on an opposite end of the base for fastening the clip onto the base. The base is substantially rectangular. A floor is defined in a middle of the base and a plurality of side walls is defined around the floor. The side walls and the floor cooperatively define a substantially rectangular cavity therebetween. A plurality of passageways is defined in the floor, for receiving a corresponding number of electrical contacts therein. Each contact comprises an arm extending beyond the floor of the housing for electrically contacting with corresponding contacting pad of an LGP. Examples of this kind of electrical connectors are also disclosed in U.S. Pat. Nos. 4,504,105, 4,621,884, and 5,302,853.
In use, the LGP is inserted into the cavity and the pads mates with the extending out arms of the contacts. After the insertion, the arms are pressed by the contacting pads of the LGP, and resiliently deform towards the floor of the housing. However, the arms of the contacts are liable accidentally damaged under long time pressure of the LGP, for no supporting member.
Referring to FIG. 6, an improved LGA connector is provided for preventing the arms 60 from being damaged. In this type of LGA connector, a plurality of protrusions 61 is defined among the exposed arms, and each protrusion 61 is separated from each other. The arms 60 of the adjacent contacts extend substantially parallel to a direction of one diagonal of the rectangular floor 63, and any two adjacent arms do not extend in a same line. In use, the protrusions 61 and the contacting portions of the contacts cooperatively support the LGP. Therefore, risk of damaging the contacts is decreased.
However, one problem with this type of LGA connector is that the separated protrusions will be probably pressed damaged by the LGP, for the limited strength of separate protrusion and the relatively high pressure from LGP.
In view of the above, a new electrical connector which overcomes the above-mentioned disadvantages is desired.

Electrical connector with continuous support member


A methanol/water scrubbing solution containing colloidal metal sulfides formed from metal carbonyls and resulting from the scrubbing of industrial gases, such as synthesis gas, is subjected to agglomeration of the metal sulfides before the scrubbing solution to be separated enters the separating column which separates the methanol from the water containing precipitated metal sulfides. The agglomeration is carried out in a precipitation vessel and the scrubbing liquid is diluted before it enters the precipitation vessel. The result is minimal encrustation of the trays or other parts of the cleaning plant for the scrubbing solution.

In the production of industrial gas, for example, synthesis gas, metal carbonyls tend to form from fuels containing heavy metal. These metal carbonyls can be detrimental in many chemical syntheses which can use such synthesis gas. Synthesis gas is comprised basically of hydrogen, hydrocarbons, carbon dioxide and carbon monoxide and may also include a number of byproducts which stem from the raw material used in the production of synthesis gas, including especially H2S, HCN, COS, and HSCN, in addition to the metal carbonyls which have already been mentioned.
From the metal carbonyls, colloidal metal sulfides may be formed in the presence of H2S and these metal sulfides can encrust or bake onto surfaces of process equipment, including the trays of separating columns and surfaces of fluid passages so that in a short time, those passages can be blocked or the equipment rendered inoperative in whole or in part.
It is thus of advantage to clean the synthesis gas and in the course of cleaning the synthesis gas, to remove colloidal metal sulfides which may have or may be formed from metal cabonyls.
To clean the synthesis gas, a number of techniques have been developed. The one of greatest significance is the Rectisol method. In the Rectisol plant, the crude gas is initially subjected to a HCN removal using a small portion of a regenerated scrubbing liquid, here methanol, in a prescrubbing step. Then the crude gas is scrubbed with the main quantity of the regenerated methanol to absorb H2S therefrom. Both the prescrubbing methanol and the main scrubbing methanol is charged with substances absorbed from the gas and contain the metal carbonyl.
The method of cleaning industrial gas, especially synthesis gas, by one or more low temperature gas scrubbing stages, utilizes methanol at a temperature of −60° C. to 0° C. and then subjects the methanol to expansion, evacuation, thermal treatment for outgasing and then a further heating step with any additional treatment in a reactor prior to recycling. Such a system has been described, for example, in German patent 26 10 892. With this process, the formation of deposits of heavy metal compounds, especially metal sulfides formed from the metal carbonyls, is prevented in the outgasing column of gas scrubbers and the operating life of such equipment is increased. Nevertheless even with the use of this process, some metal carbonyls which have been unconverted in the prereactor, carbonyls which are dissolved in prescrubbing methanol and metal carbonyls which survive elsewhere in the system can remain in the synthesis gas which may be utilized in reactions in which these metal carbonyls may be detrimental.
A further method for the removal of metal carbonyl compounds in conjunction with cleaning of synthesis gas by low temperature gas scrubbing is known from German open application 43 36 790. In this process, before being admitted to a regenerating column, a highly loaded and a poorly loaded scrubbing liquid stream are heated and each is fed to a reactor. The highly loaded stream of the scrubbing liquid, together with the condensate which is produced by the partial condensation of the vapor from the condensation system of the regenerating column is fed to a reactor providing a sufficient residence time. This method also does not ensure a complete conversion of the metal carbonyl as well as the removal of the sulfides.
The removal of metal sulfides and especially the colloidal metal sulfides resulting from metal carbonyls, above all iron pentacarbonyl and nickel tetracarbonyl, is a significant problem in the recycle gas scrubbing problem to reduce the formation of deposits in the separating column and other parts of the apparatus. For the most endangered parts of the apparatus, cleaning must be carried out at intervals and for such cleaning intervals, there is a standstill of the plant. This approach to dealing with encrustation resulting from colloidal metal sulfides on the trays of the methanol-water separation column (MWC) has not been satisfactory up to now.


Variable gain amplifiers with wider linear range are provided, in which first and second loads are coupled to a power voltage, and a transconductor cell comprises first and second transistors, a gain control transistor, and first and second current sources. The first and second transistors comprise control terminals receiving a set of input signals, first terminals coupled to the first and second loads respectively, and second terminal coupled to first and second nodes respectively. The first and second current sources are coupled between the first node and a first voltage and between the second node and the first voltage respectively. The first gain control transistor is coupled between the first node and second node, receiving a gain control voltage, in which the grain control transistor has a threshold voltage lower than that of the first and second transistors.

1. Field of the Invention
The invention relates to variable gain amplifiers and in particular to variable gain amplifiers with a wider linear range.
2. Description of the Related Art
In communications systems, analog receivers vary the amount of gain according to the specific receiver operation and the strength of the received signal, to maintain a constant signal level. Variable gain amplifiers are typically used to achieve this desired effect in the receiver. Because of the wide range of received signal strength, the variable gain amplifier must be able to vary its gain over a wide range.


An inventive arbiter controls access to a resource in a high speed computer or telecommunications network. The arbiter is capable of performing round-robin scheduling for N requests with P possible priority levels with a sublinear time complexity. The high arbitration speed is achieved through use of a tree structure with a token distribution system for implementing the round-robin scheduling policy.

Resource arbitration is a fundamental problem in computer and telecommunications network design. An arbiter controls the access of a plurality of competing inputs to a desired resource such as a bus or multiplexer in a computer or telecommunications network.
In particular, high speed arbitration among inputs with variable priorities is needed to support variable priority communications in a dynamic multi-tasking environment and to accommodate the increasing speed of highly pipelined data parallel buses and high speed statistical multiplexers. Preferably, the arbiter carries out a round-robin scheduling process to insure that all inputs of equal priority achieve fair access to the resource being arbitrated.
A variety of arbiters have been disclosed in the prior art. However, as is discussed below, only a few of the prior art arbiters support variable priority arbitration. One prior art arbiter is disclosed in Bogdan Lent, "A Variable Arbiter for Resource Allocation in Asynchronous Multiprocessor Systems," Microprocessing and Microprogramming, Vol. 9, 1982. This arbiter is based on a priority comparison matrix and can support variable priority arbitration or a first-come, first-served scheduling policy. However, this arbiter does not support round-robin scheduling on variable priority classes and, in addition, it has a space complexity of order N.sup.2, where N is the number of inputs. Thus, this arbiter increases in size too rapidly with large N.
An arbiter with a round-robin scheduling policy and with a policy for handling urgent requests is disclosed in Mary K. Vernon et al, "Distributed Round-Robin and First-come, First-serve Protocols and Their Application to Multiprocessor Bus Arbitration," The ACM 15th Annual International Symposium on Computer Architecture, 1988 and in D. M. Taub, "Arbitration and Control Acquisition Scheme for the IEEE 896 Futurebus," IEEE Micro, Vol. 4, No. 4, August 1984, pp. 28-41. However, these arbiters do not support round-robin arbitration for multiple priority classes.
To match the speed of highly pipelined buses and multiplexers, an arbiter with a round-robin scheduling policy and with a sublinear time complexity is desired. The linear array based round-robin arbiters proposed in Joseph K. Muppala et al, "Arbiter Designs for Multiprocessor Interconnection Networks," Microprocessing and Microprogramming, Vol. 26, 1989 and in G. Cioffi et al, "A Fully Distributed Arbiter for Multi-processor Systems," Microprocessor and Microprogramming, Vol. 11, pp. 15-22, 1983, have O(N) time complexity. Since the arbitration time of these arbiters increases linearly with the number of input ports, they cannot match the data transfer rate in a highly pipelined communications system where N is large.
In the case of highly parallel and pipelined bus systems, arbitration needs to be performed in each system clock cycle. Arbitration schemes that utilize a table lookup method to implement rotating priority arbitration (see. e.g., A. B. Kovaleski, "High-Speed Bus Arbiter for Multiprocessor," IEE Proc. Vol. 130, Pr, E, No. 2, March 1983 and the Vernon et al reference identified above) can reach higher speeds but their space complexity will increase exponentially with the number of inputs and the number of priority classes.
Distributed arbiters (see, e.g., the Taub, Cioffi et al, and Vernon et al references identified above) have the advantage of modularity. However, their arbitration time is relatively long compared to that of a centralized arbiter. In order to support P priority levels and N input nodes, the arbitration process needs to step through log.sup.P priority bus lines and log.sup.N node identification bus lines to reach a distributed arbitration decision. Although the distributed arbitration scheme only requires on the order of (log.sup.P +log.sup.N) time steps, each step requires a long delay due to off-chip communications, bus propagation, wire or glitch elimination, and capacitive loads of bus drivers.
Briefly stated, none of the above-identified prior art arbiters is entirely satisfactory for use in high speed computer and telecommunications networks because they are incapable of handling multiple priority classes, because they do not utilize a round-robin scheduling policy, because the time or space complexity is too great, or because centralized arbitration is not utilized.
In view of the foregoing, it is an object of the present invention to provide an arbiter and associated arbitration process which overcomes the shortcomings of the above-described prior art arbiters. It is a further object of the invention to provide an arbiter and associated arbitration process suitable for use in high speed computer and communications systems.
More particularly, it is an object of the invention to provide an arbiter and associated arbitration process whose arbitration speed increases sublinearly as the number N of inputs increases. It is also an object of the invention to provide an arbiter and associated arbitration process which implements a round-robin scheduling policy, which is capable of handling multiple priority classes and which is centralized.

Tree structured variable priority arbitration implementing a round-robin scheduling policy


In one embodiment, a method comprises receiving, by an apparatus, a Media Access Control (MAC) frame destined for a destination device; dividing, by the apparatus, the MAC frame into frame fragments; coding the frame fragments into encoded cells; and causing, by the apparatus, transmission of selected subsets of the encoded cells, as distinct flows of the encoded cells, by respective optical physical layer transmitter devices reachable by the destination device.

This section describes approaches that could be employed, but are not necessarily approaches that have been previously conceived or employed. Hence, unless explicitly specified otherwise, any approaches described in this section are not prior art to the claims in this application, and any approaches described in this section are not admitted to be prior art by inclusion in this section.
Optical networks have been proposed for propagation of data packets via optical beams output by optical transmitters such as lasers or light bulbs employing Light Emitting Diodes (LEDs).
Network coding is a technique of in-network re-coding of source packets for distribution among network elements. Network coding can provide more robust reception of data packets in lossy networks where not all of transmitted data packets are received by a receiving network element.

Distributed media access controller transmitting network coded cells via optical transmitters


Provided is a nitride semiconductor light emitting element capable of producing an emission spectrum having two peaks with stable ratio of emission peak intensity. The nitride semiconductor light emitting 1 comprises an active layer 12 disposed between an n-type nitride semiconductor layer 11 and a p-type nitride semiconductor layer 13. The active layer 12 comprises a first well layer 14, second well layers 15 interposing the first well layer 14 and disposed at outermost sides among the well layers, and barrier layers 16, 17 disposed between each of the well layers. The second well layer 15 comprises a nitride semiconductor having a larger band gap energy than the band gap energy of a nitride semiconductor constituting the first well layer 14, and the nitride semiconductor light emitting element 1 has peaks in the emission spectrum respectively corresponding to the first well layer 14 and the second well layer 15.

1. Field of the Invention
The present invention relates to a nitride semiconductor light emitting element, in particular, a nitride semiconductor light emitting element having a plurality of peaks in its emission spectrum.
2. Discussion of the Related Art
In recent years, semiconductor light emitting elements capable of emitting light in the ultraviolet region have been put into practical use, which are also used in an exposure apparatus, a disinfection apparatus, and the like. However, in the cases where a semiconductor light emitting element is used in a ultraviolet irradiating apparatus for curing a material, with a larger thickness of the irradiated material, insufficient curing of a deeper portions may result. The reasons include that the ultraviolet irradiation cannot penetrate into a deeper portion of the irradiated material. In order to allow light to penetrate deeper into the irradiated material from the surface to a deeper portion, it is efficient that the ultraviolet irradiating apparatus has a plurality of emission peak wavelengths. To obtain such an apparatus, a plurality of semiconductor light emitting elements having different peak wavelengths or a semiconductor light emitting element having a plurality of active layers having different compositions may be employed (see Japanese Laid-Open Patent Publication No. 2007-305703).
A semiconductor light emitting element having a plurality of well layers with varying compositions may be intended to provide white light with a single semiconductor light emitting element. Specific examples thereof include a structure having well layers of different emission wavelengths stacked in order of wavelength, and a structure having a repetitive stack of such structures (see Japanese Laid-Open Patent Publications Nos. H10-22525, 2001-28458, and 2004-128443).
Other examples of varying compositions in the active layer include a quantum well structure having a strain compensating layer with a larger band gap energy than that of a barrier layer interposed between the barrier layer and a well layer (see Japanese Laid-Open Patent Publication No. 2004-87763).
However, in the semiconductor light emitting element in which well layers of different emission wavelengths are simply stacked in order of wavelength, it is difficult to produce an efficient and stable ratio of emission peak intensity. For example, in a case where a well layer of longer wavelength emission having a smaller band gap energy is disposed closer to the n-type semiconductor layer side than a well layer of shorter wavelength emission having a larger band gap energy, the luminous efficiency in longer wavelength decreases, so that stable ratio of emission peak intensity is difficult to obtain. Such a nitride semiconductor light emitting element having unstable ratio of emission peak intensity is unsuitable as the light source for curing a resin or an ink.
On the other hand, if a well layer of longer wavelength emission is disposed closer to the p-type nitride semiconductor layer side than a well layer of shorter wavelength emission, emission from the well layer of longer wavelength emission is extremely facilitated, and in some cases, emission from the well layer of shorter wavelength emission may not occur.

Nitride semiconductor light emitting element


In a control circuit for at least one actuator, in particular for a capacitive actuator of an injection system of an internal combustion engine, a control current can be applied to the actuator.

Typical control circuits of the above-mentioned type are used, for example, for activating piezoelectric elements which act on a valve needle of a fuel injector, for example, in order to cause fuel injection into a combustion chamber of the internal combustion engine.
In order to achieve a stroke of the piezoelectric element which is sufficient for activating the valve needle, in conventional systems a control voltage of 160 V or more must be applied, which is typically clocked, in order to achieve controlled opening of the fuel injector and avoid damage to the ceramic of the piezoelectric element. In addition, an inductor is frequently provided in control circuits of this type, which limits the current in the piezoelectric element.
Because of the clocking of the control voltage, a triangular current curve is produced, and during the changes of the control current over time, voltage jumps also occur in supply line inductances of the piezoelectric elements, for example. The high-frequency voltage components accompanying the voltage jumps cause capacitive interference currents in particular, which flow via a housing of the fuel injector into the engine block, for example, and from there via a vehicle body connection back into the control unit, for example.
In this instance, the very low-resistance connection between the engine block, the vehicle body, and the control unit is particularly disadvantageous, due to which, together with the parasitic capacitances and possibly parasitic inductances making the interference currents possible, a high-quality resonance circuit is formed. The resonance frequency of the resonance circuit is determined by the magnitude of the parasitic capacitances and of the inductance of the return line via the engine block and the vehicle body connection. Typical capacitance values for the parasitic capacitances between the connecting lines of the piezoelectric elements and a housing of the fuel injector are, for example, approximately 500 pF to 1 nF, these values being able to vary depending on the arrangement of the piezoelectric elements or the fuel injectors.
The electromagnetic oscillations arising in the resonance circuit result in significant interference, for example, in radio receiver systems of a motor vehicle containing the control circuit or also in further electronic systems. Permissible limiting values for electromagnetic emissions of this type in the engine compartment are often exceeded.

Abstract: The control circuit has an inductor, e.g., having a core and having multiple windings, the windings being designed and connected to the control circuit such that a control current flowing into the actuator and a control current flowing out of the actuator each flow through different windings of the inductor, and a magnetic flux induced in the inductor or its core by the control current flowing into the actuator and a magnetic flux induced in the inductor or its core by the control current flowing out of the actuator mutually compensate one another.


The rotating electric machine is configured in such a way that a surface of the heat sink, on which the cooling fins of the heat sink are formed, faces the housing; and a plate, which blocks the surface of the housing facing the heat sink and forms a wind passage between the heat sink and the plate, intervenes between the cooling fins and the surface of the housing facing the heat sink; and outside air is aspirated from an inlet formed on the protective cover, and then, the outside air is passed through the wind passage formed between the heat sink and the plate so as to be passed through a window formed on the housing, and is exhausted, by the cooling fan of the rotor, from an outlet formed on the housing.

1. Field of the Invention
The present invention relates to a rotating electric machine used for a vehicle or the like, which is linked to an engine, and particularly relates to a cooling mechanism for radiating heat generated from the rotating electric machine.
2. Description of the Related Art
In a conventional rotating electric machine used for a vehicle, it has been suggested that a power assembly having switching elements, which supply electric current to a rotor having armature coils, and a control assembly having a control circuit, which controls the power assembly, are mounted on the rotating electric machines (for example, refer to Patent Document 1 and Patent Document 2).
In the rotating electric machine described in Patent Document 1, power modules composed of power semiconductor devices, insulating substrates, and heat sinks are mounted on a bracket (housing), and fins are formed on the heat sink. A fan is mounted on a rotor, and cooling wind is generated by rotating the rotor. The rotating electric machine is configured in such a way that a window for passing wind is formed on the bracket, and the cooling wind passed through the fins is exhausted from an aperture of the bracket via the window of the bracket.
Patent Document    [Patent Document 1]    Japanese Laid-Open Patent Publication No. 2004-312852 (Embodiment 2, FIG. 3 and FIG. 5)    [Patent Document 2]    Japanese Laid-Open Patent Publication No. 2010-268541 (Embodiment 3, FIG. 7)
In the rotating electric machine described in Patent Document 1, power modules are mounted overall an end surface of the bracket, and in order to effectively use the fins formed on the heat sink, it is required that the window of the bracket is formed near a rotary shaft provided at a center of the rotating electric machine. However, the bracket must hold the rotor and the stator, and a metal material is usually used for the bracket because of a structural factor. Therefore, because components without the window are covered, there is a problem in that a weight of the rotating electric machine is increased. Moreover, the bracket holds the stator as described above, so that a temperature of the bracket becomes high by a heat transfer from the stator. Therefore, when a wind passage is configured by using the bracket and the heat sink, a cooling efficiency of the heat sink, on which power modules are mounted, is deteriorated by radiant heat transmitted from the bracket to the cooling wind or radiant heat transmitted from the bracket to the heat sink.
On the other hand, in the rotating electric machine described in Patent Document 2, it is suggested that a power circuit having switching elements is mounted on a surface of the heat sink, and fins are provided on the other surface, and a stator coil and a relay plate for connecting a stator coil and the power circuit are provided at an opposite side of the fins of the heat sink, and moreover, a wind passage is configured by using the heat sink and the relay plate.
In the rotating electric machine described in Patent Document 2, the heat sink, on which a power circuit is mounted, is mounted in the inside of the housing, so that there has been a problem in that an inlet for cooling wind is positioned near an outlet, and the exhausted air is circulated, whereby temperature of the aspirated air is increased. Moreover, it is required that a bus bar for connecting a stator coil to the power circuit is provided on the relay plate. Because the whole parts of the bus bar, without a connecting portion, must be insulated, a thickness of the relay plate is increased. When the thickness of the relay plate is increased, a size in an axis direction of the rotating electric machine is increased. Moreover, in order to prevent the size in an axis direction of the rotating electric machine from changing, it is required that the fins of the heat sink become short so as reduce the thickness of the relay plate. In a former case, the size of the rotating electric machine is increased, whereby the weight of the rotating electric machine is increased. In a later case, the fins become short, whereby a cooling capacity of the heat sink is deteriorated.


An image recording/reproducing apparatus which supports recording by memorizing recording requests of a user, and a method thereof. A recording status display table stores a general recording information display part for recording such as a program recording date and a recording start time and a recording result display part for displaying a recording result. A control unit controls the recording status display table to be displayed on a display apparatus. The recording result is recorded and stored in the recording result display part of the corresponding program of the memory, and displayed if requested. As a result, the user may easily confirm the recording status without checking the recorded contents.

1. Field of the Invention
The present invention relates to an image recording apparatus and a method thereof. More particularly, the present invention is directed to a recording apparatus which supports recording by memorizing recording patterns of the user, and a method thereof.
2. Description of the Related Art
An image recording and reproducing apparatus for recording a broadcasting signal on a recording medium or reproducing the recorded broadcasting signal expands its functions according to digitalization of the broadcasting signal and development of the compression technology. The image recording and reproducing apparatus has been improved to support utilization of various image sources such as a satellite broadcast, a cable broadcast and a network broadcast based on an Internet. Furthermore, the image recording and reproducing apparatus can store data on an optical medium such as a CD-ROM (compact disc read only memory) title or a DVD (digital versatile disc) title or reproduce the stored data according to digitalization of the data and development of the compression technology. For example, the optical medium for storing image data and audio data for the DVD title generally stores a few hundred Megabytes to a few Gigabytes of data, and thus easily stores or reads a large volume of data by using an HDD (hard disk driver) which is a large capacity memory. The representative example of the image recording and reproducing apparatuses is a DVD/HDD image recording and reproducing apparatus. A DVD ROM for reproducing data recorded on a disk and an HDD for recording and reproducing data are combined in one casing. The DVD ROM and the HDD perform individual functions and share an interface for mutual data transmission and reception. In general, the DVD ROM reproduces data recorded on an optical disk recording medium such as a DVD, an audio CD, a video CD and an MP3 CD.
The DVD/HDD image recording and reproducing apparatus receives an external broadcasting signal, records data on the HDD or externally outputs the data, and records data reproduced by the DVD ROM on the HDD. When recording the signal reproduced by the DVD ROM or the external signal on the HDD, a plurality of programs are recordable on the large capacity HDD.
The DVD/HDD image recording and reproducing apparatus will now be explained with reference to FIGS. 1 and 2.
FIG. 1 is a schematic block diagram illustrating a conventional DVD/HDD combo system having a DVD player and an HDD.
The DVD reproducing apparatus includes a switching unit 10, an MPEG encoder unit 20, an HDD 30, a flash ROM 40, a control unit 50, a RAM (random access memory) 60, a light receiving unit 70, a digital signal processing unit 80 and a DVD reproducing and recording apparatus 90.
The switching unit 10 receives image data and/or voice data from sources, or outputs image data from the decoder unit 80 to display apparatus 85, for example. The switching unit 10 receives an external signal such as a component signal or a composite signal from a video source (not shown), and selectively connects the signal to functional blocks of the image recording and reproducing apparatus. For example, where the external signal is the component or composite signal, the switching unit 10 applies the signal to the MPEG encoder unit 20.
The MPEG encoder unit 20 includes a video decoder 21, an audio ADC (analog-to-digital converter) 22 and an MPEG encoder 23, AD-converts an analog image data source from the switching unit 10, and compresses the converted image data in the form of an MPEG format (for example, MPEG-2 format). Generally, when stored in a storage medium such as the HDD 30, the MPEG format image data are compressed to reduce a storage space.
The HDD 30 stores and reads the MPEG format image data and sound data in a data recording area in a form of a file.
The flash ROM 40 stores an operating system and an application program for operating the DVD reproducing recording apparatus 90 which will be explained below, and includes an application program for displaying the image data and audio data stored in the HDD 30 in the form of a file and supplementary information (such as icon, title name, recording time, and file size) on the screen through a GUI (graphic user interface) type menu, and for editing and displaying the image data and audio data through the displayed menu.
The control unit 50 stores the MPEG data from the MPEG encoder unit 20 in the HDD 30, or applies the image data and voice data stored in the HDD 30 to the digital signal processing unit 80. In order to reproduce and/or record the DVD, the control unit 50 reads information on the DVD title from the disk information file area, and records the information on a route directory area of the HDD 30. In addition, the control unit 50 reads and displays the related GUI screen from the flash ROM 40 to display on the screen the icon and title name corresponding to the image data stored in the HDD 30 in the form of a file, by executing the application program stored in the flash ROM 40.
The RAM 60 loads the file stored in the HDD 30 when the control unit 50 edits the file. That is, the file is not directly edited in the HDD 30, but edited in the RAM 60 and re-stored in the HDD 30.
The light receiving unit 70 receives a control signal (not shown) from a remote controller (not shown) for controlling the image recording and reproducing apparatus (for example, channel change, volume control, and image quality control) or a setup key of the image recording and reproducing apparatus, and applies the control signal to the control unit 50.
The digital signal processing unit 80 receives the MPEG format image data stored in the HDD 30 through the control unit 50, decodes the image data, and converts the decoded data to a video format (for example, NTSC/PAL). The converted signal can be reproduced by an image display apparatus such as a TV.
The DVD reproducing and recording apparatus 90 reads the image data and audio data from a DVD disk and applies the data to the control unit 50, or receives the signal from the control unit 50 and records the image and audio data on the DVD disk. Accordingly, the image data and audio data applied to the control unit 50 are stored in the HDD 30, or applied to and reproduced by the digital signal processing unit 80.
When the user intends to perform reservation recording by using the above apparatus, the control unit 50 displays the data stored in the flash ROM 40 and supplementary information necessary for reservation recording, such as for example, recording time, channel, recording speed (or recording density), and recording medium, input by the user on the screen through a GUI type menu as shown in a reservation recording table of FIG. 2. Generally, the user can input a recorded broadcasting channel, a reservation date, a recording start time and a recording end time as the information necessary for reservation recording. The reservation contents are stored in the flash ROM 40. In the recording time, the set channel is received by the switching unit 10, and signals are processed by the MPEG encoder unit 20 and recorded on the HDD 30. It has been described that the user directly inputs the necessary information to the reservation recording screen, but it is also possible to automatically receive and store related reservation contents by using data such as a program guide.
However, when reservation recording has been set in the image recording and reproducing apparatus, there is no way to check whether reservation recording has been successfully performed. That is, the user can confirm it by wholly reproducing the recording medium.
When the user sets reservation recording, if a plurality of recording media exists, the user can select one of the recording media. If a residual capacity of the set recording medium is deficient during recording, the set recording medium is firstly fully used, and then replaced by another recording medium. The user is not informed of change of the recording medium. Accordingly, the user has to check the recording media one by one to confirm recorded contents.
On the other hand, even though the user designates the recording speed, if a residual capacity of the recording medium is deficient, the recording speed is controlled to record the whole reservation program. There is no way for the user to confirm change of the speed.

Recording status display apparatus and method thereof


A method of and device for assembling joint components of constant velocity joints wherein into an annular first joint component with a greater diameter and a first longitudinal axis, there is introduced an annular or star-shaped second joint component with a smaller diameter and a longitudinal axis. The first joint component whose introducing aperture is smaller than the smallest radial projection face of the second joint component is ovalized for the purpose of introducing the second joint component due to the effect of at least four groups of forces, with the first and second longitudinal axes being positioned perpendicularly relative to one another.

From U.S. Publication No. 2002/0193166 A1, there is known a constant velocity joint with a ball cage which can be elastically ovalized to such an extent that, when the axes of the ball cage and inner joint part intersect one another approximately perpendicularly and upon contact between a web of the inner joint part and the inner face of the ball cage, the opposed web of the inner joint part is able to pass through an end aperture or the inner joint part is able, via the smallest side projection, to pass through an end aperture of the ball cage or the inner joint part, via the greatest diameter, is able to pass through an end aperture of the ball cage.
With the latter embodiments more particularly, the ball cage has to be subjected to a high degree of deformation which leads to the cage being subjected to a high load, so that, when the load is relieved, a permanent deformation may result.

Method of and device for assembling a constant velocity joint


A data processor compatible for use with a CD and a DVD includes a first modulation circuit for modulating recording data for recording on a CD to generate first modulated data. A second modulation circuit modulates recording data for recording on a DVD to generate second modulated data. A write signal generation circuit generates a first write signal, which is written to the CD, from the first modulated data, and a second write signal, which is written to the DVD, from the second modulated data. The write signal generation circuit is commonly used for the CD and the DVD to reduce the circuit area of the data processor.

The present invention relates to a data processor, and more particularly, to a data processor used in a recording-reproducing device for a compact disc (CD) or a digital versatile disc (DVD) to perform modulation or demodulation.
An optical disc, such as a CD or a DVD, is used as a recording medium that stores a large amount of data. The CD includes a compact disc read only memory (CD-ROM), a compact disc-recordable (CD-R), and a compact disc-rewritable (CDRW). The DVD includes a digital versatile disc read only memory (DVD-ROM), a digital versatile disc-recordable (DVD-R), and a digital versatile disc-rewritable (DVD-RW).
In recent years, a recording-reproducing device compatibly used for a CD-ROM, a CD-R, a CD-RW, and a DVD-ROM has been proposed. To achieve miniaturization, such a recording-reproducing device includes a single-chip large scale integration (LSI) circuit provided with the function of a CD decoder and the function of a DVD decoder. Further, to manufacture a compact recording-reproducing device for a data writable DVD (DVD-R, DVD-RW), an LSI provided with the function of a DVD encoder is being developed.
A writable CD, such as a CD-R or a CD-RW, has a track including grooves formed in lands of the disc. The grooves are slightly wobbled in the radial direction of the CD. Information referred to as absolute time in pregroove (ATIP) is written to the grooves in accordance with the cyclic wobble changes. In a CD-R or CD-RW, the track is traced to read the ATIP information written to the grooves and obtain the absolute time information of the present track position. The absolute time information indicates a position on the disc and is used as address information for designating a write position of the recording medium. The recording-reproducing device uses a laser pickup to detect the wobble cycle and generate a wobble signal.
In a writable DVD, such as a DVD-R or a DVD-RW, areas storing address information, which is referred to as a land prepit (LPP), is provided at predetermined intervals in a track. Unlike the absolute time information of track positions in a CD, the address information of the LPP is obtained from consecutive numbers applied to each sector. The recording-reproducing device uses a laser pickup to detect the position of the LPP and generate a LPP signal.
As described above, a CD and a DVD record address information, which indicates write positions, in a different manner. Further, a CD and a DVD use different data recording formats and perform modulation in different manners. Therefore, in the prior art, the recording-reproducing device includes a data processing circuit for recording data on a CD and a separate data processing circuit for recording data on a DVD. These circuits are arranged parallel to each other and increase the circuit scale of the LSI.

Data processor used in a plurality of optical disk recording mediums