A charged beam writing method includes acquiring reference data of shapes or positions of a plurality of apertures of a second shaping aperture, thereafter performing a writing operation, scanning a beam passed through a first shaping aperture over the second shaping aperture while a blanking deflector is driven to intercept irradiation of the shaped beam to the surface of a substrate to be processed by the blanking aperture after performing the writing operation for a certain time, measuring the shapes or the positions of apertures of the second shaping aperture by a detector, comparing the shapes or the positions with the reference data to thereby measure shift amounts of the shapes or the positions of apertures of the second shaping aperture, correcting a deflection amount of the objective deflector in accordance with the shift amount, and resuming the writing operation after stopping the driving of the blanking deflector.

1. Field of the Invention
The present invention relates to a charged beam writing technique to write an LSI pattern using a charged beam, particularly to a charged beam writing method and a writing tool configured to correct a beam positional shift on the surface of a substrate to be processed accompanying thermal deformation of a shaping aperture.
2. Description of the Related Art
In recent years, in an electron beam writing tool, a so-called character projection system has been adopted which exposes a character pattern beam formed by a character aperture beforehand to form repeated patterns on a wafer. In this system, a rectangular aperture (opening) is disposed in a first shaping aperture, various pattern apertures (character patterns) are disposed in a second shaping aperture, an image of the first shaping aperture is moved by a beam shaping deflector on the second shaping aperture, and accordingly a desired pattern can be selected. Here, it is assumed that a beam shaped by the character pattern is also categorized in shaped beam.
Additionally, most of the energy of the electron beam which does not pass through the aperture is absorbed by the second shaping aperture in a state in which the electron beam is applied onto the second shaping aperture. For example, silicon is used in a material of the aperture, and the coefficient of thermal expansion is about 2.4×10−6/K. Even when the material symmetrically expands, but when temperature rises by 40K, the opening positioned apart from a center of the aperture by 1 mm moves by about 100 nm. When a reduction ratio of electron optics is 1/15, a positional shift is about 7 nm on the substrate to be processed, and the positional shift cannot be ignored. In heat inflow during the writing, both position and quantity of heat change with time, and it is therefore difficult to predict movement of an aperture position by the thermal expansion.
In contrast, there has been proposed a method of scanning the electron beam on a mark disposed on a stage for mounting a substrate to thereby measure and correct the positional shift of the beam on the substrate to be processed (refer to, for example, Jpn. Pat. Appln. KOKAI Publication No. 2002-373856). However, in order to apply the electron beam to the mark on the stage, the stage needs to be moved to thereby retreat the substrate to be processed in such a manner as to prevent the electron beam from being applied to the substrate to be processed. Since the stage movement is much slower than deflection of the electron beam, correction of the positional shift requires a long time. Moreover, when the positional shift is corrected many times during the writing, the above-described mark measuring results in a drop of the serviceability ratio of the tool.
Thus, the beam positional shift on the surface of the substrate to be processed accompanying the thermal deformation of the second shaping aperture has not heretofore been ignorable. When the positional shift is measured using the mark on the stage, the stage needs to be moved greatly, and there has been a problem that much time is required in measurement and the tool serviceability ratio drops.
Therefore, there has been a demand for realization of a charged beam writing method and a writing tool capable of measuring and correcting the shift of the beam applied position on the surface of the substrate to be processed accompanying the thermal deformation of the shaping aperture and capable of contributing to enhancement of the tool serviceability ratio.

Charged beam writing method and writing tool


Both homojunction and heterojunction bipolar transistor structures are fabricated in unique trenched configurations so as to better utilize their surface areas by employing both the vertical and horizontal portions of their base regions with equal effectiveness. An important advantage of the unique trenched configurations is that the base region of each trenched structure is of precisely the same thickness throughout--both vertical and horizontal portions. Consequently, the transit time for charge carriers to diffuse across the base region and the base transport factor are uniform because of the uniform base thickness. Moreover, the parasitic capacitance region of each trenched structure beneath base metallization contacts is only a small portion of the entire base-collector junction region. Accordingly, the RC time constant of each trenched structure is very low and the high frequency response gain of the heterojunction trenched bipolar transistor structure is an order of magnitude higher than its conventional heterojunction bipolar transistor counterpart.

1. Field of the Invention
The present invention relates to bipolar transistor structures, but more specifically, the present invention relates to homojunction and heterojunction trenched bipolar transistor structures.
2. Description of the Prior Art
Silicon bipolar transistors are produced by a highly evolved, long established and well known technology. FIG. 1 is a generalized isometric/schematic cross-section view of a conventional homojunction silicon bipolar transistor (SBT) structure 10 which can be fabricated by this technology. The conventional homojunction SBT structure 10 comprises a base region 12 sandwiched between an emitter region 14 and a collector region 16. An active region 18 of the conventional homojunction SBT structure 10 is that area directly beneath the emitter region 14 as bounded by the dotted lines 20. The active region 18 is approximately equal to the area of the emitter region 14, which is of width w per unit length thereof. As shown, the depth d of the emitter region 14 is usually smaller relative to its width w. Thus, since the dimensions a and a' are greater than the dimension b of the base region 12, beneficial contribution of the side areas, i.e., 2 d per unit length, to the active operation of the emitter region 14 is negligible. In fact, none of the other portions of the conventional homojunction SBT struction 10 beneficially contribute to its active operation. For example, the base-to-collector junction 22, which interfaces the base region 12 and collector region 16, creates an unwanted base-to-collector parasitic capacitance. This unwanted base-to-collector parasitic capacitance lies in the horizontal and vertical planes of the base-to-collector junction 22 to the right and to the left of the dotted lines 20, outside the active region 18, i.e., the parasitic region.
Still referring to the conventional homojunction SBT structure of FIG. 1, to minimize the unwanted base-to-collector parasitic capacitance, the dimensions a, a' and b of the base region 12 should be equal. However, as illustrated in FIG. 1, in practical application, the dimensions a and a' of the base region 12 must be of sufficient width to permit metallization of the surfaces of base ohmic contacts (not shown). In addition, the width w of the emitter region 14, which translates into the width of the active region 18, and, accordingly, the beneficial width of the base-to-collector junction 22, must be kept small to minimize the effective base resistance. Thus, in actual practice, the parasitic region typically exceeds that of the active region 18. This results in the dimensions a and a' being much larger than the dimension b. Hence, the ideal conventional homojunction SBT structure 1 and its above mentioned practical counterpart does not utilize its volume in the most effective and efficient manner.

The United States of America as represented by the Secretary of the Navy


The invention provides a composition comprising a matrix of chitosan and a tannin wherein the chitosan is electrostatically bonded to the tannin to form a chitosan-tannin composite material. The chitosan can be partially or fully deacetylated, and the tannin can be a monomeric or an oligomeric proanthocyanidin or a hydrolysable tannin. The chitosan-tannin composite material can be a nanoparticle, a hydrogel film, a bio-foam, or a biogel, or the chitosan-tannin composite material can coat a liposome. The composite materials can be used for drug delivery, for antibacterial and/or antifungal applications, for tissue engineering applications, for wound healing applications, or they can be used as adjuvants for vaccination, including oral vaccinations. The invention also provides methods of preparing the composite materials and their various forms.

Natural polymers have been used in many pharmaceutical applications and medical device technologies. One natural polymer, chitosan, has been used for the preparation of nanoparticles, microspheres, hydrogels, films, fibers, and tablets. Chitosan has been used to prepare potential drug delivery systems such as oral, nasal, parenteral, transdermal and ophthalmic formulations. Chitosan has also been used to prepare wound dressings and tissue scaffolds (Kumar et al., Chem. Rev. 2004, 104, 6017-6084). However, chitosan formulations and materials suffer from numerous drawbacks including limited stability, biodegradability and tensile strength. Materials such as modified chitosan and synthetic composite materials have tested for many of the same uses for which chitosan has been evaluated but many of these materials suffer from similar drawbacks, including insufficient biocompatibility.
Accordingly, there is a need for new materials that are biocompatible and biodegradable, and that have suitable stability and mechanical properties for use in human and other mammalian treatments and therapies. These new materials and compositions would preferably have advantages over chitosan alone, such as additional and/or improved antimicrobial and antifungal properties, and improved physical properties. The ability to use these materials as tissue scaffolds and/or systems for the delivery of therapeutic agents would further aid researchers in the areas of biomaterials and drug delivery.

This patent is subject to a terminal disclaimer.


A wrench for use on an oil filter having a first curved member with a plurality of apertures formed therein at spaced intervals, a second curved member having a slot at one end so as to receive a first of the first curved member extending therethrough, and a handle extending outwardly of the first and second curved members. The slot includes a locking member affixed thereto. The locking member removably engages one and only one of the apertures of the first curved member. The handle has a first portion affixed to the first and second curved members and extending outwardly therefrom and a second portion hingedly connected to the first portion. The second portion of the handle has a first position in planar alignment with the first portion and a second position in perpendicular relationship to the first portion. The handle has a third portion hingedly connected to an end of the second portion and movable between a position in planar alignment with the first and second portions to a position perpendicular to the second portion.

There have been conventional wrenches of which a tightening member is a single curved member, chain, cap, or an interlinking of several curved members for the purpose of forming a circular configuration. The tightening member of the conventional wrench has to be held against the oil filter body with one hand while the other hand rotates the lever in order to make the tightening member tightly engage the oil filter body. This tightening is required to prevent slipping, sliding or drooping from the oil filter body before the removing force or screwing force can be applied. Without this tightening, the removing or screwing operation cannot be performed.
As described hereabove, it is very difficult or impossible to operate the conventional wrench where there is only limited room or space around the oil filter. The reason for this is that the lever arm of the conventional wrench needs a lot of room or space to travel in order to keep the tightening member tightened against the oil filter body. There must still be enough room left for it to travel so as to generate the removing force or screwing force to the oil filter body. Additionally, the conventional wrench cannot be used to remove or screw or oil filters without turning a side. Thirdly, this conventional wrench provides only one size or a very limited size variation for the oil filter body. In the past, other types of wrenches have been used which provide several size ranges by utilizing a movable clamping member. This clamping member stretches outwardly and needs a great deal of room around the oil filter body. Additionally, the conventional wrench cannot be operated in both vertical and horizontal positions if the situation should require.
U.S. Pat. No. 4,916,993, issued on Apr. 17, 1990, describes an adjustable oil filter wrench which includes an adjustable strap for accommodating oil filters of varying diameters. The straps are secured to an aligned handle and provided with an arcuate saddle for accepting an adjustably pivotal band therein for application of torque to the band over a substantial circumferential surface of the oil filter. A worm screw is provided which simultaneously engages several of the apertures formed in the band for threadedly and continuously adjusting the diameter of the wrench.
U.S. Pat. No. 4,750,388, issued on Jun. 14, 1988, to Hagen shows an oil filter gripping tool that includes a looped band, the ends of which are connected to scissor levers through a pair of double pivot hinges. The hinges allow movement of the levers to tighten the band to contract to closely fit and grip the oil filter. With the band tightened about the oil filter, turning the levers causes rotation of the oil filter.
It is an object of the present invention to provide an oil filter wrench of simple and inexpensive construction.
It is another object of the present invention to provide a wrench which provides the tightening members which can tightly engage the oil filter body without slipping, drooping or sliding.
It is another object of the present invention to provide an improved wrench which is applicable to any size of existing oil filter.
It is a further object of the present invention to provide an improved wrench which can operate in very limited spaces around the oil filter body.
It is still another object of the present invention to provide an improved wrench which can remove or screw the oil filter with the lever arm in a vertical and/or horizontal position.
It is still another object of the present invention to provide an improved wrench which can operate in both clockwise and counter-clockwise directions without sliding.
These and other objects and advantages of the present invention will become apparent from a reading of the attached specification and appended claims.


A data processor (3) executes a real time trace function which allows an external development system (7) to dynamically observe internal operations of data processor (3) without assuming a type or availability of an external bus and without significantly impacting the efficiency and speed of the data processor (3). A debug module (10) of data processor (3) provides a parallel output port for providing internal operating information via a DDATA signal and a PST signal. The DDATA signal provides data which reflects operand values and the PST signal provides encoded status information which reflects an execution status of a central processing unit 92). Furthermore, the DDATA signal also provides captured instruction address program flow changes to allow external development system (7) to trace an exact program flow without requiring an externally visible address bus or an externally visible data bus.

When a data processing system fails to operate as designed, various analysis techniques may be used to identify a source of the failure. Generally, trace functions and breakpoint functions are implemented within the data processing system to aid in the isolation of failing circuitry and the correction of failing software programs.
Trace functions provide a means for allowing an external user to observe intermediate results of execution of a data processing operation. Trace functions generally provide a status of selected registers and memory included in the data processing system after each instruction or a predetermined group of instructions of a software program is executed by the data processing system. By reflecting the status of selected registers and memory, the trace function provides the external user with very detailed information about an internal programming model of a data processor or data processing system. With this information, many types of errors may be identified and subsequently corrected. Breakpoint functions also provide a method for identifying and isolating erroneous software code or faulty circuits in a data processing system. A breakpoint function is, in effect, where a preprogrammed event occurs causing a break in a software program. Data is then retrieved to determine a status of the software program. Like the trace function, the breakpoint function allows the external user to ascertain a status of each of the selected registers and memory such that data processing errors may be identified.
Both the trace function and the breakpoint function have been integrated in currently available data processing systems to provide the previously described isolation and identification capabilities. For example, the i960 Jx microprocessor, available from the Intel Corporation of Santa Clara, Calif., is an integrated circuit microprocessor which has internal breakpoint registers which generate trace events and trace faults. In the i960 Jx microprocessor, the internal breakpoint registers are dedicated to trapping on either instruction execution addresses or on the addresses of various types of data accesses. To use the tracing facility of the i960 Jx Microprocessor, software which utilizes the microprocessor must provide fault handling procedures or interface with a debugging monitor program. Software is also required to manipulate several registers and control bits to enable various tracing modes and to selectively enable or disable the tracing function.
Similarly, the 80486 microprocessor, also available from the Intel Corporation of Santa Clara, Calif., is an integrated circuit microprocessor which has internal breakpoint registers and is able to perform the trace function. In the 80486 microprocessor, a breakpoint instruction is implemented for use by internal software debugger devices, where internal software simply refers to software running on the data processing system. During general operation, a software debug program may implement the breakpoint instruction at all desired breakpoints which depend on a type of software code executed. The 80486 microprocessor also provides a mechanism for implementing a single step trap function which executes an interrupt after the trap routine is executed.
While the i960 Jx microprocessor and 80486 microprocessor integrate the breakpoint and trace functions, the debug functionality of the microprocessors requires the microprocessors to suspend normal operation and enter into a special debug exception routine. During the debug exception routine, the microprocessors do not function as they would during normal operation and, therefore, the failures in circuitry or software may not occur in a similar manner. Consequently, the external user will not be able to verify and isolate a root cause of the failures in either microprocessor when the real-time failing conditions do not actually occur.
Furthermore, both the i960 Jx microprocessor and the 80486 microprocessor require either an internal software debug program which is executed by the microprocessor to provide program control during the breakpoint and trace functions. The use of such debug control provides a very intrusive manner of debugging which requires a significant amount of overhead. As well, the use of debug software may not provide a true reflection of a faulty circuit or sequence in the failing microprocessor.
Therefore, a need exists for a data processor which provides both real time trace and real time debug functions. If both the trace and debug functions are executed in a manner which reflects operation of the data processor during normal operation, and not in a special debug mode of operation, the external user will more accurately identify and correct failures in the circuitry and software of the data processor.

Data processing system for performing a trace function and method therefor


This invention relates to a method, system and program product to detect reduction variables in assignment statements in the source code for enabling the parallel execution of program loops. The reduction variables found using the method herein described can be tagged to the respective loops and passed to a compiler through compiler directives for parallelizing the reduction operation, along with the information about each variable's respective associative operator.

A loop in a computer program can be executed in fully parallel form if the output from the loop does not depend in any way upon the execution ordering of the data accesses from different iterations. Compiler writers often refer to such loops as doall loops. However, when a loop is not a doall loop, it may sometimes be possible to arrange the iterations into several groups such that the iterations in each group can be executed in fully parallel form provided certain synchronization conditions are met between a group completing its execution and the next group beginning its execution. An extreme case of partially parallelizable loop is the completely sequential loop where the number of groups is exactly the same as the number of iterations.
Whether a loop is fully parallelizable or not may be determined by analyzing the data dependence relations between the statements in the loop body. There are three possible types of dependencies between two statements that access the same memory location: flow (write then read), anti (read then write), and output (write then write). The simplest situation occurs when there is no flow, anti, or output dependencies, in which case all iterations in the loop are independent and can be executed in parallel.
Flow dependence: Consider the code fragment given below—
do i = 1, nA(k(i)) = A(k(i)) + A(k(i−1))if(A(k(i)) .eq. .true.) then... ... ... ... ... ...endifenddo
Since Flow dependence exists between accesses in different iterations of the loop, its semantics cannot be guaranteed if the loop is executed as a doall loop. For example, in the above code fragment, the iterations must be executed in the order of iteration number because iteration i+1 needs the value that is produced in iteration i, for 2≦i ≦n.
Anti or Output dependence without Flow dependence: In this case, the loop must be modified to remove these dependencies before it can be executed in parallel. Unfortunately, not all situations can be handled efficiently. However, two important transformations can be applied to the loop: (1) Privatization, and (2) Reduction parallelization.
Privatization can eliminate certain types of anti and output dependencies by creating, whenever possible, for each participating processor executing the loop, private copies of program variables that give rise to anti or output dependencies. The following example illustrates a loop that can be executed in parallel by privatization.
do i = 1, n/2S1:tmp = A(2*i)A(2*i) = A(2*i−1)S2:A(2*i−1) = tmpenddo
The anti dependencies between statement S1 of iteration i and statement S2 of iteration i+1, for 1≦i<n/2, can be removed by privatizing the temporary variable tmp.
In Reduction Parallelization, a reduction variable is defined as a variable whose value is used in one associative operation of the form x=x {circle around (×)} exprn, where {circle around (x)} is the associative operator and x does not occur in exprn or anywhere else in the loop. The operand exprn is called the associative operand. By their very nature, reduction variables are accessed in a specific pattern. A simple and frequently occurring example of a reduction is illustrated by statement S1 in the following example:
do i = 1, ndo j = 1, mS1:A(j) = A(j) + exprnenddoenddowhere the operator {circle around (×)}, in this case is the + operator. The access pattern of the array A( ) is read, modify, write, and the function performed by the loop is to add a value computed in each iteration to the value stored in A( ). This form of reduction is often called an update.
Reduction parallelization requires two steps: recognition of the reduction variable, and parallelizing the reduction operation.
While parallelization can be performed at run-time to a certain extent, it is desirable whenever possible, to perform it at compile time as it minimizes the execution overhead that may dilute the benefits of parallelization. Techniques for run-time parallelization have been described by Rauchwerger, L., in 'Run-Time Parallelization: It's Time Has Come', Journal of Parallel Computing, Special Issue on Language and Compilers, Vol. 24, Nos. 3–4, 1998, pp. 527–556.
The difficult part in reduction parallelization faced by compilers is in recognizing the reduction statements. So far, this problem has been handled, with limited success, at compile-time by syntactically pattern matching the loop statements with a template of a generic reduction, and then performing a data dependence analysis of the variable under consideration ensuring that it does not appear anywhere else in the loop other than in the reduction statement. The method is inadequate because there are many more patterns than there are templates.
U.S. Pat. No. 5,481,723 describes a system and method for enabling compile time parallelization for the specific case of nested do loops. It is however, not suitable for unnested loops.
The present invention describes a novel method for detecting reduction variables in source code as a pre-process before compilation. This process requires recasting of the source code expressions in accordance with the method described in U.S. Pat. Publication No. 2001/0003211 A1.
For completeness, it is to be noted that parallelizing the reduction method in a scalable manner, requires the reduction variable to be privatized in the transformed doall and the final result of the reduction operation to be calculated in an inter-processor reduction phase following the doall, that is, a scalar is produced using the partial results computed in each processor as operands for a reduction operation (with the same operator) across the processors. If the reduction operation is commutative, then the cross-processor merging phase can be done in any order, else the merging phase will have to be done in an orderly manner.

Detection of reduction variables in an assignment statement

International Business Machines Corporation


An analog buffer circuit which has small input and output offsets and reduced power consumption even if it is formed on an insulating substrate by TFTs, a display device which uses the analog buffer circuit as a peripheral driving circuit for a display unit, and a portable terminal in which the display device is provided as a screen display unit are provided. By performing offset detection on a source follower in such a manner that, for example, two capacitors Cn1 and Cn2 are connected to the gate of a NMOS transistor Qn11 as a source follower, and conduction/nonconduction control of switches Sn1 to Sn5 are performed, if needed, and by sequentially canceling the detected offsets, a final offset voltage is sufficiently reduced and high precision offset cancellation is realized.

In the field of flat-panel display devices as typified by liquid crystal display devices and EL (electroluminescence) display devices, in recent years, in order to achieve panel frame narrowness and reduced panel thickness, a so-called driver-integrated display device has been developed in which, on the same transparent substrate with a display unit composed of pixels arranged in a matrix, a peripheral driving circuit for driving the display unit is provided in an integrated form. Since TFTs are used as pixel transistors in liquid crystal display devices and EL display devices, regarding mounting of the driving circuit on the transparent substrate, the driving circuit is also formed by TFTs.
As the peripheral driving circuit for the display device, an analog buffer circuit is used in many cases in order to increase a driving capability. Here, the case of using TFTs to form the analog buffer circuit on the insulating substrate is considered. In TFTs, the absolute value of threshold value Vth is large and its variation is greatly large. Also, it is known that, when TFTs are formed on an insulating substrate such as a glass substrate, the element characteristics of the TFTs are worse than those in the case of TFTs formed on a silicon substrate. As described above, since the absolute value of threshold value Vth of the TFT is large and its variation is greatly large, when TFTs are used to form an analog buffer circuit on the insulating substrate, input and output offsets of the analog buffer circuit and their variations increase.
It is assumed that a plurality of the analog buffer circuit be arranged for, for example, an output unit of a data driver (horizontal driver) in a driver-integrated display device so as to correspond to data lines (signal lines) in the display unit. In this case, large variations in the input and output offsets of the analog buffer circuit cause a large output-potential error in each circuit. Then, this output-potential error is a potential difference between columns of the display unit, and is displayed as a vertical stripe on the screen. Accordingly, this greatly deteriorates display quality (uniformity).
Also, in the case of using TFTs to form an analog circuit on an insulating substrate, a large absolute value of TFT threshold value Vth causes large power consumption because a high power-supply voltage and a large idling current are required for circuit driving. Accordingly, this is a disadvantage in reducing power consumption of the display device, although a driver-integrated configuration is established.
In view of the above problems, the present invention is made and an object thereof is to provide an analog buffer circuit in which, even if the analog buffer circuit is formed by TFTs on an insulating substrate, it has small input and output offsets and less power consumption, a display device in which the analog buffer circuit is used as a peripheral driving circuit for a display unit, and a portable terminal provided with the display device as a screen display unit.

Analog buffer circuit, display device and portable terminal


Flat-model, 32-bit, real-mode execution may be obtained in an INTEL.TM. X86-compatible processor of a computer to increase address space, while handling interrupts transparently. A protected-mode operating system is not required. A LOADALL instruction available to an operating system may load hidden cache descriptor registers of a processor with the base addresses, segment limits, and other attributes consistent with 32-bit, real-mode operation to provide 32-bit addressing. Interrupts, would normally interfere with the contents of the hidden cache descriptor registers. A new interrupt vector table is provided, with each new vector therein pointing to one of the new interposer routines provided. Upon receipt of an interrupt, a new interrupt vector points to an interposer routine, which saves the state of the hidden cache descriptor registers. The interposer routine then simulates the interrupt to an appropriate interrupt service routine by vectoring through the old or original interrupt vector table to the interrupt service routine. After its execution, the interrupt service routine provides an interrupt return to the calling interposer routine. The interposer routine then restores the state of the hidden cache descriptor registers to the 32-bit, flat-model execution state. The interposer routine may then provide its own interrupt return, rendering its own operation transparent to both the incoming interrupt and the execution conforming thereto.

1. The Field of the Invention
This invention relates to computer systems and, more particularly, to novel systems and methods for real-mode addressing of computer memory above the one megabyte limit currently imposed by real-mode operating systems, and without resorting to protected-mode operating systems with their inherent complexity and overhead.
2. The Background Art
Computers relying on processors (CPUs) such as the X86 family of Intel processors, may operate in real mode or protected mode. Real-mode operating systems rely on 16-bit addressing. Protected-mode operating systems operate with 32-bit addressing. Real-mode addressing schemes may not create and use addresses greater than 20 bits, corresponding to approximately one megabyte of address space. Address space is simply a number in a mathematical space, but limits the ability of a processor to access the random access memory (RAM) or other memory above one megabyte.
One may think of "real-mode" addressing as 20-bit addressing. Should 4 gigabytes (a 32-bit number) of memory become available, a 20-bit addressing scheme cannot address more than about 1 megabyte of the 32-bit address space. Thus, in real mode, only approximately one four-thousandth of the total available memory or address space could actually be accessed by the processor.
Protected-mode operating systems may use addresses up to 32 bits, corresponding to approximately four gigabytes of memory. Operation in protected mode may provide descriptor tables resident in memory. The descriptor tables may include a global descriptor table (GDT), a local descriptor table (LDT), and an interrupt descriptor table (IDT). Each descriptor table contains descriptors. A descriptor may be thought of as one row of a table, for example. Within each descriptor (row) may be an access rights field, a base physical address field, and a segment length field.
During operation of a processor, the contents of a particular descriptor in any particular descriptor table (e.g., GDT, LDT, or IDT) may be loaded into a hidden cache descriptor register associated with a particular segment register of the processor. The processor relies on the hidden cache descriptor registers to perform the processor's addressing function. Since protected mode permits 32-bit addressing, the hidden cache descriptor registers must also contain sufficient capability to support 32-bit addressing.
However, in real mode, the hidden cache descriptor registers are limited by the real-mode loading scheme. Any time a segment register is loaded in real mode, a corresponding hidden cache descriptor register is loaded with values that limit the addressing functionality thereof.
For example, the base address will never be greater than a 20-bit value. The segment length may never be larger than a 16-bit value. Likewise, the access rights are set in accordance with the limitations and operations of real mode. The D/B bit is set to 16-bit addressing. Also, the access rights for the code segment register, data segment register, and the other segment registers, may all have a common value allowing all segments to have read, write, and execute access for the processor with respect to all segments.
By contrast, in protected mode, code segments are typically limited to read access and execute access only. Data segments may typically be limited to read access and write access, with no execute access permitted. The extra segment register, stack segment register, FS register and GS registers are typically treated as data registers.
Thus, in protected mode, certain operations by the processor are protected. Instead, real-mode operation allows all operations for all segments. Real mode is sometimes seen as a free-for-all that may destroy code or data without security measures intervening.
The price for protected mode may be paid in several ways, or exacted in several ways. From a programming perspective, the addressing model is much more complex than that for real mode Accordingly, addressing schemes are more complex to program. Thus, operating systems become substantially more complex to accommodate the protection mechanism implemented by the various descriptor tables (GDT, LDT, IDT). From a processor's point-of-view, management of the descriptor tables becomes substantial. A 15% degradation in performance is typical to support the loading and unloading of the hidden cache descriptor registers from the descriptors contained in any appropriate descriptor table.
What is needed, is an apparatus and method for achieving the addressing capability of a protected-mode operating system, without the attendant overhead and commensurate degradation of performance. Certain protections provided by a protected-mode operating system are desirable, and should be maintained. Thus, a real-mode 32-bit, flat-model execution is needed.

Real-mode, 32-bit, flat-model execution apparatus and method


A curb covering device for covering a portion of a curb featuring a generally flat panel; a first folding line, a second folding line, and a third folding line, wherein the first folding line is positioned about halfway between the third side edge of the panel and the fourth side edge of the panel, the second folding line is positioned between the first folding line and the fourth side edge of the panel, and the third folding line is positioned between the third side edge of the panel and the first folding line. The folding lines function to allow the panel to be folded over the portion of the curb.

When parking (e.g., parallel parking) a vehicle, it is very easy to contact the vehicle's wheels or tires with the curb. This unfortunately can cause significant damage to the wheels or tires. The present invention features a curb covering device for covering a portion of a curb. The covering device helps prevent damage to the vehicle if the vehicle comes in contact with the curb. In some cases, the curb covering device may be useful for businesses such as restaurants with valet parking because the device can help prevent damage to the vehicle and potential lawsuits. Without wishing to limit the present invention to any theory or mechanism, it is believed that the curb covering device of the present invention is advantageous because it is lightweight and does not need to be permanently attached to the curb, making it portable and easy to install.
Any feature or combination of features described herein are included within the scope of the present invention provided that the features included in any such combination are not mutually inconsistent as will be apparent from the context, this specification, and the knowledge of one of ordinary skill in the art. Additional advantages and aspects of the present invention are apparent in the following detailed description and claims.


A cylinder head gasket includes a metallic gasket layer having through-openings and, at its peripheral outer margin, a first sealing element for providing a seal. The first sealing element forms a sealing line extending circumferentially about the gasket layer and surrounding the through-openings. The side of the first sealing element facing away from the peripheral outer margin of the gasket layer includes a vent hole arranged adjacent to a sealing line break and located in a first gasket layer region which is, on only a first side of the gasket layer, on both sides of the sealing line break, continuously bounded by the first sealing element and a second sealing element. The first sealing element and the second sealing element extend around the first gasket layer region such that a fluid flow path extending from the sealing line break to the vent hole has at least one change in direction.

The invention relates to a cylinder head gasket and more particularly to a cylinder head gasket for use in relatively large engines (as compared to passenger car engines) and primarily for use in so-called large-scale engines as are employed on trucks, construction machinery and the like and are prone to heavy soiling in use of such vehicles and machines. These large engines can have a single cylinder head that extends over all combustion chambers/cylinders of a cylinder block (also called crankcase) or of a cylinder bank of a V-type engine and a single cylinder head gasket dedicated to said cylinder head or can have a separate cylinder head and a separate cylinder head gasket for each cylinder.
With these engines, the so-called seal gap that exists between the cylinder head and the cylinder block, the latter usually containing cylinder liners, and that is to be sealed by the cylinder head gasket has a relatively large height/width, generally amounting to approximately 1.2 mm to approximately 5 mm, and with an engine presenting such a wide seal gap there is a particularly high risk when the engine is operating or also when it is being cleaned, such cleaning being undertaken frequently and usually using a high-pressure cleaner, of contaminants getting into the seal gap, in particular solid particles such as dust and other dirt, but also liquids such as splashes of water getting on the engine while in operation or splashing water used in engine cleaning and usually having some detergent added thereto. It is therefore necessary for the seal gap to be sealed by the outer perimeter portion of the cylinder head gasket, and for that purpose it is known in the case of a single-layered cylinder head gasket from ElringKlinger AG, i.e., a cylinder head gasket having only a single metallic gasket layer and being configured as a so-called gasket for a single cylinder, to apply in the immediate vicinity of the outer perimeter margin of the gasket layer on each of the two sides thereof an elastomeric sealing element which is in the shape of an elastomeric sealing material bead (so-called sealing lip) and extends around the gasket layer in the immediate vicinity of the outer perimeter margin thereof.
In the case of this known cylinder head gasket, but also in the case of multi-layered metallic cylinder head gaskets incorporating such a gasket layer having peripheral elastomeric sealing elements as well as in the case of correspondingly configured single-layer and multi-layer cylinder head gaskets including several combustion chamber through-openings, there is however the following problem: It cannot be entirely excluded that, when the engine is operating, gas or liquid leakage, albeit small, may occur around one or more combustion chamber through-openings and/or through-openings for cooling water and/or for engine oil and that consequently pressure would build up, induced by said gas or liquid leakage, in the seal gap region which is located between the cylinder head gasket and the cylinder head and/or cylinder block and is enclosed by the peripheral sealing elements if said seal gap region is, on one or both sides of the gasket layer, gas and liquid-tightly sealed, i.e., a sealed to the outside, by use of peripheral, circumferential and endless sealing elements, i.e., sealing elements closed in themselves. Therefore, in the above-mentioned known cylinder head gasket from ElringKlinger AG each of the peripheral elastomeric sealing elements is interrupted at one, i.e., only at one, location—when seen in a plan view of the cylinder head gasket, each of these peripheral elastomeric sealing elements has two end regions which, when viewed from the outer perimeter margin of the gasket layer, overlap each other and extend at an extremely small distance from each other so that said seal gap region is, both between the cylinder head and the cylinder head gasket and between the latter and the cylinder block, open to the outside at that one location, thereby preventing said pressure buildup.
However, this break in each of said peripheral circumferential elastomeric sealing elements is an entrance that, albeit localized, may permit dirt and/or liquid from the outside to get into the areas of the seal gap that are located rearward of the peripheral sealing elements, particularly during an engine cleaning procedure using a high-pressure cleaner.
The present invention aims to at least minimize this problem (object of the invention).


The invention relates to a trigger system for small arms, said system including a hammer, a catch associated with the hammer, a trigger, and a trigger bar which cooperates with the trigger and has a first locking edge for engaging with a first fire locking element of the hammer. The aim of the invention is to create a trigger system which has a low trigger resistance and remains operable even in the event of firing failure. To this end, the trigger bar has a second locking edge for engaging with a second fire locking element of the hammer.

So-called Double Action Only trigger systems are already known as pure tension triggers, in which the hammer must first be placed under tension by the trigger for each shot. Through such trigger systems, high safety is provided for the weapon, since it can be stored or laid aside without an additional release of tension. However, conventional Double Action Only trigger systems have uniform trigger travel and a relatively high trigger resistance.
There are also trigger systems that are already partly under tension and have shorter trigger travel and make it possible to set off a shot with low trigger resistance. Often, however, a second pull is not possible in these trigger systems after a firing failure.
From U.S. Pat. No. 6,341,442 B1, a trigger system for Double Action small arms is known with a hammer, a locking edge associated with the hammer, a trigger, and a trigger bar that cooperates with it. The trigger bar in this known system has a rear arm with a single projection to make contact with an associated contact surface of the hammer.


A sense amplifier enable signal generating circuit of a semiconductor memory device includes: a sense amplifier enable signal generating section for receiving an input signal externally applied, and generating a sense amplifier enable signal; a delay section for delaying the sense amplifier enable signal generated from the sense amplifier enable signal generating section; a detecting section for detecting the variation of a power supply voltage in accordance with a control signal externally applied, and generating a detection signal for the variation; a transfer section for transferring the delayed sense amplifier enable signal of the delay section in accordance with the detection signal generated from the detecting means; and an output section for receiving the sense amplifier enable signal generated from the sense amplifier enable signal generating means and the delayed sense amplifier enable signal of the delay section, and generating an output signal having a constant pulse width.

Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a sense amplifier enable signal generating circuit of a semiconductor memory device capable of generating a sense amplifier enable signal having a constant pulse width irrespective of the variation of a power supply voltage.

Sense amplifier enable signal generating circuit of semiconductor memory devices

Hyundai Electronics Industries Co., Ltd.


A motor includes a fixed portion, a rotor, and at least one balancing plate fixed on the fixed portion. The fixed portion includes a stator having at least one pole plate that extends to form a plurality of pole faces, with a gap being defined between a pair of the pole faces adjacent to each other. The rotor includes a shaft and an annular magnet facing the pole faces. The balancing plate includes at least two magnetically conductive faces respectively aligned with the gaps. Each magnetically conductive face includes a length not smaller than that of an associated gap. The pole faces face at least one face of the annular magnet. When the rotor turns, the annular magnet of the rotor induces the alternating magnetic fields created by the stator and attracts the magnetically conductive faces to thereby maintain rotational balance of the rotor.

1. Field of the Invention
The present invention relates to a balancing structure for a motor. In particular, the present invention relates to a balancing structure for maintaining stable rotation of a rotor of a motor.
2. Description of Related Art
A wide variety of structures for maintaining rotational balance for a rotor of a motor have been proposed. One of these structures comprises a fixed portion, a rotor, an attracting portion, and a magnetically conductive portion. The fixed portion includes a base, an axial tube fixed on the base, a bearing received in the axial tube, a stator, and a circuit board. The stator includes a coil with axial winding or radial winding and a plurality of pole plates (or pole arms). The rotor includes a shaft rotatably extending through the bearing and an annular magnet surrounding the pole faces of the pole plates. The attracting portion is provided on a bottom of the rotor or a top end of the axial tube. Alternatively, the attracting portion is provided by the annular magnet or the alternating magnetic fields created by the pole plates of the stator. The magnetically conductive portion is made of a magnetically conductive material and may be comprised of a disc with two arcuate edges, a casing fixed in a rotor housing of the rotor, an annular plate, a plurality of arcuate plates, or a rotor housing of a spindle motor. The magnetically conductive portion may be provided on the circuit board, an inner periphery of the rotor, or the bottom of the rotor, and associated with the attracting portion. Such a structure is disclosed in, e.g., Taiwan Utility Model Publication Nos. 383818, 422365, 428838, and M241969, U.S. Pat. Nos. 6,097,120; 6,483,209; 6,700,241; and 6,727,626, and U.S. Patent Publication No. 2005/0006962.
When the motor turns, alternating magnetic fields are created by the pole faces of the magnetic pole plates (or pole arms). The magnetically conductive portion is attracted by the attracting portion during rotation of the rotor, thereby maintaining rotational balance of the rotor, avoiding disengagement of the rotor shaft from the stator, reducing rotational friction of the bearing, and prolonging the life of the motor.
It is common to make the size of the metal plate consisting of the magnetically conductive portion as large as possible so as to provide a large area facing the magnet of the attracting portion (such as the annular magnet). This may result in excessive attracting force between the magnetically conductive portion and the attracting portion for balancing the rotor. In a case that the attracting portion is provided by the annular magnet and the magnetically conductive portion is provided on the fixed portion, the magnetically conductive portion often extends across the alternating magnetic fields created by the pole faces of the stator, adversely affecting the alternating magnetic fields and lowering the rotational efficiency of the rotor. On the other hand, alternating magnetic fields do not exist in the gap between two adjacent pole faces. Thus, it is most desirable to provide the attracting portion in the gap. However, none of the conventional designs provides the attracting portion in the gap. At best, the gap is covered by an attracting portion with an excessively large area, leading to unsatisfactory balancing effect for the rotor.


A composition of matter for application to a body surface or membrane to administer oxybutynin by permeation through the body surface or membrane, the composition comprising, in combination, the oxybutynin to be administered, in a therapeutically effective amount; and a permeation-enhancing mixture comprising a monoglyceride or a mixture of monoglycerides, and a lactic ester or a mixture of lactate esters; present in specific concentrations.

The transdermal route of parenteral delivery of drugs provides many advantages over other administrative routes, and transdermal systems for delivering a wide variety of drugs or other beneficial agents are described in U.S. Pat. Nos. 3,598,122; 3,598,123; 3,731,683; 3,797,494; 4,031,894; 4,201,211; 4,286,592; 4,314,557; 4,379,454; 4,435,180; 4,559,222; 4,568,343; 4,573,995; 4,588,580; 4,645,502; 4,704,282; 4,788,062; 4,816,258; 4,849,226; 4,908,027; 4,943,435; and 5,004,610. The disclosures of the above patents are incorporated herein by reference.
In many instances, drugs which would appear to be ideal candidates for transdermal delivery are found to have such low permeability through intact skin that they cannot be delivered at therapeutically effective rates from reasonably sized systems.
In an effort to increase skin permeability, it has been proposed to pretreat the skin with various chemicals or to concurrently deliver the drug in the presence of a permeation enhancer. Various materials have been suggested for this purpose, as described in U.S. Pat. Nos. 3,472,931, 3,527,864, 3,896,238, 3,903,256, 3,952,099, 4,046,886, 4,130,643, 4,130,667, 4,299,826, 4,335,115, 4,343,798, 4,379,454, 4,405,616 and 4,746,515, all of which are incorporated herein by reference; British Pat. No. 1,001,949; and Idson, Percutaneous Absorption, J. Pharm. Sci., vol. 64, No. b6, June 1975, pp 901-924 (particularly 919-921).
To be considered useful, a permeation enhancer should have the ability to enhance the permeability of the skin for at least one and preferably a significant number of drugs. More importantly, it should be able to enhance the skin permeability such that the drug delivery rate from a reasonably sized system (preferably 5-50 cm.sup.2) is at therapeutic levels. Additionally, the enhancer, when applied to the skin surface, should be non-toxic, non-irritating on prolonged exposure and under occlusion, and non-sensitizing on repeated exposure. Preferably, it should be capable of delivering drugs without producing topical reactions, burning or tingling sensations.
The present invention greatly increases oxybutynin permeability through the skin, and also reduces the lag time between application of the oxybutynin to the skin and attainment of the desired therapeutic effect.
While it is known in the art to combine permeation enhancers, this invention utilizes a novel combination of a monoglyceride and a lactate ester. Further, the invention utilizes a specific concentration of each of the novel components. The combined effect and, further, specific concentrations, of the components produce a significant and surprising improvement over use of either a monoglyceride or a lactate ester alone or the combination in nonspecified concentrations.
Neurogenic bladder disease is a disorder involving loss of control of urination. The major symptoms of this disease are urinary frequency, urinary retention or incontinence. There are two types of lesions that cause a neurogenic bladder. The first, upper motoneuron lesion, leads to hypertonia and hyperreflexia of the bladder, a spastic condition, giving rise to symptoms of urinary frequency and incontinence. The second lesion, a lower motoneuron lesion, involves hypotonia and hyporeflexia of the bladder. The major symptoms in this condition are urinary retention, since the voiding reflex has been lost, and incontinence, which occurs when the bladder "leaks", being full to overflowing.
The majority of neurogenic bladder patients have the spastic or hypertonic bladder. The clinician usually attempts to convert the condition of hyperreflexia and hypertonia to hypotonia, thereby treating the primary problem of incontinence. When the condition has been converted to hypotonia, it can be managed by intermittent catheterization. However, there is a significant population of patients who cannot be converted completely from the hypertonic to the hypotonic condition, and who still find they have urinate every hour or are incontinent.
The use of oxybutynin chloride, as approved by the FDA in the United States, is described in the 1992 Physician's Desk Reference, pages 1332 through 1333 with reference to the drug Ditropan.RTM. manufactured by Marion Merrell Dow. Oxybutynin is normally administered to human beings orally at relatively high doses (5 mg tablets taken two to four times a day). Oxybutynin has been incorporated into tablets, capsules, granules or pills containing 1-5 mg, preferably 5 mg, of oxybutynin chloride, syrups containing 1-5 mg, preferably 5 mg, of oxybutynin chloride per 5 mL and transdermal compositions (creams or ointments) containing 1-10 weight percent ("wt %") oxybutynin chloride. See, BE 902605.
In U.S. Pat. No. 4,747,845, oxybutynin was listed as an agent that could be incorporated into a transdermal synthetic resin matrix system for extended duration drug release, but oxybutynin was not used in the device. In U.S. Pat. No. 4,928,680 oxybutynin was given as a pharmacologically active agent suitable for transdermal delivery, but as with the above reference, oxybutynin was not incorporated into the device.
Oxybutynin has been incorporated into a device having a water impermeable barrier layer, a reservoir containing oxybutynin in contact with the inner surface of the barrier layer and a removable protector layer in contact with the other surface of the reservoir. The reservoir was a polyurethane fiber mat impregnated with an aqueous solution containing 25 mg/mL of oxybutynin. The device was placed on a 20 .mu.m thick polybutadiene film. The non-barrier carrying surface was in contact with 0.05 M isotonic phosphate buffer solution. The in vitro release rate measured was approximately 12 mg over 24 hours through a 49 cm.sup.2 area or 10 .mu.g/cm.sup.2.hr. (U.S. Pat. No. 4,784,857 and EP 0 250 125).
In Pharm Res, "Development of Transdermal Delivery Systems of Oxybutynin: In-Vivo Bioavailability", P. Keshary et al, (NY)8 (10 Supp) 1991, p. S205 three types of transdermal delivery systems, using matrix-diffusion controlled and membrane-permeation controlled technologies were discussed. The in vitro permeation rate of about 9, 12 and 12 .mu.g/cm.sup.2.hr and in vitro release rates (sink condition) of about 1160, 402 and 57.2 .mu.g/cm.sup.2.hr were obtained from Silastic monolithic, acrylic pressure sensitive adhesive matrix and reservoir type delivery systems, respectively. In humans, steady state plasma concentrations of about 1.86 ng/mL were obtained after 6 hours of application of a single 20 cm.sup.2 patch of the acrylic pressure sensitive adhesive matrix type.
While it is known in the art to formulate a dual permeation enhancer system, see eg, European patent publication numbers 0295411 and 0368339, this invention utilizes a novel combination of oxybutynin with a monoglyceride and a lactate ester. Further, the invention utilizes novel concentrations of the monoglyceride/lactate ester permeation enhancer combination. The combined effect of these two permeation enhancers and further, the specific concentrations, ie, 15 to 25 wt % of monoglyceride and 8 to 25 wt % of lactic acid ester, produces a significant and surprising improvement, ie, more than an additive effect, over use of either a monoglyceride or a lactate ester alone with oxybutynin or the combination in nonspecified concentrations.

Monoglyceride/lactate ester permeation enhancer for oxybutnin


A method and apparatus enabling the analog and digital triggering of a signal analysis device such as a Logic Analyzer, wherein separate analog and digital signal paths provide separate analog and digital processing of an input test signal for enabling the triggering of a signal analysis device upon analog and digital signal conditions.

Signal analysis devices such as Logic Analyzers, digital storage oscilloscopes (DSOs) and the like, are utilized to monitor the signal activity in a wide variety of systems. For example, Logic Analyzers provide the capability to monitor the logical activity of a digital system. The Logic Analyzer is an instrument having, typically, dozens of input channels, a relatively large memory and the ability to disassemble/decode bus states and phases. Typically, a Logic Analyzer is electrically coupled to a device or system under test via a hardware interface to capture data while the device or system under test steps through a process. The Logic Analyzer tests for a preset condition or trigger to control the recording or processing of the signals generated by the device or system under test. The conditions or triggers used for Logic Analyzers are typically digital representations of events.
One problem with present digital signal analysis devices, such as Logic Analyzers, is that they capture data at a very low level of detail. The low detail level makes it difficult to correlate analog signal anomalies with analyzer data, thereby inhibiting the search for the root cause of an analog anomaly within the collected analyzer data.
In an attempt to correct for this shortcoming, some Logic Analyzers include "oscilloscopes on a board" that plug into the Logic Analyzer mainframe. These oscilloscopes are separate instruments that are contained in the same enclosure as the Logic Analyzer. In such combination instruments, in order to trigger on analog events (e.g., a runt signal), the user must attach two probes to the same point. The first probe is the digital logic probe for the Logic Analyzer and the second probe is the analog probe for the device under test. Such connection is necessary because the analog-to-digital conversion for the Logic Analyzer is performed in the probe tip. A trigger out signal from the scope unit must then be connected to the Logic Analyzer external trigger input.
Utilizing such combination instruments though, leads to increased costs, a larger form factor and timing differences which can result in measurement inaccuracy.

Method and apparatus for the digital and analog triggering of a signal analysis device


The invention describes diagnostic methods and compositions for determining the amount of protease in a body fluid sample. In particular, the invention detects proteases by a method in which both a reversible inhibitor of the protease and an irreversible inhibitor of interfering proteases during the detection step are employed to increase the sensitivity of the enzyme capture assay. The assay detects normal serum levels of activated protein C.

Proteases are proteolytic enzymes that catalyze the cleavage of peptide bonds in other proteins. The effect of such cleavage on protein molecules is diverse. In some instances proteolytic cleavage causes the cleaved protein to become inactive. In other instances proteolytic cleavage causes a once inactive protein to become activate. In yet other instances proteolytic cleavage is a mechanism whereby a single polypeptide precursor is cleaved into two or more individual polypeptides.
Proteolytic enzymes are grouped into families based on similar functions, active sites, amino acid sequences, and/or three-dimensional structures. Doolittle, Science, 214:149 (1981); and de Haen et al., J. Mol. Biol., 92:225 (1975). Examples of protease families are the cytochrome c family, the globins, mammalian serine proteases, and the cyclic nucleotide-dependent protein kinase family. Within proteolytic enzyme families are distinct subfamilies which usually share a similar type of physiological activity.
For instance, the common denominator of members in the serine protease family is a shared functional domain, i.e., the catalytic domain defined by amino acid residues Asp.sup.102, Ser.sup.195, and His.sup.57 of chymotrypsin. In addition, serine proteases sharing common physiological functions are categorized into subgroups. Examples of such subgroups are those containing serine proteases which function in the digestion, reproduction, and blood coagulation pathways.
Because proteases are involved in so many physiological processes, it is clinically useful to measure the level of a specific protease in body fluid samples. The measurement would indicate whether the specific protease is present at a level above or below that usually found in a body fluid sample, or may indicate whether a specific protease is present at at in situ, and may therefore provide a diagnostic index. Additionally, the measurement would provide insight into the fate of a specific protease administered to a patient in a therapeutic mode, or monitor the fate of a specific protease targeted by a therapeutic mode. A useful assay for a specific proteolytic enzyme should have the additional feature of indicating whether the specific proteolytic enzyme detected is "active" or capable of becoming activated.
An example of a protease for which measurement in a body fluid sample would be useful is activated protein C (APC), which is a member of the serine protease family subgroup involved in the blood coagulation pathway. Protein C (PC) is a zymogen, that is, it is inactive until converted into APC through interaction with thrombin, another serine protease active in the blood coagulation pathway. PC and APC are structurally different only in a dodecapeptide which is present at the amino-terminal end of PC and absence in APC. The 12 amino acid peptide is removed by proteolytic cleavage. The role of APC is to inactivate coagulation cofactors Va and VIIIa. Therefore, APC regulates thrombosis through its anti-thrombotic activity. In contrast to activation of PC by thrombin, APC is inactivated by the protein C inhibitors .alpha.-1-anti-trypsin, plasminogen activator inhibitor-1, .alpha.-2-antiplasmin, .alpha.-2-macroglobulin, and possibly other nonspecific proteases.
The level of APC and/or PC in a body fluid sample has medical relevance. For instance, the incidence of hereditary PC and protein S deficiency among thrombophilic patients [Gladson et al., Thromb. Haemost., 59:18-22 (1988)] is higher than in the normal population [Miletich et al., N. Engl. J. Med., 317:991-996 (1987)] and many patients have been described with heterozygous PC deficiency and familial thrombophilia [Griffin et al., J. Clin. Invest., 68:1370-1373 (1981); Horellou et al., Br. Med. J., 289:1285-1287 (1984); Bovill et al., Blood, 73:712-717 (1989)]. Complete deficiency of PC activity, whether inherited [Branson et al., Lancet, 2:1165-1168 (1983); Seligsohn et al., N. Engl. J. Med., 310:559-562 (1984)], experimental [Taylor et al., J. Clin. Invest., 79:918-925 (1987); Snow et al., Circulation, 82:III-769 (1990)], or acquired [Gruber et al., Thromb. Res., 42:579- 581 (1986); Mitchell et al., N. Engl. J. Med., 317:1638-1642 (1987)], represents a potentially fatal condition.
Thrombotic complications of PC deficiency can be controlled with PC or APC replacement therapy (Seligsohn et al., Taylor et al., and Snow et al., supra) or liver transplantation [Casella et al., Lancet, 1:435-437 (1988). The presence of measurable quantities of APC-inhibitor complexes in plasma samples from patients with intravascular coagulation indicates that APC is generated in vivo [Heeb et al., Blood, 73:455-461 (1989); Tabernero et al., Thromb. Haemost., 63:380-382 (1990)]. However, methods to detect unbound (free) APC in body samples have not been described except for assays measuring APC at elevated levels during APC infusion therapy of baboons. Gruber et al., Blood, 73:639-642 (1989). Thus, it is presently unknown if unbound APC is normally present in the vascular fluid, and if so, whether it can be measured.
Although it would be useful to detect the level of a functionally active protease with accuracy and sensitivity, including APC, in a body fluid sample, there are several limitations to achieving this goal. First, enzyme-activator interactions subsequent to sample collection will increase the activity of the protease to be measured. For example, PC present in a blood sample is activated by trace amounts of thrombin, thus increasing the level of APC measured to a value above that originally present, if at all, in a blood sample. Second, enzyme-inhibitor interactions subsequent to sample collection will decrease the activity of the protease to be measured. For example, APC which may be present in a blood sample is inactivated by any of a number of protease inhibitors, including those noted above, thus decreasing the level of APC to a value below that originally present, if at all, in a blood sample. Third, specificity of an assay depends on selective detection of the activity of only the protease desired to be detected. Thus, it is necessary to define a substrate that is highly specific for the protease to be detected. And, fourth, because proteases are present in the blood at very low concentrations, an assay to detect activity of a protease must be highly sensitive, without background interference due to factors such as those previously described.
Assays designed to detect APC in the blood have not overcome the obstacles delineated above and thus are not sufficiently sensitive to detect the activity of APC which might be present in a blood sample. For instance, Gruber et al., Blood, 73:639-642 (1989), describes an APC activity assay that measures the level of APC in the blood of baboons infused with APC. There, blood is drawn into benzamidine and citrate to block the serine protease activity in the blood sample and to inhibit complex formation between APC and its inhibitors. The treated blood then is contacted with the anti-PC monoclonal antibody C3 immobilized on microtiter plates, and the complex is washed to remove unbound blood constituents and benzamidine, a reversible inhibitor of APC. The washed complex is then contacted with a synthetic chromogenic substrate for APC and the amidolytic activity of APC is measured. The assay described in Gruber et al. supra was sensitive in the range of 0.005 to 5.0 ug/ml, a range suitable to detect the level of infused APC but too low to detect levels of APC which might be present in blood not infused with APC.
Another assay for APC activity described by Gruber et al., supra, is an APTT assay, i.e., an assay that measures the activated partial thromboplastin time (APTT) of plasma contacted with APC. Again, the data indicate that the APTT assay is useful in determining the level of APC in blood from a subject infused with APC, but is not sensitive enough to determine if APC is present in blood from a subject not infused with APC.
A functional assay for PC is described by Comp et al., Blood, 63:15-21 (1984). There, PC is activated in recalcified plasma by the thrombin-thrombomodulin complex, and contacted with immobilized anti-PC polyclonal antibodies. The activity of immobilized APC toward a synthetic substrate is measured. This assay provides an indication of the level of functional PC present in blood, i.e., PC that is capable of activation. The assay is not useful to determine the level of already activated PC, i.e., APC, that may be present in the blood.
The use of polyclonal antisera to measure PC activity also was described by Exner et al., J. Lab. Clin. Med., 107:405-411 (1986). PC was captured on immobilized antisera, activated, and then reacted with a chromogenic substrate. The assay does not detect the level of APC actually present in a blood sample.
Thus, while functional assays to detect PC in the blood and to detect APC in blood infused with APC are known, there remains a need for sensitive assays to accurately detect whether an active protease such as APC is present in a body fluid sample and, if present, to quantitate its presence.

Assay methods for detecting serum proteases, particularly activated protein C


A management computer collects a usage condition of a volume from a host computer and a storage apparatus at each site, consolidates management thereof, and prevents a volume from duplicating among applications as a copy source. This makes it possible to select a used volume in an application as a copy source without excess or deficiency and to create a copy pair configuration definition without duplication or incompatibility. If a replication environment is constructed in a large-scale storage system, the consolidated management of a usage condition of a volume collected from the host computer and the storage apparatus at each site makes it possible to create a copy pair configuration definition by a task constituted by a plurality of applications.

1. Field of the Invention
The present invention relates to a method of constructing a replication environment in which a copy pair of a volume used by a group constituted by a plurality of applications is created in a storage system including a host computer, a storage apparatus, and a management computer; and to the storage system.
2. Description of the Related Art
Along with a wide spread of information systems, an amount of data handled by computing systems has been increased explosively. Importance of the handled data has also grown drastically. A high-level reliability in protecting such data has been required. Thus, a system of disaster recovery (DR) which can protect data from a logic failure (system failure) and a physical disaster has increasingly become important.
In the DR system, data can be duplicated by storing data outputted from a host computer which performs a task, not only in a volume in a storage apparatus directly connected to the host computer but also in a volume of another storage apparatus.
Typically, so-called local copy and remote copy are used in an information system which requires a high-level reliability. The local copy refers to a copying in which a data in a volume in a storage apparatus is copied in another volume of the same storage apparatus. The remote copy refers to a copying in which a data in a volume in a storage apparatus is copied in a volume in another storage apparatus. The local copy and the remote copy are collectively referred to as a replication. With a technique of the replication, if a volume has any trouble and cannot perform its operations, another volume can take over them using a duplicated data stored therein. Two volumes as a copy source and a copy destination in a replication relationship are collectively called a copy pair.
A replication is typically performed by selecting a volume used by an application desired to be copied, as a copy source, and selecting a volume having a free space sufficient to newly create a copy from the copy source, as a copy destination. This operation creates a configuration definition of a copy pair. A remote copy is performed by, as a preliminary operation, executing an initial copy based on information on the copy pair configuration definition prepared as described above. The initial copy means a copying of all data in the copy source volume into the copy destination volume. After executing the initial copy, an update copy is performed to the copy destination volume each time the host computer provides write data to the copy source volume. If a storage system as a copy source has any trouble, a task in the copy source volume can be restored using the copy destination volume in a storage system as a copy destination.
Japanese Laid-Open Patent Application, Publication No. 2005-11311 discloses a technique of creating a copy pair configuration definition by specifying an application as a copy source, in a storage system including a plurality of host computers and a plurality of storage apparatuses.
In Japanese Laid-Open Patent Application, Publication No. 2005-11311, a resource at a copy destination (a secondary computer resource) is selected based on at least a set of user-specified policy. The policy used herein includes characteristics (for example, reliability) of a secondary computer resource and a cost thereof. Nevertheless, such a selection does not give sufficient consideration to a task executed in the host computer.
A problem in constructing a DR system is an environment construction of a replication by a task as a unit. This is because, if a task is constituted by a group configured by a plurality of applications, protection of one or more specific applications alone is not sufficient to carry on the task. Such a task may be constituted by a plurality of associated applications, or a specific application in the task may have a cluster configuration.
The present invention has been made in an attempt to solve the aforementioned problems. The present invention provides a method of constructing a replication environment in which a copy pair of a volume used by a group constituted by a plurality of applications in a storage system is created, and the storage system.

Method of constructing replication environment and storage system


An electric vehicle may include a battery system with a plurality of battery packs electrically connected together. Each battery pack of the plurality of battery packs may include a plurality of battery cells. The electric vehicle may also include a cooling system configured to cool the plurality of battery packs. The electric vehicle may further include a control system configured to selectively operate the cooling system such that at least one battery pack of the plurality of battery packs is maintained at a temperature different from another battery pack of the plurality of battery packs.

An electric vehicle (EV), also referred to as an electric drive vehicle, uses an electric motor for propulsion. Electric vehicles may include all-electric vehicles where the electric motor is the sole source of power, and hybrid electric vehicles that include an auxiliary power source in addition to the electric motor. In an electric vehicle, energy is stored in a battery system located in the electric vehicle. Typically, the battery system for an electric vehicle includes multiple batteries connected together. To power the electric motor and other electrical accessories of the electric vehicle, energy is discharged from the battery system. When the stored energy decreases, the battery system is charged (or recharged) by connecting the vehicle to an external or auxiliary power supply. The amount of current that may be directed into the battery system during charging, and drawn out of the battery system during discharging, depends on the specific operating conditions (e.g., temperature) of the battery system. By cooling or heating a battery relative to another battery of the battery system, the amount of current that can flow into, or from, the battery can be varied. By selectively cooling the batteries of the battery system, the current flow through the battery system can be balanced. Balanced current flow increases battery life and vehicle performance.


Various embodiments of this disclosure may describe a bandpass sigma-delta modulator (BP ΣΔM) comprising an electromechanical filter, a quantizer coupled to the electromechanical filter, and a feedback circuit coupled between the quantizer and the electromechanical filter. Other embodiments be also be disclosed or claimed.

In Intermediate Frequency (IF) digitization receivers, digitization is typically performed by bandpass sigma-delta modulators (BP ΣΔMs). BP ΣΔMs can be realized in both discrete- and continuous-time (DT and CT) domains. DT BP ΣΔMs refer to the ΣΔMs implemented using switched-capacitor (SC) loop filters, while CT BP ΣΔMs are realized using active-RC, transconductor-C (Gm-C) or LC filter.
DT BP ΣΔMs realized using switch-capacitor circuits cannot operate at high speed, while the CT BP ΣΔMs based on active-RC, Gm-C and LC filters suffer from process and temperature variation (PTV) and cannot achieve satisfactory performance, especially when implemented in CMOS/BiCMOS process.
Further, although some CT BP ΣΔMs have achieved reasonably good performance at high IF, they are implemented in costly III-V processes and consume significant power as seen in the CT BP ΣΔMs disclosed in "High Dynamic Range InP HBT Delta-Sigma Analog-to-Digital Converters," IEEE Journal of Solid-State Circuits, Vol. 38, No. 9, pp. 1524-1532, September 2003 " by M. Inerfield, et al. and "IF-Sampling Fourth-Order Bandpass ΣΔ Modulator for Digital Receiver Applications," IEEE Journal of Solid-State Circuits, Vol. 39, No. 10, pp. 1633-1639, October 2004″ by A. E. Cosand, et al. High-performance CT BP ΣΔMs in CMOS/BiCMOS technology at high IF have yet to materialize.
BP ΣΔMs based on electromechanical resonators have been proposed recently in [Y. P. Xu, R. Yu, W. T. Hsu and A. R. Brown, "A Silicon Micromechanical Resonator Based CMOS Bandpass Sigma-Delta Modulator," in Proc. of Asian Solid-State Circuit Conference (A-SSCC'06), November 2006. pp. 143-146; R. Yu, Y.P. Xu, "A 47.3-MHz SAW Resonator Based CMOS Second-Order Bandpass Sigma-Delta Modulator with 54-dB Peak SNDR," in Proc. IEEE Custom Integrated Circuits Conf. (CICC'05, pp. 203-206, September 2005]. These BP ΣΔMs achieve comparable or better SNDR (Signal to Noise plus Distortion Ratio) performances in narrowband (200 kHz) FM application, but are more suitable for narrowband applications. Although multiple resonators with different center frequencies can be used to achieve a wider passband in a higher-order loop filter, they are difficult to realize in practice due to the increased parasitics and complexity.
Therefore, there exists a need to provide a system and method for a bandpass sigma-delta modulator to address one or more of the problems mentioned above.

System and method for bandpass sigma-delta modulation


A multipath wireless communication is processed to recover a transmitted data signal without performing a direct matrix inversion (DMI). First, the multipath wireless communication is received. Then HHH and HHH values associated with the multipath wireless communication are determined. Weights based on HHH and HHH associated with the received data signal may then be determined and used to recover the transmitted data signal from the received multipath wireless communication.

Communication systems are known to support wireless and wire lined communications between wireless and/or wire lined communication devices. Such communication systems range from national and/or international cellular telephone systems, to the Internet, and to point-to-point in-home wireless networks. Each type of communication system is constructed, and hence operates, in accordance with one or more communication standards. For instance, wireless communication systems may operate in accordance with one or more standards including, but not limited to, IEEE 802.11, Bluetooth, advanced mobile phone services (AMPS), digital AMPS, global system for mobile communications (GSM), code division multiple access (CDMA), local multi-point distribution systems (LMDS), multi-channel-multi-point distribution systems (MMDS), and/or variations thereof.
Depending on the type of wireless communication system, a wireless communication device, such as a cellular telephone, two-way radio, personal digital assistant (PDA), personal computer (PC), laptop computer, home entertainment equipment, et cetera communicates directly or indirectly with other wireless communication devices. For direct communications (also known as point-to-point communications), the participating wireless communication devices tune their receivers and transmitters to the same channel or channels (e.g., one of the plurality of radio frequency (RF) carriers of the wireless communication system) and communicate over that channel(s). For indirect wireless communications, each wireless communication device communicates directly with an associated base station (e.g., for cellular services) and/or an associated access point (e.g., for an in-home or in-building wireless network) via an assigned channel. To complete a communication connection between the wireless communication devices, the associated base stations and/or associated access points communicate with each other directly, via a system controller, via the public switch telephone network, via the Internet, and/or via some other wide area network.
Direct or indirect communications may experience be received via multiple pathways. Multiple pathways often result in the deflection of a wireless communications signals off obstacles that can cause interference during reception. Multipath fading occurs when a wireless communications signal is received by an antenna and later the same signal is received again, reflected from an obstacle. This can result from both retransmission and different transmission paths. Under certain conditions, two or more of the signals can interfere with each other and create "fading" (a loss of signal) in the communications link. Fading may occur when signals are retransmitted or received by multiple antennas. Thus, multipath fading may be observed within both wireless and wire-line communications. As the amount of data contained within wireless and wire-line communications increase and the power of the transmitted signal is reduced, the techniques chosen to combat the multipath fading can vary.
Previously, least mean square (LMS) algorithms have been employed to avoid matrix inversion when trying to find the optimum solution to mitigate inter-symbol interference (ISI) or inter-chip interference (ICI). On CDMA downlink, there is strong ICI due to multipaths. To date, adaptive LMS algorithms have been applied to reduce ICI without multipath channel matrix inversion. However, this method produces a biased signal which is not desirable.
Further limitations and disadvantages of conventional and traditional matrix inversion processes or processes used to avoid matrix inversion will become apparent to one of ordinary skill in the art through comparison with the present invention described herein.

Adaptive unbiased least square (LS) algorithm for mitigating interference for CDMA down link and other applications


A method and system is disclosed for enabling quantities of bulk-type products to be determined using RFID tags that can also be used to determine the existence of product or packaging containing RFID tags. Packaging and/or containers for the bulk products are configured so that the RFID tags contained thereon provide an indication of an approximate relative quantity of the bulk material. More specifically, the position and/or shielded or unshielded state of RFID tags are utilized to identify a quantity of the bulk-type material.

1. Field of the Invention
The present invention relates in general to radio frequency identification tags, and more particularly, to the use of RFID tags to track quantities of loose materials or items.
2. Description of the Related Art
Radio frequency identification (RFID) technology tags are devices that are affixed to various articles so that these articles may be easily tracked during movement from one point to another, or identified through a sales transaction. Any type of object, including assets, animals, and people can be tagged so that they may be identified or tracked automatically via a reader, which is typically connected to a host computer that may contain additional data related to an object's identification number associated with the RFID tag. In addition, RFID tags generally contain program information about an object to which it is attached. Through the use of such information, RFID technology may be used to identify objects automatically and without manual handling operations as is required in most bar code systems.
The operation of typical RFID tagging systems is well known and is not described in detail herein. Many examples describing the operation of such systems can be found, for example, U.S. Pat. No. 5,822,714 assigned to International Business Machines Corporation, the contents of which are incorporated by reference herein.
With the proliferation of RFID tags on products, it is not surprising that their existence on products was leveraged for use outside of the retail establishment from which they were sold. RFID tags were originally designed to assist merchants in tracking inventory within the store and in processing the sale of the merchandise at the check out counter. However, savvy consumers quickly realized that they could also use the existence of the RFID tags in products that they purchased to, for example, keep an electronic inventory of food products, staples, etc. within the kitchen or elsewhere in the home. For example, the same technology used to monitor the existence of products in the store can now be used to monitor the existence of products in the home.
However, a problem exists when an item is of a type that is not consumed all at once and that contains bulk or loose quantities of the product. For example, items such as cereal, flour, sugar and the like will typically be used over a period of days or weeks, and existing RFID tag systems will merely provide the consumer with information regarding the existence or non-existence of the packaging containing the bulk item. Thus, for example, to a consumer, a full, unopened box of cereal will look identical to an almost completely empty box of cereal, i.e., in both cases, the consumer will only know that there is a box of the cereal in the pantry but will not be aware of the quantity of cereal within the box. Accordingly, it would be desirable to have a method and system for monitoring quantities of bulk-type items using RFID tags.

Packaging incorporating volume-measurement capability using RFID tags


A wire bonding apparatus equipped with a capillary through which a wire is passed, a torch electrode which is installed in a substantially horizontally movable manner so as to be positioned beneath the capillary, and a torch electrode driver which drives the torch electrode, in which the torch electrode is directly coupled to an output shaft of a pulse motor which is driven by a high-resolution angle control circuit, so that a resolution of the pulse motor obtained by the high-resolution angle control circuit is 30,000 parts per revolution or greater.

1. Field of the Invention
The present invention relates to a wire bonding apparatus, and more particularly, to a wire bonding apparatus that is equipped with a movable torch electrode.
2. Prior Art
In a movable torch electrode system, the torch electrode is installed so that it can move horizontally. The torch electrode is positioned beneath the tip end of the wire extending from the tip end of the capillary and is caused to discharge so as to form a ball on the tip end of the wire. Following this ball formation, the torch electrode is retracted from beneath the capillary.
Japanese Patent Application Publication (Kokoku) No. H1-58861 and Japanese Patent Application Laid-Open (Kokai) No. H9-205110 disclose bonding apparatuses equipped with movable torch electrodes of the type described above.
In Japanese Patent Application Publication (Kokoku) No. H1-58861, a metal electrode is formed at the tip end of the capillary, so that an electrical arc can be produced between the metal electrode and the movable torch electrode.
The movable torch electrode system of Japanese Patent Application Laid-Open (Kokai) No. H9-205110 includes an actuator that comprises a lateral actuating arm, a spring, a stopper and a solenoid. The actuating arm is installed so as to be movable in a horizontal direction, and a torch electrode is attached to this actuating arm. The spring pulls the lateral actuating arm toward the area beneath the capillary. The stopper positions the lateral actuating arm beneath the capillary, and the solenoid drives the lateral actuating arm so that the torch electrode is retracted from beneath the capillary.
When the solenoid is switched on, the lateral actuating arm is pulled by the magnetic force of the solenoid so that the torch electrode is retracted from beneath the capillary. When the solenoid is switched off, the lateral actuating and is caused to move beneath the capillary by the driving force of the spring, and it stops when the torch electrode contacts the stopper.
In the prior art described above, the torch electrode is stopped by way of causing the electrode to come into contact with a stopper. However, this leads to noise and causes dust as a result of wear. Furthermore, since the range of movement of the torch electrode is limited by the solenoid and stopper, there is no degree of freedom in the position of the torch electrode, and the torch electrode constitutes an obstacle. Thus, the working characteristics of wire threading, capillary replacement, etc. tend to be poor. Moreover, since driving is accomplished by a spring and solenoid, the speed of the apparatus cannot be increased.
Accordingly, the inventors of the present application invented a wire bonding apparatus in which the torch electrode is directly coupled to the output shaft of a pulse motor (Japanese Patent Application No. H11-35283). This wire bonding apparatus is superior in terms of quiet operation and in terms of working characteristics since the movement range of the torch electrode has a high degree of freedom. Also, it can increase the speed of the apparatus. However, in conventional pulse motor control methods, vibration of the torch electrode occurs with each pulse, and the residual vibration at the time of stopping is especially violent.
Accordingly, the object of the present invention is to provide a wire bonding apparatus that can minimize vibration of torch electrode and that is quiet in operation, has excellent working characteristics with high movement range of the torch electrode, and can increase the speed of the bonding apparatus.
The above object is accomplished by a unique structure of the present invention for a wire bonding apparatus which is equipped with a capillary through which a wire is passed, a torch electrode which is installed in a substantially horizontally movable manner so that the torch electrode is positioned beneath the capillary, and a torch electrode driving means which drives the torch electrode; and in the present invention, the torch electrode is directly coupled to the output shaft of a pulse motor, and this pulse motor is driven by a high-resolution angle control circuit.
In the above structure of the present invention, the resolution of the pulse motor obtained by the high-resolution angle control circuit is 30,000 parts per revolution or greater.


A femoral orthopaedic surgical instrument includes a posterior femoral trial having a cutting guide defined therein and an anterior femoral trial removably coupled to the posterior femoral trial. The anterior femoral trial may also include a cutting guide defined therein. The femoral orthopaedic surgical instrument may also include a base block couplable to the posterior femoral trial in place of the anterior femoral trial. A plurality of additional orthopaedic instruments may be coupled to the base block.

Joint arthroplasty is a well-known surgical procedure by which a diseased and/or damaged natural joint is replaced by a prosthetic joint. A typical knee prosthesis includes a tibial tray, a femoral component, and a polymer insert or bearing positioned between the tibial tray and the femoral component. The femoral component generally includes a pair of spaced apart condylar portions, the surfaces of which articulate with corresponding surfaces of the polymer bearing.
The femoral component is configured to be coupled to a surgically-prepared distal end of a patient's femur. The femur is surgically-prepared during an orthopaedic surgical procedure performed by an orthopaedic surgeon. During the orthopaedic surgical procedure, the orthopaedic surgeon typically uses a number of separate orthopaedic surgical instruments such as, for example, a femoral anterior cutting block, an femoral augment cutting block, and a femoral trial.

Modular femoral orthopaedic surgical instrument


A parallel calibration system for an electronic circuit tester comprises test and measurement electronics, a test fixture coupled to the test and measurement electronics, the test fixture comprising clock reference circuitry and clock distribution circuitry, a device under test interface, and a plurality of calibration boards coupled to the device under test interface, wherein the plurality of calibration boards and the clock distribution circuitry simultaneously test the signal paths of a plurality of test channels.

Many device testing applications, such as test applications for memory devices, require a test device capable of simultaneously testing many devices having multiple test channels. Such a test device typically requires periodic calibration to, among other items, calibrate various clock and data paths through the test device so that the test device delivers meaningful test results. Modem test devices are capable of testing many devices, and therefore have many, in some cases thousands, of test channels.
A typical electronic circuit test device tests a device under test (DUT) by applying test signals of various logic states to input terminals on the DUT. The states of the signals that are produced at the output terminals of the DUT in response to the applied test signals are monitored to determine whether the DUT is behaving predictably.
An electronic circuit tester must maintain extremely accurate tolerances so that the performance of the DUT may be characterized accurately. Previous testing devices were manually calibrated using external measurement instrumentation. Other prior testing devices used a single calibration clock reference to calibrate all channels of the test device. Unfortunately, this requires that each channel of the test device be serially calibrated, thus requiring an undue amount of time to calibrate a test device having many hundreds or thousands of channels.
Accordingly, a need exists for a way of reducing the amount of time required to calibrate a test device.

Parallel calibration system for a test device