A DRAM according to the present invention comprises a memory cell array having memory cells constituted by one transfer gate transistor (10) and a capacitor (11), and a peripheral circuit having a MOS transistor (45a) with the LDD structure. At least the source/drain region (19) connected to the capacitor of the transfer gate transistor is formed of a low concentration impurity region (19a). The low concentration impurity region has an impurity concentration substantially equal to that of the low concentration source/drain region (31) of the LDD MOS transistor of the peripheral circuit. The low concentration/drain region of the transfer gate transistor is formed by masking the surface thereof at the time of the high concentration ion implantation step for high concentration source/drain formation of the MOS transistor of the peripheral circuit. By omitting the high concentration ion implantation step, the substrate deficiency of the source/drain region of the transfer gate transistor is eliminated to suppress leakage of the charge from the capacitor.

With reference to the block diagram of FIG. 13, the circuit structure of a general dynamic type semiconductor memory will be explained hereinafter. The DRAM comprises, a memory cell array 1 having a plurality of memory cells storing unit memory information arranged in a matrix manner. It further comprises, as peripheral circuitry, a row-and-column address buffer 2 for receiving externally applied address signals (A.sub.0 -A.sub.9 ; in case of lMbit) for selecting a memory cell, a row decoder 3 and a column decoder 4 for specifying a memory cell by decoding the address signal, a sense refresh amplifier 5 for amplifying and reading out the signal stored in the specified memory cell, a data-in buffer 6 and a data-out buffer 7 for data input/output, and a clock generator 8 for generating clock signals .PHI.1 and .PHI.2. Clock generator 8 is implemented so as to receive row address strobe signal RAS and column address strobe signal CAS applied externally.
FIG. 14 is an equivalent circuit diagram of a memory cell forming memory cell array 1. Memory cell 9 is formed of one transfer gate transistor 10 and one capacitor 11. The gate electrode of transfer gate transistor 10 is connected to a word line 12, while one of the source/drain region is connected to a bit line 13, and the other connected to one electrode of a capacitor 11.
The DRAM stores data according to the presence or absence of a signal charge in the capacitor of the memory cell. The determination of the presence or absence of data is made by specifying each word line to select a memory cell, reading out from the bit line a small signal responsive to the presence or absence of a signal charge in the capacitor of the selected memory cell, and amplifying the same by an sense amplifier. The signal charge stored in the memory cell capacitor dissipates due to disturbance such as by leakage currents after some time passes. It will be necessary to update the stored information in each memory cell periodically in order to keep storing the data. The circuit operation for this purpose is called the refresh operation. More specifically, with reference to FIGS. 13 and 14, refresh operation is carried out by amplifying the small signal from the memory cell with a sense amplifier provided corresponding to each bit line, after selecting a word line to activate the memory cells connected to that word line, and returning the same to the memory cell. By executing the above mentioned refresh operation with respect to all word lines changing the row address sequentially, all information within the memory cell array is updated. It is necessary to repeat the refresh operation at a period shorter than the time period in which the signal charge is held in the memory cell. The shorter the hold time of the signal charge is, the greater the number of refresh operations, the so-called refresh division number.
FIG. 15 shows a sectional view of memory cell 9 of FIG. 14. Referring to FIG. 15, a thick field oxide film 15 for device isolation is formed on the surface of a semiconductor substrate 14. On the surface of semiconductor substrate 14 enclosed by field oxide film 15, transfer gate transistor 10 and capacitor 11 are formed.
Transfer gate transistor 10 is provided with a gate electrode (word line) 12 formed above the surface of semiconductor substrate 14 with a gate oxide film 16 therebetween. The circumference of gate electrode 12 is covered by a silicon oxide film 17 for insulation. Particularly, silicon oxide film 17 formed at the sides of gate electrode 12 is implemented with the so-called sidewall structure. Within semiconductor substrate 14, n.sup.- impurity regions 18a and 19a of low concentration are formed in a position self-aligning gate electrode 12. Also, n.sup.+ impurity regions 18b and 19b of high concentration are formed at a position self-aligning the sidewalls of silicon oxide film 17. The so-called LDD (Lightly Doped Drain) structure is formed by these n.sup.- impurity regions 18a and 19a and n+ impurity regions 18b and 19b. The impurity regions of this LDD structure become source/drain regions 18 and 19.
Capacitor 11 has a stacked structure constituted by a lower electrode 20 having impurities doped, a dielectric film 21 formed by silicon nitride film, silicon oxide film, or a multilayer film such as of silicon nitride film and silicon oxide film, and an upper electrode 22 formed of polysilicon having impurities doped. Capacitor 11 has the lower electrode 20 formed above gate electrode 12 of transfer gate transistor 10. A portion of lower electrode 20 is connected to one n+ source/drain region 19b of transfer gate transistor 10. Such a capacitor 11 having a structure in which a portion is formed over transfer gate transistor 10 is called a stacked capacitor, while DRAMs including such capacitors are called stacked type DRAMs.
Although not shown, MOS (Metal Oxide Semiconductor) transistors having the above mentioned LDD structure are used in the peripheral circuit.
The effect of the LDD structure of a MOS transistor will be explained hereinafter. The employment of LDD structure was due to advancement in high integration of DRAMs. The minute structure of MOS transistors associated with the high integration of DRAMs induced short channel effect, resulting in various problems. The electric field intensity in the channel region was increased because of the short channel, to generate hot carriers in the vicinity of the drain. This is trapped within the gate oxide film and generates surface level. This causes deterioration in characteristics such as threshold value voltage change and decrease of mutual conductance. A LDD structure with the n.sup.- impurity region of low concentration and n.sup.+ impurity region of high concentration formed offset was proposed to prevent change in characteristics caused by hot carriers. The n.sup.- impurity region of low concentration in the LDD structure decreases the electric field intensity to suppress the generation of hot carriers by reducing the junction grade of the pn junction. It is required that this n.sup.- impurity region of low concentration controls the diffusion width and impurity concentration precisely.
With reference to FIGS. 16A-16I, the manufacturing process of a DRAM will be explained. Such a DRAM manufacturing process is shown in Japanese Patent Application Laying-Open 63-44756, for example. For convenience of description, memory cell 9 and the CMOS transistor (complementary MOS: referred to as CMOS hereinafter) implementing a portion of the peripheral circuit is taken as an example.
As shown in FIG. 16A, field oxide film 15 is formed on the surface of semiconductor substrate 14 by LOCOS (Local Oxidation of Silicon) method. In the peripheral circuit region of semiconductor substrate 14, a p well region 23 and a n well region 24 for n channel MOS (referred to as nMOS hereinafter) and p channel MOS (referred to as pMOS hereinafter) formation implementing a CMOS are formed in advance.
As shown in FIG. 16B, a thin silicon oxide film and polysilicon layer are formed in sequence on the surface of semiconductor substrate 14. On the surface of the polysilicon layer, oxide films 17 and 27 are formed. Then, a predetermined shape is patterned using lithography and etching method. Thus, nMOS gate oxide film 16 implementing a memory cell, gate electrode 12, nMOS and pMOS gate oxide films 25a and 25b forming the peripheral circuit, and gate electrodes 26a and 26b are formed.
After a resist 29a covers the pMOS region of the peripheral circuit, phosphorus (P) ions or arsenic (As) ions 30a of low concentration are implanted onto the surface of the substrate. This ion implanting step causes n- impurity regions 18a and 19a of the transfer gate transistor 10 of the memory cell and n.sup.- impurity region 31 of the nMOS transistor of the peripheral circuit to be formed.
After an oxide film is deposited all over the substrate, this oxide film is etched anisotropically, as shown in FIG. 16D. This forms sidewalls 17a and 27a of oxide films at the sidewalls of gate electrode 12 of the transfer gate transistor 10 and gate electrode 26a of the peripheral circuit's nMOS transistor.
Using these sidewalls 17 and 27a of oxide film, n impurity ions 30b such as arsenic (As) or phosphorus (P) of high concentration are implanted onto the surface of the substrate. By this ion implantation, n+ impurity regions 18b and 19b of transfer gate transistor 10 and n.sup.+ impurity region 33 of the nMOS transistor of the peripheral circuit are formed.
According to the above mentioned steps, the LDD structure of transfer gate transistor 10 of the memory cell and the LDD structure of the nMOS transistor of the peripheral circuit are implemented.
As shown in FIG. 16E, a resist 29b covers the surface of the memory cell and the nMOS transistor region of the peripheral circuit, followed by implanting p type impurity ions 32 of high concentration such as boron (B, BF.sub.2) onto the surface of the substrate through sidewalls 27a of gate electrode 26b. By this ion implanting step, p.sup.+ impurity regions 35 and 35 of pMOS transistor are formed. Thus, the pMOS transistor of the peripheral circuit is formed by the above mentioned steps.
Next, the manufacturing steps of capacitor 11 of the memory cell will be explained. As shown in FIG. 16F, after an interlayer film 41 is deposited using CVD (Chemical Vapor Deposition) method on the surface of the substrate in which gate electrodes and the like of the transistor are formed, interlayer film 41 is patterned using lithography and etching method to form a contact region connecting lower electrode 20 of the capacitor with the substrate.
Then, as shown in FIG. 16G, polysilicon is deposited using CVD method. It is necessary to dope n type impurities for polysilicon to possess electrical conductivity. This is implemented by doping with gas such as phosphine (PH.sub.3) at the time of the CVD step, or by implanting and driving-in phosphorus (P) or arsenic (As) using ion implanting method after the deposition of polysilicon or after a predetermined patterning. Then, lower electrode 20 of capacitor 11 is formed by patterning this polysilicon layer.
As shown in FIG. 16H, a capacitor dielectric film 21 formed of silicon nitride film, silicon oxide film, or a composite film of these is formed using the CVD method. A doped polysilicon layer 22 is deposited thereof using CVD method. Then, patterning of a predetermined shape is carried out using photolithography and etching method. Thus, capacitor 11 is formed.
As shown in FIG. 16I, interlayer insulating film 40 is formed above the surface of the substrate where devices such as transistors and capacitors are formed, followed by opening a predetermined region to form bit line 13.
After the formation of a second interlayer insulating film 42, a predetermined region is opened to form a wiring layer 43.
Thus, a DRAM is manufactured comprising a transistor having the LDD structure, in accordance with the above mentioned steps.
As set forth throughout the above description, transfer gate transistor 10 of the memory cell in a conventional DRAM has source/drain regions 18 and 19 of the LDD structure formed by ion implantation. When n+ impurity regions 18b and 19b of high concentration are formed by ion implanting method, many crystal deficiencies are generated on the surface of the semiconductor substrate 14. The crystal deficiencies are recovered to some extent by a later heat processing for activation, but not completely. In the case where lower electrode 20 of capacitor 11 is formed over source/drain region 19 where crystal deficiencies remain, signal charge stored in capacitor 11 passes through the crystal deficiencies within source/drain region 19 flowing to the substrate side to generate leakage currents. Due to the reduction in capacitor capacitance associated with the miniaturization of the device structure in recent years, the disappearance of signal charge by leakage currents from the capacitor became a large problem. Therefore, the hold time of signal charge stored in memory cells becomes shorter, leading to problems such as the need to increase the number of refresh operations.
There was also a problem of poor contact between substrate 14 and bit line 13 or lower electrode 20 of capacitor 11. This was ascribed to multiple oxidization of incidental oxide film by impurity effect, generated on the surface of semiconductor substrate 14 where impurity regions 18b and 19b of high concentration are formed, caused by air entering the CUD chamber when the semiconductor is introduced into the chamber.
An approach to suppress the occurrence of leakage currents from the capacitor is shown in Japanese Patent Laying-Open No. 64-80065. FIG. 17 is a sectional structure view of the DRAM shown in the above mentioned laid-open application. Referring to FIG. 17, a sectional structure of a memory cell array and the peripheral circuit devices are shown. On p type silicon substrate 14, p well region 14a and n well region 14b are formed. The memory cell array and nMOS transistor 100 of the peripheral circuit are formed in p well region 14a, whereas pMOS transistor 110 is formed in n well region 14b. The memory cell constituting the memory cell array is constructed of one transfer gate transistor 10 and one capacitor 11, similar to the memory cell of FIG. 15. Comparing the structures of the second conventional memory cell of FIG. 17 and the first conventional memory cell of FIG. 15, the transfer gate transistor 10 of the second conventional memory cell has the so-called LDD structure with n.sup.- impurity region 19a of low concentration formed by ion implantation of source/drain region 19 of the side connected to capacitor 11 and n.sup.+ impurity region 19b of high concentration formed by impurity heat diffusion from lower electrode 20 of capacitor 11. The source/drain region 18 of the side connected to bit line 13 has the LDD structure with n.sup.- impurity region 18a of low concentration formed by ion implantation and n.sup.+ impurity region 18b of high concentration formed also by ion implantation. The transfer gate transistor 10 of this example suppresses the generation of crystal deficiency in the surface of the substrate by ion implantation to decrease the generation of leakage currents from the capacitor, by forming high concentration impurity region 19b without using the ion implantation method over source/drain region 19 of the side connected to the capacitor.
Bit line 13 is constituted by a three layer structure stacking a barrier metal layer 13a, an aluminum layer 13b, and a protection film 13c in sequence. Barrier metal layer 13a is formed of a refractory metal silicide layer , such as MoSi.sub.2 or the like and a refractory metal layer to prevent monocrystal silicon from being precipitated in the contact between aluminum layer 13b and source/drain region 18.
On the right hand of FIG. 17, a sectional structure view of a CMOS implementing the peripheral circuit is shown. The nMOS transistor 100 of the CMOS is constructed of a gate insulating film 101, a gate electrode 102, and a pair of source/drain regions 103 and 104. Each of source/drain regions 103 and 104 have a LDD structure formed of n.sup.- impurity regions 103a and 104a of low concentration and n.sup.+ impurity regions 103b and 104b of high concentration. On source/drain regions 103 and 104, n.sup.+ impurity regions 103c and 104c are formed. The n impurity regions 103c and 104c are provided for the purpose of preventing source/drain regions 103 and 104 from shorting with wiring layers 105 and 105.
The pMOS transistor 110 of the CMOS is implemented by a gate insulating film 111, a gate electrode 112, and a pair of source/drain regions 113 and 114. Each of source/drain regions 113 and 114 has a LDD structure with p impurity regions 113a and 114a of low concentration and p.sup.+ impurity regions 113b and 114b of high concentration.
The main steps of manufacturing the source/drain region of the transfer gate transistor of the memory cell, which is a feature of the conventional example will be explained hereinafter. FIGS. 18A-18D are sectional views illustrating the main manufacturing steps of the DRAM of FIG. 17.
FIG. 18A shows the ion implanting steps for forming sources/drains of transfer gate transistor 10 of the memory cell and nMOS transistor 100 of the peripheral circuit. Referring to FIG. 18A, a resist 120 covers the formation region of pMOS transistor 110, followed by ion implantation of phosphorus (P) or arsenic (As) under the conditions of dosage of 10.sup.13 /cm.sup.2, and implant energy of 60-120 keV. This results in the formation of n impurity regions 18a and 19a of low concentration of transfer gate transistor 10 and n impurity regions 103a and 104a of nMOS transistor 100.
Referring to FIG. 18B, resist 120 is removed, and resist 121 covers the memory cell array and nMOS transistor 100 formation region of the peripheral circuit. Then, ion implantation of BF.sub.2 or B is carried out onto p type semiconductor substrate 14 with a dosage of 10.sup.13 /cm.sup.2 and implant energy of 60-100 keV. This results in the formation of p impurity regions 113a and 114a of low concentration of pMOS transistor 110.
With reference to FIG. 18C, the formation step of high concentration impurity region of transfer gate transistor 10 will be described hereinafter. On the surface of n.sup.- impurity region 19a of transfer gate transistor 10, lower electrode 20 of capacitor 11 is formed. Ion implantation of arsenic or phosphorus is carried out onto lower electrode 20 of capacitor 11 with a dosage of 10.sup.153 /cm.sup.2 and implant energy of 75-85 keV. Then, the n type impurities introduced into lower electrode 20 are diffused to the surface of p type silicon substrate 14 by heat processing. This diffusion step causes n+ impurity region 19b of high concentration of source/drain region 19 to be formed.
FIG. 18D shows the formation step of the high concentration region of source/drain region 18 of the transfer gate transistor. In the memory cell array, interlayer insulating layer 122 is formed above the memory cell. Interlayer insulating layer 122 has a contact hole 123 formed contacting source/drain region 18 of transfer gate transistor 10. Under this state, resist 124 covers the formation region of pMOS transistor 110 of the peripheral circuit. Then, arsenic ions are implanted into the surface of p type silicon substrate 14 at a dosage of 10.sup.15 /cm.sup.2 and implant energy of 110-130 keV. This results in the formation of n.sup.+ impurity region 18b of high concentration of source/drain region 18 of transfer gate transistor 10. Simultaneously, n.sup.+ impurity regions 103c and 104c of high concentration are formed in nMOS transistor 100 of the peripheral circuit.
Thus, in the second conventional DRAM, the source/drain region 19 of the side connected to the capacitor of transfer gate transistor 10 is constituted by a LDD structure with n.sup.- impurity region 19a of low concentration by ion implantation and n.sup.+ impurity region 19b of high concentration by heat diffusion. The source/drain region 18 of the side connected to bit line 13 is implemented by a LDD structure with n.sup.- impurity region 18a of low concentration also by ion implantation and n.sup.+ impurity region 18b of high concentration also by ion implantation.
In the above mentioned second conventional example, a method is proposed where high concentration region of source/drain region of the transfer gate transistor is formed by heat diffusion from the lower electrode of the capacitor, for the purpose of suppressing the generation of leakage currents from the capacitor caused by deficiency of the surface of the substrate due to high concentration ion implantation. However, the deleterious effect of high temperature heat processing becomes significant in proportion to the increase of the DRAM's stored capacitance such as to 16 Mb or 64 Mb, and is not preferable. That is to say, miniaturization in the structure of a memory cell array is required to increase the integration density of DRAMs. As a result, the channel length of transfer gate transistor 10 of the memory cell is minimized. If source/drain regions 18 and 19 are formed using heating process of high temperature, as in the above-mentioned second conventional embodiment, under such circumstances impurities are diffused into the channel region of transfer gate transistor 10 which results in significant short channel effect. This short channel effect will cause deterioration in the characteristics of the transistor, such as reduction in reliability lifetime of transfer gate transistor 10. Therefore, the recent technical developments in the manufacturing methods of DRAMs are carried out to shift from high temperature processes to low temperature processes. The conventional method of forming a source/drain region of high concentration in a transfer gate transistor by thermal diffusion causes short channel effect in the MOS transistor of a DRAM to impede increase in integration density of a DRAM.
In the second conventional example, n.sup.+ impurity region 18b of high concentration is formed by ion implantation on the source/drain region 18 of the side connected to the bit line. This promotes the generation of incidental oxide film as stated before, leading to a problem of preventing efficient ohmic contact between the bit line and source/drain region 18.

DRAM device comprising a stacked type capacitor and a method of manufacturing thereof


This invention relates to a method for production of nanoscale size quinacridones through a wet-salt attrition process by combining a crude quinacridone pigment in the presence of (i) an inorganic salt, (ii) an organic liquid in which the quinacridone pigment and salt are substantially insoluble, and (iii) a quinacridone derivative in an amount less than 10 wt. % relative to the quinacridone pigment; discharging the ground quinacridone pigment into water; adding an acid to produce a solution pH of 1.5 or lower; and isolating the quinacridone pigment.

Pigments used in ink jet printing applications must be of a small size. The particle size has an influence on the dispersion stability. Further, the Brownian motion of minute particles helps prevent flocculation and settling. The particle size thus should be selected to optimize the stability of the dispersion, consistent with the other requirements of the intended application for the dispersion. In ink jet ink applications, the pigment particles need to be sufficiently small to permit free flow of the ink through the ink jet printing device, especially at the ejecting nozzles which typically have a diameter in the range of 10 to 50 microns. !n addition, it also is desirable to use small particles for maximum color strength and gloss. The useful range of particle size is approximately 0.005 micron to 15 microns. Preferably, the pigment particle size should range from 0.005 to 1 micron. Similarly, the toner utilized in the electrophotographic process is keenly required to have a small particle size pigment for improving its image quality.
As initially produced and isolated, crude quinacridone pigments are generally unsuitable for use in inkjet applications and must be subjected to additional finishing steps that modify the quinacridone pigment particle size, particle shape, and/or crystal structure to provide good pigmentary quality.
Other such uses and applications including but not limited to paints, plastics and toners also require small particle size and good pigment quality.
Thus, there does not exist a process to produce small particle quinacridones having increased transparency and stability in application.

Process for preparing nanoscale quinacridone


A variable valve actuation apparatus for engine cylinder valves comprises a main rocker arm having an end portion for driving association with a cylinder valve. The main rocker arm supports a sub-rocker arm. A lost motion mechanism is between the main rocker and sub-rocker arms. The main rocker arm is formed with a plunger seat. The plunger seat includes a bearing surface on which a plunger of the lost motion mechanism rests. Further, the plunger seat includes gutters for discharging lubricant oil.

U.S. Patent No. 5,297,516, issued on Mar. 29, 1994 discloses a VVA apparatus that employs a main rocker shaft supporting a main rocker arm. The main rocker arm supports a sub-rocker shaft for a sub-rocker arm. A lost motion mechanism disposed between the main rocker arm and the sub-rocker arm is operable unless a lever on the main rocker arm is locking engagement with the sub-rocker arm. The lost motion mechanism includes a spring-biased plunger that rests on an exposed portion of the main rocker shaft. According to this known apparatus, the cylindrical outer peripheral surface of the main rocker shaft serves as a plunger seat and thus the main rocker arm is not formed with any appropriately designed plunger seat for the lost motion mechanism.
An object of the present invention is to improve the variable valve actuation apparatus according to the prior art such that the cylindrical outer peripheral surface of the main rocker shaft is not used as a plunger seat for the lost motion mechanism.


A piezoelectric transducer for sending and receiving an ultrasonic wave and an FPC for applying current to the piezoelectric transducer is provided, the FPC is arranged oppositely to a side face of the piezoelectric transducer, and a soldering material for electrically connecting the piezoelectric transducer to the FPC is arranged in a corner portion formed by the piezoelectric transducer and the FPC.

1. Field of the Invention
The present invention relates to an ultrasonic probe for sending and receiving an ultrasonic wave and a method for fabricating the probe.
2. Description of the Related Art
For example, ultrasonic diagnostic equipment has been used in medical diagnosis or industrial diagnosis, in which a lesion in the body or a crack in piping is detected by sending an ultrasonic wave to a diagnostic object such as the human body or piping and receiving a reflected wave of the ultrasonic wave. The ultrasonic diagnostic equipment comprises a main body of the equipment and an ultrasonic probe for sending and receiving the ultrasonic wave.
FIG. 14 and FIG. 15 show a configuration of a conventional ultrasonic probe of ultrasonic diagnostic equipment for medical application. As shown in FIG. 14, the ultrasonic probe has a piezoelectric transducer 201. The piezoelectric transducer 201 is formed into a rectangular, piezoelectric element by dicing a platelike piezoelectric ceramic.
An audio matching layer 203 for matching audio impedance is provided at an earth electrode 201c side of the piezoelectric transducer 201, and in turn an audio lens 205 is provided on a surface of the audio matching layer 203. A backing material 209 comprising rubber having a good sound absorption performance is jointed to a signal electrode 201b side of the piezoelectric transducer 201 through epoxy based resin 207.
On both side faces of the piezoelectric transducer 201, flexible printed circuits 211 (FPCs) are disposed such that they are opposed to each other. Each of end portions of the FPCs 211 is connected to the signal electrode 201b or earth electrode 201c of the piezoelectric transducer 201 through a soldering material.
As shown in FIG. 15, the FPCs 211 are bended at approximately 90 degrees in the vicinity of the connected portion to the piezoelectric transducer 201, and a rear anchor portions of the FPCs are connected to a main body (not shown) of the ultrasonic diagnostic equipment disposed at a backing material 209 side.
When the ultrasonic probe having the above configuration is used, first an audio lens 205 is contacted to a diagnosis object. Then, an electrical signal is applied to the piezoelectric transducer 201 through the FPCs 211, thereby an ultrasonic wave is generated from the piezoelectric transducer 201. The generated ultrasonic wave is sent to the diagnosis object through the audio lens 205, and reflected within the diagnosis object, and then received by the piezoelectric transducer 201. The received ultrasonic wave is converted to an electric signal in the piezoelectric transducer 201, and transferred to the main body of the ultrasonic diagnostic equipment through the FPCs 211.
In such configured ultrasonic probe, the FPCs 211 are bent at approximately 90 degrees in the vicinity of the jointed portion with the piezoelectric transducer 201. According to the finite deflection theory, bending stress exerted on the curved portions of the FPCs 211 exceeds 100 N/mm2, therefore the jointed portions of the FPCs 211 with the piezoelectric transducer 201 were easily broken due to the bending stress exerted on the curved portions of the FPCs 211. Particularly, in dicing, large machining stress is applied to the jointed portions of the FPCs 211 with the piezoelectric transducer 201, therefore the jointed portions were still further easily broken.
Thus, a configuration in which the FPCs are connected to the piezoelectric transducer without being curved by projecting an end portion of the piezoelectric transducer from an end face of the backing material has been developed. In the ultrasonic probe, the FPCs are arranged along the end face of the backing material, and the end portions of the FPCs are jointed with the earth electrode formed on a bottom of the projected end of the piezoelectric transducer.
However, when the end portion of the piezoelectric transducer is projected from the end face of the backing material, there is a problem that a structure having the projected portion floating in the air is formed, and thus the crack is easily occurred in the piezoelectric material due to the machining stress generated in the dicing. Since the crack in the piezoelectric material has a great influence to the ultrasonic characteristics, in recent years, dicing without damaging the piezoelectric material has been required.

Ultrasonic probe with a conductive substrate connected to a transducer


An electrophotographic toner composition comprising (A) toner particles with an average particle diameter of 9 .mu.m or less comprising at least a binder resin and a colorant, and (B) an additive, wherein the additive is a fine metal oxide powder surface coated with at least one agent for imparting hydrophobic property selected from the group consisting of the following formulae (1), (2) and (3): EQU R.sub.1 Si(X).sub.3 EQU R.sub.1 R.sub.2 Si(X).sub.2 EQU R.sub.1 R.sub.2 R.sub.3 Si(X).sub.1. wherein R.sub.1 represents a substituted or unsubstituted alkyl group having a molecular weight of 113 or more, R.sub.2 and R.sub.3 each represents hydrogen, an alkyl group or an allyl group, and X represents chlorine, an alkoxy group or an acetoxy group. The toner composition causes no impaction to a carrier and no adhesion of the toner particles to a photoreceptor, and can form stable, sufficient images for a long time.

Previously, various investigations into adhesion of toner particles to photoreceptors (so-called filming) have been conducted. For example, the method of adding a metallic soap to a developer layer to prevent toner particles from adhering and the method of adding an abrasive to a developer layer to scrape off adhered toner particles.
At present, progressive investigations are made of not only inorganic photoreceptors, but also organic photoreceptors, and the share of organic photoreceptors are increasingly broaden. The techniques of copying machines and printers have also progressed so as to use small-sized toner particles to attain high image quality.
As these techniques progress, a new problem is encountered in the techniques for preventing toner particles from adhering to photoreceptors.
Namely, although tolerable effects were realized by the use of the inorganic photoreceptors described above and the toner particles having a normal particle size in the conventional techniques, the use of the organic photoreceptors and the small-sized toner particles makes it impossible to obtain sufficient effects.
One reason for this is that the organic photoreceptors are soft in their surface compared to the inorganic photoreceptors and high in their reactivity, which is liable to cause the life thereof to be reduced.
When such organic photoreceptors are used, therefore, the use of so-called cleaning assistants such as metallic soaps, waxes and abrasives results in deterioration and scraping of the photoreceptors.
On the other hand, when the size of the toner particles is reduced, the problem arises that impaction to a carrier is liable to occur and the life is reduced. Furthermore, the small-sized toner particles are inferior to the toner particles having a normal particle size (10 to 20 .mu.m) in powder fluidity, and therefore, a large amount of fine inorganic particles are required to be used. In some cases, these fine inorganic particles contribute to filming.
For this reason, when the organic photoreceptor and the small-sized toner particles are used, there is no technique at present by which sufficient images can be obtained for a long period of time and which can prevent the toner particles from adhering to the photoreceptor to a satisfiable degree.


A disc is provided which includes a disc body of disc shape having a center hole. An information recording area is formed on one side surface of the disc body. The information recording area has information thereon read by reflection of laser light. The information recording area has an inner circumferential edge positioned adjacent to the center hole. The disc body has a radius ranging from 39 mm to 80 mm, the center hole has a radius ranging from 7.5 mm to 7.55 mm, and the inner circumferential edge of the information recording area being positioned to extend from a radius of 15 mm to 22 mm from the center of the disc body. A disc may be manufactured by variations of the following disc manufacturing method including the steps of: supporting a stamper on a first mold by a supporting means; defining a forming space by clamping the first mold to a second mold; defining a center hole of the disc by advancing a center hole defining member into a center part of the forming space; connecting a injection means into the forming space by opening a gate member of a resin injection member and filling the forming space with a resin through a communicating hole from the injection means; and cooling the resin in the forming space after shutting off connection between the injection means and the forming space by closing the gate member of the resin injection member.

1. Field of the Invention
This invention relates to a disc such as an optical disc, an optical magnetic disc, a phase change optical disc and so on having an information recording area for data near a center hole of the disc and a disc manufacturing apparatus and method thereof.
2. Description of Related Art
These days, as recording media for recording digital data such as sounds, images, pictures and computer data, an optical disc becomes the mainstream. An optical disc has various size according to recording media. For example, as the representative of a disc for sound recording media, there is a compact disc whose diameter is 120 .+-.0.3 mm or 80.+-.0.3 mm, and as recording media for images and computer data and so on, there is a CD-ROM whose diameter is 120.+-.0.3 mm.
Manufacturing apparatus for producing an optical disc of this kind is described hereafter referring to FIG. 15 to FIG. 18.
FIG. 16 shows molds and a stamper 201 for manufacturing an optical disc (a compact disc whose diameter is 120 mm). FIG. 17 shows a replica disc 203 manufactured by the molds and the stamper 201 of FIG. 16. Data are recorded on the stamper 201 from the inside diameter 46 mm to 117 mm. The replica disc 203 becomes an optical disc as a final product. A fixed mold 210 has a mirror block 211 having a mirror surface 213. The stamper 201 is fixed on the mirror surface 213 by an outer stamper holder 215 and an inner stamper holder 217. A moving mold 220 has a mirror block 221 having a mirror surface 223. The mirror block 221 contains a sprue bush 225 of pipe shape. An injection port 227 for injecting a forming material melted by heat is formed at the sprue bush 225 and its top end is exposed from the mirror surface 223.
The fixed mold 210 contains a cut pin 231 of pipe shape. A sprue ejector 233 of bar shape is disposed at the center of the cut pin 231. A top end of the sprue ejector 233 caves in a little from a top end of the cut pin 231 and forms a concave shape, so that a space 235 is provided there. The sprue bush 225, cut pin 231 and sprue ejector 233 can move in the direction of an arrow 241. The sprue bush 225, cut pin 231 and sprue ejector 233 define a center hole 205 as a through hole having an inside diameter of 15 mm to 15.1 mm on the replica disc 203, in case of a compact disc. A sprue 207 is taken out from the replica disc 203 by the sprue ejector 233.
The process to manufacture an optical disc by using the above optical disc manufacturing apparatus is described hereafter. First of all, as shown in FIG. 16, in the state that the fixed mold 210 and the moving mold 220 are opened, the stamper 201 is fixed on the mirror surface 213 of the mirror block 211 of the fixed mold 210 by the holders 215 and 217 so that a data transfer surface, as an information recording area, of the stamper 201 is outside. Then, the moving mold 220 moves toward the fixed mold 210 and both molds 210 and 220 are unified by closing them each other. Next, as shown in FIG. 15, a material melted by heat, for example, synthetic resin such as polycarbonate and so on, are injected from the injection port 227 into a disc molding space defined by the data transfer surface of the stamper 201 on the fixed mold 210 and the mirror surface 223 of the mirror block 221 of the moving mold 220. The shape of the replica disc 203 at this time is shown in FIG. 17(a). The material fill up the molding space and injection pressure of the materials at this time transfers the data recorded on the stamper 201 to a boundary surface of the material between the stamper 201 and the material. Then, the center hole 205 is formed by moving the sprue bush 225, cut pin 231 and sprue ejector 233 in the direction of an arrow 243 before the melting material cool down, as shown in 17(c). At this time, the intervals among the sprue bush 225, cut pin 231 and sprue ejector 233 are unchanged. Next, the material filling the molding space is cooled to be solidified.
Thereafter, the moving mold 220 moves to separate from the fixed mold 210 and the molds 210 and 220 are opened. At the same time, the sprue bush 225 moves to the original position in the direction of an arrow 245 so that the top of the sprue bush 225 reaches the same level as the mirror surface 223. Next, the sprue ejector 233 moves further in the direction of the arrow 243 and a sprue 237 is taken out from the replica disc 203, as shown in 17(d). The sprue 237 is the material filled at the injection port 227 and the center hole 205 at manufacturing time for a disc and it is unnecessary. After taking out the sprue 237, the cut pin 231 and the sprue ejector 233 move back to the original position in the direction of the arrow 245. By the above-described process of manufacturing optional discs, the data recorded on the stamper 201 is transferred to the replica disc 203, and such a replica disc 203 having the center hole 205 at its center is taken out. Then, an optical disc having a center hole is manufactured by providing a reflective film and the like on the information recording surface thereof.
An example of an optical disc manufactured by the above process is shown in FIG. 18.
FIG. 18 is a plan view of a compact disc manufactured by a common injection mold method.
As shown in FIG. 18, a mold used for mass production bores a center hole 252, whose inside diameter is from 15 mm to 15.1 mm (in case of a compact disc) prescribed by International Electrotechnique Commission (IEC), through an information recording area 251, shown by cross-hatching, of an optical disc body 250 during manufacturing process. A recording start point 253 of the information recording area is at an inside diameter of 46 mm.
In the above disc manufacturing apparatus, boring operation for the center hole is performed during the disc molding process, so that manufacturing steps increases. In addition, the material filled in a center part of a disc, namely, a sprue part, are wasteful. Moreover, compaction of a disc is demanded as amount of information is expanded due to diversification of multi-media. That is, a disc whose diameter or size is made smaller than the present one will be needed. As an example of a compact disc on the market, a layout on a plane of a well-known compact disc shown in FIG. 18 is as follows:
the outside diameter=120 mm PA1 the largest diameter of the information recording area (recording end point)=117 mm PA1 the smallest diameter of the information recording area (recording start point)=46 mm PA1 center hole (through hole)=15 mm
Here, though the outside diameter of a disc is 120 mm, the largest diameter of the information recording area, namely, the position of a lead-out 254 (recording end point) is 117 mm, and the smallest diameter of the information recording area, namely, the position of a lead-in 253 (recording start point) is 46 mm. Therefore, only 80 percent of the whole disc area is used as an information recording area. In addition, in case of a compact disc and a minidisc which have a smaller diameter, the utility as an information recording area is lowered further.


A non-volatile semiconductor memory device and the fabricating method thereof, wherein control gates respectively formed at the active areas of the resultant structure for getting a corresponding pair of split floating gates continuously overlapped and buried diffusion areas formed at the substrate of the periphery of the field insulating layer positioned between neighboring source areas to prevent the source areas from being electrically disconnected by the field insulating layer, even if the floating gate pattern and the control gate pattern are respectively made by separate processes, so that there will be no mismatching between the aforementioned two patterns, thereby leading to no tendency of showing different characteristics of memory cells in accordance with odd/even numbered word lines, the schematic characteristic of cells makes it possible to program and erase a byte, and one contact hole is not used at each bit line, the number of contact holes gets small, thereby making it possible to scale down cells.

1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and a fabricating method thereof, and more particularly to a non-volatile semiconductor memory device and a fabricating method thereof, which prevents mismatching between a split floating gate and a control gate, so that there will be no different characteristics of memory cells in response to odd/ even numbered word line.
2. Description of the Prior Art
In general, a non-volatile semiconductor memory device has recently shown a tendency to be widely used in a variety of fields since it can not only erase/store data with electrical connection, but also store data without supply of electricity. These memory cells of the non-volatile semiconductor memory device are classified into NAND type and NOR type.
There are different advantages in those NAND and NOR types of memory cells in response to the trend of becoming high integration and high speed of memory cells, so that they have been increasingly used in a variety of applications to make the best use of those advantages of respective types.
The NOR type of the non-volatile semiconductor memory device comprises a plurality of memory cells having a transistor at a bit line connected in parallel and only one memory cell transistor positioned between a drain connected to the bit line and a source connected to a common source line. There is an advantage in the NOR type of a non-volatile semiconductor memory device in that the current of memory cells is high enough to operate at high speed, but a disadvantage in that it is difficult to have a high integration due to large area taken by the contact of bit lines and source lines.
The NOR type of the non-volatile memory device is constructed in a deposition structure in which a floating gate and a control gate are deposited with an insulation interlayer therebetween, and the processes thereof will be described below.
First of all, in programming data, when voltage is applied to the bit line and the control gate connected with the drain of memory cells, electric current flows between the source and the drain, so that electrons are injected into the floating gate by a channel hot electron injection mechanism. As a result, data are programmed.
In erasing, when voltage is applied to a source, electrons are flown out of the floating gate by a Fowler-Nordheim tunneling mechanism. As a result, data are erased.
In reading, when adequate voltage is applied to the bit line and the control gate of the selected memory cells, the presence of current at the selected memory cell transistor is read. As a result, data are read.
As memory cells are connected in parallel to the bit line in the non-volatile memory device, if the threshold voltage of the memory cell transistor gets lower than the voltage (usually 0V) applied to the control gate of the not-selected memory cells, current flows between the source and the drain, regardless of the ON/OFF state of the selected memory cells, an operational failure (wrong operation) occurs that all the memory cells may be read as the ON state thereof. Thus, there is a difficulty in the nonvolatile memory device that the threshold voltage should be strictly controlled. Also, because excessive amount of current flows at the memory cells in programming data by the channel hot electron injection mechanism, a high capacity of the pump may be required for generating the voltage in programming data.
In order to solve the aforementioned problem, the non-volatile semiconductor memory devices in a variety of structures, commonly called a split gate type, have been suggested. A representative example of all has been disclosed in U.S. Pat. No. 5,045,488 titled as a xe2x80x9cMETHOD OF MANUFACTURING A SINGLE TRANSISTOR NON-VOLATILE, ELECTRICALLY ALTERABLE SEMICONDUCTOR MEMORY DEVICE.xe2x80x9d
As shown in FIGS. 1 through 3, the non-volatile semiconductor memory device disclosed therein comprises: an active area 11 of a substrate 10 isolated by a field insulating layer 13; a pair of floating gates 15 arranged at a first gate insulating layer of the active area 11 with a source area 17 therebetween; an oxide layer 19 positioned at the floating gates 15; second gate insulating layers 21 positioned at the lateral surfaces of the floating gates 15 to be used for tunneling in erasing data; and control gates 23 simultaneously overlapping an external side of the floating gates 15, the second gate insulating layer 21 and a part of the drain area 18, that is, extensively from an external portion of the floating gate 15 to a part of the drain area 18. An interlayer 25 is deposited at the aforementioned structure, and a bit line 27 is formed for electrical connection through a contact hole 26 to the drain area 18.
At this time, the channel areas formed by the floating gates 15 and the control gates 23 are connected in series. The area marked with a dot line represents a unit cell area (UCA). L1 and L2 respectively symbolize gate lengths of selected memory cell transistors. Even if only a pair of floating gates corresponding to an active area 110 are shown in the drawings for convenient description, it should be taken for granted that a number of pairs of floating gates are repeatedly arranged correspondingly to the active areas 110 in actuality.
Operation of the conventional non-volatile semiconductor memory device thus constructed will be described below. First of all, in programming data, if a high voltage is applied to the source area 17 of the UCA, the floating gate 15 is induced into a predetermined voltage by a coupling phenomenon. Then, if a voltage, for example, higher than the threshold voltage of the transistor formed by the control gate and the channel formed by the floating gate 15 is applied to the control gate 23, current flows between the source area 17 and the drain area 18. At this time, the channel hot electron injection mechanism is performed, so that electrons are injected into the floating gate 15. As a result, data is programmed.
Therefore, if voltage applied to the control gate 23 is properly controlled, hot electrons can be formed at a lower end of the floating gate 15 and the electric field gets strong enough to improve the data programming efficiency. In addition, the current flowing between the source area 17 and the drain area 18 can also be restricted to reduce power consumption, thereby no longer requiring a high capacity of a pump to be used at the stacked NOR type of the non-volatile memory device.
In erasing data, if a high voltage is applied to the control gate 23, the electrons collected at the floating gate 15 are flown out through the second gate insulating layer 21 by the electric field formed between the control gate 23 and the floating gate 15. As a result, data are erased.
In reading data, if a predetermined voltage is applied to the bit line 27 and the control gate 23 connected with the drain area 18 of the memory cells, data can be read in accordance with the presence of the current flowing between the memory cells. At this time, if the channel area formed by the control gate 23 and the channel formed by the floating gate 15 are all made, that is, if voltage, higher than the threshold voltage, is applied to the gate, the non-volatile memory cells flow current.
In general, the select transistors of the memory cells are manufactured to have threshold voltage (Vth) of approximately 1.0V. The floating gate 15 has a high threshold voltage at the data programmed memory cells and a low threshold voltage at the data erased memory cells including xe2x88x92Vth sometimes. However, in case that the floating gate 15 has xe2x88x92Vth due to over-erasure, the select transistor having a threshold voltage of approximately 1.0V turns off the channel even if 0V is applied to the control gate 23. Therefore, there will be not problem of over-erasure any longer. In this way, even if the threshold voltage of the floating gate of the NOR type of the non-volatile semiconductor device is not strictly controlled, an operational failure (wrong operation) will not occur.
However, the floating gate pattern and the control gate pattern are simultaneously formed in a general self-aligned deposition gate type of memory cells, so that misalignment of these two patterns will not easily happen.
On the other hand, since the floating gate pattern and the control gate patterns of a conventional split gate type of memory cells are fabricated by separate processes, misalignment of these two patterns may easily happen in forming the control gate pattern. Without mismatching, the length of the select transistor gates, L1 and L2 will be the same. With mismatching, the length of the select transistor gates L1 and L2 will be different, so that there will be a tendency of showing different characteristics of memory cells in accordance with odd/even numbered word lines.
Besides, byte programming and erasing processes can not be performed due to a schematic characteristic of the memory cells. Furthermore, since one contact hole is used in each bit line, the number of contact holes of bit lines is large, which has been a factor to cause difficulty in scaling down cells.
Therefore, it is an object of the present invention to prevent mismatching of word lines, thereby not showing different characteristics of memory cells in response to with odd/even numbered word lines.
It is another object of the present invention to make it possible to perform byte programming and erasing processes.
It is a third object of the present invention to reduce the number of contact holes used at bit lines, thereby easily scaling down cells.
In order to accomplish the aforementioned objects of the present invention, there is provided a non-volatile semiconductor memory device comprising:
a first conductivity type of a semiconductor substrate having separately formed active areas and field areas formed with field insulating layers to isolate the active areas;
a first gate insulating layer formed at respective substrate of the active areas;
floating gates arranged at a predetermined interval on the first gate insulating layer;
oxide layers respectively formed at the upper surface of the floating gates;
a second gate insulating layer to be used as a tunneling insulating layer formed at lateral surfaces of the floating gates;
control gates respectively formed at the active areas of the resultant structure for getting a corresponding pair of floating gates, out of the floating gates, continuously overlapped;
a second conductivity type of source areas formed at the active area, a part of which is overlapped with the same part of the floating gates, and at a part of the neighboring active area; and
a second conductivity type of buried diffusion areas formed at the substrate of a part of the field area for preventing neighboring source areas of the same source line, out of source areas, from being isolated by the field insulating layer, and for making them electrically connected.
Preferably, the buried diffusion area is formed at the substrate of the periphery of the field insulating layer formed between neighboring source areas. The field insulating layer is an insulating layer filled in the trench.
In addition, a non-volatile semiconductor memory device in accordance with another embodiment of the present invention comprises:
a first conductivity type of a semiconductor substrate having separately formed first active areas, active areas formed between the first active areas with second active areas integrally connected to parts of both sides of the first active areas and field areas formed with a field insulating layer for isolating the active areas;
first gate insulating layers respectively formed at the substrate of the first and second active areas;
floating gates arranged at the first gate insulating layer in a predetermined interval;
oxide layers respectively formed at the upper surfaces of the floating gates;
second gate insulating layers, to be used as tunneling insulating layers, formed at the lateral surfaces of the floating gates;
control gates formed at the first active areas of the resultant structure for getting a corresponding pair of floating gates, out of the floating gates, continuously overlapped; and
a second conductive type of active source areas formed at the first active areas, a part of which is overlapped at the same portion of the floating gates, and at a part of the neighboring first active areas, wherein the second active areas are integrally connected between the source areas to prevent the neighboring source areas of the same source line, out of the source areas, from being isolated by the field insulating layer and to make them electrically connected.
Preferably, the second active areas are ion-implanted with a second conductive type of impurity.
The method of fabricating the non-volatile semiconductor memory device in accordance with the first embodiment of the present invention comprises the steps of:
forming a field insulating layer at a field area of the semiconductor substrate for isolating active areas of the first conductivity type of a semiconductor substrate;
forming first gate insulating layers at the active areas of the substrate;
respectively forming floating gates arranged at the first gate insulating layers in a predetermined interval and oxide layers at the upper surfaces of the floating gates;
forming a second conductivity type of source areas at the substrate of the active areas for getting a part thereof partially overlapped with the same part of the floating gates;
forming second gate insulating layers, to be used for tunneling insulating layers, at the lateral surfaces of the floating gates; and
forming control gates at the active areas of the resultant structure for getting a corresponding pair of the floating gates, out of the floating gates, continuously overlapped,
wherein the step of forming the field insulating layer includes the step of forming a second conductivity type of buried diffusion areas at the substrate of a part of the field areas positioned between neighboring source areas for preventing the source areas neighboring the same source line, out of all the source areas, from being isolated by the field insulating layer, and for making them electrically connected.
A method of fabricating the non-volatile semiconductor memory device in accordance with another embodiment of the present invention comprises the steps of:
forming a first active areas of a first conductivity type of semiconductor substrate and field insulating layers at the field areas of the semiconductor substrate for isolating active areas positioned between the first active areas with the second active areas integrally connected to a part of both sides of the first active areas;
respectively forming a first gate insulating layer at the substrate of the first and second active areas;
forming floating gates arranged in a predetermined interval at the first gate insulating layer and oxide layers at the upper surfaces of the floating gates;
forming a second conductivity type of source areas at the substrate of the active areas for getting a part thereof overlapped with the same parts of the floating gates;
forming a second gate insulating layer, to be used for tunneling insulating layers, at the lateral surfaces of the floating gates; and
forming control gates on the first active areas of the resultant structure for getting a corresponding pair of the floating gates, out of the floating gates, continuously overlapped,
wherein the second active areas are integrally connected between neighboring source areas for preventing the source areas neighboring the same source line, out of all the source areas, from being isolated by the field insulating layers, and for making them electrically connected.
Therefore, in accordance with the present invention, the control gates continuously overlap a pair of split floating gates of the active areas. As a result, even if the floating gate pattern and the control gate pattern are respectively made by separate processes, there will be no mismatching between the aforementioned two patterns. There will be no tendency of showing different characteristics of memory cells in accordance with odd/even numbered word lines.
In addition, the schematic characteristic of cells makes it possible to program and erase a byte. As one contact hole is not used at each bit line, the number of contact holes gets small, thereby making it possible to scale down cells.

Non-volatile semiconductor memory devices with control gates overlapping pairs of floating gates


A method is provided to identify whether video content, which includes a plurality of image frames, is likely to include an advertisement. The video content is split into a plurality of segments, each segment having a pre-specified duration. Subtitle text information is extracted from each segment and is passed through a natural language processing (NLP) language model to extract an embedding representing the subtitle text information for each of the segments, wherein the NLP language model is previously trained to differentiate between subtitle text information from video content items that were each previously identified as being an advertisement in comparison to subtitle text information from video content items that were each previously identified as not being an advertisement. The embedding representing the subtitle text information for each of the segments is passed through a classifier to obtain a probability regarding whether each segment is an advertisement or not.

Precise detection of advertisements (ads) in a video (TV) stream is of paramount importance for companies in the field of TV analytics and measurement, partly because it allows for accurate downstream analysis. Whether the task is to provide audience engagement, deeper insights into consumer behavior and attribution, or to solidify automated content recognition and categorization, accurate and automated ad detection is a very important first step.
Conventional approaches to ad detection rely largely on feature extraction from audio and video. One prior art approach that uses closed captions to detect commercials is described in Ganesh Ramesh, Amit Bagga: "A Text-based Method for Detection and Filtering of Commercial Segments in Broadcast News," 2002. However, this approach is based on a simple similarity measure within words in the captions, and does not generalize very well.
Accordingly, there is an unmet need for improved systems and methods that use closed caption text for performing advertisement (ad) detection in a video stream, and more specifically, to perform ad vs non-ad classification. The present invention fulfills this need.

Closed-caption processing using machine learning for media advertisement detection


An etchant fume exhaust apparatus is installed in a system performing an etching process during fabrication of LCDs. The etchant fume exhaust apparatus prevents the contamination and corrosion of the etching system by allowing both gaseous and liquid etchant to be discharged safely. The etchant fume exhaust apparatus includes an exhaust hole that provides a passage to discharge gaseous etchant, an exhaust plate located under the exhaust hole that collects condensed etchant dripping from the exhaust hole, a support part that fixes the exhaust plate to the exhaust hole, and an exhaust line connected to the bottom of the exhaust plate through which the etchant collected in the exhaust plate is removed from the etchant plate.

1. Field of the Invention
The present invention relates to a wet etching system, and more particularly, to an etchant fume exhaust apparatus installed in the etching system being used in an etching process for the fabrication of a liquid crystal display device, for discharging the etchant in a vapor and liquid state out of the system thereby to prevent the contamination and corrosion of the etching system.
2. Description of the Related Art
With the recent rapid development of the technologies in semiconductor device fabrication industries, improved liquid crystal display (LCD) device products are produced that are thinner and lighter. The CRT (cathode ray tube), being widely used for display devices until now, has advantages in functionality and price, but also has many disadvantages including difficulty in miniaturization and portability.
In contrast, LCD devices have many more advantages than CRTs, especially when it comes to mobile devices. These advantages include the ability to miniaturize the devices, the devices are comparatively lightweight, and have relatively low power consumption. LCD devices have become so common that they are replacing the conventional CRT devices, especially as they overcome the above problems of the CRT. Nowadays, LCD devices are used in almost all information processing systems which need display devices.
In the meantime, one driving principle of the LCD device is the optical anisotropy and the polarization property of its liquid crystal material. Since the liquid crystal material is thin and long in its structure, its molecular alignment direction can be adjusted depending on the electric field applied to a liquid crystal material having a particular orientation and polarization.
Therefore, by arbitrarily adjusting the alignment direction, light can be transmitted or blocked dependent on the alignment direction of the liquid crystal molecules by the optical anisotropy of the liquid crystal material so as to display colors and images.
Typically, the LCD device includes a first substrate (thin film transistor substrate) and a second substrate (color filter substrate), which are separated and arranged to face each other.
One exemplary description of a fabrication process of the first substrate of the LCD device will be as follows.
First, a metal layer is deposited on a transparent glass substrate, and a first mask process is performed to form a gate bus line and a gate electrode by etching. Then, by depositing a gate insulating layer, an amorphous silicon layer, and a doped amorphous silicon layer in sequence, a second mask process is performed to form a channel layer.
Then, a third mask process is performed by depositing a source/drain metal layer on the substrate having the channel layer formed thereon, and then, by etching to form a source/drain electrode and a data bus line. Further, a protection layer to protect device elements is deposited, and a fourth mask process is performed to form contact holes. Then, an ITO transparent metal layer is deposited on the substrate having the protection layer formed thereon, and by etching, a fifth mask process is performed to form a pixel electrode.
As described above, a patterning process is performed by depositing or coating a metal layer and an insulating layer on the transparent glass substrate alternately. In the case of a metal layer, the metal layer is etched by wet etching, and in the case of an insulating layer, dry etching is used by using plasma molecules.
In etching processes, the conditions of pressure and ion molecular concentration of plasma in the etching chamber are controlled dependent on the etched subjects.
Further, a black matrix in a lattice shape is formed on the transparent upper substrate of the color filter substrate. Then, color filter layers of red (R), green (G), blue (B) are formed on the black matrix to complete the color filter substrate.
Further, in the formation of the black matrix, a metal layer such as chrome is formed on the substrate by using vacuum deposition, for example, and a photosensitive resin is formed thereon. Then, patterning is performed by using photolithography and the chrome is subsequently etched.
As such, a wet etching process is included in the fabrication of the thin film transistor substrate and the color filter substrate. Such a wet etching process is classified into PSL (poly spacer LOCOS) or STI (shallow trench isolation) structure of active define process and via round etching process or the like. The etchant used in the wet etching process can be roughly classified into two component group and three component group compounds.
The two component group compound includes HF and deionized water (DIW) in which the HF dissolved in the DIW is dissociated into a small amount of HF2 to etch an oxide layer. The three component group compound is called SBOE (surfactant buffered oxide etchant), and is composed of HF, NH4F, DIW, and negative ion surfactants. In such an SBOE group etchant, all HF in the DIW is dissociated into HF2 by the added NH4F.
In the fabrication process of an LCD device, compounds such as those above are mixed and used as the etchant. The structure of the etchant supply apparatus employed in a typical etching system is illustrated in FIG. 1. FIG. 1 is a schematic representation of an etchant supply apparatus in a typical etching system.
As shown in FIG. 1, an etchant supply apparatus 100 includes a first etchant tank 110a and a second etchant tank 110b, which contain the etchant compound described above. The etchant supply apparatus 100 also includes a pump 150 for supplying the etchant from the first etchant tank 110a and the second etchant tank 110b to a supply pipe 130.
Further, etchant fume exhaust units 120a, 120b are provided in the upper portion of the etchant supply apparatus 100, for discharging a gas state of the etchant out of the etching system. Further, after the etching process is completed, a return line 140 is provided such that the etchant used in the etching process can be returned into the first etchant tank 110a and the second etchant tank 110b.
Though not shown in the drawing, the etchant supply apparatus 100 further includes a self-circulation unit and a filter unit for filtering the returned etchant and a coolant supply part, for example.
Describing in more detail, the etchant supply apparatus 100 structured as above mixes the etchant compound contained in the first etchant tank 110a and the second etchant tank 110b by the movement of the pump 150, and supplies the mixed etchant to a chamber (not shown) being used for the etching process. Then, when the etching process is performed in the fabrication of a thin film transistor substrate and a color filter substrate of an LCD device, the etchant supply apparatus 100 supplies the mixed etchant to the substrate for which the etching is processed.
After the etching process is done, the etchant used in the etching process passes through the return line 140 of the etchant supply apparatus 100 and comes back into the first etchant tank 110a and the second etchant tank 110b. Further, when another etching process is performed for the substrate, the etchant supply apparatus 100 supplies etchant to the chamber by the movement of the pump 150.
In the etchant supply apparatus 100 of the etching system, the supply of etchant to the chamber, and the return of the etchant from the chamber are all repeatedly performed. During the repetitive supply and return of the etchant described as above, the etchant, being very volatile, becomes gaseous and rises up over the etchant supply apparatus 100. Thus, etchant fume exhaust units 120a, 120b are provided in the upper portion of the etchant supply apparatus 100 for discharging the gas state of etchant out of the system.
FIG. 2 is an exemplary conceptional representation of the structure of the etchant fume exhaust apparatus installed in a conventional etching system.
As shown in FIG. 2, an exhaust hole 200 is provided in the etchant exhaust apparatus. The etchant hole 200 is located in the upper portion of the etchant supply apparatus, and is configured to penetrate the apparatus 100 so that the gas state of etchant, which has risen upward, is discharged out of the apparatus 100 through the exhaust hole 200.
While the gas state of the etchant is being discharged through the exhaust hole 200, the rising etchant often re-liquefies in the exhaust hole 200. This re-liquefied etchant returns back into the apparatus 100 from the exhaust hole 200, and the dripping etchant falls down on the etching system. This causes problems in contamination and corrosion of the etching equipment in the apparatus 100.


In a case where tone waveform sample data are to be arithmetically formed by software, there are installed, within a virtual device driver routine of an operating system, a MIDI processing routine for converting a received MIDI event into tone generator control data and a waveform forming processing routine for arithmetically forming tone waveform sample data for one frame. The MIDI processing routine is triggered by a software interrupt signal that is generated in response to a MIDI event produced from an application software program such as a sequencer software program, and the waveform forming processing routine is triggered by a hardware interrupt signal that is generated upon completion of tone reproduction for one frame.

The present invention relates to a tone generating method for arithmetically forming a tone waveform by executing a tone generating program on an arithmetic processor, and a tone generating device based on the tone generating method.
Tone generating devices have been known today, typical examples of which comprise a MIDI (Musical Instrument Digital Interface), a performance input section for entering performance information via a keyboard or sequencer, a tone generator section for generating a tone waveform, and a central processing unit (CPU) for controlling the tone generator section in accordance with the entered performance information. The CPU executes various tone generator driver processing, such as channel assignment and parameter conversion, in accordance with the entered performance information, and supplies the assigned channel with the converted parameters along with a tone-generation start (note-on) instruction. The tone generator section forms a tone waveform on the basis of the supplied parameters and is implemented by hardware such as electronic circuitry. Therefore, the conventional tone generating devices just operate as dedicated devices for tone generation, and it was always necessary to employ such a dedicated device when artificial tones were to be generated.
Recently, a tone generating method has been proposed, in which tone generator processing based on computer programs (software tone generator) is employed in place of the traditional hardware tone generator and performance processing and tone generator processing are both executed by the CPU. Similarly to the above-mentioned tone generator driver processing, the performance processing creates tone control information on the basis of received MIDI information or other performance information. The tone generator processing, on the other hand, forms tone waveform sample data on the basis of the control information created by the performance processing. With this tone generating method, tones can be generated, without any dedicated tone generating device, by just providing a CPU, software program and digital-to-analog (D/A) converter.
In order to generate tones, it is necessary to supply waveform sample data to the D/A converter every sampling cycle, i.e., every conversion timing of the D/A converter. According to the above-mentioned conventional tone generating method, the CPU normally executes the performance processing, such as detection of depressed keys. But, the CPU interrupts the performance processing, every sampling cycle, to execute the tone generator processing in order to arithmetically form one waveform sample data for a plurality of tone generating channels and then returns to the performance processing after the sample data formation.
However, in the above-mentioned conventional tone generating method, the CPU needs to transfer, from a memory into a predetermined register, various data used in the preceding calculation for each of the channels before actually executing the waveform forming calculation for the channel every sampling cycle; after completion of the calculation, the CPU needs to save the contents of the register into the memory, for next execution of the calculation. Namely, because tone waveform sample data is arithmetically formed, for each of the channels, sample by sample in the conventional tone generating method, much time would be spent in preparing operations rather than the tone formation itself, which would result in poor calculating efficiency and response and would considerably delay the tone generating processing. As a result, sufficient time can not be allocated to the waveform forming calculation.
Application programs, such as MIDI sequencer software or game software, for supplying such a software tone generator with MIDI event information or other performance information are designed to operate under an ordinary operating system (OS). When the software tone generator is to be driven by MIDI event information created by the MIDI sequencer software, the sequencer software itself can not be activated unless the OS is run; however, in such a case, it is necessary to operate the software simultaneously with the OS in a stable manner. Thus, it is difficult to operate, in real time, the above-mentioned software tone generator under the ordinary OS.
For example, with an OS based on a non-complete (non-preemptive) multitask scheme, unless a specific task being executed returns control to the OS, any other task is not executed. Thus, the software tone generator can sometimes not be executed at predetermined time intervals, and accordingly tone waveform sample data may not be stably output every sampling cycle.
Further, performance information (MIDI event information) is produced by a player's performance operation or by reproduction of an event via a sequencer, and the produced performance information is processed by the above-mentioned performance processing. Namely, each time performance information is produced, the CPU must execute the performance processing in addition to the normal tone generator processing; thus, due to non-periodically produced performance information, the amount of calculation to be performed would temporarily increase to a substantial degree. However, because the tone generator processing is periodically executed with priority over the performance processing irrespective of presence/absence of performance information, the performance processing could be substantially delayed in some cases.
One approach to avoid such time delays of the performance processing may be to give higher priority to the performance processing rather than the tone generator processing. But, this approach would result in unstable operation of the tone generator processing, such as temporary decrease in the number of generated tones or unwanted temporary break in a formed tone waveform. Particularly, such unstable operation of the tone generator processing would become a significant problem in a real-time performance.
In addition, the conventional software tone generator would require various setting operations before being actually used, because the software tone generator can not be driven by just running an application software program using the conventional hardware generator, i.e., without making any particular change to the application.

Method and apparatus for generating a tone based on tone generating software


A computer and a server may communicate via one or more local shared objects. The computer may detect one local shared object and generate a second local shared object based on the first local shared object. The computer may perform an action based on the second local shared object. The computer may display whether the action was a success.

The present application generally relates to server and computer communication, and in particular relates to server and computer communication in access control systems. Access control systems generally restrict access to certain areas, allowing certain persons access to said areas based on a credential. Some access control systems have certain limitations. Therefore, a need remains for further improvements in systems and methods for server and computer communication in access control systems.

Server and computer interaction via local shared objects


This invention relates to an improved control arm assembly for use in the front and/or rear suspension of a vehicle. The control arm assembly is constructed in a manner wherein the bushings incorporated therein may be easily removed and replaced. Such ease of replacement is facilitated by the polyurethane construction of the bushings. When inserted into the suspension, the control arm comprising the control arm assembly is prevented from moving laterally into metal-to-metal contact with a respective frame hanger bracket by the structure of the bushings inserted thereinto.

Incorporated into the front and rear suspensions of numerous automotive vehicles is a component commonly referred to as a control arm. Generally, vehicles which include control arms have an upper and lower control arm assembly which are used in conjunction with the suspension at each axle of the vehicle.
With respect to the front suspension, each of the front control arms are typically mounted adjacent the opposed ends of the front axle. Similarly, with respect to the rear suspension, each of the two rear control arms are typically mounted adjacent the opposed ends of the rear axle. Each of the control arms incorporated into the vehicle suspension extend between pairs of frame hanger brackets, one of which is attached to the vehicle frame with the other being attached to either the front or rear axle. Attached to the center portion of each of the control arms is a suspension spring which extends upwardly therefrom. Additionally, attached to one end of each of the control arms is a shook absorber which also extends upwardly therefrom.
Each control arm typically includes two control arm bushings which are disposed within apertures located adjacent the opposed ends of the control arm. In control arms as currently known and manufactured, each of the two control arm bushings are fabricated from rubber and press-fit into a respective aperture disposed within the control arm through the use of an arbor press or similar device. Each of the control arm bushings is generally sized to protrude slightly outwardly from each end of the aperture into which it is disposed. Thus, when the control arm is disposed within its respective pair of frame hanger brackets, the brackets themselves, which are typically U=shaped, come in contact with only the rubber bushing as opposed to the metal control arm itself. As can be appreciated, over extended periods of time, the rubber bushings disposed within the control arms typically wear and shrink, thereby allowing the control arm to chatter, i.e. move relative the bushing, as well as travel laterally along the length of the bushing. When such occurs, vibration dampening is decreased, and oftentimes the control arm itself comes into contact with one side of the frame hanger bracket thereby causing metal-to-metal contact. Such metal-to-metal contact in turn gives rise to diminished vehicle handling in addition to wear of the suspension components.
With control arm assemblies as currently known, once one or both of the two control arm bushings disposed within the control arm become worn, typically the entire control arm is removed and replaced. This is due to the difficulties commonly associated with attempting to press-fit new control arm bushings into the control arm. As can be appreciated, replacing the entire control arm assembly as opposed to only the control arm bushings themselves gives rise to significantly increased costs in the repair operation. Thus, there exists a need in the art for a control arm assembly wherein the control arm bushings may be easily and quickly replaced without the need for replacing the entire control arm.


Disclosed is a channel estimator adopting masking. In a channel estimator using a CIR (channel impulse response) estimating value, the present invention includes a CIR masking unit removing a noise included in the CIR estimating value. Accordingly, the present invention is capable of filtering noises resulting from finiteness of the PN sequence used in finding the cross correlator, thereby enabling to enhance accuracy for the CIR estimating value. And, the enhanced accuracy for the CIR estimating value enables to improve tracking performance to the time variable channel of the frequency domain equalizer using the channel estimator.

1. Field of the Invention
The present invention relates to a channel estimator, and more particularly, to a channel estimator adopting masking.
2. Discussion of the Related Art
Generally, a terrestrial TV signal of an 8-VSB (vestigial sideband) system passes through a dynamic multipath channel from a transmitting end to arrive at a receiving end. The received signal is severely distorted by interference with an adjacent signal, whereby adoption of an equalizer is needed to restore an original signal from the distorted signal.
A receiver, which receives a signal transmitted from a single carrier transmission system adopting VSB, mostly uses an equalizer implemented in a time domain (hereinafter called time domain equalizer). And, a non-linear decision feedback equalizer (DEF) is the most representative.
The time domain equalizer adopts LMS (least-mean-squares) to facilitate its implementation. Yet, since error propagation occurs in case of severe channel distortion, the time domain equalizer fails to achieve re-convergence even if a channel status becomes good again. Moreover, the time domain equalizer fails to operate robustly when a main path in a time variable channel varies, frame synchronization of the received signal is frequently broken.
Most of the above-described defects of the time domain equalizer can be settled by means of using an equalizer that adopts zero forcing in a frequency domain after finding an impulse response of a channel using a channel estimator.
Namely, the equalizer implemented within the frequency domain enables to show its performance constantly regardless of the number of multipath or a degree of distortion of the received signal. And, the equalizer enables to operate robustly without generating frame errors like the time domain equalizer under a channel environment that a main path varies according to time. Moreover, the equalizer can be implemented more simply than the time domain equalizer as a range of multipath that is to be equalized gets wider.
In this case, performance of the frequency domain equalizer through channel estimation substantially depends on accuracy and frequency of the channel estimation, whereby various estimating methods are actively tried.
A system, to which a frequency domain equalizer through channel estimation is applied, according to a related art is explained by referring to the attached drawing as follows.
FIG. 1 is a block diagram of a system to which a frequency domain equalizer through channel estimation is applied according to a related art.
Referring to FIG. 1, the system consists of a channel estimator 101 estimating a CIR (channel impulse response) ĥ(n) from a received baseband signal y(n), a first FFT (frequency field transform) 102 transforming the base band signal into a signal of a frequency domain, a second FFT 103 transforming the estimated CIR ĥ(n) into a signal of the frequency domain, a frequency domain equalizer 104 executing equalization by zero forcing using the baseband signal y(n) and CIR ĥ(n) transformed into the signals of the frequency domain, respectively, and an IFFT 105 inverse-transforming the equalized signals of the frequency domain into signals of a time domain.
A signal equalized by zero forcing includes a colored noise. In order to remove such a colored noise, the system further consists of a noise predictor 106 computing a noise prediction value {circumflex over (v)}(n) from an output ĥ(n)+v(n) of the IFFT 105 and an adder 108 removing the colored noise by adding the output ĥ(n)+v(n) of the IFFT 105 to the noise prediction value {circumflex over (v)}(n) outputted from the noise predictor 106.
Specifically, the channel estimator 101 is explained in detail as follows.
As estimating methods of the channel estimator 101, there are an estimating method using a training signal only, the blind method operating regardless of a training signal, and the semi-blind method using a training signal for a training section and operating as blind for the rest section except the training section.
Three kinds of methods, which can be simply implemented relatively, among practical implementations of the above-explained two methods are explained as follows.
1) A Method Using Cross Correlation between Noted Training Signal and Actually-Received Training Signal Only
In case of a channel estimator using cross correlation only, a channel estimating value is relatively inaccurate despite its simplicity. In this case, in order to enhance accuracy of the cross correlation, it may be considered to increase the number of training symbols used for cross correlating calculation. Yet, since a peak shows up due to finiteness of PN sequence occurring by 63-symbol cycle, the structure of a VSB field sink part, where PN63 sequence is overlapped, has difficulty in accurate channel estimation.
2) Least Square (LS)
The constraint of the above method 1) can be overcome by channel estimation of LS. Namely, the LS removes auto correlating relation between training symbols used in cross correlating calculation within a training section from cross correlation, thereby fitting VSB reception environment.
3) Sub-Channel Response Matching (SRM) Using Both Data and Training Symbol
In case of sub-channel response matching (SRM), it is able to estimate a channel accurately only if a length of CIR is accurately known. Hence, SRM is not appropriate for an environment that a characteristic of such a certain channel as a terrestrial channel varies according to time severely.
Hence, in case of a channel estimator using cross correlation including LS, when noise caused by data is included while the cross correlation is executed, the influence of the noise caused by the data can be reduced by taking a time domain average using the fact that the data is a probability function of which average is '0'. Thus, in case of a channel estimator using time average, the accuracy of the channel estimating value can be enhanced by finding a channel estimation sequence value every field and by taking the average of the time domain.
However, since a moving average should be taken to remove a bad influence of data included in CIR, very poor characteristics appear on the time domain estimator updated by symbol unit in case of a time variable channel.
Meanwhile, as another method of removing the influence of data in channel estimation, there is a technique of thresholding, in which CIR, as shown in Equation 1, below a specific level (ε) is regarded as '0'.ĥ(n)=0, if |ĥ(n)|<εĥ(n), otherwise.  [Equation 1]
The channel estimator, which takes the time average on the CIR of the channel estimated by the LS method, accurately estimates the CIR of the channel for a static channel that is a multipath, thereby providing characteristics remarkably superior to those of the equalizer operating as blind in the time domain.
However, in case of the above-explained method, a CIR value exceeding a critical value fails to save pulse tails by a pulse sharing filter of a transmitting end and a matched filter of a receiving end at all, whereby degradation of performance severely occurs.
Besides the above-explained problems, there exists a certain amount of disturbance of a frequency spectrum despite an excellent terrestrial DTV reception environment, whereby reception performance on a dynamic multipath channel is degraded when the related art channel estimator is applied to a DTV receiver.


A flexible pressure containment coverplate has been invented for radial flow reactors. The coverplate is for a fixed bed reactor wherein the reactor undergoes significant thermal cycles. The coverplate provides flexibility for axial and radial thermal growth, while providing a sealing capability to prevent leakage of the fluid. The coverplate has a half toroidal structure, with a semi-circular cross-section.

The olefin cracking process comprises contacting an olefin rich stream with a solid catalyst to crack larger olefins into light olefins. The process increases the yields of ethylene and propylene from processes that generate butenes, pentenes and larger olefins. The olefin cracking process utilizes a radial flow reactor design wherein the olefin rich gas flows radially, or horizontally, over a fixed bed of catalyst. The olefin cracking reactor uses a downflow seal design requiring a coverplate configuration. The coverplate connects the inner and outer screens of the radial flow reactor. This configuration enables vapor containment in a low amplitude-high frequency thermal cyclic operation. The flow of the gas over the reactor bed generates a pressure differential across the coverplate. The conventional coverplate couples the inner and outer screens which experience frequent axial and radial differential thermal growth. The pressure differential combined with the cyclic thermal operation creates potential leakage opportunities where the leakage of the seal flow has the equivalent effect of a feed bypass. The pressure differential containment requires reinforcement of the components that grow and interact with the frequent thermal cyclic operation.
This has led to the development of reinforcement of the components, such that the system is stiff, or rigid, enough to translate relative differential growth. The system is combined with numerous component interfaces that are sized with clearances which require numerous slip joint and overlapping type connections. These connections are then packed with materials for sealing the system. The conventional system requires the interaction of numerous components at multiple interfaces, and presents the opportunity for mechanical failure and subsequent leakage, resulting in significant losses.

Flexible pressure containing shaped coverplate configuration


The invention is a vehicular mirror assembly for a rectangular shaped mirror typically found on industrial trucks, earthmovers, and dump trucks. The mirror is placed in a holder with two or more pillow block bearings secured on the back of the holder. A circular rod, creating a first axis, extends longitudinally through the pillow block bearings and is swivelly secured to a mounting bracket thereby forming a second axis. A remotely controlled ram is secured to the mounting bracket and proximate to the edge of the holder allowing operator control of the left/right motion around the second axis; a second remotely controlled ram is swivelly secured to the circular rod for up/down adjustment by the operator for movement of the second axis.

This invention relates generally to remotely adjustable mirrors and more particularly to extremely large vehicular mirrors.
Many industrial vehicles, such as: dump trucks, earth movers, excavators, and the like, must employ very large mirrors in order to have a view of their surroundings for safety purposes. These mirrors are often rectangular on the order of four feet high by one foot wide and may be flat or convex.
Due to the economics involved with such large machinery, they are often operated at least two, and usually three, shifts a day. This means that multiple drivers are employed requiring that the mirrors be adjusted for each driver. Manual adjustment of the mirror is difficult and time consuming. The operator/driver must first sit to see how the mirrors are currently adjusted, get up to adjust the mirror, re-seat themselves, and repeat the process if the mirror wasn't properly adjusted. This though becomes burdensome and subsequent drivers often "make do" with the adjustment from the previous driver.
Clearly, by "making do", there are potential blind spots in the mirror's view that can pose significant risks to other vehicles and pedestrians.
Remote control, such as is found in passenger vehicles has not been feasible. The motors, gears, and basic structure used in passenger vehicles does not create a solution for such large and heavy mirrors as is found in the industrial vehicle setting. Because of this, remote control has not been employed, leaving the drivers with only the option of manual manipulation of the mirrors.
It is clear from the foregoing that there is a need for an improved mechanism and mirror which is remotely adjustable.

Adjustable extremely large mirror for a vehicle