A link referral system includes a classification arrangement for classifying Web pages that the system retrieves over the World Wide Web. In assigning a link in a Web page to a particular classification, the classification arrangement originally establishes the classification using the name for the particular section of the Web page in which the link is located. Using statistical analysis of the occurrence of related links within sections of a number of diverse Web pages, some of which are named sections, the system creates classifications of links under both named classifications as well as anonymous classifications of links that co-occur with a high degree of probability. To minimize errors in the statistical analysis, the classification arrangement determines whether different World Wide Web addresses (so-called "URL's) which are used to access the Web pages in fact identify the same Web page. The classification information is used to supplement Web pages retrieved by a client through the link referral system to indicate the availability of related link information from the link referral system. In addition, the link referral system can provide related link information to the client in response to requests, identifying particular links or classifications, from the client.

The World Wide Web, together with other resources available over the Internet, provide a mechanism by which users, using computers or other information access devices, can obtain large amounts of information about a wide variety of subjects from a large number of information providers. Generally, information provided by information providers is in the form of "Web pages," generally in HTML (HyperText mark-up language) format, which is a text-based format that describes how the respective Web page is to be displayed by the user's computer, and provides textual information, typically in ASCII form, and graphical information generally in a compressed format such as "GIF" or "JPEG." In addition, a Web page will typically have HyperText-like "links" to other Web pages which may be provided by the same provider as the one Web page, as well as other Web pages which may be provided by other information providers. Typically, the links to Web pages provided by other information providers will be those links which the provider of the one Web page knows about when the one Web page is originally generated or updated, and will likely not be an exhaustive and updated set of Web pages which may be available over the World Wide Web related thereto.

World wide web link referral system and method for generating and providing related links for links identified in web pages


A master slice type gate array has a plurality of block areas. Each block area includes a plurality of basic cells arranged in a matrix. Different block areas have transistors with different channel widths. Within each of the block areas, a plurality of basic cells are connected to one another through a wiring layer to form function cells. First layer wirings for the function cells are completed within an area between rows of power source wirings Vdd and Vss of the first layer in the transverse direction. Contacts for connecting the sources and drains of P- and N-channel type MOS transistors to the first layer wirings are arranged in rows. Even if the channel widths are changed, the position of the contacts for forming the function cells and the wiring pattern remain unchanged for every block. Therefore, the master slice type gate array can be optimized for various performance parameters such as speed, integration, power consumption and other factors. As a result, the number of steps required to arrange the function cells can be reduced.

1. Field of the Invention
The present invention relates to a master slice type integrated circuit system and particularly to such an integrated circuit system which can set the channel width of a transistor at the optimum level in a Large Scale Integration LSI chip for every block area thereof to optimize the speed, power consumption, integration and other factors depending on the circuit function. The present invention also concerns a method of making such an integrated circuit system.
2. Description of the Prior Art
A gate array, which is one form of the master slice type integrated circuit systems, comprises basic cells 2 disposed on the central area 1a of a chip 1 in the form of a matrix and input/output cells 5 disposed on the peripheral area 1b of the chip 1 in the form of a ring surrounding the basic cell matrix, as shown in FIG. 2.
Each of the basic cells 2 comprises a plurality of active elements. A plurality of such basic cells 2 are connected together by wiring to form a function cell having a logical function.
The input/output cells 5 disposed on the peripheral area 1b of the chip 1 also connected together by wiring to form an input/output function cell having a logical function. An area 4 between the central and peripheral areas 1a, 1b of the chip 1 serves as an exclusive wiring area for connecting the input/output cells 5 to the internal function cells.
In such a conventional sea-of-gate type gate array as shown in FIG. 2, the basic cells 2 have the same configuration throughout the chip, including the same channel widths Wp and Wn of the P- and N-channel type MOS transistors which define the basic cells 2.
For such a reason, the prior art is limited in that even if function blocks such as RAM, ROM and other blocks are to be formed, they must necessarily be composed of the basic cells of the same configuration. If a RAM is to be made, the area of a memory cell per one bit will be over ten times larger than that of the custom design. Since such a memory cell has its unnecessarily large capacitance, the entire LSI will have an increased power consumption. The formation of a large-capacity RAM in the sea-of-gate type gate array of the prior art is of almost no practical use in the viewpoint of economy such as integration, power consumption and others.
As a result of that the circuits have been increased in the scale, the efficiency of the gate array pursuing only higher wiring rate and speed is extremely inferior to that of an optimized custom chip which is designed to minimize a so-called speed/consumption impulse and to maximize the integration even if they have the same logical function.
It may be believed that this results from the highest priority of reduction of the time for delivery for producing many kinds of gate arrays with small production at the sacrifice of speed, power consumption and integration which should be primarily pursued in LSI.
On the other hand, it is said that in developing such system-on-silicon LSI, the number of gates for practically disposing function cells by such an automatic placement and routing as in the gate array without consideration of the floor plan is limited to twenty or thirty thousands.
It is thus predicted that such a large-scaled circuit as will be developed is in the form of a chip which includes a plurality of system clocks, bus lines, RAMs, ROMs, ALUs and registers through the entire system and further has various different logic circuits. However, we cannot adopt a full custom design which provides different channel length and width of transistors for every function cell to optimize the speed, integration and power consumption for every function block.
This is because the specification and design of the system will necessarily be changed during development of such a large-scaled circuit. In such a case, the production of LSI must basically be restarted from the first step. This leads to the delayed time for delivery and associated cost which are several times larger than those of a gate array in which the specification thereof can be changed only by changes of the wiring step.
Techniques for forming MOS transistors having different channel widths and transistor sizes in one LSI chip are disclosed in Japanese Patent Application Laid-Open No. 58-51536 and Japanese Patent Application Laid-Open Nos. 3-145762, 2-268464 and 5-48050.
In the technique of Japanese Patent Application Laid-Open No. 58-51536, gate electrodes 402 are formed on the upper layers of N- and P-type diffusion regions 400, 401 to form MOS type transistors, as shown in FIG. 18. The MOS type transistors are different in channel width W from one another in the LSI chip.
According such a technique, however, the patterns of the wiring layers (not shown) formed on the upper layers of the gate electrodes 402 are also variable. When the gate electrode 402 is to be connected to the wiring layer on the upper layer thereof according to the prior art shown in FIG. 18, contacts must be formed on enlarged area portions 402a and 402b formed outside of the N- and P-type diffusion regions 400, 401 at the opposite ends of the gate electrode 402. When the channel widths W are to be increased, the positions of the enlarged area portions 402a, 402b must be placed outside of the N- and P-type diffusion regions 400, 401.
According to the invention of Japanese Patent Application Laid-Open No. 58-51536, therefore, the positions of contacts and the patterns of the wiring layers are variable if it is particularly wanted to increase the channel width W, For such a reason, the wiring step including the design of exposure mask is required to be re-designed.
In the technique of Japanese Patent Application Laid-Open No. 3-145762, two smaller P-type diffusion regions 410 and two smaller N-type diffusion regions 411 are formed with gate electrodes 412 being formed on the upper layers of the respective diffusion regions 410 and 411 to provide first basic cells, as shown in FIG. 19. A common gate electrode 422 is formed on the upper layers of larger N- and P-type diffusion regions 420, 421 to provide a second basic cell as shown in FIG. 20. Thus, two types of MOS transistors having different channel widths are formed.
Also in the invention of Japanese Patent Application Laid-Open No. 3-145762, however, the positions of the enlarged area portions 412a and 422a must similarly be changed if it is wanted to increase the channel widths of FIGS. 19 and 20. The contact positions and wiring patterns must also be changed.
The invention of Japanese Patent Application Laid-Open No. 2-268464 forms a common gate electrode over four diffusion regions 410 and 411 shown in FIG. 19. Basically, this is of the same structure as that of the first basic cell disclosed in the Japanese Patent Application Laid-Open No. 3-145762.
In the usual steps of designing and producing such a LSI, the channel width of the MOS transistor must frequently be changed due to the change of fan-out resulting from the logical simulation. Even if the channel width or transistor size is to be optimized for every design as in the aforementioned three proposals, the change of channel width is necessarily associated with the designing and producing steps. This cannot practically be accomplished if the wiring step is greatly changed.
According to the invention of Japanese Patent Application Laid-Open No. 5-48050, P- and N-type diffusion regions having different channel widths are juxtaposed in one direction. When the contact positions and wiring patterns are changed, a MOS transistor having an appropriate one of the channel widths is formed. This invention greatly reduces the efficiency of gate utilization, since the number of wiring steps corresponding to the number of channel widths is required, and there is always some diffusion regions having unnecessary channel widths.

Master slice type integrated circuit system having block areas optimized based on function


In a SDRAM, a switch circuit is provided between a memory circuit and a data output circuit. The switch circuit provides data read out from the memory circuit to the data output circuit in a normal operation, and provides a count value of an up/down counter in a DLL circuit to the data output circuit when in a test operation. By monitoring output signals in the test operation, testing of whether the DLL circuit is proper or not can be carried out easily and correctly.

1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a semiconductor device operating in synchronization with an external clock signal.
2. Description of the Background Art
In accordance with the increase in the speed of the memory system, the standard for the input/output timing of signals has become extremely stringent in semiconductor memory devices such as a SDRAM.
In a SDRAM, an internal clock signal in synchronization with an external clock signal is generated by a DLL circuit. That internal clock signal is employed as the trigger signal of the output of data and a strobe signal thereof. The DLL circuit includes a variable delay circuit delaying an external clock signal to generate an internal clock signal, an I/O replica circuit delaying the internal clock signal by a delay time obtained taking into consideration the input path of the external clock signal and the data output path to generate a dummy clock signal, and a phase comparator comparing the phases between the external clock signal and the dummy clock signal to control the delay time of the variable delay circuit according to the comparison result. Accordingly, the output timing of the data and the strobe signal thereof can be set in complete synchronization with the external clock signal.
Although the DLL circuits plays an important role in a SDRAM, the operation state of a DLL circuit could be monitored only indirectly by the output data and the strobe signal.
However, the DLL circuit could not be tested properly since the effect of the circuit block other than the DLL circuit cannot be removed.
In view of the foregoing, a main object of the present invention is to provide a semiconductor device that can have testing of the internal clock generation operation carried out easily and correctly.
According to an aspect of the present invention, a semiconductor device includes a variable delay circuit generating an internal clock signal in synchronization with an external clock signal, a phase comparator comparing phases of an external clock signal and an internal clock signal to output first and second control signals to increase/decrease the delay time of the variable delay circuit, an up/down counter counting the number of times the first and second control signals are output, an internal circuit carrying out a predetermined operation in synchronization with an internal clock signal, and an output circuit providing the signal of the internal circuit outside when in a normal operation and providing the count value of the up/down counter outside when in a test mode. Therefore, the operation of internal clock generation can be tested easily and correctly by monitoring the output signal of the output circuit during testing.
Preferably, the delay time of the variable delay circuit is controlled by the count value of the up/down counter. In this case, the structure is simplified.
Also preferably, the semiconductor device further includes a shift register controlling the delay time of the variable delay circuit by the output signal of a plurality of registers. In this case, the delay time of the variable delay circuit can be controlled easily.
Also preferably, each of the plurality of registers at the first stage side of the plurality of shift registers retains a signal of the first logic. Each of the other registers retains a signal of the second logic. In this case, the delay time of the variable delay circuit is determined by the number of registers retaining the signal of the first logic.
Also preferably, one of the plurality of registers of the shift register retains a signal of the first logic. Each of the other registers retains a signal of the second logic. In this case, the delay time of the variable delay circuit is determined by the position of the register retaining the signal of the first logic.
Also preferably, the internal circuit is a memory circuit. The output circuit includes a switch circuit that passes data read out from the memory circuit in a normal operation mode and that passes the count value of the up/down counter when in a test mode, and a data output circuit providing outside the read out data and the count value passing through the switch circuit. In this case, the operation of the internal clock generation of the semiconductor memory device can be tested easily and correctly.
According to another aspect of the present invention, a semiconductor device includes a variable delay circuit generating an internal clock signal in synchronization with an external clock signal, a phase comparator comparing phases of an external clock signal and an internal clock signal to output first and second control signals to increase/decrease the delay time of the variable delay circuit, a shift register controlling the delay time of the variable delay circuit according to the output signal of a plurality of registers, an internal circuit carrying out a predetermined operation in synchronization with an internal clock signal, and an output circuit providing a signal of the internal circuit outside when in a normal operation mode, and providing the output signal of at least one register of each group outside when in a test mode. By monitoring the output signal of the output circuit in the test mode, the operation of the internal clock generation can be tested easily and correctly.
Preferably, the output circuit provides the output signals of the plurality of registers divided for output over a plurality of times in a time-divisional manner. In this case, the number of output signals per one time can be reduced. Therefore, the signals of all the registers can be output even when the number of signals that can be output at one time from the output circuit is smaller than the number of registers.
Also preferably, the output circuit provides the output signal of a preselected register of each group in a test mode. In this case, the signal of one register out of each group is output. Therefore, the number of output signals per one time can be reduced.
Also preferably, the output circuit provides the output signals of a plurality of preselected registers out of a plurality of groups divided for output over a plurality of times in a time-divisional manner. In this case, the number of output signals per one time can further be reduced.
Also preferably, the semiconductor device further includes a first logic circuit provided corresponding to each group to generate an OR, AND or exclusive-OR signal of the output signals of the plurality of registers belonging to a corresponding group. The output circuit provides the output signal of each first logic circuit in a test mode. In this case, the group corresponding to the head bit can easily be identified.
Also preferably, the output circuit provides the output signals of the plurality of logic circuits divided for output over a plurality of times in a time-divisional manner. In this case, the number of output signals per one time in the test mode can be reduced.
Also preferably, the plurality of registers of each group are further divided into a plurality of sub-groups. A determination circuit determines whether the logic of the output signal of the plurality of registers of each group matches or not, and selects the group does not match. The output circuit provides the output signal of at least one register of each sub-group belonging to the group selected by the determination circuit in a test mode. In this case, more detailed information can be obtained of the position of the head bit.
Also preferably, the test is divided into first and second tests. The output circuit provides the output signal of at least one register of each group in the first test mode, and provides the output signal of at least one register of each sub-group belonging to the group selected by the determination circuit in the second test mode. In this case, the number of output signals per one time can be reduced in the test mode.
Also preferably, the output circuit provides the output signals of the plurality of registers of each sub-group belonging to the selected group divided for output over a plurality of times. In this case, the number of output signals per one time can be further reduced.
Also preferably, the output circuit provides the output signal of a preselected register in each sub-group belonging to the selected group in a test mode. In this case, the number of output signals per one time in the test mode can be reduced.
Also preferably, the output circuit provides the output signals of a plurality of preselected registers out of a plurality of sub-groups divided for output over a plurality of times in a time-divisional manner. In this case, the number of output signals per one time can further be reduced.
Also preferably, each of the plurality of registers of the first stage side out of the plurality of registers of the shift register retains a signal of the first logic. Each of the other registers retains a signal of the second logic. In this case, the delay time of the variable delay circuit is determined by the number of registers retaining the signal of the first logic.
Also preferably, one register of the shift register retains the signal of the first logic. Each of the other registers retains the signal of the second logic. In this case, the delay time of the variable delay circuit is determined by the position of the register retaining the signal of first logic.
Further preferably, the internal circuit is a memory circuit. The output circuit includes a switch circuit that passes the data read out from the memory circuit in a normal operation mode, and passes the output signal of at least one register of each group in the test mode, and a data output circuit providing the read out data and the output signal of the register passing the switch circuit outside. In this case, the operation of the internal clock generation in the semiconductor memory device can be tested easily and correctly.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

Semiconductor device enable to output a counter value of an internal clock generation in a test mode


A process for improving the flocculation of suspended solids in a Bayer process liquor in a primary settler stage. The method includes the step of adding to a primary settler feed from about 1 to about 100 parts per million of a composition including a non-inverted, water-continuous polymer, said polymer being hydrolyzable in a Bayer process liquor to an acid form, said acid form being an active red mud flocculant.

1. Field of the Invention
The present invention is directed to the clarification of red mud-containing liquors; particularly the primary settler liquor generated in the Bayer process for the recovery of alumina from bauxite ore.
2. Description of the Prior Art
In the Bayer process for the production of alumina, bauxite ore is pulverized, slurried in water, and then digested with caustic at elevated temperatures and pressures. The caustic solution dissolves oxides of aluminum, forming an aqueous sodium aluminate solution. The caustic-insoluble constituents of bauxite ore (referred to as "red mud") are then separated from the aqueous phase containing the dissolved sodium aluminate. Solid alumina trihydrate is precipitated out of the solution and collected as product.
In more detail, the pulverized bauxite ore is fed to a slurry mixer where a water slurry is prepared. The slurry makeup water is typically spent liquor (described below) and added caustic. This bauxite ore slurry is then diluted and passed through a digester or a series of digesters where, under high pressure and temperature, about 98% of the total available alumina is released from the ore as caustic-soluble sodium aluminate. After digestion, the slurry then passes through several flash tanks wherein the pressure of the digested slurry is reduced from several atmospheres to one atmosphere and the temperature of the slurry is reduced from about 400.degree. F. to about 220.degree. F.
The aluminate liquor leaving the flashing operation contains from about 1 to about 20 weight percent solids, which solids consist of the insoluble residue that remains after, or is precipitated during, digestion. The coarser solid particles may be removed from the aluminate liquor with a "sand trap" cyclone. The finer solid particles are generally separated from the liquor first by settling and then by filtration, if necessary. Any Bayer process slurry taken from the digesters through any subsequent dilution of the slurry, including the flash tanks, but before the primary settler, is referred hereinafter as the primary settler feed. The slurry of aluminate liquor leaving the flash tanks is diluted by a stream of recycled wash overflow liquor.
Normally, the primary settler feed is thereafter fed to the center well of the primary settler, where it is treated with a flocculant. As the mud settles, clarified sodium aluminate solution, referred to as "green" or "pregnant" liquor, overflows a well at the top of the primary settler and is collected. This overflow from the primary settling tank is passed to the subsequent process steps.
The clarity of the primary settler overflow is crucial to the efficient processing of alumina trihydrate. If the aluminate liquor overflowing the settler contains an unacceptable concentration of suspended solids (at times from about 10 to about 5,000 mg of suspended solids per liter), it must be further clarified by filtration to give a filtrate with no more than about 10 mg suspended solids per liter of liquor. The treatment of the liquor collected after the primary settlement to remove any residual suspended solids before alumina trihydrate is recovered is referred to as a secondary clarification stage.
The clarified sodium aluminate liquor is seeded with alumina trihydrate crystals to induce precipitation of alumina in the form of alumina trihydrate, Al(OH).sub.3. The alumina trihydrate particles or crystals are then separated from the concentrated caustic liquor, and the remaining liquid phase, the spent liquor, is returned to the initial digestion step and employed as a digestant after reconstitution with caustic.
In another section of the Bayer circuit, the settled solids of the primary settler ("red mud") are withdrawn from the bottom of the settler ("underflow") and passed through a countercurrent washing circuit for recovery of sodium aluminate and soda. Overflow water from this washing circuit is recycled as primary settler feed and dilutes the slurry as it leaves the flash tanks. The efficient recovery of soda and sodium aluminate is one important way operators reduce costs and increase production.
The partial separation of the red mud solids from the pregnant liquor in the primary settler is expedited by the use of a flocculant. This initial clarification of the pregnant liquor is referred to as the primary settler stage. Flocculating agents, such as inverted latex polymers and starch, improve the separation of insolubles by increasing the rate at which the solids settle, by reducing the amount of residual solids suspended in the liquor, and by decreasing the amount of liquor in the settled solids phase. Flocculation performance is highly important in the primary settlement stages. Red muds are comprised chiefly of iron oxides (at least about 50 weight percent of the red mud solids), together with silicon oxides, calcium oxides, sodium alumino-silicates, titanium oxides and other material, and commonly represent from about 5 to about 50 weight percent of the materials of the bauxite ore. Generally these muds are comprised of very fine particles, which hinder the desired rapid and clean separation of red mud particles from the solubilized alumina liquor. If the rate of separation is slow, output is materially diminished and overall process efficiency is impaired. If the separation is not clean, the resultant solubilized aluminate liquor will require a more extensive treatment to remove residual solids, and/or the alumina trihydrate recovered will contain levels of impurities that are undesirably high for many end-uses.
Starch and inverted latex polymers are used to flocculate the suspended red mud. These flocculating agents are added in the primary settler. Starch is added to improve the clarity of the liquor overflow. However, starch disadvantageously produces a red mud which has poor rheology, and, hence, has undesirable underflow characteristics. In more detail, the red mud is removed to a wash stage via an underflow mechanism. In the wash stage, sodium aluminate and soda are recovered from this red mud. When starch is used, a mud is produced which has poor rheology and poor underflow characteristics. If not diluted, the underflow will damage plant equipment. To overcome this problem, operators have decreased the percent solids in the underflow to make it more manageable. This, however, deceases the efficiency of the soda and sodium aluminate recovery in the wash stage.
When latex polymers are used, the latex polymers must be diluted either at the process facility or prior to shipping. If the latex polymers are diluted prior to shipping, shipping costs are dramatically increased. If the latex polymers are diluted at the processing facility, equipment must be available at the facility to perform the dilution. Furthermore, other than the dilution step, the latex polymers must be inverted prior to application so that the latex polymers are contained in the water phase of the emulsion. If latex polymers are added neat (non-inverted), the non-inverted, oil phase latex polymers will not disperse in the Bayer liquor, and the oil phase will plug injection equipment. Accordingly, in light of the above problems with latex polymers, it would be advantageous to either eliminate the need for latex polymers or decrease the amount of latex polymers needed to adequately flocculate red mud solids in a Bayer process liquor.
Accordingly, it would be advantageous to provide a new flocculating agent which would expedite the separation of the red mud solids from the pregnant liquor, increase the clarity of liquor overflow, decrease latex flocculant usage, and eliminate starch.


The photoresist composition of the present invention includes a solvent mixture, a resin, a photo acid generator, and a quencher, the solvent mixture comprising a first solvent containing an ether compound and a second solvent having a polarity stronger than the first solvent, wherein an amount of the first solvent is in a range of about 61% to about 79% by weight, and an amount of the second solvent is in a range of about 21% to about 39% by weight based on a total weight of the solvent mixture.

1. Field of the Invention
The present invention generally relates to a photoresist composition, and a method of forming a pattern on a semiconductor device using the same. More particularly, the present invention generally relates to a photoresist composition for forming a photoresist film on a substrate, and a method of forming a photoresist pattern by a photolithography process.
A claim of priority is made to Korean Patent Application No. 2004-37634 filed on May 27, 2004, the content of which is herein incorporated by reference in its entirety.
2. Description of the Related Art
In general, a semiconductor device is fabricated through a series of unit processes such as a layer coating, a patterning of the layer, and a metal wiring.
In general, a semiconductor device pattern is formed by a photolithography process. The photolithography process generally includes a cleaning process, a surface treatment process, a photoresist coating process, an aligning process, an exposing process, and a developing process.
During the photoresist coating process, a photoresist material is coated on a substrate such as a silicon substrate to form a photoresist film. In the aligning process, a photo mask on which an electronic circuit pattern is formed is arranged over the photoresist film. During the exposing process, illuminating light having wavelength to which the photoresist film is sensitive thereto to cause a photochemical reaction is irradiated thereon. Molecular structures of the photoresist film are selectively changed in accordance with the irradiated illuminating light. Then the developing process selectively removes reacted portions of the photoresist film to thereby form a photoresist pattern.
In general, a photoresist material is classified as a positive type and a negative type in accordance with a molecular reaction to light irradiated thereto. When selected areas of the positive photoresist are exposed to light, high molecular compounds of the exposed portions are converted into low molecular compounds, which are more soluble to a developing solution than an unexposed portions thereof. The exposed portions of the photoresist are readily removed from the substrate.
In contrast, when selected areas of the negative photoresist are exposed to light, low molecular compounds are converted into high molecular compounds to thereby have lower solubility to a developing solution than unexposed portions. The unexposed portions of the photoresist are readily removed from the substrate. As a result, the exposed portions remain on the substrate, and the unexposed portions are removed from the substrate after the developing process to thereby form the photoresist pattern.
Subsequently, various underlying layers formed under the photoresist film are selectively removed using the photoresist pattern as an etching mask. Afterwards, the photoresist pattern is removed from the substrate to form a semiconductor pattern on the substrate.
A minimal line width of the photoresist pattern or the semiconductor pattern is determined in accordance with a resolution capability of an exposing system, and the resolution capability of the exposing system is determined by the wavelength of illuminating light. In general, if the resolution of the exposing system is high, the wavelength of the illuminating light is short. That is, a short wavelength of the illuminating light is required to form a fine photoresist pattern.
The resolution of the exposing system is determined by the following equation 1.R=K1NA/λ  (1)
Wherein λ denotes a wavelength of illuminating light; R denotes a resolution limit of the exposing system; K1 denotes a proportional constant; and, NA denotes a numerical aperture for a lens used in the exposing system. According to equation (1), wavelength λ of the illumination light and proportional constant K1 must be small, and the numerical aperture of the lens must be large to increase the resolution of the exposing system. Among these factors, changing wavelength λ is most widely utilized to increase the resolution of the exposing system.
Examples of the illumination light include a G-line light having a wavelength of about 436 nm, an I-line light having a wavelength of about 365 nm, a deep ultraviolet (DUV) light having a wavelength of about 248 nm, and an argon fluoride (ArF) light having a wavelength of about 193 nm. Although the DUV light includes a KrF light as well as the ArF light in view of the optical technology, the KrF light will be referred to as the DUV light in the present specification. The KrF light has a wavelength of about 248 nm.
U.S. Pat. Nos. 6,121,412 and 5,521,052, for example, disclose photoresist compositions having good solubility and maintenance stability without precipitation of photosensitive ingredients.
In general, a photoresist composition includes a polymer, a quencher, a photo acid generator, and a photoresist solvent.
The polymer, which is widely referred to as a resin, is a chemical compound in which two or more monomers combine to form compound molecules that contain repeating structural units. The polymer is the residual substance of the photoresist pattern remaining after the developing process. Light dissolves photo acid generator in the photoresist solvent. The photo acid functions as a catalyst during a chemical reaction to convert the molecular structure of the polymer. The photoresist solvent is a mixture of polar and non-polar solvents. The photoresist solvent also controls viscosity of the photoresist composition.
DUV light and ArF light have been frequently utilized to manufacture highly integrated and high performing semiconductor devices. As described above, the photoresist composition sensitive to the DUV light (DUV photoresist composition) is quite different from the photoresist composition sensitive to the ArF light (ArF photoresist composition). However in general, the solvents used for the DUV photoresist composition and the ArF photoresist composition are substantially the same.
The ArF photoresist composition has relatively poor solubility as compared with the DUV photoresist composition when using the same solvents, because the ArF photoresist composition is hydrophobic. Accordingly, when the ArF photoresist film is exposed to air, the resin dissolved in the solvent precipitates in very short time. The precipitated resin gathers around an injection nozzle and is injected onto a surface of a substrate during a coating process. The precipitated resin causes defects on the substrates.
The precipitated resin is a problem that must be solved to further the developments in the manufacturing of the semiconductor device.

Photoresist composition and method of forming a pattern using the same


A system and method that enforces one or more policy rules on user-allocated bandwidth portions of the overall system bandwidth, for example in an optical fiber transmission system. The policy rules may limit, for example, the range of optical wavelengths, the acceptable range on the output-power-spectral density and/or the total per-band optical power within the user-allocated bandwidth that a user may provide on the system. The system may include one or more user control units that receives respective user output signals and applies all policy rules. The resulting optical output(s) of the UCU(s) may be provided an optical transmission path for transmission to a receiving terminal. In the receiving terminal, one or more UCU(s) may apply receiver policy rules, for instance by limiting the range of wavelengths transmitted to a receive subsystem. In addition, the system may be configured to dynamically add and/or remove loading signals to the transmitted signal in response to changes in loading of the user-allocated portions of the system bandwidth, e.g. through dropping or adding of channels by a user or by equipment failures.

To maximize the transmission capacity of an optical fiber transmission system, a single optical fiber may be used to carry multiple optical signals in what is called a wavelength division multiplexed system (hereinafter a WDM system). The multiple optical signals may be multiplexed to form a multiplexed signal or WDM signal with each of the multiple signals being modulated on separate channels. Each channel may be at an associated wavelength centered on a defined frequency grid, e.g. according to a channel plan established by the International Telecommunications Union (ITU). The range of wavelengths that may be transmitted on the system is known as the system bandwidth. Systems may utilize their system bandwidth to carry a desired number of channels with desired modulation format, channel plan and bit rate.
In a known configuration, an owner of an optical system may possess all necessary transmission equipment and sell a defined amount of capacity on the system to customers. For example, the owner might sell a defined number of channels at a defined bit rate and channel plan on the system. In such an arrangement, the owner of the system would control all aspects of the physical layer, including, for example, the system channel plan, the channel power, modulation format, bit rate, etc.
Recently, however, there has been interest in a system wherein the owner of the system would sell a defined portion of the system bandwidth to each customer. In this configuration, each customer would have partial control over the physical layer including the type and configuration of equipment used to transmit signals in their portion of the system bandwidth. Each customer would also have control over certain transmission characteristics within their portion of the system bandwidth. Different customers, for example, may establish different channel plans, modulation formats, bit rates, etc. within their portions of the system bandwidth. This overall system configuration gives customers control over adding, removing and/or reconfiguring services within their bandwidth and for managing loading in the unoccupied portions of their bandwidth.
A challenge associated with such a system is that physical layer changes made by one customer within their portion of the system bandwidth may affect transmission performance in other portions of the system bandwidth owned by other customers. For example, a customer may provide a contaminated input spectrum with broadband noise outside of their allocated bandwidth that impacts other customers. Also, since customers could drop or add channels at any time, the corresponding change in path average power, peak power and optical signal-to-noise ratio (OSNR) of surviving channels may fundamentally affect the Q-factor performance of other customers. On receiver side, the customers' receiving amplifier gain and OSNR may be affected by presence of other customer's data. In addition to performance issues, security issues may arise if a customer receives signals outside of their allocated bandwidth.

System and method for applying system policies in an optical communication system having user-allocated bandwidth

TYCO ELECTRONICS SUBSEA COMMUNICATIONS LLC


A piezoelectric ceramic transformer made from a piezoelectric ceramic material stacked in a multilayer package which has a driving section 502 formed by alternately stacking piezoelectric ceramic layers polarized in a direction of thickness of the piezoelectric plate. The driving section 502 has internal interdigitated electrode layers 504A, 504B for causing piezoelectric vibration by a driving voltage applied to an input terminal (Vin). A first driven section 506, also made from piezoelectric ceramic layers polarized in the longitudinal direction of the piezoelectric plate, for generating a first output voltage (Vout1) at a first output by the piezoelectric vibration transmitted from the driving section 502. A second driven section 510, made from piezoelectric ceramic layers polarized in the thickness direction of the piezoelectric plate, for generating a second output voltage (Vout2) at a second output by the piezoelectric vibration transmitted from the driving section 502. Thus, a piezoelectric ceramic multilayer transformer with a multiple output is created.

Piezoelectric transformers utilizing the piezoelectric effect are known in the art. A piezoelectric transformer can be defined as a passive electrical energy-transfer device or transducer employing the piezoelectric properties of a material to achieve the transformation of voltage or current or impedance. Piezoelectric transformers have recently replaced wound-type electromagnetic transformers for generating high voltage in the power circuits for certain electronic applications. These piezoelectric transformers offer numerous advantages over ordinary electromagnetic transformers including a compact and slim shape, rugged construction, and high reliability in a comparably smaller package.
Piezoelectric ceramic transformers are now finding applications in a variety of applications including photocopiers, backlights of liquid crystal displays (LCDs), flat panel displays (FPDs), power converters, CRT displays, field emission displays (FEDs), and the like. FIG. 1 shows the construction of a Rosen-type piezoelectric transformer, a representative example of a piezoelectric transformer of the prior art.
FIG. 1 shows a standard multilayer ceramic piezoelectric transformer 100 formed from a co-fired ceramic package 102 interspersed with layers of a conductive metallization electrode pattern 104. Although the package is made from layers of a green ceramic tape, upon firing the package sinters into a single ceramic structure. Consequently, all FIGS. will show the fired package and the individual layers of green tape will not be shown. A voltage (Vin) is applied across the electrode layers 104 creating a potential difference across the primary region 106. The primary region 106 is polarized in the direction of its thickness, as indicated by the arrows between the electrode layers 104 shown in FIG. 1. Polarization is a process wherein a very substantial direct current (DC) voltage, in the range of 4 kV/mm, is applied to the ceramic in order to give the material its piezoelectric properties. Similarly, a portion of the piezoelectric transformer 100 indicated by reference numeral 108 is a power generating or secondary section. An output (Vout) is formed on the end face 110 of transformer 100 corresponding to the power generating section 108. Note that the end face 110 is metallized with a conductive coating, as is the top surface 112 on the primary section 106 end of transformer 100. Electrode layers 104, internal to the multilayer package, are also made from a conductive coating material. The power generating section 108 is polarized in the lengthwise direction, as indicated by an arrow in FIG. 1.
With reference to FIG. 1, the basic operation of a piezoelectric transformer can be understood. When a voltage is applied to the primary section 106 of the piezoelectric transformer, the resulting electric field causes a vertical vibration due to a change in the thickness of the driving section 106 of the transformer. This vertical vibration results in a horizontal vibration in the lengthwise direction (also known as the piezoelectric transverse effect 31 mode) along the entire length of the transformer 100. In the power generating section 108 (also known as the secondary section), a voltage having the same frequency as that of the input voltage (Vin) is derived through the output electrode (Vout) in accordance with a piezoelectric effect wherein a potential difference occurs in the polarizing direction due to the mechanical strain in the polarizing direction. At this time, if the driving frequency is set to be the same as the resonant frequency of the piezoelectric transformer, a very high output voltage can be obtained. Stated another way, by applying an alternating current through the primary section 106 of a piezoelectric material, its thickness characteristics will vary, which through coupling, causes a change in length of the secondary section 108, which results in a change in the electrical output caused by an electromechanical effect.
FIG. 2 shows another prior art piezoelectric transformer in which the primary 206 and the secondary 208 sections of the piezoelectric ceramic plates are "stacked" vertically. Referring to FIG. 2, a stack-type transformer 200 is provided. Once again, a voltage (Vin) is applied to a primary 206 section through a series of metallized electrode layers 204, which in turn results in a high output (Vout) in the secondary 208 section due to a piezoelectric effect. Top surface 210 is covered with a conductive coating, and side surfaces 212 and bottom surface 214 are selectively metallized to achieve the desired transformer properties. In stacked transformer 200, all layers are polarized in the thickness direction as is designated by the arrows shown in FIG. 2.
One problem with the present technology is that a single piece of electronic equipment may contain multiple transformers, each with its own drive circuit, and each with its own output voltage. Thus, by providing multiple outputs in a single transformer design, a substantial reduction in both size and weight may be realized. Additionally, greater integration is possible in a multiple output transformer having a single drive circuit with a small footprint. Finally, by decreasing the overall number of transformers in a single piece of electronic equipment, a cost savings is also obtained. Another problem with these transformer designs, and all other piezoelectric transformers in the field, is the fact that they have only a single driven section (power generating section) resulting in only a single output voltage. However, system designers for various applications are demanding multiple output voltage capabilities. A novel ceramic piezoelectric transformer structure which offers multiple driven sections resulting in multiple outputs wherein a single a input voltage drives two or more output voltages would be considered an improvement in the art.

Piezoelectric transformer with multiple output


A voltage regulator has a sense transistor through which a sense current flows in accordance with a magnitude of a load current, and a sense resistor through which the sense current flows. A control transistor controls the load current in accordance with a voltage across the sense resistor. A current measurement transistor measures the sense current flowing through the sense transistor and is disposed adjacent to the sense transistor. A measuring characteristics transistor measures characteristics of the control transistor and is disposed adjacent to the control transistor.

1. Field of the Invention
The present invention relates in general to a voltage regulator, and more particularly to an overcurrent protection circuit for a voltage regulator.
2. Description of the Related Art
FIG. 3 shows a configuration of a conventional overcurrent protection circuit for a voltage regulator. A reference voltage source 101 supplies a constant-voltage Vref to an inverted input terminal of an error amplifier 102. An output of the error amplifier 102 is connected to a gate of a PMOS output driver transistor 105, and is also connected to a gate of a first PMOS sense transistor 106, a gate of a second PMOS sense transistor 115, and a drain of a PMOS transistor 107 of an overcurrent protection circuit 103. A source of the PMOS output driver transistor 105 is connected to an input terminal IN and a drain of the same is connected to an output terminal OUT. A load resistor 114, a capacitor 113, and a voltage dividing circuit 104 consisting of resistors 111 and 112 are connected to the output terminal OUT. The voltage dividing circuit 104 supplies a divided voltage of an output voltage VOUT to a non-inverted input terminal of the error amplifier 102.
The overcurrent protection circuit 103 includes: the first and second PMOS sense transistors 106 and 115; the PMOS transistor 107; an NMOS transistor 108; resistors 109 and 110; first, second, and third PMOS level shifters 120, 119, and 118; and NMOS transistors 116 and 117 constituting a current mirror circuit. Here, the PMOS output driver transistor 105 has a gate width which is several times (e.g., 100,000 times) as large as that of the first PMOS sense transistor 106 for monitoring a load current Iout of the voltage regulator. Also, the PMOS output driver transistor 105 is designed so as to show a mirror relationship with the first and second PMOS sense transistors 106 and 115.
The conventional overcurrent protection circuit for a voltage regulator shown in FIG. 3 operates as follows.
If an amount of load current Iout supplied by the PMOS output driver transistor 105 to the load 114 is little, a current Isense flowing to the first PMOS sense transistor 106 is small in proportion to it. Thus, a voltage difference generated across the resistor 109 is also small and the NMOS transistor 108 is in a non-conductive state. Therefore, since a current does not flow to the NMOS transistor 108, a voltage difference is not generated across the resistor 110 and the PMOS transistor is also in a non-conductive state.
However, when a load current Iout supplied by the PMOS output driver transistor 105 to the load 114 increases, a current Isense flowing to the first PMOS sense transistor 106 also increases in proportion to it and a voltage generated across the resistor 109 also increases. Thus, the NMOS transistor 108 is in a conductive state. When the NMOS transistor 108 becomes conductive and a voltage difference generated across the resistor 110 increases, the PMOS transistor 107 conducts to increase a gate voltage of the PMOS output driver transistor 105. Thus, a driving ability of the PMOS output driver transistor 105 decreases and an output voltage OUT falls. In this way, elements are prevented from being destroyed by an overload current.
Moreover, operating states of the PMOS output driver transistor 105 and the first PMOS sense transistor 106 are usually made identical to each other based on an operation of a circuit including the second PMOS sense transistor 115, the first, second, and third PMOS level shifters 120, 119, and 118, and the NMOS transistors 116 and 117 constituting the current mirror circuit. In this case, a ratio between a value of a current caused to flow through the PMOS output driver transistor 105 and a value of a current caused to flow through the first PMOS sense transistor 106 is determined based on a transistor size ratio between the PMOS output driver transistor 105 and the first PMOS sense transistor 106. Thus, it is possible to set a load current Ipro permitting the overcurrent protecting function to be valid (refer to JP 2003-29856 A (pp. 1 to 6, and FIG. 1)).
However, the conventional overcurrent protection circuit for a voltage regulator involves a problem in that dispersion occurs in the load current Ipro permitting the overcurret protecting function to be valid due to manufacture dispersion. That is, a threshold voltage value Vth of the NMOS transistor 108 disperses. Moreover, the transistor size ratio between the PMOS output driver transistor 105 and the first PMOS sense transistor 106 also disperses due to the manufacture dispersion. Consequently, as shown in FIG. 4, the load current Ipro permitting the overcurrent protecting function to be valid greatly disperses from a target load current value Itype.

Voltage regulator having overcurrent protection circuit and method manufacturing voltage regulator


An apparatus for a mobile floor standing structure with a wheeled base, attached to a dry-erase board is described. The dry erase board can be secured to the stand at a vertical orientation to give rise to a vertically standing writable dry-erase board. Alternatively, the dry-erase board being pivotably oriented form a vertical position to a horizontal position to yield into a writable dry erase board in a table configuration. The wheeled base adds ease in maneuverability and portability of the apparatus.

Prior art examples of combination black board and table described in U.S. Pat. No. 948,905 (Snyder), a combination blackboard and folding table described in U.S. Pat. No. 2,397,405 (Burkeman), a combined table and drawing easel described in U.S. Pat. No. 2,607,646 (West camp), a convertible table and easel described in U.S. Pat. No. 6,575,103 (Holdredge) and a folding table described in U.S. Pat. No. 7,634,968 (Cornelius). The disadvantages associated with most prior art combination table is the complicated and expensive construction or assembly and the swivel mechanism being mechanically susceptible and therefore not representing a robust operational system.
Accordingly, there is a need for a portable, mobile, floor standing structure capable of being attached to a dry-erase board and being capable of pivoting the dry-erase board from a vertical position to a horizontal position to be used as a dry-erase board table in a convenient manner.

System, apparatus and methods for a mobile pivotable dry erase board


A rail for fastening installations in an aircraft, the rail including a rail base section, a running-surface section that extends in a longitudinal direction with a running surface, and a connection section that connects the running-surface section to the rail base section at the face pointing away from the running surface. The running-surface section laterally on both sides, in each case spaced apart at a predetermined pitch, includes a multitude of projections projecting away from the connection section, each with a top that has substantially the same alignment as the running surface and a bottom that has an alignment that substantially is opposed to the alignment of the running surface. The bottom of the projections forms holding surfaces for holding a fitting. The rail is attached to a floor of the aircraft.

The present invention relates to a device, and in particular to a rail, for the positioning and locking of elements and a corresponding fitting, and in particular to a rail and an associated fitting, which make possible improved positioning of elements in, for example, an aircraft.
For fastening installations or elements in an aircraft, in aircraft, and in particular in aeroplanes, rail systems are used that make it possible to fasten, for example, seats to the floor of a passenger cabin and at the same time make it possible to vary the cabin configuration.
Rail configurations are known for the cabin region, in which rail configurations a rail with an elongated groove is provided, which at regular spacing comprises projections so that counterparts of fittings or of fastening elements can be inserted in the spaces of the projections. By being slid under the projections with subsequent locking, the fittings can be securely fastened. In the fastening elements or fittings, running surfaces or sliding surfaces are provided, on which the fastening element can slide in or on the rail in order to position the element to be installed before it is subsequently locked. Due to the small size of the sliding surfaces on the fittings, the reconfiguration characteristics of an installed seat in today's seat rail constructions are insufficient in that as a result of high point loads it is easily possible for damage to the rail surface to occur. Furthermore, locking in the direction of the longitudinal axis of the aircraft has hitherto been comparatively involved. Moreover, the use of lighter but also more brittle rail materials, for example for seat rails, in today's shape of the rails has a negative effect on the results of the dynamic seat tests.
Furthermore, rail arrangements from the region of the pilot seat configuration are known, in which the rail is essentially designed like a railway line with an enlarged head, wherein in a special region of the rail corresponding openings are provided so that precisely in this region fittings can be placed on the rail, by means of which fittings the pilot seat is then attached. In this arrangement the pilot seats, in contrast to cabin seats, are very often slid along the longitudinal axis of the aircraft, but without there being a possibility or requirement to be able to install or deinstall the seat at different positions of the rail. In other words, on a fastening rail for pilot seats there is only a single seat that can be placed in a fixed position on the seat rail and that can then be positioned on this seat rail in accordance with requirements. However, in a pilot seat rail the installation position of the seat is only in a single position on the entire rail so that the seat has to be brought precisely to this position in order to be able to be installed or deinstalled. This also takes place for reasons of safety so that while in the case of negligent locking the pilot seat can unintendedly slide, it cannot however become detached from the rail.

Rail for positioning and locking of elements, and a corresponding fitting


A row decoder that includes circuitry to provide a self-timed bootstrap signal. The self-timed bootstrap signal is generated in response to the selection of the row decoder. At the same time, a capacitive device is charged in order to bootstrap a word line. The self-timed bootstrap signal causes a clock generator circuit to output a clock signal that will be used to bootstrap the word line. The self-timed bootstrap signal may be generated by other row decoders. The generation of the self-timed bootstrap signal by a row decoder is responsive to any variations in that decoder, thus always providing an accurate and precise timing of the clock signal to be used for the bootstrapping.

Typical DRAMs (dynamic random access memories) have active cycles which include access cycles for accessing the memory cells and restore cycles for restoring data read from the memory cells. Following the active cycles, typically precharge cycles occur to precharge the bit and word lines of the memory array for the next active cycle. Row decoders generally provide the circuitry to precharge the word lines and to drive the word line voltages to access and restore addressed memory cells.
A typical memory cell configuration is shown in FIG. 1. A bit line 10 is coupled to a drain electrode of a transistor 12, illustratively an n-channel, enhancement mode field effect transistor. A gate electrode of transistor 12 is coupled to or formed by part of a word line 14. A source electrode of transistor 12 is coupled to one terminal of a capacitor 16. Another terminal of capacitor 16 is coupled to a constant voltage, VCP. Bit line 10 is typically coupled to a sense amplifier circuit (not shown). Word line 14 is typically coupled to a row decoder (not shown). Generally, an array of such cells is provided.
Capacitor 16 typically is charged to VCC to store a logical "one" and 0V for a logical "zero." To read from capacitor 16, bit line 10 is typically precharged to 1/2 VCC and word line 14 must be driven to a voltage greater than a threshold voltage above either the voltage stored in capacitor 16 or the precharge voltage of bit line 10, whichever is lower. VCP is typically 1/2 VCC.
Considering a DRAM having a 5 V power supply VCC, for example, if a "zero" (0 V) is stored in capacitor 16, word line 14 must be driven to at least one threshold voltage (.apprxeq.1 V) to turn transistor 12 on. If a "one" is stored in capacitor 16 (5 V), then the word line 14 must be driven to at least one threshold voltage greater than the precharge voltage of bit line 10. If bit line 10 is precharged to 2.5 V (1/2 VCC), then the word line should typically be charged to at least approximately 3.5 V.
After the memory cell is accessed and read, the data will be restored. In this case, word line 14 will be driven to a voltage that is at least one threshold voltage greater than VCC (5 V) to allow a full VCC (5 V) to be stored in capacitor 16 from bit line 10. Providing a voltage that is greater than the chip power supply is commonly done by the "bootstrapping" technique, well-known to the art.
Typically, when a 5 V DRAM is in an active cycle, word line 14 is driven as quickly as possible to VCC (5 V) for reading the memory cell. After the memory cell is read, the word line 14 is bootstrapped to a threshold voltage greater than VCC (5 V) for the restore cycle. Since the bootstrapping of word line 14 is not done during the critical access time of the memory cell, the timing of the bootstrapping is not critical. The timing that determines when word line 14 is driven from VCC to a voltage above VCC of the 5 V DRAM is typically generated by a conventional timer circuit that is not part of the row decoder configuration.
Progress has brought about decreased device sizes and geometries, and increased chip density. Typically, the smaller device size will not operate with a chip power supply of 5 V because it would damage the device. Therefore, these smaller devices use a lower power supply voltage, such as 3 V.
A memory cell like that shown in FIG. 1 for a 3 V DRAM would have bit line 10 precharged to 1.5 V (1/2 VCC). The voltage on capacitor 16 for a logic "one" will be 3 V (VCC). To read the logic "one" from capacitor 16, word line 14 must be driven to a voltage that is a threshold voltage greater than the precharged bit line voltage. To insure reliable reading of the memory cell, the word line voltage should be driven to approximately a full VCC (3 V).
An access time problem arises from these smaller device sizes of a 3 V DRAM that the 5 V DRAM may not have. The resistor-capacitor ("RC") characteristic of word line 14 causes a delay in word line 14 being driven to 3 V to read the memory cells. This delay may be seven or eight nanoseconds, and this is critical to access times. To overcome this delay problem, word line 14 is bootstrapped to a voltage greater than VCC, which shall be referred to as VCCP, to read the memory. One way to bootstrap word line 14 to VCCP is to use p- and n-channel transistors coupled to word line 14. VCCP may be provided by an on-chip charge pump. The p-channel transistor would have its source electrode coupled to VCCP, the drain electrode coupled to the word line 14, and the gate electrode coupled responsively to some internal signal within the row decoder (not shown). The n-channel transistor would have its drain coupled to word line 14, its source coupled to ground, and its gate coupled to some signal generated by the row decoder (not shown).
The p-channel transistor operates as a pull-up device that is turned on to pull word line 14 all the way to VCCP to read the memory cell. The transistor is then turned off after the memory cell data is read. The n-channel transistor operates as a pull-down device that is turned on to pull the word line to ground for the restore cycle. The problem with this approach is the p-channel transistor has less current drive capability than an n-channel transistor (of the same size) by approximately a factor of two. A very large p-channel transistor would have to be used to quickly drive the capacitance of word line 14.
An additional drawback to this approach is the p-channel transistor has to be laid out in a row pitch of a dynamic RAM which has very limited area. It is very difficult to lay out these p-channel transistors in the pitch and have them large enough to pull up word line 14 quickly. These transistors would consume a good deal of chip area.
FIG. 2 shows one prior art implementation of another bootstrap concept consisting of a generator 17, a predecoder 18 and a decoder 19. Generator 17 has a main input clock signal .phi.XG. Generator 17 also has various other inputs, and it outputs a master clock signal .phi.X+. Master clock signal .phi.X+ is boosted to VCCP to boost eventually a word line signal WL (an output from decoder 19) to VCCP. The various other inputs are used, for example, to reset master clock signal .phi.X+ low, precharge generator 17, boost a node in generator 17 to VCCP and precharge generator 17 at the start of row address strobe ("RAS") high precharge periods.
Predecoder 18 receives, among other signals, a clock signal .phi.XDP to precharge circuitry in predecoder 18 to a high state, master clock signal .phi.X+ and address bits which are used to enable the output of a predecoded boosted clock signal .phi.X+.sub.i. The variable i represents, for example, an integer between 1 and 8. Predecoded boosted clock signal .phi.X+.sub.i is boosted to VCCP, and is eventually supplied to a word line signal WL that corresponds to the variable.
Decoder 19 receives predecoded boosted clock signal .phi.X+.sub.i clock signal .phi.XDP to precharge circuitry in decoder 19 to a high state, and address bits to enable the output of word line signal WL. Word line signal WL is raised to VCCP when main input clock signal .phi.XG is active.
The drawback of the FIG. 2 implementation is that the wordline signal WL rises to VCCP after input signal .phi.XG becomes active. In an implementation such as FIG. 2, the wordline signal WL may be quite tardy in rising to VCCP. This brings about an unnecessary delay in restoring, refreshing and/or accessing the memory cells.
Another way to bootstrap a word line of a memory array to VCCP is to use a bootstrap decoder with either internal or external timing circuitry. The timing circuitry is designed with predetermined delays. The predetermined delays are usually determined from empirical data for the bootstrapping decoders. The timing circuit is usually implemented using inverters or RC time constant delay circuits.
This later approach has many drawbacks. The timing is not accurate for each decoder circuit i.e. the decoder circuit may or may not be ready to output a word line signal WL having a voltage VCCP when it is selected. In fact, the timing is usually delayed longer than need be for the sake of reliability. Also, the timing circuit does not provide compensation for temperature variations of the devices.
Therefore, it is the general object of the present invention to overcome the above-described problems.
Another object of the present invention is to provide a simple design to implement self-timing of the decoder circuit.


A polymer electrolyte for an electrochemical half cell, in particular for a reference half cell, contains a polymer which as a first monomer component contains at least one alkyl methacrylate. The alkyl methacrylate has a substituted alkyl group with from three to seven carbon atoms and at least two substituents. The aforementioned substituents are selected from the group comprising OR1 and NR2R3, in which R1 , R2 and R3 are selected from the group comprising hydrogen, methyl, and ethyl, on the condition that the substituted alkyl group contains the substituent OH at most once.

1. Field of the Invention
The invention relates to a polymer electrolyte, to a half cell, and to uses of the half cell and of the polymer electrolyte.
2. Prior Art
Numerous half cells for electrochemical measurements, such as potentiometric or amperometric measurements, are known. In particular, such half cells can be embodied as reference electrodes, which are used in combination with potentiometric or amperometric sensors. In such reference electrodes, it is important that they output as constant a reference potential as possible.
In one type of reference electrodes, there is a fluid reference electrolyte, such as an aqueous potassium chloride solution, which can be brought into contact with a fluid measuring medium via a liquid connection (also known as a "liquid junction"). To avoid or reduce an unwanted mass transfer between the measuring medium and the reference electrolyte, the liquid junction is typically designed as a more or less porous diaphragm. One disadvantage of such liquid junctions, however, is that soiling or even plugging up of the pores can occur, which can lead to considerable faulty potentials and possibly interruptions.
In another type of reference electrodes, instead of the diaphragm, a single opening or a plurality of openings is provided, as a result of which the aforementioned problem of soiling can be largely avoided. However, this embodiment means that instead of the otherwise usual fluid or gel-like reference electrolyte, a non-flowable reference electrolyte is used, to prevent the reference electrolyte from flowing out. A polymer electrolyte in the form of a hydrogel, which for instance contains a saturated aqueous potassium chloride solution and preferably additionally suspended potassium chloride is especially well suited for this purpose.
In European Patent Disclosure EP 1124132 A1, which is hereby incorporated by reference in its entirety, a reference electrode of this generic type is described which contains a polymer electrolyte that contains a polymer on the basis of monomers selected from N-substituted acrylamides and/or methacrylates. For instance, the methacrylate is a methacrylate with at least two hydroxy groups, and in particular 2,3-dihydroxypropyl methacrylate.

Polymer electrolyte, half cell for electrochemical measurements, and the use thereof


A door system includes a flexible corrugated closure member guided between door open and closed positions in spaced apart opposed vertical and horizontal sets of guide tracks and further guided by transition guide wheels mounted on an enclosure frame for guiding the closure member between the sets of guide tracks. The transition guide wheels are supported for movement between working and non-working positions to facilitate storage or shipping the door system or an enclosure unit including the door system, as a substantially planar stack of wall, ceiling and floor members forming the enclosure.

In the art of upward acting doors and flexible closure member or so called rollup type doors, a conventional construction comprises a door which is rolled onto and off of a rotatable drum to provide for moving the door between open and closed positions. In certain applications of rollup doors and, in particular, so called sheet doors, it may be desirable to mount the door and/or ship the door wherein the door rolled onto a drum would be disadvantageous. In low headroom door applications or applications wherein the enclosure or structure using the door is collapsible, a door which is adapted for rolling onto and off of a cylindrical drum would occupy too much space. Accordingly, there has been a need for a flexible type door, or so called sheet door, which may be stored in a generally planar or unrolled condition and moved between open and closed positions without requiring a storage drum or a continuous guide track between a vertical or closed position of the door and a horizontal or open position of the door, for example. It is to these ends that the present invention has been developed.

Sheet door system with transition wheels


A storage control apparatus comprises a data I/O control unit which has communication ports adapted to connect with any of information processing apparatuses, is communicatively connected to physical disk drives for storing data, and performs data read/write from/to the drives according to a data I/O request received from the processing apparatus; a first memory storing a data read/written among the data stored in the disk drives; and a second memory storing information on management of storage resources including the communication ports, the physical disk drives, and a storage capacity of the first memory allocated for each user using the processing apparatuses. Upon reception of a request of the information on management from a user, an identifier of the communication port, an identifier of the disk drive, and a storage capacity of the first memory allocated for the user are transmitted to a user interface.

The present invention relates to a storage control apparatus and a control method thereof.
With recent progress of information technique, storage consolidation is performed so that a storage device is shared by a plurality of users. In the storage consolidation, each user uses the storage device by using storage resources such as a hard disk drive and a communication port allocated to him/her. In this case, various settings for using the storage resources should be performed by a system administrator of each user for the storage resources allocated for him/her. For example, see JP-A-5-128002.

Storage system and method for a storage control apparatus using information on management of storage resources


Methods and apparatus for providing an open content interface from importing EH&S data. The invention provides a computer-implemented method that includes: receiving a first input specifying a substance described in a database of an EH&S system; identifying product data available for the substance, the identifying being based on information stored in a first XML file; generating and displaying a data tree that indicates the product data available for the substance, wherein information stored in the first XML file is used to generate the data tree; receiving a second input selecting which of the product data is to be imported to the database of the EH&S system; retrieving the product data from second XML file that includes the product data; using mapping information stored in a third XML file to map the product data retrieved into a data format supported by the EH&S system; and storing the mapped product data.

The present invention relates to data processing by digital computer, and more particularly to Environment, Health and Safety (EH&S) systems.
In EH&S systems, for example, the EH&S system of SAP R/3, available from SAP AG of Walldorf, Germany, users can use one or more databases that include data describing various products used in the productions of life science and healthcare products. Such data will be referred to in the present specification as product data. Product data can include, for example, regulations and laws concerning the products and it ingredients. Product data can specify the legal requirements for the use of certain products, including, for example, handling requirements, storage requirements, and transport requirements. Product data can further include, for example, United Nations (UN) list substances and classification, physical and chemical characteristics of products, safety information for products, and hazardous material management data for products. Additional restrictions and information for certain products can be included.
An enterprise that uses EH&S products, for example, hazardous materials, typically need updated product data to ensure not only the safe use of the product but also compliance with the governing regulations. The enterprise will typically obtain product data from content providers, which include companies providing product data for EH&S products. The content providers usually send the product data to the enterprise through customized interfaces because the content providers usually store the product data in a data format that can differ from the data format supported by the EH&S system of the enterprise. The enterprise typically imports product data from various content providers into their databases. To allow data import from various content providers, various customized data interfaces are needed.
These interfaces can be hardware or software implemented. The interfaces provide communication between the EH&S middleware and the content providers. The interface needs to support each data format of the imported product data. Mapping of data from a content provider into the database format needs to be programmed for each respective data format. The mapping can require, for instance, assigning external product identifications (IDs) from content providers to internal product IDs of the database. Further, IDs of properties, characteristics, identifiers and/or phrases for products needs to be mapped from external to internal.
When receiving data from various content providers, a user (usually an employee of the enterprise) does not know which data is available and which data is to be include into the enterprise's EH&S system. The user needs to select from the available data and specify which of the product data available from the content provider to retrieve and map into the database. However, with different data formats for different content providers, a user interface enabling to select data is difficult to implement. The technical problem lies in the various data formats for product data.
Supporting various content providers also results in a high programming load. The technical problem of supporting various data formats of various content providers lies in the requirement of mapping programs for each data format. A further technical problem lies in the programming load to support changes in the data format of content providers. Another technical problem lies in the fact, that supporting various data formats is error prone.