A coherent coupled memory multiprocessor computer system that includes a plurality of processor modules (11a, 11b . . . ), a global interconnect (13), an optional global memory (15) and an input/output subsystem (17,19) is disclosed. Each processor module (11a, 11b . . . ) includes: a processor (21); cache memory (23); cache memory controller logic (22); coupled memory (25); coupled memory control logic (24); and a global interconnect interface (27). Coupled memory (25) associated with a specific processor (21), like global memory (15), is available to other processors (21). Coherency between data stored in coupled (or global) memory and similar data replicated in cache memory is maintained by either a write-through or a write-back cache coherency management protocol. The selected protocol is implemented in hardware, i.e., logic, form, preferably incorporated in the coupled memory control logic (24) and in the cache memory controller logic (22). In the write-through protocol, processor writes are propagated directly to coupled memory while invalidating corresponding data in cache memory. In contrast, the write-back protocol allows data owned by a cache to be continuously updated until requested by another processor, at which time the coupled memory is updated and other cache blocks containing the same data are invalidated.

Memory latency, i.e., the time required to access data or instructions stored in the memory of a computer, has increasingly become the bottleneck that prevents the full realization of the speed of contemporary single and multiprocessor computer systems. This result is occurring because the speed of integrated processors has outstripped memory subsystem speed. In order to operate most efficiently and effectively, fast processors require the contradictory features of reduced memory latency and larger memory size. Larger memory size implies greater physical size, greater communication distances, and slower access time due to the additional signal buffers needed to drive heavily loaded address, data and control signal lines, all of which increase memory latency. The primary negative effect of memory latency is its effect on processor speed. The longer it takes to obtain data from memory, the slower a processor runs because processors usually remain idle when they are waiting for data. This negative effect has increased as processor speed has outstripped memory subsystem speed. Despite the gains made in high-density, high-speed integrated memories, the progress to date still leaves the memory subsystem as the speed-limiting link in computer system design. This is true regardless of whether the computer system includes a single processor or a plurality of processors.
One way to reduce average memory latency is to add a cache subsystem to a computer system. A cache subsystem consists of a small memory situated adjacent to a processor that is hardware controlled rather than software controlled. Frequently used datum and instructions are replicated in cache memories. Cache subsystems capitalize on the property that once a datum or instruction has been fetched from system memory, it is very likely that it will be reused in the near future. Due to the close association between cache memory and its associated processor and the nature of the control (hardware as opposed to software), cache memory latency is several times less than that of system memory. Because access is much more rapid, overall speed is improved in computer systems that include a cache subsystem. As memory latency increases with memory size, hierarchical caches have been developed to maintain average memory latency at a low level. Some high-performance processors include separate instruction and datum caches that can be simultaneously accessed. (For simplicity of description, datum, instructions and any other forms of information commonly stored in computer memories are collectively hereinafter referred to as data.)
While computer systems that include a cache subsystem have a number of advantages, one disadvantage is the expense of cache memories. This disadvantage is enhanced because a cache memory does not add capacity to system memory. Rather, cache memories are add-ons to system memory, because, as noted above, cache memories replicate data stored in system memory. The replication of data leads to another disadvantage of cache memories, namely, the need to maintain coherency between data stored at two or more locations in the memories of a computer system. More specifically, because data stored at either location can be independently updated, a computer system that includes a cache subsystem requires a way of maintaining coherency between independent sources of the same data. If coherency is not maintained, data at one location will become stale when the same data at another location is updated. The use of stale data can lead to errors.
Several different types of cache management algorithms have been developed to govern what occurs when data stored in a cache are updated. The simplest algorithm is known as a "write-through" cache coherency management protocol. A write-through cache coherency management protocol causes processor writes to be propagated directly to system memory. All caches throughout the computer system are searched, and any copies of written data are either invalidated or updated. While a write-through cache coherency management protocol can be used with multiprocessor computer systems that include a large number of processors, a write-through cache coherency management protocol is better suited for single processor computer systems or multiprocessor computer systems incorporating a limited number, e.g., four, of processors.
A more complex, but higher performance, coherency management algorithm is known as a "write-back" cache coherency management protocol. Like a write-through cache coherency management protocol, a write-back cache coherency management protocol is an algorithm that is normally incorporated in the hardware of a computer system that controls the operation of a cache. In a write-back cache coherency management protocol, initial processor writes are written only to cache memory. Later, as necessary, updated data stored in a cache memory is transferred to system memory. Updated data transfer occurs when an input/output device or another processor requires the updated data. A write-back cache coherency management protocol is better suited for use in multiprocessor computer systems that include a large number of processors (e.g., 24) than a write-through cache coherency management protocol because a write-back cache coherency management protocol has a lower impact on the system interconnect because a write-through cache coherency management protocol greatly reduces write traffic.
One of the first write-back coherency management protocols was suggested by Dr. James R. Goodman in his paper entitled "Using Cache Memory to Reduce Processor Memory Traffic" (10th International Symposium of Computer Architecture, 1983). Dr. Goodman's improvement is based on the observation that if the sole copy of data associated with a specific system memory location is stored in a cache, the cache copy can be repeatedly modified without the need to broadcast write-invalidate messages to all other system caches each time a modification occurs. More specifically, Dr. Goodman's improvement requires the addition of a state bit to each cache copy. The state bit indicates that the copy is either "shared" or "owned." When a system memory location is first read, and data supplied to a cache, the state bit is set to the "shared" state. If the cache copy is later written, i.e., modified, the state bit transitions to the "owned" state. At the same time, a write-invalidate message is broadcast, resulting in the updated cache copy of the data being identified as the only valid copy associated with the related system memory location. As long as the cache location remains in an owned state, it can be rewritten, i.e., updated, without the need to broadcast further write-invalidate messages. A remote request for the data to the memory location associated with the cached copy causes a transition back to the shared state, and the read request to be satisfied by either the cache and, then, updating the related system memory location, or by the cache delaying the memory request until valid data is rewritten to the system memory location.
Recently, proposals have been made to distribute memory throughout a multiprocessor computer system, rather than use bank(s) of global memory accessible by all processors via a common interconnect bus. More specifically, in distributed memory multiprocessor computer systems, a portion of system memory is physically located adjacent to the processor the memory portion is intended to serve. Research in this area has grown out of attempts to find ways of creating effective multiprocessor computer systems out of a large number of powerful workstations connected together via a network link. In the past, distributed shared memory computer networks have used various software-implemented protocols to share memory space. The software-implemented protocols make the distributed memory simulate a common global memory accessible by all of the computers connected to the network. Memory latency is improved because the portion of memory associated with a specific processor can be accessed by that processor without use of the network link. An example of this research work is the BBN Butterfly computer system developed by BBN Laboratories, Inc. See Butterfly.TM. Parallel Processor Overview, BBN Report No. 6148, Version 1, Mar. 6, 1986, and The Uniform System Approach to Programming the Butterfly.TM. Parallel Processor, BBN Report No. 6149, Version 2, Jun. 16, 1986.
A drawback of the software-implemented protocols used in the BBN Butterfly and the like computer systems is their extremely poor performance when the amount of sharing between processors is large or when the memory associated with a single processor is insufficient to meet the needs of a program and it becomes necessary to use the memory associated with another processor and/or to make data calls to storage devices, such as a hard disk. In the past, such requirements have significantly reduced processing speed. Such requirements have also negatively impacted the bandwidth requirements of the network linking the processors together. A further disadvantage has been the increased overhead associated with the management of data stored at different locations in the distributed memory of the computer system. More specifically, the processing speed of prior art distributed memory multiprocessor computer systems have been improved by replicating shared data in the memories associated with the different processors needing the data. This has a number of disadvantages. First, replicating data in system memory creates a high memory overhead, particularly because system memory is stored on a page basis and page sizes are relatively large. Recently, page sizes of 64K bytes have been proposed. In contrast cache memories store data in blocks of considerably smaller size. A typical cache block of data is 64 bytes. Thus, the "granularity" of the data replicated in system memory is considerably larger than the granularity of data replicated in cache memory. The large granularity size leads to other disadvantages. Greater interconnect bandwidth is required to transfer larger data granules than smaller data granules. Coherency problems are increased because of the likelihood that more processors will be contending for the larger granules than the number contending for smaller granules on a packet-to-packet basis.
In summary, in the last several years, very large-scale integrated circuit (VLSI) processor speeds have been increased by roughly an order of magnitude due to continual semiconductor improvements and due to the introduction of reduced instruction set computer (RISC) architectures. As processor speeds have improved, large, fast and expensive cache memories have been needed in order to reduce average memory latency and keep processor idle times reasonable. Even with improved cache memories and improved ways of maintaining data coherency, average memory latency remains the bottleneck to improving the performance of multiprocessor computer systems.
A major portion of memory latency, i.e., memory access time, is the latency of the network that interconnects the multiprocessors, memory, and input/output modules of multiprocessor computer systems. Regardless of whether the interconnect network is a fully interconnected switching network or a shared bus, the time it takes for a memory request to travel between a processor and system memory is directly added to the actual memory operational latency. Interconnect latency includes not only the actual signal propagation delays, but overhead delays such as synchronization of the interconnect timing environment with the interconnect arbitration, which increases rapidly as processors are added to a multiprocessor system.
Recent attempts to improve memory latency have involved distributing system memory so that it is closer to the processors requiring access to the memory. This has led to sharing data in system memory, which, in turn, has required the implementation of coherency schemes. In the past system memory coherency schemes have been implemented in software. Because they have been implemented in software they have been slow. Further, system memory sharing requires that large data granules be transferred. Large data granules take up large parts of system memory, require large amounts of interconnect bandwidth to transfer from one memory location to another, and are more likely to be referenced by a large number of processors than smaller data granules. The present invention is directed to providing a multiprocessor computer system that overcomes these disadvantages.

Coupled memory multiprocessor computer system including cache coherency management protocols


In a proportional solenoid valve control device, a mode selecting switch has an auto-mode position for sending a control signal from a level converting section to a driving signal amplifying section, a valve fully-closing manual position for supplying a valve fully-closing signal to the driving signal amplifying section, and a valve fully-opening manual position for supplying a valve fully-opening signal to the driving signal amplifying section. With the mode selecting switch set at the valve fully-closing manual position, a value of the valve fully-closing driving signal can be adjusted. With the mode selecting switch set at the valve fully-opening manual position, a value of the valve fully-opening driving signal can be adjusted. This makes it possible to easily perform an initial setting operation of the proportional solenoid valve by a valve controller.

In a manufacturing line for manufacturing mass products such as industrial products, a number of proportional solenoid valves are used for controlling flow rates and pressures of fluid. For example, in Japanese Patent Laid-Open Publication No. 2002-313753, a proportional solenoid valve is used for controlling an amount of cutting water supplied to a processing unit of a dicing apparatus. Fluid to be controlled by the proportional solenoid value includes a gas such as air, an inert gas, and vapor and a liquid such as water, heated water, a chemical solution, and oil. The proportional solenoid valve includes a valve body for adjusting a valve opening degree in a fluid flow path and a solenoid for generating an electromagnetic force in proportion to a driving signal supplied to a coil. A spring force in a direction of closing the fluid flow path is applied to the valve body by a spring member, so that the electromagnetic force generated at the solenoid against the spring force allows the valve body to open the fluid flow path and also allows the valve opening degree to change continuously in proportion to magnitude of the electromagnetic force.
A valve controller for controlling the driving signal is disposed near the proportional solenoid valve. The driving signal to be supplied from this valve controller to the coil of the proportional solenoid valve is controlled by this valve controller. When the proportional solenoid valve is used in a manufacturing line for manufacturing mass products, the driving signal is sent from the valve controller so that the valve body of the proportional solenoid valve can take any opening degree within a range of a valve fully-closing state to a valve fully-opening state, on the basis of a command signal which is inputted from a main controller such as a personal computer or other computers and corresponds to the valve opening degree. In a manufacturing line in which many proportional solenoid valves are used, for example, a command signal is inputted from one main controller in accordance with each valve controller of the proportional solenoid valves, so that the respective proportional solenoid valves are driven individually.
The command signal from the main controller to each valve controller depends on a characteristic of the main controller, and there are, for example, the case where a 4 to 20 mA current loop signal is outputted as a command signal and the case where a voltage signal within a range of 0 to 10 V is outputted as a command signal. For this reason, the valve controller is provided with an input signal selecting switch so that even when either command signal is inputted to the valve controller, the driving signal of the valve opening degree corresponding to the command signal can be outputted to the proportional solenoid valve. Therefore, for example, when a 4 mA current signal as the command signal for setting the valve opening degree at the valve fully-closing state is inputted from the main controller, the driving signal corresponding to a valve fully-closing state is outputted from the valve controller to the coil of the proportional solenoid valve, and if a 20 mA current signal is inputted, the driving signal corresponding to a valve fully-opening state is outputted from the valve controller to the proportional solenoid valve. Similarly, when a 0 V voltage signal as a command signal for setting the valve opening degree at the valve fully-closing state is inputted, the driving signal corresponding to a valve fully-closing state is outputted to the coil, and when a 10 V voltage signal is inputted, the driving signal corresponding to the valve fully-opening state is outputted to the coil.

Proportional solenoid valve control device


Disclosed is a novel high 1,4-cis polybutadiene-polyurethane copolymer and a preparation method thereof. The present invention provides a high 1,4-cis polybutadiene-polyurethane copolymer represented by the following formula 1 and having an average molecular weight of at least 100,000, and a method for preparing the high 1,4-cis polybutadiene-polyurethane copolymer that includes polymerizing 1,3-butadiene or butadiene derivatives with a catalyst comprising a rare earth compound, a halogen-containing compound and an organoaluminum compound in the presence of a non-polar solvent, to prepare a polybutadiene having a high 1,4-cis content of at least 95%; and then introducing a polyurethane group to the polybutadiene. The high 1,4-cis polybutadiene-polyurethane copolymer thus obtained exhibits low cold flow and high affinity to silica or carbon black in admixture as well as excellent in elasticity and abrasion resistance:

1. Field of the Invention
This invention relates to a high 1,4-cis polybutadiene-polyurethane copolymer and a preparation method thereof. More specifically, the present invention relates to a method for preparing a high 1,4-cis polybutadiene-polyurethane copolymer that includes preparing a high 1,4-cis polybutadiene-polyurethane copolymer using a copolymer of a high 1,4-cis polybutadiene excellent in elasticity due to its linear molecular structure with high cis stereoregularity and a polyurethane excellent in abrasion resistance, and a rare earth catalyst, and adding an isocyanate compound and an alcohol.
2. Related Prior Art
Methods for preparing a high 1,4-cis polybutadiene using a rare earth catalyst are disclosed in European Patents Nos. 0,011,184 (Bayer AG) and 0,652,240 (Bayer Inc.), and U.S. Pat. Nos. 4,260,707 (Sylvester) and 5,017,539 (Jenkins et al.). In these methods, a high 1,4-cis polybutadiene is prepared by using a neodymium carboxylate compound, an alkylaluminum compound and a Lewis acid in the presence of a non-polar solvent.
U.S. Pat. No. 5,428,119 (Knauf et al.) discloses a method for preparing a high 1,4-cis polybutadiene using a rare earth carboxylate and alkylaluminum compounds such as R1AlCl2, R12AlCl or R13Al2Cl3 (where R1 is C8-C12 alkyl) and R22AlH (where R2 is C2-C6 alkyl).
UK Patent No. 2,002,003 (ANIC S.p.A.) and U.S. Pat. No. 4,429,089 (Pedretti et al.) suggest a method for preparing a high 1,4-cis polybutadiene using AlR2X (where R is hydrogen or alkyl; and X is hydrogen, alkoxy or alkoxy sulfide), alkyl aluminum, and a neodymium compound.
European Patent No. 0,092,270 (Enichem Polimeri S.p.A.) and U.S. Pat. No. 4,444,903 (Carbonaro et al.) propose a method for preparing a high 1,4-cis polybutadiene using a catalyst system comprising a rare earth metal, alkyl aluminum, and t-alkyl halogen. U.S. Pat. No. 4,736,001 (Carbonaro et al.) describes a method for preparing high 1,4-cis polybutadiene using the above-mentioned catalyst system without a solvent.
In addition, U.S. Pat. No. 4,699,962 (Hsieh et al.) discloses a synthetic method of high 1,4-cis polybutadiene using a catalyst system prepared by mixing a neodymium hydride compound, a chloride compound and an electron-donating ligand, and then adding an alkyl aluminum compound.
European Patent No. 375,421 (Enichem Elastomers Limited) and U.S. Pat. No. 5,017,539 (Jenkins et al.) also describe a synthetic method of high 1,4-cis polybutadiene by aging a neodymium compound, an organohalide compound and an organoaluminum compound at 0° C. or less.
In applications of the high 1,4-cis polybutadiene, the terminal of the polybutadiene is modified so as to control viscosity or affinity to additives in post-admixture. More specifically, the terminal of polybutadiene is modified epoxy or isocyanate by using the living property of the neodymium catalyst as mentioned in, for example, WIPO Publication No. 02/36615 (Applied Molecular Evolution, Inc.), and European Patents Nos. 0,713 885 (Nippon Zeon Co., Ltd) and 0,0267 675 (Japan Synthetic Rubber Co., Ltd.).
A low 1,4-cis polybutadiene-polyurethane copolymer that is the copolymer of low 1,4-cis polybutadiene and polyurethane is disclosed in documents (Makrmol. Chem. 1983, 651; Adv. Polym. Sci. 2002, 21, 25; Plasty a kaucuk 2002, 39, 68). In the cited documents, the polybutadiene is a hydroxyl-modified polybutadiene synthesized by using an anionic polymerization catalyst. More specifically, the polybutadiene is a low 1,4-cis polybutadiene having a 1,4-vinyl content of about 35%, a 1,4-vinyl content of about 30% and a 1,4-cis content of about 10 to 30%, with a small molecular weight of about 3000. The synthetic method of low 1,4-cis polybutadiene-polyurethane copolymer is comprised of three steps that include polymerization of polybutadiene with an anionic catalyst such as butyl lithium, adding an epoxy compound to prepare hydroxyl polybutadiene; and adding an isocyanate compound to yield low 1,4-cis polybutadiene-polyurethane copolymer. Low 1,4-cis polybutadiene-polyurethane copolymer thus synthesized is used as a resin modifier.

High 1,4-cis polybutadiene-polyurethane copolymer and preparation method thereof

Abstract: where l, m, n and o represent the number of repeating unit, 1 is 94 to 99%, m is 0 to 5%, n is 0 to 5%, l+m+n=100%, l/(m+n) is 15 to 100, o is 1 to 100%; and A and Y are C1-C20 alkyl or aryl, respectively.


A controller calculates first movement times when moving each robot hand from a movement start position to a synchronous operation position in a shortest time and decides the longest first movement time as a second movement time. The controller generates, for each robot, a robot operation plan for moving each robot hand without stopping from the movement start position to the synchronous operation position in the second movement time. The robot hand of each robot moves from the movement start position to the synchronous operation position without stopping and simultaneously reach the synchronous operation positions.

1. Field of the Invention
The present invention relates to a robot controller and a robot control method for moving each of standard moving parts of each of robots to each of synchronous operation positions respectively set and simultaneously performing operations of the robots.
2. Description of the Related Art
FIG. 23 is a drawing for explaining pressing equipment 6 of a related art. When two robots 1 and 2 are operated simultaneously and the operable ranges of the robots 1 and 2 are overlaid each other, it is necessary to prevent the robots 1 and 2 from mutual interference. As a related art, there is an art available for preventing interference using mutual communication of two robot controllers 3 and 4.
The pressing equipment 6 includes the first robot 1 for supplying a workpiece 8 before pressing to a pressing machine 7, the second robot 2 for collecting a pressed workpiece 9 from the pressing machine 7, the robot controllers 3 and 4 for respectively controlling the robots 1 and 2, and a programmable controller (abbreviated to PLC) 5 for giving an operation instruction to the robot controllers 3 and 4.
The first robot 1 holds the workpiece 8 from an unloading table 10 and arranges it at a pressing position p2 of the pressing machine 7. The second robot 2 collects the workpiece 9 arranged at the pressing position p2 of the pressing machine 7 and transfers it to the succeeding processing machine. Therefore, when the robots 1 and 2 are different in speed from each other, in the neighborhood of the pressing position p2 of the pressing machine 7 where the workpieces 8 and 9 are arranged, there is a fear of interference of the robots 1 and 2.
To prevent the robots 1 and 2 from interference, the first controller 3 stores information of a proximity position p1 on the upstream side of the pressing position p2 in the transfer direction. Further, the second controller 4 stores information of a separation position p3 on the downstream side of the pressing position p2 in the transfer direction. The first controller 3, on the basis of the information given from the second controller 4, judges whether the workpiece 8 can move into the neighboring space of the pressing machine 7 or not.
FIG. 24 includes graphs showing a change with time of the speed of each of the workpieces 8 and 9 of the robots 1 and 2. FIG. 24(1) shows a speed change of the robot hand of the first robot 1 and FIG. 24(2) shows a speed change of the robot hand of the second robot 2. As shown in FIG. 24(1), the first controller 3 stops the workpiece 8 before pressing at a point of time tp1 of arrival at the proximity position p1 where the workpiece 8 before pressing is moved. Further, as shown in FIG. 24(2), the second controller 24 moves the workpiece 9 after pressing at a point of time tp2 of arrival at the pressing position p2 where the workpiece 9 after pressing is held. And, the second controller 24 stops the workpiece 9 after pressing at a point of time tp3 of arrival at the separation position p3 where the workpiece 9 after pressing is moved.
And, at the point of time tp3 of arrival at the separation position, the second controller 4 transmits an arrival signal to the PLC 5. The PLC 5, upon receipt of the arrival signal from the second controller 4, gives a movement restart instruction to the controllers 3 and 4. The first controller 3, upon receipt of the arrival signal from the PLC 5, restarts the movement of the workpiece 8 before pressing from the proximity position p1 to the pressing position p2. Further, the second controller 4, upon receipt of the arrival signal from the PLC 5, restarts the movement of the workpiece 9 after pressing from the separation position p3 to the succeeding processing machine.
By such an operation, before the workpiece 9 after pressing is separated from the neighboring space of the pressing machine 7, the workpiece 8 before pressing is prevented from entrance into the neighboring space of the pressing machine 7. Therefore, the robots 1 and 2 can be prevented from interference with each other. This related art is disclosed, for example, in Japanese Patent Laid-Open Publication No. 7-271415.
In the related art aforementioned, the first robot 1 makes the workpiece 8 wait at the proximity position p1 at the proximity position arrival point of time tp1. And, after standby, when the workpiece 8 after pressing reaches the separation position arrival point of time tp3, the first robot 1 restarts the movement of the workpiece 8 before pressing. To prevent mutual interference of the robots 1 and 2, it is necessary to stop once them. The robots 1 and 2 are set to move as fast as possible to improve the production efficiency. In this case, even if the first robot 1 is moved at its maximum speed, if the workpiece 8 before pressing waits at the proximity position p1, compared with a case that the first robot 1 moves at a low speed and the workpiece 8 before pressing moves without stopping at the proximity position p1, the consumption of energy is increased and the energy efficiency is lowered.
Further, to prevent interference without keeping the workpiece 8 before pressing wait at the proximity position p1, it is considered to adjust manually the operation timing such as the robot speed so as to slow down the first robot 1. However, if the first robot 1 is excessively slowed down, even if the workpiece 9 after pressing reaches the separation position p3, a condition that the workpiece 8 before pressing does not reach yet the proximity position p1 is caused and a problem arises that the cycle time is increased.
Further, the timing adjustment by hand must be made whenever changing the equipment to be adjusted, workpiece shape held, movement posture, movement route, and movement position and cannot be decided uniformly. Therefore, a problem arises that the time required for preparation of the robot operation is increased. Further, also for the spot welding operation or painting operation by a plurality of robots, the similar problem is imposed.

Robot controller and robot control method for synchronous operation and adjusting robot movement based on two movement times


A synchronous rectification circuit of a switching power supply device where circuit elements such as rectification switch elements are protected when an abnormality occurs in an output of a transformer, wherein a (fault) detecting circuit detects an abnormality of a trigger signal transmitted from a transformer, a shutoff circuit quickly cuts off a discharge route of an inductor (coil) forming a gate drive signal source of a first transistor (NMOS transistor) when the (fault) detecting circuit detects an abnormality, and a (linear) driver holds (clamps) a drain-source voltage of the NMOS transistor at a constant voltage and turns on the NMOS transistor by that constant voltage so as to prevent it from turning off immediately when the detecting circuit detects an abnormality.

1. Field of the Invention
The present invention relates to a switching power source for generating a desired voltage by switching of DC voltage, voltage conversion, and synchronous rectification, more particularly relates to technique for protection of the synchronous rectification circuit.
2. Description of the Related Art
FIGS. 1A and 1B show the circuit configurations of conventional synchronous rectification circuits in switching power sources as disclosed in Japanese Patent Publication (A) No. 2003-189608 (secondary side circuits of transformers).
The circuit shown in FIG. 1A is a current doublers type synchronous rectification circuit. This circuit is the most generally used synchronous rectification circuit directly driving switch elements SW100 and SW200 (NMOS transistors) by an output of a secondary winding of the transformer. In the circuit shown in FIG. 1A, however, when the power source output is stopped, the charge stored in an output capacitor C0 passes through the secondary winding and turns on the switch elements SW100 and SW200, so sometimes induces breakage of these elements.
FIG. 1B shows a synchronous rectification circuit for controlling the ON and OFF states of the switch elements SW100 and SW200 not by directly driving the switch elements SW100 and SW200 (NMOS transistors) from the output of the secondary winding of the transformer, but by combining for example a not shown auxiliary winding and control circuit. In this synchronous rectification system, a rectification efficiency can be raised in comparison with the circuit shown in FIG. 1A.
However, in the synchronous rectification circuit shown in FIG. 1B as well, sometimes the drain-source voltages of the switch elements SW100 and SW200 exceed a withstand voltage level and induce breakage of these elements when no protection circuit is provided. Below, the mechanism by which breakage of the switch elements is induced will be explained with reference to FIGS. 2A and 2B.
FIGS. 2A and 2B are diagrams for explaining a current path in the conventional synchronous rectification circuit shown in FIG. 1B, in which FIG. 2A shows a case of no load output, and FIG. 2B shows a case after the transformer output is suspended. In the synchronous rectification circuit shown in FIG. 1B, when the power source supply has no load, since there is no current flowing in a load, the current flowing in a transformer Tm circulates through coils L10 and L20, switch elements SW100 and SW200, and the output capacitor C0 as shown in FIG. 2A. The currents flowing in the coils L10 and L20 become 0 when totaled in the reverse directions. At this time, assume that the switch element SW100 is in an ON state, and the switch element SW200 is in an OFF state.
At this time, when the drive signal on a primary side of the transformer Tm is suspended due to an abnormality, the output voltage of the transformer Tm immediately becomes 0V, but according to any configuration of the control circuit, the switch element SW100 sometimes was continuously kept ON since the time before that. Then, as shown in FIG. 2B, the current flows in reverse through the output capacitor C0, that is, the current of the output capacitor C0 is discharged through the switch element SW100. In such case, the switch element SW100 may break due to the rise of the discharge current unless the switch element SW100 is forcibly turned off. However, if the switch element SW100 is forcibly turned off here, there will no longer be a discharge loop for releasing the energy of the coils L10 and L20 (since the escape route of the current is lost), so there is a possibility that high voltages will be induced between the drains and sources of the switch elements SW100 and SW200 and these elements will be broken.


This invention relates to neurotrophic compounds having an affinity for FKBP-type immunophilins, their preparation and use as inhibitors of the enzyme activity associated with immunophilin proteins, and particularly inhibitors of peptidyl-prolyl isomerase or rotamase enzyme activity.

I. Field of the Invention
This invention relates to neurotrophic compounds having an affinity for FKBP-type immunophilins, their preparation and use as inhibitors of the enzyme activity associated with immunophilin proteins, and particularly inhibitors of peptidyl-prolyl isomerase or rotamase enzyme activity.
2. Description of the Prior Art
The term immunophilin refers to a number of proteins that serve as receptors for the principal immunosuppressant drugs, cyclosporin A (CsA), FK506, and rapamycin. Known classes of immunophilins are cyclophilins, and FK506 binding proteins, such as FKBP. Cyclosporin A binds to cyclophilin while FK506 and rapamycin bind to FKBP. These immunophilin-drug complexes interface with a variety of intracellular signal transduction systems, especially in the immune system and the nervous system.
Immunophilins are known to have peptidyl-prolyl isomerase (PPIase) or rotamase enzyme activity. It has been determined that rotamase activity has a role in the catalyzation of the interconversion of the cis and trans isomer of immunophilin proteins.
Immunophilins were originally discovered and studied in immune tissue. It was initially postulated by those skilled in the art that inhibition of the immunophilins rotamase activity leads to the inhibition of T-cell proliferation, thereby causing the immunosuppressive action exhibited by immunosuppressive drugs such as cyclosporin A, FK506, and rapamycin.
Further study has shown that the inhibition of rotamase activity, in and of itself, is not sufficient for immunosuppressant activity. Schreiber et al., Science, 1990 vol. 250 pp. 556-559. It has been shown that the immunophilin-drug complexes interact with ternary protein targets as their mode of action. Schreiber et al., Cell, 1991, vol. 66, pp. 807-815.
In the case of FKBP-FK506 and FKBP-CsA, the drug immunophilin complexes bind to the enzyme calcineurin, inhibitory T-cell receptor signaling leading to T-cell proliferation. Similarly, the complex of rapamycin and FKBP interacts With the RAFTI/FRAP protein and inhibits signaling from the IL-2 receptor.
Immunophilins have been found to be present at high concentrations in the central nervous system. Immunophilins are enriched 10-50 times more in the central nervous system than in the immune system. Within neural tissues, 50 immunophilins appear to influence neuronal process extension, nitric oxide synthesis, and neurotransmitter release.
It has been found that picomolar concentrations of an immunosuppressant such as FK506 and rapamycin stimulate neurite out growth in PC12 cells and sensory nervous, 55 namely dorsal root ganglion cells (DRGs). Lyons et al., Proc. of NaIL. Acad. Sci., 1994 vol. 91, pp. 3191-3195. In whole animal experiments, FK506 has been shown to stimulate nerve regeneration following facial nerve injury and results in functional recovery in animals with sciatic nerve lesions.
Surprisingly, it has been found that drugs with a high affinity for FKBP are potent rotamase inhibitors causing a neurotrophic effect. Lyons et al. These findings suggest the use of immunosuppressants in treating various peripheral neuropathies and enhancing neuronal regrowth in the central nervous system (CNS). Studies have demonstrated that neurodegenerative disorders such as Alzheimer's disease, Parkinson's disease, and amyotrophic lateral sclerosis (ALS) may occur due to the loss, or decreased availability, of a neurotrophic substance specific for a particular population of neurons affected in the disorder.
Several neurotrophic factors effecting specific neuronal populations in the central nervous system have been identified. For example, it has been hypothesized that Alzheimer's disease results from a decrease or loss of nerve growth factor (NOF). It has thus been proposed to treat Alzheimer's patients with exogenous nerve growth factor or other neurotrophic proteins such as brain derived nerve factor (BDNF), glial derived nerve factor, ciliary neurotrophic factor, and neurotropin-3 to increase the survival of degenerating neuronal populations.
Clinical application of these proteins in various neurological disease states is hampered by difficulties in the delivery and bioavailability of large proteins to nervous system targets. By contrast, immunosuppressant drugs with neurotrophic activity are relatively small and display excellent bioavailability and specificity. However, when administered chronically, immunosuppressants exhibit a number of potentially serious side effects including nephrotoxicity, such as impairment of glomerular filtration and irreversible interstitial fibrosis (Kopp et al., 1991, J. Am. Soc. Nephrol. 1:162); neurological deficits, such as involuntary tremors, or non-specific cerebral angina such as non-localized headaches (De Groen et al., 1987, N. Engl. J. Med. 317:861); and vascular hypertension with complications resulting there-from (Kahan et al., 1989 N. Engl. J. Med. 321:1725).
In order to prevent the side effects associated with use of the immunosuppressant compounds, the present invention provides non-immunosuppressive compounds containing small molecule FKBP rotamase inhibitors for promoting neuronal growth and regeneration in various neuropathological situations where neuronal repair can be facilitated including peripheral nerve damage by physical injury or disease state such as diabetes, physical damage to the central nervous system (spinal cord and brain) brain damage associated with stroke, and for the treatment of neurological disorders relating to neurodegeneration, including Parkinson's disease, Alzheimer's disease, and amyotrophic lateral sclerosis.

This patent is subject to a terminal disclaimer.

Small molecule rotamase enzyme inhibitors


An semiconductor device and a method for manufacturing semiconductor devices which are easily made compact. A plurality of semiconductor chips having protrusion electrodes respectively provided on a plurality of electrodes formed on circuit surfaces are integrally sealed by an insulating material so as to cover the circuit surfaces while the circuit surfaces are nearly directed to the same direction and arranged in prescribed conditions, and to expose the respective protrusion electrodes; and insulating layers and wiring layers respectively electrically connected to the corresponding protrusion electrodes are alternately laminated on the insulating material so as to have the desired number of layers in the direction of thickness. Thus, the spaces between the semiconductor chips can be extremely narrowed, and the thickness of the insulating layers and wiring layers can be significantly reduced, so that the semiconductor devices which can be made compact without difficulty and the method capable of easily manufacturing the semiconductor devices in compact forms can be realized.

1. Field of the Invention
This invention relates to an electronic device and a method for manufacturing electronic parts, and more particularly is applicable to a multichip module and a method for manufacturing the multichip module.
2. Description of the Related Art
Conventionally, as such electronic device, there has been known a multichip module in which a plurality of chip parts are mounted with high density on a multilayer wiring substrate and an entire body is thus made compact, so that the wiring length between the respective chip parts can be relatively shortened and the high speed characteristic and high frequency characteristic or the like of the respective chip parts can be improved.
As illustrated in FIG. 1, a multichip module 1 ordinarily comprises a multilayer wiring substrate 2 formed by sequentially laminating and forming insulating layers composed of ceramic substrates or organic substrates or the like and wiring layers having prescribed conductor patterns in the direction of its thickness, a plurality of chip parts 3 formed on one surface 2A of the multilayer wiring substrate 2, and protrusion electrodes 4 (referred to as soldering bumps, hereinafter) obtained by soldering a plurality of pads (not shown) respectively formed on circuit surfaces 3A of corresponding lands (not shown) on the multilayer wiring substrate 2. The respective chip parts 3 are electrically and physically connected to and mounted on the one surface 2A of the multilayer wiring substrate 2 through the soldering bumps 4.
In this connection, in the multichip module 1, since the coefficient of thermal expansion of the multilayer wiring substrate 2 has a value not smaller than two times the coefficient of thermal expansion of the chip parts 3, if the chip parts 3 generate heat owing to the operation of the chip parts 3 and so on, thermal stress may be concentrated on the respective soldering bumps 4 formed between the multilayer wiring substrate 2 and the respective chip parts 3, which may cause inconveniently the soldering bumps 4 to be broken.
For overcoming this disadvantage, in the above mentioned multichip module 1,spaces formed between the one surface 2A of the multilayer wiring substrate 2 and the circuit surfaces 3A of the respective chip parts 3 are respectively filled with an insulating material (namely, an underfilling material) 5 so as to embed the respective soldering bumps 4 therein. Thus, according to the above stated multichip module 1, the concentration of the thermal stress generated on the respective soldering bumps 4 can be mitigated because of the insulating material 5, so that the soldering bumps 4 can be prevented from being broken. Further, the insulating material 5 is designed to cover the respective circuit surfaces 3A of the chip parts 3 so that it can protect the circuit surfaces 3A from troubles due to impurities or moisture contained in outside air as well as can prevent the breakage of the respective soldering bumps 4.
In recent years, in the multichip module 1 described above, it has been desired that the construction of a multichip module 1 is made more compact, in order to mount the respective chip parts 3 on the one surface 2A of the multilayer wiring substrate 2 with a higher density.
However, according to the multichip module 1 in question, when the spaces between the respective chip parts 3 are narrowed in some degree or more, there have occurred problems that it is difficult to fill the spaces between the one surface 2A of the multilayer wiring substrate 2 and the respective circuit surfaces 3A of the chip parts 3 with the insulating material 5 so that the insulating material 5 hardly prevents the breakage of the respective soldering bumps 4, and that the circuit surfaces 3A of the respective chip parts 3 are seldom protected. Accordingly, when the respective chip parts 3 are mounted on the substrate with a higher density and the size of the multichip module 1 is made smaller, there has arisen a problem that quality and reliability of the multichip module 1 are disadvantageously degraded markedly.
In addition, in the above multichip module 1, when the number of the chip parts 3 mounted on the one surface 2A of the multilayer wiring substrate 2 is increased, a heat generation rate of the entire module depending on the operation of the respective chip parts 3 is also increased, so that the thermal stress converged to the respective soldering bumps 4, which results from the difference in the coefficient of thermal expansion between the multilayer wiring substrate 2 and the chip parts 3, is hardly lowered only by the insulating material 5. Therefore, in such a case, a method may be considered for mitigating the thermal stress concentrated onto the respective soldering bumps 4 by relatively enlarging the size of the respective bumps 4, in addition to the insulating material 5.
However, in the above mentioned case, the lands of the multilayer wiring substrate 2 have needed to be enlarged depending on the dimension of the soldering bumps 4, and therefore, the multilayer wiring substrate 2 has been undesirably made larger. In other words, the multilayer wiring substrate 27 has been enlarged, which has inconveniently caused the entire body of the multichip module 1 to be also enlarged.
Additionally, in the above described multichip module 1, when the number of the pads of the chip parts 3 mounted on the one surface 2A of the multilayer wiring substrate 2 is comparatively large, the number of wirings electrically connected to the lands of the multilayer wiring substrate 2 is also proportionally increased. Therefore, the number of wiring layers formed on the multilayer wiring substrate 2 must be increased.
In this case, however, since the insulating layers to be increased together with the wiring layers in the multilayer wiring substrate 2 has approximately 0.1 mm per layer, the multilayer wiring substrate 2 has been undesirably comparatively increased in its thickness.

Electronic device and method for manufacturing electronic device


A dynamically reconfigurable asynchronous arbitration node for use in an adaptive asynchronous interconnection network is provided. The arbitration node includes a circuit, an output channel and two input channels—a first input channel and a second input channel. The circuit supports a default-arbitration mode and a biased-input mode. The circuit is configured to generate data for the output channel by mediating between input traffic including data received at the first and second input channels, if the arbitration node is operating in the default-arbitration mode, or by providing a direct path to the output channel for one of the first input channel and the second input channel that is biased, if the arbitration node is operating in the biased-input mode. The circuit is further configured to monitor the input traffic and implement a mode change based on a history of the observed input traffic in accordance with a mode-change policy.

Developments in networks-on-chip (NOCs) in the last decade have demonstrated great promise in handling several of the key challenges facing digital system designers in the deep submicron era, including design time, scalability, reliability and ease-of-integration. However, recent findings still predict significant challenges and short-comings in terms of system latency, throughput and power consumption.
One approach that has been explored to address such challenges is elimination of the global clock, either using entirely asynchronous systems or integrating synchronous cores, nodes and memories through asynchronous communication in a globally-asynchronous locally synchronous (GALS) system. GALS systems offer the potential of more flexible integration of heterogeneous components, such as heterochronous systems that have arbitrary unrelated clock domains.
A number of recent approaches have also been explored for dynamic adaptivity in both synchronous and asynchronous domains. These approaches include asynchronous dynamic leakage management and synchronization reduction in multi-synchronous NOCs as well as other synchronous approaches, including express virtual channels.

Bi-modal arbitration nodes for a low-latency adaptive asynchronous interconnection network and methods for using the same

THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK


An improved apparatus for collecting and disposing of animal excrement has an elastic harness assembly attachably secured to the rear portion of an animal, such as a dog, and an excrement container cooperating with, and removable from, the elastic harness assembly. Specifically, the elastic harness assembly has a flexible outer ring member encompassing a rigid inner ring member to which the excrement container is removably attached. The ring members are located about the anal region of the dog and isolated in place by use of fasteners and elastic straps.

1. Field of the Invention
The present invention relates to devices for the convenient disposal of animal excrement, and more specifically to a device that can be isolated to a specific region of the animal.
2. Description of the Related Art
With the joys of pet ownership come the responsibility of "cleaning-up" after the animal has defecated, especially in public places. Many prior inventors have sought various ways to conveniently collect and dispose of animal feces.
Some such inventions involve the use of tools for handling the feces, unhandy in the backyard, let alone, public places. Others include the use of combination device such as a yoke and pouch as disclosed in U.S. Pat. No. 4,502,417 (Jenkins). Many inventors have disclosed the use of a harness worn by the animal and supporting a removable waste receptacle. U.S. Pat. No. 3,656,459 (Missud) discloses a yieldably embracing harness that, depending on the size and movement of the animal, could easily misalign the waste receptacle with respect to the anus. Another invention, U.S. Pat. No. 4,156,402 (Naiztat) discloses a device which is to be tied to the animal to isolate the excrement receptacle.
U.S. Pat. No. 3,817,217 (Matuka, et al) and U.S. Pat. No. 4,444,152 (Berardo) introduce a combination harness and excrement receptacle worn by the animal. The use of buckles and straps to isolate the excrement receptacle in an isolated location about the anus is not only unhandy, but unsightly.

Apparatus for collecting animal excrement


The present invention reduces the scale of circuitry and shortens the code phase detection time needed to achieve initial synchronization. In a correlator for calculating correlation between a received spreading code contained in a received spread-spectrum signal and a reference spreading code, a combined code generator is included. The combined code generator outputs a combined spreading code by weighting and combining a plurality of phase-shifted reference spreading codes A1–AM. Further, an arithmetic circuit calculates correlation between the received spreading code and the plurality of phase-shifted reference spreading codes simultaneously. A phase detection circuit detects the phase difference between the received spreading code and a reference spreading code, namely the phase of the received spreading code from the results of the arithmetic operation.

The present invention is directed to a correlator and a delay locked loop circuit. More particularly, to a correlator for detecting the code phase of a spreading code on the transmitting side (i.e., the code phase of the received spreading code) in a case where a direct-sequence spread-spectrum signal is received, and to a delay locked loop (DLL) circuit for maintaining the synchronization between the received spreading code and a reference spreading code.
Direct-sequence code division multiple-access based upon direct-sequence spread-spectrum (DS-SS) modulation has been considered as a wireless access scheme for next-generation digital mobile communications systems. In order to receive a spread-spectrum signal, the code phase of the spreading code on the transmitting side must be detected on the receiving side and a spreading code for despreading purposes must be generated so as to achieve phase synchronization with the spreading code on the transmitting side.
Digital cellular wireless communication systems using DS-CDMA (Direct-Sequence Code Division Multiple-Access) technology have been developed as next-generation mobile communication systems for implementing wireless multimedia communications. In a CDMA digital cellular wireless communications system of this kind, a base station transmits control information and user information after multiplying this information with a spreading code. Individual mobile stations spread and transmit information using a spreading code specified by the base station. In order for a mobile station to correctly receive information such as control information from the base station in a CDMA digital cellular wireless communications system of this kind, it is necessary to identify the timing at which the spread-spectrum modulation starts at the base station, i.e., the phase of the spreading code.
FIG. 19 shows a receiver of a mobile station for a CDMA digital cellular wireless communication system. The receiver includes an antenna 1, a receiver circuit 2 for performing amplification and frequency conversion from RF (radio frequency) to IF (intermediate frequency), a QPSK detector 3 for performing QPSK detection and outputting I, Q signals and an A/D converter 4 for converting baseband analog I, Q signals output from detector 3 to digital I, Q data, a despreading circuit 5 for applying despread processing to the I, Q data output by the A/D converter 4, a data demodulator 6 for performing synchronous detection, data discrimination and error correction, a correlator 7 for performing a correlation operation in order to identify spread start timing (the phase of the received spreading code) and a timing decision unit 8 for identifying spread start timing (phase) from correlation value.
The correlator 7 performs a correlation operation between a received spread-spectrum data sequence and a reference spreading code sequence (a spreading code sequence identical with that on the side of the base station).
As shown in FIG. 20, a spreader 9 on a transmitting side executes spread processing and transmits a signal indicated by:X(t)=a(t)·c(t)
Where a(t) represents transmitted data and c(t) a PN (pseudorandom number) sequence.
The PN sequence c(t) is a spreading code sequence of "1"s and "0"s. The same code sequence (a code sequence of N chips) is repeated on a per-symbol basis, wherein one symbol corresponds to one-bit of data.
The signal x(t) is received on the receiving side, where the correlator 7 calculates the correlation between the signal x(t) and a reference spreading code c(t−τ) and outputs a correlation value R(t) indicated by the following equation:
                              R                                (            t            )                          =                                  Σ                                                                                x                                            (                t                )                                      ·                          c                                            (                                  t                  -                  τ                                )                                                                                =                                          Σ                                                                                a                                                  (                  t                  )                                            ·                              c                                                  (                  t                  )                                            ·                              c                                                  (                                      t                    -                    τ                                    )                                                                    ,                  t          =          Tc                ,                  2                    Tc                ,                  ⋯                                                                          N            ·            Tc                              where τ represents a code shift (phase difference) between the spreading code on the transmitting side and the reference spreading code of the correlator on the receiving side. The integration interval is the duration of one symbol (the time period of N chips, which is equal to N·Tc).
If "a(t)=1" holds in the above equation, the correlation value R(t) will indicate the auto correlation value of the PN sequence. If the PN sequence is an M sequence, R(t)=N (1 when normalized) is obtained as a maximum at τ=0 and R(t)=1/N holds at τ≠0. In actuality, a(t) is unknown and may be "1" or "0". However, by assuming for example that "1"=−1 and "0"1, and integrating the absolute value of a(t)·c(t)·c(t−τ), R(t)=1 is obtained at τ=0 and R(t)=1/N at τ≠0.
Thus, by calculating correlation values while changing the phase of the reference spreading code c(t−τ) one chip width Tc at a time and detecting the timing at which the correlation value exceeds a set level, it is possible to identify the spread start timing on the transmitting side (the phase of the spreading code on the transmitting side). Accordingly, the timing decision unit 8 of FIG. 19 acquires the spread start timing (phase) based upon the timing at which the correlation value output by the correlator 7 exceeds the set level and inputs this timing to the despreader circuit 5.
A matched filter and a sliding correlator are available as the principal correlation detection techniques applied to DS-SS signals.
FIG. 21 shows a matched filter 71. The matched filter includes an N-chip shift register (s1–sN) 71a for successively shifting the received spread-spectrum data sequence of the baseband (the output of the A/D converter in FIG. 19) at the chip frequency. Also included is an N-chip shift register (c1–cN) 71b for storing the reference spreading code sequence, N-number of multiplying corresponding bits of the baseband spread-spectrum data sequence and reference spreading code sequence. An adder circuit 71d is further included for adding the outputs of the multipliers and a PN generator 71e for generating the PN sequence (the reference spreading code sequence).
The reference spreading code sequence is composed of N chips. The matched filter 71 outputs one correlation value R(t) per chip period Tc and then successively outputs a correlation value every time the phase of the baseband spread-spectrum data sequence changes by one chip width Tc. The matched filter thus outputs correlation values of N-number of different phases over the period of one symbol.
The timing decision unit 8 monitors the correlation value R(t) output by the matched filter 71, determines whether the correlation value has exceeded the set level and identifies the start of the spreading code sequence on the transmitting side (spread start timing) when the correlation value exceeds the set level.
FIG. 22 shows a sliding correlator 72, which includes a PN generator 72a for generating a PN sequence (reference spreading code sequence). The reference spreading code sequence is composed of N chips and is generated cyclically at the symbol period T (=N×Tc). Further, multiplier 72b multiples the baseband spread-spectrum data sequence (the received signal) by the reference spreading code sequence chip by chip and outputs the result.
An integrator 72c integrates N chips of the output of multiplier 72b and outputs the correlation value R(t). The integrator 72c includes an adder 73 for adding the output of the multiplier 72b and the current integrated value, and a delay circuit 74 for outputting the integrated value from adder 73 upon delaying the value by one chip period.
The sliding correlator 72 outputs one correlation value R(t) in one symbol period (the period of N chips) and shifts the phase of the reference spreading code by one chip every symbol, thereby outputting correlation values of N-number of different phases over the period of N symbols (=N2·Tc).
The timing decision unit 8 monitors the correlation value R(t) output by the sliding correlator 72 to determine whether the correlation value has exceeded the set level. Further, the timing decision unit shifts the phase of the reference spreading code if the correlation value is less than the set level and identifies the start of the spreading code sequence on the transmitting side when the correlation value exceeds the set level.
Thus, the phase of the spreading code on the transmitting side can be detected at a precision of within one chip by the matched filter or sliding correlator. (This is referred to as "synchronization acquisition".) This is followed by performing despreading by generating the spreading code sequence in sync with the detected phase to despread on the receiving side.
However, if no further action is taken once synchronization has been acquired, the synchronizing position will be lost owing to the effects of modulation and noise. This makes it necessary to exercise control in such a manner that the spreading code sequence on the receiving side will not develop a time shift with respect to a received signal for which synchronization has been acquired. (This is referred to as "synchronization tracking".) A DLL (Delay Locked Loop) is known as such a synchronization tracking circuit.
FIG. 23 shows a DLL circuit, which includes a PN generator 9a that generates a first PN sequence (the reference spreading code). The PN generator 9a has nine delay circuits D1–D9 and an Ex-OR gate provided at the input of the fourth delay circuit. This configuration outputs a PN sequence of an M sequence in accordance with X9+X4+1. The first PN sequence A1 is composed of N chips (=29=512) and is generated cyclically at the symbol period T (=N×Tc).
A delay circuit 9b delays the first PN sequence (reference spreading code) A1 by one chip and outputs a second PN sequence A2. A multiplier 9c multiplies, chip by chip, the first PN sequence A1 output by the PN generator 9a and a received spread-spectrum data sequence B. A multiplier 9d multiplies, chip by chip, the second PN sequence A2 delayed by one chip and the received spread-spectrum data sequence B.
Further, an adder 9e adds the output of the multiplier 9c and a signal obtained by inverting the code output by the multiplier 9d. The output of the adder 9e is input to a low-pass filter 9f, the output whereof is applied to a voltage-controlled oscillator (VCO) 9g, which varies the clock frequency (chip frequency) based upon the output of the low-pass filter.
The multiplier 9c and low-pass filter 9f function to calculate the correlation between the first PN sequence A1 and the received spread-spectrum data sequence B. If the phase of the first PN sequence and the phase of the received spread-spectrum data sequence match, the maximum output is obtained.
As shown in (a) of FIG. 24, a correlation value R(τ)=1 having the width of one chip is output every symbol. If the phase shifts by the width of one chip or more, the correlation value R(τ) becomes 1/N.
The multiplier 9d and low-pass filter 9f function to calculate the correlation between the second PN sequence A2 delayed by one chip width and the received spread-spectrum data sequence B. If the phase of the second PN sequence and the phase of the received spread-spectrum data sequence match, the maximum output is obtained and a correlation value R(τ) is output, as shown in (b) of FIG. 24. If the phase shifts by the width of one chip or more, the correlation value R(τ) becomes 1/N. The adder 9e adds the output of the multiplier 9c and a signal obtained by inverting the output of the multiplier 9d. As a result, a signal having an S-curve characteristic shown in (c) of FIG. 24 with respect to a phase difference τ is output via the low-pass filter 9f.
On the basis of the output of the low-pass filter, the voltage-controlled oscillator 9g controls the clock frequency in such a manner that the phase difference τ becomes zero. For example, if the phase of the PN sequence (reference spreading code) leads that of the received spreading code, control is performed so as to make the phase difference zero by lowering the clock frequency. If the phase of the PN sequence (reference spreading code) lags behind that of the received spreading code, control is performed so as to make the phase difference zero by raising the clock frequency.
Thus, the phase of the spreading code sequence on the transmitting side is detected (synchronization acquisition) at a precision of within one chip by the correlator (the matched filter of FIG. 21 or sliding correlator of FIG. 22), and then synchronization tracking is carried out by the DLL circuit.
FIG. 25 shows another example of a DLL circuit. In particular, FIG. 25a shows a DLL circuit having a configuration similar to FIG. 23. FIG. 25(b) shows a configuration of another DLL circuit obtained by modifying the DLL circuit of FIG. 25(a). Since multiplication by the PN code and adding the results of multiplication are linear operations, the operations can be interchanged in terms of their order. Accordingly, the DLL circuit of FIG. 25a provides an equivalent function even if the adjacent first and second PN code sequences are multiplied by +1 and −1 by multipliers 9h, 9I, respectively. Further, the products are added by an adder 9j and the received signal is multiplied by the value of the sum, as shown in FIG. 25(b).
The time needed to detect a code phase, the scale of the circuitry and the power consumption associated with the matched filter are compared with those associated with the sliding correlator, the following results are obtained:
(1) If the code length for obtaining correlation is N chips, the code phase detection time required for initial synchronization of reception will be N chips (=N·Tc) in case of the matched filter and N2 chips (=N2·Tc) in case of the sliding correlator. In other words, the matched filter requires less time to detect the code phase, namely 1/N of the time required in case of the sliding correlator.
(2) The scale of the circuitry in a case where the correlator is implemented by digital processing is understood from FIGS. 21 and 22. Specifically, the matched filter requires two shift registers each having a length equivalent to the number of taps (=N), multipliers equivalent to the number of taps and one cumulative adder. The sliding correlator, on the other hand, requires only one multiplier and one cumulative adder. Therefore, the scale of the hardware of the matched filter is much greater than that of the sliding correlator.
(3) The power consumption of the circuitry is considered to be proportional to the product of the number of gates used and the operating frequency based on the assumption that CMOS LSI circuitry is used. The operating frequency is the chip frequency or the over-sampling frequency of the chip in the case of both the matched filter and sliding correlator. Power consumption, therefore, is considered to be proportional to the scale of the circuitry. Accordingly, the power consumed by the matched filter is much greater than that by the sliding correlator.
Although the matched filter is advantageous in that code phase detection time is short, the scale of the circuitry is very large. A problem that arises, therefore, is that a matched filter cannot be used in a mobile station, which requires low power consumption. The sliding correlator, on the other hand, has the advantage of small-scale circuitry. However, since code phase detection time is long, achieving initial synchronization in the demodulation operation takes time which causes degradation of the system characteristics.
Further, with the conventional DLL circuit, the phase synchronization acquisition range (i.e., the lock range) is small, namely the width of one chip or −Tc/2 to Tc/2, as is evident from FIG. 24(c). However, a problem that arises is that synchronization tracking can no longer be performed if a phase shift in excess of one chip occurs.


A roller for an image forming apparatus comprises: a core body having a shaft positioned in the center thereof, the core body being formed by solidifying a fluid around an outer circumference of the shaft; and a surface layer formed on a surface of said core body, the surface layer being made of hard rubber and having a uniform thickness over the surface of the core body. A mold for the roller, comprises: an inner surface whose section is the same as a section of the core body; a pair of half-split bodies, one end wall of each half-split body having a recess for clamping the shaft, other end wall of each half-split body having a injecting hole for injecting a core body forming fluid therefrom; and a stopper body serving as an aligning member having a through hole in the middle thereof for inserting the shaft thereinto, the stopper body further projecting a stopper on an outer circumference thereof for fitting the stopper into the injecting hole.

The invention relates to a roller for an image forming apparatus such as a platen roller, and to a mold for forming such a roller.
For example, a wire dot printer forms desired characters and graphics on a recording sheet by impinging the tips of wires onto the recording sheet through an ink ribbon. As a result of this operation, there exists the problem that impinging noise is made during data writing.
In order to overcome this problem, the present applicant has proposed a platen roller in Unexamined Japanese Patent Publication No. Sho. 63-256470. Unlike a platen roller that has heretofore been constructed of a hollow metal pipe, the proposed platen roller is characterized by charging air-bubble-containing concrete into such hollow pipe. As a result of this construction, the propagation of noise is controlled to implement low noise design. On the other hand, this platen roller imposes difficulties in molding the roller shaft with correct shaft center ensured, as well as the problem of noise absorption, durability, and the like.

Method of forming a roller and mold for forming the same


Methods of fabricating metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions are provided. The MOS transistors formed by these methods may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques.

As semiconductor devices having metal-oxide-semiconductor (MOS) transistors become more highly integrated, the contact sizes and junction depths of the source/drain regions of these devices have been reduced. Accordingly, a salicide (self-aligned silicide) technique is widely used in the fabrication of highly integrated MOS transistor semiconductor devices in order to allow improvement in certain electrical characteristics of the MOS transistors such as the contact resistance of the source/drain regions. However, if metal silicide layers are formed on shallow source/drain junctions, the junction leakage current of the source/drain regions may be increased. Thus, the use of elevated source/drain structures has been proposed to help reduce and/or minimize the contact resistance. Such a technique is discussed in U.S. Pat. No. 6,440,807 to Ajmera et al.
FIGS. 1 to 3 are cross-sectional views illustrating a conventional method of fabricating a semiconductor device that is described in U.S. Pat. No. 6,440,807.
As shown in FIG. 1, a gate insulating layer 52 is formed on a semiconductor substrate 50. A polysilicon pattern 54 and a silicon nitride pattern 56 are sequentially stacked on the gate insulating layer 52. Sidewall spacers 60 are formed on sidewalls of the polysilicon pattern 54. The sidewall spacers 60 may be formed of silicon nitride. Source/drain regions 64 are formed in the semiconductor substrate 50 adjacent both sides of the polysilicon pattern 54. The source/drain regions 64 may be formed using an ion implantation process and an annealing process.
As shown in FIG. 2, an epitaxial layer 62 is grown on the source/drain regions 64 to provide elevated source/drain structures. The epitaxial layer 62 is not grown on the polysilicon pattern 54, since the polysilicon pattern 54 is surrounded by the silicon nitride pattern 56 and the insulating sidewall spacers 60. Then, as shown in FIG. 3, the silicon nitride pattern 56 is removed, and a metal silicide layer (not shown) may be formed on the polysilicon pattern 54 and the epitaxial layer 62 to lower the contact resistance of the polysilicon pattern 54 and the source/drain regions 64.
Even though the source/drain regions 64 may be formed to have a shallow junction depth, the elevated source/drain structures may provide sufficient junction depth to reduce and/or minimize the junction leakage current of the source/drain regions 64. Accordingly, by forming the metal silicide layer in the epitaxial layer 62, it may be possible to provide a device having a shallow junction depth and a relatively low contact resistance.
As noted above, epitaxial growth techniques may be used to form MOS transistors having elevated source/drain structures. However, if crystalline defects or contaminants exist at the surface of the substrate, it may be difficult to form a uniform epitaxial layer on the defective surface. For example, if impurity ions are implanted into a single crystalline semiconductor substrate, an amorphous layer may be formed at the surface of the substrate to a depth of, for example, about 300 angstroms. Such an amorphous layer may lead to an abnormal epitaxial layer. This may be particularly true in cases where P-type impurity ions are implanted into the semiconductor substrate.
As noted above, in the methods discussed in U.S. Pat. No. 6,440,807, the epitaxial layer is grown on source/drain regions that are formed using an ion implantation process and an annealing process. The ion implantation process typically generates crystalline defects or an amorphous layer at the surface of the substrate. Thus, U.S. Pat. No. 6,090,691 discloses a method of fabricating elevated source/drain structures without use of an epitaxial layer.
The crystalline defects, which are due to the ion implantation damage, can be reduced, minimized and/or eliminated by increasing the annealing process time or raising the annealing temperature. However, increasing the annealing process time and/or the annealing temperature tends to cause additional diffusion of the impurity ions in the extension regions which can lead to a short channel effect with the MOS transistor.

Methods of fabricating MOS transistors having recesses with elevated source/drain regions


An amplifier has a cascade circuit including an input circuit, a cascode circuit and an output circuit. The input circuit receives input signals via an input (10), which input signals are converted to amplified signals by the cascode circuit. These amplified signals are subsequently supplied to an output (94) by the output circuit. The cascode circuit includes two input transistors (40 and 62) and an output transistor (74). By means of three capacitors (32, 46 and 50) and a coil (48), the cascode circuit is built up in such a way that the input transistors (40 and 62) are parallel-connected for comparatively high-frequency input signals, while the input transistors (40 and 62) are series-connected for comparatively low-frequency supply signals. This results in the transconductance being doubled, while the DC collector current or drain current remains the same. By doubling the transconductance, the contribution of the cascode circuit to the intermodulation distortion in the amplified signals is reduced substantially. As the DC collector current or drain current remains unchanged, the power dissipated in the amplifier remains substantially the same.

The invention relates to an amplifier comprising a cascade circuit including an input circuit, a cascode circuit and an output circuit, the input circuit receiving input signals via an input, and the cascode circuit converting the input signals to amplified signals, the output circuit supplying the amplified signals to an output, and the cascode circuit comprising an input transistor and an output transistor.
The invention also relates to a CATV amplifier module comprising a cascade circuit including an input circuit, a cascode circuit and an output circuit, the input circuit receiving input signals via an input, and the cascode circuit converting the input signals to amplified signals, the output circuit supplying the amplified signals to an output, and the cascode circuit comprising an input transistor and an output transistor.
The invention further relates to a cascode circuit for amplifying input signals, comprising an input transistor and an output transistor.
Such an amplifier is well-known and applied, inter alia, in the CATV amplifier module BGD902 developed by PHILIPS. Such CATV amplifier modules are employed in coaxial cable networks to maintain the signal level. For this purpose, these CATV amplifier modules comprise a cascade circuit including, respectively, an input circuit, an amplifier circuit and an output circuit. As these CATV amplifier modules must meet very high distortion requirements, the amplifier circuits are generally embodied so as to be symmetrical push-pull amplifiers. By virtue of this measure, the second-order products formed cancel each other out in the output circuit. In this respect, it is very important that both amplifier branches should be symmetrically driven and loaded. In the known CATV amplifier module, two cascode circuits, accommodated in a symmetrical push-pull configuration, are responsible for amplifying the input signals. It is to be noted that the amplifier in accordance with the invention does not necessarily comprise a plurality of cascode circuits accommodated in a symmetrical configuration. The amplifier in accordance with the invention may alternatively comprise only one cascode circuit.
The known cascode circuit is responsible for a comparatively high intermodulation distortion contribution to the amplified signals.
It is an object of the invention to provide an amplifier of the type mentioned in the opening paragraph, in which the cascode circuit""s contribution to the intermodulation distortion in the amplified signals is comparatively small.
To achieve this, the amplifier in accordance with the invention is characterized in that the cascode circuit comprises a further input transistor, the input transistor and said further input transistor being parallel-connected for comparatively high-frequency input signals, and the input transistor and said further input transistor being series-connected for comparatively low-frequency supply signals. The invention is based on the recognition that the comparatively high contribution to the intermodulation distortion by the known cascode circuit is caused predominantly by the input transistor. This can be attributed to the non-linear relation between the collector current and the base-emitter voltage (for a bipolar input transistor) or between the drain current and the gate-source voltage (for a field effect input transistor). It is well known that the influence of these non-linearities can be reduced by increasing the transconductance of the input transistor.
The transconductance of a bipolar transistor can be readily increased by increasing the DC collector current Ic (a supply signal). Likewise, the transconductance of a field effect transistor can be readily increased by increasing the DC drain current Id (a supply signal). However, for many amplifiers, including the above-mentioned CATV amplifier modules, this does not constitute a workable alternative because the amplifier""s power dissipation is subject to strict limitations.
Providing the cascode circuit with an additional input transistor, which, for comparatively high-frequency (for example RF) input signals, is parallel-connected to the input transistor already present, and which is series-connected, for comparatively low-frequency (for example DC) supply signals, to said input transistor already present, results in the transconductance being doubled, while the DC collector current or the drain current remain the same. By doubling the transconductance, the contribution of the cascode circuit to the intermodulation distortion in the amplified signals is reduced substantially. As the DC collector current or drain current remains unchanged, the power dissipated in the amplifier remains substantially the same.
It is to be noted that United States patent specification U.S. Pat. No. 4,590,436 discloses an amplifier circuit wherein two transistors are parallel-connected for AC input signals and said transistors are series-connected for DC input signals. As a result of the DC series-connection of the transistors, only half the supply voltage is applied across the two transistors. By virtue thereof, the supply voltage is not limited to a value equal to half the breakdown voltage of the individual transistors. The use of a higher supply voltage will lead, however, to a higher power dissipation in this known amplifier. A further difference between this known amplifier and the amplifier in accordance with the invention resides in that the known amplifier does not comprise a cascode circuit. Besides, in said United States patent specification no mention is made of influences of the known amplifier on the intermodulation distortion contribution in the amplified signals.
An embodiment of the amplifier in accordance with the invention is characterized in that the input transistor receives the input signals on a control electrode, and the output transistor supplies the amplified signals on a first main electrode, a second main electrode of the output transistor being connected to a first main electrode of the input transistor, and the control electrode being connected via a first capacitor to a further control electrode of the further input transistor, and the first main electrode of the input transistor being connected via a second capacitor to a further first main electrode of the further input transistor, a second main electrode of the input transistor being connected via a third capacitor to a further second main electrode of the further input transistor, and the second main electrode of the input transistor being connected via a coil to the further first main electrode of the further input transistor. By virtue of the fact that all corresponding electrodes of the input transistors are connected to each other via capacitors, it is achieved in a simple way that the input transistors for comparatively high-frequency input signals are parallel-connected. In addition, the coil, which is preferably embodied so as to be a choke coil having a core of a soft-magnetic material (for example ferrite), ensures that the input transistors for comparatively low-frequency supply signals are series-connected.

Cascode circuit capable of contributing a comparatively low intermodulation distortion in the amplified signals