A semiconductor device includes: a memory having a memory space for recording data, the memory space including addresses; at least one first storage section for storing at least a portion of an address at which access to the memory space is requested and/or data which is requested to be written to the memory space; and an operation restriction circuit for at least partially restricting operations to be performed on the memory. The operation restriction circuit controls restriction on the operations to be performed on the memory based on at least a portion of the data and/or the address stored in the at least one first storage section.

This application claims priority to Japanese Patent Application Number 2000-180627 filed Jun. 15, 2000, the content of which is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to a semiconductor device having a memory space composed of rewritable semiconductor memory cells, and a control device for use therewith. In particular, the present invention relates to a semiconductor device having a security function for protecting from unauthorized access any content which is stored in the memory space, and a control device for use therewith.
2. Description of the Related Art
A semiconductor device such as a semiconductor memory device has a memory space composed of rewritable semiconductor memory cells which are represented by respective addresses. A semiconductor memory device may store information (such as copyright-protected subject matter or privacy information of individuals) which should not be subjected to unauthorized reading by a third party, or information which should not be subjected to unauthorized overwriting (as in the case of IC card applications). There have been proposed some semiconductor devices having a memory space, and control devices for use therewith, which have a security function for protecting the stored contents (data) from such unauthorized access.
Hereinafter, a conventional semiconductor device having a security function will be described with reference to FIGS. 5 to 7.
FIG. 5 is a schematic block diagram illustrating a minimum structure for realizing a security function. A semiconductor device 600 shown in FIG. 5 includes a memory accessing means 604, a memory 613 having a memory space (semiconductor memory cells) for storing data, and a security means 609 inserted therebetween. With the security means 609, it is possible to restrict some or all of the operations which are externally requested.
The memory accessing means 604 externally receives an address signal 601, a control signal 602, and a data signal 603, and outputs an address signal 605 which designates one or several of the storage units (semiconductor memory cells) in the memory space of the memory 613 to which access is to be made; a control signal 607 which designates the type and/or content of access to be performed to the memory 613; and a data signal 608 which is used for inputting or outputting of data in accordance with the designated content in the memory 613.
The security means 609 is capable of restricting some or all of the operations which are represented by a signal which is output from the memory accessing means 604 to the memory 613. For example, the security means 609 is capable of restricting the reading of any content which is stored in the memory 613, restricting the overwriting of any content which is stored in the memory 613, or both.
A given operation which is instructed by the memory accessing means 604 to be per formed on the memory 613 is represented by the address signal 605, the control signal 607, and the data signal 608 which are output to the security means 609. In the case where the content of the operation which is instructed by the memory accessing means 604 to be performed on the memory 613 is permitted, the security means 609 outputs an address signal 610, a control signal 611, and a data signal 612 to the memory 613 to perform an operation as instructed by the memory accessing means 604. On the other hand, in the case where the content of the operation which is instructed by the memory accessing means 604 to be performed on the memory 613 is not permitted, the security means 609 applies a conversion process to at least one of the address signal 610, the control signal 611, and the data signal 612. If the externally instructed operation involves outputting of the data which is stored in the memory 613, the security means 609 applies a conversion process to the data signal 608 which is output from the security means 609 to the memory accessing means 604. Thus, the operations to the memory 613 are restricted so that any operations which are not permitted will not occur, thereby realizing a security function for the memory 613.
All of the component elements of the semiconductor device 600 shown in FIG. 5 may be provided on one device. Alternatively, the component elements may be distributed over a number of devices so that a security function will be realized when the devices are used in combination. For example, in the case where the security function is to be realized on a single device, an interface circuit for interfacing with the exterior of the device may be utilized as the memory accessing means 604, while a circuit for restricting some or all of the operations which require access to the memory space may be inserted (as the security means 609) between the memory 613 as a circuit having a memory space and the memory accessing means 604.
Alternatively, in the case where the security function is to be realized on a number of devices collectively, e.g., when the memory accessing means 604, the security means 609, and the memory 613 are all provided on discrete devices, a circuit for restricting some or all of the operations which require access to the memory space may be inserted (as the security means 609) between a memory controller functioning as the memory accessing means 604 and the memory 613 having a memory space.
Hereinafter, a semiconductor device which is capable of outputting dummy data when a read access to the memory is made will be specifically described, by an illustration of a structure in which read operations to a memory are restricted until deactivation of a security function.
FIG. 6 is a schematic block diagram illustrating a conventional semiconductor device 450 which realizes the above-described security function. The semiconductor device 450 includes an interface circuit 404, a security circuit 409, and a memory 413 having a memory space composed of semiconductor memory cells. The security circuit 409 includes a password storage circuit 414 for storing a password, a comparison circuit 416, and an operation restriction circuit 418 for restricting operations to be performed on the memory 413.
In accordance with the semiconductor device 450, restriction on read operations is established (i.e., a security function is set) at the time when the semiconductor device 450 is turned ON. The security function can only be deactivated if a password (security control signal) 407 which is externally input via the interface circuit 404 matches a fixed password which is stored in the password storage circuit 414 in the security circuit 409, after which read operations can be performed normally.
In the case of making an external access to the stored content (data) which is stored in a given address in the memory 413 of the semiconductor device 450, an address signal 401, a control signal 402, and a data signal 403 are input to the interface circuit 404. The interface circuit 404 outputs an internal address signal 405 and an internal control signal 406, and if necessary an internal data signal 408, to the memory 413. In the case where the security function of the memory 413 is deactivated, the operation restriction circuit 418 outputs an address signal 410, a control signal 411, and a data signal 412 to the memory 413 in accordance with the address signal 401, the control signal 402, and the data signal 403, which are externally supplied (or more directly, in accordance with the internal address signal 405, the internal control signal 406, and the internal data signal 408). As a result, a normal operation is performed.
The semiconductor device 450 is constructed in such a manner that the security function of the memory 413 is set in an initial state which follows after the semiconductor device 450 is turned ON. As a result of the restriction on some or all of the operations to the memory 413 enforced by the security circuit 409, the semiconductor device 450 either refrains from operating at all or performs an operation which is different from an instructed operation. In applications which are arranged so as to output dummy data (instead of normal data) when a read access to the memory 413 is made, once the security function is set, only the dummy data will be output in response to any read access made to the memory 413, thereby preventing any unauthorized reading.
The following methods have been proposed as methods for realizing the aforementioned function of preventing unauthorized read. For example, a method described in Japanese Laid-Open Publication No. 59-152599 ensures that, while the security function is activated, the address signal 410 is not output from the security circuit 409 to the memory 413 unless certain conditions are satisfied. According to a method described in Japanese Laid-Open Publication No. 6-250939, the security circuit 409 encrypts the data signal 412 received by the memory 413 and outputs the encrypted version of the data signal 412 to the interface circuit 404 as the data signal 408. According to yet another method, it is ensured that, while the security function is activated, the security circuit 409 does not output the control signal 411 to the memory 413 for instructing a read operation to be commenced unless certain conditions are satisfied.
In order to deactivate the read restriction for the memory 413, a password (security control signal) 407 for deactivating the operation restriction is externally input. The externally input password 407 is compared by the comparison circuit 416 against a password signal 415 representing a pass word which is stored in the password storage circuit 414. If both passwords match, the comparison circuit 416 issues an operation restriction deactivating signal (password match signal) 417 to the operation restriction circuit 418. Upon receiving the operation restriction deactivating signal 417, the operation restriction circuit 418 permits any subsequent read operations to be performed to the memory. Thereafter, read operations will be normally performed upon request of a read.
Based on the above structure, the stored content in the memory cannot be properly read by a person who does not know the password and a method for inputting the password. Thus, unauthorized reading by a third party can be prevented if the password and the method for inputting the password are not made public.
FIG. 7 is a schematic block diagram illustrating a system 500 which realizes a security function for a semiconductor device by employing a different structure from that illustrated in FIG. 6. The system 500 includes control device 501 (e.g., CPU) which requests access to the memory, a semiconductor device 550 having a security function, and a security control device 506. In the system 500, the control device 501 outputs an address signal 502, a control signal 503, and a data signal 505 to the semiconductor device 550 to perform an operation on the semiconductor device 550. However, the control device 501 cannot take full control of the semiconductor device 550 unless the security function of the semiconductor device 550 is deactivated.
The security control device 506 is xe2x80x9cchallengedxe2x80x9d to deactivate the security function of the semiconductor device 550 as follows. The security function of the semiconductor device 550 is deactivated only when the semiconductor device 550 recognizes from the content of a security communication signal 504 that the security control device 506 is a device which is predetermined to be granted access thereto. If the transmitter/recipient of the security communication signal 504 is not recognized as the predetermined device, the security function is not deactivated, and some or all of the operations to be performed on the semiconductor device 550 remain restricted.
During an initial state after the system 500 is turned ON, the security function of the system 500 is activated, so that the contents stored in the semiconductor device 550 cannot be properly read by an external device. The semiconductor device 550 xe2x80x9cchallengesxe2x80x9d the security control device 506, i.e., transmits to the security control device 506 a signal (security communication signal) 504 for recognizing what device is being coupled to the semiconductor device 550, and the security control device 506 returns a signal which the security control device 506 generates based on the signal 504. The semiconductor device 550 determines whether or not the returned signal 504 matches an expected value. If the returned signal 504 matches the expected value, it is determined that the proper (or authorized) security control device 506 is coupled to the semiconductor device 550 as an external device, and accordingly deactivates the security function of the semiconductor device 550. The transmission/reception of the signal 504 may be repeated multiple times to gain enhanced security.
Unlike the security function of the semiconductor device 450 shown in FIG. 6, the system 500 provides a security function which may be enforced in such a manner that the xe2x80x9crightxe2x80x9d communication to occur between the semiconductor device 550 and the security control device 506 is directed to a different content each time such a communication is made. Therefore, the security function provided by the system 500 is difficult to break via simple signal analysis.
Thus, the semiconductor device 550 can provide a very secure security function because it permits a proper read operation to occur only when the security control device 506 coupled thereto is recognized as a predetermined device.
Instead of the above-described example where unauthorized reading is prevented, a security function can also be realized to restrict other types of operations as well. For example, in order to prevent unauthorized overwriting of the content stored in a memory, the same conditions as those described above for establishing or deactivating restriction on read operations can be applied for establishing or deactivating restriction on overwrite operations.
However, the above-described conventional method for realizing a security function has the following problems.
In the semiconductor device 450 shown in FIG. 6, since a fixed protocol is always used for deactivating the security function, a third party may relatively easily discover a security deactivating method by analyzing the input signals, e.g., the password (security control signal) 407.
On the other hand, the system 500 shown in FIG. 7, the content of the output (i.e., the security communication signal 504) from the security device 506 which is expected by the semiconductor device 550 can be varied, whereby a more secure security function can be realized. However, this structure has cost and/or size-related disadvantages associated with the security control device 506, which needs to be provided externally to the semiconductor device 550.
In one aspect of the present invention, there is provided a semiconductor device including: a memory having a memory space for recording data, the memory space including addresses; at least one first storage section for storing at least a portion of an address at which access to the memory space is requested and/or data which is requested to be written to the memory space; and an operation restriction circuit for at least partially restricting operations to be performed on the memory, wherein the operation restriction circuit controls restriction on the operations to be performed on the memory based on at least a portion of the data and/or the address stored in the at least one first storage section.
In accordance with the above structure, it is possible to control restriction on operations to be performed on the memory by utilizing at least a portion of data requested to be written to the memory space and/or an address at which the data is requested to be written. Some or all of the operations requiring any access to the memory space can be restricted until the operation restriction circuit deactivates restriction on operations to be performed on the memory, for example. Thus, it is difficult for a third party to decipher the method for deactivating the security function. Since it is not necessary to provide any special devices external to the semiconductor device for realizing the security function, there is no substantial penalty associated with the product size and/or cost.
In one embodiment of the invention, the access is a write operation.
In another embodiment of the invention, the at least one first storage section comprises a plurality of storage subsections.
In accordance with the above structure, (a portion of) a plurality of data requested to be written to the memory space and/or a plurality of addresses at which the data is requested to be written can be stored. Thus, it becomes even more difficult f or a third party to decipher the method for deactivating the security function, whereby a semiconductor device can be realized which cannot be easily subjected to unauthorized utilization.
In another embodiment of the invention, if at least one of the at least one first storage section does not contain the address or data stored therein, the operation restriction circuit maintains restriction on the operations to be performed on the memory.
In accordance with the above structure, security can be provided in a state (e.g., an initial state) where not all of the storage subsections contain (a portion of) data and/or an address.
In still another embodiment of the invention, the at least one first storage section includes an address storage section for storing the address, and a data storage section for storing the data; the semiconductor device includes a comparison circuit for performing a comparison of data in the memory space as designated by the address stored in the address storage section against the data stored in the data storage section; and the operation restriction circuit maintains restriction on the operations to be performed on the memory if a result of the comparison by the comparison circuit does not match.
In accordance with the above structure, a higher level of security can be realized because it is possible to confirm at the time of a read operation that the stored data has not been altered.
In still another embodiment of the invention, the semiconductor device further comprises: a second storage section for storing a reference address; and a comparison circuit for performing a comparison of the address stored in the first storage section against the reference address stored in the second storage section, wherein the operation restriction circuit deactivates restriction on the operations to be performed on the memory if a result of the comparison by the comparison circuit matches.
In accordance with the above structure, a higher level of security can be realized by comparing the addresses stored in the first storage section against the reference addresses stored in the second storage section.
In still another embodiment of the invention, the memory includes a storage unit for containing data which is to be concurrently rewritten; and the first storage section is included in the storage unit.
In accordance with the above structure, it becomes possible to vary security conditions by concurrently rewriting the contents stored in at least a portion of the memory space of the memory and the first storage section, whereby a higher level of security can be provided. Note that the second storage section should not be formed within the memory rewriting unit because if the second storage section were formed within the memory rewriting unit, the content stored in the second storage section would be lost when the rewriting unit is overwritten, thereby allowing a user an opportunity to freely set the content after the overwriting.
In another aspect of the present invention, there is provided a control device for controlling a memory having a memory space for recording data, the memory space including addresses, the control device comprising: at least one first storage section for storing at least a portion of an address at which access to the memory space is requested and/or data which is requested to be written to the memory space; and an operation restriction circuit for at least partially restricting operations to be performed on the memory, wherein the operation restriction circuit controls restriction on the operations to be performed on the memory based on at least a portion of the data and/or the address stored in the at least one first storage section.
In accordance with the above structure, it is possible to control restriction on operations to be performed on the memory by utilizing at least a portion of data requested to be written to the memory space and/or an address at which the data is requested to be written. Some or all of the operations requiring any access to the memory space can be restricted until the operation restriction circuit deactivates restriction on operations to be performed on the memory, for example. Thus, it is difficult for a third party to decipher the method for deactivating the security function. By embedding the security function in any device (e.g., a memory controller) on a given system other than the memory, the penalty associated with the product size and/or cost can be reduced.
In one embodiment of the invention, the access is a write operation.
In another embodiment of the invention, the at least one first storage section comprises a plurality of storage subsections.
In accordance with the above structure, it becomes even more difficult for a third party to decipher the method for deactivating the security function, whereby a control device can be realized which cannot be easily subjected to unauthorized utilization.
In another embodiment of the invention, if at least one of the at least one first storage section does not contain the address or data stored therein, the operation restriction circuit maintains restriction on the operations to be performed on the memory.
In accordance with the above structure, security can be provided in a state (e.g., an initial state) where not all of the storage subsections contain (a portion of) data and/or an address.
In still another embodiment of the invention, the at least one first storage section includes an address storage section for storing the address, and a data storage section for storing the data; the semiconductor device includes a comparison circuit for performing a comparison of data in the memory space as designated by the address stored in the address storage section against the data stored in the data storage section; and the operation restriction circuit maintains restriction on the operations to be performed on the memory if a result of the comparison by the comparison circuit does not match.
In accordance with the above structure, a higher level of security can be realized because it is possible to confirm at the time of a read operation that the stored data has not been altered.
In still another embodiment of the invention, the control device further comprises: a second storage section for storing a reference address; and a comparison circuit for performing a comparison of the address stored in the first storage section against the reference address stored in the second storage section, wherein the operation restriction circuit deactivates restriction on the operations to be performed on the memory if a result of the comparison by the comparison circuit matches.
In accordance with the above structure, a higher level of security can be realized by comparing the addresses stored in the first storage section against the reference addresses stored in the second storage section.
In still another embodiment of the invention, the memory includes a storage unit for containing data which is to be concurrently rewritten; and the first storage section is included in the storage unit.
In accordance with the above structure, it becomes possible to vary security conditions by concurrently rewriting the contents stored in at least a portion of the memory space of the memory and the first storage section, whereby a higher level of security can be provided. Note that the second storage section should not be formed within the memory rewriting unit because if the second storage section were formed within the memory rewriting unit, the content stored in the second storage section would be lost when the rewriting unit is overwritten, thereby allowing a user an opportunity to freely set the content after the overwriting.
Thus, the invention described herein makes possible the advantages of: (1) providing a semiconductor device having a security function for preventing unauthorized read or overwrite which can be deactivated by a method which is difficult for any unauthorized third party to analyze and decipher, such that the security function can be realized without the need to require a special external device; and (2) providing a control device for such a semiconductor device.

Semiconductor device and control device for use therewith


An electrophoresis chamber having the separation capability of a thicker chamber by the addition of a number of ports along the length of the chamber that can act as inlets or outlets. The device introduces cross flow by either a plurality of input and output ports along opposite walls of the chamber or by a tapered chamber having a plurality of output ports. Since the mobility of the particles is lateral to the direction of flow and the cross flow velocity is opposite in direction and greater than the maximum electrophoretic velocity of the particles being separated such particles are carried to the wall of a narrow linear chamber and will pass through ports provided in the wall spaced at strategic distances along the wall separation is achieved. In addition, because the sample and the outlet electrode surface are of like sign there is no deposition of the sample on the electrode surface.

1. Field of Invention
The field of this invention relates to methods and apparatus for continuous electrophoresis, that is, the separating of mixtures of microscopic charged particles in samples. More specifically, this method of continuously separating mixtures of microscopic charged particles relates to apparatus having distributive output ports for the collection of such particles in an electrical field.
2. Related Art
There are numerous methods of continuously separating mixtures of particles in electrophoresis devices. These are typified by U.S. Pat. No. 3,412,008 to STRICKLER, U.S. Pat. No. 4,061,560 to HANNIG, and U.S. Pat. No. 4,310,418 to ROSE/RICHMAN. The free flow electrophoretic process described in such patents is the result of a combination of several phenomena. The process generally utilizes a continuous laminar flow of a carrier fluid or buffer 5 through a chamber with multiple outlets as shown in FIGS. 1, 2, and 3. The sample stream 1 containing a protein or other cell particles is input into this flow and an electrical field applied to the flow in the direction generally perpendicular to the flow. The basis for separation is the resulting electrophoresis of the samples or the motion of charged particles in an electrical field. This motion is the result of the force, on the particles, which is proportional to the charge and the electrical field strength. Under the influence of this force, the particles are accelerated in a direction lateral to flow direction and approach a terminal velocity, which is the velocity reached when the force of the viscous drag on the particles and the force of the electrical field reach equilibrium. The basis for separation is that different particles generally have different lateral terminal velocities and, therefore, leave the chamber through a different exit port strategically placed for collection, thereby providing a separation device. A typical wide chamber as shown in FIG. 1 provides sufficient width to accommodate the range of mobility predicted for the sample 1. The phenomena is quantified by a characteristic known as particle mobility which is the velocity component in the direction of the electric field divided by the electrical field strength. In other prior related art, the electric field is applied across a thickness dimension of an electrophoresis chamber as shown in FIGS. 2 and 3 and a sample 1 to be separated is inserted in the laminar flow layer in the chamber. Such a method was proposed to NASA in the mid-1970s by A. STRICKLER of Beckman Instruments. This method was found to have two major faults. First, the heating of the buffer due to the electrical field and heat removal from the walls of the chamber caused convection cells which disrupted the flow at the output end of the chamber. Second, attempts to suppress the convection flow by limiting the chamber thickness resulted in very thin sample and outlet fraction layers which mixed by concentration driven diffusion thereby spoiling the separation. Electrophoresis chambers of this type have been addressed by PHILPOT in U.S. Pat. No. 3,616,453 where flow is layered between a fixed inner cylindrical wall and a rotating outer cylindrical wall causing stabilizing monotonic increases in angular momentum from the inner cylinder to the outer cylinder. The rotating cylindrical approach, while addressing these problems, results in a significant increase in mechanical complexity and potential reliability problems. The PHILPOT device as configured has 30 output fractions limiting its resolution potential. However, a relatively large sample cross-section gives it a large throughput potential.

Continuous flow electrophoresis apparatus


A magnetic field sensor that can be manufactured using the technology of surface micromechanics, having a conductor loop that has at least one deformable segment; a deformation device for deforming the deformable segment of the conductor loop with a predeterminable time dependence; a voltage sensing device for sensing the voltage induced at the ends of the conductor loop upon deformation in the presence of a magnetic field; and a magnetic field determining device for determining the present static and/or dynamic magnetic field in consideration of at least the time dependence of the deformation.

The present invention concerns a magnetic field sensor, and in particular a magnetic field sensor that can be manufactured using the technology of surface micromechanics.
Although applicable to any magnetic field sensor, the present invention and the problem on which it is based are explained with reference to a magnetic field sensor that can be manufactured using the technology surface micromechanics, for use in automotive engineering.
Magnetic field sensors can be used in many ways in automotive engineering, for example in antilock braking systems (ABS) or in automatic slip control (ASR) systems as wheel sensors, as position sensors for needle valves or ignition pulse generators, as steering wheel angle transducers, as crankshaft position transducers, etc. The demands placed on these magnetic field sensors in terms of mechanical strength, e.g. shock resistance and temperature resistance, are usually very high.
There exist in the related art a large number of known magnetic field sensors which utilize the applied force of a magnetic field on a conductor through which a current is passing. The best known example thereof is the Hall sensor.
Disadvantages that have emerged with the aforesaid known approaches are that they cannot withstand the severe mechanical and/or thermal stresses, and/or have too little sensitivity, and/or are very costly.
The magnetic field sensor according to the present invention has the advantage, as compared to known approaches to the problem, that it can be designed in such a way that it withstands severe mechanical stresses and exhibits high sensitivity simultaneously with low temperature dependence.
The underlying idea behind the present invention is that a conductor loop whose area is modulated, i.e. that has a definable time dependence, remains at a voltage as long as a magnetic field is not passing through it. As soon as this conductor loop is exposed to a magnetic field, however, the result of the area modulation is that the magnetic flux "PHgr" continually changes, causing a voltage induction that is proportional to the magnetic flux density and to the change in area over time. This voltage is picked off at the ends of the conductor loop and is analyzed in accordance with the mechanical excitation. The magnetic field sensor according to the present invention can be used to sense both constant magnetic fields and alternating magnetic fields, up to a system-related limit frequency.
According to a preferred development, in the undeformed state the conductor loop encloses an area having two longitudinal sides substantially parallel to one another, and the deformation device deforms the two longitudinal sides to change the enclosed area. It is thus advantageously possible to achieve a large change in area.
According to a further preferred development, the deformation device is configured such that it excites the two longitudinal sides to opposite-direction resonant flexural oscillations. It is thus advantageously possible to achieve a particularly large change in area utilizing resonance exaggeration.
According to a further preferred development, the conductor loop is configured such that the opposite-direction resonant flexural oscillations have a different resonant frequency from the corresponding same-direction resonant flexural oscillations. It is thereby advantageously possible to avoid interferences with the undesired same-direction resonant flexural oscillations, in which the net change in area is substantially zero.
According to a further preferred development, the deformation device is configured such that it deforms the deformable segments by way of a capacitive coupling. As a result, neither friction losses nor wear occur during excitation. In addition, capacitive excitation devices of this kind are known from other sectors, for example comb structures of acceleration sensors.
According to a further preferred development, the magnetic field sensor is manufactured using the technology of surface micromechanics, and has a substrate that is preferably made of silicon (or of another electrically conductive material). The conductor loop has substantially a rectangular shape, whose longitudinal sides are arranged floatingly above the substrate and are deformable by the deformation device, and whose widthwise sides are mounted floatingly on the substrate. This particular embodiment by high sensitivity simultaneously with low temperature dependence.
According to a further preferred development, the conductor loop has a continuous, nondeformable first widthwise side having a greater thickness than the longitudinal sides, which is connected, via at least one deformable floating strut having substantially the thickness of the longitudinal sides, to at least one connector pad anchored in the substrate. This rigid first widthwise side stabilizes the width of the surface.
According to a further preferred development, the conductor loop has a split nondeformable second widthwise side having a greater thickness than the longitudinal sides, whose parts is connected via a respective deformnable floating strut, having substantially the thickness of the longitudinal sides, to a respective connector pad anchored in the substrate. This split rigid second widthwise side also stabilizes the width of the surface, and allows the induced voltage to be picked off advantageously.
According to a further preferred development, the longitudinal sides are connected at their first end, via a deformable floating first resilient strut having substantially the thickness of the longitudinal sides, to a connector pad anchored in the substrate. With this embodiment, the split rigid second widthwise side is advantageously omitted, so that the structure becomes simpler.
According to a further preferred development, the longitudinal sides are connected at their second end, via a deformable floating second resilient strut having substantially the thickness of the longitudinal sides, to the continuous nondeformable first widthwise side.
According to a further preferred development, an additional mass is provided floatingly above the substrate in the middle of the deformable longitudinal sides. This additional mass is advantageously used to adjust the resonant frequency.
According to a further preferred development, a comb drive device connected to the longitudinal sides is provided as the deformation device. This connection can be either direct, by the fact that comb teeth are provided on the longitudinal sides; or indirect, by the fact that comb teeth are provided on an additional mass that is possibly present.

Magnetic field sensor having deformable conductor loop segment


The apparatus of the present invention improves training efficiency, and monotonous repetition of training is avoided. A unit acceptance judgment section (4) judges whether all performance of the units in the current rank have reached an acceptable standard or not. When all performance is accepted, a unit in an upper rank is designated. The performance data in the designated unit is read from a performance data storage (7) to a key depression instruction generator (8), and a key depression instruction is displayed based on the performance data. When only a part of the unit in the current rank is acceptable, a unit updating instruction is output to a lesson menu display (14), to thereby display that the unit subsequent to the currently designated is the unit to be played next. When the unit is updated, the unit having the same note information as that already accepted is not designated.

1. Field of the Invention
The present invention relates to a musical performance self-training apparatus, and more specifically, relates to a musical performance self-training apparatus that can enable efficient lesson by designating a lesson part of music to be performed, corresponding to the skill level of a player in the musical performance for a given music.
The present invention also relates to a musical performance self-training apparatus that can avoid such a situation that the training becomes boring, by having a mode in which a player him/herself can determine the training progress and a mode in which the progress is instructed automatically.
Moreover, the present invention includes a musical performance judgment apparatus that can specifically evaluate if musical performance has been done as instructed by a performance instruction based on performance data prepared in advance.
2. Description of the Related Art
There is known an apparatus which plays performance data stored in a recording medium by a personal computer, and displays an image representing sheet of music sequentially on a screen, to thereby give a performance instruction. For example, in Japanese Patent Application Laid-Open No. Hei 9-305171, there is disclosed an apparatus which gives a performance instruction in a manner of a music box in which keys are instructed sequentially by graphical bars. More specifically, in this apparatus, a figure of a keyboard is displayed on a screen, and a scroll bar having a length corresponding to the duration of key depression is also displayed corresponding to each key on the displayed keyboard, and this scroll bar is scrolled so that the scroll bar approaches the keyboard figure, as the auto-playing data is played.
According to this conventional performance instruction apparatus, the player can recognize the duration of key depression intuitively, and a key to be depressed subsequent to the key being depressed now can be known in advance. Therefore, even a player who cannot read the musical score can play smoothly, different from the apparatus which indicates performance with displaying the musical score.
However, with the conventional performance instruction apparatus, since the performance data is only played sequentially from the beginning which is monotonous, efficient training cannot be conducted and the player become bored. For example, it is quite difficult for a player, who is training for given music for the first time, to play from the top of the music to the very end all the way through. Moreover, even if the player interrupts on the way to return to the beginning, or return to a desired training part, it is troublesome and time-consuming to search the part to be played.
In a music the same phrase appears in a plurality of places, even when this phrase is mastered, when the player has the training all the way through, he/she has to play this phrase many times, and hence lesson may becomes boring. It is not efficient and not desirable to have repetitive training for the phrase mastered to a certain degree, from a viewpoint of mastering the entire music as soon as possible.
Therefore, a system in which the skill level of the entire music can be efficiently enhanced is desired, by avoiding repetition of training for the mastered phrase.
Moreover, even if there is a part which the player wants to train selectively, with the apparatus which advances training so that the entire music can be mastered at a certain skill level, selection of the training part or training progress against his/her will may be forced on the player.
In order to solve the above problem, a mode can be considered in which the player can freely determine the training progress to play, but if this mode is for freely playing far apart from the automatic mode in which the progress is instructed automatically, the relation between the automatic mode and this mode becomes weak, and hence consistent training cannot be performed. There is also a demand for a musical performance self-training apparatus, which keeps freedom in selecting progress by the player, while maintaining the training function by the automatic mode.
Furthermore, even if a player who cannot read the musical score can play certain music by an apparatus which displays a performance instruction in a manner of a music box, it is not applicable to a case in which another music is played, since the player is not able to become read the score. In other words, it is difficult to play without the performance instruction in the manner of the music box at all times.
Therefore, there is a demand for an apparatus which makes it possible not only to play particular music but also to finally play any music by reading a score, by appropriately adopting training by the score, while having training according to the performance instruction displayed in the manner of the music box.
Since the scroll bar is scrolled forward when a player has played at a right pitch, it stands by until the player plays at a right pitch, without proceeding to the next performance instruction. By this method, training can be steadily advanced, while confirming whether each note is played at the right pitch. However, according to this instruction method, the performance is standardized, and variations in performance are not allowed. Therefore, it is insufficient in view of enjoying the musical performance.
Therefore, a musical performance judgment apparatus, which is set such that even if the music performance is not conducted as instructed by the performance data, the music is advanced so long as the musical performance is within a range of a predetermined pitch, has been proposed (Japanese Patent Application Laid-Open No. 2002-175072). In this publication, it is also disclosed that players can learn performance techniques while enjoying the music, by allowing liberal judgment for the performance of music having high degree of difficulty or by adjusting the judgment method and the judgment standard in the same performance data, depending on the age and ability.
As described above, it has been heretofore considered that a player has training while confirming the played tone one by one, to learn the key-on sequence, and then gives a musical performance along to the accompaniment and metronome sound, thereby the player can finally give a natural musical performance with good tempo.
However, with respect to the rudimentary training in which a player gives a musical performance while confirming the played note one by one, and the advanced training in which the player gives a musical performance along to the accompaniment and metronome sound, a single-level performance instruction cannot correspond to these various level of trainings, since the difference in degree of difficulty between these trainings is too large.
If the ability of a trainee is finely judged, to adjust the judgment method and the judgment standard for the training highly accurately, the trainee can give a musical performance reasonably, and improvement can be expected. However, the judgment method and the judgment standard have heretofore been adjusted only according to whether the pitch is as instructed.
Therefore, there is a demand for a system, which can multilaterally judge the performance result of a trainee to recognize the ability, and determine the judgment method and the judgment standard based on the ability.
There is also proposed an apparatus which can output performance evaluation during performance or after finishing the performance (Japanese Patent Application Laid-Open No. 2001-242863). Moreover, there is known an apparatus in which when the music has not been played as instructed, for example, when a key of the right note has not been pressed, the next performance instruction is not given, nor the performance is not evaluated.
However, if the performance instruction is stopped when a player has not played correctly, a problem may occur. When the player has noticed a miss-touch, he/she can replay again immediately, but if the player has noticed a miss-touch after having played for a while, he/she must return to the beginning to give a performance again. In this case, since the evaluation after having stopped the performance instruction is not given, the player cannot know the performance evaluation, and must return to the beginning to give a performance again, without being convinced.
With such a performance instruction apparatus, the player pays attention only to the performance instruction, and cannot enjoy the performance. Trill, tremolo and the like are ways of rendition finely repeating a plurality of notes, but the number of repetition should be essentially left to the sensibility of the player. With the conventional performance instruction apparatus, however, if the number of repetition is not performed as instructed, the performance instruction is not advanced forward. Therefore, there is a demand for an apparatus which enables performance by giving much weight to the performance flow, and which can express the sensibility of the player.
In a conventional performance instruction apparatus, a player can only get information, which can be read from notes and a clef described on a musical score, and information indicating the performance timing. However, higher performance technique such as fingering cannot be understood from the musical score. Moreover, a beginner may not be able to understand the meaning of the sign written on the musical score.
As described above, in order to actually give a good performance, there are matters which a player should know other than the information expressed by the musical score, but in the conventional performance instruction apparatus, the information cannot be informed. Therefore, there is a demand for means with which the player can search the information, which is not written in the musical score, as required.

Musical performance self-training apparatus


Among other things, there are disclosed embodiments of a biopsy device using relative rotational motion to obtain a full-core biopsy sample. Inner and outer tubular members are provided connected to a handle. Each member includes a slit, and the members are rotatable with respect to each other. The device is inserted into a patient to a sampling site, and with the slits co-oriented, is extended into the sampling site. Tissue enters the tubular members through the slits, and one or both members are rotated to cut off and enclose tissue within the inner tubular member.

It is known to acquire one or more samples of tissue when particular localized medical problems are suspected, in order to test such samples and determine whether or to what extent a problem exists. For example, if a physician discovers a growth within soft tissue of a patient and wishes to test whether it is benign or cancerous, a deep biopsy sample of the soft tissue can be acquired. For such cases, biopsy devices have been developed that can be passed through skin, muscle and/or other tissues or body-walls and into the area of tissue of concern to the physician. The device's distal end cuts out a sample, e.g. a "core-sample," of the suspicious tissue.
Various forms of existing biopsy devices use a moving mandrel or cannula that facilitates movement through tissue and cutting of a sample from surrounding tissue, so that the sample may be withdrawn with the device. A quick, longitudinal movement of a cannula, for example, is generally used to cut through tissue faster than the tissue can be moved forward or out of the way by the device. Depending on the particular type of device, problems that exist with such biopsy devices can include an inability to obtain a full core of tissue. For instance, a stylet or cannula may shoot forward beyond the tissue of interest or other sampling area, or may cut only a portion of a cylinder, thus not providing a full 360-degree sample. A full core of tissue has advantages over smaller or more-limited samples in providing sufficient tissue for assay, in determining any changes or alterations in tissue at various positions in the sample (e.g. equidistant locations in various directions from the sampling path), and in noting changes in tissue as it extends from a center of the sampling area or path. Inaccuracies in the physician's or other operator's anticipation as to exactly how far the device's distal end will advance during sampling can result in the target tissue being overshot or undershot. If the operator does not know with significant accuracy the depth of the tissue of interest, or does not assess where the tissue of interest is with respect to the cutting area of the device, the insertion of the device may result in the cutting area being partially or completely outside of the tissue of interest, resulting in acquisition of tissue that does not provide the information the physician is seeking. Additionally, there may be difficulties in providing speed and/or power of forward thrust for the cannula necessary to move through and shear tens of millimeters of tissue cleanly, regardless of the tissue's density. Forward-thrusting biopsy devices, if not placed properly, if they have less-sharp edges, or if they are under-powered in propelling the cannula forward, can press tissue forward rather than shearing through it. Common results in such cases are less or no sample within the device, or crushing some or all of the tissue. It has been found that the physical state of the sample can affect its usefulness for assay or its ability to provide significant information relative to the health or other characteristics of the sample.


A sensing apparatus includes a fluxgate module which outputs an analog signal corresponding to terrestrial magnetism using a fluxgate having a magnetic substance core and a driving coil, and an analog-to-digital (A/D) converter which converts an analog signal output from the fluxgate module into a digital signal. The fluxgate module includes first and second current amplifiers for exciting the magnetic substance core by applying pulses to first and second ends of the driving coil, and a pulse restricting part for driving the first and second current amplifiers to apply the pulses and for stopping driving the first and second current amplifiers when converting the analog signal into the digital signal is completed.

1. Field of the Invention
The present invention relates to a fluxgate. More particularly, the present invention relates to a sensing apparatus having a high-efficiency fluxgate and a control method thereof capable of reducing power consumption by minimizing driving current.
2. Background of the Related Art
A fluxgate is a sensor detecting a terrestrial magnetism. The fluxgate uses a high permeability material such as permalloy as a magnetic substance core for a driving coil to apply an excited magnetic field thereto. The fluxgate also uses magnetic saturation and nonlinear magnetic characteristics of the core to measure a second harmonic component proportionate to an external magnetic field, thereby measuring the strength of the external magnetic field.
FIG. 1 is a circuit diagram of the configuration of a fluxgate module having a fluxgate to detect a signal corresponding to terrestrial magnetism. As shown in FIG. 1, the fluxgate includes a driving coil 40 for applying current to excite a magnetic substance core with current, a pulse generator 10 for generating pulses to be applied to the driving coil 40, amplifiers 30 and 31 for amplifying pulses to be applied to a first end a and a second end b, of the driving coil 40, and an inverter 20 for inverting the pulse applied to the second end b of the driving coil 40 to generate current.
Signals for turning the current amplifiers 30 and 31 on and off are due to a pulse P1 generated from the pulse generator 10. The pulse P1 from the pulse generator 10 is directly transmitted to the current amplifier 30, and is inverted through the inverter 20 to have a reversed phase when transmitted to the current amplifier 31.
Thus, pulse signals P2 and P3 applied to the first and second ends a and b, respectively, of the driving coil 40, which are respectively connected to the amplifiers 30 and 31, have opposite phases. When, at q1 of FIG. 1, the pulse signal P2 has a high level at the first end a and the pulse signal P3 has a low level at the second end b, current flows from a to b along the coil 40. On the other hand, when, at q2 of FIG. 2, the pulse signal P2 has a low level at the first end a, and the pulse signal P3 has a high level at the other end b, current flows from b to a along the coil 40. As a result, current is applied to the driving coil 40 in response to the pulse signals, thereby exciting the magnetic substance core on which the driving coil 40 is wound.
To drive the fluxgate, the pulse generator 10 is driven to apply a pulse train to the driving coil 40. Thus, when the fluxgate is driven with the driving coil 40 being driven by the generated pulse train, current flows constantly causing a high current consumption in a unit time interval.
MEMS (Micro-Electro Mechanical System) is a technology implementing mechanical and electrical parts using a semiconductor manufacturing process. A fluxgate may be minimized and integrated using MEMS technology. A fluxgate manufactured by a MEMS manufacturing process for a potable small-size terminal is generally used when there is a limited power source. Therefore, characteristic high current consumption of a fluxgate in a unit time interval can be a significant problem.
Meanwhile, the signal detected from the fluxgate goes through chopping, amplification and filtering to be input to an analog-to-digital (A/D) converter. In this case, if there are a plurality of the fluxgates, a plurality of circuits for the chopping, amplification and filtering are needed. Therefore, in the case of a fluxgate sensing apparatus to detect 2-axis magnetism, space occupied by circuits for signal processing is large. Thus, the fluxgate sensing apparatus is not compact.

This patent is subject to a terminal disclaimer.

Reduced power sensing apparatus having fluxgate and control method thereof


An imaging system and methods for using an imaging system where the operator is able to variably adjust the parallax distance for enhanced stereo performance are disclosed. In addition, by coordinating the parallax distance with the optical settings of the camera, artificial 3D experiences can be created that give a user the perception of observing a scene from a distance different than that actually employed. The imaging system may also include a plurality of stereo camera supersets, wherein a first one or more stereo camera supersets are positioned at a different height relative to a first stereo camera superset. Novel specific uses of the camera system, such as in capturing events of interest are described. Useful techniques for extracting or encoding wide field of view images from memory are also disclosed.

U.S. Pat. Nos. 7,982,777 and 8,004,558, for inventions of the present inventor with others are hereby incorporated herein by reference in their entirety. They teach a biologically inspired arrangement of cameras (and/or camera pairs) that mimics the location of the eyes of a binocular animal (such as a human) as the head is turned side-to-side or up-and-down.
A differentiating characteristic of the above technology is that, due to the arrangement of cameras, it creates potential obscuration between neighboring cameras. This is done to realize the most simple and compact configuration (as a function of parallax distance) possible. And Prechtl et. al. describe, at length, techniques by which this obscuration can be addressed and managed.
A significant parameter affecting the performance of a stereo camera system is the parallax distance employed. Some practitioners have addressed the possibility of varying the parallax distance in stereo, such as in U.S. Pat. No. 7,224,382 and US Pat. Apps. #2013/0044181 and #2013/081576.
The era of video-on-demand (VOD) is well established. Consumers are able to purchase a wide variety of videos to consume, as desired, as part of their multimedia collections. Some prior art describes the capture of a scene from multiple cameras in different ways. This is taught in U.S. Pat. No. 8,326,113 and US Patent Application #2008/0275881.
There is also a large body of art that addresses the problem of managing electronic media. This is taught in U.S. Pat. Nos. 7,243,364, 8,527,549, 8,544,047, 8,548,735, and 8,676,034.
There is also art related to measuring the size of the audience watching an event, such as that taught in U.S. Pat. No. 8,249,992.

Adjustable parallax distance, wide field of view, stereoscopic imaging system


Two opposing hinged cable routing assemblies each have a base portion and a hinged strap portion. The hinged strap portion is releasably secured to the base portion to releasably secure multiple cables therein. The cable is bent about the radiused end portion, to reduce the stress on the bent cable and to avoid damage to the radiused cable. The excess cable is taken up between the opposing cable routing assemblies. A score line is provided on the base portion adjacent to the radiused end portion, to provide a break-away radiused end portion. An intermediate cable routing apparatus may be formed of a flexible coiled wrap portion, or a flexible spiral wrap portion. The cable routing apparatus may be marked with indicia to identify a selected cable.

DEFINITIONS: For purposes of this invention, the term "cable" is intended to include electrical cable, insulated electric wire, uninsulated electric wire, twisted wire cable, fiber optic cable, plastic cable, and all cable conforming to the "Commercial Building telecommunications Cabling Standard TIA/EIA-586-A and ISO/IEC 11801, which is incorporated by reference herein.
Cable routing is a problem where cable is pre-assembled, and excess cable length has been provided to assure sufficient length for connection of a plurality of cable to a fixed location. Where numerous cables are connected to a fixed location, the excess length of each of the cables becomes a problem, creating a "rat's nest" of tangled cable, which is difficult to work with, and may create a safety hazard where emergency repairs are quickly needed.
U.S. Pat. No. 3,520,988 issuing to Ralph Ballock on Jul. 21, 1970 discloses a cable support for temporarily reducing the overall length and to eliminate tangled excess lengths.
U.S. Pat. No. 4,475,649 issuing to Willem Haarbosch on Oct. 9, 1984, discloses a storage case for an electric cord.
U.S. Pat. No. 5,168,128 issuing to Alan Thomsen on Dec. 1, 1992, discloses an anti-tangle spaced stiffener for elongated flexible members, to prevent tangling and for folding the elongated flexible member into a compact storage relationship.
U.S. Pat. No. 5,144,100 issuing to Gregory Andel on Sep. 1, 1992 discloses a wire separator apparatus having a cover flap and parallel mounting flanges.


A method and a system for authentication and synchronization is disclosed. The user provides a first one time code (OTC) to the authentication manager. If this OTC is within a small access window, the user is directly authenticated and granted access to the system. If the provided OTC is outside the small window but within a big window, the authentication manager saves the first OTC, and a second OTC is required from the user. If the new, second OTC and the first OTC are in sequence, the end user will be authenticated, and admitted access to the system and the requested service.

The need for secure electronic transactions and access to remote services involving a user and a transaction system such as an Internet based shopping site, Internet banking or an automatic teller machine (ATM) at a bank, has increased dramatically during recent years. A major question relating to secure transactions is that of authentication of the user to the system. That is, how to identify a user as being the owner of, e.g., a bank account from which the user is to withdraw money from when using an ATM or Internet banking services.
A well-established method of authenticating users in such systems is that of providing the user with an electronically readable device containing information about the user and his account. Such cards are common and contain magnetically stored information. In order to allow the user to use his card in an ATM, the issuer (e.g. the bank) has provided the user with a secret code to be supplied to the ATM when using the card. The code is used to "unlock" the card for use by the user every time the user makes use of his card.
However, a drawback of such a method is that one and the same code is used every time a user authenticates with a system. This increases the risk of unauthorized use of the card if the user loses the card.
To this end, solutions have been developed using different codes from occasion to occasion, so called one time codes (OTCs). Such OTCs could be provided to the user by means of a sequence of codes to be used one time each, and perhaps in a pre-determined order. Alternatively, the OTCs could be generated by means of portable code-generating devices, in which a new code is generated each time it is used, based on personalizing information provided by the user, such as a personal PIN-code. Such devices are generally of two types. A first type is specifically developed gadgets with entering means such as a keyboard, a display, a processor for generating the code, etc. A second type relates to so called smart cards or integrated circuit card (ICC), i.e. cards provided with a chip. For example, the document WO 02/01325 of the same applicant discloses such an authentication system using OTCs.
However, a problem in using OTCs is the problem of synchronizing the code generation/selection process at the user side and in the authentication manager, respectively. In case the processes are unsynchronized, the user will not be authenticated and authorized to access the required services or the like, even though a correct OTC was entered. Synchronization could be achieved by keeping and updating synchronization data, such as a sequence number, a time value or the like, in the same way at both user side and the authentication manager side. However, the synchronization data could easily become unsynchronized, for example due to manual errors, failed authentication attempts, different clock rates, etc.
Attempts have been made in the past to alleviate this problem. For example, several acceptable OTC could be generated or selected at the authentication manager, e.g. corresponding to a sequence of synchronization data. However, hereby the security level decreases, and the problem is only partly solved, since the sequence, or window, of acceptable OTCs may still not be enough to handle the occurred unsynchronization.
Another known solutions attempts to restore the synchronization. However, these known solutions are generally very cumbersome and tedious for the user, and may also imply a security hazard.

Method and system for user authentication in a digital communication system


A method of forming microstructures. An article including a metal atom precursor is disproportionally exposed to electromagnetic radiation in an amount and intensity sufficient to convert some of the precursor to elemental metal. Additional conductive material may then be deposited onto the elemental metal to produce a microstructure.

A multitude of techniques for shaping (such as stamping, grinding, and milling) and joining (such as welding and mechanical joining) metals are highly developed for the fabrication of macroscopic structures. Application of these techniques to the fabrication and assembly of metallic microstructures (structures having features<100 μm) becomes increasingly difficult as the feature sizes become smaller. For that reason, new approaches to microfabrication that are not derived from fabrication techniques used on a large scale have been developed. A widely used technique for fabrication of metallic microstructures is microelectrodeposition of metals on an appropriately shaped mandrel or template. Two examples of this class of processes are through-mask electroplating and LIGA (Lithographie, Galvanoformung, Abformung), both of which are based on projection photolithography (for LIGA, commonly carried out using x-rays, although the availability of the SU-8 class of photoresist has reduced the need for x-ray exposure in making thick structures). Although these methods provide ways to form metallic microstructures, they are processes with several steps, and require facilities of limited availability.
Recently, methods for the microfabrication of metallic, 2D and 3D structures based on the combination of soft lithography and microelectrodeposition have been described, the latter both through a mask of photoresist and onto patterned, conducting surfaces. The pattern-transfer step in these soft lithographic techniques typically uses an elastomeric stamp with a surface relief structure that carries the desired pattern. These stamps are usually formed by molding polydimethylsiloxane (PDMS) against a 'master' composed of a relief pattern in photoresist, and obtained by photolithography. These masters may be generated using a technique based on high-resolution commercial printing and high-resolution optical reduction. This procedure is efficient: from design, through stamp, to initial structure typically requires no more than 24 hours. Both the preparation of the mask and the generation of the master by photolithography may require access to specialized devices and facilities (i.e., high-resolution image setters, clean rooms) that are more readily available than the mask-making facilities required in high-resolution photolithography, but that are still not available to every laboratory that might benefit from medium resolution microfabrication.

Fabrication of metallic microstructures via exposure of photosensitive composition


A method of creating large hollow spheres and other shapes and structures produced according to such method, such method including suspending in a zero gravity environment a molten material mixed with a blowing agent which is caused to foam, expanding into a mass wherein the exterior sphere wall is solidified and the interior is hollowed out.

1. Field of the Invention
This invention relates to production techniques of spheres and other shaped structures at zero gravity and more particularly relates to a method of producing strong lightweight, large, Chin-walled carbon or other material spheres or other shapes for a variety of uses.
2. History of the Prior Art
The production of materials in outer space in a weightless environment including the manufacture of hollow metal spheres has been appreciated and discussed in the prior art in U.S. Pat. No. 3,534,926 to H. F. Wuenscher entitled Space Manufacturing Machine. The production of hollow spheres in a normal environment has been disclosed such as in U.S. Pat. 4,303,603 to Torobin. The desirability of spheres in outer space has been appreciated in U.S. Pat. No. 4,734,021 to Maddock.

Method of large sphere production at zero gravity


A bridge fault extractor. A computer-implemented method for performing fault extraction from an integrated circuit layout includes determining maximum critical areas from the layout for a maximum defect size of a set of defect sizes to be analyzed wherein each maximum critical area corresponds to a net-name pair. The maximum critical areas are then locally merged by net-name pair to determine an area of a union of maximum critical areas for each net-name pair.

1. Field
An embodiment of the present invention relates to the field of analysis of defects in integrated circuits and, more particularly, to extracting likely bridge sites.
2. Discussion of Related Art
A component of defect analysis is a process used to identify areas of an integrated circuit that are more likely to be adversely affected by a manufacturing defect. The output of this process is used to design manufacturing tests targeted at detecting failures that may result from such defects.
A list of bridges, for example, may be identified during defect analysis. A bridge occurs due to a point defect that extends across two or more conductive lines or nets to cause an electrical short between them.
The likelihood of occurrence of a particular bridge may be measured by its weighted critical area (WCA). The critical area for a two net bridge for a given defect size, as the term is used herein, is the area over which the center of the defect can lie and cause the two nets to bridge. The WCA of two nets is defined as the sum of the critical areas for a particular defect size weighted by the probability of occurrence of that defect size.
Carafe, developed at the University of California, Santa Cruz, is an example of such a tool that may be used to extract potential bridges. For each layer and each adjacent layer pair in a flattened layout of an integrated circuit, Carafe generates fault primitives referred to as xe2x80x9clength-widths.xe2x80x9d Then, for each defect size to be analyzed, Carafe calculates corresponding critical areas from each of the length-widths. These critical areas are merged or intersected for an entire layer or layer pair to produce the critical area contribution of two-net bridges for the layer or layer pair for the particular defect size. The critical areas for each layer and layer pair for that defect size are then added together to find the overall critical area for the defect size. This overall critical area is then weighted with corresponding defect data to produce the WCA for the defect size. The above-described method is repeated for each defect size.
This approach has a drawback in that critical areas are computed from fault primitives for each separate defect size to be analyzed. These calculations can be time consuming, particularly where many defect sizes are used. As more defect sizes are used to more closely approximate a range of defect sizes, this inefficiency becomes even more pronounced and may preclude the use of this tool for larger or more complex layouts. Further, merging the critical areas for an entire layer or layer pair can be expensive both in terms of time and storage space on a host computer.
CREST, developed at Carnegie Mellon University, is another example of a prior fault extraction tool. CREST calculates the WCA of bridges from a hierarchical layout description. By using a hierarchical layout description instead of a flattened layout as used by Carafe, CREST may save storage space on a host computer. In doing so, however, CREST may sacrifice accuracy in computing WCA values and may fail to identify important bridges that could be identified using the flattened layout.
LOBS is another example of a prior fault extraction tool. LOBS uses a sliding window algorithm to identify critical areas. LOBS places a xe2x80x9cwindowxe2x80x9d at one corner of a layout in a layer or layer pair. A small set of rules is then used to calculate the critical area contributions from the region of the layout within the window. The window is then shifted to an adjacent area and the process is repeated until the entire layout has been covered. In using the predefined rules for calculating the critical area within the window, LOBS uses approximations when the rules are not readily applicable. These approximations can cause accuracy problems that may adversely affect the output from this tool.
Thus, the particular extraction tool used to identify likely bridges can have a significant impact on the accuracy and efficiency of the fault extraction process. Inaccurate fault extraction may compromise the quality of integrated circuit tests developed based on the output of the fault extraction. Inefficient fault extraction may take an excessive amount of time such that it is not feasible to completely analyze larger, more complex circuits.
As integrated circuits continue to increase in complexity, fault extraction using prior fault extraction tools may become increasingly difficult.
A method and apparatus for extracting bridges from an integrated circuit layout are described.
For one embodiment, a computer-implemented method for performing fault extraction from an integrated circuit layout includes determining critical areas from the layout for a defect size of a set of defect sizes to be analyzed wherein each critical area corresponds to a net-name pair. The critical areas are then locally merged by net-name pair to determine an area of a union of critical areas for each net-name pair.
Other features and advantages of the present invention will be appreciated from the accompanying drawings and the detailed description that follows below.

Method and apparatus for extracting bridges from an integrated circuit layout

Abstract: Critical areas for defect sizes smaller than the maximum defect size are determined from the maximum critical areas and locally merged by net-name pair to determine an area of a union of critical areas for each net-name pair for each smaller defect size.


In equipment with a built-in fuel cell, there are provided a plurality of secondary cells, and each of the secondary cells has a first state in which an electric power is supplied to a load within the equipment, and a second state in which the electric power that is supplied from the fuel cell is charged, and the first state and the second state is selectively used. The present invention can provide the fuel cell-carried equipment that stably operates due to a power system on which a fuel cell and plural secondary cells are mounted.

A fuel cell is an electric generator that is comprised of at least a solid or liquid electrolyte, and two electrodes consisting of an anode and a cathode which induce an electrochemical reaction. It directly converts a chemical energy of the fuel into an electric energy with a high efficiency. As the fuel, there is the used of fossil fuels, hydrogen that has been chemically converted from water, methanol, alkali hydride, hydrazine which are liquid or solution in the normal environments, or dimethyl ether which is a pressurized liquidized gas. As an oxidizer gas, air or oxygen gas is used.
The fuel is electromechanically oxidized in the anode, and oxygen is reduced in the cathode, to thereby produce an electric potential difference between both of those electrodes. In this situation, when a load is applied between both of those electrodes as an external circuit, ionic migration is generated in the electrolyte, and an electric energy is provided for the external load. Various fuel cells are greatly expected as a large-scaled generator system as substitute for fire power equipment, a small-scaled diffusion type cogeneration system, or an electric vehicle power supply as substitute for an engine dynamo. Thus, the fuel cells have been actively developed so as to put into practical use.
Among those fuel cells, attention has been paid to a direct methanol fuel cell (DMFC), a metal hydride fuel cell, and a hydrazine fuel cell as effective fuel cells for a downsized mobile or portable power supply because the volume energy density of the fuel is high. In particular, DMFC employing methanol that is readily dealt with and expected to be produced from biomass in the near future as fuel is an ideal power system.
Japanese Patent Laid-Open No. 2002-216782 discloses a hybrid system having a fuel cell and plural secondary cells that are connected in parallel with the fuel cell.
The fuel cell has a propensity that it takes a long time until stably supplying an electric power required for a load (for example, electronic equipment) after starting the fuel cell because the fuel cell is a generator that converts a chemical energy into an electric power.
In view of the above, an object of the present invention is to provide equipment that is stably operated by a power system by carrying a fuel cell and plural secondary cells.


An apparatus for electrolytically generating small volumes of a selected gas such as hydrogen for introduction into a flowing gas stream is described. The gas stream flows through an electrolytic cell wherein the selected gas is generated at an electrode and a portion of the gas stream is diverted through a needle valve and a non-conducting capillary with a small orifice to deliver gas to the electrodes so as to dislodge the selected gas bubbles forming thereon and carry them into the flowing gas stream. To maintain the level of electrolyte in the cell, the cell is connected by a narrow tube to a reservoir of electrolyte. The reservoir has a volume and surface area many times greater than that of the cell and the gas volume above the reservoir is maintained at the pressure and composition of the gas stream entering the electrolytic cell.

Many devices have been designed for the electrolytic dissociation of water to produce H.sub.2 and O.sub.2 gases, for example U.S. Pat. No. 4,465,570 Y. Oda et al., 1984; U.S. Pat. No. 4,726,888 M. Mc Cambridge, 1988. Some devices are designed such that a gas stream, U.S. Pat. No. 4,124,463 A. H. Blue, 1978, or a stream of inert liquid, U.S. Pat. No. 4,226,683 V. A. Vaseen, 1980, passes across the electrodes to dislodge the gases evolved from the water. However, there is no electrolytic device currently available which is designed to produce known H.sub.2 concentrations in a gas stream which purges the electrolytic cell. Such a device, if capable of producing low, stable concentrations of H.sub.2, would be extremely useful for the calibration of analytical instruments which measure low concentrations of H.sub.2 in a flowing gas stream. In order to produce stable H.sub.2 standard gases by electrolysis, the H.sub.2 evolved at the electrodes must be removed as it is formed, rather than accumulating in bubbles at the electrode surface. If bubbles are allowed to form, they produce irregularities in the H.sub.2 content of the gas in the air space above the electrolyte. The H.sub.2 generating device described in the present application minimizes bubble formation by reducing the surfaces on which bubbles may collect, and by passing a gas stream across the electrode surfaces during dissociation of water. In this way, H.sub.2 is swept away from the electrodes as soon as it is formed, and the accumulation of H.sub.2 in the air space above the electrolyte is determined only by the current supplied to the electrodes and the rate of gas flow through the air space.
Usual methods for calibrating instruments for the detection of low concentrations (of the order of a few parts per million) of gaseous H.sub.2 generally involve the use of pressurized gas cylinders containing H.sub.2 of known concentration, or the production of H.sub.2 standard gas mixtures using pressurized gases attached to gas mixing pumps. Both of these methods require adequate space for the storage and use of pressurized gases, and are also expensive in the long term. The H.sub.2 generating unit described herein requires little space and is inexpensive compared to accurate gas mixing devices or the cumulative cost of purchasing special H.sub.2 standard gases. An example of an instrument which could be calibrated using the electrolysis unit described in this patent application is a nitrogenase activity analysis system (NAAS) which measures nitrogenase activity as the rate of H.sub.2 evolution from N.sub.2 -fixing plant material. The NAAS is described in detail in copending patent application entitled An Apparatus for Measuring Low Concentrations of Gases in a Flowing Gas Stream, filed concurrently herewith and commonly assigned.

Electrolytic apparatus for generating selected concentrations of gas in a flowing gas stream


An apparatus for assessing topology of a surface of a target including an optical source for generating a probe laser beam. The apparatus also includes a means for scanning the probe laser beam across at least a portion of the surface of the target and a beamsplitter for redirecting a return signal toward the means for detecting the return signal in a substantially quadrature condition. A quadrature interferometric method for determining the presence or absence of a target analyte in a sample comprising a laser probe beam having a wavelength λ and a waist wo to probe at least a portion of a substrate having a reflecting surface that includes at least a first region having a layer of recognition molecules specific to the target analyte and a second region that does not include a layer of recognition molecules specific to the target analyte.

In the field of material processing, it is desirable to be able from a stand-off distance to detect surface heights or densities using a laser probe. In the more specific case of chemical, biological, medical, and diagnostic applications, it is desirable to detect the presence of specific molecular structures in a sample. Many molecular structures such as cells, viruses, bacteria, toxins, peptides, DNA fragments, and antibodies are recognized by particular receptors. Biochemical technologies including gene chips, immunological chips, and DNA arrays for detecting gene expression patterns in cancer cells, exploit the interaction between these molecular structures and the receptors. [For examples see the descriptions in the following articles: Sanders, G. H. W. and A. Manz, Chip-based microsystems for genomic and proteomic analysis. Trends in Anal. Chem., 2000, Vol. 19(6), p. 364-378. Wang, J., From DNA biosensors to gene chips. Nucl. Acids Res., 2000, Vol. 28(16), p. 3011-3016; Hagman, M., Doing immunology on a chip. Science, 2000, Vol. 290, p. 82-83; Marx, J., DNA Arrays reveal cancer in its manyforms. Science, 2000, Vol. 289, p. 1670-1672]. These technologies generally employ a stationary chip prepared to include the desired receptors (those which interact with the target analyte or molecular structure under test). Since the receptor areas can be quite small, chips may be produced which test for a plurality of analytes. Ideally, many thousand binding receptors are provided to provide a complete assay. When the receptors are exposed to a biological sample, only a few may bind a specific protein or pathogen. Ideally, these receptor sites are identified in as short a time as possible.
As a separate example, both biological chips and electronic chips (including, but not limited to, semiconductor wafers) contain complex surface structures that are fabricated as part of the function of the chip. These surface features are becoming steadily smaller, scaling now into the nanometer range. Conventional laser profilometers are not able to detect such small changes. Interferometric techniques have been successfull in this range, but require stringent vibration isolation and mechanical stability to operate.
There is a need for improved interferometric and/or techniques that may be used to measure these surface structures.

Laser scanning interferometric surface metrology


A mophead includes a holder having an attachment location for attaching flexible absorbent mop material to the holder, and an attachment member which is spaced from the mop material attachment location and which can directly engage a scrub element with the holder independently of the mop material. The attachment member is a, preferably elongate bar, clamp which, in use, presses the scrub element directly to the mophead to clamp it thereto.

This invention relates to a mophead for mops which are used, primarily, for wet mopping of floors. In particular, but not exclusively, this invention relates to a mophead in combination with scrub element.
Mops comprise a mophead attachable or attached to a handle. The mophead generally has a holder to which flexible absorbent mop material is attached or attachable. It is known from GB2323024 to provide such a mophead where the mop material is in the form of strands and a brush or like cleaning implement is positioned amongst the strands. Such an arrangement is beneficial due to the ease by which the brush can contact the surface being cleaned. However, a problem becomes apparent in that the mop strands interfere with the brush. This results in the brush not only being unable to easily contact the cleaning surface uniformly, but also damage to the strands.
A further problem presents itself in that other types of mop material, such as a sponge and/or sheet or sheets of absorbent material, cannot readily be used.
The present invention therefore seeks to provide a solution to these problems.


A method for manufacturing a semiconductor device includes forming a SiGe layer on a Si substrate, forming a dummy pattern to expose a surface of the Si substrate, and wet etching the SiGe layer while an etchant is contacted with, the dummy pattern.

1. Technical Field
Several aspects of the present invention relates to a method for manufacturing a semiconductor device, in particular, a technique to prevent an etching selectivity of SiGe with respect to Si from deteriorating.
2. Related Art
A field-effect transistor formed on a silicon-on-insulator (SOI) substrate has been drawing attention recently because of its usability in terms of easy-element isolation, latch-up free, and small source/drain junction capacitance. Especially, since a fully depleted SOI transistor enabling low power consumption and high-speed operation is easy to drive at a low voltage, researches to drive an SOI transistor in a fully depleted mode are actively carried out. A method capable of manufacturing an SOI transistor economically by forming an SOI layer on a bulk substrate (i.e. Separation by Bonding Si islands (SBSI) is disclosed In JP-A-2005-354024 and Separation by Bonding Si islands (SBSI) for LSI Applications. (T, Sakai et al.), Second International SiGe Technology and Device Meeting, Meeting Abstract, pp. 230-231, May (2004). In SBSI, after Si and SiGe layers are formed on a Si substrate, only the SiGe layer is selectively removed by using a difference in etching rates between Si and SiGe so as to form, a cavity between the Si substrate and the Si layer. Then, a SiO2 layer is embedded between the Si substrate and the Si layer by thermally oxidizing the Si exposed in the cavity, forming a BOX layer between the Si substrate and the Si layer.
In the SBSI described above, a process to selectively remove a SiGe layer is important to obtain a stable process yield and a high yield of electric characteristics. In a manufacturing method in related art, a logic circuit and a memory circuit have a plane pattern of an active layer (SOI layer) that is less various in size and density, thereby providing a stable process yield and electric characteristics.
However, in a circuit, having a bulk silicon device and an SOI device mounted in combination, and in a circuit including devices having various driving voltages and being mounted in combination, differences in area and density between plane patterns of the SOI layers are generally large. Here, in the manufacturing method in related art, an etching speed of SiGe layer is deteriorated (that is slowed down) depending on a spot due to high or low density of the patterns. Further, especially, when an etching time is longer, an etching speed of Si becomes faster.
That is, in the manufacturing method in related art, when a semiconductor having various devices such as a bulk silicon device and an SOI device mounted in combination is manufactured, an etching selectivity of a SiGe layer with respect to a Si layer is partially deteriorated. Therefore, it is hard to form an SOI layer with a large area having a stable shape and an even film thickness, or an SOI layer into various shapes with high yields. As the above, the manufacturing method in related art has been required to improve a process yield and stabilize electrical characteristics of a semiconductor having various devices described above mounted in combination.

Method for manufacturing semiconductor device