A computer-implemented method for facilitating a payment transaction wherein a cardholder purchases an item from a merchant on behalf of a buyer is provided. The method includes receiving proposal data from a buyer computing device including at least one of an identification of an item proposed for purchase, a particular merchant, and a merchant purchase price. The method includes receiving a selection message from the buyer computing device indicating a selected cardholder chosen to purchase the item on behalf of a buyer using a merchant payment card associated with the particular merchant. The method includes reserving at least the merchant purchase price and a cardholder processing fee associated with the merchant payment card in a buyer account. The method includes transferring funds from the buyer account to a selected cardholder account, the funds determined at least in part by the merchant purchase price and the cardholder processing fee.

The field of the disclosure relates generally to payment transactions, and, more particularly, to facilitating a multi-party payment transaction that includes a cardholder purchasing a product from a merchant on behalf of a buyer wherein the cardholder makes the purchase using a payment card associated with the merchant.
Customer loyalty is one critical factor of the success of any business. To ensure that customers choose to return to a particular merchant, many merchants offer co-branded payment cards and/or private label payment cards. A merchant who offers one of these merchant payment cards may incentivize customers to utilize the merchant payment card at the merchant's business by offering discounts on merchandise, giving out rewards points redeemable for items of value, or any combination thereof. For example, a merchant specializing in the sale of electronics may provide a merchant payment card to customers and offer a 20% discount for purchases made with the payment card. Therefore, a customer associated with the particular merchant payment card of the merchant, hereinafter referred to as a "cardholder," may purchase a television that would generally cost $1,000 dollars for only $800 dollars.
However, not all customers may have the ability or desire to acquire a merchant payment card for the particular merchant from whom they wish to purchase an item. These customers, hereinafter referred to as "buyers," are not associated with the merchant payment card for the particular merchant, but may still wish to take advantage of the benefits offered by the merchant payment card. As merchant payment cards have become more popular, buyers may have multiple merchant payment cards available to them, but be unable to comfortably keep track of them. Buyers may additionally be unable to generate a credit history for multiple merchant payment cards. In other circumstances, a buyer may have sufficient funds to make a purchase, but not have acceptable credit to be approved for the merchant payment card.
In addition, cardholders may not be receiving any value from their merchant payment card. For example, a cardholder may have acquired a merchant payment card for a particular purchase, and utilized the card relatively infrequently since that time. Currently, cardholders may have significant credit available to purchase items from the merchant, but no need or desire to do so.
Therefore, there is a need in the art for systems and methods for facilitating a transaction wherein a cardholder purchases an item from a merchant on behalf of a buyer using a merchant payment card. In such systems and methods, the buyer receives some of the savings made available by the merchant payment card, without the need to acquire his or her own merchant payment card. In addition, the cardholder receives some value for purchasing an item on behalf of a buyer using the merchant payment card of the cardholder.

This patent is subject to a terminal disclaimer.

Systems and methods for facilitating multi-party payment transactions


A test circuit is disclosed for testing embedded synchronous memories. A BIST controller is used to address the memory and provide reference data that is compared to the memory output. Pipeline registers are used to allow the BIST controller to perform reads and/or writes during every clock cycle. In one aspect, the BIST controller includes a reference data circuit that stores or generates data for comparison to the memory output. A pipeline register is positioned before the reference data circuit or between the reference data circuit and compare circuitry. Additional pipeline registers may be positioned between a compare capture circuit and the compare circuitry. The pipeline registers free the BIST controller from having to wait for a read to complete before starting the next read or write. To reduce the number of pipeline registers needed, a negative-edge BIST controller can be used with a positive-edge memory or vice versa.

Many of today's integrated circuit (IC) designs are a complete system on a chip (SOC) that include a processor core, multiple embedded memories, logic, I/O ports, etc. Embedded memories are the densest components within a SOC, accounting for up to 90% of the chip area. Memories are also the most sensitive to manufacturing process defects, making it essential to thoroughly test them in a SOC.
As ICs are produced with greater levels of circuit density, efficient testing schemes that guarantee very high fault coverage while minimizing test cost and chip area overhead have become essential. However, as the complexity of circuits continues to increase, high-fault coverage of several types of fault models becomes more difficult to achieve with traditional testing paradigms.
There are generally three approaches to testing of embedded memories. One technique is to use automatic test equipment (ATE) that is located external to the circuit under test and that applies test patterns stored in the ATE. FIG. 1 is a block diagram of a conventional system 18 for testing digital circuits with scan chains. External ATE 20 applies a set of fully specified test patterns 22 one by one to a circuit under test 24 in scan mode via scan chains 26 within the circuit. The circuit is then run in normal mode using the test pattern as input, and the test response to the test pattern is stored in the scan chains. With the circuit again in scan mode, the responses are routed to the tester 20, which compares the response with the fault free reference response 28. This approach is advantageous because there are a wide variety of test algorithms that can be used and the algorithms can easily be changed in the ATE. However, as the complexity of circuits continues to increase, the ATE approach to testing embedded memories has become increasingly difficult. First, larger integrated circuits have a very high and still increasing logic-to-pin ratio that creates a test data transfer bottleneck at the chip pins. Second, larger circuits require a prohibitively large volume of test data that must be then stored in external testing equipment. Third, applying the test data to a large circuit requires an increasingly long test application time. Fourth, present external testing equipment is unable to test such larger circuits at their speed of operation, unless prohibitively expensive ATEs are used. Testing at the speed of operation allows for the detection of timing faults that might otherwise be undetected at slower speeds. This is particularly significant for memories that operate at very high speed.
Another technique for testing of embedded memories is to use an embedded CPU. Using an embedded CPU is advantageous because no additional testing hardware is needed and the test algorithms can be easily modified. However, the CPU does not always have access to all of the memories on the integrated circuit. Additionally, it is difficult to automate the process to program the CPU for generation of the memory test algorithms. Finally, it is very difficult to test the memories that store the memory test program itself.
The third approach to testing embedded memories is to use Built-in self-test (BIST) techniques. BIST has become the most popular method for testing embedded memories. To use this method, one or more BIST controllers are inserted within the SOC during the chip's design using a software design tool. The chip is then fabricated with the added BIST controllers. During testing of the fabricated chip, a BIST controller is instructed to supply a series of patterns to the ports of an embedded memory. These patterns, also called test algorithms, typically include, but are not limited to, march-type and checkerboard-type patterns that cause a memory to produce deterministic output data. The output data can be directly compared with reference data from the BIST controller. The comparison generates a signal indicating that the memory passed or failed the test.
Unfortunately, BIST requires additional hardware overhead and there is a performance penalty of BIST controllers and access logic. However, as memory sizes continue to increase, the hardware overhead is becoming relatively small. There are several advantages to BIST. The BIST circuitry generates a wide variety of memory test algorithms to achieve a high quality test. Additionally, BIST provides diagnostic resolution down to one memory cell. Finally, BIST can operate with a very low cost ATE.
FIG. 2 shows a prior art BIST designed for testing embedded memories. A BIST controller 30 includes a finite state machine 32 and control, data, and address registers 34-36, respectively, for reading and writing data to a memory 38. Other logic, shown generally at 40, represents the core logic that performs the IC's functions during normal operation. Multiplexers 42 are used to switch the IC from a test mode (where the BIST controller 30 controls the memory 38) to an operational mode (where the logic 40 reads and writes memory 38). In the test mode, compare circuitry 44 is used to compare values read from memory 38 to reference data 46 stored in the BIST controller 30. Once the compare is completed, the compare circuitry 44 is responsive to a compare capture register 48 in the BIST controller to output the resulting data, which indicates whether the read passed or failed. Although not shown, a clock controls both the BIST controller and the memories being tested so that the two are synchronized. Also, although only one memory is shown in FIG. 2, typically, a BIST controller tests multiple memories.
FIG. 3A shows a timing diagram for a read operation of the circuit of FIG. 2. The read operation takes three clock cycles to complete. During a first clock cycle, the control and address registers 34, 36 of the BIST controller 30 are set up for a read operation. This typically includes storing an address of the desired memory element in the address register 36 and setting the control register 34 for a read operation. On the next clock cycle, the memory outputs the data to the compare circuitry 44. During this cycle, the compare circuitry compares the value read from memory with the reference data supplied from register 46. The compare circuitry 44 then determines whether the reference data matched (passed) the memory data or whether it did not match (failed). On a third clock cycle, the compare circuitry 44 outputs the pass/fail signal as controlled by the compare capture register 48. After the first read is completed, a second read begins that requires three additional clock cycles.
FIG. 3B shows a write operation for the circuitry of FIG. 2. The write operation requires two clock cycles. During a first clock cycle, the BIST controller 30 stores the address of the desired memory location in the address register 36. The BIST controller also stores the data to be written in the data register 35 and places the control register 34 in the proper configuration for a memory write. On the next clock cycle, the memory writes the data from data register 35 to the memory addressed by the address register 36. Every subsequent write operation requires two additional clock cycles.
There are several problems with the prior art test circuitry of FIG. 2. Foremost, the read operation requires three clock cycles to complete and a write requires two cycles to complete. In normal operation, the memory can run much faster. As a result, some timing faults may go undetected. Additionally, the overall testing time is extremely long because of the long read and write cycles. As memory sizes continue to increase, overall testing time will also increase.
Thus, there is a need for a test circuit that tests memory at full-speed and that requires less overall test time to complete a memory test.

Full-speed BIST controller for testing embedded synchronous memories


A shock absorber includes a gas spring cylinder containing a piston moveable between an extended position and a compressed position within the gas spring cylinder. A mechanical actuator is arranged whereby a bleed port is automatically closed when the gas spring is compressed to a predetermined position corresponding to a desired sag setting. In one embodiment, the position corresponds to a predetermined sag setting whereby the gas spring is partially compressed. In another embodiment, a proper sag setting is determined through the use of a processor and sensor that in one instance measure a position of shock absorber components to dictate a proper sag setting and in another instance calculate a pressure corresponding to a preferred sag setting.

1. Field of the Invention
The invention relates generally to vehicle suspensions and, more specifically, to methods and apparatus for suspension adjustment.
2. Description of the Related Art
Vehicle suspension systems typically include some form of a shock absorber. Many integrated damper/spring shock absorbers include a damper body surrounded by a mechanical spring. The damper body often consists of a vented piston and a shaft telescopically mounted in a fluid cylinder. Some shock absorbers utilize gas as a spring medium in place of, or in addition to, a mechanical spring. The spring rate of such shock absorbers may be adjustable such as by adjusting the preload of a mechanical spring or adjusting the pressure of the gas in the shock absorber. In that way the shock absorber can be adjusted to accommodate heavier or lighter carried weight, or greater or lesser anticipated impact loads. In vehicle applications, including motorcycles, bicycles, and, particularly, off-road applications, shock absorbers are pre-adjusted to account for varying terrain and anticipated speeds and jumps. Shocks are also adjusted according to certain rider preferences (e.g. soft-firm).
One disadvantage with conventional shock absorbers is that adjusting the spring mechanism to the correct preset may be difficult. The vehicle must be properly loaded for the expected riding conditions such as with a rider or driver sitting on or in the vehicle while the spring mechanism is adjusted to create a proper amount of preload. Often times such adjustment requires both a rider sitting on the vehicle and a separate mechanic performing the proper adjustment at the location of the shock absorber. A further disadvantage is that many current systems rely on imprecise tools and methods to set the initial amount of preload.
As the foregoing illustrates, what is needed in the art are improved apparatus and techniques for easily and accurately adjusting the amount of preload applied to a spring in a shock absorber.

Methods and apparatus for suspension adjustment


A light tunnel includes a first optical element, a second optical element, a third optical element and a fourth optical element. The first optical element has a first recess. The second optical element is disposed opposite to the first optical element and has a second recess. The third optical element connects the first optical element with the second optical element and has one end disposed in the first recess or the second recess. The fourth optical element is disposed opposite to the third optical element, connects the first optical element with the second optical element, and has one end disposed in the first recess or the second recess. Inner surfaces of the first to fourth optical elements form a light passage. A projection system is also disclosed.

1. Field of Invention
The invention relates to a display system and a light tunnel thereof, and, in particular, to a projection system and a light tunnel thereof.
2. Related Art
Due to demands for large display area and compact, light-weight systems, image projection systems have now become one of the most popular products in the opto-electronic industry.
Referring to FIG. 1, an image projection system, hereinafter referred to as a projection system 1, has a light source 10, a color wheel assembly 11, a light tunnel 12, a lens assembly 13, a digital micro-mirror device (DMD) 14 and a projecting unit 15. The light source 10 emits light to the color wheel assembly 11 and then into the light tunnel 12. Then, the lens assembly 13 focuses the light onto the DMD 14. Driving electrodes are provided to control tilt angles and deflection times of micro mirrors (not shown) on the DMD 14 to switch reflection directions of the light, and then the light is projected onto a screen 16 through the projecting unit 15 for imaging.
Referring to FIGS. 1 and 2, the conventional light tunnel 12 is mainly composed of four optical elements 121, which are assembled using a jig to fix the four optical elements 121. Then, an adhesive 122 is applied to all the junctions between adjacent pairs of optical elements 121 so that the optical elements 121 can be combined together. Because inner surfaces of the light tunnel 12 have reflective layers, the light emitted from the light source 10 enters the light tunnel 12 through an inlet 123, then is reflected by the reflective layers many times, and then is outputted from an outlet 124 so that the luminance of the light becomes uniform.
However, because a space for the adhesive 122 has to be left between the optical elements 121, a contact surface S between the optical elements 121 is smaller, as shown in FIG. 2. When an external force is applied to the light tunnel 12, the optical elements 121 may be separated due to insufficient structural integrity so that the efficiency of the light tunnel 12 is adversely influenced. In addition, because the temperature of the light emitted from the light source 10 is very high, the environmental temperature is elevated such that the adhesive 122 of the light tunnel 12 adjacent to the light source 10 tends to become brittle. Similarly, the structural intensity between the optical elements 121 of the light tunnel 12 is insufficient and the optical elements 121 tend to separate from one another.

Projection system and light tunnel thereof


A method for directed retry in a mobile communication system including measuring the reception level of the signal from the neighboring cells of the target cell in the mobile station, sending the measurement results as a report message from the mobile station to the mobile communication network, detecting the need for directed retry, selecting at least one neighboring cell as the candidate cell for directed retry on the basis of the measurements, and executing directed retry into the selected target cell. It is characteristic for the method according to the invention that the change in the reception level of the signal of at least one candidate cell is determined on the basis of the measurements performed in the mobile station, and the target cell for directed retry is selected from the candidate cells by using the determined changes in the reception levels of the signals so that, the selected target cell is the candidate cell whose value for the change in the reception level of the signal meets a predefined criterion.

This invention relates to a method for directed retry in a mobile communication system. The method consists of the following steps: measuring the reception level of the signals from the neighboring cells of the target cell in the mobile station, sending the measurement results as a report message from the mobile station to the mobile communication network, detecting the need for directed retry, selecting at least one neighboring cell as the candidate cell for directed retry on the basis of the measurements, and executing the directed retry to the selected target cell.
Additionally, the invention relates to a control unit for controlling the directed retry.
FIG. 1 (attached) shows a simplified block diagram of the Pan-European GSM mobile communication system. The MS (Mobile Station) is connected via a radio path to a BTS (Base Transceiver Station), in FIG. 1 to base station BTS1. A BSS (Base Station Sub-system) consists of a BSC (Base Station Controller) and the base stations BTS controlled by it. An MSC (Mobile Services Switching Center) usually controls several base station controllers BSC. The mobile services switching center MSC is connected to other mobile services switching centers and, via a GMSC (Gateway Mobile Services Switching Center), the GSM network is connected to other networks, such as the public switching telephone network PSTN, another mobile communication network PLMN or the ISDN network. The operation of the entire system is controlled by the OMC (Operation and Maintenance Center). The subscriber data of the mobile station MS is permanently stored in the HLR (Home Location Register) of the system and temporarily in the VLR (Visitor Location Register) of the area in which the mobile station MS is currently located.
The mobile station MS continuously measures the signals of the base stations BTS nearest to the cell in which it is located, for example, to determine the base station that offers the best signal and to be ready for a cell handover. Each base station BTS continuously transmits in its cell broadcast channel information intended for all mobile stations MS. This information includes, among other things, the BSIC (Base Station Identity Code), the LAI (Location Area Identifier), and information about the frequencies of the neighboring base stations which the mobile stations MS should be measuring. For example, in the GSM mobile communication system the mobile station MS can measure the reception level and quality of the serving base station and simultaneously the reception level of up to 32 other base stations BTS. When in radio connection with a base station BTS, the mobile station MS frequently sends the measurement results as a report message to the base station controller BSC via the serving base station. The report message contains the signal measurement results for the serving base station and for up to the six best neighboring base stations.
When the mobile station MS moves in the area of the mobile communication network, it normally connects to the base station BTS with the strongest signal. Thus the system attempts to establish any mobile station MS terminated or mobile station MS originated call via this base station BTS. If the base station BTS into which the mobile station MS is connected cannot offer a traffic channel for call setup, for example, because of overload, the system executes a so-called directed retry. In this case, the traffic channel is selected during the call setup phase from a cell other than that in which the signaling was performed. The mobile communication network selects the next strongest base station by using the measurement results delivered by the mobile station MS as a report message during call setup signaling and directs the call to be established to the traffic channel of this base station.
The problem with the directed retry according to the prior art is that the serving base station is selected according to single measurement results, even though the mobile station may just be leaving the coverage of the base station selected. The selection of a base station unsuitable in relation to the movement direction of the mobile station will in this case shortly result in a handover. In other words, the problem is the inability of the directed retry according to the prior art to predict, for how long the selected target cell will be the best cell as far as the mobile station call setup is concerned.
The purpose of this invention is to implement the directed retry in such a manner that, for traffic initiation, the system will select the base station whose signal will probably be sufficient for maintaining the call for longer than any other of the possible base stations.
This will be accomplished by using a system of the type described in the introduction for directed retry for which it is characteristic according to the invention that the measurements performed in the mobile station are used to determine the change in the reception level of the signal of at least one candidate cell, and the target cell for directed retry is selected from the candidate cells by using the determined changes in the reception levels of the signals so that the target cell selected is the candidate cell whose value for the change in the reception level of the signal meets a predefined criterion.
Additionally, the invention relates to a control unit for controlling the directed retry. The control unit is adapted to receive measurement reports, to detect the need for directed retry, to use the results of the measurement report to select at least one neighboring cell as the candidate cell for directed retry, and to initiate the directed retry into the selected target cell. It is characteristic for the control unit, according to this invention, that it is additionally adapted to determine the change in the signal reception level of at least one candidate cell on the basis of the received measurement reports and to select as the target cell for the directed retry by using the determined changes in signal reception levels the candidate cell whose value for the change in the signal reception level meets a predefined criterion.
The invention is based on the idea that the system attempts to determine the direction of movement of the mobile station in relation to the base station of the candidate cell for directed retry by comparing the consecutive measurement results delivered by the mobile station for the base station signal of the candidate cell in question to one another and by monitoring the change in the signal. As the target cell for directed retry is selected the cell for which the change in consecutive measurement results of the base station signal increases most or decreases least. When the base station signal increases rapidly, it may be assumed that the mobile station is moving towards the base station and thus will remain in the coverage of the base station for a longer time than in the coverage of those base stations whose signal strength increases less. If all base station signals decrease, the selected target cell, according to this invention, is one for which the reception level of the base station signal received in the mobile station has decreased least. In one embodiment of the invention it is possible to set a threshold value for the target cell selection, and the change in the base station signal level must exceed this threshold in order for the system to select the traffic channel from the base station in question.
The advantage of this kind of method is that the probability of success for directed retry is improved and thus the probability for the call being cut off decreases.
Another advantage of the method according to this invention is that the need for handovers is decreased.
Yet another advantage in this invention is that the load of the mobile communication network is divided in a more optimal fashion between the different base stations when the call is not always transferred to the same cell with the strongest signal level but to the cell that is best in relation to the movement direction of the mobile station.


An apparatus for correcting a signal, includes a correction value calculator that determines a transmission distance of a transmission path through which a timing signal is propagated, the timing signal having a periodically changing frequency, and determines a deviation between a frequency of the timing signal and a frequency of received data, as a correction value, from the transmission distance; and a corrector that corrects the frequency of the timing signal by the correction value for synchronizing transmitted data with the timing signal.

Communication schemes have been well-known where clock signals (clocks), as well as data signals, are transmitted between transmitting and receiving devices.
One such example is the PCI Express® wherein clocks are transmitted in the side band upon transmitting bus signals in servers, personal computers (PCs), or devices. (As for the PCI Express®, refer to PCI express OCuLink Specification Rev 0.5).
The PCI Express® is one communication standard for performing communications via a pair of transmitting and receiving paths for serial transmissions (such paths are referred to as lanes).
The maximum speed of a single lane is 8 gigabytes (GB) per second (GB/s), and 32 lanes can be bundled at maximum. The bundle of the transmission paths are collectively referred to as a link.
A typical PCI Express® system includes a root complex, an end point, a switch, and a bridge.
The root complex is a device located at the bottom of the hierarchy, and includes a host bridge and is connected to a CPU, a memory, and the like.
In PCI Express®, an input/output (I/O) device is referred to as an end point.
In the meantime, the recent increase in data communication speeds has underlined the influences of the noises caused by electro magnetic interferences (EMIs).
For addressing such EMI noises, an increasing number of systems and/or architecture have adopted clocks having periodically varying frequencies, as standard clock, such as spread spectrum clocks (SSCs), as their standard clocks. SSCs are clocks where the bandwidth is spread by sweeping the clock frequency.
SSCs intentionally fluctuate the frequency of the clocks, thereby preventing energy to be concentrated on a particular frequency, which may cause EMIs to reduce noises.
FIG. 8 is a graph illustrating an SSC waveform used in a transmission system. This SSC represents a down spread wherein a triangular wave having a modulation frequency of 30 kHz, as specified in PCI Express®, is modulated only to the lower-frequency side, with a frequency of 100 MHz and a modulation index of 0.5%, for example.
As depicted in FIG. 8, since SSCs have frequencies that vary over time, the signal intensity for each frequency is reduced, which reduces the influences of EMIs.
In the meantime, demands for long-haul data transmissions have increased in recent years. For example, for interconnections between server racks, e.g., Internet data centers (iDCs) and centralized management of devices, inter-enclosure connections among peripheral devices, CPUs, and memory blades, located in separate enclosures, are increased. Furthermore, a desire to transmitting massive data to monitors at higher speed is increased in commercial PCs.
With a significant increase in the transmission distances, deviations between the changing frequency of SSCs and the frequency of received data have become problematic.
To address such deviations, techniques are proposed for minimizing the diffusion coefficient of SSCs. For example, there are techniques that minimize the diffusion coefficient of SSCs by checking the status of devices that are connected.
There is, however, a tradeoff between the diffusion coefficient and the transmission delay time. Hence, in systems where sufficient diffusion coefficients are required for SSCs, the SSCs cannot be transmitted in a longer distance.
FIG. 9 is a schematic diagram illustrating a configuration of a conventional data transmission system, and FIG. 9B a graph illustrating an SSC waveform used in the data transmission system 1 in FIG. 9A.
The data transmission system 1 uses signals having periodically changing frequencies (e.g., SSCs), as clocks.
The data transmission system 1 communicates data, in accordance with any suitable communication standard, such as the PCI Express®, for example. As depicted in FIG. 9A, the data transmission system 1 includes an upstream port 11, a downstream port 21, and an optical fiber 30.
The upstream port 11 may be a root complex of the PCI Express®, for example, which may be provided on a mother board of a server, for example. The upstream port 11 includes a reference oscillator 12.
The optical fiber 30 is a bundle of optical fiber cables, and includes a clock transmission path, a downstream data transmission path, and an upstream data transmission path.
The downstream port 21 may be an end point of the PCI Express®, for example, and may be provided in any suitable peripheral devices, such as hard disk drives, for example. The downstream port 21 includes a phase locked loop (PLL) 22.
Here, the clock is expressed in F(x) in FIG. 9B. The frequency of a clock, which is used for data generation by the upstream port 11 at Time t is expressed by F(t) and is indicated with the arrow in the double dashed line.
For t which is the time required for a signal to be transmitted from the upstream port 11 to the downstream port 21, the reference when the data is received in the upstream port 11 corresponds to the clock at the time when the data was generated in the downstream port 21, and the clock has been transmitted from the upstream port 11. In other words, the clock is the clock before 2T, and the frequency at that time is expressed in (t−2T) and is indicated with the arrow in the single dashed line FIG. 9A.
Therefore, in the upstream port 11, data generated using the clock with the 2T-old frequency F(t−2T) is strobed using the latest clock F(t).
In this manner, upon sending SSCs having a frequency which varies over time, occurrence of any transmission delay during transmission changes the frequency of the clock, thereby inducing the difference (deviation) in frequencies between the clock and a data signal. The greater the delay, the greater the frequency difference becomes, which is problematic for long-haul transmissions.
Specifically, if there is a difference between the reference clock of data and a clock used for strobing, the strobe point of the data may gradually deviate, which hinders the data from being received correctly.
For the above reason, in PCI Express® requires that the difference be within several hundred pars per million (ppm), for example.
In conventional configurations where hard disk drives are directly connected to a server, the difference in frequencies does not cause any problem since the transmission distance is small and hence T is negligible.
As set forth above, although demands for long-haul transmissions of SSCs become intense, an increased transmission delay hinders the SSCs from being transmitted for a longer distance.
In one aspect, the present disclosure is directed to enabling transmissions of timing signals having periodically varying frequencies in a longer distance.
Note that it is another object of the present embodiment to provide advantages and effects that can be obtained by the best modes to implement the embodiment described below but cannot be obtained with conventional techniques.

Apparatus for correcting signal, transmission apparatus, method of correcting signal, and transmission system


A delay mechanism including one or more suction cups which during a normal cycle of dispensing from a liquid dispenser come to engage on a surface and thereby delay the return of an actuating member in the dispenser to a position for further dispensing until such time as the suction cup disengages from the surface.

Many dispensers for flowable materials such as hand soaps, hand lotions, creams, alcohol cleaners and other flowable materials whether powders, pastes or liquids or combinations thereof are known which dispense individual allotments of the material in a cycle of operation. Many such known dispensers suffer the disadvantage that they are open to use by users so as to dispense more material that is necessary as by repeated cycling of the dispensing mechanism in a short period of time. The use of excessive amounts of material is particularly objectionable where the material being dispensed is expensive.


A multiprocessor system includes first and second processors and a multi-path accessible semiconductor memory device including a shared memory area and a pseudo operation execution unit. The shared memory area is accessible by the first and second processors according to a page open policy. The pseudo operation execution unit responds to a virtual active command from one of the first and second processors to close a last-opened page. The virtual active command is generated with a row address not corresponding to any row of the shared memory area. For example, bit-lines of a last accessed row are pre-charged for closing the last-opened page.

1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to a multi-path accessible semiconductor memory device that responds to a virtual row active command to prevent a pre-charge skip for an opened page upon transfer of access authority.
2. Background of the Invention
Generally, a semiconductor memory device having a plurality of access ports is called a multi-port memory device. In particular, a memory device having two access ports is called a dual-port memory device. The dual-port memory device is known in the prior art as an image processing video memory device having a RAM (random access memory) port accessible in a random sequence and a SAM (sequential access memory) port accessible only in a serial sequence.
In addition, a dynamic random access memory (DRAM) device having a shared memory area accessible by multiple processors is herein called a multi-path accessible semiconductor memory device. For example in recent mobile communication systems, electronic devices such as handheld multimedia players, handheld phones, or personal digital assistants (PDAs) each include a multiprocessor system with multiple processors as shown in FIG. 1 for effectively operating with high speed.
FIG. 1 shows a block diagram of a multiprocessor system in a mobile communication device according to the conventional art. The multiprocessor system of FIG. 1 includes a first processor 101 and a second processor 201 connected to each other through a connection line B3. The multiprocessor system of FIG. 1 also includes a first flash memory device 301 and a first DRAM (dynamic random access memory) device 401 coupled to the first processor 101 via a first system bus B1.
The multiprocessor system of FIG. 1 further includes a second DRAM device 402 and a second flash memory device 302 coupled to the second processor 201 via a second system bus B2. The first processor 101 may include applications for data communication or for games, and the second processor 201 may include applications for MODEM functions such as modulation/demodulation of a communication signal.
The flash memory devices 301 and 302 may each be an NOR flash memory device having a NOR structure or a NAND flash memory device having a NAND structure. The NOR or NAND flash memory device is a nonvolatile memory device comprised of an array of memory cells each having a floating gate. The nonvolatile memory device stores data that is not changed even when power is removed. The DRAM devices 401 and 402 are used as main memories for data processing by the corresponding processors 101 and 201.
However in the multi processor system of FIG. 1, each of the processors 101 and 201 is connected to respective DRAM devices 401 and 402. In addition, UART, SPI, or SRAM interfaces operating with relatively low speed are used therein resulting in low data transmission speed. Accordingly, a multiprocessor system of FIG. 2 with just one DRAM device 403 is implemented for increased data transmission speed and reduced sized.
The multiprocessor system of FIG. 2 includes the first processor 101 and the second processor 201 connected to a first flash memory device 303 and a second flash memory device 304, respectively, via system buses B4 and B5, respectively. The multiprocessor system of FIG. 2 also includes the one DRAM device 403 connected to both the first and second processors 101 and 201 via system buses B1 and B2, respectively.
Accordingly in FIG. 2, the one DRAM 403 is accessed by each of the first and second processors 101 and 201 through two different paths, as also disclosed in U.S. Patent Application No. US2003/0093628 to Matter et. al. In such prior art, the one DRAM device 403 includes a memory cell array with first, second, and third portions. The first portion of the memory cell array is accessed only by the first processor 101. The second portion of the memory cell array is accessed only by the second processor 201. The third portion of the memory cell array is a shared memory area accessed by both of the first and second processors 101 and 201.
Mediation is needed for access to the shared memory area by the first and second processors 101 and 201. A UART, SPI or SRAM interface has been used for communication between conventional processors via the system bus B3. However, such an interface operates with limited speed and increased number of pins for three-dimensional games or image communications. Thus, an interface with higher operating speed is desired. Further in FIG. 2, having respective flash memory devices 303 and 304 for each of the processors 101 and 201 may result in complication or increased cost.
Accordingly, a multiprocessor system of FIG. 3 includes first and second processors 100 and 200 that share one DRAM 400 and one flash memory device 300. A data interface between the processors 100 and 200 is implemented through the multi-path accessible DRAM 400. Also in FIG. 3, the first processor 100 is not directly connected to the flash memory device 300 but indirectly accesses the flash memory device 300 through the multi-path accessible DRAM 400.
Each of the processors in FIGS. 2 and 3 may support a page open policy to read or write data from or to the one DRAM device 400. The page open policy has higher data access speed than a page closed policy. For example, when reading data from memory cells connected to a same word line according to the page open policy, the word line is activated only one time, and the bit lines of such memory cells are sensed thereafter.
In contrast for reading such data according to the page closed policy, the word line is re-activated every-time a bit-line is sensed. Thus, additional time for pre-charging the bit lines and re-activating the word line is needed in the page closed policy. Accordingly, recent processors use the page open policy for increased speed for accessing a memory device.
FIG. 4 illustrates a pre-charge skip that occurs upon transfer of access authority according to a page open policy supported by the processors of FIG. 2 or 3. Referring to FIG. 4, a waveform PC indicates commands generated in a page closed policy, and a waveform PO indicates commands generated in a page open policy.
Referring to waveform PC, for reading/writing data from a memory cell connected to an intersection of word line W/L1 and bit line B/L1, a row active command ACT is generated to activate word line W/L1 during a time interval I1. Subsequently, a read/write command R/W is generated to sense or activate bit line B/L1 during time interval I2.
Then for reading/writing data from a memory cell connected to an intersection of the word line W/L1 and bit line B/L2 different from the bit line B/L1, a command PRE to pre-charge the bit line B/L1 is first generated. Thereafter, a row active command ACT to activate the word line W/L1 is then generated. Such pre-charge and row active commands PRE and ACT are applied on the one DRAM 400 or 403 during a time interval A. Subsequently, a read/write command R/W to sense or activate bit line B/L2 is applied on the one DRAM 400 or 403 during a time interval I3.
In contrast referring to the waveform PO in FIG. 4, for reading/writing data from a memory cell connected to an intersection of word line W/L1 and bit line B/L1, a row active command ACT is applied on the one DRAM 400 or 403 to activate word line W/L1 during a time interval T1. Subsequently, a read/write command R/W is applied on the one DRAM 400 or 403 to sense or activate bit line B/L1 during a time interval T2.
For the read mode for example, data is read from the memory cell connected to the intersection of the bit line B/L1 and the word line W/L1 of the one DRAM 400 or 403. Subsequently, in reading/writing data from/to a memory cell connected to an intersection of the word line W/L1 and a bit line B/L2 different from the bit line B/L1, another read/write command R/W is immediately applied to the one DRAM 400 or 403 to sense or activate bit line B/L2. Thus, the pre-charge and row active commands PRE and ACT shown during the time interval A of the waveform PC are omitted in the waveform PO.
Accordingly for the page open policy, the bit lines of memory cells connected to the same word line are sensed or activated with the same word line being maintained to be activated without the time interval A for the page closed policy. Thus, data is accessed with higher speed in the page open policy than in the page closed policy.
When a page is changed in the page open policy, a page close operation should be executed for the opened page when another word line is selected to be activated. However, when authority to access the multi-path accessible DRAM 400 or 403 of FIG. 2 or 3 is transferred from one processor to the other processor (such as at time point to in FIG. 4), a pre-charge operation for bit lines of the shared memory area within the multi-path accessible DRAM 400 or 403 may be skipped with the page open policy.
With such a pre-charge skip, data error may result during a read/write operation performed after the authority transfer. For example, when access authority to the shared memory area of the multi-path accessible DRAM 400 or 403 is transferred from the first processor 100 to the second processor 200 at a time point t0 in FIG. 4, pre-charge of the bit lines B/L1 and B/L2 is skipped.
Subsequently, when the second processor 200 activates another word line and bit line through port B, data error results for the read/write operation. Furthermore, when a bit line is not pre-charged or two word lines are activated simultaneously in a general DRAM, data error results in a read/write operation. Thus, when access authority is to be transferred in a page opened state, the opened page is desired to be closed before the transfer of access authority for preventing data error.

Multi-path accessible semiconductor memory device with prevention of pre-charge skip


A fiber texture presents the shape of a strip extending in a longitudinal direction over a determined length between a proximal portion and a distal portion, and in a lateral direction over a determined width between first and second lateral edges. The fiber texture presents three-dimensional or multilayer weaving. The proximal portion of the fiber texture includes an end portion extending in the lateral direction so as to be set back from at least one of the first and second lateral edges and over a determined width that is less than the width of the fiber texture. The end portion projects in the longitudinal direction from at least one longitudinal edge of the fiber texture, the end portion extending in the longitudinal direction between a first end connected to the fiber texture and a free, second end opposite from the first end.

FIG. 1 shows the profile of an aeroengine fan casing 10 in section. The casing 10 presents a shroud 11 that extends widthwise in an axial direction DA, with two flanges 12 and 13 extending respectively from the two ends of the shroud 11 in a radial direction DR.
The fabrication of such a casing begins by making a fiber texture in the form of a strip, the fiber texture being made by three-dimensional weaving between a plurality of layers of warp yarns and a plurality of layers of weft yarns. The fiber texture as obtained in this way is wound for a plurality of turns on a mold or tooling 90 having the shape of the casing that is to be made and the texture is held between the mold 90 and segments 94 forming a mold cover so as to obtain a fiber preform 40, as shown in FIG. 2. In order to improve the mechanical strength of the casing, in particular against impacts, an overlap zone 41 is arranged in the preform 40 in which the thickness of the preform, and consequently the thickness of the resulting casing, is of greater size since it includes an additional thickness of preform corresponding to a proximal portion 42, i.e. the start of winding the preform on the mold, being overlapped by means of a distal portion 43 of the preform 40, i.e. the end of winding the preform on the mold. This overlap makes it possible to retain good mechanical characteristics in the zone corresponding to the start and to the end of the winding of the fiber preform.
Once the fiber preform has been made, i.e. after the fiber texture has finished being wound, the tooling carrying the fiber preform is closed by the mold covers and then transported to a stove or oven in which the preform is densified with a matrix, which matrix may be obtained in particular by injecting a matrix-precursor resin into the fiber preform and then polymerizing it.
Nevertheless, that fabrication technique presents drawbacks, in particular concerning the flanges in the overlap zone. Specifically, although extra thickness of the shroud is necessary in the overlap zone in order to provide the casing with its mechanical performance, this same extra thickness needs to be eliminated in a zone adjacent or close to the flanges so as to enable the casing to be mounted on an aeroengine. Thus, once the flanges have been fabricated by injection and polymerization, they are machined in the overlap zone in order to eliminate their local extra thickness. Such machining presents the following drawbacks:                increasing the time and the cost of fabrication;        difficulty in obtaining correct dimensions, since machining areas of the flanges leads to releasing internal stresses within the part in a manner that is difficult to predict or control; and        running the risk of decreasing the mechanical performance of the casing by breaking some of the fibers during the machining.

Fiber texture for fabricating an aeroengine casing


The present invention provides a method of identifying a human subject having increased or decreased sensitivity to warfarin, comprising detecting in the subject the presence of a single nucleotide polymorphism in the VKOR gene, wherein the single nucleotide polymorphism is correlated with increased or decreased sensitivity to warfarin, thereby identifying the subject having increased or decreased sensitivity to warfarin.

The function of numerous proteins requires the modification of multiple glutamic acid residues to γ-carboxyglutamate. Among these vitamin K-dependent (VKD) coagulation proteins, FIX (Christmas factor), FVII, and prothrombin are the best known. The observation that a knock-out of the gene for matrix Gla protein results in calcification of the mouse's arteries (Luo et al. (1997) "Spontaneous calcification of arteries and cartilage in mice lacking matrix GLA protein" Nature 386:78-81) emphasizes the importance of the vitamin K cycle for proteins with functions other than coagulation. Moreover, Gas6 and other Gla proteins of unknown function are expressed in neural tissue and warfarin exposure in utero results in mental retardation and facial abnormalities. This is consistent with the observation that the expression of VKD carboxylase, the enzyme that accomplishes the Gla modification, is temporally regulated in a tissue-specific manner with high expression in the nervous system during early embryonic stages. Concomitant with carboxylation, reduced vitamin K, a co-substrate of the reaction, is converted to vitamin K epoxide. Because the amount of vitamin K in the human diet is limited, vitamin K epoxide must be converted back to vitamin K by vitamin K epoxide reductase (VKOR) to prevent its depletion. Warfarin, the most widely used anticoagulation drug, targets VKOR and prevents the regeneration of vitamin K. The consequence is a decrease in the concentration of reduced vitamin K, which results in a reduced rate of carboxylation by the γ-glutamyl carboxylase and in the production of undercarboxylated vitamin K-dependent proteins.
In the United States alone, warfarin is prescribed to more than one million patients per year and in Holland, it has been reported that approximately 2% of the population is on long term warfarin therapy. Because the dose of warfarin required for a therapeutic level of anticoagulation varies greatly between patients, the utilization of warfarin is accompanied by a significant risk of side effects. For example, it has been reported that following initiation of warfarin therapy, major bleeding episodes occurred in 1-2% of patients and death occurred in 0.1-0.7% of patients. In spite of the dangers, it has been estimated that warfarin use can prevent 20 strokes per induced bleeding episode and is probably underutilized because of the fear of induced bleeding.
The present invention overcomes previous shortcomings in the art by providing methods and compositions for correlating single nucleotide polymorphisms in a subject with an increased or decreased sensitivity to warfarin, thereby allowing for more accurate and rapid determination of therapeutic and maintenance doses of warfarin at reduced risk to the subject.

Methods and compositions for the correlation of single nucleotide polymorphisms in the vitamin K epoxide reductase gene and warfarin dosage

The University of North Carolina at Chapel Hill


In an image processing method for reducing an input image while preventing moire without deterioration of image quality, presence/absence of periodicity is detected for each pixel on the input image, and if there is periodicity, an image period is detected (S4). Sample points are sequentially extracted from the input image at prescribed sampling intervals (S5). A value is obtained by multiplying the image period by n (n is a natural number) that exceeds the sampling interval, to set a smoothing area. Pixels around a sample point is smoothed in the set smoothing area. The pixel value for a reduced image is obtained (S6). If there is an unprocessed sample point (NO at S8), the step goes back to S6, and the next sample point is subjected to a similar process. If the process is terminated for all the sample points (YES at S8), the reduced image is output.

Conventionally, in an image processing device, an input image is generally reduced at a prescribed ratio to create a reduced image. The reduced image is created by smoothing the input image while extracting pixels at prescribed sampling intervals.
However, when the image has periodicity which is inconsistent with the sampling intervals, moire occurs. The occurrence of moire is particularly significant at a dot portion such as Screen-tone. This is because the number of dots included in an area to be smoothed changes with periods dependent to the sampling intervals and the image periods, and a pixel value after smoothing also varies with periodicity, for each sample point.
In order to eliminate such moire occurring at the dot portion, a method is provided for detecting dots in advance and smoothing the dot portion across an area of a certain size. However, there are many different types of image periods of dots, and a relatively large area must be smoothed in order to eliminate occurrence of the moire at dot portions of all types, resulting in deterioration of image quality.
Moreover, random dots that have no periodicity may also be subjected to a similar smoothing process, which is unnecessary, causing further deterioration of the image quality.


A device for examining the visual field of the human eye which includes a cup-shaped screen, onto the base of which one or several test marks are projected, and usable for both kinetic and also static perimetry testing and offers test marks of a uniform size and brightness over the entire testing area. The screen consists for this purpose of a transparent material, whereby the test marks are projected from the back side onto the screen approximately parallel to the surface normal. The test mark is thereby arranged to move parallel and relative to the back side of the screen, so that each test mark is moved at an equidistant spacing from the screen.

The measurement of the visual field in addition to the measurement of pressure has an important role in the ophthalmology practice. It is known to use the perimeter of Goldmann for measuring the visual field, which perimeter enables the user to carry out both a kinetic-quantitative and also a static-quantitative examination. This kinetic-quantitative perimetry works with a movable test mark of a specific brightness, with which the points of the same contrast sensitivity are located perpendicularly to the visual field limits to be expected or isopters, which is guaranteed by the free mobility of the test mark in every direction. In the static-quantitative perimetry, the patient is offered a stationary test mark with a specific brightness, which is recognized as a superthreshold at any point in the visual field. Both examining methods are as a rule carried out side-by-side so that a device with which both examining methods can be carried out is advantageous.
The Goldmann perimeter is a cup-shaped projection perimeter with a direct registration of the test mark position. The even and constant illumination of the inside of the cup is supposed to guarantee during each examination always the same adaption state of the eye. The test mark, with which one determines the stimulus threshold of the light sensed in the central and peripheral visual field portions, is projected from the cup opening onto the base of the cup. Since, however, the head of the patient is fixed exactly onto the center of the cup, it is compulsory that the projection system is arranged eccentrically. Distortions of varying strength of the test mark in dependency of the respectively chosen test mark position result from this eccentric arrangement. With this not only the shape of the test mark is changed but also its brightness distribution so that sources of error can occur.


A disk drive including a disk drive base, a disk coupled to the disk drive base, and a head stack assembly coupled to the disk drive base. The disk drive further includes an airflow diverter filter component disposed upstream of the head stack assembly with respect to disk rotation induced airflow for modifying the disk rotation induced airflow adjacent the head stack assembly. The filter component includes a first filter element disposed adjacent the disk surface, a second filter element disposed between the first filter element and the head stack assembly, and a third filter element having a porosity finer than the first and second filter elements. The third filter element is generally radially further than the second filter element from the axis of rotation. The disk rotation induced airflow generally enters the filter component through the first filter element and exits through the second and third filter elements.

1. Field of the Invention
The present invention relates generally to disk drives, and in particular to a disk drive including an airflow diverter filter component.
2. Description of the Prior Art
The typical hard disk drive includes a head disk assembly (HDA) and a printed circuit board assembly (PCBA) attached to a disk drive base of the HDA. The head disk assembly includes the disk drive base, a cover, at least one magnetic disk, a spindle motor for rotating the disk, and a head stack assembly (HSA) that includes a transducer head supported by a slider (collectively referred to as "head" or "slider") for reading and writing data from and to the disk.
The spindle motor includes a spindle motor hub that is rotatably coupled to the disk drive base. The spindle motor hub has an outer hub flange that supports a lowermost one of the disks. Additional disks may be stacked and separated with annular disk spacers that are disposed about the spindle motor hub. The spindle motor typically includes a spindle motor base that is attached to the disk drive base. A shaft is coupled to the spindle motor base and the spindle motor hub surrounds the shaft. The spindle motor hub may be rotatably coupled to the shaft and therefore the spindle motor base typically via a pair of bearing sets. A stator is positioned about the shaft and is attached to the spindle motor base. A magnet element is attached to the hub flange. The stator includes windings that selectively conduct current to create a magnetic field that interacts with the various poles of the magnet element. Such interaction results in forces applied to the spindle motor hub that tend to rotate the spindle motor hub and the attached disks.
The printed circuit board assembly includes a servo control system in the form of a disk controller for generating servo control signals. The head stack assembly is controllably positioned in response to the generated servo control signals from the disk controller. In so doing, the attached sliders are moved relative to tracks disposed upon the disk.
The head stack assembly includes an actuator assembly including the sliders and a flex circuit cable assembly attached to the actuator assembly. A conventional "rotary" actuator assembly (also referred to as "rotary actuator" or simply "actuator") typically comprises an actuator body, a pivot bearing cartridge, a coil portion that extends from one side of the actuator body to interact with one or more permanent magnets to form a voice coil motor, and one or more actuator arms which extend from an opposite side of the actuator body to a distal end of the actuator assembly. The actuator body includes a bore and the pivot bearing cartridge engaged within the bore for allowing the actuator body to rotate between limited positions. At least one head gimbal assembly (HGA) is distally attached to each of the actuator arms. Each head gimbal assembly biases a head towards the disk. In this regard, the actuator assembly is controllably rotated so as to move the heads relative to the disks for reading and writing operations with respect to the tracks contained on the disks.
A topic of concern is the desire to reduce the effects of airflow generated within the disk drive due to rotation of the disks. Of particular concern is the occurrence of turbulent airflow which may tend to excite a resonance response of the actuator assembly. This results in an increase in the percent off-track values of the associated head. Further, such disk rotation induced airflow may result in a force applied to the actuator assembly, i.e., windage. In addition, such disk rotation induced airflow may result in vibration of the disks or disk flutter.
Another topic of concern is contamination within the disk drive, and in particular, the rate and efficiency of filtering contamination. Various airflow circulation filtering systems have been utilized in the art. A typical arrangement is to provide a vertically disposed rectangular filter within a cavity of the disk drive. The filter is positioned such that disk rotation induced airflow impinges upon the filter. While much of the airflow flows through the filter, some airflow is found to flow upwards towards the cover. Such redirected airflow may tend to flow about the surface of the uppermost disk. In this regard, the heads at such location have been observed to be relatively more susceptible to failures due to contamination.
Accordingly, there is a need in the art for an improved disk drive configuration for filtering and mitigation of disk rotation induced airflow in comparison to the prior art.

Disk drive with airflow diverter filter component


A magnetic element control device controls a magnetic element during detection of an intensity of a stationary magnetic field by a time-resolved magnetic balance system where the magnetic field is applied to a flux-gate magnetic element that is constituted of an excitation coil and a detecting coil. The magnetic element control device includes: an excitation signal generator; an excitation signal adjuster; a detection signal comparator; a feedback signal converter; a feedback signal adjuster; and a data signal converter. The excitation signal adjuster superimposes a feedback signal on an alternating voltage signal and thereby generates an excitation signal, and applies the generated excitation signal to the excitation coil.

The present invention relates to a signal processing circuit, a physical quantity measurement device using a signal processing circuit, particularly, a magnetic element control device that drives a magnetic element utilizing a time-resolved flux gate system (hereinbelow, referred to as FG system), a magnetic device control method, and a magnetic detecting device that detects a magnetic field by use of the magnetic device control method.

Magnetic element control device, magnetic device control method, and magnetic detecting device


Novel tungsten hexa(dialkyldithiocarbamates) of the general formula I ##STR1## in which R and R.sup.1 can be identical or different, branched or straight-chain, saturated or unsaturated alkyl radicals having 1-18 carbon atoms are prepared by a process in which 6 mols of an alkali metal dialkyldithiocarbamate of the general formula II ##STR2## in which R and R.sup.1 are as signified above and Me can be sodium, potassium or ammonium, are reacted with 1 mol of tungsten hexachloride in a solvent which is inert with respect to the reaction. The alkali metal chloride or ammonium chloride formed is separated off and the tungsten hexa(dialkyldithiocarbamate) is isolated. The tungsten hexa(dialkyldithiocarbamates) of the invention can be used as additives for prolonging the life of hydraulic oils or permanent gear lubrication oils.

1. Field of the Invention:
This invention relates to tungsten hexa(dialkyldithiocarbamates) as well as to processes for the production of such compounds. The invention also relates to improved lubricating oil and hydraulic fluid compositions containing these compounds.
2. Brief Description of the Prior Art:
In accordance with conventional industrial processes, heavy metal dithiocarbamates are prepared either by double displacement reaction of alkali metal or ammonium dithiocarbamates with heavy metal halides or by reaction of metal oxides with amines and carbon disulfide.
When metal oxides of metals having a valence of 2-4 are used in the the conventional industrial techniques, the reaction yields oxide-free dialkyldithiocarbamates of the formula ##STR3## in which x represents the valency of the metal employed, in this case 2-4.
When the reactions are conducted using oxides of metals of higher valency the result is formation of oxide-containing dialkyldithiocarbamate mixtures of the general formula ##STR4## wherein n, m=1-2.
Oxide-free tungsten dithiocarbamates are hitherto unknown.
Accordingly, a need has continued to exist to prepare oxide-free tungsten dithiocarbamates and for a method of preparing them.

Tungsten hexaldialkyldithiocarbamates, process for their preparation and oil compositions containing them


A semiconductor device includes a semiconductor body including a drift zone of a first conductivity type, an emitter region of a second, complementary conductivity type configured to inject charge carriers into the drift zone, and an emitter electrode. The emitter electrode includes a metal silicide layer in direct ohmic contact with the emitter region. A net impurity concentration in a portion of the emitter region directly adjoining the metal silicide layer is at most 1×1017 cm−3.

The application relates to an electrical contact to semiconductor areas. For many known contact and barrier materials no or no ideal ohmic contact is feasible, if the contacted semiconductor material is lowly, e.g. lowly p-doped. In this case the persued ohmic contact reveals to be more like a Schottky contact including all its unfavorable characteristics, like an increased contact resistance, temperature dependent Schottky barrier and an accumulation of charge carriers of the other species.
In the field of semiconductor power devices like IGBTs (insulated gate bipolar transistors), RC-IGBTs (reverse conducting insulated gate bipolar transistors), diodes, lowly doped Silicon emitter areas are beneficial for enabling an adequate device performance with respect to low switching losses.
It is desirable to provide an improved electrical contact to an emitter region and to provide a manufacturing method thereof.

IGBT with emitter electrode electrically connected with impurity zone


A method of grinding an ingot for use in manufacturing a semiconductor or solar wafer is disclosed. The method includes providing an ingot including four flat sides and four rounded corner portions, each corner portion extending between an adjacent pair of the flat sides, and grinding a plurality of planar facets on each corner portion, each planar facet of the corner portion joined to an adjacent facet at a juncture and oriented such that each corner portion has a substantially arcuate shape. A wafer and ingot are also disclosed.

Single crystal silicon is the starting material in many processes for fabricating semiconductor electronic components and solar materials. For example, semiconductor wafers produced from silicon ingots are commonly used in the production of integrated circuit chips on which circuitry is printed.
To produce the semiconductor or solar wafers, a single crystal silicon ingot may be produced by melting polycrystalline silicon in a crucible, dipping a seed crystal into the molten silicon, withdrawing the seed crystal in a manner sufficient to achieve the diameter desired for the ingot, and growing the ingot at that diameter. The silicon ingot is then machined into a desired shape from which the semiconductor or solar wafers can be produced. For example, slicing a cylindrical ingot into thin, circular sheets produces circular wafers.
In some applications, a silicon ingot is machined into a pseudo-square ingot. To ensure precise dimensions, a grinding process is commonly used to improve certain features (e.g., flatness, parallelism, and surface finish) of the ingot. For example, in a true round grind process, the pseudo-square ingot is continuously rotated while a grinding surface grinds the ingot, grinding rounded portions on the pseudo-square ingot. However, at least some known grinding processes include rotating the ingot such that the grinding surface impacts the ingot, which may result in cracks, chips, and/or other damage to the ingot.
This Background section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.


A method and apparatus for controlling transfer of data in which a plurality of burst transfer operations starting from an arbitrary byte as a start address are performed consecutively without a high-speed adder provided in the conventional data transfer apparatus performing burst transfer. Data is transferred between memories by a plurality of consecutive burst transfer operations performed on data stored in consecutive addresses. Each of the burst transfer operations is performed on the data stored in a respective one of memory cell areas each of which corresponds to a unit of burst transfer. A first address representing an address of one of the memory cell areas storing data to be transferred is calculated. The first address is a part of a start address of a second or later burst transfer operation. A second address representing an address of one of memory cells provided in the one of the memory cell areas is calculated separately. The data transfer operation is started from the one of the memory cells. The second address is a part of the start address of the second or later burst transfer operation.

1. Field of the Invention
The present invention relates to a method and apparatus for controlling transfer of data and, more particularly, to a method and apparatus for controlling transfer of data using a burst transfer method which is generally performed in a data processing system.
2. Description of the Related Art
FIG. 1 is a block diagram of a part of a conventional data processing system in which a burst transfer operation is performed. In FIG. 1, an arithmetic processor 1 processes data. A memory 2 is an external memory comprising a dynamic random access memory (DRAM) having a capacity of 4 giga-bytes and a burst transfer mode. An external address bus 3 has a 32-bit structure. An external address bus 4 has a 64-bit structure.
FIGS. 2A-2E represent is a timing chart of a burst transfer operation performed between the arithmetic processor 1 and the external memory 2. FIG. 2A shows an external clock signal. FIG. 2B shows the state of a bus request signal output from the arithmetic processor 1 for requesting use of a bus. FIG. 2C shows a state of a bus acknowledge signal provided to the arithmetic processor 1 to permit use of a bus. FIG. 2D shows the state of the external address bus 3. FIG. 2E shows the state of the external address bus 4.
In the example shown in FIGS. 2A-2E, an address A1 is output to the external address bus 3 as a start address of the first cycle of burst transfer after a permission of use of the bus is provided upon the request for use of the bus output from the arithmetic processor 1. Then, the sets of data D1-D4 are sequentially output to the external address bus 4 in the order D1.fwdarw.D2.fwdarw.D3.fwdarw.D4. Thus, a burst transfer (a store transfer for the external memory 2 or a load transfer for an internal memory of the arithmetic processor 1) is performed for the sets of data D1-D4.
Thereafter, an address A2 is output to the external address bus 3 as a start address of the second cycle of burst transfer. Then, the sets of data D5-D8 are sequentially output to the external address bus 4 in the order D5.fwdarw.D6.fwdarw.D7.fwdarw.D8. Thus, a burst transfer is performed for the sets of data D5-D8.
Thereafter, an address A3 is output to the external address bus 3 as a start address of the third cycle of burst transfer. Then, the sets of data D9-D12 are sequentially output to the external address bus 4 in the order D9.fwdarw.D10.fwdarw.D11.fwdarw.D12. Thus, a burst transfer operation is performed for the sets of data D9-D12.
In the above-mentioned example, a number of consecutive sets of data transferred by a single burst transfer, which is referred to as a burst length, is 4. In this case, the period for calculating the address is one fourth of that of a case where the address is output for each of the sets of data D1-D12 for each clock pulse. This allows the design of a high-speed data processing system.
In the conventional burst transfer, the word length typically comprises several bytes, for example, 4 bytes or 8 bytes, so as to perform the data transfer on the word basis. Thus, it is no longer standard to perform a data transfer in which the transfer is started from an arbitrary byte, as a start address, in a single word.
When a plurality of burst transfer operations starting from an arbitrary byte as a start address are performed consecutively, it is required to calculate the start address for each clock signal pulse if the start address for the second and later burst transfer operations is determined by counting the number of words which have been transferred. Thus, there is a problem in that a high-speed adder for the address calculation is needed.

Data transfer control method and apparatus for performing consecutive burst transfer operations with a simple structure


The N-benzylindole- and benzopyrazole derivatives of the general formula 1 ##STR1## possess anti-asthmatic, anti-allergic, anti-inflammatory and immunomodulating effect and are suitable for the preparation of medicaments.

1. Field of the Invention
The invention relates to N-benzylindole- and benzopyrazole derivatives having anti-asthmatic, anti-allergic, anti-inflammatory and immunomodulating effects.
2. Background Information
Indole derivatives have many uses as synthetic building blocks for the synthesis of drugs, for example the drugs indomethacin and acemethacin have an N-substituted indole skeleton.
Indomethacin is the prototype of compounds having a predominantly anti-inflammatory and anti-rheumatic effect.
An indazole derivative that can be cited is the substance bendazac which has an anti-inflammatory effect; the synthesis of the substance, IUPAC name [(1-benzyl-1H-indazole-3-yl)oxy]acetic acid, is described in US PS 3 470 194.
DE-OS 42 25 756 and EP 392 317 describe benzimidazoles which constitute angiotensin antagonists, in particular angioterlsin-II antagonists.
DE-OS 27 31 647 describes 1,3-benzothiolanes and their pharmaceutically useful salts.
Colantti (Chim. Ther 6(5), 367-79) describe indole derivatives which have coccidiostatic properties.
Clark et al (J. Med. Chem, 36 (18), 264-57) describe 1H-indole-3-carboxamides substituted by quinuclidyl radicals and derivatives at the acid amide nitrogen. These compounds are 5HT.sub.3 antagonists and can, for example, be used as anti-emetics.
EP 490 263 describes N-methyl-indole derivatives as 5-HT-antagonists.
EP 485 962 describes N-methyl-indole derivatives as S.sub.3 -receptor antagonists.
WO 88/5432 describes N-alkyl substituted 3-indole-carboxylic acid derivatives as diuretics and cardiovascularly active substances.
WO 93/2062 also describes N-alkyl-substituted 3-indole carboxylic acid amides, in which the amide nitrogen is substituted by a heterocyclic system, such as a tetrazole ring or a substituted tetrazole ring.
EP 580 502 describes 3-(hydroxybenzylidenyl)-indoline-2-one-derivatives with an anti-inflammatory, analgesic, anti-arteriosclerotic and anti-asthmatic effect. The compounds, which can be present as an E/Z-isomer mixture, inhibit LTB.sub.4 synthesis.
The compounds carry various substituents at the indoline nitrogen; there is a keto- or thioketo group at the 2-carbon atom of the indoline ring.

N-benzylindole and benzopyrazole derivatives with anti-asthmatic, anti-allergic, anti-inflammatory and immunemodulating effect


Conductivity of carboxylic acid membranes can be increased for use in fuel cells when the membrane comprises a Lewis base, which has, in its protonated form, a pKa greater than the pKa of the carboxylic acid groups of the membrane. When the invention is employed in direct methanol fuel cells, water transport and methanol crossover though the membrane are decreased compared to conventional direct methanol fuel cells employing sulfonic acid membranes.

Fuel cells are generally made up of a cathode in its compartment and an anode in its compartment separated by an ion-exchange membrane that is usually a fluoropolymer having acid groups, e.g. sulfonic acid groups attached to the polymer chain. These are referred to as sulfonic acid ionomers, or, in membrane form, as sulfonic acid membranes. A fuel such as hydrogen or methanol is fed to the anode compartment, where it is oxidized, generating protons, which pass through the membrane and combine with oxygen at the cathode, producing water.
The management of water in the fuel cell, particularly control of water passing from the anode to the cathode side of the membrane, is important, because membrane conductivity is a function of water content and excessive water transport can result in drying out of the anode side of the membrane. In addition water accumulation at the cathode can result in flooding of the cathode, which interferes with cathode functioning and reduces fuel cell performance.
Existing fuel cell sulfonic acid membranes often have higher water transport than is desirable for best operation.
Direct methanol fuel cells (DMFC) use methanol as fuel directly, i.e. without first reforming the methanol to produce hydrogen to be used in the cell, typically use about 1-6% solution of methanol in water. Permeation of methanol through the membrane that separates the anode from the cathode is a problem in direct methanol fuel cells. This is referred to as methanol crossover. Crossover represents a loss of fuel cell efficiency because the crossover methanol is consumed without producing electric current. This direct consumption of methanol at the cathode also adversely affects the functioning of the cathode. Reduction of methanol crossover in direct methanol fuel cells is needed.
Membranes containing carboxylic acid ionomer, present as a layer laminated or coextruded with a layer of sulfonic acid ionomer, are widely used in the chloralkali industry as membrane separators in cells for the electrolysis of brine because of their superior ability to reject anions. These membranes, in chloralkali electrolyzers have lower water transport properties than do sulfonic acid ionomer membranes. However, though carboxylic acid ionomer membranes show acceptable conductivity in the chloralkali environment, where sodium or potassium ions conduct the current through the membrane, their conductivity when protons are the current carriers, as in the case of fuel cells, is very low. It is generally believed that carboxylic acid ionomer membranes are not useful in fuel cells.

Carboxylic acid-based ionomer fuel cells


A semiconductor device includes a semiconductor layer, an electrode layer arranged on the semiconductor layer, a crack starting point layer arranged above the semiconductor layer, and a solder layer being in contact with the electrode layer and the crack starting point layer. A joining force between the solder layer and the crack starting point layer is smaller than a joining force between the solder layer and the electrode layer.

In a general semiconductor device, due to a temperature cycle in which a temperature of the semiconductor device repeatedly rises and falls during its use, there may be a case where a stress is exerted on an inside of the semiconductor device and a crack (cracking) occurs. Patent Literature 1 (Japanese Patent Application Publication No. 2011-023631) discloses an art for improving resistance to cracks that occur in a semiconductor device. A configuration disclosed in Patent Literature 1 includes a semiconductor element, and an electrode layer arranged to face the semiconductor element. Moreover, this configuration includes an intermediate joint layer and a solder joint layer on a surface of the semiconductor element that faces the electrode layer. Moreover, semiconductor element protection resin is provided in a coating manner on the semiconductor element, and at least in an outer peripheral surface region between the intermediate joint layer and the solder joint layer.


An embodiment method for massively parallel processing includes initiating a management instance on an initial machine, the management instance generating an initial partition corresponding to the initial machine, determining a total number of partitions desired for processing a database, the total number of partitions including the initial partition, determining a number of additional machines available to process the database, grouping the initial machine and the additional machines together in a pod, and launching the management instance on the additional machines in the pod to generate the total number of partitions desired for the database. Additional embodiment methods and an embodiment system operable to perform such methods are also disclosed.

The concept of massively parallel processing (MPP) is the coordinated processing of a program by multiple processors, with each processor working on different parts of the program. The processors communicate with one another to complete a task with each of them using its own operating system and memory resources.
An MPP database system is based on shared-nothing architecture, with the tables of its databases partitioned into segments and distributed to different processing nodes. There is no data sharing among the processing nodes. When database queries arrive, the work of each query is divided and assigned to one of the processing nodes according to a data distribution plan and an optimized execution plan. The processing entities in each processing node manage only their portion of the data. However, these processing entities may communicate with one another to exchange necessary information during their work execution. A query may be divided into multiple sub-queries, and the sub-queries may be executed in parallel or in some optimal order in some or all the processing nodes. The results of the sub-queries may be aggregated and further processed, and subsequently more sub-queries may the executed according to the results.
One of the challenges in an MPP database system has always been in setting up the distributed system, which includes configuring the machines, creating the database, partitioning the tables, and distributing the segments. How data is distributed and how much the distribution is aligned with the business logic greatly determines the overall performance of the system.
A traditional MPP database system allows a database administrator to create a database and distribute its data (i.e., create database partitions) to a fixed number of processors that are setup ahead of time. Unfortunately, the number of partitions a database administrator can create is fixed and directly corresponds to the number of processors available in the traditional MPP database system. In other words, the number of partitions and the number of processors is always the same. If additional partitions are desired, the entire process of setting up instances and partitions must be repeated.

System and method for flexible distributed massively parallel processing (MPP)


The invention relates to a composition, especially a cosmetic composition, comprising at least one hyperbranched polyol and at least one acrylic film forming agent, as well as to methods of using such compositions.

Many cosmetic compositions, including pigmented cosmetics such as foundations, concealers, lipsticks, and mascaras, and other cosmetic and sunscreen compositions, have been formulated in an attempt to posses long wearing properties upon application. Unfortunately, many of these compositions do not possess long lasting shine properties. Moreover, shiny compositions oftentimes do not possess good wear and/or comfort properties.
Such compositions can contain a large amount of film forming agents to achieve long wear properties, possibly in combination with volatile solvents. However, these formulations generally possess poor shine characteristics, both initially and over time.
Alternatively, two step products have been developed, using a topcoat to provide shine and/or comfort to a basecoat which is matte and/or dry.
Thus, there remains a need for improved cosmetic compositions having improved cosmetic properties, particularly good wear, feel, shine and texture characteristics upon application.
Accordingly, one aspect of the present invention is a care and/or makeup and/or treatment composition for keratinous materials which has good cosmetic properties such as, for example, good shine, feel, wear and/or texture properties upon application.

Compositions containing hyperbranched polyol and acrylic film former


The invention relates to a substrate for epitaxy, especially for preparation of nitride semiconductor layers. Invention covers a bulk nitride mono-crystal characterized in that it is a mono-crystal of gallium nitride and its cross-section in a plane perpendicular to c-axis of hexagonal lattice of gallium nitride has a surface area greater than 100 mm2, it is more than 1,0 μm thick and its C-plane surface dislocation density is less than 106/cm2, while its volume is sufficient to produce at least one further-processable non-polar A-plane or M-plane plate having a surface area at least 100 mm2. More generally, the present invention covers a bulk nitride mono-crystal which is characterized in that it is a mono-crystal of gallium-containing nitride and its cross-section in a plane perpendicular to c-axis of hexagonal lattice of gallium-containing nitride has a surface area greater than 100 mm2, it is more 1,0-μm thick and its surface dislocation density is less than 106/cm2. Mono-crystals according to the present invention are suitable for epitaxial growth of nitride semiconductor layers. Due to their good crystalline quality they are suitable for use in opto-electronics for manufacturing opto-electronic semiconductor devices based on nitrides, in particular for manufacturing semiconductor laser diodes and laser devices. The a.m. bulk mono-crystals of gallium-containing nitride are crystallized on seed crystals. Various seed crystals may be used. The bulk mono-crystals of gallium-containing nitride are crystallized by a method involving dissolution of a gallium-containing feedstock in a supercritical solvent and crystallization of a gallium nitride on a surface of seed crystal, at temperature higher and/or pressure lower than in the dissolution process.

1. Field of the Invention
The invention relates to a bulk nitride mono-crystal especially for use as a substrate for epitaxy. Such a substrate for epitaxy is particularly suitable for preparation of nitride semiconductor layers in a process for manufacturing of various opto-electronic devices.
Known nitride-based opto-electronic devices are manufactured on sapphire or silicon-carbide substrates, differing from the thereafter deposited nitride layers (i.e. heteroepitaxy).
2. Description of the Related Art
In the most commonly used Metallo-Organic Chemical Vapor Deposition (MOCVD) method, GaN depositing is performed from ammonia and metallo-organic compounds from the gaseous phase, and the growth rates attained make it impossible to receive a bulk layer. However, MOCVD cannot produce a bulk crystal having a substantial thickness. In order to reduce surface dislocation density a buffer layer is first deposited on sapphire or silicon substrate. However, the reduction of surface dislocation density achieved is not bigger than to about 108/cm2.
Another method that has been proposed for the manufacturing of bulk mono-crystalline gallium nitride, involves epitaxial depositing using halogens in the gaseous phase and is called Halide Vapor Phase Epitaxy (HVPE) ["Optical patterning of GaN films" M. K. Kelly, O. Ambacher, Appl. Phys. Lett. 69 (12) (1996) and "Fabrication of thin-film InGaN light-emitting diode membranes" W. S. Wong, T. Sands, Appl. Phys. Lett. 75 (10) (1999)]. The method allows generation of GaN substrates 2 inches in diameter, but the quality is insufficient for application in laser diodes, because the surface density of defects still remains in the 107 to 109/cm2 range. Besides, the HVPE GaN substrates have tilted crystal axes because of distortion caused by epitaxial growth on hetero-substrates, for example on sapphire.
Recently, defect density decrease is attained by using the Epitaxial Lateral Overgrowth (ELOG) method. In this method, a GaN layer is first grown on the sapphire substrate, and then SiO2 is deposited in the form of strips or grids. Next, such a substrate may be used for lateral GaN growing, reducing the defects density to about 107/cm2.
Due to significant differences in chemical, physical, crystallographic and electrical properties of substrates such as sapphire or silicon carbide and semiconductor nitride layers deposited thereon by hetero-epitaxy, big technological effort is needed to advance progress in opto-electronics.
On the other hand growth of bulk crystals of gallium nitride and other nitrides of Group XIII elements is also extremely difficult (numbering of the Groups is given according to the IUPAC convention of 1989 throughout this application). Standard methods of crystallization from alloy and sublimation methods are not applicable because of decomposition of the nitrides into metals and N2. In the High Nitrogen Pressure (HNP) method ["Prospects for high-pressure crystal growth of III-V nitrides" S. Porowski et al., Inst. Phys. Conf. Series, 137, 369 (1998)] decomposition is inhibited by applying a nitrogen atmosphere under high pressure. Growth of crystals is carried out in melted gallium, i.e. in the liquid phase, resulting in production of GaN platelets about 10 mm in size. Sufficient solubility of nitrogen in gallium requires temperatures of about 1500° C. and nitrogen pressures of the order of 1500 MPa.
In another known method, supercritical ammonia was proposed to lower the temperature and decrease pressure during the growth process. It was proven in particular that it is possible to obtain crystalline gallium nitride by synthesis from gallium and ammonia, provided that the latter contains alkali-metal amides (KNH2 or LiNH2). The processes were conducted at temperatures of up to 550° C. and pressure 500 MPa, yielding crystals of about 5 μm in size ["AMMONO method of BN, AlN, and GaN synthesis and crystal growth" R. Dwiliński et al., Proc. EGW-3, Warsaw, Jun. 22-24, 1998, MRS Internet Journal of Nitride Semiconductor Research, http://nsr.mij.mrs.org/3/25].
Use of supercritical ammonia also allowed recrystallization of gallium nitride within the feedstock comprising finely crystalline GaN ["Crystal Growth of gallium nitride in supercritical ammonia" J. W. Kolis et al., J. Cryst. Growth 222, 431-434 (2001)]. Recrystallization was made possible by introduction of amide (KNH2) into supercritical ammonia, along with a small quantity of a halogen (KI). Processes conducted at 400° C. and 340 MPa gave GaN crystals about 0.5 mm in size. However, no chemical transport processes were observed in the supercritical solution, in particular no growth on seeds.
The thus obtained nitride mono-crystals are of no industrial use as substrates for epitaxy, mainly because of their insufficient size and irregular shape.
Lifetime of optical semiconducting devices depends primarily on crystalline quality of the optically active layers, and especially on surface dislocation density. In case of GaN-based laser diodes, it is beneficial to lower dislocation density in the GaN substrate layer to less than 106/cm2, and this is extremely difficult in the methods used so far. On the other hand industrial processes for manufacturing such optical semiconducting devices can be performed only on reproducible substrates meeting strict quality specifications.

Bulk nitride mono-crystal including substrate for epitaxy


This safety cap comprises a unitary shell made of a rigid, light weight and impact-resistant plastic material and forming a dome shaped body to fit the wearer's head with ventilation openings and a rear recess for the passage of a wearer's pony tail. An air permeable fabric cover completely covers the shell body for the purpose of thermal insulation, for esthetic value and for preventing entering of insects through the shell ventilation openings while allowing ventilation within the shell body. The fabric cover has a dependent flange which is folded around the exposed edge of the shell body and attached to the interior surface of the shell body by hook and loop fastener bands. This flange is padded and extends around the wearer's head. The rear portion of the cover has also a recess in register with the shell body recess and is provided with length adjustable fastening straps to secure the cap in position.

Head injuries can be very severe when high velocity objects impact with the head. This is true in many sports, such as golf and baseball. Rigid, impact-resistant baseball safety caps are known but they do not protect against biting insects and they lack in air ventilation and in esthetic value. Known golf caps made of fabric with different patterns and colors have an esthetic value, are useful for thermally insulating the wearer's head, are air permeable to allow head ventilation and provide a barrier against insects. However they cannot resist an impact.
U.S. Pat. No. 3,315,273 issued Apr. 25, 1967 to E. C. Bullard and entitled "Safety cap" shows and describes a safety cap to be used by industrial and commercial workers. It comprises a rigid, impact-resistant shell having a front visor and a cloth cover adapted to fully cover the shell; the shell has no ventilation openings and the cloth cover is snapped onto the outer surface of the rigid shell by means of studs outwardly protruding from the shell rim. The purpose of the cloth cover is to prevent electrical static charge, adjustment of the cap to different head sizes is accomplished by forming the shell into a plurality of segments obtained by vertical slots in the shell. These slots cannot provide air ventilation since they are covered by an inside padding made of sponge rubber and not air permeable.