Loaded chamber indicator systems semi-automatic handguns wherein a loaded chamber indicator is extended by the empty cartridge ejector when the empty cartridge ejector rests on a cartridge in the handgun chamber. In one embodiment, the loaded chamber indicator is in an opening or hole in the back of the slide, with the inner end of the loaded chamber indicator being enlarged and fitting within an inclined slot in the empty cartridge extractor so as to be extended or retracted dependent on whether the empty cartridge ejector rests on a cartridge in the handgun chamber. The empty cartridge extractor may be mostly molded plastic with a metal end for engaging cartridges, and the loaded chamber indicator may be entirely molded plastic. Multiple embodiments are disclosed.

1. Field of the Invention
The present invention relates to semiautomatic slide handguns (referred to herein as simply semiautomatic handguns).
2. Prior Art
New semiautomatic handguns must have what is referred to as a loaded chamber indicator. A loaded chamber indicator is a safety device. It is usually a small button that pops out to indicate the presence of a round in the chamber. By way of example, on the Beretta 90two, the loaded chamber indicator is a small red tab (extractor) that protrudes further from the slide when a round is in the chamber. The tab is located on the right side of the pistol's slide, near the cartridge chamber, and can be both seen and felt, allowing the user to check the chamber at night by feel or during the day by checking for the increased protrusion of the red tab.
On Glock semiautomatic handguns, the loaded chamber indicator also extends out the side of the slide when a cartridge is in the chamber. Commonly, the loaded chamber indicator of the prior art is a red button on the empty cartridge extractor, extending outward when the front of the extractor does not move substantially inward because of its encountering a casing of a loaded cartridge in the chamber.

Loaded chamber indicator systems for semiautomatic handguns


The present invention provides a method and a computer-readable program for providing generation of graphical congestion images during placement driven synthesis optimization. These graphical congestion images enable a design engineer to make changes and/or improvements to subsequent processes in the design flow before the current placement driven synthesis step completes, thus saving time. This information also provides valuable debug information to PDS developers.

Modern semiconductor design relies heavily on the use of various software tools, which perform the tasks required to implement a desired circuit design onto silicon. In general, a traditional serial design process, as shown in FIG. 1 element 100, begins with a definitional design 102 which, as it names implies, describes the desired logical, timing and power parameters of the desired circuit. The definitional design is typically implemented in a computer readable file written in a hardware description language ("HDL") such as Verilog, HDL, VHDL, DSL, etc. The definitional design is also referred to as a behavioral description or model of the circuit. The HDL file is then provided to two categories of tools, which are used to test the design and convert the HDL into other computer readable files needed to actually fabricate the circuit.
The first category includes functional design and verification tools 104 (e.g., simulation tools) which are used to test the circuit's logical performance (i.e., whether the circuit generates the desired output signals in response to a predefined set of input signals). The functional design and verification tools are typically software implemented processes which are run on a workstation or other computer processors. These tools use the HDL file to create a software model of the definitional design. A variety of simulated inputs may then be applied to the software model. The resulting outputs of the model are recorded and compared to expected outputs to determine whether the definitional design produced the logical results required. Since simulation is concerned, primarily, with the logical performance of the design, simulation tools are largely technology independent (i.e., the design has not been mapped to specific cell libraries which contain data for constructing actual electronic components according to known fabrication processes).
The second category includes synthesis and implementation tools. Like simulation tools, synthesis and implementation tools are typically implemented in software which runs on a workstation or other computer processor. However, these tools are highly technology dependent and are used to create an implementation of the circuit components onto the chip. Specifically, logic synthesis tools 106 are used to generate a mapped logic "netlist", which contains a description of the gates and interconnections between gates for the desired circuit. Within traditional logic synthesis tool 106, interconnect delay is modeled using wire-load models (WLM's). Wire load models are statistical predictors of average net behavior which predict wire capacitance, not length or resistance. A designer iterates between synthesis, HDL changes and choice of WLM's (with the aid of a floorplanning tool 108) until synthesis indicates timing closure at the proposed area.
Recently, synthesis tool vendors have added power optimization (i.e., minimization of power consumption), to this logic optimization process. Once the designer achieves closure in synthesis, Design for Testability logic 110 is inserted into the design. This logic includes scan chains, and more powerful DFT extensions such as IEEE 1149.1 structures and Logic Built-in Self Test. The designer defines and inserts clock (and other fanout) powering networks. Next, sign-off tools 112, such as timing analysis, are applied to the design, to assess conformance to criteria for entry into the layout process.
The design then enters the layout process. First, a netlist is provided to a placement tool 114. The placement tool 114 determines where the gates of the circuit will be physically located within a location on the chip which has been predesignated to contain the circuit. This location is referred to as the "image". Physical designers measure timing based on estimated wire delays using methods such as Steiner estimation. The physical designers also resolve timing and congestion problems, using a variety of optimization tools 118 and manual changes, until estimated timing and congestion appear to be good. Sometimes, these problems require logic or floorplan changes by the logic designer, requiring a design handoff between the logic design and the physical designer. Then, further optimization tools are used to re-order the scan chains to minimize wire lengths and latch wire loads. The designer balances the clocks using a clock optimization tool, which re-organizes the connectivity amongst clock buffers and latches with respect to placement, and minimizes buffer loading towards an objective of minimal clock skew at each level of repowering.
After the circuit has been placed, the data from the placement tools is provided to a router 116. The router generates the fabrication data required to construct the metal lines on the chip that connect the components of the circuit together. After routing, parasitics for final timing analysis are extracted. At this point, further engineering changes (ECO's) may be required to fix timing issues such as early mode hold problems, or to alleviate congestion issues. Again, this may require a design hand-off between the physical designer and the logic designer. These final fixes are affected using various optimization tools 118 and manual means. Prior to release of the design to manufacturing, a test engineer produces a set of test vectors for the design, where a final set of manufacturability checks are executed.
After routing and verification, all the files containing the computer data required to fabricate an implementation of the circuit are available. This is referred to as the final design data 120. The final design data is then sent to manufacturing where the final design data from other circuits on the chip are integrated together and the actual chip is manufactured.
In the traditional design flow of FIG. 1, there is significant iteration between design engineering actions (in both the logical and physical design disciplines) and the CPU-intensive tasks of logical & physical design processing and logical and physical optimization.
Recent advances in the area of Placement Driven Synthesis (PDS) have improved this situation. As shown in FIG. 2 element 200, placement driven synthesis techniques can be executed as an early timing closure technique, in which an enhanced logical synthesis tool 202 creates an initial placement that is simultaneously optimized with the logic design. In other words, PDS optimizes a design for timing and area based on input constraints (e.g., timing constraints, die size, technology information, etc.). PDS requires some initial block-level floorplanning, as provided by floorplanner 204. A timing closure feedback loop exists whereby information from logic synthesis 202 is passed back through a timing correction tool 206 and block level floorplanner 204, before being fed back into the logic synthesis tool 202. Since placement information is available within PDS, actual wirelengths, rather than WLM's, are available to aid the designer when optimizing the logic design.
After this early timing closure, the logic designer proceeds to DFT logic and clock logic insertion 110. Placement Driven Synthesis techniques can also be executed as a late timing closure technique by the physical designer. A fully placed design, with an estimated, global, or detailed route, is optimized using a placement-based synthesis tool 208 capable of localized changes to the logic and/or the placement, to fix localized timing or electrical issues. Thus, Placement Driven Synthesis improves the total design process flow by reducing the number of design iterations required between the physical and logical design engineers.
The Placement Driven Synthesis operation is a very complex, multi-step, compute-intensive process which can take several days to complete. Existing design automation tools can be used to graphically view congestion information related to the design before or after PDS optimization. However, executing a post-PDS process step can be time consuming and is meant mostly for interactive debug. In addition, such a step only provides a snapshot of what a design looks like at the end of PDS, and not during the process.
There is a need for a tool to provide graphical congestion data concurrent with a placement driven synthesis operation. Such a tool should provide a graphical, real-time snapshot of what the design looks like during several steps within the placement driven synthesis process. Such information would enable a design engineer to make changes and/or improvements to subsequent processes in the design flow before the current placement driven synthesis step completes, thus saving time. This information would also provide valuable debug information to PDS developers.

Generation of graphical congestion data during placement driven synthesis optimization

International Business Machines Corporation


A locking device for a carton comprising a first part and a second part complementary to the first part, the first part comprising a first panel (12) having an aperture for receiving the second part, the second part comprising a tab (22) coupled to a second panel, the tab having a fold line (15a, 15b) foldable to form a leading edge, the tab being inserted into the aperture in a folded condition, the tab comprising at least one engaging edge (30a, 30b) for engaging with the first panel.

In the field of packaging it is often required to provide consumers with a package comprising multiple primary product containers. Such multi-packs are desirable for shipping and distribution and for display of promotional information. For cost and environmental considerations, such cartons or carriers need to be formed from as little material as possible and cause as little wastage in the materials from which they are formed as possible. Another consideration is the strength of the packaging and its suitability for holding and transporting large weights of articles.
It is desirable in such packages to provide a fastening device for locking two panels of a carton together. In use, fastening devices known in the art can be inadvertently disengaged. It is therefore desirable to provide a fastening means which is robust and remains in a locked condition, but which may be unlocked if required.


In one embodiment, an apparatus can include a service broker configured to: (i) register a service classifier, and to provide context information to the service classifier; and (ii) register a plurality of service nodes. The service broker can also receive capability and service requests from the service classifier. Further, the context information can include a service header, a reachability indication, and an encapsulation, where the service header and the encapsulation may be attached or related to a packet in the service classifier. In addition, the service classifier can use this information to redirect the packet to a first service node.

In modern Internet Protocol (IP) networks, there may be no consistent or uniform way to add "high-touch" services, or other services or features, to the network. Each unique service is typically added in a service-specific manner. Due to complexities in deployment and management, potential services may be foregone because of a lack of a consistent, inter-service architecture. As a result, such systems can suffer: (i) higher deployment costs; (ii) lower network availability; (iii) modified network topology; (iv) additional complexity in network operations and management; and/or (v) inability to use certain services in enterprise, commercial, or service provider networks.
Conventional approaches can include adding features to a forwarding path, providing hardware alterations (e.g., adjusting cable connections, or adding external devices), or performing other static configuration changes, software traces, and/or internal routing to add services to a network. However, such conventional approaches typically differ for different services, and thus may not provide a consistent, inter-service architecture for adding services to a network.


A safelock system for removable gears is provided having a self-seating gear segment rotatably mounted on a helical ball spline for bi-directional axial movement with respect to the gear teeth to be locked. A relubrication structure is provided to service the interior of the ball spline. The interlocking teeth are two-dimensionally tapered from the point of initial engagement. Diverse biasing structures are employed to facilitate the axial self-seating reaction of the gear segment after initial engagement with the gear to be locked.

The present invention relates generally to arrangements for preventing the movement of a gear and, more particularly, to gear locking mechanisms having jam prevention structures.
A wide variety of devices have been used to selectively prevent rotational movement of gears and lock against actuation of whatever application is driven by the gears. In general, such arrangements can be referred to as "safelock" systems. However, the environment where the safelock system is employed can restrict the availability of certain prior devices for that purpose.
For example, in an aircraft hydraulic, mechanical and/or electrical power sources can employ gears to transmit power or actuation force to a variety of applications. In addition to the positive lock and safety criterion of ground-based safelock systems, the aircraft environment requires the arrangement to be lightweight, compact in size, highly reliable over long periods of time and unusually rugged with respect to mechanical and thermal stresses. In addition, ease of maintenance and serviceability are important design considerations.
As a specific example, safelock systems have previously been used to prevent inadvertent actuation of weapons access doors on military aircraft. One such safelock system included a gear segment which was selectively rotatable into engagement with the carrier gear of a hydraulic motor. The gear segment was supported for axial movement in either direction (backward or forward with respect to the direction of travel of the gear teeth) along the rotational axis between a plurality of biasing springs by a cam and pin assembly. Such bi-directional axial motion was intended to reduce the incidence of jamming between the gear teeth and the teeth of the gear segment by permitting the gear segment to be self seating between the gear teeth.
To further prevent such jamming, the gear teeth and the teeth of the gear segment were modified to include a taper from the side upon which those teeth first engage. That taper was typically "two dimensional" in that it was directed both inwardly from the side and downwardly from the top of the teeth.
Unfortunately, such prior safelock devices were subject to undesirably high friction upon actuation and, thus, did not always perform optimally. Accordingly, it was previously suggested to replace the cam/pin assembly with a ball bearing assembly. Unfortunately, single or three ball sets proved insufficient to sustain the load requirements, and significantly reduce actuation friction. As a result, a multiple ball array, such as a helical ball spline, was proposed. While such an array permitted significantly lower actuation friction, reliability maintenance for longer periods of time required relubrication of the array, preferably at the interior and outwardly from the longitudinal axis of the array. It was found, however, that acceptable relubrication structures interfered with the use of prior bi-directional spring biasing structures.
Biasing for axial motion of the gear segment forward with respect to the jack gear was still feasible using the prior biasing structure with the relubrication structure, but there was insufficient room for the prior backward motion biasing structure without at least significantly enlarging the size of the safelock assembly and complicating serviceability. In general, the prior biasing structures included helical springs on either side of the gear segment to achieve axially backward and forward biasing. Where only axially forward biasing was used, a helical spring was mounted on one side of the gear segment.
Accordingly, it is an object of this invention to provide an improved safelock system, especially for use in efficiency conscious environments such as aircraft. Further objects include at least providing a safelock system:
A. requiring reduced actuation friction, PA1 B. having a long useful life, PA1 C. with a decreased tendency to jam, PA1 D. of minimal cost and dimension, and PA1 E. which is easy to maintain and service.
These objectives are attained by the provision of a safelock system having a self-seating gear segment rotatably mounted on a helical ball spline for bi-directional axial movement with respect to the gear teeth to be locked. A relubrication structure is provided to service the interior of the ball spline. The interlocking teeth are two-dimensionally tapered from the point of initial engagement. Diverse biasing structures acting on opposing sides of the gear segment are employed to facilitate the axial self-seating reaction of the gear segment after initial engagement with the gear to be locked.
Other objects, advantages and novel features of this invention will become readily apparent from the following drawings and detailed description of preferred embodiments.

Method and apparatus for a low friction safelock system


A dielectric ceramic composition may include a base powder represented by (1-x) BaTiO3-xBiMO3 (M being configured of Mg and Ti) containing a first main component represented by BaTiO3 and a second main component represented by BiMO3, x satisfying 0.005≦x≦0.5, and Some embodiments of the present disclosure may provide a novel dielectric ceramic composition capable of securing X8R temperature characteristics and reliability.

The present disclosure relates to a novel dielectric ceramic composition having guaranteed X8R temperature characteristics and reliability, and a multilayer ceramic capacitor containing the same.
Generally, electronic components using ceramic materials, such as capacitors, inductors, piezoelectric elements, varistors, thermistors, and the like, include a ceramic body formed of a ceramic material, internal electrodes formed in the ceramic body, and external electrodes mounted on a surface of the ceramic body to be connected to the internal electrodes.
Among the ceramic electronic components, a multilayer ceramic capacitor includes a plurality of stacked dielectric layers, internal electrodes disposed to face each other, having a dielectric layer therebetween, and external electrodes electrically connected to the internal electrodes.
The multilayer ceramic capacitors have been widely used as components for computers, mobile communications devices such as personal digital assistances (PDAs), mobile phones, and the like, due to advantages such as a small size, high capacitance, easiness of mounting, and the like.
The multilayer ceramic capacitor is generally manufactured using a sheeting method, a printing method, or the like.
Dielectric materials used for high-capacitance multilayer ceramic capacitors and the like, according to the related art, are ferroelectric materials based on barium titanate (BaTiO3), and have high dielectric constant characteristics at room temperature, comparatively low dissipation factor characteristics, and excellent insulation resistance characteristics.
However, the dielectric material, based on barium titanate (BaTiO3), may be problematic in terms of securing reliability with the use thereof, while satisfying X8R characteristics, namely, stable operating characteristics at temperatures of up to 150° C.
Therefore, a material capable of securing reliability while satisfying X8R characteristics, at temperatures of up to 150° C., is in demand.

Dielectric ceramic composition and multilayer ceramic capacitor containing the same


Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P+ doped drain region is disposed in the high-V N-well. A P+ diffused region and an N+ doped source region are disposed in the P-body doped region. A gate structure is disposed on the semiconductor substrate with one end adjacent to the N+ doped source region and the other end extending over the insulation region.

1. Field of the Invention
The invention relates to electrostatic discharge (ESD) protection devices, and in particular, to insulated gate bipolar transistor electrostatic discharge (IGBT-ESD) protection devices.
2. Description of the Related Art
Conventional high voltage electrostatic discharge (ESD) protection devices include lateral diffused metal oxide semiconductor (LDMOS) power transistors, metal oxide semiconductor field effect transistors (MOSFET), silicon control rectifiers (SCR), bipolar junction transistors (BJT), diodes and field oxide devices (FOD). For a device experiencing high voltage electrostatic discharge (ESD), an inner circuit may either be damaged or result in a latch-up effect due to an overly high trigger voltage and an overly low holding voltage. Therefore, by adding an additional driving circuit to the device, or by regulating layout parameters, trigger voltage can be reduced such that a holding voltage of the device can be higher than an operation voltage. Thus, resulting in high voltage electrostatic discharge (ESD) protection.
For conventional ultra-HV devices, a silicon-on-insulator (SOT) substrate and fabrication processes thereof are adopted to isolate individual devices, thereby eliminating parasitic effects between devices during high voltage operation. However, by using the silicon-on-insulator (SOT) substrate and fabrication processes thereof, heat dissipation ability of the ultra-HV devices may be diminished. Thus, an effective solution for dissipating heat generated by ESD protection devices has long been pursued. Meanwhile, during fabrication of high-voltage devices, the diffused concentration of well doped regions is quite low, such that relative impedance increases, therefore, diminishing the ability for the ESD protection devices to be uniformly turned on.

Vanguard International Semiconductor Corporation


An image formation device having a hierarchically structured function setting menu in which plural function setting items including a function setting item for an optional device are managed in a hierarchical structure, the hierarchically structured function setting menu being sequentially displayed according to the hierarchical structure to select a desired function setting item to perform a function setting, the image formation device including a detector that detects a connection of the optional device, and a changing unit that changes the function setting item for the optional device to a top level of the hierarchically structured function setting menu when the connection of the optional device is detected by the detector.

1. Field of the Invention
The present invention relates to an image formation device and its control method, and particularly to an image formation device and its control method which are designed to selectively display an optimal menu screen according to the connection status of an optional device connected to the image formation device having an operation panel formed by an LCD (liquid crystal display) or the like, and thus are capable of improving its usability for operators.
2. Description of the Related Art
An operation screen is displayed on an LCD (liquid crystal display) of an operation panel provided in an image formation device such as a copier, a printer, or a facsimile. Conventionally, this operation screen includes plural menu screens formed in a hierarchical structure. A desired menu option is selected on an initially displayed menu screen. If the selected menu option includes further options to be selected, a subsequent selection menu screen is displayed to display those menu options. The selection menu screens are displayed sequentially in this manner to allow the user to select a desired menu options thereon.
The display sequence of the operation screens having such a hierarchical structure is preset before factory shipment of the image formation device. A function setting menu screen also has a hierarchical structure in which plural function setting items including those of optionally connected devices are managed by the hierarchical structure, and the function setting menu screens are sequentially displayed according to the preset hierarchical structure regardless of the connection status of an optional device connected by the user to the image formation device.
When the user performs a predetermined operation using such operation screens that are displayed in the preset sequence according to the hierarchical structure, a function setting menu screen may be displayed on the LCD to prompt the user to select whether a certain optional device is to be used or not even though no such optional device is connected to the image formation device. This causes a problem in usability.
Therefore, there is a demand for a method to display an operation screen in a highly usable manner, with its hierarchical structure being optimized according to the connection status of an optional device connected to the image formation device. For example, Japanese Patent Application Laid-Open No. 11-240229 proposes a recording system the usability of which is improved by optimizing the hierarchical structure of menus displayed on a display panel such as an LCD according to the connection status of an optionally connected apparatus.
The recording system proposed by Japanese Patent Application Laid-Open No. 11-240229 is designed to optimize an optimal operation menu for an optional device such as an automatic cutter or a barcode verifier connected thereto, that is displayed by an LCD for the system user, by the method of detecting the connection status of the optional device by means of a sensor and an I/O port, and dynamically changing the hierarchical structure of the operation menu according to a result of the detection.
In the recording system described in Japanese Patent Application Laid-Open No. 11-240229, however, if the optional device requires various settings to be performed on the display panel before using the same, these settings are added into the menu regardless of whether or not the optional device is connected. Thus, the recording system has a problem in the usability in the default settings.

Image formation device and its control method


Regulatory B cells (tBreg) are disclosed herein. These regulatory B cells express CD25 (CD25+) a pan B cell marker such as B220 (B220+), and also express CD19 (CD19+). These regulatory B cells suppress resting and activated T cells in cell contact-dependent manner. Methods for generating these regulatory B cells are also disclosed herein, as are methods for using these regulatory B cells to produce regulatory T cells (Treg). In some embodiments, methods for treating an immune-mediated disorder, such as an autoimmune disease, transplant rejection, graft-versus-host disease or inflammation, are disclosed. These methods include increasing regulatory B cell number or activity and/or by administering autologous regulatory B cells. Methods for treating cancer are also disclosed herein. These methods include decreasing regulatory B cell activity and/or number.

Cancer escape is an active process that regulates immune responses employing at least two types of suppressive cells, myeloid-derived suppressive cells (Gr1+ CD11b+ MDSCs) and regulatory T cells (Tregs) (Youn et al., J. Immunol. 181, 5791-5802, 2008; Nagaraj and Gabrilovich, Cancer Res. 68, 2561-2563, 2008; Liu et al., J. Immunol. 178, 2883-2892, 2007; Olkhanud et al., Cancer Res. 69, 5996-6004, 2009). For example, cancer cells produce or induce production of GM-CSF, IL-1β, IL-6 and TGFβ to promote generation of Gr1+ MDSCs and M2 macrophages which, in turn, impair antitumor immune responses and promote metastasis (DuPre et al., Int. J. Exp. Pathol. 88, 351-360, 2007; Danna et al., Cancer Res. 64, 2205-2211, 2004; Sinha et al., J. Immunol. 174, 636-645, 2005). This occurs through direct action or indirectly by activating Tregs.
Tregs, as a key subset of CD4+ T cells that control peripheral tolerance to self- and allo-antigens (Sakaguchi et al., J. Immunol. 155, 1151-1164, 1995), represent a group of regulatory T cells expressing CD25 (IL-2Rα), CTL-associated antigen 4 (CTLA-4), scurfin and importantly a fork-head box P3 (FoxP3) gene product (Fontenot et al., Nat. Immunol. 4, 330-336, 2003). They are responsible for direct or indirect inhibition of T cell responses through the suppression of antigen-presenting cells, such as dendritic cells (Serafini et al., Cancer Immunol. Immunother. 53, 64-72, 2004; Huang et al., Cancer Res. 66, 1123-1131, 2006). To do this, they utilize (Fontenot et al., supra 2003; Zheng et al., J. Immunol. 172, 2778-2784, 2004; Cavani et al., J. Invest Dermatol. 114, 295-302, 2000) cell contact-dependent processes involving FasL/Fas and PD1/B7-H1 (Olkhanud et al., supra, 2009; Phares et al., J. Immunol. 182, 5430-5438, 2009; Probst et al., Nat. Immunol. 6, 280-286, 2005), though the use of secreted suppressive factors such as IL-10, TGF-β, IL-27 and IL-35 have also been reported (Groux et al., Nature 389, 737-742, 1997; Annacker et al., J. Immunol. 166, 3008-3018, 2001; Awasthi et al., Nat. Immunol. 8, 1380-1389, 2007; Collison et al., Nature 450, 566-569, 2007). As a result, Tregs are considered to play a key role in the escape of cancer cells from anti-tumor effector T cells (Ishida et al., Clin. Cancer Res. 9, 3625-3634, 2003; Curiel et al., Nat. Med. 10, 942-949, 2004; Woo et al., J. Immunol. 168, 4272-4276, 2002; Beyer et al., Blood. 106, 2018-2025, 2005). In addition, Tregs play an active role in breast cancer lung metastasis by protecting metastasizing cancer cells from NK cells (Olkhanud et al., supra, 2009).
However, a need remains to identify other regulatory immune cells, and to use these cells for the treatment of immune-mediated disease. In addition, a need remains for inhibiting regulatory immune cells that can inhibit immune-mediated therapy, such as for the treatment of cancer.

Regulatory B cells (tBREGS) and their use

The United States of America, as represented by the Secretary, Department of Health and Human Services


The present invention is a switching power source device which converts AC power of an AC power source into DC power and outputs the DC power, the device including: a rectifying-smoothing circuit configured to output a rectified-smoothed voltage signal obtained by rectifying and smoothing an AC voltage of the AC power source; a transformer having a primary winding, a secondary winding, and an auxiliary winding; a switching element connected to the primary winding of the transformer; and a control circuit configured to turn the switching element on and off based on a voltage signal which is based on an average value of current flowing through the switching element and the rectified-smoothed voltage signal from the rectifying-smoothing circuit.

1. Technical Field
The present invention relates to a switching power source device and a control IC for lighting LEDs which are capable of performing constant power control.
2. Background Art
FIG. 1 is a configuration block diagram showing a conventional LED lighting device described in Japanese Patent Application Publication No. 2006-210836. In FIG. 1, an EMI filter 1 is connected between both terminals of an AC power source AC, and an output terminal of the EMI filter 1 is connected to an input terminal of a full-wave rectifying circuit DB configured to rectify an AC voltage of the AC power source AC. An output terminal of the full-wave rectifying circuit DB is connected to a capacitor Cin. The full-wave rectifying circuit DB and the capacitor Cin form an input-side rectifying-smoothing circuit. A stage subsequent to the capacitor Cin is formed by a flyback converter having a transformer TR, a switching element Q1, a control integrated circuit (IC) 10, and an LED-group load device 3.
The transformer TR has a primary winding W1, a secondary winding W2, and an auxiliary winding W3. The secondary winding W2 and the auxiliary winding W3 are wound to have reversed phase compared to that of the primary winding W1. The switching element Q1 is formed with a MOSFET, and is connected to the primary winding W1 of the transformer TR and driven by the control IC 10 configured to generate an on/off drive signal.
An output-side rectifying-smoothing circuit formed by a series circuit of a diode D1 and a capacitor C1 is connected between both ends of the secondary winding W2 of the transformer TR, and the LED-group load device 3 having series-connected LED1 to LEDn is connected between both terminals of the capacitor C1. A rectifying-smoothing circuit formed with a series circuit of a diode D2 and a capacitor C2 is connected between both ends of the auxiliary winding W3 of the transformer TR, and a voltage generated at the capacitor C2 is supplied as a power source voltage Vcc for the control IC 10.
To perform constant current control on a load current flowing through the LED-group load device 3, a constant current circuit (CC circuit) is formed, and a detected load current is inputted, as a feedback signal FB, to a current-control error amplifier (not shown) in the control IC 10 so that the load current may have a predetermined average current value.
However, when the constant current control is performed on currents for LEDs whose forward voltages VF largely vary, power inputted to the LEDs varies, causing variations in the amount of luminous flux among individual lighting devices.
In some cases, to suppress the variations in the amount of luminous flux, constant power control is performed on the LED loads. In the constant power control on the LED loads, a constant current IF is decreased when the forward voltage VF of an LED is high while the constant current IF is increased when the forward voltage VF is low. In this case, a computation of VF×IF=constant needs to be performed by circuitry. For example, VF×IF=constant can be achieved by using a multiplier or the like to generate an FB signal having information for constant power.
When VF×IF=constant is achieved using the multiplier or the like, a single path is formed for the FB signal by placing the multiplier or the like at the secondary side of the transformer TR, but a photo coupler or the like is needed to form an insulating power source. Thus, the circuit configuration becomes complicated. Moreover, it is difficult with a conventional circuit technology to perform the constant power control with a simple circuit other than the multiplier or the like.
An objective of the present invention is to provide a switching power source device and a control IC which are inexpensive and small and are capable of performing constant power control without a multiplier and a photo coupler and reducing variations in the amount of luminous flux even when the forward voltages VF vary.

Switching power source device and control IC which are capable of performing constant power control


A spectrometer apparatus for measuring spectra of a liquid sample, such as a beverage like wine. The apparatus has an integrating cavity with a reflective inner wall to receive a cuvette containing the liquid sample within the integrating cavity. A combination of light inlet ports and light outlet ports are provided to receive light from at least one light source and deliver light to a spectrometer. A light path adjuster is configured to selectively adjust a light path through the integrating cavity so at least two distinct light paths are provided wherein when the light path adjuster is in a first configuration, the apparatus is in transmission mode in which light from the light source follows a first light path; when the light path adjuster is in a second configuration, the apparatus is in a diffusely reflecting mode in which light from the light source follows a second light path.

Standard UV-VIS spectroscopy is performed by shining a light source through a sample and measuring the transmitted light as a function of wavelength. The sample is generally a liquid that is contained within a square cuvette placed with the cuvette faces being perpendicular to the light beam. The transmitted light is then converted into an absorption spectrum which gives a measure of the absorbing power of the sample at every wavelength used. Absorbance can be used as a measure of the concentration of dissolved species (absorbance is proportional to concentration, known as the Beer-Lambert Law) or to identify the chemical content of a solution based on absorbance peaks of species at known wavelengths.
UV-VIS spectrometers are a standard instrument in analytical chemistry and can be used for both quantitative and qualitative analysis of liquids. UV-VIS spectrometers measure the spectrum of light directly transmitted by the sample, and determine the absorption spectrum based on the assumption that the only loss of light occurs due to absorption in the sample. This leads to the general requirement of brilliantly clear sample liquids in UV-VIS spectrometers.
In the more general case including turbid liquids, light is lost due to scattering by the sample, and UV-VIS spectrometers will measure the extinction spectrum instead of the absorption spectrum. In short:extinction=scattering+absorption.
The intensity of light scattered generally is wavelength dependent, leading to a scattering spectrum. In UV-VIS spectrometers absorption and scattering spectra are superimposed and cannot be disentangled without separate knowledge of one of the two constituent spectra. In strongly scattering liquids (e.g. milk, paint, blood, wine) the light reaching the detector is diminished to a degree which renders the absorption spectrum component virtually indiscernible from the measured extinction spectrum, even if the scattering spectrum was known. For scattering/turbid samples standard UV-VIS is therefore of very limited general applicability, and if used, nonetheless requires sample pre-processing (e.g. filtration, centrifugation or other methods to remove the scattering species). Dilution of the sample is generally not helpful because it reduces both scattering and absorbance of the sample in the same proportion.
In summary, there is a significant range of samples where UV-VIS either does not work or time-consuming processing is required in order to allow analysis of cloudy solutions. Moreover, it can be impossible to separate out the relative contribution of scattering and absorption using standard UV-VIS spectroscopy.

Spectrometer apparatus for measuring spectra of a liquid sample using an integrating cavity


A system for a healthcare provider to administer a portable interactive hearing assessment is provided. The system allows the healthcare provider to administer the hearing assessment in a way that accurately detects hearing loss and provides recommendations for seeking further assistance from qualified hearing health specialists and/or an ENT physician. The system includes a hearing test device, and a processor that receives and processes a pressure test result associated with each of the patient's ear from a tympanometer and the patient's response to one or more pure tone frequencies transmitted by the hearing test device. The processor may also provide a report and recommendation based on received pressure test result and the determined hearing results, and demonstrate effects of any hearing loss to a person accompanying the patient so that the accompanying person understands a scope of the patient's hearing loss.

The incidence of hearing loss in the United States was 266 per thousand households in 1989, 283 per thousand in 2004, and 295 per thousand in 2008. In 2008, 43.25 million reported hearing difficulty. Between 2004 and 2008, the hearing impaired population grew 8.8% compared to a 4.5% increase in US households. Furthermore, the percent of the population that acknowledged a hearing loss grew from 10% in 1989 to 11.3% in 2008.
People with hearing loss rarely acknowledge the disorder. From the time hearing loss is first noticed, the average hearing impaired person delays seven years before seeking assistance. Reasons given by some are they may not believe that they can afford a hearing aid, so they don't inquire about a hearing analysis. Others fear ridicule and taunting by family and friends if they use a hearing aid. And yet for others, acknowledging hearing loss means they have to acknowledge that they are aging and that their bodies are simply not able to do things they once took for granted.
Technology used in hearing aids is improving rapidly in a manner parallel to other chip-based consumer goods. Newest technologies remain relatively expensive, but slightly older technologies are more affordable. Furthermore, continuous improvement has been made in designs to make hearing aids less cumbersome and noticeable in the ear along with better ability to eliminate background or undesirable noise. So many more people would benefit from hearing assistance than those currently seeking such care.
Moreover, many people might typically seek advice from a physician or other healthcare provider to provide at least some guidance on the matter, but most are not prepared to provide such guidance. Current tools for performing hearing tests available to the healthcare professionals at large remain expensive and labor intensive relative to reimbursement for such tests. Furthermore, if under such conditions a hearing disorder is identified, the patients are often not referred in an expeditious and efficient manner for diagnosis and/or treatment.
Thus, what is needed is a way to provide a hearing assessment by a wide range of healthcare providers who have not traditionally participated in hearing analysis, e.g. primary care physicians, pediatricians, neurologists, naturopath doctors, chiropractic doctors and the like, referred to herein as a general "healthcare provider" as distinguished from hearing health specialists described hereinbelow. There is a need, therefore, for a system, method and computer-readable medium that provides a simple, cost effective hearing assessment to be administered by the general healthcare provider. There is a further need to provide a simplified means for referral by the healthcare providers to a hearing health specialist (e.g. audiologists and otolaryngologists).

This patent is subject to a terminal disclaimer.


A method is provided that performs a path search that identifies several path extensions. The method performs a viability check on a particular path extension by identifying first and second circuit geometries. The first circuit geometry is associated with a particular segment of a route that would result from the particular path expansion in a design layout. The second circuit geometry is associated with a circuit element to which the particular segment connects. The viability check also determines whether connecting the segment with the first geometry and the circuit element with the second geometry is allowable based on predetermined rules. The method stores the particular path expansion in a storage medium as a viable path expansion when the viability check determines that connecting the segment with the first geometry and the circuit element with the second geometry is allowable.

An integrated circuit ("IC") is a device (e.g., a semiconductor device) that includes many electronic components, such as transistors, resistors, diodes, etc. These components are often interconnected to form multiple circuit components, such as gates, cells, memory units, arithmetic units, controllers, decoders, etc. An IC includes multiple layers of wiring that interconnect its electronic and circuit components. Traditionally, IC's use preferred direction ("PD") wiring models, which specify a preferred wiring direction for each of their wiring layers. In preferred direction wiring models, the preferred direction typically alternates between successive wiring layers. One example of a PD wiring model is the PD Manhattan wiring model, which specifies alternating layers of preferred-direction horizontal and vertical wiring.
Design engineers design IC's by transforming logical or circuit descriptions of the IC's into geometric descriptions, called layouts. IC layouts typically include (1) circuit modules (i.e., geometric representations of electronic or circuit IC components) with pins, and (2) interconnect lines (i.e., geometric representations of wiring) that connect the pins of the circuit modules. A net is typically defined as a collection of pins that need to be connected. A list of all or some of the nets in a layout is referred to as a net list.
To create layouts, design engineers typically use electronic design automation ("EDA") applications. These applications provide sets of computer-based tools for creating, editing, and analyzing IC design layouts. One EDA tool is a router that defines routes for interconnect lines that typically connect the pins of nets. While some commercial routers today might allow an occasional diagonal jog, these routers do not typically explore diagonal routing directions consistently when they are specifying the routing geometries of the interconnect lines. This, in turn, increases the total wirelength (i.e., total length of interconnect lines) needed to connect the nets in the layout.
There are certain techniques during manufacturing that require certain geometries have a minimum length. FIG. 1 conceptually illustrates a portion of an IC layout design 100 consisting of a pin 105, a via 110 (vias are further described in Section I below), an interconnect line 115 connecting the pin 105 and the via 110, and another interconnect line 120 in the same layer connecting the via 110 to other circuit geometries. Ideally, after the manufacturing process, the corresponding fabricated portion of the IC must look like a single piece of metal 125 with the same outline as the original IC layout design 100.
In order to generate a pattern such as 125 on an IC wafer, some IC fabrication processes use a photomask and a visible or ultraviolet light source. The wafer surface is covered by a layer of either electrically insulating or electrically conductive material. This material is then coated with a photosensitive resist. The light source is then used to project the image on the photomask onto the wafer. The resist is then developed in a developer solution after its exposure to light to produce patterns that define which areas of the wafer are exposed for material deposition or removal.
In practice, in order to make the fabricated pattern 125 to look as close as the original IC layout design 100, certain techniques such as Optical Proximity Correction (OPC) are utilized that would require some geometries on the IC surface to have a minimum length. For instance, the OPC technique improves the IC yield by applying systematic changes to the photomask geometries to compensate for nonlinear distortions caused by optical diffraction and resist process effects. OPC makes small changes to the IC layout that anticipate the distortion. Small shapes may be added or subtracted from comers to produce comers in the fabricated IC that are closer to the ideal layout. As a result, certain edges in the IC design layout have to have a minimum length for OPC or similar processes to work properly. There is, therefore, a need in the art for a technique to ensure a minimum length for certain edges and interconnects lines during the routing process.


The present invention relates to a coated cemented carbide insert (cutting tool), particularly useful for wet or dry milling of steels at high cutting speeds, milling of hardened steels, and high feed copy milling of tool steels. The cutting tool insert is characterised by a cemented carbide body comprising WC, NbC, and TaC, a W-alloyed Co binder phase, and a coating comprising an innermost layer of TiCxNyOz with equiaxed grains, a layer of TiCxNyOz with columnar grains and a layer of α-Al2O3.

1. Field of the Invention
The present invention relates to coated cemented carbide inserts (cutting tools), particularly useful for wet or dry milling of steels at high cutting speeds, milling of hardened steels, and high feed copy milling of tool steels.
2. Description of the Related Art
When machining low and medium alloyed steels and hardened steels with cemented carbide tools, the cutting edge is worn according to different wear mechanisms, such as chemical wear, abrasive wear, adhesive wear and by edge chipping caused by cracks formed along the cutting edge. The domination of any of the wear mechanisms is determined by the application, and is dependent on properties of the machined material, applied cutting parameters, and the properties of the tool material. In general, it is very difficult to improve all tool properties simultaneously, and commercial cemented carbide grades have usually been optimized with respect to one or few of the above mentioned wear types, and have consequently been optimized for specific application areas.
EP 1493845 relates to a coated cemented carbide insert (cutting tool), particularly useful for milling of stainless steels and super alloys but also milling of steels in toughness demanding applications. The cutting tool insert is characterised by a cemented carbide body comprising WC, NbC and TaC, a W-alloyed Co binder phase, and a coating comprising an innermost layer of TiCxNyOz with equiaxed grains, a layer of TiCxNyOz with columnar grains and a layer of α-Al2O3.
WO 2007/069973 discloses a coated cutting tool insert particularly useful for dry and wet machining, preferably milling, in low and medium alloyed steels, stainless steels, with or without raw surface zones. The insert is characterized by a WC—TaC—NbC—Co cemented carbide with a W alloyed Co-binder phase and a coating including an innermost layer of TiCxNyOz with columnar grains and a top layer at least on the rake face of a smooth α-Al2O3.
WO 01/16389 discloses a coated milling insert particularly useful for milling in low and medium alloyed steels with or without abrasive surface zones during dry or wet conditions at high cutting speed, and milling of hardened steels at high cutting speed. The insert is characterized by WC—Co cemented carbide with a low content of cubic carbides and a highly W-alloyed binder phase and a coating including an innermost layer of TiCxNyOz with columnar grains and a top layer of TiN and an inner layer of κ-Al2O3.
EP 1352697 provides coated cemented carbide inserts (cutting tool), particularly useful for milling at high cutting speed in steels and milling in hardened steels. The inserts are characterized by a WC—Co cemented carbide containing NbC and TaC and a W-alloyed binder phase and a coating including a first, innermost layer of TiCxNyOz with equiaxed grains, a layer of TiCxNyOz with columnar grains and at least one layer of Al2O3 consisting essentially of the κ-phase.
What is needed is a coated cutting tool with enhanced performance for milling of steels, hardened steels, and tool steels. The invention is directed to these, as well as other, important needs.


The invention provides a tensile tester, for characterising the extension properties of a fabric, comprising: a plurality of dual-mode fabric-engaging units located at a plurality of points. The fabric-engaging units are operable in a first fabric-gripping mode to releasably grip a fabric to be tested, and in a second fabric-tensioning mode to impart tension to a fabric to be tested, between gripped points, by displacing the fabric. The tester also has force measurement means to measure the tension so imparted and displacement measuring means to measure the displacement of the fabric. The fabric-engaging units are arranged and controlled so as to measure displacement-force characteristics along two or more axes of the fabric to be tested. Embodiments of the invention allow for determination of stretch characteristics in the Course, Wale, and two Bias directions of a fabric, as well as the characterisation of tension decay.

Demand for stretch garments, which apply varying degrees of compressive stretch for sportswear, cosmetic body shaping and medical applications is increasing. In evolutionary terms stretch garment pattern design is in its infancy. Pattern drafting techniques for woven block patterns are well established. Applying these techniques to generate patterns for stretch fabrics can be successful, but it is often at a cost. Using the simplified shapes of modified traditional patterns, proportionately reduced by an arbitrary amount or using smaller sized patterns, can generate garments of dubious fit. All conventional pattern-drafting techniques are based on mathematical formulae that have evolved encompassing an implicit fit rationale. How companies arrived at their approximation of the ideal pattern profile for their particular demographic fit model is usually dependent on the subjectivity and expertise of the designer/technologist fitter. Currently determining the degree of fabric extension and how to apply the amount of available stretch in the pattern reduction process is subjective. Traditional approaches to pattern geometry combined with an arbitrary degree of stretch extension introduces variables at each stage, thus impeding objectivity and the technological evolution of stretch pattern profiling.
Stretch fabrics are produced in a broad range of fibre content and weights with a stretch extension capacity for a variety of applications. Manufacturers of stretch fabric normally use laboratory based electronic testing instruments for the climatically controlled measurement of tensile characteristics. British and American Standard Tests include methods for: fatiguing or ageing specimens; determining extensions at a specific force, modulus, tension decay, residual extension, fatigue set, elastomeric thread break and runback. Fabric and fibre producers and garment technologist use these standard tests to assess the fitness for purpose of a garment fabric and have specific quality assurance parameters in common.
Most manufacturers tend to state a single averaged course/wale stretch for the fabric quality, usually attributed to a range of fabrics but this can be misleading as it is not generally stated that the degree of stretch is obtained by applying differing loads to the individual fabrics This averaged stretch figure is inadequate for stretch pattern design (Ziegert, B. and Keil, G., Clothing and Textiles Research Journal, 1988, 6(4), 54-64).
Information on stretch fabric characteristics and the way stretch extension is quantified in the process of constructing a stretch pattern is not straightforward. To quantify the degree of stretch technical publications for garment pattern construction recommend the hand stretch test method, which is generally agreed to mean 'the useful limit of extension'. Theoretically it is the point at which the stretched fabric has reached its maximum extension without deforming the hard yarns or fibres (Murden, 1966:356, Elastomeric Thread Review (II): Elastomeric and Fabric Test Method. Textile Institute and Industry, Vol. 4, December, pp. 355-358). Samples of fabric of varying widths different lengths (Haggar, 2004:272, Pattern Cutting for Lingerie, Beachwear and Leisurewear. 2nd Ed., Oxford: BSP Professional Books; Armstrong, H., 1995, Patternmaking for Fashion Design, 2nd Ed., Harper Collins, 471, Murden 1966:356) are pulled until a reasonable resistance to stretch is felt, or until they are visually unacceptable. The degree of extension is then measured on a rule and categorised as low, medium or high stretch. This method of assessing fabric stretch extension is also difficult for the designer/technologist to apply objectively in stretch garment design.
Having first recognised the shortcomings of the present technologies, the problem is to establish a qualitative procedure for measuring, recording and specifying fabric characteristics that would be accessible throughout the clothing and allied industries. This would include fabric manufacturers and distributors, designers/pattern technologists, clothing and allied trades manufacturers and retailers.


A single sheet has multiple separation lines arranged such that the sheet can be printed on by a standard printer such as a personal computer printer, and the sheet may thereafter be separated and/or folded in any one of three different configurations to form different possible compact disc jewel case inserts including both face labels and spine labels. One embodiment is of a sheet having at least four longitudinal lines of weakness extending across at least a major portion of the length of the sheet, and at least three latitudinal lines of weakness extending across a major portion of the width of the sheet, with at least one longitudinal line of weakness being a fold about which at least one portion is folded.

As well known, there are different configurations of cases for holding and storing compact discs. One type of case is a "standard" sized case into which can be inserted a booklet of four or more pages, an insert for the front cover that is only a single sheet, and/or a separate spine portion to label the spine of the CD case.
Another type of compact disc case is the so-called "slim line" case, which also accepts booklets and/or inserts for labeling the front of the case.
Attempts have been made to create perforated sheets that can be printed in a local printer, such as an ink jet printer and/or a laser jet printer. However, as shown in U.S. Pat. Nos. 5,789,051 and 6,155,026, the prior art requires at least two different kinds of sheets in order to print an insert or a booklet. This arrangement is costly to the end-user, in that they need to buy a supply of both types of sheets in order to perform different functions.
Consequently there is a need for a single, versatile sheet onto which a user may selectively print a booklet, an insert, or an insert having a spine portion for insertion into a slim line case.

Versatile printable sheet for forming jewel case inserts and booklets